Patent GB-1156249-A (GB)
Title: Data Processing Systems
IPC: G06F9/38
Filed: 1967-09-21
Abstract: 1,156,249. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 21 Sept., 1967 [28 Sept., 1966], No. 43028/67. Heading G4A. In a data processing system, devices connected to a bus hold tags to control distribution of data on the bus between the devices, or provision is made for transferring the tag of one device to another device. In a floating point processing unit (Fig. 17A) of the system, main storage feeds floating point buffers FLB and is fed from store data buffers 244 (each of which has an associated tag register). Three reservation units RU1, RU2, RU3 (only one shown explicitly), each capable of registering two operands and a tag associated with each operand, can feed an adder (with provision for subtraction) unit 188. A similar two reservation units RU4, RU5 can feed a multiply/divide unit 192. Floating point registers FLR (each with an associated tag register) can feed the RU's via an FLR bus and the FLB's can feed the RU's via an FLB bus. A common data bus CDB can be fed from the FLB's, the adder unit and the multiply/divide unit and can feed the RU's, the store data buffers 244 and the FLR's. The FLR bus can be gated (not shown) to the CDB to permit the contents of one FLR to be transferred to another. Instructions from an in struction unit called the I-box are buffered at FLOS and decoded in turn at 595 to set the tags to control data routing. When (or just before) a given block in Fig. 17A feeding the CDB or FLR bus or FLB bus needs to send data it requests a time slot on the bus and when this is granted (subject to priority ranking in the case of simultaneous requests) it applies a tag identifying itself to the bus, this tag being compared with the tags stored at all registers &e. which can be fed from the bus and which have tags set. The data is applied to the bus after the tag and is gated into each possible destination at which the tag comparison gave equality. The tag and data occupy different lines of a bus, permitting the tag of one transfer to be on a bus at the same time as the data of a previous transfer. In the case of a two-operand arithmetic instruction (for definiteness) the two operands will normally come from FLR's or one will come from an FLR and the other from an FLB (load instructions permit the FLR's to be previously loaded from memory via the FLB's), the operands being supplied to an RU associated with the adder unit or multiply/divide unit as appropriate in the way described, and the result being sent back to the or one of the operand FLR's. However, if an operand is the result of a previous instruction and is not available when the current instruction is decoded, the tag at the result FLR is transferred to the RU to be used for the current instruction and replaced at the FLR by a tag identifying that RU, so when the result of the previous instruction is available it will be gated straight from the CDB into the RU for the current instruction without first going to the FLR. The result of the current instruction goes to the FLR, since the latter is holding the tag identifying the RU concerned in the operation, unless of course this tag has been transferred from the FLR to another RU in response to a further instruction before the result arrives. In this way, greater concurrency of instruction execution is achieved by preventing bottlenecks due to frequent programmed use of a given register. Transfer of tags for this purpose is not limited to tag transfer from an FLR to an RU but can occur from one FLR to another or to a storage data buffer 244. A zerotester fed from the CDB has a tag register usable in the same way as those of the RU's. The FLR bus and FLB bus could be dispensed with as separate entities by extending the CDB, or there could be a plurality of CDB's. The I-box prefetches instructions from main storage into a set of buffers. Small programme loops can be iterated from the buffers without repetitive storage accesses. In response to a conditional branch instruction where it is not yet known if the branch condition is satisfied, prefetching is performed along the branch path to some extent in case the branch is taken, as well as continuing along the non-branch path. The abridgment of Specification 1,151,041 (the latter being referred to) gives more details of these features. A preliminary decoding of the instructions determines whether they require operands from storage and issues the instructions as appropriate to the floating point processing unit or a fixed point processing unit, both of which include instruction buffers (FLOS in the former case). The fixed point processing unit includes a number of general purpose registers which are used as operand sources and result sinks for the unit and for address modification in the I-box. Each general purpose register has two associated counters which restrict use of the register by the I-box when they are non-zero. The first counter is incremented on decoding of each instruction which uses the register as a result sink and is decremented on execution of such an instruction. The second counter is incremented on decoding of each instruction which uses the register as an operand source and is decremented on execution of such an instruction. Specification 1,151,041 is also referred to, the abridgment thereof giving details of the memory accessing in the present system.