Patent GB-853341-A (GB)
Abstract: 853,341. Counting-apparatus. COMPAGNIE IBM FRANCE..Nov. 13, 1957 [Nov. 13, 1956], No. 35450/57. Class 106 (1). An electric pulse counting device adapted to count pulses on first and second input channels has means for merging signals applied to both input channels into a common output channel in which each input channel includes a device for producing a pulse of predetermined duration in response to an input signal and a gating circuit, the gating circuit of each channel being so operable under the control of pulses passing through the other channel that the application to said output channel of a pulse initiated in either of said input channels is delayed until a predetermined minimum time after the application of any input signal already present in the other of said input channels. As shown, Fig. 4, negative pulses on the leads 101, 102 are merged to appear on the single output lead 103. First case: in the absence of a pulse on the lead 102, a negative pulse on the lead 101 triggers a monostable flip-flop 111 to produce a positive 4 microsecond pulse whose negative-going trailing edge triggers a monostable flip-flop 112 to deliver a 20-microsecond positive pulse which passes through a gate 116 since the terminal 116G is at earth potential, the negative 16 microsecond pulse produced.by a flip-flop 131 having no effect since the gate 126 is closed. A capacitor 217 delivers a positive pulse followed by a negative pulse 20 microseconds later, however only the positive pulse affects an inverter 115 to produce a final output negative pulse at 103 which is delayed by 4 microseconds from the original input pulse. Second case: when a pulse is absent on the lead 101 and a negative pulse appears on the lead 102, this pulse triggers the monostable flip-flop 121 to produce a 24 microsecond positive pulse which passes the gate 126 to an inverter 123, the negative leading edge of this pulse after inversion triggering the monostable flip-flop to produce a 14 microsecond positive pulse which is differentiated and inverted to appear as a negative output pulse on the lead 103 simultaneously with the input pulse. Third case: pulses arrive on the leads 101, 102 within 24 microseconds of each other. As shown in Fig. 5b, a pulse 512 on the lead 102 arrives less than 12 microseconds after a pulse 511 on the lead 101 so that the gate 126 transmits only that portion 516 of the pulse 515 produced by the monostable flip-flop 121 which occurs after the end of the pulse 514 produced by the monostable flip-flop 131 and the gate 116 transmits only that portion 518 of the pulse 513 produced by the monostable flip-flop 112 which occurs before the beginning of the pulse 517 produced by the monostable flip-flop 122 which is energized by the leading edge of the pulse delivered by the inverter 123 on receiving the pulse 516. The output pulse 519 corresponds to the input pulse 511 and is produced by the leading edge of the pulse 513 but the output pulse 520. resulting from the input pulse 512 from the leading edge of the pulse 516 is delayed, until the end of the pulse 514 and therefore appears 12 microseconds after the pulse 519. Suitable transistor circuits for the flip-flop and inverter are described.