Patent GB-1480754-A (GB)
Title: Drive pulse generator for use in electronic analogue display clock apparatus
IPC: G04G3/02
Filed: 1974-11-19
Abstract: 1480754 Electronic timepieces TOKYO SHIBAURA ELECTRIC CO Ltd 19 Nov 1974 [9 March 1974] 49978/74 Heading G3T An electronic timepiece having a stepping motor coupled to an analogue time display comprises a crystal controlled oscillator 11, Fig. 2, followed by a frequency divider chain 12 and drive circuit arranged to pass current pulses through the motor 14 in opposite directions alternately, a delay circuit 18 being connected between the (n-1)<SP>th</SP> and n<SP>th</SP> stages of the divider, and means 28, 30 connected to apply a reset pulse to reset the delay circuit and at least the (n-1)<SP>th</SP> stage of the divider when correction of the time displayed is to be effected. The circuit Fig. 2 provides a drive pulse in a unit length of time after resetting is released by opening switch 28 upon precise time information being given, and ensures that this initial drive pulse is applied in the opposite direction to the drive pulse applied immediately before the resetting was effected. The delay circuit 18 effects a delay on the divider 12-n-1 output signal Q n-1  to produce signal M Fig. 4 (not shown). The amount of this delay is determined by the output Qm and its complement Qm from divider stage 12-m (the particular stage chosen is dependent upon the response time of the motor) and is equal to half the period of Qm. To actuate a second hand at one step/sec the signals Q n-1  and Q n-1  are at 1Hz. The delayed signal M and signal Q n-1  are fed to a NOR gate 19 which consequently produces pulses X having a pulse width equal to the imposed time delay and a period of 1 sec. The signal X and its complement Y are divided in frequency at divider counter stage 12-n to give outputs Q n , Q n  at a 2 sec. period i.e. 0À5 Hz which are applied to NAND gates 21, 22, together with signal X. The outputs of gates 21, 22 control an FET switching bridge 23, 24 (detailed Fig. 6) to pass current pulses OA, OB through the motor coil 25 in opposite directions alternately at intervals of one second. TIME CORRECTION When time correction is required a switch 28 is depressed to apply a positive reset pulse to the delay circuit 18 and to divider stage 12-n at least. To increase accuracy and reduce power consumption a reset pulse may be applied to all of the divider stages 12-1---12-n which will reduce time error in said unit length of time i.e. the interval between release of the resetting switch and the initial drive pulse thereafter. In response to a reset pulse, the binary divider stages produce a Q output of zero volts irrespective of existing output condition, while the delay circuit holds its existing output. Accordingly the NOR gate 19 output X is held at zero volts and the outputs Q n , Q n  are held at their levels prior to resetting. When resetting is released, the levels of Q n-1  and hence M change causing the NOR gate 19 to produce output X within the unit length of time after release of the reset (subject to a "time error" depending upon the binary counter or counters which also receive a reset signal, e.g. if the 9<SP>th</SP> to 15<SP>th</SP> counters are also reset the time error will be 1/128 sec, i.e. the period of the 8<SP>th</SP> counter output), whereupon-assuming inverter 23 produced drive pulse OA to the coil IL immediately prior to resetting, the inverter 24 will produce pulse OB in the unit length of time after release of the reset, and vice-versa. In a modification Fig. 7 (not shown), the reset signal is applied to an AND gate together with the signal Y. This prevents resetting during a period when current is passing through the motor coil. The delay circuit may be a static half-bit shift register.