Patent GB-987609-A (GB)
Title: Improvements in digital calculating devices
IPC: G06F7/491
Filed: 1962-12-20
Abstract: 987,609. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 20, 1962 [Dec. 26, 1961; May 17, 1962; May 25, 1962], No. 48176/62. Heading G4A. Means are provided for adding or subtracting by complement addition floating point decimal numbers in series by digit, highest order first, and in parallel by bit. Redundant zeros are eliminated with suitable modification of the exponent if they are significant. The decimal numbers are in a 2-out-of-7 code and the adder is merely a set of and circuits suitable for combining a pair of such coded digits and for providing signals indicating whether the sum is greater, less than, or equal to 10 or if it is equal to 9. Additionally, for the purpose of eliminating zeros, signals indicating whether the sum digit is 0 or 1 are provided. Initially the operands have equal exponents. Addition. The operands are held in registers 10,11. Sum digits are sent alternately to registers 13, 14. As a digit is sent to one register the digit in the other is transferred to output register 18. In passage the digit may be incremented or decremented by one in circuit 17. Occasionally a digit is not transferred from register 13 or 14 and the sum digit is supplied from a digit generator 16 which provides 9's or 0's which may be incremented or decremented by circuit 17. The exponent of the two operands is initially in register 19, may be increased or decreased in counter 15 and is finally held in register 20. During an addition, if the sum of two operand digits is 9, nothing is gated to registers 13 or 14 but the setting of counter 15 is incremented by one. Assuming that counter 15 does not contain the exponent, there are four possible cycles of operation: (a) If the sum is less than 9 and the counter 15 is set at zero, the sum digit is gated to register 13(14) and the contents of register 14(13) are transferred unchanged to register 18. (b) If the sum is greater than 9 and the counter 15 is set at zero, the low order digit of the sum is gated to register 13(14) and the contents of register 14(13) are transferred to register 18, incremented by one. (c) If the sum digit is less than 9 and the counter stands at a count of N, the sum digit is sent to register 13(14) and the contents of register 14(13) are transferred to register 18 unchanged. Additionally N9's are sent to register 18 from digit generator 16. At the conclusion of this cycle the counter registers zero. (d) If the sum is greater than 9 and the counter stands at a count of N, the low order sum digit is sent to register 13(14), the contents of register 14(13) are transferred to register 18, incremented by one and N9's are transferred to register 18, each incremented by one to give a set of N 0's. It can be said that each order of the sum is held until it can be determined whether there is an in-carry either from the next lower order or from an order preceded by a set of 9's. Subtraction is performed by taking the 10's complement of each digit of the smaller number. It is first assumed that register 11 contains a smaller number than register 10. If the first sum digit is greater than 10 the assumption is correct and the operation proceeds. If the first sum digit is less than 10, the operation is stopped and restarted, complementing the digits of register 10. If the first sum digit is equal to 10, the highest order digits of the operands are equal. The exponent is decreased by one, suppressing the zero, and the operation restarted under the assumption that register 10 contains the larger operand. The subtraction operation is similar to the addition save that when the sum is 10 nothing is transferred to register 13 or 14 and the counter is incremented by one. When the sum is less than 10 the previous sum digit is transferred to register 18 decremented by one. When the counter registers a non-zero count a set of zeros are generated by circuit 16. Dependent on whether the sum digit is greater or less than 10 the zeros pass unchanged or decreased by one (as 9's) to output register 18. Exponent modification. The exponent is initially transferred from register 19 to counter 15. If the operation is addition and the sum digit is greater than 10 the 1 is passed directly to register 18 and the counter incremented by one. The exponent is then transferred to register 20. If the operation is subtraction and the sum is equal to 10 the zero is not passed to output and the counter decremented by one. Again, the exponent is transferred to register 20. Modifications of these processes occur when the sums are 9 or 1 with a lower order carry or borrow. If necessary the exponent can be returned from register 20 to the counter. Suppression of zeros. When, in addition, the counter is at a non-zero count, the last sum is equal to 10, and a signal is received from registers .10 and 11 that the last order has been summed the action of circuit 16 is inhibited thus preventing the transfer to register 18 of a set of non-significant zeros. A similar situation is catered for when the operation is subtraction. The control circuits are described in some detail but are not thought to be of general interest.