Patent GB-1138854-A (GB)
Title: Apparatus for simulation of multi-phase operations representable by planning diagrams
IPC: G06Q10/00
Filed: 1966-02-09
Abstract: 1,138,854. Operational simulating apparatus. C. MARQUIS, P. DRIAY, and P. LAMBILLIOTTE. 9 Feb., 1966 [12 Feb., 1965; 6 April, 1965], No. 5713/66. Heading G4G. An industrial or commercial operation is represented by a P.E.R.T. network (Fig. 1) having input 1 and output 2 with nodes 2, 3, 4, 5, 6, 7 interconnected by arms t 12 , t 13 , t 24 , t 25 , t 36 , t 47 , t 56 , t 57 , t 68 , t 78 each representing the time of execution of a phase of the operation, the phases being interdependent according to the nodal interconnections, and the problem for solution being the determination of the longest succession of operative time phases (i.e. critical path analysis) with the various series of arms of the diagram representing the various paths in which delay of execution will delay carrying out the whole programme. The longest time corresponding to the central path will be one of Alternatively, the time variable may be replaced by a cost variable. The input represents the commencement of the operation and the output its termination, and the time or cost scale may be chosen at will. The diagram is simulated by a board T (Fig. 2) having fixing means F for individual components, which carries a pulse generator I at the input and a clock H triggered therefrom at the output. Arms t 12 , t 13 , t 24 , t 25 , t 36 , t 47 , t 56 , t 57 , t 68 and t 78 are represented by corresponding adjustable time delay devices 12, 13, 24, 25, 36, 47, 56, 57, 68 and 78 variable to represent the duration or cost of the corresponding operations and emitting a pulse after a delay from pulse receipt which is a function of actual time, and the convergent nodes 6, 7, 8 are represented by time discriminators receiving pulses from the delay devices in the carrying arms; such discriminators having inductors (e.g. lamps) showing the input through which a first (or second) pulse has arrived by, e.g. extinction. The clock is started by a trigger pulse over line D and stopped by the first (or last) arriving pulse, so that the minimum (or maximum) time (or cost) for the operation is determinable. The control path of the pulse is indicated by the lamps of the discriminators, which represent the sequence of operations for the most (or least) economical expenditure of time or money. The time delay devices may be adjusted during the simulation, and convergent arms numbering n> 2 may be received by (n-1) discriminators (Fig. 3, not shown). A more sophisticated simulator (Fig. 4, not shown) for operational diagrams of n nodes comprises (n-1) n elements each comprising a delay device corresponding to an arm of the diagram; a two input time discriminator, and a plug and jack switch on a detachable and interchangeable patch board. Each element is numbered with two digits corresponding to the input and output nodes of its arm, the discriminators of the elements having identical second digits are cascaded, and the switches of elements of identical first digits are commoned to a trigger source (I 1-9 ). Clocks (H 1 ) to (H 9 ) are connected to the outputs of the respective cascades of time discriminators. A triggering conductor (D 1-9 ) starts the clocks when an associated trigger (I 1 to I 9 ) pulses, and a pulse generator (Z) supplies the discriminators at the head of each cascade at the input opposite to that of the corresponding delay device, to permit zeroing after a simulating operation. Initially, the nodes of the operational diagram are numbered (as in Fig. 1) and the plug and jack switches represented by the numbers of the ends of each corresponding arm are closed. A pulse from (Z) is transmitted to zero the discriminators, the delay devices are adjusted, and a further pulse from the trigger source corresponds to the input node. Discriminators of element (12, 13) trip, and energize elements (24, 25) and element (36) whose discriminators energize the further selected elements until the cascade of discriminators numbered for node (8) is reached. The number of the cell whose discriminator has triggered, e.g. (68) is noted, reference is made to the cascade numbered (6), and the numbers of successive triggered discriminators are noted so that the control path is determined as (68), (56), (25), (12) etc.; and clocks (H8), (H6), (H5), (H2) indicate the passage times of the final pulse corresponding to the critical path as an indication of time (or cost) of the complete operation and its component phases. The multiple clocks may be replaced by a single multiple recording clock. The delay devices may be supported on a subchassis 101 (Fig. 5) surmounted by a movable panel 110 carrying control knobs 111 for the corresponding units, wherein conductive plate 113 with a stop 114 is rotatable coaxially with another such plate 104 with a stop 105 engageable with stop 114. The latter plate is rotatable by a ratchet wheel 102 pawl actuated by electromagnet 106 responsive to input pulses, against spiral spring 108, while electromagnet 107 responsive to zeroizing pulses releases the ratchet. Slidable contacts 109, 115 connect plates 104, 113 to earth and to input socket 116. If a train of pulses is applied to 106 through socket 118, plate 104 is rotated and after a time delay the stops engage to close a circuit through socket 116 permitting output pulsing. Slider 109 may be connected to pulse energize an input of further delay device after the inherent delay has been inserted, or to connect the input of a further delay device to a preset potential or earth. A discriminator comprises inputs E 1 , E 2 energizing relays closing contacts to bias the bases of flip-flop transistors T 1 , T 2  (Fig. 6) whereof the emitters are commoned to supply, and the collectors cross connected to the bases to operate indicator lamps L 1 , L 2 ; changeover switch 120 determining response to first or last arriving pulse. The discriminators are mounted in box assemblies (Fig. 7, not shown) carried on the removable panel 110, each having inputs sockets (E 1 ), (E 2 ) and triple outputs sockets (S 1 , S 2 , S 3 ) connected to the common output (S). Patch cords and plugs permit any desired interconnection, and panels 110 may be pre-set and interchanged. Alternatively (Fig. 8, not shown) the elements are mounted on a chassis carrying the adjusting knobs of the delay devices, and the pilot lamps of the discriminators are mounted on a removable transparent sub panel on which the relevant diagram is inscribed. The connections between the various elements are effected on a removable patchboard.