Patent GB-757251-A (GB)
Title: Improvements in and relating to electronic computers
Inventor: HAUSER ARTHUR ARMSTRONG
IPC: G06G7/16
Filed: 1954-04-02
Abstract: 757,251. Electric analogue calculating apparatus. SPERRY CORPORATION. April 2, 1954, No. 9739/54. Class 37. A multiplicative or divisive computer operating analogously to the solution of similar triangles comprising sources of first, second and third voltages; at least one of which is made variable and proportional to a factor of the computation while two of such voltages are of like electrical phase and the remaining voltage is of distinct electrical phase, together with a source of a fourth voltage in phase with the latter voltage and variable in magnitude by a control voltage, there being provided separate means for vectorially summing the respective pairs of out of phase voltages to summation voltages which are compared in a phase detector whose output is applied to control the magnitude of the fourth voltage so that the phase difference of the summation voltages is zeroized, and the computer output being taken from the fourth voltage source. Fig. 2 shows a multiplying or dividing computer in which co-phased voltages V 1  and V 3  are derived from adjustable input potentiometers 34, 36 at terminals 32, 32b and a voltage V of phase angle # with reference thereto is derived from potentiometer 35 at terminal 32a. Voltage V 1  is vectorially combined with a voltage V 2  Proportional to the voltage V in summation network 39 to produce a voltage difference vector Va and voltage V 3  3 is similarly vectorially combined with the output voltage V 4  of a variable gain amplifier 37 energized by voltage V 2 , in summation network 40 to produce a difference voltage vector Vb which is compared as to phase angle with difference vector Va in phase detector 38 which develops a unidirectional output voltage controlling the gain of amplifier 37 in such sense as to vary voltage vector Vb into phase angular coincidence with voltage vector Va. From the vector diagram (Fig. 1, not shown) V 4= V 2  V 3 /#V 1  so that by making V 1  constant the output V 4  of amplifier 37 represents the product of the analogue variables of V 2  and V 3  while by making V 2  constant it represents the quotient of the analogues of V 3  and V 1 . By making V 1  constant and V 2 =V 3  representing a single input variable the output V 4  represents its square, and higher powers thereof may be obtained by suitably cascading plural similar computer circuits. Alternatively voltages V 1 , V 3  and V 2 , V 4  may be vectorially added in corresponding pairs (Fig. 3, not shown), and the resultant vectors Va, Vb compared in a phase detector controlling the variable gain amplifier to restore phase coincidence, whereby V 4 = V 2 V 3 /V 1  as before. Fig. 5 shows a modification for extraction of square roots wherein voltage V 3  on terminal 32b represents the input variable while a co-phased reference voltage V 1  on terminal 32 is applied to a variable gain amplifier 42 to develop a reference output voltage V 4  on terminal 48. A co-phased reference voltage V on terminal 32a is phase shifted 90 degrees to develop a voltage V 2  which is compared in vector summation network 44 with voltage V 4  in quadrature therewith, and the voltage V 4  is phase-shifted 90 degrees to produce voltage equivalent to V 1  which is compared with the voltage V 3  in quadrature therewith in a vector summation network 47. The vector sums of voltages V 2 , V 4  and V 1 , V 3  are compared in phase detector 45 whose unidirectional output voltage controls the variable gain amplifier 42 in such sense as to restore phase coincidence of the vector sums. From the vector diagram (Fig. 4, not shown) V 3 /V 4  = V 1 /V 2  and if V 1  is made equivalent to V 4  and V 2  equivalent to unity V 4 <SP>2</SP>=V 3  and V 4 =#V 3 . Higher even roots are obtainable by operating plural similar computing circuits in tandem. Fig. 7 shows a modification for extraction of cube roots wherein co-phased reference voltages are applied to input terminals 51, 52, 54 and a co-phased voltage V 7  representing the input variable is applied to terminal 53 while a constant voltage V 2  on terminal 50 representing unity is applied to a 90 degree phase-shift network 55 where output is compared with the output voltage V 4  of a variable gain amplifier 57 energized from terminal 51 in a vector summation network 56, and the output voltage V 3  of a variable gain amplifier 58 energized from terminal 52 is compared in vector summation network 59 with a voltage V 1  equal in magnitude to and 90 degree phase-shifted from V 4 . The outputs of the two vector summation networks 56, 59 are compared in phase detector 61 whose unidirectional output voltage regulates the gain of amplifier 58 in such sense as to reduce the vector sums of V 2  V 4  and V 1 , V 3  into coincidence so that from the vector diagram (Fig. 4, not shown) V 4 /V 3  = V 2 /V 1  and since V 1  is made equal to V 4  in magnitude and V 2  represents unity, V 3 =V 4 <SP>2</SP>, and this voltage is phase-shifted by 90 degrees and combined as V 5  equal in magnitude to V 4  with input voltage V 7  on terminal 53 in a vector summation network 63, while a constant voltage V 6 , 90 degree phase-shifted from the reference voltage on terminal 54, and representing unity, is combined with voltage V 8  equal to V 4  in phase and magnitude in vector summation network 66, whose vector difference output is compared with that of network 63 in phase detector 64, which develops a unidirectional voltage controlling the gain of amplifier 57 in such sense as to zeroize the phase difference between the vector voltages. Then from the vector diagram (Fig. 6, not shown) V 8 /V 7  = V 6 /V 5  and since from above V 5 = V 4 <SP>2</SP> in magnitude, V 8 =V 4  in magnitude and phase, V 6  represents unity, V 4 <SP>3</SP>=V 7  and V 4  = 3 1/#V 7  as required.