Patent GB-1290559-A (GB)
IPC: H01L29/00
Filed: 1970-12-02
Abstract: 1290559 Thyristors LICENTIA PATENT VERWALTUNGS GmbH 2 Dec 1970 [2 Dec 1969] 57344/70 Heading H1K A NPNP thyristor, e.g. for a pulse inverter, comprises a silicon wafer 10 having N-type emitter 11, P-type base 12, N-type base 13 and P-type emitter 14; the base 12 having component regions 12a, 12b, 12c; and inter-regional junctions J 1 , J 2 , J 3 . Annular cathode 15 and circular gating electrode 16 are of gold-silicon eutectic with superimposed vapour deposited chrome-gold-chrome sequential layers while anode 17 is a molybdenum disc alloyed to the silicon through a foil of aluminium-silicon eutectic and externally plated with gold. The bevelled margin of the wafer has an insulating protective layer to prevent breakdown at the surface. The N-type emitter 11 is annular, underlying cathode 15 and leaving annular area 19 adjacent gate 16, while plural distributed P-type shorting passages 12b penetrate the N- emitter and connect region 12a of the P-type base between junction J 2  and region 11 to the cathode. A shorting area 12c at the outer edge of N-emitter 11 connects base region 12a to cathode 15. It is shown by physics that a desirable low value of t q /γ is achieved, where tq is release time and # is charge carrier lifetime (Fig. 2, not shown).  In construction, lapped or etched silicon wafers are cleaned with trichloroethylene, acetone, and aqua regia and thermally diffused with gallium in a closed quartz ampoule from a silicon source into which gallium is dissolved, mechanically spaced from the wafer, which acquires a PNP structure. The wafers are cleaned in aqua regia and thermally oxidized in wet oxygen, after which the oxide is partially removed by hydrofluoric acid etch over a screen printed resist. After further chemical cleaning, phosphorus is thermally diffused into the exposed surfaces in a closed quartz ampoule from a gallium phosphide source to convert the structure into NPNP (Fig. 1); gallium simultaneously diffusing into the entire wafer surface. Thereafter the wafers have a high acceptor surface concentration N A -N D  in the surface areas of regions 12b, 12c and a monotonous fall of such concentration from the surface towards the PN junction J 2 . Certain wafers are withdrawn for determination of geometrical dimensions and dopant concentration of the individual regions, and of the interior carrier lifetime, and test wafers are ultrasonically drilled therefrom, cleaned with hydrofluoric acid, and the regions 12 and 11 removed by lapping. The wafers are etched in nitric, hydrofluoric, and acetic acids and alloyed to form PNN+ test diodes with molybdenum anodes connected to the P-region over a fused-on silicon-aluminium foil, and a gold-silicon cathode formed by alloying antimonious gold foil to the N-region while a N + recrystallized silicon region with antimony doping forms below the cathode. After further chemical etching to remove crystallographically disturbed margins the carrier lifetimes are measured by injectionextraction, and values outside the range 10- 20 ÁS are corrected by further treatment. The processed wafers are provided with electrodes 15, 16, 17 by successive vapour deposition and alloying. The remaining oxide layer is etched off, and a gold layer is vapour deposited for cathode 15 and gate 16 and thermally alloyed, to develop an underlying eutectic of gold and silicon overlying a recrystallized silicon layer; the gold atoms acting as recombination centres in the parts of such region adjoining gallium doped P-regions 12, 12b, 12c to establish high recombination boundary surfaces. A molybdenum anode is connected to the P-region 14 over a silicon aluminium foil. The gold layers are reinforced by vapour deposition of chromium, gold and chromium in succession, while edge 18 is ground and chemically etched over masking to protect the boundaries of N-region 11 and P-region 12. The exposed surfaces, e.g. face 18, are protected with silicone rubber, which is thermally stabilized, pressure contact leads are fitted, and the contacted wafers are encapsulated. In a modification (Fig. 3) the PN emitter base junction is partially shorted by an electrode at least on one side of the wafer. The cathode and anode are in the form of shorting electrodes, and N-base 13 comprises portion 13a between PN-junction J 2  and portions of PN-junction J 3  parallel thereto, and also shorting passages 13b and marginal shorting area 13c between anode 17 and N-region 13a. The thyristor blocks only in the forward direction, and a reverse blocking diode is series connected; giving a high critical rate of rise of positive reverse voltage and short release time. 'The shorted emitter feature may be used at both sides of the wafer, to give a very low t q /#, and the operation is explained by physics. There is a low contact resistance between anode 17 and P-emitter region 14, and the contact between anode 17 and shorting regions 13b, 13c is ohmic of low contact resistance.