Patent GB-1238720-A (GB)
IPC: H02J1/00
Filed: 1968-11-29
Abstract: 1,238,720. Static electrical converter systems. ALLMANNA SVENSKA ELEKTRISKA A.B. 29 Nov., 1968 [1 Dec., 1967], No. 56711/68. Heading H2F. A D.C. and an A.C. network are interconnected by a converter controlled so that each rectifier therein is supplied with a control pulse when the period after the last control pulse to the previous rectifier in the commutation sequence, is equal to the A.C. network period divided by the number of control pulses per A.C. cycle. A member 6 (Fig. 1) derives the network period T by measuring the time between two consecutive zero passages of a phase voltage to give T/2; and divides the period T by the converter pulse number n, where n is 6 in present example. The line voltages are taken out by a transformer 61 the output voltage of which is phase shifted by a unit 62 so that it passes through zero a certain time before the respective line voltages of the network, i.e. a suitable time before the next commutation. A member 5 measures the time t since the last pulse from a pulse generator 18, which controls rectifiers 11-16 via a ring counter 19. The outputs of .5 and 6 are fed to a summation member 4, the output of which is fed to a comparator 7. When the outputs from 5 and 6 are equal there is zero output from the summation member 4 and the comparator 7 will emit a signal which is fed via gates 8, 9 to the pulse generator. A control pulse is accordingly fed to the appropriate rectifier. The output from summation member 4 may be modified by a regulator circuit 3 to vary the delay angle a in dependence upon the difference between the magnitude of the converter direct current and a desired value. The converter direct current is detected by a unit 30 comprises an A.C. fed coil coupled to the D.C. line and a rectifier. The desired value is set up on a potentiometer 33 and the difference if any is fed via a control amplifier 31 to alter the moment of zero passage of the output voltage from member 4 and consequently the times t 1 , t 2  &c. between the control pulses from the pulse generator and the delay angles a are altered. Units 81, 91, limit the minimum and maximum delay angles α respectively. The minimum limit unit 81 is connected to the AND gate 8 and ensures that the signal from comparator 7 cannot be passed to the pulse generator until a certain minimum delay angle has been passed. The unit 91 is connected to an OR gate 9 and delivers a signal to the pulse generator at the maximum limit if the delay angle from comparator 7 is too large. Instead of having fixed minimum and maximum delay angles they may be selectively variable to give a desired minimum commutation voltage U K  and minimum commutation margin angle # (Fig. 4, not shown). If the A.C. network is asymmetrically loaded the regulator will. cause different periods between successive firing pulses. Thus the limit units 81, 91, are arranged to influence-electronic switches 82, 92-respectively. For instance when the minimum limit unit 81 becomes active for the first of the rectifiers, it is arranged to close switch 82 which via a diode 83 discharges. to earth any positive regulator voltage for a certain time and prevents the ignition of two subsequent rectifiers earlier than would occur with symmetrical loading. If a pulse from comparator 7 arrives before a pulse from 81 then a positive pulse from the regulator should be discharged through switch 82. If the pulse from 81 arrives first the regulator voltage must pass freely to the member 4. A logic circuit to control the switch 82 (or 92) from comparator 7 and unit 81 (or 91) is illustrated Fig. 4 (not shown). Similarly too. high a direct current can cause a negative regulator voltage and cause an increase in angle a and when it reaches an upper limit set by unit 91 any negative regulator voltage is discharged through switch 92 and diode 93 to earth so that two succeeding rectifiers cannot ignite later than with an interval of 60 degrees.