Patent GB-991791-A (GB)
Title: Variable monitoring and recording apparatus
IPC: G06F17/40
Filed: 1961-06-05
Abstract: 991, 791. Calculating apparatus; electric signalling. G. W. DIMMICK. (Panellit Inc). June 5, 1961, No. 20284/61. Headings G4A and G4H. In a monitoring system, variable data transducer means are scanned and data is fed to a store for subsequent read-out at a slower rate or is read out immediately. The output is through OSR register 17 and electronic typewriters 6a, 6b. Means are provided for totalizing specified flow variables which are scanned periodically under control of clock pulses. Operation. Flip-flop 21 is set for a new programme cycle and a pulse generated by scan control unit 4d resets ADC buffer storage 12b and transfers thereto the value of the variable scanned from the ADC 12a. Output from the transducers passes through one of amplifiers 10 scaled to produce equally weighted output voltages. Data is fed to an adder 16b and thence to line L5 for read-out or storage, the sign being detected by unit 37. Complimenter 16a permits subtraction of data and a number may be passed direct through the adder using zero unit 96. Drum address system. Block address shift register 40 has five channels in four cascaded stages (Fig. 7c, not shown). When the register is filled the code groups in the 2nd, 3rd and 4th stages are transferred by a pulse to units, tens and hundreds units 44, 46, 48 providing continuous voltage signals. Data may be received from drum address constants register 42 containing block addresses not associated with a variable. Block addresses of linearization tables C are in register 45b and linearization constants register 45a which may also be read into non-destructive units, tens and hundreds storage units 45d, 45e, 45f and thence to comparison matrices 52, 53, 55. Matrices 52, 53 are also connected through "not" gates to storage registers 44, 46 and storage register 48 to channel selection matrix 91. The second inputs of comparison matrices 52, 53, 55 are outputs of units, tens and hundreds counters 58, 60, 61 fed from clock pulse channels 63 or 66 through amplifier 65. Outputs from matrices 52, 53 set flip-flop 71 to operate a word counter 74. To locate a linearization address, outputs of matrices 52, 53, 55 are fed to overall comparison detector 80 to operate flip-flop 71 and gate 73 together with pulses from a word pulse track on line 70. Word counter 74 is reset after every fourth word pulse and is fed to comparison matrix 75 together with the output from the word address storage register 79 fed from word address constants register 81. When coincidence is obtained pulses from matrix 75 to terminals CL of gates 82, 83, 84, 85 control drum pick-up and recording heads through a channel selection matrix 91. Path of information flow. Output from adder 16b is on line L5 with branches B0-B1. . . Branch B0 is to an error detector with a horn 100 and control for shutting off power supply. Branch B1 is to a magnetic core data shift register 104 with outputs to complementer 16a and to adder 16b or through gate 110a to recirculate data through the register, or through gates I11a, I11b . . . to output shift register 17 and thence to electric typewriting devices 6a, 6b which operate with information from clock register 107 and variable identification information from register 113. Branch B2 feeds an accumulator register AR 115 with five stages whose contents may be shifted in either direction controlled by advance pulses on lines AP, A<SP>1</SP>P<SP>1</SP>. Output is either to adder 16b or to multiplier quotient register MQR 118 with four stages which registers together from one large overspill register ARMQ. Shifts may be in one, two or three stages. Multiplication and division of data uses registers AR, MQR and DSR. Figs. 14 and 15 (not shown) show the flow of information for these operations. Branch B4 leads to a magnetic core instruction shift register 127 with four stages leading to a bistable buffer storage register 128 giving continuous voltage signals to decoding matrix 129 leading to programmer 14a, linearization address register 45, and variable identification register 113. Line 154 from decoder 129 sets alarm conditioned transfer circuit in programmer 14a when units digit of instruction is zero indicating normality. Line 22 to scan control 4d indicates when the block address is a scan point. Keyboard 155 sets address register 40 and associated buffer registers 44, 46, 48 and may also feed data to the drum via line B6. Key K-1 is depressed when data is to be fed to section C of the drum. Keys "on demand", "totals demand" and "off normal summary" may be depressed when it is desired to print-out all log entries on the drum or up-to-date accumulated totals or all abnormal variables at a time between the normal print-out of such characteristics. The Specification describes a method of programming the apparatus when flow variables are scanned. The programmer includes a series of stages of magnetic cores MC forming a shift register, which may be triggered, if set in the appropriate state, by a pulse passing through the system to operate the gates and registers of the apparatus. In a first stage a magnetic core 200 is set by a line 202 and triggered by a pulse or line 204 to generate a pulse on line 206 through a rectifier 207 to an "out" terminal which either sets a flipflop 221 or sets the "in" terminal of the next stage. Pulses applied to "time" terminals originating from clock pulse tracks on the drum set a flip-flop 219 for a pulse to the next stage. Stage 3 illustrates a conditional transfer stage wherein a pulse applied to terminal Ti determines whether the output should proceed to stage 4a or 4b through one of gates 230 or 229. The terminals are connected by printed circuit cards or sheets.