Patent GB-742463-A (GB)
Title: Improvements in means for translating information on record cards into electric signals or vice versa
Inventor: POLLARD BRIAN WATSON
IPC: G11C11/23
Filed: 1950-08-20
Abstract: 742,463. Statistical apparatus; digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Aug. 20, 1951 [Aug. 20, 1950], No. 21445/50. Class 106 (1). In means for translating data in the form of separate character-defining punchings or markings in different columns of a record card into electric signals or vice versa, the signals are stored in a device having a separate location for each card column, and the storage locations are repeatedly made accessible in turn in cyclic manner, in synchronism with means for effecting a reading, punching or marking operation under control of groups of repetitive characterrepresenting electric signals. General arrangement. As described, the translating means are employed in the recordcard input and output, Figs. 2 and 11, of an electronic binary digital computer CM, e.g. as described in Specifications 705,479, 731,341 and 742,522. Both the input and output equipment include a C.R.T. store AS, e.g. similar to those described in Specifications 657,591 and 705,474, the scanning system, including the Y-shift generator YSG, providing eight lines on the C.R.T. screen each of five 4-digit sections. These sections each store the binary-coded equivalent of the decimal value represented by a hole 11 differentially positioned in a corresponding column of a record card 10, Fig. 2. The store AS is synchronized with the computer CM so that one line is scanned during each minor cycle or beat comprising twenty active and five blackout digit intervals, Fig. 4, e, and means (not shown) are provided between CM and AS for translating numbers from series-mode binary to the binary-coded decimal form and vice versa. The digit intervals within the 4-digit sections are defined by pulses P0<SP>1</SP>-P3<SP>1</SP>, Fig. 4, i-l, obtained by combining the p-pulses, Fig. 4, f-h, of the computer in circuits such as that indicated in Fig. 6, and the sectiondefining potentials Cc0-Cc4, Fig. 4, m-q, are generated in circuit CTR1, Figs. 2 and 11, under control of selected p-pulses and pulses P3<SP>1</SP>. The circuit CRT2, for generating the line-defining potentials Cl0-Cl7 applied to YSG, comprises a pulse-dividing circuit and series-connected bistable trigger circuits controlled by waveform Cc4 and the black-out waveform, Fig. 4, q and e. Binary-coded pulse trains corresponding to decimal values 9-0 in turn are repeatedly obtained from dymamicisor DSR, Figs. 2 and 11, comprising pentodes V1-V4, Fig. 9, controlled by potentials from brushes CBO-CB3 of a coding commutator 23 rotated by the shaft 48 in synchronism with the card-feeding or punching mechanism. When a brush, such as CB0 and CB3 in the " 9 " position of the commutator shown in Figs. 2 and 11, engages a conductive insert 24, a positive potential is applied to the control grid of the corresponding pentode (VI, V4) so that selected ones (p0<SP>1</SP>, p3<SP>1</SP>) of the inverted pulses p0<SP>1</SP>-p3<SP>1</SP> applied to the suppressor grids are gated and passed through cathode follower V5 to line 52, Fig. 2, or circuit NEC, Fig. 11. The shaft 48 also rotates switch-controlling cams 37, 38 and 32, 33 so as to apply a negative potential to line 60, to open gate GC50 or GC51, only during the operative portions of the card or punch travel corresponding to the width of the holes 11. Gates GC0-GC39, e.g. of the multiple-diode type, each corresponding to a different card column, are opened in sequence in synchronism with the cyclic regneration of the store AS, by selected ones of potentials Cc0-4 and Cl0-7. Some of the elements described above may be used for both the input and output. The C.R.T. store AS may be replaced by a magnetic or mercury delay line store. Other modifications are described below. Input equipment; card-reading. As shown in Fig. 2, the card 10, fed continuously by mechanism 43, 46 operated by shaft 48 is read by brushes B0-B39 which, when they register with a card hole 11, contact the table 20 thereby applying a negative potential via the corresponding gate GC0-GC39, when opened, to the gate GC50 to allow the binary representation of the hole value to pass from the dynamicisor DSR to the write unit 17 of the store AS. When the card-reading has been completed and the store filled, the data thereon may be read out from unit 16 and passed to the computer via gate GC60, e.g. under control of shaft 48. In a modification, the holes are sensed by photo-electric cells the outputs from which control the gates GC0-GC39. Alternatively, the holes may be replaced by printed marks and the photo-electric cells receive light reflected from the card. Output equipment. In the arrangement shown in Fig. 11, series-mode pulse trains representing the 4-digit binary numbers in store AS are applied in succession from read unit 16 to circuit NEC (described below) where they are compared with the pulse trains from the dynamicisor DSR. When agreement occurs, an output pulse is applied during the following 4-digit period through gate GC51, and the particular gate GC0-GC39 then open, to a related control circuit IM39, IMO ... IM38 comprising a hard valve trigger circuit or gasfilled discharge tube. The circuits IM0- IM39 energize magnet coils M0-M39 which lock corresponding punch bars against further movement by shaft 48. When all the punch bars have been differentially set in this way, punching is effected by relative movement between the bars and the card and the circuits IM0-IM39 are reset by a negative pulse applied through cam-controlled contacts 72 and lead 70. The punching mechanism may be replaced by means for printing differentially positioned marks on the card. Alternatively, differentially movable type bars may be used for printing a 40-digit number in a line on the card. Comparing circuit. The two inputs x, y, Fig. 12, to the circuit NEC, to which trains of negative pulses are applied, are connected through cathode followers CF10-CF13 to " or " and " and " gates comprising diodes D10; D11 and D12, D13, respectively. The output of gate D12, D13 is applied to a " not " device comprising a pentode V13 having positive inverted " dash pulses from the computer CM applied to its suppressor grid and having its anode output applied through cathode follower V14 to diode D17, and the output of D10, D11 is applied through V12 to D16. Diodes D16, D17 form a further " and " gate which, if a pulse occurs at x or y, but not both, causes an actuating pulse to be applied to trigger circuit TC10. If this trigger is actuated at any time during a 4-digit period, when it is reset by the trailing edge of inverted pulse p3<SP>1</SP> an actuating pulse will be applied to trigger TC11 whicn will then apply an inhibiting potential to a gate G62 during the following 4-digit period until reset by the leading edge of the following pulse p3<SP>1</SP>. If gate G62 is not inhibited a punch-control pulse p0<SP>1</SP> is allowed to pass over lead 27<SP>11</SP> to gate GC51, Fig. 11. Specifications 645,691 and 682,156 also are referred to.