Patent GB-1068077-A (GB)
Title: Multiplier circuit
IPC: G06F7/52
Filed: 1964-10-09
Abstract: 1,068,077. Multipliers. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 9, 1964 [Oct. 29, 1963], No. 41221/64. Heading G4A. A multiplier comprises a matrix of adders each requiring intervals S, C and R, starting concurrently, to generate sum and carry outputs and become ready for the next addition respectively, S/C and R/C being integers of which at least one is not equal to unity, there being means for applying each multiplicand digit repeatedly to the adder or in rotation to the adders of a corresponding matrix column at intervals C, subject to gating by a train of multiplier digits, the matrix having - R/C rows, and having interconnections between any two columns associated with multiplicand digits differing in order by S/C such that the column associated with the less significant digit has each adder connected to receive a sum output from the other column in phase with the multiplicand digit applied to that adder, the carry output from each adder being applied to the next adder in the same column to receive a multiplicand bit, and the final product being derived from the sum outputs not supplied to adders of the matrix. In the particular embodiments, the (asynchronous) operation of the system is considered to be divided into phases, the duration of one phase equalling C. In the drawings, a number occurring inside each block indicates the phase at which the block gives an output, the phases being numbered to repeat after R/C, e.g. in Fig. 1, R/C= 2 so the phases are 1, 2, 1, 2, 1, 2 &c. In the Fig. 1 embodiment, R = 2C, S = C. The multiplicand bits circulate, once every two phases, in respective storage loops 10a, 10b, 10c, 10d, with 10a holding the most significant bit. The multiplier bits travel along respective storage devices 28a, 28b, 28c, 28d, without recirculation, in four phase times, 28a storing the most significant bit. The multiplier bits are supplied, least significant first, via OR gates 22, 26 to gate (not not) the multiplicand bits to the adder matrix. The first and third multiplier bits (if ONE) gate the multiplicand to the top adder row 40a, 40b, 40c, 40d, and the second and fourth to the bottom adder row 44a, 44b, 44c, 44d. The final product is read sequentially into a shift register (not shown) from the lines 52d, 50d, alternate bits appearing on alternate lines. Fig. 2 (not shown) shows a modification in which R = 3C, S=C which differs from the above in having three matrix rows, three-phase storage loops 10a, 10b, 10c, 10d, and three AND gates for each column of the matrix. Fig. 3 (not shown) shows another similar embodiment for R = 4C, S = C, with four matrix rows. In the Fig. 4 (not shown) embodiment, R = C, S = 2C, and two partial products are formed, using the odd-ordered and evenordered bits of the multiplicand respectively, and then added together in a consolidation adder (80). A one-phase delay (82) is provided to shift one partial product with respect to the other. Fig. 5 (not shown) shows a modification of the Fig. 4 (not shown) embodiment for R = 2C, S = 2C, having two adder rows, two consolidation adders (80) and two delays (82), with means for supplying the multiplicand bits under control of the multiplier bits as in Fig. 1. Figs. 6 and 7 (not shown) show further modifications of the Fig. 4 (not shown) embodiment for R = 3C, S = 2C and R = 4C, S = 2C having three and four adder rows respectively. In the Fig. 8 (not shown) embodiment, having R = C, S = 3C, three partial products are formed, each using one multiplicand bit in three, the first two being then added, one having been shifted one bit position by a onephase delay (82), in a first consolidation adder (80), and the result from this adder being added in a second consolidation adder (90) to the third partial product after the latter has been shifted by a two-phase delay (92). Figs. 9, 10, 11a-11b (not shown) show modifications having two, three and four matrix rows respectively for R = 2C, 3C, 4C, with S = 3C in each case. Figs. 12a-12c (not shown) show another embodiment on the above lines for R = 4C, S = 4C, having four matrix rows and three consolidation adders per row. Storage devices.-Each multiplicand or multiplier bit storage device consists of a chain of one-phase delays preceded by a tunnel-diode majority logic block (threshold 2), with or without a feedback loop (Fig. 17, not shown). Adders.-Fig. 18 (not shown) shows an adder with S=3C, utilizing delays (D), inverters (I) and tunnel-diode majority logic blocks of threshold 2 (M 1 ), each introducing a one-phase delay. Fig. 19 (not shown) shows an adder with S = 2C, the nature of the blocks being as in Fig. 18 (not shown) except for two majority logic blocks (M 2 ) which are like the other such blocks (M 1 ), each followed by an inverter of zero delay. A reference is given for the detailed structure of the majority logic blocks.