Patent GB-1473460-A (GB)
Title: Electronic data processing computer
IPC: G06F9/22
Filed: 1975-07-16
Abstract: 1473460 Digital computers Ing C OLIVETTI & C SpA 16 July 1975 [21 Aug 1974] 29870/75 Heading G4A An electronic computer comprises a first memory for instructions and data, a second memory addressable by the instructions to provide sequences of microinstructions, and a third memory addressable by the microinstructions to provide sequences of one or more nanoinstructions, a logic unit (e.g. ALU) and a plurality of registers, each nanoinstruction having a group of signals to select operations and a group of signals which are serialized and supplied to the registers to control timing of operations. As disclosed, there are two ALU's (for high and low order bits respectively) fed from respective sets of working registers and feeding via switching and shift networks to two buffer registers which feed to a peripheral channel unit and also back to the working registers. Signals from the channel unit are fed into the switching and shift networks, as are signals from a condition unit and a memory register fed from the first and second memories. The first and second memories are respectively RAM and ROM parts of a common memory, and the third memory is a ROM. Each nanoinstruction has a first group of fields, supplied in part via a decoder, to partially control the condition unit (also responsive to the ALU's), select inputs at the switching and shift networks, select one of these networks to feed one of the buffer registers, control the ALU's and select the sets of working registers, the decoder controlling e.g. the channel unit. Each nanoinstruction also has a group of bits to enable (subject to timing signals) writing into working registers, condition unit register, common (first and second) memory address register, to inhibit writing into a working register, and to indicate whether one or two nanoinstructions are used for the execution phase of the microinstruction (the read-out phase requires the nanoinstruction), respectively. This last bit, if 1, increments the third-memory address. Each nanoinstruction also has a group of timing bits which are serialized on read-out and supplied to the registers to time write-in into those currently selected by the enabling bits (see above): the series of timing bits consists, say, of a series of 0's to define a first time interval by its length, then a series of l's to define another, and so on. A field of the microinstruction is used to select register(s) within the selected set(s) of working registers. The channel unit handles peripheral microinterrupt requests according to priority level, interrupt of a granted request by one of lower priority being prevented by inhibiting strobe pulses (relating to the relevant priority levels) normally used for sampling microinterrupt requests at the end of each microinstruction. One bit of the microinstruction indicates whether the input of the common memory address register should be loaded thereinto directly or with a one-bit shift to the right (division by two), according as the ROM or RAM portion is being accessed (these having 16 and 8 bit parallelism respectively). The serialization of the timing bits of the nanoinstruction is stopped during the cycle of the common memory.