Patent GB-1361353-A (GB)
Title: Data transmission system
IPC: H04L12/423
Filed: 1972-10-06
Abstract: 1361353 Data transmission system INTERNATIONAL BUSINESS MACHINES CORP 6 Oct 1972 [14 Dec 1971] 46154/72 Heading G4H [Also in Divisions H3-H5] In a data transmission system comprising a central station arid a plurality of remote stations connected in series in a loop, the central station includes means for transmitting a control signal authorizing transmission of data from the remote stations followed by an uninterrupted series of like signal bits and each remote station has means for detecting the control signal, then detecting the presence of N consecutive like bits in said series, initiating the transmission of data from the remote station, if required, after the detection of N consecutive like bits, means responsive to the receipt of N+1 consecutive like bits to continue data transmission and means responsive to a different bit after said N bits to inhibit data transmission. The first data bit transmitted by a station is different from the N bits so that downstream stations on the loop are inhibited. As described the N bits are a chain of nine "1"s. The drawing shows one remote terminal on the loop and data from the central terminal flows from left to right along line 15. The circulating information is picked up by detector 20 which has a first output for "1" pulses and a second output for "0" pulses. The 1 pulses are fed to counter 22 and both types are fed to shift register 26 which is clocked by pulse movement along line 15 and contains a constantly updated history of bit patterns on the line 15. The 0 pulses are also led via OR gate 23 to reset the counter. The shift register contents are read by decode logic 25 which provides an output on one of several lines I, U, A1, A2 when a particular bit combination is in the register. The terminal comprises an I/O terminal 18 for receiving and transmitting data which, when it requires to transmit data provides a "SERV NEEDED" signal which enables AND gate 28. The 9 output of the counter is connected via AND gate 28 to TRANS LATCH 29 which operates switch control 31 to move switch 16 from P1 to P2. The TRANS LATCH is released at either a count of 0 or on end of message (EOM) signal from the I/O terminal. The 10 output of the counter sets MEM LATCH 27 which inhibits further input to the counter. Transmission remote to central.-The central station transmits coded pattern U which resets counter 22 to zero. This is followed by a string of "l"s. Assume that the terminal is first on the loop and requires to transmit. When nine "1 have been received, LATCH 29 is actuated, switch 16 moved to P2 and the first output digit (which is always a "0") is sent via stuffing circuit 38 (described later) on to the loop. At the next incoming "1" the counter steps to 10 and further input is inhibited so that the transmission can proceed. The signal received by the next remote station is nine "l"s followed by the 0 transmitted from I/O circuit 18 and thus resets its subsequent stages counters and prevents transmission. At the end of the message the latches and switches are reset by the EOM signal. The stuffing circuit 38 inserts a 0 after each sequence of eight "l"s that may occur in the data and the destuffing circuit removes a 0 from after a sequence of eight "l"s in incoming data. Transmission central to remote.-The station may have a unique address A1 or an address A2 relating to a group. On receipt of its unique address Al, RECV LATCH I (32) is actuated and switches 16 to P2, the I/O terminal to receive and starts "l"s generator 34. While the message is being received via destuffing circuit 37 a string of "1"s is transmitted round the remainder of the loop so that later stations may transmit data. When a group address A2 is received, switch 16 stays in position P1 and the "I"s generator is not enabled so that the data can be received by all addressed stations. Alternative embodiments.-The means at the remote station for receiving data from and inserting data into the loop may be a shift register having at least one bit of storage and arranged in the loop and clocked by a three phase clock which, in the first phase shifts transmitted data out and receives new input data, reads and samples in the second phase and inserts new data in the third.