Patent GB-1458200-A (GB)
Title: Computer performance monitoring
IPC: G06F11/34
Filed: 1973-12-04
Abstract: 1458200 Monitoring data processors XEROX CORP 4 Dec 1973 [5 Dec 1972] 56228/73 Heading G4A Signals representing both hardware and software related conditions are supplied to a monitoring system 20 via an interface 28 which is responsive to control signals to vary the format (including the way in which the signals are logically combined with each other) and the selection of signals to be supplied to the monitoring system according to a plurality of monitor programs run in cyclic sequence. The control signals 44, 45 are supplied as direct I/O commands from a host CPU 23 which executes monitoring programs and which in practice may be the same as the subject CPU 22 whose performance is being monitored. The subject system may be run in a multiprogrammed time-sharing mode in which case the software related conditions may be user identifiers for the currently running program. Monitor interface 28 includes signal conditioning and switching logic interconnected by patch panel wiring on a replaceable plugboard having a wired-in identification code which can be read by the host CPU to check that the plugboard is compatible with a particular monitor program being run. A write direct command from the host CPU includes a field which determines the manner in which other command fields are to be used, and fields for controlling the interface conditioning and switching logic are stored in flip-flops in the interface to allow read-back and checking by the host CPU and to allow other write direct commands to supply software identifiers, memory addresses, instruction OP codes and so on, with the interface in the same conditioning/selection configuration. The interface may also recognize when the subject CPU is in master (executive) or slave mode to stop and start a timer in the monitoring system 20 so as to exclude "overhead" programs from measurement. Different clock rates for the timer are selectable in the interface and it is also possible to arrange the interface so that the last core memory address accessed by a subject CPU instruction is loaded into the monitor register 32. Monitoring system 20 includes associative and buffer processors 37, 38, Fig. 2, each of which is program controlled to process the information supplied to it by the interface 28, the programs being loaded into the respective control memories by the host CPU. In general, the associative processor 37 controls the transfer of a plurality of bytes from the monitor register 32 to an associative memory 35 where read, write and compare operations may be performed, and the buffer processor 38 controls the transfer of a sequence of individual bytes from the associative and buffer memories 35, 36 to the input registers 63, 69 of those memories, the bytes undergoing specified modifications during the operation, whereby data may be accumulated in the buffer memory 36 to represent monitored parameters. As an example, to examine the instruction mix in a particular program running in the subject CPU, the associative memory 35 is loaded with all the possible instruction OP codes and a corresponding word in buffer memory 36 is incremented each time a given OP code is encountered. Associative processor is triggered by the interface 28 when a specified event, e.g. an instruction fetch in the subject CPU, has occurred, though not every instruction need be monitored in this way. Each associative processor instruction can specify the loading of a register 61 from monitor register 32, the loading of a constant register 72 from a constant field of the instruction and the selection of four particular bytes in registers 61, 72 by a switching matrix 62. A mask register 64 of the associative memory 35 may also be loaded from a literal mask field of the instruction. The OP code of each instruction determines the operation performed in associative memory 35, word match indicators being set if a compare operation is performed. A buffer processor control field in each instruction determines the conditions in which operation of the buffer processor is required, e.g. start if there is a set match indicator in memory 35 or unconditional start. The next instruction to be executed is selected by a next instruction address in the current instruction or by a branch address if specified conditions, e.g. presence of a match in memory 35, or buffer memory 36 full, are satisfied. If a stop flag is set, execution of the next instruction awaits a run command from the host CPU or a manual control panel. Buffer processor 38 is started (by the appropriate control field of an associative processor instruction) at a corresponding instruction in its program i.e. initiation by the nth associative instruction starts the buffer processor at its nth instruction. Each instruction of the buffer processor program can specify reading of a series of sequential bytes from memory output registers 65, 66, a memory address register (in block 74), a timer buffer register 67 or constant register 72 to either of registers 63, 69. Other fields of sequential bytes may also be transferred from register 66 to register 69. The OP code of each instruction allows each field transferred to be incremented, decremented, passed unchanged, increased by the timer buffer or constant register contents or replaced by the timer buffer contents if the latter are higher (or lower) than the field. Writing of the register 69 into memory 36 may also be specified, and if a hold flag is set execution of the next instruction awaits a start signal from the associative processor. Monitor control programs are stored in a magnetic tape or disc memory of the host/ subject computer system and are accessible to users to allow addition or deletion of programs, program listing, generation and play-back of history files, and selection of programs for controlling the monitor sytem. The history files are built up from information read from the monitor system under control of direct read commands from the host CPU. A user can select the set of programs to be run cyclically, each for a specified number of sampling intervals. Between sampling intervals the accumulated data are read into a history file and the control memories of the monitor system are loaded with the next control program.