Patent GB-712034-A (GB)
Title: Improvements relating to computing apparatus
Inventor: REY THOMAS JULIUS
IPC: G06F17/17
Filed: 1950-05-10
Abstract: 712,034. Digital electric calculating-apparatus. ELECTRIC & MUSICAL INDUSTRIES, Ltd. May 4, 1951 [May 10, 1950], No. 11578/50. Class 106 (1) Apparatus for effecting computations of a form where {aij} denotes a vector with components aij... anj, comprises a multiplying device having two inputs, stores for the values x 1 , x 2  ... xn respectively connected by a first series of gates to a first multiplier input, groups of vector component stores for separately storing the values of the vectors {ai 1 }, {ai 2 } ... {ain}, a second series of gates, one corresponding to each group of stores, having their outputs connected to the other multiplier input, a third series of gates respectively connecting the vector component stores individually to corresponding gates of the second series, means for opening the gates of the first series in predetermined succession to feed x 1  ... xn successively to the first multiplier input, means for opening the second series of gates in similar succession, and means for opening the third series of gates in more rapid succession, so that the required products x 1  {ai 1 } ... xn {ain} are formed, and an adder for adding the resultant individual products in groups, each group containing only products having the same i-number. The electronic digital computing apparatus illustrated is designed to find the value Y of a function of n independent variables x 1  ... xn, where the nearest tabulated value is Yo at the point (#X 1  ... #Xn), according to the interpolation formula Xi, Xj=#Xi, #Xj, and # may indicate a differencing rather than a differentiating operation. In the apparatus, it is assumed that aij=aji so that the formula reduces to y= <SP>#</SP> i xi [ai+#xj j  aij] the factor ¢ being introduced when i=j, and n(n-1/2) of the coefficients aij being zero. As shown in Fig. 1, 2 coefficients for each value of i are taken to be zero (since n=5). The evaluation of Y is divided into four part(s MAC I-IV) the first three of which are illustrated in Figs. 1-3 respectively. MAC I consists in the formation of the column matrix or vector {#ai} = #xj j  {aij} =[Aij} (xj) where (aij) are column vectors formed from the columns of the square matrix [aij] and (xj) is a row vector. In MAC II, the column vector {u<SP>1</SP>i} is found where {ai}={ai}+{#ai}. MAC III produces y=(xi).(a<SP>1</SP>i), and MAC IV produces Y=Yo+y. The computing apparatus comprises a circuit, as described in " Report on a Conference on High Speed Automatic Calculating Machines " (Cambridge University Mathematical Laboratory, Jan. 1950) pages 41-46, for multiplying positive or negative numbers represented by seriesmode pulse trains. The control circuits (not shown) provide pulses P1-P12 and P<SP>1</SP>1-P<SP>1</SP>7 defining the digit pulse intervals # from a main clock and slow clock (or " slock ") respectively. The cycle of " stock " is normally completed by P<SP>1</SP>6, P<SP>1</SP>7 introducing a delay to retard the slock " relative to the main clock as described below. The control circuits also include counters CX, CV which count up to ten and five respectively to provide gating potentials 0-9 and 0-4. CX is advanced by pulses P<SP>1</SP>1. A master counter MAC receives a pulse at the end of each part of the computation, and further scale-of-two counters are provided for distinguishing between odd and even cycles, e.g. of the clock. The quantities xi, ai (of 12 digits) and aij (6 digits) are held in stores, Figs. 1 and 2, e.g. of the mercury tank or magnetic delay line type. The quantities xi are dynamicized by clock pulses and ai, aij (which may have been originally obtained from punched cards) by " slock " pulses. During MAC I, the multiplying circuit has its terminals P<SP>1</SP>l, P<SP>1</SP>p, Pp-1 and Cm connected for receiving control pulses, as shown in Fig. 1, and its terminals U1-U4 connected for receiving data from the stores for xi and aij and passing computed results to a store T2 of delay length 60#=2pn# where p is the number (6) of digits in a standard word. T2 could be replaced by five separate stores and switching means. During the first sub-part I 1  of MAC I, potential CVO opens gate Gxl so that x1 is applied via u1 to trigger L. The first six digits are ignored in this calculation but the seventh, coinciding with pulse Pl 1 (even cycle), is staticized by L for a whole " stock " cycle until the trigger is reset by pulse P<SP>1</SP>6 (even) via one-digit delay D1. Potential CVO opens also gate GVI, and potentials CX1, 3 and 5 open gates CV 1, 2 and 3 respectively so that the non-zero elements of the vector {ail}. spaced by 6# intervals, are fed via u2 to the multiplying circuit, during even slock " cycles, so that the product {ail }.x1 (seventh digit) is formed. At every tenth slock " cycle, delay pulse P<SP>1</SP>7 is introduced so that during cycles eleven to twenty, {ail} is similarly multiplied by the eighth digit of x 1  and so on, the product x1 {ail} being obtained after sixty cycles. Counter CV is advanced by the coincidence of pulses P6 and P<SP>1</SP>7 so that gates Gx2, GV2 are then opened by potential CV 1 to form similarly during MAC I2 the product x2 {ai2} which is added to x1 {ail} stored in T2. Similar operations occur during sub-parts MAC I3-I5 so that at the end of MAC I, {#ai} = #xj j  {aij} is available in T2. The elements #ai of 12-digit length are subjected to a "tailing and topping" operation in unit TATO, which operation commences 6# intervals before the start of MAC II and the transmission of the elements ai via gates Ga1-Ga10, opened by potentials CXO-9, and terminal U5 to the adder of the multiplying circuit. No delay in " slock " occurs during MAC II and the addition to produce vector (a<SP>1</SP>i) in T2 is performed during once cycle of CX. For MAC III, Fig. 3, store T2 is connected to multiplicand terminal U2, and another store T3 is connected to receive the 24-digit product y=(xi). {a<SP>1</SP>i.} Counter CV is advanced at the start of each odd " slock " cycle so that, due to the control pulses applied to P1, P<SP>1</SP>p, trigger L staticizes the first digit of x1 for " slock " cycles 1 and 2, the first digit of x3 for cycles 5 and 6, and so on in the order xl, x3, x5, x2, x4, these digits operating on the corresponding components, a<SP>1</SP>i in T2. Thus after 120#, the vector {a<SP>1</SP>i} has been multiplied by the first digits of all the elements xi. At this stage, a delay is introduced in the " slock " (i.e. P<SP>1</SP>7 occurs after the twentieth cycle) and the vector-representing pulse train is delayed one digit period by a unit D switched into series with store T2 (i.e. D is operative after 60# and remains in circuit for 61#). This causes the second digits of the elements xi to be effective during the next two circulations of {a<SP>1</SP>i} in T2. This process continues until (xi) {a<SP>1</SP>i} is accumulated in T3. MAC IV is similar to MAC II and is not described in detail. It is stated that the invention may be applied to a parallel-mode computer.