Patent GB-1282177-A (GB)
Title: Integrated circuit interconnections
IPC: H01L23/29
Filed: 1969-09-09
Abstract: 1282177 Integrated circuits HUGHES AIRCRAFT CO 9 Sept 1969 [25 Sept 1968] 44483/69 Heading H1K A standard interconnection pattern is used to interconnect the elements on each individual one of similar wafers. Since the location of good and defective elements varies from wafer to wafer, good elements are found by testing and the contacts of the required number of these are relocated as necessary to standard positions of the subsequently formed interconnection pattern. This is effected by coating the wafer with an insulating layer, by exposing the contacts of the required good elements, and by forming conductive tracks to terminal pads formed at the standard positions. All subsequent steps in forming the interconnection pattern are then the same for similar wafers and may employ standard stencils or standard programming of a scanning light pen for exposing the various photoresist layers. Part of a typical wafer is shown in Fig. 5a. Here the top right quadrant 28 represents the physical location of a good element and the lower left quadrant 30 a position occupied by a defective element but at which the standard pattern requires a good element. (The other two quadrants in this case are occupied by defective elements but in general some good elements are superfluous). An overall insulating layer is applied and is penetrated by lead-throughs only at pad locations 24. Conductive tracks 32 are formed over the insulation and are connected to further pads 24<SP>1</SP> which lie on top of the insulation only. Thus the good circuit is effectively relocated in quadrant 30. (The Figure shows also the location of optional metallization 100 to be used later in the formation of cross-unders in some standard interconnection patterns). A further insulating layer is applied, apertured to expose only pads 24<SP>1</SP> which lie at the standard positions. From this point processing continues to be the same for all wafers. The wafers may have insulation lined pockets containing the elements. This insulation may be made wide in plan to act as a bearing surface for the relocation tracks to avoid running them over adjacent elements with possible need for extensive cross-unders. Each element may be designed so that it may be connected as a single circuit unit though formed as, say, four independent sub-units. If desired such sub-units may be relocated to different standard positions. At these they may also be combined with relocated sub-units of different elements. An element may be relocated as a whole but the relative disposition of its sub-units may be transposed during relocation. Elements may be relocated into circuit groups of a predetermined pattern and these groups then relocated en bloc to the standard position. The location of standard positions may take notice of the expected density of good circuits on the wafer-thus there will normally be a greater density of standard positions near the centre of the wafer than towards its edges. (Predetermined relocation may be used from expected areas of high density of good circuits to more disperse standard positions to allow better heat dissipation and readier access to bonding areas). Detail is given of the relocation and standard interconnection but the processing steps are largely conventional. Aluminium or gold is used for lead-throughs and conductive tracks, and low-sodium glass or silicon is used for the insulating layers. When an insulating layer is deposited, hardened photoresist is left at the desired location of lead-through apertures. When the structure is heated the difference in expansion of the photoresist and insulation is sufficient that the insulation breaks up over the photoresist and may be readily removed exposing the photoresist which may be removed conventionally.