Patent GB-1035520-A (GB)
Title: Data storage device
IPC: G11C11/06
Filed: 1963-12-24
Abstract: 1,035,520. Magnetic information storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1963 [Dec. 31, 1962], No. 51016/63. Heading H3B. [Also in Division G4] In a coincident current-memory matrix energizing means are provided to selectively energize (a) all column read drive lines and simultaneously a selected one of the two read drive lines and (b) a selected one of the column read drive lines and simultaneously a selected one of the row read drive lines. In the arrangement shown in Fig. 1, the columns P 1 , P 2 , P 4 , Q 1 , Q 2 , Q 4  and R 1 , R 2 , R 4  each define a data bit with the column groups P, Q and R representing character positions within the data word defined by rows A, B, C. Parallel Read.-The desired row address is fed into decoder 3 and then to one of the lines 5, 6, 7 connected to gate inputs 8-9, 10-11, 12-13 of row drivers WD-A, RD-A, WD-B, RD-B, WD-C, RD-C so as to condition these drivers. At the same time a parallel mode signal developed by read selector 21 is passed to gate terminals 23, 24, 25 of column read drivers RD-P, RD-Q, RD-R to condition the latter. A read timing pulse from 29 on line 30 then causes all the drivers having conditioned inputs to produce half select currents on output lines 33 or 35 or 37 and 38, 39 and 40. Those elements where row and column driver lines intersect are driven towards negative remanence and those elements initially at positive remanence induce a current in the associated sense winding 42-50 connected to sense amplifiers SA-P1, P2, P4, SA-Q1, Q2, Q4 and SA-R1; R2, R4 to provide a signal on lines 51 to 59 and set the associated triggers P1, P2, P4, Q1, Q2, Q4 and R1, R2, R4 of data register 60. Parallel write.-Register 60 is first cleared and information to be written is entered by setting the appropriate triggers which have output lines 61-69 connected to gate terminals of word drivers WD-P1, P2, P4, WD-Q1, Q2, Q4 and WD-R1, R2, R4 so as to condition the drivers when the triggers are in the binary 1 state. Write drivers WDA, B, C are conditioned by decoder 3 so that when a timing pulse from unit 79 is fed over line 80 these drivers having conditioned inputs are activated to produce half select currents in one of the lines 32, 34, 36 and lines 90 to 99. Timing unit 79 also applies an inhibit signal to the sense amplifiers during the write operation. Serial read.-In this operation only one character at a time is read out so that one of the row drivers RDA, B, C is conditioned as for Parallel Read and one of the column read drivers RDP, RDQ, RDR conditioned by a signal on one of lines 115, 116, 117 from character address decoder 113. A timing pulse from unit 29 then causes half select currents on one of the lines 33, 35, 37 and one of the lines 38, 39, 40 so that elements acted on by coincident currents which change state induce signals in sense lines 124, 125, 126 wound to include all elements of a particular bit in all characters and all words, and connected to sense amplifiers SA-1, 2, 4. The outputs of the sense amplifiers are connected by lines 127, 128, 129 to the " 1 " trigger inputs of T1, T2, T4 and thence to output data lines 131, 132, 134. Serial Write.-Row address is first fed to decoder 3 so as to condition one of the row drivers WDA, B, C and a character address is fed to decoder 113 so as to produce a signal on one of the lines 115, 116, 117 which selects one of the group of column write drivers through AND gates 136, 137, 138. In order to select the Q character AND gate 137 is conditioned so that a timing pulse from unit 79 on line 80 causes half select currents on output lines 94, 95, 96 of write drivers WD-Q1, Q2, Q4 which have been conditioned by the output from triggers T1, T2, T4.