Patent GB-1302231-A (GB)
IPC: G01R19/25
Filed: 1970-03-13
Abstract: 1302231 Analogue to digital converter JOHN FLUKE MFG CO Inc 13 March 1970 [14 July 1969] 12182/70 Heading G4H An analogue to digital converter comprises a differential amplifier A1, receiving an analogue input 10 and a first negative feedback path operable over a first digit period to derive from the output a variable voltage proportional to the first digit value of the input and a remainder feedback path to apply a second negative feedback signal proportional to the arithmetic difference between said first digit value and said input, storage means such as capacitor 38 connected to said remainder feedback path for deriving and storing a recirculatable remainder analogue signal proportional to said difference multiplied by the digit base and control means connected to said storage means for applying said recirculatable remainder analogue signal substitutionally for said input analogue signal and causing reoperation of the differential amplifier to derive the second digit value of said input analogue signal. As described, a positive analogue input appears at 10, and is fed to amplifier A1 via switch S1. If the input is negative it is fed to 10<SP>1</SP> and passes through a polarity detector 16 which causes switch Sl<SP>11</SP> to close shorting terminal 12 to earth. The output of amplifier A1 is fed to two comparators, comprising Q4 and Q5, and Q2 and Q1 respectively. If the output is less than 10 volts then no signal is obtained on unit 22 and the output of Q1 and Q2 passes through a voltage divider comprising resistor 32 and the resistance of decade ladder 26, to appear as a negative feedback input on amplifier A1. The voltage divider 26 divides the voltage by a factor of 10. Feedback voltage which appears at 34 is in this case a remainder voltage. The remainder voltage multiplied by 10 is stored on either capacitor 38 or capacitor 40 depending on which of switches S4 or S5 happen to be open. If the voltage is greater than 10 volts then a signal is incident on current controlled oscillator 22 which sends a series of pulses, the number of which depends on the number of units of 10 volts incident on the comparator, to single decade counter 24. This switches the single decade ladder divider network to provide a voltage proportional to the input, which appears on the amplifier Al as a negative feedback. The single decade counter 24 also operates a binary digital decoder 60 which operates the Nixie tube indicator. During the balancing operation as different parts of the ladder network are switched, the voltage incident on the comparator falls, eventually it falls below 10 volts, so that no further pulses are emitted by currentcontrolled oscillator 22. When this happens the comparator circuit comprising Q1 and Q2 operates as it does when the initial voltage incident on the comparators is less than 10 volts. When the value of the first decade has been determined and the remainder stored on capacitor 38, the input is isolated from amplifier 12 and the stored value of the remainder multiplied by 10, stored on capacitor 38 is fed to the input of amplifier A1 via switch S2, say, the switch S5 is closed and switch S4 is opened. The next digit is then determined by the unit operating in the same manner as before, this time the remainder being stored on capacitor 40. In this way the analogue signal'is digitized one digit at a time, and the remainder signal is stored at each stage on capacitors. In a second embodiment, the analogue signal may be stored in its entirety on a bank of capacitors, and switched into the input. In this way, the system locks on to a particular reading.