Patent GB-754206-A (GB)
Title: Improvements in or relating to regenerative telegraph repeaters
Inventor: BREWSTER ARTHUR EDWARD
IPC: H04L25/24
Filed: 1954-04-06
Abstract: 754,206. Telegraph regenerative repeaters. STANDARD TELEPHONES & CABLES, Ltd. April 6, 1954, No. 10033/54. Class 40 (3). An electric telegraph regenerative repeater for mark-space signal combination employs crystal triode devices throughout for the various trigger and counting circuits. The regenerator employs normal mid-point sampling of incoming signals, and has provision for inserting a minimum length of stop signal and false start suppression. The regenerator is also arranged to regenerate a permanent space condition. The invention is described as applied to the conventional five-unit start-stop signalling code although it may be applied to signals generated at regular intervals (e.g. from perforated tape) as described in Specification 721,838. General arrangement, Fig. 1. The timing of the whole circuit is controlled by a 5.4 Kc/s. crystal oscillator 11, the output from which is applied to counters 12, 13 and 14 having counts down of 54, 2 and 6 respectively. A first pulse from counter 13 appears after 10 mins. and thereafter pulses appear after every further 20 mins., i.e. at the centres of correctly timed incoming signal elements. Counter 14 does not become operative until after the first pulse from counter 13 and produces a pulse therefore at 10+6Î20=130 mins. Counters 12 and 13 are normally held inoperative and controlled by a bistabletwo-condition trigger device 15, the primary reset device, whilst counter 14 is controlled by a second trigger device 16, the secondary reset device. Incoming signals are received on relay 1 and control the potentials of mark and space leads 2 and 3, lead 2 becoming of zero potential for mark and 4-15 volts for space whilst the reverse conditions are produced on lead 3. A trigger pulse generator 4 produces a positive pulse on each signal transition. The outgoing signals are generated by relay 8 which is controlled by the current from a pair of trigger devices 9, 10 which are interconnected at 20 so as to form a flip-flop device, the triggering of one extinguishing the other. The devices are conditioned in accordance with the potentials on leads 2 and 3, and triggered by positive pulses from counter 13 over conductor 82. On receipt of the start space signal, a positive pulse is sent from trigger pulse generator 4 to trigger primary reset device 15 and start the count. At 10 mins. the first pulse matures from counter 13 and triggers flip-flop device 9, 10, now conditioned for space over lead 2, and sets the outgoing relay correspondingly to space. The pulse also trigger the secondary reset device 16 and releases counter 14. The further pulses maturing at 30, 50, 70 mins. &c. then trigger the flip-flop device 9 and 10 back and forth in accordance with the conditions appearing on leads 2 and 3 and so regenerate the incoming signal. At 130 mins., i.e. at the mid-point of the stop signal, a negative pulse is produced from counter 14 and over lead 40 resets both the primary and secondary reset devices 15 and 16 to reset and block the counters. The circuit has now reverted to its original condition and is ready to receive a further signal combination. Minimum length of stop signal. In order to ensure a minimum length of stop signal a positive pulse is also produced from counter 14 at 130 mins. and applied over lead 42 to trigger a short stop convector circuit 18. This circuit, when tiiggered, resets in a time which may be adjusted between, say, 8 and 18 mins. and provides a blocking pulse which prevents the primary reset device from being retriggered by a following start signal. False start suppression. To prevent the regenerator being put through its cycle of operation in response to a false start signal, e.g. interference, lasting for less than 10 mins., a gate 19 is provided connecting a negative output from counter 13 back to the primary reset device. The gate is normally blocked during the start interval by a potential from space lead 3 applied over conductor 118 but should the incoming signal revert to mark the gate opens and allows the pulse at 10 mins. from counter 13 to trigger the reset device and stop the cycle of operations. After 10 mins. during normal operation the gate is held blocked by a potential over conductor 119 from the secondary reset device. Reset device 15 restores counter 12 directly and restores counter 13 by means of a false start reset device 17 the need for which arises due to a difference in the circuits of counters 12 and 13 (see below). The 10 mins. pulse from counter 13 to flip-flop device 9, 10 effects no change since the incoming condition at this time has reverted to mark. Permanent space condition. In the event of a permanent space condition appearing on the line as may occur in certain exchange systems, the regenerator is started in the normal manner, regenerates as though all the signal elements were space and rests with the outgoing relay correctly at space. Upon the reversion to mark condition, the regenerator is again started by trigger pulse generator 4 but restores after 10 mins. as described above for false start operation. Relay 8 is however set to mark by the 10 mins. pulse from counter 13 since the incoming conditions remain reversed. Oscillator, counters and false start reset device, Fig. 4. The oscillator comprises a crystal triode 54 together with a 5.4 Kc/s. piezo-electric crystal 58 and is constructed as described in Specification 728,866, [Group X]. The negative half-cycles of the output are selected by rectifier 78 and applied to trigger the first stage 65 of counter 12 at the base. The counters are arranged as described in Specification 754,154, [Group XL (c)], with positive triggering between the collector of one stage and the emitter of the next succeeding stage. When triggered the emitter of a stage goes negative to 15 volts (the potential of supply 63) and then restores to the triggering level in a time determined by a C.R. coupling. The restoration time determines the count of a stage. In counter 12, stage 65, 66, 67 and 68 count down by 3, 3, 3 and 2 respectively. Holding or catching rectifiers 72-75 are brought out to a common connection 76 which extends to the primary reset device (see below). The potential on this connection is normally - 15 volts which holds the counters cut off, but when the reset device is triggered the potential becomes - 3 volts and allows the potentials of the emitters to rise towards the trigger level. The first stage triggers on the third pulse from oscillator 54 and therefore the first output pulse from the final stage occurs at 54/5.4=10 mins. Counter 13 comprises a single stage 69 arranged to count down by 2 but the holding rectifier 70 is connected directly to a - 3 volt supply 71 so that the stage responds to the first trigger pulse from counter 69. An output is derived therefore at 10 mins. and thereafter pulses appear after every further 20 mins. The positive pulse outputs are derived from the collector circuit at leads 81 and 82 and the negative pulse output at lead 84 via transformer 83. Stage 86 comprises the false start reset device and comprises a trigger stage responsive to a negative pulse from the primary reset device over lead 21 to restore counter 69 within a period less than 10 mins. so that it may be ready to respond to the first of any pulses produced by counter 68. The stage is normally conducting and when triggered cuts off to render rectifier 91 conducting and connect resistor 87 in parallel with resistor 92 to reduce the time constant of the C.R. coupling network to the counter. Counter 14, Fig. 5 (not shown), comprises two stages dividing by 3 and 2 respectively and arranged as described in Fig. 4 but having the potential of their holding rectifiers controlled by the secondary reset device. Primary reset device, gate and short stop corrector, Fig. 6. The primary reset device employs a crystal triode 102 arranged in a trigger circuit as described in Specification 740,056, [Group XL (c)]. The stage is normally conducting with the emitter and base substantially at - 15 volts (the potential of supply 63). When a positive going trigger pulse arrives on the collector over lead 6 from generator 4, the base potential rises and cuts off the emitter whose potential is arranged to rise less rapidly by a capacitor 111. The base potential rises to E potential where it is held by rectifier 105 connected over lead 40 to earth in counter 14. On cessation of the trigger pulse the stage remains cut off since the trigger rises to only - 3 volts, the voltage of supply 108, where it is held by rectifier 107. The change in emitter potential from - 15 to - 3 volts is applied over lead 76 to trigger on counter 12. The crystal triode is triggered on again by the negative pulse from counter 14 over lead 40. - The pulse drives the base below the emitter potential of - 3 volts and so causes the triode to conduct. The resulting sudden fall in base potential is communicated over conductor 21 and triggers the false start reset device 17. Gate 19 comprises rectifiers 113-116. During normal operation earth potential from conductor 3 over lead 118 allows rectifiers 115 to short circuit the negative pulse from counter 13 on lead 84 and prevent triode 102 from being triggered on. In the event of a false start signal, lead 1'18 returns to - 15 volts and rectifier 115 becomes non-conducting. Rectifier 116 connects with the secondary reset device which applies earth to lead 119 after 10 mins. to hold the gate shut. The short stop corrector 18 comprises a crystal triode 120 connected as a trigger circuit and normally conducting so that the base is at substantially - 15 volts. The stage is triggered by the positive pulse from counter 14 at 130 mins. which is applied over lead 42 to the collector. The rise in base potential cuts off the emitter, the circuit restoring in a time determined by C.R. circuit 124, 125. The positive pulse from the base renders re