Patent GB-1338731-A (GB)
Title: Data processing system
IPC: H03M7/42
Filed: 1972-01-28
Abstract: 1338731 Coding and decoding INTERNATIONAL BUSINESS MACHINES CORP 28 Jan 1972 [3 March 1971] 4053/72 Heading G4C Fixed length code words are encoded into variable length code words having variable length prefix portions, each prefix uniquely representing a particular word length, and variable length remainder portions, decoding then being effected by using the prefix portion to derive a base address for a memory storing the corresponding fixed length code words to which address is added an address corresponding to the remainder portion to derive a complete address. Encoding.-Incoming data is coded by examining pairs of fixed length bytes (each of 8 bits in the embodiment described), frequently occurring pairs being assigned a variable length code word with a variable length prefix portion and less frequently occurring pairs being encoded by adding a main prefix or "copy code" to the two 8-bit bytes. Successive pairs of bytes are each used to address a code table (10, Fig. 1, not shown) to find the corresponding variable length code word or the "copy code" which is fed to a register 12, the prefix representing the length of variable length code words being read to a counter (14) to control shifting of the register (12) during read out. If a "copy code" is read out it is followed by the original two bytes. Decoding.-If the maximum possible length of the variable length prefix portion of encoded data is 6 bits, during decoding six bits are entered into a register R5 (Fig. 4) and compared with the stored prefix portions in associative memory 20 which, when a match is indicated, gives a signal on an associated lead to a memory 22 to read out to a register R1, the prefix length, to a register R2, the remainder length, to a register R3 an indication of whether the "copy code" prefix is recognized and to register R4 a base address in a memory 24 at which, for non "copy code" words, the byte pairs having the detected prefix are stored. The prefix length is used to shift register R5 so that the decoded prefix is discarded, the number of bits in the remainder then being shifted under the control of register R2 into register R4 to give the complete address of the byte pair in memory 24, the bytes being entered into register R7 from which they are read out as decoded data. For a "copy code" word the register R3 controls register R5 to shift out both the succeeding bytes (which have not been encoded) to a register R6 from which they are read out as the decoded data. Detailed decoding operation (Figs. 6-9, not shown). Data is entered into register R5 via gate 62, register R1 being initially set to a count of 6 and decremented for each data bit entered so that after the entry of six bits a gate 66 is enabled to enable via OR gate 88 a single shot 90, the resulting signal D5 controlling associative memory 20 to switch bi-stable 34 in its read out lines to their "1" state. Subsequently single shot 92 switches on, the resulting signal D6 controlling the application of data in register R5 to memory 20 so that all bi-stables 34 except the one associated with the data in register R5 are set to their "0" state. Single shot 94 is then triggered to generate a signal D7 to prime AND gates 36 so that the bi-stable in its "1" state gives a signal to read out the associated word in memory 22 into registers R1, R2, R3, R4. Bits are then shifted out of register R5 and register R1 is simultaneously decremented until it is at zero, indicating that the prefix portion of the code word has been discarded, when, if the contents of register R3 are "zero" indicated that the word is not a "copy code" word single shot 124 is triggered. This results in the contents of register R2 being examined and if digits follow the prefix code a single shot 136 is triggered to shift register R4 one bit, single shot 140 being subsequently triggered so that one bit is shifted from register R5 to register R4. A new bit is then entered from the incoming data to register R5. This process is repeated until register R2 is at zero when register R4 contains the complete address at which the corresponding fixed length data is stored and register R5 stores the highest order bit of the next code. The data stored in memory 24 at the address indicated by register R4 is then read into register R7 from which it is read out via gate 234 to an output device. A counter 40 initially set to the number of words to be decoded is simultaneously decremented. The counter 40 is then examined and if its count is not zero the process is repeated. If when the prefix code is discarded the contents of register R3 are found to be zero indicating a "copy code" word, a single shot 206 is triggered to set register R1 to a value of 16 representing the number of bits to be shifted out of the register R5. Single shot 210 is triggered to enable gate 212 so that the first bit is transferred from register R5 to register R6. Register R5 is then shifted one bit and the new data entered into it. Counter R1 is simultaneously decremented, this process being repeated until the counter R1 is at zero when gate 220 is enabled to trigger a single shot 232 which enables gate 234 so that the contents of register R6 are read out to the output device.