Patent GB-975958-A (GB)
Title: Improvements in and relating to arithmetic circuitry
IPC: G06F7/504
Filed: 1961-06-22
Abstract: 975,958. Binary adders; plugboard computors. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 22,1961 [July 11, 1960], No. 22583/61. Heading G4A. A serial full binary adder (Fig. 1a) consists of a trigger 101 storing one input bit X the state of which may be changed as a result of the comparison of the second input bit Y and an in-carry bit. The triggers 101 and 102 are primed by high potentials on their "diamond" inputs and are switched by a clock pulse CPC on the "arrow" inputs. Trigger 101 is complemented when input 105 is high whereas carry storage trigger 102 is set to whichever side has two "diamond" inputs up. The state of trigger 101 is compared with the input X bit in an exclusive-or circuit comprising and circuits 115<SP>1</SP>, 116<SP>1</SP> and or circuit 114<SP>1</SP>. If the present state is the same as the X bit no change is necessary and line 105 is down. A CPC pulse is then applied to trigger 101 and the marking of the sum output lines represents the X bit. The carry and Y bits are compared in an exclusive or circuit comprising and circuit 118<SP>1</SP>, 119<SP>1</SP> and or circuit 117. If these bits differ line 106 is up with the result that the next CPC pulse complements trigger 101 and sets trigger 102 to the value previously held in trigger 101. If these bits are the same the setting of trigger 102 at the beginning of the addition represents the out-carry. The adder is embodied in the plug-board controlled computer shown in Figs. 2a to 2j operating on 32-bit words stored in rows of a core matrix shown in Fig. 2a. Only three rows are indicated, associated with the hubs 37, 38 and the bottom row to accommodate the other half of a double length word occurring in multiplication or division. Machine timing. The period during which two 32-bit words X and Y are read from memory, operated on, and returned to memory is known as a scanning cycle. In each cycle are sixteen T pulses each lasting for the time necessary to read and rewrite two orders of each word into memory, thirty two D pulses each associated with an order of the X and Y words, thirty two X pulses and the same number of Y pulses each associated with one order of an X or Y word. During each X or Y pulse there occur CPB, CPC and CPD pulses which are action pulses, switching triggers &c. after system conditions have determinedwhat switching is to take place, and pulses g 1  to g 4  used in reading and writing from memory. Pulses g 1 , g 3  occur simultaneously and are used for read-out, while pulses g 2  ,g 4  also occur simultaneously for read-in, with the proviso that g 2  only occurs if there is an output from or circuit 225 (Fig. 2h), i.e. if it is necessary to write a binary one into memory. Basic arithmetic cycle. A bit of the X word is read -out from memory and stored in trigger 101 (Fig. 2c) corresponding to the same-referenced trigger of Fig. 1a; the X bit if rewritten into memory at its original location. The like ordered Y bit is read out from memory, the operation is performed, and the result of the operation rewritten in the Y bit location of memory. Hub 77 (Fig. 2e) is an X-word hub energized by X pulses and by connecting hub 77 to e.g. hub 37 the contents of a row of memory are selected as the X word. Similarly hub 78 is a Y word hub. Energization of hub 37 closes switches 42 and 45 during X time and a T 1  pulse closes switches 53 and 54. At X time a g pulse from generator 57 issues on the line controlled by switch 42. Simultaneously a g 3  pulse from generator 7 issues on the line controlled by switch 53, which threads the first and second columns of memory in opposed directions. These pulses combine additively only at the first core of the X word row which is switched is storing binary one, the resulting output on sense lines 85 (Fig. 2a) setting trigger 86. The on output of trigger 86 is applied through diode 99 and or circuit 90 to series inverters 91, 92. If the output of 91 is high this will indicate that the trigger is not on and a binary zero has been read-out. A high output from inverter 92 indicates the readout of a binary one. These outputs are applied to and circuits 115 and 116 where they are compared with the present setting of trigger 101. If it is necessary to switch the trigger 101 that it may represent the bit read from memory, or circuit 114 activates line 105 and a CPC pulse switches the trigger. If trigger 101 stores a one bit line 126 is up and this activates and circuit 226 to produce an output from or circuit 225 which leads to the generation of a g 2  pulse. The g 2  and g 4  pulses are controlled by switches 46 and 54 and coincide additively to record at only the first core of the X row. Arithmetic: general. The operation required is specified by plugging to hub 76 or a corresponding hub associated with triggers 72 to 74 addition, subtraction, multiplication or division hubs, AM, SM, M or D respectively. The arithmetic unit consists of trigger 101 to 104 of which 101 and 102 are accumulator and carry triggers and trigger 103 is switched on for subtraction while trigger 104 is switched on when a result is to be complemented. All results are stored in memory in true form. The operations are algebraic i.e. note is taken of signs of the operands. For certain operations it is necessary to have a delayed indication of the state of trigger 86. At X time the setting of trigger 86 is transferred to trigger 87 and at 7 time the setting of trigger 87 to trigger 88. Addition. The operation of triggers 101, 102 is as described with reference to Fig. 1a. The subtract trigger 103 is operated if the signs of the two operands are unlike. A negative sign is indicated by the first bit of the 32-bit word being a one. If the sign of the X word is negative and circuit 131 is activated to provide a signed through or circuit 128 switching the subtract trigger 103. If the sign of the Y word is negative and circuit 131 is again conditioned to switch trigger 103. Unlike signs cause only one switch of trigger 103 and the operation is effectively subtraction. Subtraction. If the X and Y words are both positive (zero in sign position) and circuit 133 is activated at Y time to switch trigger 103. If both are negative addition of the X and Y sign digits sets trigger 103 at Y time. Differing signs cause trigger 103 to be switched twice or not at all. Subtraction is then done by adding the complement of Y and X and complementing the result. In addition the comparison of the carry digits takes place in and circuits 118, 119 which together form an exclusive-or circuit acting as described with reference to Fig. 1a. In subtraction the comparison takes place in and circuits 120, 121 which produce an output if the carry and Y bits are the same, an may be considered an exclusive- or circuit having as inputs the carry bit and the complement of the Y bit. Complementing the result takes place as each bit is determined: and circuit 230 (Fig. 2h) is such that it produces an input if the subtraction trigger 103 is on and the accumulator trigger 101 is registering zero; or circuit 225 will then cause a one to be recorded in the Y word in memory. Recomplementing and adding one to the result will be necessary if the subtrahend is smaller than the minuend as shown by trigger 102 storing a carry at the end of subtraction. This condition is sensed by and circuit 136 and recomplement trigger 104 is tuned on. X pulses are inhibited and only the Y word is read from memory. Triggers 101,102 and 103 are each set to off. If the first bit of the Y word is a one it is entered in trigger 101 and rerecorded in the Y word location in the usual manner. The second bit of the Y word is effectively added to the first bit, carry being taken into account and the setting of the accumulator trigger is recorded in the Y word memory location. Multiplication. A multiplier in W2 operates on a multiplicand in W1. The product is stored in W2 with overflow of higher orders in a location W3. During a first cycle the signs of the multiplier and multiplicand are added and the multiplier transferred to W3. In 2nd, 4th, 6th..... cycles following a left shift is made in W3 and the Value of the highest bit determined. In subsequent odd cycles a left shift is made in W2 and if the highest bit in W3 was found to be a one W1 added into W2. This takes two scanning cycles: one for the shift with overflow into W3, the other for addition into W2 and possibly W3. The operation is controlled by the counter comprising triggers 140 to 145 (Fig. 2h). Division A divisor in W1 divides a double length dividend in W3 and W2. The quotient is recorded in W2, the remainder in W3. In a first cycle signs are added to get that of the quotient, and the portion of the dividend in W2 is shifted left. In a second cycle the divisor in W1 is subtracted from the dividend in W3 shifted one place left. In odd cycles a left shift is made of the contents of W2 and if the subtraction made in the previous even cycle did not give a negative result a one is entered in the lowest place of W2. In subsequent even cycles, if the subtraction of the previous even cycle had led to a positive remains der a subtraction of W1 from W3 shifted one place left is made; if, however, the subtraction had led to a negative remainder the divisor is added to W3 after a left shift. This combines the re-addition of the divisor (D) on the previous even cycle with the subtraction of the divisor on the present even cycle since On the last subtraction W3 is not shifted and if an overdraw is made the divisor is simply added back. Miscellaneous program controls. Pulse generators 179, 180 cause advance from one instruction to the next by setting that trigger from 71 to 74 which has its hub 75 energized, thus providing means for energizing word selection hubs 77, 78 whem emitter followers 197 or 198 are up. Hub 79 is connected to a hub 75 to determine the next step in the program, or ma