Patent GB-1018075-A (GB)
Title: Circuit arrangement for generating a multiphase signal
IPC: H03K3/26
Filed: 1962-07-18
Abstract: 1,018,075. Electronic counters. GENERAL ELECTRIC CO. July 18, 1962 [July 28, 1961], No. 27629/62. Heading G4A. [Also in Divisions H2 and H3] A generator for developing multiphase signals comprises a number of bi-stable circuits N interconnected to provide a predetermined number of states and combining means connected to provide a multi-phase signal having N or 2N phases, displaced by <SP>360</SP>/N or <SP>360</SP>/ 2N  degrees. In a first embodiment, Fig. 1, three bi-stable circuits 11, 12, 13 are connected in cascade to form a shift register, with the output from stage 13 reversed and fed back to the input of stage 11. Application of a series of clock pulses from a generator 10 causes the bi-stable circuits to take up the states given in the truth table, Fig. 2A (not shown), and produce the waveforms 110, 120, 130, Fig. 2B (not shown), at their outputs, respectively. A three-phase output signal is obtained by taking the outputs from circuits 11, 13 and the inverse of the output from circuit 12, each output being fed through a separate amplifier 14, 15, 16 respectively. In order to prevent unwanted sequences being set up if the circuit is initially in one of the unwanted states 1-0-1, 0-1-0 an " AND " circuit 17, and an " OR " circuit 18 are included in the arrangement to bring the circuit to the state 0-0-0 where a true sequence can commence. In a second embodiment, Fig. 3, the three bistable circuits 48, 49, 50 are arranged as a counter with a feedback path 56, 57 between circuits 49, 48 which operates following the circuit 49 taking up its " 1 " state to increase the count by one, thus making the circuit count to a scale of six instead of eight. Waveforms 480, 490, 500, Fig. 4B (not shown) represent the " 1 " terminal outputs of stages 48, 49, 50, respectively. Only waveform 500 is of the required form for the three-phase output, and in order to develop the outputs for the remaining phases the outputs from the circuits 48, 49, 50 are selectively combined by AND circuits 47, 51, 52, 53 and OR circuits 54, 55 to produce the waveforms 540, 550, the third phase waveform 580 being obtained directly from waveform 500. In a third embodiment, Fig. 5, the first bistable circuit 59 acts as a binary counter to supply a single output pulse at the " 0 " output for every two input pulses on terminal T. The second and third bi-stable circuits 60, 61 are connected as a shift register connected to count to three so that a complete cycle of permutations of states occurs every six input pulses. In order to develop the required three-phase output signal, the outputs from the three bi-stable circuits are selectively combined by AND circuits 63, 65, 67 and OR circuits 64, 66, 68. Bi-stable circuit.-One form of bi-stable circuit, Fig. 6, comprises a pair of reciprocally coupled transistors 27, 28. The set and reset inputs S, R are integrated by RC network 39, 37 and 43, 41, respectively, to give a delay, the trigger input T being differentiated by the same networks. An auxiliary trigger input T1 is also connected to the base of transistor 28 for applying the necessary feedback to bi-stable circuit 48 of the embodiment of Fig. 3.