Patent ES-374158-A1 (ES)
Title: Frame synchronization system
IPC: H04L7/04
Filed: 1969-12-02
Abstract: In a time division multiplex PCM frame synchronizing system, means are provided for examining successive bits of the incoming signal to recognize a synchronizing signal and apply correction to locally generated timing signals when synchronism is lost. In comparison with systems which examine the incoming signal only once per frame the present system is stated to reduce the time required for correcting for lack of synchronism. The Specification defines three types of synchronizing codes, first a distributed code including one bit per frame and two or more frames per multi-frame, for example, a "1" in one frame and a "0" in the other frame of a multi-frame. A second type is a lumped code, i.e. a specific code pattern such as 101101 appearing in each frame, and a third type is a combined distribution and lumped code, e.g. 101101 in one frame and 010010 appearing in the other frame of a multi-frame. As shown in Fig. 4, the frame rate of the signal from source 4 is 8 kc./s. and the synchronizing code is of the distributed type consisting of "1" and "0" in adjacent frames. A clock 3 generates bit rate pulses which are supplied via an INHIBIT gate 5 to binary counters and logic circuitry 6 to produce the required timing signals. For recognizing the sync. code a 4 kc./s. square wave REF is generated so that the positive half cycle is present throughout one frame and the negative half cycle throughout the succeeding frame aid is supplied to an EXCLUSIVE OR gate 7 together with the incoming signal. A synchronization bit timing signal ST having a constant width of one clock period and a halt time signal HT of variable duration are also generated at 6. The signal HT prevents the system from locking in an unsynchronized condition on initially switching on the equipment. The output of gate 7 will be 0 if the two inputs coincide and otherwise will be 1. This signal MMF is applied to a bi-stable 8 triggered by a signal MT from an AND gate 9 receiving signal ST and the signals from clock 3 so that if signal MMF represents a mismatch the output of bi-stable 8 will be a binary 1. The output of gate 7 is also supplied via an inverter 10 to the bi-stable 8 so that if the signal MMF represents a match the output of the bi-stable is binary 0. A decision circuit 11 receives the output of bi-stable 8, circuit 11 comprising a Miller integrator including a differential amplifier, Fig. 5 (not shown), the output of the integrator being compared with a reference voltage providing a decision level. The output of the bi-stable 8 is supplied to the inverting input of the differential amplifier. The output of gate 7 is also coupled directly and via an inverter 20 to a bi-stable 19 triggered by a signal SHC provided by an AND gate 21 and OR gate 22. The signal ST and the output of an AND gate 23 are supplied to the OR gate 22 and the AND gate 21 receives the bit rate signals from clock 3 and the output of the OR gate. When circuit 11 has a voltage below the decision level its output is a binary 1 and above this level it is binary 0, the decision level being adjusted, for example, for minimum average search time at a specified bit error rate. Also, when there is a mismatch as indicated by signal MMF the output of bi-stable 19 will be binary 1. The outputs of circuit 11 and binary 19 together with the signal HT are supplied to the AND gate 23. When all the input signals are binary 1, gate 23 produces an inhibiting pulse which blocks the gate 5 to stop the counters of circuit 6 to provide a phase shift of the timing signals. If during the next bit of the incoming signal a match occurs, bi-stable 19 will change state but not bi-stable 8. Fig. 9 shows the situation when the decision circuit voltage is below the decision level voltage and the first signal sample is a match. The output SL is binary 1 but the output of bi-stable 19 is binary 0 so that gate 23 is inoperative and produces no halt pulse. In Fig. 10 the decision circuit voltage is below the decision level voltage, the first sample is a mismatch and the second sample is a match. Bi-stable 19 advances the condition of signal MMF by one bit period so that gate 23 is operative and a halt pulse having a width of one clock period is produced to inhibit the gate 5 for this period. In Fig. 11, the decision circuit voltage is below the decision level, the first and second samples are mismatches and the third sample is a match. In this case the halt signal extends for two bit periods and a halt pulse of two clock periods duration is produced which blocks two clock pulses from source 3 to circuit 6. For increasing numbers of mismatches the halt pulse is extended correspondingly until a match is achieved. The system may be adapted for a lumped type code by replacing the gate 7 with a digital comparator such as a shift register, the "1" and "0" outputs being coupled to an AND gate in accordance with the coding together with the reference signal, Fig. 13 (not shown). Alternatively, for the combined lumped and distributed code, a pair of shift registers respectively connected in accordance with the two codes are gated into use alternatively by the reference signal, Fig. 14 (not shown).