Patent GB-909943-A (GB)
Title: Clock pulse synchronizing circuit
IPC: G06V30/224
Filed: 1960-10-11
Abstract: 909,943. Automatic character reading. NATIONAL CASH REGISTER CO. Oct. 11, 1960 [Dec. 23, 1959], No. 12581/62. Divided out of 909,942. Class 106 (1). [Also in Group XXXIX] Clock pulses used for sampling signals derived from sensing a character as described in Specification 909,942 are synchronized with a trigger signal by being variably delayed in a circuit having first and second variable delay circuits into one of which is set a delay so that the clock pulses are delayed by the time interval between the leading edge of a clock pulse and the trigger signal. The variable delay circuit is as described in Specification 907,492 and consists of a magnetic core 1, Fig. 1, having an approximately square hysteresis characteristic and two openings 2 and 3. The winding 5 " resets " the core by establishing, say, an anticlockwise flux when a pulse is applied to terminal R. Winding 4 sets the core by removing part of the reset magnetism by a contrary flux, the proportion removed being dependent upon the length of the pulse applied to terminal S. The flux is now as shown by the arrows in the neighbourhood of the opening 3. This flux is reversed by energization of a winding 6 by current from 50 volts source through transistor 11 when a clock pulse V1 is applied at terminal 12. The other end 13 of the winding 6 is connected through a diode to the 4-volt source and through a resistor to the 50- volts source. When the positive pulse V1 is first applied to terminal 12 the impedance of the coil 6 is high because of the flux reversal around the opening 3. This keeps up the potential of the end connected to the 50-volts source and causes terminal 13 to remain at 4 volts. When the flux is fully reversed, the impedance falls and the coil 6 becomes substantially a shortcircuit so that the potential at terminal 13 falls to zero as shown at V 0  in Fig. 2. At the end of the clock pulse V1 the transistor 11 cuts off de-energizing winding 6 and allowing permanently energized winding 7 to start resetting the flux round opening 3. This gives rise to a positive pulse V2 which is connected to cause transistor 14 to conduct and hold point 13 to zero potential. At the end of the resetting period the transistor 14 cuts off and the point 13 returns to 4 volts as shown at V 0 , Fig. 2. Both the leading and trailing edges are therefore delayed by the variable period. In the complete circuit, Fig. 3, the clock pulses C are amplified and applied to gates 18 and 19 in inverted and true forms respectively. The triggering pulse is applied to a flip-flop G the " 0 " output of which is applied to both gates, and the " 1 " output to gates 21, 22. Normally, with the flip-flop G unset, the clock pulses C are applied through gate 19 to the reset terminal R of delay circuit XI and the set terminal S of X 2. The inverted clock pulses C<SP>1</SP> through gate 18 to the set terminal S of delay circuit XI and the reset terminal R of X2. Normally the cores of the delay circuits are reset and set alternately the two circuits working in anti-phase. The gates 18, 19 close when the trigger pulse sets flip-flop G so that whichever circuit is being set the setting process is cut short. The delay interval is arranged to equal the period during which setting has taken place. The clock pulses at C are delayed by that amount in the set circuit. Flip-flop Q is set or reset by the outputs of the gates 18, 19 to open one of the gates 21, 22 to pass the delayed clock pulses from the appropriate circuit. A third input to these gates is from flip-flop G to ensure that clock pulses are transmitted only after a trigger pulse has been received.