Patent GB-1069375-A (GB)
Title: Calculator apparatus for distinguishing meaningful digits
IPC: G06F3/00
Filed: 1965-05-03
Abstract: 1,069,375. Electrical calculator. WYLE LABORATORIES. May 3, 1965 [May 18, 1964], No. 18442/65. Heading G4A. Apparatus for storing numbers comprised of series of ordered digits and for performing arithmetic operations with respect to the numbers, include apparatus for examining each of the numbers to determine which digits are significant and which are not and second apparatus for tagging the significant digits differently from the digits which are not significant. In a computer of the kind described in Specification 1,031,235 decimal numerals are indicated by bit pulses in bit spaces P1-P9 of 12- bit spaces in each digit sector, 1 bit signifying 1 up to 9 bits signifying 9. Significant bits are tagged by applying the pulses in bit space P 10  and the display is arranged such that significant digits are supplied to a cathode-ray display screen whereas insignificant and hence untagged digits are suppressed. In operation a clear pulse (Fig. 7, not shown) indicating that the arithmetical operations have been completed generates an edit sequence. This changes a cycle counter to a state 1A (Fig. 9b, Fig. 7, not shown) wherein the cycle counter is incremented via an AND gate (700) for each digit occurring prior to the decimal point position indicated by a signal Kp. Pulse Kp acts to set logic flip-flop L 0  via AND gate (702) thus rendering the I 0  input to gate (700) zero and retaining the cycle counter at a count corresponding to the position of the decimal point as the rest of the number is read from the memory. After the memory cycle an origin signal at the commencement of a re-cycle switches the cycle counter to state II A  (Fig. 9d, not shown). During this period the cycle counter is increased to correspond to the position of the most significant digit via an AND gate (710). The input from the appropriate memory track, determined by a word counter, is applied to AND gate (710) via AND gates (706) and OR gate (708). When the most significant digit is detected the cycle counter is changed to state III A , Fig. 9e. In state III A  tag bits are entered into an A counter and transferred to an R counter which counts down to zero as clock pulses are applied to it to return the number to the memory. As the number is returned through OR gate 726 tags are entered in position P 10  via AND gate 750 if logic flip-flop L 1  is set. L 1  is set if L 0  is reset when the least significant digit occurs via OR gate 746 and AND gate 744 or when the decimal point (at pulse Kp) occurs via AND gate 748 as long as the decimal point is not coincident with the most significant digit, indicated by pulse KDc. L 0  is reset by a pulse K<SP>1</SP>DC which is KDC delayed by 1 digit period. At the end of State IIIA the word counter is incremented and the edit procedure is repeated on the next word. The display apparatus is illustrated in Fig. 10 (not shown). The beam is normally blanked but is brightened when a signal applied to input 772 is true. This is rendered true when the decimal point signal Kp occurs. The displayed signals are dimmed except when input 770 is false. This occurs when calculations are being performed and also when L 0  is set. L 0  is set via AND gate 786 when bit P 10  is present when calculations are not being performed and when there is a memory output from OR gate 708. Numbers inserted in the memory by an operator keyboard are automatically tagged.