Patent TW-335493-B (TW)
Title: Matrix-memory in virtual-ground-architecture
Inventor: DR ROLAND THEWES
IPC: G11C11/56
Filed: 1997-07-25
Granted: 1998-07-01
Abstract: A sort of matrix-memory, which memory crystal cell (Zn, k) are disposed in the lines and rows, for saving of logic "0" or "1", and in each of the saving logic "0", the memory crystal cell has a variable resistor having the first, second and third end; for numbering these columns, all the resistors disposed in the even lines being designed in the following ways: by applying the first programmed power (Vpc) to the first end, applying the second programmed power (Vgnd) to the second end and by applying the second programmed power (Vw1) to the third end, the resistor between the first and second end being minimum, making the power difference between the first end and the second end compensate during the programmed time for readout; by applying the first programme dpower to the first end, te second programmed power to the second end and the fourth programmed power (Vgnd) to the third end, the resistance between the first end and the second end being maximum, making the power difference between the first end and the second end remain the same basically during the programmed period during the readout time; being these resistances disposed on the odd lines being designed as follows: by applying the first and the second programmed power to the first end, being the first and the second programmed power different from the fifth programmed power (Vvm), the second end and the second programmed power at the third end, being this resistance between the first and the second end being minimum, making the power difference between the first and the second end compensate within the time period programmed by the readout; by applying the first programmed power on the first end, applying the fifth programmed power on the second end and applying the fourth programmed power on the third end, this resistance between the first and the second end being maximum, making the power difference between the first and the second end be the same during the period programmed by the readout; this memory having bitlines (BLn), which only electrically link the first end or the second end of the resistance disposed on the lines; for the pair formed on the even lines after an odd line or after it, one of the bitline having the first end of the resistance in the column of the pair connect, and in connection with the second ends of the resistance in the column of the pair formed by an even column and the odd column after it; having the memory a wordline (VLk) which has all the first and third end of the resistance disposed in each column in electrical connection; this memory having switches (Sn,pc, S,gnd, Sn,vm), with the bitline passing by the switches for connection with the power (Vpc, Vgnd, Vvm) of the first, second and fifth programmed power; for each pair formed by an odd column and the even column after it, the first programmed power may be added to this configuration on the first end of the resistance on the column of pair, the second programmed power may be applied to the second end of the resistance on the column of pair, the fifth programmed power may be applied to the second end of the resistance on the odd column; this memory having a switch (S^k,vw1, S^k,gnd), for the wordline to pass the switches for connection with fourth programmed power and each of the wordlines going by the switches for connection with the third programmed power; this memory having other switches (Sn,read), for connection of each of the bitlines connected with the first end with the calculation circuit (AVS) by means of the switch (Sn,read).