Patent GB-1519169-A (GB)
Title: Signal processor
IPC: G06F17/10
Filed: 1975-10-07
Abstract: 1519169 Data processing systems INTERNATIONAL BUSINESS MACHINES CORP 7 Oct 1975 [27 Dec 1974] 40908/75 Heading G4A A plurality of control units are each connected to an associated computing unit over a respective bidirectional data and priority bus, and the buses are interconnected to form a tree-structure with master-slave relationships between control units at different levels and with each control unit operable in priority mode which allows interrupt of any program in progress in response to a service request from a unit connected to the respective bus and having a higher priority than the program in progress. Control units, Fig. 7, each include program storage IS, and a double word instruction register, one word W0 directly providing operands or addressing operands in register stacks SA, SB, and the other word W1 controlling an ALU and determining, in part, the next instruction address. A plurality of next instruction address registers NIAR may be provided, one for each priority level, and one of these may be selected according to the highest priority service request being received from the slaved control units and I/O parts associated with that control unit's N-bus. Highest priority (level 0) interrupts may be forced at regular intervals by a timer and selected levels of interrupt may be forced or masked by registers PIRR and MASK. Two programs on different priority levels (respectively in an even and odd group of levels) may be run simultaneously, instruction fetch for one program being overlapped with instruction execution for the other program. The output of the ALU can be gated to the associated N-bus to provide control words CW, addresses and data to the slaved control units and I/O ports. The program storage IS is loaded under control of a loading program in a ROM which provides read instructions to a terminal, e.g. card reader, for entry into a RAM forming the main part of the control unit IS store. I/O ports and the adapters interconnecting the N-buses are all addressable from the control units for the transfer of read/write commands and interrupt requests. The computing units, Fig. 4 (not shown), perform the basic functions of multiplication and accumulation and may be controlled so that the overall system acts as a signal processor, e.g. telephone exchange or modem. A control word CW supplied to a computing unit from the master control unit includes an OP code defining a particular microprogram in a ROS to be used, and three address pointers. Described functions which may be performed by a computing unit include Z=#ax-#by; Y+jZ=#[(a+jb)(x+jy)] used when simulating a transversal, complex transversal or recursive filter and Cn = C n-1  + K 1 X + K 2 Y, e.g. when generating signalling tones by accessing selected stored samples of a sine wave. The data store Si-S may contain values x t  in sequential addresses of a table; similarly tables of coefficients, e.g. a t , may be stored. Flags associated with these tables may indicate the end of the data set or series of data sets or may indicate chaining of the same or another set of coefficients with the same CW operation. The CW address pointers may indicate the addresses of new data, the first data item in a set and the first coefficient in a set. The usual address branching logic for the control store is provided, and the adder is provided with parity prediction and checking logic.