baber/WOPTO huggingface dataset:
Patent JP-H1169153-A (JP)
Title: Image processor
Inventor: MIKAMI FUMIO
IPC: H04N1/60
Filed: 1997-08-19
Abstract: PROBLEM TO BE SOLVED: To unnecessitate a memory exclusive for shading correction in an image processor in which line sensors for separating an original image into red, green and blue color signals are arranged in parallel, the line sensors are scanned in a direction perpendicular to the lengthwise direction and shading is corrected for the original image read in the order of the red, green and blue signals. SOLUTION: Memories 1-6 for summing sampled data are used for memories 1-6 for calculating a means value and values excluded from the mean value is stored in a line interval absorption buffer memories 7, 8 to utilize the memories effectively. Furthermore, only two memories are employed for the line interval absorption buffer memories 7, 8 then three R, G, B colors are sampled not simultaneously but sequentially. Then idle areas of memory addresses are used sequentially.
Patent JP-H06236840-A (JP)
Title: Method and device for electron beam exposure
Inventor: SHINADA HIROYUKI
IPC: H01L21/027
Filed: 1992-08-21
Abstract: PURPOSE:To provide an electron beam exposing device having high through put and requiring no mask corresponding to each pattern. CONSTITUTION:The planar electron emission source, which is farmed by dividing a semiconductor electron emission material 1 into lattice form, is allowed to perform an ON/OFF function for every picture element, the pattern signal such as an integrated circuit and the like is sent thereon so that the electron beam 8 of the desired pattern can be formed freely. Also, even when the light to be projected on a photo cathode, which is used as a planar electron emission source, is formed into an optional shape using a shutter which can be controlled electrically, the electron beam 8 of the desired pattern can be obtained.
Patent JP-S6191274-A (JP)
Inventor: HANSU PEETERU PATSUTSUSHIYUKE
IPC: C09D5/44
Filed: 1985-10-04
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0563124-A (JP)
Title: Hybrid integrated circuit device
Inventor: TAKAHASHI TAKASHI
IPC: H01L23/40
Filed: 1991-09-03
Abstract: PURPOSE:To relax the transmission of stress on a ceramic board, etc., due to caulking at a time when two master and slave aluminum heat sinks are stuck through caulking. CONSTITUTION:Stress at a time when two master and slave heat sinks 2, 3 having projecting sections 10 and holes 11 for caulking respectively are caulked and laminated is concentrated and applied to the grooves of the heat sink 3 by forming the grooves 5 centering around the holes 11 to the heat sink 3 with the holes 11, thus relaxing the transmission of stress on a ceramic board 1, etc., on the heat sink 3.
Patent JP-2001047056-A (JP)
Title: Water treatment apparatus
Inventor: TAKEZAWA MASAMOTO
IPC: C02F1/48
Filed: 1999-08-05
Abstract: PROBLEM TO BE SOLVED: To make a magnetic water treatment apparatus freely detachable with respect to an arbitrary water guide system. SOLUTION: This water treatment apparatus is equipped with a suction port 11a, a pump 12, a filter 13, a magnetic water treatment device 14 and a discharge port 11e, and the pump 12 sends the water sucked from the suction port 11a to the filter 13 and the filter 13 filters the water sent from the pump 12 and the magnetic water treatment device 14 is connected across the outlet of the filter 13 and the discharge port 11e and constituted so as to pass water through a magnetic field.
Patent JP-S6282415-A (JP)
Title: Preservation system for memory sheet
Inventor: IKENOUE YOSHIKAZU
IPC: G06F1/26
Filed: 1985-10-07
Abstract: PURPOSE:To reduce the consumption of a backup battery by storing and preserving a memory sheet in a storage part of a power unit when the memory sheet is not connected to an information processor or the like. CONSTITUTION:A memory sheet 1 is provided with a RAM, a battery 3 for backup of the RAM, a flexible substrate 2, input/output terminal 11 and 12, etc. and is held between protective sheets 5 and 6. Input/output terminals 11 and 12 consist of electrodes 13 and 14, which receive the backup power of the RAM from binder type power supply device or the like when the sheet 1 is connected to the external power terminal of this power supply device, and a photodetector 15 and a light emitting element 16 provided for optical communication with an external device. When the sheet 1 is not connected to another information processor, the sheet 1 is stored and preserved in the storage part of the power supply device and power is supplied form the power unit through electrodes 13 and 14, thus reducing the consumption of the incorporated battery.
Patent JP-S63107299-A (JP)
Title: Stereoscopic sound field recording system by right and left channels and microphone installation unit
Inventor: SUMINO YOSHIHIKO
IPC: H04R5/027
Filed: 1986-09-19
Abstract: PURPOSE:To record a sound wave similar to a waveform approaching an eardrum by positioning a microphone sound collecting part at the entrance of an external auditory meatus. CONSTITUTION:The width and vertical directions (h) and (n) in which the microphone installation unit is placed are adjusted so that a width adjusting tool 1 is placed on the head and so that an ear hanging fitting 5 is placed along the upper half of the root of the ear. The vertical and horizontal directions (i) and (j) are adjusted so that the arm part of an installation arm 4 is placed along the outer edge of an external ear. A microphone adjusting tool 6 is adjusted in a horizontal direction (k) and a microphone holder 7 in a vertical direction (l), and it is oriented toward the entrance of the external auditory meatus from the oblique back of the external ear without allowing into contact with the external ear. Then a microphone is moved horizontally (m) to position the microphone sound collecting part at the entrance of the external auditory meatus, and a microphone cord is connected to the channel of a sound recording unit.
Patent JP-H0969705-A (JP)
Title: Tool and method for characteristic measurement of non-radioactive dielectric line parts
Inventor: TANIZAKI TORU
IPC: H01P5/08
Filed: 1995-08-31
Abstract: PROBLEM TO BE SOLVED: To correct a measurement system by providing a specific heads and correction parts so as to define the contact plane set to the input/output plane of a component as a measurement reference plane without suffering any influence of the characteristic of a conversion part when the component is connected to a measuring device. SOLUTION: Each of both heads 1 and 2 has an input/output plane set opposite to that of a non-radioactive dielectric line parts and a conversion part which converts the propagation mode between the waveguides 3 and 4 of the dielectric line parts. Each of plural correction parts has two input/output planes opposite to the input/output planes of heads 1 and 2 respectively. These correction parts include those that function as lines and reflectors. Then the measurement is carried out with a correction parts like a line substrate 24, etc., placed between the input/output planes of both heads 1 and 2 which are set against the input/output plane of the non-radioactive dielectric line parts. A measurement system is corrected by a TRL boat correction method, etc.  Thus the characteristic of a single component unit is measured with the input/output planes of both heads 1 and 2 defined as the measurement reference planes.
Patent JP-2000038596-A (JP)
Title: Liquid bleaching detergent composition
Inventor: KAWAGUCHI KOJI
IPC: C11D3/34
Filed: 1998-07-22
Abstract: PROBLEM TO BE SOLVED: To obtain a liq. bleaching detergent compsn. which is excellent in foaming properties and stability of an alkali metal hypochlorite and can be stored for a long term by incorporating a specific sulfonate-contg. org. compd., a specific surfactant, a specific amine oxide, an alkaline substance, and an alkali metal hypochlorite into the compsn. in a specified ratio. SOLUTION: This compsn. contains a compd. represented by the formula, an anionic surfactant represented by the formula: R8-O-(CH2CH2O)p-SO3A, an amine oxide represented by the formula: R5R6R7N→O, an alkaline substance, and an alkali metal hypochlorite in a mass ratio of the compd. of the formula to the anionic surfactant of (100/1)-(2.5/1), in a content of the sum of the compd. of the formula and the surfactant of 0.1-7 mass %, in a content of the alkaline substance of 0.1-10 mass %, and in a content of the hypochlorite of 0.5-10 mass %. In the formulas, R1 and R2 are each alkyl provided the sum of the numbers of carbon atoms of them is, on average, 8-16; A1 and A4 are each an alkali metal; R8 is 6-20C alkyl; (p) is 0-20; R5 is R8 or alkenyl; and R6 and R7 are each 1-3C alkyl.
Patent JP-S59112500-A (JP)
Title: Semiconductor memory device
Inventor: SHIMOTORI KAZUHIRO
IPC: G11C11/413
Filed: 1982-12-18
Abstract: PURPOSE:To measure the level of an external terminal and to decide whether a redundant function is used or not by providing a gate circuit for gaining OR of each stand-by decoder output signal of a stayd-by decoder. CONSTITUTION:When a defective bit is not detected in a memory cell array, and a redundant function is not used, stand-by fuses 13a1-13m2 are not cut. On the other hand, when a memory cell is activated, as for address input signals (AO, -AO), etc. one of them always obtains a high potential, therefore, one of MOSTs 12a1-12m2 always obtains a conducting state. Thus, an output node 11 is discharged, a stand-by decoder output is not sent out of stand-by line decoders 6a-6n, and a stand-by line is not selected at a low level. Therefore, the output of an NOR gate 7 obtains a high level. Whether a semiconductor memory device uses a redundant function or not can be decided easily by measuring whether or not output terminal 8 of the NOR gate circuit 7 obtains a high level or a low level.
Patent JP-H0272988-A (JP)
Title: Manufacture of loop form ink ribbon
Inventor: KOBAYASHI MASAKO
IPC: B41J31/00
Filed: 1988-09-07
Abstract: PURPOSE:To contrive prolongation of the service life of a welded part by leaving an ink ribbon to stand in a specified atmosphere for at least a predetermined time before welding, in a loop form ink ribbon produced by welding both end parts of an ink ribbon to each other. CONSTITUTION:An ink ribbon 1 is left to stand in an atmosphere of 40 to 60% at a temperature of 20 to 30 deg.C for at least 20hr, prior to welding. Then, both end parts of the ink ribbon 1 are welded to each other by ultrasonic vibration to produce a loop form ink ribbon. The welded part of the loop form ink ribbon is formed by solidification 3 after melting of the ink ribbons 1, 2 by the ultrasonic vibration.
Patent JP-H0562206-A (JP)
Title: Magnetic disk protection system in case of power interruption
Inventor: KOGA YASUKO
IPC: G11B21/12
Filed: 1991-09-04
Abstract: PURPOSE:To prevent a magnetic disk from damaging in the case of power source interruption and to improve the reliability of a magnetic disk device. CONSTITUTION:By a power source interruption judging means 6, power source interruption information is sent to a power source control means 7 when a main power source 8 is interrupted by failure. By the power control means 7 receiving the power source interruption information, a power source changing over switch 5 is switched from the main power source 8 to the spare power source 9 side of an inside. It is displayed to a display device 1 from the main power source 8 through an information processor 2 that the power source is interrupted. Then, by the power source control means 7, write process is ended at the time of writing a data to a disk, a magnetic head is retracted and turned to a home position. The switching of the power source changing over switch 5 from the spare power source side to the main power source side in ended when the retracting process is ended. In the course of reading from the disk, the magnetic disk is retracted and the switching from the spare power source side to the main power source side is ended.
Patent JP-S6283868-A (JP)
Title: Elasticity improvement in boiled fish paste
Inventor: OZAKI HIROTADA
IPC: A23L17/00
Filed: 1985-10-08
Abstract: PURPOSE:The 'SUWARI' (gelling) process for boiled fish paste products is divided into two stags, the former stage and the latter stage at higher temperature to give products of high values as commodities, because of their good elasticity, water retention and quality. CONSTITUTION:Ground fish meat or similar paste is ground together with salt, then the product is subjected to two-stage 'SUWARI' (gelling) process, in which the former stage is carried out at 0-55 deg.C for 5min to 36hr and the latter process is effected at 0-55 deg.C and about 10-20oC, higher than the former stage for 5min to 36hr.
Patent JP-S6284552-A (JP)
Title: Manufacture of semiconductor device
Inventor: UENO KATSUNOBU
IPC: H01L21/822
Filed: 1985-10-08
Abstract: PURPOSE:To form an silicon thin-film resistor having high precision and an silicon leading-out electrode for a resistor by forming an EGI silicon layer on a lower-layer insulating film covering the surface of an silicon semiconductor substrate by using an EGI technique. CONSTITUTION:An N<+> type buried diffusion region 2 is formed to the surface of a P-type single crystal silicon substrate 1 through a normal gas diffusion method, etc., and a magnesia spinel layer 3 is shaped through a vapor phase growth method. A first silicon dioxide layer 4 is formed onto an Si surface in the lower section of the MgO.Al2O3 layer 3 through normal thermal oxidation. Openings 5, 6 are shaped to the MgO.Al2O3 layer 3 and the first SiO2 layer 4, and a non-doped Si layer 7 is grown on the substrate in an epitaxial manner. Isolated SiO2 films 8 are formed through a selective oxidation method, and boron ions are implanted in low concentration through a first resist mask 9, and boron ions are implanted in high concentration through a second resist mask 10, thus shaping a P-type base region 11 and a P<+> type base leading-out Si electrode 12. Arsenic ions are implanted in predetermined concentration through a third resist mask 13, the resist mask 13 is removed, and an N-type Si thin-film resistor 14 is formed through prescribed annealing treatment.
Patent JP-H04106441-A (JP)
Title: Pressure sensor
Inventor: KOIKE YASUHIRO
IPC: G01L9/00
Filed: 1990-08-28
Abstract: PURPOSE:To efficiently and economically seal the integrated circuit part of a sensor by a resin by forming not only an integrated circuit but also a pressure introducing port to a substrate. CONSTITUTION:For example, an integrated circuit is formed to a ceramic substrate 20 and a pressure introducing port 22 is also formed thereto. A plurality of lead pins for flip flop bonding surrounding the pressure introducing port 22 are arranged in the vicinity of the peripheral edge of the pressure introducing port 22 and electrically connected to at least a part of the integrated circuit. A pressure sensitive element 23 to which a bump electrode electrically connecting the lead pins to internal elements is formed is connected to the lead pins by flip flop bonding. Thereafter, the surfaces of the parts of the integrated circuit containing the pressure-sensitive element 23 are sealed by a resin to form a sensor. By this method, the inflow of a liquid resin 25 to the pressure introducing port 22 is prevented at the time of the sealing of the resin by the pressure-sensitive element 23 itself. Therefore, the surfaces of the parts of the substrate 20 can be sealed by the resin without sealing the pressure introducing port 22 by the resin.
Patent JP-S6284561-A (JP)
Title: Semiconductor device
Inventor: MORI SHINTARO
IPC: H01L29/78
Filed: 1985-10-08
Abstract: PURPOSE:To increase withstanding voltage easily without adding processes by forming a channel stop at a predetermined distance from a source and a drain while arranging a region between a gate region and the channel stop so that a gate electrode is superposed through an insulator of small thickness. CONSTITUTION:An insulator 4 is shaped on the surface of a P<-> type (an N<-> type) semiconductor substrate 1, a gate electrode 5 is disposed so as to be superposed between N<+> type (P<+> type) semiconductor source-drain regions 2, 3, and the gate electrode 5 functions as a gate region 6 in a field-effect transistor. A P<+> type (an N<+> type) semiconductor region 7 in concentration higher than the substrate is shaped at some prescribed distance from the source-drain regions 2 and 3 and the gate region 6 in a field-effect transistor, and the gate electrode 5 is arranged so as to be superposed to the P<+> type (the N<+> type) semiconductor region 7. The film thickness of the insulator in a region 4a held by the gate region 6 in the lower section of the gate electrode 5 and the P<+> type (the N<+> type) semiconductor region 7 is shaped at a small value.
Patent JP-H0274556-A (JP)
Title: Oxide-based high-temperature superconducting ceramics
Inventor: DAIMON HIROSHI
IPC: C01G1/00
Filed: 1988-09-09
Abstract: PURPOSE:To provide a readily producible oxide-based high-temperature superconducting ceramics having high critical temperature and stable superconducting characteristics, consisting essentially of rubidium, alkaline earth element, copper and oxygen. CONSTITUTION:This oxide-based high-temperature superconducting ceramics consists essentially of rubidium, an alkaline earth element, copper and oxygen. A composition shown by the formula Rb1AxCuyOz (A is alkaline earth metal; 0.5<x<7; 0.5<y<6; 1.5<z<16.5) may be cited as the preferable composition. A production is preferably done by a method wherein oxides of each constituent element of rubidium, alkaline earth element and copper are mixed by dry blending or wet blending method and then previously sintered and then sintered. The prepared superconducting ceramic can be readily shaped into a film, wire material, molded article, etc.
Patent JP-H04108393-A (JP)
Title: Production of oleic acid-containing lipid and microorganism
Inventor: WATABE KAZUO
IPC: C12R1/01
Filed: 1990-08-28
Abstract: PURPOSE:To obtain a readily purifiable oleic acid-containing lipid of high purity by culturing a microorganism capable of producing the oleic acid-containing lipid and producing the oleic acid-containing lipid. CONSTITUTION:A new microorganism capable of producing a lipid containing oleic acid in high purity is cultured to produce the oleic acid-containing lipid and the oleic acid or phospholipid oleate or both, as desired, are isolated to produce the oleic acid-containing lipid, oleic acid and/or phospholipid oleate. SCRC-S007 (FERM P-11671) can be cited as an example of the aforementioned microorganism. Culturing may be carried out by using any of a solid and a liquid culture media. In order to obtain the objective oleic acid in a large amount, the liquid culture medium is preferably used to preform the culturing under aerobic conditions by a stationary culture, shaking culture or aeration.spinner culture method. The phospholipid oleate can be obtained by treating the oleic acid-containing lipid by precipitation with acetone.
Patent JP-H0775409-A (JP)
Title: Sensor for defective seedling of rice transplanter
Inventor: FUKUTAKA YASUSHI
IPC: A01C11/02
Filed: 1993-09-09
Abstract: PURPOSE:To provide a sensor for defective seedlings capable of surely sensing the quality of seedlings in successively transplanting pot seedlings such as a cabbage or lettuce in a ridge while traveling. CONSTITUTION:This sensor for defective seedlings is provided by installing a seedling chuter 62 capable of guiding each pot seedling (c) delivered from a seedling receiving tray to a planting means therebetween and holding the pot seedling during the movement of the planting means to a position for receiving the seedling and a seedling detecting sensor 84 capable of detecting a stem or a leaf (a) of the pot seedling (c) in the seedling chuter 62.
Patent JP-S60117494-A (JP)
Title: Semiconductor memory circuit
Inventor: FUJII TAKEO
IPC: G11C11/409
Filed: 1983-11-29
Abstract: PURPOSE:To obtain a semiconductor device which is accessed in a high speed and is operated stably, by connecting the output terminal of an amplifying circuit, which is energized with a signal controlling a transfer gate, to a part near which a pair of common data lines are connected to the transfer gate. CONSTITUTION:A gated amplifier is provided which is connected near connection points between busses IO and -IO and transistors TRs Q4 and Q11 and is constituted with TRs Q9, Q10, and Q12. A memory cell MC and a dummy cell DC are selected by a column selecting clock phix, and a potential difference of about 200mV, namely, a signal appears between data lines D and -D. This minute signal is amplified by a sense amplifier SA activated by a clock phiSE. This part is most important in a one-transistor memory and is the important factor which determines capacity and yield. At this time, it is desirable that one, for example, the data line D out of data lines D and -D has a power source potential and the other has an earth potential.
Patent JP-S60117878-A (JP)
Title: Facsimile signal processing circuit
Inventor: AZAMI SHINTAROU
IPC: H04N1/413
Filed: 1983-11-29
Abstract: PURPOSE:To attain ease of processing by means of a microprocessor by providing a counter circuit constituted to be restored to the initial value at each detection of a line synchronizing code and a processing circuit including the microprocessor or the like and allowing the processing circuit to process an n-bit parallel output of a shift register every time the counter circuit takes the initial value so as to make the line synchronizing code in a facsimile signal coincident with a byte or word boundary. CONSTITUTION:A facsimile signal subject to redundancy compressing coding is inputted to a shift register 1 via a terminal 11, shifted one by one bit sequentially in matching with the timing signal inputted via a terminal 12 and 12-bit parallel outputs Q0, Q1,..., Q11 are obtained. The outputs Q0,..., Q11 of the shift register 1 are inputted to a line synchronism detecting circuit 2, where the pattern of the line synchronizing code is detected, the line synchronism detection signal is outputted and a counter circuit 3 is reset. On the other hand, the counter circuit 3 applies 1/8 frequency-division to a timing signal inputted from the terminal 12. An output of a register 4 sectioned into 8-bit and an output pulse of the counter circuit 3 are inputted to a processing circuit 5 so as to attain the signal processing in the unit of 8-bit by means of the microprocessor or the like.
Patent JP-S60116139-A (JP)
Title: Manufacture of semiconductor device
Inventor: INOUE MASAHIRO
IPC: H01L21/316
Filed: 1983-11-29
Abstract: PURPOSE:To prevent the stepwise disconnection of wirings and to save the time and cost by laminating thickly a silicon oxide film formed by coating Si(OH)4 solution on an oxide layer and a polycrystalline Si layer. CONSTITUTION:Silicon oxide 21 is formed on the surface of an Si substrate 20, and a portion which becomes a transistor is removed. Then, silicon dioxide 22 which becomes a gate is generated, and a polycrystalline Si layer 23 is accumulated on the overall Si substrate 20. Then, part of the silicon 22 which becomes a gate is removed. Then, P type impurity is diffused to form source and drain regions on portions 34, 35 of the exposed substrate 20. Subsequently, a silicon oxide film 26 formed by coating Si(OH)4 solution is accumulated 3 times of the layer 23. Thus, the film 26 is formed to have smoothed curve. Thereafter, to stabilize the surface, a silicon oxide film 27 formed by coating Si(OH)4 solution including P is laminated. According to this manufacturing method, the stepwise disconnection of wirings 28 can be prevented, and time and cost can be saved.