baber/WOPTO huggingface dataset:
Patent JP-S6228110-A (JP)
Title: Cutting method for pipe in seam welded pipe manufacturing equipment
Inventor: KASHIMOTO TATSUO
IPC: B23D21/00
Filed: 1985-07-26
Abstract: PURPOSE:To prevent deformation and a burr from being generated in a cut port part, by forming a cut over the whole periphery of a material pipe in a position, where a seam welded pipe must be cut, while clamping parts of the pipe before and after the cut position by chucks and turning one of the parts to break a cut part. CONSTITUTION:A seam welded pipe A, after its preliminary correction is performed, forms a V-shaped cut B by a cutting machine in a part to be cut. Here the cutting method chucks a part of the pipe A before and after the cut part by chucks. Thereafter, the method corrects again the external shape of the pipe A. The method, turning only the chuck in the downstream side of the pipe A in one direction, twists the pipe A to be cut. A depth of the cut B is set to about 60-75% pipe thickness. A fine cut port is obtained by this twist cutting.
Patent JP-H0214120-A (JP)
Title: Manufacture of container
Inventor: TAKADA YUKIO
IPC: B29C51/26
Filed: 1988-07-01
Abstract: PURPOSE:To open a sealed container easily, save the processes and enhance productivity by melt sealing a cover to a flange section by means of a seal component and forming a weakening line before or simultaneously with said melt sealing. CONSTITUTION:A container main body 10 is formed almost in a cup shape with a flange section 13 at its top, and a skirt section 14 as a curved and folded section toward the bottom section side is formed on an outer peripheral edge 13B except an opening section 13A. A cover 15 is melt sealed on the whole periphery of the flange section 13 except a knob 15A. Said melt seal is constituted of a belt-shaped section 16 and a linear seal section 17 formed almost in the center of said belt seal section. A cut line 18 as a weakening line is formed along the outer edge 15A of the cover 15 on an inner layer section 11 of the flange 13, while a notch 19 is formed on the inner side away from the belt- shaped section 16 by the dimension T. When the seal of the cover 15 is opened, the inner layer section 11 and an outer layer section 12 can be peeled off from the cut line 18 to the notch 19 and the seal of the container is opened.
Patent JP-H1113165-A (JP)
Title: Crack-preventing sound absorption panel and manufacture thereof
Inventor: KAWAHARA YUKINORI
IPC: E04B1/86
Filed: 1997-06-23
Abstract: PROBLEM TO BE SOLVED: To prevent decline of sound absorption capacity by preventing occurrence and progress of continuous long cracks. SOLUTION: The method for manufacturing a sound absorption panel comprises stages wherein the first layer of no-fines concrete is placed first at indents of a cement board and after that a nonwoven fabric is laid thereon and then no-fines concrete is placed up to the upside and crack-preventing members made of foamed plastics are buried in the built-up no-fines concrete. Accordingly, the sound absorption panel is made up with the nonwoven fabric 4 laid on the no-fines concrete layer 31 and the crack-preventing members 5 made of foamed plastics such as foamed polystyrene buried in the no-fines concrete layer 32 formed at the upper side.  Each of the crack-preventing members 5 is formed of a rodlike body having a fixing part at its lower end and in a structure wherein at least two hands are extending from a part of the rodlike body, and the crack-preventing members are buried with the hands placed at the depth 5-10 mm deep from the surface of the no-fines concrete layer.
Patent JP-S6226921-A (JP)
Title: Timing generator
Inventor: SENDA MAKOTO
IPC: H03K5/156
Filed: 1985-07-29
Abstract: PURPOSE:To obtain a timing generator excellent in extending performance and general-purpose applications such as ease of timing design and ease of external change of a pulse change point in the period of timing by selecting a stage corresponding to a pulse change point according to an external command. CONSTITUTION:A ring counter 100 having the number of stages (delay circuit) corresponding to a period of a desired timing outputs each stage output to a selection circuit 101 selecting an optional stage output according the external command. Then a OR circuit 102 ORing output of the selection circuit connects to an inverse delay circuit 103 whose logic is inverted when the OR is logical 1. The logic of the inverse delay circuit 103 is inverted when the OR of the OR circuit 102 is logical '1' and the logic state is kept when logical '0'. Thus, an optional pulse timing is generated depending on the mode of the output selection by the selection circuit 101 inputted to the OR circuit 102.
Patent JP-H11318368-A (JP)
Title: Coating for tempura
Inventor: TAKEUCHI TAKUYA
IPC: A23L29/244
Filed: 1998-05-12
Abstract: PROBLEM TO BE SOLVED: To obtain the subject coating giving a stable coating liquid viscosity and making it possible to prepare Tempura (deep batter fried food) having good water penetrability, crispy touch and texture by compounding devil's tongue mannan in the form of powdery devil's tongue. SOLUTION: This coating used for Tempera and having a high edible fiber content is obtained by compounding (A) devil's tongue mannan in the form of powdery devil's tongue (concretely obtained by once producing devil's tongue from devil's tongue powder by a conventional method, washing the produced devil's tongue with water until to produce the neutral devil's tongue without using an organic acid, or the like, drying the produced neutral devil's tongue and subsequently grinding the dried neutral devil's tongue). The coating is obtained e.g. by sufficiently mixing wheat flour with the devil's tongue powder A in a dry amount of 1-50 wt.% based on the wheat flour and subsequently further mixing the mixture with water under agitation.
Patent JP-S6226980-A (JP)
Title: Synchronizing signal generator
Inventor: NISHIZAWA MASAJI
IPC: H04N5/06
Filed: 1985-07-29
Abstract: PURPOSE:To form immediately a stable composite synchronizing signal and chrominance subcarrier synchronously with an external composite synchronizing signal by using an external frame signal to reset once an internal composite synchronizing signal when a frame phase deviation is large to decrease the deviation and using a PLL to lead-in the phase thereby having only to add a simple gate circuit. CONSTITUTION:An external frame signal from a frame signal detection circuit 5 is inputted to a Set terminal of a phase comparator 7 and a frame signal from a frame signal detection circuit 3 is inputted to a Reset terminal respectively and its comparison result is outputted from a Phase Detect Out terminal. When the deviation of frame phase is larger to a degree, since the pulse width of the pulse signal from the Phase Out terminal is increased, an integration output from an integration circuit 8 is increased and a gate of a gate circuit 9 is opened. Thus, the external frame signal from the frame signal detection circuit 5 is impressed to a V.Reset terminal of a composite synchronizing signal generating circuit 1 to reset a counter of a frequency division circuit 1c.
Patent JP-S5688446-A (JP)
Title: Bridged polyethylene resin pipe
Inventor: DOI SHIYUUHEI
IPC: B29C48/32
Filed: 1979-12-20
Abstract: PURPOSE:To obtain a bridged polyethylene resin pipe having excellent heat resistance and good fusion bonding property from a water-bridged ethylene-unsaturated silane compound copolymer. CONSTITUTION:A copolymer containing approx. 0.0-15wt% unsaturated silane compound is obtained from radical polymerization of ethylene and an olefinic unsaturated silane compound of the formula (where R is an olefinic unsaturated hydrocarbon group or a hydrocarbonoxy group, R' is an aliphatic saturated hydrocarbon group, Y is a hydrolyzable organic group, and n is 0, 1, or 2), e.g., vinyltrimethoxysilane, etc. Then, said copolymer is mixed with approx. 0.001-10wt% silanol condensation catalyst, e.g., dibutyltin dilaurate, in an extruder and extruded to form a pipe. Then, the pipe thus obtained is brought into contact with water at ordinary temperature to 100 deg.C for 10sec to a week for bridging to obtain a product.
Patent JP-S5688355-A (JP)
Title: Semiconductor memory device
Inventor: NATORI KENJI
IPC: G11C11/41
Filed: 1979-12-20
Abstract: PURPOSE:To enhance the integrity and the performance of the semiconductor memory device by forming the device of ordinary MOS transistors and MOS transistors having two layer gate electrode. CONSTITUTION:The first MOS transistor Q11 having ordinary configuration and  the second MOS transistor Q12 having two-layer gate electrode are formed on the  same semiconductor substrate, the source of the tansistor Q11 is connected to the  first gate electrode layer of the transistor Q12, and the connector is used as an information memory anode. The first and second bit lines BL1 and BL2 selected by  the addresses in column direction are connected to the drains of the transistors Q11  and Q12 respectively, the first and second word lines WL1 and WL2 selected by the  addresses in row direction are connected to the first and second gate electrodes of the transistors Q11 and Q12 respectively, and a power source voltage B is connected  to the source of the transistor Q12. Thus, the transistor Q12 is conducted or shut off  corresponding to the information ''1'' or ''0'', and operated to read as prescribed.
Patent JP-H0815730-A (JP)
Title: Production of substrate for display
Inventor: NODA KAZUHIRO
IPC: H01L29/786
Filed: 1994-06-24
Abstract: PURPOSE:To prevent peeling and rupturing of flattening films by improving a flattening treatment in a multilayout system of substrates for display. CONSTITUTION:A wafer 1 consisting of an insulating material is first prepd. and plural blocks 3 parted from each other via prescribed separating bands 2 are set. Next, lower layer regions 4 including numerous thin-film transistors are integrated and formed in the respective blocks 3. In succession, the wafer 1 is selectively coated with the flattening films 5 exclusive of the separating bands 2 to fill the ruggedness of the surfaces of the lower layer regions 4 formed in the respective blocks 3. Further, numerous pixel electrodes are integrated and formed in a matrix form on the flat surface of the flattening films 5 within the respective blocks 3, by which upper layer regions 8 are formed. These upper layer regions 8 are electrically connected via the flattening films 5 to the lower layer regions 4. Finally, the wafer 1 is cut along the separating bands 2 and is separated to the individual blocks 3, by which the substrates for display in the form of chips are obtd.
Patent JP-S6225233-A (JP)
Title: Simulation device on equivalent path
Inventor: ETO AKIRA
IPC: G01M17/00
Filed: 1985-07-26
Abstract: PURPOSE:To speed up the generation of a command value and to improve the response of the reproduction of a run resistance value by obtaining direct acceleration by the detection of shaft torque and then generating an inertial resistance value. CONSTITUTION:When a rotating shaft 21 has acceleration omega, a torque output T corresponding to the acceleration omega and the quantity I0 of inertia of a reference flywheel 83 is generated on the shaft 91 of a shaft torque detector 82 united with the rotating shaft. This output is inputted to an adder 70 together with the output of a rolling and windage resistance value generator 50 while a coefficient (I-I1)/I0 (I: weight equivalent inertia quantity of vehicle 23 to be tested, I1: inertia quantity of rotating part of simulation device) is doubled by an arithmetic part 84, thereby controlling the load on a dynamometer 10. At this time, inertial resistance omegaI1 is generated at the rotating part of the simulation device and the sum of both resistances, i.e. run resistance value to be reproduced is applied to the vehicle 23 to be tested.
Patent JP-H0462875-A (JP)
Title: Semiconductor device
Inventor: ISHII KAZUTOSHI
IPC: H01L21/76
Filed: 1990-06-25
Abstract: PURPOSE:To restrain variation of characteristics of high breakdown strength transistor and to enable reduction of cell size by making a bird's beak of an isolation oxide film of a high breakdown strength MOS type transistor region longer than that of an isolation oxide film and by matching the position of a gate electrode end and the position of a bird's beak end of the isolation oxide film. CONSTITUTION:An isolation oxide film 3 of a short bird's beak length is selectively formed in a 5V transistor region 2 in an area near a surface of a P-type semiconductor substrate 1, and an isolation oxide film 5 of a long bird's beak length is formed in a high breakdown strength transistor region 4 in an area near a surface of the P-type semiconductor substrate 1. Then, a gate oxide film 7 is formed in a region 6 which is to become a channel enclosed with the isolation oxide film 5 of the high breakdown strength transistor region 4. A gate electrode 8 is formed whose channel direction extends to a bird's beak end of the isolation oxide film 5 and channel width direction extends to the isolation oxide film through the gate oxide film 7. Thereby, it is possible to relax an increase of 'on' resistance caused by alignment deviation between the gate electrode 8 and a bird's beak end of the isolation oxide film 5.
Patent JP-S5868346-A (JP)
Title: Data transmission system
Inventor: NANBU SHIGEO
IPC: G06F13/368
Filed: 1981-10-18
Abstract: PURPOSE:To increase an effective data transmission speed by providing a request line exclusively used by a monitor station in addition to a common request signal that a master station when searching for respective stations. CONSTITUTION:A monitor station 10 and process control stations 11 are connected mutually by a transmission line 5, a common request line 7 that a master station uses in search, and a request line 6 exclusively used by the monitor station 10. The line 6 is connected to a power source +5 through a pull-up resistance 8, the output port 18 of the monitor station 10 is connected to the line 6 through an open-collector output 15, and the interruption signal generating circuit 17 and input port 19 of the control station 11 are connected through an input buffer 14. Further, a pull-up resistance 9 is connected to the line 7, and the circuit 17 and input port 19 of the monitor station 10 are connected through a buffer 14; and the output port 18 of the control station 11 is connected by the open collector output 15, and the circuit 17 and input port 19 are connected through a buffer 14.
Patent JP-H0215640-A (JP)
Title: Manufacture of mos transistor
Inventor: KITAGUCHI HIROHISA
IPC: H01L21/225
Filed: 1988-07-04
Abstract: PURPOSE:To further miniaturize devices and to increase circuit integration density in a diffusion layer forming process by a method wherein a doped oxide section is formed in a specified region on a semiconductor substrate and the impurity contained in the doped oxide section is allowed to be diffused into the semiconductor substrate. CONSTITUTION:A doped oxide section is organized in a specified region on the surface of a semiconductor substrate, and the impurity contained therein is caused to diffuse into the semiconductor substrate, which results in a low concentration doped layer to develop into second diffusions layers 29a, 29b. The doped oxide section also serves as a mask useful in a process of etching away useless protrusions from a gate region whereon a gate electrode 32 is to be built. This allows the second diffusion regions 29a, 29b and the gate region to form by self-alignment, when the gate region will be practically same in width as the part to serve as a gate electrode. Accordingly, the aligning process may be dispensed with. With a margin for alignment not being required, the effective gate width W1 will be equal to the active gate width W2, realizing a structure suitable for an enhanced circuit integration density.
Patent JP-S5792487-A (JP)
Title: Nonvolatile memory
Inventor: ARAKAWA HIDEKI
IPC: G11C17/00
Filed: 1980-11-26
Abstract: PURPOSE:To reduce the size of a memory and to eliminate malfunction by forming a writing and an erasing part of transistors (TR) for storage separately from a main part. CONSTITUTION:Both MOSTRs Q1 and Q2 for storage and selection are divided into an MOSTRQ11 for readout and a writing and erasure part Q12, and TRs Q21 and Q22 for selection. For writing operation, a Y, Y' and an X are held high for a selected cell to turn on the TRs Q21, Q22 and Q3, and a high voltage is applied to the drain of the Q11 and the diffused area WED of the Q12. Since a control gate CG is held at level zero, electrons are extracted from the floating gate FG of the Q12 to the area WED, thus performing the writing operation. In a half-selected or unselected cell, the Q22 and/or Q3 are off and the high voltage is not applied to the area WED of the Q12, so that the writing operation is not performed. To erase all data at a time, the Y held at O, and Y, X and CG of every cell are held at high levels, and consequently electrons are applied from the WED to the FG of the Q12. Thus, erasure is carried out.
Patent JP-H0916604-A (JP)
Title: Information processing system
Inventor: NANJO HIDEKO
IPC: G06F17/28
Filed: 1995-06-30
Abstract: PURPOSE: To recognize characters included in a television(TV) picture and to effectively utilize the recognized result. CONSTITUTION: An extraction part 21 extracts character information included in picture information stored in a TV device, a recognition part 22 recognizes the character information and a conversion part 23 converts the recognized result into a text. A translation part 24 translates the text to another language, an output part 25 outputs the translation data to the TV device and outputs the translation data and the text data to an information processor.
Patent JP-S6411295-A (JP)
Title: Display device
Inventor: ASAKA TAKAO
IPC: G09G5/00
Filed: 1987-07-03
Abstract: PURPOSE: To update image data and speed up display operation by updating image data in two image memories alternately in screen units and selectively displaying image data after update in one memory and image data before update in the other memory, and continuously performing the said processes. CONSTITUTION: The image data, stored in the two image memories 5 and 6 stored with the image data of one screen respectively, are updated alternately in screen units, the image data after update stored in one image memory 6 during image data update and image data before update stored in the other image memory 5 are selectively outputted to a display part, and the update and display of the image data are successively performed. Consequently, the update and display of the image data can be performed fast.
Patent JP-2000004504-A (JP)
Title: Control method of electric torque converter
Inventor: HORIE TATSURO
IPC: B60L50/10
Filed: 1998-06-15
Abstract: PROBLEM TO BE SOLVED: To reduce the installation capacity of an inverter and realize miniaturization and cost reduction, by dividing the winding of a motor into a plurality of sets of windings, connecting the respective windings to the inverter, and connecting respective inverters to DC power supply in series. SOLUTION: An internal combustion engine 1 serving as a prime mover is used for the power of an AC generator 2, and its output is changed into DC power using a rectifier 3. A plurality of inverters 4, 4B, 4C are connected to the DC power, or power supply in series, and a plurality of pairs of armature windings 10, 11, 12 are connected to the respective inverters 4, 4B, 4C. The inverter 4C and the armature winding 12 are used to generate prescribed torque in a low speed range under this conditions, the inverter 4B and the armature winding 11 share the prescribed torque, and the inverter 4 and the armature winding 10 generate the prescribed torque. It is thus possible to reduce the capacity of the respective inverters 4, 4B, 4C serving as control power supply to approx. a half.
Patent JP-2000354171-A (JP)
Title: Color gamut compressor and color gamut compression method
Inventor: TAKAHASHI MARIKO
IPC: H04N1/60
Filed: 1999-06-14
Abstract: PROBLEM TO BE SOLVED: To compress a color into the one with high visual matching performance with respect to a hue without losing consecutiveness of the color. SOLUTION: The color gamut compressor 1 converts a color expressed by an input system information device 21 into a color within a color gamut reproducible by an output system information device 22 to compress the color gamut. In this case, the compressor 1 is provided with a converging point calculation section 103 that calculates a coordinate on the basis of any point representing a color with a hue equal to that of a color resulting from reproducing a digital signal value of the input system information device 21 corresponding to the color decided by the color expressed by the input system information device 21 by the output system information device 22, within a color gamut of the output system information device 22, sand representing a chromatic color to be a converging point.  The compressor 1 is also provided with a 1st compression point calculation section 104 that calculates any coordinate of any point nearly on a straight line tying the converging point and a point corresponding to the color expressed by the input system information device 21 and within the color gamut by the output system information device 22 as a compression point, and a compression section 106 that converts the color expressed by the input system information device 21 into a color corresponding to the compression point calculated by the 1st compression point calculation section 104.
Patent JP-H11351540-A (JP)
Title: Thermal storage type combustion gas treating apparatus
Inventor: ARANAGA HIDEOMI
IPC: F23G7/06
Filed: 1998-06-15
Abstract: PROBLEM TO BE SOLVED: To reduce in size and to improve performance of a thermal storage type combustion gas treating apparatus. SOLUTION: The thermal storage type combustion gas treating apparatus comprises ventilation inversion switching means v1 to v4 for alternately switching a ventilation route of a gas G to be treated to a first ventilation state for sequentially passing the gas G through a first thermal storage unit 5A, a combustion chamber 6 and a second thermal storage unit 5B in this order or to a second ventilation stage for sequentially passing the gas G through a second thermal storage units 5B, the chamber 6 and a first thermal storage unit 5A in this order,  an untreated gas recovery switching means 9 for switching a guiding route of these gases to a recovery state for introducing the gas passed through a second thermal storage unit 6B in a first ventilation stage and the gas passed through the unit 5A in a second ventilating state to an exhaust stage for sending the gas to an exhaust passage 10 or to a recovery stage for introducing the gas to a tank 11, and a circulating means 12 for circulating the gas G introduced into the tank 11 to the unit 5A in the first state and to the unit 5B in a second state.