Patent GB-1450770-A (GB)
Title: Electrical apparatus for performing digital calculations
IPC: G06F9/38
Filed: 1972-12-29
Abstract: 1450770 Data processing system MARCONI CO Ltd 7 Jan 1974 [29 Dec 1972] 59972/72 Heading G4A A data processing system includes a number of units 1-5, only 1 and 2 shown, interconnected via a common data highway 6, at least one of the units being a read write store and others being arranged to perform mathematical operations on data. supplied thereto, and a controller 7 connected to each unit via two address highways 11 and 12, the arrangement being such that in operation the controller supplies addresses to the two address highways and data is supplied to the data highway by a unit adressed by signals on a first address highway 11  and data is received from the data highway by a unit addressed by signals on the other address highway 12. The controller 7 has a microprogram store 13 addressed by a normally incremented register 14 to supply instructions to a buffer 15 into which they are gated in response to a signal 17 from logic 16 indicating that the previous operation is complete. Each instruction includes a source and a destination address which are supplied to highways 11 and 12 respectively. Separate registers within a unit may be individually addressed as a source or destination, e.g. the registers within the store 1 or, in a multiplication operation, by registers 8 and 9 which receive operands in response to successive instructions. The unit 2 being arranged automatically to perform the multiplication when all required data are present and to supply the result to register 10 from where it may be accessed by a third instruction. For operations such as multiplication which may take a relatively long time the relevant unit (e.g. 2) supplies a busy signal over line 21 which may inhibit fetching of the next instruction, or allow different instructions to be fetched to avoid wasting time, the different instructions may be supplied by a second similar controller which time shares the units with the first controller. Jump instructions may be executed. For example one of the units, e.g. 4, may be arranged to compare two data words and as appropriate produce "skip" signal on line 28 to cause the next instruction in the sequence to be omitted. Alternatively a special "jump" instruction may specify two addresses one being characteristic of a jump instruction which is recognised by the controller and the other indicating by how much address register 14 should be incremented. Conditional jumps are possible by using a combination of the above two procedures. The "skip" being to a "special" jump instruction. The address register 14 may also be addressed and supplied with data from the data highway. One of the units, e.g. (5) Fig. 2 (not shown) may be connected to a large data store (22) which is accessed by addressing registers in unit (5) and supplying two data words to respective ones of the registers over highway 6, one being an address in store (22) and the other being data to be read into the store. In a read operation only one (address) word is supplied, store (22) feeding data to highway 6 via the appropriate register in unit (5). Instruction words may also be written into program store 13, from store (22) or from a magnetic tape reader. A write address register (not shown) associated with store 13 is addressed and supplied with data over highway 6 to address a location in store 13. A second instruction then causes an instruction word to be supplied over highway 6 and written into the addressed location in store 13. Store 13 may be an integrated circuit device and the units 1-5 may include dividers, adders, subtractors, floating point units, mathematical function units, interfaces for printers or other peripheral equipment &c. The arrangement is said to be of use as an aircraft simulator or in other real time applications.