Patent GB-1078309-A (GB)
Title: Intermediate exchange for pulse code modulated time division multiplex signals
IPC: H04J3/06
Filed: 1964-09-18
Abstract: 1,078,309. Automatic exchange systems. TELEFONAKTIEBOLAGET L. M. ERICSSON. Sept. 18, 1964 [Sept. 18, 1963], No. 38311/64. Heading H4K. In an intermediate exchange in a time division multiplex transmission system in which pulse code modulated signals arrive at the exchange over a number of incoming links and have to be transferred through the exchange to a number of outgoing links, signals in an incoming link not necessarily corresponding as regards link and channel position with those in the outgoing link, and in which signals on different incoming links are of different phase due to the different propagation times of the links, a memory is provided in which the signals incoming to the exchange are entered in coded form in phase with the pulses on the incoming link, the position in the store being governed by the destination address of the signal element, defined by the number of the outgoing channel and by the number of the outgoing link and the signals are read out of the store under the control of a central clock and thus in phase one outgoing link with another. In the described embodiment an intermediate exchange has 32 incoming links each carrying the time multiplexed signals of 24 channels. Each channel comprises 8 bits of information, 7 bits being used for speech signal transmission and the 8th bit of each of the 24 channels being used to transmit a synchronizing signal, and, in each fourth cycle, to set up a 24-bit data channel to send information about the calls, e.g. as described in Specification 903,208. The main exchange over the data channel, interrogates each speech channel in turn and if the condition of the speech channel has changed since the last interrogation the subexchange transmits a stop signal to the main exchange to halt the interrogation, from which time the data channel is used to transmit information about the condition of the one speech channel, e.g. sub-exchange calling, destination address &c. Fig. 13 shows the layout of an exchange according to the invention, showing part of the equipment associated with 2, L1 and L2, of the 32 links. Fig. 13 shows how the synchronizing signals from one of the links are selected via a relay R to drive a clock system for the whole exchange via a control channel. Should the synchronizing signal in the selected link fail then relay R operates to derive the control channel signal from a different link. In each link, e.g. L1, the pulse signals are fed from the line into a shift register SKA which takes the 7 digits of the p.c.m. speech signal and on the 8th digit, the synch. digits, the 7 p.c.m. digits are fed to a buffer register, SKB, enabling the register SKA to take the 7 p.c.m. digits of the following channel. An address store AM has stored in it, in p.c.m. form, the link address and channel address of each incoming channel, the addresses being derived from a computer fed with the data channel formed by each fourth cycle of the eighth pulse in each channel and applied to the memory AM on leads DM. The address register AM is read, channel by channel, in response to the stepping counter KRA and the address corresponding to each coded speech channel element is fed to a second memory KM by translators ORL and ORK to define the storage position into which the speech element in buffer register SKB is to be fed via the gates 01 to 07. As previously mentioned the signals on the various incoming links may be out of phase but, due to their being entered in coded form into the store KM and then read out from this store under the control of the central exchange clock, the signals outgoing from the exchange are all in phase. Fig. 15 shows the read-out arrangement for the store KM in which each incoming link is associated with one plane of the store, the coded channel signals being stored on the plane in a position appropriate to its destination link and channel address and being read out channel by channel in response to pulses from the stepping counter KRB, each digit of the coded channel signal and each corresponding channel of each outgoing link simultaneously into a buffer register SKC, one register provided for each link. The signals from buffer register SKC are converted into serial form by the shift register SKD from which they are fed, together with the synchronizing and data digits, to the outgoing lines from the exchange.