Patent DE-3765562-D1 (DE)
Inventor: KERN ROLF DIPL ING
IPC: G06F9/38
Filed: 1987-03-20
Granted: 1990-11-22
Abstract: 1. Arrangement for processing branch instructions in pipelined data processing systems comprising an instruction editing processor (PLU) for instruction reading (LB), instruction interpretation (IP), address computer (AR) and parameter provision (PB), with an instruction execution processor (EXU) for the actual instruction execution (AF) and with a common buffer and main memory, the instruction decoder (IDEC) of the interpretation stage (IP) being coupled to an indicator monitoring device (AZ-CONTROL) for temporarily storing and evaluating indicator change indications (CH-AZ) supplied during the interpretation of each instruction (for example n) for the purpose of generating a control signal (AZV) declaring the existing indicator (AZ) as valid, the conditional branch instruction being treated like an unconditional branch instruction in the presence of the control signal (AZV) declaring the existing indicator (AZ) as valid during the interpretation phase of each conditional branch instruction in a branch instruction evaluating device (B-CONTROL) and the indicator (AZ) being used for checking whether the branch condition has been satisfied or not, and the further control sequence for instruction editing being correspondingly influenced (UNB.NERF, UNB.ERF signals), whilst the control sequence corresponding to a conditional branch instruction (BED signal) is maintained when the indicator can still be changed, characterized by - a predetermined number of storage flip-flops, for example (MFF-A to MFF-C) for storing in each case one of the indicator change indications (CH-AZ) supplied by the instruction decoder (IDEC), - by a selection counter (SELC), which can be cyclically stepped on by control pulses (CL-SELC) for selecting in each case one of the storage flip-flops (for example MFF-A) for transferring an available indicator change indication (CH-AZ) in dependence on a separate storage clock (CLM), - by an OR gate (for example 015), which is connected to the outputs of the storage flip-flops (for example MFFa), with inverted output which supplies the control signal (AZV) declaring the present indicator (AZ) as valid, and - by a preceding control device (STE) for generating the control pulses (CL-SELC and CL-M) for the storage flip-flops (MFF-A to MFF-C) and the selection counter (SELC) in dependence on control signals (for example TRUESW, CL1, CL2 and CL4) in each case present during the pipelined instruction processing and control signals (BED, BED.NERF), supplied by the evaluating device (B-CONTROL) and relating to the execution of a conditional branch instruction, - an advance counter (PAC) the count of which is incremented by one step by a control pulse (CL-PAC) supplied by the preceding control device (STE) with each instruction forwarded by the interpretation stage (IP) in the pipeline and is decremented by one step with each instruction terminated in the execution stage (AF), - by a validity counter (VAC-A to VAC-C) which is individually associated with each storage flip-flop (MFF-A to MFF-C) and can also be selected by the selection counter (SELC) for transfering the count (for example 3) in each case provided by the advance counter (PAC) in dependence on a load pulse (L-VAC) supplied by the preceding control device (STE), the load counts of all validity counters (VAC...) also being decremented step by step by the count-down pulses supplied to the advance counter (PAC) and - by switching elements (011 to 013) in each case monitoring the count of the validity counters (VAC...), which inhibit the output signals of the associated storage flip-flops (for example MFF-A) with a count of 0.