Patent GB-923955-A (GB)
Title: Improvements in or relating to digital information transfer systems
IPC: H04Q1/45
Filed: 1962-01-25
Abstract: 923,955. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Jan. 25, 1962 [Feb. 16, 1961], No. 2788/62. Class 40 (4). [Also in Groups XXXVIII and XL (c)] Binary data, indicating the state and identity of lines in a pbx or concentrator system, is transmitted to a central office as shifts between two voice frequency rectangular waves such that each binary bit has the same time duration and comprises M cycles of one frequency or N cycles of the other frequency, M and N being integers. As embodied the frequencies chosen are 1000 c/s. and 2000 c/s., binary 0 comprising one cycle of the 1000 c/s. waveform and binary 1 comprising two cycles of the 2000 c/s. waveform. The transmitter is shown in Fig. 2 where the data is presented in mark/space form by a source 27. A clock source of 2000 c/s. is divided by two at 22 and the resulting 1000 c/s. is used to control the serial output of data from source 27 where it is originally in parallel form on a shift register. The data controls AND gates 23, 24 to gate one or other frequency to an OR gate 25 which is a linear inverting amplifier matched to the line. The line may be a telephone trunk. An example of the waveform transmitted is shown at A in Fig. 7 where a binary 0 is followed by a binary 1. A receiver is shown in Fig. 3 where the waveforms of Fig. 7 occur as indicated by the circled reference letters. Distortion of the incoming signal is corrected by a squaring amplifier 31 which produces the waveform A. To detect  binary 0 an integrator 32, comprising a capacitor, times an interval of about 600 ms. measured from negative-going transitions of waveform A. The integrator rises above the slice level shown in waveform B in the presence of binary 0 only. An amplifier 34 is biased to provide the slice level and to amplify only that portion of the integrator output which lies above the level. The sliced output. which is inverted, is shown in waveform C. Since the waveforms A and C are negative together in response to binary 0 only, AND gate 35 produces waveform D giving the binary 0 output. A synchronizing waveform is extracted from the signal by a divideby-two circuit 33. Since only the binary 1 signals require division to produce a 1000 c/s. pulse train shown at G, the divide-by-two circuit 33 is reset by the binary 0 output whenever an attempt is made to divide the binary 0 signal. The output of the divider is shown at E and F, the negative-going transitions of waveform E being regularly spaced and providing a drive for the pulse generator 36 producing the pulses G which govern the registration of the serially arriving bits in parallel on a shift register. Waveform F is produced to provide an independent binary 1 output determined by AND gate 37 supplied by negative values of the A, D and F waveforms. A receiver which responds to an inversion of the transmitted signal may be placed in parallel with the receiver described above so that disparity between the two sets of binary output signals may be used to signal an error. Transistor circuits for the transmitter and receiver are described with reference to Figs. 5 and 6 (not shown).