Patent GB-1260780-A (GB)
Title: Data processing apparatus
IPC: G06F9/50
Filed: 1970-09-03
Abstract: 1,260,780. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 3 Sept., 1970 [15 Sept., 1969], No. 42097/70. Heading G4A. Data processing apparatus incorporates a number of data processors each capable of operating independently of the others to process data in accordance with a sequence of instructions addressed thereto, detection in such a sequence of a FORK instruction representative of a number of tasks which can be undertaken independently of each other causing issue of a respective FSW (fork status word) including an indication of the number of tasks, these tasks being distributed to the processors under the control of the FSW and stored indications of which processors are free and which busy, the indication of the number of tasks being updated as successive tasks are accomplished. Each task is a sequence of instructions, the first task ending with a JOIN instruction and each other task ending with an END instruction. A task may include a further FORK instruction which causes issue of a respective FSW. Each FSW specifies: (a) the number of tasks in the fork which are as yet undistributed, (b) the number of tasks in the fork which are distributed but not yet completed, (c) a pointer to the first instruction of the first task, (d) a pointer to the first data parameter of the first task, (e) the type of the tasks, (f) whether the processor which issued the current fork has aborted (departed) from the group of processors working on the tasks of this fork (abort bit), (g) whether this FSW is the initial FSW of this fork, (h) the return address of the next instruction after the JOIN instruction, (i) the address of the current FSW in its particular queue, (j) the address of the FSW associated with the current FORK instruction, (k) the type of the task associated with the current FORK instruction, (l) the identification code of the processor which issued this FSW. Each processor has a queue of FSWs, a FSW register, and a sub-queue of FSWs, the latter permitting the processor to distribute tasks of a FSW using-the FSW register, even though tasks of a previous FSW have not been completed, this previous FSW being saved in the sub-queue. A resource table is provided indicating for each processor its identification code, the type of tasks it can handle, and whether it is free or busy (free and busy bits). If a processor encounters a FORK instruction, it inserts items (i) and (j), see above, into the FSW, and requests resources (processors of the appropriate type). If the FSW queue is not empty, the abort bit (f) is set and the FSW is put into the queue, but if the queue was empty the FSW is put into the FSW register. In either case, enquiry is made whether all tasks are distributed. If yes, the processor reports in free, but if not (as is the case at this point) the next task is distributed to this processor and item (a) is decremented. Then the processor decodes its next instruction except that if all tasks are now distributed the following actions also occur: the FSW sub-queue is shifted down (thus receiving the FSW from the FSW register) and if the FSW queue is empty the resource request is turned off whereas if it is not empty, the next FSW is shifted down from it into the FSW register. When a processor reports in free, then if it has been requested (a resource request flip-flop associated with it being on), its busy bit is set and enquiry is made whether all tasks are distributed, operations following from this point as above. If a processor encounters an END instruction, item (b) is decremented, then if all tasks are not complete, enquiry is made whether all tasks are distributed, operations following as above (the completed task information also being stored if all tasks are distributed), but if all tasks are complete, the abort bit is tested and if the issuing processor has not aborted, the completed task information is stored and the processor reports in free, whereas if the issuing processor has aborted, the processor acquires item (h) then if this is the original FSW in the fork situation, the job is completed and the processor reports in free, whereas if it is not the original FSW, the data from this fork is co-ordinated and the previous FSW is accessed followed by an enquiry whether all tasks are complete, operations following from this point as above. If a processor encounters a JOIN instruction, the FSW is accessed, then if all tasks are not complete, a priority interrupt request, if present, causes abort, whereas if all tasks are complete, an enquiry is made whether this is. the original FSW in the fork situation. If it is, the processor completes the job and reports in free. If it is not, the processor continues instruction processing until it reaches an END instruction when the data from the fork is co-ordinated and the issuing FSW is accessed. If all tasks are complete, item (h) is acquired, the job is completed and the processor reports in free, whereas if all tasks are not complete an enquiry is made whether all tasks are distributed, operations following from this point as before. Thus, inter alia, data co-ordination is done by the issuing processor unless it has aborted in which case it is done by the last processor out. In a modification, an END instruction is used in place of each JOIN instruction. The processors may be similar to those in Specification 1,241,403 (referred to).