Patent GB-1261599-A (GB)
Title: Time-multiplex switching centre
IPC: H04J3/06
Filed: 1970-01-22
Abstract: 1,261,599. Automatic exchange systems. INTERNATIONAL STANDARD ELECTRIC CORP. 22 Jan., 1970 [30 Jan., 1969], No. 3171/70. Heading H4K. In a TDM, PCM tandem exchange, connections between channels on incoming and outgoing highways are effected over a spacespace-time-space-space switching network in which the PCM bits pertaining to each channel are conveyed in parallel mode. The time switch comprises a plurality of junctors that allow time slot interchange in respect of both directions of transmission. The space switch comprises two stages of matrices having the highways connected to one side thereof and the junctors connected to the other side thereof. Control of the crosspoints and of the read/write gates in the junctors is vested in cyclically operative memories located in the junctors. The highways are arranged in groups in which the signals from all the channels are supermultiplexed. The basic system is depicted in Fig. 10 which shows the space-time-space network in respect of a call between a channel in trunk super group SG1.1 and another channel in trunk super group SG8.2. Although shown as an unfolded network crosspoint switches Q2, Q<SP>1</SP>8 do in fact belong to the same stages as switches Q2 and Q<SP>1</SP>1 respectively. At the centre of the network is located a junctor containing a slot changing speech memory MDJ and a time path memory MCT. Each of the crosspoint switches is controlled by a memory MSS<SP>1</SP>, MSS for calling side connections during a time slot tx and MSA, MSA<SP>1</SP> for called side connections during a time slot ty. Every junctor contains a block of six such memories which are addressable by a common address circuit. Thus junctor 5 of super junctor group SJ2 has the four memories shown plus another two memories MSS<SP>1</SP> and MSA<SP>1</SP> not shown. The shown memories MSS<SP>1</SP> and MSA<SP>1</SP> belong to junctors 2 in super junctor groups SJ1 and SJ8 respectively and they (as indeed all the memories) are accessed initially by a common control unit (not shown) in order to serve the considered call. In more detail the two stages of the network are depicted in Figs. 7 and 8 wherein each matrix is of the 8 Î 8 (h Î v) variety, each crosspoint comprises 16 gates (8 Go and 8 Return) and, each column has a control memory MSS for controlling the relevant crosspoint during the calling side time slot tx and a control memory MSA for a similar purpose during the called side slot ty. Fig. 5 shows the path of the call in still more detail, the calling side switches having been reduced to gates Pa1 (Go) and Pa2 (Return) and the called side switches to gates Pa3 (Go) and Pa4 (Return). At this point it is convenient to discuss the super group terminology touched on above. Every incoming trunk is of the 4-wire type and carries 24 channels utilizing 8 bit serial PCM code. The first task that must be performed on the incoming channels is to synchronize them for passage through the exchange. In part, this is performed by converting their contents into 8 bit parallel code and then inserting this code into a well defined position in a 192 position memory. The conversion and buffering are effected in unit SCR1 and half-unit MDG1/I for the calling side (Fig. 5 and Fig. 3, not shown). (The other half-unit of the memory is akin to the half-unit MDG2/P, but this latter pertains to another group of trunks in the case under consideration). Here the odd-numbered trunks N1-N7 of the group of eight trunks associated with SCR1 are allocated positions in memory MDG1/I whereby each of the 96 (24 Î 4) individual channels on these four trunks has a unique position in the memory. The even numbered trunks have a separate half memory (not shown. ) The full memory is associated with one inlet h of a first stage crosspoint switch (Fig. 7), the odd and even half memories being used for calling and called side connections in conjunction with control memories MSS and MSA respectively. The h i.e. 8 memories associated with the inlets of one Q<SP>1</SP> switch comprise a super group of 8 x 8 trunks. Each outlet of a Q switch is connected to a junctor whereby 8 such junctors associated with one Q switch form a junctor super group (Fig. 8). Reverting now to Fig. 5. The control of half memory MDG1/I pertaining to a channel x in one of the oddnumbered trunks N1e ... N7e are read-out in the normal process of cyclically reading this memory and passed virtually instantaneously via a register RG11 and the switching stages Q<SP>1</SP>1, Q2 (i.e. gate Pa1) to a position x in junctor memory MDJ which has been allocated to the call. Simultaneously, the existing contents of position x in MDJ are read-out and passed via the same crosspoints (i.e. gate Pa2) to a demultiplexer DXG1/I prior to application to the relevant Return channel of the calling trunk. In the course of cyclically reading time path memory MCT in the junctor, at the time ty allocated to the called side of the connection, the address of the same position x in memory MDJ is obtained so that during the second half of time slot ty, the contents of x which were inserted at tx are passed via stages Q2, Q<SP>1</SP>8 i.e. gate Pa4 to a demultiplexer DXG2/P. Simultaneously, the contents of position y in half memory MDG2/P are read-out and passed via stages Q<SP>1</SP>8, Q2 i.e. gate Pa3 into position x of MDJ for subsequent transmission to DXG1/I at the next occurrence of time slot tx. The demultiplexers DXG each contain a parallel/serial converter comprising a shift register associated with each trunk. The central control ensures that data is routed to the correct shift register for immediate read-out in the appropriate channel of the trunk. Synchronization including compensation for drift, phase jitter and framing loss are effected by the systems described in Specifications 1,165,268 and 1,261,598. Timing (Fig. 1).-The output of the system clock (81 nsec. period) is divided, in two bistable-stage counters, to provide a basic frame period TR of 125 Ásec. This consists of twenty four 5À2 Ásec. channels V1-V24 each of which contains eight 650 nsec. digit time slots m1-m8. Each pair of digit slots has a ts and a tA pulse associated therewith-these being the two half time slots for calling and called side connections referred to hereinabove. Each of these half time slots is divided into sub time slots a 1 , a 2 , b, c, d 1 , d 2  which are used for fine time control of the gates depicted on the Figures. Alternative connections of super groups to switch (Fig. 11, not shown).-It should be noted firstly that the two halves of the memory associated with the odd and even numbered trunks of a group are read simultaneously, the contents of the two halves being buffered for successive transmission through the same inlet of the switch Q<SP>1</SP> during two successive half time slots. In the alternative, which does not restrict the trunks to permanent allocation as calling or called, the two half memories are again read simultaneously but this time their respective outputs are passed to two separate inlets of the switch Q<SP>1</SP> although such passage, as before, occurs only during the half-time slot associated with each memory. Tone transmission and supervision of digit repetition when the exchange is a tandem or toll exchange. Both these facilities are provided by units in the junctors. Tone-or at least a code indicative of the tone to be usedis inserted in the relevant half connections to the calling and called channels, tone signalling being unidirectional. A special memory (Fig. 12, not shown) containing the addresses of channels requiring tone, and the type of tone required, is utilized. Digit repetition is normally supervised by a junctor in a bypath connection (Fig. 13, not shown). Path finding is effected by a computer with the aid of a network map. The block of memories in each junctor (see above) has an independent power source and sub-clock so that a failure thereof has only a limited effect on the system and also expansion of the system is facilitated. Instead of having a "horizontal set" of memories in each block (dotted line MDJ in Fig. 8), some of the memories in a block may be selected from different verticals in different ranks of the switches (Fig. 14, not shown). Path finding in this case is simplified since with a known inlet i.e. a channel, and a preselected junctor the route through the switching network is immediately known in its entirety.