Patent GB-1220144-A (GB)
Title: Computer system
Inventor: HARMON SHERRIL ALLAN
IPC: G06F13/26
Filed: 1968-05-29
Abstract: 1,220,144. Data input/output control. GENERAL ELECTRIC CO. 29 May, 1968 [29 May, 1967; 21 June, 1967], No. 25806/68. Heading G4A. In a computer system in which fixed length information words may consist of a selected number of bytes, each comprising a plurality of binary digits, means are provided for controlling the transfer of information bytes between a memory providing storage locations of capacity of one word each and one or more peripheral devices. As disclosed, information words of 24 bits each may be divided into 1, 2, 3 or 4 bytes of 24, 12, 8 or 6 bits each respectively. A parity bit is also included with each word. In a computer system as shown (Fig. 3), when a peripheral device 17 wishes either to transfer information into a magnetic core memory 11 or to receive information from the memory a request signal is sent by way of a buffer unit 16 and lines 149 to an automatic program interrupt unit 15 which grants requests according to an order of priority. When a request is granted, a response address corresponding to the requesting device is issued by the unit 15 to a transfer matrix 150 comprising a diode read only store (Fig. 4, not shown). If the requesting device is one for which a control word is provided, the matrix 150 informs the arithmetic and control unit 10 that such a request has been granted and the direction of transfer involved and further transmits signals to the peripheral input/ output buffer 16 identifying the channel and device effected. If the requesting device is one for which a control word is not provided, then transfer is effected in known manner (not described) under control of an instruction or a sub-routine. The unit 15 also transmits said response address to the memory 11 to cause the control word (or instruction as the case may be) associated with the granted request to be transferred from memory into the arithmetic and control unit 10. Each control word (Fig. 2) comprises an N-field indicating in 1's complement form the number of words to be transferred, a C-field indicating the number of bytes of the current word still to be transferred, a P-field indicating in 2's complement form the number of bytes per word and a Y-field indicating the address in memory 11 to which the information is to be transferred to or from. Unit 10 updates the control word (fields N, C and/or Y depending on whether a word has just been completed or not), returns the updated word to memory 11, reads the information word identified by the Y-field of the control word from memory 11 into the unit 10, effects the transfer of one byte between control unit 10 and the peripheral device and returns the information word to memory 11, register 100 of the control unit 10 being constructed as a shift register for selective shifting of data as successive bytes are assembled under the control of a counter responsive to the contents of the P. The peripheral units connected through multiplexer 18 to the input/output bus may comprise card or tape readers or punches or control units associated with a process to be controlled in real-time by the computer system. Other peripheral devices which may be connected to the memory multiplexer 12 and to interrupt unit 15 may comprise data links, printers and magnetic tape or disc units. Reference is made to selectively stepping the program sequence counter by one or two units (for jumps).