Patent GB-987444-A (GB)
Title: Magnetic memory
IPC: H04J3/20
Filed: 1961-12-20
Abstract: 987,444. Automatic exchange systems; circuits employing bi-stable magnetic elements. TELEFONAKTIEBOLAGET L. M. ERICSSON. Dec. 20, 1961 [Dec. 20, 1960], No. 45712/61. Headings H3B and H4K. Subscriber-to-highway and inter-highway gates in a time-division multiplex electronic exchange are controlled to effect a connection in a particular time slot by information identifying the gates stored in a row of a magnetic cored matrix the rows of which are read out cyclically and correspond with the time slots of the exchange cycle. Each subscriber is connected to separate go and return highways serving 36 subscribers with a cycle of 20 time slots. There are 12 highway pairs and for each pair there are 12 pairs of inter-highway gates connecting each go and return highway of the pair to the return and go highways, respectively, of all other pairs. As shown in the block diagram of Fig. 2 the gates and highways are located in the network TK. A scanner LA provides the marker M with the identity of calling lines and a connection is set up to a register REG which gives the marker the identity of the wanted line. If the wanted line is available and does not belong to the same group as the calling line the marker finds an idle two-out-of-four codes which for the plane MTI1 selects one subscriber to-go-highway gate and for the plane MTU1 selects one subscriberto-return-highway gate. Each two-out-of-four code is converted by translators ORy, ORx, to one-out-of-six marking on each co-ordinate of the 6 x 6 array of subscribers gates associated with each highway. Rows K9 to K14 in plane MTI1 store a two-out-of-six code which is translated to a one-out-of-twelve marking by circuit ORF1 to operate the selected interhighway gate. To connect subscribers served by different highway pairs two pairs of memory planes will be involved to control connections in both groups simultaneously. Rows K9 to K14 in plane MTU1 store a two-out-of-six code which is translated to a one-out-of four marking in a signalling circuit SK to control gates SK which provide exchange tones when necessary. The operation of subscriber-to-highway gates is shown in Fig. 4 where the translators ORx and ORy are simple AND gate arrays and each cross-point of the 6 Î 6 array selectively connects a transformer primary TR to switch transistors T1 and T2 in the resonant transfer gate IDK between one of the subscriber's wires a and the highway F. As shown in Fig. 7, separate markers are employed to control the odd and even time slot in which the subscribers may be connected over the highways and writes the identity of the subscribers in the rows of a store KM corresponding to this time slot. If the wanted line is served by the same go and return highways as the calling line a time slot is seized for each highway and two rows of the store KM will be involved. The rows of KM are read out cyclically by a distributer PD and repeatedly open the gates in the network TK necessary to make the connections. As shown in Fig. 3, two pairs of highways La1, Lb1, and La2, Lb2, have their subscriber-to-highway gates arranged in 6 x 6 matrices F1 and F2. The ten other pairs of highways are not illustrated. The inter-highway gates are shown at FK in a 12 x 12 matrix each row of which is common to one highway pair. The subscriberto-highway and inter-highway gates associated with each highway pair are served by two planes of the magnetic cored matrix store KM, the planes serving the highway pair La1, Lb1, being shown. Each matrix plane has 14 columns and 22 rows. The rows with cores Mka serve to write into the matrix as instructed by the marker, the rows with cores Mkb serve to read-out to the marker, while the remaining 20 rows each correspond to a time-slot determined by the cyclic read/write pulses ppl to pp20. Rows K1 to K8 contain two rows of a matrix plane. The cores MKa and MKb which form the so-called active part of the matrix plane are consequently provided in duplicate. Also included in the active part of the plane are cores MKr which effect erasure in the storage rows, and cores MKk which provide compensation of disturbances in the cores MKb. Fig. 6 shows how the active parts of the 24 matrix planes are selected for access by the marker. The active parts are collected into six groups MG1 to MG6 and in Fig. 6 only one row of cores is shown from any one matrix plane and it is to be noted that the columns of Fig. 6 correspond to rows of Fig. 7 and vice versa. Each group of active parts has individual row wires a1 to a4 (shown as columns in Fig. 6) and has common group wires d1 to d6, and f1 to f6. A wire c is common to the rows of all groups as is a bias wire e. All groups have column wires (shown as rows in Fig. 6) b1 to b14 in common. The cores MKa are employed to write codes from the marker into a storage row and they are normally held reset by additive blocking currents in the a, b and c wires. Inhibition of current on chosen a and c wires, a write pulse on a chosen f wire, and inhibition on a required pattern of b wires, causes the pattern to be set up on a particular row of write cores MKa. The pattern is cleared within the same time slot by a single pulse on the d wire which returns all cores to the set condition. When the write cores are set up by the marker they generate a pulse in the sensing wires s, seen in the columns of Fig. 7, and cause bi-stable circuits W in sensing circuits AK to switch from state 0 to state 1. In the one state, circuits W connect a re-write pulse to the column wires w so that, in coincidence with the write portion of the read/ write pulse pp for the time slot and associated row in question, the pattern from the marker is written into the storage portion of the matrix involving cores MKm. During subsequent cycles, the row storing the pattern is read out to control the highway gating network and causes automatic re-write by switching the bi-stable circuits W. To erase a pattern the marker inhibits current in an a wire and an h wire to select the correct active matrix portion in the groups MG1 to MG6 and switches an erase core MKr so selected by a pulse on the wire f. Output on the erase core winding r causes the bi-stable circuits W to be disconnected from the sense wires s and to be reset to the 0 state thereby inhibiting automatic re-write and clearing the storage row associated with the time slot of the connection to be released. Erasure may be effected by cores associated with each column that operate in the same manner as the write cores MKg except that the output is operative to reset the storage cores MKm. The sensing cores MKb are selected from the active portion groups MG1 to MG6 in the same manner as the write cores MKa but do not involve the common wire c. They do, however, involve the re-write wires w so that when subjected to a pulse on the wire d while the storage cores MKm are active the sense cores are set. A subsequent read pulse from the marker on wire f resets the cores to provide output on the b wires which supply the marker with the storage row code. Since re-write pulses on wires w disturb the sense cores and pulse the wires b residually, compensation is provided by the cores MKk which are connected in the reverse manner to the sense cores so as to provide an equal and opposite disturbance in the b wires when the w wires are pulsed.