Patent GB-1502184-A (GB)
Title: Automatic flight control systems
IPC: G05D1/00
Filed: 1975-06-20
Abstract: 1502184 Monitoring computer operation in flight control systems SPERRY RAND CORP 20 June 1975 [5 July 1974] 26286/75 Heading G4A [Also in Divisions G2-G3] An automatic flight control system for an aircraft having aerodynamic control surfaces 35, Fig. 1, and associated servos 34 coupled therewith for positioning the control surfaces, and having sensors 10-12 for providing sensor signals in accordance with flight conditions experienced by the aircraft, comprises a digital computer 24 having input means 13, 16, 17 responsive in operation to the sensor signals, a program memory 52, Fig. 2, a repertoire of instructions operative in the flight control system, and output means 26, 32, 33 connectible to the servos 34 for applying control surface command signals thereto. A program stored in the program memory 52 comprises a plurality of first program segments for sequential execution by the computer, via a program counter 85, for controlling the computer to sequentially perform a plurality of tasks to provide the control surface command signals to the output means, a plurality of second program segments respectively associated with the first program segments for setting task completion indicia in accordance with the completion of the respective tasks, and a third program segment for testing the indicia for said set state thereby testing the indicia for completion of the tasks. The program utilizes all of the instructions of the repertoire within at least one of the sets: first program segments, second program segments, third program segment, so as to cause at least one of the indicia to remain unset when an instruction is not executed properly. The program further includes a failure program segment 62 that is entered when at least one of the indicia remains unset, the failure program segment including instructions for stopping program execution. A fourth program segment 63 generates a dynamically varying validity pattern by causing a signal at the output means to assume one level during an execution of the program and a different level during a subsequent execution thereof. The program is repeatedly executed, a detector 43 coupled to the output means receiving the validity pattern signal and detecting whether this signal is in an abnormal state during a time interval in which repeated executions of the program would normally provide the dynamically varying valaditiy pattern, and providing a failure signal to a block 45, to shut down the system, in accordance therewith. The system, as shown, may comprise one channel, in which case the system is "fail passive", i.e. shutting down is complete, or may comprise two channels each identical to that shown, in which case the system is "fail operative"; shutting down of one channel leaves the other operating alone. Each channel may be further divided into subchannels A, B, the sensors 10, 11 being respectively assigned thereto, and the tasks also divided into subchannel A and subchannel B tasks, represented as respective blocks 69-72 and 73-76 in the program memory 52. Further tasks may require the entire channel and are designated as "single-channel" tasks, and represented by blocks 65-68 in program memory 52. A task list word stored in a data memory 53 may have particular bit positions set to 1 if the corresponding task is to be performed, the task completion indicia constituting respective bit positions of a further word stored in data memory 53. The contents of the two words are combined bit-by-bit to determine which tasks have been successfully completed, the result of the combining operation being 0 in successful cases. Not all of the tasks need be performed in each execution of the program; this is achieved by setting the required bit positions of the task list word to 0. Task list words are formed for each of the subchannel A, B tasks and for the single channel tasks. The program segments may be arranged as an executive program with subroutines 77-80 and corresponding jump instructions, the transfer addresses being derived using the instructions of the repertoire to cause the program to follow an abnormal path upon failure of any one of the so utilized instructions, thereby causing at least one of the indicia to remain unset. The repertoire may include an instruction to wait for an interrupt, in a block 64, the interrupts being generated by a real-time clock at intervals of, e.g., 50 milliseconds. The processed signals from sensors A, B may be stored in dual data memory banks, the contents of the memory banks being compared to test correct operation of the memory banks. The input means of the digital computer 24 comprises multiplexers 13, 17 and an A/D converter 16, whereas the output means comprises a multiplexer 26 and a plurality of D/A converters 32. The outputof D/A converters 32 is fed back to the multiplexer 13 for "end-around" checking in the usual manner. The validity pattern may be a square wave, the abnormal state thereof being either a static state or an incorrect dynamic state, e.g. noise. An example is discussed, in relation to the 1819 computer, of a calculation of pitch increment in terms of bank angle, weight, and flap deflection.