baber/WOPTO huggingface dataset:
Patent TW-475191-B (TW)
Title: Control and monitoring device for the opening/closing of electric operating elements
Inventor: CEREDA CARLO
IPC: H01H9/16
Filed: 1999-11-11
Granted: 2002-02-01
Abstract: Control and monitoring device for actuating means for the opening/closing of operating elements, featuring a mobile contact and a fixed contact, comprising measuring means for the current and voltage of one or more electrical phases and a processing unit equipped with means for performing the following functions: receiving in input from said measuring means signals indicating a succession of moments measured in which the voltage and/or current assumes a desired value; iteratively executing a calculation of the period of succession of moments measured; executing a predictive calculation of a succession of moments in which the current and/or voltage assumes said desired value; calculating, following an operating command, the time window for the opening/closing of said electric operating elements; sending a command to said actuator means on the basis of the time window determined and of the operating times of said electric operating elements; characterised by the fact that said processing unit: executes a first algorithm envisaging normal network operating conditions; executes a second algorithm envisaging non-normal operation of the network.
Patent TW-432791-B (TW)
Title: Apparatus and method for converting differential voltage to fully balanced currents
Inventor: ZDZISLAW CZARNUL
IPC: H04L25/08
Filed: 1999-11-06
Granted: 2001-05-01
Abstract: The apparatus for converting a differential input voltage to two fully balanced output currents is achieved by providing a common mode control circuit of a simplified circuit construction to an operational transconductance amplifier. The apparatus includes an operational transconductance amplifier that is comprised of an OTA input section for converting two input voltages of the differential input voltage to a pair of interim output currents and an OTA output section for converting the interim output currents to the output currents, and a common mode controlling circuit for providing a control voltage to the OTA. The common mode control circuit is comprised of a substantially same circuit construction as the OTA output section and generates two output control currents based on the interim output currents from the OTA input section and the two output control currents from the common mode control circuit are summed and kept to be substantially zero in order to control the output currents from the OTA output section fully balanced.
Patent TW-428318-B (TW)
Title: The manufacturing method of the bit line of flash memory
Inventor: LI DUNG-SHING
IPC: H01L27/115
Filed: 1999-12-16
Granted: 2001-04-01
Abstract: A manufacturing method of the bit line of flash memory, wherein a SOI substrate is provided which comprises a buried oxide layer and the silicon layer on the buried oxide layer followed by forming a patterned hardmask layer on the silicon layer, remove the exposed silicon layer by using the hardmask layer as the mask, and form a bit line opening till the depth of the buried oxide layer of the portion under the silicon layer. Then cover a conformal lightly doped polysilicon layer on the substrate followed by covering a heavily doped polysilicon layer on the substrate, and fill the opening of the bitline. Then remove part of the lightly doped polysilicon layer and heavily doped polysilicon layer till the surface of the silicon layer to form a buried bitline, and then remove the hardmask layer.
Patent TW-528998-B (TW)
Title: Liquid crystal display apparatus and electronic device for providing control signal to liquid crystal display apparatus
Inventor: SAKAMOTO ATSUSHI
IPC: G09G3/36
Filed: 1999-12-24
Granted: 2003-04-21
Abstract: A liquid crystal display apparatus includes a liquid crystal display device; a light source for illuminating the liquid crystal display device; a LCD device driving circuit for providing a driving voltage to the liquid crystal display device based on a display data signal and a plurality of liquid crystal driving signals including a display data latch signal; a dividing circuit for dividing a frequency of the display data latch signal by a factor of N so as to obtain a period which is N times as large as that of the display data latch signal, where N is an integer greater than zero; a duty control circuit for changing an ON duty ratio of the frequency-divided signal by using the frequency-divided signal as a reference frequency; and a light source driving circuit for turning the light source ON/OFF based on a signal from the duty control circuit having the ON duty ratio set in the duty control circuit, wherein, where a driving duty is (1/D), and a remainder of D divided by the integer N is A, each of the integer N and the value D is set to an integer greater than zero which satisfies the following expression: -1 ≤ {(N/A)-2} ≤ 1.
Patent TW-497275-B (TW)
Title: Composite light-emitting device, semiconductor light-emitting unit and method for fabricating the unit
Inventor: MAEDA TOSHIHIDE
IPC: H01L33/38
Filed: 2000-01-11
Granted: 2002-08-01
Abstract: A composite light-emitting device according to the present invention includes a light-emitting element having a transparent substrate and a multilayer structure formed on the substrate. The multilayer structure includes first and second semiconductor layers of first and second conductivity types, respectively. The device further includes a submount member for mounting the light-emitting element thereon. The principal surface of the submount member faces the multilayer structure. The submount member is electrically connected to the light-emitting element. The light-emitting element is covered with a wavelength-shifting resin member. The resin member is provided on the principal surface of the submount member and contains a photofluorescent or filtering compound. The photofluorescent compound shifts the wavelength of radiation that has been emitted from the light-emitting element, while the filtering compound partially absorbs the radiation.
Patent TW-475041-B (TW)
Title: Device for immobilising an element of a kinematic system
Inventor: CHICHERY LAURENT
IPC: F16D71/00
Filed: 2000-01-19
Granted: 2002-02-01
Abstract: The invention consists in a device for immobilising an element (1) of a kinematic system comprising a member (11) having on its periphery upstanding parts and recessed parts of complementary profile to upstanding and recessed parts of the element to be immobilised and mounted at the end of an arm (14), a unit for moving the member (11) between a passive position disengaged from the element (1) to be immobilised and an active position in which the respective upstanding and recessed parts of said element (1) and said member interpenetrate to immobilise the element, means for indexing the position of the element (1) for placing the upstanding parts opposite the recessed parts of said element (1) and said member (11), respectively, and means for detecting the position of the arm (14) carrying said member (11). The invention applies to immobilising a toothed ring of a steelmaking converter ladle.
Patent TW-487731-B (TW)
Title: Preparation of multifunction lubricant additives
Inventor: YE MAU-RUNG
IPC: C10M129/68
Filed: 2000-02-14
Granted: 2002-05-21
Abstract: Multifunction lubricant additives (MFLA) consist of three major functional groups. They are phosphoric ester with resisting extreme pressure ability, amines with clean effect, and either phenol or aromatic amine with antioxidative ability. Their utilities not only promote tribological effect of mechanical operation, but also avoid interaction between various additives. In this invention, We have modified the synthetic ways of MFLA to improve the resisting extreme pressure ability.
Patent TW-434782-B (TW)
Title: Method for manufacturing capacitors having selective hemispherical grained polysilicon
Inventor: CHEN JUNG-YI
IPC: H01L21/70
Filed: 2000-02-18
Granted: 2001-05-16
Abstract: There is disclosed a method for manufacturing capacitors. The bottom electrode of the capacitor has selective hemispherical grained polysilicon (S-HSG). The selective hemispherical grained polysilicon is formed by an ex-situ process. In accordance with the present method, an ion implantation step is added after the S-HSG generation process to replace the conventional wet cleaning step. Because such a cleaning step is cancelled, the produced residuals are no longer existed and the generation of structural defects is avoided. The insertion of ion implantation process is used to compensate the insufficient doping of the in-diffusion process. In the embodiment, the ion implantation and in-diffusion is combined to achieve a complete doping effect, so that the structural body still has a good capacitor quality even though the cleaning process (doping preprocess) is cancelled.
Patent TW-498553-B (TW)
Title: Active matrix substrate, electro-optical apparatus and method for producing active matrix substrate
Inventor: TAKENAKA SATOSHI
IPC: H01L21/84
Filed: 2000-02-29
Granted: 2002-08-11
Abstract: The purpose of the present invention is to provide an active matrix substrate to inspect MIS transistor easily and correctly, an electro-optical apparatus using the same, and method for producing the active matrix substrate. The solution is: on this active matrix substrate, film quality inspection areas 80 with approximately 1 mm<SP>2</SP> area are formed at the parts where an image display area, a scanning line driving circuit, a data line driving circuit, a signal wiring, etc., are not formed. In these film quality inspection areas 80, film quality inspection semiconductor film 1c (silicon film) are formed which are of the same layers as the highly doped source and drain domain of a TFT 50 and is doped with the same dopant with the same concentration. Since film quality inspection insulating film 1c is exposed from an opening part 8c of each interlayer insulating film 4, 71, 72, the film analysis can be proceeded immediately.
Patent TW-465074-B (TW)
Title: Semiconductor integrated circuit device
Inventor: MIZUNO HIROYUKI
IPC: G11C11/406
Filed: 2000-03-22
Granted: 2001-11-21
Abstract: This invention introduces a low power semiconductor integrated circuit device. A semiconductor integrated circuit device comprises a memory that includes memory cells and circuit blocks, power supply switch means, and a refresh controller and has first and second operating modes, wherein the refresh controller refreshes the memory cell by supplying power to the memory by using the power switching means in the first operation mode, and stops the power supply to at least one circuit block by using the power switching means in the second operation mode so as to set up an operating mode in which transition between the first and second modes are repeated plural times. The power needed is lowered while such a semiconductor integrated circuit device including a memory element with a long refresh cycle is in a standby mode, thereby reducing the overall power of the semiconductor integrated circuit device.
Patent TW-451253-B (TW)
Title: Dielectric barrier discharge lamp light source
Inventor: OKAMOTO MASASHI
IPC: H01J65/00
Filed: 2000-04-24
Granted: 2001-08-21
Abstract: The present invention provides a dielectric barrier discharge lamp light source, which has the output terminals (10, 11) of said power supply device (9), and said electrodes (5, 6) and the connection mechanism (12, 13) of said electrodes (5, 6) and the output terminals (10, 11) of said power supply device (9) to prevent the risk of abnormal discharge in any part of the dielectric barrier discharge lamp light source in a safe and economical way. A dielectric barrier discharge lamp light source device has discharge space (3) filled with discharge gas that emits light through dielectric barrier discharge. The device is provided with a dielectric barrier discharge lamp (1) having a structure in which dielectrics (7, 8) are interposed between at least one of two electrodes (5, 6) to induce a discharge phenomenon in the discharge gas and a power supply device (9) to provide alternating current with high voltages to electrodes (5, 6) of the dielectric barrier discharge lamp (1). Its feature is: the power supply device (9) has abnormal discharge detection circuit (14) to detect abnormal discharge occurring within transformers (81 or 114) in the power supply device (9) or in the section from the secondary side terminal of a transformer to the electrodes (5, 6). The power supply device (9) halts the supply of alternating current with high voltage from the power supply device (9) to the dielectric barrier discharge lamp (1) when abnormal discharge detection circuit (14) detects abnormal discharge. The abnormal discharge detection circuit (14) is characterized by having the ability to detect only abnormal discharge arising from electric behavior of the power supply device (9) without being a detector of special abnormal discharge due to photo-, acoustic, thermal- or chemical matter.
Patent TW-I243672-B (TW)
Title: New use of compounds as antibacterial agents
Inventor: EEK ARNE
IPC: A61K45/06
Filed: 2000-05-19
Granted: 2005-11-21
Abstract: The present invention discloses a new use of NO-releasing NSAIDs, especially NO-releasing NSAIDs of the formula I, or a pharmaceutically acceptable salt or enantiomer thereof, for the manufacture of a medicament for the treatment of bacterial infections, especially caused or mediated by Helicobacter pylori. Disclosed is also the new use of a NO-releasing NSAID in combination with an acid susceptible proton pump inhibitor for the treatment of bacterial infections.
Patent TW-442363-B (TW)
Title: Device and method of the end point detector for the CMP
Inventor: YANG MING-SHENG
IPC: B24B37/04
Filed: 2000-06-12
Granted: 2001-06-23
Abstract: Device and method of the end point detector for the CMP are described below. The first layer material is on the surface of a wafer and the second layer material is beneath the first layer material. The first layer material of a wafer is polished by the CMP device with slurry. The waste slurry obtained from mixing the by-product of the removed first layer material and the slurry has a first color. The first color of waste slurry is monitored on line when the wafer is polished. The end point of the polishing process is defined when the first color of waste slurry disappears.
Patent TW-I235626-B (TW)
Title: Liquid thermosetting resin composition and method for permanently filling holes in printed circuit board by the use thereof
Inventor: TAKAHASHI RIEKO
IPC: C09D171/10
Filed: 2000-07-05
Granted: 2005-07-01
Abstract: A liquid thermosetting resin composition and a method for permanently filling holes in a printed circuit board by the use of the composition are provided. The liquid thermosetting resin composition comprises (A) an epoxy resin assuming a liquid state at room temperature, (B) a phenolic resin assuming a liquid state at room temperature, (C) a curing catalyst, and (D) a filler, wherein the filler (D) contains a spherical filler and a ground filler. Preferably the spherical filler includes a spherical fine filler and a spherical coarse filler. In a method for permanently filling holes in the printed circuit board, the composition is applied to the board so as to fill the holes in the printed circuit board and precured by application of heat. Thereafter, the parts of the precured composition protruding from a surface defining the holes is removed by polishing and then the precured composition is further heated to cause final curing thereof.
Patent TW-469597-B (TW)
Title: Method to produce a vertical semiconductor-transistor component and said vertical semiconductor-transistor component
Inventor: AEUGLE THOMAS
IPC: H01L51/30
Filed: 2000-07-13
Granted: 2001-12-21
Abstract: A vertical semiconductor-transistor component with vertical cylindrical structures (12, 12') formed above the substrate (1) under the utilization of a statistic mask, said cylindrical structures (12, 12') in the bottoms are conductively connected with a 1st common electrical contact (K1), in vertical direction include layer-areas (5A, 6A, 7A; 5A', 6A') of different conductivity, on their surrounding-walls are provided with isolation-layers (13, 13'), where a conductive material (14) is located between the cylindrical structures (12, 12') isolated around the circumference, said conductive material (14) realizes a 2nd electrical contact (K2) of the semiconductor-transistor component, and on the cover-side are conductively contacted with a 3rd common electrical contact (K3).
Patent TW-I241995-B (TW)
Title: semiconductor ceramic and resistance element using the same
Inventor: NABIKA YASUHIRO
IPC: H01C7/02
Filed: 2000-07-24
Granted: 2005-10-21
Abstract: A semiconductor ceramic device comprises a body composed of a semiconductor ceramic having a positive resistance-temperature coefficient primarily composed of barium titanate and electrodes provided on the body, in which the resistance-temperature coefficient is 9%/DEG C or more, resistivity is 3.5 Omega.cm or less, and withstand voltage is 50 V/mm or more. As the semiconductor ceramic forming the body provided in a thermistor having positive resistance-temperature characteristics, a semiconductor ceramic having a positive resistance-temperature coefficient is used, in which the semiconductor ceramic has an average particle diameter of about 7 to 12 mum and comprises barium titanate as a major component and sodium in an amount of about 70 ppm or less on a weight basis.
Patent TW-I236913-B (TW)
Title: Hydrolyzed cellulose granulations of salts of drugs
Inventor: ERKOBONI DAVID F
IPC: A61K9/20
Filed: 2000-09-29
Granted: 2005-08-01
Abstract: The present invention provides a method for preparing a spray-dried, compressible granular formulation for preparing pharmaceutical tablets in which essentially water-insoluble, acidic, amphoteric, and basic pharmaceutically active agents are converted to more water-soluble salts which are granulated with hydrolyzed cellulose, drug-containing slurries, the resulting granulations, capsules containing granulations, and pharmaceutical tablets compressed from such granules. In these formulations there is employed from 1% to 85% by weight of the pharmaceutically active agent and its salt form, from 5% to 99% of hydrolyzed cellulose, based on the dry weight of the granulation, and optionally, conventional granulation and/or tableting additives such as surfactants, disintegrants, and antiadherents/flow aids. Said tablets have significantly increased dissolution of the pharmaceutically active agent at the pH of the gastrointestinal tract in comparison with the unconverted free pharmaceutically active agent.
Patent TW-490614-B (TW)
Title: UART automatic half-duplex direction control with programmable delay
Inventor: LO SUN M
IPC: G06F13/38
Filed: 2000-10-09
Granted: 2002-06-11
Abstract: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.
Patent TW-479168-B (TW)
Title: Device and system for processing data
Inventor: TOMONAGA KAZUHIRO
IPC: G06F9/34
Filed: 2000-10-19
Granted: 2002-03-11
Abstract: A data processor 1 has a normal mode with the narrow access space of a CPU 2 and an advanced mode with the wide access space. Even in the normal mode, a transfer control part 3 enables data transfer control over an address range accessible for the CPU at that time. Even when a program or the like is generated over the limitation of program capacity in respect to the access range of the CPU in the normal mode, by storing the program just for the excess of that limitation in the non-access area of a ROM 6 in the normal mode, the transfer control part can access this program and can transfer it to a RAM 7 and the CPU in the normal mode can access and utilize the program or the like transferred to the RAM.
Patent TW-480405-B (TW)
Title: Multi-computer data synchronous control device and method for parallel port
Inventor: HUANG JIUN-YAU
IPC: G06F13/20
Filed: 2000-10-20
Granted: 2002-03-21
Abstract: The present invention provides a multi-computer data synchronous control device and method for parallel port. When the synchronous server transmits data to a plurality of client apparatuses at the client side via a parallel port, a device composed of a server side parallel port connector, a plurality of client side parallel port connectors, a server side chip circuit, client side chip circuits with a number equal to the plurality of client side parallel port connectors, and a synchronous control chip circuit, makes the data reach each client apparatus synchronously. Furthermore, with the feedback control signal of each client apparatus, the server will start the transmission of next data when all of the client apparatuses response the control signals.
Patent TW-495673-B (TW)
Title: Method and apparatus for transmitting registered data onto PCI bus
Inventor: LIN CHANG-FU
IPC: G06F13/38
Filed: 2000-11-10
Granted: 2002-07-21
Abstract: The present invention provides a method and apparatus for transmitting registered data onto PCI bus. The inventive apparatus and method can reduce the delay time of the output signal, and without greatly increasing the circuit complexity. The apparatus uses a 2R1W data buffer to advance one pulse cycle of the actual AD action for one PCI bus to send out the current phase data and the next phase data, and uses the multiplexer to select the current phase data and the next phase data based on the selection signal. The selection signal is the result by the OR operation for the IRDY# signal and the TRDY# signal. The apparatus uses the flip-flop to drive the output signal from the multiplexer to the PCI bus during the actual AD operation period. Thus, the inventive apparatus cannot only reduce the delay time for the output signal, but also be easy to implement.
Patent TW-498662-B (TW)
Title: Communication method and communication device
Inventor: MATSUMOTO WATARU
IPC: H04M7/00
Filed: 2000-11-20
Granted: 2002-08-11
Abstract: The invention relates to the communication method that conducts data communication among the communication devices connected with forwarding path in multiplexing way using multiple carriers modem method. When the said multiple communication devices in multiplexing connection are concurrently executing data transmission, the specific control device (1) activated as host goes through the communication states of managing and holding forwarding path to realize dramatic decrease of transmission delay and achieve the real-time data communication required for voice, motion picture regeneration and so on.
Patent TW-466585-B (TW)
Title: Exposure system and exposure method
Inventor: YANAGIHARA MASAMITSU
IPC: H01L21/027
Filed: 2000-11-22
Granted: 2001-12-01
Abstract: The present invention provides an exposure system and exposure method capable of minimizing the residual components of errors of linear correction, and realizing higher fineness in upsizing a photosensitive substrate and device. Projection optical systems 12a to 12e of the scanning exposure system which make a mask 10 and the photosensitive substrate 14 to synchronize and scan for exposure in synchronization have an image formation characteristic regulating mechanism 120 for regulating the positions in said scanning direction of the projected images to be projected to the substrate. The nonlinear components of the exposure errors in the scanning direction are determined and are previously registered as the correction values. The pattern exposure is executed while the image formation characteristic regulating mechanism 120 in the scanning direction of the projection optical systems is continuously controlled in accordance with the correction values.