Patent GB-1248829-A (GB)
Title: Digital integrator-synchronizer having low noise susceptibility
IPC: G06G7/186
Filed: 1969-08-25
Abstract: 1,248,829. Integrators and synchronizers. BENDIX CORP. 25 Aug., 1969 [11 Sept., 1968], No. 42196/69. Heading G4G. An integrator synchronizer system includes a disabling device which operates when the input falls below a certain level and thus protects the system from unwanted external stimuli. The system shown comprises a source 2 of D.C. or demodulated signals, a converter 6 providing a pulse output whose frequency is proportional to input amplitude, a pulse counter 8 and a digital-to-analogue converter 10 for providing an analogue output signal. Capacitors 20, 22 and 24 provide noise filters. When operating as a synchronizer, the output is added to the original signal from source 2 in a summing circuit (Fig. 2, not shown). The system also includes a polarity detector 16 feeding a generator 18 of command signals which determine the sense of the count performed by counter 8. According to the invention, the level of the input signal is detected by a circuit 14 which disables converter 6, command generator 18 and counter 8 when the signal falls below a certain minimum. The detector comprises operational amplifiers 80, 82, Fig. 4, connected in the manner shown to the signal source 2 and to +ve and -ve D.C. sources 84, 86 which determine the desired threshold level. When the input signal is zero (e.g. in the " hold " mode with switch 4, Fig. 1, open and switch 4A closed), the amplifiers are at +ve saturation, diodes 88, 90 are reversed biased by D.C. source 92 and the (output) voltage at P is at a high logic level equal to the voltage of source 92. This high level output provides the inhibiting signal. When the input signal exceeds the threshold level in either +ve or -ve direction, one of the amplifiers will switch to -ve saturation and will forward-bias a corresponding diode 88 or 90 thereby reducing the voltage at P to low logic level and removing the inhibiting signal. The converter 6 comprises an operational amplifier 32 and a capacitor 36 which charges to the D.C. level of +ve and -ve D.C. sources 48, 52 at a rate proportional to the amplitude of the input signal. The voltage appearing at the collector 63 of transistor 60 falls to a low logic level and FET 62, the gate of which is connected to collector 63, short circuits the capacitor 36 and causes the voltage at the output 38 of amplifier 32 to fall to zero. Thereupon, transistors 60, 62 are rendered non-conducting and the capacitor begins to charge again. When a high logic level (inhibiting) signal from detector 14 is applied through diode 56 to the base of transistor 60, the transistor is driven to saturation and the gate of FET 62 is clamped to ground. The polarity detector 16 (details in Fig. 5, not shown) consists of an operational amplifier having an inverting input terminal connected to the source 2 and a non-inverting input terminal connected to ground. The output is shunted by a Zener diode. When the input from source 2 is +ve, the output of detector 16 is zero and when the input is - ve, the output is equal to the breakdown voltage of the Zener diode. The command generator (details in Fig. 6, not shown), comprises two gates to which the output of detector 16 is applied respectively directly and through an inverter. The outputs of the gates provide respectively count-up and count-down commands. The inputs of both gates are also connected to the level detector 14 in such a manner that a high level (inhibiting) signal causes an output from both gates, thereby locking the counter.