Patent GB-1451386-A (GB)
Title: Reconfigurable memory structure
IPC: G06F12/06
Filed: 1974-01-02
Abstract: 1451386 Modular memory system HONEYWELL INFORMATION SYSTEMS Inc 2 Jan 1974 [3 Jan 1973] 00094/74 Heading G4A A main core memory system contains 32 memory modules each having 40,000 (in octa notation) locations each storing a 9 bit character. The modules are arranged in four columns each of eight modules with its own independent timing and control circuits so that one module in each column can be simultaneously accessed. Each column of eight modules is divided into two drawers each of four modules with corresponding drawers of timing and control circuits (Fig. 1 not shown) so that all address ending in 0 or 4, i.e. 0, 4, 8, 12, 16, 20, 24, 28 in Fig. 5c are in drawer R, all those ending in 1 or 5 are in drawer S, 2 or 6 in drawer T and 3 or 7 in drawer U. A memory interface determines the amount of memory space available and indicates overflow if more memory space than this is required. A parity check is performed on the data read from each module to determine if the module meets a minimum standard of reliability. The modules are supplied with addresses using a series of comparators and adders (Figs. 2c, 2d). A number defining the maximum number of modules in the system A 0 -A 3  is supplied to a plurality of comparators 210-1a to 210-4a equal in number to the number of modules. Supplied to the first comparator and to the first adder 210-2a is an address number B 0 -B 3  less by 1 than the lowest address, i.e. 1111 for a first address of 0000. If the comparator 210-1a finds inequality a '1' is supplied to the adder 210-2a at input Cn to be added to the address number to form 0000 which is the address of the first module and which is supplied to its respective module select circuit (Fig. 2e not shown) by unit 210-6a and to the amplifier 210-2b and comparator 210-4b of the next module. The second comparator and adder will form an address of 0001 and so on until the maximum number is reached, where equality is achieved and the comparator supplies a '0' to the adder. Each module select circuit (Fig. 2e not shown) compares the number from its respective adder with the four high order address bits for the memory system to set a latch on equality except when the respective adder does not receive a '1' from its comparator. Each module has a module purge latch (Fig. 2f not shown) switched to a '1' when parity checks are not achieved to produce signals M10FL10 to M40FL10 which are supplied to gates feeding the carry input Cn of the respective adders (Figs. 2c, 2d). The signals can also be produced by an operator using a switch on a control panel to remove selected modules for repair or replacement. The gates inhibit the supply of a carry '1' signal to the appropriate amplifier and place a '1' on the output of the appropriate amplifier M10FL30 to M40FL30. This prevents the module latch from being set so the module is not accessed and the next module in the column is provided with the address of the faulty unit since an unincremented address is supplied to the next amplifier and comparator where it is incremented, e.g. in Fig. 5c if module 12 with address 0011 is faulty the address 0011 is produced by the next amplifier in the chain so module 16 now has address 0011, module 20 has address 0100 &c. The modules in the other columns are unaffected. The memory may be provided with a spare module in each column so that data is not lost if one module in each column is found to be faulty.