Patent GB-1069629-A (GB)
Title: Telephone system for transmitting call address information
IPC: H04L5/06
Filed: 1963-12-19
Abstract: 1,069,629. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Dec. 19, 1963 [Dec. 28, 1962], No. 50127/63. Heading H4K. In a signalling system for transmitting call addresses over a telephone trunk circuit the dialled digits are stored in a sender at the originating end of the circuit, the stored digits are sampled and formed into a continuous serial binary pulse train which is applied to a frequency shift modulator for transmission over the circuit, at the receiving end of the circuit the signals are demodulated and applied to a decoder which allots successive portions of the pulse train representing individual dialled digits to appropriate storage locations in the register. The invention may be used with the multichannel data transmission system described in Specification 1,069,628. Dialled digit encoder, Fig. 2.-At the commencement of operation sender 13 delivers a pulse on line SP and gates the output of oscillator 27 to the clock synchronizer 28 and clock 29. The clock comprises a four-stage binary counter having feedback to make the counting cycle twelve rather than sixteen. The clock synchronizer on the receipt of the SP. pulse sets the clock counter to its zero position and the attainment of this position results in a signal on line ADV which, applied to the sender 13 steps it to the condition to send the first character which is a start digit (KP digit) comprising marks in all positions except position five and this character will appear, in parallel form, on leads 22 from the sender. The clock counter 29 has each stage's output connected via a matrix to 24, 25 and 26 so that gates 24 and 25 sequentially connect each of their six inputs to one of the inputs of gate 26 and gate 26 alternately presents the outputs of gates 24 and 25 to the oscillator modulator 30, thus the KP digit appearing in parallel on leads 22 is fed serially to the modulator 30. Whilst the KP digit is transmitted the first dialled digit is set up on leads 23 in response to the second ADV pulse, and when the KP digit has been transmitted gate 26 operates and connects the output of gates 25 to the modulator whilst, in response to a further ADV pulse, the second dialled digit is set up on lines 22. Thus the complete dialling sequence is transmitted followed by a stop signal of a predetermined form set up by the sender. The serial digital signal fed to the modulator 30 is converted to a frequency shift signal, e.g. Œ 100 cycles about an 1170 c.p.s. centre frequency and this is applied via a filter and hybrid network 32. Error detection.-At the receiver, error detection circuits are provided and if an error is recognized a tone, ;which is present all the time digits are being transmitted but is normally switched off when the stop pulse is received, is received over the line 33 at the transmitter after the stop pulse has been transmitted, and this tone, selected by filter 34 and squared in rectifier trigger 35, is applied to the sender and transmission of the dial sequence is repeated. Dialled digit receiver and decoder, Fig. 3.-The frequency shift signal from the line 55 is applied, via hybrid 40, to a limiter discriminator 43 to obtain the serial chain of pulses representing the dialled digits. The pulses shaped in slicer 44 are applied via amplifier 45 to a start detector 47 which comprises au integrator circuit which responds to the unique characteristic of the start (KP) digit, i.e. four consecutive marks, to produce pulse to initiate the operation of a clock pulse generator in synchronizer 48, the clock pulses being synchronized with the centre of each received bit interval. The clock pulses are fed to a timing source 50 which comprises a chain of four binary counters with feedback to determine the counting cycle as twelve, the outputs of the counting stages are combined in a matrix and the outputs of the matrix operate gates in the odd and even allotors so that the incoming serial bits are allocated to the correct one of the leads of the lead groups 53 and 54 at the input to the register. Odd-even sampler 49 allots the groups of digits alternately to the appropriate odd or even allotter and pulses from the timing source 50 at the end of each digit group are applied over lead ADV to cause the registration of the appropriate digit. At the end of the complete dialling sequence the stop digit ST is received and recognized in the register and an output from the register stops the operation of tone generator 41 which, while in operation, is used as described above as an indication to the transmitter that the receiver is ready to receive the dialling signals. The error detector 46 comprises a two-stage binary counter which is reset at the end of each digit group by the timing source and is fed on its counting input with the incoming dialling bits. Each digit group should contain two and only two bits and if the count is not satisfactory, i.e. other than two bits counted, at the end of a group a signal appears on the ER line to the register and the tone generator is maintained in operation until a second transmission has been received.