Patent JP-S56132041-A (JP)
Title: Switchable free running scrumbler and descrumbler
Inventor: YOOZEFU DEEMAA
IPC: H04L25/49
Filed: 1981-02-20
Abstract: 1. A switchable, free running scrambler/descrambler arrangement having a multi-stage clock pulse controlled shift register (S1', S11') in which the outputs of the sixth (S6') and the seventh (S7') stages are connected to the inputs of a first EXCLUSIVE-OR gate (E1') which, together with at least one second (E2) and one third (E3') EXCLUSIVE-OR gate is contained in a first feedback arm, that the outputs of further shift register stages (S8', S11') are respectively connected to an input of a fourth (E4') and a fifth (E5') EXCLUSIVE-OR gate which, together with a following NAND gate (N') and a clock pulse controlled counter (Z') connected to the output of the NAND gate, is contained in a second feedback path, that the multi-stage shift register is preceded by a first additional clock pulse controlled shift register stage (S0') whose output is connected to the input of the second EXCLUSIVE-OR gate (E2') which is arranged in the first feedback path and is additionally connected to the first input (b) of a first change-over switch (U1') whose other input (a) is connected to the output of the third EXCLUSIVE-OR gate (E3') and to the signal output (DA), and that the output of the first change-over switch (U1') is connected to the input of the shift register, whereas the output of the counter (Z') is connected to an input of the second EXCLUSIVE-OR gate (E2') arranged in the first feedback path, characterized in that an eleven-stage shift register (S1' ... S11') is provided, that the output of the first (E1') and the second (E2') EXCLUSIVE-OR gates are each separately connected to the inputs of the third EXCLUSIVE-OR gate (E3'), that an input of the fourth (E4') and the fifth (E5) EXCLUSIVE-OR gates are separately connected to an output of the eighth (S8') and the eleventh (S11') shift register stages, that the output of the fourth EXCLUSIVE-OR gate (E4') is connected to the D-input of a first clock pulse controlled D-flip-flop (D1'), and the output of the fifth EXCLUSIVE-OR gate (E5') is connected to the D-input of a second clock pulse controlled D-flip-flop (D2'), that the Q-outputs of these two D-flip-flop are each separately connected to the inputs of the NAND gate (N'), that a sixth EXCLUSIVE-OR gate (E6') is provided whose inputs are each separately connected to the outputs of the fourth (S4') and the fifth (S5') shift register stages and whose output is connected to the first input of a seventh EXCLUSIVE-OR gate (E7') whose other input is connected to the input (DE') for the signal to be converted and whose output is connected to the D-input of a third D-flip-flop (D3'), that a second change-over switch (U2') is provided whose first input (a) is connected to the Q-output of the third D-flip-flop (D3') and whose other input (b) is connected to the Q-output of a second additional shift register stage (S1') which is connected between the signal input and the first additional shift register stage (S0'), and that the the output of the second change-over switch (U2') is connected to the second inputs of the fourth and fifth EXCLUSIVE-OR gate (E4', E5).