Patent JP-5589224-B2 (JP)
IPC: G01R31/26
Filed: 2009-03-19
Granted: 2014-09-17
Abstract: The test structure for measuring metal oxide semiconductor (MOS) capacity (ST), comprises a first (DT 1) semiconductor device and a second (DT 2) semiconductor device, each comprising MOS transistors, and two complementary metal oxide semiconductor inverters (INV1, INV2), each loading a respective device among the first (DT 1) and the second (DT 2) devices. Gates of the transistors are electrically connected with a first node (n1, n1'), and sources and drains of the transistors are electrically connected with a second node (n2, n2'). The transistors are of same type. The test structure for measuring metal oxide semiconductor (MOS) capacity (ST), comprises a first (DT 1) semiconductor device and a second (DT 2) semiconductor device, each comprising MOS transistors, and two complementary metal oxide semiconductor inverters (INV1, INV2), each loading a respective device among the first (DT 1) and the second (DT 2) devices. Gates of the transistors are electrically connected with a first node (n1, n1'), and sources and drains of the transistors are electrically connected with a second node (n2, n2'). The transistors are of same type, and have same length and width. The surface (S e q u i v) difference between the two devices is non-zero, and expressed as S e q u i v= (L iW i)- (L' iW' i), where L i, W iare the length and width of a transistor T1 of a first device DT 1, and L' i, W' iare the length and width of a transistor T'1 of a second device DT 2. The first device (DT 1) comprises a first transistor (T 1 0) with a first length L and a first width W, and a second transistor (T 2 0) with a second length l and a second width v, where L is greater than l and W is greater than v. The second device (DT 2) comprises a first transistor (T' 1 0) of which the length and width are equal to the first length L and second width v respectively, and a second transistor (T' 2 0) of which the length is equal to the second length l and width is equal to the first width W. The first device (DT 1) further comprises a transistor (T 1 0 0) with a first length l1 and a first width v1, a second transistor (T 2 0 0) with a second length l2 and a second width W, and a third transistor with a third length L and a third width v2, where L is greater than l2 greater than l1 and W greater than v2 greater than v1. The second device (DT 2) further comprises a first transistor (T' 1 0 0) of which the length is equal to the second length l2 and width is equal to the third width v2, a second transistor (T' 2 0 0) of which the length is equal to the first length l1 and width is equal to the second width W, and a third transistor (T' 3 0 0) of which the length is equal to the third length L and the width is equal to the first width v1. A first connection structure is arranged in the device for connecting the first node to a first test plot (p1, p1'), and a second connection structure is arranged for connecting the second node to a second test plot (p2, p2'). The first connection structure and the second connection structures are identical for both devices. The P-type transistors of the two inverters receive a common control signal (V p) and the N-type transistors of two inverters receive a common control signal (V n). The control signals of P and N transistors are of non-overlapping type. The two inverters are made close to each other at a distance of less than 1000 mu m. An independent claim is included for a process for making a test structure for measuring MOS capacity.