Patent GB-1238360-A (GB)
IPC: H01L21/764
Filed: 1968-11-05
Abstract: 1,238,360. Igfets. HITACHI Ltd. 5 Nov., 1968 [13 Nov., 1967 (3); 15 Nov., 1967 (2)], No. 52317/68. Heading H1K. [Also in Division H3] In an IGFET the maximum gate voltage of which is clamped by an integrated parallel connected diode to protect the gate insulation from breakdown provision is made for preventing bipolar transistor action between one zone of the diode and the drain of the IGFET. Where the device is used in a half bit dynamic shift register such transistor action, which might occur due to noise signals forward biasing the protective diode, has the effect of imposing a lower limit on the operating frequency. It is avoided or reduced to a tolerable level by one or more of the following methods: (1) Connecting an external auxiliary protective diode across the built-in diode, the auxiliary diode having either a lower forward threshold voltage or a similar threshold voltage but a steeper I-V characteristic than the built-in diode so that most of the noise signal is diverted through it. In this way injection from the built-in diode is minimized. Since the noise is normally of high frequency a similar shunting effect can be achieved by a capacitor. (2) Disposing a high impedance between the source of noise voltage and the common point of the IGFET gate and protective diode. This ensures that only a small fraction of the noise voltage appears across the diode. The impedance may be resistor or a plurality of rectifier diodes poled oppositely to the protective diode. (3) Applying a fixed reverse bias to the protective diode greater than the positive noise voltages, thus preventing the diode from becoming injecting. The bias which must be less than the difference between the conducting threshold voltage for the channel and the noise voltage amplitude, may be derived from a potential divider in the output circuit of a transistorinverter through which clock pulses are applied to the gate of the IGFET, or from the common point of a resistor and a voltage source or Zener diode in the same location. (4) Electrically isolating the built-in diode from the substrate and connecting it to the IGFET gate externally by a metal connection. Isolation is obtained in one example by interposing a diffused P-type region between the N region of the diode and the N substrate of the IGFET, the P region preferably being negatively biased with respect to the substrate. In other examples the diode zones are isolated from the substrate by a layer of insulation or an air gap. (5) Disposing an auxiliary region of the same conductivity type as the injecting region of the protective diode in the direct path between it and the drain of the IGFET to intercept injected minority carriers or divert them into a highly doped region where they rapidly recombine. This is most effective when the junction between the auxiliary region and the substrate is reverse biased. Specific physical structures embodying the arrangements referred to in (4) and (5) above and the conventional diffusion and deposition techniques by which they are made are described in the Specification with reference to Figs. 21a-21e, 25a and 26a and 26b (not shown).