Patent GB-1104064-A (GB)
Title: Magnetic access switches
Inventor: BLAHUT DONALD EDGAR
IPC: H03K17/84
Filed: 1965-07-20
Abstract: 1,104,064. Magnetic data storage apparatus. WESTERN ELECTRIC CO. Inc. 20 July, 1965 [20 July, 1964], No. 30742/65. Heading H3B. In a multilocation memory access switch each location of the switch comprises a different pair of bi-stable magnetic flux circuits which are driven in such a manner that flux is switched in either both or one flux circuit to provide different amplitude pulses in access means for a memory. In the arrangement of Fig. 1 a two-core-per-bit piggy-back waffle iron memory M and a two-core-per-location waffle iron access switch AS share a common low reluctance baseplate 11 having posts protruding therefrom. Juxtaposed with the posts of the memory are films f1 and f2 of high and low coercive force respectively and with the two columns of the access switch AS a film f of the same coercive force as f1. Two-core-per-bit organization is realized through three adjacent posts, the portion of the base-plate therebetween and the overlayer therebetween and similarly each location of the access switch is formed by three adjacent posts, overlay and base-plate. Word conductors W1-W4 selectively energized by the access switch AS and digit conductors d1 to d7 energized by positive or negative pulses depending upon the digit to be stored are arranged as shown. In operation a positive prime pulse is applied to conductor XI at time t 1 , Fig. 5, so as to reverse the flux in one of the cores C2 of each location BL1L and BL2L ,Figs. 2, 3, 4 (not shown), initially the flux being in the same direction in the cores of each location. At tune t 2  a negative drive pulse is applied to XI to reverse the flux in cores C1, C2 of BL1L and BL2L and thereby induce a large clear positive pulse W + in the word conductors W1, W2. Positive pulses Y1, Y2 are then applied at times t 3 , t 4  to reverse the flux in cores C1 of the locations BL1L, BL2L and so produce negative write pulses W- in the word conductors W1, W2. At time t 5  a positive prime pulse is applied to conductor XI to return the flux pattern of cores C1, C2 to that before the application of negative pulse XI and then pulses Y1 and Y2 are applied in sequence at times t 6 , t 7  to reverse the flux in cores C2 and induce a read-out pulse Wr in the conductors W1, W2. The Wr pulse is of an amplitude to reverse flux only in the low coercive overlay of the memory, which is changed back again after the removal of the read pulse by the flux in the high coercive force overlay thereby providing non-destructive read-out. In order to write information into the memory positive or negative digit pulses are applied to the appropriate digit conductors d1 to d7 coincident with the W-pulses depending on whether the information to be stored is a " 1 " or " 0." Figs. 6a-6d (not shown) show the pertinent flux patterns in the cores C1, C2 of the two-core-per bit locations BL1 &c. of the memory for writing and reading a " 1" with a "0" stored previously, writing and reading a " 1 " with a " 1 " stored previously, writing and reading a " 0 " with a " 0 " stored previously and writing and reading a " 0 " with a " 1 " stored previously.