Patent GB-841685-A (GB)
Title: Magnetic core flip-flop
IPC: H03K17/82
Filed: 1956-08-30
Abstract: 841,685. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 30, 1956 [Sept. 1, 1955], No. 26499/56. Class 40 (9). Two magnetic cores are used as a flip-flop which gates sampling pulses through a " 1 "  output or a " 0 " output according to the setting. When core 11 returns to state Br after saturation, by a " 1 " set pulse (Fig. 4), in winding 14, sampling pulses (c) in winding 13 produce " 1 " output pulses (d) in winding 15 in the non-destructive manner described in Specification 789,668. If the flip-flop is then set to " 0 " by a " 0 " set pulse in winding 14 of core 10, an inhibiting pulse in winding 12 of core 11 returns the core to point Bt in the hysteresis loop. Further inhibiting pulses leave the core in state Bt after each pulse. In this condition, a sampling pulse in winding 13 does not produce local saturation and no output pulse is induced in winding 15. With position-setting pulses the cores 11, 10 are in either of two conditions +Br, +Bt or +Bt, +Br. With negative setting pulses the cores are in condition - Br, - Bt or - Bt, - Br. Specification 841,426 also is referred to. 841,836. Automatic exchange systems. AUTOMATIC ELECTRIC LABORATORIES Inc. Oct. 29, 1956 [Nov. 23, 1955], No. 32992/56. Class 40 (4). In a 100-line exchange, ten finder-connector links are allotted different periods of 10 microsees. in the 100-microsec. cycle of a time division multiplex system. Each link comprises ferrite core shift registers. Tens and units registers in a link line-finder are stepped by pulses allotted to the link, until the calling line is found and registers in a link connector are stepped by the dialled impulses. The shift registers are controlled by equipment common to all links. This common equipment may be regarded as a finder and a connector common to all the links, the equipment being operated by each link in turn during a multiplex cycle. The shift registers store the identities of the lines to which the corresponding links are connected. An allotter ensures that the links are used in a fixed order. A sequence switch in each link conditions the link for successive operations as a call progresses. Recirculating delay lines, magnetic drums and ferro-electric arrangements may be used instead of ferrite cores. Normally conducting and normally non-conducting transistors are marked respectively by dots and rings. In PNP and NPN transistors the emitter bears an arrow pointing respectively towards and away from the base. Line circuit of Station No. 11, Fig. 1.-Normally, the point 13 is at negative battery potential ( - 48 v.) and is unaffected by ground pulses on finder leads CT1, CUT. Rectifier 27 is normally short-circuited through rectifiers 25, 26. When the loop is closed at 5, the potential at 13 becomes more positive and coincident scanning pulses on leads CT1, CU1 are repeated by transistors TR3, TR4 as negative pulses on lead C to the allotted link 400, Fig. 4, which is marked by a negative marking potential on allotter lead B<SP>1</SP> and a negative link marking pulse on terminal PN1. A dialled impulse is repeated to the link 400 as a break in the train of pulses on lead C. If the station makes the call, speech is transmitted both ways over repeater 50 and lead L, the pulses being gated by rectifiers 60, 62 under the control of transistor TR7 and finder leads LT1, LU1. If the station is called, speech is transmitted over repeater 50 and lead N, the pulses being gated by rectifiers 64, 65 under the control of transistor TR8 and connector leads NT1, NU1. Busy pulses for use on the connector are transmitted over lead CN and are derived from connector leads CT1<SP>1</SP>, CU1<SP>1</SP> by means of transistors TR5, TR6. Ring- ing current is applied to the line to operate ringer 3 when ringing control pulses on lead RC are applied to transformer 40 while rectifiers 35, 36 are scanned by positive pulses. Tube 42, to which 160 v. and 60 v. are applied in successive half-cycles, is broken down by ringing control pulses on RC pulse in the 160 v. halfcycle and extinguishes during the 60 v. halfcycle. Condenser 8 feeds a portion of the ring- ing current past rectifier 45 to provide a ring- back tone. The circuit is marked busy to linefinders by transistors TR1, TR2. Pulses from gate 60 or gate 65 in the transmission circuit trigger transistors TR1, TR2 and clamp point 13 to negative battery after a delay in charging smoothing condenser 53. The transistors are restored for the 10 microsecs. characteristic of the load in each cycle by the pulses transmitted by condenser 54. Line finder, Figs. 2, 2a.-Each of the ten links has a lead DP1-DP10 linked with one row of ferrite cores in each of two 10 x 10 matrix stores, X and U. The two rows identified by lead DPI constitute the tens and units stores of link 400, Fig. 4. A 5-microsec. positive read pulse and a 5-microsec. negative half-write pulse are applied sequentially to lead DPI once every cycle of 100 microsecs. in the 10 microsec. period allotted to the link. The vertical conductors are connected to transistors RT1, RT2, &c. in the tens store and to transistors RU1, RU2, &c. in the units store. These transistors are arranged in blocking oscillator circuits which amplify output pulses on the vertical conductors and repeat them to the line circuits over CT1, CU1, &c. and when appropriate over leads LT1, LU1, &c. Clock pulses from RM1 transmit a negative pulse either on lead WS or on WS1 in accordance with signals received by switching circuit 190. The clock pulses start 3 microsecs. after the start of every read pulse and persist for the remaining 2 miorosecs. of the read pulse. Similarly clock pulses from RM2 and switching circuit 195 transmit negative pulses on either WD or WD1. Consider only the link 400 and the lead DPI and assume that the first core of each of the two rows linked with DPI stores the digit (1), the rest storing (0). The effect of a read pulse and a half-write pulse on DPI is to step the register U one place. The X register steps one place for every ten steps of the U register. As this counting operation proceeds the 100 lines are scanned by pulses on leads CT1, CU1 and on LT1, LU1 if there are link pulses on SPN. The read pulse applied to the first core in U destroys the record of the digit (1) and feeds a negative output pulse to transistor RU1. An amplified pulse induced in winding E3 operates WU2 and re-writes the digit (1) in the second core as the negative marking pulse from switching circuit 195 normally appears on lead WD1. In the tens register X transistor RT1 normally makes WT1 conductive to rewrite the digit in the same core, the marking signal being on lead WS. When transistor RUO conducts in register U at the end of a count of 10, a positive signal from winding Z2 is fed to the base of transistor INH2 in switching circuit 190 and the negative pulse is switched from WS to WS1. The tens register shifts one place. Transistors RT1, WT1 together produce an 8 microsec. scanning pulse on lead LT1 if rectifier 113 is blocked by pulses on SPN from the link 400. The transistors both produce 5 microsec. pulses but WT1 is delayed pending the clock pulse from RM1. Connector, Figs. 3, 3a.-This comprises matrix stores XC, UC and control-circuits arranged in substantially the same manner as in a line-finder. Normally, there are no pulses on leads PNA, TS1 and all the transistors are non-conductive. On seizure of the link, negative pulses on lead PNA in the characteristic link period are repeated by switching circuits 390, 395 as pulses or leads WS1, WD<SP>1</SP>. Only transistors WTO<SP>1</SP>, WUO<SP>1</SP> conduct in response to these pulses in view of the permanent battery connections. The digit (1) is written into the first cores and is repeatedly read and re-written. The tens and unit digits are signalled by negative pulses on leads TS1, US1 and the registers step substantially as in the line-finder. The Allotter, Fig. 5, comprises a ring of flipflops FF3-FF13 individual to the links, transistor 503 being non-conductive when FF3 is set to allot link 400. Lead B<SP>1</SP> is then of negative battery potential. When link 400 is seized, negative battery returned on lead A<SP>1</SP> restores flip-flop FF3 to its unallotted condition and operates FF4 to allot the next link. Sequence switch, Fig. 6.-Pairs of transistors 601, 602 are arranged in a chain so that a conductive condition is stepped from one pair to the next, as in a shift register, by pulses on lead S. Transistors 601, 602 are normally conductive. As the conductive state moves four steps, markings are applied to leads HOLD and ST1 for the duration of the call and are applied successively to leads TS, US, BT and BT with ST2. The switch is restored to normal by pulses on lead R at the end of a call. Link 400 and general operation.-A link is marked with pulses in the characteristic 10 microsecs. of the cycle on terminals PN1-PN9. When the loop is closed at the set 5, the negative pulses are produced on lead C as described. If the link 400 is allotted (negative battery marking on lead B<SP>1</SP>) transistor TR9 repeats negative pulses in the link period marked at PN1 in the AND-1 circuit. A pulse on lead PN operates switching circuits 190, 195 in the finder and locks the finder to the calling line. With a slight delay, trigger pair TR10, TR11 is switched ON, the pulses from TR9 being rectified and smoothed to form a step from which framing pulses (one per 100 microsec. cycle on terminal FP) can operate the trigger pair. Once ON, the trigger pair remains ON until the pulses from TR9 are interrupted as in dialling or release. The potential of lead PRO drops when the link is seized or a transistor TR 17 becomes non-conductive. On dialling, impulses are transmitted as interruptions in the pulse train on lead C and as positive pulses on lead PRO. Digit counting and sequence switch operation.- When l