Patent GB-910211-A (GB)
Title: Improvements in or relating to computers
IPC: G06F7/544
Filed: 1958-11-28
Abstract: 910,211. Digital electric calculating. MINNEAPOLIS-HONEYWELL REGULATOR CO. Nov. 28, 1958 [Dec. 2, 1957], No. 38553/58. Class 106 (1). Two computers are used in the accurate '' real-time " derivation of a function of an input variable, a fast computer 10 preferably an incremental machine in which f<SP>1</SP>(x 0 ) - #x is added to f(xo) to give f(x 1 ) and a slower and more accurate computor 14 which calculates the series expansion of f(x) for samples of the input variable. The output of computer 10 is stored in a delay device 21 at the time a sample is fed to computer 14, and is compared with the output of computer 14, preferably in a subtractor 17, so that a correction can be fed to computer 10. As an example apparatus for the calculation of sin and cos # will be described. The Specification also describes the calculation of e<SP>x</SP>, and log x. In Fig. 4 an input representing an angle # appears on line 140 which is connected through switch 141 to a machine 145 which calculates cos # using the Maclaurin series expansion, through switch 142 to storage delay device 147 and subtracter 153 and through switch 143 to a machine 151 which calculates sin # by means of the series expansion. Switches 141 and 143 operate under the control of timer 207 to sample the input #, while switch 142 operates at the speed of the fast incremental computors. Delay 147 stores the input # for a period equal to the time between operations of switch 142 and feeds to the subtractor 153. Since the other input of subtracter 153 is connected with switch 142 the output on line 156 is ## which is fed to one input of a multiplier 160, and to a negative multiplier 162. Since # (sin #) = cos #. ##, and # (cos #) = - sin # . ##, the sin output 204 of the fast machine is fed to the negative multiplier 162 and the cos output 173 to multiplier 160. Considering only the negative multiplier 162, the output is # (cos #) on line 166 which connects to the cosine accumulator 171 through a switch 167. The accumulator 171 performs the operation cos # + # (cos #) the resultant of which appears on line 173. Line 173 is connected through switch 175 to a storage delay device 177, which stores cos # for a period equal to the time of operation of the slow cos computor 145 and then feeds its contents to subtractor 182, which receives the output of computer 145. The output of subtractor 182 is thus the difference between cos # 0x  as computed by the fast and accurate computors and this is fed through switch 186 to cosine accumulator 171 as a correction to the fast computed cos # 1 . As described the fast computor calculates thirty values per second, the slower computor one value per second. A preferred logical circuit for the slow calculator is shown in Fig. 6 in which the x-input is fed to multipliers 280 to 286 while the output of each multiplier forms the second input of the next multiplier, x being fed on two lines to multiplier 280. With each multiplier and the x-input is associated corresponding multipliers 301 to 308 which respectively form A n x<SP>n</SP>. The outputs of multipliers 301 to 308 connect to an adder 317 which may also receive a constant from unit 320, the output of which is the required series.