Patent GB-919969-A (GB)
Title: Improvements in junction transistors
Inventor: SHOCKLEY WILLIAM
IPC: H01L29/00
Filed: 1959-04-01
Abstract: 919,969. Transistors. SHOCKLEY TRANSISTOR CORPORATION. April 1, 1959, No. 11130/59. Class 37. A junction transistor comprises a base zone of one conductivity type, consisting of thick ribs interconnected by one or more thin webs, sandwiched between two zones of opposite conductivity type, one of which completely covers one face of the base zone and the other of which forms a PN junction with the web or webs and part of the ribs. Ohmic contacts are made to all three zones. The ribs enable a low base resistance to be obtained without a corresponding loss in current gain of the device. This leads to improved high frequency performance or greater power handling capacity at normal frequencies. The device shown in Fig. 7F is made by the following steps. An N-type wafer is provided with parallel grooves either mechanically or by etching through a mask or photo-engraving, and an acceptor impurity diffused into all its surfaces. The resulting P+ zone and grooves are removed to leave parallel P+ zones, as shown in Fig. 7C, and an N+ layer formed over the entire surface by inward diffusion of a donor impurity (Fig. 7D). After bevelling the edges of the resulting wafer an acceptor is diffused through the N+ layer to form a continuous P layer beneath it and over the bevelled surfaces (Fig. 7E). After removal of the unwanted P and N+ zones to lines 23 and etching to remove any overdoped surface layers resulting from the diffusion processes a contact is made to the bevelled edge of the base zone and collector and emitter contacts 11, 13 to the other zones. Alternatively, the base contact is formed by alloying aluminium through the emitter zone or by masking, removing the exposed part of the emitter zone by electrolytic etching and making contact to the exposed base zone. To increase the reverse breakdown voltage of the collector junction the edge may be further bevelled to give a feather-edged base zone 24 (Fig. 7G). Subsequently, the edges may be heated to redistribute the impurities adjacent the junctions to alter the positions of and reduce the concentration gradients at the emitter and collector junctions (Fig. 7H). In an alternative method of making the above devices acceptor impurity is diffused outwards from one face of a P +PP+P... structure formed by rate growing to form N zones as shown in Fig. 9. Subsequently, an N-type zone is provided over the entire face by diffusion and an emitter zone formed on top of it. The device is finished off as above. Another embodiment is made by the steps of heating a P-type wafer in the presence of a donor impurity to produce an N+ layer on one face, reheating in the absence of the impurity to diffuse the donor outwards and further inwards to produce an N+ zone between two N zones, cutting parallel grooves through the N zones and then diffusing donors into the grooved surface to form an N+ surface layer, removing the N+ layer between the grooves and finally diffusing acceptor impurity into the wafer to give the zone configuration shown in Fig. 8H. The net impurity concentrations along the lines a and b are shown in Fig. 8I. Another device is made by the steps of treating a surface of a P + wafer to reduce the acceptor concentration in the surface zone, diffusing donor impurity into the surface to form a very heavily doped N zone over said surface zone, cutting parallel grooves through the surface zones into the P+ material and then diffusing donors into the outer surface to form an N layer. An insulating film, e.g. of silica or magnesium fluoride is next provided on the wafer surface between the grooves by evaporation from directional evaporators so disposed that the grooves are shadowed. A continuous acceptor metal film, e.g. aluminium or a goldgallium alloy is then evaporated on to the surface and heated to produce alloy emitter PN junctions in the grooves (Fig. 10C). Alternatively, the insulating layer at the edges of the grooves partially shadows them to isolate the metal deposited in the bottom of the grooves from that between the grooves, thus reducing the emitter capacity of the transistor. After bevelling the edges of the wafer to expose the N+ + base layer as shown in Fig. 13, which is a cross-section of the device transverse to the grooves, a base contact is provided by plating, alloying or evaporation. The P + region which forms the collector is soldered to a massive support 41 and a pressure or soldered or welded contact made to the emitter. Further reduction in the base resistance of the above devices may be produced if the parallel ribs are replaced by a grid of intersecting ribs. The device shown in Fig. 16 comprising only a single web is formed by similar techniques. The emitter zone 42 is situated on the walls of the deep groove and of a shallower groove communicating with it. An emitter contact is made to the zone in the shallower groove which does not extend into the P+ zone.