Patent GB-1440856-A (GB)
Title: Computers
IPC: G06F9/22
Filed: 1974-09-26
Abstract: 1440856 Microprogramming HONEYWELL INFORMATION SYSTEMS ITALIA SpA 26 Sept 1974 [26 Sept 1973] 41983/74 Heading G4A A microprogrammed computer has microinstructions stored in both a control memory 2 (ROS), Fig. 1, and in a magnetic core main memory 122, Fig. 3, a single bit of an addressed microinstruction being transmitted to a flip-flop 24 which indicates in which of the memories 2, 122 the next microinstruction is stored, the set state (binary 1) indicating main memory and the reset state (binary 0) control memory. The control memory 2 has an address register 5, and the address stored therein may be incremented by one by passage through a loop comprising a register 6, an incrementing unit 7, a channel 17 and gates 13, 14 and 11. Alternatively the address in register 5 may be incremented by an integral quantity K from the microinstruction register 3 via a channel 18 and a gate 15. In a further form the new address may be obtained directly from the microinstruction register 3 and is then fed to register 5 via channel 18 and a gate 10. Alternatively, a new address obtained from a register (A) of the operating section (Fig. 2, not shown) may be loaded into register 5 via a channel 19 and a gate 9. The contents of register (A) may originate from other registers of the operating section, from an external peripheral unit or from the main memory 122. The microprogram address register 5 may address the main memory 122 via a channel 129, a gate 134 and a main memory address register SI, and the read-out microinstruction, stored in a main memory output register DI via a gate 126, may be loaded into the microinstruction register 3 via a channel 29, a register 27 and gates 28, 30. A logical sequencer 25 controlled by the flipflop 24 generates a sequence of microcommands, which are fed, together with microcommands obtained from register 3 via a decoder 4, to a logic network 4A having a plurality of OR gates which generates a set of microcommands C 1 - C N . A clock circuit 20 generates sets of clock pulses T 1 -T N  and TC 1 -TC N , the set T 1 -T N  being fed to various gates as enabling and inhibiting signals, whereas the set TC 1 -TC N  is fed to a conditioning network 21 where it is converted by the set of microcommands C 1 -C N  into a set of clocked microcommands CT 1 -CT N  which is fed to various other gates. The logical sequencer 25 is described in some detail with reference to Fig. 4 (not shown) and comprises a two-bit binary counter. Operations (addressing, reading out and transferring) on microinstructions stored in the main memory 2 are controlled by microcommands generated by the logical sequencer 25. Switching between memories 2, 122 may take place "statically", i.e. at the end or beginning of a microprogram, or "dynamically", i.e. wherein a combination of a part of a microprogram stored in one memory and a part of a microprogram stored in the other memory, is used. The latter is accomplished by means of a "jump microinstruction" which may be stored in the control memory 2 and optionally also in the main memory 122 and which contains the microinstruction address and information as to in which memory said microinstruction is stored. A starting address may be transmitted from a console to register 5 via a channel 8, and the START input of the clock circuit 20 may be energized simultaneously. For operations on the main memory 122, the flip-flop 24 may be set to binary 1 by a bit provided from the operating section on a channel 19 via a gate 9<SP>1</SP>, or by a bit passed from register 3 through channel 18, or by a signal provided on a channel 8<SP>1</SP> from the console.