Patent GB-808247-A (GB)
Title: Device for effecting synchronisation of serial pulse groups in plural channel information systems
IPC: G11B20/20
Filed: 1957-02-11
Abstract: 808,247. Electric digital-data-storage apparatus; digital electric calculating apparatus. SPERRY RAND CORPORATION. Feb. 11, 1957 [March 2, 1956], No. 4557/57. Class 106 (1). [Also in Group XXXIX] In a multichannel information circuit wherein trains of electrical pulses (which may be out of phase with one another) are received on a plurality of input lines, each train is stored in a plural stage register and when the pulse train storage has been completed in all registers, the pulse trains are read out from all the registers simultaneously. The pulse trains may be obtained from channels of a magnetic tape in which case the phase displacement may be due to skew between the tape and its transducer, or from long transmission lines the phase displacement being due to different delay characteristics in the individual lines. As shown, each train on input channel 2, 3 ... N comprises information pulses X (pulse for " 1," no pulse for " 0 ") preceded by a group of sync. pulses Y, and is applied through an amplifier to a similar control circuit 20, 30 ... 50 (only 20 being shown in detail) each controlled by regular sprocket pulses from channel 1 which after being amplified, and inverted and shaped in circuits 10, 11, are applied to terminal 12. In circuit 20, the sprocket pulses are applied, together with the output pulses of a flywheel oscillator 21 shaped in circuit 23, to a frequency comparator 24 which applies a control potential to reactance tube circuit 22 to control the oscillator frequency. The oscillator receives the pulse train on channel 2 and is locked in phase by the Y- pulses so as to produce a regular series of output pulses in phase with the pulse positions of the subsequent X-pulses. These oscillator output pulses open gate G3, whereby the pulse train is applied to shift register 26, and also act as shift pulses via gate G2 and delay D. When the register is filled, the last stage 28 produces an output on line 31 which sets bi-stable flip-flop FF-2 to condition C in which it inhibits gate G3, sets flip-flop FF-1 to B to inhibit gate G2, and opens gate G4 connected to the shift register stage 29 containing the first information pulse X. When the shift registers in all the control circuits have been filled the coincidence of outputs on all lines such as 31 operates gate 32 so as to set to condition E a flip-flop FF-3 which may be part of an information utilization circuit 60, e.g. a digital computer. Flip-flop FF-3 then opens gate G6 to pass high-frequency pulses from oscillator 35 via gate G5 and delay D to the shift pulse input of register 26 and similarly to the shift pulse inputs of the other registers. The X- pulse trains from all the registers are thus read out simultaneously via gates such as G4 to input terminals such as 64 of the circuit 60. When enough shift pulses to clear the registers have been applied, an output from counter 36 resets FF-2 to condition D via buffer 33 (and similarly resets the other control circuits), and resets FF-3 to condition F. Details of circuits 10, 11 and 21-24 are given.