Patent GB-948058-A (GB)
Title: Improvements in or relating to solid state devices
IPC: H03F7/00
Filed: 1960-05-25
Abstract: 948,058. Parametric amplifiers. WESTERN ELECTRIC CO. Inc. May 25, 1960 [June 12, 1959], No. 18458/60. Heading H3B. [Also in Division H1] A parametric amplifier includes a voltage variable capacitance unit comprising a dielectric layer contacting a semiconductor region of material with a carrier mobility of at least 100 cms.<SP>2</SP> per v.sec. Fig. 1 shows an N-type silicon wafer 1 sandwiched between layers 2 and 3 of silicon oxide having evaporated metal layers 4 and 5 with lead wires attached. When this ONO (i.e. oxide-N-type-oxide) device is biased with layer 4 positive, a depletion layer forms at the negative silicon-oxide interface 1-3, the thickness t of which varies as (Vp)¢ where # is the resistivity of the silicon and V the bias voltage, thus providing a variable capacity in series with the capacity due to the oxide layers. If V is large enough, the depletion layer occupies the whole of the silicon layer, but there is no punch-through effect. The effect of thermally generated electron-hole pairs is discussed, whereby holes tend to accumulate at the negative interface, possibly forming an inversion layer, and electrons tend to cancel positive fixed changes in the depletion layer and possibly form an accumulation layer; this results in decreased sensitivity for the variable depletion layer capacitance. The tendency for accumulation and inversion layers to form, may be reduced by providing a leakage path through the oxide layer such as by reducing its resistivity to, say, 10<SP>12</SP> ohm cms., or providing a thin conducting coating over the oxide-semiconductor junctions. Limiting frequencies and figure of merit are discussed. Other types of units are described with different layer arrangement. If one oxide layer is omitted, the arrangement constitutes an ON device which has less accumulation effects and the capacity variation occurs at the same frequency as the pump, instead of twice this frequency as in the ONO device. An ONPO device containing a PN junction is described wherein depletion layers occur at the PN junction with reverse bias or at the ON and PO junction with forward bias. Reference is also made to a number of ON devices mounted in series, either by a plurality of layers as described, or by having a number of coated particles or flakes bonded together, for example by using low melting point glass such as described in Specification 923,338 or 942,755 containing As and S or As and Se with Te. In this case, the glass provides the dielectric in place of the oxide layer. These may be in the form of plastic tapes. In another embodiment, an OIO structure (i.e. oxide-intrinsic-oxide) is described, the intrinsic layer being 1 Debye length thick. When biased, an accumulation layer is formed at each face and there is no depletion layer. Other arrangements referred to include OIN, OINIO, ONPNO and OPNPO structures; also an ON+N in which the presence of the N+  layer increases the sensitivity of the accumulation layer capacity, and an ONN + which tends to have a low series resistance as well as a low accumulation layer capacitance. In ONO or ON arrangements, avalanche breakdown may be utilized to provide a sharp change in capacitance. The area of one of the metal layers may be restricted to provide a small capacitance for matching purposes. Fig. 12B shows the semiconductor element mounted between metal elements 131 and 135 and enclosed by ceramic housing 136. Alternatively, the element may be coated overall with the oxide coating since this has high resistivity. Semiconductor materials, referred to, with a carrier mobility of more than 100 cm.<SP>2</SP> per volt second are silicon, germanium, copper-oxide, indium antimonide and gallium arsenide. The oxide coating may be produced anodically, vapour deposited or grown thermically. The metal contacts may be made by thermal compression bonding, gold bonding or evaporation of gold, chromium or aluminium, or pressure contact or soldering. In one example, the thickness of the oxide layer was 10<SP>-5</SP> cms., the silicon layer was 2.5Î10<SP>-3</SP> cms. thick, and donor concentration was 10<SP>16</SP>. Fig. 12A shows the device 124 mounted in an adjustable waveguide section. A signal is introduced through port 121, which is coupled to a filter and a circulator, through adjustable iris 122 into 124. Pump energy is supplied through port 125, the waveguide section being tunable by plunger 126. Tunable coaxial line 127 and waveguide 130 provide coupling. Fig. 11 shows a parametric amplifier circuit, in which a pump frequency of 12 k. me. is supplied from source 106 to the parametric element 105. The input signal at 6 k. mc. is received at antenna 107, and passed through circulator 108 and filter 109 to element 105 for amplification. The signal returns through filter 105 which attenuates the 12 k. mc. pumps frequency, to circulator 108 and crystal 110 where it is mixed with local oscillations at 6060 mcs. from source 111 to supply a 60 mcs. signal to I.F. amplifier 112. The invention may be applied to digital computers based on the phase of a parametric diode.