Patent GB-904487-A (GB)
Title: Improvements in or relating to electric frequency dividers
Inventor: CATTERMOLE KENNETH WILLIAM
IPC: H03B5/12
Filed: 1959-02-27
Abstract: 904,487. Transistor pulse frequency dividing circuits. STANDARD TELEPHONES & CABLES Ltd. Feb. 27, 1959, No. 6992/59. Addition to 726,496. Classes 40 (5) and 40 (6). A pulse frequency dividing circuit comprises a junction transistor provided with regenerative feed-back through a transformer from the collector electrode to the emitter electrode of the transistor, a delay network being connected to shunt the feed-back path whereby the circuit generates rectangular pulses of a length determined by the delay network on being suitably triggered and a further delay network being connected in the circuit of the base electrode of the transistor whereby on the circuit being triggered by the application of a suitable combination of pulses to the emitter and base electrodes, a pulse is applied to the second delay network, these pulses being reflected from the line and appearing at the base electrode as gating pulses which, after the elapse of a suitable time for the circuit to recover, permit further triggering of the circuits when they occur in coincidence with a subsequent input pulse. In the circuit shown in Fig. 1, the transistor 3 is normally biased off by the connection from its emitter electrode to the potentiometer 15 through the diode 14. On the application of a large-amplitude positive initiating pulse to the transformer 13, the diode 14 is switched off whereby the emitter electrode of the transistor goes positive and conduction occurs, the rise in potential at the collector electrode being applied through the input impedance of the delay network 9 to the emitter electrode, thus causing a rapid switch on of the transistor 3. The pulse produced at the collector electrode is reflected from the open end of the delay line 9 and appears at the emitter electrode a short time later with a negative polarity so as to switch the transistor off, the positive feed-back again increasing the switching speed. Since the transistor 3 is a junction-type and has a current gain less than unity, an auto-transformer 8 is provided so that sufficient current positive feedback may be applied to the emitter. As a result of the switching of the transistor a positive pulse appears at the base electrode; this travels down the delay network 10, being reflected from the short-circuited end thereof and appearing at the base electrode with reversed polarity. This process is repeated so that a succession of pulses which are alternately positive and negative appear at the base electrode. The pulses to be divided in frequency are applied to transformer 13 and are of smaller amplitude than the initiating pulse whereby, even after recovery of the transistor 3, they are unable to trigger the circuit; however, when the circuit has recovered, coincidence between an input pulse and a negative gating pulse from the delay network 10 causes fresh triggering of the transistor 3 and the production of an output pulse at terminal 17, the process then being repeated as already described. Fig. 2 shows an arrangement whereby in, for example, a pulse multiplex system, the division ratio may be changed for one cycle of operation to alter the channel selected by the circuit. An intermediate point of the delay network 10, corresponding to that shown in Fig. 1, is connected to the emitter electrode of a switching transistor 19 which is normally non-conducting but which may be rendered conducting by the application of a suitable pulse to the terminal 22. On the application of such a pulse, the line is effectively short-circuited at the intermediate point and the time interval between successive gating pulses from the delay network is reduced. By suitably timing the application of the switching pulse to the terminal 22, it can be arranged that the frequency division effected by the circuit is altered and hence a different channel pulse selected. Fig. 4 shows means whereby the pulse applied to the terminal 22 may be generated. A pulse is applied to the circuit 38 which generates a gating pulse of a length substantially equal to the period between successive output pulses from the divider circuit 36; this opens the gate 39 to allow one output pulse from the terminal 17 to be applied to the circuit 40 which generates a pulse of the required length and timing for application to the terminal 22. Preferably in order to prevent malfunctioning due to two pulses from the terminal 17 passing through the gate 39 in succession the generation of a pulse by the circuit 40 prevents the generation of a further pulse in the subsequent period of pulses from the terminal 17. Specification 784,379 is referred to.