Patent GB-1371288-A (GB)
Title: Data processing systems
Inventor: KAMMERL A
IPC: H04L12/52
Filed: 1972-05-03
Abstract: 1371288 Digital transmission; exchanges SIEMENS AG 3 May 1972 [24 June 1971] 20522/72 Heading H4P Data traffic is switched cyclically between a termination unit having terminals assigned to incoming and outgoing links, each having identification means, and at least one central storage unit containing a notepad memory and special notepad memory for recording incoming and outgoing pieces of data. Feeder cells, assigned to each link, store criteria for processing incoming information and are situated with substitution cells in a block storage area. Data which is offered as input to the central storage unit when a cycle application is emitted by a control unit is supplied as a characteristic to a cycle buffer assigned to the control unit where it is intermediately stored until data is read out during as assigned cycle, the characteristic and stored data being available to an evaluation circuit assigned to the control unit wherein on evaluation, further processing of incoming data, which is either transferred to an outgoing link, or is operated on by a further programme, in which event data necessary for the execution of such programmes is intermediately stored in a subsidiary cycle buffer assigned to the control unit until a new cycle is produced when data is transferred to a free stage of the cycle buffer store. Preferably the cycle buffer and subsidiary cycle stores are multistage, data being placed in the lowest free stage and periodically displaced towards the lowest stage, data from which being available for the following processing operation. In a known traffic control system signals on line terminating units SA are recognized by identifying units ECW, ACW and data is passed to a central storage and control unit SP through at least one communication control unit UEAS for which the present invention is mainly concerned and shown in Fig. 3. Data blocks from ECW pass through DE and are offered to address selector AdAW, word selector WAW and selector device MTAW and may pass to storage unit SP through address output register AdAR and with register WAR. A cycle selector ZAWS is provided which has access to cycle control unit ZS through which cycle applications pass to unit SP. Data from SP passes through WER to an evaluating device BW and output device DA which has access to output converters ACW connected to outgoing links. The control unit also contains permanent address indicator FA clock UZG also counters required for addressing the command store, and notepad and special notepad memories in SP. A free stage buffer ZP and subsidiary four stage buffer NP store the data of three or four consecutive cycles. The stores may be alternatively arranged in parallel. On arrival of the first cycle, input data (EO) via UEAS to SP is recorded in stage O of ZP which is completed by timing pulse 4 (see Fig. 2, not shown). The next block of input data E1 is placed in stage 1 and E2 in stage 2 of ZP. As however the first cycle has now terminated, E1 E2 are moved forward a stage at timing pulse 13 with a gap of two pulses before the next data E3 is entered. Other cycles of operation are described in the Specification.  The arrangement may form part of a store and forward exchange system.