Patent GB-1342909-A (GB)
Title: Speech detection device
IPC: G10L25/78
Filed: 1971-04-19
Abstract: 1342909 Detecting speech in noise POST OFFICE 19 April 1971 [13 March 1970] 22171/71 Heading H4R In an apparatus for detecting speech signals in the presence of noise an input signal is sampled periodically, e.g. at a frequency of 8 KHz, the polarity of each sample is determined and a pulse indicating detection of a voice signal is generated after a predetermined polarity sequence is received for greater than a predetermined time. The polarity sequence may be alternate positive and netative for a time greater than 2 Msec., or 16 samples of one polarity followed by 4 to 8 samples of the other polarity, or vice versa. As described the input signal is sampled and the samples converted to pcm form in which the first digit represents polarity. The input pcm stream is clocked into a flip-flop 1 by a clock signal B1 coincident with the first digit of each sample so that the flip-flop state indicates the sample polarity. The flipflop output Q1 is compared by an exclusive-or gate 2 with an input signal I of alternate positive and negative polarity at a frequency B1/2. The output from the gate 2 sets a flipflop 3 into one condition or the other depending on whether the signal Q1 is of the same or different polarity to the signal I, and is provided mainly to eliminate transients at the output of exclusive-or gate 2. The output of flip-flop 3 is applied to a further flip-flop 4 clocked by a pulse B3 delayed slightly on the pulse B2 clocking flip-flop 3 so that the exclusive-or gate 5, connected to compare the outputs of the flipflops 3 and 4, generates a pulse whenever there is a change of state of the signal at the output of flip-flop 3, i.e. whenever the input signal derived from the speech deviates from alternate positive and negative polarity. The output of gate 5 is used to reset a counter 6, counting clock pulses at 4 KHz, the fourth stage output of which provides a "speech present" signal which is produced whenever the alternate positive and negative sample sequence is maintained for a period greater than 2 mSec. i.e. the counter is not reset before the final stage is triggered. A similar system using exclusive-or gates 7 and 10 and flip-flops 8 and 9 operates to detect runs of one polarity followed by runs of the opposite polarity. In this case the exclusive-or gate 7 is fed with a comparison signal B1/32 which has a cycle which is of one polarity for 16 sampling periods and the opposite polarity for the following 16 sampling periods. In addition the output pulse from gate 10 only resets the last three stages of the counter 11 which means that the coincidence has to last for a time interval which is statistically variable between 20 and 24 samples, before the NAND gate 12 is operated to produce a speech present signal. The first detector responding to alternate polarity samples is operated by sibilants and the second, responding to runs of one polarity followed by runs of the other, by voiced sounds to provide respective speech present signals. The detector system described. can be combined with a level comparator 13, Fig. 4, which operates on signals exceeding a predetermined threshold to provide a further detection circuit responding to high level speech sounds.