Patent GB-1299530-A (GB)
Title: Decoding circuit
Inventor: OWEN CHARLES EDWARD
IPC: H04L25/49
Filed: 1970-09-19
Abstract: 1299530 Data storage INTERNATIONAL BUSINESS MACHINES CORP 19 Sept 1970 44747/70 Heading G4C [Also in Division H3] A decoding circuit for decoding a train of input pulses, the pulses being spaced from each other by one of two nominal intervals, uses each pulse to cause flyback in a sawtooth, an output being produced whenever the sawtooth passes a threshold, the flyback having one of two different magnitudes according to the presence or absence of an output, these magnitudes being fixed so that displacement of an input pulse from its nominal position dces not effect the time at which the succeeding ramp either reaches or, but for an intervening flyback, would have reached the threshold. In Fig 1, the input 1 has a long interval between consecutive pulses to represent "1" and two-thirds this interval to represent "0" The sawtooth generator is basically a Miller integrator, with controlling capacitor 3 and Darlington pair 4, 5. Each ramp is produced by discharge of 3 via resistors 6, 7 and transistor 8. When the (negative-going) ramp goes below a threshold E, a long-tailed comparator 18, 19 sets a trigger 2 to produce an output T indicating "1" A capacitor 9 normally charges via resistors 13, 14, but each input pulse at 1 reduces the charging voltage by enabling transistor 11 to provide a shunt of resistance depending on the presence or absence of T at transistor 12. The reduction in charging voltage for capacitor 9 charges capacitor 3 (flyback). The ramp slope is varied to compensate for long-term frequency variations (due to speed variation in the drum or disc from which input 1 comes) by using the level on a capacitor 21 via a low-pass filter 22 to control the resistance of the discharge path 6, 7, 8 of ramp capacitor 3, at transistor 8. While the sawtcoth is above a reference level defined by a potentiometer 23, as determined by a long-tailed comparator 24, 25, capacitor 21 is charged via a transistor 26 (except that in the case of a preceding "0" bit, half the current is diverted via a transistor 27 due to the control of a transistor 29 by trigger 2, to provide for the fact that the sawtcoth is below the reference level for twice as long for a "1" as for a "0"). While the sawtooth is below this reference level, capacitor 21 discharges via transistor 27, so that in the absence of frequency variations, the average level on capacitor 21 is zero. Non- ideal flyback can be compensated for by a capacitor (short time constant) connected between transistor 11 collector and transistor 24 base. Synchronization of the circuit is achieved by an initial block of zerces followed by a block of ones. The invention can be applied to double-frequency encoded input (having regular clock pulses, a data pulse being present or absent half way between consecutive clock pulses for "1" and "0" respectively, viz. long interval for "0", two short intervals for "1") by subtracting the long interval indicating signal from the input signal and dividing the remainder by two to get pulses indicating "1"s. Decoding of address marks represented by omission of the clock pulses can also be done using suitable logic.