Patent GB-1369322-A (GB)
Title: Telephone dial pulse corrector
IPC: H04Q1/36
Filed: 1972-07-27
Abstract: 1369322 Automatic exchange equipment STANDARD TELEPHONES & CABLES Ltd 27 July 1972 35083/72 Heading H4K An impulse correcting repeater comprises a first logic for determining and storing the duration of the make plus break portions of each incoming impulse and, a second logic for producing a corresponding outgoing impulse the length of whose break portion is determined by the information stored in the first logic such as to ensure that the output break/make ratio is a constant.  In the arrangement shown, spurious pulses in an incoming impulse train are eliminated by a suppressor circuit 2 while a control signal generator 1 produces a short pulse c.f. row 42 in Fig. 4, at the trailing edge of each make pulse of the incoming train (row 41). Each short pulse is gated via a gate 4 and a delay device 3 (whose duration is just sufficient to permit data transfer from a counter to a store) to a counter 6 so as to reset the latter and thus permit it to start counting-up divided clock pulses supplied via a gate 8 and divider 7. The appearance of the next short pulse from gate 4 is effective via timing circuit 9 to cause the current content of counter 6 to be read-into store 10-and is also effective via delay 3 to reset the counter 6. This procedure may be gathered from rows 45 and 46 corresponding respectively to the counting state of counter 6 with the short vertical parallel lines representing the data transfer period, and to the storage period within store 10 (Read-in to the latter destroys any preexisting contents). Meanwhile the original short pulse has traversed delay 5, c.f. row 43, so that at some time before or after (depending on whether the incoming train is slow or fast respectively) store 10 contains its first count corresponding to the make plus break period of the first impulse, a second counter 12 is started to enable it to count undivided clock pulses. The contents of store 10 and counter 12 are compared by a comparator which produces a make pulse for as long as the content of 12 is less than that of 10 whereafter it restores to the break condition c.f. row 48. Counter 12 continues to count with no effect until it is reset by the appearance of the next short pulse. Following the last make pulse of the incoming train, timing circuit 9 times-out to artificially mark the end of the succeeding break pulse and thus the end of the train. The count of counter 6 is transferred to store 10 for the last time but the counter is not reset nor is it allowed to be incremented by further clock pulses (closure of gate 8). Counter 12 is stopped when it reaches a maximum count as denoted by the feedback circuit 14. These conditions persist until a new impulse train arrives. It will be appreciated that store 10 contains a number corresponding to the duration of each make plus break pulse as counted at some fraction of clock rate. Counter 12 counts at clock rate so that it reaches this same number in a time less than the make plus break duration. This time will always be a fraction of the make plus break duration which is independent of either the make or break portions thereof. During this time a corrected outgoing make pulse is transmitted. The terms make and break as used hereabove are of course interchangeable.