Patent RU-2076458-C1 (RU)
Inventor: MARTIROSOV VLADIMIR E
IPC: H04L27/14
Filed: 1995-03-06
Granted: 1997-03-27
Abstract: FIELD: radio electronics, in particular, discrete data transmission systems, can be used for demodulation of signals with frequency-shift keying. SUBSTANCE: the device features an enhanced performance in terms of error probability due to reduced level of arrival curve distortions and distortions of the "predominance" type. It is attained due to the use of discrimination characteristic with a dead zone and without hysteresis, which allows it to reduce fluctuations of the fronts of demodulated signal, i.e. the value of arrival curve distortions. Employment of a clock pulse generator operating at a fixed frequency and a reference signal driver serving as a tunable generator of the phase-lock control system makes it possible to reduce the instability of frequency of reference oscillations decrease the random initial frequency detuning and, consequently, to decrease the level of distortions of the "predominance" type. The signal demodulator with a frequency-shift keying has a pulse shaper, as well as the first and second AND gates; the pulse shaper input is connected to the device input, and the first inputs of the first and second AND gates are connected together, the first and second D-flip-flops, "excluding OR" gate, RS flip-flop, clock pulse generator and reference signal driver; the D inputs of the first and second D-flip-flops are connected to the pulse shaper output; the first input of the "excluding OR" gate is connected to the output of the first D-flip-flop, the second input of the "excluding OR" gate is connected to the inverter output of the second D-flip-flop, the first inputs of the first and second AND gates are connected to the output of the "excluding OR" gate, the second input of the first AND gate is connected to the output of the first D-flip-flop, the second input of the second AND gate is connected to the inverted output of the second D-flip-flop, the R input of the RS flip-flop is connected to the output of the first AND gate, the S input of the RS flip-flop is connected to the output of the second AND gate, the output of the RS flip-flop is connected to the device output, the first input of the reference signal driver is connected to the output of the first D-flip-flop, the second input of the reference signal driver is connected to the inverted output of the second D-flip-flop, the clock input of the reference signal driver is connected to the output of the clock pulse generator, and the C inputs of the first and second D-flip-flops are connected to the first and second outputs of the reference signal driver, respectively. The reference signal driver has the third and fourth D-flip-flops, code converter, delay element, counter and a decoder; the D inputs of the third and fourth D-flip-flops are connected to the first and second inputs of the reference signal driver, respectively, the clock inputs of the third and fourth D-flip-flops and the input of the delay element are connected to the clock input of the reference signal driver, the first and second inputs of the code converter are connected to the outputs of the third and fourth D-flip-flops, respectively, the counter data input is connected to the output of the code converter, the counter clock input is connected to the output of the delay element, the counter recording enabling input is connected to the counter overflow output, the decoder input is connected to the counter data output, and the first and second decoder outputs are connected to the first and second outputs of the reference signal driver. EFFECT: enhanced performance in terms of error probability. 2 cl, 2 dwg