Patent GB-1245371-A (GB)
Title: A data communication system
IPC: H04J3/24
Filed: 1970-01-01
Abstract: 1,245,371. Computer input/output. INTERNATIONAL BUSINESS MACHINES CORP. 1 Jan., 1970 [15 Jan., 1969], No. 128/70. Heading G4A. In a data communication system, an information entity including address, control and data information is transmitted from a central station along a loop to a plurality of area stations in turn and back to the central station which processes it for re-transmission around the loop, each area station being capable of altering the entity before passing it to the next station in the loop, examining the address information and altering or utilizing the data information. The central station communicates with a computer and each area station has one or more I/O devices for the computer. In the central station, each of 13 so-called " channels " (which are essentially time-slots) has a storage location in frame (core) storage, the location holding a frame for the " channel". The frames for "channels" 1, 2 . . . 7, 8; 9; 1, 2 . . . 7, 8; 10; 1, 2. . . 7, 8; 11; 1, 2 . . . 7, 8; 12; 1, 2 . . . 7, 8; 13 are read out in that order repeatedly. Each frame is four 8-bit bytes, being respectively for the address of an area station (but see below), the address of an I/O device at the area station, a control byte and a data byte. The frame, preceded by a start byte and followed by 25 sync. bytes (some of which may be used for data instead) is passed byte-by-byte to an output one-byte shift register for serialby-bit application to a twisted pair transmission line forming part of the loop. The last sync. byte following the channel 13 information before the next channel 1 information is replaced by an extra start byte so there are two adjacent start bytes. Output from the central station to the loop is under control of an oscillator. At each area station, a one-byte shift register is fed from the twisted-pair transmission line from the preceding station and feeds the transmission line to the next station in the loop. Clock signals are derived from the incoming pulses at the area station to provide its timing, sync. and start bytes being recognized in the shift register for synchronization purposes. The station address byte is decoded to determine if it specifies that the data and control bytes are for this station or if for " all stations'', or if it specifies " any station " in which case if an I/O device at this station requires service it can cause its address and the station address to replace the address bytes in the current frame in the loop. The I/O device address can also be decoded to select a required I/O device. The control byte is also decoded and if necessary altered before transmission further along the loop. On return to the central station, an input shift register receives the bytes. Clock signals are derived from the pulses for timing, and start, sync. and start-start are recognized for synchronization. The corresponding frame is accessed from the frame storage into an input frame register and can be compared byte-bybyte with the incoming frame bytes to detect changes. The " any station " address byte, if present in this frame from storage, is recognized. The control byte from frame storage and that from the loop are both decoded. The input shift register can feed both address bytes and the data byte to the input frame register which also receives a new control byte in dependence on the previous control byte and that from the loop. Error is indicated if the response control byte, i.e. that from the loop, is invalid. Data bytes are transferred in either direction between the input frame register and the computer, and the contents of the input frame register are rewritten into the frame storage which can also receive new frames from the computer. Data sent from an area station is sent twice, the two versions being compared as a check in the comparison circuit above.