Patent GB-809669-A (GB)
Title: Improvements in electrical networks operating as buffers and gates
IPC: H03K19/084
Filed: 1956-07-16
Abstract: 809,669. Transistor logical circuits. SPERRY RAND CORPORATION. July 16, 1956 [July 25, 1955], No. 21977/56. Class 40 (6). In a logical network, substantially similar units are cascaded, each unit comprising a digital signal combining circuit and a complementer, the output of the complementer being connected to the input of the combining circuit of the next unit so that the value of the digital signals changes from unit to unit and they operate alternately as AND and OR gates. Transistor 10, operated as an OR gate, is held conducting due to a connection from the base over resistors R1, R2 to a negative potential B. A positive-going pulse applies to any of the diodes 16, 17, 18 raises the potential of the base of transistor 10, cutting it off so that the collector potential goes negative. Transistors 11, 12 are similarly connected to transistor 10 and when both transistors 10, 11 are cut off the potential of junction 45 may fall. Transistor 13 operates as an AND gate and is normally cut off by the diodes 25, 26 conducting to maintain the base near earth potential. When the diodes 25, 26 are both cut off the junction 45 falls in potential so that transistor 13 conducts to feed out a positive-going pulse at the collector. An inhibiting positive-going pulse may be applied over diode 27 to prevent transistor 13 from passing to the conducting state. When one of the transistors 10, 11 is conducting the junction 45 is near earth potential so that in order to maintain the transistor 13 near cut-off a resistor R3 is necessary to provide bias for the base. The output from transistor 13 feeds the input of the next OR gate. In order to overcome the difficulty of biasing off the base of diode 13, a potential divider coupling arrangement may be employed, Fig. 3 (not shown). Alternatively a transformer may be employed, Fig. 4 (not shown). In a further modification, Fig. 5 (not shown) transformers are inserted between the diodes 16, 17, 18 and resistor R1 and the diodes 25, 26 and the base of the transistor 13. The transistors may be operated in the common base connection and regeneration provided by a resistor R11, Fig. 6, between the collector and emitter. The potential divider chain R10, R11, R12 is arranged to bias off the emitter of the transistor. A positive-going input applied over one of the diodes 84, 85 raises the emitter potential causing collector current to flow so that the collector potential rises and hence the emitter potential rises further. A transformer input may be provided, Fig. 7 (not shown). In a modification, Fig. 2, the OR gates 50, 52 are normally non-conducting and the AND gate 51 is cut off. A negative-going pulse applied to either diodes 53, 54 causes transistor 50 to conduct so that the potential of the collector rises. Transistor 51 is maintained conducting due to current flow through diodes 59, 60, 61 but when these diodes are all cut off the transistor 51 is rendered non- conducting to feed out a negative-going pulse from the collector. This pulse is applied over one of the input diodes 57, 58 to the next OR gate transistor 52. The clamping diode 66 is provided so that when transistor conducts the positive potential applied to diode 57 is limited to B by the diode 66 so that the transistor 52 may be readily made non-conducting again.