Patent GB-1077380-A (GB)
Title: Improvements relating to pattern recognition devices
Inventor: JARRETT JOHN JAMES
IPC: G06V10/88
Filed: 1963-03-06
Abstract: 1,077,380. Automatic character reading. ELECTRIC & MUSICAL INDUSTRIES Ltd. March 6, 1964 [March 6, 1963 (2)], Nos. 8862/63 and 8863/63. Heading G4R. [Also in Division G1] In a character reader in which the image of a character is applied in turn to a series of pattern masks each of which provides a match signal, the extreme value signal is found by a circuit comprising a comparison circuit, a gain controlled amplifier for applying the signals individually to the comparison circuit where they are compared with a reference level and a gainadjusting output produced whenever the signal attempts to exceed the reference level. The gain control output is thereby adjusted to a value such as to reduce the signals to the reference level and it remains at this value until a further gain-adjusting output is produced. The signal producing the last gain-adjusting output is identified and represents the pattern mask producing the best match with the character read. An image of the character is passed, by a rotating polygonal mirror, over a set of masks and two background masks which together comprise a single background mask comprising a transparent area representing primarily the superimposition of the patterns to be recognized. The background mask may be modified to guard against partial matches occurring at certain positions between characters. It is also designed to cater for specific mutilations, e.g. heavy printing. The light transmission through the character masks is measured by photo-cells connected to terminals (1-3, Fig. not shown), and the two background masks are represented on terminals (4 and 5). The signals are applied to emitter-follower units (6-10) having a band width designed to remove noise. Automatic gain controlled units (16-20) normalize the largest outputs at 10 volts. Positive outputs from the character channels are modified by being combined with negative outputs from the background in resistors (21-23 etc.). Feed-back amplifiers (31- 35) have feed-back resistors (30-34) suitably related to the values of the summing resistors (21-29). The gain control signal for unit (16-20) is obtained by connecting all the channels to an OR gate (36) and comparing the output (at 79) with a reference level of 10 volts (at 81). The gain is reduced from a maximum at the beginning of each reading operation, and the match of each pattern is indicated by the extent to which the signals attempt to exceed the normalized value-10 volts. The gain control voltage is :stored in capacitor store (84). When a maximum signal occurs on one of the leads it causes a -corresponding comparator (41-43), in which it is compared with - 10 volts, to set a trigger (44-46). As each new maximum occurs the corresponding trigger is set and an output produced from the associated beginning element (50-52). These are connected via OR gates (53 and 67) to reset, via gates (47-49), all those triggers whose comparators are giving a negative output. By this means each maximum erases the stored record of the previous maximum. The triggers control AND gates (37-39) to apply only those signals which are not maximum via an OR gate (40) to comparator (76) having as the other input (75) a voltage of 9 or 9À5 volts. If a following non-maximum signal is above this, i.e. too close to the maximum it causes trigger (70) to be set and gate (59) enabled to pass a reject signal at the end of the operation. As the four-sided mirror revolves, photo-cells (95) are energized in turn to provide clock pulses which are applied to gate (72). Gate (72) is opened by a signal from a trigger (71) which is set when an output from one of the comparators passes through gate (96). The appearance of a maximum signal therefore causes a train of pulses to enter a counter (69) which gives an output after counting (12). This causes a monostable (68) to give a read-out signal resetting trigger (71) to close gate (72), producing a reject signal if gate (59) has been opened by trigger (70) being set or opening gates (55-56) if trigger (70) is not set. If a trigger, e.g. (44) is set by a maximum signal occurring on that channel and a larger maximum occurs later to set trigger (45), the first is reset by a pulse transmitted by beginning element (51) via OR gate (53), gate (67) and gate (47) which is now open whereas gate (48) is closed by the absence of a signal from comparator (42). The recognition signal is also rejected if the largest signal preceding it is too large, the gain control voltage corresponding to the previous largest signal being stored for this purpose at (86). If there are more than one output through there being equal signals on two or more channels gate (54) responds and passes a resetting signal to reset the triggers (44-46).