Patent GB-1133600-A (GB)
Title: Display systems
IPC: G09G5/39
Filed: 1966-11-03
Abstract: 1,133,600. Display systems. INTERNATIONAL BUSINESS MACHINES CORP. 3 Nov., 1966 [7 Dec., 1965], No. 49244/66. Heading G4H. A display system includes a composer, control means and terminal units, each terminal unit comprising a buffer store, a display device and an input keyboard, the coded output from which is converted in the composer to video signals and stored in the associated buffer store from which they are fed to the display device. In the embodiment described data is transmitted from keyboards 20-22 (Fig. 2) in binary coded decimal parallel form to three sets of AND gates 26-28 sequentially enabled by a polling circuit 32 to pass the data via OR gates 38 to the composer 100 and a parallel to serial converter 104. The composer 100 converts the data to video signals. It comprises two decoders (401, 402, Fig. 7, not shown), one of the outputs of each of which is enabled. The output of the first decoder (401) selects one of the planes (1-8) i.e. one of a plurality of sets of magnetic cores (Fig. 8, not shown) and the output of the second decoder (402) selects one of the characters represented in that plane so that selected magnetic cores are set. When shift registers (470, 471, Fig. 8, not shown) are enabled, the first shift register (470) delivering a signal on each of its output leads for each output signal from the second shift register (471), trains of pulses are gated via AND gates (451-455, Fig. 7, not shown), sequentially enabled by video and bit counter 105 (Fig. 2), which commences its count when a marker bit is detected and OR gate (456, Fig. 7, not shown), to output lead (126). A marker bit is inserted at each sixth clock pulse from counter 105 so that each character is stored in video form as a forty-two bit digit in the associated delay line buffer 200-202 (Fig. 3) which is enabled by the polling circuit 32 (Fig. 2). The parallel to serial converter 104 (Fig. 6) comprises AND gates 330-337, AND gates 330-334, 337 being enabled during a first cycle of counter 105 to transmit the bits or input leads A, B, C, 8, 4 and AND gates 335, 336 being enabled during a second cycle to transmit the bits on input leads 2 and 1 together with a marker bit. The video signals are transmitted from the delay lines to the associated TV displays 220-222 (Fig. 3). When the display has been verified as correct by an operator, a key is pressed at the associated keyboard, so that a signal is transmitted via OR gates 250 (Fig. 4) to a computer 260 and the identity of the keyboard is entered into a buffer register 271 for transfer to the computer on receipt of a signal on line 272. The computer then transmits a signal on one of lines 52-54 to stop the polling station 32 (Fig. 2) on the associated terminal and the data from the associated store 220-222 (Fig. 3) is read into the computer during vertical retrace via AND gates 286-288 (Fig. 4), OR gate 292 and registers 291, 271. Data is entered into the computer until one of the marker bit controls 203-205 (Fig. 3) recognizes a marker bit in the associated delay line store and a stop signal is transmitted. When the computer has data for transmission to one of the stations, a signal on the appropriate one of lines 52-54 (Fig. 4) stops the polling circuit 32 (Fig. 2) on the associated terminal so that a delay line store is prepared. The computer then transmits data on lines 295 via a buffer register 102 (Fig. 2), OR gate 40 and composer 100 into the store. The televisions are capable of displaying eighteen rows of eight characters during 4800 microseconds of which 714 microseconds is taken for vertical retrace during which time binary coded data from the converter 104 is read into the delay line and read out into the computer.