Patent GB-683882-A (GB)
Title: Improvements in or relating to electronic circuits for digital computing systems
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G06F7/50
Filed: 1948-07-26
Abstract: 683,882. Calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 14, 1949 [July 26, 1948], No. 19967/48. Class 106 (i). Binary numbers, represented by pulse trains, are added on the basis that the sum digit of the digits A and B=A+B+C D  - 2C, where C D  is the carry from the previous order and C that to the next. The digit pulses A and B, and the carry digits C D  from a one-cycle delay store, are added in a first thermionic valve circuit 1 (Fig. 2) and limited at 2 to pulses >1¢ times the input amplitude to produce the carry pulses C which are passed to store. The pulses C are also doubled and inverted and, together with the same pulses A, B and C D , applied to a second adding circuit 3 to produce an output train representing the answer. Both adding circuits combine the function of limiter (shown separately at 2 and 4 in Fig. 2), and operate by diversion or increase of grid current in proportion to input digits to produce an anode output pulse when appropriate. First adding circuit. The adder 1 and limiter 2 of Fig. 2 comprises (Fig. 3) a valve V7, whose grid normally draws current through R2, and is controlled by switching means comprising diode pairs D9-D14 with coupled cathodes connected to negative through resistances R1. The A, B and C D  pulse trains are negative-going from 3 volts positive and are applied to the anodes of the left-hand diodes. In the quiescent state, therefore, the left-hand diodes conduct and the right-hand diodes are cut off, so that all the current through R2 passes to the grid of V7, but without appreciably raising the grid potential above that of the earthed cathode. The arrival of a digit pulse at any of the three diode pairs switches it over so that the righthand diode conducts and shares the current through R2. The circuit is adjusted so that this diversion is insufficient to change the grid potential of V7 when one diode pair only is switched. If, however, two or all three pairs are switched, owing to the simultaneous occurrence of two or three A, B or C D  pulses, then the grid of V7 is driven negative and a positive pulse, limited by D8, appears at the anode. These pulses are the carry pulses C and are passed through V8 to the delay store. Second adding circuit. The second adding circuit comprises a valve V9 similarly controlled by switching diodes R17-D22 to add the same pulses A, B and C D . A further and reversed diode pair D15, R16 connected to positive is, however, arranged to subtract the C pulses produced by the first adding circuit. Each C pulse adds two digit increments of grid current to V9 so, in effect, subtracting 2C from the remaining pulses. If the balance of pulses is >¢ the grid of V9 is driven negative; the resulting anode pulses are inverted by V10, reshaped on the back edge by a dash-wave introduced by D25 and passed to an output valve V11 for the answer. Carry digit delay store. The carry store, which receives C pulses from V8 and holds them back to form the C D  pulses, comprises a valve V12 whose grid is fed with the positive C pulses through a differentiating circuit and a diode D26 arranged to cut-off V12 at the back edge of each pulse. V12 remains cut-off owing to a condenser C2 until a strobe pulse, applied through D27, arrives at the next digit period. The negative-going edge then at the anode of V12 is passed by D28 to the grid of the cathode follower V13 which is held negative by C3 until driven positive at the end of the dash period of a dash waveform introduced by D29. Delayed C pulses are thus developed at the output of V13 and are the C D  pulses passed to the adding circuits. The input pulses to be added may be derived from a cathode-ray tube store as described in Specifications 657,591 and 682,156.