baber/WOPTO huggingface dataset:
Patent TW-369739-B (TW)
Title: Card connector
Inventor: HASHIGUCHI OSAMU
IPC: G06K13/08
Filed: 1998-05-20
Granted: 1999-09-11
Abstract: A card connector which permits insertion of a card from a side of an insulator thereof is provided. A protruded portion is formed on the bottom of a rear end of a slider movably accommodated with a hollow insulator. When the slider is moved in the direction of insertion of a card (miniature card) to bring a recessed terminal array portion of the card to a position exactly above a protruded terminal array portion of a circuit board, the protruded portion is caused to drop into a recess formed in a bottom wall of the insulator to thereby incline the slider with respect to the direction of insertion of the card to fit the protruded terminal array portion of the miniature card on the protruded terminal array portion of the circuit board. The slider is urged against the bottom wall of the insulator by a spring, and urged toward an insertion opening of the insulator by another spring. An ejection button is arranged in the insulator for returning the card to a level position.
Patent TW-428083-B (TW)
Title: Interconnection apparatus between thermogravimetric analyzer and mass spectrometer
Inventor: LING YUNG-JIAN
IPC: G01K17/00
Filed: 1998-06-08
Granted: 2001-04-01
Abstract: The invention provides an interconnection apparatus between a thermogravimetric analyzer and a mass spectrometer. The design of interconnection is series-connecting the thermogravimetric analyzer to a separator via a capillary with a larger inner diameter, wherein another capillary with a smaller inner diameter extends into the larger capillary inside separator, and then a TGA/MS system is constructed by series-connecting the smaller capillary to the mass spectrometer. The separator uses an inert gas as flushing gas to carry out redundant gas and dilute gas to be measured, and there is a constant temperature process controller in the interconnection system.
Patent TW-424120-B (TW)
Title: Calendered and embossed tissue products
Inventor: JENNINGS RICHARD DOUGLAS
IPC: D21H27/02
Filed: 1998-06-08
Granted: 2001-03-01
Abstract: High bulk tissue webs are processed sequentially through separate calendering and embossing units to optimize the balance between sheet caliper for winding tension and embossing element height for pattern definition resulting in embossed, high-bulk tissue products with improved embossing pattern clarity. The multiple step converting process enables the use of male embossing elements having a height of about 0.04 inch or greater. The tissue webs have Residual Waviness value of 12 micrometers or greater, which is attributable to average surface waviness values for the spot embossments being about 30 micrometers or greater.
Patent TW-400390-B (TW)
Title: Soft cold-rolled steel sheet and method for making the same
Inventor: FUNEKAWA YOSHIMASA
IPC: C21D8/04
Filed: 1998-07-28
Granted: 2000-08-01
Abstract: A soft cold-rolled steel sheet contains: 0.06 wt.% or less C, 0.1 wt.% or less Si, 0.5 wt.% or less Mn, 0.03 wt.% or less P, 0.03 wt.% or less S, 0.006 wt.% or less N, 0.009 wt.% or less B and the balance being Fe. The method comprises the steps of: continuously casting a steel to produce a slab; hot-rolling the slab to form a hot-rolled steel sheet; cold-rolling the hot-rolled steel sheet to produce a cold-rolled steel sheet' and continuously annealing the cold-rolled steel sheet.
Patent TW-429480-B (TW)
Title: The thermal processing apparatus for sheet-like workpieces
Inventor: HARADA TAKAYUKI
IPC: G05D23/20
Filed: 1998-09-07
Granted: 2001-04-11
Abstract: The present invention relates to a thermal processing apparatus for sheet-like workpieces such as semiconductor wafers, or optical disc or liquid crystal substrates. A plurality of Peltier devices are allocated in the electric heater clamped in the lower portion of heat transferring plate for transferring heat to the sheet-like workpieces, and a cooling part is also allocated.
Patent TW-423123-B (TW)
Title: Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same
Inventor: ONDA MAMORU
IPC: H01L21/48
Filed: 1998-09-10
Granted: 2001-02-21
Abstract: A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of  external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said  semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin , or vice versa, and the solder comprise gold/tin solder. This constitution contributes to an improved in reliability with respect to temperature cycling in lead-patterning substrates, semiconductor devices, and electronics devices.
Patent TW-410393-B (TW)
Title: Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing
Inventor: EVANS DAVID R
IPC: H01L27/10
Filed: 1998-09-11
Granted: 2000-11-01
Abstract: A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.
Patent TW-588051-B (TW)
Title: Novel 5-membered ring heterocycles, their preparation, their use and pharmaceutical preparations comprising them
Inventor: WEHNER VOLKMAR
IPC: A61P1/00
Filed: 1998-09-25
Granted: 2004-05-21
Abstract: The present invention relates to compounds of the formula I, in which B, E, W, Y, Z, R, R2, R2a, R2b, R3, g and h have the meanings indicated in the claims. The compounds of the formula I are valuable pharmaceutical active compounds, which are suitable, for example, for the therapy and prophylaxis of inflammatory disorders, for example of rheumatoid arthritis, or of allergic disorders. The compounds of the formula I are inhibitors of the adhesion and migration of leucocytes and/or antagonists of the adhesion receptor VLA-4 belonging to the integrins group. They are generally suitable for the therapy or prophylaxis of illnesses which are caused by an undesired extent of leucocyte adhesion and/or leucocyte migration or are associated therewith, or in which cell-cell or cell-matrix interactions which are based on interactions of VLA-4 receptors with their ligands play a part. The invention furthermore relates to processes for the preparation of the compounds of the formula I, their use in the therapy and prophylaxis of the disease states mentioned and pharmaceutical preparations which contain the compounds of the formula I.
Patent TW-419876-B (TW)
Title: Apparatus and method for producing high voltage to ionize gas
Inventor: SEBALD THOMAS
IPC: H01J27/08
Filed: 1998-10-13
Granted: 2001-01-21
Abstract: An apparatus for producing ions in gas is formed by an ion emitting electrode, opposite electrodes, and a high voltage generator. The high voltage is produced by heating and cooling the pyroelectricity material.
Patent TW-408218-B (TW)
Title: Optical density measuring apparatus
Inventor: HIGASHI NOBORU
IPC: G01N21/35
Filed: 1998-10-28
Granted: 2000-10-11
Abstract: An optical system for measuring an optical density of a sample in which homogeneity of light employed for measuring the density thereof is secured by including optical information upon a light source (0) uniformly inside a measurement space about an optical axis (P) therein even if the fluctuation occur in the light source in the system. A beam of light (I1, I2) emitted from the light source (0) and then focused on an interference filter (F1) is transformed into a parallel light through a collimator lens (L2), and the parallel light is then split into two parallel pencils of light by an optical mask (M1). The parallel light uniformly includes the optical information upon the light source. A reference cell (C1) is placed in a first split parallel pencil of light, and a sample cell (C2) is placed in a second split parallel pencil of light. The lights that have passed through the two cells (C1, C2) are focused on an optical receiver (R) by a focusing lens (L3).
Patent TW-396409-B (TW)
Title: Semiconductor device and method for manufacturing the same
Inventor: TERAUCHI TAKASHI
IPC: H01L21/60
Filed: 1998-12-08
Granted: 2000-07-01
Abstract: A semiconductor device is formed by a stable self-aligned contact process. It has a suitable structure to prevent contact electronic resistance on the contact area. The semiconductor device has an oxide film 26 formed on a silicon substrate and a layout pattern 34 formed on the oxide film. On and surround the layout pattern, an upper nitride film 36 and a surrounding nitride film 38 are formed. After the deposition of oxide film 40 between layers, a contact hole is formed by applying self-aligneded method. Then, an isotropic etching proceeds removes the oxide film 26's surrounding part 32 to below the surrounding nitride film 38. Inner diameter of bottom contact hole 42 is enlarged by the said isotropic etching to form contact 44.
Patent TW-420767-B (TW)
Title: Compact camera
Inventor: KOBAYASHI KIYOTAKA
IPC: G03B9/08
Filed: 1999-01-25
Granted: 2001-02-01
Abstract: A compact camera has a camera case that covers up more than half of a camera body in a resting position where the camera case covers a taking lens, a flash projector, a battery chamber and a cartridge chamber. By sliding the camera case to a working position uncovering the taking lens and the flash projector, the flash projector springs up to a flashing position, and a main switch is turned on. Then, a lens barrel is protruded out of the camera body. Locking mechanisms are provided to stop the camera case at the working position. The camera case is allowed to move from the working position to the resting position by stowing the flash projector into the camera body. The camera case is allowed to move from the working position in an uncoving direction by operating a knob that is mounted in a room provided inside the battery chamber. The battery chamber is located behind the flash projector in the stowed position, and a battery chamber lid and the flash projector are mounted rotatable about the same axis. A door opening mechanism is provided for opening and closing a door member of a photo film cartridge loaded in the cartridge chamber in cooperation with sliding movement of the camera case. The door opening mechanism is interconnected with a ratchet lever such that the ratchet lever stops the camera case at a safety lock position where it is impossible to open the cartridge chamber, so long as the door member is open.
Patent TW-533570-B (TW)
Title: Method for forming passivation on copper
Inventor: LIOU JUNG-SHI
IPC: H01L23/522
Filed: 1999-04-16
Granted: 2003-05-21
Abstract: The present invention discloses a method for forming passivation on copper so as to increase the anti-oxidization capability of copper components (such as interconnect and plug). The method includes the following steps: (a) providing a semiconductor substrate formed thereon a copper component; (b) performing a reduction procedure to the copper component by ammonia plasma; (c) forming a copper silicide layer on the exposed surface of the copper component; and (d) depositing a protection layer including silicon nitride on the copper silicide layer.
Patent TW-515025-B (TW)
Title: Manufacturing method of capacitor with low voltage coefficient
Inventor: PANG SHU-KOON
IPC: H01L27/06
Filed: 1999-05-14
Granted: 2002-12-21
Abstract: A kind of manufacturing method for capacitor with low voltage coefficient is disclosed in the present invention. The first dielectric layer is formed to cover the substrate that has the first electrode. The second electrode is formed to cover part of the first electrode. The second electrode structure, from bottom to the top, is composed of a doped polysilicon layer, a silicide layer and the second dielectric layer. A flattened insulation layer is formed and is followed by forming two contact windows in the insulation layer and the second dielectric layer as well as the insulation layer and the first dielectric layer, respectively, so as to expose the surfaces of the silicide and the first electrode.
Patent TW-I237563-B (TW)
Title: Pharmaceutical composition elevating pyruvate dehydrogenase (PDH) activity and process for their preparation
Inventor: BUTLIN ROGER JOHN
IPC: C07D263/46
Filed: 1999-05-29
Granted: 2005-08-11
Abstract: The use of compounds of the formula (I), and salts thereof; and pharmaceutically acceptable in vivo cleavable prodrugs of said compound of formula (I); and pharmaceutically acceptable salts of said compound or said prodrugs, wherein: ring C is phenyl or a carbon linked heteroaryl ring substituted as defined within; R1 is an ortho substituent as defined within; n is 1 or 2; A-B is a linking group as defined within; R2 and R3 are as defined within; R4 is hydroxy, hydrogen, halo, amino or methyl; in the manufacture of a medicament for use in the elevation of PDH activity in warm-blooded animals such as humans is described. Pharmaceutical compositions, methods and processes for preparation of compounds of formula (I) are also described.
Patent TW-476776-B (TW)
Title: Orange dye mixtures of fiber-reactive azo dyes
Inventor: PEDEMONTE RONALD P
IPC: C09B67/22
Filed: 1999-06-24
Granted: 2002-02-21
Abstract: The present invention concerns orange dye mixtures of fiber-reactive azo dyes, suitable for dyeing hydroxy- and/or carboxamido-containing material such as cellulose fibers, like cotton, or wool and nylon, which comprise one or more monoazo dyestuffs corresponding to the general formula (1) and one or more monoazo dyestuffs corresponding to the formula (2) in which D1 and D2 are each, independently from one another, a radical of a benzene or naphthalene nucleus, R1, R2, R3 and R4 are each, independently from one another, hydrogen, methyl, ethyl, methoxy, ethoxy, sulfo or carboxy, M is hydrogen or an alkali metal and the group Y1-SO2- and Y2-SO2- are each fiber reactive groups of the vinylsulfone series.
Patent TW-454278-B (TW)
Title: Semiconductor device, method of manufacture thereof, circuit board and electronic device
Inventor: HASHIMOTO NOBUAKI
IPC: H05K1/11
Filed: 1999-06-29
Granted: 2001-09-11
Abstract: A method of manufacturing a semiconductor device in accordance with the present invention comprises a first step of providing a substrate (12) provided with interconnection patterns (10) and covered with a protective layer (50) except those portions to be connected electrically with the electrodes (22) of a semiconductor element (20), and providing anisotropic conductive material (16) between the interconnection patterns (10) and the electrodes (22) on the substrate (12), the anisotropic conductive material extending to the protection layer (50) from the area where the semiconductor element (20) is to be mounted; and a second step of connecting between the interconnection patterns (10) and the electrodes (22) electrically by bonding the semiconductor element (20) to the substrate (12) with the anisotropic conductive material (16).
Patent TW-455773-B (TW)
Title: System on chip (SOC) four-way switch crossbar system and method
Inventor: SPADERNA DIETER W
IPC: H03K17/00
Filed: 1999-08-25
Granted: 2001-09-21
Abstract: A system on chip (SOC) has been provided which includes a crossbar switch between 64 functional I/Os internal to the chip, and 40 external connection pins. The crossbar switch permits a signal at any of the 64 functional I/Os to appear at any of the connector pins. The cross bar switch, permitting signals as the 40 connector pins to appear at any of the 64 specified functional I/Os. Because the switching is done with 4-way switches, the total number of hierarchical switch layers is reduced to 3. A parallel, opposite oriented, network of switches permits input signals delivered to the physical I/Os to be switched to any of the 64 functional I/Os. The small number of switch layers permit connections to be made with a minimum of delay across the switch. A method corresponding to the above-described crossbar switch system is also provided.
Patent TW-472395-B (TW)
Title: Semiconductor integrated circuit
Inventor: MIKI ATSUNORI
IPC: H03K19/0944
Filed: 1999-08-30
Granted: 2002-01-11
Abstract: The subject of the present invention is to switch the switching circuit even when the voltage of power source is very low in order to supply the required voltage to the output node. The solving means of the invention is provided with the followings: N-type transistor M3 on the triple-layered well region, in which source and substrate are connected together, and the drain is connected to the first voltage source while the first switching signal is applied to the gate; N-type transistor M2 on the triple-layered well region, in which the drain is connected to the source of transistor M3, and the second voltage source is connected to the source and the substrate while the second switching signal is applied to the gate; and a circuit, which is used to actuate either the first switching signal S1 or the second switching signal S2 such that either the first or the second voltage is selected from the first or the second voltage source, which is then applied to the output side.
Patent TW-550071-B (TW)
Title: Denaturants for sympathomimetic amine salts
Inventor: BESS WILLIAM S
IPC: A61K31/135
Filed: 1999-09-10
Granted: 2003-09-01
Abstract: The instant invention makes impractical the use of sympathomimetic amine compositions in illicit drug production. More specifically, the preparation of methamphetamine from the disclosed pseudoephedrine hydrochloride formulations is inhibited. The present invention defines pharmaceutical compositions comprising a sympathomimetic amine salt and at least one combination inhibitor, the combination inhibitor which acts both to interfere with the isolation of the sympathomimetic amine from the composition and to interfere with the conversion of the sympathomimetic amine to another pharmacologically active compound. The contemplated compositions may also include reaction and separation inhibitors in any mixture to assure maximum protection against the use of the sympathomimetic amine-containing compositions for illegal drug manufacture. The presence of the combination, reaction and separation inhibitors does not significantly alter the release of the sympathomimetic amine from the composition.
Patent TW-452680-B (TW)
Title: Electrical circuit, semiconductor integrated circuit device, circuit design method, record media and data distribution method
Inventor: MIZUNO HIROYUKI
IPC: H03L7/18
Filed: 1999-10-16
Granted: 2001-09-01
Abstract: In the conventionally known semiconductor device having macro, skew is generated between the latch clock provided for the inside of its main circuit and the latch clock provided for the inside of macro. Because these clock skews can prohibit clock frequency of semiconductor device from being made to become high frequency, semiconductor device is made unable to operate at high speed. A kind of semiconductor device has the followings: the first clock processing mechanism 101, which inputs the first clock 120 as well as the second clock 104, and makes the first and the second clock be in phase with each other and have the same frequency in order to generate the third clock 102; the second clock processing mechanism 111a, which inputs the third clock 102 as well as the fourth clock 114a, and makes the third and the fourth clocks be in phase with each other and have the same frequency in order to generate the fifth clock 112a; and, the first latch group and the second latch group, which are composed of latches. In this case, the second clock is generated from the third clock through a buffer or frequency divider 103. The fourth clock is generated from the fifth clock through a buffer or frequency divider 113a. The third clock is supplied to the first latch group through a buffer and the fifth clock is supplied to the second latch group through a buffer.
Patent TW-424325-B (TW)
Title: DRAM cells and method for making the same
Inventor: HUANG JENN-MING
IPC: H01L27/108
Filed: 1999-11-06
Granted: 2001-03-01
Abstract: The present invention provides a novel DRAM cell of the giga bit generation and a method for making the same. The method comprises forming a conductive plug, forming an isolated insulating layer, in which a self-aligned technique is used to enable the internal structure of the element can be scaled so that the memory cells have a consistent electric property, and other isolation layer will not be damaged when performing the production process of the self-aligned contact. When the isolation layer is damaged, the isolation effect will be affected and a leakage current may occur. The void formed due to an excessive aspect ratio during the deposition of the insulating layer can be used as a best isolation, and the insulating material used by the insulator can greatly reduce the parasitic capacitance in the wordlines and bitlines of the memory cells.
Patent TW-464830-B (TW)
Title: Approaching process method of digitized vector font
Inventor: CHEN FRED HUAI-YAN
IPC: G06K11/00
Filed: 1999-11-26
Granted: 2001-11-21
Abstract: The invention relates to an approaching process method of digitized vector font, which is used to process a set of line segments obtained from the conversion of font model and makes it become the set of digitized vector approaching to line segment with terrific look and compact data size. The invention determines the best end points of a vector line segment by means of the approaching tolerance of each line segment node for constructing any vector line segment and the sum of the integral of percentage shared in the vector line segments, capable of reducing the accumulated tolerance effect of each line segment node, to acquire better approaching quality. Together with the point-to-point approaching process means from the tailing node to the heading node of the set of line segments, the minimum vector line segments of vector font can be acquired to achieve the goal of data amount reduction.