Patent GB-1169095-A (GB)
Title: Improved Interface System for Digital Computers and Serially Operated Input and Output Devices
IPC: G06F3/09
Filed: 1967-02-21
Abstract: 1,169,095. Buffer register. WESTING- HOUSE ELECTRIC CORP. 21 Feb., 1967 [25 March, 1966], No. 8115/67. Heading G4C. [Also in Division H3] An interface system comprises a buffer register 38, a source 14 of serial data signals, synchronizing means enabling transfer of data between the source and the register and means enabling transfer of data between the register and a data processing device. As described a start signal from a teletypewriter (R.T.M.) causes relay 18 to enable an AND gate 56, set in INPUT MODE SWITCH, and start a transister oscillator and a one shot multivibrator which ensures a sequencer 38 commences in its correct state. The sequencer is driven by signals from the oscillator to enable appropriate gates at successive times corresponding to the various bit signals from the teletypewriter. Thus signal A.B. corresponds to bit time 1, B.C. to bit time 2 and C.D. to bit time 8. The serial data passes coupling device 42 and whichever AND gate 40 is enabled to be appropriately stored in a silicon controlled rectifier register 32. The data can then be read out in parallel via AND gates 46 and INPUT TRANSFORMER CIRCUITRY to a computer 12. Data can be read in parallel from the computer via the OUTPUT TRANSFORMER CIRCUITRY and OR gates 44 into the S.C.R. register and then via AND gates 46 enabled at the appropriate bit period by SEQUENCER 38 to the OR gate 48 to operate a relay DRIVER 50 and RELAY 24 to return data to the teletypewriter. At the end of each operation the S.C.R. register is reset via OR gate 57. The circuits forming the register are illustrated in Fig. 2. only one of the eight S.C.R.'s 74 being shown. Pulses from the teletypewriter operate the relay 18. Transister 70 is normally conducting except when a timing pulse is applied at terminal 72. Thus junction 80 may be held at earth or at a potential determined by resistors 86, 82, 109 and a voltage source. Diodes 73, 76, 78 form an AND gate, operated during the appropriate bit time when a "1" or mark is applied via diode 78. The voltage at 80 is sufficient to cause the S.C.R. 74 to conduct and store a "1". Alternatively a "0" at 58 holds junction 80 at earth, the S.C.R. doesn't conduct and stores a "0". Similarly a "1" in the computer when a pulse is passed through transformer winding 114 induces at "1" in winding 110 and also causes the S.C.R. to conduct. A "0" causes the energy in winding 114 to be absorbed and prevents a signal being induced in winding 110. Similarly a read-out pulse in winding 100 causes an appropriate read-out signal to be induced in winding 102. The S.C.R. is held conducting by current supplied via resistor 89 thus back biasing diode 90 since junction 84 is held at a low potential except at the bit time corresponding to the inputs supplied to the AND gate formed by diodes 74, 76. Thus at the appropriate time each S.C.R. can be read out via an OR gate formed by diodes 120 to operate relay 24 each space signal overcoming the potential applied by Zener diode 118 to drive the transistor conductive to open contact 16 of the relay. A CLEAR SWITCH 91 can be operated to reset all the S.C.R's. Diodes 103 ensure holding current diversion through the CLEAR SWITCH 91 when it is made conductive.