Patent GB-1118054-A (GB)
Title: Computer memory circuits
Inventor: SHIVELY RICHARD PAUL
IPC: G11C11/14
Filed: 1965-10-27
Abstract: 1,118,054. Matrix stores. LITTON INDUSTRIES Inc. 27 Oct., 1965 [10 Nov., 1964; 1 March, 1965], No. 45578/65. Heading G4C. [Also in Division H3] A computer memory circuit comprises a bi-stable circuit formed from a controlled semiconductor rectifier (or equivalent reciprocally coupled PNP and NPN transistors) so biased that simultaneous application of signals to the gate electrode and the anode/cathode path is necessary to switch it from its leakage current state to its holding current state. Fig. 7 shows an array of such circuits to be used as a storage matrix, each cell 150, 250, 350, 450 &o. comprising a circuit of the invention. When a " 0 " is stored, the SCR 168 passes leakage current only, transistor 154 being conducting and transistors 184 and 560 cut off. To write in a " 1 " a potential is applied to terminal 558 (or 658 &c.) to make transistor 560 conduct, together with diodes 170, 270 . . . corresponding to bits " one " of all the words. At the same time, a potential is applied to terminal 185 (or 285 &c.) to make transistor 184 conduct, corresponding to all the bits of word " one." The SCR 168 that represents bit " one " of word " one " is thus turned on and remains so after the energizing potentials have ceased, current flowing through transistor 154, the SCR and diode 182, the latter being biased conducting by source 178. To read-out non- destructively, a potential is applied to terminal 185 (or 285 &c.) to turn on transistor 184; the potentials of the anode and cathode of the SCR then both drop, and the change is sensed at terminal 172 (or 372 &c.). After the termination of the read-out pulse, the SCR potentials rise again and the SCR remains conducting. To change a stored " 1 " to a " 0 " in all the bits of a word, a potential is applied to terminal 162 (or 262 &c.) to cut off transistor 154 and interrupt the current through all the SCR's of that word. The circuit may be made up in' integrated form. Modifications of individual storage cells.- The circuit of an individual cell is given in Fig. 5 (not shown). In Fig. 6 (not shown) the base-collector path of a transistor is connected across the gate and anode of the SCR to reduce the value of the gate leak resistor. In Fig. 1 (not shown), the diode 182 is replaced by a resistor to a negative source. The transistor 184 has its base connected to the cathode of the SCR instead of its collector, and is used for reading out. The transistor 154 is replaced by a diode (or a switch for changing from stored " 1 " to " 0 "). Read-in is via a diode to the anode of the SCR in combination with a signal on the gate. A read-out signal is also applied to the SCR anode, and if the latter is conducting, transistor 184 saturates and its collector voltage shows a " 1." In Fig. 3 (not shown), this read-out transistor is replaced by a diode and series resistor. Modification of matrix.-In Fig. 4 (not shown) there is described a three-dimensional matrix formed of cells as in Fig. 1, selective switching of the SCR being performed by (a) switching signal to gate, (b) switching signal to anode, and (c) switching the read-out transistor. The bi-stable circuits themselves form the subject of Specification 1,118,055.