Patent GB-1000498-A (GB)
Title: Improvements in or relating to information processing systems
IPC: H04Q11/04
Filed: 1964-01-30
Abstract: 1,000,498. Digital data storage. SIEMENS & HALSKE A.G. Jan. 30, 1964 [Jan. 31, 1963], No. 4091/64. Heading G4C. [Also in Division H4]  In an arrangement for intermediate storage of information, and in which items of information belonging to different groups may arrive in any order, two stores are provided having corresponding sections, in one of which the information item is stored, and in the other the identity of the group to which the item belongs. As an item of information is received it is entered into the first free section after that in which the last item of that group is stored. The information of a group may then be taken out in the order in which it was received. As described the invention is described with reference to a telephone exchange system in which digits, received from a subscriber by push-button " dialling," are stored prior to being extracted one at a time for onward transmission to another exchange in decade pulsed form. In this case, as described, the group identity is the identity of the inter-exchange line used for the connection. It may, however, instead be the identity of the digit receiver in question. The " sections " of the stores are pulse positions in combinations of circulating delay lines. Receipt of digits.-Fig. 4 illustrates a time division highway MS to which subscribers Tn, digit receivers MM and exchange lines All . . . Aly have access. Circulatory store Ub contains addresses of called subscribers, and a further store (not shown) contains addresses of calling lines. Store Uk contains addresses of inter - exchange lines. A calling subscriber is allocated a digit receiver, and on receipt of an interexchange prefix the digit receiver inserts the pulse associated with the connection in store Ug. Counter KG emits cyclically a different exchange line address, dwelling on each for two multiplex cycles. In the first cycle, comparator Vk tests if the address is already in Uk (i.e. is busy) and if not opens Gkv for the second cycle, during which the pulse in Ug opens Gkg to admit this address at the appropriate pulse phase into store Uk. Meantime the digit receiver has arranged that all subsequent digits (for onward transmission to the next exchange) should be inserted in store Z, gate Gbi being arranged at the same time to gate out the inter-exchange line identity to store K. Intermediate storage, Fig. 1.-The first digit is received in Z and the associated information (inter-exchange line address) is received in K. At the beginning of an even cycle trigger Szi operates to enable Gzi which is thereupon enabled at the first free pulse position in ZPS to accept the digit stored in Z. Simultaneously Gki opens to accept the associated information into KPS. A marker pulse is also inserted into store LPS. This marker indicates the position of the latest information so far received which is associated with the particular information stored in KPS. When the next digit relating to the same associated information is received in Z, then during an odd cycle, comparator Vi compares K with all the addresses in KPS and when identity is accompanied by a marker pulse from LPS, Glz opens to set Slz. This inhibits the setting of Szi at the beginning of the even cycle. Szi must now wait for the duration of one multiplex cycle whilst the Glz pulse passes through delay line IT whereupon it is set to enable the information to be stored in the next free pulse position. A new mark is also inserted at this phase in LPS, the old being deleted by the output of the comparator Vi. This information is stored in KPS, the order in which it is received, interspersed with other information, the items of one set of information being identified by being accompanied by the same entry in KPS. Pulsing out of digits.-When the scanner KG, Fig. 1, reaches the inter-exchange line identity, a signal is received on lead be, as described below, indicative of the pulse phase of the connection to that line. This causes the enablement of gate Gbe during the even cycle, and during this cycle, comparison at Ve of the scanned address KG and the first of those in KPS causes a pulse via Gb, Gbe to open Gze to read out the first digit to store ZZS. Two periods after the receipt of the line pulse position on be, gate Gpz opens to feed the stored digits in that pulse position, in complementary form, to store BDZ, Fig. 3, and simultaneously a pulse is inserted in UPZ. Terminal zi emits pulses at 100 m.sec. intervals and these open Udg to pass the channel pulses to step the counter BDZ, which when counted out, deletes the pulse from UPZ. The pulses from Vdz are also gated by a gate such as SZ1, opened in synchronism, to a pulse lengthener AS which thus passes the digits as pulses of the correct duration to the inter-exchange line All. When the digit is counted out a pulse is entered in UPL via UGl opened once every 400 m.secs. by pulses from li. Just prior to the next li pulse ei is pulsed to pass the UPL pulse via UGb to gate UGbe. Provided the comparator Vk (Fig. 4) is still giving a comparison up is pulsed at this time and so be is energized so enabling the circuit of Fig. 1 to pass the next stored digit for onward transmission. Incoming pulsed digits.-Mention is made of the use of the circuit of Fig. 3 for counting incoming pulses received over ej and converted into binary form as combinations of markings on leads ad. In this case a different position of the counter is used for the " counted out " position so as to disable the operation of the intertrain pause counter at the bottom of the Figure.