Patent SG-11201900966T-A (SG)
Title: Semiconductor devices employing field effect transistors (fets) with multiple channel structures without shallow trench isolation (sti) void-induced electrical shorts
Inventor: XU JEFFREY
IPC: H01L29/06
Filed: 2017-09-14
Abstract: 1) 316(1), 318— 310(2),__ `320(2) 312(1), 314 12(2). 314 0 308(1) 308(2) 304 312(3), 306(3) 314316(3), 322(1) 306(2) 322(2) 318 306(1) 310(3) 316(4), 318 312(4), 314 310(4) 302(2) FIG. 3 302(1) 306(4) ') 306(5) 306(6) (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 22 March 2018 (22.03.2018) omit n OH E 100111111011001101101101110#011 (10) International Publication Number WO 2018/053090 Al WIPO I PCT (51) International Patent Classification: H01L 21/762 (2006.01) H01L 29/06 (2006.01) (21) International Application Number: PCT/US2017/051505 (22) International Filing Date: 14 September 2017 (14.09.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/266,214 15 September 2016 (15.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration, 5775 Morehouse Dri- ve, San Diego, California 92121-1714 (US). (72) Inventors: XU, Jeffrey, Junhao; 5775 Morehouse Dri- ve, San Diego, California 92121 (US). YANG, Haining; 5775 Morehouse Drive, San Diego, California 92121 (US). YUAN, Jun; 5775 Morehouse Drive, San Diego, Cali- fornia 92121 (US). RIM, Kern; 5775 Morehouse Drive, San Diego, California 92121 (US). CHIDAMBARAM, Pe- riannan; 5775 Morehouse Drive, San Diego, California 92121 (US). (74) Agent: TERRANOVA, Steven, N.; Withrow & Terrano- va, PLLC, 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, (54) Title: SEMICONDUCTOR DEVICES EMPLOYING FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE CHANNEL STRUCTURES WITHOUT SHALLOW TRENCH ISOLATION (STI) VOID-INDUCED ELECTRICAL SHORTS (57) : Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to [Continued on next page] WO 2018/053090 Al MIDEDIMOMOIDEIREEMOOMMILIMMOMMEHOIS KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.