Patent GB-1310772-A (GB)
Title: Telecommunication line multiplexer
IPC: H04J3/16
Filed: 1971-07-27
Abstract: 1310772 Digital transmission; multiplexing INTERNATIONAL BUSINESS MACHINES CORP 27 July 1971 35060/71 Heading H4P A telecommunication line multiplexer comprises a plurality of bit buffer stores each connectible to a different plurality of telecommunication lines, a plurality of character buffer stores to each of which is connected at least one bit buffer store, and a multiplexer control unit which is arranged in operation successively and repeatedly to be connected to the character buffer stores for the transfer of message and control information, characterized in that the bit buffer stores are associative stores holding function tables whereby data bits are transferred between the bit buffer stores and the connected telecommunication lines under the control of programmes selected by tablelook-up operations, the tables being such that lines with different transmission rates can be connected to the same bit buffer. A plurality of bit buffer stores 10 are connected to lines 11 through interfaces 12 each of which is a cyclic shift register having stages 13 each connected to a line 11 and one stage to store 10. As information is circulated store 10 is connected successively to each line 11. Data can flow both ways between 12 and 10 also 11 and 10 so that transmission and reception can be proceeding concurrently on different lines. The main function of store 10 is to provide temporary storage and execute control by table look-up selection and comprises a number of line buffer registers each uniquely associated with a line 11. Character buffer stores 13 sequentially scan line buffers either for the purpose of bit-by-bit transfer or assembly of received bits into a character. Store 10 may also exercise line control and store 14 character control the latter being connected sequentially by line scheduler 14 for fixed periods of time to enable transfer of control information and message characters. Synchronism within the arrangement is maintained by a clock 20 but its output is not supplied to the elements as a train of pulses but is coded at 21 into the form required. Lines transmitting data at differing rates may be connected to the same interface 12 with certain restrictions; i.e. start-stop signals and bit synchronous signals cannot be connected to the same interface nor can bit synchronous lines clocked at modems with those clocked by a multiplexer. Units 10, 14, 16 are preferably identical and difference in operation is adjusted by means of function tables. Units 10, 14 may be single associative stores similar to that disclosed in Specification 1,186,703 and unit 16 may include several stores and a control store. Definition of search and read/write fields is by means of a mask which blanks off all except the search field, but due to complexity of operations two masks are used in each cycle, one for the search phase and the other for the read/write phase. If a mask store holds 16 mask pairs, four control bits are necessary to define each pair. Each store 10 executes a 3-cycle loop during each period of clock 20. In the first cycle a search-read operation is executed and data representing the status of the line as the previous sample time is read to input/output register. In cycle 2 the search-next-read operation is performed and line status is updated. In cycle 3 the search-write operation is carried out and data representing present status of the line is restored. Fig. 3 (not shown) illustrates the arrangement of tables for controlling data to start/stop lines on a bit basis and, Fig. 4 (not shown), for synchronous lines on a character basis. Detailed operation of the invention is described in the Specification.