Patent GB-1433069-A (GB)
Title: Amplifiers
IPC: H03G3/10
Filed: 1974-03-06
Abstract: 1433069 Transistor differential amplifier; P.C.M. encoding WESTERN ELECTRIC CO Inc 6 March 1974 [12 March 1973] 9991/74 Headings H4T and H3H In a differential amplifier including first and second transistors 15, 18 the base of at least one of the transistors is for receiving an input signal 1, first means 6 is connected to feed current to a constant current regulator 10 and is serially connected to the collector emitter paths of the transistors, the impedance of the first means is variable in response to variations in the magnitude of the input signal 1 to vary the bias current of the differential amplifier and second means 7 is connected to feed current to the regulator whereby in operation the constant current maintained by the regulator 10 equals the current fed to the regulator by the first and second means 6, 7. The differential amplifier is shown in a current folder and coding circuit where a differential switch 21-24 functions to provide "folding" by obtaining a single polarity input to a comparator 25 regardless of the polarity of the alternating signal input 1. The coding of the analog input switch is obtained by comparing the voltages or currents proportional to the input analog signal with one of a plurality of reference voltages or currents generated by a weighting network 27. The results of this comparison are then fed to a logic circuit 26 for arrangement as a P.C.M. word. This weighting and coding network forms a digital to analog converter. Errors in amplitude of the output coded signal introduced in the weighting and coding network are reduced for low amplitude input signals 1 by the dynamic bias control circuit 4-9 which responds to the low amplitude input signals to reduce the conduction of current through a transistor 6. This reduces the current through the differential amplifier transistors 15, 16 so that I#R drops or errors produced in resistors in the weighting and coding network and transistor leakage current errors in the main coding paths such as 30, 27, 28, 21, 15, 17, 10 and 11 or 30 29, 22, 18, 20, 10 and 11 are reduced. Reducing the current flow in the main coding paths reduces the I#R drops or error due to variations between the resistances of resistor 28 and 29 and 17 and 20 to proportionally small value and also reduces the base emitter bias currents in each of transistors 15, 18, 21-24 to enable the coding to be performed with the required accuracy. Thin film techniques may be used. The longitudinal compensation circuit 30 compensates for large input voltage swings from 1 which cause the current through a transistor 30 to increase as a result of reduced current through a transistor 7 and increased current through the transistor 6. The effect is to keep the average voltage at the interconnection of the emitter of the transistor 30, the weighting network 27 and the resistor 29 relatively constant for large input voltages. The circuit could be used in an unfolder circuit with the weighting network interchanged with the input source 1 and the comparator 25 replaced by a differential operational amplifier. The Specification refers to copending Specification 1,433,070.