baber/WOPTO huggingface dataset:
Patent TW-438632-B (TW)
Title: Chemical spray system for semiconductor device fabrication facility and waste liquid tank used in the same
Inventor: CHOI DUG-KYU
IPC: B01J19/00
Filed: 1998-08-03
Granted: 2001-06-07
Abstract: There is provided a chemical spray system for semiconductor device fabrication facility and a waste liquid tank used in the same, wherein deionized water is supplied in a generator for suck-back and removing the developer present thereon so as to prevent the corrosion of the generator and confirm the supply of the deionized water helping the easy discharge of waste liquid, the chemical spray system comprising having a pipe connected to a nozzle for spraying chemicals on a wafer for suck-back, and a first opening/closing means installed on the pipe and for controlling the discharge of chemicals for suck-back into a waste liquid tank, the chemical spray system comprising: a generator installed on the pipe between the first opening/closing means and the waste liquid tank, and generating air flow toward the waste liquid tank for suck-back; a deionized water supply part installed between the first opening/closing means and the generator, and supplying deionized water to the generator by the absorbing capability by the air flow of the generator during the suck-back; and a deionized water control circuit receiving the opening/closing signal of the first opening/closing means and applying the signal for the deionized water supply to the deionized water supply part.
Patent TW-395028-B (TW)
Title: A metal fuse structure and a method of forming a terminal via in a fuse structure
Inventor: LEE GILL YOUNG
IPC: H01L23/525
Filed: 1998-08-05
Granted: 2000-06-21
Abstract: Disclosed are metal fuse structures and methods for making the same. The method includes forming the fuse structure from a metallization layer. Depositing a bottom oxide layer, that is an HDP oxide, over the fuse structure that is formed from the metallization layer. Depositing a doped oxide layer over the base oxide layer. Depositing a top oxide layer over the doped oxide layer. Etching through the top oxide layer. Detecting an increased level of a dopant species that is emitted when the doped oxide layer begins to etch. The method further includes terminating the etching when the increased level of dopant species is detected. Wherein at least the bottom oxide layer remains over the fuse structure that is formed from the metallization layer.
Patent TW-403913-B (TW)
Title: Integrate dram with high speed interleaving
Inventor: FANG HONG-GEE
IPC: G11C7/10
Filed: 1998-09-24
Granted: 2000-09-01
Abstract: An integrated circuit includes a controller and a memory to implement a graphics controller. The controller and memory are controlled by a common clock signal to operate synchronously with each other. The memory is organized in a plurality of storage arrays, organized in two banks. A set of bit-line sense amplifiers is provided for each bank. A pair of row decoders decode a row address to select a row of data from each bank. The selected row of data is received by a pair of bit-line sense amplifiers. A column decoder selects a column of data from the pair of bit-line sense amplifiers. A pair of multiplexers select one-half of the selected column in response to a HI/LO signal and then select the remaining half of the selected data in response to a change in value of the HI/LO signal. Main or data sense amplifiers amplify the output of the multiplexers to provide data outputs in the form of full swing signals.
Patent TW-486481-B (TW)
Title: Phosphine-substituted cobaltocenium salts, process for their preparation and their use as catalyst constituents
Inventor: SALZER ALBRECHT
IPC: C07F17/02
Filed: 1998-09-29
Granted: 2002-05-11
Abstract: Phosphine-substituted cobaltocenium salts of the formula I, in which R1 are identical or different and is hydrogen; alkyl or alkoxy radicals having 1 to 14 carbon atoms and furthermore cycloalkyl, aryl or aroxy radicals having 6 to 14 carbon atoms; a fused benzene ring, an acid amide radical -C(O)-NR2R3, in which R2 and R3 are identical or different and are hydrogen, alkyl radicals having 1 to 14 carbon atoms, or cycloalkyl or arkyl radicals having 6 to 14 carbon atoms; the carboxyl group or an ester radical -C(O)-OR4, in which R4 is an alkyl radical having 1 to 14 carbon atoms, or a cycloalkyl or aryl radical having 6 to 14 carbon atoms; n are identical or different and are an integer from 0 to 4; m is an integer from 1 to 3; and X is hexafluoroantimonate, tetraphenylborate, tosylate, tetrafluoroborate, triflate, trifluoroacetate, triiodide, tribromide, nitrate, perchlorate, sulfate, phosphate, sulfonate, -O-S(O)2-R5 in which R5 is an alkyl radical having 1 to 14 carbon atoms, a cycloalkyl or aryl radical having 6 to14 carbon atoms, or a carboxylate -O-C(O)-R6, in which R6 is hydrogen, an aklyl radical having 1 to 14 carbon atoms or a cycloalkyl or aryl radical having 6 to 14 carbon atoms, and a process for their preparation are described. These compounds are suitable as ligands for metal complexes which can be used as catalysts in chemical processes.
Patent TW-494273-B (TW)
Title: Lens-fitted photo film unit with protective cover
Inventor: MIKAMI YUJI
IPC: G03B19/04
Filed: 1998-10-02
Granted: 2002-07-11
Abstract: A protective cover (13) for a taking lens is provided in the front of a lens-fitted photo film unit. The protective cover cooperates with a shutter locking mechanism which locks a shutter button (4) when the protective cover is in a closed position in front of the taking lens. The protective cover also cooperates with a flash prevention mechanism which turns off a flash charge switch off when the protective cover moves in the closed position, prevents the flash charge switch from being moved to its ON position so long as the protective cover is in the closed position, and allows the flash charge switch to be moved to the ON position when the protective cover is moved away from the taking lens. The protective cover is slidable in a horizontal direction on a front surface portion of the film unit, and the front surface portion is straight in the horizontal direction. The protective cover has a vertical length that does not interfere with a bottom lid (12) that is provided for removal of an exposed photo filmstrip. A first label is stuck on a front surface of the protective cover, and a second label is wrapped around the film unit excluding the front surface portion the protective cover slide thereon, to decorate and dust-proof the film unit and reinforce the unit housing.
Patent TW-393607-B (TW)
Title: A method for reading and debugging of computer's peripheral storing device
Inventor: LIN GUANG-SHIN
IPC: G06F13/00
Filed: 1998-10-23
Granted: 2000-06-11
Abstract: This invention is a method for reading and debugging of computer's peripheral storing device, which uses the low level command of computer's operation system to replace the driver of peripheral storing device, to detect, read and correct the peripheral storing device by low level command directly through the operation system, so that the problems that a sector with a little damaged data in the storing media cannot be correctly read out, or even the whole storage media cannot be read due to a little damaged data when the driver is reading the peripheral storing device can be solved. This enables the peripheral storage device to be able of reading the most possible amount of data.
Patent TW-364039-B (TW)
Title: Arrangement in a two cycle combustion engine with internal combustion
Inventor: HENRIKSEN LEIF DAG
IPC: F02B75/24
Filed: 1998-10-23
Granted: 1999-07-11
Abstract: A combustion engine (10) has a number of engine cylinders (21-1 to 21-5) arranged in an annular series around a common middle drive shaft (11) with the cylinder axes running parallel to the drive shaft. Each cylinder includes a pair of pistons (44, 45) movable towards and away from each other, which work in a common, intermediate working chamber (K). Each piston (44, 45) forms-via a piston rod (48, 49) with associated support roil (53) support and control via a "sine"-plane ("sine"-curve 8a, 8b) in a cam guide device. The two pistons (44, 45) in each cylinder (21; 21-1 to 21-5) have mutually differing piston phases, which are controlled by mutually differing cam guide devices. The cam guide devices are designed with equivalent mutually differing "sine"-planes ("sine" curves 8a, 8b)
Patent TW-394883-B (TW)
Title: Method and system for computer access and cursor control using a relief object image generator
Inventor: DICKINSON ALEXANDER
IPC: G06F3/033
Filed: 1998-12-23
Granted: 2000-06-21
Abstract: A system  and method for using a relief object image generator for cursor control, computer access control, and operational parameter control is disclosed. The system includes a relief object image generator (10), a sensor array (72), an image processor, and a memory. The relief object image generator (10) generates images of relief objects, such as fingerprints, brought in proximity of the exposed surface of the image generator (10). The image processor receives the image from the sensor array (72), processes the image, and compares the resulting descriptive information to stored information corresponding to authorized users. If a match is found, the user is granted access to the computer. The image processor may also process the image to determine image movement or the image's  presence or absence. Detected movement is used to generate directional signals while the presence and absence of the image is used to generate highlight and select signals. These signals conform to those generated by known mouse devices so the system of the present invention can replace a position variable device in the keyboard of a laptop or other portable computer without sacrificing functionality for the system. Other uses of the system disclosed herein include control of operational parameters for a device such as brightness and contrast for a monitor and the transmission of relief object images to remote sites for authentication of a user.
Patent TW-416179-B (TW)
Title: Permanent magnet type electric motor
Inventor: NASHIKI MASAYUKI
IPC: H02K1/27
Filed: 1998-12-22
Granted: 2000-12-21
Abstract: The invention is relates to a permanent magnet type electrical motor. It has a N pole used magnetic line 5 that commonly connected to the permanent magnet 7; a S pole used magnetic lint 6 that commonly connected to the permanent magnet 7; the number R of N poles that has the shape of N protruding pole, that is a part of the N pole used magnetic line, and the number is different to the number m of the stator placed for the outside around the rotor. And R protruding pole shaped S pole magnets is part of the S pole magnet line, and placed for the perimeter around the rotor. And alternately placed for the direction of the motor's rotation to use as the motor can effectively use each permanent magnets.
Patent TW-404009-B (TW)
Title: The method of manufacturing self-aligned contact (SAC)
Inventor: LIN GUANG-MING
IPC: H01L21/60
Filed: 1999-01-27
Granted: 2000-09-01
Abstract: A manufacture method of self-aligned contact (SAC). A layer of insulated layer is formed and covered on top of the substrate after proceeding the etching step and forming the contact opening in the process of manufacturing the self-aligned contact (SAC); and filling up the thin gap produced in the thin oxide between the spacer and the gate structure when proceeding the etching step; next, remove part of the insulated layer using back-etch method to form an isolated layer to separate the gate structure and the contact opening to avoid the short-circuit phenomena of the device.
Patent TW-412848-B (TW)
Title: New method for manufacturing flash memory
Inventor: SUNG GUO-DUNG
IPC: H01L21/8242
Filed: 1999-02-01
Granted: 2000-11-21
Abstract: A method for manufacturing flash memory based on the combination of self-align source and shallow trench isolation processes is offered. After a spacer is formed at two sides of the control gate and the floating gate, the oxide in the shallow trench isolation structure between common sources is stripped, and the oxide on the substrate surface of the common source is also stripped to expose openings on the substrate surface. Then, a tilted spinning ion implantation process is utilized to form an ion implantation area in the exposed substrate, resulting in a common source line parallel to the control gates.
Patent TW-411570-B (TW)
Title: Manufacturing method of self-aligned contact
Inventor: TSAI TZ-JING
IPC: H01L21/768
Filed: 1999-02-02
Granted: 2000-11-11
Abstract: The invention provides a manufacturing method of self-aligned contact and includes the following procedures: (a) a conduction layer of the gate electrode, the silicon dioxide layer, and the first silicon nitride layer are sequentially formed on the silicon substrate in which the source/drain regions already formed; (b) the first silicon nitride layer, the silicon dioxide layer, and the conduction layer of the gate electrode are then selectively etched such that a trench is formed to expose the source/drain region; (c) a layer of borophosphosilicate glass is formed to fill in this trench and is extended to the surface of the first silicon nitride layer mentioned above; (d) a layer of photoresist is coated and patterned such that the location of the desired opening hole is exposed; (e) this layer of photoresist is used as the etching mask to remove the borophosphosilicate glass in the trench so that a self-aligned contact hole is formed; (f) the photoresist layer is then stripped; (g) the second silicon nitride layer is deposited and formed on the sidewall of the self-aligned contact; (h) an etch-back process is then conducted onto the second silicon nitride layer to form the nitride spacer. Based on this invention, the well known drawback of too small narrow opening can be avoided so as to make the process control easier.
Patent TW-451313-B (TW)
Title: Manufacturing method of gate electrode sidewall silicide
Inventor: LI JUNG-SHIUNG
IPC: H01L21/336
Filed: 1999-02-08
Granted: 2001-08-21
Abstract: This invention provides manufacturing method of gate electrode sidewall silicide, which includes: firstly, forming a gate oxide layer and then a conductive layer on a given semiconductor substrate; forming a gate electrode on the semiconductor substrate by defining the conductive layer; performing a low concentration ion implantation to form a lightly doped source/drain structure; forming a silicon nitride layer on the substrate; subsequently, etching back part of the silicon nitride layer to form a spacer; forming a source/drain area by using spacer and gate electrode as a mask to perform a high concentration ion implantation; removing the spacer to expose gate sidewall, and performing a salicide process.
Patent TW-414973-B (TW)
Title: Method of insulating devices in flat-cell mask ROM
Inventor: YOU JR-CHENG
IPC: H01L21/31
Filed: 1999-05-07
Granted: 2000-12-11
Abstract: A method of insulating devices in a flat-cell mask ROM is provided. The method comprises simultaneous forming a P-type light-doped region and a surface implanted insulating region. The method of the invention comprises providing a semiconductor structure having a region for forming MOS transistor, and a flat-cell with interlaced word lines and bit lines. A photoresist layer is formed on the semiconductor structure and exposes the PMOS transistor region and the flat-cell region. A P-type dopant is implanted on the PMOS transistor region and the flat-cell region to form the P-type light-doped region and a surface implanted insulating region.
Patent TW-436683-B (TW)
Title: Semiconductor device and process of producing the same
Inventor: IKEDA KOUICHI
IPC: H01L21/301
Filed: 1999-05-18
Granted: 2001-05-28
Abstract: An object of the present invention is to provide a semiconductor device and its manufacturing process that can reduce the fraction defective and that also enables the required steps to be simplified in case of manufacturing the semiconductor device which can be high density packaged. A plurality of semiconductor chips 1 (processor tip 1a and memory tip 1b) of the different types are formed on a semiconductor wafer 2 and are inspected for acceptability at a time. Then, the semiconductor device is manufactured by cutting the semiconductor device is manufactured by cutting the semiconductor wafer 2 into a set of the adjacent processor tip 1a and memory tip 1b side by side determined to be acceptable such semiconductor chips 1. Subsequently, this semiconductor device is mounted on the substrate 4 to manufacture a semiconductor module 10.
Patent TW-I228260-B (TW)
Title: Sorbent-based gas storage and delivery system for dispensing of high-purity gas, and apparatus and process for manufacturing semiconductor devices, products and precursor structures utilizing same
Inventor: HULTQUIST STEVEN J
IPC: B01D53/22
Filed: 1999-05-20
Granted: 2005-02-21
Abstract: A sorbent-based gas storage and dispensing system, including a storage and dispensing vessel containing a solid-phase physical sorbent medium having a sorbate gas physically adsorbed thereon. A chemisorbent material is provided in the vessel to chemisorb the impurities for gas phase removal thereof in the storage and dispensing vessel. Desorbed sorbate gas is discharged from the storage and dispensing vessel by a dispensing assembly coupled to the vessel. The chemisorbent may be provided in a capsule including an impurity-permeable, but sorbate gas-impermeable membrane, and installed in the vessel at the time of sorbent material loading. Semiconductor manufacturing processes and products manufactured by such processes are described.
Patent TW-387083-B (TW)
Title: Diffusing reflector and manufacture of the same and reflection type display apparatus
Inventor: KATAOKA HIDEO
IPC: G09F9/00
Filed: 1999-06-07
Granted: 2000-04-11
Abstract: There is provided a method of manufacturing a diffusing reflector which assures high diffusion efficiency and excellent reflection characteristic for the lighting. First, a resin film having photosensitivity is formed on a substrate 2. Next, gathering of pillar-shaped bodies isolated each other by the patterning of resin film with the photolithography is provided. Subsequently, the uneven surface layer having the maximum inclination angle under 12 DEG is formed by gently deforming individual pillar-shaped bodies with the heat treatment. Moreover, the gently deformed uneven surface layer is coated with the resin and the flat openings between pillar-shaped bodies arranged discretely are buried to ease the inclination angle. Finally, a metal film 13 formed on the gently deformed uneven surface layer.
Patent TW-448086-B (TW)
Title: Prevention of wafer breaking in the chemical mechanical polishing process
Inventor: JENG WEN-GUNG
IPC: H01L21/304
Filed: 1999-06-17
Granted: 2001-08-01
Abstract: This invention provides the method to prevent wafer breaking in the chemical mechanical polishing process for semiconductor manufacture. Surface tension between wafer and aqueous solution in the polishing platen is reduced during the dechucking of the wafer out of the platen by means of vacuum using wafer carrier in the planarization process of chemical mechanical polishing by increasing the water temperature or adding interface active agent. This decreases the wafer deformation when the wafer is under vacuum-suction and thus improves the otherwise serious wafer breaking situation.
Patent TW-410207-B (TW)
Title: Improvement on an impermeable and thermally insulating tank comprising prefabricated panels
Inventor: DHELLEMMES JACQUES
IPC: F17C1/12
Filed: 1999-07-08
Granted: 2000-11-01
Abstract: Impermeable and insulating tank built into a load-bearing structure, the tank having two successive sealing barriers alternated with two thermally insulating barriers, the secondary barriers and the primary insulating barrier consisting of a set of prefabricated panels, each panel comprising, in succession, a first rigid board, a first thermal insulation layer (104), a second thermal insulation layer (108), and a second rigid board, the junction regions between the primary insulating barrier elements of two adjacent panels being filled with insulating tiles each consisting of a thermal insulation layer (115) covered with a rigid board, the continuity of the secondary sealing barrier being provided in the junction regions of two adjacent panels by flexible strips (120) which are impervious to gas and to liquid, each strip being hermetically bonded to a secondary insulating barrier element of a panel by a lateral marginal region (120a) and to a secondary insulating barrier element of the adjacent panel by an opposite lateral marginal region (120b), so that its central region (120c), which covers the junction region, is free to deform elastically and/or elongate with respect to the insulating tiles.
Patent TW-445622-B (TW)
Title: Integrated circuit with electrical junctions which can be separated by energy-effect
Inventor: MOECKEL JENS
IPC: H01L23/525
Filed: 1999-07-29
Granted: 2001-07-11
Abstract: The integrated circuit has at least three electrical junctions (1, 2, 3) which can be separated by energy-effect. The central junction (1) is, viewed in either a first direction or a second direction perpendicular to the first direction, arranged between said two outer junctions (2, 3). The junctions are the components of a central conductive-track (10) or outer conductive-tracks (20, 30), which are mutually parallel and basically extend in the first direction. Each outer conductive-track (20, 30) has at the height of the central junction (1) an offset that is far away from the outer conductive-track and at the height of the outer junctions (3, 2) of other outer conductive-track (30; 20) an offset that is towards the outer conductive-track. The central conductive-track (10) has at the height of said two outer junctions (2, 3) an offset that is far away from the central conductive-track (10).
Patent TW-447114-B (TW)
Title: Semiconductor device and the manufacturing method thereof
Inventor: TORII KAZUNARI
IPC: H01L21/02
Filed: 1999-08-10
Granted: 2001-07-21
Abstract: The object of the present invention is to provide a method preventing the reaction of the inter-layer insulation layer with the high ferroelectric film and suitable for highly integrated micro-memory cell structure. In the present invention, the structure is to insert a reaction preventing layer 43 between the high ferroelectric film 71 and the inter-layer insulation layer 32; and, the sidewall of the diffusion stop layer 51 is not directly contacted with the high ferroelectric film 71; therefore, the invention can eliminate the reaction of the inter-layer insulation layer 32 and the high ferroelectric film, and preventing the film peeling of the high ferroelectric film 71.
Patent TW-463257-B (TW)
Title: Heat treatment apparatus and cleaning method of the same
Inventor: SAITO YUKIMASA
IPC: C23C16/44
Filed: 1999-11-26
Granted: 2001-11-11
Abstract: A semiconductor wafer (15) is contained in a reaction tube (11), and the reaction tube (11) is exhausted through an exhaust pipe (63) while supplying ammonia and dichlorosilane into the reaction tube (11). A silicon nitride film is deposited on an object to be heat-treated by a reaction of ammonia and dichlorosilane. Subsequently, TEOS is supplied into the reaction tube (11), while the reaction tube (11) is exhausted through the exhaust pipe (63). A silicon oxide film is deposited on the object by resolving the TEOS. A semiconductor wafer on which a laminated layer of the silicon nitride film and the silicon oxide film is formed is unloaded from the reaction tube (11). Then, reactive products attached into the exhaust pipe (63) and the reaction tube (11) are removed, by conducting fluoride hydrogen thereinto, thereby cleaning the pipes. The top end of the exhaust pipe (63) is split into two vents (71, 72), either one of which is used for discharging exhaust gas for forming films and the other one of which is used for discharging HF gas for cleaning the pipes.