Patent GB-1486424-A (GB)
Title: Data transmission
IPC: H04N7/085
Filed: 1974-11-19
Abstract: 1486424 Television MULLARD Ltd 19 Nov 1974 [21 Dec 1973 24 May 1974] 59464/73 and 23449/74 Heading H4F A television transmission system is adapted to transmit binary data within a normal television video signal. Only one bit of binary data is inserted into the back porch of each line blanking period of the video. The binary states are produced either by: on/off pulses; long or short colour bursts; bi-phasal pulses; or bifrequency pulses. The bit information is clocked into the back porches under the control of clock pulses derived from the line sync pulses suitably delayed. Fig. 1 shows a transmitter in which normal video from a source 4 is applied to an amplifier 1. The line sync pulses, extracted from the video, are applied to: a delay 2 and subsequently to a data source 5 having an associated keyboard or other data selection means 5<SP>1</SP>; and an AND gate 3 to which the data bits from source 5 are also applied. The AND gate output is also applied to amplifier 1 where it is inserted in the video prior to application of the composite data/video signal to an output stage 12. Fig. 2 shows a receiver having a conventional video detector stage 16. Line sync pulses are extracted from the video and delayed at 15 before passing to AND gate 14 which also receives the composite video, D.C. level corrected by comparator 13. The delayed line sync pulses clock the data bits out of the video. The bits pass to a decoder 17 which also receives the delayed line sync pulses which in turn clock the decoded data into a memory 18 operable in known manner to produce a display either superimposed on the video at 19 or on a separate display 19<SP>1</SP>. In cases of poor reception pulse detection may be difficult, an alternative embodiment Fig. 3 (not shown) utilizes an integration circuit to form the integrand of the back porch under the control of delayed line sync pulses extracted from the received video. The integrand is applied to a comparator for bit analysis prior to decoding and storing of the binary data. A further embodiment Fig. 5 is arranged specifically for character display, whereby a viewer may select any of a plurality of captions for superimposed display on unit 19. Field and line sync pulses Fp and Lp are extracted from the video by unit 37. The composite video is applied to display unit 19 and bit extractor 36 via unit 16. The data bits are extracted under the control of the line sync pulses Lp acting as clocking pulses. The bits are applied to a series to parallel converter 38, which is interrogated by an address recognition unit 39 in accordance to the required caption address fed to it from a viewer operated caption selector 40. Converter 38 feeds two 32 x 6 bit caption row stores 41, 42 the outputs of which are multiplexed 43 to a character generator 44. Timing circuit 45 controls the entire operation under the influence of the line and field sync pulses. Circuit 45 also clocks row counter 46 and shift register 47 to obtain characters from the generator 44 for display on unit 19. A suitable transmission format employs 8 bit character words ASCII coded. Each caption display consists of two 32 character rows, a single two row caption being transmitted during two fields. Each caption is updated every two seconds so there is a choice of 50 different captions. In each field lines 20 to 284 contain data bits, those in lines 20 to 26 identify the caption and the bit in line 27 the caption row. Bits from lines 28 to 284 identify the 32, 8-bit character string of the caption row.