Patent GB-750475-A (GB)
Title: Arithmetic units for digital computers
IPC: G06F7/505
Filed: 1951-10-10
Abstract: 750,475. Digital electric calculating-apparatus. HUGHES AIRCRAFT CO. Oct. 10, 1951 [Oct. 10, 1950], No. 23628/51. Class 106 (1). An electronic computer for performing a mathematical operation upon N binary digits each represented by a primary and a complementary electric signal, comprises 2N input terminals to which the signals are applied, a network including " and " and " or " circuits, and at least one output terminal at which is produced an electric signal representing the result of the operation. The operations are expressed in the form of " Boolean equations " involving " logical " multiplications and additions which are performed by " and " and " or " circuits respectively which, as described, each comprise a crystal or thermionic diode network. The half-adder illustrated in Fig. 10, for example, produces result and carry signals R, C given by the equations where A, #A, B, #B are the primary and complementary (or inverted) input signals obtained from switches 1018, 1010 and battery B (which in a practical embodiment would be replaced by electronic switches). C is produced by " and " gate 8 which provides a large voltage drop across resistance Rc and thus a positive, output signal at terminal 1028 only if positive signals A, B (representing digits " one ") are applied to the cathodes of both diodes D1031, D1032 thus preventing conduction therethrough in the forward direction. Gates 6, 7 similarly produce positive output signals only if both A, B and both A, B respectively are positive (representing " one "), and these outputs are combined in " or " gate 9 comprising diodes D1041, D1042 to produce the R signal at terminal 1027. The same output signals may be produced by other networks corresponding to other equivalent forms of the equations, e.g. may be produced by four " or " gates and two and " gates, one of which has three inputs (Fig. 11, not shown). Fig. 12 shows a halfsubtractor in which C = A.B is produced by gate 6, and gate 8 is not required. Another form of half-subtractor also is described, and combined elements which add or subtract according to the position of a switch at an input to gate 8 or the output from gates 6 and 8. The half-adder shown in Fig. 16, in addition to producing signals R and C + by gates 6, 7, 8 as in Fig. 10, produces the complementary signals by means of further " and " gate 18 and " or " gates 20, 19. This arrangement may be further extended to produce a half-adder-subtractor (Fig. 17, not shown). Magnetic store.-The input signals for the computer elements may be obtained from a magnetic drum in which digits are represented by magnetic flux states. Any change in flux will cause a positive or negative pulse to appear at the output of a reading head, and if these pulses are employed to switch over a bi-stable trigger circuit, Fig. 2, e.g. of the Eccles-Jordan type, the output signal A at terminal a will correspond to the flux states on the drum, the complementary signal A being produced at the other terminal a. Series adders and subtractors.-In the series adder shown in Fig. 18, series-mode numberrepresenting signals from sources 1820, 1821 are supplied to a first half-adder 1812, similar to that of Fig. 16 but without gate 19, to produce outputs Ro, Ro and Co; Ro, Ro and the carry signals D, #D are supplied to a second half-adder 1813 to produce the result signal R and a carry signal C1. Signals Co, C1 are passed to " or " circuit 1815 and inverter 1814 to produce C = Co + C1 and the complementary signal #C which, after being delayed one digit period in circuit 1816, become the signals D, #D. Another form of full-adder is described (Fig. 19, not shown) which corresponds to the equations Extensions of this adder, for addition or subtraction, and for producing the complementary signals R, C (Fig. 21, not shown), also are described. In another form of carry delay circuit, Fig. 23, signals C, #C are applied to resistancecapacitance circuits the time-constants of which are so chosen that the signals indicated in lines 1 and 2, Fig. 24, cause the signals on lines 3 and 4 to be applied to " and " gates 2350, 2360 to which clock pulses, line 5, are applied from generator 2310. The gate outputs, lines 6 and 7, are such that, when applied to opposite sides of a bi-stable trigger circuit 2370, they produce at terminals 2374, 2375, lines 8 and 9, the signals D, #D i.e. the signals C, C delayed by one digit period. For example, the positive state of C (representing " one ") during the second digit period, line 1, Fig. 24, produces a signal, line 3, which due to its slow rise, gates the third, and not the second, clock pulse applied to gate 2350 thus switching trigger 2370 to the " one " state at the beginning of the third digit period. Since the trigger circuit will only change its state upon a change in the carry condition, and pulses such as the third and fourth in line 6, Fig. 24, are redundant, signal C given by equation (I) above may be replaced by C* = A.B and #C may be similarly replaced by #C* = #A.#B. A full-adder-subtractor which produces these modified carry signals, and similar signals for subtraction, is described, Fig. 26 (not shown). Parallel adders and subtractors.-Fig. 22 shows a parallel adder and/or subtractor comprising one half-adder-subtractor 220 and N-1 fulladders-subtractors 221-1 to 221-(n-1) (which may be of the forms referred to above in connection with Figs. 17 and 21, not shown, respectively) connected by carry-over lines 222, 223. The result signals R1-Rn and Rn + 1 appear simultaneously at result terminals 224-1 to 224-n and the carry terminal 225-n of the highest element 221-(n-1). The complementary result signals R1-Rn and Rn + 1 may also be produced. Reference has been directed by the Comptroller to Specification 685,218.