Patent SE-7508438-L (SE)
Inventor: SONG C-L
IPC: H04J3/00
Filed: 1975-07-24
Abstract: 1506262 Delta modulation; digital-to-analogue conversion NORTH ELECTRIC CO 22 July 1975 [25 July 1974] 30650/75 Heading H3H In a telephone system, analogue signals are converted into 56 kHz adaptive delta modulation signals, transmitted to a central office where they are converted to linear P.C.M. signals, digitally filtered, reduced in speed (by selecting every seventh word) to 8 kHz linear P.C.M. signals and then companded. At the receiving end, the companded P.C.M. signals are converted to linear P.C.M., increased in speed to 56 kHz by repeating each word seven times, digitally filtered, and converted to adaptive delta modulation signals for transmission to a subscriber where they are converted to analogue voice signals. The adaptive delta modulator, Fig. 3, includes a pattern detector 76, which may increase the step size on occurrence of 2 (or 3) consecutive identical bits in the output delta bit stream and decrease it on occurrence of 2 (or 3) consecutive alternations. Alternatively it may obey the 7-7-4-3 rule, i.e. if the last change in step size was an increase, 7 consecutive identical delta bits are required for a further increase but only 4 consecutive alternations for a decrease, and if the last change in step size was a decrease, 7 consecutive alternations are required for a further decrease but only 3 consecutive identical bits for an increase. Details of three pattern detectors are given, Figs. 9 to 14 (not shown). Details of the D-to-A converter 80 are given hereinafter. The conversion from adaptive delta modulation to linear P.C.M. is as shown in Fig. 4. The conversion from P.C.M. to adaptive delta modulation, Fig. 6 (not shown), involves a negative feedback loop including an arrangement similar to that in Fig. 4, and the final conversion to analogue is by means similar to the feedback path in Fig. 3, Fig. 7 (not shown). Digital-to-analogue conversion.-Three converters suitable for use as D-to-A converter 80 in Fig. 3 are described. In one, Fig. 15 (not shown), a 3-bit reversible counter counts up increase and down decrease pulses from the pattern detector. The counter is arranged so as not to over- or underflow. Its output is decoded to mark one of eight lines connected to a linear D-to-A converter, the overall conversion characteristic being exponential. In another, Fig. 16 (not shown), an eight stage shift register contains a single 1 bit which is shifted one way by increase pulses and the other way by decrease pulses from the pattern detector. To prevent overflow, if the 1 bit is stepped off either end of the register it is rewritten into that end stage. The parallel outputs from the register are connected to a linear D-to-A converter, the overall conversion characteristic being exponential. In the third, Fig. 17, a single 1 bit is shifted up and down register 622' by increase and decrease pulses from the pattern detector, overflow being prevented by rewriting in the end stages. OR gates 694, 696 enable one of two gates 702, 704 to conduct a timing pulse, controlling a constant current generator 660 to charge a capacitor 668 for the time taken for a binary counter 684, counting clock pulses 692 to mark the appropriate one of leads 682, the overall characteristic being exponential.