baber/WOPTO huggingface dataset:
Patent TW-520356-B (TW)
Title: Process for the preparation of aldehydes
Inventor: BAHRMANN HELMUT
IPC: C07C45/50
Filed: 1998-09-29
Granted: 2003-02-11
Abstract: The invention relates to hydroformylation of olefins or olefinically unsaturated compounds in the presence as catalyst of an organic solution which comprises at least one rhodium compound and at least one phosphine-substituted cobalticinium salt, which comprised using phosphine-substituted cobalticiniurd salts of the formula I, where R1 is identical or different and is hydrogen; alkyl or alkoxy radicals having 1 to 14 carbon atoms; in addition cycloalkyl, aryl or aroxy radicals having 6 to 14 carbon atoms; a fused benzene ring; an amide radical -C(O)-NR2R3, in which R2 and R3 are indentical or different and are hydrogen, alkyl radicals having 1 to 14 carbon atoms, cycloalkyl or aryl radicals having 6 to 14 carbon atoms; the carboxyl group or an ester radical -C(O)-OR4, in which R4 is an alkyl radical having 1 to 14 carbon atoms, or in addition a cycloalkyl or aryl radical having 6 to 14 carbon atoms; n is identical or different and is an integer from 0 to 4; m is an integer from 1 to 3; and X is hexafluoro-phosphate, hexafluoroantimonate, tetraphenylborate, tosylate, tetrafluoroborate, triflate, trifluoroacetate, triiodide, tribromide, nitrate, perchlorate, sulfate, phosphate, sulfonate, -O-S(O)2-R5, where R5 is an alkyl radical having 1 to 14 carbon atoms, a cycloalkyl or aryl radical having 6 to 14 carbon atoms, or carboxylate -O-C(O)-R6, where R6 is hydrogen, an alkyl radical having 1 to 14 carbon atoms or additionally a cycloalkyl or aryl radical having 6 to 14 carbon atoms. An aqueous solution of 1,1-bis(diphenylphosphino)-cobalticinium nitrate and of a rhodium compound is suitable as hydroformylation catalyst in a two-phase process.
Patent TW-455594-B (TW)
Title: Acrylic molding compound, processes for the preparation of the same, process for the production of acrylic synthetic marble, and thickening agent
Inventor: KOYANAGI SEIYA
IPC: C08F20/00
Filed: 1998-10-27
Granted: 2001-09-21
Abstract: An acrylic mold compound, in which when a polymer powder (C) having a bulk density in the range from 0.1 to 0.7g/ml, an oil absorption of linseed oil in the range from 60 to 200ml/100g, a degree of swelling by methyl methacrylate is 16-fold or more and a specific surface area in the range from 1 to 100 m2/g is added as a thickening agent, hot water resistance is improved by using a polymer powder (C1) containing no surfactant, a polymer powder (C2) containing as a constituent component a reactive surfactant, or thickening speed is controlled by using a non-cross-linked polymer powder (C3) having a Mw from 100,000 to 2,500,000, a non-cross-linked polymer powder (C4) having a Mw from 2,500,000 to 5,000,000, a crosslinked polymer powder (C5) and a polymer powder (D) having a specific surface area from 0.01 m<SP>2</SP>/g to 1 m<SP>2</SP>/g; a production method thereof; a method for producing acrylic artificial marble in which components are extruded by kneading extruder (9) into given shape; and a thickening agent.
Patent TW-388951-B (TW)
Title: Method for producing mixed mode semiconductor devices
Inventor: JANG GUANG-YE
IPC: H01L21/70
Filed: 1998-10-31
Granted: 2000-05-01
Abstract: A method for producing mixed mode semiconductor devices is introduced. First, a substrate with a gate oxide layer and a device isolation region is formed a common conductive layer on them. Second, form a common dielectric layer on the conductive layer and then define the dielectric layer to form a polysilicon inter-oxide layer. Third, form a common conductive material layer on the conductive layer and the polysilicon inter-oxide layer and define the conductive material layer. Forth, remove a portion of the conductive material layer until exposing the conductive layer and use the conductive material layer and the polysilicon inter oxide layer as the etching mask to remove a portion of the conductive layer until exposing the gate oxide layer and the device isolation region. Finally, form a gate and a capacitor on the substrate.
Patent TW-402823-B (TW)
Title: Miniature galvanic cell having optimum low surface area conductive collector
Inventor: HEINZ JR HENRY
IPC: H01M50/533
Filed: 1998-11-09
Granted: 2000-08-21
Abstract: A miniature galvanic cell employing a cup-insulating member-current collector assembly, preferably a plastic insulating member and low surface area current collector, to prevent or minimize the formation of gases, such as hydrogen, on the current collector member. A process for producing such a cell is also disclosed.
Patent TW-426549-B (TW)
Title: Device for wet granulation of liquid slag
Inventor: ULVELING LEON
IPC: C21B3/08
Filed: 1998-11-11
Granted: 2001-03-21
Abstract: A smple and compact device for wet granulation of liquid slag comprises a granulating basin (14) with an injection device for the granulating water and a decanting basin (16) separate from the granulating basin (14). A distributor duct (40) for the granulate/water mixture extends over the decanting basin (16) and has on its underside outlets (42) for the granulate water mixture distributed over its length. A vertical inflow shaft (54) open at the bottom, into which the outlets (42) for the granulate/water mixture discharge, is arranged under the distributor duct (40) in the granulating basin (14).
Patent TW-I250210-B (TW)
Title: An isolated DNA sequence coding for an enzyme involved in the mevalonate pathway or the pathway from isopentenyl pyrophosphate to farnesyl pyrophosphate
Inventor: HOSHINO TATSUO
IPC: C12N9/10
Filed: 1999-04-27
Granted: 2006-03-01
Abstract: The present invention is directed to an isolated DNA sequence coding for an enzyme involved in the mevalonate pathway or the pathway from isopentenyl pyrophosphate to farnesyl pyrophosphate, vectors or plasmids comprising such DNA, hosts transformed by either such DNAs or vectors or plasmids and a process for the production of isoprenoids and carotenoids by using such transformed host cells.
Patent TW-434107-B (TW)
Title: A carrier head with a flexible membrane for chemical mechanical polishing
Inventor: CHEN HUNG-CHR
IPC: B24B37/32
Filed: 1999-08-02
Granted: 2001-05-16
Abstract: A carrier head for a chemical mechanical polishing apparatus has a base, a flexible membrane extending beneath the base to define a pressurizable chamber, a support structure positioned in the chamber, and a spacer ring positioned outside the chamber. The flexible membrane includes a lower surface of the flexible membrane provides a mounting surface for a substrate, and a perimeter portion that extends in a serpentine path between the spacer ring the support structure.
Patent TW-453105-B (TW)
Title: Scanner having both monochrome and color image sensor modules
Inventor: CHEN MICHAEL
IPC: H04N1/04
Filed: 1999-10-29
Granted: 2001-09-01
Abstract: The present invention provides a scanner having both monochrome and color image sensor modules. The scanner comprises a housing, a control unit installed in the housing to control the operation of the scanner device, and a scanner module installed in the housing and which is electrically connected with the control unit to scan the image transmitted by a document. The scanning module comprise a housing body, a color image sensor module installed in the housing body and which is electrically connected with the control unit to scan the image transmitted by the document and to generate the corresponding color image signal, a monochrome image sensor module installed in the housing body and which is electrically connected with the control unit to scan the image transmitted by the document and generate the corresponding monochrome image signal, a lens set installed inside the housing body to focus the image transmitted by the document so that the image of the document can be focused onto the color or monochrome image sensor module, and a lens module installed inside the housing body to transmit the focused image by the lens set to the color or monochrome image sensor module to generate the corresponding color or monochrome image signal.
Patent TW-442835-B (TW)
Title: Semiconductor device, its manufacturing process, and manufacturing apparatus
Inventor: OKUMA HIROKO
IPC: H01L21/768
Filed: 1999-11-01
Granted: 2001-06-23
Abstract: The object of the present invention is to provide a manufacturing method of a semiconductor device which can avoid breaking of a wire in a through hole. The through hole 21 penetrates an inter-layer insulating film 3 and a reflection preventive film 5 so that part of the top surface of a first wiring layer 2 is exposed. A gap under an eaves 5a of the reflection preventive film 5 is filled with a gap filling member 9. The exposed surface of the first wiring layer, the internal wall surface of the through hole 21, and the top surface of the inter-layer insulating film 3 are continuously covered with a barrier metal film 7. A second wiring layer 8 is connected to the first wiring layer 2 through the through hole 21 by interposing the barrier metal film 7 in the first wiring layer 2.
Patent TW-455875-B (TW)
Title: Charge pump circuit simple in construction and free from trouble even at low voltage
Inventor: KAWAI KEN
IPC: G11C16/06
Filed: 1999-12-07
Granted: 2001-09-21
Abstract: In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.
Patent TW-503551-B (TW)
Title: Electrostatic discharge protection circuit with low leakage current
Inventor: KER MING-DOU
IPC: H01L23/60
Filed: 1999-12-16
Granted: 2002-09-21
Abstract: The present invention provides a low leakage current electrostatic discharge (ESD) protection circuit that is disposed between a high power source line and a low power source line. The ESD protection circuit contains a semiconductor-controlled rectifier (SCR) and a diode string circuit. The anode of the SCR is connected to the high power source line. The diode string circuit is formed by at least one diode that is connected in series in the forward direction. The string circuit contains one positive electrode, which is coupled with the cathode of the SCR, and one negative electrode, which is coupled with the low power source line. When the integrated circuit is in a normal operation state, the SCR is in a closed state so as to make the ESD protection circuit, which is connected between a high power source line and a low power source line, have an extremely low leakage current. When the integrated circuit is subjected to the ESD effects, the ESD protection circuit is triggered and turned on such that a discharging route between a high power source line and a low power source line is formed to discharge the ESD current.
Patent TW-490291-B (TW)
Title: A method for the production of footwear and the footwear produced according to this method
Inventor: FINI CARLO
IPC: A43B13/14
Filed: 2000-01-20
Granted: 2002-06-11
Abstract: The method for the production of footwear comprises the following steps: production of a shoe (1a) in which the upper (2) and the base (3) define a total internal volume (V1); moulding of a standard inner sole (4) made of a material which may be plastically deformed using a form (5), the inner sole (4) having a second volume (V2a) less than the first volume (V1) and, when the inner sole (4) is inserted in a shoe (1a), leaving a free volume (V2b), smaller than the total volume (V1), inside the shoe (1a); insertion of the standard inner sole (4) in the shoe (1a) and fixing in place, so as to create a shoe-inner sole assembly (1) which can be separated and in which, between the base (3) and standard inner sole (4) there is at least one space with an empty volume (V3) substantially corresponding to the difference between the total volume (V1) and the second volume (V2a); heating of the shoe-inner sole assembly (1) made In this way to the preset temperature (T1) necessary for the thermoforming of the inner sole (4); insertion of a foot (7) in the shoe-inner sole assembly (1), so as to shape the standard inner sole (4) in the areas around the space (V3) according to the features of the sole of the foot (7).
Patent TW-538399-B (TW)
Title: Output circuit
Inventor: FUKUO MOTOO
IPC: H03F1/26
Filed: 2000-04-01
Granted: 2003-06-21
Abstract: The output circuit is provided with an operational amplifier, a current supply circuit and an impedance changing circuit. The current supply circuit supplies current to the operational amplifiers at rising and falling of an output signal delivered by the operational amplifier. The impedance changing circuit changes the impedance between the operational amplifier and an output terminal.
Patent TW-471104-B (TW)
Title: Low dielectric constant, porous film formed from regularly arrayed nanoparticles
Inventor: STEVEN MCCONELL GATES
IPC: H01B19/00
Filed: 2000-04-17
Granted: 2002-01-01
Abstract: The method of the invention produces a low k porous dielectric body with a uniform dielectric characteristic throughout its bulk and about its surface. The method initially starts with a mixture of a solvent, a first quantity of sacrificial nanoparticles and a second quantity of structural nanoparticles. The structural nanoparticles include an organic component. The mixture is concentrated in a manner to allow assembly of the structural nanoparticles into a lattice structure with interspersed sacrificial nanoparticles. The structural nanoparticles are then fused together to enable a rigidification of the structural nanoparticles and lattice structure. Then the sacrificial nanoparticles are removed from the lattice structure to leave voids therein. Finally, the surfaces of the voids are coated with a hydrophobic material. A device constructed in accord with the method is also described.
Patent TW-452812-B (TW)
Title: Plasma display panel
Inventor: OVERSLUIZEN GERRIT
IPC: H01J11/38
Filed: 2000-04-27
Granted: 2001-09-01
Abstract: Plasma display panel in which the fluorescent layer, a dielectric layer having a high relative dielectric constant, is provided between the electrodes and the phosphor(s). This improves the efficacy of the device and lowers minimum sustain voltage and firing voltages.
Patent TW-472454-B (TW)
Title: Fast reconfigurable programmable device
Inventor: CLINE RONALD L
IPC: H03K19/177
Filed: 2000-07-05
Granted: 2002-01-11
Abstract: A programmable cell comprises an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable memory configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.
Patent TW-451290-B (TW)
Title: Method for making a metal capacitor
Inventor: WU BING-CHANG
IPC: H01L21/02
Filed: 2000-07-21
Granted: 2001-08-21
Abstract: The present invention provides a method for making a metal capacitor on the dielectric layer on the surface of the semiconductor wafer. The method first forms a bottom plate groove on the surface of the dielectric layer, and then forms a metal bottom plate in the bottom plate groove. Next, the method forms an insulation layer on the surface of the metal bottom plate, and forms a via hole in the insulation layer. Then, the method forms a first metal layer on the surface of the insulation layer and simultaneously fills the via hole to form a contact plug. Finally, the method forms a metal top plate on the surface of the insulation layer and forms a metal line on top of the surface of the contact plug.
Patent TW-I247986-B (TW)
Title: Firmware mechanism for correcting soft errors
Inventor: QUACH NHON TOAI
IPC: G06F11/16
Filed: 2000-10-09
Granted: 2006-01-21
Abstract: A computer system includes processor having dual execution cores and a nonvolatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.
Patent TW-449921-B (TW)
Title: MOS transistor structure
Inventor: MA SSU-PIN
IPC: H01L29/772
Filed: 2000-10-09
Granted: 2001-08-11
Abstract: The present invention provides a MOS transistor structure, which is suitable for a semiconductor substrate. The structure comprises: a polysilicon gate constituted by a plurality of polysilicon blocks connected in series, and formed on the surface of the semiconductor substrate; one or multiple source/drain ion doped areas formed in the active area of the semiconductor substrate of both sides of the polysilicon gate; and a plurality of metal connecting members formed on the surface of the polysilicon gate for connecting the polysilicon gate to a predetermined circuit.
Patent TW-480185-B (TW)
Title: Automatic retraction-type safe injector
Inventor: LIAU CHING-FU
IPC: A61M5/50
Filed: 2000-10-27
Granted: 2002-03-21
Abstract: An automatic retraction-type safe injector comprises a needle having a needle pipe, a waterproof ring and a hook, a retraction spring, a retraction clip, a push bar and a push bar cap and a push bar plug, a needle fastening ring buckle, an outer cylinder, and a needle cap. According to a structure of the above mentioned automatic retraction-type safe injector that a retraction spring and a retraction clip are installed in the needle retraction groove of the push bar, the needle can be brought into the needle retraction groove of the push bar in cooperation with the operation of the push bar plug and the fastening needle ring buckle, thereby completing the operation of automatic retraction.
Patent TW-476898-B (TW)
Title: A human resource management service system
Inventor: FUKUI MASAHIRO
IPC: G06Q50/00
Filed: 2000-10-31
Granted: 2002-02-21
Abstract: An object is to provide a human resource management service system which makes it possible to perform human resource management necessary for the operations of worker dispatching companies utilizing the system without introducing any special equipment and also to greatly save time for the person seeking employment to register plural worker dispatching companies. By connecting the terminal device of a person seeking employment, the human resource management center, and the terminal devices of worker dispatching companies via network, management center on the network unitarily renders services. The management center provides the person seeking employment with the service to register, via the network, human resource information including the person's experiences, skills, and qualifications by designating the worker dispatching company the information is to be registered with. The management center stores, when the person seeking employment designates the company the information is to be registered with, a part or the whole of the human resource information of the person seeking employment as primary information of the registrant, which can be referred to and retrieved by the designated company, and stores, in a read-write enabled state, secondary information per company in relation to the primary information with respect to the registrant, thereby providing the companies with the service making the primary and secondary information available via the network.
Patent TW-I282909-B (TW)
Title: Lithographic apparatus and a method for manufacturing a device
Inventor: BURGHOORN JACOBUS
IPC: G01B11/00
Filed: 2000-12-13
Granted: 2007-06-21
Abstract: In a lithographic apparatus having a movable object table in vacuum, an interferometer-based alignment system for detecting the position of that object table has a passive part in vacuum and an active part outside the vacuum chamber. The active part contains the beam generator, e.g. a laser, and the electronic detectors whilst the passive part contains the illumination and imaging optics. The two parts are coupled by optical fibers. The interferometer may make use of different diffraction orders from measurement and reference gratings and the order separation may be included in the passive part.
Patent TW-464974-B (TW)
Title: Method for using the gettering layer to improve the flash memory in the chemical mechanical process
Inventor: TSENG U-WAY
IPC: H01L21/306
Filed: 2000-12-26
Granted: 2001-11-21
Abstract: The present invention provides a method for using the gettering layer to improve the flash memory in the chemical mechanical process (CMP), which is provided to improve the electrical reliability of the flash memory after high temperature baking, and improve the margin of the dielectric material of the interlayer dielectric (ILD) in a chemical mechanical process (CMP) for planarizing the dielectric material, thereby increasing the thickness of the array arranged denser and the peripheral interlayer dielectric for increasing the etching or polishing margin, so as to improve the interlayer dielectric in the chemical mechanical process.
Patent TW-I262202-B (TW)
Title: Curable composition, cured product and laminate
Inventor: YAMAGUCHI YOSHIKAZU
IPC: B32B27/42
Filed: 2001-01-16
Granted: 2006-09-21
Abstract: The invention relates to a curable composition comprising (A) particles prepared by bonding at least one oxide of an element selected from the group consisting of silicon, aluminum, zirconium, titanium, zinc, germanium, indium, tin, antimony, and cerium, and an organic compound which comprises a polymerizable group, (B) a compound having a melamine group and one or more polymerizable groups and (C) a compound having at least two polymerizable groups in the molecule other than the component (B); and to cured products and laminates with a with low reflectance and superior chemical resistance.