Patent GB-869950-A (GB)
Title: Improvements in and relating to electrical delay devices
IPC: G06F7/491
Filed: 1959-10-05
Abstract: 869,950. Digital electric calculating apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 5, 1959 [Oct. 3, 1958], No. 33685/59. Class 106 (1). An adder or subtractor (by complement addition) utilizes tapped delay devices each having a terminating impedance which reflects an input pulse, and gating elements selectively energizable to pass either the tapped input or reflected pulses. The operation is performed by imposing delays on an input pulse proportional to like order digits of e.g. the addend and augend, the total delay being representative of their sum. A master delay line 21 is four and a half unit delays in length and has taps 0: 9, 1 : 8 ; ... 4: 5, spaced at unit intervals. The taps are connected to banks of switches 25, 45, 65 on which the units, tens and hundreds digits of the augend or minuend are set by closing one switch of each bank. If, for example, switch 25-1: 8 is closed a pulse appears on line 26 one time unit, or a reflected pulse of inverted polarity appears eight time units, after an input pulse from source 23 is applied to the delay line 21. The normal pulse is applied to AND unit 27b, the reflected and inverted pulse to AND unit 27a, after inversion by circuit 27c. The other input of one of the AND units is marked from source 28, as determined by the setting of switch 30a and double-pole switch 31a, 31b. Switch 30a is closed on contact 30c if the digit entered on bank 25 is from 0 to 4, on contact 30b if from 5 to 9. Switch 31a, 31b is set in the position shown for addition, to its other position for subtraction. Thus to subtract 8 switch 25-1: 8 is closed and AND unit 27b is enabled to receive the normal pulse appearing on line 26 after one time unit, one being the nines complement of eight. The pulse appears on line 36 and is further delayed in line 38, similar to the master delay line, on an associated switch bank 39 of which the units order digit of the subtrahend is set. A pulse representing the unit order sum appears on line 43. Similar circuits derive the tens and higher order sums but provision is made for the pulses to traverse additional unit delays 61, 81 representing carries or borrows. Two input pulses from source 23 are required to produce a true sum including carries or borrows, on the first the output pulse from each order is timed by comparison with pulses from tapped delay line 102 to determine whether the sum of the digits of the order lies between 10 and 19, or for tens and higher orders, whether provision for carry on carry is to be made. If a carry is required triggers 112, 122 or 132 are set marking output lines 118, 128, enabling AND units 62b, 82b to produce an output on reception of a pulse on lines 64b, 84b which include the unit delays 61, 81. If the triggers are in their normal state AND units 62a, 82a are enabled and the carry delays are by-passed. If the tens order sum is 9 for addition, 0 for subtraction, AND unit 123 sets trigger 124 to provide one input for AND unit 123, the other input is from line 119. If then there is a carry from the units order, the tens order carry trigger 122 is set. It follows that on the first input pulse from source 23, output pulses from tens and higher orders pass through AND units 62a, 82a ... to set such carry-borrow triggers as may be necessary, but that on second or following input pulses a true sum appears on lines 43, 63, 83. As shown, these lines are connected in turn to an output device comprising a reflective delay line 97 tapped to provide inputs to AND units, the outputs of which are connected to OR circuits to mark one out of ten lines. The output pulse of each order is applied to all the AND units and coincidence occurs or the AND unit which the pulse on delay line 97 has reached. An addsubtract switch 91a, 91b is provided to determine which section of delay line 97 is used.