Patent UA-94311-U (UA)
Title: driver of a SINGLE package of two symmetrical CODE SERIES of pulses with programmable time parameters
IPC: H03K3/78
Filed: 2014-05-19
Abstract: The generator of a single pack of two symmetrical code series of pulses with programmable time parameters multiple of the period of continuous periodic pulse sequence supplied to the input from the quartz oscillator output that comprises: two reversible binary counters having an input of synchronization pulses, input for adjustment to addition / subtraction mode, input of permit of synchronous parallel loading and the inputs of loading data , count mode permit input, input of asynchronous installation to zero state, the overflow output; the first (four-input), the second (three-input) and third (two-input) OR elements; two inverters; circuit comprising connected in series resistor and capacitor; synchronous D-flip-flop with input of asynchronous installation to zero state; first and second two-input AND gates; first and second OR elements; the common point of connected in series resistor and capacitor is connected to the data input of the first D-flip-flop, to one input of AND gates; output of first AND element is connected to the input of asynchronous installation of D-flip-flop to zero state; the clock input of D-flip-flop forms the start pulse input; the second input of second AND element is connected to the output pf the second OR gate, one input of which is connected to the D-flip-flop output; output of the second AND gate is connected to the inputs of asynchronous installation to zero state of the counters; outputs of the bits of the second counter are connected to the inputs of the first element OR; clock inputs of the counters are connected together to form the driver input – input for supply of continuous periodic pulse sequence from the output of external oscillator; parallel loading inputs of the first counter form the inputs of driver setting onto output pulses specified parameters. There are included: JK-flip-flop with input of asynchronous installation to zero state; third reversible binary counter which has a clock pulse supply input ,adjustment to the addition / subtraction mode input, input of permit of synchronous parallel loading and inputs for loading data, count mode permit input, input of asynchronous installation to zero state, the overflow output; fourth element OR; first and second two-input AND-NOT elements, wherein the overflow output of the third counter, which forms the output of the driver is connected to the permit input of synchronous parallel loading, input of the fourth OR gate, input of the second counter count mode permit, and the input of the first inverter, output of which is connected to the input of third counter counting mode permit, the second input of the first AND gate, and first and second inputs of AND-NOT element; output of the first OR gate is connected to the second input of the fourth OR gate and the input of the second inverter, its output is connected to the first input of the third OR gate and the second input of the first AND-NOT element with its output connected to permit input of the first counter counting mode; output of the fourth OR gate is connected to the second input of the second OR gate and the inputs J and K of JK-flip-flop; the JK-flip-flop output is connected to the third input of the second OR gate; bit outputs of the second counter are connected to the inputs of the third counter data loading; first counter overflow output is connected to the second input of the third OR gate and the second input of the second AND-NOT element; output of the third OR gate is connected to the input of adjustment to the summation / subtraction mode of the second counter; output of the second AND-NOT element is connected to the loading mode permit input of the first counter; the clock input of the third counter and the JK-flip-flop is connected to the clock inputs of the first and second counters; input of asynchronous installation to zero state of JK-flip-flop and the third counter is connected to the output of the second element AND.