Patent GB-1193101-A (GB)
Title: Digital Delay Measurement System.
IPC: G01S13/70
Filed: 1967-01-14
Abstract: 1,193,101. Radio ranging. HOFFMAN ELECTRONICS CORP. 14 June, 1967 [14 June, 1966], No. 27538/67. Heading H4D. Specification describes a digital range measuring system for use for example with a TACAN beacon. The contents of a variable register 21 represent the assumed range of the target and one read out on transmission of an interrogating pulse. This produces a gating pulse which, by means of time discriminator 10 fed with the return pulse produces signals representing the error in the assumed target range and corrects said register contents. Thus an interrogation transmitter pulse on line 42 enables transfer gates 24 whereby the contents of register 21 are parallel fed to counter 26. The interrogation pulse also sets bi-stable 43 whereby AND gate 41 is enabled to pass pulses at 3À23M pps from clock 34 to a countdown input of counter 26 When the count transferred to 26 is reduced to zero the counter 26 produces a pulse at 28 which is fed to a counter and range gate generator 29. Abutting early and late range gates are produced on lines 30 and 31 respectively, 40 Ás after the pulse at 28 (40/Ás being the delay at the TACAN beacon between receiving the interrogation pulse and transmitting the reply pulse). The gate signals are fed to discriminator 10 which gives an output at 13 indicating by its magnitude and polarity the position of the return pulse with respect to the time abutting edges of the early and late gates. This output is fed via low pass integrating or memory filter 14 to a voltage controlled oscillator. Depending on the polarity of said output, pulses are produced by the oscillator on its count-up or count-down outputs. These pulses feed respective inputs of the register 21 to adjust the contents thereof to the correct value. Means 29 produces a third range gate (including the first two mentioned) at 48 and this is used to reset bi-stable 43 and halt the count-down of counter 26. Outputs at 22 can feed the register contents to a digital range indicator. The system operates in a search or track mode, the above description being that of the track mode. In the search mode the contents of register 21 starts at zero by means of reset input 70 and advances by means of counting up the output of the clock 34 via AND gate 36 and OR gate 19. Gate 36 is enabled by the set output of bi-stable 74 which is set by the output of gate 77 thereby indicating the simultaneous presence of a search input at 85, a a range gate pulse at 76 and an input at 88. This latter input indicates that means 81 has detected less than three gated reply pulses in response to five consecutive interrogations. Due to the advancement of the register, the range gates produced by 29 walk through the range until a reply pulse is detected. The gated reply pulses are integrated at 79 via AND gate 72 and the acquisition of three or more consecutive replies is detected by level detection 83. A track mode signal is then produced on output 84. The interrogation pulse repetition frequency is controlled at 39 such as to increase in the search mode and to keep pace with detected target acceleration as indicated by the output of discriminator 10.