baber/WOPTO huggingface dataset:
Patent JP-H02134585-A (JP)
Title: Magnetoelectric converter
Inventor: INOUE TETSUO
IPC: G01R33/06
Filed: 1988-11-15
Abstract: PURPOSE:To enhance sensitivity by reducing a diamagnetic field and a saturated magnetic field by constituting a main current passage of a plurality of ferromagnetic parts formed at a predetermined interval and a plurality of non-magnetic conductor parts connecting the same. CONSTITUTION:Ferromagnetic membranes 12, 13 are formed on a glass substrate 11 and have a continuous fold-back pattern shape and are constituted of main current passage parts 14, 15 and bent parts 16, 17 and arranged so that the current directions thereof cross each other at a right angle. The passage parts 14, 15 consist of a plurality of ferromagnetic parts 14a, 15a formed into an almost square shape and non-magnetic conductor parts 14b, 15b electrically connecting the same respectively. One end parts of the passage parts 14, 15 are electrically connected to an output terminal 18 and power supply terminals 19 are respectively connected to the other end parts of said passage parts 14, 15. A voltmeter 35 is connected between the lead wire 33a from the terminal 19 and the terminal 18 through a lead wire 34. By the voltmeter 35, a change of voltage due to the sensed current changed by the anisotropic magnetic resistance effect of the membranes 12, 13 is detected.
Patent JP-H05128048-A (JP)
Title: Information processor
Inventor: MATSUMOTO TAKAYUKI
IPC: G06F13/28
Filed: 1991-11-01
Abstract: PURPOSE:To improve the occupation rate of a data bus at the time of continuously transferring data by means of direct memory access(DMA) by converting data from a bus with a large size into the bus size of a data bus through a data register, an address register and a bus conversion register. CONSTITUTION:In the case that the memory reading of continuous addresses based upon DMA transfer is executed through a bus 2 whose bus size is larger than that of a data bus 4, a data register 13 stores data read out from the memory through the bus 2 and an address register 14 in a register control circuit 16 stores the address of the data. When the circuit 16 judges that the address corresponds to data in the range of the register 13 in each data transfer, a bus conversion register 15 converts the data into the bus size of the data bus 4 and outputs the converted data to the bus 4. Consequently the occupation rate of the bus 2 can be improved (lowered) and the continuous transfer of data can efficiently be executed.
Patent JP-H09111646-A (JP)
Title: Spun tone cloth
Inventor: NAKAGAWA MASANORI
IPC: D06C27/00
Filed: 1995-10-11
Abstract: PROBLEM TO BE SOLVED: To obtain a spun tone cloth almost free from hardening of feeling and decrease in strength, and having bulky feeling. SOLUTION: Cloth is produced of cellulose multifilament yarn spun from an organic solvent and having dry strength of >=3g/d and <=5g/d and dry elongation of >=5% and <=10%. In this cloth, fluffs of 100-300μm in length are randomly entangled on its surface and such states are homogeneously distributed.
Patent JP-S62145858-A (JP)
Title: Semiconductor integrated circuit device
Inventor: OGATA TAKASHI
IPC: H03F1/08
Filed: 1985-12-20
Abstract: PURPOSE:To avoid a parasitic npn transistor by potentially shortcircuiting between a second epitaxial layer and a first separating layer to shortcircuit between the collector and the base of the transistor. CONSTITUTION:An n-type epitaxial layer 30 of dummy island is disposed on the periphery of the pattern of a driving transistor 1 in which its collector potential becomes a negative potential, and the layer 30 is electrically shortcircuited with a separate p-type layer 25 by a contact designated by a region 28 and aluminum wirings 29. Thus, the collector and the base of a parasitic npn transistor 16 are shortcircuited therebetween, and the operation of the transistor 16 does not occur. Thus, the adverse influence to other circuit element generated due to the transistor 16 can be avoided.
Patent JP-H01130439-A (JP)
Title: Switch for motor driven tool
Inventor: NAGATA KUNIO
IPC: H01H21/02
Filed: 1987-11-14
Abstract: PURPOSE:To simplify and miniaturize the assembly by the connecting common contact of two switches to the ends of a motor, shortcircuiting NO terminals with each other and NC terminals with each other, connecting their NO contacts with the lower supply, and by connecting the NC contacts to a revolving speed control circuit. CONSTITUTION:Common contact of two switches A, B is connected with the ends of a motor M, and NO terminals each other and NC contacts 50, 51 each other are shortcircuited, and their NO contacts 48, 53 are connected with the power supply while the NC contacts 50, 51 are connected to a revolving speed control circuit 58. Therefore, either of the two switches A, B is selected, and the common contact is switched over from the NC contacts 50, 51 to NO contacts 48, 53 to cause shortcircuiting, and thereby regular or reverse rotation of the motor M is selected. Thus regular/reverse rotation of motor M, power input to the motor M, power input to revolving speed control circuit, and braking action at the time of motor being stopped can be accomplished through selection of the switches A, B. This enables making the arrangement in small size and enhances the efficiency in assembly.
Patent JP-H06138940-A (JP)
Title: Autonomous mobile robot
Inventor: NISHIYAMA TAKASHI
IPC: G05D1/02
Filed: 1992-10-27
Abstract: PURPOSE:To omit the reloading of the path data by generating an optimum path between the present position and a target position by the parallel processing. CONSTITUTION:A data fetching means 40 fetches the peripheral distance data on a robot main body and also reads the position coordinates and the traveling direction angle of the robot out of a dead-reckoning device 6 to transmit these data, coordinates and angle to a path following means 41 as the present time information. Meanwhile the means 40 transmits the data on the position coordinates to a path generating means 42. The means 42 generates an optimum path from the data on the moving environment of a map data base, etc., and based on the coordinates of a target position and the present position and gives the optimum path to the means 41. Thus the means 41 decides the traveling speed and the steering angle of the robot based on the received distance data, the data on the robot position coordinates, the data on the traveling direction angle, and the pat data. Then the means 41 gives a command to a wheel rotational speed/direction controller 5.
Patent JP-H02136597-A (JP)
Title: Blower blade
Inventor: KUNO OSAMU
IPC: F04D29/30
Filed: 1988-11-15
Abstract: PURPOSE:To prevent the generation of turbulent flow of air by setting the thickness dimension on the suction side of a blade piece over the max. thickness dimension on the discharge side, having a prtiting line in molding which is generated on the side surface of the blade piece as boundary, in a blower blade having a plurality of blade pieces which are erected radially on a disc-shaped basic board part. CONSTITUTION:As for an intermediate-shaped ventilating fan, a motor 27 is supported through a supporting plate 28 in a nearly cylindrical body frame 21, and a blower blade 29 is installed onto the rotary shaft 27a of the motor 27. The blower blade 29 is integrally equipped with a nearly conical basic board part 31 having a shaft insertion hole 30 at the center part, several pieces of blade pieces 32 which are projectingly installed aslantly outwardly onto the outer surface, and annular connecting plate 33 for connecting the top edge of each blade piece 32, and formed integrally by using the upper and lower molds which can be separated in the axial direction. In this case, in the blade piece 32, the thickness dimension D1 on the suction side 32a of the blade piece 32, having a parting line 34 as boundary, is set over the max. thickness dimension D2 on the discharge side 32b, and the generation of turbulence of air on the side surface of the blade piece 32 is prevented.
Patent JP-H08148753-A (JP)
Title: Semiconductor laser
Inventor: NAKAMURA KOJI
IPC: H01S5/00
Filed: 1994-11-22
Abstract: PURPOSE: To reduce carrier generation probability in the window area of a GaAs or AlGaAs semiconductor laser provided with a window structure so as to prevent the optical damage on the resonator edge plane even when laser power is increased. CONSTITUTION: On a substrate 12, a bottom clad layer 14, a light guide layer 16, an active layer 18, an upper clad layer 20 and a contact layer 42 are subsequently provided. In a gain area 26 wherein the active layer 18 is to be provided, a pair of drive electrodes 28 and 30 are provided, and in a window area 22 wherein the active layer 18 is not to be provided, a pair of extraction electrodes 28 and 32 are provided. The common electrode is used for the drive electrode 28 and the extraction electrode 28. The drive electrode 30 and the contact layer 42 in the gain area 26 and the extraction electrode 32 and the contact layer 42 in the window area 22 are separated, and isolation resistance is formed between the electrodes 30 and 32. Carriers are extracted from the window area 22 through the pair of extraction electrodes 28 and 32.
Patent JP-H01162012-A (JP)
Title: Real ttl output converter driver including real ecl three-state control
Inventor: OORANGUZEBU KEI KAAN
IPC: H03K19/0175
Filed: 1988-11-15
Abstract: PURPOSE: To increase a speed of transition from 'tri-state' mode into 'operating mode' considerably and to improve delay performance of the transition from 'tri-state' mode into 'operating mode' by forming a circuit to drive a TTL bus from an ECL circuit so as to eliminate the need for a converter and a buffer. CONSTITUTION: A true ECL/true TTL converter 11 is made up of three transistors(TRs) Q1-Q3 forming an inverter. Then a base voltage of the TRQI is changed by ±0.5Vbe around an ECL standard voltage Vr1. Thus, in the case of Vb(Q1)>Vr1, the TRQ1 produces a full Vbe and reaches a forward conduction state, then a relation of TR (Q2)<0.5Vbe is established and the TRQ2 is regarded to be nonconductive. As a result, a current source lcs1(Q3/R11) is satisfied by the TRQ1. Then in the case of Vb(Q1)<Vr1, the TRQ2 produces a full Vbe and reaches a forward conduction state, then a relation of TR(Q 1)<0.5Vbe is established and the TRQ1 is regarded to be nonconductive. As a result, a current source Ics1 is satisfied by the TRQ2.
Patent JP-S62144803-A (JP)
Title: Multi-stage rolling mill
Inventor: KIZAKI KIYOSHI
IPC: B21B13/14
Filed: 1985-12-20
Abstract: PURPOSE:To make construction simpler and smaller in size by supporting one work roll to a pyramid shape by two pieces of intermediate rolls and supporting the other work roll by a piece of offset intermediate roll and divided rolls. CONSTITUTION:The upper work roll 5 is supported to the pyramid shape by the upper intermediate rolls 2, 3. The rolls 2, 3 are pulled by springs 4 and are supported by an upper back up roll 1. The upper divided rolls 7, 8 are provided to the upper stream and down stream sides of a pass line 28 of the rolls 2, 3. The rolls 7, 8 are engaged with a crown adjuster consisting of wedges 9, 10 and cylinders 11, 12. The lower work roll 19 is supported by the offset intermediate roll 18 and the bending of the roll by pushing the same from both sides with divided rolls 23, 24 is made possible. The size of the work rolls 5, 19 is made smaller and the construction is made simpler and smaller by the above-mentioned mechanism.
Patent JP-S62146743-A (JP)
Title: Interior trim parts for vehicle
Inventor: TAMURAYA MAKOTO
IPC: B60R13/02
Filed: 1985-12-20
Abstract: PURPOSE:To facilitate the fitting/removal of interior trim parts by integrally forming a bulge section bulged toward the room inside at the upper portion of a flange formed at the lower end section of a rear pillar interior trim fitted to a rear pillar panel. CONSTITUTION:A flange 2a overlapped with the side end of a parcel interior trim 5 fixed to a parcel panel 4 bent toward the room inside R is formed at the lower end section of a rear pillar interior trim 2 fitted to a rear pillar panel 1 so as to cover it via a clip 3. In this interior trim 2, a bulge section 12 bulged toward the room inside R is integrally formed at the upper portion of the flange 2a so that a space 11 is formed on the rear pillar panel 1 side. The bulged quantity L of this bulge section 12 is set to a level that the flange 2a does not interfere with the side end of the interior trim 5 when the interior trim 2 is brought down to the room inside R using the vicinity of the clip 3 fitting as a fulcrum.
Patent JP-H01129648-A (JP)
Title: Telephone reserving device
Inventor: YOSHIDA TATSUO
IPC: H04M1/656
Filed: 1987-11-16
Abstract: PURPOSE:To obtain a device to confirm the result of reservation by providing an automatic response means responding to a call signal and a comparison means or the like setting the number of reserved persons, and comparing it with the number of effective called persons to apply reservation of diagnosis in an interactive form in voice. CONSTITUTION:A call signal is detected by an incoming detecting circuit 3 and a detection output is fed to a CPU 12. The CPU 12 operates a loop closing circuit 4, reads a voice data stored in a RAM 15 and supplied it to a voice synthesizing circuit 6 to send a guide message. When a caller applies the data of birth and its name in response to the message, they are recorded on a tape recorder 11. The CPU 12 compares the number of reservation possible persons and the number of reserved persons in the RAM 15, and when the reservation is possible, the message representing the reservation is sent and recorded on a tape recorder 11. When the number of reserved persons is occupied or in case of closing the medical treatment, a message representing disabled reservation is sent.
Patent JP-H0770012-A (JP)
Title: Production of excitatory amino acid receptor- antagonist and intermediate
Inventor: ANITA MERIKIANNBADARIAN
IPC: C07F7/18
Filed: 1993-11-18
Abstract: PURPOSE: To provide a novel hydroisoquinoline compound useful for the preparation of a hydroisoquinoline compound being an excitatory amino acid receptor antagonist and to provide a novel intermediate therefor.  
     CONSTITUTION: There is provided a compound of formula I [wherein R 11  is CN, CH 2  OH or the like; R 2  is H, an alkyl, an alkenyl or the like; R 3  is H, an alkyl, an alkenyl, benzyl or the like; R 4  is H, SO 2 R 7  (wherein R 7  is an alkyl or the like) or the like; and X is CH 2 , C=O or C=S] or a pharmaceutically acceptable salt thereof. It is exemplified by methyl-2S-2-N-acryloyl-2N- benzylamino-6-oxohepta-4-E-enoate. There is further provided a compound of formula II [wherein Q is C(=O)CH 2 , C(DR 10 =CH (wherein R 10  is silyl, an alkyl or the like)) or a pharmaceutically acceptable salt thereof. It is exemplified by 3S-4aS,8aR-N-benzyl-1,6-dioxo-1,2,3,4,4a,5,6,7,8,8a-decahydroisoquinoline-3- carboxylate. For example, a compound of formula IIa can be obtained from a compound of formula Ia via a compound of formula 19. 
     COPYRIGHT: (C)1995,JPO
Patent JP-H09106445-A (JP)
Title: Key changing method for information recording medium and information recording medium
Inventor: HAYASHI MASAHIRO
IPC: G06F21/62
Filed: 1995-10-12
Abstract: PROBLEM TO BE SOLVED: To change the key of an information recording medium such as an IC card while securing security. SOLUTION: This key changing method sets previously a key-generation algorism for generating a new key to the information recording medium, a key-generation key that this algorism necessitates for key generation and a parameter data after setting a new key to the information recording medium only once. Then the parameter data to be used for key generation is specified from outside so as to generate a key by the key-generation algorithm through the use of the key-generation key and this specified parameter to rewrite the old key with the generated key so that the key is internally changed without transmitting a new key from outside. The information recording medium adopts a changing method like this.
Patent JP-S63141176-A (JP)
Title: Electronic slip system
Inventor: IKEDA SAKAE
IPC: G06Q10/10
Filed: 1986-12-03
Abstract: PURPOSE:To attain an electronic slip system to automatize a flow of slip and a slip processing by providing a business processing flow control means based on a business processing flow. CONSTITUTION:A terminal equipment 1 is a terminal which is connected to an electronic mail transmitting receiving mechanism 2 and can be displayed and printed only by a person having a discriminating card. The mechanism 2 transfers a slip between the terminal equipment 1 and a slip body storing file 4 and communicates the information of the storing of the slip to the file 4 to a slip control mechanism 5. The mechanism 5 has the function of the interface of the mechanism 2, checks the form and contents of the slip and distributes the control to an approving information control mechanism 6 and a business processing flow control mechanism 8. The mechanism 6 inspects the information of the slip and controls an approving route. The mechanism 8 refers to a business processing flow describing file 7 and controls the business processing flow of an electronic mail. A business processing automatizing program 10 executes the business processing mechanism under the control of a business processing automatizing program activating monitoring mechanism 9.
Patent JP-H01130628-A (JP)
Title: Adder circuit
Inventor: NAKAJIMA KENGO
IPC: G06F11/10
Filed: 1987-11-17
Abstract: PURPOSE:To make the arithmetic operation of a Galois field including Zero accurate without using other means by providing a 1st logic circuit obtaining OR of each AND of two n-bit data and a 2nd logic circuit obtaining OR between bits of n-bit outputs. CONSTITUTION:The 1st and 2nd logic circuits 50, 60 are added to an adder 30 and a logic circuit 40 respectively. The logic circuits 50, 60 invalidate the output of the logic circuit 40 if at least one data in two n-bit data Xe, Ye is 2<n>-1 and outputs the value 2<n>-1 and validate the output of the logic circuit 40 if not and outputs the sum of 2 n-bit data by using the value 2<n>-1 as the modulo. Thus, the arithmetic operation of a Galois field including Zero is applied accurately without using other means.
Patent JP-H10207771-A (JP)
Title: Method for shortening memory operation
Inventor: JAY MICHAEL ANDREWARTHUR
IPC: G06F12/08
Filed: 1997-10-22
Abstract: PROBLEM TO BE SOLVED: To improve the throughput of a memory by removing an unnecessary clock cycle existing in full burst reading, correction and writing operation. SOLUTION: Each of plural nodes consists of a processor 100, a processor agent chip(PAC) 111, a cross bar router chip (RAC) 112, a memory access chip(MAC) 113, a memory 114, a doughnut type access chip(TAC) 115, an SCI ring 116, and an I/O sub-system 117. When a 1st memory line is read out, a mask signal is turned on in order to prevent remaining memory lines from being read out. When tag data read out from the 1st memory line are updated, the updated data are written in one of the remaining memory lines other than the 1st memory line. After the writing, data are written in the 1st memory line by using the updated tag data.
Patent JP-S62149063-A (JP)
Title: Cassette loading device
Inventor: WATANABE KAZUMASA
IPC: G11B15/675
Filed: 1985-12-23
Abstract: PURPOSE:To load a cassette by providing a roller, a means for depressing the roller to the top of cassette and a roller shaft in a direction slightly clockwise from the direction perpendicular to the cassette loading direction to only guide the cassette at one side face of the cassette holder. CONSTITUTION:The roller 12, levers 14, 20, springs 16, 21 serving as a means for depressing the roller 12 against the top of cassette, and the roller shaft 13 in parallel with a direction driven slightly clockwise from a direction perpendicular to the cassette loading direction are provided. Thus, it is prevented that the cassette 1 is loaded counterclockwise from the direction of arrow 11 and the cassette back is guided for loading by a cassette holder 2. Then the cassette loader using the lengthwise direction of the cassette as the loading direction is realized.
Patent JP-H08140475-A (JP)
Title: Device for preserving cut flower
Inventor: TAMAOKI YUICHI
IPC: A01G5/06
Filed: 1994-11-24
Abstract: PURPOSE: To provide a device for preserving cut flowers, equipped with a water tank in which flowers are put and a cooling device for cooling the water tank, capable of preserving cut flowers for a long period of time without being contaminated with bacteria, etc., and making a user appreciate and enjoy cut flowers. CONSTITUTION: This device for preserving cut flowers is equipped with a water tank 2 which is supplied with water and in which cut flowers 4 are put, a stand 3 to be arranged in water in the water tank 2 and a cooling device 6 which places a cooler 7 below the stand 3 and cools water in the water tank 2. A thermomodule which is brought into contact with the bottom of the water tank 2 and cools water in the water tank 2 is preferably set.
Patent JP-H02137070-A (JP)
Title: Picture processor
Inventor: SHISHIZUKA JIYUNICHI
IPC: G06T3/00
Filed: 1988-11-18
Abstract: PURPOSE:To perform the conversion of colors with use of the look-up tables in number smaller than the number of frame memories and to attain the effective use of hardware by referring to the conversion information corresponding to the display data on plural memories based on the mask information added to the display data. CONSTITUTION:The picture data stored in the frame memories 10 and 11 are inputted to a synthesizer 12 at one time and then outputted according to the display priority indicated by a control circuit 16. The synthesizer 12 outputs the picture data on the memory 10 or 11 in response to the states of the mask bits stored in both memories 10 and 11 as well as a control signal 18. A look-up table LUT 13 refers to a table for the memory 10 or 11 to convert the color and the density of the picture data based on the control information 17 received from the circuit 16. As a result, the number of look-up tables and the effective use of hardware is attained.
Patent JP-H03151664-A (JP)
Title: Master slice system semiconductor integrated circuit device
Inventor: SAWA SHINJI
IPC: H01L27/118
Filed: 1989-11-08
Abstract: PURPOSE:To achieve a RAM with high operation speed by making an element set with a plurality of second N-channel or P-channel transistor as a basic element set in addition to the same number of P-channel and N-channel transistors. CONSTITUTION:For example, three P-channel transistors and three N-channel transistors as well as four second N-channel transistors are made as a basic element set. Thus, a plurality of P-channel transistors, the same number of first N-channel transistors as the P-channel transistor, and a plurality of second N-channel transistors are made as a basic element set, and an adjacent basic element set is formed on nearly the entire surface on a semiconductor substrate so that a P-channel transistor, a first N-channel transistor, and a second M- channel transistor share one or more sources or drain regions 4a-4d. Thus, a RAM can be configured in a high density and a load capacity of a signal line between memory cells constituting the RAM can be reduced, thus constituting a RAM with a fast operation speed.