baber/WOPTO huggingface dataset:
Patent JP-S62284931-A (JP)
Title: Injection timing control device for fuel injection pump
Inventor: INAGAWA KEIJI
IPC: F02D1/18
Filed: 1986-05-31
Abstract: PURPOSE:To obtain the optimum lead angle value ranging over low gear and a high gear and in accordance with change in atmospheric pressure by applying the hydraulic pressure of a working pressure chamber or a pressure fuel chamber to a throttle valve for controlling the opening area of a variable orifice. CONSTITUTION:A feed pump 3 sucks up fuel from a tank 4 and feeds the fuel to a pressure fuel chamber 2. The fuel pressure in the pressure fuel chamber 2 is transmitted to an operating pressure chamber 30 via an orifice 32 and in introducing passage 31. When the atmospheric pressure is high, for example, since the atmospheric pressure introduced from an atmospheric air open port 42 into an atmosphere chamber 41 is also high, bellows 40 is contracted, the annular groove 39 of a throttle valve 38 fully opens the opening area of an orifice 37, and a large quantity of fuel in the operating pressure chamber 30 is allowed to escape through an escape passage 33. As a result, a timer piston 28 is moved leftward and a cam roller 15 is advanced by the rotating amount of a roller ring 25. Accordingly, the injection timing of fuel becomes a timing corresponding to the fuel pressure in the operating pressure chamber 30.
Patent JP-S5828875-A (JP)
Title: Semiconductor integrated circuit
Inventor: KOYAMA MASASHI
IPC: H01L29/792
Filed: 1981-08-13
Abstract: PURPOSE:To eliminate ununiformity of writing levels different by bits by a method wherein, in a semiconductor integrated circuit including nonvolatile-memory transistors which have floating gate terminals respectively, writing can be performed on the same writing voltage and writing current for any memory transistor in cell matrices as well as electric current for writing is maintained at a lower value. CONSTITUTION:Common interconnection lines X1, X2...Xm are provided for the control gate terminals of nonvolatile-memory transistors; common interconnection lines Y1, Y2...Ym for the drain terminals of the same; and common interconnection lines Z1, Z2...Zm for the source terminals of the same. The gate terminals are connected to one of the common interconnection lines X1, X2...Xm for the control gate terminals of the said nonvolatile-memory transistors; the drain regions are connected to at least one of the common interconnection lines Z1, Z2...Zm for the source terminals of the said nonvolatile-memory transistors, and the source regions are provided with at least m units of MOS transistors which are formed on the same wafer as the said grounded nonvolatile-memory transistors.
Patent JP-S6018763-A (JP)
Title: Immunological measurement
Inventor: SHIYOUJI MASAHIRO
IPC: G01N33/543
Filed: 1983-07-13
Abstract: PURPOSE:To attain to simplify immunological measurement and to enhance the accuracy thereof, by using a first plate having a large number of wells each filled with a liquid and a second plate having protrusions inserted into said wells so as to provide play in combination while using the protrusions in immobilizing an antigen (antibody). CONSTITUTION:A first plate having a large number of wells each filled with a solution to be examined or a reagent solution containing an antigen (including hapten) or an antibody and a second plate having protrusions, which are inserted and immersed in wells at the corresponding position of each well and to which, for example, the antibody to the antigen in a specimen solution is adhered in an immobilized state so as to be capable of reacting the same with the solution in each well by the up-and-down movement thereof, are prepared. The first plate and the second plate are stacked to perform antigen-antibody reaction, and thereafter, a known amount of an antigen labeled with enzyme put in each wall of the first plate in place of the specimen solution and the second plate after reaction is stacked to the first plate to perform reaction. In the next step, the second plate is detached and the label amount of the unreacted labeled antigen in each well is measured. By this method, the measurement of plural specimens are enabled simply and simultaneously.
Patent JP-H04352223-A (JP)
Title: Variable volume system for magnetic disk
Inventor: TAKAHASHI MINORU
IPC: G06F3/06
Filed: 1991-05-30
Abstract: PURPOSE:To provide the system which effectively uses the capacity of the magnetic disk and easily performs capacity control. CONSTITUTION:The system consists of plural magnetic surfaces 9 where data are recorded, heads 8 which read and write the data, head access mechanisms 6 which place the heads in divisional operation, a head access controller 5 which controls the access of the heads, and physical volume information 4 which contains divided volume identification names, etc.
Patent JP-2000323798-A (JP)
Title: Semiconductor light emitting device and semiconductor laser
Inventor: HORIE HIDEYOSHI
IPC: H01S5/343
Filed: 1999-05-07
Abstract: PROBLEM TO BE SOLVED: To enable combination with a good external resonator by forming a layer which functions as an optical guide or a barrier in an active layer structure comprising n-type impurities at least in a part thereof. SOLUTION: A semiconductor light emitting device has a semiconductor laser with an active layer structure 5 comprising In, Ga and As as constituent elements on a GaAs substrate 1 and an external resonator in a projection direction of light of the semiconductor laser. The active layer structure 5 of a semiconductor laser has a layer which functions as an optical guide or a barrier and an active layer and at least a part of an active layer structure comprises n-type impurities. Thereby, stable combination with an external resonator in a wide temperature range and furthermore in a wide light output, region is possible and as a result, a region of single longitudinal mode oscillation is enlarged. It is because gain characteristic of a semiconductor laser becomes a wide band mode when compared to a conventional semiconductor laser that such results are produced.
Patent JP-H05205553-A (JP)
Title: Fitting structure of impact vibration generating component
Inventor: YAMADA SHIGETO
IPC: H01H50/04
Filed: 1991-05-30
Abstract: PURPOSE:To provide a fitting structure of an impact vibration, generating component capable of preventing the malfunction of a vibration protection component fitted to a fitting board because of generated vibration when an impact vibration generating component fitted to the fitting board operates. CONSTITUTION:A first long slot 6 and a second long slot 7 are provided between an impact vibration generating component 2 and a vibration protection component 3, both of which are fitted to a vibration damping fitting board 5 reducing the propagation of vibration energy, so as to form a detour lengthening the propagation distance of the vibration energy. Thereby the vibration energy can be successively reduced owing to the detour provided on the vibration damping fitting board having vibration damping action.
Patent JP-H07335893-A (JP)
Title: Semiconductor device
Inventor: OZAKI TORU
IPC: H01L29/786
Filed: 1994-06-09
Abstract: PURPOSE:To obtain a double gate transistor having symmetry in transistor characteristics, by forming a back gate electrode composed of a P-type impurity layer in a silicon substrate, in a self-alignment manner, so as to face a front gate electrode. CONSTITUTION:A P-type impurity layer 2 is formed by implanting ions through an oxide film 3 on the surface of a silicon substrate 1. A silicon film 4 is formed by sticking together silicon layers. After an oxide film 4 is formed by thermally oxidizing the surface of the silicon film 4, a poly silicon layer 5 to which P-type impurities are added is formed. A front gate electrode 5a is used as a mask, and N-type impurities are implanted, thereby forming a source.drain diffusion layer 6. At the same time, an N-type impurity layer 2a is formed. The region 2b of an N-type impurity layer 2 is formed, in a self-alignment manner, under the front gate electrode 5a, and turned into a back gate electrode, so that symmetry of a double gate transistor is improved.
Patent JP-H09311066-A (JP)
Title: Method and apparatus for measurement of axle load
Inventor: SAKAI MASAHIKO
IPC: G01G19/03
Filed: 1996-05-22
Abstract: PROBLEM TO BE SOLVED: To provide a method and an apparatus for the measurement of an axle load, by which the axle load of a vehicle being run can be measured precisely and simply. SOLUTION: The vibration as the up-and-down vibration of a road caused by the up-and-down vibration of both the front wheels and the rear wheels of a truck 17 being run is detected by a vibration meter 13. Vibration data Z (t) which is output from the vibration meter 13 is divided into a former half and a latter half on a time base. The former half and the latter half are Fourier-transformed respectively. The frequency and the phase of respective vibration terms of the front wheels and of the rear wheels are found. In addition, the load of the truck 17 being run is measured by a load meter 11. The axle load of the front wheels and the axle load of the rear wheels are found on the basis of axle-load data X (t) which is output from the load meter 11 and on the basis of the frequency and the phase of the vibration terms.
Patent JP-H05326057-A (JP)
Title: Microconnector and manufacture thereof
Inventor: IMAI AKIRA
IPC: H01R4/01
Filed: 1992-05-20
Abstract: PURPOSE:To provide a microconnector prevented from easily coming off, easy to mount and remove without improper contact by using an LIGA process to form the microconnector whose material is a shape memory alloy. CONSTITUTION:An LIGA process is used to prepare a resist 2 on a substrate 1, to form a resist pattern 2' by applying exposure and developing processes to this resist 2. A shape memory alloy is sputtered to the resist pattern 2' thus formed to obtain a microconnector. In this way, dimensional accuracy of the microconnector can be improved. Further by applying shape memory treatment to the shape memory alloy, the microconnector prevented from easily coming off, easy to mount and remove without improper contact can be provided.
Patent JP-H01296409-A (JP)
Title: Magnetic recording and reproducing device
Inventor: MIZUMAKI HIDETAKA
IPC: G11B5/027
Filed: 1988-05-25
Abstract: PURPOSE:To attain recording and reproducing without distortion by modulating an analog signal to a pulse signal, whose polarity is reversed with changes in level, to have a prescribed cycle and duty ratio and executing the recording and reproducing. CONSTITUTION:The input analog signal is converted to the pulse signal of a frequency to correspond to the signal level. This pulse signal is modulated to the recording pulse signal, whose polarity is reversed with changes in level, to have the prescribed cycle and duty ratio in a recording pulse signal generating means 25. The recording is executed by a magnetic head 26 for recording on the basis of this recording pulse signal and the reproducing is executed by a magnetic head 31 for reproducing. Accordingly, since the analog signal is recorded and reproduced as the pulse signal, the distortion is not generated in the reproduced signal even when a magnetic resistance effect type head for thin film is used and the recording and reproducing of high quality can be executed.
Patent JP-S619303-A (JP)
Title: Wheel cover for vehicle
Inventor: IWATA TAKAO
IPC: B60B7/04
Filed: 1984-06-21
Abstract: PURPOSE:To reduce air resistance, to improve appearance, and to prevent entrance of contaminant, by a method wherein in a title cover having spoke-like appearance, radial projection lines and metallic glossy layer are formed on the inner surface of a cover body made of clear synthetic resin, and the outer surface of the cover is smoothed. CONSTITUTION:A conical clear part 11b, extended radially from a central recess part 11a, is formed on a wheel cover body 11 made of clear synthetic resin, such as polycarbonate, and radial projection lines 11d and 11e are formed on the inner surface of the clear part in a manner that the projection lines cross each other. A metallic glossy layer 14 is formed on the surfaces of the projection lines 11d and 11e by hot stamp, and a protection film layer 15 is formed thereon. This constitution causes formation of the flush outer surface of the wheel cover body, and reduces air resistance. Further, the metallic glossy layer of the projection line can be seen from the outside in a manner that it glitters in a spoke-like manner, resulting in improvement of appearance.
Patent JP-S5252648-A (JP)
Title: Prepartion of optical fibers
Inventor: IMOTO KATSUYUKI
IPC: C03B37/018
Filed: 1975-10-27
Abstract: PURPOSE:To render it possible to prepare wide-band and low loss optical fibers by heating and reacting raw gases on the inner wall of a quartz glass pipe having on its outer surface a heat- and corrosion- resistant film for preventing devitrification to depositel the reaction product thereon, and crushing the glass pipe to thereby thicken its section.
Patent JP-S62285654-A (JP)
Title: Three-phase brushless motor
Inventor: SAKAMOTO SATOSHI
IPC: H02K29/00
Filed: 1986-06-03
Abstract: PURPOSE:To reduce a spiky torque ripple by mounting commutating poles having polarity reverse to main poles on both sides of the boundary of the different main poles in the detection region of a position detecting element for a rotor magnet. CONSTITUTION:Commutating poles 12N, 12S for removing a spiky torque ripple are fitted to the detection regions such as outer edge sections, to which a position detecting sensor for a rotor magnet 2 is faced oppositely, in the position detecting sensor in the rotor magnet 2. The commutating poles 12N, 12S are set up at polarity reverse to main poles 5N, 5S, and mounted at a position that separates only by an electrical angle of /pi4 from the boundaries of the main poles 5N, 5S.
Patent JP-H05324984-A (JP)
Title: Note receipt/payment device
Inventor: NEI HIDETO
IPC: G07D9/00
Filed: 1992-05-21
Abstract: PURPOSE:To prevent the stop of operation of a note receipt/payment device and to reduce the burden of a restoring job on an operator by automatically remove the notes jammed in a payment transaction mode. CONSTITUTION:A drive means freely rotatably drive a transfer path as well as the type-based temporary note accumulating mechanisms 39-41 and the type- based note separating mechanisms 45-47 of a cash receipt/payment unit 53 in the normal/reverse direction. Then, the jammed note detecting means 74a-74b detect the occurrence of jams on the transfer path. Furthermore, the jammed note storing boxes 71-73 are provided near the cash type-based storing boxes 33-35. When the jammed notes are detected by the means 74a-76b, the mechanisms 45-47 are revesely rotated by the drive means to return the jammed notes to the cash type-based temporary holding plates 42-44. Then, these notes are ejected from the plates 42-44 and stored in the boxes 71-73.
Patent JP-H05323821-A (JP)
Title: Cleaning device for fixing device
Inventor: HANATSUKA KAZUSHI
IPC: G03G15/20
Filed: 1992-05-21
Abstract: PURPOSE:To increase certainty of stain removal by a roller in a fixing device and to sustain the stain removing effect for a long period without increasing the number of the cleaning devices by making the cleaning surface in approximately a V-shaped form. CONSTITUTION:The cleaning surface 14a of a cleaning member 14 has approximately a V-shaped form and when the cleaning member 14 is pressed to a heat roller 11, the cleaning member 14 comes in contact with two places of the contact points 14b, 14c apart in the circumferential direction for the heat roller 11 (being in a linear form in the longitudinal direction). Thus the stain removal can be performed in two stages for the heat roller 11 and the stain removal is extremely sure. Also since most part of the cleaning surface 14a is efficiently used for the stain removal the removal effect sustains for a long period. Besides since a space 17 appears between the contact points 14a, 14b, the part becomes a deposit place of the removal stain and from this point the removal effect be sustained for a long period.
Patent JP-2000321380-A (JP)
Title: Alarm clock
Inventor: MINATO HIROYUKI
IPC: G04G13/00
Filed: 1999-05-10
Abstract: PROBLEM TO BE SOLVED: To provide an alarm clock providing a wake-up alarm at an optimal time according to a condition of a traffic congestion by using road traffic information. SOLUTION: If a setting mean 4 setting a time sets an arbitrary time, an alarm clock 1 provides a wake-up alarm from an alarm mean 9 when the set time is reached. The alarm clock 1 is provided with a receiver unit 12 receiving road traffic information, and a control mean 15 receiving the road traffic information from the receiver unit 12, calculating a time difference between a congestion time on an arbitrary traffic route and the set time set by the setting mean 4, and controlling to correct an activation time of the alarm mean 9 according to the time difference.
Patent JP-H04328034-A (JP)
Title: Slip control device for vehicle
Inventor: TSUYAMA TOSHIAKI
IPC: B60W10/188
Filed: 1991-04-30
Abstract: PURPOSE:To perform adequate slip control in accordance with a road surface condition, in the case of a slip control device for a vehicle where a driving force distributing means for distributing an engine output to right/left drive wheels is provided in a power transmitting route reaching the right/left drive wheels from an engine. CONSTITUTION:By an ECU40 for controlling action of opening/closing valves 26, 27, 31, 32 and relief valves 33, 34 in a brake control system 15 and action of a throttle opening adjusting actuator 38 for adjusting an opening of a subthrottle valve 29 based on signals from wheel speed sensors 41 to 44 for detecting a rotational speed of each wheel 1 to 4, a spin condition of the right/ left rear wheels 3, 4, which are drive wheels, is periodically detected. Simultaneously, split decision is performed in accordance with a split decision map preset based on the detected spin condition of the right/left rear wheels 3, 4. An engine control target value of limiting an engine output is increased at the time of split decision.
Patent JP-H11330008-A (JP)
Title: Dicing method
Inventor: YAMAMOTO HIDENORI
IPC: H01L21/301
Filed: 1998-05-12
Abstract: PROBLEM TO BE SOLVED: To provide a dicing method for cutting and dividing a semiconductor wafer into chips without damaging blades and causing contamination to stick on the surface of the semiconductor wafer. SOLUTION: This method consists of a process for integrally sticking the rear side of the semiconductor wafer and a frame 13 with a tape 12, a process for hardening a sticky layer 14a of a UV tape by having a UV tape irradiated with ultraviolet rays, a process for releasing the sheet layer of the UV tape while remaining only the hardened sticky layer 14a on the surface of the semiconductor wafer, a process for dicing the semiconductor wafer together with the hardened sticky layer, and a process for releasing the hardened sticky layer from the surface of the semiconductor wafer.  As a result, since the viscosity of the hardened sticky layer 14a is almost eliminated, it will not be rolled into the blade or clogged, moreover without damaging the blade or furthermore without contamination sticking on the surface of the semiconductor wafer because of the existence of the hardened sticky layer, dicing of cutting can be efficiently executed.
Patent JP-H10321069-A (JP)
Title: Attachment structure of grommet to wire and manufacture of the grommet
Inventor: MORI HIROSUKE
IPC: H01B17/58
Filed: 1997-05-19
Abstract: PROBLEM TO BE SOLVED: To prevent gaps from occurring between wires in the case of a grommet formed by insert-molding the wires. SOLUTION: A grommet 10 is equipped with a small diameter tube part 11 for putting a plurality of wires w therethrough and a conical tube part 12 whose diameter is enlarged from one end of this small diameter tube part 11 and is provided with a locking recess part 13 for a member to be attached provided on an outer circumferential surface of this conical tube part 12. In this case, a region, where a plurality of wires are juxtaposed with spaces, then insert-molded, and formed into a grommet, is provided on at least a part of the small diameter tube part 11, a resin 14 being filled between the wires in this insert-molded part, thereby eliminating gaps.
Patent JP-S61287349-A (JP)
Title: Address duplication detecting system
Inventor: NAGATA SATORU
Filed: 1985-06-13
Abstract: PURPOSE:To ensure the detection by exchanging an ID exchange command and an ID exchange response between plural devices so as to detect the duplication of address. CONSTITUTION:A network system communicating equally with optional opposite party between plural equipments is provided with a means 4 sending an ID exchange command XID command addressed to the own equipment included in the data part of a random number NR, a timer means 11 to supervise an ID exchange response and the XID response from an opposite equipment at the transmission of the XID command and a means 6 receiving and analyzing the XID command. Further, the means 4 receiving the XID response and sending the XID command to a sender equipment, a means 7 receiving the XID response and analyzing it, a means 8 comparing the random number of the received XID response with the random number NR added to the sending XID command and a counter means 12 counting the retransmission number of times of the XID command are provided. Then the duplication of address is detected by exchanging the XID command and the XID response for plural number of times.
Patent JP-H11327604-A (JP)
Title: Process controller of closed loop system including pid adjusting device
Inventor: SONODA TAKASHI
IPC: G05B11/36
Filed: 1998-05-12
Abstract: PROBLEM TO BE SOLVED: To obtain desired performance without depending on the magnitude of control gain to be operated by making an output of an integrator to which the error between a target value differentiated through a primary delay element and a controlled variable is inputted proportional gain. SOLUTION: In a control gain adjusting device, a desirable target value α* is obtained by such a manner that a differentiator 18 differentiates a signal whose disturbance is eliminated from a target value r(t) 6 by a primary delay element 20, and inputs it to an absolute value generator 19 and its output is multiplied by a value αthat is set by a constant generator 21. Also, an error correction circuit obtains an absolute value ϕ* from an absolute value generator 26 by differentiating, using a differentiator, controlled value y(t) at a differentiator 24, controlled variable y(t) 4 from the value α* through a primary delay element 25. Next, a subtracter 23 calculates an error (α*-ϕ*), a value that is obtained by a function generator 28 provided with a dead zone is inputted to one of a multiplier 27 through a coefficient unit 29 and an output of the generator 28 is inputted to the other. An output of the multiplier 27 is operated by an integrator 30 having limitation and becomes a proportional gain value of a PID adjusting device as an output K(t) 17.