Patent GB-1405673-A (GB)
Title: Method and apparatus for the determination of the percentage of zeros in a binary digital data word
IPC: G06F7/60
Filed: 1972-09-01
Abstract: 1405673 Selectively inverting data PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 1 Sept 1972 [4 Sept 1971] 40576/72 Heading G4C At least some of the bits of a data word are inverted if the percentage of zeroes in the word lies outside a predetermined range. As described the word is divided into groups of sub-words, the groups being looked at sequentially and subwords within a group being selectively inverted until the percentage of zeroes in the resulting modified word lies within the desired limits. The sub-words may be of variable length. In the embodiment of Fig. 7 the words are divided into eight sub-words S1-S8, held in a store FF, each sub-word having an associated inverter X1-X8 and zero determining means U1-U8, the latter being connected to a group zero determining unit V connected to a deciding unit W controlling the inverters. First the percentage of zeroes in the word is determined and if it lies between 44% and 56% the word is written into for example a core or semi-conductor store unmodified. Otherwise all sub-words of a group A (Fig. 6) containing less than half 1s are inverted. The percentage of 1s in this modified word is then determined and if it lies between 44% and 56% the word is written into store. If it is less than 44% a second group B2 of sub-words is treated. If it is greater than 56% a third group B1 forming a sub-group of A is reexamined. This process is repeated until the number of zeroes lies within the required limits. Zero determining means (Fig. 8, not shown).- The outputs of flip-flop (FF1-FF4) storing the bits of a sub-word are connected to the bases of transistors (T1-T8) to render them selectively conductive, the conducting currents being added across resistors (R5, R6) resulting in terminals (K12, K13) carrying voltages proportional to the number of ones and zeroes respectively. A difference amplifier (A1) with feedback is driven to saturation if the sub-word contains more ones than zeroes.  Control circuitry (Fig. 9, not shown).-The output terminals (K12, K13; ... K82, K83) from the zero determining means for each of the sub-words are connected to associated transistors (T11, T13; ...T81, T83), the first terminal also being connected to a second transistor (T12 ... T82). The currents through the first transistors (T11-T81) representing the number of ones in each sub-word are added and applied to a feedback amplifier (A5) to derive a signal (L2) indicating whether there are more ones than zeroes in the word. Similarly currents through the second transistors (T12 ... T82) are added and applied to a second feedback amplifier (A4). If however a sub-word is being inverted (indicated by the state of an associated book keeping flip-flop (F11-F81) the current from the other transistor (T13 ... T83) is used. If the percentage of ones exceeds 56% the output of an amiplifier (A2) becomes high and if it is less than 44% the output of a further amplifier (A3) becomes high, these amplifiers controlling an OR-gate (03) which generates the "proceed" or ''terminate process" signal. Logic circuitry connected to the outputs of the amplifiers (A4, A5) controls the deciding circuitry W.