Patent GB-1464650-A (GB)
Title: Data processing system
IPC: G06F9/48
Filed: 1974-12-17
Abstract: 1464650 Data processing HONEYWELL INFORMATION SYSTEMS Inc 17 Dec 1974 [17 Dec 1973] 54422/74 Heading G4A In a data processing system in which a central processing unit executes instructions in a native mode and an emulation unit coupled to the CPU executes instructions in a non-native mode to emulate a different CPU, when the emulation unit is in its wait state means are included to permit the CPU to continue processing in the native mode. The system includes a processor sub-system (101, Fig. 1, not shown), peripheral sub-system (103) (e.g. disc and tape stores) and a semiconductor capacitive (MOS chips) storage subsystem (102). The processor sub-system includes emulation facilities, a computational unit and a buffer store which is accessed at each memory read, if the required information is not there it being fetched from main memory. An associative memory (132) stores the most recently used addresses in main memory. Of 33 registers in the CPU, 16 are general registers used to manipulate fixed point binary numbers, 8 are base registers used during address computation, and 4 are optional scientific registers. There is also an instruction counter register (containing the address of the current instruction), a status register, a stack register (T register) holding a pointer to the top of a stack associated with the currently running procedure, a boundary address register holding the upper limit addressable by software and a hardware control mask register. Process control block (Fig. 4, not shown).- Each process has its own process control block PCB, the block associated with the currently running process being addressable using a J table word and the J number of the process (held in system base) to access a J table, the address contents being used together with the P number of the process (also in system base) to access a P table to derive the address of the PCB. All other PCB's are addressed using their associated (J, P) logic name. The PCB includes two words (ASW) which hold the address of two segment tables for large (up 2<SP>22</SP> bytes) and small (up to 2<SP>16</SP> bytes) segments assigned to the process. Segments are addressed by a segmented address comprising a segment number and a relative address within the segment. Procedure and data segments are grouped into a 4 class hierarchy in a ring system (level zero being the innermost) with (1) a procedure having only free access to data in a relatively outer ring, (2) a procedure only being able to branch to a procedure in a relatively inner ring and (3) data segments having two ring values representing the maximum read and write ring values for a procedure to access in the read and write modes. Procedure calls.-These are used to transfer from one procedure to another and necessitate the construction of a stack frame (stacks residing in stack segments) with storage space assigned for the saving of base, general and scientific register contents. One stack segment is assigned to each protection ring per process with the start addresses for rings 0, 1, 2 being held in the process control block. Process dispatching.-Processes move from one state to another (there being 4 possible states-running, ready, waiting, suspended) under the control of a dispatcher which uses queues to manipulate processes in the ready or waiting states. The GO entry in a G table (801, Fig. 9, not shown), which is accessed using a word in system base points, together with an internal process queue word (IPQW) (also in system base), to a GO segment which contains process links and active processes and free process links of suspended processes. Each link specifies the process name (J, P), the process priority and a pointer to the next process link in the queue, there being separate ready and wait queues. When the running process changes state the dispatcher uses the (J, P) name at the head of the ready queue to access the process control block of the new process. Associated with each wait queue is a semaphore (in a semaphore descripter segment) indicating why the processes are waiting and pointing to the head of the wait queue. The semaphore receives a signal from a process when the required information is available (a V operation) and sends the signal to a process waiting for the information (a P operation), Bytes stored in the process control block contains the local name of the semaphore to which the process (if waiting or suspended) is linked. The dispatcher performs a rolling out operation on a process losing control of the system to effect storage of the contents of its register and to place it in the appropriate queue before performing a rolling in operation on the new process. Control unit (Fig. 13b, not shown).-Control store unit (1301) is formed of both a bipolar integrated circuit programmable read only memory and a random access store, each location storing an 84 bit instuction to operate the system in (I) native mode, (2) emulation mode, (3) concurrent native and emulation mode or (4) diagnostic mode. The read-out micro instruction is decoded to provide sequential control signals for the system, 3 bits representing sequencing, 23 bits representing branching and/ or micro operation, 14 bits representing constant generation or designation, 8 bits representing data bus, 32 bits representing micro operation and 4 bits representing checking. Data extension mode.-This is entered by performing a 32 bit native mode instruction EXDE, 8 bits being the OP code, 8 bits a DEXT field (i.e. the number of the data extension) and 16 bits the DEA field (the data extension argument). When this instruction is detected by a detector 1518 (Fig. 17) the DEXT and DEA field are stored in buffer 1520. Provided the DEXT field is not zero, comparator 1524 enables gates 1530, 1532 to supply from the process control block 400 of the associated process a DETSZ field (8 bits defining the number of entries in a data extension table) and a DETA field (24 bits giving the absolute address in main memory of the table) to buffers 1534, 1536 respectively. Comparator 1538 enables gate 1544 provided that the DEXT field is less than the DETSZ field so that the DETA field is then used to select the required table. Gate 1546 is also enabled so that the DEXT field to select the required bit in the table. If it is set indicating that emulation is allowable, comparators 1556-1 ... 1556-N are enabled in turn to compare the DEXT field with numbers from DEXT blocks 1557 ... 1562, the numbers being set in the blocks only if the hardware/firmware is present in the system. At comparison OR gate 1566 is enabled to enable gates 1570, 1572 so that the DEA field is fed to the emulation unit. If more than one instruction is to be performed in non-native mode gate 1568 is also enabled so that the DEXT number is stored in the process control block in case the process is interrupted. The emulator runs as two processes, one acting as an interface between the emulator and operator and one being responsible for execution of the emulated central processor. It is structured into three components, a firmware capability feature CF, an emulator software package ESP and a peripheral conversion package PCP. The CF emulates most emulated central processor (ECP) instructions, detects native events representing emulator type interrupts (using semaphores) and processes these interrupts. The ESP has an emulator control function used for setting up data to be communicated to the CF and an auxiliary services function used inter alia for emulation of the emulator wait state. The memory of the ECP is a large segment in the CPU memory for which a descriptor is permanently maintained, the memory being addressed using the ECP address and the segment descriptor. A double word represents the ECP current program state (PSW). Communication between firmware and software of the emulator is effected via a set of tables in an emulator communication region (ECR). Entry of the ESP from the CF is effected by the latter storing an appropriate service class number (SCN) in the interrupt flag word of the ECR. SCN's are grouped into input/output execution, memory protect service, asynchronous event detection and exception ECP condition detection. Exceptional ECP conditions (Fig. 21).- Included in this group is the ECP wait state which is indicated when the CF has detected the wait state bit set in the PSW in the ECR. If no interrupts are allowable (indicated by the PSW system mask being all zero) a "hard wait" state is entered presenting wait state simulation and control is returned to the CF. Otherwise wait state simulation is initiated and the ESP monitors the wait state using an interval timer and notifies the operator periodically of how long the wait state has been in effect. Wait state simulation functions by the ESP causing an internal timer to be set and to post a message in a semaphore SEM-M in the ECR. The ESP then queues on SEM-M until the semaphore receives a message. If the message is that the ECP timer has run out an external interrupt flag is set and if the interrupt is allowed control is transferred to the CF so that the system continues processing in the emulation mode. When no allowable interrupts are pending a control flag is set enabling the CPU to operate in native mode. If the message is an input/output event, an input/output interrupt flag is set and the interrupt is processed if it is allowed. If the message is that the internal timer has run out, if the ECP timer has become negative the interrupt flag is set. Otherwise a wait state counter is incremented and if its count indicates that a monitoring period, specified in the ECR, has elapsed a message is sent to the operator. Otherwise the internal timer is set again. In this way the operator is signalled at regular intervals that his system is not functioning in an emulation mode.