Patent GB-724460-A (GB)
Title: Improvements in or relating to electric binary pulse code translating apparatus
IPC: H03M7/16
Filed: 1953-03-24
Abstract: 724,460. Pulse code modulation systems; pulse circuits. WESTERN ELECTRIC CO., Inc. March 24, 1953 [March 29, 1952], No. 8067/53. Classes 40 (5) and 40 (6). A pulse group representing a number in a first binary code is translated into another pulse group representing the number in a second binary code by a disparity recognizer, which provides an output pulse of one kind on the application of like pulses to its two input circuits and a pulse of another kind when unlike pulses are applied, the pulse group to be translated being applied to one of the input circuits and the same or the translated group being applied to the other input through a single pulse period delay device. As described, the two codes are the conventional and the reflected binary code described in Specification 663,872, and the two kinds of pulses are positive and zero or negative and zero representing 1 and 0. Circuits are described for translating each code into the other with input pulse groups in which the pulses are in order of increasing or decreasing digital significance. In an embodiment suitable for pulses in order of decreasing significance and conventional to reflected code translation or vice versa incoming pulses are applied to input 11, Fig. 1, of the disparity recognizer circuit 10, the translated output being derived from conductor 13. The second input 12 is fed, through the single pulse period delay device 15 and normally closed switch 16, with pulses from a switch 18 which is set according to the translation it is desired to effect. For conventional to reflected binary code, the switch 18 is in its upper position so that the second input pulses are the incoming pulses, while for translation from reflected to conventional binary code with switch 18 in its lower position the second input is the translated output from conductor 13. In each case switch 16 is opened while the most significant digit pulse of a group is arriving at the first input 11 of the disparity recognizer so that the first comparison is with zero pulse on the second input. Switch 16 is opened for this purpose by an auxiliary pulse applied to its control terminal 19 from a generator 20 controlled by the incoming pulse train. In an embodiment for translating from conventional to reflected binary code, when the pulses are in order of increasing digital significance, the direct input to the disparity circuit is through the normally closed switch which is opened while the first digit 'pulse is arriving and the second input is fed from the incoming pulses through the single pulse period delay circuit, Fig. 6 (not shown). A further embodiment, for translating from reflected to conventional binary code when the pulses are in order of increasing digital significance, comprises a disparity recognizer 70, Fig. 7, having inputs 71, 72 and an output 73. Input 71 receives the input pulses and input 72 is connected to the output 73 through the contacts of a relay 83 and a single pulse period delay device 75. The latter also feeds a circuit 76 which introduces a delay of n 1 code elements, where n is the number of digits in a group, the output of circuit 76 being connected to a phase splitter 77. One or other of the two outputs of the latter is selected by contact 79 of relay 80 to be fed to the output conductor 78. The relay 80 is controlled by a double stability multivibrator 81. The pulse generator 82 produces a pulse when the most significant output digit pulse of a group appears at the output 73 of circuit 70 and operates relay 83 to disconnect this pulse from delay device 75, and feed it to the multivibrator 81. Thus it is the nature of the last output pulse from circuit 70 which decides the position of contact 79 and hence from which output of the phase splitter 77, the translated pulse group is fed to the output conductor 78. The disparity recognizer may comprise, in one embodiment, a transformer, the two inputs being applied to the terminals of the primary winding 28, Fig. 2, the ends of the centre-tapped secondary 24 being connected through rectifiers 25, 26 to the output terminal. The circuit is balanced and the output zero for similar inputs but for dissimilar pulse inputs a pulse occurs at the output. In a second circuit, designed for pulse inputs of opposite sign, the inputs are applied to the grids of triodes 30, 31, Fig. 3, the commoned anodes feeding one end of a centre-tapped coil 32 arranged like the secondary coil 24 of Fig. 2, with rectifiers 33, 34 having a common output terminal 13. With no inputs, or simultaneous positive and negative inputs the anode potential is unvaried and no output pulse occurs. With a single input only on either valve a positive pulse occurs at terminal 13. In a further arrangement, the two inputs of positive pulses are applied to opposite corners A, C, Fig. 4, of a bridge of rectifiers 40, 41, 43, 44, the other corners B, D being connected through resistors R1, R2, respectively, to the positive and negative terminals of a voltage source and also respectively to the grids of a difference amplifier 45 comprising a pair of triodes V2, V1, having a common cathode resistor R7. With two zero inputs there is no pulse output. If a pulse occurs simultaneously at both inputs, points B and D both rise in potential and due to the degenerative action of the cathode resistor the anode potentials only change slightly. If a pulse occurs at one input only corner B remains fixed in potential and corner D rises so that V2 is cut off by the rise in current in resistor R7 and valve VI. The resultant pulse at either anode may provide the output pulse. In a fourth circuit the two inputs of negative pulses are applied to the grids of triodes V3, V4, Fig. 5, respectively. Due to the large amount of cathode feed-back the decrease of anode current when pulses are applied simultaneously to both grids is only small. The junction B<SP>1</SP> of rectifiers 50, 51, connected respectively to the triode anodes, and which is connected to the output lead 55, rises negligibly in potential. When a pulse is applied for example to valve V4 only, the voltage across rectifier 54 reverses to render it conducting so that V4 is cut off, its cathode current being transferred to V3. The resulting negative pulse at the anode of V3 renders rectifier 50 conducting to transfer the pulse to the output 55. Specifications 652,908 and 694,030 and U.S.A. Specifications 2,527,649, 2,527,650 and 2,546,316 also are referred to