Patent GB-908052-A (GB)
Title: Improvements relating to electrical storage arrangements
Inventor: BLOOMFIELD JAMES WARMAN
IPC: H04M1/272
Filed: 1960-03-11
Abstract: 908,052. Automatic exchange systems. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. March 2, 1961 [March 11, 1960], No. 8727/60. Class 40 (4). In an arrangement for the sequential storage and transmission of digits, each of which is received as a distinctive combination of markings on a plurality of input marking wires mW ... mZ (Fig. 1), there is provided for each marking wire a register Rw . . . Rz consisting of a plurality of bi-stable circuits S1. . . S10, the bi-stable circuits occupying corresponding positions in the several registers together constituting a storage unit for one digit, the bi-stable circuits S1 of the first storage unit being set by markings on the corresponding input marking wires to record a received digit, and each of the bistable circuits of the other storage units being set in response to the resetting of the bi-stable circuit immediately preceding it in the same register, thus to progress the received digit along the registers step-by-step. Recurrent resetting pulses are applied to all the bi-stable circuits of each register in such manner that an applied resetting pulse resets a bi-stable circuit in a particular storage unit only if the bi-stable circuits in the immediately succeeding storage unit are all unset. The outpulsing circuit includes a counter which counts recurrent pulses fed to it, and impulse control means responsive to the counting out of the counter for permitting a resetting pulse to reset any set bi-stable circuit in the last storage unit, the resetting of the last bistable circuit of a register marking a corresponding output marking wire so as to extract a digit from the last storage unit and thus cause the counter to assume a condition representing the complement (with respect to the counter capacity) of that digit, so that the number of pulses required to count out the counter corresponds to the digital value, that number of pulses being transmitted. Bi-stable circuits employed,-These are bistable trigger circuits each employing a pair of transistors, and as they are all identical, only that constituting the keying control circuit KC Fig. 2) will be described in detail. Two transistors Tr1, Tr2 have their collectors and bases cross-connected by capacitors Cx1 Cx2 in parallel with resistors Rz1, Rx2, the collector being also connected via collector resistors Rc1, Rc2 to negative supply terminals (-), while the bases are connected via base resistors Rb1 Rb2 to positive terminals (+), the emitters being directly grounded. The unset state is with Tr2 fully conductive, the circuit being set by the application of a positive signal to the base of Tr2, and reset by a similar signal applied to the base of Tr1 Setting and resetting gates GSK, GRK are provided. The components of other similar gates will be identified by the references, in brackets, of the corresponding components of KC, or its input gate GRK or GSK. Operation of key-sender (Figs. 1 and 2). When this is taken into use all the register storage circuits are reset, while the four counting stages C1-C4, the inter-train pause circuit IT, the impulse control circuit IC, and the keying control circuit KC are set (in any suitable manner-not shown), and the register pulse generator RG commences producing pulses on the common pulse lead PL. The dialling pulse generator DG is inhibited as the set state of IC holds Tr6 fully conductive. On depression of one of the digit keys K1 . . . K10, ground is applied to the marking wires mW ... mZ to set the S1 storage circuits in accordance with the complement of the digit keyed (with respect to 16). The k<SP>1</SP> contact of the depressed key applies a positive (ground) bias to resetting gate GRK and to the hold-off gate GH, so that the next pulse produced by RG resets KC, whereafter further pulses from RG are ineffective while the key is depressed. When the key is released, the next pulse from RG passes through the hold-off gate GH to the gate GSK and, with all the S2 storage circuits unset, passes therethrough to set KC. The resulting rise in potential of lead PL1 resets, via the relevant GR gates, any S1 storage circuits which had been set, the resetting resulting in the setting of the corresponding S2 storage circuits. The next pulse from RG passes via the resetting gates RG of the S2 storage circuits to reset those so set, thus setting the corresponding S3 storage circuits; successive pulses producing similar progressing of the stored digit until it is stored in S10. Subsequent operation of the same or another digit key causes setting of the relevant S1 storage circuits but KC is not set until all the S2 storage circuits are unset, signifying that the first digit is clear of the S2 storage circuits. The second digit is progressed in like manner to the first and, assuming that the first is still in S10, will be retained in S9. Further digits are stored in like manner, until finally the S1 storage circuits are held set to record digit markings which they cannot clear. On release of the digit key, the set state of the S1 circuits then results in lamp Lf in the register-full circuit LCF being lit. The repetition rate of the RG pulses is much greater than the maximum rate of keying, so that in normal working the S1 storage circuits are always clear. In practice the first pulse on PL 10 after the S10 circuits are set to store the first digit, resets those circuits thus transferring the digit stored to the counter SC to reset the relevant stages C1 . . . C4 thereof. The impulse control circuit IC is also reset to back off Tr6 in the dialling pulse generator DG which then produces positive pulses which are applied to C1 to drive SC, and negative pulses which are applied to the impulsing circuit IP to cause impulsing of relay P. When C4 is set at the end of the counting-out, it resets the inter-train pause circuit IT, which in turn resets any of the stages C1 . . . C4 which are strapped to their resetting input gates GR3 by strappings w, x, y or z, so that by selective use of these strappings the counter SC can be preset to count out an intertrain pause. Relay P does not respond during this pause because in the unset state of IT, Tr8 in circuit IP is non-conductive. When C4 is set at the end of the pause, it sets IT which sets IC. The resetting gatse GR of the S10 storage circuits are thus opened and the next pulse on PL10 resets those storage circuits so that they can receive the next digit markings, if any. While digits are stored in RW-RZ, IC is only momentarily set by IT and Tr9 is not conductive long enough to light lamp Le in the register-empty circuit LCE, so this lamp lights only when IC remains set through the registers being empty. Operation of registers in response to incoming impulses.-This is described with reference to Fig. 3 (not shown), which illustrates a receive pulse counter which is set by an incoming impulse train and marks the wires mW ... mZ accordingly.