Patent GB-1455539-A (GB)
Title: Pulse tracker ranging system with increased resolution
IPC: G01S13/66
Filed: 1975-03-03
Abstract: 1455539 Radar SPERRY RAND CORP 3 March 1975 [22 March 1974] 8709/75 Heading H4D A digital range DME tracker system is described giving range resolution sufficient for use in terminal navigation instrument landing systems. Using an economical 16 MH 3  clock-pulse an inadequate resolution of À005 miles would be produced. To achieve the required resolution of À001 miles using the same clock-pulse frequency, a digital second order range tracking servo is used which implements the equation:- where PR N+1  is the predicted range for sample time ( N+1 ) computed at time N, PR N  is the predicted range for sample time N, computed at time ( N-1 ), #R N =MR N -PR N  where MR N  is the measured range at time N, and K 1  and K 2  are servo loop constants less than one. In general the ranging system comprises a range counter 14, Fig. 1 providing pulses indicating predetermined events within each measuring interval as started by the transmission of an interrogation pulse T1RX, a range gate generator 25 for providing a range gate for coincidence investigation of any received response pulses P1RX, a measured range counter 23 for determining, using the MH 3  clock pulses, the timing of any such found coincident response pulses, a set of holding registers 34, 35, 36 for temporary storage of various ones of the parameters in the above equation, a multiplexer system 37, 371 for combining, under the control of a circuit 13, required outputs of the range counter 23 and the three holding registers, to thereby provide a combined signal, a distributor 43 for feeding said combined signal back to the measured range counter 23 or one of the registers as controlled by the circuit 13 and a shift register 53 for receiving from a a BCD counter 50 a course measurement of range and from binary to BCD converter 54 a fine measurement of said range. Description of system in tracking mode.-It is assumed that the system of Fig. 1 has acquired and locked on to a valid pulse and is tracking on the received PIRX pulses. Each interrogation signal P1TX at terminal 10 causes gate flip-flop 11 to be set, which in turn enables AND gate 12 to pass 16 MH 3  clock pulses to range counter 14. This first of all produces, at output 15, a pulse 60 Á after the interrogation pulse representing the fixed transponder delay, and an R-max signal at output 16, which signal resets the range counter 14 back to zero and resets flip-flop 11, thereby disabling the AND gate 12, stopping the count until the next P1TX pulse. The clock pulses are at 16À18753 MHz. producing an exact range resolution of À005 nautical miles. The 60 Á pulse sets flip-flops 17 and 22 thereby enabling AND gates 21 and 22 to start passing the clock pulses. The clock pulses gated through 21 pass to a 16 stage down-counter 23, only the 13 most significant stages being utilized in the countdown mode. The 16 stages are also utilised as a parallel register, the significant three least significant stages of the counter being used in a tracking function to increase the resolution. In a counting mode the counter operates in the modulo R-max maximum range fashion, the 13 most significant stages of the counter having a maximum count R-max. The counter is reset by a signal from timing circuit 13. A 16 stage down-counter 25 receives the output of the clock pulses through AND gate 22. The counter and range gate generator 25 has a decoder providing an early gate pulse at output 26 and a late gate pulse output 27. The range gate pulse on output 30 having a leading edge coincidence with the leading edge of the early gate pulse and the trailing edge coincident with trailing edge of the late gate pulse. The early gate is produced when the counter or range gate generator 25 reaches a predetermined count just before zero count and the late gate pulse is generated when the same count is reached beyond zero count, i.e. the zero count occurs at the centre of the range gate. The range gate pulse at 30 gates through the received pulse P1RX at gate 31. The gated through received pulse then resets, via OR gate 32, flip-flop 17. The late gate pulse resets flipflop 20 to thereby stop the countdown of the range gate generator 25. The range gate generator 25 has been preset to a predicted range PR N  and the measured range counter 23 is reset to zero count by a signal on lead 24. The resetting of gate 17 disables AND gate 21, thereby stopping the passage of the clock pulses to measured range counter 23, thus stopping the count. Range gate generator 25 continues counting the clock pulses, via AND gate 22, until said gate is disabled, by the flip-flop 20 being reset by a late gate pulse from said rate gain generator. Range counter 23 therefore has a measurement of the time between the P1TX and the P1RX pulses minus the 60 Á fixed transponder delay, i.e. the distance between the airborne interrogator and the ground transponder 23. The counter 23 counts backward from zero to produce a binary number indicating the negative measured range (-MR N ). Due to the prediction of the range, the range gate generator counter should be at least near zero count when the P1RX pulse is received. The range tracker 33 analogues the said tracking equation Multiplexer 37 combines the output of measured range counter 23 holding register 34 and holding register 35, whilst multiplexer 37<SP>1</SP> combines the outputs of the three holding registers 34, 35, and 36. Control circuit 13 produces signals on lines 14 and 14<SP>1</SP> which cause a desired input to output connection. The output of multiplexer 37 can also be caused to be zero by signal from control 13. The outputs of the multiplexer are added at 42 and fed to a distributor 43. The binary coded decimal counter 50 provides an output indication for the system and receives a clock input from the control circuit 13 and also a reset impulse. The measured range counter sends a signal to the control circuit 13 when it has reached a zero count. Thus when the measured range counter has counted down to zero at a time indicative of the range, the BCD counter has by then counted up to a count also indicative of the range, the impulse from the measured range counter to the control circuit 13 stopping the countdown and countup such that the BCD counter 50 retains the range count. The three least significant stages of register 36 provide an output for binary BCD data converter 34, which passes the converter data into a shift register 53 which also receives the output of BCD counter 50, the output from the BCD counter 50 produces range measurements to resolution of 1/100th of a nautical mile whilst the converter 54 produces data to the resolution of 1/1000th. The logic and decisions unit 56 determines whether the P1RX signal is a true or false reply, the unit 56 also resets gate flip-flop 17 if the P1RX pulse fails to occur within the range gate. Assume the (N - 1) pulse transmission interval has just occured whereby the range counter 14 and measured range counter 23 are reset to zero. The holding register 36 is storing the predicted range PR N  for the nth transmission interval. The shift register 53 stores this predicted range in BCD format and the register 34 contains the accumulated sum of past range errors. During the nth pulse transmission interval the P1TX pulse causes control circuit 13 to order the shift register to shift the predicted range for the nth interval to provide the output data for the system. The AND gate 31 is enabled by the range gate in accordance with this predicted range when the P1RX signal is received hopefully within the time of the range gate pulse. Countdown in the measured range counter 23 stops. The end of range signal then produced by range counter 14 orders the control circuit 13 to perform a series of steps to compute the above tracking equation using the measured and stored ranges. Step 1.-The measured range counter 23, because it is a countdown counter provides a negative 2s complement of MR N  on lead a of multiplexer 37, i.e. -MR N  whilst holding register 36 holds and produces on lead d<SP>1</SP> the PR N  signal. Control circuit 13 causes input lines a and d<SP>1</SP> to be connected to the respective multiplex outputs where they are combined in adder 42 to produce a signal PR N -MR N  this is equal to the negative of the difference required, whereby said sum signal is fed via distributor 43, through an inverter 45 to holding register 35 to produce the required difference signal #R N . Logic and decision circuit 60 may indicate that an erroneous measurement has been made or a miss recorded. This therefore produces a signal on line 57 resetting the contents of register 35 to zero. Step 2.-Holding register 34 has been storing the accumulated sums of the error signals #R N  up to the N-1 return. To update this summation input 6 of multiplexer 37 and input C<SP>1</SP> of multiplexer 37<SP>1</SP> are combined in adder 42 to produce the updated sum and fed via distributor 47 back into register 34. Step 3.-This is used to provide the coefficient K1 and the term K1#R.K1 is less than unity and is a binary multiple and is produced by right shifting the #R and/or by summing a priority of different right shifts of #R, e.g. <SP>5</SP>/ 32 #R can be produced by summing #R shifted by 1 bit, i.e. ¢#R and #R shifted by 5 positions <SP>1</SP>/ 32 #R. #R is held in register 35 and multiplexers 37 and 37<SP>1</SP> have their inputs d and b<SP>1</SP> respectively connected to the their outputs. For this step the inputs to the multiplexers are hard wired to produce the required number of shifts such that at the output of the two multiplexers the #R N  signal has been multiplied by the required power of ¢. The sum of these two outputs is then fed from adder 42 via distributor 43 into the three least significant stages of measured range counter 23. Step 4.-The value K1#R N  just stored in measured range counter 23 now appears on input a of multiplexer