Patent GB-1100461-A (GB)
Title: Improvements in or relating to magnetic core matrix data storage devices
Inventor: SHERLOCK JAMES FRANCIS
IPC: G06F12/04
Filed: 1963-10-02
Abstract: 1,100,461. Electric digital data storage. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. 17 Sept., 1964 [2 Oct., 1963], No. 38767/63. Heading G4C. [Also in Division H3] In a magnetic core matrix store the means for effecting the operations involved in reading in and reading out information are actuated sequentially, the completion of one operation serving to initiate the next. In the example shown in Fig. 1 reading is effected by currents passing from left to right and bottom to top, a particular core being selected by choosing one of four secondary selectors RXS1-RXS4 and one of two primary selectors PXP1 or PXP2 in the X direction, a similar arrangement being used for the Y direction. For writing, the current flow is in the opposite direction. Two sense wires S1 and S2 are provided, each threading in series the cores in diagonally opposite quadrants. This reduces the possibility of spurious signals being produced in the sense wire due to the disturbance of partially selected cores. Two inhibit wires I are also provided, each threading in series the cores in half the plane. A store is described in which 4096 words of forty-eight bits are stored in fifty-two planes (leaving four planes spare) each consisting of a 64 x 64 array of cores. In this instance there are eight primary and eight secondary selectors for both the X and Y directions. Core selection.-The operation of the store is fully described with reference to Figs. 5-10 (not shown). The store is operated in parallel mode in conjunction with an asynchronous parallel computer. The store address selection signals from the computer are in the form of twelve bits comprising four groups of three bits each group defining one of the four selector required to locate a particular word. The address is carried on two sets of twelve leads the signals on one set being the inverse of the signal on the other. The address toggles are set by one of these signals and the other signal is used in a fault finding circuit to check that they are correctly set. Means are also provided to verify that only one primary and one secondary selector in each direction are selected. Reading and writing.-Any cores which were at " 0 " after the previous writing operation may have entered a minor hysteresis loop. To ensure that they return to the major loop a pre-operate disturb pulse is first applied to the inhibit wires. Thereafter one of three operations may take place, reading, reading and rewriting or reading and writing. When reading, all cores storing a " 1 " are driven into the " 0 " condition and thus produce an output on certain sense wires which affect corresponding read amplifiers. These in turn control a set of output toggles in the output register. A checking circuit then checks the output of each read amplifier against its associated toggle to ensure that the output register is correctly set up. A " read finish " toggle is then set by the output from a delay line to indicate the completion of the operation to the controlling computer. When rewriting, the output toggles cause the inhibit wire to be pulsed if the corresponding toggle is storing a " 0 " condition. A timing toggle defines the duration of this pulse and then produces a " write finish '' signal. When writing to the store, a read cycle must precede this operation to ensure that all cores of the selected word are in the " 0 " condition. Thereafter if a " 1 " is required the corresponding inhibit wire is not pulsed and the operation of the X and Y selectors causes the selected core to change its state. If a " 0 " is required the inhibit wire is pulsed thus preventing a change of state.