Patent GB-1332797-A (GB)
Title: Programme interrupt facilities in data processing systems
IPC: G06F9/48
Filed: 1971-08-24
Abstract: 1332797 Programme interrupt system PLESSEY CO Ltd 24 Aug 1971 [2 Sept 1970] 41951/70 Heading G4A In a system including at least one processor, a memory and at least, one peripheral unit, the memory stores a plurality of object programmes and a plurality of control programmes and includes a discrete common storage area containing a plurality of interrupt demand indicating bits which are marked when a corresponding interrrupt is required by a processor or peripheral unit. and the current programme in each processor is periodically inhibited for interrogating the common storage area, the processing of the inhibited programme in the interrogating processor being suspended upon detection of a marked interrupt demand bit and the processing of a particular one of the control programmes being started in place of the suspended programme. Each processor is similar to that disclosed in Specification 132,972 and includes an interrupt cycle generator ICG (the generators are asynchronous), a schedular timer register STR indicating the total processing time that an object programme should experience before entry into a schedular programme, and an interval timer register ITR indicating the length of time elapsed since a particular control operation was performed, e.g. impulse transmission in a telephone system. Each peripheral unit is arranged to set a particular interrupt demand bit in the system interrupt word SIW in the common storage area whenever an input or output transfer operation has been completed. When a system interrupt signal is produced by ICG or one of the timers produces an internal interrupt signal in a given processor, the following sequence of operations (see Fig. 7) is performed at the end of the current instruction step. S1. The base address of a local start up area DLSA appropriate to the processor is added to an offset to obtain the address of an interrupt mask word IMW for that processor, and after performing a memory protection check on this address the IMW is read from memory into a mask register MSK REG. S2. The SIW is transferred from memory to the processor operand register OP REG, the two most significant bits of this register being set by the states of the integral interrupt timer triggers STRZ, ITRZ. S3. IMW and SIW are AND merged and the result-is passed to a result register RES REG. S4. The RES REG is tested to see if it is zero (i.e., it contains no currently acceptable interrupt demands for that processor). S5. If RES REG is zero SIW is rewritten, unaltered into the common storage area and the next instruction of the current programme is selected. S6. If RES REG is not zero, a code indicating the position of the highest marked acceptable bit in SIW is sent to an interrupt accept word register IAR. S7 and S8. The selected bit is reset in OP REG and the relevant trigger STRZ, ITRZ. S9. The modified SIW is returned to the common storage area so that it may now be interrogated by another processor. S10. Parameters of the current programme are dumped in a process dump area. S11. and S12. An interrupt handler programme pointer is used to obtain access to the IHP. S13. Parameters of the IHP are copied into the processor. The IHP is then entered by referencing the interrupt accept word register IAR. The IHP can be made non-interruptable by performing a Q SWAP R instruction which causes all zero's to be written in the IMW, the original IMW being saved, and the IHP then ends with a further Q SWAP R instruction which returns the original IMW to the local start-up segment. The SIW and interrupt accept word may be longer than one computer word, in which case S6 is performed a word at a time and the result includes a word count as well as a bit count.