Patent GB-1228192-A (GB)
IPC: H04J3/06
Filed: 1968-07-05
Abstract: 1,228,192. Multiplex pulse code signalling. GENERAL ELECTRIC CO. Ltd. 7 July, 1969 [5 July, 1968], No. 32242/68. Heading H4L. A synchronizing arrangement for a timedivision - multiplex pulse - code - modulation receiver comprises first circuit means responsive to a first por tion of a synchronizing pulse pattern to reset the phase of operation of the receiver to a predetermined phase reference, and second circuit means responsive to a second portion of the synchronizing pulse pattern, when received in predetermined time relation with said first portion in a predetermined number of successive cycles of said synchronizing pulse pattern, to inhibit said first circuit means. General Description.-The system has eight pulse-elements per channel, with twenty-four channels per frame, and the synchronizing pulse pattern occupies the first pulse-elements of channels nine to twenty-four of the first frame of each four-frame cycle, and is coded 1101010101010101. In the receiver, incoming signals are taken to a clock pulse generator (10), Fig. 1 (not shown), which is locked to the bit rate thereof, and to a distributer (27). There are connected to the generator (10), in order, a gate (31) and cyclic counters (24), (25), (26). The counter (24) provides eight trains of digit pulses D1-D8, successively staggered by one digit to correspond with the eight digits of each channel, the counter (25) provides twentyfour staggered trains of channel pulses CH1- CH24, and the counter (26) provides four staggered trains of frame pulses F1-F4. The gate (31) may be inhibited by a pulse from terminal 28 of Fig. 2 to a second input, so that a clock pulse in the train being counted down is missed, and the phase is effectively slipped by one digit time slot. The counter (25) is re-set to its channel 10 (CH10) output and the counter (26) is re-set to its frame one (F1) output when a pulse is received from terminal 32 of Fig. 2. Two bi-stable circuits 3, 4, Fig. 2 are connected in cascade and are both triggered by the first digit pulse (D1) in each count of eight. Bi-stable circuit 3 has one state steered by the received signal and the other state steered by that signal after inversion. Outputs from the bi-stable circuits 3, 4 are taken to AND-gates 5, 6, which each have a further input of the second digit pulse (D2) in each count of eight. At each D2 pulse, and AND-gate 5 is enabled if the preceding two D1 signals indicated "11" and the AND- gate 6 is enabled if the preceding two D1 signals indicated "00". Outputs from the AND-gates 5, 6 are taken to an OR-gate 7, which is enabled if either of them is enabled, and which provides one input to an AND-gate 2. Said AND-gate 2, when enabled, provides the above-mentioned pulse at the terminal 32, for channel and frame re-set. Other bi-stable circuits 11, 12, 13 are also connected in cascade, and may either be "set" to an error state (referenced E) or "offset" to a no-error or correct state. Bi-stable circuit 11 is triggered to its off-set state when a pulse is received from channel 10 of frame 1 at a terminal 9, and an output pulse is received from the AND-gate 5. This indicates the coincidence of a channel ten pulse with the second of two signals ("11") in successive D1 positions. A self-triggering input to the set state of bistable circuit 11 is derived from the output of the OR-gate 7 via an inhibit gate 14, the inhibit input being supplied with the channel ten pulse. Bi-stable circuit 11 is thus triggered to its set state when either "11" or "00" occurs in successive D1 positions, and the second "1" or "0" does not occur in channel 10. Triggering inputs of the bi-stable circuits 12, 13 are derived from an AND-gate 15, with inputs of the channel twenty-three pulse (CH23) and the frame one pulse (F1). AND-gates 16, 17 are respectively enabled when the bi-stable circuits 11, 12, 13 are all in their set states, or in their off-set states. A bi-stable circuit 18 has the same triggering input as the bi-stable circuits 12, 13 (CH23 pulse in F1) and is steered to its set state by output from the AND-gate 16, and to its off-set state by output from the AND-gate 17. Output from the set or error state of the bi-stable circuit 18 provides a second input to the AND-gate 2 and also one input to an AND- gate 1, the output side of which is connected to the above-mentioned terminal 28. Said AND- gate 1 also has an input from a blocking oscillator 20, which provides a single digit-pulse occurring not more than once every four frames, and an inhibit input from an AND-gate 19. Said AND-gate 19 also inputs from the off-set output of the bi-stable circuit 11, and from a channel twenty-three (CH23) pulse which is stretched over approximately three cycles, or twelve frames. Operation.-Assuming that initially the receiver is not in synchronism with the transmitter, the bi-stable circuit 18 will either be set in its error state or will attain it shortly after switching on. The AND-gate 2 will be enabled at every pulse from the OR-gate 7 resulting from the reception of a "11" or "00" pattern in successive D1 positions, and the receiver will be re-set to channel ten of frame one. In general, the time between re-settings is insufficient for channel twenty-three to be reached. Consequently, the gate 3 is not inhibited by an output from the gate 19, and approximately once in every four frames of the received signal the AND-gate 1 will be enabled, so that the receiver phase is slipped by one digit interval. Eventually, a true synchronism condition is achieved, and the bi-stable circuit 11 is set. The repeated "01" sequence which follows the "11" part of the synchronizing pattern will prevent any further re-setting of the receiver, so that a channel twenty-three pulse will arise, and inhibit the digit re-set, by way of the gates 19 and 1, at the same time off-setting the bi-stable circuit 12 to the noerror state. The receiver is brought into immediate synchronism by the single marker pattern ("11") which must appear in the bistable circuits 3, 4 at the next synchronizing pattern. The second channel twenty-three pulse to arise will transfer the no-error indication to the bi-stable circuit 13, and at the following marker pattern, the bi-stable circuit 11 will again be off-set (if not previously so) and the AND-gate 17, providing an indication of three successive marker patterns, is enabled. At the third channel twenty-three pulse, therefore, the final bi-stable circuit 18 is off-set to its no-error state, and the digit and channel re-set AND- gates 1, 2 are disabled. If there is a phase slip from synchronism, a "11" marker pattern will fail to coincide with the channel ten pulse, and the bi-stable circuit 11 will be set to its error state. Continuation of the phase slip will cause the error state to be stepped along to the bistable circuits 12, 13, whereupon the bi-stable circuit 18 will be set to its error state. The digit and channel re-set gates 1 and 2 are thereby enabled, to reset the phase as above described.