baber/WOPTO huggingface dataset:
Patent TW-I266274-B (TW)
Title: Driving circuit of liquid crystal display panel and method thereof
Inventor: SHIH PO-SHENG
IPC: G09G3/36
Filed: 2003-02-24
Granted: 2006-11-11
Abstract: The present invention discloses a driving circuit of liquid crystal display (LCD) panel and a method thereof. The storage capacitors of pixels on each scan line are connected to an alternating current signal source. In accordance with the pixel polarity inversion time, the signal source generates suitable signals. By means of capacity coupling effects, the signals can generate a coupled voltage to change the potential of the pixel electrode and increase the field transformation speed of the liquid crystal capacitors for the LCD to display high-speed continuous motions.
Patent TW-I230687-B (TW)
Title: A method for growing arrays of carbon nanotubes
Inventor: LIU LIANG
IPC: C01B31/02
Filed: 2003-03-28
Granted: 2005-04-11
Abstract: The present invention pertains to a method for growing arrays of carbon nanotubes on a surface of a metal substrate. The method includes selecting a metal substrate having a smooth surface, oxidizing the metal substrate so as to form an oxide layer on the smooth surface of the metal substrate, depositing a catalyst layer on the oxide layer, and exposing the catalyst layer to a carbon source gas, thereby forming the arrays of carbon nanotubes extending from the metal substrate, following the formation of carbon nanotubes a by-product, such as hydrogen gas is produced and reduces the oxide layer.
Patent TW-588462-B (TW)
Title: Method of fabricating a thin film transistor array panel
Inventor: YANG KO-CHIN
IPC: H01L21/77
Filed: 2003-03-31
Granted: 2004-05-21
Abstract: A method of fabricating a thin film transistor array panel is described. A gate and a scan line electrically connected with the gate are formed on a substrate, and a gate insulating layer is formed on the substrate. A channel is formed on the gate insulating layer above the gate. A transparent conductive layer and a metal layer are formed over the substrate. Then, patterning the metal layer and the transparent conductive layer to define a source/drain, a data line and a pixel region. A passivation layer is formed over the substrate exposing the metal layer in the pixel region. The metal layer is removed by using the passivation layer as a mask for forming a pixel electrode. Since the present invention only needs four masks, the process cost can be decreased.
Patent TW-I220316-B (TW)
Title: Flash memory cell, flash memory cell array and manufacturing method thereof
Inventor: HSU CHENG-YUAN
IPC: H01L29/423
Filed: 2003-05-22
Granted: 2004-08-11
Abstract: A flash memory cell array is consisted of a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structure is formed on the substrate which including a stack gate structure is consisted of a select gate dielectric layer, a select gate and a cap layer; a spacer is set on the sidewalls of the stack gate structure; a control gate connected to the stack gate structure is set on the one side of the stack gate structure; a floating gate is set between the control gate and the substrate; a inter-gate dielectric layer is set between control gate and floating gate; and a tunneling dielectric layer is set between floating gate and the substrate. The source region/drain region is set in the substrate near outer control gate and stack gate structure of the flash memory cell array.
Patent TW-I281933-B (TW)
Title: Polyolefin compositions and production method thereof, and injection moulded articles thereof
Inventor: PELLICONI ANTEO
IPC: C08L23/10
Filed: 2003-06-18
Granted: 2007-06-01
Abstract: Polyolefin compositions comprising (percent by weight): (1) 55-90% of a crystalline propylene homopolymer or copolymer containing up to 15% of ethylene and/or C4-C10 alpha-olefin(s) and having values of MFR equal to or higher than 25 g/10 min; (2) 10-45% of a copolymer of ethylene with one or more C4-C10 alpha-olefin(s) containing from 10 to 40% of said C4-C10 alpha-olefin(s); said compositions having values of MFR equal to or higher than 20 g/10 min, a total content of ethylene of 20% or more, a total content of C4-C10 alpha-olefin(s) of 4.5% or more, a ratio of the total content of ethylene to the total content of C4-C10 alpha-olefin(s) of 2.3 or more, a total fraction soluble in xylene at room temperature of less than 18 wt% and an intrinsic viscosity value of the fraction soluble in xylene at room temperature of 1.7 dl/g or less.
Patent TW-595123-B (TW)
Title: Data synchronization method, method defining data synchronization format and storage media
Inventor: LUO KUO-HSUAN
IPC: H03M7/30
Filed: 2003-08-22
Granted: 2004-06-21
Abstract: There is provided a data synchronization method that is applicable to music broadcasting program for broadcasting music data and displaying lyrics synchronously, in which music data is in form of MP3 and the MP3 format contains ID3 format field. The method comprises the steps of: firstly reading music data and the ID3 format field of the music data including at least a text data and time mark data of corresponding time in music data for representing text data; then, generating index mark table according to the text data and corresponding time mark data, wherein the index mark table is used to represent the display time of text data while playing music data; and finally using the music broadcasting program to broadcast music data and synchronously display text data on a display device in accordance with the index mark table.
Patent TW-I225933-B (TW)
Title: Universal test platform and test method for latch-up
Inventor: WANG JIE-HONG
IPC: G01R31/28
Filed: 2003-09-01
Granted: 2005-01-01
Abstract: A test platform and a test method for testing latch-up phenomena of an IC chip. The test platform includes a memory, a parameter measurement unit (PMU), a latch-up testing program, and a processor. The memory stores a testing program of the IC chip for testing the functions of the IC chip. The test method includes (a) using the processor executing the latch-up testing program to get the testing program of the IC chip; (b) getting data of pins of the IC chip from the testing program of the IC chip; (c) setting an initial value for input pins of the IC chip; (d) using the PMU providing a test current to a pin of the IC chip then measuring if the current between the voltage source and ground larger than a first value.
Patent TW-I223103-B (TW)
Title: Wire grid polarizer with double metal layers
Inventor: CHIU CHIH-HO
IPC: G02B5/30
Filed: 2003-10-23
Granted: 2004-11-01
Abstract: A wire grid polarizer with double metal layers for the visible spectrum. Parallel dielectric layers having a period (p) of 10 to 250 nm and a trench between adjacent dielectric layers are formed on a transparent substrate. A first metal layer having a first thickness (d1) of 30 to 150 nm is formed in the trench. A second metal layer having a second thickness (d2) of 30 to 150 nm and a width (w) is formed on the dielectric layers. A vertical distance (1) between the first and second metal layers is 10 to 100 nm. The first thickness (d1) is the same as the second thickness (d2). A ratio of the width (w) to the period (p) is 25-75%.
Patent TW-I230274-B (TW)
Title: Color filter substrate, method for fabricating the color filter substrate, and display device
Inventor: OHSAKI MORIHIDE
IPC: G02F1/1343
Filed: 2003-12-25
Granted: 2005-04-01
Abstract: A color filter substrate includes a transparent substrate with first and second opposed edges, a color filter layer including color filters of first, second and third types extending in a first direction with the third type interposed between the first and second types, and an opaque layer including opaque portions extending in the first direction and another opaque portion connected to the other opaque portions along the second edge. The color filter substrate is fabricated by (a) forming the opaque layer on the transparent substrate, and then (b) forming the color filter layer thereon. The step (a) includes forming an opening between one end of each color filter of the third type and the second edge. The step (b) includes attaching and rolling a dry film in the first direction on the transparent substrate after the color filters of the first and second types have been provided thereon.
Patent TW-I241548-B (TW)
Title: Sequential multi-segment pulse width modulated display system
Inventor: WILLIS DONALD HENRY
IPC: G09G3/36
Filed: 2004-01-16
Granted: 2005-10-11
Abstract: A field sequential pulse width modulated display system (10) comprises a digital micromirror device (DMD) (24) having a plurality of micromirrors that each selectively pivot to reflect light onto a screen (28) to illuminate a corresponding pixel. A driver circuit (30) controls the DMD (24) responsive to sequences of pulse width segments formed by a processor (31). The processor (31) actuates at least one pulse in a first pulse width segment for a given color to increase pixel brightness with a range lying between first and second pixel brightness values. To further increase pixel brightness, the processor actuates at least one pulse within additional pulse width segments associated with the same given color to increase pixel brightness above the second brightness boundary. The pulses within the additional segments are actuated unequally so that the additional pulse width segments closest in time to the first segment (i.e., the segment first in brightness) have a greater total duration of actuated pulses for a given pixel brightness compared to the additional pulse width segments farther in time from the first segment. Actuating the pulses in this manner serves to: (a) limit the time dispersal of darker objects within a picture, (b) minimize the light redistribution between time segments for incremental brightness changes, and (c) taper up and down light intensity for the sequence of pulse width segments for a given picture, all to minimize motion artifacts.
Patent TW-I276402-B (TW)
Title: Method of soil amendment with biofumigant (PBGG) in reducing incidence of damping-off diseases and application the same
Inventor: HUANG JENN-WEN
IPC: A01N63/04
Filed: 2004-03-10
Granted: 2007-03-21
Abstract: The present invention is related to a biofumigant (PBGG) which was developed using the granular formulation consisted of Pseudomonas boreopolis, Brassica seed pomace, glycerin and sodium alginate. The PBGG biofumigant is an effective soil fumigant. When applied to the soil or other growth substrates, the PBGG biofumigant in the present invention was effective in reducing incidence of damping-off diseases of vegetable crops and increasing growth and activities of antagonistic microorganisms such as actinomycetes in the soil. Meanwhile, soil amendment with PBGG had no harmful effects on seed germination and seedling growth of vegetable crops. Therefore, PBGG is an effective and environmentally sound fumigant for control of crop diseases caused by soilborne fungal pathogens. The present invention related to a method for producing a biofumigant. The present invention related to a method for selecting a microorganism which secretes myrosinase. The present invention also related to the bacterium, Pseudomonas boreopolis.
Patent TW-I256628-B (TW)
Title: Optical disk for mobile device
Inventor: RO MYONG-DO
IPC: G11B7/24
Filed: 2004-03-11
Granted: 2006-06-11
Abstract: An optical disk for a mobile device is provided. The optical disk includes a substrate, having an outer diameter less than 120 mm and not smaller than 30 mm and a thickness less than 1.1 mm and not smaller than 0.40 mm, so that a deflection angle of 0.7 DEG or smaller can be obtained. Alternatively, the optical disk includes a substrate, having an outer diameter not smaller than 30 mm and a thickness not smaller than 0.435 mm, so that a deflection angle of 0.6 DEG or smaller is obtained.
Patent TW-I231863-B (TW)
Title: Detection circuit and method for detecting the saturation status of inductors
Inventor: CHEN YAU-MING
IPC: G01R27/00
Filed: 2004-03-19
Granted: 2005-05-01
Abstract: A detection circuit and method for detecting the saturation status of inductors is provided. As an inductor is an important power storage unit in switching type power converters, it should avoid to operate the inductor in a saturated status during the actual operation. The detection circuit of this invention determines whether the inductor reaches the status of saturation by detecting variance in the slope of current. This invention applies a second order differential operation to the current of the inductor for determining a current slope variance signal, and then uses the gate control signal of a power switch unit in the switching type power converter to eliminate any possible erroneous message which occurs when the power switch unit is turned on or off and fast variance in the slope of current is encountered, thereby correctly determining whether the inductor reaches the saturated state or not.
Patent TW-I232845-B (TW)
Title: Rotary electrostatic micro actuator
Inventor: YEH JER-LIANG ANDREW
IPC: B81B5/00
Filed: 2004-05-26
Granted: 2005-05-21
Abstract: The invention provides a rotary electrostatic micro actuator that comprises a substrate, plural stationary electrodes, plural movable electrodes and plural flexible support beams. The substrate comprises a first surface. The stationary electrodes are fixed onto the first surface of the substrate, and each stationary electrode has at least a first comb finger. The movable electrodes are fixed onto the first surface of the substrate in a movable way, and each movable electrode has at least a second comb finger. The first comb finger and the second comb finger are interdigitated corresponding. The flexible support beams comprise a rotation center. Each flexible support beam comprises a first end that is fixed to the first surface of the substrate and a second end that is connected to the rotation center.
Patent TW-I264267-B (TW)
Title: Dissipation module with noise reduction function
Inventor: KAO PING-SHENG
IPC: H01L23/467
Filed: 2004-05-31
Granted: 2006-10-11
Abstract: A dissipation device includes a dissipation fin set and a centrifugal fan. The centrifugal fan outputs airflow toward the dissipation fin set to remove the heat from it. The centrifugal fan includes a centrifugal impeller mounted on a motor. An outer housing houses the motor and the centrifugal impeller therein. An inner wall of the housing's outlet has feathered structure to reduce noises. The dissipation fin set includes a fin structure adjacent to a heat source, as well as an airflow channel housing. The airflow channel includes featured structures for reducing noises.
Patent TW-I261411-B (TW)
Title: Amplitude regulation circuit and method, motor driving control apparatus and method, and semiconductor integrated circuit device
Inventor: KINUGAWA HIROKI
IPC: H02P6/06
Filed: 2004-06-18
Granted: 2006-09-01
Abstract: In an amplitude regulation circuit, a maximum detection circuit outputs maximum signal MAR that is distorted to some extent during and around a time when a highest-level signal switches between signals V1, V2, and V3. Meanwhile, a minimum detection circuit outputs minimum signal MIN that is distorted to some extent during and around a time when a lowest-level signal switches between signals V1, V2, and V3. Such distortions serve to reduce variations in amplitude detection signal AMP that represents a difference between MAX and MIN. The amplitude regulation circuit amplifies rotor position signals H1 to H3 based on amplitude detection signal AMP according to AGC, thereby keeping amplitudes of signals V1 to V3 constant while maintaining sinusoidal waveforms. A motor driving control apparatus drives a motor based on signals V1 to V3. Since this circuitry does not include a smoothing capacitor, high AGC responsiveness is achieved.
Patent TW-I311971-B (TW)
Title: Fitments,carton,container and method of manufacturing fitment
Inventor: VON SPRECKELSEN HENNING
IPC: B65D5/74
Filed: 2004-06-30
Granted: 2009-07-11
Abstract: A carton fitment ( 2 ) has a base flange ( 4 ) and a pour spout ( 6 ) closed by a screw on overcap ( 8 ). The base flange ( 4 ) has a barrier foil ( 30 ) coated on both sides with a plastic layer embedded in a sacrificial receiving wall ( 32 ) surrounding the periphery of the base flange ( 4 ).
Patent TW-I285764-B (TW)
Title: Liquid crystal display device and manufacturing method thereof
Inventor: SAWASAKI MANABU
IPC: G02F1/1339
Filed: 2004-06-30
Granted: 2007-08-21
Abstract: The present invention relates to a liquid crystal display device that is used in display portions of electronics devices and a manufacturing method thereof, and intends to provide a liquid crystal display device that can obtain excellent display quality and a manufacturing method thereof. The method of manufacturing a liquid crystal display device includes preparing a pair of substrates that have a structure P1 having a height Hpl and a structure P2 having a height Hp2, the heights Hp1 and Hp2 satisfying a relationship of 0.3 (mum) <= Hp1-Hp2 <= 1.0 (mum); controlling a dropping amount V of liquid crystal so that a cell gap G1 that is determined by the dropping amount V of liquid crystal, the height Hp1 and the height Hp2 satisfy a relationship of Hp2 < G1 < Hp1; dropping the controlled dropping amount V of liquid crystal on one of the pair of substrates; and attaching the pair of substrates in a vacuum followed by returning to an atmospheric pressure to fill in the liquid crystal between the pair of substrates.
Patent TW-I240177-B (TW)
Title: Intelligent yarn grading method and device
Inventor: LIEN HSIN-CHUNG
IPC: G06F15/18
Filed: 2004-07-21
Granted: 2005-09-21
Abstract: The present invention provides an intelligent yarn grading method and device, wherein the intelligent yarn grading device comprises a personal computer with the learning template database and intelligent yarn grading method. The intelligent yarn grading method employs the yarn n-order attribute vector as the n input vectors of neural network, and the s yarn grades are corresponding to the s output nodes of the neural network respectively; then, inputting the yarn attribute vectors into the neural network and automatically recognizing the yarn grade; wherein, in the learning and dimension reduction process, using K-L expansion method to convert the yarn attribute vector onto the orthogonal axis to obtain the minimum axis vector number required for maintaining the yarn recognition precision, so as to simplify the complexity of recognition; and, the neural network uses the training samples to adjust the weight of each node to be optimized, and enhance the recognition precision of neural network; and, in the inspection process, fixing the weight for each node of the neural network having completed of learning; and, conducting the axis conversion and dimension reduction on the attribute vector of the inspection sample, and inputting into the neural network for yarn grading evaluation, and if there is a fault determination sample in the evaluation process, it will store the fault determination sample data in the learning sample database for obtaining the re-learning data; the re-learning process adds the fault determination samples into the learning sample database to make the K-L expansion re-adjusting the axis direction and the neural network adjusting the weight of each node, so as to prevent the fault determination for the samples similar or identical to the fault determination samples. Thus, the present invention can improve the recognition precision of the intelligent yarn grading method and device.
Patent TW-I239897-B (TW)
Title: Method for optimizing ink jet from nozzles of a print-head of a printer
Inventor: LEE CHENG-LUNG
IPC: B41J29/393
Filed: 2004-08-05
Granted: 2005-09-21
Abstract: A method for optimizing ink jet from nozzles of a print-head of a printer. Before printing a swath, the nozzles of the print-head jet a predetermined number of ink drops towards an absorption substance at the maintenance station of the printer. This number is corresponding to a swath density of the swath to be printed so as to preheat a chip of the print-head to an optimal temperature before printing.
Patent TW-I359170-B (TW)
Title: Polymer mixture and its use for injection-moulded
Inventor: WICKER MICHAEL
IPC: C08L51/00
Filed: 2004-08-16
Granted: 2012-03-01
Abstract: Polymer blends with a specified combination of tensile modulus, Vicat softening point, impact strength and melt flow index, containing (a) low-mol. wt. (meth)acrylate copolymer, (b) impact modifier based on crosslinked poly(meth)acrylate, (c) high-mol. wt. (meth)acrylate (co)polymer and/or (d) a (meth)acrylate (co)polymer other than (a). Polymer mixtures (I) containing (a) a low-mol. wt. (meth)acrylate (co)polymer with a solution viscosity (SV; in chloroform at 25[deg]C; ISO 1628, Part 6) of not more than 55 ml/g, (b) an impact modifier based on crosslinked poly(meth)acrylate, (c) a high-mol. wt. (meth)acrylate (co)polymer with an SV of 65 ml/g or more and/or (d) a (meth)acrylate (co)polymer other than (a) with an SV of 50-55 ml/g, optionally with conventional additives and/or fillers etc. Test pieces made from (I) show a tensile modulus ( ISO 527) of at least 2600 MPa, a Vicat softening point ( ISO 306-B50) of at least 109[deg]C, an impact strength ( ISO 179-2D; flatwise) of at least 17 kJ/m 2> and a melt flow (volume) index ( ISO 1133; 230[deg]C/3.8 kg) of at least 1.5 cm 3>/10 min. An independent claim is also included for injection mouldings made from (I).
Patent TW-I241027-B (TW)
Title: Method of preparing electronic device
Inventor: HU TARNG-SHIANG
IPC: H01L29/786
Filed: 2004-09-30
Granted: 2005-10-01
Abstract: A method of preparing electronic device is disclosed, which includes the following steps: (a) provide one substrate; (b) form one first strip on the substrate; (c) coat one insulating layer material onto the first strip and the substrate to cover completely the first strip and the substrate; (d) form one second strip onto the insulating layer material; (e) form one conductive polymer material on to the insulation layer material and completely cover the second strip; (f) uses plasma etching to etch the conductive polymer material to completely remove the conductive polymer material on the second strip; and (g) form one semiconductor layer material onto the second strip and the conductive polymer material.
Patent TW-I252285-B (TW)
Title: Boot for universal shaft coupling
Inventor: NAKAMURA SABURO
IPC: F16J3/04
Filed: 2004-10-05
Granted: 2006-04-01
Abstract: The invention relates to a boot for a universal shaft coupling, by which an improvement of an assembling workability can be expected, and an improvement of a sealing performance can be expected. The boot for the universal shaft coupling is formed by a rubber elastic body, and separated portions (22) are formed linearly along a generatrix. A fastener pair (26) is arranged in both sides of the separated portions (22) so as to form a seal portion. The fastener pair (26) is constituted by an occluding portion (32) formed in end edge of the separated portion (22) and provided with a bulge locking portion (32a) in a leading end, and an occluded portion (34) formed in another end edge of the separated portion (22) and provided with an occluding groove (33) occluding with the bulge locking portion (32a). A guide fin (36) is provided in an inner side of the occluding groove (33) on a separated portion end surface (22b) in a side forming the occluded portion of the separated portion (22), in a side of a crest portion (28) of a bellows portion (24). The guide fin (36) is provided a guide surface (40) at a position partly overlapping the occluding portion (32) at a time of facing to the occluding portion (32).