Patent GB-1486105-A (GB)
Title: Multiplexer
IPC: H04J3/17
Filed: 1975-02-17
Abstract: 1486105 Multiplex systems INTERNATIONAL BUSINESS MACHINES CORP 17 Feb 1975 [17 May 1974] 6558/75 Heading H4M A multiplexer for handling circuit switched (synchronous) traffic and store and forward (asynchronous) traffic comprises a set of registers 12-16 each associated with one of a first set of sources of circuit switched traffic and a buffer store for storing data from a second set of sources of store and forward traffic, with a transferring arrangement (OR gate 34 and adapter 36) for transferring data alternately from the registers and the buffer store to a common transmission line 38. A first selector (counter 51, input/output register 10, decoder 70 and gates 72-90) selectively activates outputs of the registers to release data to the transferring arrangement during discrete assigned time slots of repetitive frames in accordance with control data in a control store 10 and a second selecting arrangement (counter 62, comparator 68, gate 78) activates the buffer store to release data to the transferring arrangement only during discrete time gaps between the assigned time slots. The selectors operate such that a non zero minimum capacity is provided for store and forward traffic in each frame. A minimum part M (Fig. 3) of a frame is reserved for asynchronous traffic, while in the rest of the frame M priority is given to synehronous traffic; but any space unused by synchronous traffic may be occupied by asynchronous. The store and forward switched data is fed to the buffer store 18 via an editing unit 20 which arranges the data packets in sequence and adds identification and control information. Data is fed to the transmission path 38 via an assembler comprising OR gate 34 and adapter 36. The outputs of the registers 12-16 are selectively actuated in accordance with control data in a control store 10 to feed synchronous data to the multiplex channel and if no data is released from the registers (indicated by an output 58 from the store) the buffer store 18 is selectively activated to release asynchronous data to the multiplex channel. The store is associative and holds information on time slot assignments for synchronous data, each row of the store recording the first bit position of a time slot in the frame, the time slot width and the number of the data channel to which the time slot is assigned. In response to a bit clock 40, a counter 50 is incremented. The count is fed to gate 51 and thence to the store. Each count that corresponds with a bit position recorded in the first column of the associative store results in an output from the store indicator I which sets the flip-flop 54 and enables the counter 62 and comparator 68. When the counter 62, incremented by the bit clock 40, reaches the valve of time slot width stored in the second column of the associative store 10, a signal which resets the flip-flop 54 is delivered, providing a signal on line 48 to actuate the buffer 18 to release asynchronous data to the multiplex line. The flip-flop 54 remains reset in the intervals between synchronous time slots. During the set periods, in the synchronous time slots, the channel numbers for the slots are read out to decoder 70 which provides signals to read out the appropriate registers 12-16 to the gate 34 and hence the line 38. The frame sync pattern is held in a register 84 and this is read out to the line at an appropriate time determined by the store 10 from information in its first two rows 000 and 001. The system further incorporates a main store which contains lists defining the time slots (defined by starting bit position and width) available to both synchronous and asynchronous data, and also holds information defining the minimum number of bits which must be available for asynchronous data. When requests are received by the system for further allocation of time slots for synchronous data, the store determines whether any bits beyond the minimum needed for asynchronous data are available. If so, a search is conducted to find the slots whose width most nearly matches the new data. Information is then sent to the associative store at the multiplexer so that this records the position and width of the new time slot. This information must also be sent to the demultiplexer at the receiver in the system, which contains a similar associative store. This operation takes time, which could result in data assigned to a new synchronous time slot at the transmitter being interpreted as asynchronous at the receiver and thus transferred to the wrong output. To prevent this, newly entered words in the associative store are marked by "10" in "transition mask" locations, and this mask prevents the words being accessed until a signal is returned from the demultiplexer indicating that it has recorded the information. Then the mask changes to 11 to indicate an active row (free or passive rows are marked 00).