Patent GB-1127711-A (GB)
Title: Improvements in communication system
IPC: H04J3/24
Filed: 1967-01-06
Abstract: 1,127,711. Telegraphy; transistor pulse duration detectors. ULTRASONIC SYSTEMS CORP. 6 Jan., 1967 [11 Feb., 1966], No. 876/67. Headings H3T and H4P. In a telegraph system comprising a number of stations arranged in a loop so that each station receives all the data in a data cycle on the line, the data cycle comprises a synchronizing pattern followed by time slots each of which may be filled by a multi-element signal for a corresponding receiver, each receiver responding only to data in a certain time slot. Transmission.-When a station (e.g., A) wishes to transmit to another station (e.g., B) the corresponding time slot B is examined. If it contains a " Busy " bit a warning is generated and A sends no signal. If slot B is not busy the transmitter inserts a Busy bit. The next bit position is left blank for an Acknowledge signal and is followed by the first character of the message and a parity bit. When the signal has been received the receiver at B adds an Acknowledge bit, the data in slot B being otherwise unchanged. When slot B returns to station A the Acknowledge bit is cancelled, the parity checked, and the next character transmitted. After the last message character has been transmitted an all space character is transmitted and this will circulate in the loop, the Acknowledge bit being inserted by receiver B and cancelled by transmitter A at each cycle. When the transmitter is turned off, receiver B receives an Acknowledge bit, whereupon the receiver cancels the Busy bit. The signal in slot B now indicates, by the absence of the Busy bit, that receiver B is ready to receive a further message. Reception.-Station B examines time slot B. If slot B contains a Busy bit and no Acknowledge bit the character received is passed to the output teleprinter, and an Acknowledge bit added to slot B. Warnings are developed in the case of parity error and if a received character overlaps a character previously received but not yet passed to the output. General.-The loop contains a control unit which generates the sync. pattern when the system is first started. It also checks that the pattern recurs regularly. If the pattern is absent for more than a certain time the control unit clears the loop of all signals and restarts the system by generating a new sync. pattern. The unit may also comprise a delay to ensure that the loop delay is correct. Each time slot may be common to several receivers and each transmitter may insert characters in several time slots for broadcast transmission. More than one data cycle may be present in the loop if the loop delay is sufficiently great. Duplex transmission can be used. The timing of all operations at the receivers and transmitters is controlled by clock generators synchronized by the sync. pattern. A transistor circuit, Fig. 12c, provides an output when the duration of a negative signal at In exceeds a certain period. When In is negative capacitor 45 charges slowly and eventually cuts off transistors 46, 46<SP>1</SP> so turning 47 off and 49 on so that the output Out goes approximately to earth. If the input reverts to earth before 46, 46<SP>1</SP> are cut off the capacitor is discharged and Out remains negative.