Patent GB-1447728-A (GB)
Title: Error detection and correction apparatus for use in magnetic tape system
IPC: G06F11/10
Filed: 1974-03-14
Abstract: 1447728 Storage system HONEYWELL INFORMATION SYSTEMS Inc 14 March 1974 [9 May 1973] 11483/74 Heading G4C In a storage system using a multi-channel storage track, data is read from the track to a de-skewing buffer (20, Fig. 1, not shown) having a plurality of stages, each having two bistable storage devices (one for a "1" bit and one for a "zero" bit) which are re-set to their zero states when the data is transferred to the next stage, an over-skew condition being detected by determining when the bi-stables of the first stage are in differing states at a predetermined time in a bit cycle (that is when they are still storing information owing to the fact that all following stages are full). Incoming data pulses with, for channel 1, "1" bits on line RSP 1110 (Fig. 1b) and "0" bits on line RSP 0110 are applied from sense amplifier (10, Fig. 1, not shown) to a first stage 22 of the de-skew buffer, pseudo clock circuits (14, Fig. 1, not shown) providing pulse signals RS 25 110, RS 75 110 which are used to derive a signal RSAR 130 from amplifier 21-12 representing the start of a bit interval during which the sensed data may be read in. When a pair of storage bi-stables, e.g. 24-2, 24-12 in stage 24 have been reset output RSMB 130 of inverter 28-2 becomes zero to (1) in all the AND gates 24-4, 24-14 to transmit the states of the preceding stage 22 to the stage 24 and to reset the bi-stables 22-2 22-12. When a dropped bit is indicated in a channel, for example for channel 1 by both bi-stables 26-2 26-12 being in their "1" state, the output of amplifier 28-30 becomes "1" and if channel 2 has also dropped a bit the output of amplifier 29-10 (Fig. 1c) is also "1" so that the output RSDB 230 of inverter 28-32 is zero. If neither channel has dropped a bit the output RSSDB4A of amplifier 28-36 is "1", these signals being fed to detection circuits to correct for a dropped bit in channel 1. For each channel, e.g. for channel 1 there is a circuit 41 (Fig. lc) providing an output signal RSOS 150 at its "1" level when either of the two bi-stables in the first stage 22 of the associated channel store a "1", this signal passing gate 41-18 set to bi-stable 41-12 when the bi-stables have not been cleared at the start of the next bit interval to provide a binary "1" output RSCF 110 indicating an over-skew. Since this indicates that there is insufficient storage for the next bit this bit is derived using dropped bit correction circuitry. Bi-stables 41-10, 41-11, 41-12 also operate as a counter to count consecutive drop bits, bi-stable 41-10 being set when an output byte is assembled in register 26 and both bi-stables 26-2, 26-12 are in their "1" state indicating a first dropped bit. If the next two bits are successively dropped, bi-stables 41-11, 41-12 are successively set so that the circuit provides an output signal after three successive bits have been dropped. The output signal from the overskew detector is used to set both the bi-stables of the second stage 24 to their "1" state. They remain in this state causing the channel to be "dead tracked" i.e. the correction circuitry of Fig. 1d provides the correct data bits for this track. A parity generator 32-2 (Fig. 1d) receiving the signal from one bi-stable in each channel section of stage 26 delivers a "0" when a "1" bit has been dropped and a "1" signal when a "0" bit has been dropped, this information being used to correct a data byte as it is transferred from register 26 to an output register (30, Fig. 1, not shown). When there is more than one dropped bit error, error detector circuit 32 sets a bi-stable 32-27 to its "1" state.