Patent SG-11201907532V-A (SG)
Title: Active boundary quilt architecture memory
Inventor: LAURENT CHRISTOPHE VINCENT ANTOINE
IPC: G11C11/22
Filed: 2017-08-30
Abstract: WO 18/ 15 175 6 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 23 August 2018 (23.08.2018) WIP0 I PCT O V SID o OH H How iflo VII IE (10) International Publication Number WO 2018/151756 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) (21) International Application Number: PCT/US2017/049441 (22) International Filing Date: 30 August 2017 (30.08.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/434,401 16 February 2017 (16.02.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: LAURENT, Christophe Vincent Antoine; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (54) Title: ACTIVE BOUNDARY QUILT ARCHITECTURE MEMORY (57) : Methods, systems, and apparatus that increase avail- 415_a able memory or storage using active boundary areas in quilt architec- ture are described. A memory array may include memory cells overly- ing each portion of a substrate layer that includes certain types of sup- port circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a differ- ent configuration from other portions of the memory array, may be po- sitioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighbor- ing memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in num- ber of available data in conjunction with the active boundary portions. El Core portion Boundary portion Control circuit portion FIG. 9 900