Patent GB-938003-A (GB)
Title: Improvements in or relating to arrangements for handling binary numbers
Inventor: ALLUM ROBIN DEVENISH
IPC: H04Q3/00
Filed: 1960-06-01
Abstract: 938,003. Automatic exchange apparatus. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd., and STANDARD TELEPHONES & CABLES Ltd. June 1, 1960, No. 19369/60. Class 40 (4). [Also in Group XIX] A magnetic drum registers permanent information relative to p.b.x. and junction line groups the information being distributed at random over tracks of the drum and characterized by a group number and a priority number, and the information being read-out by an arrangement which determines the highest priority number amongst idle lines of the wanted group. Lines of a group are referred to as multiple appearance lines. Drum storage.-The drum tracks are divided into 100 words of 28 bits each. The bits of each word are marked by timing pulses TA1 to TA28. To ensure accuracy strobe pulses are used as trigger pulses while the timing pulses act as priming pulses. The tracks are divided into groups of tracks each group having eight sub-groups and two operate tracks. Each subgroup has a main library track, Fig. 4, each word holdinga directory number in bits TA1 to TA16 and a " multiple appearance " mark in TA18 to indicate whether the line belongs to a group or not. Two of the sub-groups have auxiliary tracks which cater for p.b.x. and junction line data, bits TA1 to TA16 holding the line group number and bits TA19 to TA24 holding the sequence number indicating the priority of the line in the line group. The operate tracks mark the lines of the drum group idle or busy and, since they are outnumbered one to four, are divided into quarter words. As the provision of quarters puts the operate tracks out of rack with their associated library tracks the operate tracks are read one word in advance. As shown in Figs. 5 and 6 the tracks from all groups are read simultaneously so that choice of the highest order sequence number must be made first from the simultaneously read words in rack across the groups and this choice must then be compared with the further choices as the words of each group are read serially. General arrangement of read-out circuits. In Fig. 5 is shown the read-out equipment necessary for sub-groups in drum groups 1 to N, only the terminal sub-groups being illustrated. Fig. 6 shows common equipment in which a Wanted Number Store registers the number of the wanted line group. The operate tracks are read one word in advance and idle markings are preserved in a Memory Circuit for use during the next word when they enable a Line Discriminator. The group number is then read and compared with the contents of the Wanted Number Store by way of the Line Discriminator which is disabled if the numbers are not the same. Should the group number read be the wanted one, a Sequence Number Bit Gating Circuit is enabled to receive the sequence number from the auxiliary track starting with the highest order digit first. Since it is necessary to compare each bit received with the preceding bit a one-bit Delay Circuit is employed. Before the sequence number is read the main library track produces a mark from a bit TA18 which, over a Multiple Appearance Line Detector enabled from the Line Discriminator, signals a Multiple Appearance Line Staticizer which merely records that at least one member of the line group is available. All the Sequence Number Bit Gating Circuits act in concert with a Preceding Bit Memory to enable the highest value sequence number encountered in the simultaneous inspection of sub-group words to be stored in a Sequence Number Staticizer. In the subsequent inspection serially of further sub-group words in rack across the drum the Sequence Number Staticizer co-operates with the Preceding Bit Memory to permit storage of a higher valued number only. A Sequence Bit Gating Circuit will give passage to a binary 1 if it is the first bit read, or if it has not been preceded by binary 0, or, if a 1 has been preceded by 0, it will be given passage only if no other number being read or registered in the Sequence Number Staticizer has been preceded by fewer binary 0's. Detailed arrangement of gates and toggle circuits.-The toggle circuits are of the kind described in Specification No. 801,681, Group XL (c), and are primed by information read for example at time TA1 but are not triggered until the end of the period when a strobe pulse appears. The toggle therefore operates from time TA2 onwards after a delay equal to one bit of information. The operate tracks produce binary 1 and 0 outputs indicated as RC1, and RC1, and control the Delay Circuit comprised by toggles M13, M14. The gates G1, G2 are shown as available at times TA1 but if quarter words other than the first were involved they would be made available at times TA8, TA15, or TA22. Whichever of these times is employed M13 records. the 1 state to indicate a busy line, or 0 to indicate idle, during a period one word in advance and sets M14 accordingly over gates G3, G4, during time TA1 at the start of the next word. If the line has been found busy the Line Discriminator toggle M1 is set to 0 to block the equipment. If the line has been found idle M14 does not interfere and toggle M1 is set to 1 at time TA28 of the preceding word preparatory to the present word being inspected. The group number is now read simultaneously with and is compared with the number in the Wanted Number Store. Binary 1 and binary 0 from the Store gives outputs WGN and WGN, and from the auxiliary track gives outputs RC2 and RC2. Should the two group numbers disagree at any point, output RC2 will occur with WGN, or RC2 with WGN, and Line Discriminator toggle M1 will be set to the blocking 0 state over gates G7, G8. If the group numbers agree M1 stays in the 1 condition and the sequence number is examined. Before the sequence number is read the multiple appearance line mark in bit TA18 of the main library track appears as output RC3 and over gate G51, which constitutes the Multiple Appearance Line Discriminator, sets multiple Appearance Line Staticizer toggle M11 to the 1 state to mark the fact that at least one member of the line group is available. With Line Discriminator toggle M1 indicating a free line of the wanted line group gates G11, G12, G13, G14 are enabled in the Sequence Number Bit Gating Circuit. The Delay circuit is comprised by the toggle M2 which because of its inherent one bit delay marks the gates G11, G12, or G13, G14, depending on whether the preceding digit read RC2 or RC2. Toggles M3, M4 provide the Preceding Bit Memory and each handle alternate digits as they require time to be reset. Toggles M3 and M4 are connected to all the sub-group reading circuits. Toggle M2 is at 0 initially by virtue of RC2 which is always read out at TA18 and M2 and M3 will be at 0. If the first digit is 1, RC2 primes M2 and over G13 in time TA19 primes M3. In time TA20, M2 and M3 will have a 1 state and M3 will write 1 in the Sequence Number Staticizer to be described later. If the first digit reads binary 0 in TA19, M2 and M3 register 0 in TA20 unless M3 is set to 1 from another sub-group. If M3 registers 0 the Staticizer will record the first digit as 0. If the second digit is binary 1 and the first digit was also binary 1, M2 enables G12 at TA20 and M4 is set to 1 to control the Staticizer at time TA21. Had the preceding digit read binary 0, M2 would enable G14 so that M4 would be set to 1 only if M3 records 0 indicating that no other sub-group has found a binary 1 in the preceding bit position. If M3 records 1 indicating that a higher valued number is being inspected elsewhere, markings from M2 and M3 enable gate G17 and Line Discriminator toggle M1 is set to the 0 state to disconnect the sub-group. Thus a sequence number is relayed to the Staticizer by toggles M3 and M4, lower valued numbers being rejected. When the next word is encountered in each sub group the process is repeated but a comparison must be made with the contents of the Sequence Number Staticizer. This comprises the toggles M5 to M10 which are gated over G19 to G24 to the outputs of toggles M3 and M4 alternately, and in sequence at times TA20 to TA25 and are thereby set up to register a number. Gates G25 to G29 are provided so that if a registration is changed from 0 to 1 in any toggle circuit M5 to M10 the immediately subsequent toggle is set to 0 and by means of gates G30 to G33 the Reset Circuit comprised by toggle M12 is sent to its 1 state. With M12 in a 1 state gates G34 to G37 are enabled for the remainder of the word period being read so that the residue of toggles out of M7 to M10 is set to the 0 state before registering the new sequence number. At the end of the word M12 is reset over gate G50. The Sequence Number Bit Staticizer also communicates with the toggles M3, M4, of the Preceding Bit Memory to ensure that a number is rejected, as described above, if it has a value lower than that in the Staticizer. To read the number in the Staticizer gates G39 to G49 are provided. If M5 holds its 1 state this is communicated directly over gate G49 to M3. The toggles M6 to M10 may be in their 1 states at the time they are read out but be in the process of restoration to the 0 state and it is necessary to inhibit reading of the 1 state in these circumstances. Thus if M5 registers 1 M6 cannot be subject to change and is read out over G39 at TA20. If M5 registers 0 it may be changed to 1 from M3 but this is not so if M3 is at 0 and gate G40 is enabled by M3 to read M6. If M3 is at 1 gate G40 remains closed and M6 is not read. Toggle M7 is similarly read in dependence on the states of M6 and M4 which control gates G41, G42, and so on through all the toggles of the Staticizer. Gates G41 to G48 also depend on Reset Circuit toggle M12 being in the 0 state so that if at any point of a word cycle the Staticizer is subjected to registration of a higher valued number no read-out is allowed to the Preceding Bit Memory. At the end of a drum revolution the Sequence Number Staticizer is read out to control seizure of the chos