Patent GB-924753-A (GB)
Title: Improvements in or relating to electric pulse communication systems
Inventor: PINET ANDRE EUGENE
IPC: H03M1/00
Filed: 1961-03-28
Abstract: 924,753. Pulse code modulation systems. A. E. PINET. March 28, 1961 [March 28, 1960], No. 11358/61. Class 40 (5). A pulse communication system includes first means for sampling an incoming signal, second means for comparing the amplitude of each signal sample with each of a number of reference signals increasing progressively from zero, wherein consecutive reference signals define an amplitude range, third means responsive to the comparison to supply a first binary pulse code combination which indicates in which one of the plurality of amplitude ranges the amplitude of the respective signal sample lies, and fourth means for supplying a second binary pulse code combination indicating the position of the signal sample in the respective range. The incoming signal is subjected to amplitude compression during coding by providing three amplitude ranges each using a different quantization unit. Thus in Fig. 2, with a maximum sample amplitude of A, the code combination 32 corresponds to amplitude A/4, 48 corresponds to amplitude A/2 and 64 corresponds to amplitude A, giving the three-slope characteristic shown. The converse takes place at the decoder. A 7-unit code is used, the unit of highest order representing the polarity of the input signal. Coder.-The incoming signal at 101, Fig. 3, is supplied to a sampling circuit 1 including a circuit 102 for determining the polarity which switches a bi-stable device 103 to the " 1 " state if the signal is positive and leaves it in the " 0 " state if the signal is negative. In the " 1 "  position the trigger 103 also supplies a potential to an AND gate 410 supplying a tap on the delay line 400 feeding the output circuit 10. The input signal Uc is also fed via an inverting amplifier 104 and gate 105 or via a gate 106, according to the polarity of the signal, to a comparator 3 where it is compared with reference voltages Up supplied by a potentiometer 2 consisting of resistors 201 to 206 having values R, 2R ... 32R controlled by respective AND gates 211 to 216. A control circuit 8 permits the voltage supplied to the potentiometer resistors 202 to 206 via the line 22 to assume a value 2V, V, or V/2, and the voltage supplied to the resistor 201 via the line 21 to assume the value V or zero, according to the quantization unit required. A circuit 7, comprising bi-stable devices 711 to 716 is responsive to the comparison at 3 to select the appropriate resistors 201 to 206 through the gate circuits 211 to 216. Clock pulses are supplied by a generator 5 and supplied at intervals t 0 a to t 8 a by a tapped delay line 6a and at intervals t 0 b to t 6 b by a tapped delay line 6b, the interval t 0 b following t 0 a in time slot t 0 , and so on. The state of the devices 713 to 716 is checked at the instant t 7 a and passed via the delay line 400 to the output line 10. Bi-stable devices 711, 712 store a code combination representing the amplitude range with which the incoming signal is associated for combination with the code representing the amount by which the signal exceeds the lower limit of the range. At the start of the coding cycle all the bi-stable devices are in the " 0 " state except 808. Trigger 808 opens gates 803, 804, and voltage V is supplied to lead 21 and 2V to lead 22. At time t 0 a trigger 711 is switched to " 1 " and gate 211 opened to apply voltage V to resistor 201 of value R and supply a voltage Up to the comparator corresponding to the value A/2 between the ranges 42, 43, Fig. 2. Assuming that the voltage Uc is greater than A/2, the portion A/2 is represented by a two-unit binary code combination representing 48 and the portion exceeding A/2 is represented in the appropriate quantization units by a conventional binary code representing a number which may vary between 0 and 15. Since Uc-A/2 is positive, a signal is supplied via amplifier 9 which blocks the gates 722 to 726 and 827, 828, and gate circuits 803, 804 remain open. The quantization unit in the range 43 equals A/32. Trigger 711 1  also is switched to the " 1 " state at time t 0 a denoting a binary " 1 " of the sixth order corresponding to the number 32. At time t 1 a trigger 712 1  is switched to " 1 " via OR gate 737 and AND gate 809, thus denoting a binary " 1 " of the fifth order, i.e. 16, thus recording a total of 48. At this stage the gate 212 is not operated and the output of the potentiometer is still A/2. At times t 3 a, to t 6 a the triggers 713 to 716 are switched successively to the " one " state and reset to " zero " or maintained at " one " in accordance with the sign of the result of the comparison at 3 between the voltage Uc and the sum of the output voltages of the potentiometer stages of higher orders plus that of the stage under consideration. For example, at time t 3 a trigger 713 is switched to " 1 " and remains there if the voltage Up, which is then equal to 3/A4 is lower than the voltage Uc. The resulting positive signal from 3 blocks the gate 723 at time t 3 b and prevents trigger 713 from being reset, and the next comparison voltage will be 7A/8. If Uc is smaller than Up the negative signal from 3 causes gate 723 to operate and reset trigger 713 to " 0," and the next comparison voltage will be 5A/8. At time t 7 a the gates 410 to 416 are opened and the code signal applied to the output line 10. Assuming the voltage Uc to be coded is less than A/2, Uc-A/2 is negative and AND gate 828 is opened at time t 0 b to reset trigger 808 to " zero," and gates 803, 804 are blocked. At time t 1 a trigger 807 is set to " 1 " via gate 806 and opens gate 802 to apply voltage V to the line 22; the voltage on line 21 being zero. Trigger 711 is also set to " zero " at this time to block the gate 211, and the trigger 712 is set to " 1 " to open gate 212 and supply the voltage V to resistor 202 of valve 2R, thus applying a voltage Up=A/4 to the comparator. If the voltage to be coded is larger than A/4 the portion A/4 is represented by the two unit binary code equivalent to the number 32 and the portion in excess of A/4, i.e. between 0 and 15 is coded using the appropriate quantization unit. The positive difference signal from the comparator 3 blocks the gates 722 to 726 and 827, 828 and the trigger 807 is held in the " 1 " state. The quantization unit in the range 42, Fig. 2, is A/64. At time t 0 a the trigger 711 has been set to " 1 " and when 711 is reset it remains at " 1 " thus storing the combination corresponding to the number 32, the trigger 712, representing the number 16 remaining at " zero." The trigger circuits 713 to 716 operate as before but with successive comparison voltages of A/8, A/16, A/32, A/64. At time t 7 a gates 410 to 416 are opened as before. When the voltage to be coded is lower than A/4 the number to be coded in the appropriate quantization unit steps may vary between 0 and 31 and the stage 202, 212 previously used for checking in which coding range the signal to be coded is situated is now used for the coding proper. For this reason the trigger 712 is maintained in the " 1 " state for periods t 1 a, t 1 b and t 2 a, tab, and during the first interval co-operates with the potentiometer 2 to supply a comparison voltage of A/4 and during the second interval when the potentiometer is V supplied with voltage - a voltage of A/8. The 2 first comparison at 3 produces a negative output signal and gate 827 conducts at time t 1 b, returning trigger 807 to " zero." Gate 802 is blocked and gate 801 conducts and supplies voltage V/2 to line 22 and the quantization unit is thus made equal to A/128 for the lowest range 41. Trigger 711 1  is set to " zero " via gates 728, 738. If Uc is larger than Up (A/8 at this stage) trigger 712 remains at " one " and this state is transmitted at time t 5 a to trigger 712 1  via gates 727, 737. The trigger circuits 713 to 716 operate as before but with comparison voltages of A/16, A/32, A/64, A/128. At time t s a all triggers are reset to zero except trigger 808 in readiness for the next cycle. Decoder.-The incoming pulses on line 10, Fig. 4, are supplied to a tapped delay line 1400, similar to delay line 400 at the coder, and the pulses present are transferred via AND gates 1411 to 1416 to set appropriate triggers 1711 to 1716 controlling via gates 1211 and 1213 to 1216 a potentiometer 12 including resistors 1201 to 1206 having the same values as in the potentiometer at the coder. The decoding depends upon the coding range as determined by the second and third pulses of the code combination as received, the first pulse denoting the sign, and the selection of the coding range is effected by circuit 18. If the amplitude lies between 0 and A/4, the trigger 1711 is at " zero," gate V 1801 is conductive, and voltage - is supplied 2 to lead 122. If a pulse of the next order is present, trigger 1712 opens gate 1809 and voltage V/2 is supplied via lead 123 to resistor 1202 of value 2R. For the second range 42, Fig. 2, trigger 1711 is in the " one " state and trigger 1712 at " zero," and gates 1802, 1807 conduct to supply voltage V to the lead 122. Gate 1802 1  also conducts and resistor 1202 is supplied with voltage V, producing at the output 13 the voltage A/4. In the third range 43 triggers 1711, 1712 are in the " one " state, and gates 1808, 1804 conduct to supply voltage 2V to the lead 122. The gate 1211 also conducts via gate 1808 and voltage V is supplied to resistor 1201 of value R, producing at the output 13 the voltage A/2. The sign restoring circuit 11 is the same as that in Fig. 1, with the sign detector circuit 102 omitted. Trigger 1103 controls one or other of gates 1105, 1106, according to the sign signal, an inverter stage 1104 being connected between gate 1105 and the output 1101. The samples at the output 1101 are passed in the usual way through a lowpass filter.