Patent GB-910787-A (GB)
Title: Improvements relating to pulse width modulators
Inventor: JAQUES ANTHONY FRANCIS
IPC: G06G7/161
Filed: 1958-02-13
Abstract: 910,787. Pulse modulation systems. ELECTRIC & MUSICAL INDUSTRIES Ltd. Feb. 13, 1959 [Feb. 13, 1958], No. 4685/58. Class 40 (5). Relates to pulse width modulators, e.g. for use in analogue computers to set the mark to space ratio of the rectangular wave of a timedivision multiplier circuit. In a known arrangement, a modulating signal X is applied via a terminal 6, Fig. 2, and summing resistor 3 of resistance R to a Miller integrator circuit comprising a D.C. amplifier 1 and feed-back capacitor 2. A constant voltage +K is applied via terminal 7 and summing resistor 4 of value R to the integrator circuit, and a constant voltage - K is applied via terminal 8, summing resistor 5 of value R/2, and a switch 9, to the integrator circuit. The output of the integrator circuit is connected to a trigger 10 so that the trigger changes from a first state to a second state when the output from the integrator exceeds a first datum level and changes back to the first state when the output of the integrator falls below a second datum level which is lower than the first level. The trigger 10 opens the switch 9 to interrupt the voltage - K when in the first state and closes the switch when in the second state, and the first and second states respectively define the mark and space periods of the output signal. In operation, the integrator output rises steadily at a rate determined by the sum of the applied voltages X+K, the value of the resistance R, the gain of the amplifier, and the size of the feed-back capacitor, to the first datum level. When the output exceeds the first datum level the trigger switches to the second state and switches in the voltage - K. The values of the resistors 4 and 5 are arranged so that the resultant input from 7 and 8 is equal to - K, and the total applied voltage is equal to X - K. The output of the integrator now starts to fall until the second datum level is passed and the trigger reverts to its first state. The trigger output is amplified at 11 and clipped to the desired amplitude at 12, the output being taken from terminal 13. In one embodiment of the invention, the output of the amplifier 11 is inverted at 14 and fed to a limiter 15 which limits the positive and negative excursions of the inverted waveform to + K and - K respectively. The output of the limiter 15 is smoothed at 16 and fed via resistor 17 to the input of the amplifier 1. The input signal X is fed as before through a resistor 3 which has its value reduced to R/N, the resistor 17 having a value equal to R/N-1. If the modulator introduces an error in the value of X and hence in the value of - X fed back, the arrangement produces an effective output to the integrator of N - 1 times the error signal in addition to the input signal X whereby compensation for the error is effected. In an alternative arrangement, Fig. 3 (not shown), the smoothed output of the limiter 15 is combined in a summing amplifier with the input signal X before application to the integrator 2. In a further embodiment, Fig. 4, the input signal X is applied at terminal 6 to an integrating amplifier 1 via a resistor 3, a trigger 10 being controlled as before by the integrator and the output amplified at 11 and clipped at 12 to the desired limits. The output of the amplifier 11 is inverted at 14 and limited at 15 to the values + K and - K fed in at terminals 7 and 8, respectively, this limited waveform being fed via a resistance 21, which has the same value as resistance 3, to the integrator 1. In this way the feedback loop provides a reduction in the errors of the modulator and also provides the change of input to the amplifier 1 with the change of state of the trigger 10, the switch 9 being dispensed with.