Patent GB-761884-A (GB)
Title: Improvements in or relating to analogue-to-digital converters
IPC: H03M1/00
Filed: 1954-01-12
Abstract: 761,884. Selective signalling. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Jan. 12, 1954 [Jan. 12, 1953], No. 881/54. Class 40 (1). In an analogue to digital voltage converter, the analogue voltage is compared with a second analogue voltage which is varied in accordance with the setting of a digital register, the register setting being advanced stage-by-stage by the comparison voltage until the compared voltages are equal. Positive or negative numbers may be registered, the sign of a number being indicated by a separate digital stage set prior to the stage indicating the magnitude of the number. General operation. As shown, an analogue voltage U applied at 11 is converted into its binary equivalent on a counter 10 having three denominational stages I, II, III, representing 2<SP>0</SP>, 2<SP>1</SP>, 2<SP>2</SP>, respectively, and a further stage S to register the sign of the voltage. The counter setting is fed to a reading unit 6 and to a decoder 5 which converts the digital setting into a corresponding analogue voltage Z the sign of which is reversed in an amplifier 51 before being fed at 7-9 to a comparator 8, where it is added algebraically to the analogue input U. The comparator differential output (U-Z) is amplified at 77 and actuates a bi-stable trigger 31 according to its sign. If (U-Z) is positive, the triode 22 of the trigger conducts and blocks a pentode 32 in a transfer circuit 13. If negative, the trigger triode 23 conducts, and unblocks the transfer circuit to permit timing pulses do, Fig. 2, applied at terminal 14 to be passed over an inverter stage 33 to the control grids of gating valves 15 ... 18 over which the counter stages are set successively. These valves 15 ... 18 are gated successively by pulses ds, d4, d2, d1, Fig. 2, fed over terminals 19, 20, 21, 26 to their suppressor grids. Setting the counter. A negative reset pulse Ro, Fig. 2, is applied over terminal 28, Fig. 3, to zeroize all stages of the counter at the beginning of each encoding cycle, the sign stage S being reset to correspond to positive. The decoder output then being zero, the comparator output is of the same sign as its input so that only if the analogue input U is negative, is the do pulse passed by the transfer circuit 13 during gating of the valve 15 by pulse ds, whereby the counter stage S is switched to its "one " condition indicative of the negative sign. During the following sequential gating periods of the valves 16, 17, 18 short dt pulses, Fig. 2, are applied over terminal 27 to set the associated counter stages III, II, I to the " one " condition, each counter stage being reset to zero by the immediately following do pulse occurring during the same long gating pulse d4, d2, dl, if the transfer circuit 13 is unblocked. The transfer circuit being controlled by the comparator circuit, as above described, in accordance with the sign of the comparator output (U-Z) the counter stages are thus set in accordance with the magnitude of the analogue input U. Decoder. This comprises triodes 38, 39, 40 which conduct in series with respective diodes 55, 56, 57 when the associated counter stages I, II, III are in their zero condition. When the highest denominational stage III is driven to its " one " condition, as above described, the tubes 40, 57 are blocked whereby a voltage of + 4 volts, corresponding to the counter stage setting, and applied at terminal 43, is fed over an input summing resistor 48 to the amplifier 51. Similarly, voltages of + 2 and + 1 volts are fed from terminals 42, 41, respectively, when the associated counter stages II, I are driven to their " one " condition, to summing resistors 47, 46. A triode 75 in the decoder conducts when the sign registered in counter stage S is positive, whereby a tube 76 is blocked and permits diode 52 to conduct, whereby a resistor 49 is clamped to zero potential. When the sign registered is negative the triode 75 is blocked; 76 is unblocked and blocks the diodes 52, 54 whereby a potential of - 7 volts, applied to terminal 45, is fed to the summing resistor 49. The diodes 55, 56, 57 apply zero potential to the respective summing resistors in the zero positions of the associated counter stages. The sum Z of the voltages on the summing resistors 46-49, which is thus the analogue value of the counter registration, is inverted at 51 and fed to the comparator 8 as above described. Reading unit, 6. Reading pulses are applied at 70 simultaneously to the control grids of pentodes 66, 67, 68, 69 which are controlled by the corresponding register stages I, II, III, S to transmit the reading pulse only if the associated register stage is in the binary one condition. The outputs of these pentodes are connected to input taps 64, 63, 62, 65 of a delay line, so that at the output end 74 of the line, pulses appear whose time spacing indicates in binary digital from the number registered on the counter, the first pulse indicating the sign of the number. Alternatively, the outputs of the tubes 66-69 may be connected directly to the output line 74 and the reading pulses applied through a delay line so as to reach the tubes sequentially.