Patent GB-1184653-A (GB)
Title: Self-Adaptive Filter
Inventor: MOYE LAURENCE STANLEY
IPC: H03H21/00
Filed: 1967-01-03
Abstract: 1,184,653. Equalization systems. INTERNATIONAL STANDARD ELECTRIC CORP. 3 Jan., 1967, No. 210/67. Heading H4R. In an automatic equalization system an input signal is fed through a number of orthogonal networks, which may be delay circuits, resonant circuits, or circuits having Laguerre or Legendre functions for the impulse response, and the networks are automatically adjusted to make the total network output signal the same as a target signal. Fig. 1 shows a number of orthogonal networks # 1 (#) ...# n (#), the outputs of which are combined via multipliers 10 and adders 11 to form an output signal X<SP>11</SP>(t). The orthogonal networks may be delays in which case the filter 2 forms a transversal equaliser. The networks in the filter 2 are adjusted by the outputs of the correlator 1 which includes a similar set of orthogonal networks # 1 (#) ... # n (#) the outputs of which are multiplied in 5 by the difference, obtained in 12, between the output of the adaptive filter, x<SP>11</SP>(t), and the desired signal, x<SP>1</SP>(t). The resulting product is integrated in order to derive the cross correlation function of these functions, and the integrator output is used to adjust the multipliers 10 of the adaptive filter so that the output signal x<SP>11</SP>(t) is made to agree with the target signal x<SP>1</SP>(t). Since the sets of orthogonal networks used in the filter and the correlator are identical they may be replaced by a single set of networks as in Fig. 2 (not shown). In a practical embodiment the linear network would be the communication system, e.g. a line, which signals would traverse from B to A, and the adaptive filter would attempt to restore the output from the line, i.e. x(t), to match the input to the line, i.e. x<SP>1</SP>(t). In this case the signal x<SP>1</SP>(t) would not be available at the location of the adaptive filter and so either the line would be fed with a known signal and a similar signal would be generated and used at the receiver to provide the " target " signal or, as shown in Fig. 10, the target signal would be derived from the output of a detector 72 fed with the adaptive filter output, the delays To and Td being respectively the delay suffered by the target signal in traversing the filter and the detector, and the delay in the channel 73. Adaptive filter using recirculating delays is shown in Fig. 8. In this embodiment the signal to be equalized and the target signal are converted to digital form and fed to the equipment. Samples of the signal to be equalized, x(t), are fed into delay 61 periodically to replace the oldest sample being circulated, one sample being replaced each sampling period and the complete train of samples being circulated once in each sampling period and the complete train of samples is presented to the multiplier 62 in sequence. Also presented to the multiplier are the error signal samples derived in the differencing circuit from the output of the transversal filter and the target signal x<SP>1</SP>(t). The output from the multiplier is added to the previous signals circulating in delay 63 so that the signal samples circulating in the delay 63 correspond to the signals appearing at the outputs of the correlator in the basic circuit shown in Fig. 1. These signals, multiplied in 64 by the signal samples circulating in the delay 61, are added together in the accumulator 65 and the sum is shifted into register 66 from which it is available via the digital to analogue converter 67 as the output of the system. The system is similar to the arrangement of Fig. 1 except that the operations are performed serially by one circuit rather than simultaneously by one circuit per stage. Adaptive filter using Laguerre networks. Fig. 5, shows one stage of an embodiment using a Laguerre network 22 for the orthogonal network. This is most suitable for production in integrated micrologic form in that it uses feedback amplifiers in place of the delay networks. This arrangement is equivalent to one stage of the Fig. 1 arrangement modified to use one orthogonal network for both the adaptive filter and the correlator, i.e. as described with respect to Fig. 2 (not shown). In this embodiment, since the arrangement does not have to respond at high speed, a stochastic multiplier 23 is used for the multiplier which multiplies the orthogonal filter output with the error signal on line 28 and the output is fed to a reversible binary counter 24 which replaces the integrator. The output multiplier and adder are combined in 25.