Patent SE-7505920-L (SE)
Inventor: FERENCZY P
IPC: H04N9/64
Filed: 1975-05-23
Abstract: 1502392 Television systems VIDEOTON RADIO ES TELEVIZIOGYAR 23 May 1975 [25 July 1974] 22542/75 Heading H4F A receiver for quadrature-modulated suppressed carrier television signals, consisting of first and second sub-carrier components modulated by respective first and second chrominance signals, includes means for adding a sub-carrier in phase quadrature to both components so as to generate quadrature signals phase-modulated with respective chrominance signals, and means for removing any amplitude modulation of the phase-modulated signals by limiters. In one embodiment, Fig. 2, the received quadrature-modulated signals selected by filter 12 pass to adders 14, 15. If the signal is a PAL signal phase shifter 13 reverses at line frequency the phase of the signal fed to adder 14; if it is an NTSC signal no phase shift is used. Each adder receives a locally generated (20) sub-carrier which is in quadrature with the sub-carrier component fed to it, and which has an amplitude at least ten times that of the component. Each adder gives an output which has a phase approximating to one of the chrominance signals and an amplitude approximating to the other one. The amplitude modulation is removed by amplitude limiters 16, 17 and the resulting quadrature phase-modulated signals demodulated in phase detectors 18, 19 with sub-carriers which are in phase with the relevant phase modulated signal. In a second embodiment, Fig. 3, the received NTSC quadrature-modulated signal from filter 14<SP>1</SP> passes to adders 15', 16' where locally generated (25) quadrature sub-carriers are added as described above. The adder outputs are then passed via line-sequential switch 17<SP>1</SP> to a common amplitude limiter 18<SP>1</SP>. The resulting line-sequential phase-modulated signal passes direct and via line delay 19' to a line-frequency switch 20' which outputs simultaneous chrominance signals to limiters 21<SP>1</SP>, 22<SP>1</SP> and phase detectors 23<SP>1</SP>, 24<SP>1</SP>. If a PAL signal is received a phase inverter precedes one of the adders as in Fig. 2. In a further arrangement, Fig. 4 (not shown), the received PAL signal passes to a single adder (14<SP>11</SP>) where it is summed with an in-phase sub-carrier during alternate lines and a quadrature carrier during the remaining lines. The resulting linesequential signal passes via an amplitude limiter (15<SP>11)</SP> to a phase detector (18<SP>11</SP>) fed with in-phase and quadrature carriers during successive lines. The line-sequential chrominance signal from the detector passes to a line-sequential switch (20") direct and via a line delay (19")to generate simultaneous chrominance signals. In a modification of Fig. 2, Fig. 5 (not shown), instead of feeding each phase detector via a single adder, two adders are used (120, 121; 128, 129), one being fed direct and the other via a phase inverter (122, 130) with locally-generated sub-carrier. The adder outputs have equal but opposite phase deviations and are fed via respective + 45 and -45 degree phase shifters (123, 124; 131, 132) and limiters (125, 126; 133, 134) to a phase comparator (127, 135) which outputs a phase-difference signal representing the chrominance signal.