Patent GB-935654-A (GB)
Title: Digital phase-pulse detector
IPC: H04L27/18
Filed: 1960-05-25
Abstract: 935,654. Multiplex phase-shift signalling. COLLINS RADIO CO. May 25, 1960 [Sept. 9, 1959], No. 18506/60. Class 40 (5). In a multiplex system in which information is transmitted by changing the phase of an A.C. signal relative to a previously existing phase, two filters are provided capable of receiving and storing the A.C. signals of the two phases, a square-wave signal being formed from one of the filter outputs, and a short pulse being formed from the other of the filter outputs and means being provided for determining whether or not coincidence occurs between the square wave and the pulse. Fig. 1 illustrates an arrangement for receiving signals modulated in " twinplex " fashion, the phase changes for the various combinations of marks and spaces for the two channels being illustrated in Figs. 2A, 2B. This figure also illustrates the phase domains corresponding to the reception of marks and spaces for the respective channels. The phasemodulated signal Fig. 3 (A) is fed to the inputs of filters 21, 22 which are enabled alternately by drive pulses, Figs. 3 (F, G), to enable an oscillation of the appropriate phase to build up in the filters, each drive pulse being preceded by a quench pulse which damps the previously stored oscillation. The outputs from the filters are switched during alternate periods by a relay (which may be electronic) so that the stored phase, i.e. the preceding or reference phase is fed to lead 31 and the new phase is fed to lead 32. The stored phase is fed to a former 43 to produce square waves, Fig. 4 (B). The new phase is fed to a pulse forme which produces a short pulse each time the wave crosses the zero line in an upwards direction. If this corresponds to a 45 or 135 then a M 1  signal is present as seen from Fig. 4. If the short pulse corresponds to 135 or 225 then a S 1  signal is present. The output of circuit 44 is thus sampled during one cycle by a sampling pulse 49 and fed to gate 52 which is thus open for an M 1  signal but not for an S 1  signal, the channel 1 output being pulsed or not accordingly. For obtaining the channel II signal the stored pulse is delayed at 41 by 90 and squared up to produce the waveform of Fig. 4 (C) to provide an input to gate 51. As can be seen from Fig. 4, phase shifts of 45 or 315 corresponding to M 2  produce an output from gate 51 but phase shifts corresponding to S 2  do not. In a modification, Fig. 6 (not shown), the outputs from output gates are provided, enabled respectively from the square wave, the inverted square wave, the 90 displaced square wave and the inverted 90 displaced square wave. Thus positive outputs from the respective gates are obtained in respect of S 1  and S 2  as well as M 1  and M 2 . The mark and space outputs of the respective channels are fed to the two inputs of bi-stable circuits whose outputs are thus D.C. of different levels for mark and space. The circuit of Fig. 6 also omits the change over relay of Fig. 1. This results in alternate polarity reversals for channel I and a correction circuit is inserted in this channel. In a further modification, Fig. 7 (not shown), the response time is decreased by making use of not only of the upward crossings but also of the downward crossings for determining the phase displacement. Thus pulses due to upward crossings are fed during the sampling period to one bus-bar and crossings due to the downward crossings are fed to another, the latter being 180 out of phase with the former. Thus the channel outputs are then obtained by the combined outputs from two gates fed from the respective bus-bars but opened 180 out of phase with each other. Further modifications are given for receiving combinations represented by phase shifts of 0, 90, 180 and 270, Fig. 5 (not shown). In a further modification three channels are supplied, channel III signals being effected by varying the phase 22¢ on either side of the phases shown in Fig. 2. The resulting phase diagram, Fig. 9, shows that the M 3  phase domain is divided into two opposite 90 segments, as is also the S 3  domain. Fig. 8 illustrates the additional equipment necessary to receive channel III. This consists of two phase shifters of +45 and - 45 respectively, each followed by square wave formers 92, 94. Gate 98 is fed with the outputs from 92 and the inverted output from 94 and corresponds to the upper part of the M 3  domain. Gate 99 is fed by the outputs of 94 and the inverted output of 92 and corresponds to the lower part of the M 3  domain. Coincidence registered in either of these gates with the output from circuit 44 causes a mark signal to appear on channel III. The invention may also be applied to ordinary phase-modulated time division systems. Specification 866,632 is referred to.