Patent GB-1271597-A (GB)
Title: Automatic transmission control systems for automatic automtive transmissions
Inventor: WAKAMATSU HISATO
IPC: F16H61/02
Filed: 1970-07-23
Abstract: 1,271,597. Change-speed control. NIPPONDENSO K.K. 23 July, 1970 [6 Aug., 1969], No. 35736/70. Heading F2D. [Also in Division H3] In an electronic control for solenoid shiftvalves 40 of an automatic transmission (not shown) on a motor-vehicle, wherein ratio shift is in response to vehicle speed, detected at 10 by generating signals at speed-responsive frequency and converting them at 113 to voltage signals; and to engine throttle 20 or intake depression, these signals jointly controlling a memory circuit 170 provided with a cut-off to lock in the prevailing ratio on complete release of the throttle control, the output speed detector 10 is itself also used to generate a near-zero (2 K.p.h.) speed signal in a low-speed detector circuit 116, which releases the lock imposed on the memory circuit, so that, on decelerating in a higher ratio with released throttle, first ratio is established before the vehicle finally stops, thus avoiding the shock which might otherwise occur if downshift to first ratio could only occur on re-depression of the throttle pedal to restart the vehicle. Two, three, four or five ratios may be controlled, the only embodiment being for four ratios.  Speed detection.-An output driven alternator 10 (not described) generates a frequency proportional to vehicle speed, which is processed in an amplifier 110 to a square wave of constant amplitude, which is converted in a digitalanalogue converter 113 to a D.C. output signal voltage 115 proportional to speed. The output 112 of the amplifier 110 is fed to the input 117 of the low-speed detector 116 (described below) which emits a zero signal 118 when vehicle speed falls below 2 K.P.H. Engine load detection 20, is by intake depression or throttle-pedal setting, only the latter being described. A switch arm (24, Fig. 4, not shown), supplied with constant voltage, makes successively three contacts 21, 22, 23 as the throttle pedal is depressed. With the throttle pedal completely released there is zero voltage signal in a line 179 to the memory circuit 170, which is thereby locked, as described below, in the ratio setting which prevailed before such release. Depression of the throttle pedal in a "light" range makes the first contact 21, sending a voltage signal to the line 179 unlocking the memory circuit 170 for normal shift control. In the medium range of pedal depression the second contact 22 is additionally made and in a full throttle range the third contact 23 is also made. The contacts 22, 23 supply a throttle circuit 120 consisting of a series and parallel resistor network (Fig. 5, not shown), with constant voltage supply, and emitting a voltage signal 124 which increases in three stages, corresponding to light, medium and full throttle. Complete circuit.-The analogue speed signal 115 and throttle signal 124 supply 1-2; 2-3; and 3-4 signal generators 130, 140, 150, comprising comparison and feed-back circuits (not described), each of which has two output signal lines 133, 134 &c. 1-2 upshift is signalled by voltage in the line 134 and zero in 133, this being reversed for 2-1 downshift. 2-3 and 3-4 signal pairs are similar. A logic circuit 160, not described, receives the shift signals 133 ... 154, and, for each ratio, supplies a single output voltage signal to a corresponding one of each of four lines 161<SP>1</SP> ... 164<SP>1</SP>, the remaining three lines having zero voltage. This logic output feeds the memory circuit 170 at respective inputs 171 ... 174. The memory circuit 170, Fig. 9, comprises two bi-stable multi-vibrators 1700, 1700<SP>1</SP>, each comprising two transistors 1702 ... 1705, two, 1703, 1704, or which have their bases grounded through capacitors to ensure prior switching of the other two. Power 1701 initially switches on 1702, 1704. A first ratio input signal at 171 only, through diodes 1710, 1716, switches off 1702, 1704, which switch on 1703, 1705, providing voltage signals at outputs 176, 178, zero at 175, 177. Similarly the second ratio input signal 172 switches off 1703, 1704 and on 1702, 1705 providing output voltage signals at 175, 178, whilst third and fourth ratio inputs 173, 174, provide outputs at 175, 177 and 176, 177 respectively, the remaining two outputs in each case being at zero. The throttle-release memory lock and its low speed release are as follows. In normal running, with the throttle pedal depressed above idle, the throttle switch 20 provides a voltage signal in the line 179, which switches on a transistor 1709 and off a transistor 1708, unlocking the memory. Release of the throttle pedal to idle cancels the signal 179, which switches off 1709 and on 1708, the latter, through diodes 1720...1723, grounding all the ratio input signal lines 171 ... 174, locking the memory circuit 170 in its existing ratio setting. At near zero vehicle speeds (2 K.P.H.) the voltage signal at 179<SP>1</SP> is zeroized by the low speed detector 116, so that transistor 1708 is switched off, releasing the memory lock for downshift to first ratio. A valve drive circuit 180 receives the paired output signals 175 ... 178 of the memory circuit 170 and emits single voltage signals 185 ... 188, each representing a ratio, to an electromagnetic valve unit 40 which establishes the ratios. The valve drive circuit 180, Fig. 10, not shown, comprises four transistors (1801 ... 1804) in an AND circuit, switching four power transistors (1805 ... 1808) supplied with power at 31 from a manual selector switch 30 in an automatic setting, remaining settings directly controlling the valve unit 40 for manual first, second and third ratios and reverse, the automatic setting giving all four forward ratios. Low speed detector 116 comprises an input 117, fed directly with constant-amplitude squarewave speed-responsive frequency by the amplifier 110 of the speed detector 10. Terminal 1163, Fig. 2, receives 12 volt supply, and 118 emits output signals. With zero input voltage at 117 a transistor 1161 is cut off and current flows from 1163 through a resistor 1162 and constant-voltage (seven volts) Zener diode 1168, to switch on a transistor 1169, having a grounded emitter, providing a zero signal at 118. Application of the square-wave input 117 causes the transistor 1161 to be switched on and off alternately at input frequency. During the off period a capacitor 1167 is charged and instantaneously discharged through the transistor 1161 when it is again switched on. If the interval between the triggering of the transistor 1161 (as determined by input frequency) exceeds the time required to charge the capacitor 1167 to a voltage above the striking voltage of the Zener diode 1168, the latter switches on the transistor 1169 to provide a zero voltage signal at 118, to the terminal 179<SP>1</SP> of the memory circuit 170. Frequencies above this value maintain the transistor 1169 off, so that voltage exists at the memory circuit terminal 179<SP>1</SP> to trigger the memory transistor 1708 on throttle release to lock the memory.