Patent GB-1082804-A (GB)
Title: A time-division multiplexed pcm transmission system
IPC: H04J3/06
Filed: 1964-11-09
Abstract: 1,082,804. Multiplex pulse code signalling. NIPPON ELECTRIC CO. Ltd. Nov. 9, 1964 [Nov. 7, 1963], No. 45546/64. Heading H4L. In a time division multiplex p.c.m. system in which a separate group of pulses represents the information in each channel, means are provided at the transmitter for inserting groups of frame synchronizing pulses into the multiplexed pulse train and for inserting at least one channel synchronizing code element into a preselected position in each of said groups including the frame synchronizing groups, such that the channel synchronizing code elements in adjacent groups form a predetermined recurring pulse pattern. As described, a 7-digit code is used for the signal samples and the frame synchronizing signal also consists of a 7-digit combination which is not used to represent any of the sampled values, e.g. 1111111, the frame synchronizing signal appearing at the start of each frame. In addition, each channel pulse group and the frame synchronizing pulse group is preceded by a single digit providing the channel synchronizing signal and appearing as alternate 0 and 1. Other recurring code sequences may be use dfor the channel synchronizing signal. The system is stated to be particularly suitable for radio transmission liable to fading or other interruption. Transmitter, Fig. 2. Voice signals on 240 channels from source 8 are sequentially sampled at 31 under the control of channel and frame synchronizing pulse generator 32 and the resulting time division multiplex signals are pulse coded at 33 under the control of pulses A, Fig. 3 (not shown), from bit timing generator 34. Pulses A also control a channel timing signal generator 35 via a chain of bi-stable devices 351 to 354 the " 1 " output of bi-stable 353 providing channel timing pulses B, and the output of gate 356 providing the channel synchronizing " 1 " pulses C. Pulses B control a bi-stable chain 3205 in pulse generator 32 which supplies a matrix 3206 which in cooperation with a further bi-stable chain 3215, a matrix 3216 and a matrix 3220 provides the 240 channel control pulses for the sampler 31. The 241st control pulse (D241) is given a fivebit delay at 3221 to form frame synchronizing control pulses E, the pulses E also being used to reset counters 3205, 3215. Pulses E are supplied to an AND gate 361 together with pulses B to control a frame synchronizing pulse generator 36 including a monostable device 362 producing a pulse G of seven bits duration. The p.c.m. signals F, the frame synchronizing signals G and the channel synchronizing pulses C are supplied via an OR gate 371 to a radio transmitter 38 which is modulated in conventional manner. Receiver, Fig. 4. The demodulated signal L is supplied to a bit timing frequency generator 52, 53 and the resulting bit frequency pulses (I) Fig. 5 (not shown), control a channel synchronizing signal generator 54 producing via a bi-stable chain 5402 to 5405 channel timing pulses (J), an inter-channel pulse train (K) and first and second channel reference pulse trains (K<SP>1</SP>, K<SP>11</SP>) which appear alternately at half the repetition frequency of pulses (K). Pulses (I) and (J) control a decoder 57 in the normal manner. Pulses (K<SP>1</SP>, K<SP>11</SP>) are supplied together with the received p.c.m. signal to gates 551, 552 respectively of a channel synchronizing error detector 55 which produces an error signal via binary chain 554, 555 if the channel synchronizing is incorrect. This error signal is applied to generator 54 via gate 5413 to shift the leading edge of the pulses generated by a one-bit interval when a frame synchronizing error is also applied thereto, and the operation is repeated until channel synchronizing is restored. Binary chain 556 to 558 is arranged to reset chain 554 to 555 at a repetition frequency equal to twice the channel interval. Pulses (I), (J) and (K) together with the received signal are supplied to a frame synchronizing error signal generator 56 which produces via binary chain 5603 to 5606 a pulse (N) when the frame synchronizing signal is detected at the correct time. The output of decoder 57 is supplied to a distributer 58 controlled by channel distribution signals (O 1  to O 240 ) supplied by pulse generator 591 under the control of pulses J and N. Generator 591 produces a frame synchronizing reference pulse train (P) within the time interval allotted to the 240th channel and if frame synchronizing is correct the pulse (P) will coincide with pulses (N). This is checked via gates 5612 to 5614 co-operating with bistable chain 5615 to 5617, providing a delay of four frame intervals and if an error occurs for at least four frames a pulse is supplied via gate 5618, 6-bit delay 594 and agate 595 to reset channel pulse distributer control circuit 591, and pulses are supplied to gate 5413 of the channel synchronizing generator 54 to allow the operation of generator 54, and to distributer 58 to prevent signals being transmitted to the wrong channels. Each time circuit 591 is reset the 240th channel distribution signal (O 240 ) is supplied as a pulse (P) via 4-bit delay 592 to checking circuit 5612 &c. and when synchronism is recovered a pulse N resets bi-stable chain 5615 to 5617 to prevent the generation of a frame synchronizing error pulse. The 241st channel distribution signal resets generator 591 via 4-bit delay 593.