baber/WOPTO huggingface dataset:
Patent TW-578123-B (TW)
Title: Pixel having transparent structure and reflective structure
Inventor: LU AN-HSU
IPC: G02F1/1362
Filed: 2002-12-03
Granted: 2004-03-01
Abstract: A pixel having transparent structure and reflective structure comprises a scan line on a substrate, a gate dielectric layer on the substrate covering the scan line, a data line on the gate dielectric layer, a passivation layer on the gate dielectric layer covering the data line, a transparent pixel electrode on the passivation layer, a reflective pixel electrode on the gate dielectric layer and a double drain TFT on the substrate. The double drain has a gate, a channel a source and two drain, and source is electrically connected to the data line, the two drain are electrically connected to the transparent pixel electrode and the reflective pixel electrode respectively, and the gate is electrically connected to the scan line.
Patent TW-571458-B (TW)
Title: Gas humidification apparatus for a fuel cell bi-polar plate
Inventor: YAN YI-YIE
IPC: H01M8/04
Filed: 2002-12-20
Granted: 2004-01-11
Abstract: The invention relates to gas humidification apparatus for a fuel cell bi-polar plate by setting a connecting channel in the middle part of the fuel channel of the bi-polar plate and attaching a material which absorbs water in the bottom of the fuel channel guiding the humidification water into the fuel channel and making the fuel to get enough vapor to increase the humidity of the proton exchange membrane and to improve the efficiency of the fuel cell.
Patent TW-I260636-B (TW)
Title: Low power content addressable memory architecture
Inventor: KIM JIN-KI
IPC: G11C15/00
Filed: 2002-12-27
Granted: 2006-08-21
Abstract: A low power CAM architecture is disclosed. Matchlines of the CAM array are segmented into a main search portion and a main search portion. After issuing a search command, a main search operation is conducted on the main search portion of the matchline. If the result of the main search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of main search is a mismatch, then the main-search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Main search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the main search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.
Patent TW-588358-B (TW)
Title: Semiconductor memory device and its refreshing method
Inventor: SATO HAJIME
IPC: G11C11/406
Filed: 2003-03-03
Granted: 2004-05-21
Abstract: The purpose of the present invention is to obtain the refreshing method for semiconductor memory device, in which the refreshing method is featured with having excellent noise tolerance, low electric power consumption and low cost. In the memory cell blocks ((BLK0 to BLK3), the entire word lines (WL) of the non-selected memory cell block in the automatically refreshing mode is controlled at a floating electric potential roughly close to the ground level. Based on the control, it is capable of preventing the memory cell from information destruction and current leakage due to noise even that short circuit is formed between the word line and the bit line. In addition, because it is unnecessary to install the fuse component for preventing leakage current, low cost can be obtained.
Patent TW-I224677-B (TW)
Title: Probe card and method for manufacturing probe card
Inventor: ARISAKA YOSHIKAZU
IPC: G01R31/28
Filed: 2003-03-06
Granted: 2004-12-01
Abstract: A probe card that is manufactured inexpensively. The probe card includes a base plate, a flexible substrate, and a contact probe. The contact probe is a flexible substrate formed from polyimide resin. The contact probe has a plurality of parallel wires. Each wire has a distal end that functions as a contact. The contact probe is produced by cutting a general purpose substrate having a plurality of parallel wires formed at a predetermined pitch. The number of the parallel wires is equal to the number of pads of an LSI chip.
Patent TW-579456-B (TW)
Title: Substrate treatment device
Inventor: FUKUCHI TAKESHI
IPC: G03F7/16
Filed: 2003-03-26
Granted: 2004-03-11
Abstract: The present invention provides a substrate treatment device which can detect the defect coating of the substrate in the early stage. A carrying stage 3 is installed in the coating unit 14 of the substrate treatment device, it has: a holding plane 30 to carry the rectangular substrate 90; a bridge structure 4 installed above the holding plane 30 about horizontally; a photographing part 23 to take the picture of the surface of substrate 90. A nozzle support part 40 is disposed on the bridge structure 4. It has a slit nozzle to spurt the photoresist, so as to scan the surface of substrate 90 by the slit nozzle, and to coat the photoresist at the same time. When coating the photoresist is terminated, the photographing part 23 takes the picture of the surface of the substrate 90, and transfers the image data to the determination part 24. The determination part 24 proceeds the image recognition process onto the image data, and determines the coating condition depending on whether the substrate 90 generates defect coating such as exposed white spots, etc. or not.
Patent TW-I223194-B (TW)
Title: High performance hybrid processor with configurable execution units
Inventor: WANG ALBERT
IPC: G06F9/38
Filed: 2003-04-04
Granted: 2004-11-01
Abstract: A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.
Patent TW-I276368-B (TW)
Title: Compacting moisture-sensitive organic materials in making an organic light-emitting device
Inventor: GHOSH SYAMAL KUMAR
IPC: C23C14/56
Filed: 2003-05-28
Granted: 2007-03-11
Abstract: A method of compacting moisture-sensitive organic material adaptable for making an organic layer on a structure which will form part of an organic light-emitting device, includes placing such a desiccant material in a powder form inside a die cavity and applying a pressure to such a desiccant powder in the die cavity sufficient to compact into a porous desiccant bed; providing moisture-sensitive organic material in a powder form; and placing such moisture-sensitive organic material inside the die cavity over the porous desiccant bed, and applying sufficient heat to the moisture-sensitive organic material in the die cavity to cause moisture to escape from the moisture-sensitive organic material and be absorbed by the porous desiccant bed, and then applying sufficient pressure to compact the moisture-sensitive organic material into a solid organic pellet.
Patent TW-586996-B (TW)
Title: Wafer transport robot arm
Inventor: CHU FU-TANG
IPC: B25J15/06
Filed: 2003-07-04
Granted: 2004-05-11
Abstract: A wafer transport robot arm including an arm body comprises a wafer-carrying plane, a first vacuum channel and a second vacuum channel. The wafer-carrying plane forms a plurality of first vacuum ports and second vacuum ports. The first vacuum ports are formed at an inner side of the wafer-carrying plane and link to the first vacuum channel. The second vacuum ports are formed at the outer side of the wafer-carrying plane and link to the second vacuum channel. The first vacuum channel and the second vacuum ports do not link together and build up the vacuum individually for sucking a wafer and transferring the wafer.
Patent TW-I253077-B (TW)
Title: Integrated circuit having nonvolatile data storage circuit
Inventor: YOKOZEKI WATARU
IPC: G11C14/00
Filed: 2003-08-14
Granted: 2006-04-11
Abstract: An integrated circuit has a sleep switch, provided between a first power line and a second power line, which is constituted by a transistor of a first threshold voltage, and which becomes non-conducting in a sleep mode, and further has a latch circuit, connected to the second power line, which is constituted by a transistor of a second threshold voltage which is lower than the first threshold voltage, and a ferroelectric capacitor for storing data held in the latch circuit in accordance with the polarization direction of a ferroelectric film thereof. The integrated circuit also comprises a control signal generating circuit which, when returning to an active mode from the sleep mode, generates a plate signal for driving a terminal of the ferroelectric capacitor to generate a voltage in the latch circuit in accordance with the polarization direction, and generates a sleep signal for causing the sleep switch to conduct to thereby activate the latch circuit following the driving of the ferroelectric capacitor.
Patent TW-I220696-B (TW)
Title: Testing device and its operation method of the flat-panel display
Inventor: LIN HSIAO-YI
IPC: G01R31/00
Filed: 2003-09-12
Granted: 2004-09-01
Abstract: A testing device and its operation method of the flat-panel display, the device electrical-couples to the first driving line, image signal source and the shorting bar signal source, and further includes the first pad, n numbers of tester terminals and n numbers of switching elements. In this invention, n numbers of tester terminals electrical-couples to the first pad, and the n is positive integer which is equal and greater than 1. The gate of every switching element electrical-couples to the shorting bar signal source. And the first terminal of every switching element electrical-couples to the image signal source, and the second terminal of every switching element electrical-couples to the one of the n numbers of tester terminals which is corresponding to the second terminal. In this invention, the testing device uses the voltage that is providing by the shorting bar signal source to control the flat-panel display taking the shorting testing or the all terminals testing.
Patent TW-I232554-B (TW)
Title: Information memory element, method of manufacturing same and memory array
Inventor: YAMAGUCHI SHINYA
IPC: H01L27/115
Filed: 2003-11-28
Granted: 2005-05-11
Abstract: The information memory elements, the method of manufacturing the same and the memory array are disclosed, the information memory elements are able to read/write information by means of the mechanical performance of the floating gate layer, wherein the gate insulative film has a cavity (6), and the floating gate layer (5) that has two steady flexure states including a steadily bent state towards the channel side of the transistor and a steadily bent state towards the gate (7) is provided within the cavity (6). The steady flexure states of the floating gate layer (5) is changed by the Coulomb forces of the electron (or the electron hole 8) pre-accumulated in the floating gate layer (5) and the external electric field, and the writing/reading of the information is performed by reading the changed state of the floating gate layer (5) by the channel current.
Patent TW-I246624-B (TW)
Title: Manufacturing method of optoelectronic substrate, manufacturing method of optoelectronic apparatus, and the optoelectronic apparatus
Inventor: YASUKAWA MASAHIRO
IPC: H01L21/84
Filed: 2003-12-19
Granted: 2006-01-01
Abstract: The present invention is related to the manufacturing method of optoelectronic substrate, the manufacturing method of optoelectronic apparatus, and the optoelectronic apparatus. The subject of the invention is to provide a method capable of manufacturing highly reliable optoelectronic substrate with high production rate. In the invented manufacturing method of optoelectronic substrate, a compound substrate formed by bonding the support substrate 210 together with the semiconductor substrate 260 having single crystal silicon layer (semiconductor layer) 226 is manufactured to form the optoelectronic substrate. The invention is featured with containing the following engineering: forming the light-blocking layer 211 on the support substrate 210 from the regulated patterns; forming the insulator layer 212 on the patterned light-blocking layer 211; conducting the oxidization process onto one part of the semiconductor layer 206 to form the oxide layer 226a; and removing the oxide layer 226a to make the thickness of oxide layer 226a smaller than that of the insulator layer 212.
Patent TW-I242744-B (TW)
Title: Apparatus, pipeline microprocessor and method for avoiding deadlock condition and storage media with a program for avoiding deadlock condition
Inventor: MCDONALD THOMAS C
IPC: G06F12/0802
Filed: 2004-01-13
Granted: 2005-11-01
Abstract: An apparatus for avoiding a deadlock condition in a microprocessor with a speculative branch target address cache (BTAC) that predicts a target address of a branch instruction contained in a cache line output by an instruction cache in response to a fetch address is disclosed. The BTAC is incorrectly predicts the branch instruction is wholly contained in the cache line; consequently, the microprocessor fetches from the target address without fetching the next sequential cache line containing the rest of the instruction. An instruction formatter detects the instruction is only partially contained in the cache line and waits for the next cache line. However, the formatter receives no more cache lines because the target address misses in the cache and the missing cache line is not fetched from memory because the processor does not generate speculative instruction fetches. To avoid deadlocking, the apparatus invalidates the BTAC target address and retries.
Patent TW-I278298-B (TW)
Title: Cartridge for the preparation of beverages
Inventor: HALLIDAY ANDREW
IPC: A47J31/44
Filed: 2004-01-27
Granted: 2007-04-11
Abstract: A cartridge (1) containing one or more beverage ingredients (200) and being formed from substantially air- and water-impermeable materials, the cartridge defining a storage chamber (130; 134) containing the one or more beverage ingredients and a manifold chamber (16), the cartridge comprising an opening (12) through which the one or more beverage ingredients can be filled into the storage chamber, the opening being closed by a lid (5) having a first portion overlying the manifold chamber and a second portion overlying the storage chamber, wherein the first portion of the lid is pierceable in use to accommodate an inflow of an aqueous medium into the manifold chamber and the lid is pierceable in use to accommodate an outflow of beverage formed from interaction of the aqueous medium and the one or more beverage ingredients in the storage chamber.
Patent TW-I232809-B (TW)
Title: Functional liquid loading device and liquid drop emission device having the same, and production method for electro-optic device, electro-optic device and electronic equipment
Inventor: TAKANO YUTAKA
IPC: B41J2/01
Filed: 2004-02-13
Granted: 2005-05-21
Abstract: This invention includes a liquid passing device located at the head cap side 102, that passes the functional liquid in a functional liquid tank 231 to pass through a functional liquid drop emission head 31 to communicate with the functional liquid drop emission head 31. A detection means 161 for detecting the functional liquid has reached the head cap 102. A control device 6 stops to drive the passing device based on the result of the detection means 161. The detection means 161 includes: a crystal oscillation unit 301 provided in the head cap 102 or a waste fluid pipe 252, and a detector 303 for detecting existence of the functional liquid based on the changes in the resonance of the crystal vibrating unit 301.
Patent TW-I239480-B (TW)
Title: Input method and control module defined by initial location and moving direction and the electronic product thereof
Inventor: SHEN TZUNG-YI
IPC: G06K11/06
Filed: 2004-03-15
Granted: 2005-09-11
Abstract: An input method defined by initial location and moving direction is provided. A control module identifies the different gestures upon the touch control device. Each of the gestures generates different control signals to provide a main frame for the subsequent control functions. The initial location is set as the location of first touching the touch control device, and a parameter data set is defined for comparing in the control module by matching gestures of different moving directions to the initial location of first touching. Then, it detects whether there is any conformed gesture upon the touch control device. Finally, the gesture that meets initial touching location and matches up the moving direction is compared with the parameter data set defined in the control module, and the result is outputted to the main frame.
Patent TW-I233652-B (TW)
Title: Method for making semiconductor device
Inventor: UMEMOTO MITSUO
IPC: H01L21/44
Filed: 2004-04-02
Granted: 2005-06-01
Abstract: This invention provides a method for making a semiconductor device in which a high reliability of electrical connection between the electrodes and the substrate is assured. A sealing resin (4) is applied to a region of substrate (2) where first electrodes (3) are not formed. A semiconductor chip (6) having second electrodes (7) formed on the end portions of the semiconductor chip (6) is prepared, and is so disposed that a face side of the semiconductor chip (6) faces a face side of the substrate (2). A first movable plate (8a) is lowered to depress the end portions of the semiconductor chip (6) from the back side of the semiconductor chip (6), to press-connect the second electrodes (7) with the first electrodes (3). Thereafter the second movable plate (8b) is lowered to depress a central portion of the semiconductor chip (6) from the back side of the semiconductor chip (6) to fill the space between the substrate (2) and the semiconductor (6) with the sealing resin (4).
Patent TW-I243245-B (TW)
Title: Probe sheet and probe sheet unit using same
Inventor: MACHIDA KAZUMICHI
IPC: G01R1/06
Filed: 2004-04-28
Granted: 2005-11-11
Abstract: It is an object of the present invention to provide a probe sheet capable of achieving correct measurement independently of a dispersion in height of electrodes of measurement objective; and a probe sheet unit using the same. A probe sheet unit A is a sensing section of a measuring instrument (not shown) for a measurement objective B and includes: a base plate 100 mounted to a prober of the instrument; and a probe sheet 200 mounted to a lower surface of the base plate, and the probe sheet 200 includes: a sheet member 210 having a flexibility; and plural probes 220 for measurement provided on one surface of the sheet member 210, wherein a probe 220 has a shape capable of elastic deformation in a direction, upward or downward.
Patent TW-I343117-B (TW)
Title: Stacked chip semiconductor device and method for manufacturing the same
Inventor: ARAI YOSHIYUKI
IPC: H01L25/18
Filed: 2004-06-30
Granted: 2011-06-01
Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.
Patent TW-I259601-B (TW)
Title: Fuel cartridge with connecting valve
Inventor: ADAMS PAUL H
IPC: H01M8/02
Filed: 2004-07-12
Granted: 2006-08-01
Abstract: A shut-off valve or connecting valve capable of connecting a fuel supply to a fuel cell is disclosed. The valve comprises a first valve component and a second valve component. Each valve component has an outer housing and a biased slidable member disposed inside the housing forming an internal seal. During the connection process, the two valve components establish an inter-component seal. Afterward, in one suitable embodiment the slidable member moves inward and opens the internal seal in the valve component to establish a flow path. In another embodiment, the slidable member moves inward and exposes a first filler and the first filler abuts a second filler in the other valve component to establish a flow path. In other embodiments, at least one valve component is sized and dimensioned to limit access to the internal seal.
Patent TW-I266349-B (TW)
Title: Chip protection method in semiconductor packaging process
Inventor: ZENG ZHAO-CHONG
IPC: H01L21/00
Filed: 2004-08-06
Granted: 2006-11-11
Abstract: There is provided a chip protection method in semiconductor packaging process. In accordance with the present invention, a semiconductor wafer formed thereon plural circuit layouts is first provided, and at least one contact solder pad is included to perform under bump metallization (UBM) to the wafer for covering the contact solder pad with a UBM layer. A passivation layer is coated on the surface of the wafer for encapsulating the contact solder pad. Next, the wafer is sawed into plural chip units. Then, a pick and place process is performed to place the chip units into, for example, circuit boards of IC package substrate for being used in the subsequent semiconductor packaging process.
Patent TW-I364464-B (TW)
Title: Method and an apparatus for applying a coating on a substrate
Inventor: BIJKER MARTIN DINANT
IPC: C23C4/12
Filed: 2004-08-11
Granted: 2012-05-21
Abstract: A method and apparatus for applying a coating on a substrate, wherein, opposite the substrate, at least two expanding thermal plasma (ETP) sources are arranged which provide the substrate with a coating, wherein the substrate is located in a process room in which the pressure is lower than the pressure, prevailing in the ETP sources, of a carrier gas which is introduced into the process room via the sources and which forms the expanding plasma, wherein the coating provided by each source has a layer thickness according to a certain deposition profile, for instance a Gaussian deposition profile, and wherein different process parameters are chosen such that, after the coating process, the addition of the deposition profiles results in a substantially uniform layer thickness of the coating on a relevant part of the substrate. Preferably, the distance between sources producing plasma at the same time is chosen and/or settable such that the expanding plasmas substantially do not influence each other.