Patent GB-980728-A (GB)
Title: Improvements in or relating to digital signal detector circuits
IPC: H04L25/49
Filed: 1963-09-30
Abstract: 980,728. Telegraphy. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 30, 1963 [Oct. 8, 1962], No. 38358/63. Heading H4P. In a data transmission system each bit is represented by a negative and a positive excursion from a datum in different half waveform periods. Different bits are indicated by opposite phase waveforms. The invention provides means for deriving from these waveforms the corresponding bits. To do this the received signal is added to the delayed received signal in the same sense, the delay being a half waveform period. The resultant signal provides an indication of one bit whenever the amplitude exceeds a positive threshold, and of the other bit whenever a negative threshold, there being gating means to ensure that only the second half of each bit period can provide an indication. In a first embodiment, Fig. 1 (part shown), received data as Fig. 2A is fed direct, and via a ¢ bit delay and inverter-resulting in Fig. 2B- to adder 21. The resultant signal, Fig. 2C, feeds threshold detectors 24, 25 whose outputs are gated at 26, 27 to " 0 " and " 1 " bit stores. The gating is enabled only during the second half of each bit period. Units 29 ,30, 31 act as a flip-flop having an unstable time of ¥ bit period. Thus during the first bit, unit 25 pulses to provide a " 1 " bit to the store and the flip-flop arrangement is triggered. Hence the output from 24 during the first half of the second bit cannot pass gate 26, preventing erroneous indication of a " 0 " bit. The gates 26, 27 are enabled again, however, by the time the second half of this bit is received-see Fig. 2E-so the second bit is indicated as a " 1 " bit. Each series of bits is separated by a bit period and must start with a " 1 " bit. If a series of bits does not start with a " 1 " bit the series will be decoded incorrectly until a " 1 " bit is detected, whereupon the gating arrangement will lock on to the correct half cycle. In a noisy channel the waveforms may be distorted such that the thresholds are not reached e.g. during the second bit, Fig. 2C<SP>1</SP>, resulting in the gating unit locking on to the wrong half-cycles. Any change in bit will then cause resynchronization to take place, Fig. 2E1. In the case of noise affecting one bit, as in Fig. 2C<SP>1</SP>, there is an erroneous bit indication 1 ¢ bit periods after the last correct indication. In Fig. 3, gate 35 gives an error indication when gate 28 gives pulses at 1¢ bit intervals. This output feeds toggle 29 so that the gating unit is prevented from locking on to the wrong half bits. The error is corrected by means not shown. If adjacent bits are alike, there will be a half cycle (shaded) between the half cycles on which a decision is made. This fact is used in Fig. 4 (not shown) to verify previous decisions or to provide the correct one where the decision is indeterminate. The period of zero amplitude in the adder output when adjacent bits are unlike can also be used for decision, Fig. 5 (not shown). In a final embodiment, Fig. 7 (not shown), the adder output is inverted and fed with a half-bit delay to the adder input, whereby the amplitude of the adder output is partly doubled and the signal/noise ratio increased.