Patent GB-1003641-A (GB)
Title: Computer input-output system
IPC: G06F15/17
Filed: 1962-07-12
Abstract: 1,003,641. Digital computers. SPERRY RAND CORPORATION. July 12, 1962 [Dec. 1, 1961], No. 26872/62. Heading G4A. A data processing system comprises a central digital computer and external data handling and/or processing devices, the computer memory storing " buffer control words " for the various nput/output channels, which words contain the addresses of the memory locations required for storage or read-out in the data transfer operation. General arrangement.-The system described comprises a central computer 10, Fig. 1a having 14 input channels and 14 output channels, two channels of each set being for communication between the central computer and other computers, the remaining channels being for communication with ordinary types of external equipment such as paper tape punches or readers, typewriters, magnetic tape units, magnetic drum units, data transfer taking place over channels 16 by 30-bit words in parallel mode. The data transfer is under the control of " buffer control" (also called " index ") words which are stored in the computer memory and comprise 30 bits, a 15-bit " upper " half word determining the address of the last word to be stored or read out and a 15-bit " lower " half word determining the addres of the first or next word stored or read out, the lower half-word being incremented by unity after each word transfer, the transfer operation being terminated when the two word halves are equal. Operation.-Upon execution by the central computer of an instruction calling for a data transfer, the four bits of the instruction which designate the particular channel are decoded by a translator 142, Fig. 4b, to mark one of 14 lines 144 corresponding to the required channel, thereby setting an associated flip-flop 146-150 or 206-210, Fig. 4c, according as an input or an output transfer is required. For an input data transfer to take place, the external equipment must provide an " input request " signal to the central computer such signals being applied over lines 160-164, Fig. 4d. When an input request signal from one of these input lines is dropped and a signal from one of the flip-flops 146-150 is applied to one-shot circuits 154-158, Fig. 4d, an output signal results which is applied to input request gates 180-184. Similarly, " output request " signals from the external equipment are applied over lines 186-190, Fig. 4d, and, if an " output active " flip-flop 206-210 is set a corresponding one-shot circuit 214-218, Fig. 4d, is rendered active, if the computer has executed an instruction calling for an output data transfer. External interrupt.-A peripheral unit may send an " external interrupt " signal to the computer over lines 220-224, Fig. 4d, together with the reason for this interruption over lines 120-124, Fig. 4c, thereby causing the computer to take its next instruction from a specified memory location. For example, a tape break in a tape unit may require appropriate corrective action. Internal interrupt.-By choice of programme instructions, a data transfer operation may, if desired, be terminated by an " internal interrupt" signal. When such an instruction is executed, an " input monitor " flip-flop 254- 258, Fig. 4a, or an " output monitor " flip-flop 260-264, Fig. 4a, is set. Outputs from the monitor flip-flops 254-264 are connected to " internal interrupt generators " 272-280, 288-292, Fig. 4a, which also receive inputs from the internal and external " active " flipflops 146-150, 206-210, Fig. 4c, the arrangement being such that when an " active " flipflop 146 &c. changes to its inactive state, the generators 272 &c. transmit signals via a cable 284 or 294 to an " internal interrupt " flip-flop 286 or 296. Sub-priority circuits.-The input request oneshot circuits 154-158, output request one-shot circuits 200-204 and external interrupt oneshot circuits 234-258 are connected to respective " interrupt " flip-flops 300, 304, 308, Fig. 4d. Each flip-flop 286, 296, 300, 304, 308 is connected to a sub-priority network 310 (Figs. 17a-17c, not shown), which determines the order in which the various types of request will be honoured, the priority being (1) external interrupt, (2) output internal interrupt, (3) input internal interrupt, (4) output request, (5) input request. When the request to be honoured has been determined an output on a cable 312 is effective to enable the appropriate gates 180- 184 &c. Priority circuits.-These circuits 316, Fig. 4b (and Figs. 18a-18e, not shown), are effective to determine which one of a plurality of requests of the same type will be honoured first, the highest numbered channels having highest priority. Time sharing.-If several input and output requests are presented simultaneously, the input and output word transfers are interlaced by a time-share circuit (not shown), the output word transfer on the highest numbered channel being taken first. Data transfer instructions.-Computer instructions comprise 30 bits as shown in Fig. 3 and include a 6-bit operation (function) part f and a 15-bit operand part y. In an input or output data transfer instruction a 4-bit part j<SP>*</SP> determines the particular external equipment concerned, and when such an instruction is executed a 30-bit buffer control word is read out from the address in the core memory 386 determined by the y part of the instruction, and read back into a buffer control register (not shown) in the memory. The priority network 316 develops the address of the particular channel to be honoured first in the event of multiple requests, and this address is transmitted to the S-register 326 where, if an output transfer is being honoured, the data word at the address contained in the S-register is read out for transmission to the peripheral device concerned via the memory access Z-register 134 and Coregister 344. If an input transfer is being honoured, the channel address from the priority network 316 is transmitted via OR gates 140 to the translator 142 to provide an output which passes via a cable 144 to enable input amplifiers 126-130 to transmit data from the external equipment to the memory access Z-register 134. In an output transfer, a signal from the translator 142 is effective to set a flip-flop in the group 354, Fig. 4c, indicative of the particular equipment to receive data, thereby notifying that equipment that data is available in the computer output register Co, Fig. 4a. In an input operation, an " acknowledge " gate 370 corresponding to the honoured channel is set to send an " acknowledge" signal to the peripheral device which transmitted the last data word received by the central computer. Each time that a word is entered or read from the memory 386, the lower half of the buffer control word is incremented by unity at 328, the transfer operation being terminated when the two halves of the control word are equal as detected by a comparator 388, thereby resetting the active channel flip-flop 146-150, 206-210, Fig. 4c. External interrupt request.-In an external interrupt operation, the channel address generated by the priority network 316 is temporarily stored in a register 325 and then transferred to the S-register 326. The computer programme then accesses the jump instruction at this address and executes the required interrupt subroutine such as a corrective sub-routine. Data transfer between computers.-When data is to be transferred between two computers, the receiving computer executes an " input buffer " instruction, the transmitting computer testing whether such an instruction has been executed. The transmitting computer then transmits as its first word a buffer control word for the receiving computer, the lower half of this word determining the initial storage address and the upper half determining the final storage address. The output buffer mode is then initiated in the transmitting computer by the execution of an appropriate instruction. Assuming that the transmitting computer is connected to channel 0 of the receiving computer, data is placed on cable 120, Fig. 4c. The transmitting computer then sets its " ready " flip-flop 396, Fig. 4e, to generate a " ready " signal which becomes an input request for channel 0 of the receiving computer and is processed by the sub-priority and priority networks of the receiving computer. Assuming there are no requests of higher priority, the priority network 316 develops an address for channel 0 which is decoded by the translator 142 whose output gates the 30-bit data word to be received from the cable 120 via gates 126 to the memory access register 134, the word then being stored at a memory address specified by the buffer control word. The receiving computer then sets the input acknowledge line for channel 0, the resulting signal passing via amplifier 374, Fig. 4c, as a " resume " signal for the transmitting computer. Time sharing with inter-computer transfer.-If a computer is communicating with two other computers simultaneously, a " working register " 400, Fig. 4e, is effective as a time-share circuit. Thus, if a computer A is simultaneously transmitting to computers B and C, the working register 400, which comprises two flip-flop stages, controls time-sharing between the two transmission channels by alternating data transmissions between computers B and C. A gate 404, Fig. 4e, is provided to give intercomputer transfer lower priority than other transfers, this gate being enabled only when no other transfer is being requested, to set a flip-flop 418 in the sub-priority network, causing transmission of the intercomputer transfer request to the priority network 316 which generates the channel address for transmission to the storage address register 326. The buffer control word thereby addressed is read out from the memory and employed to access the data word to be transmitted, this word being applied to a 30-bit output register 426, Fig. 4b. The output data word is transmitted to both external