Patent GB-1054785-A (GB)
IPC: H04Q3/54
Abstract: 1,054,785. Automatic exchange systems. SIEMENS & HALSKE A.G. Aug. 13, 1963 [Aug. 13, 1962], No. 31942/63. Heading H4K. A telecommunication system comprises a store comprising a plurality of storage cells arranged to be sampled cyclically. The cells are arranged in groups relating to different functions. When a sampling of a cell in one group indicates that information has to be stored in cells of another group the sampling causes the storage of relevant information in an order store. When subsequently cells of the other group are sampled and an empty cell in that group is found the information stored in the order store is transferred thereto. In the arrangement described, one cell group relates to sampling the loop condition of the line, another cell group is used for storage of the busy condition of the line and further cell groups are used for timing the duration of loop makes and breaks and storage of digit counts. The arrangement may also be used for counting out digits on retransmission. Each subscriber or incoming exchange line has a device such as a core or relay contact 4BT for indicating the loop condition, and a core T4BS for indicating the free or engaged condition of the line. Corresponding cores in these two groups are scanned simultaneously using an address generator 4AS and control circuits 4TT, 4TS. When a newly off-hook subscriber is scanned, gates 4K1 ... 4K5 are opened to pass the address of the subscriber to sections 56 . . . 60 of store 4P, and a 1 is written into the corresponding cell T4BS. On subsequent scannings the output from the latter inhibits 4G7 to prevent further registration in 4P. After all cells 4TT, T4BS have been sampled the stores W4BS are sampled. When a section not containing a subscriber's address in portions 21 . . . 25 is encountered, gates 4G1 ... 4G5 are opened to pass the subscriber's address thereto from 4P. Thereafter on repeated samplings of this section the address is read out to the control circuits 4TT, 4TS the former testing the loop condition of the line. When an open loop is detected inverter 4I passes a pulse to adding circuit 4N which adds 1 to the count stored in sections 7 ... 10 of the appropriate section of W4BS and restores the answer therein. The number of scans is used to time the break interval. When this count reaches any of the values 4 . . . 7 the next closure of the loop opens K20 to pass a pulse to the adder 4D and 4N (and consequently portions 7 ... 10 of the store) is zeroized. 4D stores the count in portions 27 . . .31 of the section in question for use in the adder when the next dial pulse is to be counted and so on. A further counter 4V (whose circuitry is not shown) times the interval between dial pulses. When all the dial pulses have been received, counter 4V puts a 1 in portion 36 to indicate this fact. If the count of 4N exceeds eight, this indicates termination of the connection and K29 pulses 4TS to cause a O to be written in the T4BS cell and deletion of all information in the appropriate section of W4BS. Assuming now that the dialled digit is stored in portions 27... 31 of W4BS, when the'section is next scanned, the output from portion 36 opens gates 4K7 ... 4K11 to pass the section address to a free section of store 4H. When the setting control unit is free and during a pause in the scanning of 4AS scanner 4AH causes sampling of the sections of 4H and the stored section address is read out to 4TS, which thereupon reads out the dial pulse count in portions 27 ... 31 to the setting control circuit 4E. Successive digits are thus collected by 4E. If the first digit indicates an outgoing connection, the setting control circuit establishes a connection to an outgoing exchange line whose identity is then fed back to portions 33... 36 of W4BS. When the next digit has been received and stored and when the section is next scanned, the presence of the exchange line identity causes the section address to be passed to sections 51 ... 55 of 4P (rather than to store 4H). When sections of A4BS are sampled, and a free section is found, gates 4G9...4G13 are unblocked and the information in 4P (51 . . . 55) is passed to control circuit 4TS to cause the address generator 4AS to be stopped and the information in the section of W4BS to be passed to the free section in A4BS. The transferred information is the address of the exchange line (33 . . . 35) and the dial pulse count (27... 31). When the section in A4BS is subsequently scanned the exchange line address is fed to 4TA and a pulse via 4M10 is applied to the read-in circuit 67 and also whilst a dial pulse count exists in A4BS a pulse is applied to adder 4L. This continues for four scannings after which gate 4K18 cuts-off the pulses to circuit 67, counting being effected with the aid of portions 2 ... 5 of A4BS. The pulses delivered to the exchange line circuit are integrated by a trigger circuit or slow-releasing relay which delivers a pulse to the outgoing exchange line. The counter 4L then counts a further three samplings, after which the count in 4D (and portions 21.. 25 of A4BS) is reduced by 1. The counter 4L is now reset and the next dialled impulse is sent in the same way and so on until portions 27 ... 31 of A4BS are empty, whereupon 4K17 causes cessation of pulses sent to 67. The exchange line address in portions 33... 35 is then deleted by means not shown. Timing diagrams are given for the durations of the scannings of the various circuits which ensure no confusion between the insertion and collection of the information from the various stores.