Patent GB-1140103-A (GB)
Title: A bistable flip-flop
IPC: H03K19/173
Filed: 1966-05-31
Abstract: 1,140,103. Bistable flip-flop for use in digital computers. SCIENTIFIC DATA SYSTEMS Inc. 31 May, 1966 [1 June, 1965], No. 24255/66. Heading G4C. [Also in Division H3] A bistable flip-flop having set and reset states and comprising a master portion having two output circuits connected to a slave portion, the two output circuits consisting of two coincidence circuits each being responsive to a clock signal alternating between first and second states and each being responsive to input signals that when either flip-flop state exists the corresponding coincidence circuit provides a clock dependent output and the other coincidence provides a clock independent output, and when one flipflop state exists and an input signal for switching the flip-flop to its other state is recieved during a first clock state the coincidence circuit corresponding to the existing flip-flop state is rendered clock-independent, thereby preventing the output thereof from changing when the clock signal changes state and thereby establishing the other flip-flop state when the clock signal changes state, the slave portion comprising two gates connected to receive the outputs of the coincidence circuits respectively and each cross-coupled. Absence of erase signal (E = 0).-In the unit shown in Fig. 2 GSR, GE, GR, GS and GQ are AND gates N2, N3, N4, N5, NR and NS are NOR gates I1, I2, I3 and N1. are inverters and A stands for amplifier. Assuming E = 0 causes AND gates GE and GQ to be enabled. The master flip-flop is set or reset when the clock pulse changes from a true state to a false state. If this has occured, the Boolean equation for GS is while the clock pulse C is false i.e. gates GR, GS are enabled. Thus regardless of the value of S or R, GS remains unaltered and hence so does GR. During the following true clock pulse states AND gates GR, GS are both inhibited, however, the slave flip-flop maintains the state previously maintained by the master flip-flop. At the next change of state of the clock pulses from true to false the equations apply i.e. if a set signal S occurs regardless of the presence of a reset R signal GS is enabled and GR inhibited. If only a reset signal is present GR is enabled regardless of the previous value of the flip-flop. If neither set nor reset pulses occur then the master flip-flop returns to its previous state i.e. if #Q=l then GR is enabled, if #Q = 0 then GS is enabled. Presence of erase signal (E = 1) .-If an erase signal is applied AND gates GE and GO are inhibited. GR will be enabled on the change over from a true clock pulse to a false clock pulse and GO will be inhibited to render Q = 0. The feed-back paths will maintain appropriate signals at the other gates GS, NR. The gates are provided by transistor circuits (Fig. 3, not shown) the amplifier being a common base amplifier, the inverter being a common emitter amplifier, the NOR gate being formed from two inverters having their collectors coupled and their emitters coupled to form parallel collector-emitter paths, and the AND gates being formed by connecting together the outputs from the previous gates. A circuit is described (Fig. 4, not shown), for converting voltage levels in different portions of a data processing machine using the flip-flops to feed various logic circuits and being controlled by counter and further flip-flops to perform processing operations.