Patent GB-1334234-A (GB)
Title: Multiplexing
IPC: H03K19/0175
Filed: 1970-11-17
Abstract: 1334234 Digital transmission; multiplexing GENERAL INSTRUMENT MICROELECTRONICS Ltd 17 Nov 1970 [9 Feb 1970] 6166/70 Heading H4P In an integrated circuit arrangement for multiplexing n digital data channels on to a lesser number m conductors, a plurality of pulse trains for switching the channels are generated within the integrated circuit(s) which are derived from a lesser number of input clock pulse trains. The plurality of pulse trains may be generated by a shift register or a counter-decoder arrangement. In a bi-directional system having a separate synchronizing line 18, integrated circuits on master chip 1 and slave chip 2 which may be mode p-channel insulated gate field effect devices (MIS) having for example circuits 3-6 connected through MIS devices 1-3 and 5-7 to a line L7 via inverting device 12, 13. Data is transmitted by switching the MIS devices cyclically at a frequency greater than the data rate by clock pulses #1 generated at 16, 17. Phase displaced pulses #2 of the same frequency may also be generated. Generators 16, 17 each comprising a two-bit shift register 19, 20 and decoder 21, 22 which may be constructed of NAND gates, having outputs 1'8 providing phase displaced pulse trains defining time slots of quarter clock frequency, slots 1-3 and 5-7 switching devices of the same numeral. Slot 4 (8) disables device 12 (13) to permit subsequent transmission to 4 (5); slot 8 synchronizes operation of chips 1, 2 as data is not transmitted in this slot. In slots 1-3 therefore transmission is from 3 to 5, the circuit being switched in slot 4 and transmission is from 6 to 4 in slots 5-7. Synchronization is achieved by receipt of the slot 8 pulses by OR gate 25 feeding a NOR 26 also receiving a feedback signal from counter 20. If counters 19, 20 are in synchronism output of OR 25 = 0 which maintains NOR 26 open for continuous operation of counter 20. If counters 19, 20 are not in synchronism OR 25 = 1 hence NOR 26 = 0 hence counter 26 counts to eight and stops until counter 19 reaches 8 when counter 20 is released. Fig. 2 (not shown) illustrates a simplified arrangement for uni-directional data flow where synchronization is achieved in slot 8 through an inverter (23). Fig. 3 (also not shown) is similar arrangement to Fig. 2, allowing bi-directional data flow via the data line L7. As the switching rate is greater than the data rate any one slot may include like bits i.e. "1, 1" or "0, 0" hence the sync. signal in slot 8 may be 10101 obtained by dividing by two, one of the outputs other than output 8, of counter 19 or decoder 21. Selective output e.g. D is divided by two at (30) fed to NOR (31) together with (8) inverted at (23) to produce a sync. signal S = 1 in slots 1-7 which isolates L7 from the sync. generator. Exclusive OR (25) receives sync. signals from line also D ¸ 2 from counter 20, the outputs from ex. OR (25), inverted at (27) feeding gate (28) also receiving slot 8 signals the output from which is passed through an isolating device (29) to gate (26). The time slot signals may also be generated by shift registers. In Fig. 5 (not shown) a seven stage master register (33) is controlled by pulses #1, #2. Signals from shift register (33) feed through NOR gate (35) and isolating stage (36) to the register input, double clock frequency being required. Receiver shift register (34) is similar to be synchronized by supplying a bit 8 or #8 to (37) in slot 8.