Patent GB-1278694-A (GB)
Title: Improvements in or relating to apparatus for testing electronic circuits
Inventor: DAVIS DAVID CEMER
IPC: G01R31/3193
Filed: 1969-07-04
Abstract: 1278694 Testing digital circuits SPERRY RAND CORP 4 July 1969 33827/69 Heading G1U [Also in Division G3] A digital circuit 20, Fig.1 having a plurality of inputs and outputs is tested by applying (31) a set of input bits to the circuit on occurrence of STROBE 1 pulse, sensing the circuit outputs on occurrence of a STROBE 2 pulse, which is delayed with respect to the STROBE 1 pulse, by checking the output voltages against a reference level in an evaluator 37, and sequentially comparing (39) each output bit with the corresponding expected output bit. A NO GO indicator 43 is actuated if there is any discrepancy due to an output of the circuit 20 (i) having a wrong binary value, or (ii) not rising to the proper binary value within the time set by the delay between the two STROBE pulses. If this first test is satisfactory, a second similar test is made with a longer delay between the two STROBE pulses, and it is stated that this second test checks the fall times of the voltages at the circuit outputs. These two tests make up a complete test cycle which may then be automatically repeated for another set of input bits. Establishing the Test Conditions and Input Signals. Circuit components for establishing '0' and '1' reference voltage levels, selecting one of a number of available clock pulse frequencies (107), Fig. 3, and providing connection to, and load impedances for, the circuit under test are carried by switch-selectable or plug-in circuit boards 32. The remaining information required for carrying out each test cycle is stored on a magnetic drum 19 in the form of three successive 25-bit words. The address of the three words of the first test cycle is entered manually on switches 27, and drum position and channel selectors 23, 25 then select the required words and read them into respective registers 100, 141 both Fig.2 (not shown) and 221 Fig.4. The bits of WORD 2 determine the set of binary signals to be applied to the inputs of the circuit under test, and those of WORD 3 represent the expected binary output signals. The bits of WORD 1 are used to set up required test conditions as follows: bits 1-6 set an initial value in counter 102, Fig.3, which is stepped on by clock pulses (107) as the test proceeds, the counter outputs 105A-F providing synchronizing pulses, e.g. for the STROBE 1 and 2 pulses; bits 7-12 determine the basic delay (113) between the two STROBE pulses; bits 13-18 select certain monostables (115) to determine the duration of the STROBE and other pulses; bits 19-24 are for miscellaneous functions. After the three words have been read into their registers a STROBE 1 pulse is generated at a time determined by counter 102, and this STROBE pulse operates gates 145 so that the bits of WORD 2 cause level selectors 143 to apply '1' and '0' signals to the inputs of the circuit under test. Examining the Output Signals. Each output bit of the circuit under test is passed to a corresponding evaluate circuit, Fig.5, which has provision for comparing the output bit with two reference levels, viz the highest acceptable level for binary '0' (205), and the lowest acceptable level for binary '1' (203). In any test only of the reference level comparators 203, 205 will be operative, as determined by flip-flop 207 set by bits 20, 21 of WORD 1. Whichever reference level comparator is selected, a binary '1' is produced at the output of inverter 213 if the output signal level from the circuit under test is acceptable for that particular reference. The output of inverter 213 is sampled on occurrence of the STROBE 2 pulse, and if the circuit output and selected reference agree a pulse is supplied to a flip-flop 217 which has been set initially by flip-flop 207 in accordance with the particular reference selected. The output of flip-flop 217 is applied to an associated stage of a test result 201, Fig.4. The bits in the test result and correct result registers 201, 221 are compared sequentially, and pulses are supplied to a counter 227 so long as corresponding bits agree. If there is a disagreement the sequential comparison is stopped, gates 229 opened to show the count number on indicator 231, and flip-flop 233 switched to light a NO GO lamp. If there is no disagreement, the counter 227 overflows on the last bit to set flipflop 235 and light a GO lamp. Maintaining a Succession of Tests. After completion of the first test in each test cycle, flipflop 235, Fig. 4, switches counter 237 to provide a signal to gate 139, Fig. 3, for changing the delay between the two STROBE pulses for the second test, and the whole procedure is repeated. After both of the tests which make up a test cycle have been completed, counter 237 provides an UP DATE signal, which causes the drum position and channel selectors 23, 25, Fig.1, to select the next group of three words from the magnetic drum 19. The final of a series of tests is indicated by bit 24 of WORD 1 thereof.