Patent GB-1115553-A (GB)
Title: Improvements in or relating to encoder/decoder systems
IPC: H04L1/00
Filed: 1966-03-04
Abstract: 1,115,553. Error correcting decoders. CODEX CORPORATION. 4 March, 1966 [10 March, 1965], No. 9530/66. Heading G4A. In a burst error correcting decoder for a linear code wherein the decoder comprises a syndrome device for checking the status or parity of the coding constraints in the received digits, a logic device for inspecting the syndrome, and a corrector device responsive to said logic device to correct errors in the received digits, said decoder is characterized in that said logic device is adapted to locate an error burst in accordance with a probabilistic determination and to correct most bursts in a predetermined range of lengths longer than the maximum guaranteed correctable error burst length of said code, said logic device comprising an insepction circuit connected to inspect said syndrome for the occurrence of a predetermined condition or one of a set of conditions confined to a minor portion of the length of the syndrome, said corrector device being connected to make corrections in response to the detection of such condition based on the assumption that a burst is confined to a definite region of the received digits determined by the location of said detected syndromes, said region having a length greater than the maximum guranteed correctable error burst length defined by the code. In the arrangement shown (Fig. 4) for a linear convolutional code, information digits from an input channel are directed into an information shift register 10a and the check digits are directed to a sum modulo-2 adder 25 the other input of which receives the output from a further sum modulo-2 adder 12a which is connected to individual storage locations of register 10a in such a way as to recalculate the original check digit. If the original and recalculated check digits agree, a binary 0 is transmitted to the syndrome shift register 24; if they disagree, the transmitted signal is binary 1. A threshold decision device 42 receives signals from the indicated positions of the register 24<SP>1</SP> and generates a correction signal for the digit at 3N + 5 position in register 10a if three or four of its inputs equal binary 1. Line 46 allows for correction of the syndrome digits. This is called the diffuse threshold decoding mode. If an error burst longer than 2N digits occurs the burst indicator 48 operates to open switch A and close switch B whereby the decoder is transferred to the burst mode of operation. In this mode, the correction digit is applied to a sum modulo-2 adder 26a. The check digit input to adder 25 could alternatively be directed to adder 12a and adder 25 dispensed with. The detection of burst conditions longer than 2N digits is achieved by means of a circuit (Fig. 6, not shown) including two counters operating in leap-frog manner and keeping track of the two most recent occurrences of ones on leads Z or Y from the threshold device 42 and the end of the syndrome register 24<SP>1</SP>. Each counter is started by an apparent error and increased by one for each successive pair of digits received by the decoder and reset on reaching a predetermined count (3n + 4). The burst mode is turned on whenever a counter exceeds a predetermined threshold (n + 1) and a further pulse is received on lead Z or Y. A number of modified arrangements are disclosed, a simpler decoder being illustrated in Fig. 3 (not shown) but equivalent to Fig. 4 in its burst mode, a diffuse convolutional decoder only being illustrated in Fig. 5 (not shown) equivalent to Fig. 4 in its diffuse operating mode and a decoder (Fig. 8, not shown) for a code having a rate of <SP>2</SP>/ 3  (as opposed to the ¢ rate in the other embodiments). A circuit diagram (Fig. 7, not shown) illustrates a counter circuit for use in the counters of Fig. 6 (not shown) and comprising flip-flops 50, NAND-gates 52 and AND gates 53. A signal on lead T indicates a count of 10 whereas a signal on lead L2 indicates a count of two or less.