Patent GB-1537340-A (GB)
Title: Signal separating apparatus
IPC: G06V30/10
Filed: 1976-06-23
Abstract: 1537340 Character recognition INTERNATIONAL BUSINESS MACHINES CORP 23 June 1976 [9 July 1975] 26113/76 Heading G4R From the output signal 131 (Fig. 1, not shown) from character recognition circuitry (130) which represents the pattern scanned by an optical reader (100), and pattern edge signals (401, 405, Fig. 2, not shown) which identify scan signals representing the edge of a character, a composition unit (600) derives a single output signal for each pattern. As described the optical reader comprises an array of photodiodes (which may be in a hand held wand), the outputs of which are connected via video circuits to the character recognition circuitry (130). Left and right sense circuitry.-(Fig. 4, not shown). Vertical discrimination unit (420) detects a horizontal stripe indicating an inter line gap so that left and right gap logic (430, 435) is restricted to a single line of data. If left horizontal logic (410) or right horizontal logic (415) detects a character left or right edge respectively, a corresponding latch (430, 435) is set resulting in a further latch (461, 466) being set to deliver a LS (401) or RS signal (405) respectively if minimum character requirement logic (440) detects a character or if character recognition detector (450) produces the recognition signal (451). The right hand latch (466) is also set when the right hand side of the character 4 is detected. Direction detector (Fig. 5, not shown).-Each stage of shift register (510) has three elements storing left sense signals (401), right sense signals (405) and an inverted form of the recognition signal (451) from the character recognition detector (which consequently represents a reject character). A latch (521) is set when signal (451) stored in stage (514) of the shift register is zero and the signal (401) stored in either of stage (513, 514) is one. Consequently if the signal (405) stored in a subsequent stage (515) is one, a latch (520) is set to generate a LR signal (501). Similarly if a signal (401) is stored in stage (515) followed by a signal (401) in stages (513, 514) a latch (536) is set to generate a RL signal (502). LR latch (521) and the corresponding RL latch is reset by each end of packet signal (544) (when none of the shift register stages have a signal) and latches (526, 536) are reset by each end of line signal (derived when a predetermined number of consecutive rejects are counted by the counter (551)). Composition unit (Fig. 6, not shown).-A latch (631) holds the current character recognition signal (131) which is compared with the next signal in comparator (633), at comparison (or if the character in latch (631) is a reject character, detected by a detector (632)), an AND gate (635) being enabled to permit the new signal (131) to be stored in the latch. Otherwise, if the current and next character signals differ, an AND gate (637) is enabled for a predetermined "conflict" signal to be stored. The LS and RS signals (401, 405) are combined ingatinglogic (620) with the LR and the RL signal (502, 501) to provide an end of character signal (621) which is used to load the output signal (201) from latch (631) into an output device (140, Fig. 1, not shown). Programming may be included in the output device to reverse signals derived from scanning backwards across the print line.