Patent GB-853614-A (GB)
Title: Improvements in or relating to electrical digital-data-storage apparatus
Inventor: CHAIMOWICZ ADAM
IPC: H03K23/76
Filed: 1956-04-06
Abstract: 853,614. Electric digital-data-storage apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd. March 15, 1957 [Apxil 6, 1956], No. 10564/56. Class 106 (1). Electric digital-data-storage apparatus includes a plurality of bi-stable storage devices arranged in rows and columns, a signal transfer circuit associated with each column of storage devices and adapted to be operated by read-out signals from any device of that column, each signal transfer circuit being adapted to apply read-in signals to all the storage devices of at least one column other than that with which the circuit is associated, means adapted to generate read-out signals from a selected row of storage devices, and means adapted to select a row of storage devices to be set by read-in signals generated by the signal transfer circuits in response to the read-out signals. In a first embodiment a matrix of saturable cores Aa, Ab, Ba ... &c. is adapted to be scanned row-by-row under the control of a selector circuit 33. Reading-out arrangements. The rows of A, B, C ... &c. are threaded by common windings 1, 2, 3 ... &c. respectively, which are subjected, in turn, to a current pulse of a magnitude sufficient to drive a core in the " set " state. (representing binary " one ") back to its " reset " state (binary " zero "). When such an event occurs, say in column b, an output pulse is set up ir line 7 which via a transformer 9 raises the grid potential of a cathode-follower 10. The positive output pulse from the cathode of valve 10 passes a diode 25 and charges up a capacitor 13 connected to the grid of a second cathode follower 12. The positive signal appearing at the cathode of valve 12, which is held as long as the capacitor 13 remains charged, serves to open a set of four AND gates 14, 39, 41 and 15, each having a second input coming from a control circuit 38. Thus, a pulse delivered on line 18 to the opened gate 14 passes via a buffer diode 43 to the grid of a valve 11 whose anode circuit is transformer coupled with a conductor 5 serving the same column b from which the output pulse was received. The pulse in conductor 5 is arranged to have a magnitude of half the current necessary to set a storage core, and occurs at the same time as a secondary pulse of the same sense and magnitude on one of the selector windings 1, 2, 3 ... etc.; thus, the core which is subjected to both magnetizing currents will be changed to the " set " state. This would normally be the core from which the read-out pulse was obtained, but could be another core in that column. Shifting to left or right. If the control circuit 38 supplies a pulse on line 40 while the gate 39 is held open by the valve 12, a signal passes via a buffer diode 43a to the input valve 11a associated with column a of the matric. Thus, information from column b is transferred to column a, and since all the columns have circuits equivalent to column b (including valves 10-12 and gates 14, 39, 41-15, &c.) a pattern of information from a plurality of columns can be shifted step-by-step towards the left. Gate 41 at the cathode of valve 12 enables the same sort of shift to be made towards the right. Output. The gate 15 provides an outlet for information to a utilization device 28. When the information signal which raised the grid voltage of valve 12 and opened the gates 14, 39, 41, 15 has been utilized in one or more of the ways described above, a negative pulse on line 19, acting via a capacitor 20 and diode 21, serves to discharge the capacitor 13 thus cutting off the valve 12 and closing the gates 14, 39, 41, 15, before the next read-out pulse from the selector circuit 33. Input arrangements. When information is to be entered in a core or cores of the row selected by a secondary pulse (see above) a positive pulse appears from control circuit 38 on the lines 16 associated with each appropriate column. As shown, the capacitor 13 is charged via a diode 17 and the cathode follower 12 opens the gate 14 &c. as before to allow a pulse on line 18 to pass to the grid of triode 11 for entry as described above. Since reading and writing do not take place simultaneously, the windings 5 and 7 could be replaced by a single winding. In another embodiment (Fig. 3, not shown) single cores with associated circuits 8 ... 15 &c. are paired and cross-connected to form binary trigger elements which are arranged in cascade so as to form a binary counting chain. Instead of separate cores a perforated ferrite sheet may be used, or a ferro-electric storage matrix or valve or transistor trigger circuits could be employed.