Patent GB-949947-A (GB)
Title: Binary-decimal converter
IPC: H03M7/12
Filed: 1960-10-26
Abstract: 949,947. Binary-decimal converters. LICENTIA PATENT - VERWALTUNGS-G. m. b. H. Oct. 26,1960 [Oct. 27,1959], No. 36753/60. Heading G4A. A binary-decimal converter operating by doubling the highest order bit, adding the next order bit and doubling, and so on,the doubling being performed in a shift register, is characterized in that, if the doubling will lead to a number greater than nine,five is subtracted from the number to be doubled and a carry entered into a store representing the next higher decimal digit. The binary number is set up on the switches I - a known parallel to serial converter is also described-and the ring R is stepped by pulses f 1  which are also applied to shift registers E, Z and H. These registers each comprise storage S o  to S 3  and intermediate stores ZS o  to ZS 3 . The stepping pulses t 1  cause potentials representing the state of successive switches I to appear as successive inputs to flip-flop S o  of register E. Intermediate pulses t 2  transfer the state of the flip-flops S to the stores ZS. The flip-flops S o  to S 3  represent respectively the decimal numbers 1,2,4,8. The stores ZS have inputs e o  to e 3  to a subtraction matrix e.g. E<SP>1</SP> and if these inputs represent a number less than five,the state of the inputs e is reproduced on outputs a 1 ,a 2  and a 3  of the matrix; if the inputs represent a number greater than four, five is subtracted in the matrix and the output u to the "1" flip-flop S o  of the next register Z or H is marked. For the setting of switches I shown, the first t 1  pulse to set S o  in E will be that passed by switch r 6 . The next t 2  pulse will set ZS o  and mark input e o . Since this only represents the value 1,a 1  will also be marked and the next t 1  pulse will set S 1  as well as S o  (r 5  is closed). The store E now holds the value 3. The next t 2  pulse transfers this value to the stores ZS o  and ZS 1  and the lines a 1  and a 2  will be marked. The following t 1  pulse sets S 2  and S 1  but leaves S o  unset since switch r 4  is open. The value 6 is now stored. At the next t 2  pulse this is transferred to the stores ZS 1  and ZS 2 . The inputs e 2  and e 1  to the subtraction matrix are marked but in this case the output a 1  and the interstage carry u are marked and as a result the next t 1  pulses sets flip-flop S 1  of store E and flip-flop S o  of store Z, besides flip-flop S o  of E as switch r 3  is closed. The process continues until the last pulse of the ring cycle gates the settings of flip-flops S o  to S 3  to flip-flops AS o  to AS 3  respectively and the binary coded decimal numbers are translated to pure decimal in matrices E<SP>111</SP> ,  Z<SP>111</SP> and H<SP>111</SP>. The result may be displayed by successive energizations of a multi-cathode tube having cathodes in the shape of decimal numbers. Fig. 4 shows a subtraction matrix: if the inputs e 0  to e 3  represent a number less than five the and circuits formed by the diodes connecting the outputs of flip-flops N 0  to N 3  to the conductors 10. . 23 pass the input unchanged as outputs a 1  to a 3 ; otherwise five is subtracted, e. g. marking of lines e 0  to e 3  causes circuit &<SP>1</SP> to operate and set flip-flop N 3 . N 0  to N 2  are set directly and the result is that conductor 21 and thus a 2  is marked together with u.