Patent GB-1256371-A (GB)
Title: Scrambling arrangement for sampled-data time-allocation communication systems
IPC: H04L9/00
Filed: 1968-12-13
Abstract: 1,256,371. Multiplex pulse code signalling; TASI systems. SOC ITALIANA TELECOMUNICAZIONI SIEMENS S.p.A. 13 Dec., 1968 [14 Dec., 1967], No. 59429/68. Headings H4L and H4R. In a system for providing secrecy in a time division multiplex system of the type in which the number of available channels per frame is less than the number of subscriber lines, only coded samples from the active lines being included in each frame and a channel distribution signal being sent at the start of each frame, means are provided for varying the time position of the samples in each frame in a pseudorandom manner in dependence upon signals transmitted in predetermined channels of the preceding frame and noise signals in digital form are introduced into unused channels in a frame. General arrangement, Fig. 1.-A scrambling circuit CM receives pulses b, corresponding to the channel time slots, Fig. 5, from the transmission system TS and a pulse As corresponding to the period of the channel distribution signal (generated at TS in known manner) whereby the distribution signal appearing on the transmission line c<SP>1</SP> is selected and supplied to the scrambler CM. A circuit Mec tests the contents of the first three channels of a frame (twentyfour bits) stores the resulting signal and transfers it to CM in the following frame where it is used to modify the distribution signal, the modified signal b<SP>1</SP> being supplied to TS to control the transmission of signals on the active lines. The signal samples from TS are supplied to a coder Cod whose output is supplied to the line c<SP>1</SP> via an insertion circuit In and the distribution signal Ms and supervisory signals Sn are also supplied via circuit In to the line. At the receiver, Fig. 2 (not shown), the reverse takes place, similar circuits CM and Mec being used. A noise generator Ng, Fig. 1, is coupled via an AND gate Ag to circuit In, the remaining inputs to the AND gate being a signal As, so that is only operative when the distribution signal is not being transmitted, and the output of an OR gate OC 1 . The OR gate receives a signal 61  from TS so that it only passes a signal when there is an unused channel, and also receives the output of a bi-stable Bn which is set by a signal fd at the end of a distribution signal period and reset by a synchronizing signal Si at the end of each frame. Details of circuits CM and Mec, Fig. 3.-As described, the system allows for 48 channels. The circuit CM is connected to the transmission line c<SP>1</SP> via an AND gate At controlled by pulse As, a counter counting up to 24 and providing an output 1 to 24 according to the number of bits in the distribution signal. This output is supplied to a logic circuit RC which produces outputs in the following manner. Any one of inputs 1 to 24 produces output U24, any one -of inputs 2 to 24 produces output U23 ... any one of inputs 23 or 24 produces output U2 and input 24 produces output U1. Thus a count of 7, signifying that there are seven active lines, produces seven outputs U18 to U24. Each of these outputs is supplied via AND gates A1 to A24 and OR gates OI1 to OI24 to set the respective bi-stables B1 to B24 of a shift register. The circuit Mec includes bi-stables BI1 to BI24 which via AND gates Ac1 to Ac24 store the twenty-four bits contained in the first three channels following the termination of signal As, the outputs of the bistables being supplied via AND gates AI1 to AI24 to reset the bi-stables BI1 to BI24. In operation, the bi-stables B1 to B24 are first set by pulse S via OR gates OI1 to OI24 and then reset in accordance with the signal stored in bi-stables BI1 to BI24 by pulse R via the corresponding AND gates AI1 to AI24. Pulse P via AND gates A1 to A24 then sets bi-stables B24, B23 &c. in correspondence with the number of bits counted at Co, this ensuring that the signal b<SP>1</SP> will contain a number of pulses at least equal to the number of signal samples to be transmitted in a frame. At this time pulse P causes a new signal to be stored by bi-stables BI1 to BI24. Every ten pulses P a pulse P10 sets all the bi-stables B1 to B24 in order to avoid errors which may arise at the receiving end. The signal stored in the shift register B1 to B24 is read out by pulses b via gate Au and fed as signal b<SP>1</SP> to the unit TS or the corresponding unit at the receiver, the inverse signal b1 controlling the insertion of noise signals into the vacant time slots. In the example shown in Fig. 5 it is assumed that three signal samples are to be transmitted and the resulting count ensures that the last three pulses b<SP>1</SP> of the twenty-four time slots of a frame are available However there are three further pulses b<SP>1</SP> in the 7th, 12th and 19th time slots due to the pseudorandom signal and these are used for the transmission of the signal samples nothing being sent in the last three time slots.