Patent GB-763734-A (GB)
Title: Improvements in or relating to electrical circuits employing transistors
Inventor: ODELL ALEXANDER DOUGLAS
IPC: H03K3/30
Filed: 1953-12-03
Abstract: 763,734. Electronic counters; pattern movement stepping registers. STANDARD TELE - PHONES & CABLES, Ltd. Nov. 26, 1954 [Dec. 3, 1953], No. 33618/53. Class 106 (1). [Also in Group XL (c)] Transistors XI ... XIII are arranged so that only one is in the on or conducting state at any instant, the remainder being off and pulse leads, SET, are provided so that any transistor may be switched on, any other transsistor which is on then automatically being switched off. In the off state, the emitter is held near earth, the collector at - 12 volts and due to the potential divider R1, R2, G1 and R7 the base is maintained at +6 volts. A negative pulse applied over lead SET and diode G8 carries the base negative so that the transistor XI conducts and due to the regenerative action of the base resistance, the transistor rapidly passes to the on state. Capacitor C1 charges, due to the emitter-collector current, and the transistor emitter and base assume potentials slightly positive with respect to the collector, the emitter being at - 10 volts. The potential on the lead P is normally + volts so diodes G4, G41 and G141 conduct, biasing off diodes G1 and G51. This potential also biases off diodes G5 and G151. Master pulses are ineffective to lower the potential of the junction G111, R171 since diode G151 conducts to maintain it at earth. Similar action occurs at the other junctions but at junction G11, R71, diode G51 is non-conducting so that the junction falls to - 10 volts switching transistor XII on at its base. The emitter potential is held near earth by capacitor C11 so the collector rises nearly to earth potential, switching-off transistor XI. The capacitor C11 charges to nearly - 12 volts, any tendency for the common collector line to pass to a more negative potential being prevented by diode G3. The Provisional Specification describes a two-stable state circuit, Fig. 1 (not shown), in which the emitter is held near earth over a capacitor shunted by a resistor and the base potential is lowered to trigger the circuit on, all the electrodes taking up a potential near that of the collector supply, the circuit being reset by a positive pulse applied to the collector which turns the transistor off. A trigger pair is formed by employing two such circuits, Figs. 2 and 5 (not shown), with a common collector load, the resetting circuit being in the base lead of the second transistor. A number of trigger pairs may be controlled by gating rectifiers to form a shifting register, Fig. 7. Negative pulses are applied over the appropriate SET and RESET leads to give the desired pattern, it being assumed that transistors X2, X11 and an earlier transistor connected to lead A are made conducting. Master pulses P bias off the diodes G4, G41, allowing the negative potential on lead A to reverse the transistor pair X1, X2. In a similar manner, diodes G14, G141 are biased off to allow transistors X11, X12 to take up the state of transistors X1, X2. Changes in the emitter potentials of each stage are delayed by capacitors C1. Specification 29848/53 is referred to in the Provisional Specification.