Patent GB-765768-A (GB)
Title: Improvements in or relating to data storage equipment
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: G06F9/32
Filed: 1955-01-14
Abstract: 765,768. Electric digital-data-storage apparatus. STANDARD TELEPHONES & CABLES, Ltd. Jan. 14,1955, No. 1253/55. Class 106 (1). [Also in Group XXXIX] Data storage equipment comprises a matrix of storage elements in any row (or column) of which a word (i.e. an ordered set of characters considered as a unit) may be stored, and a distributer whose condition corresponds to the next row (or column) for writing or reading, the distributer being stepped on in response to reception of a word to be written or to a reading signal, whereby words are sequentially written into or read out from successive rows (or columns) of elements. In the magnetic core matrix store described, writing and reading are controlled by two separate, similar circuits each including a distributer comprising further bi-stable magnetic cores. The matrix, Fig. 2, may be as described in Specification 760,048, each row may be selected by energizing the corresponding wire W1, W2 ... Wn from the write distributer, Fig. 1, to record a word received in static register SR and represented by selective energization of wires B1 to Bm; and a word may be read out on parallel leads connected to amplifiers such as OA1, by energizing a row-selecting wire R1, R2 ... Rn from the read distributer (Fig. 3, not shown). The storage circuits are initially reset by a pulse PP which may also be applied to reset windings (not shown) on the matrix cores. The distributers may comprise switching matrices. Writing operation. As soon as a binary word is received in SR, Fig. 2, a " 1 " output from one of SR1 to SRm will pass through gate RIG, Fig. 1, and set bi-stable circuit WSA to the " 1 " condition in which, with the " 0 " output from circuit WSB, it opens gate G1 so that the next recording clock pulse PW sets WSB to the " 1 " condition in which after a delay, due to circuit D4, it opens gate G2. The next pulse PW will then provide a pulse PWS which resets WSA, WSB and steps on the writing distributer via a splitting circuit (including bi-stable device SA and cross-connected gates G3, G4) which switches pulses via amplifiers AMP1, AMP2 alternately to leads L1, L2, connected to driving windings on alternate distributer cores WT1 to WTn. The first pulse on L1 resets WT1, which is initially in the operative magnetic condition, thereby applying an energizing pulse to wire W1 to enter the first word in the top row of the matrix, and to the input winding of WT2 which is thus set ready to select the next row. The pulse PWS also resets SR, after delay D1, so that another word can be entered. Subsequently received words are similarly recorded in successive rows, the corresponding energized wires W2-Wn also setting a " chalkmark " element in the preceding row (righthand column), such elements being used in the reading operation. Reading operation. The rate of reading is determined by a pulse generator (not shown) which controls a synchronizing circuit like WSA, WSB, Fig. 1, whereby read clock pulses PR (interleaved with pulses PW, see Fig. 2) are gated to produce pulses PRS for stepping on the read distributer and successively energiz. ing wires R1-Rn. Such pulses are produced under control of signal X obtained, after delay, from bi-stable circuit RC when set in the " 1 " condition to indicate that there is data still to be read, this circuit being reset by each pulse PRS. The " chalk-mark " elements are reset in turn as the corresponding wires R1, R2 ... Rn are energized, and only if an element has been previously operated, indicating that a word is recorded in the next row, is an output obtained to set RC to " 1 " via amplifier OAC and delay circuit D9.