Patent GB-1396789-A (GB)
Title: Television receivers
IPC: H04N5/63
Filed: 1972-05-24
Abstract: 1396789 Television receivers; transistor switching gating and muting circuits MATSUSHITA ELECTRIC INDUSTRIAL CO Ltd 24 May 1972 [27 May 1971 29 May 1971 31 May 1971] 24393/72 Headings H3Q and H3T In a T.V. receiver having a rectifier circuit 2, Fig. 1, for rectifying the A.C. voltage from a power source 1 to provide the D.C. supply for D.C. energizable stages of the receiver, at least one of the D.C. energizable stages is connected through a switch 3 to the rectifier circuit 2 and the switch 3 is controlled so as to isolate the D.C. stage from the D.C. supply in response to a cessation of at least a component of a transmitted television programme signal received by the receiver. When the television receiver is switched on switch 13, Fig. 1, is closed for a time to charge a capacitor 15. This turns on FET 8 and allows the output from a gate phase controller 6 to pass via a transistor 7 to trigger a thyristor 3 on so that the rectified output of a rectifier 2 connected to an A.C. supply 1 is fed to provide a stabilized D.C. for the television receiver connected to 4, 5. Vertical or horizontal synchronizing pulses obtained from the received T.V. signal by the sync separator are applied to 11 to maintain the capacitor 15 charged and to keep the FET 8, the transistor 7 and the thyristor 3 on. When the programme broadcasting is terminated the T.V. signal at 11 ends and FET 8 is maintained on for a time until the capacitor 15 has discharged whereby the transistors 7 and 8 and the thyristor 3 turn off to disconnect the D.C. supply. The signals applied to 11 may be the signals from which the vertical or horizontal sync signal is not separated or may be the AGC signal. A bipolar transistor may be used in place of FET 8. In a modification (Fig. 2, not shown), the FET may shunt the input to the base of the transistor 7 so that the FET is cut off when receiving a T.V. signal and becomes conductive when the T.V. signal ends. In further modifications (Figs. 3 and 4, not shown), a D.C. source (19, 20) is connected to the FET 8 so that it may be more positively made to conduct and cut off. In a still further modification (Fig. 5, not shown), the FET 8 may have a second gate fed from the smoothing circuit 10 via a switch (24). A timer circuit comprising a capacitor (22) and a variable resistor (23) is connected to the second gate so that when the switch (24) is opened when the T.V. receiver is receiving the capacitor (22) discharges through the variable resistor (23) until the gate voltage falls to a certain level to turn the FET off so as to stop the operation of the receiver after a predetermined time. In a further embodiment, Fig. 6, D.C. is supplied to a tuner, an IF amplifier, a detector and a synch separator 46 and when a T.V. signal is received FET 48 is cut off so that the thyristor 34 conducts to connect the D.C. power from 32 to a video output signal amplifier, a deflection circuit and a sound channel of the receiver connected at 35, 36. On termination of the T.V. signal the supply to 35, 36 is disconnected as described above. In a modification (Fig. 7, not shown), the FET 48 may be connected in series with the transistor 39.