Patent GB-1404104-A (GB)
Title: Data processing apparatus
IPC: G06F9/32
Filed: 1973-08-21
Abstract: 1404104 Branch instructions in a virtual memory system INTERNATIONAL BUSINESS MACHINES CORP 21 Aug 1973 [21 Sept 1972] 39423/73 Heading G4A In a data processing system having a virtual memory system conditional branch instructions read from the main memory specify a branch address and whether the address is virtual or real and the system is arranged in response to a non-branch instruction and a branch instruction where the condition is not satisfied to increment the current real memory address to obtain the next instruction, and in response to a conditional branch instruction where the condition is satisfied to supply the branch address (after translation where it is virtual) to the main memory addressing arrangements. The virtual memory system is preferably a microprogram control store although it may store program (macro) instructions. The memory system may be formed in a control processor or in an input/output control unit and includes main 10 and backing 97 stores. The main memory 10 is addressed by register 13 which contains page and offset (word) address parts. A microinstruction read from memory 10 is stored in output register 10 and may consist merely of bits each of which directly operates a gate or control circuit or may have a coded operator portion. In the latter case the op code is decoded at 17 to provide control signals on lines 18 and 22, the latter indicating that the instruction is a branch instruction. Where the instruction is a branch the remaining part other than the op code specifies a branch address in terms of page and offset and whether the address is real or virtual. When the instruction is not a branch instruction circuit 41 increments the current address via gate 34 enabled by the NOT BRANCH signal on line 31 to obtain the next instruction. Provision is made for a virtual/real address translation when the incrementing causes a page boundary to be crossed and also for the appropriate transfer between the backing and main stores when necessary. When the instruction is a branch instruction circuit 76 tests whether the branch condition is fulfilled. If the condition is not fulfilled gate 34 is enabled via line 77 and the current address is incremented as before. If the condition is fulfilled a signal on line 78, via line 83, enables gate 58 to feed the offset part of the branch address from register 15 to the memory address register. AND circuit 53 tests whether the page part of the address in register 15 is non-zero and virtual or real. If zero, gate 53 is blocked and no page address is transmitted via gate 55. As a result the branch address is formed by the offset part of register 15 in the same page as the branch instruction since the page part of memory address register 13 remains unchanged. If the page part of the address in register 15 is non- zero and real, gate 53 actuates gate 55 to pass the page part from register 15 to memory address register 13. If the page part is virtual gate 82 enables the address translation circuit 54 which includes a conventional table look up arrangement. If the requested page is resident in main memory 10 the translated address is fed via line 90 and gate 91 to the memory address memory 13. If the page is non-resident translator 54 signals a page fault which accesses a predetermined sequence of microinstructions to perform the appropriate transfers between the main and backing stores. The transfer is made without having to transfer the page to be replaced from the main to the backing store, the latter containing all pages at all times. Following the transfer the translation arrangement 54 is updated accordingly and operation resumes as above. Real page addresses are used in branch addresses when it is certain that the branch address is in a page which is resident in the main memory, e.g. a branch within the same page or to a page constrained to be resident in main memory 10 permanently. Since an all zero page address in a branch address implies a branch within the current page no branching is possible to the page stored in the zeroth page location in main memory. This page may be used to store the translation tables.