Patent GB-1342447-A (GB)
Title: Encoding system
IPC: H03M7/32
Filed: 1972-09-05
Abstract: 1342447 Delta modulation INTERNATIONAL BUSINESS MACHINES CORP 5 Sept 1972 [3 Nov 1971] 41080/72 Heading G4H Apparatus for providing a #-modulated output representing amplitude variations of an input signal, preferably derived from scanning a picture, chart, &c., is adapted to respond to abrupt changes in the input signal to prevent amplitude or phase distortion in the decoded output owing to "slope-overload" in the system, i.e. owing to changes occurring in the input which have a rate of change greater thanthe maximum rate of change that may be represented by the coded signals. The sequence of operations is controlled by 14 clock pulses from clock 46 occurring on 14 separate output lines in the order shown. This sequence is repeated 8 times between two sampling points of the input analog signal. The input analog signal is sampled and converted to 8-bit digital words, and 3 such consecutive words V k -V k+2  are stored in a shift register 40. A 3-bit binary counter 50 is set to 000 and the absolute value A k  of an output word is derived in the deltadecoder 44 using the value A k-1  stored in the register 52 from a previous cycle and the bit N k  (0) which is held in the counter 50. The value A k  so derived is stored as shown at 52 and passed to an arithmetic unit 54 together  with the first V k  of the stored sequence at 40 and the value (V k -A k )<SP>2</SP> is derived and stored therein. The operation is repeated using the newly derived value A k  and the next bit N k+1  (0) of the counter value at 50, and the value A k+1  is obtained. This is stored as shown and applied also to the unit 54 together with the value V k+  1  where the value of (V k+1 -A k+  1 )<SP>2</SP> is derived and stored. This procedure is undertaken using the values N k+2 , A k+1  and V k+2  and the function is derived at 54 and passed to a comparator 56, the other input of which is derived from a store 58 which was set to a maximum value at the start of the cycle. If the value derived at 54 is less than the value presented from 58, the calculated value is overwirtten into store 58, the stored value at A k  is written into box A k *, and the bit at N k  is written into store N k *, these steps being omitted if the value at 54 is greater than that at 58. The last clock pulse, 14, cause the counter to increment by 1 and the whole process is repeated for the word 001 stored in the counter. When the number 111 is reached and the cycle completed, the values at N k * and A k * will be respectively the delta output bit to be transmitted corresponding to the value V k1  and the value of the demodulated signal corresponding to the input V k , both derived from the 3-bit code word giving the least value for the function above which thereby takes into account changes that will occur in the next two samples of the input signal and thereby causes the output bit stream to change before the actual change occurs so that the peaks at the input and output of the system coincide. A pulse from the counter 50 then resets all the apparatus and shifts register 40 to receive a new converted sampled analog input.