baber/WOPTO huggingface dataset:
Patent JP-H03232255-A (JP)
Title: Semiconductor integrated circuit device of master slice layout
Inventor: YOSHIZAKI SHOICHI
IPC: H01L27/118
Filed: 1990-02-08
Abstract: PURPOSE:To enable a ROM to be formed of only conventional transistors by a method wherein a basic unit ROM is composed of two P channel transistors which possess a drain in common, two N channel transistors which are possessed of a drain in common, a bit line connected to the two common drains, and four word lines which can be connected to the gates of the transistors and the ROMs are arranged. CONSTITUTION:Word lines 33 and 35 are set in an enabled state and word lines 34 and 36 are set in a disenabled state, whereby the data fixed in a first ROM are made to appear at a bit line 31. When the word lines 33 and 35 are set in a disenabled state and the word lines 34 and 36 are set in an enabled state, whereby the data fixed in a second ROM are made to appear at the bit line 31. The first and the second ROM are made to serve as a basic unit, and two or more basic units are provided onto a master slice to obtain a required ROM.
Patent JP-S63198540-A (JP)
Inventor: FUKUI YASUHIRO
IPC: H02J3/38
Filed: 1987-02-10
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S61184139-A (JP)
Title: Carrier vehicle
Inventor: KANO TAKAO
IPC: B60P1/36
Filed: 1985-02-13
Abstract: PURPOSE:To make it possible to automatically store a cargo in a storage container, by laying a carrier bed on a vehicle bed which carries storage containers, by winging a chain on the carrier bed and a sprocket which is rotably journalled to the rear and of the vehicle bed, and by attaching a stopper to the chain so that is projects from the chain to engage with a cargo. CONSTITUTION:When a motor 24 is rotated in, for example, the clockwise direction in such a condition that a front rail 15 is fixed at, for example, its outer position, a sprocket 10 rotates clockwise, and therefore, a chain 12 wound around sprockets 6, 8, 10 also rotates clockwise. At this stage, when a cargo W such as, for example, a used tire is loaded on a receiving bed 23 so that it is engaged to stopper 20 on the chain 12, the cargo W is moved along stationary and movable guide rails 13, 14. Further, when the cargo reaches the front end of a rear rail 16, the stopper 20 is rotated outward due to the weight of the cargo W, the cargo W is charged into the left side of, for example, a rear storage container 3r.
Patent JP-S61185835-A (JP)
Inventor: OMURO MASARU
IPC: H01H73/48
Filed: 1985-02-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H11234651-A (JP)
Title: Supervisory camera system
Inventor: KATO SUMIO
IPC: G03B15/00
Filed: 1998-02-09
Abstract: PROBLEM TO BE SOLVED: To obtain a supervisory image with excellent visual confirmation performance on which an image sensing signal and a television signal are superimposed. SOLUTION: The supervisory camera system is provided with supervisory camera means 1, 2, 3, 4, 5, 8, 9, 10 that obtain a television signal for image supervision, image sensing means 1, 2, 3, 11, 12, 13, 14, 15, 16, 17 that obtain an image sensing signal for high speed image processing and a signal adder 6 that superimposes the television signal and the image sensing signal.
Patent JP-S59152856-A (JP)
Inventor: KISHIDA KAZUO
IPC: B32B27/30
Filed: 1983-02-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63194343-A (JP)
Title: Method of controlling wire bonding apparatus
Inventor: KOBAYASHI HIROAKI
IPC: B23K20/10
Filed: 1987-02-09
Abstract: PURPOSE:To perform bonding operations under optimal conditions for improving productivity and quality of products, by controlling bonding pressures indenpendently and discriminately before and after bonding parts are contacted with each other and, after the parts are contacted, further controlling them independently and discriminately before and after the application of supersonic waves is started. CONSTITUTION:If a bonding tool 7 is lowered to a predetermined level, thrust F of a voice coil motor 10 is decreased from a set value of a rapidly lowering period T1 to a set value of a soft approaching period T2. As soon as the lower end of the bonding tool 7 reaches the surface to be bonded, the thrust F is raised to a next set value. After lapse of a period T3 the thrust F is lowered so as to provide a pressure suitable for the bonding operation. This output U is applied for a set period T4 to complete the first wire bonding operation. After another bonding tool 6 is lifted to a predetermined level, a larger thrust F is employed to start the next bonding opera tion. The thrust F is not changed for a soft approaching period T8 and, after a lapse of a period T9, the thrust F is increased so as to provide a pressure suitable for the bonding operation. This output U is applied for a set period T10 to complete the second bonding operation.
Patent JP-H0731141-A (JP)
Title: Constant voltage circuit
Inventor: KANEKO TOSHIYUKI
IPC: G05F1/613
Filed: 1993-02-17
Abstract: PURPOSE:To allow positive control of an output voltage by applying a reference voltage obtained by superposing a voltage induced in an auxiliary coil on the voltage induced in the secondary coil of a transformer to a feedback circuit for regulating the output voltage, a constant voltage control section, or a secondary control section. CONSTITUTION:A transformer 13 has a secondary coil 13b and an auxiliary coil 13c on the secondary. When a voltage and current detecting section 17 is applied with a reference voltage obtained by superposing a voltage induced in the auxiliary coil 13c on the voltage induced in the secondary coil 13b, a control signal is fed to a feedback circuit 15 and a constant voltage control section 12 based on the reference voltage in order to regulate the output voltage. Furthermore, the voltage and current detecting section 17 turns the secondary control section 16 ON/OFF. Consequently, the feedback circuit 15 and the constant voltage control section 12 are controlled positively without causing under- drive voltage. When the current increases over a reference value under heavy load on the constant voltage circuit 10, the secondary control section 16 is controlled to interrupt a dummy resistor, for example, thus decreasing the burden on the circuit.
Patent JP-H04253277-A (JP)
Title: Logic inspection system for hardware
Inventor: KOBAYASHI YUKIO
IPC: G06F17/50
Filed: 1991-01-29
Abstract: PURPOSE:To present the logic inspection system to shorten time required for inspection at a hardware simulator. CONSTITUTION:This system is constituted by providing logic hardware simulator 1 to control an inspection program to travel on the logic hardware, and a processor to execute the judged part of the inspection program at extremely high speed in comparison with a tested part. The processor is equipped with a dummy hardware simulator 6 in charge of simulation together with the logic hardware simulator and a dummy hardware 8 to execute only the judged part of the inspection program at extremely high speed under the control of the dummy hardware simulator, and the tested part and judged part of the inspection program are respectively executed while being shared by an inspection logic hardware 2 and the dummy hardware. As the result, time for simulation is considerably shortened.
Patent JP-S58143260-A (JP)
Title: Electrophoresis apparatus
Inventor: FUJII HIDEHIKO
IPC: G01N27/447
Filed: 1982-02-22
Abstract: PURPOSE:To improve the accuracy of velocity of a high velocity electrophoresis, by isolating an electrophoresis tube from an electrode cell by a filter impregnated gel to porous substance. CONSTITUTION:There is no connection among a duct between valves V1, V2 and between electrodes cells 2, 3 in a hydrodynamic meaning and both duct and cell are completely intercepted. Gel layers are held in filters 4, 5 by a porous substance and passing by diffusion of a solvent molecule and solute ion is made possible and then, solutions in the baths 2, 3 and that of in an electrophoresis tube 1, are connected electrically. And electric migration is caused to floating particles in the tube 1 by applying voltage between electrodes 10, 11.
Patent JP-H11317737-A (JP)
Title: Atm network and its data transmitting method
Inventor: CAI BIAODONG
IPC: H04L29/06
Filed: 1999-02-05
Abstract: PROBLEM TO BE SOLVED: To provide a traffic merging network and a network which can merge data below frame level, and their operating method. SOLUTION: The network is equipped with origination stations 20, 30, and 40 which are discriminated with SIDs and connected to an unmerged VC 50, ATM switches 60 and 80 which have input terminals where the unmerged VC 50 is connected and an output terminal where merged VCs 70 and 90 are connected, and a reception station 100 which is corrected to the merged VCs 70 and 90 and has an SID allocation table of respective SIDs.
Patent JP-H08221010-A (JP)
Title: Information display device
Inventor: SATO MITSURU
IPC: G09F9/00
Filed: 1995-02-16
Abstract: PURPOSE: To miniaturize a display surface in its widthwise direction and also the device itself in its depthwise direction and to perform day and night a display having excellent visibility in reducing irregularity of the display. CONSTITUTION: A display substrate 4 having through holes 5 corresponding to dots of display information is arranged in the inside of a case 1 on the front surface side. A shutter unit 30 equipped with a shutter plate 32 is arranged for each through hole 5 on the display substrate 4. A light transmission plate 11 having translucency, where a dot reflecting surface 16 corresponding to each through hole 5 is formed on the rear surface is arranged on the rear surface side of the display substrate 4. Slant surfaces 26 formed on both side end surfaces of the light transmission plate 11 are provided with reflecting members 27 respectively.  Sunlight is incident upon the upper end surface of the light transmission plate 11 via a sunlight introducing plate 3 on the upper surface of the case 1, and light of a light source 12 is reflected by the reflecting members 27 from the rear surface of the light transmission plate 11 and is incident. These kinds of light are reflected by the dot reflecting surface 16, and a dotwise light surface is emitted by the light transmission plate 11, and hence when the shutter plate 32 corresponding to the dot of the display information is opened, the transmission light from the light transmission plate 11 is passed through the opened through hole to make a desired display.
Patent JP-S58145733-A (JP)
Title: Production of polyolefin film for electrical insulation
Inventor: YOTSUI HIKARI
IPC: H01B19/00
Filed: 1982-02-25
Abstract: PURPOSE:To produce the titled film which does not contain any oil bubbles and is suitable for use as an insulating material for high-voltage OF cables, by immersing a stretched polyolefin film in a soln. of a low-molecular polyolefin. CONSTITUTION:A soln. obtd. by dissolving 0.05-2.5% low-molecular polyolefin such as polypropylene having an MI of 100-75 in an insulating oil such as an alkylbenzene DDB or polybutene oil for OF cables, is used. A stretched film of a polyolefin such as high-density polyethylene or isotactic polypropylene is immersed in said soln. at a temp. which is 50-10 deg.C lower than the m.p. of the polyolefin.
Patent JP-H05220508-A (JP)
Title: Sleeve roll for rolling
Inventor: KOBAYASHI MOTOO
IPC: B21B27/03
Filed: 1992-02-14
Abstract: PURPOSE:To provide a sleeve roll for rolling which is made so that it is usable for the more upstream side of rolling stage by increasing the fixing force of a hard sleeve which is amounted on a shaft without extending the space for parts. CONSTITUTION:The hard sleeve 4 is closely fitted on the shaft by pressing a taper sleeve 5 between itself and the shaft 1 on which this sleeve is amounted. A shrinkage ring 6 is interposed between a nut 7 which is screwed to the shaft 1 and the hard sleeve 4 and annular tapered clamping surfaces 3a, 6a provided on both of a fixing ring 3 and the shrinkage ring 6 which are received with a flange 2 are made to closely contact to the end faces 4a of the sleeve which is conformed to their surfaces. The shrinkage ring 6 which is heated at the time of fastening the nut 7 is shrinked by cooling after the nut is fastened and frictional forces on the end faces and the inner surface of the sleeve are increased by pressurizing the shrinkage ring 6 in the axial direction and inward in the radial direction by wedge effect that is generated in this way. In this way, the sleeve is firmly fixed, the roll withstands high rolling torque and the sleeve roll can be made to use for the rolling stands also in the upstream stages.
Patent JP-S62192455-A (JP)
Inventor: KURISUTOFU TAUBITSUTSU
IPC: C08L77/00
Filed: 1987-02-12
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H01202787-A (JP)
Title: Image memory
Inventor: HIRAI MASAYUKI
IPC: G09G5/32
Filed: 1988-02-09
Abstract: PURPOSE:To execute a parallel processing of each storage part and to execute picture drawing in an image memory at a high speed by controlling an operation of a picture drawing storage part and a store storage part by a built-in picture drawing control part. CONSTITUTION:The structure of the title image memory contains a store storage part 15 in which a bit pattern is stored as data, a picture drawing storage part 17 in which a prescribed bit pattern is brought to picture drawing by the data fetched from the store storage part 15, and a picture drawing control part 11 for giving an address of a picture drawing position to the picture drawing storage part 17, and also, controlling an output of the data sent to the picture drawing storage part 17 from the store storage part 15. Accordingly, an operation of each storage part 15, 17 is controlled by the picture drawing control part 11 being independent from the outside. In such a way, a parallel processing of each storage part 15, 17 can be executed, and picture drawing in an image memory 1 can be executed at a high speed.
Patent JP-H03233376-A (JP)
Title: Semiconductor test system, calibration means used in the same, and pin electronics
Inventor: IKEUCHI FUMIO
IPC: G01R31/28
Filed: 1990-02-09
Abstract: PURPOSE:To perform the calibration of a timing and amplitude at the connection point of a test device by performing the draw-out of each signal of a test head from a calibration unit via a resistor a little higher than the characteristic impedance of wiring when it is drawn out. CONSTITUTION:A sampler 16 placed in the calibration unit 15 converts a fast signal that is the target of calibration to an analogous slow speed waveform, thereby, the measurement of the parameter of a waveform required for the calibration can be performed at a slow speed high accuracy circuit. At this time, the calibration with an absolute value can be performed by a reference signal 27 from a reference signal generator 17. Also, a high resistor 12 placed at a signal draw-out point for the calibration is provided with a resistance value of several ten times the signal impedance, therefore, no influence on the waveform of a signal line is applied. Also, the state of the connection point 13 can be recognized by performing the time domain reflectometry of the wiring from a signal draw-out point to the connection point 13 of the device by using a signal from each signal source, and observing the waveform with the unit 15, thereby, the calibration of the connection point 13 can be performed.
Patent JP-S60174463-A (JP)
Inventor: TOGUSA KENJI
IPC: F25B47/02
Filed: 1984-02-20
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H02208722-A (JP)
Title: Pseudo fifo memory
Inventor: HATA YASUHIRO
IPC: G06F5/06
Filed: 1989-02-09
Abstract: PURPOSE:To artificially realize the FIFO of a large capacity by using a large capacity RAM by constituting this FIFO memory so that data written from an input data bus is read out of an output data bus in the order of write without executing an address control from the outside. CONSTITUTION:As for a read-out address, since a read-out pulse signal RD inputted to a terminal 22 is inputted to a read-out address counter 14 through an AND gate 16, this read-out address counter 14 is counted up automatically, and data can be read out of a new address at any time. In such a manner, data can be read out successively from a random access memory 6. Accordingly, the FIFO of a large capacity can be realized artificially and easily by using a large capacity RAM being on the market.
Patent JP-H10216651-A (JP)
Title: Metal sorting method and metal sorter using the method
Inventor: TOYAMA YOSHINARI
IPC: G01N23/223
Filed: 1997-02-13
Abstract: PROBLEM TO BE SOLVED: To conveniently sort >=3 kinds of metals regardless of the size, shape, surface state (dust, rust), etc. SOLUTION: Plural kinds of metallic pieces 1 consisting respectively of a single metal are successively irradiated with X-rays, the fluorescent X-ray spectra radiated from the metallic pieces are analyzed, and the metals are sorted from the spectra. Meanwhile, the metal sorter using this method is composed of a conveyor 12, a position detector 14, a metal identifier 16 and a metal sorting and discharging device 18. The sorting and discharging device 18 is provided with plural dischargers 19, and the metallic pieces 1 are sorted by a controller 20 and discharged.
Patent JP-H06244313-A (JP)
Title: Semiconductor package and mounting method
Inventor: OCHI TAKAO
IPC: H01L25/10
Filed: 1993-02-18
Abstract: PURPOSE:To mount semiconductor chips in high density and in general purpose style by dividing semiconductor package at the thinned parts to divide the semiconductor packages. CONSTITUTION:The title semiconductor comprises semiconductor chips 2, the lead materials 3 that are connected with the electric terminals 6 of the semiconductor chips and the molding plastic 1 that covers the part of the semiconductor chips 2 and the lead materials 3. The ends of the lead materials 3 are led out to the outside of the molding plastic 1. At the connecting area where the plural semiconductor chips are connected, there formed dividing areas 8 composed of the thinned parts 7 of the molding plastic 1 to make it possible to divide semiconductor chips 2. In such a way, plural semiconductor chips 2 are mounted in a package with a minimum space and as the package space is minimized, the mounting process is simplified.
Patent JP-H05224168-A (JP)
Title: Ferroelectric liquid crystal display element
Inventor: MOCHIZUKI AKIHIRO
IPC: G02F1/1337
Filed: 1992-02-17
Abstract: PURPOSE:To enable an efficient gradation display by shifting the rubbing directions of the oriented films of upper and lower substrates from a counter- parallel state. CONSTITUTION:This ferroelectric liquid crystal display element makes the gradation display by relatively varying a selection voltage Vs, half selection voltage Vhs and non-selection voltage Vns at the time of multiplex driving and is constituted by shifting the rubbing directions of the oriented films applied on the glass substrates formed with the patterns of transparent electrodes by 1 to 10 deg., more preferably 1 to 5 deg. from the counter parallel. Namely, the rubbing directions of the polyimide oriented films are provided with a slight angle thetawithout making the directions counter parallel with the upper and lower substrates, by which a change is generated in the threshold characteristics. As a result, the transmittance in a black display region is low and the effective gradation display is executed when the element exhibits a steep rise.
Patent JP-H02207388-A (JP)
Title: Character recognizing device
Inventor: SUZUKI KENJI
IPC: G06K9/68
Filed: 1989-02-08
Abstract: PURPOSE:To realize fast and flexible dictionary updating function by writing character data to a prescribed address, where prescribed data are written, in a storage circuit when the character data are newly stored and writing the prescribed data to the address to be deleted when the character data are deleted. CONSTITUTION:In a second storage circuit 15 provided in a storage circuit 10, when the character data are newly written and stored, the character data are written and stored to the prescribed address where the prescribed data are written. When the character data are deleted from the storage circuit 10, the prescribed data are written and deleted to the address to be deleted. As a result, since the number of the data to be processed in an arithmetic circuit 40 is fixed regardless of new registration or deletion, the parameter change of the character data number is not needed. It is not necessary to execute the rearrangement processing of the character data after the deleted character data and it is enough only to execute reload the deleted character data and prescribed data. Thus, a character recognizing device with the fast and flexible dictionary updating function can be realized.
Patent JP-H02208002-A (JP)
Title: Lumber-transferring process in sawmill machine and its device
Inventor: ISHIDA KEIICHIRO
IPC: B27B31/00
Filed: 1989-02-08
Abstract: PURPOSE:To enable a roughly sawn plate to be fed to next process at the state as it is by a method in which orderly set condition and reversely set condition are detected in transferring, and only the roughly sawn plates having been reversely set are sent to the branched conveyer having a turning over device. CONSTITUTION:The receiving part 41C provided on an intermediate conveyer 41 turns slowly so as to support a primary sawn plate A1, and said plate A1 to be transferred on the intermediate conveyer 41 is placed in reversely set condition at the side of the intermediate conveyer 41, and in orderly set condition at the side of a feeding device 9. The primary sawn plate A1 is acted by a projected part 41b and is successively placed on a transferring conveyer 42, and then is transferred to a transferring direction-changing unit 43. Two transferring direction-changing units 43 operate alternately at a prescribed time interval and feed the roughly stripped plates to each branched conveyer 44 so that the primary sawn plate A having been orderly set is placed on one branched conveyer and said plate A1 having been reversely set is placed on the other branched conveyer. On the branched conveyer 44 on which the primary sawn plate A1 having been reversely set, is fed, a turning over device 46 operates, whereby the reversely set condition is corrected into the orderly set condition, and it is fed to secondary sawing process.
Patent JP-S64129-A (JP)
Title: Interleaf-containing, fiber-reinforced epoxy resin prepreg material
Inventor: TANAKA HIDEHO
IPC: B29C70/08
Filed: 1988-02-12
Abstract: PURPOSE: To obtain the title epoxy resin prepreg material which can give a high-strength, high-toughness laminated composite material, by using a fiber- reinforced epoxy resin matrix and an interleaf comprising a polyimide film subjected to a specified treatment.  
     CONSTITUTION: A reinforcing fiber (e.g., glass fiber) is impregnated with an epoxy resin to produced a fiber-reinforced epoxy rein matrix. Separately, an imide polymer (e.g., a polymer of formula I or II) is molded into a film, and the obtain polyimide film is subjected to corona discharge treatment and/or matting. An interleaf 1 comprising the treated polyimide film is laminated on a fiber-reinforced epoxy resin matrix 2, and bonded together by pressing to obtain the purpose interleaf-containing fiber-reinforced epoxy resin prepreg material A composite material produced by using this prepreg material can be suitably used as, e.g., a structure material for aircraft. 
     COPYRIGHT: (C)1989,JPO&Japio
Patent JP-S61193258-A (JP)
Inventor: YOAHIMU HAINTSURU
IPC: G06F3/00
Filed: 1986-02-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。