Patent GB-777244-A (GB)
Title: Improvements in or relating to apparatus for translating a number from a first to a second notation
Inventor: TRUSSELL ALEC
IPC: H03M7/00
Filed: 1953-01-30
Abstract: 777,244. Digital electric calculating-apparatus. BRITISH TABULATING MACHINE CO., Ltd. Nov. 13, 1953 [Jan. 30, 1953], No. 2725/53. Class 106 (1). [Also in Group XL (c)] In electronic apparatus for translating a number from a first to a second notation, the equivalents in the second notation of digital values in the first notation are read out sequentially in serial form from storage means and applied through gating means to an accumulator, and sequencing means renders means settable to represent each digit of the number effective in turn to control the gating means when the equivalent corresponding to that settable means is read out. In the decimalto-binary translator shown, e.g. for input of data into a binary series-mode computor, the number to be translated is obtained from a record card in which each digit is represented by a differentially positioned hole which, when the card is sensed while being fed over contact roller 2, produces a differentially timed electrical impulse at a corresponding brush 3 which sets an associated bi-stable doubletriode trigger 4 controlling gate 5 (only the brush, trigger and gate circuit for the tens denomination being shown). The binary equivalents of successive powers of ten are stored serially around a single track of a magnetic drum 1 and read by a head 10. The drum has three other tracks which respectively supply clock, end-of-revolution and end-of-word pulses to lines 16, 9 and 14. At the commencement of each card-sensing index time, cam-operated contacts 7 close to apply a pulse to trigger circuit 6 which sets it in the condition to open a gate 8 so that the next end-of-revolution pulse passes through this gate and sets a trigger circuit 11. This pulse is so timed that it occurs just before the first equivalent word, corresponding to 1 (10), is read from the drum, and is also used to reset a 4-stage binary counter 13. At the end of each word (taken to be 32 binary digits) a pulse on line 14 steps on the counter and when all sixteen words have been read out the counter returns to the initial condition and produces a carry pulse on line 12 which resets triggers 6 and 11. For each condition of the counter a positive marking potential appears on a corresponding output line of a diode decoding matrix 15. The gates 5 are each connected to one output line (103 for the tens demonination shown) whereby these gates are selected in turn and, if the trigger 11 and associated trigger 4 are set, pass clock pulses from line 16 to allow the equivalents read from the drum to be passed through gate 17 to an accumulator comprising a binary adder 19, e.g. as described in Specification 738,269, and a shifting register 20. Thus, each equivalent is entered once into the accumulator for each card index time during which the corresponding trigger 4 is set, the number of entries therefore depending on the time of setting of this trigger and thus on the corresponding decimal digit. Circuit details are given for the matrix 15, trigger circuits and gates, the latter comprising coincidence triode circuits (see Group XL (c)). The drum may be replaced by an acoustic delay line. A number of tracks on the drum may be used for storing the equivalents for different, e.g. non-uniform, notations, or a single track may be used to store different equivalents under control of a programme instruction. Reference is made also to translation to or from the binary-coded decimal form in which each decimal digit is represented by the values 1, 2, 4, 8.