Patent GB-1333244-A (GB)
Title: Analogue stores
IPC: G11C27/02
Filed: 1971-09-28
Abstract: 1333244 Analogue signal stores PERRANTI Ltd 28 Sept 1971 [6 Oct 1970] 47359/70 Heading G4G An A.C. or D.C. analogue store comprises a voltage storage device, e.g. a capacitor, and a variable resistance, e.g. a FET, whose value depends upon the stored voltage. As shown in Fig. 1, a constant A.C. reference signal from source 15 is applied to a transformer 13 having a centre-tapped secondary 12 the two halves of which are connected to the inverting input 21 of an operational amplifier 22 respectively through series resistors R 2 , R 3  and resistor R 1 . The junction between resistors R 2 , R 3  is connected to earth via the source/drain electrodes of a FET 25 the gate electrode of which is connected to earth via a storage capacitor 26. The variable input signal is applied to terminal 27 and determines the voltage across capacitor 26 and hence the resistance of the FET 25. When this resistance has a datum value equal to R 2  and if 3R 1 =R 2 =R 3  terminal 21 is at zero potential and the output of amplifier 22 is zero. Changes in the datum resistance value of the FET unbalance the circuit and cause flow of current in a direction determined by the sign of the change in feedback resistor R 4 . Hence the amplitude and phase of the output at terminal 24 is determined by the value of the input voltage stored in capacitor 26 and the sense of its departure from the datum value. If the gain characteristic of the FET is insufficiently linear, modifications may be applied as shown in Fig. 3, where the store (Fig. 1) is indicated as box SA. The A.C. input signal is compared with the output signal in a comparator 31A and an error signal applied to a phase-sensitive demodulating circuit 32 energized by transformer 13 (not shown in Fig. 3). The rectified output of the demodulator is applied to the input terminal 27A of the storage capacitor via an integrating stage 33A. The reference signal from transformer 13 is also applied to a D/A converter 42 which receives a 12-bit signal from a digital computer 41. The D/A converter has an address output 45 which is connected to normally closed gates G1A, G2A, G3A via lead 45A. The reference input 43 and the converter address output are also connected to further storage circuits (e.g., as indicated, to two further circuits) of the same form as the one shown in the Figure. On receipt of a command word, the D/A converter opens the gates G of an appropriate circuit and the analogue output, applied on lead 44, actuates that circuit only. If e.g. the signal is addressed to the circuit shown, gates G1A, G2A, G3A close to complete the circuit paths and the new value is fed to the comparator 31A and hence to the store SA. The gates are then closed by a further signal on the line 45A. Where an unbalanced reference supply with one pole earthed is used, the circuit may be modified as shown in Fig. 5 where the values of the resistances are such that when the FET 25 has datum resistance value, the potentials at terminals 21, 23 are equal and that at terminal 24, zero. For a D.C. output, the transformer 13 is replaced by a centretapped battery. The feedback capacitor of a Miller integrator may be used as the storage element (Fig. 4, not shown).