Patent GB-772714-A (GB)
Title: Improvements relating to digital code information interchange systems
Inventor: WHITE ERIC LAWRENCE CASLING
IPC: H03M1/00
Filed: 1953-05-16
Abstract: 772,714. Electric selective signalling. ELECTRIC & MUSICAL INDUSTRIES, Ltd. May 17, 1954 [May 16, 1953], No. 13782/53. Class 40 (1). [Also in Group XL (c)] In a digital code information interchange system, common equipment acts alternately to encode analogue information into digital form and to decode digital information into analogue form. The equipment may be that described in Specification 772,716, [Group XL (c)], Figs. 3, 4 (not shown), or in Specification 772,715, [Group XL (c)], Figs. 5, 6 (not shown). In another embodiment, in which encoding is completed before digital information is transmitted and decoding is initiated after the reception of digital information has been completed, storage facilities J, Fig. 1, in the form of a combined binary counter and shifting register, as described in Specification 738,738, [Group XIX], are provided. At the beginning of a coding operation, a positive potential at terminal T5, conditions circuit J for counting and opens gates G1, G2, gate G3 being opened by a positive potential through switch S1 from amplifier B fed with the negative analogue potential from terminal T1. At the same time gate G4 is open since its inhibitor voltage is only received when the counter in circuit J is full, so that condenser C1 commences to charge linearly and positively, through resistance R1 and amplifier A, from the voltage - Eo. Meanwhile the counter commences to count clock pulses from terminal T6, until gate G3 closes when the potential on condenser C1 reaches the analogue potential at terminal T1 to reduce the negative input to amplifier B to zero. Subsequently the potential at terminal T5 changes to condition circuit J to function as a shifting register, the reading of the counter being fed to an output terminal T3 as a group of binary digit pulses representing the input analogue potential. At the same time, gates G1, G2 are closed, and G5 opened to discharge condenser C1. When decoding is to take place, the shifting register input is connected through switch S2 and a complementer circuit K to the digital input terminal T2, while gate G3 is opened by a fixed positive potential through switch S1. The potential at T5, which conditions the shifting register for operation, closes gates G1, G2, and opens G5. Thus the complement of the received code group is registered and thereafter the potential of T5 is switched to initiate counting of pulses from T6 and the growth of potential across C1, the amplifier B being inoperative. Since the complement of the input was stored in the register, the counter full state is reached after a count equalling the input. At this point an inhibiting voltage to close gate G4 is developed by circuit J and the potential at terminal T4 of condenser C1 is the voltage analogue of the input digital pulse group. If the circuit J is capable of subtraction, the complementer K may be omitted. In a further embodiment, a group of two-state devices L1...Ln, Fig. 2, form a digital static register and a group of " reset " and " set " pulse gates G11, G12; G21, G22 . . . Gnl, Gn2, control their alternate input connections. Their outputs control gates G31...G3n which can connect a voltage source - Eo through resistances of values R, 2R . . . 2<SP>n-1</SP>R respectively to the input of amplifier A, which is also connected through a resistance of value R/2 to the positive input analogue potential terminal T7. At the commencement of coding all the set gates have a positive potential Eo applied, through switch S4 to their side connections so that devices L1...Ln are triggered in succession into state " 1 " by pulses from a distributer P, which may be of the kind described in Specification 766,987, [Group XIX], fed from the clock pulse terminal T6. When L1 only is in state " 1," amplifier A receives, through resistance R, a current arranged to be half that at the same point due to the maximum analogue potential and received through resistance R/2 from terminal T7. When the difference of these two currents produces a positive amplifier output a two-state device F is triggered, through switch S3, into state " 1 " to open gate G1 to transmit a clock pulse, after a delay of half a period in network DN, to the digital output terminal T8. This pulse is also applied to the second input of device F to reset it to state " O," while L1 remains in state " 1." If, however, the difference is such as to produce a negative amplifier output, device F remains in state " O," the clock pulse is transmitted instead through gate G2, and the reset gate G11, to trigger L1 to state " O." The same process is repeated for each of the devices L2 . . . Ln and at each step the input of amplifier A receives a current increment half as large as the previous one. The total current from - Eo is compared with that from T7 and the sign of the remainder is tested to decide whether or not a code pulse is transmitted and whether the last current -increment is maintained or cancelled. Between successive coding operations all stages of the register are reset to zero by means not shown. For decoding incoming digital pulse groups at terminal T8, the position of switches S3, S4 is reversed and the trigger circuits L1 . . . Ln are set successively into state " 1 " or " O " by the pulse distributer P depending upon whether the set gates G12, G22, &c. are opened or not by a received pulse. The amplifier A in this case functions as a see-saw summing amplifier producing output analogue potentials at terminal T7, and the device F is out of action.