Patent GB-895350-A (GB)
Title: Improvements in transistor trigger circuits
IPC: H03K3/012
Filed: 1959-05-12
Abstract: 895,350. Transistor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 12, 1959 [May 14, 1958], No. 16181/59. Class 40(6). [Also in Group XIX] Fig. 1 shows a two-stage binary trigger circuit comprising an input inverter stage 11  fed through an input gate stage 19, 20, 21 the stage 11 being connected in series with an emitter follower stage 22. In the no signal condition transistor 35 is non-conductive and 36 conductive so that OUT A is at minus 6 volts. Lamp 51 protects transistor 36 against current overload and also acts as an indicator. With the waveforms as shown in Fig. 2 applied at time T1 GATE A waveform is at 0 volts and the voltage at point 1 approaches 0 volts exponentially so that as SET A rises current flows in 21 the voltage at point 2 rises and transistor 11 is cut off. Thus the volts at point 3 drop from 0 to minus 6 so that transistor 35 conducts and simultaneously 36 is cut off. Since stage 35 forcibly drives 36 out of saturation a very good rise time is produced even when the stage is loaded and a voltage OUT A change from minus 6 to 0 volts is produced. At time T1 GATE B is at minus 6 so that the voltage at point 6 approaches minus 6 from a more negative condition so that the rise of SET B input pulse does not affect the voltage at 7 so that the stage 54 remains conductive and when OUT A rises from minus 6 to 0 volts the voltage at point 8 rises. This voltage rise passed by the emitter follower stage 55 to cut off 56 and render stage 57 conductive so that the trigger has been changed over and therefore at time T2 GATE B will admit an input pulse and GATE A is shut. At time T2 the voltage at 6 rises above zero with the input pulse SET B so that the stage 54 is cut off and OUT B rises. The feedback over line 33 is connected to points 4 and 5 so a negative wave is produced at OUT A and the trigger remains in this state until time T3. Either or both stages A, B may be reset to the "OFF" state by a reset pulse applied via diode 29. If one reset pulse for example RESET A ends before RESET B stage A will turn on to indicate the relative sequence of the pulses. This feature of the trigger circuit may be used in a detector, Figs. 5 and 6 not shown, which indicates an error condition when the RESET B pulse precedes the RESET A pulse instead of following it as in the normal condition. A number of the binary trigger stages of Fig. 1 may be connected in a counting ring as shown in Fig. 3 the triggers being connected so the common input on ADVANCE line turns off the stage that is on and turns on the next stage. With the first stage reset to the on state GB1 (GATE Bl) and GA2 (GATE A2) condition the respective set inputs so that the first advance pulse turns stage 1 off and 2 on. After the first pulse OA2 (OUT A2) conditions gate B2 and A3 so that the next pulse turns off stage 2 and turns on stage 3 this continues until after N advance pulses the ring of N stages is recycled and stage 1 turns on again. Fig. 4 shows the application of trigger circuits of the type shown in Fig. 1 to a shift register. The triggers are connected so that the common shift input sets each stage to the state of the previous stage prior to the shift pulse and the first stage receives information from an external source.