baber/WOPTO huggingface dataset:
Patent TW-410232-B (TW)
Title: Leather tanning processes
Inventor: SCHEEN HANS J
IPC: C14C3/28
Filed: 1996-04-20
Granted: 2000-11-01
Abstract: The production of household-machine washable and dryable, waterproof, nonflammable, and extrememly colorfast leathers from wet blue hides by a process which has the advantage that significantly reduced volumes of toxic wastes are generated. The wet blue hides are washed and treated to equalize the pH at the surface and in the interior of the leather and to build at least one wanted end characteristics such as suppleness into the leather. This is followed by the introduction of additional character builders into the pores of the hide and the substitution of one or more softening agents for fats originally present in the pores of the hide. Next in a typical application of the invention are dyeing and the fixing of previously introduced substances in the pores of the hide. This is followed by refloatation with a hydrophobic waterproofing agent and buffering for pH equalization and increase of the pH. The hides are next treated to impart a pleasing, silky feel to the leather into which the hides are being converted and a hydrophobic silicone which promotes waterproof-ability and washability; and this is followed by a second fixing step.
Patent TW-302523-B (TW)
Title: Manufacturing method with stable polysilicon resistance
Inventor: JENG SHENG-WENN
IPC: H01L21/70
Filed: 1996-07-15
Granted: 1997-04-11
Abstract: A manufacturing method of polysilicon resistor with high resistance comprises of the following steps: (1) forming polysilicon on the semiconductor substrate, in which the polysilicon will be used as polysilicon resistor; (2) forming first dielectric on the polysilicon; (3) forming conductive layer on the first dielectric; (4) forming second intermetal dielectric layer on the conductive layer;(5) implementing thermal processing to nitrogen and hydrogen-containing environment to enhance hydrogen atom diffusion to increase stability of the polysilicon resistance; (6) forming metal conductive layer on the second dielectric.
Patent TW-382856-B (TW)
Title: Delay time controlling circuit
Inventor: OKAYASU TOSHIYUKI
IPC: H03K3/86
Filed: 1996-10-23
Granted: 2000-02-21
Abstract: A delay time controlling circuit which generates accurate delay time signal and consumes electric power small, with adding simple circuit in the circuit which keeps the delay time of gate predetermined value. The delay time controlling circuit includes: front end delay circuit A 11 and post end delay circuit B 12, each circuit exists in the delay circuit inputting a pulse of predetermined cycle; delay time/duty transition circuit14 which is reset by the pulse generated by delay circuit B12; integrator 15 which translates duty into voltage level signal; delay time controller 16 which control the delay time of the delay circuit in order that duty results in predetermined value; delay time setting voltage DAC 17 which adjusts the set value of the delay time ; logic threshold voltage controlling circuit 18 which generates another delay control voltage, from the delay control voltage of delay time controller 16; logic circuit13 which is a general circuit inside of IC and which delay time is controlled by the delay control voltage.
Patent TW-343999-B (TW)
Title: High density sputtering target for forming ferroelectric film
Inventor: MORI AKIRA
IPC: C23C14/34
Filed: 1996-12-31
Granted: 1998-11-01
Abstract: A high density sputtering target for forming ferroelectric film, which is a sputtering target having a density ratio of over 95.1% and formed of (1) a composite oxide sintered body of Ba and Ti, (2) a composite oxide sintered body of Sr and Ti, or (3) a composite oxide sintered body of Ba, Sr and Ti, which is characterized in that: the S content is limited to be less than 50 ppm.
Patent TW-347408-B (TW)
Title: Radiation curable supersizes
Inventor: GWO SHIN SWEI
IPC: C09D1/00
Filed: 1997-01-18
Granted: 1998-12-11
Abstract: A supersize formulation of a coating grinding agent, which comprises a supersize additive selected from a group consisting of potassium fluoroborate, sodium fluorosilicate, potassium fluoride, iron sulfate, potassium phosphate, molybdenum disulfide and calcium hydrogenphosphate, the supersize additive being dispersed in a liquid, hydrophobic and radiation-polymerizable binder medium which is selected from the group consisting of acrylated epoxy oligomer, acrylated carbamate oligomer and acrylated polyester oligomer and mixtures thereof; in which the radiation means UV light and a radiation by an electron beam having 0.1 to 10 Mrad dosage.
Patent TW-425771-B (TW)
Title: An image compensating device and method
Inventor: SU WEI-MING
IPC: H04N1/401
Filed: 1997-02-15
Granted: 2001-03-11
Abstract: A device to compensate for the white level value of contact image sensor, wherein the analog/digital converter which costs more is replaced by several delicate resistors and analog multiplexers. Each pixel is compensated by digital technology, so that the working speed of the circuit is faster and the sample-hold circuit and the operational amplifier can be eliminated. Therefore, the design of the hardware product is easier and the manufacturing cost is reduced. It comprises: a power supply to provide a plurality of voltage sources with different voltage levels; an analog multiplexer to receive the above mentioned plurality of voltage sources with different voltage levels, and which is controlled by a digital signal to select a voltage output from the above mentioned plurality of voltage sources; an image sensor which can scan the image pixels and output the image voltage VIMG of the pixel, or scan a white level pixel and output the white level voltage Vp of that pixel; an analog/digital converter with two input terminals which can receive the output voltage from the above mentioned analog multiplexer and the above mentioned image voltage VIMG or white level voltage Vp to output the white level gray scale G(x,y) of the pixel or the uncompensated image gray level g(x,y); a microprocessor which can (1) compare the plurality of white level gray scales outputted from the above mentioned image sensor and select the maximum Gmax, and the maximum voltage which the contact image sensor can output is defined to be the value VPMAX corresponding to the x-axis coordinate point pixel of GMAX; (2) the digital signal is set based on the VPMAX value to control the analog multiplexer to select a voltage level which is greater than and the closest to VPMAX as the voltage output Vout; (3) compute the plurality of the white level gray scale G(x,y) to calculate the average value G'(x) of a plurality of the white level gray scale G(x,y); (4) compute the uncompensated image gray level g(x,y) based on G'(x) to find the compensated image gray level g'(x,y).
Patent TW-369497-B (TW)
Title: Apparatus and method for filling and sealing intravenous solution bags in a sterile environment
Inventor: GLINIECKI ROBERT L
IPC: B65B3/17
Filed: 1997-03-07
Granted: 1999-09-11
Abstract: An improved apparatus for filling and sealing sterile bags in a sterile enclosure is disclosed. A turntable rotatably mounted within the enclosure suspends two or more bags. Port tubes extend from the bags, and the bags are suspended from the port tubes. One of the bags is filled with sterile solution within the enclosure and the port tube is sealed by vibration welding. The turntable then rotates and the sequence is repeated on a new bag.
Patent TW-340269-B (TW)
Title: Multiple polarity wideband planar antenna
Inventor: SHENG Y PENG
IPC: H01Q21/24
Filed: 1997-03-17
Granted: 1998-09-11
Abstract: A multiple polarity wideband planar antenna comprising: a soft or rigid circuit board; a front copper foil formed with a plurality of leaf-like patterns, a narrowing opening being formed between two adjacent patterns, a hollow frequency modulation cavity being formed in the leaves, the opening being extended to the cavity forming a number of sets of horn planar antenna in different directions; a back copper foil formed with wave antennas corresponding to each hollow frequency modulation cavity of the front copper foil, one end of each wave antenna being extended from the copper foil forming an individual contact; in which three sets of integrated planar antennas with different directivity are formed according to the corresponding relationship between each set of wave antenna and each horn antenna.
Patent TW-402773-B (TW)
Title: Multielectrode electrostatic chuck with fuses
Inventor: KUMAR ANANDA K
IPC: H02N13/00
Filed: 1997-04-15
Granted: 2000-08-21
Abstract: A failure resistant electrostatic chuck 20 for holding a substrate 35 during processing of the substrate 35, is described. The chuck 20 comprises a plurality of electrodes 25 covered by an insulator 30, the electrodes 25 capable of electrostatically holding a substrate 35 when a voltage is applied thereto. An electrical power bus 40 has a plurality of output terminals 45 that conduct voltage to the electrodes 25. Fuses 50 electrically connect the electrodes 25 to the output terminals 45 of the power bus 40, each fuse 50 connecting at least one electrode 25 in series to an output terminal from the power bus 40. The fuses 50 are capable of electrically disconnecting the electrode 25 from the output terminals 45 when the insulator 30 punctures and exposes the electrode 25 to the process environment causing a current to flow through the fuse 50. A current detector 175 and electrical counter 180 can be used to provide early detection and counting of the number of failures of the electrodes 25 by detecting the current discharges through the fuses 50.
Patent TW-468265-B (TW)
Title: Multi-chip module
Inventor: NAPIERALA DIETER
IPC: H01L25/16
Filed: 1997-04-18
Granted: 2001-12-11
Abstract: The present invention is related to a multi-chip module that has a carrier substrate, in which an IC component and other electronic components are mounted on the installing side. These components are interconnected by way of electrically conductive interconnects, in which electrical through-lines are led from the installing side to the bottom side of the carrier substrate and are joined to soft solder contacts arranged on the bottom side for the electrical connection of the multi-chip module to a structure set carrier. To reduce the thickness of conducting traces on the topside of the multi-chip module, and to decrease the number of layers of the carrier substrate required between an IC component and carrier substrate, a carrier part is arranged. The carrier part has conducting traces and structure components, which are connected to the respective IC component by way of the first terminal pad, and are connected to terminals on the carrier substrate by way of the second terminal pad.
Patent TW-464670-B (TW)
Title: Stabilizer mixtures containing a hindered amine
Inventor: GUGUMUS FRANCOIS
IPC: C08K5/353
Filed: 1997-06-25
Granted: 2001-11-21
Abstract: A stabilizer mixture containing (A) either (A1) at least one compound of the formula, in which R1 is for example hydrogen or C1-C8alkyl; R2, R3, R5 and R6 are for example hydrogen, C1-C30alkyl or phenyl; R4 is for example C1-C30alkyl or 2,2,6,6-tetramethyl-4-piperidyl; and n1 is a number from 1 to 50; or (A2) at least one compound of the formulae, wherein n2 and n2* are a number from 2 to 50; (B) magnesium oxide, magnesium hydroxide, zinc oxide, zinc hydroxide or an organic salt of zinc or magnesium; and (C) either; (C1) an UV absorber or (C2) a pigment or (C3) an UV absorber and a pigment; with the proviso that, when component (A) is at least one compound of the formulae (IIIa) and (IIIb), component (B) is magnesium oxide, magnesium hydroxide or an organic salt of zinc or magnesium. Such a stabilizer mixture is particularly useful for stabilizing a polyolefin against light-induced degradation.
Patent TW-387915-B (TW)
Title: Process for preparing polyethylene terephthalate
Inventor: NODA SEISHI
IPC: C08G63/181
Filed: 1997-09-05
Granted: 2000-04-21
Abstract: Disclosed is a process for preparing polyethylene terephthalate comprising a liquid phase polycondensation reaction step, a precrystallization step and a solid phase polycondensation reaction step, wherein the precrystallization step comprises (A) heating PET chips at a temperature (T1) not lower than Tg and not higher than 180 DEG C, with stirring the PET chips, to crystallize the PET to a crystallinity of at least 30%; (B) heating the PET chips, with allowing them to stand, to a a temperature (T2) in the range of from  (Tbm-40 DEG C) up to Tbm to crystallize the polyethylene terephthalate to a crystalinity of at least 30% , wherein the Tbm is defined as the endotherm starting temperature of a sub-peak from among endothermic peaks observed when the polyethylene terephthalate is heated by means of a differential scanning calorimeter (DSC) at a heat-up rate of 10 DEG C/min; and (C) heating the PET chips with stirring to raise the temperature of the PET chips up to the solid phase polycondensation temperature. Precrystallization of polyethylene terephthalate can efficiently be achieved even in the case of copolymerized polyethylene terephthalate.
Patent TW-412503-B (TW)
Title: Mesoporous silica and its process for preparation and use
Inventor: ROSER JOACHIM
IPC: C09C1/30
Filed: 1997-09-23
Granted: 2000-11-21
Abstract: Mesoporous silica has a specific surface area of the mesopores of at least 500 m<2>/g and a volume of the mesopores of at least 1.0 ml/g and is prepared by converting a silica precursor in a water-containing reaction medium, the reaction medium containing a polymer dispersion.
Patent TW-340889-B (TW)
Title: Folding telescopic prefabricated framing units for non-load-bearing walls
Inventor: RONALD W CAMPBELL
IPC: E04C3/11
Filed: 1997-10-22
Granted: 1998-09-21
Abstract: A prefabricated framing unit for constructing non-load-bearing walls and partitions, having: 1) a lower horizontal element; b) an upper horizontal element; c) a plurality of vertical elements, of which the upper and the lower end are articulated onto the split of said upper and lower horizontal lements; where each of the vertical elements has an adjustable length, including an external element and an internal element, which is included inside the external element and in parallel alignment to the external element, being each of the internal elements sliding inside the external element and in parallel to the external element, for extending or shortening the vertical element, in which the upper end of either the internal or the external element is articulated onto the upper horizontal element and in free sliding with respect to the internal and external elements on the upper end of either of the internal or the external elements; while the lower end of the other of the internal or external lement is articulated onto the lower horizontal element and in free sliding with respect to the internal and external elements on the upper end of either of the internal or the external elements.
Patent TW-392088-B (TW)
Title: Active matrix substrate, liquid crystal apparatus using the same and display apparatus using such liquid crystal apparatus
Inventor: KUREMATSU KATSUMI
IPC: G09G3/36
Filed: 1997-10-17
Granted: 2000-06-01
Abstract: A liquid crystal apparatus comprises an active matrix substrate including a plurality of scanning lines and a plurality of signal lines, transistors arranged respectively at the crossings of the scanning lines and the signal lines and having the source region connected to the corresponding signal line and the gate region connected to the corresponding scanning line and pixel electrodes connected respectively to the drain regions of the transistors, an opposite substrate disposed oppositely relative to the active matrix substrate and a liquid crystal material filled in the space between the active matrix substrate and the opposite substrate. A source region is shared by each pair of adjacently located transistors and connected to the corresponding signal line.
Patent TW-416863-B (TW)
Title: Electrical method for purifying water
Inventor: LIN JE-REN
IPC: B01D35/06
Filed: 1997-12-12
Granted: 2001-01-01
Abstract: This invention describes a process to purify water through electrical filtration. An outer-ring electrical field is properly applied to enhance the filtering material whose surface is negatively or positively charged for adsorption and filtration of the suspended particles and micro-organisms carrying negative or positive charges and thus improving the adsorption-filtration effect of the input water flow.
Patent TW-401427-B (TW)
Title: Polyurethane prepolymers for making polyurethane-urea elastomers having improved dynamic properties, preparation thereof and the elastomers
Inventor: QUAY JEFFREY RAYMOND
IPC: C08G18/66
Filed: 1998-01-20
Granted: 2000-08-11
Abstract: An isocyanate-terminated polyurethane prepolymer comprising the reaction product of a polyisocyanate and a polyol composition consisting essentially of a polyether polyol of 350-2000 equivalent weight and a low molecular weight polyol of 62 to <300 molecular weight, in an equivalent ratio of low molecular weight polyol to polyether polyol o 0.25-2.7:1. A polyurethane-urea elastomer having good dynamic properties can be prepared by reacting the isocyanate-terminated prepolymer with an aromatic amine chain extender at an equivalent ratio of 0.9-1.1:1.
Patent TW-434510-B (TW)
Title: Method for conditionally loading segments of programs
Inventor: WU PEI-JI
IPC: G06F9/06
Filed: 1998-01-18
Granted: 2001-05-16
Abstract: To be used in various configurations, software designs usually have specific code for specific configuration. Conditional compiling is usually used to generate various executable versions from one source code version. A critical limitation of conditional compiling is that the values of configuration parameters must be determined at compile time. This invention discloses a method that conditionally selects segments of programs at load time. An executable file usually contains several sections, which are mainly categorized into text and data. This method allows a section to be associated with a conditional expression that contains load-time configuration parameters. When the operating system links and loads an executable file, it decides which sections to be loaded into main memory in according to the values of configuration parameters and conditional expressions.
Patent TW-441221-B (TW)
Title: Organic electroluminescent device
Inventor: SAKAI TOSHIO
IPC: H05B33/14
Filed: 1998-02-20
Granted: 2001-06-16
Abstract: This invention is to provide an organic electroluminescent (EL) device with a long life and high light-emitting efficiency. An organic compound layer that includes at least an organic light-emitting layer is sandwiched between a pair of electrodes of anode and cathode, and this organic light-emitting layer is formed of two or more layers, wherein these organic light-emitting layers are all doped with a fluorescent substance of the same type or the same color that constitutes the organic EL devices.
Patent TW-426688-B (TW)
Title: Hollow forms of chitosans and method for its production
Inventor: WEI YA-JUNG
IPC: C08B37/08
Filed: 1998-03-06
Granted: 2001-03-21
Abstract: The present invention relates to the preparation of hollow forms of chitosans and their shaping methods. By swelling high polymers of chitosans in acidic solutions containing anionic surfactants, chitosan form colloidal casing with solution inside. After immersion in alkaline solution, high polymertic chitosan with hollow structures can be obtained. The present invention also involves the tretment of powder form of chitosans to form spherical bead; in another aspect for film-like chitosans, the tretment can produce gelatin-like capsules, and still in another aspect for fibrous chitosans, hollow fiber can be obtained.
Patent TW-400592-B (TW)
Title: The semiconductor device, the thin-filmed carrier belt, and its manufacturing method
Inventor: HASHIMOTO NOBUAKI
IPC: H01L23/495
Filed: 1998-03-19
Granted: 2000-08-01
Abstract: This invention discloses a semiconductor device for improving the adhesion of the wiring pattern and the resin that has the convex portion, the thin film sheet of the etched wiring pattern, and the semiconductor chip with electrodes jointed with convex portion. The device also sets the resin of the wiring pattern in the regions outside the convex portion. The wiring pattern and the resin contact face is a rough surface.
Patent TW-373254-B (TW)
Title: Method for prevention of protection layer etch broken hole and light block squeeze out
Inventor: CHEN SHIH-SHIUNG
IPC: H01L21/30
Filed: 1998-04-22
Granted: 1999-11-01
Abstract: A kind of method for prevention of protection layer etch broken hole and light block squeeze out. This invention increases a step for using hydrophile substance to even protection layer, thus proceed to form light block layer which shall not impact uneven thickness due to the concave/convex surface, and the protection concave portion shall not encounter etching due to the light blocking to be too thin, to generate protection broken hole. And using the incompatible characteristics of the two items of hydrophile substance and light blocking layer, to avoid light blocking to flow into concave part of protection layer. Therefore, future alloy production method processing, it shall have light blocking protection layer to force discharge through concave area. The method of this invention, comprising the following method: settling a protection layer on the completed section metallized process on crystal balls; coating a hydrophile substance on the said protection layer, for using in evening the concave part of the protection layer to plane; forming a light blocking layer on the said protection layer; to process micro-image process, to define the said protection layer holes in image; etch the said protection layer; and, to remove the remained on the aforementioned light blocking layer.
Patent TW-380308-B (TW)
Title: Semiconductor device and a process for forming the device
Inventor: JIMING ZAN
IPC: H01L21/28
Filed: 1998-06-24
Granted: 2000-01-21
Abstract: A semiconductor device has a continuously graded portion of a first film, such as a barrier film, that is used within conductive structures, such as interconnects and conductive plugs. The continuously graded portion includes a first element and a second element, such as a refractory metal and nitrogen. The continuous grading has an changing concentration of the first element nearer a more conductive second film. Another semiconductor device includes a first conductive film and a second conductive film that is mostly copper. The first conductive film has a first portion, a second portion, and a third portion. The second portion lies between the first and third portions, and the third portion lies closest to the second conductive film. The nitrogen concentration of the second portion is higher than a nitrogen concentration of each of the first and third portions. Processes for forming the semiconductor devices are also described.
Patent TW-409365-B (TW)
Title: Fabrication method of polycide gate capable of preventing the silicide layer from being peeled off
Inventor: LI TZUNG-HAN
IPC: H01L21/768
Filed: 1998-07-23
Granted: 2000-10-21
Abstract: A method of fabricating polycide gate is disclosed. Firstly, there are formed a polysilicon layer and a silicide layer sequentially on the substrate having a gate oxide. Then, there are formed a multiple insulated layer and a hard material layer sequentially on the silicide, wherein the multiple insulated layer is composed of multiple insulated layers, and the thermal expansion coefficient of these insulated layers is between those of the multiple insulated layer and the hard material layer. The difference between the thermal expansion coefficient of these layers and the hard material layers is decreased layer by layer. Then, there are defined the hard material layer, the multiple insulated layer, the silicon metal layer and the polysilicon layer, so as to form a polycide gate; and there is formed a thin dielectrics on the surface of the polycide gate. Then, there is formed an insulated spacer on the lateral side of the polycide gate having dielectrics, so as to complete the polycide gate.