baber/WOPTO huggingface dataset:
Patent TW-242199-B (TW)
Title: Fabrication method and structure for flash memory with floating gate
Inventor: HORNG YEUN-DING
IPC: H01L27/115
Filed: 1994-02-15
Granted: 1995-03-01
Abstract: A fabrication method and structure for flash memory with trench-type floating gate includes: 1. growing one pad oxide on the silicon layer; 2. depositing the first polysilicon and forming massive polysilicon layer with space by photolithography; 3. forming oxide with high width by chemical vapor deposition, and adhering the oxide to the oxide spacer of massive polysilicon layer by amorphous etching; 4. etching vertical trench on silicon layer; 5. removing the massive polysilicon layer; 6. conducting drain ion implantation by using the oxide spacer as implant stop material, and separately forming N+ drain and N+ source on the trench bottom and between the neighbor oxide spacer; 7. etching to remove oxide spacer and pad oxide; 8. growing tunnel with thin thickness; 9. depositing/doping to form the second polysilicon layer; 10. amorphous etching the second polysilicon layer to convert it to spacer adhering to the vertical wall in the trench; 11. depositing to form dielectric layer and depositing/doping to form the third polysilicon layer and implementing word line mask to make the third polysilicon layer form respective word line.
Patent TW-436293-B (TW)
Title: Aqueous compositions containing an organic peroxy acid
Inventor: NICOLLE REMY
IPC: A61K8/00
Filed: 1994-07-20
Granted: 2001-05-28
Abstract: The invention relates to an aqueous composition which is stable with time, containing an organic peroxy acid and at least one thickening agent in a concentration such that the viscosity of the composition is greater than 100 mPa.s, as well as the use of this composition, in particular as a disinfecting and/or cleaning agent.
Patent TW-289143-B (TW)
Title: Method of metabolizing semiconductor integrated circuit
Inventor: LU HUOO-TIEE
IPC: H01L21/76
Filed: 1994-05-24
Granted: 1996-10-21
Abstract: A method of metabolizing semiconductor integrated circuit, which is used to performing metallization on semiconductor substrate with device structure, comprises the steps of: (1) forming dielectric and patterning node contact on the semiconductor substrate; (2) forming metal layer with metal material in the node contact and the dielectric; (3) implanting ion to predetermined position of the metal layer, making the portion with implanted oxygen ion form insulating oxide, defining the metal conductive layer pattern; (4) forming passivation.
Patent TW-278227-B (TW)
Title: IC packaging device of joint pad method lead frame
Inventor: HWANG JIANN-PYNG
IPC: H01L23/488
Filed: 1995-10-30
Granted: 1996-06-11
Abstract: An IC packaging device of joint pad method lead frame, that consists of die pad, chip, wafer coating, lead and package resin, features that chip is pasted on die pad, lead is across chip, lead frame and die pad frame is bonded by jointing. Next wire bonding the lead and bonding pad on chip, and encapsulating the whole device with resin.
Patent TW-302578-B (TW)
Title: The digital filter bank structure and its application method
Inventor: CHEN YEONG-LONG
IPC: H03H17/02
Filed: 1996-04-10
Granted: 1997-04-11
Abstract: A digital filter bank structure includes: Input signal selecting unit to select output of the outside input signal or one of multi-level low communication signal; Filter bank unit, which is according to a level status control signal to define the level status of current element, in order to receive output signal from input signal selecting unit, then proceed wave filter to output the high, mid and low communication signal and feedback the low signal to the input signal selecting unit ; Band selecting unit to receive each level high, mid, or low communication signal from filter bank unit and decide one band signal for output.
Patent TW-474835-B (TW)
Title: Polysulfone hollow fiber semipermeable membrane
Inventor: SHIMAGAKI MASAAKI
IPC: B01D69/02
Filed: 1996-07-01
Granted: 2002-02-01
Abstract: Respective hollow fiber membranes suitable for use in removing undesired contaminants from blood, in particular in an artificial kidney, have: (1) per membrane area of 1.6 m<SP>2</SP>, in vitro clearances for urea and phosphorus respectively of ≥ 195, and ≥ 180, ml/min, a β2-microglobulin clearance ≥ 44 ml/min and an albumin permeability ≤ 0.5%; (2) an albumin permeability ≤ 1.5% and an overall mass transfer coefficient Ko ≥ 0.0012 cm/min; and (3) a vitamin B12 dialyzance of ≥ 135 ml/min and an albumin permeability ≤ 3%. The membranes can be prepared by spinning hollow fibers from a spinning solution comprising a polysulfone, a hydrophilic polymer, a solvent and water, the spinning solution having a viscosity x at 30 DEG C of 25-130 poise and a quantity y % of water given by: -0.01x + 1.45 ≤ y ≤ -0.01x + 2.25. The membranes can be incorporated into a hemodialyzer module by a method in which they are preimpregnated with a wetting agent, thereafter kept separate from one another by spacers and then inserted in the module.
Patent TW-400581-B (TW)
Title: Vertical compensation semiconductor device and method for improving its current in closed status
Inventor: LIN JIUNG-WEI
IPC: H01L21/322
Filed: 1996-10-02
Granted: 2000-08-01
Abstract: The invention is related to a vertical compensation semiconductor device, which includes a channel region, a source/drain region and a high-resistance material region, wherein such a high-resistance material region is vertically distributed between the channel region and the source/drain region to form a vertical compensation region. This invention is also related to a method for improving the close current of the semiconductor device, which is to let the high-resistance material distributed vertically between the channel region and the source/drain region to form a vertical compensation region in order to lower the close current of the semiconductor device.
Patent TW-451100-B (TW)
Title: Non-chiral smectic C liquid crystal display
Inventor: LEE SIN-DOO
IPC: G02F1/137
Filed: 1996-10-19
Granted: 2001-08-21
Abstract: A liquid crystal display according to this invention has a pair of transparent electrodes, a non-chiral smectic liquid crystal therebetween, a polarizer and an analyzer which are attached to the electrodes. The smectic layers are perpendicular to the electrodes and the liquid crystal has a twisted structure where the twist angle is twice the molecular tilt angle. In this configuration, the molecular director is forced to continuously rotate along the cone surface formed by the requirement that the molecules are tilted with respect to the layer normal and pinned at the surfaces. The basic principles of the optical modulation in the present invention are similar to those in twist nematic liquid crystal structures.
Patent TW-342365-B (TW)
Title: A printing mask with a plastic printing plate and process for producing the same
Inventor: KINOSHITA SHINGO
IPC: B41F15/36
Filed: 1996-12-16
Granted: 1998-10-11
Abstract: A printing mask with a plastic printing plate, which is used as the printing mask of plastic plate for a plate material, and is characterized in that: the plastic plate is directly attached to the mask frame.
Patent TW-352473-B (TW)
Title: Method and process for making ROM
Inventor: WEN RONG-MAO
IPC: H01L29/786
Filed: 1997-02-25
Granted: 1999-02-11
Abstract: A method and process for making ROM comprises the steps: (a) to provide a first substrate with pad oxide layer on it; (b) the pad oxide layer will become a photoresist layer, defined with the photoresist pattern and to build a pluarlity of grooves in parallel to the first direction; (c) the photoresist layer becomes a mask, using a first electric ion to dope so as to form a plurality of barriers, then remove the photoresist layer; (d) to form a first insulation layer on the substrate and the groove surface; (e) to form a first conductive layer on the first insulation layer and fill up the groove; (f) back etching the first conductive layer until the first conductive layer has the same height of the substrate surface; (g) to remove the first insulation and the pad oxide layer till to expose the substrate; (h) to build a second insulation layer on the substrate and the first conductive layer; (I) to create a second conductive layer on the second insulation layer; (j) to anneal the second conductive layer; (k) to implant ion on the second conductive layer and adjust the threshold voltage; (l) to define the pattern on the second conductive layer and to partition a pluraltiy of source electrode and drain eelctrode regions in parallel to the first direction, and a plurality of paths of source electrode and drain electrode region in parallel to the first direction and cross the second direction at a defined angle, a pluarality of opening occurred at the cross section sturcture in the source electrode and drain electrode region; (m) to form a third insulation and fill the opening with the third insulation layer; (n) to perform a second electric ion inplant in the source electrode and drain electrode regions; (o) to proceed numbering source electrode and drain electrode region contact window sequence and inplant ion on the paths; (p) to create and to planarize a fourth insulation layer; (q) to define the pattern on the fourth insulation layer, to build a plurality of gate region contact window and a plurality of source electrode and drain electrode region contact window and to expose the gate region contact window out of the first conductive layer, the source electrode and drain electrode region contact window out of the source electrode and drain electrode region; and (r) to fill in a third conductive layer among the gate region contact window and the source electrode and drain electrode region contact window to form a plurality of electrodes for both the gate region and source electrode and drain electrode region.
Patent TW-482797-B (TW)
Title: Process for forming polyisocyanate-based foam and product formed thereby
Inventor: STEVENSON RICHARD
IPC: C08J9/14
Filed: 1997-03-03
Granted: 2002-04-11
Abstract: A blowing agent for use in preparing a polyisocyanate-based foam which comprises a major portion of HCFC-123, a minor portion of HCFC-141b, and hexane and/or octane.
Patent TW-375614-B (TW)
Title: New aryl-glycin-amide derivatives, process for preparing them and pharmaceutical compositions containing these compounds
Inventor: ESSER FRANZ
IPC: A61P37/00
Filed: 1997-03-06
Granted: 1999-12-01
Abstract: An aryl-glycin-amide derivatives of general formula I or their pharmaceutically acceptable salts, wherein Ar is unsubstituted or mono- to penta-substituted phenyl, or unsubstituted or mono- to bi-substituted naphthyl (wherein the substituents of phenyl and naphthyl are each independently halogen (F, Cl, Br, I), (C1-4) alkyl or O-(C1-4) alkyl, or Ar is phenyl substituted by -O-CH2-O- or -O-(CH2)2-O-; R1 and R2 together with their bonded N is a ring of following formula (II) or (III), wherein r, s and t are 2 or 3; R6 is H, (C1-5) alkyl, (C3-5) alkenyl, alkylenyl, hydroxy (C2-4) alkyl, methoxy (C2-4)alkyl, di (C1-3) alkyl amino (C2-4) alkyl, amino (C2-4) alkyl, amino, di (C1-3) alkyl amino, monofluoro-pan fluoro (C1-2) alkyl, N-methyl hexahydropyridyl, pyridyl, pyrimidyl, pyridazinyl, pyrimidinyl, or -CH2-C(O)NR14R15 group, wherein R14 is H or (C1-4) alkyl and R15 is H, (C1-4) alkyl, (C3-6) cycloalkyl, hydroxy (C2-4) alkyl, alkoxy (C2-3) alkyl, phenyl (C1-4) alkyl, or R14 and R15 together with their bonded N form a ring (1-pyrrodinyl, 1-hexahydro pyridyl, N-morpholinyl or 1-methylhexahydro pyridazinyl-4-yl); R7 is as defined in one of (a) to (d), (a) hydroxyl, (b) 4-1-hexahydro pyridyl hexahydro pyridyl, (c) (formula), wherein R16 and R17 are each independently H, (C1-4) alkyl, (C3-6) cycloalkyl, hydroxy (C2-4) alkyl, (C1-3) alkoxy (C2-4) alkyl, phenyl (C1-4) alkyl or di (C1-3) alkyl amino (C2-4) alkyl, or only when R16 is H or (C1-4) alkyl, R17 is possibly -CH2C(O)NR18R19, wherein R18 and R19 are as defined for R14 and R15 above; (d) (formula), wherein R20 is H, (C1-4) alkyl, (C4-6) cycloalkyl or -CH2C(O)NR21R22, wherein R21 and R22 are as defined above for R14 and R15; R8 is H, R9 and R10 are each independently (C1-4) alkyl; R11 is H, (C1-5) alkyl, (C3-5) alkenyl, alkylenyl, hydroxy (C2-4) alkyl, methoxy (C2-4)alkyl, di (C1-3) alkyl amino (C2-4) alkyl, amino (C2-4) alkyl, amino, di (C1-3) alkyl amino, monofluoro-pan fluoro (C1-2) alkyl, N-methyl hexahydropyridyl, pyridyl, pyrimidyl, pyridazinyl, pyrimidinyl, or -CH2-C(O)NR23R24 group, wherein R23 and R24 are as defined above for R14 and R15; R3 is H or (C1-4) alkyl; R4 is phenyl (C1-4) alkyl or naphthyl (C1-4) alkyl, wherein phenyl can be substituted by 1 to 3 substituents, wherein these substituents are each independently halogen (F, Cl, Br, I), (C1-4) alkyl, O-(C1-4) alkyl, CF3, OCF3, or NR27R28 (wherein R27 and R28 are each independently H, methyl or acetyl); and R is H, (C1-4) alkyl, or (C3-6) cycloalkyl.
Patent TW-371793-B (TW)
Title: Heat sink apparatus
Inventor: AMOU MITSURU
IPC: H01L23/367
Filed: 1997-06-06
Granted: 1999-10-11
Abstract: A heat sink apparatus for cooling a highly heat-generating semiconductor device in which a base of a heat sink is made larger in volume in its central portion than in its peripheral portion.
Patent TW-337562-B (TW)
Title: A circuit and method for modulo address generation with reduced circuit area
Inventor: MIN-JOONG RIM
IPC: G06F9/355
Filed: 1997-09-09
Granted: 1998-08-01
Abstract: A modulo address generator including: an adder set for the receiving of current address value and an address increment value to generate an incremented address value plus an adder/subtracter circuit for the adding of a data region size value to the incremented address value; an adder/subtracter set for the receiving of incremented value, corresponding to the size value of a specific data area and the address increment value sign bit where the adder/subtracter further set a negative value to correspond the sign bit to add the incremented address to the data area size value and the negative of the corresponding sign bit and subtracts the data region size value from the incremented address value when the sign is positive in order to generate a revised address value and an output selection circuit for the selection of either the incremented address value when the sign bit is negative, or the revised address value when the sign bit is positive, for the comparison to a minimum address of the data region in order to generate a comparison result value properly set, in case of a greater address value selected than or equal to the minimum address, to a negative value and combined with the sign bit for the selection of one of the incremented address value and the revised address value for output as the next address value.
Patent TW-351699-B (TW)
Title: Method and installation for the manufacture of plastic tubes with biaxial stretching and plastic tube thus obtained
Inventor: PREVOTAT BERNARD
IPC: F16L47/06
Filed: 1997-09-11
Granted: 1999-02-01
Abstract: A method for the manufacture of plastic tubes, in which the tube blank (Te) brought to a temperature near its molecular orientation temperature is subjected to biaxial stretching as a result of the radial expansion of the tube blank within a forming barrel (2), with the formation of a blister at one end of the tube and controlled displacement of the blister as far as the other end of the tube, and with longitudinal stretching; the radial expansion is carried out in at least two phases; (a) a first phase during which the tube blank (Te) is inflated to an intermediate diameter (Di) determined by a double-walled casing(21) introduced into the forming barrel(2), with a hot fluid circulating between the two walls of the casing(21), and, subsequently, the casing (21) is progressively taken out of the forming barrel(2) in order; and (b) during a second phase, to allow the radial expansion of the plastic tube to the inside diameter of the forming barrel (2) and the longitudinal stretching of the said tube.
Patent TW-354260-B (TW)
Title: Filter element for filter unit
Inventor: MORIYA MASAYUKI
IPC: B01D29/07
Filed: 1997-10-17
Granted: 1999-03-11
Abstract: The present invention provides a filter element for a filter unit that is disposed in a fluid flow channel for filtering contaminants contained in fluid, where the filter element for a filter unit is characterized in comprising a plurality of filters having different densities, the plurality of filters being placed in series in the ascending order of density from the inflow side towards the discharge side of the fluid.
Patent TW-405123-B (TW)
Title: Composite mode substrate voltage generation circuit for dynamic random access memory
Inventor: CHOI JOO-SUN
IPC: H01L21/8242
Filed: 1997-10-30
Granted: 2000-09-11
Abstract: A composite mode substrate voltage generation circuit for a DRAM which has a memory cell block and a peripheral circuit block formed on a single substrate. The circuit comprises a back-bias voltage generator for generating a first back-bias voltage in response to a normal refresh mode control signal or a second back-bias voltage in response to a self-refresh mode control signal and supplying the generated first or second back-bias voltage to the memory cell and peripheral circuit blocks, a first voltage level detector for detecting a level of the first back-bias voltage from the back-bias voltage generator, comparing the detected level of the first back-bias voltage with a first reference voltage level and controlling a voltage pumping operation of the back-bias voltage generator in accordance with the compared result, and a second voltage level detector for detecting a level of the second back-bias voltage from the back-bias voltage generator, comparing the detected level of the second back-bias voltage with a second reference voltage level and controlling the voltage pumping operation of the back-bias voltage generator in accordance with the compared result. A self-refresh operation can stably be performed at low power consumption, resulting in an increase in refresh efficiency of the DRAM.
Patent TW-362270-B (TW)
Title: Electroplated interconnection structures on integrated circuit chips
Inventor: ANDRICACOS PANAYOTIS C
IPC: H01L23/50
Filed: 1997-12-16
Granted: 1999-06-21
Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
Patent TW-373379-B (TW)
Title: Image scanner having DC motor
Inventor: Li jun-yan
IPC: H04N1/04
Filed: 1998-01-16
Granted: 1999-11-01
Abstract: This project provides a kind of image scanner having DC motor, for scanning a scanning object, wherein the said scanner comprised: an optical mold set, for using in projecting an initial optical signal to the said scanning object, and receiving a scanning object optical signal generated from the said scanning object reacting to the initial optical signal; and a DC motor, for generating a relative dispositioning from the said scanning object and the optical mold set, making the said optical mold set able to scan the scanning object in successive rows.
Patent TW-367461-B (TW)
Title: Programmable display device
Inventor: NAKAMURA SATOSHI
IPC: G09G5/39
Filed: 1998-01-21
Granted: 1999-08-21
Abstract: It comprises a main CPU, a main memory for storing the programs, display data and other data, a data processing circuit for performing a processing to convert the display data in the main memory to the data format for the display, a display memory section for storing the converted display data, an output processing circuit for performing a processing to output the display data on the screen a DMA for performing a data access to the main memory, a program memory, a data memory, a display processor for interpreting the commands/data described in the program memory and the data memory and transferring the display data according thereto, and a sync signal generating circuit.
Patent TW-379520-B (TW)
Title: Detaching apparatus and detaching method for components of printed circuit boards
Inventor: YOKOYAMA SADAHIKO
IPC: H05K13/04
Filed: 1998-03-03
Granted: 2000-01-11
Abstract: A detaching apparatus including a detaching unit that applies a shear force to the components which is in parallel with the mounting face of components, particularly the detaching unit having a pair of  rotary cylinders mutually parallel each other and a predetermined space formed in between the rotary cylinders. The components can be effectively detached by applying the shear force to the components when the printed circuit board inserted with components is led into the space in between the rotary cylinders.
Patent TW-417301-B (TW)
Title: Method for production of semiconductor device
Inventor: NISHIKAWA NOBUYUKI
IPC: H01L21/822
Filed: 1998-06-04
Granted: 2001-01-01
Abstract: The method of the production of a semiconductor device including the step of forming the dielectric film on or above the semiconductor substrate, placing the semiconductor substrate and the dielectric film in the atmosphere of reduced pressure and introducing into  the atmosphere of reduced pressure the reaction gas for the deposition of metal or metal nitride and the oxidizing gas thereby forming the oxygen-containing conductor film formed of metal or metal nitride on the dielectric film.
Patent TW-428415-B (TW)
Title: Panel-form loudspeakers
Inventor: MORECROFT DENIS
IPC: H04R7/06
Filed: 1998-07-03
Granted: 2001-04-01
Abstract: A loudspeaker comprises a panel member (11, 21, 31, 41, 61, 71, 81, 91) as resonant acoustic radiator relying on bending wave action and a driver (12, 22, 32, 42, 62, 72, 82, 92) coupled to the panel member to cause bending waves therein. The panel member has its mass and/or bending capability of the panel member locally altered or otherwise different, particularly locally of the driver as coupled to the panel member. Local holes (16, 26, 36, 46), affixed mass (66) or affixed damping material (76) are effective to reduce high frequency due to drumming effects at the driver coupling (17, 37, 47, 67, 77, 87).
Patent TW-393765-B (TW)
Title: Semiconductor memory
Inventor: OSHIMA SHIGEO
IPC: G11C11/407
Filed: 1998-08-12
Granted: 2000-06-11
Abstract: This is a semiconductor storage device that is capable of operating with some margin of a sufficient cycle time even when latency decreases. Clock pulse CLK is supplied to an input buffer circuit 11a. A delay circuit 12a has a delay time which corresponds to a difference between the cycle time when a latency clock pulse CLK at CL=3 and that when at CL=2. When CL=2 is set, a transfer gate 12c outputs a delayed clock signal in the delay circuit 12a as a clock signal CLK2, and executes an operation in correspondence to a second stage of CL=3 by this clock signal CLK2.