Patent GB-1496083-A (GB)
Title: Computer systems
IPC: G06F9/38
Filed: 1975-01-29
Abstract: 1496083 Pipe-line processor COMPUTER GES KONSTANZ mbH 29 Jan 1975 [31 Jan 1974] 3974/75 Heading G4A A data processing system includes an instruction pipe-line a1-a5 and is arranged to process, in logic unit 2, two or more independent instruction streams each comprising a series of instruction groups each of which includes a predetermined number (which may be different for the various streams) of instructions and terminates with an instruction which requires a substantial waiting time, e.g. a branch instruction. Each instruction stream has an associated pair of buffer stores 11, 51 and 12, 52 one pair being connected to the pipe-line by switches S1, S2. When a branch instruction is detected in the pipe-line at stage a2 switch S1 unconditionally connects the other buffer 11, 12 to the pipe-line so that an instruction group from the other stream can be handled and the delays caused by the branch instruction reduced. As described a first instruction stream A associated with buffers 11, 51 has 6 instructions per group, there being 6 stages in the buffer 51. At the end of the fourth cycle instruction A1 is in stage a4 from where it issues an access request for data from store 3 via secondary pipeline b1-b3 which may be a delay line, the stages of the secondary pipe-line being used, e.g. for virtual-real address translations, testing whether the store is accessible &c. The access request takes 3 cycles to reach stage b3 and, it is assumed, a further 5 cycles for the store to be accessed i.e. 12 cycles in all. The instruction A1 reaches the last stage of buffer 51 after cycle 11 and then has to wait for one cycle until the data reaches logic unit 2 from store 3. The instruction is then processed, it being assumed that on average each instruction requires 2 cycles within logic unit 2 for processing. The instructions are processed in this way except that the final branch instruction in the group is detected at stage a2 causing stage al to be cleared and buffer 12 for instruction stream B to be connected to the pipe-line. The first instruction of stream B which has three instructions per group reaches stage a4 at the end of cycle 11 and initiates a store access as above. Simultaneously the branch instruction SB is detected in stage a2 causing a switch to buffer 11. However no A instructions are available until the branch instruction SA from the first group has been processed. When the branch instruction has been processed an access for the next instruction is initiated by unit 41 and the instructions from the first B group are passed from buffer 52 to logic unit 2. It is assumed that instructions are stored in a fast access store so that generally after 3 cycles the next A instruction group is passed to buffer 11 and thence along the pipe-line. The details of the above procedure may be varied in accordance with various assumptions as to the time spent processing each instruction in logic unit 2, the access time of store 3, whether or not a fast access store is provided for instructions and/or data, and the probability of data being present in the fast store, the lengths of the pipe-lines, the number of instructions in the groups &c., it being stated that the present arrangement is substantially more efficient (in terms of the time spent processing as opposed to waiting) than single instruction stream systems and unconditionally switched systems in which instructions from the two streams are fed alternately to the pipe-line.