Patent GB-1193328-A (GB)
Title: Improvements in Electrical Converter Plants
Inventor: DYBVIG ARNE
IPC: H02M7/162
Filed: 1967-10-05
Abstract: 1,193,328. Converting; control of D.C. motors. ALLM€NNA SVENSKA ELEKTRISKA A.B. 5 Oct., 1967 [6 Oct., 1966], No. 45456/67. Headings H2F and H2J. In a system comprising two converters whose D.C. outputs are connected in antiparallel and pass current alternately in opposite directions through a load (e.g. a reversible motor), the length of the control pulse of each converter is compared with a reference pulse and if shorter the corresponding converter is blocked. In Fig. 1 the two converters 1, 2 are energized by pulses from units 3, 4, giving, e.g. six pulses per cycle the timing of which depends on the value of a voltage Us. The A.C. inputs to the converters are monitored at 7, 8 and rectified at 7<1>, 8<1> and compared (alternately) in a unit 5 with a reference voltage UR. The difference is amplified and fed to the pulse-generators 3, 4 in opposite polarities. The rectified voltages from 7<1>, 8<1> are also applied to threshold devices 13, 14 (Fig. 1a) which give outputs when these voltages exceed a predetermined level. These outputs are compared in units 19, 20 with the outputs of the monostable circuits 23, 24 and control two bi-stable circuits 11, 12 to be in their " 0 " states if the pulses from 13, 14 are longer but in their "1" states if the pulses from the monostable circuits are longer. When the bi-stable circuits are in their " 1 " states gates 9 and 10 (Fig. 1) are blocked to prevent firing pulses from reaching the converters 1, 2 but a change to the " 0 " state opens one of these gates to allow the corresponding converter to operate. The two bi-stable circuits are crosscoupled through time-delay units 21, 22 (Fig. 1a) so that they cannot both be in the " 0 " state simultaneously. Thus one converter cannot be turned on until the other has been turned off, after a delay equal to the interval between two firing pulses. The bi-stable circuits output also control differentiating circuits 15, 16 which permit triggering pulses from the generators 3, 4 to fire only one of the monostable circuits 23, 24 at a time. When the value of the reference UR is low the pulses from 13, 14 will always be shorter than the monostable outputs and the system will oscillate, connecting each converter in turn to the load, the mean value of the current in the latter corresponding to the value of UR. For starting, the bi-stable circuit 11 is initially triggered to its " 0" state through a differentiating circuit 26, this path being inhibited in operation by an OR-gate 25 which will always have one input energized whatever the state of the circuit. The difference between the output voltages at the moment of changeover is compensated by feeding the error signal US via a function generator 27 to control the pulselengths of the monostable circuits 23, 24 according to the magnitude of the control voltage. The above circuit ensures that after being unblocked, a converter will not be re-blocked until at least one commutation has taken place. This prevents false switching due to the first current pulse being short on account of the converter being switched on at a particular point in the commutation cycle. If it is desired to block both converters, an external signal can be arranged to set both bi-stable circuits in the " 1 " state.