Patent GB-794633-A (GB)
Title: Electronic computing system
IPC: G06F15/78
Filed: 1956-05-08
Abstract: 794,633. Digital electric calculating apparatus. BENDIX AVIATION CORPORATION. May 8, 1956 [May 18, 1955], No. 14291/56. Class 106 (1). A calculator having a rotary device with a plurality of storage locations adapted to contain numerical data, is characterized by the combination of means for transferring data between the storage locations to perform arithmetic and logical operations thereon in accordance with a flexible programme, and means for transferring data between certain of the storage locations to perform operations in accordance with a fixed, programme of integration, whereby results from the arithmetic and logical operations can be used as data for an integration operation and vice versa. General. A constantly-rotating magnetizable drum provides all the data-storage facilities of the computer including fourteen tracks, referred to as " magnetic storage circuits " 0 to 13, Fig. 1, each providing for the storage of 108, 29-digit words, and forming the main store for general-purpose computing, five similar tracks 14 to 18 available both for general purpose computing and also for use with differential analysis control circuits DA, magnetic registers I and II each with a capacity of only four, 29-digit words to provide rapidaccess storing facilities, and other, storage tracks forming parts of the arithmetic circuits. The accumulator A is connected not only to the main buses EB and LB but also accepts data from sign control circuits and delivers data to input-output circuits O. Multiplication and division by repeating methods are performed by numerical circuits N. Control circuits I and C implement programme commands under the control of timing circuits T which, in addition to a basic digit clock pulse CP, produce special pulses at the first, second, 13th, 28th and 29th digit times, at the first digit position of alternate words, at the end of every fourth word, and once every drum cycle. Programming and control circuits. The sequence of command words constituting the programme of computation is normally entered in storage circuits 0 and 1, Fig. 1, storage circuit 0 being provided with switching means to receive data from the input-output circuit O. The make-up of a 29-digit command word is shown in Fig. 17. The first digit indicates whether a single or double-lengthword is being dealt with, digits 7 to 11 indicate its address in the store, and digits 2 to 6 determine its destination. The first thirteen digits of each command word are entered into a shifting register I11 ... I26, Fig. 18, by metering thirteen shift pulses to the register as the command word is being read from store. According to the resulting binary settings of the trigger circuits I11 . . . I26, output control signals are passed by one gate in each of four groups of gates D0 ... D7, DU ... DX; S0 . . . S7, SU ... SX influenced by the triggers. The interpretations of the various possible combinations of signals from these gates is set out in Fig. 19. Trigger circuits I11 and I12, which register the twelfth and thirteenth digits of a command, are interpreted in conjunction with the condition of gates S7 and D7, as shown in Fig. 22. They control the sign control circuits X, Fig. 1 (Fig. 23, not shown), through which all circulating numerical information is passed, modifying the sign digit, complementing numbers, or passing them unchanged 'according to the initial sign of the number and the operation to be performed upon it during transfer. The time of the next command is determined from digits 14 to 20 of the command word and whether it is to be implemented immediately or deferred, is indicated by digit 29. If deferred, the time of transfer is defined by digits 22 to 28. These times are interpreted by a counting process. After entering an appropriate correction number, the special thirteenth digit clock pulse is counted causing the number derived from command digits 14 to 20 to be increased by one each word cycle until it overflows into the 21st digit position. This changes the control circuits C from a " wait command " to a " read command state. If digit 29 indicates a deferred command a similar counting process now starts in positions 22 to 28 until overflow causes " read command " to change to " transfer ". This occurs immediately if digit 29 indicates an immediate transfer, the number in digit positions 22 to 28 then indicating the number of words to be transferred by one command. The breakindicating digit position 21 is utilized to stop the machine, the presence of a signal requiring also the manual operation of a switch to effect a halt. Arithmetic circuits. The accumulator (Fig. 24), comprises a circulating memory loop including a length of magnetic track A10 sufficient to store a 29-digit word. Significant digit signals picked up by a read head A11 are passed via an amplifier A12 to set a trigger circuit A13 which also receives resetting clock pulses CP. Output signals on line A14 go via a buffer-inverter A15 to the input of a binary adder A16, the output signals from this passing via a further amplifier A18 to the write head A19. Entry of data into the accumulator circuit requires significant signals on lines D7 and DV simultaneously (see Fig. 19) which open a gate A23 to allow signals from bus LB (see Fig. 1) to pass via a buffer-inverter A25 to the adder A16. Here they will normally be added to the circulating data entering via A15, but in the case of a transfer of information into the accumulator to replace the circulating data a signal passes a gate A26 which serves to lock the buffer-inverter A15 in the zero state while the hew data replaces that read from the track. Read. out from the accumulator is effected when signals occurring simultaneously on lines S7, SU open a gate A21 communicating with the bus EB (see Fig. 1). A signal on the terminal CS allows the accumulator to be used as a oneword delay by routing information from IB through A35, A25, A16, A18, A19, A10, A11, A12, A13 and A37 to a gate A34, while the buffer-inverter A15 is locked in the zero condition. Another feature enables a number placed in the accumulator to have digits added to it until a predetermined number of additions have been effected. It is also possible to enter data under manual control. The binary adder A16 is of the type in which both positive and negative representations of the digits to be added are applied to the input terminals BA1, BA2, Fig: 11, setting trigger circuits BA5, BA6 which, together with a " carry "-registering trigger BA7, are interconnected with coincidence gates BA4, BA8, BA10, BA11, so as to cause one of these to pass a significant pulse to the output terminal BA3 each time the sum of the three digits is 01 or 11. GatesBA9andBA12 control the carry trigger BA7 according to whether or not a significant pulse is to be carried over into the next higher denomination. Further circuits (Fig. 26) provide (i) a multiplicand or divisor register (track N53), (ii) a product or dividend register (track N10), and (iii) a multiplier or quotient register (track N42). Each of these comprise circulating loops with entry and exit gates similar to those associated with the accumulator, the product/dividend register, however, being the only one which includes a binary adder N16. Information circulating in the other two registers can be processed or shifted by varying the length of the circulating loop (e.g. by momentarily introducing a buffer-inverter N50 and trigger circuit N52). Examples of multiplication and division by repeating methods are described with reference to Figs. 27 and 28 (not shown). Differential analysing circuits. The solving of differential equations is performed in a digital manner by a network of interconnected integrating systems each controlling the flow of data between certain of the magnetic storage circuits. The basic theory and operation of this section of the computer is described in detail in Specification 748,267. Each integrating system comprises a Y register DA12, Fig. 36, which accumulates signals representing increments #Y, coupled through a transfer system DA18, controlled by #X signals, to an' R register DA14 which accumulates the Y values received on the occurrence of each AX pulse and gives out a #Z signal upon each overflow of the register. This output normally forms the #X input to a further integrating system, as shown diagrammatically in Fig. 37, and several such integrator-multiplier combinations would be combined to perform differential analysis. The values R, Y, AX, and #Y are stored on magnetic tracks 14 to 17 respectively, Fig. 38. A " one " digit AX signal picked up from the track 16 must coincide with a similar signal from a further track DA20 which passes from a read head DA23 via an amplifier DA24, trigger circuit DA25, and a recirculation control circuit DA26, to the AX register DA30, before this accepts an entry. The circuit DA26 serves to delay circulating data by one digit position at a time when integration is in progress, thereby effecting a precession of the signals on the magnetic track DA20. The sign of the #X digit is determined by whether or not a coincident signal is picked up from another track DA21. This signal, if present, indicates a positive AX, and is passed through an amplifier DA28 and trigger circuit DA29 to another recirculation control circuit DA31 from; which it passes to the #X register DA30. AY signals from the magnetic track .17 are applied to the #Y register DA32 which also receives signals from the recirculation control. circuits DA26 and DA31. Integration is performed during the second and subsequent even word times. Assuming the presence of a AX digit, the #Y information is added to the Y value from track 15 in an adder DA36, and they new value of Y is then added to R information taken from the track 14 in an adder DA37. These new values of Y: and R-are then written into their respective storage tracks 15 and 14. Info