Patent GB-1106910-A (GB)
Title: Improvements in redundant analog failure correction and detection process and apparatus
IPC: G06G7/14
Filed: 1965-11-18
Abstract: 1,106,910. Electric analogue calculating. GENERAL ELECTRIC CO. 18 Nov., 1965 [23 Nov., 1964], No. 49026/65. Heading G4G. [Also in Divisions H3 and H4] In a data control process for selection of the median signal of plural unbalanced redundant analogue input signals, three input signals A, B, C (Fig. 2) are applied through summation units 12, 22, 32 to each of three median selecter units 11, 21, 31 to produce identical outputs in the absence or failure of input signal or of median selection. Balancing signals #A, #B, #C are derived by subtracting each redundant signal A, B, C from the median output at 13, 23, 33; introducing a time lag in the difference signal and summing the lagging signals with the respective input signals to develop corresponding balanced redundant signals A+#A, B+#B, C+#C so that if input B has median value identical with the output signals and the remaining signals are bracketed about B, a fall in A will leave A + #A slightly less than B, while C+#C slightly exceeds B, with #B=C; so that the median output signal remains unaffected while B is constant. A failure causing B<A + #A causes the latter to define median value while if B > A + #A causes C + #C to define the median value. Persistance of failure causes #A or #C to decrease under control of the time lag 14 or 34 until the median value output is defined by A or C. The system follows normal changes of value of B, and may be extended to median selection from 5 inputs. The system is applicable (Fig. 3, not shown) to pulse-width modulated redundant input signals A, B, C recurrent at a fixed rate with a duty cycle deviating from 50% in proportion to the positive or negative value of the variable; the summation with balancing signals #A, AB, #C being performed in conventional servo preamplifiers and the output being developed as a pulse width modulated positive signal persisting for the duration of any two input pulses. The subtraction circuits (Fig. 4) have parallel branches operating on bi-polarity signals, receiving the median, selector output in common and complementary outputs from the servo-amplifier, while the negative branch signals are inverted and combined with positive branch signals in corresponding summing amplifiers (Fig. 5) supplying dual polarity signals to the servo pre-amplifiers. The subtraction circuit outputs are fed through isolation diodes to operate a common failure detector/indicator (Fig. 6) responsive to the most positive signal. Fig. 4 shows a suitable subtraction circuit converting the algebraic difference of width between two pulse width signals into a proportional output signal, the smaller signal being inverted. Both signals are injected over diodes 77, 78, into transistor 80 which conducts when the inputs are both positive and when the balanced signal exceeds the median selector output signal in the positive branch, and vice versa in the positive branch. Conductive switches on current generator transistors 81, 82 wherein 81 is held off by positive bias resistor 83 by shorting resistor 84, whereby the base voltage of 81 drops to that set by Zener diode 85 and coupled diodes 86, 87, so that the resultant base voltage of 81 is lowered by the drop across the coupling diodes, which temperature compensate the base emitter diodes of 81, 82. The gain of the current generator is determined by resistor 88 and the voltage across Zener diode 85, and the pulse current voltage drop across capacitor 89, and the input impedance of the succeeding summing amplifier represents the subtraction voltage output with a time constant # 1 second; capacitor 89 charging by the pulse error signal and discharging for the remainder of the pulse width period to convert the pulsed signal from 81, 82 to a direct' voltage representing the difference of the input signals. Fig. 5 shows a suitable summation amplifier, wherein positive and negative branch inputs are fed to terminals 91, 92 of which the latter is connected to one base of a dual transistor forming a high gain unity feedback amplifier 95 together with feedback resistor 93, while the former is connected to the remaining base and load resistor 96. The second emitter of the transistor is connected to the base of transistor 97 whose emitter energizes feedback resistor 93, and the summed outut is attenuated by resistors 98, 99 and appears at output 100. Fig. 6 shows a failure indicator circuit wherein input 101 is applied to the base of emitter follower transistor 102 driving RC low-pass filter 103, 104 and base 106 of differential dual transistor 105, whose base 107 is energized from a Zener diode stabilized voltage divider over temperature compensating diodes 108, 109. When the input exceeds the set level, collector 112 conducts, transistor 113, conducts and silicon control rectifier 115 fires to operate an indicator lamp (not shown) and remains fired until reset by zeroizing or track biasing its anode over diodes 114, 117. The system is also applicable (Fig. 8, not shown) to amplitude variableredundant analogue voltage signals in which identical balancing channels balance corresponding input signals A, B, C and supply-balanced signals A + #A, B + AB, C + #C to the remaining channels, and median selection is performed by D.C. coupled current limited transistorized amplifiers with a common output impedance giving the median output signal; balancing being conducted by subtracting the appropriate input from the median selector output introducing capacitative lag, and feeding back the amplified signal to the operational amplifier of the median selector. The system is stated to be applicable to mechanical analogue signals.