Patent GB-1016941-A (GB)
Title: Selection system for circuits or electrical equipment
IPC: H04Q3/00
Filed: 1964-01-31
Abstract: 1,016,941. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. Jan. 31, 1964 [Feb. 1, 1963], No. 4209/64. Addition to 946,263. Heading H4K. In an automatic exchange system having a connection network and a route-selection network which simulates the connection network and in which a free path between endmarked points of the selection network is chosen by successively blocking a proportion of all the possible free routes between said points until only one route remains, the block is effected by applying suitable control potentials to the inlets of a decoding matrix whereby corresponding potentials are obtained from the outlets of the matrix, which potentials are then used to control the equipment of the selection network. General description of system.-The route simulation network is shown in Fig. 9 in which the amplifiers AA to AD correspond to cross-bar switches of a four-stage connecting network and the links lp4 to lp2 correspond to interstage links. Gates pt corresponding to subscribers' lines are located in the inlets fl4 and gates pj corresponding to local, incoming and outgoing junctions are located in the outlets from the network. The gates pa, pb, pc and pd are open or closed in dependence upon the free or busy conditions of their associated links in the connection network. The electronic scanners EXA to EXJ each comprise a decoding matrix. In operation, a gate pt and one or more gates pj are opened whereby signals from scanner EXJ can pass through all the possible free routes between the marked gates to the relevant inlet fl4. The scanner EXA then gradually blocks the AA amplifiers until only the relevant one remains conductive following which scanners EXB to EXJ in turn gradually block the free amplifiers (i.e. routes) until only one amplifier remains conductive in each stage. The amplifiers of each stage may be arranged in a matrix (Fig. 6, not shown), the rows and columns bpx and bpy of which are supplied with inhibiting potentials by the decoding matrix. Decoding matrix (scanner). This consists of a Y matrix M (Fig. 3) and an X matrix (Fig. 4) and since both matrices are similar only the operation of the Y matrix will be described. When the scanner is not in use each of the inputs bmr to bxl0/3 (Figs. 3 and 4) are at earth potential and the various transistors connected to these inputs are in such a state that the eight transistors bTyp0/7 and the four transistors bTxp0/3 are cut-off whereby inhibiting potentials are present on all of the wires bpy and bpx (Fig. 2). When the scanner is taken into use these conditions are reversed whereby all the amplifiers AA to AD which are free are energized and the wires fl1/4 (Fig. 9) supply signals to the logic circuit CL indicating that free routes are available. The logic circuit then earths input bym0 whereby transistors bTym0 and bTy0 cut-off. The wires bYO then attain the potentials of- 12V. and earth respectively provided by a bi-stable circuit bY0. Consequently transistor bTyal cuts off and bTyaO remains on whereby the inlets bY0 and bY0 of the matrix M are marked with potentials of - 24V. and earth respectively. Hence the even-numbered transistors bTyc0 to bTyc6 saturate and the corresponding transistors bTyp0 to bTyp6 cut off whence inhibit potentials are supplied to the even-numbered wires bpy. If the signals on fl4 (assuming stage Z is being scanned) now cause the logic circuit earths wire byr whereby bi-stable counter bC adopts the " 1 " state and is followed into this state .by bi-stable circuit bY0 The oddnumbered wires bpy are now caused to carry the inhibit potentials while the even-numbered wires are restored to their previous condition. The logic circuit then successively earths inputs bym 1 to 3 and if necessary, alters the state of bC until only one wire bpy remains energized. A similar sequence is adopted for the X matrix so that finally only one amplifier AA remains conducting. The other switching stages are similarly treated so as to eventually select a single route. It may not always be necessary to scan all the amplifiers of a stage, e.g. if the logic circuit " knows " the location of a subscriber and hence which amplifier or amplifiers AA he is connected to, it may cause the remaining amplifiers to be inhibited by suitable operation of bi-stable circuits bM0/7 (Fig. 3) which then cause certain of the matrix outlets to be marked with a potential of - 24V. irrespective of the condition of inputs bym0/3. This operation can thus considerably shorten the selection time. The final position of the bi-stable circuits BY0, BY1, BY2, BX0, BX1 is noted in the logic circuit whence the latter can then operate the relevant crosspoints in the corresponding switching stages. It is mentioned that in practice an amplifier should not have more than 6 links incoming thereto or outgoing therefrom (Fig. 11, not shown), a circuit for such an amplifier being depicted in (Fig. 10 not shown). A duplicate scanner may be provided for each stage.