Patent GB-1372188-A (GB)
Title: Frequency synthesizers
IPC: H03B21/04
Filed: 1970-10-02
Abstract: 1372188 Frequency synthesizers RACAL INSTRUMENTS Ltd 30 Sept 1971 [2 Oct 1970] 46866/70 Heading H3F A frequency synthesizing arrangement includes frequency synthesizing means operative to produce an adjustable intermediate frequency F1, frequency dividing means to divide this frequency by an adjustable division factor to produce an output frequency F0, setting means operable to set up the desired value of the output frequency, and control means automatically responsive to the setting means to adjust the synthesizing means and the dividing means such that the value of intermediate frequency F1 is such that when divided by the division factor of the dividing means, the desired output frequency F0 is produced. In an embodiment the frequency synthesizing means comprises four synthesizers 10, 12, 14, 16, Fig. 1, each of which may comprise a mixer by a filter selecting the upper sidebands in the mixer output. Synthesizer 10 combines a fixed frequency Fr (0À6 MHz) with one of ten frequencies selected by switch 44, to give an output F2 (6À0-6À9 MHz): this output is divided in fixed x 10 divider 50 to give a frequency F3 (0À6-0À69 MHz). The synthesizer 12 combines frequency F3 with one of ten frequencies selected by switch 54 to give an output frequency F4 (6À0-6À99 MHz) which forms one input to synthesizer 16. The second input, of frequency F5 (74-153 MHz) to synthesizer 16 is derived from synthesizer 14 which combines frequency FB (4-13 MHz) selected by switch 66 with frequency FA (70-140 MHz) as selected by switch 72. The intermediate frequency F1 forming the output from synthesizer 16 is applied to divider 20, which divides by 10<SP>m</SP>À2<SP>n</SP> where m = 0, 1, or 2 and n = 0, 1, 2 or 3, the output F0 of the divider on line 22 being the desired output frequency. The switches 44, 54, 66 and 72 are electronic and controlled by control units 46, 56, 68 and 74 respectively. Any of the synthesizers 10, 12, 14, 16 may alternatively comprise a mixer which mixes one of the input frequencies with the output of a voltage controlled oscillator, and a phase sensitive detector which compares the lower sideband output from the mixer with the other of the two input frequencies, and so controls the oscillator as to maintain zero difference between the two compared frequencies. The control units 46, 56, 68, 74 derive control voltages on lines 48, 58, 70, 76 respectively in binary coded decimal form, from the corresponding outputs of a multiplier unit 28, which in turn is jointly controlled by outputs from (1) digit-setting control panel 24, and (2) indices selector 26. The indices selector 26 also controls the variable divider 20. Variable divider.-The divider 20 receives an input on line 18, Fig. 2 which is fed to one input of AND gate 102, via x 10 divider 108 to one input of AND gate 104, and via both divider 108 and a further x 10 divider 110 to one input of AND gate 106. The AND gates 102, 104, 106 respectively receive second enabling inputs m0, m1, m2 from indices selector 26 (Fig. 1), and their outputs are connected to the respective inputs of an OR gate 112. The output from OR gate 112 is fed to a chain 114, 116, 118 of x 2 dividers and also to one input of AND gate 120; the dividers 114, 116, 118 respectively feed a first input of AND gates 122, 124, 126 respectively. The AND gates 120, 122, 124, 126 are respectively conditioned to produce an output on line 22, via OR gate 128, by means of second inputs nO, n1, n2, n3 respectively.  Multiplier.-The multiplier 28, Fig. 1 comprises a synchronous clock divider 126, Fig. 3, which receives 10 MHz clock pulses on line 124, and is controlled by signals m0 to n3 on line 100 (Fig. 1). It produces an output on line 128 comprising pulses at fixed repetition frequency 10/800 MHz which are applied to a five-phase clock generator 130 and also to a pulse generator 132: a second output comprising pulses at a frequency 10Q/800 MHz where Q is determined by the signals on channel 100 (Fig. 1), is derived on line 134 and fed to a serial dynamic binary coded decimal (BCD) multiplier unit 136. The five-phase clock generator 130 has five output lines carrying signals #1 to #5, Fig. 5, each output comprising a succession of negative 800 ÁS pulses but with respective phase displacements. The pulse generator 132 has four output lines 138, 140, 142 and 144 carrying signals P2 to P5 respectively (Fig. 5) each of which depends upon the BCD control signal on the corresponding channel 90 to 96 and derived from the control panel 24 (Fig. 1). Each of the signals P2 to P5 comprises positive going pulses whose trailing edges are in phase with the corresponding pulse #1 to #5, but their length in multiples of 80 ÁS is directly proportional to the BCD signal on the corresponding control channel 90 to 96. The serial multiplier unit 136 serially receives pulses of the signals P2 to P5 in that order. Serial BCD multiplier unit 136.-The unit 136 comprises four AND gates 148 to 151, Fig. 4, all receiving on one input clock signals on line 134 and receiving on their other inputs the signals P2 to P5 respectively. The outputs of AND gates 148 to 151 are respectively connected to the inputs of scale of ten cascaded decimal counters 153 to 156, the outputs of which are connected to BCD encoders 158, 160, 162, 164 respectively, which respectively energize the channels 48, 58, 70, 76. Each pulse in signal P2 opens gate 148 and clock pulses pass through to be counted by counter 153, the number being proportional to the length of the pulse P2, i.e. the product of the decimal value set up by control 24A and the division factor Q selected by indices selector 26. In succession, pulses P3, P4, P5 arrive and open gates 149, 150, 151 respectively in succession, causing counters 154 to 156 to count the products of Q and the values to which controls 24B, 24C, 24D are respectively set. The counters being cascaded, their outputs continuously carry the product of Q and the numbers set up by the controls 24A to 24D: the BCD encoders 158 to 164 convert the decimal signals into BCD form and respectively energize channels 48, 58, 70 and 76. The counters are reset during each pulse #1 by means of a line 165, while the encoders are up-dated during each pulse #1, before the counters are reset, by means of a line 166. The control 24E has only two positions (0 and 1) and the final product is indirectly affected by its setting since it affects the value of the division factor Q, which in turn affects the value of the product produced by multiplier 28.