Patent GB-1484443-A (GB)
Title: Data processing systems
IPC: G06F13/36
Filed: 1975-07-14
Abstract: 1484443 Peripheral controllers OMNUS COMPUTER CORP 14 July 1975 29455/75 Heading G4A A data processing system comprises a CPU 20, Fig. 1, and a plurality of input-output devices 28 connected thereto by means of respective input, output and control buses 22, 21, 25, each of the input-output devices 28 having a respective associated controller, shown in detail in Fig. 5, each controller having means 65, 67, 74 for decoding units of information supplied thereto on output bus 21 and generating an enabling signal on an output 75 when a unit of information having a predetermined content is decoded, a register 80 connected to the output bus 21 receiving the enabling signal from output 75 subsequently to the reception of a unit of information from output bus 21 and generating one of a plurality of control outputs EI-CI as determined by that unit of information. The control outputs EI-CI act as enabling signals for components 85, 93, 97, 100, 101, 134 and 138 which serve to selectively transmit units of information between the input and output buses 22, 21 and the input-output device 28 connected to the controller. In operation, a "connect" instruction having bits zero and one respectively equal to 0 and 1 is placed on the output bus 22. AND gate 67, enabled by bit 0 of the connect instruction and by signals from the control bus 25, clocks D-type flip-flop 74 to pass the enabled signal of AND gate 65, in turn enabled when it receives the predetermined content (bits 3-10) of the connect instruction, to output 75. In this way the flip-flop 74 of that controller determined by bits 3-10 of the connect instruction is enabled, and the flip-flops 74 of all other contollers are disabled. Further instructions on output bus 22 therefore do not need to contain a field designating a particular input-output device; the set flip-flop 74 remains set until a further connect instruction designating another input-output device 28 is placed on the output bus 22. Such shorter instructions permit an extension of the size of the instruction set of the system. Bits 3-8 of instructions placed on output bus 22 subsequently to a connect instruction condition the enabled register 80 to generate an appropriate control output CI-EI for permitting transfer of data, instructions, status information and a connect instruction to the CPU 20 from an input-output device 28, and to permit the transfer of data and control data to a connected input-output device 28. If an input-output device 28 desires to interrupt the CPU 20, it sends an interrupt request to a flipflop 127 and, if interrupts are being permitted at that time, this request passes via an enabled gate 129 to a priority circuit 130 for resolving conflicts between two or more concurrent interrupt requests. The selected interrupting device enables, via a line 132, register 80, producing control output EI which in turn enables a circuit 134 to pass an interrupt instruction from the controller to the CPU 20. By passing interrupt instructions in this way from a controller to the CPU, the space occupied in main memory by the interrupt programme is reduced. Interrupt instructions may be sent to CPU 20 from a controller in one of four different ways, in the first of which an instruction, generated in a block (140), Fig. 7 (not shown) of the controller, has a similar effect to a normal interrupt instruction stored in main memory, in that the present status of the system is saved and a jump is made to an instruction routine, on the completion of which the original status is restored. In the second way, one or more instructions are delivered from a read-only memory (146) of the controller at each interrupt request. Thirdly, a combination of instructions from a read-only memory (150) and events detected by an inputoutput device may be sent to the CPU 20. Lastly, instructions generated by an inputoutput device, which in this case may be another computer operating with a stored program, may be transferred directly to the CPU 20 on lines (155).