Patent GB-765704-A (GB)
Title: Improvements in or relating to electric multiplying devices and to electric adder circuits
IPC: G06F7/52
Filed: 1954-07-02
Abstract: 765,704. Digital electric calculating-apparatus. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. July 2, 1954 [July 2, 1953], No. 19534/54. Class 106 (1). An-electric device for multiplying by repeated addition numbers represented by coded pulse trains includes an accumulating loop storage circuit comprising one or more " gate-conditioned " adders (as described below), a delay line, a recirculation gate and an output gate. Artificial electromagnetic delay lines and pentode gates may be used. In the device shown, the N-digit mulplicand M and multiplier m, each represented by a series-mode pulse train (pulse for " 1 " no pulse for " 0 ") are applied at 5, 6 respectively. The first and second multiplier digits are allowed through gates 13, 63 respectively by timing pulses applied at 14, 64 and are set up on one-digit stores or bistable trigger stages 15, 65 which are reset by pulses at 16, 66 after a complete number period or minor cycle. If a multiplier digit is " 1," the corresponding gate 18 or 68 is opened to allow the multiplicand train to be applied to adder 24 or 74, the delay element 79 providing a denominational shift of one digit period #. The multiplicand is also stored in a loop circuit comprising a delay line 1 of " length " N# and recirculating gate 3, and gate 10 allows the third to highest multiplier digits to be stored in loop circuit comprising a delay 55 of (N-2) #. The adder 24 is " gate-conditioned," i.e. the carry feed-back circuit including one-digit delay 34 comprises also a gate 42 which suppresses a carry formed during the last pulse period of an addition, such carry being applied through gate 45 to the result output, and a gate 36 prevents the first digit of a result train appearing on such output, similar gates being provided for the adder 74. The result output of 24 is connected to an input of 74 and the result output of the latter is connected to a delay 47 of (N-2) #, the output of which is connected to output gate 51 and via recirculation gate 27 to an input of 24. If the least significant or " complement " portion of the product pulse train is required, the suppressed first digits may be applied through gates 40, 70 as shown to a further loop storage circuit including delay 48 of (N-2) #, recirculation gate 49 and output gate 53. In operation, the first two partial products obtained from gates 18, 68 are accumulated during the first minor cycle. At the beginning of the next cycle, the third and fourth multiplier digits are in position to be allowed through gates 13, 63 to control through stores 15, 65 and gates 18, 68 the passage to the adders of the third and fourth partial products, and so on. During the N/2th minor cycle, when the last two partial products are formed, gate 49 is closed and gate 53 opened to cause the " complement " product train to pass to output 35, and during the following minor cycle, gate 27 is closed and gate. 51 opened to cause the more significant portion of the product to pass to 35. Another multiplication can commence during the same minor cycle, so that a complete product is obtained in N/2 minor cycles. Other forms of multiplying device are described comprising a single adder (Fig. 3, not shown) or a number p of adders, or comprising different arrangements of delay elements for compensating for internal delays in the adders.