Patent GB-1031686-A (GB)
Title: A synchronising device for a pulse code transmission system
IPC: H04L7/04
Filed: 1963-08-23
Abstract: 1,031,686. Multiplex pulse code signalling. NIPPON ELECTRIC CO. Ltd. Aug. 23, 1963 [Aug. 29, 1962], No. 33474/63. Heading H4L. In a synchronizing arrangement for a time division multiplex pulse code transmission system, the received signal consists of N bits per frame of which the first channel consists of q bits arranged in a predetermined synchronizing pattern and the remaining N-q bits are the p.c.m. combinations for the respective channels. A detection circuit for the synchronizing signal provides an end-of-code signal at the qth bit when synchronization is correct which produces a reset signal to set the equipment for reception of the first of the p.c.m. combinations. The reset signal is also generated if the end-ofcode signal is no more than a pre-selected number m of bit places away from where it should be. As described m = 2. If the end-ofcode signal occurs outside the range m a control signal is derived which switches the channel separator back in steps of m + 1 bits until it is brought within the range m. As shown in Fig. 1, the incoming p.c.m. signals A are supplied to a decoder 13 controlled by channel separator 16 to supply decoded channel signals to the appropriate output lines 12, and are also supplied to a clock pulse generator 14 producing pulses B at the signal bit frequency. The clock pulses control the channel separator 16 which has outputs 15 including outputs for the first q bit places (sync. code), the next m bit places (permissible error), the bit places required by the decoder 13 for its decoding and distributing functions, and the Nth and last bit place which has reset function for the decoder 13. The clock pulses also control a synchronizing pattern detector 21 receiving also the pulses A which delivers a pulse T at the end of the synchronizing signal, and a reset pulse shift register 32 in a synchronism controller 20. An OR gate 22 provides an output Q<SP>1</SP> when the qth output of the channel separator 16 is energized or when any of the outputs within the range m = 2, i.e. q - 2, q - 1, q+ 1, or q+2  are energized. When this output coincides with the output from detector 21 an AND gate 23 supplies a reset pulse R to the channel separator 16 to set the separator to its (q + 1)th position for the reception of the first of the P.C.M. combinations. This output is thus at one of 2m + 1 bit positions. A control pulse generator 24 includes a shift register 32 with 2m + 1 stages controlled by the clock pulses which also receives the output of AND gate 23 so that if the synchronization, or lack thereof, is within the range m one of the stages will be set. The outputs q - 2, q - 1, q+ 1 or q+ 2 of the register form inhibit inputs for a gate 34 which receives the (q+m)th output from the separator 16 so that the gate 34 provides an output S if after q+m bit places have been counted by the separator 16, there has been no detection of the synchronizing combination. Thus, if signal T occurs not more than m bit positions too late or too early the separator 16 is reset, but if the synchronization code has not been detected when the (q+m)th bit place is counted by the separator 16, gate 34 provides an output to cause separator 16 to back-step (w+1) bit positions so that it is set to output 15q. This produces a pulse P M  and if this is in the range m a reset pulse R is produced to restore synchronization. If not, the process is repeated. In a modification, Fig. 2 (not shown), m = 0 and the control pulse generator 24 is dispensed with. The output T of the pattern detector 21 is supplied to the inhibit terminal of a gate 41 which also receives the output of line 15q of the separator 16. When synchronism is correct the separator steps normally, but otherwise a control pulse S causes resetting of the separator to position 15q successively until synchronism is restored. In a further arrangement, Fig. 3 (not shown), a delay may be introduced into the clock pulses from generator 14 and logic circuits are provided to determine whether the channel separator is to be advanced or retarded. As before, if the error exceeds a predetermined amount a pulse S effects stepby-step control until the required range is reached. In a modified synchronization pattern detector, Fig. 4 (not shown), an adder 66 is connected to the output of the pattern shift register 27 so as to produce a pulse U whose voltage is the sum of the output pulses on the leads 28 and which is supplied to a slicer 68 so that an " end of pattern " pulse T<SP>1</SP> is produced only when the voltage of pulse U exceeds a predetermined level. This allows a pulse T<SP>1</SP> to be produced if there is, for example, a one bit error, and allows for the possibility of distortion of the synchronizing signal. A modification uses two slicers with different slicing levels, one or other being selected under the control of pulses S. The application of pulses S to the channel separator may be delayed for one or more frame periods to prevent unnecessary stepping in the presence of noise, Fig. 6 (not shown).