Patent GB-1373021-A (GB)
Title: Schottky barrier diode
IPC: H01L27/102
Filed: 1972-11-10
Abstract: 1373021 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 10 Nov 1972 [20 Dec 1971 (2)] 51960/72 Heading H1K In an integrated circuit (Fig. 3) containing plural circuit components a P-substrate 26 is diffused with N+ region 28 over which an N- epitaxial layer 30 is deposited into which region 28 diffuses. A P + isolation region 32 is indiffused into 30 and an N+ region 34 is indiffused to provide the cathode of a Schottky diode. A thin SiO 2  layer 36 is deposited on oxide layer 37 formed thermally during the previous processing and contact openings 38, 39 are photolitho etched therein. Regions 40, 41, 42 are then formed to provide the Schottky diode anode and contacts to the cathode and anode respectively by thermally evaporating an Al-Cu alloy over the surface, and sintering in N 2 ; after which the layer is etched off to define regions 40, 41 providing the diode and interconnections with other active and passive devices of the substrate. The alloy may alternatively be Cu Al Si; the Si preventing Al from entering the semi-conductor material; and the device may be coated at 43 with sputtered quartz. A Schottky diode may be integrated (Fig. 4) into the collector of a transistor having base region and contact 45, 46 with emitter region and contact 48, 50. The diode comprises anode 50 contacting the Al Cu Si layer and a cathode contact 52 on the N+ region. Alternatively (Fig. 5, not shown) an N epitaxial region has a N+ layer buried therein, with an anode contact applied to the Al Cu Si junction and a cathode contact to an N+ diffused region 68, or a P+ isolation region (Fig. 6, not shown) has N epitaxial region formed thereon with an anode contact and cathode contact. Voltagecurrent characteristics of the Schottky diodes are given (Figs. 1, 7, not shown) and they are incorporated in a 1024 bit read only memory (Fig. 2) wherein the Y sense five true-complement address generators accommodate decoding signals A to E of which generator 10 is shown for A to give true and complementary output signals A and #A. Similarly in the X sense three generators accommodate decoping signals of which generator 12 is shown for F to give true and complementary output signals F and #F. In the Y sense one of 32 decode driver circuits is shown at 14 and in the X sense one of 8 decode driver circuits is shown at 16, while the system is completed by portions of the 1024 bit read only diode array and output sense amplifiers shown at 18, 20; the generators 10 and 12 being identical. In circuit 10, Schottky diodes D 1 , D 2  isolate emitters of transistors TX1, TX2 one from the other to allow performance of logic functions at both emitters and collectors and are integrated into the collector of TX3, while Sohottky diodes D3, D4 clamping transistor TX4 are connected in series between its base and collector to produce an enhanced critical voltage. In decoder 14, plural Schottky diodes are inserted in the several inputs to provide AND function in co-operation, while memory 18 comprises eight Schottky diodes DA whose resistance characteristics are graduated by geometry and size in dependence on their position in the array (Fig. 7, not shown). In driver circuit 16, Schottky diodes D9<SP>1</SP> and D10 respectively clamp transistors TX7, TX8 and diodes D11, D12 in series translate voltage between emitter of TX9 and circuit node 24. In amplifier 20 Schottky barrier diode D13 provides critical voltage drop between collector and base of TX10 while diodes D14, D15 isolate each of the diode columns in memory array 18 one from the other and translate their cathode voltages to the base of TX10.