Patent GB-1445788-A (GB)
Title: Reiceiver digital detectors and methods of operation of such detectors
IPC: G01S13/76
Filed: 1974-07-15
Abstract: 1445788 Secondary radar SPERRY RAND CORP 15 July 1974 [20 July 1973] 31213/74 Heading H4D In an aircraft interrogating a DME or TACAN beacon, it is required to pick out and lock on to the synchronous replies to its interrogations from amongst the general pulse emissions of the beacon. To do this, a shift register 10 (having, e.g. 265 stages for a maximum range of 420 miles) is shifted by a series of clock pulses (e.g. at a period of 20 Á sec.) started by the interrogation pulse (PRF) and stopped when 265 pulses have been used. Pulses from the beacon (fill-in pulses as well as the true response) are fed to the input of the register via a recirculation logic, input and correlation circuitry 22. If it is assumed that a pulse is received during the 5th 20 Ás increment, the register will finish at the end of the clocking, with its 5th stage at 1 state. At the next interrogation and clocking, the 1 state will pass through the circuitry 22 during the 5th increment, where it is cancelled if a synchronous replay is not received or augmented by a 1 state in the 6th increment, if a synchronous reply is received. This is continued until, if five successive synchronous replies are received and a corresponding train of five successive 1 states are present in the register, said successive 1 states are detected and a synchronous reply acquired signal is generated. This causes a change from "search" to "track" mode. To determine when the correct number of clock pulses have fed to the register, said pulses may be counted (18), Fig. 2 or Fig. 1, at the beginning of each PRP or scan a unique coded pulse train, e.g. 1,0,1,0, may be loaded into the first stage of the register, and the clock pulses stopped when it is detected (34) that the coded pulse train has been recirculated back to the first stages. The loading of the coded pulse train is produced simultaneously with the clearing (39) of the register. In the detailed exposition of the arrangement of Fig. 1, shown in Fig. 4, the register 10 is divided into three parts in series, a first four stage part 46 for the insertion of the coded pulse train, a second 256 stage part 48, and a third 8 stage part 50 for the generation of certain inhibit gate pulses. The clock output is fed to the register parts 46, 48, 50, via an AND gate 60 controlled by a bistable 62m set by the PRF pulse via bi-stable 92, load 154 and OR gate 64, and reset by the output of a circuit 34 (80, 82, 84) detecting the presence of the coded pulse train. Replies are fed to the input 61 of register part 46, via AND gate 66, bistables 68, 70 and OR gate 72. The recirculation of the 1 states of the register is from output stage H, via line 160, AND gates 76, 78 and OR gate 72. To stop pulses immediately preceeding and following the reply pulse from interfering with the processing, early and late inhibiting gates are generated by inhibiting logic circuitry 86, 88, 90, 92 and fed to the recirculating AND gates 74, 76. An AND gate 98 detects when stages D, E, F, G all have 1 states and causes a bi-stable 104 to generate an "aquisition" signal at its Q output. This in turn causes a "track" command signal to be fed to track circuitry 112 and the generation of a tracking gate for feeding to the reply input AND gate 66. Slight time shifting of the replies from one PRF to the next due to movement of the aircraft, is adjusted for by phase-shifting of the clock pulses at 58 for the register parts 48, 50.