Patent GB-1357028-A (GB)
Title: Data exchanges system
IPC: G06F13/362
Filed: 1971-09-27
Abstract: 1357028 Data processing systems HITACHI Ltd 27 Sept 1971 [25 Sept 1970] 44957/7l Heading G4A The invention relates to a system for data exchange between a plurality of independent computers. The computers and a central control unit are all coupled to a bus-bar 31-33; a computer wishing to transfer data to another transmits a one bit interrupt signal to the busbar which signal is received by the central control unit causing it to emit an interrogation signal to find out which computer is calling; on receipt of the interrogation signal the calling computer transmits the address of the computer to which it wishes to transfer data and indicates its own address; the central control unit stores the pair of addresses and then periodically transmits the pair to the bus-bar; the two computers respond to the address pair by respectively transmitting and receiving data from the bus-bar. Several pairs can be stored and the data exchanged on a time sharing basis. The bus-bar comprises three lines 31, 32, 33. The line 31 carries a continuously repeated sequence of clock pulses (Fig. 3), of period T, consisting of two groups of elementary pulses. The central control unit normally operates to transmit the pairs of addresses during the periods T1, while the computers respond by transmitting data in the periods T2; the line 33 carries the data and addresses. The interrupt signal is carried by line 32 to an interrupt generator 12 (Fig. 6, not shown) of the central control unit; the generator 12 responds by transmitting an all ones address cl15 to the line 33; interrupting a signal cl13 to stop the normal transmission of addresses and producing a signal cl12 to open the input gate (181) of an address recognizing unit 18 (Fig. 10, not shown). The all ones address is read into a register (232) in an address discriminator 23 (Fig. 15, not shown) of each computer and compared with a memory to generate a signal t1 to start a counter (266) in a sequencer 26 of the or each calling computer. When the counter (266) of a calling computer has counted l periods T of the clock pulses a gate (244) is enabled to release the address of the requested computer to the line 33. The value of l is different for each computer; therefore the timing of the transmitted address(es) indicates the address(es) of the calling computer(s). Each transmitted address is read into a register (182) in the address recognizing unit 18 and another counter decodes the timing to obtain the address of the calling computer. An address memory 15 (Fig. 11, not shown) comprises a register (153) for each computer and each address from the register (182) is read into the register corresponding to the calling computer; associated with each of these registers is a permanent memory (152) holding the addresses of the respective computers. Thus, at the end of an interrupt period one or more register-memory pairs of the memory 15 will contain pairs of addresses (d); which one will be indicated by the setting of respective ones of a plurality of flip-flops (156). When the normal operation is resumed by restoring signal cl13 the contents of the register memory pairs are shifted cyclically during each period T of the clock pulses enabling them to be read out bit by bit through respective gates (157). A transmitter circuit 16 connects the gates (157) one after another to the bus line 33 and when selected any gate (157) which is enabled by a set flip-flop (156) transmits the respective address -pair. Each address pair is read into the register (232) of the address discriminator 23 of each computer and again compared with a memory; if the first part of the pair corresponds to the address of the computer the discriminator 23 issues a signal t2 enabling the computer to receive data from the line 33; if the second part of the pair corresponds it issues a signal t3 enabling the computer to transmit data to the line 33. When all the data has been transmitted an "end" word is sent and a detector 17 in the central control unit resets the flip-flops (156) of the address memory 15.