baber/WOPTO huggingface dataset:
Patent TW-396133-B (TW)
Title: Method for protecting objects, especially ships, that emit a radiation, particularly infrared radiation, against missiles
Inventor: WARDECKI NORBERT
IPC: F41H11/02
Filed: 1995-10-17
Granted: 2000-07-01
Abstract: Method for protecting objects, especially ships, that emit a radiatio, particularly infrared radiation, against missiles that are equipped with intelligent homing heads, particularly scanning, imaging, correlating and/or spectrally filtering homing heads, preferably infrared homing heads, whereby a dummy target cloud, particularly an infrared dummy target cloud, having a higher radiation capacity than the threatened object, particularly an infrared radiation capacity, is formed by firing a projectile body loaded with a combustible projectile means from a launcher tube installed on the threatened object or in the proximity thereof, by dispersal of the projectile body and simultaneous iqnition and distribution of the projectile means next to the target in the region of the homing optics of the homing head, characterized in that a radiation means located in the projectile body is already activated upon launch of the projectile body, this radiation means radiating an energy form corresponding  to the later dummy target in an intensity relevant for the homing head beginning immediately after the launch until the dummy target, particularly the infrared dummy target, has been built up.
Patent TW-394937-B (TW)
Title: Digital signal recording method and apparatus and recording medium therefor
Inventor: HIGURASHI SEIJI
IPC: H04N9/804
Filed: 1996-03-28
Granted: 2000-06-21
Abstract: Digital signals are recorded in sequential tracks on a tape-form recording medium. In the case where the digital signals are recorded in accordance with one recording format, digital signals for normal reproduction are recorded in a single area of the first format on each track. In the case where the digital signals are recorded in accordance with a second recording format, the first digital signals are recorded in a specific area among divided areas of the second format, the divided areas being independantly rewritable on each track, with the specific area being common for both the first and second formats. Furthermore second digital signals for special reproduction are recorded in previously determined areas among recording areas on each track, the recording areas being common for both the first and second formats.
Patent TW-457089-B (TW)
Title: Pharmaceutical composition for treating or inhibiting the growth of tumors or cancers susceptible to treatment
Inventor: JAMES BERGER CAMDEN
IPC: A61K31/27
Filed: 1996-05-13
Granted: 2001-10-01
Abstract: This invention is a pharmaceutical composition that inhibits the growth of cancers and tumors in mammals, particularly in human and warm blooded animals. The composition contains a 10:1 to 1:10 mixture of (1) N-chlorophenyl carbamates and N-chlorophenylthiocarbamates and (2) N-phosphonoglycine derivatives which are systemic herbicides. This composition can also be used to treat viral infections.
Patent TW-327226-B (TW)
Title: Data carriers having an integrated circuit unit
Inventor: EPHRAIM SUHIR
IPC: G06K19/077
Filed: 1996-08-29
Granted: 1998-02-21
Abstract: A data carrier, which is characterized in that: a card (30) comprises a material with a Young^s modulus, the card having a horizontal midplane (35), in which a cavity (40) filled with a material with a Young^s modulus and having a length and a thickness, in which the cavity (40) is positioned in the horizontal midplane of the card (30) with the thickness, and an integrated circuit (50) comprises a material with a Young^s modulus, the integrated circuit comprising a length and thickness less than 12 mils and being located in the cavity (40) and positioned in the horizontal midplane (35) of the card (30) with the thickness, in which the cavity is made out of a material that has a Young^s modulus that is higher than the Young^s modulus of the card (30) but lower than Young^s modulus of the integrated circuit (50).
Patent TW-337596-B (TW)
Title: Process for producing self-aligned silicide
Inventor: LIOU HANN-SHING
IPC: H01L21/31
Filed: 1996-12-12
Granted: 1998-08-01
Abstract: A process for producing a self-aligned silicide, which comprises: (a) forming a first Ti metal layer on a MOS structure defined with a gate and formed with a source/drain active region; (b) forming a TiN layer on the Ti metal layer; (c) forming a second Ti metal layer on the TiN silicide; (d) heating the first Ti metal layer, TiN layer and the second Ti metal layer so that silicon (Si) in the gate, source/drain active region and the first Ti metal layer form a TiSi2 layer; (e) removing the second Ti metal layer, TiN layer and the first Ti metal layer which is not reacted into TiSi2 with silicon; and (f) heating the TiSi2 layer to convert the TiSi2 layer into a TiSi2 layer with a lower resistivity.
Patent TW-347643-B (TW)
Title: Circuit arrangement
Inventor: OSCARJAN DEURLOO
IPC: H05B41/14
Filed: 1997-03-10
Granted: 1998-12-11
Abstract: A circuit arrangement for igniting and operating a high-pressure discharge lamp, provided with: input terminals for connection of a supply source; output terminals for connection of the lamp; switching means for operating the lamp at a nominal lamp voltage Vla during stable lamp operation and for generating an open voltage V0 at the output terminals before the lamp has ignited; ignition means for generating an ignition voltage pulse when the voltage at the output terminals reaches a threshold value Vi; a control circuit for controlling the switching means; which is characterized in that the control circuit comprises means for limiting the voltage at the output terminals to a value Vb such that the following is trueVla < Vb < Vi.
Patent TW-338796-B (TW)
Title: Circuit for detecting overcharging and overdischarging
Inventor: MASUKO TAKESHI
IPC: H02J7/00
Filed: 1997-05-24
Granted: 1998-08-21
Abstract: A circuit for the detection of overcharging and overdischarging, having the circuit: 2 cumulative batteries in series for generation of battery voltages; dividing voltage circuit in connection with the cumulative batteries for generation of dividing voltage for the batteries; reference voltage circuit for generation of fixed voltage; voltage comparative circuit for the comparison of output from the dividing voltage circuit and output from the reference voltage circuit, for the change of the output signals; and control circuit, which generates signals based on the output signals from the voltage comparison circuit, for the control of the charge or discharge of the cumulative battery; where the voltage comparison circuit having an N-channel MOS input differential comparator, with the voltage comparison circuit connected to the positive voltage of the cumulative battery in use as a common negative voltage output reference voltage circuit and the voltage comparison circuit having a P-channel MOS input differential comparator, with the voltage comparison circuit connected to the positive voltage of the cumulative battery in use as a common positive voltage output reference voltage circuit.
Patent TW-393693-B (TW)
Title: MOS device with air-gap spacers and its manufacturing method
Inventor: JOU JR-WEN
IPC: H01L29/49
Filed: 1997-07-26
Granted: 2000-06-11
Abstract: A MOS device with air-gap spacers is introduced. The L-shaped air-gap is formed between the gate area and the spacer to isolate the spacer, the gate area, and the light doped drain area and reduces the fringe capacitor between the gate area and source/drain area. Meanwhile, its shallow implant the extended light doped drain area is shallowly implanted. It can avoid the occurrence of the short-channel effect and the punch-through phenomenon.
Patent TW-353748-B (TW)
Title: Speech encoding method and apparatus and pitch detection method and apparatus
Inventor: IIJIMA KAZUYUKI
IPC: G10L25/90
Filed: 1997-09-12
Granted: 1999-03-01
Abstract: A pitch detection method capable of realizing high-precision pitch detection even for speech signals in which half-pitch or double-pitch exhibits stronger autocorrelation than the pitch to be detected, in which an input speech signal is judged as to voicedness or unvoicedness and a voiced portion and an unvoiced portion of the input speech signal are encoded by a sinusoidal analytic encoding unit and by a code excitation encoding unit, respectively, for producing respective encoded outputs; the sinusoidal analytic encoding unit performs pitch search on the encoded outputs for finding the pitch information from the input speech signal and sets the high-reliability pitch information based on the detected pitch information; the results of pitch detection are determined using the so-set high-reliability pitch information and the results of decision voicedness/unvoicedness of the frames other than the current frame.
Patent TW-363027-B (TW)
Title: Motorcycle of scooter type
Inventor: NAGATA YUMIKO
IPC: B62J23/00
Filed: 1998-02-17
Granted: 1999-07-01
Abstract: A kind of motorcycle of scooter type which provides the miniaturized front cover and installs the head light on the front cover and the head light is installed eminently before the front cover. The motorcycle with the head light on top of the front cover whose features are to separately install the head light cover around the said head light and the head light cover is mounted at the opening which is in front of the front cover. The head light cover is shaped according to the shape of head light and there is no clearance between the two in order to miniaturize the front cover and with the assembly of head light cover and head light installed on the front cover so as to install head light eminently in front of the front cover.
Patent TW-374167-B (TW)
Title: Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level
Inventor: TERNULLO LUIGI JR
IPC: G11C11/34
Filed: 1998-04-07
Granted: 1999-11-11
Abstract: A semiconductor memory device comprises a pair of data lines, and an acceleration circuit coupled to the data lines wherein, when a data signal is transferred to the first and the second data lines, a data signal on one of the data lines is used to excite the acceleration circuit to increase the speed of the signal passing through the second data line. The acceleration circuit comprises a set of crisscrossed field effect transistors, a pair of acceleration transistors crisscrossed together so that the gate of the first acceleration transistor is connected to the drain of the second acceleration transistor, as well as connected to the second data line; while the gate of the second acceleration transistor is connected to the drain of the first acceleration transistor, as well as connected to the first data line. When a low signal passes through one of the data line causing one of the acceleration transistors to be applied with a bias voltage in order to provide an extra current to the other data lines, a complementary data signal generated on the data line is accelerated.
Patent TW-377473-B (TW)
Title: Structure of polycide layer
Inventor: Lin yong-chang
IPC: H01L21/3205
Filed: 1998-05-19
Granted: 1999-12-21
Abstract: This invention relates to an application of CoSix for forming a polycide structure with reduced electrical impedance and enhanced data transmission rate, as well as in the manufacturing process of semiconductors with smaller line-width. The structure thereof comprises a polycide layer formed on the substrate of semiconductor, a stop layer over the polycide layer, and a CoSix layer over the stop layer, where the CoSix layer, stop layer and polycide layer together form the CoSix polycide layer. CoSix layer can be formed by sputtering or CVD, and then a dielectric interlayer is formed on top of CoSix layer as the cover layer. Lastly, definition is given for the said layer. The polycide structure can be used as gate structures and lead wire structures.
Patent TW-464870-B (TW)
Title: Circuit for sensing memory cell having multiple threshold voltages and method thereof
Inventor: SEO SEOK-HO
IPC: G11C16/26
Filed: 1998-06-03
Granted: 2001-11-21
Abstract: A circuit for sensing a memory cell having a plurality of threshold voltages is disclosed, which is capable of implementing a low power and voltage sensing operation and reducing the size of a multiple level memory cell by minimizing the size of the circuit and includes a switch for applying or blocking a current to/from a memory cell in accordance with a switching control signal inputted into a bit line connected with a selected memory cell, a current comparison unit for comparing the sizes of a current flowing on the bit line and one reference current and outputting a result of the comparison, a memory for storing a result of the comparison performed by the current comparison unit, and a counter register circuit provided to correspond with the number of multiple levels of the memory cell.
Patent TW-436979-B (TW)
Title: Method for eliminating the buried contact trench
Inventor: WU SHIE-LIN
IPC: H01L21/76
Filed: 1998-06-04
Granted: 2001-05-28
Abstract: The method of the present invention comprises the steps of: forming a gate insulation layer on the substrate; forming a first silicon layer on the gate insulation layer; defining a buried contact opening in the first silicon layer and the gate insulation layer; doping the substrate to form a buried contact area; forming a second silicon layer and a mask layer on the substrate and the first silicon layer; removing part of the mask layer and the second silicon layer to define the opening of a protection area and also define the second silicon layer as an upper electrode of the gate and an interconnect; then, forming a passivation layer; next, removing part of the first silicon layer to define a lower electrode of the gate; removing the mask layer; doping the substrate to form a second doped area; forming a sidewall structure on the sidewall of the upper electrode and bottom electrode of the gate; doping the substrate to form a third doped area; and finally performing a thermal process to complete the structure of the buried contact.
Patent TW-405263-B (TW)
Title: Semiconductor device comprising capacitor and method of fabricating the same
Inventor: ARIMA HIDEAKI
IPC: H01L27/108
Filed: 1998-07-02
Granted: 2000-09-11
Abstract: This invention provides a semiconductor device which could ensure to have a certain capacitance, be highly integrated and have high degree of reliability, and method of fabricating the same. In the semiconductor device comprising the memory cell domain and the peripheral circuit domain, and on the major surface of the semiconductor substrate (1), there is provided an insulating film (59) having an upper surface for forming and extending the above-mentioned memory cell domain to the peripheral circuit domain. A capacitor bottom electrode (170a) is form to extend to the upper surface more than the upper surface of the insulating film (59) on the major surface of the semiconductor substrate (1) in said memory cell domain; and there is formed a capacitor upper electrode (150) which extends on the upper surface of the insulating film (59). The capacitor bottom electrode (170a) is the capacitor bottom electrode portion comprising the top face (301) and the bottom face (302). The upper surface of the insulating film (59) is located between the top face (301) and the bottom face (302) of the capacitor bottom electrode portion.
Patent TW-497170-B (TW)
Title: Method of manufacturing semiconductor devices
Inventor: JEON MI-SOOK
IPC: H01L21/306
Filed: 1998-08-03
Granted: 2002-08-01
Abstract: There is provide a semiconductor device fabrication method comprising the steps of: (a) carrying out an exposure and a development on a semiconductor substrate in order so as to selectively remove the photoresist deposited on a given film of the semiconductor substrate; (b) etching the exposed portion of the given film by the selective removal of the photoresist; and (c) carrying out a strip process for completely removing the photoresist remaining on the semiconductor substrate by using dimethylacetamide after the above selective removal of the photoresist.
Patent TW-401515-B (TW)
Title: Anti-fogging and anti-reflection optical article
Inventor: HATAKEYAMA HIDEYUKII
IPC: A61F13/15
Filed: 1998-08-04
Granted: 2000-08-11
Abstract: Disclosed herein is an anti-fogging and anti-reflection optical article which comprises a substrate, a first water-absorbing film provided on the substrate, a thin film of high refractive index provided on the first water-absorbing film, and a second water-absorbing film provided on the thin film of high refractive index, wherein the first water-absorbing film contains a water-absorbing polymer and provided on the substrate, the thin film of high refractive index comprises a polycondensation product of a hydrolysate of a metal alkoxide, and the second water-asorbing film comprises a water-absorbing polymer.
Patent TW-446755-B (TW)
Title: Method and solution for producing gold layers
Inventor: BACKUS PETRA
IPC: C23C18/42
Filed: 1998-09-08
Granted: 2001-07-21
Abstract: A combination of nickel and gold layers is usually applied to metal structures of electric circuit substrates for further processing. The baths used for this purpose for electroless gold plating have the following disadvantages: the baths are not sufficiently stable and therefore they have a tendency to wild growth on locations on the circuit substrate that are not to be gold plated, the gold layers that can be achieved are not thick enough for certain applications, and when thicker layers are deposited, the nickel layer is corroded so severely that the gold layer no longer adheres adequately to the substrate. These problems are solved with a method of producing gold layers wherein (a) palladium layers are first applied to the workpiece, (b) an aqueous solution containing at least one compound from the group of compounds containing gold (I) and gold (III) ions and additionally at least one organic compound from the group consisting of formic acid, aromatic carboxylic acids having the chemical formula, where R1, ..., R4=H, alkyl, alkenyl, alkynyl, OH, and the salts, esters or amides of these compounds is used, the solution is adjusted to a pH of 1 to 6 using pH adjusting agents, and the workpiece is brought in contact with the solution.
Patent TW-410253-B (TW)
Title: Orifice for pressure-type flow rate control device and its manufacturing method
Inventor: OMI TADAHIRO
IPC: G05D7/01
Filed: 1998-10-09
Granted: 2000-11-01
Abstract: An orifice for pressure-type flow rate control device can be easily manufactured with a low cost. The manufactured orifice has a wide range of pressure ratio P2/P1 (P1 is the pressure at the upstream side of the orifice and P2 is the pressure at the downstream side of the orifice). A linear characteristic exists between the pressure P1 at the upstream side of the orifice and the flow rate. The flow rate characteristics among a plurality of orifices can be easily adjusted. More specifically, the orifice has a structure comprising a tapered inlet section 1 wherein one open end of a bottom hole 6 bored into a main body member D is cut into a shape like the mouthpiece of a trumpet, and a short drawn parallel part 2 continuing therefrom; and a short expanded tapered section 3 formed by expanding the diameter of the other open end of the bottom hole 6 and continuing from the drawn parallel part 2, and an expanded parallel part 4 continuing therefrom.
Patent TW-384531-B (TW)
Title: Semiconductor device, method of manufacturing semiconductor device and a method of manufacturing lead frame
Inventor: HOZUMI KOJI
IPC: H01L21/48
Filed: 1998-10-15
Granted: 2000-03-11
Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.
Patent TW-505633-B (TW)
Title: Substituted pyrimidine herbicides
Inventor: GERARD MICHAEL KOETHER
IPC: A01N43/56
Filed: 1998-11-04
Granted: 2002-10-11
Abstract: Compounds of formula I, and their N-oxides and agriculturally suitable salts, are disclosed which are useful for controlling undesired vegetation wherein J is and J, W, X, Y, Z, A, R1-R8 are as defined in the disclosure. Also disclosed are compositions containing the compounds of formula I and a method for controlling undesired vegetation which involves contacting the vegetation or its environment with an effective amount of a compound of formula I.
Patent TW-527300-B (TW)
Title: Vehicle drive assembly and vehicle comprising the same
Inventor: GAY JORDAN L
IPC: B62M7/12
Filed: 1998-12-11
Granted: 2003-04-11
Abstract: A vehicle drive assembly with a motor configured for driving the vehicle and including a rotatably driven motor shaft. A first swing arm has a first end housing the motor and a second end pivotably and supportively attachable to a vehicle body, with an elongated portion joining the ends. The vehicle also has a gearbox housing configured for transmitting torque to a road surface through a road engaging member, and a transmission directly engaged with the motor shaft and housed within the gearbox housing. The transmission is configured for transmitting torque from the motor shaft to the housing. A second swing arm is pivotably and supportively attachable to the vehicle body. An axle is fixed to the second swing arm, received within the gearbox housing, and attached to the transmission such that the second swing arm is supported by the transmission. The transmission preferably includes a planetary gear reduction unit with a gear carrier rotationally fixed to the first swing arm and a plurality of gears operatively associated with the shaft and the gearbox housing to transmit torque therebetween. Preferably at least one of the gears is mounted to the gear carrier, more preferably a plurality of planetary gears is mounted to the gear carrier.
Patent TW-402794-B (TW)
Title: Stack structure of electronic device
Inventor: LEE CHUN-CHI
IPC: H01L23/28
Filed: 1999-01-05
Granted: 2000-08-21
Abstract: A substrate comprises an organic material layer and a metal layer. Such organic material layer comprises an upper pothole cavity and an lower pothole cavity from the upper surface and the lower surface of the substrate intersecting through the upper surface and the lower surface of the metal layer. When the upper electronic device and the lower electronic device are inserted into the inner of the upper pothole cavity and the lower pothole cavity, such electronic device's bottom face contacts the metal layer of the substrate to dissipate the heat. The encapsulating body is filled into the upper pothole cavity and the lower pothole cavity to completely and tightly sealed the upper electronic device and the lower electronic device. When the substrate is fixed on another substrate through the metal ball stack, the encapsulating body on each substrate does not contact each other. A print circuit board is provided, on each of the upper surface and the lower surface, with a plurality of stack substrates which makes the print circuit board to be a multi chip module (MCM).
Patent TW-407348-B (TW)
Title: Manufacture of the flash memory
Inventor: LI JUNG-SHIUNG
IPC: H01L21/8247
Filed: 1999-02-03
Granted: 2000-10-01
Abstract: A kind of manufacture method of flash memory with the STI structure and buried bit line is disclosed. Since this invention uses the STI structure to replace of the traditional field oxide as the isolation structure, it could highly elevate the integration of the device and shrink the size of the device. The STI is formed prior to the doping process, so the lateral diffusion resulted from thermal process is prevented and the also the short channel effect. By the way, because use the poly silicon to electrically connect the doping area, the resistance of the buried bit-line is lower and the read and write speed is also higher.