Patent GB-824059-A (GB)
Title: Digital integrators
IPC: G06F7/66
Filed: 1957-07-26
Abstract: 824,059. Digital electric calculating-apparatus. BENDIX AVIATION CORPORATION. July 26, 1957 [Aug. 27, 1956], No. 23803/57. Class 106 (1). An integrating device having means for totalizing the pulses of a first electrical pulse train representing a function to be integrated, means for receiving a second electrical pulse train representing a variable of integration and means for emitting a third pulse chain at a variable frequency proportional both to the value of the totalized number of pulses in said first train and to the frequency of the pulses in the second train, whereby a cumulated total of the said emitted pulses of the third train will represent an integral of said function with respect to said variable of integration, whereby each pulse represents a differential increment of the related variable, and wherein means are provided for assigning to the increments represented by the pulses of at least one of said trains a selected one of at least two different absolute values other than zero. The invention is applied to a digital integrator comprising a Y register to register the values of a quantity Y depending on an independent variable X and an R register, wherein discrete variations in the variable X cause the contents of the Y register to be added into the R register, the R register being adapted to give an output signal and return to zero upon predetermined values being attained. As shown, Fig. 9, a Y register 68 has binary digit positions B 1 -B 6  and an R register 70 has binary digit positions B<SP>1</SP> 1 -B<SP>1</SP> 6 . The registers may utilize bi-stable multivibrators, magnetic cores, or be delay lines or magnetic drum tracks, and digits are stepped along by the application of clock pulses P 1 -P 6 . The output from the Y register 68 passes to a binary adder 72 (Fig. 7, not shown) of known construction whose other input 80 represents increments #Y and whose output passes via a gate 82 to the other end of the register 68. The position B 1  normally holds a sign digit (0 for positive, 1 for negative) and the positions B 2 - B 6  normally correspond to values of ¢, , #, <SP>1</SP>/ 16 , <SP>1</SP>/ 32'  respectively. The incremental value #Y 1  is <SP>1</SP>/ 16  and of #Y¢ <SP>1</SP>/ 32 , so that these increments are represented by 0-00010 and 0-00001, if positive and by 1-11110 and 1-11111, if negative, the first digit in each case being the sign digit and pulses as indicated are applied to the gates 76, 74, 83 to route the required numbers to the adder 72. The carry flip-flop 74<SP>1</SP> is blocked during pulse times P 6 , P 7  to prevent round carry. R register.-The contents of the R register 70 circulate normally through an adder 92, the six digits having denominational values of ¢-<SP>1</SP>/ 64 , no sign digit being present. If the output from the adder 72 via the gate 82 and line 102 is fed to the adder 92, then one-half the value of Y will be added the contents of the R register, whereas if the output from the position B 1  via the line 104 is fed to the adder 92, there is no halving. Addition.-If a full increment #X 1  occurs, the gate 106 is opened to pass during pulse times P 2 -P 6  the value of Y to gates 108, 110, the former being opened if #X 1  is positive to apply the value of Y directly to the adder 92, the latter being opened if #X 1  is negative to apply the complement of Y to the adder 92, the complement being formed by passing Y through an inverter 112 and an adder 114 which adds one during the pulse time P 1 . Thus for a full increment #X 1  the content of the Y register 68 is added or subtracted depending on the sign of #X 1  to or from the contents of the R register 70. For a half increment #X¢, the gate 116 is opened during pulse times P 1 -P 5  to pass the delayed value of Y from the position B 1  directly or after complementation to the adder 92. R register outputs.-If an increment added to the R register value causes the register to attain the value ¢ (i.e. a 1 occurs in the most significant position), a positive half increment #Z¢ is produced, whereas if the register capacity is exceeded positively, a full increment #Z is produced. Appropriate outputs for attainment of the value -¢ and exceeding the register capacity negatively are produced when an increment is subtracted from the R register value. The sign of the output #Z which depends on the sign of its component factors AX and Y is ascertained by the passage of a pulse by one of the gates 118, 120 during the pulse time P 6  setting the flip-flop 124 to indicate a negative output increment by the sign digit #Z #  being high and #Z #  low and the failure to pass such a pulse resetting the flip-flop 124 from the inverter 130 to indicate a positive output increment. The gate 118 is fed with #X #  and the sign digit of Y to give an output when the increment is positive and Y is negative, and the gate 120 gives an output when the signs are reversed, the Y signal being passed through an inverter 132. If AX and Y have the same sign, neither gate 118, 120 passes a pulse and the flip-flop 124 is reset. Formation of output signals.-If the value Y last added to the R register was uncomplemented the inverter 130 emits a pulse and the appearance of a one digit at pulse period P 6  in the carry flip-flop 96 of the adder 92 indicates the attainment of the value ¢ so that the gate 150 passes a pulse via the gate 138 which ensures that no output is produced unless an increment in X has occurred, to the flip-flop 134, which is set. If the value Y last added to the R register was complemented an increment - #Z¢ is produced on attainment of the value - ¢. If an output increment occurs, the pulse from the flip-flop 96 at pulse time P 6  is blocked from returning to the adder 92 by the gate 160. Full output increments #Z 1  are produced from the flip-flop 136, the gates 156, 158 receiving inputs from the input to the flip-flop 96 indicative of the capacity of the R register being exceeded. Specifications 745,816, 748,267 and 751,101 are referred to.