Patent GB-852794-A (GB)
Title: Improvements in or relating to saturable magnetic core circuits
IPC: H03K19/16
Filed: 1958-09-08
Abstract: 852,794. Controlled non-linear inductors. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. Sept. 8, 1958 [Oct. 12, 1957; Jan. 6, 1958; June 7, 1958], No. 28734/58. Class 40 (9). [Also in Group XIX] A saturable magnetic core arrangement which utilizes material with a rectangular hysteresis loop comprises two flux paths having a common A.C. winding and separate input windings, the A.C. winding when energized from an alternating supply causing the flux of both cores to alternate between saturation and a non-saturated degree of magnetization to an identical extent, while the application of an input signal to one input only causes the associated core to remain saturated and the other core to double its degree of flux variation. General details. Two separate cores 1, 2, Fig. 1, may provide the two flux paths, the cores having a common A.C. winding M and separate input and output windings n1 n2, N1, N2. Alternatively the A.C. winding may be located on one limb of a three-limbed core, Fig. 2 (not shown). A composite core structure, Fig. 6, may also be used comprising a toroidal core having a rectangular hysteresis characteristic and a yoke 23 of magnetically soft material. The A.C. winding M1 may be arranged as illustrated or may be carried by the yoke 23, Fig. 5 (not shown). A further construction using two magnetically soft yokes 23 is shown in Fig. 7. Shifting registers. In the two register stages shown in Fig. 9, corresponding output and input windings N1, n1 and N2, n2 are connected together by way of a rectifier D. In operation, an input signal to one or other of the windings nl, n2 on the first stage causes the associated flux path to remain saturated. An alternating flux of increased magnitude is then obtained in the other flux path and generates an output which acts on the next stage. Since an input to n<SP>1</SP> produces an output on N2 and vice versa, the signal relationship is reversed from stage to stage. In a modification, the equal output voltages developed when no input is present may be suppressed by the provision of a D.C. bias source or an auto-bias circuit 25, Fig. 10, in a common return path for the windings N1, nl and N2, n2. Alternatively a D.C. bias winding m may be provided on each yoke 23, Fig. 11. In this register, auxiliary alternating voltages E1 and E2 are connected in the common return paths and act in opposition to the voltages induced in the output windings. In this way a current circulates in an output-input circuit such as N1-D-n1 only when flux path 11 is saturated, and the complementing property of alternate stages is overcome. As the information is passed from stage to stage in the same form, the windings N2, n2 need not be provided, Fig. 12 (not shown). A further shift register is shown in Fig. 14 in which the A.C. energization of windings M1, M2 is derived from lines a, b and D.C. is applied to bias windings m1 m2 from terminal A. The windings N1, n1 and N2, n2 of adjacent stages have a common return path which includes circuit elements P and F. Signal inputs representing binary " 1 " and " 0 " are respectively applied to and saturate cores 1 and 2. Spurious voltages and currents transmitted by one stage to a preceding stage due to flux changes in the cores are suppressed by the P and F elements which may respectively take the form shown in a, b or c in Figs. 15 and 18. A modified register is shown in Fig. 19 in which the element F is constituted by a D.C. source G common to a number of stages, a damping circuit comprising a resistor r and inductor l being connected in series. In Fig. 21, the D.C. source G is connected between, wires b1 b2 and d which are associated with one terminal of the A.C. source. Alternatively the A.C. source is connected to a centre-tapped transformer T, Fig. 22, and the D.C. source G together with resistor r and inductor l is associated with the central tapping. A modification is described. Fig. 24 (not shown), in which a parallel tuned circuit is connected to the tapping so as to speed up the read-in operation and slow down the read-out operation by enhancing the second harmonic frequency. One branch of the parallel tuned circuit may also include both inductance and capacitance so as to present zero impedance as the fundamental frequency. Logical circuits. Several input windings may be associated with each core 1, 2, as shown in Fig. 26, the A.C. and D.C. energizations being effected by windings AB, A<SP>1</SP>B<SP>1</SP>. The input windings, when energized, act in a direction tending to maintain saturation of the associated core so that no output is produced. Binary signals x, y and z are applied to core 1, and v and the complementary z signals are applied to core 2, the logical outputs (#x . #y . #z) and (x+y+z) being obtained from N1 and N2, respectively, for signals x, y and z, while the outputs (z+v) and (z . v) are obtained from N1 and N2, respectively, for the signals v and z. Details of the preceding logical stage showing how the z and z inputs are obtained from the opposed outputs of a pair of cores are in Fig. 27 (not shown). Separate A.C. and D.C. windings may be provided on each core, Fig. 28 (not shown). Several cores 1-5 may be associated with separate input and output windings n1-n5 and N1-N5, Fig. 30. A common A.C. and D.C. supply AB is used, and outputs are produced by those cores to which input signals are not applied. A code switching arrangement is shown in Fig. 31 in which the outputs xy, xy, xy and xy are produced at 61, 62, 63 and 64, respectively, in response to the combination of any two input signals x, y, x, y.