Patent GB-974666-A (GB)
Title: Logical element
IPC: H03K19/16
Filed: 1961-08-03
Abstract: 974,666. Circuits employing bi-stable magnetic elements. KOKUSAI DENSHIN DENWA KABUSHIKI KAISHA. Aug. 3, 1961 [Aug. 3, 1960 (3)], No. 28217/61. Heading H3B. An information storage element comprises an even number of magnetic cores, each having at least one input and one output winding, the input winding being arranged in at least two groups so that input signals of a first or a second polarity, or of opposite polarities cause the cores to be set in one of four different patterns, the output windings being connected so that a read-out pulse produces in a load output pulses of first or second polarity, or no output pulse depending on the pattern of setting of the cores. In Fig. 3, cores M a , M b , M c  and M d  have an output winding N 0  connected to rectifiers D 1  to D 4  to form a bridge to which reading pulses are applied between T r  and T ra . The cores are initially set in the states (-)( + )( + )(-) by a current s, then signals y 1 , y 2  are applied to windings I 1 , I 2  simultaneously with a writing pulse w. If y and y 2  are in the same direction the cores are switched to the states ( + )( + )( + )( + ) or (-)(-)(-)(-) depending on the direction of the input signals, so that in the former case a subsequent reading pulse meets low impedance through the output windings of cores M a  and M c , and high impedance through those of cores M b  and M d , while in the latter case, the impedances are reversed. Current therefore tends to flow downwards through load Z1 in the former case (+1) and upwards in the latter case (-1). If y 1  and y 2  are in opposite directions the cores are switched to (+)(+)(-)(-) or (-)(-)(+)(+) and a reading pulse then meets low impedance through the windings of cores M a  and Md, or of cores Mb and M c , respectively, and substantially no output current is produced (0). The arrangement may be used to control the transfer of a binary digit x to a memory element by providing a control signal z = 1 when x is to be transferred, and z = 0 when x is not to be transferred, and making y 1  = x.z and y 2  = x+z. Additional divided input windings may also be provided (Fig. 4), to which signals x 1 , x 2 , y 1 , y 2 , z 1 , z 2  are respectively applied. If y 1  = v, y 2  = v, z 1  = 0 and z 2  = 1 (v being a " transfer " command signal) then the transfer of signals x 1 , x 2  corresponding to binary information x to a memory can be controlled by controlling v. The threevalued output of the arrangement of Fig. 3 or Fig. 4 may be applied to two windings of a four core device described in Specification 949,038, a third input winding being supplied with a binary input C (0 or 1). Using the Fig. 4 arrangement, depending on the values of C, z 1  and z 2 , the system may be adapted to produce outputs corresponding to the logical functions (x 1 +y 1 )(x 2 +y 2 ), x 1 y 1 x 2 y 2 , or x 1 +y 1  +x 2 +y 2 . In a modification of the Fig. 3 embodiment (Fig. 5, not shown), the input winding is further divided, with a separate input for each core, to give a five-valued output (2), (1), and (0). A similar modification of the Fig. 4 embodiment is shown in Fig. 6 and this arrangement may be used in conjunction with the device described in Specification 949,038 to obtain the logical product x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4 , and the logical sum x 1 +x 2 +x 3 +x 4 +y 1 -y 2 +y 3 +y 4 , of eight inputs. A device using only two cores is also described (Fig. 7), in which each output winding is connected in series with a rectifier and one of two similar loads Z l1 , Z l2  across the reading pulse source. If both inputs are in the same direction the cores are switched to (+)(+) or (-)(-), so that one output winding presents a higher impedance than the other and most of the reading current passes through one or other load. If the inputs are in opposite directions both output windings present equal impedance and the two loads carry equal currents. The loads may be head windings of a magnetic memory drum.  Production of reading pulse r. It is stated that when using the device to write information into a magnetic drum memory apparatus a (0) output pulse should be of longer duration than a (1) in order to ensure complete erasure of a (1) already in the memory. This is accomplished (Fig. 9) by applying clock pulses to two gate circuits with gates G p  and G n  respectively controlled by a (1) and a (0) of the information already written into the memory. A delay unit D imparts a delay to the pulses reading gate G p . The outputs of the gates are applied to multivibrators which determine the width of the reading pulses. The multivibrator outputs are then passed to a coupling device CD and power amplifier PA.