Patent EP-0545266-A2 (EP)
Inventor: NAKAYAMA HIROSHI
IPC: H02M3/07
Filed: 1992-11-25
Abstract: An LSI containing a voltage drop circuit for dropping an external power source voltage to obtain an internal power source voltage and a substrate biasing voltage generator circuit for applying a reverse biasing voltage to a semicondictor substrate thereof having one surface formed with an internal circuit is disclosed in which a delay of start of operation of the LSI and an increase of power consumption due to delay of increase of the internal power source voltage as an operating power source voltage of said substrate biasing voltage generator circuit after the application of the external power source voltage are avoided. 
     The LSI includes the voltage drop circuit for generating the internal power source voltage, the substrate biasing voltage generator circuit for generating the substrate biasing voltage and a power-on circuit for monitoring a voltage rising rate of the external power source after application thereof. The substrate biasing voltage generator circuit includes a standby mode substrate biasing voltage generator circuit portion operable when the LSI is in a standby mode and an active mode substrate biasing voltage generator circuit portion operable at a time the external power source voltage is applied and when the LSI is in an active mode. The active mode substrate biasing voltage generator circuit portion is responsive to a control signal generated by the power-on circuit according to a result of the monitor to switch its substrate current absorbing capability at the application of the external power source voltage to the LSI in two steps. 
     In the LSI according to the present invention, with the application of the external power source voltage, the power-on circuit causes the active mode substrate biasing voltage generator circuit to be operated with the external power source voltage and then with the internal power source voltage. Therefore, even if there is a delay in rising of the internal power source voltage in an initial stage of the application of the external power source voltage, the substrate biasing voltage is lowered at a higher rate than when it operates with only the internal power source voltage, reliably following the rising of the external power source voltage, so that the biasing voltage reaches a predetermined voltage value reliably at a start of operation of the LSI. Therefore, there is no increase of power consumption of the LSI after start of operation due to reduced threshold voltage of the MOS transistor which is caused by delay of reduction of the substrate biasing voltage due to delay of operation of the voltage drop circuit. 
     In the conventional 16 M bits DRAM, when the substrate biasing voltage generator circuit is operated with the internal power source voltage of 3.3 V obtained by dropping the external power source voltage of 5 V to apply a substrate biasing voltage of -2.2 V, there may be a case where the standby current in the standby mode is increased from 300 A to about 1 mA depending upon a delay of rising rate of the internal power source voltage. There is no such increase of power consumption or damage of memory cell content in the 16 M bit DRAM to which the present invention is applied.