Patent GB-713620-A (GB)
Title: Improvements in devices for separating synchronizing pulses and signal pulses in pulse-code modulation systems
IPC: H01F7/02
Filed: 1952-11-25
Abstract: 713,620. Multiplex pulse code signalling; pulse circuits. PHILIPS ELECTRICAL INDUSTRIES, Ltd. Nov. 25, 1952 [Nov. 28, 1951], No. 29788/52. Addition to 698,708. Classes 40 (5) and 40 (6) The device for separating synchronizing pulses, indistinguishable from channel pulses but occurring with invariable periodicity in a multiplex train of code pulses, described in the parent Specification, is modified by the addition of a local pulse generator switched on by a relay, which operates when the selection of synchronizing pulses has been achieved, and synchronized thereby. In one embodiment, the incoming pulse train is fed to a gate circuit 1, Fig. 1, which opens only for the synchronizing pulses, when the initial hunting has ceased, and passes them to the output circuit 8. The gate 1 is controlled by a flip-flop circuit 2 which is operated to close the gate when a pulse passing through and applied to a delay line 6 reaches the tapping 3. The condition of circuit 2 is reversed again when the pulse reaches tapping 4 to re-open the gate after a period shorter than one synchronizing cycle but longer than one synchronizing cycle less one signal interval. After a period of hunting only synchronizing pulses pass the gate. When this occurs, the number of pulses at the output of a coincidence circuit 12, fed with synchronizing pulses delayed by one cycle in line 6 and the incoming multiplex train, reaches a maximum and relay 11 operates to close switch 9. The pulses from line 6 are then fed to a regenerator 10 and thence over conductor 7 back to the input of the line. The closed loop thus formed acts as a continuous source of pulses for the output circuit 8, the pulses being synchronized by the incoming synchronizing pulses. The relay 11 may alternatively be operated by a pulsetime demodulator controlled by the selected pulses. In a second embodiment, the incoming pulse train is applied to terminals 21, Fig. 4, and thence to the control grid of valve 22 of the gate circuit 1, the suppressor 'grid being connected to a potential divider 26 across the output of'the flip-flop circuit 2 comprising valves 27, 28. The output circuits of the gate 1 and flipflop 2 are connected to tappings 18, 19 respectively of a delay line 17 which is correctly terminated at end 25 and short-circuited at end 15. The gate being open, a synchronizing pulse applied at tapping 18 reaches tapping 19 to reverse the state of flip-flop 2 and close the gate. Just before the next synchronizing pulse is due the pulse reflected with reverse polarity from end 15 of line 17 reaches tapping 19 and operates the flip-flop again to re-open the gate. The negative pulses at tapping 18 provide the output separated synchronizing pulses and are fed over lead 7 to the output stage 8, the rectifiers 32, 33 ensuring that valve 34 thereof is operated only by negative pulses. The relay 11, 9 is operated to introduce the local generator by the coincidence valve 41 when the synchronizing pulses have been selected. These pulses are fed ,to the control grid and the suppressor grid is fed by pulses from the terminated end 25 of delay line 17 at which pulses arrive delayed by one synchronizing cycle. Otherwise this circuit 12 operates as in Fig. 1. When switch 9 closes, valve 37 is rendered operative by connecting its screen grid potential and, under control of flip-flop 2 on its suppressor grid, passes pulses from end 25 of line 17 to tapping 18 to form the local pulse producing loop.