baber/WOPTO huggingface dataset:
Patent TW-I266456-B (TW)
Title: Manufacturing method of connector terminal
Inventor: CHAN PO-TSANG
IPC: H01R13/04
Filed: 2003-02-20
Granted: 2006-11-11
Abstract: The present invention relates to a manufacturing method of connector terminal. A terminal module having plural conductive terminals and material tapes is formed by pressing the metal sheet. The conductive terminal has an opposed connection section, and the rear side of the opposed connection section has an engagement section, a soldering section and a bending section sequentially. The bending section of the conductive terminal is extended and connected to the material tape, so that the plural conductive terminals and material tapes form a flat sheet. With only one bending, the engagement section of the conductive terminal can be engaged with the insulation seat body of the preset connector in the perpendicular direction, so as to effectively prevent the situation that the conductive terminal is bent/deformed at high temperature when the connector is in soldering furnace, and to increase the production efficiency and save the working time/cost of the manufacturing process greatly.
Patent TW-595001-B (TW)
Title: Manufacturing method of thin film transistor
Inventor: WANG CHENG-CHI
IPC: H01L29/786
Filed: 2003-03-05
Granted: 2004-06-21
Abstract: A manufacturing method of thin film transistor is disclosed in the present invention. First, the gate, the insulation layer, the semiconductor layer and the doped semiconductor layer are formed on the substrate in sequence. Then, the semiconductor layer and the doped semiconductor layer are patterned to form a layer-shaped island. After that, the barrier layer and the photoresist (PR) layer are sequentially formed; and the PR layer is patterned to make it have the first opening and the second opening, which are opposite to two edge regions of the layer-shaped island, respectively. The second conductive material is filled into the first opening and the second opening. Then, the PR layer is removed to form the first electrode and the second electrode. Finally, by using the first electrode and the second electrode as the mask, the barrier layer and the doped semiconductor layer are removed.
Patent TW-591470-B (TW)
Title: Dynamic combined website advertisement publication and broadcast management system and method thereof
Inventor: YANG JOE
Filed: 2003-03-07
Granted: 2004-06-11
Abstract: A dynamic combined website advertisement publication and broadcast management system and method thereof can actively go through dynamic link to connect to advertisement database and instantaneously acquire multiple advertising contents for editing and then insert to interconnected web page when website system generates web page link request so that the combined website advertisement in single advertising layout page of connected web pages can be broadcasted. The dynamic combined website advertising publication and broadcast system primarily comprises the advertisement publication system, advertisement database and advertisement broadcasting system for providing all sorts of advertisement publication management operation and executing broadcast procedures for all sorts of advertisements.
Patent TW-588350-B (TW)
Title: Testing machine of optical disc
Inventor: KAO CHIH-WEN
IPC: G11B7/26
Filed: 2003-03-11
Granted: 2004-05-21
Abstract: A kind of testing machine for optical disc includes a supporting apparatus and an adding force apparatus. The supporting apparatus is used for supporting optical disc. The adding force apparatus is used to add force to the optical disc.
Patent TW-I223455-B (TW)
Title: Crystalline silicon TFT panel having multi-gate structure used for LCD or OELD
Inventor: LEE SEOK-WOON
IPC: H01L33/00
Filed: 2003-05-01
Granted: 2004-11-01
Abstract: The present invention is related to a kind of crystalline silicon thin film transistor (TFT) for TFT-LCD or organic electroluminescent display (OELD). According to the present invention, in the pixel region of TFT panel, metal induced lateral crystallization (MILC) is used to form a pixel transistor and a storage capacitor containing a crystalline silicon thin film; and a driving transistor is formed in the driving circuit region of TFT panel. In addition, two or more than two gate electrodes are formed on the pixel transistor so as to effectively lower the turning-off current of the pixel transistor. Therefore, the invention has the required advantage of semiconductor device, in which the pixel transistor of TFT panel and the driving circuit can be manufactured at the same time through a relatively simple way of manufacturing, and the characteristics of turning-off current and turning-on current required for the pixel transistor and the driving circuit, respectively, can be satisfied simultaneously.
Patent TW-I334701-B (TW)
Title: Digital receiver arrangement and related method
Inventor: PETER ALAN LEWIS
IPC: H04L27/26
Filed: 2003-06-23
Granted: 2010-12-11
Abstract: The present invention provides for a digital receiver arrangement and related method, in which a digital receiver arrangement comprises a tuner/demodulator circuit, an analogue-to-digital converting means, and further includes means for storing an impulse wavelet representation, means for determining if an interference impulse is present in a received signal, and means for introducing the stored representation of the impulse wavelet to a detected received impulse so as to counteract the effect thereof within the received signal.
Patent TW-I259007-B (TW)
Title: System and method for tight inter-working between wireless local area network (WLAN) and universal mobile telecommunication systems (UMTS)
Inventor: MENON NARAYAN PARAPPIL
IPC: H04L12/56
Filed: 2003-07-01
Granted: 2006-07-21
Abstract: In a system having a PLMN and a WLAN IP GW, an Inr interface providing handover between a PLMN and the WIP-GW. Mobile Internet protocol (Mobile IP) provides session management and data tunneling between the PLMN (home agent) and the WLAN. The WIP-GW functions as the foreign agent toward the PLMN. Services are provided by the PLMN MIP over DIAMETER for registration, authentication and subscriber management, working into the HLR/HSS and the CGF in the PLMN. The use of single architecture to support the loose inter-working scenarios is such that the architecture minus the Iur interface and MIP becomes a loose inter-working architecture. The UMTS PLMN billing platform is made via the DIAMETER/UMTS inter-working. Authentication is provided by the UMTS PLMN HSS/HLR. The architecture concept can be broadened to cover the inter-working of other access technologies with UMTS.
Patent TW-I224032-B (TW)
Title: Method for processing and reducing waste glass materials into thermal insulation ceramic tiles
Inventor: CHYN WEN-LONG
IPC: B09B3/00
Filed: 2003-07-11
Granted: 2004-11-21
Abstract: This invention relates to a method for processing and reducing waste glass materials into resources, particularly to one for recycling and reducing waste glass materials into thermal insulation ceramic wall tiles and floor tiles, wherein the waste glass materials are added with clay materials and foaming agents, and stirred, ground and dehydrated to form particles. A forming machine then uses a mold to compress and form preforms of all kinds of sizes, which are subject to a kiln for foaming and sintering, heat treating, cooling and then removed from the kiln thereby obtaining thermal insulation ceramic wall tiles and floor tiles. If secondary processing is required, the products may further be decorated with glaze, trimmed, edge/surface ground to obtain special decorative effects thereby recycling the resources.
Patent TW-I221932-B (TW)
Title: Optical system for projection display and projection method thereof
Inventor: CHANG SEAN
IPC: G02B5/04
Filed: 2003-07-24
Granted: 2004-10-11
Abstract: An optical system for projection display includes a light source, a light path switch and prisms. The prisms are disposed between the light path switch and a projection lens, and at least two gaps are formed between adjacent prisms. Light provided from the light source is incident on the light path switch by the total reflection occurring in the interface between the gap and the prism that the light first encounters. A micro-mirror array composed of a plurality micro-mirrors is formed on the light path switch, and the light path switch is adjustable between a ""light-state"" position and a ""dark-state"" position by the way of changing the tilt of the micro-mirrors. Under the ""light-state"" position, light reflected from the light path switch passes through the prism and into the projection lens; under the ""dark-state"" position, light reflected from the light path switch is further reflected, by total reflection, at the interface between the gap and the prism that the light reflected from the light path switch first encounters.
Patent TW-I259184-B (TW)
Title: Gas phase polymerization process
Inventor: EHRMAN FRED D
IPC: C08F210/16
Filed: 2003-09-04
Granted: 2006-08-01
Abstract: A gas phase polymerization process for producing a polyolefin composition is described, which includes passing a gaseous stream containing hydrogen gas and one or more monomers, including ethylene monomers, through a reactor that includes a fluidized bed, under reactive conditions, in the presence of a catalyst that includes metallocene, to provide a polyolefin composition, wherein in one embodiment the fluidized bulk density is 60% or more of the settled bulk density (or, a voidage of 40% or less); and wherein the voidage is controlled by a number of factors including, in certain embodiments, (a) the reactor temperature being maintained at 100 DEG C or below; (b) the molar ratio of hydrogen gas to ethylene introduced into the reactor being 0.015 or below.
Patent TW-I220314-B (TW)
Title: Manufacturing method of deep sub-micron meter process of electrostatic discharge protection apparatus
Inventor: GAO RONG-ZHENG
IPC: H01L23/60
Filed: 2003-09-12
Granted: 2004-08-11
Abstract: The present invention reveals a kind of manufacturing method of deep sub-micrometer process of electrostatic discharge (ESD) protection apparatus. In the deep sub-micrometer process, self-aligned silicide is applied in the transistor source/drain regions including the ESD-protection device, and non-uniformly high current causes damage of ESD protection device; to improve the problem, a self-aligned silicide blocking-manner is adopted in the present invention. Inside the ESD protection device region, no silicide is formed; and a resistance buffer region is disposed between the drain contact and polysilicon gate such that it is capable of having one more uniform manner to eliminate the high current generated by ESD, so as to prevent the ESD protection structure from being damaged.
Patent TW-I233188-B (TW)
Title: Quad flat no-lead package structure and manufacturing method thereof
Inventor: PAN JUI-HSIANG
IPC: H01L23/498
Filed: 2003-10-07
Granted: 2005-05-21
Abstract: The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The chip package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.
Patent TW-I237381-B (TW)
Title: Semiconductor packaging substrate for diminishing impedance mismatch within adjacent conductive through holes
Inventor: HSIEH TSUNG-TIEN
IPC: H01L23/538
Filed: 2003-10-15
Granted: 2005-08-01
Abstract: A semiconductor packaging substrate for diminishing impedance mismatch of high frequency of products is proposed, which includes a substrate body having a plurality of conductive vias formed therethrough, wherein at least two adjacent conductive vias are managed to form a differential pair. At least an electrically consolidating layer, such as a grounding layer or a power layer, is formed in the substrate body. Then the region of the electrically consolidating layer between the differential conductive vias is removed to form a hole whose cross-section is of an area sufficient to accommodate the differential conductive vias. By this arrangement, capacity effect between the differential conductive vias and the electrically consolidated layer can be decreased to reduce resist enhancement. Therefore, the impedance mismatch can be diminished, so as to adapt requirement of wires connection of high frequency product.
Patent TW-I232978-B (TW)
Title: Driving method for display
Inventor: CHEN CHIEN-PIN
IPC: G09F9/35
Filed: 2003-11-20
Granted: 2005-05-21
Abstract: The present invention relates to a driving method for display, which is applied on a display. It comprises the following steps: apply a first signal on a common line, which is switched between a first electrical potential and the ground potential, so as to select the pixel; apply the second signal on the segment line of the selected pixel, which is different in phase with the first signal and which is switched between the second and third electrical potentials, so as to drive the selected pixel into a reflective state; apply the third signal on the segment line of the selected pixel, which has the same phase as the first signal and which is switched between the second and third electrical potentials, so as to drive the selected pixel into a transparent state; apply the fourth signal fixed at the fourth electrical potential on the common line of the selected pixel, so as to release the selected pixel; wherein the first, second, third, and fourth electrical potentials have the same polarity with respect to the ground potential, and their values are made such that the differential signal between the common line and segment line in each pixel is centered at the ground potential in each pixel.
Patent TW-I319399-B (TW)
Title: Biguanide and dihydrotriazine derivatives
Inventor: DAVID P JACOBUS
IPC: C07D317/64
Filed: 2003-11-21
Granted: 2010-01-11
Abstract: Biguanide and dihydrotriazine derivatives, preferably substituted asymmetrical imidodicarbonimidic diamides derived from hydroxylamines, and compositions containing biguanide and dihydrotriazine derivatives are disclosed. In addition, methods of using the biguanide and dihydrotriazine derivatives, inter alia, as antimicrobial agents and methods of using the dihydrotriazine derivatives in biological assays are disclosed. Methods of making the biguanide and dihydrotriazine derivatives are also disclosed.
Patent TW-I246393-B (TW)
Title: Heat dissipation module
Inventor: HUANG CHUNG-YUAN
IPC: H05K7/20
Filed: 2003-12-31
Granted: 2005-12-21
Abstract: A heat dissipation module for carrying a projector-power board and a projector-ballast board, and dissipating heat therefrom is provided. The heat dissipation module comprises a frame and a heat dissipation device, wherein the frame comprises an air inlet and an air outlet. The projector-power board and the projector-ballast board are fixed in the frame, and an air duct is formed by the air inlet and the air outlet. In addition, the heat dissipation device is assembled on the air outlet of the frame, it can provide strong convection of air at the same time to enable the heat dissipation device to dissipate heat from the projector-power board and the projector-ballast board outside the frame.
Patent TW-I271609-B (TW)
Title: Clock generator and frequency multiplexer circuit
Inventor: LIU CHUN-CHIH
Filed: 2004-02-09
Granted: 2007-01-21
Abstract: A clock generator has the first PLL (phase lock loop), the second PLL and the third PLL. The first PLL receives an input oscillation signal and an input clock signal, which need to spread spectrum, to generate the first clock signal and the second clock signal. The first PLL chooses the first or the second clock signal to generate the third clock signal. Otherwise, the second PLL receives the input oscillation signal to generate the fourth, the fifth and the sixth clock signals. Then, the third PLL receives the input oscillation signal to generate the seventh and the eighth clock signals. The present invention only need one input oscillation signal, then the present invention could generate the plurality of output clock signals.
Patent TW-I242264-B (TW)
Title: Nonvolatile memories with a floating gate having an upward protrusion
Inventor: DING YI
IPC: H01L29/423
Filed: 2004-02-12
Granted: 2005-10-21
Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are presented in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.
Patent TW-I339212-B (TW)
Title: Preparation of tetrahydrofuran copolymers
Inventor: HAUBNER MARTIN
IPC: C08G65/26
Filed: 2004-03-31
Granted: 2011-03-21
Abstract: The present invention relates to a process for the single-stage preparation of polyoxyalkylene glycols by copolymerization of THF and alpha, omega-diols in the presence of a heteropolyacid, wherein the content of organically bound nitrogen in the alpha, omega-diol is less than 15 ppm.
Patent TW-I241383-B (TW)
Title: Pump
Inventor: LIAU YAN-KAI
IPC: F04D5/00
Filed: 2004-05-12
Granted: 2005-10-11
Abstract: The present invention relates to a pump comprising an upper section, an intermediate section, and a lower section. The upper and lower sections of the pump each accommodate therein a circuit board on which a plurality of windings is provided in a spaced manner. The intermediate section of the pump accommodates therein a ring-configured vane assembly. A metal plate and a ring magnet are arranged below the ring-configured vane assembly. A liquid inlet tube and a liquid outlet tube are connected to a side wall of the intermediate section. Since the ring-configured vane assembly that is rotatable is arranged inside the intermediate section, when the windings are excited, the ring magnet and the ring-configured vane assembly can rotate in unison to draw a coolant liquid through the liquid inlet tube into the intermediate section of the pump to be driven by the ring-configured vane assembly for supplying through the liquid outlet tube toward a central processing unit arranged inside a notebook computer. With the increased power of the pump, the ring-configured vane assembly can rotate smoothly and effect excellent heat dissipation for the central processing unit.
Patent TW-I251202-B (TW)
Title: Correction of uneven image appearance by use of small-size data
Inventor: KAMADA TSUYOSHI
IPC: G02F1/133
Filed: 2004-05-13
Granted: 2006-03-11
Abstract: A circuit for display correction includes a memory which stores first data indicative of size and position of a rectangular region on a display screen and second data indicative of gray level changes in a surrounding region around the rectangular region in an isometric manner with respect to a horizontal direction and a vertical direction, and an image processing unit which adjusts gray levels of image data in response to the first data and the second data stored in the memory.
Patent TW-I250404-B (TW)
Title: Method of applying a flash memory as a buffer in an electronic appliance
Inventor: LIN CHIEN-YU
IPC: G06F12/02
Filed: 2004-07-20
Granted: 2006-03-01
Abstract: The present invention relates to a method of applying a flash memory as a buffer in an electronic appliance, comprising: installing a microprocessor in the electronic appliance, wherein said microprocessor receives or executes commands of a user; installing a flash memory in the electronic appliance, wherein said flash memory is connected to said microprocessor and comprises a file address table of a recordable file address and a data block for storing data or program. Furthermore, a portion of the flash memory can be allocated as a buffer, thereby effectively reducing the cost of using an additional RAM and I/O pins needed by the RAM externally connected to the microprocessor.
Patent TW-I276021-B (TW)
Title: Electro-optical device, method for manufacturing the same, and electronic equipment
Inventor: FUKUHARA KEIJI
IPC: G09F9/30
Filed: 2004-07-22
Granted: 2007-03-11
Abstract: The present invention provides an electro-optical device, method for manufacturing the same, and electronic equipment. The subject is to perform more stable operation of an electro-optical device by preventing moisture from entering into a laminated structure constructed on a substrate, in particular into a thin film transistor constituting a part thereof. The solution is provided by building a thin film transistor including data lines, scanning lines and a semiconductor layer on a substrate, and a pixel electrode to which a picture signal is supplied through the data line via the thin film transistor. The solution is further equipped with an interlayer insulating film disposed between the data lines and the pixel electrode and a passivation coating disposed on the surface of the interlayer insulating film.
Patent TW-I236058-B (TW)
Title: Method of performing double side processes upon a wafer
Inventor: SHAO SHIH-FENG
IPC: B81C1/00
Filed: 2004-08-06
Granted: 2005-07-11
Abstract: Primarily, a wafer having a front surface and a back surface is provided. Then, a first heat sensitive tape is utilized to fix the back surface of the wafer on a first carrier, and at least a semiconductor process is performed upon the front surface of the wafer. Following that, a second heat sensitive tape, having a separating temperature higher than that of the first heat sensitive tape, is utilized to fix the front surface of the wafer on a second carrier, and the first heat sensitive tape is heated to separate the wafer from the first carrier. Finally, at least a second semiconductor process is performed, and the second heat sensitive tape is heated to separate the wafer from the second carrier.
Patent TW-I257144-B (TW)
Title: Method of fabricating inlaid structure
Inventor: LIU CHI-WEN
IPC: H01L21/302
Filed: 2004-11-26
Granted: 2006-06-21
Abstract: A method of fabricating an inlaid structure. A sacrificial layer having a opening over a substrate is provided. A metal layer is deposited over the sacrificial layer filling the openings. A first CMP is performed to remove excess metal layer above the sacrificial layer to form an interconnect structure. The sacrificial layer is removed to expose the interconnect structure. A first low-k dielectric layer is deposited over the substrate covering the interconnect structure. A second CMP is performed on the first dielectric layer to planarize the first dielectric layer.