baber/WOPTO huggingface dataset:
Patent TW-466155-B (TW)
Title: Apparatus for improving the polishing uniformity in a chemical mechanical polishing system
Inventor: WU KUEN-LIN
IPC: B24B7/20
Filed: 1998-04-13
Granted: 2001-12-01
Abstract: An apparatus for improving the uniformity of semiconductor wafer surface processed by a chemical mechanical polishing system is disclosed. The apparatus comprises first a pressure regulating device used for increasing the pressure of slurry in the chemical mechanical polishing system. The chemical mechanical polishing system substantially comprises a plurality of polishing heads used for putting a plurality of semiconductor wafers closely onto a polishing pad and therefore the semiconductor wafer surfaces are respectively polished by the polishing pad. The apparatus also comprises a plurality of nozzles used for dispensing the slurry into a plurality of slurry streams. The surface of the polishing pad and the movement direction of the plurality of slurry streams are at an angle smaller than 90 DEG.
Patent TW-440838-B (TW)
Title: Semiconductor memory device performing a simple merged data test
Inventor: KWAK JIN-SEOK
IPC: G01R31/28
Filed: 1998-04-17
Granted: 2001-06-16
Abstract: A semiconductor memory device, including a plurality of local input output line groups, a plurality of global input output line groups, a plurality of memory blocks and a plurality of merged data test circuits, is provided. The plurality of local input output line groups are each comprised of a plurality of local input output lines, and arrayed in parallel to each other. The plurality of global input output line groups intersect with the local input output line groups, each is comprised of a plurality of global input output lines, and are arrayed in parallel to each other. The plurality of memory blocks which store data are each located between the local input output line groups, and electrically connected to the local input output lines. The plurality of switches are each installed at a predetermined one of the intersections between the local input output line groups and the global input output line groups, which electrically connect the local and global input output lines to each other, in response to a memory activation signal which becomes active when the memory blocks are activated. The plurality of merged data test circuits each have inputs which are connected to the global input output lines electrically connected to two neighboring memory blocks among the plurality of memory blocks. When the memory cells selected by predetermined row and column addresses in the memory blocks are all normal, the merged data test circuits output 1, and when any one of the memory cells selected by the predetermined row and column addresses in the memory blocks is faulty, the merged data test circuit electrically connected to the inferior memory block outputs '0'.
Patent TW-373150-B (TW)
Title: Apparatus and method for computer resources access control
Inventor: MIYAMOTO KOHTAROH
IPC: G06F9/38
Filed: 1998-05-12
Granted: 1999-11-01
Abstract: As one of a plurality of processing means requests an exclusive access to a portion of a resource, a lock range processing part 122 permits an exclusive access only when the process does not result in an inexpedience, for example, as other processing means is not permitted to gain an exclusive access to an overlapped portion. Further, the lock range of processing part 122 inhibits permission of an exclusive access to other portion overlapping a portion and permits an exclusive access to such portion as the number of permissions of exclusive accesses to other portion overlapping this portion exceeds a given number while an exclusive access to such portion is not permitted. The lock range processing part 122 thus prevents a starvation from occurring by limiting the number of permissions of an exclusive access to other overlapping portion passing a portion which overlaps the other overlapping portion.
Patent TW-368553-B (TW)
Title: Dual fuel nozzle for inhibiting carbon deposition onto combustor surfaces in a gas turbine
Inventor: LOPRINZO ANTHONY J
IPC: F23R3/28
Filed: 1998-06-26
Granted: 1999-09-01
Abstract: The dual-fuel nozzle for a gas turbine and combustor includes a liquid fuel nozzle surrounded by a gas fuel nozzle. A converging sleeve surrounds the converging outer wall of the combined liquid fuel and gaseous nozzle to form decreasing cross-sectional area in a downstream direction whereby air flow through the duct accelerates toward the conical droplet spray pattern emerging from the liquid fuel nozzle. An inside swirler is located upstream of the liquid fuel tip to swirl the air flowing through the duct. An outer swirler is provided about the downstream end of the sleeve, likewise to swirl air. The accelerated swirling air flow through the duct and outer swirling air flow preclude impingement of oil spray droplets onto metal surfaces of the nozzle and hence prevent carbon deposition thereon which would otherwise be deleterious to the liquid fuel and gaseous nozzles.
Patent TW-440619-B (TW)
Title: Method for detecting and displaying state of broken yarn in yarn storage unit
Inventor: YE TZ-BIN
IPC: D04B35/14
Filed: 1998-07-27
Granted: 2001-06-16
Abstract: Disclosed is a method for detecting and displaying state of broken yarns in a yarn storage unit, in which communication chips of various address codes are provided within the yarn storage unit. The chips are connected to a sensing rod switch. The communication chips of various yarn storage units are serially connected to a computer mainframe. The computer mainframe sends address codes to communication chips of each yarn storage units sequentially, such that when the address codes received by the chips are identical to its address switch, the state of broken yarns and the operation state of each component are sent to the computer mainframe and displayed by the monitor of the computer mainframe, for achieving the object of sensing the location of broken yarns and operation state of each component.
Patent TW-384572-B (TW)
Title: Clock recovery circuit
Inventor: TAKANORI SAEKI
IPC: G06F1/10
Filed: 1998-08-03
Granted: 2000-03-11
Abstract: A clock recovery circuit enables a time for obtaining synchronized state of one pair of gate voltage-controlled oscillator to be shortened in a phase locked loop (PLL). In the clock recovery circuit, data is inputted to a pulse-duration generating circuit, before generating pulse width less than 1/4 minimum data cycle from H of pulse, L of pulse, or both edges of H and L, thus the pulse is outputted both to a latched-circuit and a synchronous delay circuit. The synchronous delay circuit causes a delay time in proportion to data cycle to be generated at both edges of pulse or edge of two pulses, thus the delay time is maintained. An output pulse from a delay circuit is outputted both to a delay circuit and a latched-circuit by way of clock from the pulse synthesis circuit. The latched-circuit causes the data as an input to be latched by the clock from the pulse synthesis circuit, thus outputting regenerative data in company with the clock.
Patent TW-438629-B (TW)
Title: Method and arrangement to recognize the distribution-information on letters
Inventor: ZEHREN JURGEN
IPC: G06K9/03
Filed: 1998-09-23
Granted: 2001-06-07
Abstract: This invention relates to the recognition of distribution-information on letters with automatic OCR-reading and video-coding, in which at non-clear results in one of the automatic running OCR-steps said step holds in an actual state in order to read quickly and cheaply. >From the obtained clear and non-clear results/middle results now, a video-coding order with indication of the current result and the to-be-carried-out operations is automatically transmitted to one or more video-coding-areas so as to attain some clear results of said step. With said clear video-coding, which can replace said non-clear result, said held OCR-step can be ended successfully and the following step will be started.
Patent TW-460435-B (TW)
Title: Process for producing cycloolefin
Inventor: ASHIDA KEITA
IPC: C07C13/00
Filed: 1998-09-29
Granted: 2001-10-21
Abstract: A process for producing a cycloolefin by partial hydrogenation of a monocyclic aromatic hydrocarbon with hydrogen in the presence of a catalyst slurry comprising a ruthenium catalyst, water and a metal sulfate, which comprises a step of controlling the catalytic activity. The controlling step generally comprises at least one step of: reducing the catalytic activity by adding an alkaline compound; and enhancing the catalytic activity by adding sulfuric acid, to the catalyst slurry under the condition that the pH of the aqueous phase in which the catalyst is present, as measured at ordinary temperature and ordinary pressure, is within the range of from not less than 2.5 to less than 7.0. The addition may be carried out either during or prior to the reaction.
Patent TW-440973-B (TW)
Title: Bump tape carrier and producing method therefor
Inventor: AMANO TOSHIAKI
IPC: H05K3/24
Filed: 1998-10-07
Granted: 2001-06-16
Abstract: The bump tape carrier for mounting semiconductor chips on a circuit board is constituted of insulating films, conductive patterns which are formed on the insulating films, and metal bumps which are formed on the conductive patterns and are used to connect to semiconductor chips. Said metal bump has a cylindrical shape which actually has a vertical side against said surface of the conductive patterns as its feature.
Patent TW-439390-B (TW)
Title: Organic EL device and method of manufacturing the same
Inventor: FUKUZAWA SHINICHI
IPC: H05B33/10
Filed: 1998-11-20
Granted: 2001-06-07
Abstract: The present invention reveals a method of manufacturing organic EL device, which comprises the following steps: forming a plurality of stripes of a first electrode on the surface of a substrate extending in the same longitudinal direction of the substrate, forming a plurality of stripes of an insulating partition wall on said first electrode in the longitudinal direction perpendicular to said first electrode stripes, forming an organic layer containing a hole transporting layer, a light emitting layer and an electron transporting layer on these partition wall stripes, and forming a second electrode layer on the organic layer; adhering a sealing glass cap so as to cover the first electrode, the partition wall stripes, the organic layer and the second electrode, and evacuating the inside of said sealing glass cap, and irradiating a laser light from the outside of the sealing glass cap toward the partition wall stripes so as to separate the second electrode and the organic layer to form a divided groove on the partition wall. Since the separation of the second electrode by fusion is carried out in a vacuum, so that the metal chips 11 evaporated by photo-ablation on the inside surface of the glass cap will not contaminate the isolated portion, which prevents the shorting of the second electrode and increases the manufacturing yields in the manufacturing process.
Patent TW-390956-B (TW)
Title: Positioning mark and alignment method using the same
Inventor: MIYAKE EIICHI
IPC: H05K3/00
Filed: 1998-11-25
Granted: 2000-05-21
Abstract: Each of positioning marks of the present invention comprises a plurality of mark elements. The mark elements are adapted to be individually determined for their respective positions and configurations. A reference point of the positioning mark is located on the basis of data obtained by determining respective positions and configurations of the mark elements.
Patent TW-393812-B (TW)
Title: A manufacturing method of high-density electrical connector and its product
Inventor: LI MING-WU
IPC: H01R43/24
Filed: 1998-12-24
Granted: 2000-06-11
Abstract: This is a manufacturing method of a high-density electrical connector and its product.  The terminal and the insulation body of the electrical connector are bonded tightly with two injection molding steps after the electrical connector terminal is directly inserted in a mold.  A basic structure of the locating terminal is formed after the first injection molding, and the semi-finished product has properly-distributed runners and gaps to facilitate the second injection molding.  The second injection molding can be performed after properly adjusting the terminal positioning, and the final product of the electric connector can be obtained after assembling other elements.  With this invention, the terminal can be effectively positioned during the manufacturing process, and the high-density terminal and the insulation body of the electric connector can be conveniently assembled with a high assembly yield rate.
Patent TW-417063-B (TW)
Title: Improvements for a microprocessor with pipeline synchronization
Inventor: HELLER JR THOMAS J
IPC: G06F9/38
Filed: 1999-01-16
Granted: 2001-01-01
Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of said processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have said second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements. The second processor will have more pipeline stages than the first in order processor to feed the first processor and reduce the finite cache penalty and increase performance. The processing and storage of results of the second processor does not change the architectural state of the computer system. Results are stored in its gprs or its personal storage buffer. Resynchronization of states with a coprocessor occurs upon an invalid op, a stall or a computed specific benefit to processing with the coprocessor as a speculative coprocessor. In an alternative embodiment the foregoing process is generalized for both processors allowing processors to forward and store architectural state changes for future use as required by the other processor when at a later time the processor which is permitted to change the overall architectural state of said computer system is changed.
Patent TW-423058-B (TW)
Title: Method for simultaneously manufacturing poly gate and polycide gate
Inventor: YU JIUNN-LIANG
IPC: H01L21/28
Filed: 1999-01-29
Granted: 2001-02-21
Abstract: The present provides a method for simultaneously manufacturing poly gate and polycide gate. The method only requires one deposition process in depositing the common portion of gate oxide layer and polysilicon layer for the polysilicon gate and polycide gate, and each one is etched for one time, without being repeatedly deposited and etched. On the other hand, an oxide passivation layer is used as a mask of a silicide, which is the major component of the polycide gate, in etching polysilicon layer, so as to eliminate the problems in the prior art, thereby simplifying the manufacturing process, avoiding the generation of excessive spacer, enlarging the manufacturing window, being able to control the gate channel, and avoiding the loss of the gate top.
Patent TW-419592-B (TW)
Title: Current accumulating value detecting apparatus, current detecting apparatus and the battery set used
Inventor: NODA MASARU
IPC: G01R31/36
Filed: 1999-02-08
Granted: 2001-01-21
Abstract: This invention provides current accumulating value detecting apparatus, current detecting apparatus and the battery set used, which are not sensitive to the bias of operation amplifier. The invention includes the followings: a current detecting resistor connected in series with the current flowing path of battery; an integrator; an input status selector, which is used to guide the electric potential of two ends of the current detecting resistor into the integrator input; an integration capacitor connected to the integrator; an inverter of the integration capacitor provided between the integrator and the integration capacitor, which is to switch the connection polarity of the integration capacitor. This input status selector regularly interchanges the switching status a and the switching status b. At the status a, the voltage corresponding to the battery current value of two sides of current detecting resistor is guided into the input of integrator. At the status b, the voltage corresponding to the battery current value of two sides of current detecting resistor is inverted and guided into the input of integrator, or the voltage in between two ends of the current detecting resistor, under the assumption of zero battery current, is guided into the integrator input. This integration capacitor inverter makes the alternate inversion synchronously with the status a and the status b of the status selector so as to switch alternatively the connection polarity of the integration capacitor.
Patent TW-411540-B (TW)
Title: Stacked MCM micro ball grid array package
Inventor: CHIANG KUO-NING
IPC: H01L21/60
Filed: 1999-03-04
Granted: 2000-11-11
Abstract: The present skill relates to a stacked MCM micro ball grid array package, which re-designs the conventional single-chip micro ball grid array package to obtain a stacked MCM micro ball grid array package. In accordance with the present skill, the four sides of the chip are designed to have a local area without I/O terminals, so as to enhance the yield of the assembled product and disclose a novel stacked MCM micro ball grid array package. In accordance with the present skill, it is also applicable to install heat dissipation material into the product for increasing the heat dissipation effect, electrical performance, and product reliability. Furthermore, an encapsulation process can be performed to enhance the reliability of the product.
Patent TW-404101-B (TW)
Title: Oscillator starting method
Inventor: SANNER ANDERS
IPC: H03B5/26
Filed: 1999-03-11
Granted: 2000-09-01
Abstract: The present invention relates to a device for generating a sinewave output signal and comprising an oscillator. The oscillator includes means for respectively connecting and disconnecting one of the device supply voltages, such that when connecting said supply voltage the sinewave output signal will be stabilised after a time period corresponding to an interval of 1-5 periods of the sinewave output signal. The invention also relates to a method of quick-starting a sinewave output signal.
Patent TW-409309-B (TW)
Title: Semiconductor wafer mount-plate and semiconductor wafer polishing method using the mount-plate and management device thereof
Inventor: AZUMA JUNICHIRO
IPC: B24B37/30
Filed: 1999-03-23
Granted: 2000-10-21
Abstract: The object of the invention is to provide a semiconductor wafer mount-plate and semiconductor wafer polishing method using the mount-plate and management device thereof which eliminate the need for repairing of the mount-plates to efficiently polish the semiconductor wafers by preventing the deformation of the mount-plates due to the changes with age. To achieve the object, both a front face 11 and a rear face 12 of a mount-plate 1 are precisely flattened. The mount-plate 1 is inverted for each batch of polishing. In relation to the mount-plate 1 from which semiconductor wafers 10 are peeled off and which is cleaned, identification data and the surfaces in use are recognized, and the amount of deformation of the surfaces and the state of the frequencies of application, are sensed. When the deformation is not more than a specified value, the mount-plate is sent again to the process of mounting. When the deformation is more than the specified value, the mount-plate l is replaced with new one.
Patent TW-404110-B (TW)
Title: Using equalized data for filter selection in HDTV receiver
Inventor: NIELSEN LARRY E
IPC: H04N5/44
Filed: 1999-04-12
Granted: 2000-09-01
Abstract: A digital television receiver includes a filter for minimizing NTSC interference with a received signal having a constant symbol rate. An equalizer has two one-symbol delays for each tap. A filtered and a non-filtered version of the received signal are applied to a multiplexer at the input of the equalizer, which is operated at twice the symbol rate. The outputs of the multipliers in the equalizer are combined and applied to a demultiplexer. The filtered and non-filtered equalized signals are compared and a selection as to which of the filtered or non-filtered received signals is to be processed is made based upon the comparison.
Patent TW-446748-B (TW)
Title: Stabilizer composition for halogen-containing thermoplastic resin compositions
Inventor: REITH WALTER
IPC: C08K13/02
Filed: 1999-06-02
Granted: 2001-07-21
Abstract: The present invention relates to a stabilizer composition for halogen-containing thermoplastic resins, the stabilizer composition comprising (a) calcium hydroxide and/or calcium oxide which may optionally be surface-modified; and (b) a hydroxyl group-containing isocyanurate. This stabilizer composition is particularly suited for weather-resistant halogen-containing resin compositions such as rigid PVC.
Patent TW-460944-B (TW)
Title: Laterally diffused metal oxide semiconductor with gradient doped source/drain and manufacturing method thereof
Inventor: DUNG MING-TZUNG
IPC: H01L21/22
Filed: 1999-05-06
Granted: 2001-10-21
Abstract: The present invention relates to a method for forming a laterally diffused metal oxide semiconductor device. The method comprises the following steps. First, a conductive semiconductor layer is provided and then a field insulating layer is formed therein. Next, a gate dielectric area is formed over a portion of the field insulating layer and a first conductive drain region is formed in the semiconductor layer and adjacent to the field insulating layer that has a first doped concentration. A second conductive source/drain region is formed in the semiconductor layer and is separated from the field insulating layer by a channel region. A conductive lightly doped region is adjacent to the channel region and the filed insulating region wherein the conductive lightly doped region has a first doped concentration. The conductive main region is next to the filed insulating region and it has the first doped concentration smaller than the second doped concentration and is separated from the channel region. A conductive region is formed in the semiconductor layer and is separated form the first drain region by a channel region. A deep part of the conductive region is formed in the semiconductor layer and it has a third doped concentration smaller than the second doped concentration and is separated from the surface of the semiconductor layer.
Patent TW-457194-B (TW)
Title: Integrated power system for electric vehicles
Inventor: LIOU DAU-CHING
IPC: B60L50/15
Filed: 1999-05-07
Granted: 2001-10-01
Abstract: An integrated power system for electric vehicles is provided with a motor, a driving device, batteries, and an external power, in which the motor consists of three-phase coils, auxiliary coils and a rotor; the driving device is connected to the motor and consists of several switching devices; batteries supply driving electric power in normal mode to induce electromotive force in the three-phase coils by the switch control of the switch device in the driving device, and therefore drive the rotor of the motor; the external power supplies the auxiliary coils with alternating current in the charging mode, and induces electromotive force in the three-phase coils. Therefore, the batteries are charged by the switch control of the switch device.