Patent GB-983861-A (GB)
Title: Improvements in or relating to transistor logic circuits
Inventor: HOLMES BRIAN JAMES
IPC: H03K19/084
Filed: 1960-06-29
Abstract: 983,861. Transistor pulse circuits. INTERNATIONAL COMPUTORS & TABULATORS Ltd. June 9, 1961 [June 29, 1960], No. 22763/60. Heading H3T. In a pulse shaping circuit a transistor which is normally biased to cut-off has its base connected to a gating circuit responsive to input, timing and feedback pulses which cause the transistor to conduct and provide output signals the voltage of which is limited by a series arrangement of two limiting devices connected across the load to control maximum values of the collector voltage and the load voltage. Fig. 1 shows a circuit which may be modified as shown in Fig. 1 to accord with the invention. It comprises three " OR " gates 10, 11, 12 each comprising three diodes 13, 14, 15 connected respectively with " AND " gates 18, 19, 20 supplying a common diode gate 24 connected to the base of the transistor 36. Clock pulses are applied to the base over diode 27 and feedback from the output at 38 is applied to the base over diode 28. The emitter and collector are connected to ground over protective current limiting temperature dependent resistors 30 and 33 and the collector is connected to the primary winding of an output transformer 32 having secondary windings 38 . . . 41 connected in pairs in opposite senses through diodes 42 . . . 47 to provide outputs 44, 48, 45, 49, the amplitude of the former being 2 volts and the latter 2.7 volts. In operation, when a negative pulse e.g. binary digit 1, is applied to one or more inputs of the " OR " gate 10, diode 21 is cut off together with " AND " gate diode 18. Similar inputs to " OR " gates 11 and 12 cut off gate diodes 19, 20 thus opening the " AND " gate to cause current flow through diode 24 to either the base of the transistor 26, or a source of the clock signals in dependance on the polarity of the clock pulse. A negative clock pulse causes current flow to the base of the transistor 26 and a pulse in primary winding 31, which pulse appears as a negative-going output pulse at 44, 45 and a positive-going pulse at 48, 49. Feedback from the secondary winding 38 to the base of the transistor maintains conduction of the transistor until the clock pulse goes positive and this may extend over a number of digit periods. Negative swing of the collector and the output waves form is limited by diodes 36 and 42-47 thereby allowing rapid recovery of the circuit and the positive swing by a diode 37. Where some gates e.g. 11, 12 are not used, they may be maintained in the " open " state by connecting a diode to a source of negative potential through resistors 56. Alternatively, the corresponding " AND " gates may be broken by removable links. When the input pulses are applied to the " OR " gates through delay lines, clamping diodes e.g. 22 are provided to limit the input potential to the gate irrespective of the current supplied by the delay lines. In the modified collector circuit, Fig. 2, a Zener diode 53 limits the voltage swing across the transformer and a diode 37 limits the collector potential rise to - 1.5 V. In a further modification, the arrangement may be such that an output pulse is extended over a number of digit periods. Also the circuit may need to perform " inhibit " operations by maintaining the " OR " gates normally open by bias over resistors such as 56. In this case the gates are closed and opening of the " AND " gate and triggering of the transistor are prevented by applying positive-going " inhibit " pulses to the " OR " gates. False triggering of the transistor by spurious spike signals is overcome by applying a second clock signal from a source 55 over diode 54 in leading phase relation to the first clock, the phase difference being such that the " AND " gate is closed during the time period in which the spurious signals occur. Correctly terminated lines may provide the input signals.