Patent GB-1021927-A (GB)
Title: Pulse code signalling systems
IPC: H03M13/51
Filed: 1964-05-22
Abstract: 1,021,927. Multiplex pulse code signalling. STANDARD TELEPHONES & CABLES Ltd. May 22, 1964 [May 29, 1963], No. 21217/64. Heading H4L. In a pulse communication system for transmitting a first type of intelligence, e.g. speech, in the form of digital code groups and a second type of intelligence, e.g. data represented by code characters, means are provided for detecting idle intervals in the first type of intelligence and for transmitting the second type of intelligence only during those idle intervals. Transmitter.-Speech from source 2 is pulse coded at 1, the output of the coder being supplied to an AND gate 4 and to a demodulator 5. The output of the demodulator 5 is amplified at 6, rectified at 7 and compared in a Schmitt trigger 8 with a reference voltage which is below the lowest quantizing level in coder 1. If the output of rectifier 7 is above the reference level the output of trigger 8 is high and the " 1 " output of flip-flop 9 is also high and AND gate 4 will pass the output from coder 1 via OR gate 10 to the transmitter 11. When the talker pauses, the output from rectifier 7 and trigger 8 falls and AND gate 4 is blocked, but due to the inverter 8a an output is provided by AND gate 12 to trigger a generator 13 to generate a predetermined code pattern which is sent via OR gate 10 to alert the receiving equipment to accept data signals. When the code pattern has been transmitted a reset pulse is supplied from generator 13 to flip-flop 9 to provide an output at " 0 " thereby blocking gate 12 and enabling AND gates 14, 15. The next clock pulse, via AND gate 14, triggers the data storage device 16 to supply a character via a shift register 17, AND gate 15 and OR gate 10 to the transmitter and data will continue to be sent during the lull in the conversation. When the talker resumes, rectifier 7 causes trigger 8 to supply a large output and inverter 8a causes AND gate 14 to be blocked to prevent more characters being transferred to the register 17. When register 17 is empty a voltage on output 18 is supplied to AND gate 19 together with the " 0 " output from the flip-flop 9 and the output from trigger 8, thus triggering a generator 20 to transmit a code pattern via OR gate 10 indicating to the receiver that P.C.M. speech signals are about to be received. When thiscode pattern has been transmitted, generator 20 supplies a pulse set flip-flop 9 so that gate 4 is open for the P.C.M. signals. Receiver.-Receiving equipment 22 supplies the incoming signals to a shift register 23 whose output stages are sampled by a matrix 24 arranged to detect the code pattern of generator 13 or 20. During speech reception both flipflops 25, 26 are set and provide a high " 1 " output so that the P.C.M. speech signal is supplied via AND gate 27 and OR gate 28 to the demodulator. When the code pattern of generator 13 is detected, an output from the matrix 24 via AND gate 30 changes over the flip-flop 25 so that AND gate 27 is blocked AND gates 32, 33 are enabled, and via delay line 34 and AND gate 35 the flip-flop 26 is changed over. This allows AND gate 32 to pass data signals to the output circuit and AND gate 33 to pass data timing pulses. Also the " 0 " outputs of flip-flops 25, 26 are supplied via OR gate 135 to enable AND gate 36 which passes to the P.C.M. demodulator a predetermined code sequence from coder 37 which represents the zero level of the speech code. When the code pattern of generator 20 is recognized, the flip-flop 25 is reset and via delay 40 flip-flop 26 is reset so that P.C.M. signals are passed through the gate 27, the gate 36 being blocked. When the data signals cease the clock pulses are also blocked by gate 33 so that the storage device is not activated and space is not taken up by gaps n the data transmission.