Patent SG-11201809795V-A (SG)
Title: Memory access techniques in memory devices with multiple partitions
Inventor: QAWAMI SHEKOUFEH
IPC: G06F13/16
Filed: 2017-04-18
Abstract: Memory Controller 150-a 215-a 215-b 215-n Local Controller 0 Local Controller 1 Local Controller n 220-a 220-b 220-n r -1 Partition 0 Partition 1 • • • Partition n 225-a 225 b 225 n Data Buffer 0 1r\" ) Data Buffer 1 Ir j Data Buffer n (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 09 November 2017 (09.11.2017) WIP0 I PCT omit VIII Hot 0 omiolomoncio Elio lII ois (10) International Publication Number WO 2017/192259 Al (51) International Patent Classification: G06F 9 / 3 0 (2006.01) GOOF 13/16 (2006.01) G06F 3/06 (2006.01) (21) International Application Number: PCT/US2017/028177 (22) International Filing Date: 18 April 2017 (18.04.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/145,628 03 May 2016 (03.05.2016) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventors: QAWAMI, Shekoufeh; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). SUNDARAM, Rajesh; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, (54) Title: MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS Command — Addr Bus 110-a 210 FIG. 2 200 (57) : Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information. [Continued on next page] Data Bus WO 2017/192259 Al 0 111 TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3))