Patent GB-1239250-A (GB)
IPC: G11B5/74
Filed: 1968-09-27
Abstract: 1,239,250. Magnetic data stores. SPERRY RAND CORP. 27 Sept., 1968 [27 Sept., 1967], No. 46052/68. Heading G4C. [Also in Divisions H1 and H3] A magnetic storage element for use in DRO or NDRO modes comprises two pairs of magnetic thin film layers sandwiching a common bit/sense line 20 each pair of layers consisting of one layer 32 or 36 of relatively high H K  and the other film 30 or 34 of low H K  and having their easy axes 28 inclined to the direction perpendicular to the bit/sense line at an angle # at least as great as the dispersion angle α of the high H K  layers 32, 36. To write a " 0 " into the element in the NDRO mode a pulse is applied from pulse source 92 to the word line 90 to provide a magnetic field along axis 2-2 and saturate the magnetic films along this direction. When the pulse ceases the magnetization of the high H K  layers 32, 36 rotates back to the easy axis 28 and the field due to the H K  layers acts on the adjoining low H K  layers 30, 34 to bring their magnetization into antiparallel alignment with them, Fig. 10. To write a " 1 " in the element a transverse pulse from pulse 92 is applied to the word line 90 and before this pulse ceases a longitudinal pulse is applied from source 98 to the bit/sense line 20 which steers the magnetization of the layers back along the easy axis 28, the layers 34, 36 being steered in one sense and the layers 30, 32 being steered in the opposite sense, Fig. 11. In order to read out a reading pulse of much smaller amplitude than the write pulses is applied to the word line 90 and as it commences a strobe pulse is arranged to gate open amplifier 104. The reading pulse does not effect the magnetization of the high H K  layers 32, 36 and if a " 0 " is stored does not effect very much the magnetization of the low H K  layers 30, 34 since they are strongly influenced by the layers 32, 36 and no material output signal is induced in bit line 20. If a " 1 " is stored the magnetization of the low Hz layers 30, 34 are rotated along axis 2-2 and a pulse is induced in sense/bit line 20. After the strobe pulse terminates but while the read pulse is still applied a pulse is applied to the bit/sense line 20 which, if a " 1 " had been stored, steers the magnetization of the low Hz layers 30, 34 back into their original directions along the easy axis. DRO mode.-The element is first set into the state shown in Fig. 11 by applying a pulse to word line 90 and a steering pulse to the bit line 20 after the word line pulse has been established. The element is then operated in a succession of read/write cycles in which a read/write pulse of magnitude insufficient to cause switching of the high H K  layers 32, 36 is applied to word line 90. During the read part of the cycle the amplifier 104 is gated open and the voltage induced in the bit/sense line 20 is sensed by amplifier 104 which voltage will be positive or negative dependent on whether a " 1 " or " 0." is stored, Fig. 11 or Fig. 14 and is produced by rotation of the magnetization of the low H K  layers 30, 34. During the second half of the word line pulse a steering pulse of one or the other polarity is applied to the bit/sense line 20 to steer the magnetization of the low H K  layers into alignment with the easy action to store a " 1 ", Fig. 11 or a " 0 ", Fig. 14. Convertible memory operation.-The memory elements may be arranged in a store such that at any one time some are operating in the NDRO mode and others are operating in the DRO mode, Fig. 15. The memory elements of the store 120 are arranged in stacked plane arrays lying in the XY plane with word lines passing in the Z direction and coupled to one element in each plane. Each plane contains a single bit/sense line connected at one end to bit driver selector 122 and at the other end to the sense amplifier and gate selector 124. A word driver selector 128 is arranged so that parts of it may be selected to give either the write pulses and read-restore pulses of the NDRO to portion 120a of the memory or the read write pulses of the DRO to portion 120b of the memory 120.