Patent GB-1363581-A (GB)
Title: Complementary silicon-insulator-semiconductor field effect transis tor integrated circuit and a method for its manufacture
IPC: H01L27/092
Filed: 1972-05-01
Abstract: 1363581 Semi-conductor devices HUGHES AIRCRAFT CO 1 May 1972 [26 May 1971] 20206/72 Heading H1K  An integrated circuit comprises a pair of opposite conductivity SISFET devices 21, 23 (Figs. 1 to 4) formed in an, e.g. N-type semiconductor substrate 13 which has insulant layer 15 with a pair of openings therein for the SISFETS. Device 21 includes spaced source and drain regions 25, 27 formed in the substrate, between which a gate electrode 31 of polycrystalline Si is spaced from the surface by an insulant layer 29. A complementary region 43 of, e.g. P-type conductivity is formed in the substrate within which are formed N-type  source and drain regions 45, 47 between which a gate electrode 51 is spaced from the surface by insulant layer 49. Gate 31 is integrally part of the conductor overlying the insulant layer 15 to contact the N-type device 23 while gate 51 is integrally part of the similar conductor contacting other circuit components (not shown), and these conductors are covered by insulant layer 33. Other overlying conductors contact the source and drain regions 25, 27, 45, 47 through openings in layer 33. A portion 55 of the overlying conductors interconnects gate 31 to drain 47 and contacts 53, 39, 41 are further continuations of the overlying conductors, while the complementary substrate extends beyond source 45 to contact overlying conductor 57 through an opening of layer 33, and overlying conductor 59 contacts an extension of gate 51. In a modification using similar construction (Figs. 5, 6, not shown) formed three N-devices and three P-devices formed in a common substrate are interconnected into a three stage cirduit through two-level overlying insulated conductors, wherein an input signal is conditionally transferred through first stage MISFETS under control of gate signals to complementary inverting MISFETS feeding other MISFETS operating as rectifier and amplifier respectively. In fabrication, an oxide layer 15 is formed thermally on surface 14 of substrate 13 with openings 17, 19 over a masking layer of SiO 2  and Si 3 N 4  (Figs. 7a, 7b, 7c, not shown) after which a complenentary substrate is formed by boron doped oxide on surface 14 and thermally diffused in N 2  or by ion implantation. Thereafter, an electrically insulant oxide layer 135 (Fig. 7d) is thermally formed on the substrate surface 14 in oxidizing atmosphere, with a thin barrier layer of Si 3 N 4  thereon. A polycrystalline layer 137 is deposited on layer 135 from pyrolytic decompo - sition of silane and diborane doped with boron and overlain with layer of Si 3 N 4 , followed by a photoresist mask 141 which is removed from all areas except where layer 137 is to be retained (Fig. 7e) by etching with HF to leave a two layered mask of photoresist and Si 3 N 4 . The photoresist is removed and the polycrystalline Si layer is etched using the Si 3 N 4  as a mask, while exposed portions of the SiO 2  layer 135 are removed. The source and drain regions are doped in to the substrate and the complementary substrate by ion implantation or diffusion or boron or phosphorus using photoresist or SiO 2  masks, followed by thermal drive in (Fig. 7g). The remaining masks are removed and insulant layer 147 deposited, to cover all the conductors 137 and openings 17, 19 and oxide portions 15. Contact openings are etched to source, drain, and complementary substrate at 151, 153, 155 and also to expose selected parts of lower conductors 137. A layer of aluminium is evaporated over layer 147 and etched to define the required upper set of conductors (Figs. 7h, 7i).