baber/WOPTO huggingface dataset:
Patent TW-426588-B (TW)
Title: Porous abrasive grain grinding stone and its manufacture
Inventor: ISHIZAKI KOZO
IPC: B24D3/00
Filed: 1998-12-03
Granted: 2001-03-21
Abstract: To improve combining force between super abrasive grains and a combining material and improve weariness of the combining material in a grinding process and material of a grinding stone. The present invention provides a porous abrasive grain grinding stone which is characterized in that this grinding stone is made of super abrasive grains as abrasive grains and metal powder as a binder, the binder is formed in a porous body holding the super abrasive grains by chemically and physically binding, and after it is formed into the porous body, at least its surface is modified in ceramics. The present invention also provides a method to manufacture a porous grinding stone with materials of the super abrasive grains as the abrasive grains and the metal powder as the binder, which is characterized in that, firstly, ejection of the abrasive grains is controlled, and thereafter, a holding state of the abrasive grains is controlled. These super abrasive grains are diamond and cubic boron nitride, and the binder is more than one kind selected from a group consisting of Fe, Cu, Ni, Co, Cr, Ta, V, Nb, Al, W, Ti, Si and Zr, porosity of the whole grinding stone is 5-60%, favourably 5-45%.
Patent TW-426545-B (TW)
Title: Silver catalyst for production of ethylene oxide, method for production thereof, and method for production of ethylene oxide
Inventor: SHIMA MASAHIDE
IPC: B01J37/00
Filed: 1998-12-22
Granted: 2001-03-21
Abstract: A catalyst for the production of ethylene oxide is formed by causing a carrier having Α -alumina as a main component thereof to incorporate therein silica and a metal or a compound of at least one element selected from the elements of the groups Ib and IIb in the periodic table of the elements such as, for example, silver oxide and depositing silver on the carrier. The carrier is obtained by mixing at least Α -alumina, a silicon compound, an organic binder, and a compound of at least one element selected from the elements of the groups Ib and IIb in the periodical table of the elements and then calcining the resultant mixture at a temperature in the range of 1,000 - 1,800 DEG C.
Patent TW-404832-B (TW)
Title: The oral medicine with good stability cotaining the omeprazole or the analogues
Inventor: SHIU TZUNG-MIN
IPC: A61K31/454
Filed: 1999-01-27
Granted: 2000-09-11
Abstract: An oral pharmaceutical composition containing omeprazole or the analogues , that comprising: sugar seed: 6%-12% (w/w); drug layer;: omeprazole: 7.5%-14.5% (w/w); polyvinyl alcohol with molecule weight of 20,000-100,000: 0.1%-7%(w/w); sub-coating layer: 32%- 60% (w/w) as the adhesion agent and for spherical shaping; entero-coating layer: 26%-50% (w/w) as the entero-coating polymer.
Patent TW-424174-B (TW)
Title: Heat dissipation device of integrated circuit
Inventor: LIOU CHU-GANG
IPC: G06F1/20
Filed: 1999-02-19
Granted: 2001-03-01
Abstract: There is provided a heat dissipation device of integrated circuit, which comprises a fan, a control circuit, and a heat dissipation tube. The control circuit determines the rotation speed of the fan and the operating efficiency mode of the integrated circuit based on the load of the integrated circuit, the temperature of the integrated circuit, the ambient temperature, and a reference temperature. When the temperature of the integrated circuit is in a tolerant range, the heat dissipation tube is continuously used to dissipate the heat of the integrated circuit. When the control signal output from an adder is larger than a tolerant value, the fan is activated to dissipate heat based on the output value of the the control circuit.
Patent TW-444324-B (TW)
Title: Manufacturing method of dielectric layer with a low dielectric constant
Inventor: SHIAU JR-SHIANG
IPC: H01L21/76
Filed: 1999-03-05
Granted: 2001-07-01
Abstract: A manufacturing method of dielectric layer with a low dielectric constant comprises: forming a metal line on the substrate; forming a spacer on the sidewall of the metal line; forming an oxide layer on the substrate; and simultaneously forming voids in the oxide layer between metal lines by controlling the formation of the oxide layer.
Patent TW-541229-B (TW)
Title: Substrate retainer
Inventor: ZUNIGA STEVEN M
IPC: B24B37/28
Filed: 1999-05-05
Granted: 2003-07-11
Abstract: A retainer is used with an apparatus for polishing a substrate. The substrate has upper and lower surfaces and a lateral, substantially circular, perimeter. The apparatus has a polishing pad with an upper polishing surface for contacting and polishing the lower face of the substrate. The retainer has an inward facing retaining face for engaging and retaining the substrate against lateral movement during polishing of the substrate. The retaining face engages a substrate perimeter at more than substantially a single discrete circumferential location along the perimeter.
Patent TW-408051-B (TW)
Title: Welding method for heterogeneous metals
Inventor: JUNG CHING-CHI
IPC: B23K11/00
Filed: 1999-05-11
Granted: 2000-10-11
Abstract: This invention provides a method for welding different kinds of metals together. Especially, there is no need of any agent and filler in the welding processes. Under protection of an inert gas; utilizing the thermal energy, heat up two or more kinds of metal to an elevated temperature to make structures and crystals at the two metal contacting interface transform into a magnetic state to attract one another. This will cause the microstructure and crystals at the connecting interface of the two metals to have the same intergranular boundaries, so called intergranular boundary co-existing, and give tightly structure connection with each others.
Patent TW-523498-B (TW)
Title: Negative thermal expansion materials including method of preparation and uses therefor
Inventor: MERKEL GREGORY ALBERT
IPC: C04B35/495
Filed: 1999-05-15
Granted: 2003-03-11
Abstract: Negative thermal expansion materials, methods of preparation and uses therefor are disclosed. The materials are useful for negative thermal expansion substrates, such as those used for optical fiber gratings.
Patent TW-425568-B (TW)
Title: Memory with a test unit and its testing methods
Inventor: LEU ANTHONY
IPC: G11C29/00
Filed: 1999-05-28
Granted: 2001-03-11
Abstract: The present invention provides a memory having a test unit and its testing methods. The memory consists of several word lines, several bit line columns, several memory units, several data write-in units, several test units, and several bit line switches. Each bit line column includes binary bit lines. A memory unit is installed between every word line and every bit line of each bit line column. Each data write-in unit has two output ends and is electrically connected with a binary bit line of every bit line column to output two binary bit data having different directions. Testing methods for the memory include: (1) Use the word lines connected with the respective memory unit to activate the memory unit. (2) Use a data write-in unit connected with the respective memory unit to write a designated binary bit data into the memory unit through a specific output end of the data write-in unit connected with the memory unit and the bit line switch and the bit line connected with the specific output end. (3) Turn the respective bit line switch OFF after the designated binary bit data is written into the respective memory unit. (4) Use the test unit connected with the specific output end to test whether the binary bit data output from the respective memory unit to the respective bit line is the same as the designated binary bit data output from the specific output end before generating a corresponding test signal.
Patent TW-413887-B (TW)
Title: Method for forming trench-type power metal oxide semiconductor field effect transistor
Inventor: FAN JIUN-LIANG
IPC: H01L21/336
Filed: 1999-06-09
Granted: 2000-12-01
Abstract: The present invention provides a manufacturing method for trench-type power metal oxide semiconductor field effect transistor on a semiconductor substrate. The method comprises: firstly, forming pad oxide on the surface of semiconductor substrate and forming mask layer on the top surface of the pad oxide; then, etching the mask layer and pad oxide to define the trench pattern on the mask layer and pad oxide; next, using the mask as the etching mask to perform an etching process to the semiconductor substrate to form trench structure on the semiconductor substrate; then, forming gate oxide along the surface of trench structure; forming doping area in the semiconductor substrate for being used as the source in which the doping area contacts the lower surface of the pad oxide and is adjacent to the sidewall of trench structure; then, forming the side spacer on the sidewalls of mask layer and pad oxide and forming the field oxide on the top surface of conductive layer.
Patent TW-400408-B (TW)
Title: Building elements
Inventor: DOONAN ROSS
IPC: E06B7/23
Filed: 1999-07-03
Granted: 2000-08-01
Abstract: Leasable joint (1) includes a first member (2) having an elongate generally T-sectioned connecting formation (3) defining opposed securing flanges (4) and (5) respectively. The second part of the joint includes a second member (6) having a corresponding generally elongate undercut channel (8) in a surface (7) thereof defining, at the edge of said channel, two opposing retaining protuberances (9) and (10) respectively. The connecting formation and undercut channel are configured such that the channel (8) is adapted to: (i) receive therein from a direction generally transverse to the plane of said surface (7) the generally T-sectioned connecting formation (3) of the first member, and (ii) permit subsequent displacement of the connecting formation within the undercut channel (8) into a locking position wherein removal thereof in a direction transverse to said surface is prevented by said retaining protuberances (9) and (10). In the locking position a receiving groove (12) is simultancously defined along an edge of said channel immediately adjacent one of the securing flanges (4) or (5). The joint also includes an elongate resilient beading element (13) adapted to be captively retained upon insertion into said receiving groove (12) so as to urge and maintain said connecting formation (3) in the locking position within the undercut channel (8).
Patent TW-424041-B (TW)
Title: Method of producing multi-color zipper plate and structure thereof
Inventor: CHERN DANN-MING
IPC: B29D5/00
Filed: 1999-08-27
Granted: 2001-03-01
Abstract: The present invention relates to a method of producing a multi-colorful zipper plate and its structure. The method comprises separating forming a metal plate and a trademark block, and combining the two; injecting a surface layer to encompass the periphery and the surface of the metal plate and permanently fasten the trademark block on the metal plate to form a multi-colorful zipper plate. The structure of the multi-colorful zipper plate comprises a metal plate the surface of which has a positioning hole and a through hole; and a trademark block having a positioning block for inserting into the positioning hole of the metal plate for positioning. The through hole of the metal plate can be used for the attachment of the surface layer of a rubber (plastic) after injection forming for permanent fastening without falling off. The implementation of the present invention enables a zipper plate with a plurality of colors to further distinguish the trademark pattern.
Patent TW-443082-B (TW)
Title: Manufacturing method of wiring circuit board, and wiring circuit board
Inventor: OCHI HIROSHI
IPC: H01L21/48
Filed: 1999-09-27
Granted: 2001-06-23
Abstract: Fine lines of line width of 40 mu m or less are obtained stably without defect on a ceramic substrate, and hence a circuit board of high density and high precision is obtained. The method comprises: (a) a step of fabricating a ceramic substrate, (b) a step of polishing the surface of the ceramic substrate to surface roughness Ra of 0.5 mu m of less, (c) a step of forming a photosensitive conductor layer on the surface of the ceramic substrate, and (d) a step of processing the photosensitive conductor layer by photolithography, and forming a specified wiring pattern. The step of forming the photosensitive conductor layer includes a step of applying a photosensitive conductor paste on the surface of the ceramic substrate, and a step of drying the photosensitive conductor paste. The photolithography process includes a step of exposing the photosensitive conductor layer through a photo mask, and  a step of developing the exposed photosensitive conductor layer and removing the unexposed region. Herein, supposing the roughness curve to be y=f(x), the extracting length of the roughness curve in the center line direction to be L, the central axis of the extracting portion to be X-axis, and the direction vertical to the X-axis to be Y-axis, Ra is the value calculated in the formula.
Patent TW-487870-B (TW)
Title: Keyboard input devices, methods and systems
Inventor: WONG CONSTANT TSAI SHI
IPC: H03M11/04
Filed: 1999-10-22
Granted: 2002-05-21
Abstract: The application described a keyboard, specifically a Chinese language keyboard, but one which can be applied to other languages. The keyboard has a plurality of keys, each key having at least one unit associated therewith, the keys being so arranged that visually similar units are found on the same or an adjacent key, the arrangement being such that an operator may select at least one key which relates to the whole or part of the visual appearance of the required character, the arrangement being that after each key is entered it provides a mapped value which can be consistent with a character or a number of characters in a database, on a number of keys being entered a character which is unique to the keys is identified and can be displayed. Also described is a method of ascertaining a character using a keyboard as described above where each key is mapped and where there is more than one mode of operation of the key, the particular mode is differently mapped; the arrangement being such that after a key is actuated the mapped value of the key is recorded, when a second key is actuated the mapped value of this key is recorded and so on, the recorded values being used to search for a valid character using the values. The keyboard and the method are described in relation to word processing and the provision of a dictionary.
Patent TW-447214-B (TW)
Title: Dynamic focus voltage amplitude controller and high frequency compensation
Inventor: GEORGE JOHN BARRETT
IPC: G09G1/04
Filed: 1999-10-25
Granted: 2001-07-21
Abstract: A video imaging apparatus includes a cathode-ray tube (10) including a focus electrode (17). A source of a first parabolic signal (V5) at a frequency related to a deflection frequency, selected from a plurality of frequencies, has an amplitude determined in accordance with the selected frequency. A control circuit (Fig. 1B) has an input coupled to the source of the first parabolic signal (V5) for generating an output signal (OUT). The output signal is for maintaining the amplitude of the first parabolic signal (V5) for the plurality of deflection frequencies. An amplifier (97), that is responsive to the output signal, is coupled to the focus electrode (17) for amplifying the parabolic signal to generate a dynamic focus voltage at the focus electrode.
Patent TW-525320-B (TW)
Title: Manufacturing method of printed circuit board, printed circuit board, double-sided layout connection component of printed circuit board
Inventor: NOJIOKA SHINICHI
IPC: H05K1/11
Filed: 1999-11-02
Granted: 2003-03-21
Abstract: The subject of the invention is to realize high-density mounted double-sided circuit pattern that is capable of conducting printed circuit board (PCB), having high reliability at low cost and having no reduction of production characteristic. The solving method is described in the following. A device 10a for conduction is used. The device for conduction includes the followings: a plane portion 12, which can be suck and held through a mounting machine for surface mounting device; a wiring portion 13 of through hole 8, which can be inserted and formed on the PCB body 1, and a connection portion 14, which is connected to A face side of the PCB body 1. The plane portion 12 of the device for conduction 10a is suck and held through the mounting machine for surface mounting device, and is mounted on the PCB body 1. Therefore, by using soft soldering to adhere the device for conduction 10a to both faces of the mounted PCB body 1, the substrate 4 formed on A-face side of the PCB body 1 and the connection portion 14 of the device for conduction 10a can be connected. In addition, the wiring portion 13 and the substrate 5 formed on the periphery of through hole 8 on B-face side of PCB body 1 can be connected.
Patent TW-449897-B (TW)
Title: Semiconductor package
Inventor: WANG SHING-SHENG
IPC: H01L23/498
Filed: 1999-11-24
Granted: 2001-08-11
Abstract: A semiconductor package is disclosed, which has a semiconductor chip. A soft plate is pasted on the surface of the chip through a bonding layer. A center area of the chip or the peripheral I/O bond pad area is exposed to the bonding layer. There is an attached metal circuit on the soft plate whose surface has a plurality of protruded spots connected to said bond pad individually aligned as the bridge of electrical conduction. Said protruded spots are formed by sing mold to apply pressure on the metal plate with mechanical force or by other metal ball adherence method. There is a shadow mask of conductive ball located on top of the metal circuit. The exposed area is the ball-mounting area. The conductive ball is located above said ball-mounting area. The protruded spots are formed by applying pressure of external force on the exposed metal grid structure of the metal circuit, or formed by metal ball adherence. The metal grid structure can be located on the center area, area of both sides, or the area surrounding the conductive solder ball. A plurality of soldered solder balls are electrically connected to the printed circuit board. The solder ball is formed by BGA technology.
Patent TW-434665-B (TW)
Title: Multi-chip module structure
Inventor: LIN CHUN-HUNG
IPC: H01L21/00
Filed: 1999-12-31
Granted: 2001-05-16
Abstract: A multi-chip module structure is provided which includes at least two semiconductor chips, wherein each chip has a row of solder pads arranged at one edge on the front side thereof. The two chips stack each other and are disposed on a substrate, wherein the back side of the upper chip is placed on the front side of the lower chip and the solder pads on the lower chip are not covered by the upper chip so that the wire bonding process for the lower chip is not impeded. In the present invention, the two semiconductor chips stack each other and are disposed on a substrate, and then a wire bonding process is performed at the same time. Therefore, the wire bonding process can be performed in one step so as to increase yield per hour and reduce production cost.
Patent TW-439176-B (TW)
Title: Manufacturing method of capacitors
Inventor: HOU JIA-SHIN
IPC: H01L21/02
Filed: 2000-03-17
Granted: 2001-06-07
Abstract: The present invention provides a manufacturing method of capacitors, which is suitable for the hybrid circuit process. The method comprises: forming a first dielectric layer, a stop layer and a second dielectric layer on a substrate having a conductive region; next, forming a first opening in the second dielectric layer; then, forming a second opening in the stop layer and the first dielectric layer, such that the first opening and the second opening form a dual damascene opening exposing the conductive region; next, filling a first conductive body in the dual damascene opening for simultaneously forming a via plug and a bottom electrode of the capacitor electrically connected to the conductive region; forming a third dielectric layer on the substrate and between the upper and bottom electrodes, so as to fully cover the bottom electrode and part of the second dielectric layer adjacent to the bottom electrode; and forming a patterned second conductive layer on part of the third dielectric layer, thereby forming an upper electrode layer capable of fully covering the bottom electrode.
Patent TW-476890-B (TW)
Title: Punctuating method of sentence
Inventor: JOU PEI-LIN
IPC: G06F17/00
Filed: 2000-03-24
Granted: 2002-02-21
Abstract: The invention relates to a punctuating method of sentence, in particular a concept using probability and thermodynamics to organize and manage data in database, allowing user to be able to promptly and correctly acquire the required information in case of searching the relevant data.
Patent TW-477834-B (TW)
Title: Yarn heat treatment roller
Inventor: TANIGAWA MOTOHIRO
IPC: D06B23/02
Filed: 2000-08-14
Granted: 2002-03-01
Abstract: The object of the present invention is to provide a yarn heat treatment roller that improves the durability of a bearing by controlling the rise in temperature of the bearing. The yarn heat treatment roller of the present invention is provided with a ring-like dented groove 38 on a boss 15 of a roller main body 4 and a junction 37 of a revolving shaft 3, so that the conduction area S of the roller main body 4 and the revolving shaft 3 is reduced, and the conduction amount transferred to the inner rings of each bearings 11 and 12 is inhibited.
Patent TW-I225485-B (TW)
Title: Piperazine derivatives of formula (I), pharmaceutical composition for the treatment of conditions mediated by tachykinins of a mammal comprising them, and processes for preparing the same
Inventor: ALVARO GIUSEPPE
IPC: A61P25/06
Filed: 2000-10-07
Granted: 2004-12-21
Abstract: The present invention relates to piperazine derivatives of formula (I), R represents a halogen atom or a C1-4 alkyl group; R1 represents hydrogen or a C1-4 alkyl group; R2 represents hydrogen, a C1-4 alkyl, C2-6 alkenyl or a C3-7 cycloalkyl group; or R1 and R2 together with nitrogen and carbon atom to which they are attached respectively represent a 5-6 membered heterocyclic group; R3 represents a trifluoromethyl, a C1-4 alkyl, a C1-4 alkoxy, a trifluoromethoxy or a halogen group; R4 represents hydrogen, a (CH2)qR7 or a (CH2)rCO(CH2)pR7 group; R5 represents hydrogen, a C1-4 alkyl or a COR6 group; R6 represents hydrogen, hydroxy, amino, methylamino, dimethylamino a 5 membered heteroaryl group containing 1 to 3 heteroatoms selected from oxygen, sulphur and nitrogen or a 6 membered heteroaryl group containing 1 to 3 nitrogen atoms; R7 represents hydrogen, hydroxy or NR8R9 wherein R8 and R9 represent independently hydrogen or C1-4 alkyl optionally substituted by hydroxy, or by amino; R10 represents hydrogen, a C1-4 alkyl group or R10 together with R2 represents a C3-7 cycloalkyl group; m is zero or an integer from 1 to 3; n is zero or an integer from 1 to 3; both p and r are independently zero or an integer from 1 to 4; q is an integer from 1 to 4; provided that, when R1 and R2 together with nitrogen and carbon atom to which they are attached respectively represent a 5 to 6 membered heterocyclic group, (i) m is 1 or 2; (ii) when m is 1, R is not fluorine and (iii) when m is 2, the two substituents R are not both fluorine, and pharmaceutically acceptable salts, and solvates thereof.
Patent TW-544555-B (TW)
Title: Display assembly with contrast inversion including two superposed display devices
Inventor: NACI BASTURK
IPC: G04G/
Filed: 2001-02-19
Granted: 2003-08-01
Abstract: A second device (24) is mounted on a first device (22) formed of a liquid crystal (27"") display cell (26) at the front of which is arranged a first linear polariser (40), of a liquid crystal (29) optical valve (28) at the back of which is arranged a second polariser (44) and means (23) for controlling the valve (28) and the cell (26) from a switched state to a non switched state. When the cell (26) is switched to display a data item, by associating a first light or dark device (22) with a second absorbent or reflective polariser (44), an inversion of the contrast in said data is obtained by switching the valve (28).