Patent GB-1268898-A (GB)
Title: Improvements in or relating to redundancy reduction transmission systems and apparatus
Inventor: MOUNTS FRANK WILLIAM
IPC: H04N7/32
Filed: 1970-04-24
Abstract: 1,268,898. Video signal redundancy reduction. WESTERN ELECTRIC CO. Inc. 24 April, 1970 [30 April, 1969], No. 19715/70. Heading H4F. The apparatus for reducing the redundancy in a video signal consisting of frame and line portions is similar to that described in Specification 1,268,899 excepting that when a run of consecutive samples are all selected for transmission, and the address word is only transmitted with the amplitude word in the case of the first sample, a code word is transmitted after the amplitude and address words of the first sample, indicating the number of samples in the run having addresses consecutive on the first. In the group word assembler and code word generator shown in detail in Fig. 3, pulses # 1 , # 2 , "start run" SR, "continuing run" CR and "end run" ER, are produced from the transmit signal and the sample interval pulses # in the same manner as described in Specification 1,268,899. The amplitude words are passed to a gate 318 via a normally enabled gate 316, which is only inhibited during the blanking intervals by the sync. word detector 337. The first 8-bit amplitude word accompanied by a transmit signal produces an SR pulse and is fed via gate 318, enabled by the SR pulse via OR gate 319, to cells C 4  and C 5  of data register 320, with the four most significant bits in cell C 5 . The corresponding address word is fed to cells C 1  and C 2  via gate 322. The SR pulse puts a "1" pulse into stage S1 of flag register 321. Register 320 comprises four parallel stages per cell for the four bits of the words, and cells C 3  to C 36  may contain an extra stage forming the stages of register 322. The SR pulse is fed to five delay circuits 351/355 and produces therefrom on line 361 five closely spaced pulses which, on application to the shift inputs of the registers 320, 321, shift the address word and the amplitude word to cells C 6 , C 7 , C 9 , C 10  and the "1" state of stage S 1  to stage S 6 . All this is completed before the next sample. The second amplitude word, accompanied by a transmit signal and a CR pulse is passed into now empty cells C 4 , C 5  of register 320, via gate 318 enabled by the CR pulse. Gate 322 is not enabled so that the address word is not fed to the register. The CR pulse is fed to delay circuits 356, 357 to give shift pulses which shift the amplitude word for the second sample, and the address and amplitude words for the first sample to cells C 6 , C 7 , C 8 , C 9 , C 11 , C 12  and the "1" state to stage S 8 . This action is repeated for any succeeding transmitted samples, the amplitude words being all first placed in cells C 4 , C 5  and then shifted along two places and the "1" state also being shifted along two places. The CR pulses are counted at 323 to give a count of the number of samples in the run after the first sample. This count is read-out for short runs into memory 325 by the ER pulse at the end of the run. The code word being 'of M = 4 bits can only convey a count of up to 15. If a run contains more than 16 samples, then, when detector 330 determines that a count of 15 has been reached it produces a pulse which, at the next # 2  pulse, reads out the count in 323 in to the memory. The pulse from detector 330 also clears circuit 307 by OR gate 306 so that the next transmitted sample produces a new SR pulse and the circuit behaves as if a new run has commenced. Runs of greater than 15 samples are thus broken down into groups of 15. When the amplitude word of the first sample has reached cells C 35  and C 36 , a total of 15 samples (not necessarily from one run) have their amplitude words stored in register 320. The next pair of shift pulses read out the first amplitude word to the buffer amplifier via enabled gate 334. After this, the cell C 36  is empty and the "1" state reaches stage S 34  such that gate 335 is enabled by the next # 1  pulse. This enables gate 336 and reads out the sample count in memory 325. The count passes via gate 336 into the empty cell C 36  for transmission to the buffer by the next shift pulses, followed by the address word of the first sample. The sync. word is read into cells C 4 , C 5  for transmission.