Patent GB-1371815-A (GB)
Title: Digital echo suppressor
Inventor: FARIELLO E
IPC: H04B3/20
Filed: 1972-01-10
Abstract: 1371815 Echo suppression POST OFFICE 10 Jan 1972 [8 Jan 1971] 1046/72 Heading H4R In a communications system in which first and second transmission circuits interconnect first and second terminal units each having means for converting an analogue signal into a pulse code signal representing the instantaneous amplitude level of said analogue signal, there is provided in at least one of the terminal units apparatus for suppressing echo comprising means for detecting the instantaneous amplitude levels, represented by pulse coded signals, of incoming signals received over the first transmission circuit and means responsive to said detecting means for maintaining the second transmission circuit disabled, in the absence of signals required to be transmitted over the second transmission circuit, for a time needed to suppress all echo signals due to the incoming signals. General description, Fig. 1.-There is shown a transmission system interconnecting two telephone subscribers, party A and party B, in which each terminal unit includes a subscriber station, hybrid 3, 12; an analogue to digital coder 18, 5 and a transmitter or carrier terminal 6, 20 in the outgoing path; and a receiver or carrier terminal 7 followed by a digital to analogue decoder 9 in the incoming path. Not shown is a stationary orbit satellite via which the two terminal units communicate. At the terminal unit associated with subscriber A is shown the echo suppression device of the invention comprising units 8, 10, 15-17, 19 and 21. Such an echo suppressor may also be provided at the terminal unit associated with subscriber B. In operation, assuming subscriber B is speaking, the incoming digital speech codes are directed via a switch 8 to a peak level detector 10 which in accordance with the level represented by the signal received causes a threshold generator to be enabled for 50 ms to generate a digital code which represents a level 5 db below the initial level detected. A level comparator 17 is then used to compare this digital signal threshold level with digital signals emanating from the hybrid of subscriber A via the coder 18. Assuming subscriber A is not speaking, the only signals received will be echo signals and, as the 5 db reduction is chosen on the grounds that the echo signals are 6 db attenuated, the echo signal received will be below the threshold level and a hangover time generator 19 will inhibit the transmitter 20. If an incoming digital signal following the signal that caused the threshold level to be set represents a peak level greater thn the preceding signal, the threshold level is immediately updated. However if the following signals represent lower levels, the initial threshold level remains set for 50 ms after which it is set to a level corresponding to the greatest level received during the 50 ms period. The 50 ms period is chosen in accordance with the time a particular signal will take to travel from the switch 8 to the hybrid 12 and on, as echo, to the level comparator 17. If the subscriber A starts to speak he may break into the conversation i.e. switch on transmitter 20, by speaking at a level above 5 db below the subscriber B level. In addition once the level comparator 17 has indicated that the digital signals being received from hybrid 12 are above the threshold, a digital attenuator 21 may be switched into the other transmission path so as to cause a reduction in the threshold level. The subscriber A can then lower his voice to a certain extent without having the transmitter 20 cut off.  Detailed operation, Fig. 2 and Figs. 3-6 (not shown).-In the following it is assumed that each digital pulse signal is a seven bit binary word in which the first bit merely indicates whether the word is positive or negative. A received one of such signals is first fed to a peak level detector which comprises a shift register followed by a plurality of logic gates (Fig. 3, not shown). The six significant bits are fed into the shift register in serial form and are then read out to the inputs of a plurality of logic gates in parallel form. The arrangement of the gates determines a set of signal levels which are each separated by 2 db. An output corresponding to each signal level is fed to a respective one of a number of gate generators G1 to Gn and according to the level represented by the incoming digital signal a number of the gate generators corresponding to levels below the received level are enabled. Each such generator (Fig. 4, not shown) includes a four stage divide by 16 counter which is driven by dividing by 64 the frame clock output for the coder/decoder. The pulse received from the peak level detector is used to set the fourth stage of the counter to 0 and the first stage to 1. The fourth stage being set to 0 causes an output of 1 which is fed to the threshold generators. The output is also used to enable a gate by which the clock pulses are fed to the counter. The output then remains at 1 until a 1 occurs in the 4th stage, a count of 16 later. This causes an output 0 and stops the counter. This is arranged to take 48-60 ms. The 1 output is used to enable a corresponding threshold generator T1-Tn and to inhibit all the threshold generators corresponding to lower threshold levels. Each of the threshold generators may be an "AND" gate having one input from a clock providing pulses which are synchronized with one of the bit positions, one input from the corresponding gate generator, and inhibit inputs from gate generators corresponding to higher threshold levels. Hence a code, such as 1000100 or 1001000 &c., may be generated repeatedly for 48-60 ms unless a gate generator corresponding to a higher threshold level is enabled during this time, this action immediately causing the inhibition of the previous threshold generator and the enabling of the threshold generator corresponding to the new level. The codes generated by the threshold generators are each chosen to be about 5 db below the level which caused the generator to be enabled. The digital signal produced by the operative threshold generator is then fed to the level comparator together with the signals incoming from the hybrid 12. The level comparator (Fig. 5, not shown) comprises an AND gate, a NAND gate and a bi-stable circuit; the digit signals and their complements are fed to the circuit which is arranged in such a way that no output is obtained from the circuit if the incoming signal from hybrid 12 is below the threshold level. The digital attenuator 21 (Fig. 6, not shown) is used to attenuate a signal derived from hybrid B by 6 db when subscriber A is speaking at a level sufficient to turn the transmitter 20 on. It comprises four shift registers and one summing circuit. The incoming signals are divided into 8 segments, S000XYZ to S111XYZ each segment comprising 8 quantized levels. It is further assumed that the first two segments S000XYZ and S001XYZ are linearly compounded and the remaining segments are logarithmically compounded. The circuit therefore attenuates the signals in the first two segments by shifting the word one place to the right, e.g. S001010 becomes S000101 and those in the remaining segments are attenuated by adding the code S111000 (complement of 7) to the code and ignoring the carrying of the 1 to the sign bit; this is equivalent to subtracting the binary number 8, e.g. to attenuate code S111XYZ, 111000 is added to give (S+1)110- XYZ which on ignoring the carry 1 gives S110XYZ.