Patent GB-1140491-A (GB)
Title: Improvements in or relating to shift registers
IPC: G11C19/00
Filed: 1967-02-09
Abstract: 1,140,491. Digital shift registers. SIEMENS A.G. 9 Feb., 1967 [10 Feb., 1966], No. 6208/67. Heading G4C. A shift register (Fig. 4) comprises a series of NOR gates G1, G2, G3 &c. sequentially crossconnected between input and output (Fig. 2 not shown) in pairs, to form bi-stable trigger stages G1, G2; G2, G3; G3, G4 &c. and also to form bi-stable trigger stages in threes: G1, G2, G3; G3, G4, G5 &c. Inputs of the NOR gates G1, G2, G3, G4 &c. are connected sequentially to the pulse lines P1, P2, P3, P4 as are the inputs of gates G5 to G8, G9 to G12 &c. If the trigger stage of G4, G5, G6 is so set that logic 1 appears at the output of G5, gates G4, G6 are correspondingly blocked so that their content is zero. Logic 1 at the output of G5 and logic 0 at the output of G6 signifies binary logic 0 at G5, and logic 1 at G6 signifies binary zero, so that binary 1 is stored in G5, G6. The shift sequence is such that, at pulse time to, logic 1001 appear at the inputs of G4, G5, G6, G7; at time t 1  the inputs of G4, G5, G6 are maintained, while the input of G7 changes from 1 to 0; so that this gate is released and the bistable circuit originally of two gates G5, G6 is increased to comprise three NOR gates G5, G6, G7. At time t 2 , gate G5 is blocked by an input logic 1, so that G6, G7 form a bi-stable trigger stage while adjacent gates G5, G8 are blocked by input logic 1. At time t 3  the bistable trigger is extended by gate G8 in the shift direction, so that the stage comprises G6, G7, G8; G5 remaining blocked. At time t 4 , G6 is blocked so that the bistable trigger stage comprises only the NOR gates G7, G8. The information initially in G5, G6 is thus advanced at time t 4  to G7, G8, and further shifts are effected in similar manner, while further information, e.g. a binary zero stored in G1, G2, is correspondingly shifted. Shift direction is reversed by reversal of direction of progression of pulse pattern. In modifications, plural NOR (Fig. 3, not shown) gates may be used for each bit stored, while NAND gates may replace NOR gates, with logic 0 replacing logic 1 and vice versa. An alternative shift register (Fig. 5) comprises alternate OR gates (G1, G3, G5 &c.) sequentially cross-connected with AND gates (G2, G4, G6 &c.); the output of such being connected to the input of the other (Fig. 6, not shown). A binary zero is initially stored in G5, G6 at time t 0 , and at time t 1  the OR gate G7 is freed by input logic zero, so that the bistable trigger (previously G5, G6) is now OR gates G5, G7 plus AND gate G6, while AND gate G4 is blocked by input logic 0. At t 2 , OR gate G5 is blocked, so that the bi-stable trigger now comprises AND gate G6 plus OR gate G7. At t 3 , AND gate G8 is freed to extend the trigger stage, while at t 4  the latter remains freed while AND gate G6 is blocked, so that the trigger comprises OR gate G7 plus AND gate G8. After four pulses, the information to be shifted resides in the latter stage. Binary zero is denoted by logic 0 at the outputs of both trigger stages, and simultaneously with the binary zero shift, information stored in the trigger G1, G2 is transmitted in the same direction and is binary 1, since logic 1 appears at the output of G1, G2. The pulse pattern at to applied to gates G1 to G4 is 0110, at t 1  is 0100, and at t 2 , t 3  is 1001, 1011 by inversion of the bits of the first two stages at t 0  t 1 .