Patent GB-1523744-A (GB)
Title: Memory including a sense amplifier
IPC: H03K19/017
Filed: 1975-10-07
Abstract: 1523744 Transistor logic circuits INTEL CORP 7 Oct 1975 [3 Feb 1975] 53730/76 Divided out of 1523743 Heading H3T A programmable read-only memory disposed on a single silicon substrate and including a plurality of storage memory cells each of which has a floating gate for storing charge, further includes a sense amplifier coupled to the storage memory cells, the sense amplifier comprising a first branch including a first load means and a first transistor, the first transistor being coupled to the storage memory cells, a second branch coupled in parallel with the first branch, the second branch including a second load means and a second transistor, and a dummy memory cell for establishing a reference potential, the dummy memory cell including a floating gate and being coupled to the second transistor, whereby the reference potential provided by the dummy memory cell establishes a level for the sense amplifier. In order to avoid problems caused by the body effect of a more highly doped first region of the substrate which contains the plurality of storage memory cells and by the slow charging of the floating gates under certain conditions, the memory employs two separate grounds, an external ground (shown as 16 in the Figs.) and a substrate ground (shown as 18), the substrate ground being held at a potential of approximately -5 volts relative to the external ground. Some of the transistors of the peripheral circuitry have their thresholds raised by ion-implantation of their channels, this being indicated by shaded areas 15. Each bit of an address fed to the memory passes via a respective conventional address buffer to a respective address level shifter, Fig. 2 (not shown), which shifts the reference level of the address from the external ground 16 to the substrate ground 18, the output of the address level shifter feeding a respective push-pull address output buffer, Fig. 3 (not shown), which produces an output signal in true and complement form to a respective address decoder, Fig. 4, which is used to address the memory cells and also to permit a programming signal to pass to the memory cells. During programming data is fed to the memory cells via a conventional data buffer and a data level shifter respectively identical with the conventional address buffer and address level shifter. Data is read from the memory cells via a sense amplifier, Fig. 6, and via a data level shifter integral with the sense amplifier, the data level shifter shifting the reference level of the data from the substrate ground 18 to the external ground 16. Address level shifter, Fig. 2 (not shown),-When a positive signal is present on its input line (46), transistors (43, 45) heavily conduct and a transistor (44) only slightly conducts, clamping its output line (47) to substrate ground 18. Conversely when input line (46) is at the potential of external ground 16, transistors (43, 45) only slightly conduct and the gate of transistor (44) is bootstrapped by a circuit (38, 39, 40, 41), forcing transistor (44) to heavily conduct and causing output line (47) to be pulled towards a potential (V 1 ) of approximately 5 volts. Push-pull address output buffer, Fig. 3 (not shown).-When a high level signal is present on its input line (48), a transistor (53) conducts heavily and cuts off transistors (54, 55 and 60), the cutting off of transistor (54) causing a bootstrap circuit (51) to raise the potential on the gates of transistors (56 and 59) to more than a potential (V 2 ) of approximately 12 volts, an output line (57) thus being pulled towards potential (V 2 ) and an output line (67) being clamped to substrate ground 18. Conversely when input line (48) carries a low level signal a bootstrap circuit (50) is activated, pulling line (67) towards potential (V 2 ) and clamping line (57) to substrate ground 18. Address decoder and programming circuit, Fig. 4.-The output lines 57, 67 from the push-pull address output buffer are connected to respective series-connected and parallel-connected decoding transistors 64 etc.; 65, 66 &c. When the decoder is activated by an address its output line 72 is either coupled to the potential V, via a transistor 62 if line 57 is activated or is clamped to substrate ground 18 if line 67 is activated. During programming, bootstrap circuits (not shown) coupled to the gates of transistors 64, 65 allow the passage of a high voltage (25 volts) programming signal from an input line 27 to the output line 72 and thence to the memory cells, passage of the programming signal back to the push-pull address output buffer being prevented by transistors 63, 74 to avoid breakdown of the transistors 55, 56. Sense amplifier, Fig. 6.-This is a differential amplifier comprising two parallel branches each including a loading means 92, 94 and a transistor 93, 95. The amplifier, which has outputs 106, 107 taken from the two parallel branches, operates on differences in potentials of the gates of transistors 93, 95, the gate of transistor 93 being coupled to a column of the memory via a line 82 and to a potential V 3 of approximately -2 volts (for reading) via transistors 90, 91. The gate of transistor 95 is coupled by means of transistors 96, 97 between the potential V 3 and a dummy memory cell 110, whose floating gate is uncharged, the gate of transistor 95 thus being held at a predetermined reference potential. The dummy memory cell 110 may have the same dimensions as each of the storage memory cells and may be disposed in the more highly doped first region of the substrate. The memory cells are erasable by subjecting them to ultraviolet radiation. The disclosure is identical to that of the Specifications 1,523,743 and 1,523,745, which is also divided from the Specifications. These Specifications are referred to.