Patent GB-1249064-A (GB)
Title: A high speed modular data processing system
Inventor: FRESH WALTER CHARLES
IPC: G06F13/24
Filed: 1969-03-03
Abstract: 1,249,064. Data processing. BURROUGHS CORP. 3 March, 1969, No. 11320/69. Heading G4A. A modular data processing system comprises a plurality of input/output control modules connected to peripheral devices and a plurality of computing modules, the modules of each type being individually connected to each of a plurality of high speed memory modules, each input/output control module including a pair of identical input/output control units and a memory communication unit selectively connected to each of the pair to enable each of the pair to individually communicate with each of the memory modules on an alternate basis while the pair are simultaneously communicating with a pair of the peripheral devices. Main memory (core) modules can communicate via a central exchange with computer modules and I/O control modules and the latter can communicate via an I/O exchange with I/O devices. Each computer module utilizes instruction overlap and includes a local thin-film memory of 128 one-word registers (Figs. 13A, 13B, not shown, give register uses). Input - output details.-Each I/O control module includes two identical I/O control units which communicate with main memory via a common main memory interface unit including a one-word communications buffer and address registers, and communicate with peripherals for input via a common input device interface unit, and communicate with peripherals for output via a common output device interface unit. Each I/O control unit includes a one-word information register, a two-character buffer and a one-character output buffer arranged in series with each other (but transfer is parallel-by-bit) permitting operation overlap, and also includes a character counter and a descriptor register. A computer module initiates I/O by causing a main memory module to send a sequence of release, set-up, and command descriptors to an I/O control module which will eventually send a result descriptor back (Fig. 7, not shown, gives the descriptor formats). Transfer of instruction, control and status signals between I/O control module and peripheral is described in detail. Interrupt.-Error, I/O and other interrupts (Fig. 5, not shown) to a given computer module, with the exception of the two highest-priority types, set respective stages in an interrupt register to initiate a respective interrupt routine in a first control mode. An error interrupt occurring while this routine is being executed causes initiation of a respective interrupt routine in a second control mode. An error interrupt during this causes halting of the computer module. Completion of an interrupt routine in either control mode causes return to the original programme in the normal mode, using information saved in the thin-film memory, which also provided base addresses for first and second control mode tables in (different) main memory modules. Each table gives the starting addresses of the interrupt routines used in the respective control mode. Some stages of the interrupt register can be masked by respective groups of one or more bits in a mask register.