Patent GB-742660-A (GB)
Title: Process and arrangement for ciphering certain types of impulse signals
IPC: H04L9/22
Filed: 1953-02-02
Abstract: 742,660. Multiplex pulse code signalling; discharge tube gating circuits. SOC. FRANCAISE RADIO-ELECTRIQUE. Feb. 2, 1953 [Jan. 31, 1952; Feb. 28, 1952], No. 2959/53. Classes 40 (5) and 40(6). Relates to a system of ciphering a sequence of equidistant binary code signal pulses having an amplitude 0 or 1, where 0 and 1 represent any two constant amplitudes. For this purpose a key signal is generated comprising a repeated succession of similar pulses of the same recurrence frequency and phase as the signal pulses. Groups of the key pulses, for example comprising two pulses, together with the group of signal pulses occurring simultaneously, jointly produce a ciphered group for transmission according, for example, to the following " multiplication " table. though other arrangements may be used so long as at least two lines of the table are different and the same group does not appear more than once in the same line. The particular table given is based on a rule which is identical for ciphering and deciphering, the same key being used. A circuit for carrying out the ciphering or deciphering comprises the source 21, Fig. 3, of signal pulses which feeds four group identifiers 16 which respond, under the control of triggering pulses from a source 23, to the groups 00, 01, 10 and 11 respectively, to produce a single output pulse. Similarly the key pulse sequence repeatedly produced by the source 22, 7 (t), is fed to four further group identifiers 16, controlled by the source 23. Upon the occurrence of each triggering pulse from the latter, the appropriate one of the sixteen circuits 17 receives a pulse on its input lead 18 from a signal group identifier, and a pulse on its input lead 19 from a key group identifier and responds to the double input to produce a single output pulse on lead 20. The output leads 20 of circuits 17 are connected, in accordance with the ciphering table to one of four pulse group generators 7 connected in parallel to the output channel 24 and producing respectively pulse groups 00, 01, 10, 11. The key signal generator 7(t) may comprise a plurality of valves 1, Fig. 1, the anodes of which are connected to tappings on a delay line 3. When a control pulse is applied from line 5 simultaneously to their control grids, it is passed to the delay line tappings only through those valves whose grids are returned to earth through switch 2, the other valves being cut off by a negative voltage applied through the switch. The resulting pulses reach the output lead 6 spaced out in time by the delay line. With the switches set as shown, the pulses produced are 1, 0, 1, 1, 0. A pulse group identifier circuit, arranged to produce a single output pulse when fed with the four-pulse group 0011, comprises a delay line 9, Fig. 2, to the tappings 16 ... 19 of which are connected the control grids of valves 11 which are normally cut off. The anodes of valves 11 are connected through shunted diodes 13 to the common output lead 15 with the inter. position of phase-inverter stages 14 where the valve 11 is associated with a 0-pulse. When the correct pulse group is displayed at the tappings 16 ... 19, after entering the line 9 at input lead 8, a suitably timed control pulse applied from lead 12 to unblock the valves 11 at their screen or suppressor grids will produce the condition that none of the anodes of the diodes 13 remains at the high-tension positive potential so that a corresponding negative pulse appears on the output lead 15. For any other pulse group at least one of the diode anodes remains at high tension positive potential and no output pulse is formed. The circuit may be adapted to identify pulse groups of any number of pulses. The code may be periodically changed by automatic means controlled by special triggering impulses or by clocks. If the " groups " of key and signal pulses each comprise one pulse only and the ciphering comprises the " multiplications" 0x0=0, 0x1=1 and 1 x 1=0, these may be performed by applying the negative key and signal pulses to valves 36, 37, Fig. 5. Their parallelled output is fed through valve 39 and rectifier 41 to the output line 32. If the two inputs are zero the output is zero, but if one of the inputs is a " 1 " pulse, the resultant negative pulse produced at the anode of valve 39 is passed by the rectifier 41. If both the inputs are " 1 " pulses, the double amplitude pulse in the common output of valves 36, 37 is able to overcome the bias on a further valve 38 which feeds a negative pulse to a valve 40, the positive output of which is added to the output of valve 39 and is of such amplitude that the resultant pulse is positive. This pulse cannot pass the rectifier 41 so that the output on line 32 is zero. Specification 714,908 is referred to.