Patent GB-1138151-A (GB)
Title: Improvements in or relating to digital instruments
Inventor: CATHERALL REGINALD
IPC: H03M1/00
Filed: 1965-01-04
Abstract: 1,138,151. Digital control apparatus, electric analogue calculating. SOLARTRON ELECTRONIC GROUP Ltd. 4 Jan., 1966 [4 Jan., 1965], No. 307/65. Headings G4A, G4G and G4H. [Also in Divisions G1, H2 and H3] Digital control apparatus, including a clock pulse source, feeding, through switching mechanism, clock pulses to a counter connected to a digital display, is adapted to receive different plug-in units. The clock pulse source MV1 (Fig. 1E), is controlled by four switches S2, S3, S4, S1 (Figs. 1C, 1E), to provide clock pulses at 50c/s, 10c/s, 2c/s, or any of these pulse rates divided by ten respectively. The counter comprises a range decade RD (Fig. 1B), four least significant figure decades D1-D4 and a most significant figure unit BD1 (Figs. 1A, 1B). The decade to which the clock pulses are fed is controlled by switches SRD, SD1, SD2, SD3, SD4, (Figs. 1D, 1F), controlling bi-stable devices B1, B2, B3 to enable one of the AND gates (A14, A15, A16, A17, A18). The binary coded decimal count in the counter is converted into decimal code in decoders DC1, DC2, DC3, DC4 DRD (Figs. 1A, 1B), the outputs from the decoders controlling logic means so that certain limit conditions are detected e.g. all the counters are zeroized or a count of 10,000 is stored. The apparatus may be used for measuring frequency by converting the frequency to a voltage by means of frequency discriminators and comparing the unknown voltage with a voltage representing the count in the counter in a differential comparator which emits an output pulse of -6 volts when the count in the counter is too low and a pulse of zero volts when the count is too high. These pulses control a bi-stable device which controls the direction of count in the counter and feeds clock pulses initially to the range decade (RD) until the balance line is crossed. Under the control of bi-stable devices B1, B2, B3 the clock pulses are then directed to the next most significant decade, this process being repeated until the decades RD, Dl, D2, D3 are balanced and the decade D4 is as near a balance as possible. The apparatus may also be used for measuring resistance, the binary coded decimal output from four decades of the counter being used to control switch contacts and weighted reresistances. The voltage from the reistances which varies as clock pulses are fed into the counter is compared with the voltage from an unknown resistance until a balance is obtained. The apparatus may be used for generating sine and cosine waveforms by using the count in the counter to control resistances in a variable frequency integrator (VF1, Figs. 9 and 11, not shown), to which are connected alternating sources of positive and negative potential to give a sawtooth output waveform. A level detector detecting the upper and lower limits of the sawtooth waveform controls switching means (SW11) controlling the supply of positive and negative voltages to the resistances. The sawtooth output is applied to shaping means and an inverter to generate a sine wave, the frequency of which is dependent on the count in the counters. It is also back biased by a voltage of -15 volts to give a wholly negative sawtooth which is applied to shaping means and an inverter to generate a cosine wave. The sine and cosine waves are fed to potentiometers and then added to give an output waveform Y = a cos # + b sine #. The counters D1, D2, D3, D4 (Figs. 1A, 1B), may be used to count logarithmically by connecting the output leads from the 2, 4 and 8 stages of the first decade D1 to a binary counter represented by bi-stable devices B7, B8, B9 (Figs. 1C, 1E) which enable an AND gate A30 to pass one pulse from a second pulse generator MV2 for each pulse from the first pulse generator to the counter whenever the count exceeds 2000, to pass three pulses whenever the count exceeds 4000 and to pass seven pulses when the count exceeds 8000. In this way the count in the counter increases logarithmically for a steady supply of pulses from the pulse generator MV1. A crystal delay plug-in unit which enables an output pulse to be generated in response to an applied pulse after a time delay determined by the setting of the decade units in the counter includes an AND gate (A101, Fig. 4, not shown), which generates an output pulse when a count of 11111 is reached in the counters, the counters being previously set to the complement of the number representing the required time delay. The frequency of an oscillator in the form of a Wien-Bridge oscillator (Fig. 3, not shown) is controlled by the count in the counter, outputs from the decades of the counter controlling contacts to connect resistors and capacitors into the circuitry.