Patent GB-1525634-A (GB)
Title: Television cameras
IPC: H04N9/04
Filed: 1975-08-22
Abstract: 1525634 Solid state colour television camera GENERAL CORP 22 Aug 1975 [5 Sept 1974 (5) 13 Sept 1974 16 Oct 1974] 34909/75 Heading H4F Colour television camera comprises a solid state image sensor X-Y array of photosensitive elements e.g. a CCD array, with the elements arranged to be sensitive to different colour components by applying coloured paints to the elements or locating colour filters in front of the elements e.g. dot filters or vertical or horizontal strip filters. The camera may comprise columns of photoelements arranged alternately with vertical analog shift registers which in turn are connected to a horizontal output analog shift register (Fig. 1a, not shown), or an array of photoelements the charge from which is transferred to a like storage array of elements and then line sequentially into a horizontal output register (Fig. 1b, not shown). In the following Figures the vertical shift registers of Fig. 1a or the storage array of Fig. 1b have been omitted. In Fig. 3 (not shown) the array is provided with dot (elements) filters in the horizontal sequence RGB i.e. effectively vertical stripe filters, so that a dot sequential colour signal is generated. In Fig. 4 (not shown) the dot filters effectively comprise horizontal strip filters in the sequence RBGRBG, a lineinterlaced line-sequential signal RGBRGB being generated by replacing each vertical shift register of the Fig. 1a camera by two vertical shift registers. An interlaced effect may be given to a non- interlaced line sequential signal by averaging the line sequential signals on two adjacent lines of the same colour (involving a three line period delay) during alternate fields only, Fig. 7 (not shown), the resulting signal and one and two line period delayed signals being converted into simultaneous R, G and B signals. Two colour line sequential interlaced and non-interlaced signals may be generated, Figs. 8 and 9 (not shown) and to improve a resulting displayed image quality either of these signals may be converted into two simultaneous signals 41-43, Fig. 10, in which each line signal is repeated, and then fed directly and via a one line delay 44(45) to an adder 46(47) so that the R signal comprises R1, (R1+R2)/2, R2, (R2+R3)/2, ... and similarly the B signal. If the input signal at 40 is not line interlaced then an interlaced effect may be added to the output signals of Fig. 10 by passing each of them to a circuit shown in Fig. 11 which includes a one-line delay 50, adder 51 and a field frequency switching circuit 53 so that the input signal is outputted during odd fields but during even fields the signal (3R1+R2)/4, (R1+3R2)/4, (3R2+R3)/4, ... is produced. The arrangement of Figs. 10 and 11 may be applied to a dot sequential signal, and the arrangement of Fig. 11 to the brightness signal e.g. from a second solid state camera. Fig. 12 shows a two colour dot sequential type camera having separate horizontal output shift registers 22 and 24 for each colour so that the R and B signals are obtained simultaneously, this being in accordance with the invention claimed. Fig. 13 shows how a pair of line sequential signals using two sets of clock pulses is obtained wherein information from the first two rows of photoelements (R and B rows) are simultaneously obtained and correspond to the first scan line L1; the fifth and sixth rows corresponding to the second scan line L2, with the remaining rows corresponding to the interlaced scan lines L264, L265. Alternatively, Fig. 14 (not shown), the same row pairs may be used for the odd and even fields, and instead of only R and B rows the camera may have R, G and B rows, Fig. 15 (not shown), the simultaneous line sequential output signals R, B, G ... and G, R, B being converted into three simultaneous signals by means of a line frequency gate circuit and a one line period delay, Fig. 16 (not shown). Using the same arrangement as Fig. 15 improved interlaced scanning is achieved by grouping the rows which are simultaneously read-out as shown in Fig. 17, the resulting signals being convertible into a simultaneous signal, Fig. 18 (not shown). In a further embodiment, Fig. 19, the even rows are alternately R and B sensitive while the odd rows are G sensitive. Arrangements with three sets of clock pulses are described with reference to Figs. 20-23 (not shown) with the same or different combinations of rows being simultaneously read, and an arrangement with four sets of clock pulses is described with reference to Figs. 24 and 25 (not shown).