Patent GB-1207710-A (GB)
Title: Improvements in devices for transferring information between a central unit and peripheral elements
IPC: G06F13/12
Filed: 1968-11-05
Abstract: 1,207,710. Digital electric data processor. SOC. INDUSTRIELLE BULL - GENERAL ELECTRIC. 5 Nov., 1968 [16 Nov., 1967; 24 Jan., 1968], No. 52452/68. Headings G4A and G4C. A stored programme data processor has a plurality of peripheral units provided with a connecting system containing an instruction decoding register receiving a transfer instruction from the processor, an order memory containing data, called code orders, specifying the direction of data transfer and a local control unit arranged to select a code order, under the control of the transfer instruction, to correspond to the direction of transfer specified in the transfer instruction and to transmit the code order to the processor to cause the processor to co-operate with the local control unit to control the transfer of data in the required direction.  The central unit has an instruction memory 10 coupled to an address register 14 and readout storage register 16 both controlled by pulses from central control unit 13. If an accessed instruction relates to peripheral units OT1-4, which may be magnetic tapes or discs, punched tape or printer the instruction is fed to one of the standby registers RI1-4 prior to transfer to the peripheral unit, each register being associated with a particular peripheral unit. Each peripheral instruction has a section indicating which peripheral unit is being addressed, the section being decoded by decoder-writer 16 to cause an instruction distributer 15 to supply the instruction to the appropriate register RI1-4. If -no peripheral unit is addressed decoder 16 receives an all zero section of the instruction word and causes the word to be supplied to register RITB in which it is decoded to provide a branch instruction. Data passing to the peripheral units is held in an output register EVDQ and data coming from the peripheral units is received in an input register RVCQ the data being transferred over lines VDQ and VCQ connected to all the peripheral units. The transferred instruction is received by the peripheral unit in a register RVDQ1-4 and passed to an instruction register RD1-4 to be decoded. Each peripheral instruction comprises a fixed number of characters, as described five characters, the first of which T.O. or type of operation defines the operation to be performed, i.e. printing, reading or writing and determines the direction in which transfer occurs. Each peripheral unit has an order memory containing seven code orders each consisting of a single character to specify to the control unit the direction of data transfer, the character being accessed depending on the TO character. Each code order is transmitted via output register EVCQ 1-4, input register RVCQ1-4 and gate 21 to a decoding register RCO forming part of the central control unit 13. This is decoded to enable switching to take place to allow transfer of data in the required direction. The central unit then sends back a signal indicating the availability of the central unit, this signal being a code response held in a permanent data register RPU to cause decoding to occur in the peripheral unit to trigger a character tra sfer which is either the required data or a state of apparatus character generated by the peripheral unit to indicate the end of the transfer operation. The central unit and peripheral units are further connected by a series of order conductors OR1-4 and a series of transfer control conductors XREP1-4 to maintain co-ordination between the respective units. When the code response is stored in register RVDQ1-4 the appropriate order conductor carries a signal calling for transfer of a character, in response to which the appropriate transfer control conductor XREP1-4 carries a control pulse triggering the transfer of a character. Data sent or received by the central unit is held in a memory 17 and passes through input/output register RES under the control of gates EM, SM enabled by the central control unit 13. The central unit can control the peripheral units on a time division multiplex arrangement. If time division multiplex is used only one magnetic tape unit at a time can be used so a single input and a single output register are used for all the tape units and the instruction includes a character indicating which tape unit is to be used. The instructions also have a character controlling tape drive to position the tape to access the address required for reading or writing operations. A T.O.C. character defines the number of data blocks that must be driven past the write or read head before the required address is reached. The instruction also indicates how many blocks of data are to be transferred the number being decreased by 1 at each transfer. Each block of data carries an end of block character read by a special detecting device when the tape is driven to send a counting pulse to a block counting register. If the tape is travelling in a forward direction the counter indicates the number of the block passing under or about to pass under the reading head 4. If the tape is travelling in the reverse direction the pulse is not sent to the counter until the block has passed the writing or reading heads and so the counter indicates the value of the block which has last passed under the heads. Thus if the tape is stopped immediately the count changes value under the control of a comparison device the new value represents the number of the block about to pass under the heads travelling in the forward direction. Each tape unit can be isolated after an end of incident operation code order has been transmitted by the operator passing an OF button and returned to operation by pressing an ON button.