Patent GB-757839-A (GB)
Title: Time separation switching systems
IPC: H04Q11/04
Filed: 1954-06-25
Abstract: 757,839. Automatic exchange systems. WESTERN ELECTRIC CO., Inc. June 25, 1954 [June 26, 1953], No. 18677/54. Class 40 (4). In a time-division multiplex system for connecting a number of local subscribers' lines to a number of junctions leading to other exchanges, each junction is assigned to a particular time position in a repeated cycle and its connection to a particular line is achieved as a result of the insertion of a signal identifying the line into the time position corresponding to the junction in a circulating memory means which includes a delay line. As shown, connections between six subscribers' lines 20 and seven junctions 27 leading to remote exchanges are established over a common speech path 22. Each junction 27 is allocated a particular section, referred to as a " time slot," of the operative cycle of the apparatus. A synchronizing circuit 34 produces synchronizing pulses at a frequency of 160 kc/s. and these actuate a junction sequence circuit 55 comprising a scale-of-ten counter, which may be of the type described in Specification 729,172, [Group XIX], containing four binary pairs. Each step of the counter marks one time slot, and ten steps constitute an exchange cycle. The sequence circuit 55 presents various combinations of potentials in successive time slots to the inputs of a junction translator 53. This comprises a number of AND diode networks and applies a positive potential to its outputs in turn in response to corresponding inputs, thereby enabling junction gates 28 in sequence. Similarly, line gates 21 are enabled by a line translator 52 in response to signals from a circulating memory circuit 56 which includes a fused silica acoustic delay line, the total delay in the memory circuit being equal to one exchange cycle. Each subscriber's line 20 is represented by a code of three binary digits which may circulate simultaneously in the memory, each in a separate channel of distinct frequency. The code pulses in the memory are regenerated at each cycle under the control of the synchronizing pulses. To establish a connection between a particular subscriber's line and a particular junction, the code of the line is inserted into the memory in the time slot of the junction, so that their respective gates are enabled simultaneously. Call from subscriber at remote exchange. A calling condition on a junction 27 causes a pulse shaper 105 to produce a positive output pulse in the corresponding time slot. This enables a junction scan network 106, unless the latter is disabled by pulses from a blanking repeater 109 (indicating that the control circuits have been seized by a prior call) or from a memory indicator 108 which becomes operative under the control of the memory 56 through an OR network 110 in the time slot of any junction engaged in a call. A junction scan repeater 112 repeats a pulse 113 from the scan network 106 to an exchange cycle delay circuit 114-117 and also to a dial pulse detector circuit 120 which triggers an enabler circuit 121 to open the gate 116 in the delay circuit, the enabler 121 being held by a hold circuit 124. Pulser 114 marks the time slot of the calling junction, and pulsers 115 and 117 cause the blanking repeater 109 to disable the junction scan network 106 and repeater 112 during all other time slots. Repeater 112 also actuates a dial tone control circuit 131 which controls a dial tone gate 133 so that the calling exchange receives tone from a source 134. The reception of the first dialled impulse restores the hold circuit 124, but the enabler 121 is sufficiently slow-releasing to hold during the dialling. The dialled number is stored in binary form in a register 140 and is applied to a code gate 142 which is held disabled by the enabler 121 through an insert network 143 consisting of an AND gate. Enabler 121 finally restores, closing gate 116, and the next (and final) pulse from pulser 114 causes the insert network 143 to enable the code gate 142. Register 140 applies the called line code also to a line code comparator circuit 148 which compares it with the codes of busy lines circulating in the memory 56. If a match is found, showing that the wanted line is busy, comparator 148 enables a line busy detector sircuit 151 which causes code gate 142 to insert, by means of an insert repeater 158, a special code into the time slot of the calling junction in the memory 56. The line translator 52 thereupon applies a positive potential to a lead 152, enabling a busy tone gate 154. If, however, the wanted line is idle, the comparator 148 remains inactive and the code of the wanted line, stored in register 140, is inserted by means of code gate 142 and insert repeater 158 into the time slot of the calling junction in the memory 56, so that the line translator 52 enables the gate 21 of the wanted line in this time slot, ringing current being simultaneously applied by means not shown. Meanwhile the restoration of enabler 121 has tripped a lock-out circuit 160 which enables the insert repeater 158, disables the junction scan network 106 by means of the blanking repeater 109, and then releases after at least one exchange cycle to disable the insert repeater 158 and reset the register 140 to zero. Call from local subscriber. The ninth time slot is not assigned to a junction but is used for scanning the common path 22 for signals from calling lines. Each line code in turn is inserted into the ninth time slot in the memory 56 so that the lines 20 are scanned at the rate of one per exchange cycle. The junction translator 53 applies its ninth time slot pulse TS9 to a scan gate 163, which responds to the trailing edge of the pulse and advances a scan register 164 by one step. During the following nine time slots a scan comparator 166 compares the code stored in register 164 with the codes of busy lines circulating in the memory 56. If a match is found, scan comparator 166 pulses to lock up a scan busy detector 176 and disable a line call code gate 168, thereby preventing the insertion of the stored code into the memory 56. At the next ninth time slot the response of scan gate 163 restores the detector 176 and scanning continues. If, -however, no match is found, this means that the corresponding line is not busy and may be calling. The next ninth time slot pulse TS9 passes through an insert switch 167 to enable the line call code gate 168 which inserts the code from register 164 into the insert repeater 158 and thence into the ninth time slot of the memory 56, so that the gate 21 of the line corresponding to the inserted code is enabled in the ninth time slot. Pulse TS9 also enables a line scan network 171 to pass any pulse from shaper 105. If no pulse is received, the line is not calling and the scan gate 163 advances the scan register 164 to the next line code. The inserted code is erased from the ninth time slot of the memory 56 after one cycle by the arrival of the delayed eighth time slot pulse TS8 from the junction translator 53 via a delay circuit 175. If, however, the line is calling, the resultant pulse from shaper 105 is passed by the line scan network 171 to a line scan repeater 180 which trips an enabler 181 through a line dial pulse detector 183. The enabler 181 disables the scan gate 163 so that the scan register 164 inserts the same stored code into the memory 56 in the ninth time slot of each cycle, thus seizing the calling line. The repeater 180 also actuates the dial tone control circuit 131. The first dial impulse releases the hold circuit 182 to initiate the slow release of enabler 181. The line dial pulse detector 183 delivers the dialled number to a line call register 185 which stores it in binary form. A junction code comparator 188 compares the stored code with the outputs of the junction sequence circuit 55. A match occurs in the time slot of the wanted junction and causes the comparator 188 to emit an identifying pulse 189. If the wanted junction is idle, the pulse 189 passes through a junction busy switch 192 to the insert switch 167. When the enabler 181 restores, the conduction state of the insert switch 167 is reversed so that it sends the pulse 189 to the line call code gate 168, causing the code of the calling line which has been stored in the scan register 164 to be inserted into the memory 56 in the time slot of the wanted junction. The insert switch 167 restores itself after a delay of at least one exchange cycle, removes a disabling condition from the scan gate 163, and resets the line call register 185 to zero, so that scanning for calling lines is resumed. If, however, the wanted junction is busy, the OR circuit 110 sends a pulse 196 in the associated time slot to a busy comparator circuit 197 which causes the junction busy switch 192 to block the junction identifying pulse 189 but pass the tenth time slot pulse TS10 from the junction translator 53 to the insert switch 167. When the enabler 181 restores, the code of the calling line is inserted into the tenth time slot of the memory 56. The busy tone gate 154 also is enabled in the tenth time slot, so that the caller receives busy tone. Erasure of codes from memory. An erase scan network 203 passes delayed synchronizing pulses from a delay circuit 202 only in a time slot in which a code appears in the memory but there is no pulse from the common path 22 via shaper 105, indicating either the breaking of the connection or a momentary interruption of pulses. If this condition persists for a predetermined length of time, a pulser 209 erases the relevant code from the memory 56.