baber/WOPTO huggingface dataset:
Patent JP-S61276429-A (JP)
Title: Multiplex system for cmi code
Inventor: KIYOTA SHINJI
IPC: H04L25/49
Filed: 1985-05-31
Abstract: PURPOSE:To suppress the number of consecutive 1s or 0s to four or below by forming exclusive OR to multiplexed signals at 2-bit each of CMI codes synchronized in plural channels while using a repetitive signal of 1100 of 1-bit delay. CONSTITUTION:An input converting an original signal 1-bit into 2-bit CMI code is given to input terminals 11-13 of a multiplex circuit 2, a CMI code 00 11 01 00... is given to a terminal 11, a CMI code 10 11 00... is given to a terminal 12 and a CMI code 00 11 00... is given to a terminal 13. The signals are multiplexed at 2-bit each and inputted to an input section 21 of a coding circuit 3 in the form of 00 10 00 11 11 11 01 00 00 00.... On the other hand, a scrambler circuit 4 gives a signal of 1 10 01 10 01 10... delayed by 1-bit from the multiplexed CMI code of the circuit 3, which forms exclusive OR of them and outputs an output signal 1 00 01 01 10 01 00 10 01 10... from an output section 31.
Patent JP-S5910007-A (JP)
Title: Amplification circuit of field effect transistor
Inventor: KIKUCHI KENICHI
IPC: H03F3/34
Filed: 1982-07-07
Abstract: PURPOSE:To obtain an EFT amplification circuit incorporating a simple and highly accurate bias setting function, by connecting a bias setting field effect transistor FET in series to a bias power supply and setting the voltage of the bias power supply within a range where the FET is actuated in a saturated region. CONSTITUTION:As FETs Q1 and Q2 are connected in series, the DC drain current IdO is always equal between the FETs Q1 and Q2. Furthermore the gate- source voltage of the FETQ2 is always set at O. The bias power supply voltage VB is set within a range where the FETQ2 is actuated in a saturated region, and therefore the current IdO is equal to the saturated current of the FETQ2. While the gate-source voltage is set automatically for the FETQ1 so that the drain current of the FETQ1 is equal to the current IdO. Then W2/L2=beta(W1/L1) is satisfied, where W1 and W2 and L1 and L2 show the gate width and the gate length of the FETs Q1 and Q2 respectively with the bias current set beta times as high as the saturated current. As a result, the bias can be set accurately and easily regardless of the variance of the production conditions of an FET, the bias resistance Rg, etc.
Patent JP-S5544733-A (JP)
Title: Diode
Inventor: NAKAGAWA AKIO
IPC: H01L29/41
Filed: 1978-09-27
Abstract: PURPOSE: To obtain low voltage drop in the forward direction, high, reverse resisting pressure and low leakage currents, by lessening built-in potential by lowering the concentration of the impurities of a p-type layer by manufacturing an electrode at the p-side so that Schottky junction be formed.  
     CONSTITUTION: The concentration of the impurities of a p-type layer is let down by producing an electrode at the p-side, which is extracted as one side electrode of a diode, in order that Schottky junction be made up, and built-in potential ϕB is reduced. When the concentration of the impurities is brought to proper value, high resisting voltage is acquired because reverse leakage currents are not enlarged. Thus, low voltage drop in the forward direction, high, reverse resisting voltage and low, reverse leakage currents can be secured. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-H0416279-A (JP)
Title: Production of pure water
Inventor: HASHIMOTO NOBUKO
IPC: C02F1/44
Filed: 1990-05-08
Abstract: PURPOSE:To increase the specific resistance of pure water by injecting an alkali solution to the raw water supplied to the reverse osmosis membrane of a front stage to adjust the pH of the raw water at 8.6+ or -0.2. CONSTITUTION:Raw water 10 is passed through an activated carbon tower 12 and adjusted to pH at 8.6+ or -0.2 in a pH control tank 14. In this case, the injection amount of an alkali solution 16 is automatically controlled on the basis of the indicated value of the pH meter arranged in a pH control tank 12. The raw water whose pH is adjusted at 8.6+ or -0.2 is passed through the reverse osmosis membrane 18 of a front stage and the reverse osmosis membrane 20 of a rear stage, and the pure water as the transmitted water from the membranes is sent to the ultrapure water making apparatus 22 of the next stage. As the material quality of the reverse osmosis membranes 18, 20, a polyamide composite membrane is pref. because it is excellent in durability within a pH range and one having a high cation degree is selected as the reverse osmosis membrane 18 of the front stage and one having a high anion degree is selected as the reverse osmosis membrane 20 of the rear stage. By this method, the specific resistance of pure water can be increased.
Patent JP-S597982-A (JP)
Title: Picture display device
Inventor: TAMURA YASUYUKI
IPC: G03G15/22
Filed: 1982-07-07
Abstract: PURPOSE:To feed a picture before erasure to a display part again backward and to display it again by setting the picture formation area of an endless belt image carrier to more than twice as long as a display visible area. CONSTITUTION:A toner image is sent to the display part 15 and viewed there through glass 16 from the outside. When the display of the 1st toner image at the display part 15 is completed, a photoreceptor 11 is moved as shown by an arrow, so that while the toner image after the display disappears, a next toner image appears at the display part. The endless belt photoreceptor 11 is more than twice as long as the visible area of the display part, so the 1st toner moves to the part guided by guide rolls 17-19 to hold the image as it is. For this purpose, the photoreceptor 11 is only rotated reversely to display the 1st toner image displayed last time on the display part 15, and the moving speed of the photoreceptor 11 is set optionally.
Patent JP-H07325125-A (JP)
Title: Method and equipment for testing semiconductor
Inventor: SATO MASATOSHI
IPC: G01R31/28
Filed: 1994-05-31
Abstract: PURPOSE:To realize simultaneous test of circuit parts operating at different clock frequencies in a semiconductor device by providing a pattern generator having an expected value pattern memory for storing a dummy pattern every predetermined test cycle. CONSTITUTION:A pattern generator 100 having an expected value pattern memory 1012 stores a dummy pattern every predetermined test cycle. A test data printing section Pinn prints a test data in a semiconductor device DUT to be tested. A test result inputting/comparing section Pin(n+1) compares test results read out from the DUT logically with an expected value data and outputs an open processing data in response to the dummy pattern thus stopping the logical comparison operation. When a clock pulse having a common clock frequency is fed to a semiconductor device where circuit parts operating at different clock frequencies are mixed, the circuit parts can be tested simultaneously.
Patent JP-S61276091-A (JP)
Inventor: WATANABE YOSHIHIRO
IPC: G07D9/00
Filed: 1985-05-31
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63282858-A (JP)
Title: System for preventing program runaway
Inventor: SAITO SEIICHI
IPC: G06F11/30
Filed: 1987-05-15
Abstract: PURPOSE:To prevent a microprogram from generating runaway by interrupting a microprocessor at a fixed period, reading out the state of a processing flag from processing flag register to detect whether respective processing is successively executed or not, and executing prescribed abnormality processing when the processing is not successively executed. CONSTITUTION:A processing flag is inverted every end of each processing out of processing #1, #2 and the processing flags '1', '0' are alternately changed at the time of executing the microprogram. The processing flag can be decided by checking that the contents of a register 5 storing the processing flag is alternately changed to '1' and '0' every external periodical interruption, i.e. every time when the output of a counter 2 is inputted to an INT terminal of the microprocessor 1 as an interruption. Consequently, highly reliable runaway prevention can be attained.
Patent JP-2000305512-A (JP)
Title: Image display device
Inventor: TANABE HIDEO
IPC: H01J11/34
Filed: 1999-04-26
Abstract: PROBLEM TO BE SOLVED: To provide an image display device using a display discharge tube capable of high luminance display and high definition display which are selectable according to applications without a complicated constitution by provid ing a controller with a display mode switching circuit to perform switching between a high luminance display mode and a high resolution display mode. SOLUTION: In an image display device, a controller 24 controls a display voltage and first and second address voltages to each of a display electrode driver 21 and a first address electrode driver 22 as well as second address electrode drivers 23a, 23b. The controller 24 is provided with a display mode switching circuit 25. The circuit 25 has a function to perform switching between a high luminance display mode to implement main electric discharge for the display between a pair of display electrodes 5M1, 5M2 and a high resolution display mode to implement main electric discharge for the display between one of the electrodes 5M1, 5M2 and a first address electrode 6.
Patent JP-S5242353-A (JP)
Title: Timing control circuit by delay element
Inventor: YATSUSE OSAMI
IPC: H03K5/15
Filed: 1975-09-30
Abstract: PURPOSE: To make start stop control by external signal for the development of pulse train having arbitrary pulse width and phase without the loss due to queuing time, by combinating delay element and control register. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-H06332589-A (JP)
Title: Semiconductor integrated circuit
Inventor: OGAWA HIROAKI
IPC: H03K19/0175
Filed: 1993-05-20
Abstract: PURPOSE:To reduce the power consumption while keeping the operation speed of a function block requiring the high-speed operation. CONSTITUTION:A C-MOS semiconductor integrated circuit 1 produces the voltage applied to an input terminal 2 by an oscillation circuit 3 and a clock signal by a clock generation device 4. A voltage lowering circuit 5 reduces the voltage applied to the input terminal 2 to a prescribed voltage. The clock generation device 4 convertes the voltage level of a clock signal into the voltage level reduced by the voltage lowering circuit 5 with an output voltage conversion circuit 11 and sends it to a system clock wiring. Function blocks 6-1 to 6-n convert the voltage level of the signal taken in from the system clock wiring by the voltage conversion circuit 10 from the voltage level reduced by the circuit 5 to the voltage level applied to the input terminal 2 and perform the data processing or the like. The voltage level of the signal sent to the databus wiring is converted into the reduced voltage level and the voltage level of the signal taken in from the databus wiring is converted into the voltage level applied to the input terminal 2.
Patent JP-H06330238-A (JP)
Title: Cold rolled steel sheet for working excellent in baking hardenability and weather resistance
Inventor: HAYASHIDA TERUKI
IPC: C22C38/16
Filed: 1993-05-20
Abstract: PURPOSE:To produce a cold rolled steel sheet having extremely good workability, baking hardenability and good weather resistance. CONSTITUTION:This steel sheet has a compsn. contg., by weight, 0.010 to 0.038% C, <=0.04% Si, 0.05 to 0.25% Mn, 0.010 to 0.120% P, 0.002 to 0.020% S, 0.05 to 0.50% Cu, 0.010 to 0.10% Al and <=0.0060% N, and the balance Fe with inevitable impurities, has a particle-regulated structure in which the average particle size 15 regulated to 10 to 45mum and is incorporated with solid solution carbon in the range of 2.5 to 8.0ppm. In this way, the cold rolled steel sheet for working excellent in baking hardenability of >=4kgf/mm<2> and weather resistance can be produced.
Patent JP-H05313008-A (JP)
Title: Color resist and manufacture of color filter using the color resist
Inventor: NOMURA SHIGERU
IPC: G02B5/20
Filed: 1992-05-12
Abstract: PURPOSE:To provide color resist and a color filter manufacturing method using this color resist enabling the formation of a color filter layer uniform in film thickness, light transmittance and color in a mass production process without the risk of causing danger in handling and environmental pollution. CONSTITUTION:This color resist includes a coloring solution composed mainly of water, a surface active agent, a pigment and dispersant; a water soluble high polymer displaying sol-gel transition according to the temperature; and light hardening resin or a heat cross-linking agent. This color resist 3 is applied uniformly onto a glass base 1 on which an ITO film 2 heated by current application is provided in the pattern state. A current is applied to gelatinize the color resist in the part corresponding to the ITO film 2, and after removing the ungelatinized color resist by dissolving it with a water developer, a residual color resist coat 30 is photo-cured or heat-cured to form a color filter layer 4.
Patent JP-H11311511-A (JP)
Title: Ultraprecision rotating device
Inventor: FUJII TORU
IPC: G01B11/30
Filed: 1998-04-28
Abstract: PROBLEM TO BE SOLVED: To obtain an ultraprecision rotating device whose rotational accuracy can be enhanced, by a method wherein an electromagnet is controlled while a member for center detection is being observed by scanning probe microscopes which are arranged on both sides of a rotor, and a position which becomes the central axis of the rotor is adjusted fine. SOLUTION: A rotor 1 is supported freely rotatable around the central axis L in a levitated state by first electromagnets 2, and it is turned around the central axis L. Then, while crystal lattices 6a of members 6 for center detection are being observed by probes 7a of scanning probe microscopes 7 arranged on both sides of the rotor 1, the electromagnets 2 are controlled, and a position as the central axis L of the rotor 1 in the members 6 for center detection is adjusted fine so as to be situated in the center of the rotation of the rotor 1. Then, when the rotor 1 is turned, the position of the rotor 1 is controlled by the electromagnets 2 in such a way that the center crystal lattices are not turned in an arc but situated always in one point. As a result, the central axis L of the rotor 1 can be situated with high accuracy in the center of rotation of the rotor 1.
Patent JP-H10308143-A (JP)
Title: Main circuit disconnector
Inventor: HORIKIRI KAZUHITO
IPC: H02B13/02
Filed: 1997-05-09
Abstract: PROBLEM TO BE SOLVED: To provide a main circuit disconnector capable of keeping the voltage proof characteristic without increasing the space occupied by the insulation. SOLUTION: A shaft part 3a of a movable shield 3 is pierced in the center of a contact base 1. A return spring 5 is freely fitted around the shaft part 3a of the movable shield 3, and its forward end is fitted to a back side of a head part 3b formed on the forward end of the movable shield 3, and its rear end is fitted to a projected part 1c of a bottom part of the contact base 1. A spring pin 16 is press-fitted to the rear end of the shaft part 3a of the movable shield 3 to position the return spring 5 in the returned condition. In a condition where the head part 3b of the movable shield 3 is returned, a forward end face is slightly projected from a forward end face of a shield 2.
Patent JP-H04234999-A (JP)
Title: Selective amplifying system using q beta replicase
Inventor: JIEIMUZU II SUTEFUANO
IPC: C12Q1/68
Filed: 1991-04-24
Abstract: Mutant forms of midivariant RNA are disclosed which are replicated efficiently by the enzyme Q beta  replicase in the presence of an agent(s) which is useful for the real time, quantitative detection of the accumulating RNA products. This agent(s) also suppresses the replication of non-mutant wild type midivariant RNA. The mutant MDV RNAs, when modified by the addition of specific probe sequences, retain their replication properties in the presence of the detection agent. This method allows the replication to be monitored using a real time mode thereby providing a reliable method for monitoring the kinetics of the reaction, and determining the initial level of amplified RNA.
Patent JP-H0415897-A (JP)
Title: Coin processor
Inventor: MITA KATSUYA
IPC: G07D9/00
Filed: 1990-05-09
Abstract: PURPOSE:To reduce cost and to shorten memory reception processing time by constituting a system in such a way that all received true coins are once storage-processed in the same safe. CONSTITUTION:When the coins are received in a reception/payment port 13, they are taken inside through a finder 17 one by one and they are authenticated in an identification part 18. Then, they are collection-operated from a temporary storage part 20 to the collection safe 24. When there is a supply signal, the coins outputted from the collection safe 24 are led to the reception/payment port 13 through a return conveyance belt 26, and are led to the identification part 18 one by one. The types of the coins are judged in the part 18 and the coins are supplied to respective storage cylinders 31a-31h by individual coin types through a sorting plate 28, an individual conveyance line 19 and a supplementary chute 27. Since the system is constituted in such a way that all the received true coins are once storage-processed in the same safe, a memory- receiving route with simple constitution becomes short by omitting a money detector, and cost can be reduced, whereby money reception processing time can be shortened.
Patent JP-H11310029-A (JP)
Title: Air conditioner for vehicle
Inventor: SAGAWA KATSUHIKO
IPC: B60H1/00
Filed: 1998-04-28
Abstract: PROBLEM TO BE SOLVED: To prevent an uncomfortable feeling to an occupant when switching a guide port mode. SOLUTION: A target opening computed in accordance with a target blow-out temperature TAO is converted into a target rotation amount according to a correcting map to control an inside and outside air switching door 2 (a servo motor 14). In this way, the occurrence of a difference between an air quantity rate determined by the target opening and an actual air quantity rate is prevented. An uncomfortable feeling to an occupant is thus prevented when a guide port mode is switched.
Patent JP-H068521-A (JP)
Title: Figure preparation device
Inventor: IZAWA HIDETO
IPC: G06F3/153
Filed: 1992-05-12
Abstract: PURPOSE:To enlarge and reduce an output of an always well-balanced and good-looking figure by allowing an automatic decision of the necessity to change the setting of a thickness of figure line and an execution of the change, if such a necessity occurs. CONSTITUTION:The subject figure preparation device is composed of a key input part 11 which designates and enters a multiplying factor for the enlargement and reduction of figure data indicating a specified figure and a control part 12 which determines the thickness of a figure line after the enlargement and reduction, referring to a conversion table stored in a linear thickness correction part 14 based on the multiplying factor for enlargement and reduction designated by the key input part 11, and the thickness of a figure line of figure data stored in a figure data storage part 13. A specified figure based on figure data is enlarged or reduced in size in accordance with the thickness of a figure line determined by the control part 12, and the enlarged or reduced specified figure is printed out using a printer 15.
Patent JP-S61281240-A (JP)
Title: Exposing method for photomask
Inventor: TACHIKI FUTOSHI
IPC: G03F1/86
Filed: 1985-05-31
Abstract: PURPOSE:To prevent leakage of exposing light even under foreign matter and to decrease a pinhole defect rate of a photomask by forming a pattern image, by scanning of an electron ray, on a photosensitive material film on the photomask and applying the electron ray, after the end of scanning, to the part where exposing is obstructed by the foreign matter. CONSTITUTION:A sensor 11 detects the secondary electron 12 generated when the electron ray 11 is irradiated on the foreign matter during the scanning by the electron ray. The sensor calculates the position of the foreign matter 10 relative to a photomask 1 and stores the information on the calculated position into a memory in a controller 3. The position of the foreign matter 10 is indexed from the calculated position after the end of the scanning for forming a pattern image onto the photosensitive material film 1c on the mask 1, then the electron ray 7 is applied diagonally with respect to the mask 1 as shown by a solid line 7a or broken line 7b to irradiate the photosensitive material film part 1d under the foreign matter 10. The part 1d is thus subjected to the exposing treatment as well.
Patent JP-H05315977-A (JP)
Title: Method for decoding soft decision maximum and decoder
Inventor: ONISHI MAKOTO
IPC: H04L1/00
Filed: 1992-05-12
Abstract: PURPOSE:To reduce difficulty of reducing status tolerance by reducing a weight coefficient compared with the case the size of signal amplitude is large when the signal amplitude is reduced and probability is reduced. CONSTITUTION:An automatic gain control circuit(AGC) 81 is provided together with a soft decision branch tolerance calculating circuit 2 and a decoder 83. Although an amplitude average value over a certain time section is normally used for the AGC, the instantaneous amplitude value of a receiving signal is used in this case and the receiving signal itself is simultaneously sent to the circuit 82. The circuit 82 for calculating the branch tolerance of respective code sequences for a receiving sequence similarly to a branch tolerance calculating circuit in a convensional Viterbi decoder 83 has also a function for calculating soft decision tolerance and a function for multiplying the tolerance by a weight coefficient based upon signal amplitude. The found soft decision tolerance is sent to an addition comparator in the decoder 83. Thus branch tolerance obtained when the amplitude is small and an error rate is high is integrated upon the status tolerance.
Patent JP-S5822460-A (JP)
Title: Data processor
Inventor: NIHONYANAGI TOSHIHIRO
IPC: G06F9/48
Filed: 1981-07-31
Abstract: PURPOSE:To reduce the probability of production the queuing of processing, and to obtain accurate time, and to increase the flexibility of a system, by allowing a hardware time to have a prescribed time and also to indicate plural reporting means the prescribed time later. CONSTITUTION:The circuit control memory 1 of a data processor is provided as working memories corresponding to circuits; data on a prescribed time from timer counter software 6 is written as a timer set value 1a in the memory 1 and additional information 1b as specification information on a hardware queue after the prescribed time is further written. Every time the memory 1 is scanned by a scanner 2 on time-division basis, the timer set value 1a is decreased and when a borrow is generated, an overflow state is reported to the software 6. At this time, report orders are written in queues 4 and 5 by a queue loading circuit 3 on the basis of the indication of the additional information 1b. Then, the queue 5 is processed preferentially by the software 6 on break-in processing basis, and when the queue 4 is in idle time, the queue 5 is processed.
Patent JP-H10313013-A (JP)
Title: Bonding apparatus, bonding, and manufacture of semiconductor device
Inventor: KANDA MAKOTO
IPC: H01L21/52
Filed: 1997-05-09
Abstract: PROBLEM TO BE SOLVED: To provide a bonding apparatus and method which can eliminate the need for an operator to set bonding conditions. SOLUTION: The bonding apparatus automatically calculates bonding conditions including a central position of a semiconductor chip 1 and a central position of a die pad 3a on the basis of image data detected by a camera 12. Accordingly, it is unnecessary for an operator to set the bonding conditions in the bonding apparatus. Further, since position control of a housing 7 is carried out based on the bonding conditions calculated by the apparatus, the semiconductor chip 1 can be accurately mounted on a lead frame 3 at a suitable position.
Patent JP-S61276589-A (JP)
Inventor: TAKANO KUNIO
IPC: D05B3/20
Filed: 1985-05-31
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。