Patent GB-960951-A (GB)
Title: Fast multiply system
IPC: G06F7/52
Filed: 1962-07-18
Abstract: 960,951. Binary multiplying apparatus. SPERRY RAND CORPORATION. July 18, 1962 [Aug. 30, 1961], No. 27675/62. Heading G4A. An electrical circuit for multiplying a multidigit multiplicand by an N-digit multiplier in N/2 iterative cycles comprises means for producing, 0, 1, 2 and -1 times the multiplicand in response to the sensing of a pair of multiplier digits and means for inserting correction digits in the orders in the partial product register which receive no inputs during a cycle of the multiplication. As described, a multiplication operation for multiplying a multiplicand by a 24-binary-digit multiplier is performed in twelve iterative cyles each comprising four pulse times, together with a set-up cycle and an end correction cycle. Numbers X lie in the range -1 # X < 1 and in the set-up cycle, the operands are sensed. If either operand is 0, the product is zero; if either operand is -1, the product is the complement of the other operand; and if either of these conditions is recognized, a normal multiplication operation is not performed, but a shortened operation produces the correct answer. If both operands are -1, the product 1 is outside the range of representation and in this case the circuit performs a shortened operation and emits a signal indicating an error. Assuming that none of these special cases applies, a normal multiplication operation is as follows. In the initial set-up cycle the multiplier is placed in a 24-stage register Q and the multiplicand in a 24-stage register X. The first eleven iteration cycles are substantially the same. The partial product is built up in a 24-stage register A and shifted to the right in each cycle, the lowest two digits being transferred to the highest places in the register Q the contents of which are also shifted to the right so that the registers A and Q together are effective as a double length register. During each cycle the part of the partial product in the register A is fed to an "add tree", (Fig. 6, not shown) together with a value 0, Œ 1 or 2 times the multiplicand from the register X, the resulting sum being transferred to a register A* associated with the register A, the multiplier being transferred from the register Q to an associated register Q*. While the multiplier is in the register Q* the next pair of digits i.e. those in stages Q* 20 and Q* 21 apply signals to the multiply sequence control circuit, Fig. 1a to control the operation of the next cycle, the contents of stages Q* 22 and Q* 23, controlling the present cycle also being supplied to the control circuits since their value may also affect-the operation in the next cycle. The contents of the registers A*, Q*, regarded as a single register are then transferred with a shift of two places to the right to the registers A, Q, regarded as a single register, the two lowest digits of the register Q* being lost and the two highest stages A 00 and A 01 of the register A being left vacant. The stages A 00 and A 01 may be supplied with correction digits. Thus when twice the multiplicand is added it may be necessary to insert an overflow digit into the stage A 01. The number of iterative cycles is counted in a counter comprising two registers K and K*, Fig. 1a. The 12th cycle is different from the preceding ones in that only one multiplier digit, that in Q* 23, controls the addition of the multiplicand and there is a shift of only one place in the registers A, Q. After the 12th cycle an "end correction" cycle is effective to subtract the multiplicand X from the partial product of the sign digit now in stage Q* 23 is negative. The contents of A* and Q* are then transferred to A and Q without shift to complete the multiplication operation. Circuit details. The various registers are described in detail in the Specification and each comprise 24 flip-flop stages and associated gating circuitry controlled by the sequence control circuit Fig. 1b which also comprises flip-flops and associated gating circuits (Figs. 9a-9d, not shown) and receives signals from a main computer (not shown) to control timing and to initiate the multiplication operation, and from the various registers in the multiplier during the course of the multiplication operation. The parallel adder (Figs. 6a-6d, not shown) comprises six groups of four stages each, a carry output signal from any group being applied to each group containing higher order stages.