Patent EP-3817035-A3 (EP)
Inventor: PARK SANG-SICK
IPC: H01L25/065
Filed: 2020-09-25
Abstract: A semiconductor package includes a base substrate (100) having a first semiconductor substrate (110) and a first protective layer (130) covering a top side thereof. A first semiconductor chip (200) is disposed on the first protective layer (130). A first fillet layer (420) (e.g., an underfill) fills a space between the first protective layer (130) and the first semiconductor chip (200). A first side surface (SS1) of the base substrate (100) extends in a first direction (Y), and second and third side surfaces (SS2, SS4) extend in a second direction (X). The base substrate (100) includes two corner regions (CR1, CR2) and a side region (ER11) between the corner regions (CR1, CR2). The first protective layer (130) in the side region (ER11) includes a first side trench (T11) which overlaps the first semiconductor chip (200). A part of the first fillet layer (420) fills the first side trench (T11). The side trench (T11) restricts the amount of the first fillet layer (420) spreading from the center (CP) of the base substrate (100) toward the side surface (SS1) of the first semiconductor chip (200). The first side trench (T11) may include a first sub-side trench (T11a) and a second sub-side trench (T11b, T11c), spaced apart from each other in the side region (ER11), wherein the first sub-side trench (T11a) and the second sub-side trench (T11c) may have same or different lengths, widths, depths or volumes. The first side trench (T11) may comprise a concave surface facing away from a center (CP) of the base substrate (100). The first protective layer (130) in the first corner region (CR2) and the second corner region (CR1) may omit a trench. Alternatively, the first protective layer (130) in the first corner region (CR2) may include a corner trench (T22) at least partially overlapping the semiconductor chip (200), wherein a volume of the first side trench (T11) is greater than a volume of the corner trench (T22), and wherein a part of the first fillet layer (420) at least partially fills the first side trench (T11) and the corner trench (T22). A length (L1), width (W1) or depth (D1) of the first side trench (T11) may be greater than, respectively, a length (L3), width (W3) or depth (D3) of the corner trench (T22). The base substrate (100) may further include a second side region (ER22) disposed between the first corner region (CR2) and the first side region (ER11), wherein the first protective layer (130) in the second side region (ER22) includes a second side trench (T32) at least partially overlapping the first semiconductor chip (200), and wherein the volume of the second side trench (T32) is smaller than the volume of the first side trench (T11) and is greater than the volume of the corner trench (T22). The base substrate (100) may include a first penetration via (140) penetrating both the first semiconductor substrate (110) and the first protective layer (130), wherein a first bump (410) electrically connects the first penetration via (140) and the first semiconductor chip (200) and the first fillet layer (420) at least partially surrounds the first bump (410). The semiconductor package may further comprise a second semiconductor chip (300) disposed on the first semiconductor chip (200) and a second fillet layer (520) at least partially filling a space between the first semiconductor chip (200) and the second semiconductor chip (300), optionally at least partially surrounding a second bump (510) connecting the first semiconductor chip (200) to the second semiconductor chip (300).