Patent GB-685218-A (GB)
Title: Improvements in or relating to electronic digital computing devices
Inventor: UTTLEY ALBERT MAUREL
IPC: G06F7/501
Filed: 1949-12-23
Abstract: 685,218. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Dec. 14, 1950 [Dec. 23, 1949], No. 33023/49. Class 106 (i). [Also in Group XL (c)] A computing circuit in a binary electronic computing apparatus employing digit signals of opposite senses comprises matrix circuits, each adapted to provide an output signal only in response to a combination of signal elements, the algebraic sum of which exceeds a given threshold level, and each related to a given possible combination of digit signals, the signal elements applied to each matrix circuit representing an appropriate translation of the related combination of digit signals into sense-retained and sense-reversed form, and means for delivering the appropriate digit signals representing the result of the computation in response to an output signal from any of said matrix circuits. If a digit-signal is absent, none of the matrices will produce an output signal and an alarm may be operated or the apparatus stopped. An adding circuit, Fig. 5, employs eight matrices 1-8 arranged in four pairs each similar to the pair of circuits 1 and 2. Digit signals corresponding with the three digits to be added in a given denominational order-the corresponding digits A, B of the two numbers to be added and the carry digit C1 from the next lower order-are applied respectively to three equal resistors of each matrix. Each digit pulse produces one unit of current through the corresponding resistor so that when and only when three digit pulses of the same sense are applied to a matrix the total current taken is three units. When the three pulses are negative, a circuit similar to the matrix 1 produces an output and when they are positive, a circuit similar to the matrix 2 produces an output. In each matrix a resistor R1 or R1<SP>1</SP> is connected to a bias potential and supplies 2¢ units of current, normally drawn through a rectifier D1 or D3. When, however, three pulses of the same appropriate sense are applied, ¢ unit of current is drawn through an output rectifier D2 or D4. A matrix is provided for each of the eight possible combinations of three binary digits and the sense of one or more of the digit signals applied to each is reversed. The connections are arranged so that for any combination of three digits, only one matrix will produce an output and the sense of the output will correspond with the resultant carry digit C2. The output from the matrices is applied via an amplifier 11 (see Group XL (c)), which produces a constant amplitude output, to the carry output terminal, and also to a phase reversing amplifier 12, the output of which forms the sense reversed carry input for the next order. One-digit delay devices 14, 15 are incorporated in series-mode machines. Except when the three digits to be summed are the same, the sum digit S is different from the carry digit C2. Additional matrices 9, 10, similar to the matrices 1, 2 and with the same input connections (each input signal is sensereversed), detect whether the three digits are the same and to each the carry output C2 is connected via a resistor R6 or R7. Each of these matrices is also connected via double diodes D7-D8 or D9-D10 and resistors to both the carry output C2 and the sense-reversed carry output so that whatever the carry output a negative signal is applied to the matrix 9 and a positive signal to the matrix 10. The arrangement is such that when the three digits are equal, the sum output S from an amplifier 13 to the input of which the outputs of the matrices 9 and 10 are connected, is equal to the carry output, but otherwise it is of opposite sense to represent the other digit. The absence of a signal at either the carry output or the sum output, at a digit time indicates a fault. To test the sum output, for example, the latter is connected via a rectifier D11, Fig. 7, and via a rectifier D12 and a sense-reversing pentode V4 to the grid of a pentode V3, so that the latter is cut-off during each sum digit pulse whatever its sense. If no pulse is present, a clock pulse applied to the suppressor grid of the pentode V3 will cause the latter to conduct. The anode is connected to a trigger circuit 20 which is thereby switched to release a relay 21 arranged to operate an alarm or stop the apparatus. In a modification, Fig. 8, each pair of matrices is combined, the rectifiers D1, D3 being connected to a common bias potential and the rectifiers D2, D4 being connected to points in the resistors R1, R1<SP>1</SP>. Specification 683,882 is referred to.