Patent GB-797411-A (GB)
Title: Improvements in electronic data processing system
IPC: G06F11/14
Filed: 1955-02-21
Abstract: 797,411. Digital electric calculating-apparatus. DEHN, S. G. (Remington Rand, Inc.). Feb. 21, 1955, No. 5168/55. Class 106 (1). In an electronic calculating system of the type that is programmed to execute a sequence of arithmetic computations, checking means perform, after each individual computation, a complementary computation to check the result of the first computation and are effective to restart the programme sequence or the last individual computation, if the check computation delivers a differing result. General. The calculator shown in Fig. 1 comprises a control unit and a data processing and storage unit and is associated with an input-output unit comprising a known record-card-reproducing punch (not described in detail) including a reading and a punchingstation ; reference is made to other forms of input and output, e.g. magnetic or electrostatic storage. The data processing and storage unit comprises an accumulator with associated input and output circuits and stores, described separately below, and the control unit comprises a programme-control plugboard, half of which is-shown in Fig. 36a, and other elements as shown, which, as well as the accumulator, its input-output circuits and the result store, each comprise one or more chassis, the chassis lay-out for the front half of the calculator being shown in Fig. 2. Detailed circuit diagrams are given for all the calculator elements. The circuits consist primarily of triodes employed in amplifiers, cathode followers, coincidence gates, bi-stable trigger circuits and monostable flip-flops, the different types of circuit elements being generally represented by similar blocks and differentiated by a letter and number code given in detail in the Specification. The calculator can perform the four rules; each separate computation is followed by the. complementary check computation (e.g. addition is followed by subtraction of the two factors from the result) before the calculator can proceed to the next programme step which is determined by the sign of the result of the preceding step. The decimal counter controls the shifting of amounts in the accumulator to align decimal points. Various output cardcontrol or -punching operations may also be programmed. If the check indicates an error in a computation, or if the test counter arranged to count a predetermined number of switchselected calculator operations reaches its capacity, the last programme step or the whole programme sequence (as determined by plug connections) is re-started. Accumulator. This comprises 22 decimal stages 1-A to 11-A, 1-M to 11-M (not shown), each of which is similar to that described in Specifications 665,707 and 665,714, and comprises double triode bi-stable trigger circuits for registering digits in a biquinary code, and associated indicating neon tubes. Each stage comprises also a carry trigger, gating or switchamplifiers, whereby the triggers may be connected selectively for addition or subtraction as described in Specification 676,672, under control of the sign bias chassis, and shift gates for transferring the registered digit to the next higher stage, as described in Specification 674,210, in response to shift pulses from a shift impulse generator (not shown). The contents of the highest order stage 11-M are shifted to the lowest order 1-A. Carries are effected under control of a carry impulse generator (not shown) which is started by a control pulse (CX) only if one of the accumulator carry triggers has been actuated. Stage 11-M provides a special control output signal when zero is registered. Numbers are entered and read out from stages 1-A to 10-A which each have an input-output chassis I-O, Fig. 2, associated therewith. Input translator for accumulator. The input portion of an input-output chassis comprises gating circuits, Figs. 21a and 21c, for translating a decimal digit from the " 90 column " card code, Fig. 44, to the biquinary accumulator code. The digit is entered by raising the potentials of terminals 23, 25, 31, 9 and 15, corresponding to 1, 3, 5, 7 and 9, respectively, and causes one-valued pulses RIG 1<SP>1</SP>, RIG 1, Fig. 43, from terminals 13 and 5 to be selectively applied (as indicated in Fig. 44) to the accumulator via terminal 3, and two-valued pulses or pulse trains RIG 2, RIG 4, RIG 6, RIG 8 from terminals 27, 29, 11 and 7 to be selectively applied via terminal 21, these pulses being obtained from the registration impulse generator, Fig. 1. A high potential on the " 9 " input terminal 15, for example, will bias the grid of the lower half of gate tube I-79 whereby the positive pulse RIG 1<SP>1</SP> from 13 will produce an anode output pulse which is passed to 3. Similarly the pulse RIG 1 from 13 is gated to 3 through the top half of tube I-09 whose grid is biased from the commoned cathodes of buffer double diodes C17, C35 having their anodes connected to the " 1," " 3," " 5 and " 7 " input terminals. The RIG 2 and RIG 4 pulses are passed to terminal 21 via the top and bottom half of tube I35 when the " 3 " and " 5 " input terminal is high, respectively, and RIG 6 pulses are passed through the top half of I 79 when the " 7 " input is high. The RIG 8 pulses are passed via gating and amplifier tube 19 and the bottom half of I 09 when the " 9 " input terminal is high and the " 1," " 3," " 5 " and " 7 " input terminals are all low, the cathode output of diodes C17, C35 biasing I9 through inverter IA9. Registration impulse generator. This comprises a series of three bi-stable triggers and a multivibrator (Figs. 27a-27c, not shown) arranged to operate through a cycle in which the accumulator control pulses of Fig. 43 are supplied to the input translator, Fig. 1, followed by the carry control pulse (CX). The RIG 11 pulse may also be gated to accumulator stage 11M or 1M during multiplication and division respectively. Output translator and result storage. This comprises, in each input-output chassis, gating circuits (Figs. 21b and 21d and 45, not shown) for translating potentials from the triggers of the associated accumulator stage, representing the registered decimal digit, into operative potentials selectively applied on output lines, corresponding to values 1, 3, 5, 7, 9, in accordance with the " 90 column " code, Fig. 44. These lines are connected to corresponding terminals of an associated stage in each of 8 10- digit result stores P-Y, Fig. 2. The stores are divided into chassis, Figs. 31a and 31b, which store two digits each by selective actuation of relays R1, R3, R5, R7, R9 via triodes S1, S3, S5, S7, S9. The " 1," " 3," " 5," " 7," and " 9 " input terminals (31, 25, 19, 13 and 7 for the lefthand half) are connected to the triode grids, and a store-selecting terminal 36 is connected to the commoned cathodes. When a low potential is applied to 36 from the storage set chassis, Fig. 1, via the regulator, those triodes having a positive potential on their grids will conduct and energize corresponding relays which will be held through contacts H. For each store, a sign relay (not shown) also is energized when the stored number is negative. The stored value may be read out to card-punching magnets via contacts P, or to the input buffer and translator via contacts I, by energizing terminal 2 or 1, respectively. A store is zeroized under control of the storage zeroize chassis, Fig. 1, by raising the potential at 36 to equal that of 34, thus de-energizing the relays. The stores are selected by the keyboard bias chassis and, for zeroizing during a programmed clear operation, also through manually set switches. Card sensing and storage; card punching. For each of the 90 columns of a sensed card, a set of 6 sensing pins each close an associated switch # (representing 0), 1, 3, 5, 7, and 9, Fig. 41, if they sense a card hole. These switches and the associated punch magnets are connected to a " card column cable " terminating in a 14-prong plug. Each plug may be inserted in any of 57 input or 80 output sockets (not shown). The input sockets are divided into groups A-I (not shown) of from 10 to 1 digits whereby numbers of different lengths may be selectively fed via the input buffer to some or all of the input-output chassis I-O, Fig. 2. If a number in a storage group may be negative one of the 540 sensing switches is selected to represent its sign by connecting a 2-prong plug thereto. An input storage group is selected by the keyboard bias chassis which energizes the common lines C, Fig. 41, of the appropriate column cables and, also, one lead of the associated sign plug. The 80 output sockets correspond to the 80 digit positions of the result stores P-Y and, by plugging the appropriate cables, the stored numbers may be punched in any desired card columns; 90 " reproduce " sockets also are provided to enable data in any card columns to be reproduced in other columns. Constant storage. Constants may be set up on 120 rotary digit switches which are divided into 20 storage groups (K1-N5, not shown) of 10, 6 or 4 digits each. The switches in a group and an associated sign switch, which is closed for a negative number, have a common connection to a keyboard bias output which is energized for read-out. Keyboard bias storage selection; input buffer. One of the 8 result stores P-Y, 9 card sensing stores A-I, or 20 constant stores K1-N5 is selected, e.g. for read-out to the accumulator, by a pulse from an associated plugboard socket to a keyboard bias amplifier circuit, such as KB(B), Fig. 46a, the output from which is applied through the storage switches or relay contacts and neon diodes in the input buffer, Fig. 1, to the input translator; the output is also applied through the sign switch to the sign-control " minus neon common " line and to the decimal switch. Decimal switches and counter. A 12-position decimal switch, Figs. 46a and 46c, for each of the 37 stores, is set to indicate the decimal