Patent SE-364594-B (SE)
Inventor: PETRUZELLA J
IPC: H01L23/373
Filed: 1970-05-05
Abstract: 1312702 Semi-conductor assemblies GENERAL ELECTRIC CO 4 May 1970 [5 May 1969] 21375/70 Heading H1K A semi-conductor assembly comprises a silicon crystal 102 having major surfaces 104, 106 lying in the 100 crystallographic plane. A central zone 108 (Fig. 2) has N conductivity and is separated from the major surfaces by first and second zones 110, 112, of P conductivity forming 1st and 2nd junctions 114, 116. A third zone 118 between a portion of the 1st zone and the first major surface is of N+ conductivity and forms junction 120. A V-shaped border groove 122 spaced from the outer edge surrounds the crystal and divides it into centre 124 and periphery 126, being bounded by intersecting slopes 128, 130, cutting the first and second junctions and filled with a thick passivating layer 132 of alkali free, e.g. lead borosilicate glass whose thermal coefficient of expansion does not exceed that of silicon and is of high insulation resistance and dielectric strength. An ohmic contact layer 134 overlies the second major surface and single or multiple contact layers 136, 138 overlie the third zone 118 and a portion of the first zone 110 adjacent the first major surface; an oxide or nitride layer covering the uncontacted portions. The crystals are processed while integrally joined in a wafer and junctions 114, 116 are formed by diffusion while 118 is formed by diffusion or alloying. The grooves are formed by masking the wafer with, e.g. silicon oxide or nitride which is selectively removed, and etching with alcoholic potassium hydroxide, and the glass passivating layer is deposited from an aqueous slurry of frit, dried and sintered. Individual devices are separated by sawing or scribing. The device may be incorporated into an assembly by attaching layer 134 to a metal plate heat sink having an integral terminal lead and fixing tab and the first and third zonal layers are fly wire connected to further terminal pins; after which a plastic housing is formed to envelop the device, the heat sink, and the inner ends of the terminals; which may be of silicone, phenolic; epoxy, or polyester resin. (Fig. 3, not shown). The devices may be assembled on a single metal plate for heat sinks and terminals, which is divided after connections have been made, and then encapsulated. An avalanche thyristor is fabricated by omitting layer 138, and bilateral thyristors, PN, P+PN, PIN, and PNN+ diodes may be similarly made. In a modification (Fig. 4) the crystal is divided into central portion 202 and concentric peripheral portion 204; a collector zone 206 extending through both portions and adjacent major surface 208 while base zone 210 is adjacent major surface 212, to form collector junction 214. An interdigitated emitter layer 216 lies adjacent the second major surface and forms an emitter junction with the base zone, while carrying ohmic emitter contact 218. A base contact 220 spacedly surrounds the emitter contact. Bevelled edges 222, 224 define surrounding grooves filled with a glass passivating layer 226. The assemblies are formed simultaneously from a single wafer, the base and emitter contacts are unitarily formed and divided by selective etching, and the grooves are formed by etching through with alcoholic potassium hydroxide while the element is supported on a substrate, after which the glass layer is inserted and the elements divided by sawing or scribing through the peripheral portions. The glass intersects the collector junction 214. The grooves may be trapezoidal in profile.