Patent GB-868236-A (GB)
Title: Signal translating device
Inventor: ECKERT JOHN PRESPER
IPC: H03K19/16
Filed: 1957-06-17
Abstract: 868,236. Magnetic amplifiers; circuits employing bi - stable magnetic elements. SPERRY RAND CORPORATION. June 17, 1957, No. 18965/57. Class 40 (9). The invention relates to magnetic cores with rectangular hysteresis characteristics which are magnetized to saturation in one sense by periodically-applied power pulses, and are magnetized to saturation in the opposite sense whenever a signal pulse is applied, the signals being effective in the intervals between the power pulses, and the resultant flux excursion between the saturation limits inducing a voltage in an output winding. A basic arrangement is shown in Fig. 2 in which a magnetic core C has power, output and signal windings I, II, III and a diode D is provided in the output circuit for suppressing the unrequired output during the periods when the core flux is initially charged by a signal pulse. Other spurious voltages induced in the power and signal windings during operation may be suppressed by the use of appropriate blocking pulses and/or diodes. The power winding is energized from a constant current source, Fig. 4, comprising a positive potential source S and a diode P, the current being diverted away from the power winding III except when a power pulse is applied to terminal A. The use of a separate output winding is avoided in Fig. 9, in which the output load RL is connected via diode D across the power winding I, blocking pulses being applied during the signal input periods at terminal D1. In a further arrangement, Fig. 10, the core has but one winding which serves all three purposes, the power pulses being applied to diode D1 and the signal pulses to capacitor F. Output pulses are then obtained over diode D4. In a modification the signal input circuit including diodes D2, D3 up to point X may be connected to a tapping B on the core winding. Arrangements may also be provided for suppressing the spurious output which occurs during each power pulse period in the output circuit due to non- rectangularity of the core hysteresis loop. In one arrangement an equal and opposite pulse is injected in the output circuit during each power pulse period. Alternatively, since the spurious pulses have a high frequency content, high and low-pass filters may be connected in shunt and in series respectively with the load, Fig. 12 (not shown). A further method is the use of an opposed coil in the output circuit, the core of which produces a pulse just sufllcient to cancel the spurious pulse. Use of a condenser in parallel with the load is mentioned for integrating the output pulses, Fig. 15 (not shown). Alternatively a continuous output may be obtained by connecting the output coil II to several spaced points of a delay line, Fig. 16. A complementer is also described, Fig. 17, the signal at terminal A acting on a gate G so as to inhibit the application of periodically-applied timing pulses to the signal winding III. The output pulses obtained from a core may be maintained constant in both amplitude and duration by the provision of a biased diode D1, Fig. 18, in the output circuit. Alternatively this method may be applied to the input circuit of the power winding by using a diode D2 and the circuit shown in dotted lines. When a constant voltage power source is used, Fig. 19, the power pulse source is applied through a diode D1, and the other end of the power winding is grounded by a diode D2 when the power pulse exceeds a certain value determined by a negatively-biased resistor R1. The latter circuit may also be used as a complementer, the inverse output being obtained from terminal A. Applications of the magnetic core arrangements described are also outlined, the core arrangements being connected in circuit with gates and buffers to form a pair of cores providing interlaced outputs over a common channel, Fig. 20 (not shown), trigger units which provide a constant output in response to an input pulse until such time as a restore pulse is applied, Figs. 21 and 21c (not shown), a frequency divider, Fig. 23 (not shown), and a shifting register, Fig. 25 (not shown).