Patent ES-354217-A1 (ES)
Title: Monolithic integrated structure including fabrication thereof
IPC: H01L27/118
Filed: 1968-05-22
Abstract: In an integrated circuit comprising a semiconductor substrate having formed therein a number of devices sufficient to permit any one of a number of different circuits to be formed by appropriate interconnections, a plurality of terminal structures is provided spaced around the area in which the devices are formed. Each structure consists of a metal contact disposed above and insulated from an electrically isolated region in the substrate. The devices, isolation regions and underpass connections are formed in the following series of steps on a 10-20 ohms cm. P type silicon wafer the surface of which is 2À5 degrees off a 111 plane in the direction of a 110 plane. First a silica coating produced by conventional techniques is formed into a mask by standard photoresist and etching steps, and N+ regions formed by diffusion from degenerate arsenic-doped silicon, or by epitaxial growth into pits etched through the mask. Next depressions are formed over these regions, by oxidizing the surface and then etching away the oxide, to facilitate location of the regions after a À09 ohm. cm. 5À5 Á N type layer has been epitaxially deposited. After forming a further oxide mask on the layer boron is diffused to form an isolation network. Then, following further oxide masking, diffusion and drive-in steps to complete the device zone structures, contact holes are formed in the oxide by a process in which successive photoresist masks are used to avoid the risk of pin holes in the oxide. Aluminium or molybdenum is then deposited overall and pattern etched to form interconnections and contacts which are rendered ohmic by sintering. A coating of silica or glass is sputtered on and holes etched through it to expose selected contact lands on which terminals are formed by masked deposition of chromium, copper and gold. Finally lead-tin solder is applied and melted to form balls via which the circuit is soldered to lead-tin coated lands on an insulating header. The devices in the structure include the following: (i) Groups of P type resistors formed by diffusion into common isolated N type regions and each provided with a plurality of tapping points for maximum flexibility. (ii) Resistors consisting of isolated sections of the epitaxial layer contacted via contacts located on N+ surface diffusions. (iii) Underpass conductors consisting of P+ regions diffused through the epitaxial layer and contacted via P + + surface zones. (iv) Resistors consisting of elongate N+ regions buried under the epitaxial layer. These are wider at the centre than at the ends and are contacted through electrodes located on elongate N + surface diffused regions disposed transverse to the narrow ends. This arrangement provides maximum manufacturing tolerances, and gives sufficient space for several conductors to cross the wide centre section on insulation of optimum thickness. (v) Transistors with two base and two collector electrodes. (vi) Test transistor structures as described in Specification 1,080,177 at the periphery of the wafer. To facilitate mask alignment and to indicate what stage of the process has been reached each mask incorporates alignment and alpha-numeric identification marks. Normally a number of wafers initially form part of a master slice and to facilitate dicing the corners of each wafer are provided during metallization with comb like graduated marks. The corner contact pads also include symbols spaced 90 degrees apart to facilitate alignment of the glass aperturing mask. Orientation and mechanical handling is facilitated by having two pairs of terminal structures on opposite edges spaced more widely than the others. In the typical logic circuit shown in Fig. 5 undesirable voltage drops in the the metallization are minimized by having the resistors 1R close to the -V terminal P 9 and components are generally disposed to reduce the lengths of interconnections and number of cross-overs.