Patent GB-1143355-A (GB)
Title: Hybrid computer
IPC: H03M1/00
Filed: 1966-10-21
Abstract: 1,143,355. Hybrid product/quotient computer. ADAGE Inc. 21 Oct., 1966 [23 Oct., 1965], No. 47414/66. Headings G4A and G4G. [Also in Division H3] General.-A hybrid product and quotient computer comprises a variable gain network (Fig. 1, not shown) wherein an inverting amplifier of high gain is connected in tandem with a non-inverting amplifier of low gain and the analog input is connected over a digitally controlled attenuator comprising n binary weighted resistors graduated 1, 2, 4 &c. in order and having conductances graduated 1, ¢,  &c. in series with a range of respective corresponding electronic switches controlled by binary input signals. A second similar digitally controllable feedback attenuator is connected from the output of the second to the input of the first amplifier and comprises n binary weighted resistors in series with a corresponding range of switches so that a binary input signal inserts a proportional conductance. Capacitors corresponding to at least the smaller resistances of the range are connectable across the input and output of the first amplifier and have capacitances given by RC = K where K is constant and R, C are values of corresponding capacitances and resistances, which stabilize the system by reducing the amplifier bandwidth when the digital input signal exceeds a predetermined level. Multiplication or division is effected by supplying digital input signals to corresponding ranges of switches to set the appropriate attenuator to an appropriate conductance value; the remaining unit being set to unity. Computer details.-Fig. 2 shows a sophisticated computer wherein an analog input signal is multiplied or divided by a digital signal expressible by a sign bit plus 14 bits specifying value; positive numbers as a binary fraction between 0 and 1 and negative numbers by the inverse of the corresponding binary fraction with a logic 1 sign bit for negative. An 8 bit control signal is stored in register CR comprising plural flip-flops P1F to P6F; DF; and DRF; each set to logic 1 state to produce positive at output 1 and negative at output 0 for positive potential at set terminal S; and to reset to logic 0 to produce positive at input 0 and negative at output 1 when positive is applied to reset terminal R. Bits P1 to P6 stored in P1F to P6F select any desired set out of six analogue input signals for application to six analogue input terminals x 1  to x 6 , and DF is set to logic 1 for divider and to logic 0 for multiplier operation. DRF turns the computer on at logic 1 and off at logic 0, and the respective pulses P1 and P1 are selectively applied to set the required flipflop states from a programmed digital computer e.g. as described in Specification 1,143,356. A similar value register VR stores a 15 bit value signal for multiplication or divisions in which flip-flop BOF stores the sign bit and 14 flip-flops BIF to B14F store the signal. The analogue signals at x 1  to x 6  are applied over resistors R1 to R6 and electronic switches SS1 to SS6 to a summation junction 1; the switches being closed for positive at terminal a, derived when flip-flop DRF is at logic 1 and a corresponding selection flip-flop P1F to P6F is at logic 1; switches SS1 and SS6 receiving PIDR and P6DR signals respectively from conventional gates G1. Junction 1 is the input to conventional amplifier A3 with feedback over R2 developing output representing the algebraic sum of signals at terminals x 1  to x 6  as selected by switches SS1 to SS6. The output energizes two-stage amplifier A1 A2, as described, over plural paths selected by settings of registers CR and VR. A first path comprises resistance R8 and conventional electronic switch S18, closed when DF and DRF are set and 30F is reset, by a signal D.DR.BO from gates G1 responsive to the registers; thus multiplying the input unity in divide condition with a positive digital value applied. A second path comprises resistor R9, inverting feedback amplifier A4 summation resistor R11, and electronic switch S19, closed by signal DR.BO from gates G1 in response to setting for flip-flops DRF, BDF when a negative number is stored in register VR, to multiply the input signal by -1 when the system is in divide (or multiply) condition and a negative digital value is applied to VR. A third path comprises a digitally controlled attenuator DAC1 having 14 digital inputs dl to d14 selecting appropriate conductance paths as described in response to logic 1 signals from gate circuit G1, when a corresponding flip-flop B1F to B14F is set, DF is reset and DRF is set. The first and second tandem amplifiers A1, A2 as described carry digitally controlled feedback over attenuator DAC2 similar to DAC1, with 15 digital input terminals d1 to dis setting appropriate conductance paths in response to gates G1 and the input values and signs stored in registers VR and CR; the conductances representing the stored value when the latter is positive and its inverse when negative. An intermediate input terminal connected to the gain of the amplifiers introduces a selected capacitative feedback over amplifier A1 to restrict the bandwidth for stability, as described. The gate circuits may each comprise (Fig. 4, not shown) three interconnected NOR gates. Attenuator details.-Fig. 3 shows an attenuator DAC as in DAC1, DAC2, wherein 15 electronic switches S1 to S15 select conductances between input a and output b, and capacitances between input c and output b dependent on digital signals supplied to inputs d 1 to d 15. Switch S1 similar to remaining switches S2 to S8, comprises PNP transistors Q1, Q2 and NPN transistor Q3 inter-connected as shown with the collector of Q1 returned through resistances to a negative bus 7 with the base thereof: the latter being connected over Zener diode Z1 to respective inputs d1 to d8. The emitter of Q2 is connected to output C over bandwidth control cpacitor C1 and to input A over resistances R16, R17, while the emitter of Q3 is connected to output b. For logic 0 (negative) or zero signal at input d1, Q1 conducts, Q2 saturates, and Q3 is cut off to disconnect b. For logic 1 (positive), Q1 cuts off, Q2 cuts off, and Q3 saturates in response to bias stored on capacitor C8, to connect an appropriate conductive path from a to b over resistors R16, R17, and an appropriate capacitance path from b to c. No capacitance insertion is necessary subsequent to switch S4, and switches S9 to S15 are simplified since switching currents are reduced. In S9 to which S10 to S15 are similar, a NPN transistor Q4 and PNP transistor Q5 are connected as shown with the base of Q4 connected to input d9, the collector returned to a positive bus; and the emitter to a negative bus; while the emitter of Q5 is grounded over resistance R25 and connected to output over resistance R24 and connected to input a over resistances R21, R23. For logic 0 input (negative) Q4 is cut off and Q5 saturated to ground output b, while for logic 1 input (positive) Q4 conducts and Q5 cuts off to insert the appropriate conductance between input a and output b Additional switch S15 inserts conductance in the feedback attenuator corresponding to unity divisor when the apparatus is in multiplying condition, since application of logic 1 signals to d1 to d14 introduces a division factor differing from unity by 1 bit. Operation.-A control is loaded into register CR and a value into register VR, and a set of analogue input signals is applied to terminals x 1  to x 6 . Flip flop DRF is set, so that the apparatus produces at c an ouptut analogue signal proportional to the algebraic sum of inputs x 1  to x 6  as selected by the settings of flip-flops x 1  to x 6 , multiplied or divided by the stored values in flip-flops B1F to B14F as selected by the state of flip-flop DF. Whether the signal at junction 1 is positive or negative for the digital multiplication, logic 1 signals are applied to inputs d1 to d15 of attenuator DAC2 to establish division by 1. Switch S18 is open, and switch S19 is closed for negative and open for positive, so that if the signal to be multiplied is positive the path from point 3 to point 5 is through digital attenuator DAC1 set to a conductance dependent on the value stored in register VR. If negative switch S19 is closed and negative numbers expressible as their inverses are approximated by the comple - ments referred to unity with small error correctible by arranging switch S15 of DAC1 to introduce an additional 1 bit in the least significant position, to insert a conductance proportional to the time complement in DAC1 so that its output represents the complement referred to unity of the digital input multiplied by the analogue signal at terminal 3, while amplifier A4 supplies a signal proportional to the negative value of signal at S, so that the resultant at S is identical to the negative number expressed at the corresponding inverse fraction. Division is directed by setting flip-flop DF1 and the digital value signals are applied (inverted for negative) to input terminals d1 to d14 of feedback attenuator DAC2 and no input is supplied to input d15 of DAC2. If the number is negative, switch S19 is closed to produce a signal at input 5 of A1 equal to (-1) x the signal at input 3. If the number is positive, this switch is opened and switch S18 is closed to produce a signal at input 5 equal to (1) x the signal at input 3, so that the output at a has polarity dependent on the signs of the algebraic sum of the input signals and on the digital value.