Patent GB-1016865-A (GB)
Title: An information storage and retrieval system
IPC: G11C11/44
Filed: 1962-07-18
Abstract: 1,016,865. Associative matrix stores. GENERAL ELECTRIC CO. July 18, 1962 [July 25, 1961 (2)], No. 27630/62. Heading G4C Binary data stored in superconductive memory matrix 1 is addressable by content, enabling " tag " searches from register 2, and a ranking matrix 6 is provided to select only one row of the matrix 1 in case of multiple agreement with the tag, this row being read out serially over line 8 and then invalidated before further agreements are searched for. Each data bit in matrix 1 is stored as a circulating current in one of the loops 16-24, and other loops 3 and 10 are provided for each row, for control purposes. Cryotron gates are shown at, for example, 29 and 31; current in the wire shown as continuous (26 in these cases) will render the previously superconductive conductor crossing near it resistive. The entry of data into the matrix and a subsequent search for data words having specified bits in specified positions will now be described. Entry.-Current is passed through line 43; this divides equally in each of the circuits 3 between the right- and left-hand paths. A current through line 44 renders gates 45 in the left-hand paths resistive diverting the current in 43 through the right-hand paths, and when that in 44 ceases the current will continue in the right-hand path only. When the current in 43 is cut off a circulating current of half its amplitude will be established in each circuit 3, since their two sides have the same inductance. An interrogating word consisting of all zeros is now entered into data register 2, and compared with the previously stored words to select the empty row nearest to the bottom of the Figure (this action is explained below; its effect is to produce a current in the conductor 30 of the selected row which closes the gate 46 of corresponding circuit 3 and breaks the circulating current). The data word to be entered is now transferred to register 2 and produces currents in lines A, B ... n, the current being in one direction for binary 1 and the other for binary zero. As described above for circuit 3 these currents divide in the circuits 16-24 and when " set memory " line 4 is pulsed this will be transmitted via the previously selected circuit 3 (circulating currents in the others holding their gates 48 closed) to its line 33 to set up circulating currents in that row, clockwise or anticlockwise according to the bit, when the pulse on line 4 ends. Interrogation.-Circulating currents are established in all circuits 3 as described above. An interrogation word is entered into register 2; this consists of a binary 1 or 0 in each position in which comparison is desired (the tag), the remaining positions being " blank." This word is then presented to the matrix as a current in each of the " tag " lines in the opposite sense from that used to enter the same bit. This divides in each of the circuits 16 &c. so that current cancellation will occur in the right-hand leg of each circuit in which identity between the stored and interrogating bit occurs. Where these two bits are unequal the current in the right-hand leg will be increased, and in the case of blank positions in register 2 it will be unchanged. Gates 31 are so designed that except in the case of unequal bits the gate will remain open, so that in each row where identity between all the tag bits and the corresponding stored bits occurs the conductor 30 (insofar as it lies inside matrix 1) will have a "zero" resistance. The conductors 30, each with a parallel conductor 36, are connected in series and a " compare " current applied, which will flow through one at most of the conductors 30 since current in one will close gates 38 in all others above it. The address of the selected row may be obtained from decoder 40 (a cryotron gate decoder is illustrated in Fig. 6, not shown) and the closing of gate 47 as described above opens gate 49 to allow serial read-out of the data in the row by pulsing the lines A, B &c. in turn and detecting the impedance of line 35. A circulating current is now set up in circuit 10 of the selected row by pulsing lines 52 and 9 and this renders conductor 30 resistive (gate 54) so that after setting up currents in all circuits 3 again a further interrogation can be effected to select the next row in which identity occurs.