Patent GB-1496921-A (GB)
Title: Data terminal apparatus
IPC: G09G1/00
Filed: 1975-01-10
Abstract: 1496921 Data terminal; program control TELETYPE CORP 10 Jan 1975 [28 Jan 1974] 1030/75 Heading G4A A data terminal, e.g. of the kind having a display to display data stored in a memory, includes a program memory and two instruction decoders each responsive to the same instruction to initiate different operations of the terminal simultaneously. Program instructions stored in a read only memory 12 are accessed by ROM address register 38 and fed to two instruction decoders 48, 50 which are selectively enabled by bits from the instruction over lines 58 and 60. The decoders supply command signals over bus 56 to control the remainder of the terminal and, where two operations do not conflict, e.g. only one requires the use of the data memory 16, both decoders are enabled and the two operations performed simultaneoulsly in response to the same instruction. The two status selectors 52, 54 are selectively enabled by bits from the current instruction over lines 62, 64 to test for status determined by the instruction. Any positive response causes the ROM address register 38 to be incremented twice to skip an instruction whereas a wholly negative response causes the ROM address register 38 to be loaded in accordance with the current instruction. Examples of sequences of operations which include cycles where two non-conflicting operations are performed simultaneously are given in the Specification. As described the terminal includes a data memory 16 storing characters to be displayed (at 18) with attributes, e.g. underlining of characters, stored in additional bit positions associated with each character. The terminal is connected via I/O port 22 to an I/O device 24, e.g. a keyboard or data line. A multiplexer 30 controlled by the program instructions selectively connects the ROM 12, the data memory 16, and the I/O port 22 to a buffer 28 which is connected to the data memory and I/O port. Data loaded in the buffer under program control is compared continuously by comparator 32 with the current instruction from the ROM. The comparator is however activated only by a specific compare instruction when negative and positive results cause the ROM address register 38 to be loaded from the current instruction and incremented twice to skip an instruction respectively. The comparator is used for example to check whether a character in the buffer which is to be transferred to device 24 via the I/O port 22 has a particular attribute, e.g. it is underlined. If so the addressing of the ROM accesses instructions to send the character, to send a backspace character derived from the ROM 12 and loaded in buffer 28 via multiplexer 30, and to send the attribute character. If no attribute is present the ROM is addressed to access instruction to send the character to the device 24 and to access the next character to be sent from the data memory. The data memory 16 is addressed by memory address unit 20 which may be as described in Specification 1,474,289 and which includes means to display a cursor to allow the data to be edited. When a data character is being displayed, i.e. the data memory 16 is in use, the ROM address register 38 is inhibited to prevent a new instruction being accessed, when the current instruction also requires access to data memory 16. When the display operation terminates the instruction can then be executed.