Patent GB-1349369-A (GB)
Title: Time division multiplex telecommunication system
Inventor: DE KOE O B P R
IPC: H04Q11/04
Filed: 1971-06-21
Abstract: 1349369 Digitalr tansmission; automatic exchange multiplexing PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 21 June 1971 [24 June 1970] 28943/71 Headings H4P and H4K In a known multiplex exchange system comprising a group of sources of multiplexed signals 100-0 &c. derived from single channels, cyclic data stores of receive line units 102 are connected to an adjustable second order multiplexer 105 controlled by a cyclic address store 126 of cycle time = 1 frame, and of size = number of sub time intervals, the multiplexer 105 being connected to a second order de-multiplexor 107 also controlled by a second cyclic address store 128 similar to 126. A third cyclic address store of cycle time = 1 frame and size = number of main time intervals is associated with each receive line unit to provide arbitrary association of store locations of the cyclic store with single transmission channels. A plurality of sources 100-0 &c. of multiplex signals, each of which comprises a plurality of single non-multiplex channels, supplies a multiplex signal on a given time scale consisting of e.g. equal frame time intervals divided into main equal time intervals to-tn each having a same position in each frame associated with a single source. Main time intervals are further divided into sub-intervals. Single sources may be connected via concentrators or a remote exchange from which multiplex signals are forwarded and terminated in the present exchange by regeneration and synchronizing units which convert the time scale of the remote exchange to that of the present apparatus. Single sources are allocated a number in this channel and contain synchronization information. Sources 100-0 &c. are connected to receive line units 102-0 giving an input to the second order multiplexer 105 output from which is connected via a central highway 106 to the demultiplexer 107 and via intermediate highways 108-0 &c. to send line units 103-0. Each of the main time intervals is divided into m equal sub-time intervals so that one frame = 32m. Clock pulses cs from generator 109 applied to a modulo-m pulse counter 110 having a cycle of m pulses has its output presented in parallel to comparison units 125 also having an input from an internal address store 123 and on identity reverses a switch 116 during a sub-interval to sample incoming signals from 100-0 thus reducing the duration of each character from one main time interval to one sub-time interval. During the remainder of the time the output of a delay unit 115 is connected back to its input thus providing circulation. Delay unit 115 forms a cyclic store having a duration of one main time interval and m store locations in each of which a character may be stored; when characters are admitted from 100-0 the previous character in the relevant store location is automatically erased. All characters originating from a single channel are stored in the same location but an arbitrary store location can be associated with a single channel. Second order multiplexer 105 acts as a matrix between input and output, connection points being controlled by a cyclic address store 126 of one frame interval via decoder 127. The locations of store 126 are numbered according to the number of main time intervals x and subintervals y where xy is the cross point. De-multiplexer 107 and decoder 129 controlled by cyclic store 128 numbers in store 128 identifying a send line unit 103-0 &c. are connected via highway 106 and operates inversely to multiplexer 105, comprising character registers 130, 131 switched alternately by 132 controlled by output from counter 113 so that one register receives from highway 108-0 at the same time that the other transmits to a receiver 101-0.