Patent GB-1314180-A (GB)
Title: Electrical data transmission systems
IPC: H04J3/24
Filed: 1969-11-21
Abstract: 1314180 Multiplex pulse code signalling, telephone systems; digital transmission; stations connected to a common line; transistor pulse circuits PLESSEY TELECOMMUNICATIONS RESEARCH Ltd 1 Jan 1971 [21 Nov 1969] 57198/69 Headings H3T H4K H4L and H4P A common transmission bus is seized on a demand assignment basis by signal stations with messages to transmit, the number of stations injecting current into a common access bus with resistance to earth providing an indication at each station of the level of demand, each station having a timer of characteristic duration so that concurrent demands are timed out one after the other until just one is left to seize the transmission bus. Access to the common transmission bus may be for one message at a time with all other stations locked out until the transmitting station has finished. Alternatively, a station may be given access to look for a spare time interval occurring in repetitive transmission frames, the station compiling packages of data for transmission in each appearance of the time interval until such time as the message is completed. The packages of data may comprise 20 bits of delta-modulation with heading, address, and end of packet codes, where the station transmits speech. Pulse code modulation may be employed. With teleprinter terminals each packet may comprise a separate character, access to the common transmission bus being made afresh for each character. Other types of station, referred to as competing for the transmission bus, are data terminals and computers. Accessing arrangements.-As shown in Fig. 2 each station has a control unit 11, a circuit 15 for injecting current on the common access bus AL, and a circuit 17 for detecting the voltage level existing on the bus so as to discriminate between fewer than two stations injecting current on the bus and two or more stations injecting. If, when the presence of a message for transmission is signalled at terminal 10, the level detector 17 indicators fewer than two stations on the bus AL, the control unit causes circuit 15 to inject. If, after the station injects, detector 17 still indicates that fewer than two stations are injecting, it is concluded that the transmission bus is free and transmission is started. When transmission ends, the injection from 15 is cut-off, or where access is given in time periods of a recurring transmission time frame, injection is cut-off when seizure of a time period has been effected. If, however the signal on terminal 10 indicating a message for transmission, occurs when the detector 17 shows fewer than two stations injecting and, after injection from circuit 15, the detector shows two or more stations injecting, the control circuit starts counter 19 which times out a period characteristic of the station. If, during the count out of 19 the station currently using the transmission bus, or in process of selecting a time period the transmission bus, withdraws, the level detector shows a change to fewer than two and transmission, or selection, can begin. If the count out of 19 is completed before detector 17 shows a change, the station cuts off injection and the cycle of application to the access bus starts again. If, when a signal on terminal 10 indicates a message for transmission, the level detector 17 shows two or more than two stations injecting on bus AL, the station will wait until the level detected falls to fewer than two when control circuit 11 causes circuit 15 to inject and starts counter 19. A number of stations may accumulate in the waiting condition and they may all inject together when the level detectors show a drop to fewer than two. Such a group of concurrent demands is whittled down to just one by the counters 19 which withdraw the stations one by one and put them back into the waiting condition until that station with the counter set to time the longest interval is the only station remaining and, in consequence, the bus level falls to fewer than two. A logical circuit for the control unit is described with reference to, Fig. 4 (not shown), and is such as to introduce a small delay between the decision to inject current on the bus and the actual injection, and to introduce a somewhat longer delay before starting transmission or starting the counter 19. Transistor circuits.-The rise and fall times of pulses injected on the access lens AL are made short by the transistor circuits of Figs. 4a and 4b (not shown). The leading edge of a pulse is speeded up by a capacitor in the collector circuit of a PNP transistor while the trailing edge is sharpened by a capacitor in the base circuit of an NPN transistor The arrangement of Fig 4b is additionally designed to give constant current output. Channel selection for transmission of packages of #-modulated speech samples.-Station apparatus for a speech transmitter is shown in Fig. 6. Speech signals appearing at terminal 50 are #-modulated at 56 and assembled in 12-bit packages on a register 88. Such packages are transferred to store 92 for subsequent transfer to an outgoing shift register 72 along with destination address data and end of package codes. It is said that the buffer store 92 may be dispensed with and the data stream be handled serially throughout. The bits read out of shift register 72 are converted to bipolar signals and are modulated for transmission over the common highway DL. The timing of such transmission is effected by a frame duration timer 70 and a signal sensor 78 acting on a gate 96. The frame timer 70 counts out to indicate that transmission should take place in the next clear gap, and sensor 78 recognizes the gap when it subsequently appears. The transmission frame is determined by a dummy station transmitting a package to mark out the frame interval. It is said that the speech may be pulse code modulated instead of #-modulated. The appearance of speech at terminal 50 is detected at 58 and causes access circuitry to function as described above. When access is obtained the data line sensor 78 is gated to the shift register 72 in order to inspect the data stream. Periods of signal on the transmission bus cause ones to be written into the register; signal-free periods cause noughts to be written. At the inset of a signal-free period the frame timer 70 is started but is reset by the recurrence of signal. If the signal free period is sufficient for register 72 to be filled with noughts, gate 107  opens to initiate seizure of the period with frame timer 70 cycling to indicate where the period occurs in the system frame. On the next appearance of the period the first package loaded into 72 is read out serially on to the common transmission bus. If no package is yet compiled a dummy package of alternate ones and noughts is dispatched. Having seized a time period the access circuit is signalled to free the station from the access bus and allow selection of the next station for a free time period search. Such release is delayed by 10 Á secs. to allow for transmission time over the common transmission bus. If speech is absent for a period in excess of 200 millisecs. the time period is released and any further recurrence of speech requires a fresh search for a free time period. The frame timers at the stations are set to run somewhat faster than the system frame as established by the dummy station. Because the gating of data packages is, in these circumstances, determined by the detection of nosignal by the signal sensor 78 in operating gate 96, package distribution will tend to crowd together against the dummy package on the transmission bus. Final sanction for transmission obtained in this way from signal sensor 78 allows a station to elbow its way into a space smaller than a package to be transmitted since subsequent packages will be delayed until their signal sensors 78 detect the end of the preceding package. It is said that a space about half the length of a package can satisfactorily be seized with no disruption of later packages To indicate congestion an integrating device may be employed to monitor total data traffic and, when this is such as to provide no space for an additional package, access may be barred. Reception of data packages.-Each station examines the data stream on the transmission bus by setting up the packages on a shift register When the address code of a package corresponds with the station address, the message portion of the package is read out to a buffer store, the message portion being aligned for read out in parallel by detection of the end-ofpackage code. This procedure allows a shift register of shorter length than a package to be employed. As the packages arrive at an uneven rate the amount of packaged data waiting to be demodulated is used to control the rate at which it is demodulated to speech. The more data existing in the buffer the faster the rate of demodulating the package bits. Interconnection of common bus systems - About 200 stations can be served by a single common transmission bus. Connections between a common bus of one system and a common bus of another system can be effected by an address indicating the other system, a buffer store holding received inter-system messages until an access circuit gains admission to the other system, Fig. 8b, not shown. A group of intersystem links may be made available on demand as a non-numerical group or groups of such links may constitute a stage of numerical selection. The systems may be linked to incoming and outgoing other-exchange lines.