Patent GB-889431-A (GB)
Title: Electronic computer system
IPC: G06F1/04
Filed: 1958-03-06
Abstract: 889,431. Digital electric-calculating and storage apparatus. SPERRY RAND CORPORATION. March 6, 1958 [March 28, 1957], No. 7197/58. Class 106 (1). An electrical computer having a memory, saturable magnetic core translating elements for carrying out processes on data, and means for generating energizing pulses whose timing and recurrence rate is determined by timing signals derived from the memory, is characterized in that the translating circuits are energized and synchronized entirely by the pulses. General.-The decimal computer described, Figs. 10A-10C, comprises magnetic core circuitry which operates under control of A and B phase " power pulses," Fig. 4B, obtained from pulse generator PP, Fig. 10C, which is controlled by signals from a sprocket track on the magnetic memory drum 35A. The drum comprises also time selection and memory bands, each comprising four tracks in which the bits of binary-coded decimal digits are stored in parallel. The time selection band contains tuning signals, applied via lead 101A to timing circuits, Fig. 10C, and address signals applied via lead 101 to buffers 20 from which the signals may be routed to comparator 17. The read/ write heads 30 for the memory bands are selected by circuits 28 controlled by an address in " C " register 13 which stores the current instruction word. The computer includes also the following one-word magnetic core registers: an accumulating or " A " register 15 associated with adder 18; an " L " register 14 used, e.g. for storing a multiplicand or divisor; an " X " register 16 used, e.g. in conjunction with the " A " register for a double length shift operation; and an " O " register (not shown in Figs. 10A-10C) for input-output buffering. Each of these registers comprises four parallel recirculation channels for storing the separate bits of the coded digits. The signs of the numbers in the A, L and X registers are stored in flip-flop elements 11B, 11C and 11A. During an addition or subtraction operation, the calculation is performed jointly by elements 17 and 18 to which the two numbers are supplied via buffers 19 and 20 from the A register and memory respectively. A complement flip-flop element 21 controlled in accordance with the signs of the numbers determines whether the number from the A register should be effectively supplied in complement form. During a shift operation or a multiplication by repeated addition. a multiplier quotient counter 23 counts down the number of cycles required. This counter operates also, during division by repeated subtraction to produce the quotient digits. A static register 25 stores the command or function portion of an instruction word, the instruction being executed under control of signals from a decoder 26 and encoder 27. The register 25 acts also as a sequence control for multi-cycle instructions, viz. those for shift and arithmetic operations. An overflow flip-flop element 22 causes a branching of the computer programme if the result of an addition or subtraction exceeds one word, or if an improper division occurs. In Figs. 10A-10C, the references 11A-35A indicate the numbers of the drawings in which detailed illustrations of the related elements may be found. The input-output equipment (not shown) may comprise a typewriter; reference is made also to record tape readers and printers. Basic circuits.-The computer circuits consist primarily of magnetic " amplifiers " and " complementers " with associated diode gates and buffers. The amplifier shown in Fig. 2A comprises a core 30 preferably of material exhibiting a substantially rectangular hysteresis characteristic. Normally the positive and negative power pulses a, Fig. 2B, applied from 33 to output winding 31 are used up in driving the core alternatively to its positive and negative remanent condition and no appreciable output is obtained. If, however, a positive input pulse c, Fig. 2B, is applied to input coil 32, this will counteract the effect of the negative power pulse with which it coincides so that the core remains in the positive remanent condition. Thus the next positive power pulse will be presented with a relatively low impedance, thereby producing a positive pulse output b, Fig. 2B, at 35. In the detailed circuit diagrams, such as Fig. 18A, this amplifier is represented as in Fig. 2C, the letter " B " indicating the phase of the applied power pulses (see Fig. 4B). A complementer comprises a similar magnetic core circuit which provides positive output pulses in the absence of input pulses, and is represented as in Fig. 1B. When amplifiers and complementers are serially connected, e.g. in a register chain (see Fig. 50), they are connected alternately to the A and B phase power sources. A group of diodes GB, Fig. 6A, coupled to the input winding 90 of a magnetic amplifier or complementer may act as a coincidence gate for low level input signals (indicated by a " . ") or as a buffer for high level input signals (indicated by a " + "). Networks of gates or buffers forming decoders or encoders may be represented, as in Fig. 7C, each dot indicating a diode connection. Fig. 8A shows a two-state or " flip-flop " circuit in which amplifier 113 and complementer 112 are connected in a loop through gate 115. The flip-flop is set to state #, in which a low level output is obtained from 112 while positive pulses are obtained from associated amplifier 111, by applying a positive input pulse at terminal 117, and is restored to the reverse or # state by a positive pulse at terminal 118. Word code.-A word length comprises 12 pulse periods P 0 -P 11 , Figs. 9A and 9B, in which decimal digits may be represented according to a 4-bit biquinary code. The " space between words " position P 11  always contains " 0 " and, in the case of a number, Fig. 9A, position P 0  contains the sign (" 0 " for positive, " 1 " for negative), and the numerical digits are contained in positions P 1 -P 10 , the number . represented in Fig. 9A being +0.0876543210. In an instruction, Fig. 9B, P 0  always contains " 0," P 9  and P 10  contain the command or function-representing portion, and P 5 -P 8  and P 1 -P 4  contain portions m end c which normally represent the memory address of an operand and of the next instruction respectively. Certain alphabetical or typewriter symbols may also be represented by the 4-bit code. Magnetic drum memory.-Fig. 35B illustrates a portion of the sprocket track 14 the time selection band 12 and one of the memory bands 13A on the surface of the drum. Each memory band contains 200 words whose sequential time addresses 000-199 are recorded in positions P 1 -P 3  of the time selection words, the timing signals 0 1  " sentinels " being recorded in positions P 8 . The drum comprises 20 " slow " memory bands, Fig. 10C, each with a single read-write head assembly and 5 " fast " memory bands each having four head assemblies, such as 6-9, spaced 90 degrees apart. A memory word position is selected by a 4-digit address m or c, Fig. 9B, in the C register 13. This address is applied to selection circuits 28, and also via buffers 19 to comparator 17 where it is compared with the time addresses applied via buffers 20. On comparison agreement, time selection flip-flop 12B is set and causes register 25 to produce a signal indicating that reading or writing may commence. Circuits 28 comprise a gating network which sets band selection flip-flops in accordance with the hundreds and thousands address digits, and also performs a binary subtraction between particular bits of the tens and hundreds digits of the address in C and the time address so as to determine, in the case of a fast band, which of the four head assemblies should be selected. The outputs of the flipflops in circuits 28 are applied via decoding switches 29 to centre taps on the head windings in array 30, the ends of the windings being connected through diodes to read-write circuits 31 one set of four (corresponding to the four bit positions) for the slow memory bands and a separate similar set for fast bands. Start-stop and timing circuits.-The basic digit-position-defining timing pulses t 0 -t 11  (see Figs. 9A and 9B and Fig. 35B) are obtained from cycling unit 34, Fig. 10C, comprising a chain of magnetic core circuits along which a pulse is propagated in response to each timing sentinel detected on the time selection band. If a timing sentinel does not occur at the proper time, error detecting circuits produce a stop signal. If circuit 32B receives a stop signal from circuit 33B or elsewhere, it inhibits decoder 26, Fig. 10B, to prevent the execution of further instructions. The computer is started by a pulse from a start bar applied to synchronizing start circuits which are controlled by a signal generated every other word period by circuit 33A. Operating sequence.-Each new instruction word is selected from the memory 35A, Fig. 10C, in accordance with an address (normally c) in the C register. When the word is found, the time selection flip-flop 12B is set. A " B " step then occurs in which the new instruction word is passed to the C register 13, Fig. 10A, the command portion, Fig. 9B, being passed also to static register 25, Fig. 10B. If portion m of this word represents a memory address, register 25 will set CT flip-flop 12A to cause this portion to be read out from the C register to circuits 19 and 28, and execution of the instruction is delayed, until this address has been found. After the instruction nas been executed, register 25 is cleared and the next instruction is selected. For transfer-of-control and input-output instructions, the next instruction may be obtained from memory address m instead of c. Instructions.-The commands which may be set up in the static register 25 are of the following types: (1) transfer between one register and another or between a register and the memory 35A; (2) logical operations; (3) conditional trans