Patent GB-1382937-A (GB)
Title: Symbol generating apparatus
IPC: G09G1/10
Filed: 1973-02-23
Abstract: 1382937 Cathode-ray tube displays HUGHES AIRCRAFT CO 23 Feb 1973 [23 Feb 1972] 9109/73 Heading H4T The Specification describes a cathode-ray tube symbol generating and display system in which the symbols are formed from line segments having selected ones of a finite number of predetermined directions the size of the symbols being varied by producing the segments in a selected number of unit lengths. Fig. 1, shows the predetermined directions, together with the binary digital codes which specify such directions and Fig. 2, shows a symbol 16, e.g. an aircraft or target in flight, formed by the sequential selection of certain directions during equal time periods commencing at S 0 , S 1  ... S 7 , S 0 , S 1 , S 2 , the beam of the tube being unblanked except during second occurrence of the periods commencing at S 0  and S 1 . Each symbol is defined by one or more 32-bit words and Fig. 3 shows two such words 20, 22 which define the eleven segments forming the symbol 16, the first three most significant bits of each 4-bit segment defining the direction and the fourth bit specifying beam unblank by a "1" and beam blank by an "0". Additionally, each symbol word or words is associated with an X-Y word 28 comprising 10 bits X 0  ... X 9  and 10 bits Y 0  ... Y 9  which specify the start X-Y coordinates (referenced to an zero or or origin point 12 or 32) together with 2 bits C 1 , C 2  which specify the length of the segments. The storage format may be such that all bit positions are occupied. In the general operation of the system, data from any suitable source, as shown in Fig. 4a, from a computer 40, is supplied following a Word Request initiated by a push-button PB190, to a symbol register 52 and to an X-Y word register 54 and a symbol start signal from a flip-flop 214 is supplied to a symbol generator clock 60 (Fig. 4C). The output of the latter is supplied to a size control circuit 62 which also receives the C 1 , C 2  bits (derived by strobing register 54) to produce via a 3 bit up counter 80 and a decode circuit 86, a series of eight segment pulses S 0  ... S 7  having count lengths of 2, 4, 8 or 16 (Fig. 9, not shown) determined by the bit valve of C 1 , C 2 . The segment pulses are then associated with the corresponding segment codes M 0  to M 3 , ... M 28  to M 31  (derived by strobing register 52) in a NAND gate circuit 90 (Fig. 4b) to produce the indicated outputs which are then combined as shown via NAND gates 108 to 110 to produce outputs B 0 , B 1  and B 2  indicative, respectively, of the first three most significant bits in each segment code and via NAND gate 111 to produce an output B 3  indicative of the least significant bit in each segment code. The bits B 0 , B 1  and B 2  are then decoded in circuit 118 to provide UP, DOWN and STOP signals for X and Y counters 68, 70 (Fig. 4C) and the B 3  bits are supplied to a beam blanking circuit 182. The counters 68, 70 then operate to produce counts having magnitudes and directions determined, respectively, by the lengths of the segment pulses S 0  to S 7  and by the bits B 0 , B 1  and B 2  and these counts, after conversion to analogue form in D/A converters 122, 124 are supplied via deflection amplifiers 140, 142 to the deflection plates or coils of the display tube 160, the start position being determined by the X-Y word derived from register 54, converted to analogue form in D/A converters 150, 152 and combined with the symbol deflection quantities in amplifier 140, 142. Details of a typical stage that may be used in the UP/DOWN counter are given with reference to Figs. (not shown), and details of the decoder 118 and of the size control circuit 62 are described with reference to Figs. 6 and 7 (neither shown).