Patent GB-1292772-A (GB)
Title: Code conversion apparatus
Inventor: RAVIV JOSEF
IPC: H03M7/30
Filed: 1971-05-28
Abstract: 1292772 Code conversion INTERNATIONAL BUSINESS MACHINES.CORP 28 May 1971 [10 Aug 1970 8 Sept 1970] 17819/71 Heading G4C Variable-length codes and corresponding fixed-length codes are held in a store which may be accessed in response to a given variablelength code and fixed length code to obtain the corresponding fixed-length code and variablelength code respectively. The store may be an associative array each word location of which contains corresponding variable- and fixedlength code pair and a length count indicating the number of significant bits in the V-L code. Associative memory, Fig. 2.-Each cell includes a FF22 storing a binary data bit and a FF24 which is set at 1 if the data bit is significant and set at 0 to represent a "don't care" state, the cells of each word being set by a common word select line 32, and 1, 0 and "don't care" lines 26, 28, 30. Associative interrogation pulses are supplied on pairs oflines 44, 46 so that, for a cell storing a significant bit, a mismatch output is obtained from gate 40 or 42 when the stored bit in FF22 does not correspond to the interrogate bit on lines 44, 46 to set a word match indicator (MI) to the 0 state. A read pulse on line 66 is routed by the MI remaining in the 1 state and indicative of a matching word to gate out all bits of the matching word (VL, FL and length count fields) on to lines 74, 76. Encoding.-Parallel-bit fixed-length (ID) code to serial-bit variable length (VL) code. The number of ID bytes to be encoded is entered in byte counter 80, Fig. 3B, and clock E1 gates the first of these ID bytes into argument register 100 and resets the match indicators of associative memory AM to the "one" state. Clock E2 reads out argument register 100 on to the associate lines (44, 46) of the ID field in AM. Clock E3 pulses read line 66 to read out the matching word (all three fields) into data register 120, and decrements byte counter 80. Clock E4 gates out the right-hand bit of the V-L field to the output device and clock E5 shifts register 120 one place to the right and decrements the length field counter section of register 120. Clock E6 tests the state of the length counter at gate 138, Fig. 3B, to cause return to E4 followed by read out of the next bit from register 120 as before, until the length counter reaches 0, when a return to E1 made to repeat the process for the next ID byte to be encoded. When all bytes have been encoded, counter 80 reaches 0 and an END signal is produced at clock E6 time. Decoding serial-bit V-L code into parallelbit ID code. Byte counter 80 is loaded with the number of codes to be decoded and clock D1 resets the length counter section of register 120 to all zeros, representing 16-the maximum word length. Clock D2 gates the first V-L code bit to argument register 178 and decrements the length counter. Clock D3 tests the state of the length counter at gate 202, Fig. 3B, and D4 shifts register 178 one place to the right and causes return to D2 to enter the next V-L code bit in register 178 until, when all 16 bits of the V-L field have been entered, the length counter is again at all zeros and D3 causes a step to D5 to reset the match indicators to the 1 state. Clock D6 reads out the argument register 178 on to the associate lines (44, 46) of the V-L field in AM and clock D7 reads out the matching word (all three fields) into data register 120 and decrements the byte counter 80. Clock D8 gates out the ID code from register 120 and clock D9 shifts register 178 one place to the right and decrements the length counter. Clock D10 gates in the first bit of the next V-L code to be decoded into register 178 and clock D11 tests the state of the length counter -at gate 248, Fig. 3B. Operation under clocks D9-D11 is repeated until the length counter is at 0 when D11 causes a return to D5 to decode the next V-L code now fully in register 178 or to produce an END signal. Copy mode.-Some data compaction may be sacrificed to save on the size of the memory AM by arranging the system to handle only the most frequently occurring V-L codes. Thus, AM may have only 150 say locations for matched V-L, ID pairs plus an additional location for a copy code (in the V-L field) and an ID code different to all the others. Since only the most frequent (shorter) V-L codes are stored, a smaller number of bits per word is also required in AM. In an encoding operation when no ID match is found, the copy code is read out from register 120 followed by the ID code from the argument register 100. In a decoding operation incoming codes which may include copy plus ID codes are entered in argument register 178, and if a copy code is present it is erased by shifting register 178 and the ID code which is then at the right-hand end of this register is read out in parallel.