Patent GB-1167566-A (GB)
Title: Method and Apparatus for Firing Inverters
IPC: H02M7/527
Filed: 1966-12-19
Abstract: 1,167,566. Inverters; control of A.C. motors. WESTINGHOUSE ELECTRIC CORP. 19 Dec., 1966 [13 Jan., 1966], No. 56729/66. Headings H2F and H2J. [Also in Division H3] An inverter provides two pulses to the output circuit during each half-cycle of each phase of the output voltage, the leading edge of the pulses in the half-cycle being spaced by 60 degrees and the width of the pulses being variable. The 60 degree spacing reduces the third harmonic, whereby greater efficiency in the operation of a variable-speed single- or threephase induction motor may be obtained (see Figs. 3, 4, 15 and 16, not shown). In the Fig. 7 inverter, A, B, A<SP>1</SP>, B<SP>1</SP>, are the main inverter thyristors. The sequence of operation of the connection between the D.C. supply line 12 and 14 and the load terminals 18, 22 for the positive half-cycle is as follows:- A and B<SP>1</SP> on to energize the load (the freewheeling thyristor D also being on); A and B<SP>1</SP> extinguished by means not shown and E on to carry free-wheeling current; A and B<SP>1</SP> again on, E<SP>1</SP> on to extinguish E, and finally A and B<SP>1</SP> off and E on. The negative half-cycle continues similarly with B and A<SP>1</SP> becoming conductive twice. The power supplied to the load may be varied by adjusting the on periods of the main thyristors. An alternative sequence (Fig. 9, not shown) allows the main thyristors to conduct for a longer period, the D.C. power being connected to the load only when the conducting periods of the upper and lower thyristors (e.g. A and B<SP>1</SP>) overlap. A conventional three-phase inverter (Fig. 11, not shown) may also be operated to provide two pulses to each output terminal during each half-cycle, the conduction sequence again being of the type in which current flows to the load only when the conduction periods of the thyristors overlap (Figs. 17, 18 and 19, hot shown), Fig. 19 also illustrating the main and free-wheeling currents for different power factor loads. Fig. 15 (not shown) illustrates similar curves for prior circuits feeding a motor load. Fig. 21 shows another three-phase inverter in which F and G are commutating thyristors, single-phase operation being possible by omitting certain components. Fig. 28 shows a pushpull, parallel type inverter similar to that described in Specification 988,009 in which 516 and 518 are the main thyristors 522 and 524 the commutating thyristors and 548 is a network which short-circuits the windings at appropriate times. The frequency and pulse width of the inverters described may be varied. Control circuit for Fig. 1.-This circuit (Fig. 20) comprises a variable frequency clock generator 124 which provides turn-on and variably delayed turn-off clock pulses, a gating circuit 126 (and Fig. 24, not shown) which under the control of these pulses high frequency burst firing pulse circuits 106 to 120 for the respective thyristors and a bi-stable circuit 128 (and Fig. 26, not shown) controlled by the clock pulses to determine which of the commutating thyristors F and G is operative. A simplified two-phase version of this control circuit is described with reference to Fig. 27 (not shown). The clock pulse generator (Fig. 25, not shown) comprises a variable frequency uni-junction transistor oscillator (368) supplying turn-on pulses at 218 and indirectly at 216, turn-off pulses delayed by an amount dependent upon the resistance of a charging resistor (390) of a uni-junction transistor delayed pulse generator. The gating circuit (Fig. 24, not shown) comprises two groups of three transistors controlling diode gates, one transistor in each group being non-conducting and the non-conducting state being stepped around the group. The firing circuits for the thyristors, Fig. 23, comprise an input line 134, 136 for high-frequency (20 kc/s.) pulses derived from a multivibrator (Fig. 20, not shown). Transistor 190 is normally conducting so that diodes 186 and 188 conduct allowing these pulses to pass through a transformer 180 to provide a reverse bias to the gate-cathode connection 130, 132. When a clock pulse at 206 coincides with a gating pulse at 148 transistor 166 conducts and turns 190 off. 190 terminates the reverse bias supply and 166 allows the 20 kc/s. pulses to pass through transformer 146 to provide a firing signal for the respective thyristor. Feedback may be provided between terminals 154 and 148 to maintain the state of a circuit until the control pulse renders 166 non-conducting again. Control circuit for Fig. 28.-This circuit (Figs. 29 and 30, not shown) is similar to that described in Specification 988,009, the thyristors being fired by a saturable transformer under the control of a magnetic amplifier which varies the conduction angle. It differs from the prior circuit in that it provides a firing sequence in accordance with the invention and also includes a diode bridge network (554) which shortcircuits the output winding 506 of Fig. 28 whenever all the thyristors are off. The frequency of the output voltage and thus the speed of the motor is varied by varying the speed of a D.C. motor driving an A.C. generator controlling the firing networks.