Patent RU-94030340-A (RU)
Inventor: DUKHNICH E I
IPC: G06F17/16
Filed: 1994-08-23
Abstract: FIELD: computer engineering. SUBSTANCE: device has m registers P... P, (2m-1) adders-subtracters S... S, m sign decoders α... α, (m-1) XOR gates XR... XR, (m+3) multiplexers MS... MS, three shift registers 1, 4, 7, sign alternation unit 2, unit 3 for multiplication by one of n constants, m operand inputs X... X, m inputs Z... Zfor analysis of signs of operands, m result outputs Y... Y, loop index input 5, mode setting input 6, input 8 for setting weight of processed bit. Inputs of registers P... Pserve as operand inputs X... X, while their outputs are connected to first inputs of output adders-subtracters S... S, respectively. Inputs of sign decoders α... αserve as inputs Z... Zfor analysis of operand signs. Outputs of sign decoders α... αare connected to second inputs of XOR gates XR... XR, respectively. First inputs of XOR gates are connected to output of sign decoder α, their outputs are connected to first inputs of multiplexers MS... MSrespectively. Second inputs of these multiplexers are connected to outputs of sign decoders α... αrespectively. Loop index input 5 is connected to control inputs of shift registers 1, 4 ,7 and multiplication unit 3. Output of register Pis connected to first input of adder-subtracter Sthrough shift register 1 and sign alternation unit 2. Second input of first adder-subtracter is connected to output of register P, its control input is connected to output of multiplexer MSand output is connected to first input of adder-subtracter S. Adders-subtracters S... Sare connected to serial circuit. First input of j-th element in this circuit is connected to output of (j-1)-th element, its second input is connected to output of (j+1)-th register, its control input is connected to output of multiplexer MS, its output is connected to first input of (j+1)-th element. Output of adder-subtracter Sis connected to input of multiplication unit 3, which output is connected to second input of adder-subtracter Sthrough shift register 4. In addition output of multiplication unit 3 is connected to first input of multiplexer MS. Output of adder-subtracter Sis connected to second input of multiplexer MS, which first input is connected to output of first register and output is connected to first device output Y, second input of multiplexer MSis connected to output of shift register Pthrough shift register 7, its output is connected to first input of multiplexer MSand to second inputs of adders-subtracters S... S. Second input of multiplexer MSis connected to input 8 for setting weight of processed bit. Its output is connected to second input of adder-subtracter S. Control inputs of adders-subtracters S...Sare connected to inputs of multiplexers MS...MSrespectively. Control input of adder-subtracter Sis connected to output of multiplexer MS, which first input is connected to output of multiplexer MS, its second input is connected to output of multiplexer MS. Control inputs of all multiplexers are connected to mode setting input 6. Outputs of adders-subtracters S... Sare connected to device outputs Y... Yrespectively. Output of sign decoder αis connected to control input of sign alternation unit 2 and to control input of adder- subtracter S. Novel feature of device is conversion of components of vector in m-dimensional space as single macro operation which takes approximately n operations of additions, where n is bit length of operands. This is achieved by either orthogonal reflection transform or by Gauss (or Gauss-Jordan) transform. Device provides possibility to perform delta-transform of matrix, reduction of matrix to two-diagonal form (by reflection transform), and to diagonal form (by Gauss-Jordan transform), to solve systems of linear algebraic equations, to find matrix latent roots, to perform matrix reversal and other operations of linear algebra. EFFECT: increased field of application. 1 dwg