Patent GB-819346-A (GB)
Title: Improvements in or relating to data storage apparatus
Inventor: BOOTH ANDREW DONALD
IPC: G06F3/00
Filed: 1955-01-11
Abstract: 819,346. Electric digital-data-storage apparatus; electric counting apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd., [formerly BRITISH TABULATING MACHINE CO. Ltd.]. Jan. 10, 1956 [Jan. 11, 1955], No. 826/55. Class 106 (1). Data-storage.-A data storage apparatus has a cyclic access storage device, such as a mercury delay line (store 1, Fig. 1) having a plurality of data storage locations, means for reading out data from a selected one, or a selected group of these locations in each of a number of cycles said means including a gate 11 which is opened by pulses from a control circuit so that the data in a different location or a different group of locations is read out in each cycle. The data in mercury delay line store 1 is continuously circulated through gates 4 and 5. If the store is able to hold m words each having n digits the total capacity is mn digits. If the time between digit-representing pulses is t microseconds the data in the store circulates in a time of mnt microseconds. To enable the data to be read out at a lower frequency than this, the gate 11 is opened once during each cycle so that only one digit is read out in each cycle. The control circuit consists of another mercury delay line, store 2, the contents of which circulate through gate 9 and amplifiers 7 and 8. The capacity of store 2 is arranged to be mn + 1, that is a capacity of 1 digit more than store 1. To read out one store location in each cycle, one pulse is put into the store 2 which circulates at a frequency of (mn + 1)t. This signal is applied through gate 14 to open gate 11 so that data is read out from locations in store 1 spaced mn + 1 locations apart. This means that successive digits are read out from the store 1 in turn, one in each cycle and entering into shifting register 12. If more than one pulse is put into store 2, say four consecutive pulses, and the capacity of store 2 is increased to mn + 4, then a group of four adjacent digits is read out in each cycle. The data in register 12 is shifted one stage by each signal through gate 14 so that digits from store 1 are received in adjacent stages in the register. Data can be read into store 1 on line 18 through gate 13 which is opened by pulses from gate 14. In the form of Fig. 2 the data is recorded on a rotating drum 20 and is read out or in by a read-head 22. Reading out is through a gate 25 corresponding to gate 11 of Fig. 1 which is opened say once during each revolution of the drum 20. The gate 25 is controlled from a counter 26 which is of such a type that it gives an output signal after a predetermined number of input pulses. These come from a timing track on the drum read by head 21. The value of the predetermined number is set by loading register 28 with this number through line 29. The counter consists of a series of trigger stages as described later each being associated through a coincidence gate 27 with the corresponding stage of register 28. When the counter has received a number of pulses equal to that entered in the register the corresponding gate 27 sends a signal through gate 30 to open gate 25. If nine digits are recorded on the drum and the value " nine " is put in the register the counter will give an output pulse every ten pulses and this causes succeeding digits from the drum to be read out. The input to the drum is through gates 34, 35 which are opened at the lower frequency by counter signals sent through gate 33. Counting apparatus.-The control circuit in the form of Fig. 2 consists of a counter unit 26, a coincidence circuit 27 and a register 28. These are shown in detail in Fig. 3. The counter 26 comprises a series of double triodes V2, V4, V6, &c., connected as triggers. The first trigger is connected to line 50 (carrying the clock pulses from the drum 20) through double diode V1. The stages are coupled by connections from the right-hand anode of the double triode through double diodes V3, V5, &c., to the grids of the double triodes. The double diodes pass only negative pulses so that the trigger of one stage is only triggered by the change from left side conducting to right side conducting of the trigger in the previous stage. The change from right to left produces a positive pulse which does not pass the diode. The left-hand grids of V2, V4, V6, &c., are connected to a resetting line 52. A negative voltage on this line zeroises the counter. The register (28, Fig. 2) comprises a series of trigger valves V7, V8, V9 connected in a generally similar way to the double triodes of the counter. The cathodes of each inter stage double diode V10 are connected together through two capacitors 53 and the central point is connected to a line 55 on which negative shifting pulses are applied. Input to the register is by way of line 29 connected to one cathode of a double diode V 11. The other cathode is connected to a bias line 57 held at a positive voltage. Shift pulses from line 55 are also applied to valve V 11. Shift pulses are applied to all stages simultaneously so that data represented by the setting of one stage is transferred to the following state. Data entered in the first stage is thereby shifted along the register. Associated with the first stages of the register and counter is a coincidence detecting circuit comprising a double triode V12 having anodes connected to line 44 and cathodes through resistor 61 to earth. When V2 and V7 are both in the same state (both representing " 1 " or " 0 ") each grid of V12 is connected to one anode at high voltage and another at low voltage. When V2 and V7 are opposite one or the other grid of V12 is connected to anodes which are both at a high voltage. All the other stages of the register and counter are connected by similar coincidence detecting circuits, having valves V13, V14, &c. A further double triode V15 is connected in a manner similar to V12, V13, &c., except that the right-hand grid is connected to the junction of resistors 64, 65 forming a potential divider between lines 44 and 47 together with a resistor 81. The grid is thereby held at about 110 volts. The voltage of both grids of V12 is about 75 volts on coincidence and the voltage of one grid is 110 volts on non- coincidence and consequently the common cathode line is held at about 110 volts while any of valves V12, V13, &c., are conducting. Negative clock pulses (about 30 volts) are applied to the right-hand grid of V15. When coincidence occurs the cathode potential is still held at 110 volts by conduction through V15 but the clock pulse lowers the grid voltage and the cathode voltage follows it until it falls below the voltage of the left-hand grid. This is held at about 80 volts by connection with resistors 81 and 65. At this point the left-hand side of valve V15 conducts and the current flows through the primary winding 83 of a pulse transformer. A secondary winding 84 applies the resetting pulse to the counter on line 52. A secondary winding 85 provides a negative pulse to the gates 30 and 33 (Fig. 2) via line 86. The output pulses from V15 occur one clock pulse time after coincidence has been achieved and consequently the value entered in the register is one less than the effective counter capacity required. The recording head is supplied through a transformer having a centre-tapped primary consisting of two windings. A binary " 1 " is recorded by energizing one winding and a binary " 0 " by energizing the other winding, the direction of current in these two windings being opposite.