Patent TW-201721649-A (TW)
Title: Static random access memory comprising a memory array, a plurality of control circuits, a plurality of pre-charge circuits, a standby start circuit, a plurality of word line voltage level conversion circuits and a plurality of high-voltage level control circuits
Inventor: SHIAU MING-CHUEN
IPC: G11C11/413
Filed: 2015-12-10
Abstract: A static random access memory comprises a memory array, a plurality of control circuits (2), a plurality of pre-charge circuits (3), a standby start circuit (4), a plurality of word line voltage level conversion circuits (5) and a plurality of high-voltage level control circuits (6). The memory array is composed of a plurality of rows of memory cells and a plurality of columns of memory cells, and each row of memory cells is provided with a control circuit and a word line voltage level conversion circuit (5), and each memory cell (1) comprises a first inverter (consisting of a first PMOS transistor P11 and a first NMOS transistor N11), a second inverter (consisting of a second PMOS transistor P12 and a second NMOS transistor N12) and an access transistor (consisting of a third NMOS transistor N13). Each control unit (2) is connected to the source of the first NMOS transistor (N11) and the source of the second NMOS transistor (N12) of each memory cell in the corresponding row memory cell, for controlling a source voltage of the first NMOS transistor (N11) and a source voltage of the second NMOS transistor (N12) in response to different modes of operation. In a first stage of a read mode, the source of the first NMOS transistor (N11) near the bit line (BL) is changed from the original ground voltage to less than the ground voltage, and at this time, a smaller ratio of channel length to channel width can be configured for the first NMOS transistor (N11) and the second NMOS transistor (N12) to complete the read operation, without hindering the reading operation of the second NMOS transistor (N12), which is away from the bit line (BL), due to the instantaneous conduction when reading the logic 0. And, in a second stage of the read mode, the source of the first NMOS transistor (N11) is set from a level lower than the ground voltage back to the ground voltage so as to reduce unnecessary power consumption. In a write-in mode, the source voltage of the first NMOS transistor (N11) near the bit line (BL) is maintained at the original ground voltage, and because a smaller ratio of channel length to channel width is configured for the first NMOS transistor (N11) and the second NMOS transistor (N12), it is possible to effectively avoid the difficult problem of writing a logic 1 in the single-port SRAM of a single bit line in the prior art. In a standby mode, the leakage current can be effectively reduced, and in a hold mold, the original electrical characteristics are maintained. Furthermore, by the design of the standby start circuit (4), the single-port SRAM can be rapidly brought into the standby mode, and thus the standby performance of the single-port SRAM is effectively improved. In addition, with the design of the plurality of word line voltage level conversion circuits (5) and the plurality of high voltage level control circuits (6), the on-resistance of the third NMOS transistor (N13) is increased and the on-resistance of the first NMOS transistor (N11) is reduced in the read mode to effectively reduce the semi-selected cell interference at the time of reading.