Patent GB-1225253-A (GB)
IPC: G06F9/28
Filed: 1967-09-12
Abstract: 1,225,253. Data processor. PLESSEY CO. Ltd. 12 Sept., 1968 [12 Sept., 1967], No. 41470/67. Heading G4A. A digital electric stored programme data processing device of the type in which each programme step is controlled by an instruction word consisting of an instruction code, defining the operation to be performed, and at least one address code, defining the data or the address of the data to be used in the required operation and comprising a control module and a plurality of functional modules is characterized in that each module includes a control signal store used to provide control signals to activate the data manipulative equipment provided within the associated module, the control signal stores in the functional modules being addressed by further control signals generated by the control signal store in the control module which is addressed by the instruction code of each instruction word in a programme. The data processor is divided into four modules, Control (CM), Store Access (SAM), Processor (PM) and Input/Output (IOM), each module having a standard interface divided into sections. Word length data inputs and outputs, coded command inputs, conditional control inputs and outputs and completion signal outputs. Command signals to modules PM, SAM, IOM are amplified and applied to micro-command diode gates, which have one or two further inputs. One of these is a timing input, the other being a conditional input. A command signal first triggers a synchronous or asynchronous timing slot generator in the module, the pulses from which select the required gates in the correct sequence in accordance with the conditional sequence. In the control module the gates accept a main command and convert it to a sequence of commands to be applied to the appropriate processors in the other modules. Two controllers are used, the first driven by the matrix of main command gates, the second by condition generators, and dealing with normal operations and forced operations respectively, the latter including keyboard operations priority interrupt and indirect address. Several modules can operate simultaneously. The processor module performs the arithmetic and logic operations under the control of the synchronous timing generator STSGP and the control logic. Six registers hold programme operands, an address modifier, an operand used during iterative operations, or a mask, a page code defining a particular section of the memory, the base page code of the programme data area, and an operand respectively. The result of an arithmetic operation is held in a Results register (RES). An instruction word has an address part (bits 1-18) a function code (bits 9-14) and two tags M (bit 15) and I (bit 16). The actual address is formed by adding bits 1-18 to the current page code or the base page code, the store being divided into sections called pages. The selection is determined by the state of the I bit. Each instruction word obtained from memory contains the address or the modification instructions to the address of the next word. The Specification includes tables of the various micro-commands produced by the stores in the performance of such operations as store to register transfer, literal transfer, addition and register to store transfer.