Patent GB-959767-A (GB)
Title: Improvements relating to timing waveforms in electronic telephone exchange apparatusand the like
Inventor: DAWSON JOHN
IPC: H04Q11/04
Filed: 1959-10-19
Abstract: 959,767. Pulse shaping and switching circuits. ERICSSON TELEPHONES Ltd. Oct. 19, 1960 [Sept. 10, 1959], No. 30978/59. Heading H3P Apparatus for handling time division multiplex data, in which the data is stored in recirculating delay lines, the inputs and outputs of which are controlled by gates, such as 23, Fig. 9, comprises an asynchronous generator 21 which produces timing pulses, the rise time of which exceed the width of a time slot, and a synchronous generator 24 producing inhibit pulses, the trailing edges of which fall between stroke pulses pertaining to successive time slots and prevent the timing pulses from opening the gates until they attain a predetermined amplitude. The timing pulses are fed to the required gates by a control 22. Control pulses R, Fig. 6, are fed to a bi-stable circuit 10 changing its state to produce a first output 13 and a second output fed to AND-gate 12. Arrival of a pulse from the recirculating 20 micro second delay line 15 opens gate 12 to trigger monostable circuit 14, the output of which is fed to AND-gate 16 to which is also connected a 15 microsecond tap on the delay line. The output 17 from this gate is applied back to bi-stable circuit 10 to restore it and terminate the inhibit pulse 13. The monostable circuit 14 could be replaced by a second bi-stable circuit. In Fig. 7 the bi-stable circuit comprises valves V11, V12 with the cathode follower V16 producing the inhibit pulse O/P. Input pulses applied to terminal 11 switch the circuit to apply pulses to the grid of V10b which together with V10a form the AND-gate, the second input being applied to the grid of valve V10a. The output is taken from the common cathode and fed to the monostable circuit . V13(a), V13(b), the output from which is fed as one input to AND-gate V9(a), V9(b) which resets the bi-stable set. The circuit associated with the recirculating delay line 15 has a pulse initiating circuit comprising valves V1, V2, V3, V4, Fig. 8, which drive the delay line and two pulse amplifying circuits comprising valves V5, V6 and V7, V8 connected to the first and second outputs respectively which give 15 and 20 microseconds delay. Pulses are initiated by applying a strobe pulse SF to diode X1 of an AND-gate comprising diodes X1, X2, X3. This pulse applies a positive potential to the grid of valve V2 making the valve conduct heavily to charge C1 negatively. A second strobe pulse SB discharges C1 producing a sharp negative pulse which is fed through valves V3, V4 and applied to the I/P of the delay line. The pulse is also applied to a second capacitor C2 which reduces the cathode potential of V1b such that diode X3 prevents the gate opening on the next strobe pulse SF. In an alternative Inhibit Generator, Fig. 12, pulses R are fed to a bi-stable circuit V21, V22 and also to the Inhibit input of an INHIBIT- gate V23a. The bi-stable circuit is thus triggared from its datum state to produce an inhibit pulse on output 29. Strobe pulses S3 occurring 0.9 micro-seconds before strobe pulses SF are applied via the gate V23a to reset tho bi-stable circuit V21, V22, and terminate the inhibit pulse. Resetting is delayed until the timing waveform also initiated by R, has reached sufficient amplitude by the application of pulse R to inhibit gate 28. Before application to gate 23a, the pulses R are applied to a pulse-lengthening circuit comprising R26, X26, C22. The output 29 is obtained from the bi-stable circuit via a transformer T1 in an output stage V25. The transformer has a tertiary winding coupled to a valve V24b which ceases to conduct if the pulses fail, causing neon N1 to flash. Specification 841,498 is referred to in the Provisional Specification.