Patent GB-1448588-A (GB)
Title: Field effect transistor integrated circuit structures protective headgear
IPC: H01L27/10
Filed: 1973-12-12
Abstract: 1448588 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 12 Dec 1973 [2 Jan 1973] 57519/73 Heading H1K A semi-conductor data storage (Fig. 1) comprises two memory cells 10 each with PET 12 and storage capacitor 14 in series therewith over electrodes 22; each FET having gate electrode 16 and current flow electrodes 18, 20. The remaining capacitor electrodes are formed by field shields 24 in the regions 26 coextensive with electrodes 22. Bit sense lines 28 connect the current flow electrodes 18 to bit driver sense amplifier 30 while gates 16 are connected over word line 32 to word driver 34 and field shield 24 biased by battery 38 which is connected to the FET substrates over lines 36. In operation, information is stored in cells 10 by presence or absence of charge on capacitors 14, and to read in coincident pulses are sent by word driver 34 over line 32 and by bit driver 30 over line 28. Current flow from pulse on line 28 charges capacitor 14 and the FETs turn off on conclusion of pulse on line 32 to trap the charge in the capacitor. To read out, a pulse on line 32 from driver 34 turns on the FETs allowing the capacitor charges to escape as signals on bit lines 28; whereby all memory cells 10 are read out simultaneously and the signals are detected by sense amplifier 30. Decay of stored charge is restored by readout, one word line at a time, from capacitors 14 and writing back the information as described in Specification 1,397,007. A preset pulse on bit line 28 prior to pulsing word line 32 and continuing until the reading conclusion may be substituted for grounding or biasing the bit line. The dual memory cell of Fig. 1 is comprised in an integrated circuit (Fig. 2) wherein a p-Si substrate is diffused with bit line 28, of which portion 18 forms current flow electrodes of the FETs 10 and other diffusions 20, 22 form the remaining flow electrodes and the electrodes of capacitors 14. A composite insulant layer 42 overlying the substrate includes layer 44 of SiO 2  overlain by layer 46 of Si 3 N 4 . The layer 42 is covered by a polysilicon field shield 24 with openings overlying the gaps between electrodes 18, 2 of the FETs and portions 26 of the shield form electrodes of capacitors 14. A second thicker insulant layer 48 overlies the field shield 24 and electrode 26 and overlies the edges of the shield to insulate the polysilicon layer 24 from conductive layer 32 of aluminium, forming the word lines of the storage circuits and the gates of the FETs 12. In fabrication (Specification 1,444,386) diffusions 18, 20, 22 are formed in the Si substrate by deposition of As doped oxide which is etched off except where deposition is required, and an undoped oxide layer is thermally grown over the substrate and doped oxide, during which the dopant is in-diffused into the substrate. The oxide layers are removed, and the composite SiO 2  and Si 3 N 4  layer 42 and the polysilicon layer 24 are deposited, e.g. by chemical vapour deposition the layer 24 being doped with B similarly to the silicon substrate. Openings are then etched in layer 24 between diffusions 18 and 20, 22 to allow insertion of gate electrodes 16. SiO 2  layer 48 is then thermally grown on the polysilicon layer 24 to cover its edges 50. Contact holes are then made to expose the substrate diffusions into which an aluminium line is vacuum evaporated and etched. Alternatively a thin thermal oxide may be grown thermally on a p-Si substrate on which a Si 3 N 4  layer is chemically deposited. A diffusion pattern is then etched through and P or As is in-diffused to produce underlying n-regions forming the current flow electrodes of the FETs and one electrode of the storage capacitors. A thin thermal oxide layer is then overgrown followed by chemical deposition and diffusion of polysilicon, which is etched to define the required field shield pattern. The remaining Si 3 N 4  is etched off and a thermal oxide grown over the polysilicon shield in which contact holes are etched. An Al layer is vacuum deposited and etched to form the word lines and gates. The field shield may be biased relatively to the substrate.