Patent GB-871386-A (GB)
Title: Data processing system
IPC: G06F9/26
Filed: 1959-02-23
Abstract: 871,386. Digital electric-calculating apparatus. NATIONAL CASH REGISTER CO. Feb. 23, 1959 [March 10, 1958], No. 6095/59. Class 106 (1). A programme control device comprises sets of bistable magnetic devices, each set being assigned a computer command and each device of a set controlling a different one of a plurality of step operations of that command, and means whereby the logic operations performed during the one cycle co-operate with the operative magnetic device to determine which magnetic device shall be operative in the next cycle. A transfer and arithmetic diode network 60, Fig. 1, interconnects a computer memory 66, several registers 61, 66a, 66b, 73a, counter 65 and a programme control device 67. The arithmetic network is controlled by the programme device 67 and by counter 65 which provides 24 pulses PO-P23 to each cycle, a cycle beginning at pulse P16. The programme control device 67 has a magnetic core array 150, individual cores of which are switched one at a time by flip-flops N1-N7 and N8-N17 operating through decoding matrices 75, 83. N1-N17 are set at time P16, P17 in the cycle normally under the control of memory 66, but may also be controlled by the state of flip-flops K1, K2 which are themselves dependent on the results of operations in the arithmetic network 60. An address in the L register 66a selects a cell in the 60-plane core-memory 72, the information being read out in periods P20-P23 of the basic operating cycle and set up in the M register 66b. This information is shifted step-by-step into network 60 during periods P0-P9 so that each character (six bits to a character) can be operated on, after which the 60-bit word is transferred in parallel during periods P11-P13 to its originating cell in core memory 72 via inhibit driver 66c. The operation of each core memory plane is as described in Specification 807,700. An S register has a core array 73a and a column select counter D1-D5 used for shifting the position of characters. Programme control device 67, Fig. 3. A row is normally selected by instruction register flipflops N8-N10 and N11-N13 on an octal basis, under the control of memory 66. N11- N13 control instruction matrix 152 to select one of eight row groups. N8-N10 control matrix 153 to select drivers from a group 154, each driver being connected to one drive line in each of the row groups. N8-N13 therefore select one drive line, say 169, passing through a row of cores. Similarly, N1-N6 select one column drive line 168 out of forty. Thus, during periods P16, P17 one core is operated. Change of state sets up one or more related latching circuits 164 so producing an output on related control lines 11c<SP>1</SP> connected to related network units in the arithmetic network 60, Fig. 1. At the end of P17 the operated core is restored by main bias line 170. Sequential selection of columns is normal but in certain conditions, described later, selection is not sequential. Fig. 4 shows the core-array 150 with 80 main rows and 40 columns. Certain of the rows in groups 3, 7 and 8 are selectable by N15, N16 according to command modes. For some computer commands more than 40 basic operating cycles are required. In such a case a row, say 44(0), and a sub-row, say 44(40) may be used and N7 operates so that first one and then the other is effective. Fig. 7 shows the detailed circuit of part of the programme control core array 150 and Fig. 8 shows part of a sequential flow diagram or operations block diagram for illustrating typical sequential step operations within two different commands. Each block, corresponding to the operating core, represents a set of logical equations defining the portions of the arithmetical network 60 to be effective during periods P23-P10 of the cycle. At the same time the next core to be effective is being selected so that the operations are self-sequencing. At block 03-11 the computer may advance normally, may skip to 03-13 or may stick at 03-11, as determined by the results within the arithmetic network 60 and indicated by K1, K2, Fig. 3. At certain points a choice may be made between alternative operations blocks, e.g. 03-16, 03-16-1, by one of the mode flip-flops N14, N17, Fig. 3, controlled by the M register. The first two blocks -00 and -01 are common to all principal.rows and are concerned with looking up the control number and the first word of the command: KT, Fig. 1 (and Fig. 17, not shown), performs copying. KWS (Fig. 18, not shown), controls copying of data into the S register. -