Patent GB-1151041-A (GB)
Title: Data Processing Systems.
IPC: G06F13/18
Filed: 1967-08-16
Abstract: 1,151,041. Data processing systems: data storage systems. INTERNATIONAL BUSINESS MACHINES CORP. 16 Aug., 1967 [12 Sept., 1966 (2)], No. 37601/67. Headings G4A and G4C. A data processing system includes a memory means for executing fetch requests, inhibiting means for inhibiting execution of a fetch request when the memory is busy due to the execution of a fetch request or a storage request, detecting means for detecting a fetch request which relates to the same storage location as does a fetch request already being executed, and means responsive to the detecting means for preventing inhibition of execution of such a fetch request. First embodiment.-Fig. 2 shows a main storage control element MSCE through which various units of the computer communicate with main storage modules 104 and (via a unit PSCE) with peripheral storage and input/output units. Each fetch or store request on a storage address bus SAB is entered into one of the 4 rows of a request stack RS and into the top row of an accept stack AS. The contents of each row in both stacks are tagged valid or invalid, being subsequently ignored if tagged invalid. The contents of the accept stack AS are shifted down by one row each machine cycle (9 machine cycles corresponding to one main storage cycle). A row of the accept stack AS holds the required storage address at 248 (top 5 rows only), the identity of the sink, i.e. the unit and register within it to which fetched data is to be sent at 249 (top 8 rows only) and the designation of the storage module concerned at 250. AS also holds control information. The storage module of a request on SAB is compared with those of requests in process as specified by the fields 250. If the required module is not busy, the request is tagged valid in AS and invalid in RS. If the required module is busy the reverse applies except that if the required address in a fetch request is one of those already the subject of a fetch or store request as determined by comparison at 252 with the fields 248 the request is accepted,i.e. tagged valid in AS and invalid in RS. In this latter case the required data can be obtained direct from the storage data register of the relevant module (into which accessed data from the store is written and from which data is written into the store), since it was placed there in response to the previous request and only one actual storage access is necessary. Requests are entered into RS in the first row tagged invalid. When a given storage module becomes free, requests in RS can be applied to SAB on a first-in-first-out basis. Store requests are buffered in store address registers SAR (holding the required address, an indication of which bytes of the accessed word are to be replaced by the new data, and control information) until the data to be stored has arrived in a corresponding storage data buffer SDB. A fetch request on SAB which relates to the same storage address as a previous store request still unexecuted is delayed until the store request has been executed, being tagged valid in RS and chained to the corresponding entry in SAR, each address on SAB being compared at 254 with those in SAR to detect this situation. A fetch request on SAB for an address already the subject of an unexecuted fetch request in RS is detected by address comparisons at 253 and chained to the latter request so the two will normally be dealt with in immediate succession using only one actual storage access. More than two fetches may be chained in this way. Two successive store requests for the same address are detected by comparison at 254 and chained together in SAR. The priority order of requests from various units of the computer and of the MSCE (RS, SAR) is described. The information shifted out of the lowest row of field 249 of AS passes to the units of the computer to prepare them to receive data they have requested. The busy indicating means for each main storage module comprises three flip-flops the outputs of which fall 4, 2 and 1 machine cycles before the end of the storage cycle respectively. Every nth programme instruction is stored in a given main storage module, where n is the number of modules. Conditional branch.-When the computer is in conditional mode, store requests which should only be executed if the condition causing branch is not satisfied are marked in SAR to prevent execution until the condition is determined to be not satisfied. However, if the condition is satisfied, the requests are deleted. Second embodiment.-Fig. 3 shows a modified MSCE and main memory modules MSM1, MSM2, MSM3, MSM4, and also peripheral storage EMS. A fetch request from a CPU at 3000 is passed by a priority circuit 3002 to a bus 3004 to be stored in a request stack 245 and also applied to the main memory modules. The required module recognizes that the request is for it (decoder 3006) and if the module is not busy (busy flip-flop 3016) accepts the request and causes (via bus 3020) its deletion from the request stack 245. If it is busy, further CPU requests are inhibited at 3002 and the request in the stack 245 is applied to bus 3004 repeatedly until accepted. An exception occurs when the required address in a request is the same as that of the request currently being executed by the module (in the busy case) as determined by comparison at 3008. In this ease an accept-2 flip-flop 3030 will be set and provided it was not already set both fetches will be dealt with and the request in the stack 245 will be deleted. The accept-2 flip-flop 3030 is provided since no more than two fetches to the same address may be dealt with at a time. Just before a memory module is going to require use of the common storage-bus-out SBO it applies a signal DOG to bus 3020 to store a gate-out request in an MSM queue. The peripheral storage EMS also stores such requests, in an EMS queue. Priority in use of SBO is given to the EMS queue requests on a first-in-first-out basis, then to MSM on the same basis. Store requests from the CPU are placed in the SAR registers 241 shown, the data to be stored being placed in the corresponding SDB1-3 registers 244 shown. When the data is available in SDB, the request in SAR is gated on bus 3060 to the priority circuit 3002 where it is given priority over requests on buses 3000 and 3026 and thereafter supplied to the storage modules and request stack 245 as with a fetch. Two store requests for the same address are chained together, and the first request received is executed first. If the address of a fetch request is equal to that of a store request in SAR, as determined by comparators 820, the fetch is inhibited until after the store has been performed. I/O (input/output) requests at 3066 are given priority (at 3002) over requests on buses 3060, 3026, 3000. I/O store requests utilize a SAR and the SDB I/O shown.