Patent GB-1029953-A (GB)
Title: Improvements in or relating to calculating machines
Inventor: KITZ NORBERT
IPC: G06F7/491
Filed: 1961-10-02
Abstract: 1,029,953. Electric calculating apparatus. BELL PUNCH CO. Ltd. Sept. 28, 1962 [Oct. 2, 1961], No. 35559/61. Heading G4A. A keyboard-operated decimal calculator for the four arithmetic operations comprises a pulse generator PG delivering a pulse to each of its outputs 0-9 in turn, a number of orders 1K- 10K of decimal keys each receiving the pulses and on operation of a key in that order delivering a selectively timed pulse to its gate 1KG- 10KG, and a number of decimal counting stages forming a decimal accumulator 1R-12R which receive through gates 1RG-12RG at inputs H a number of pulses controlled by the timing of the output pulses from 1KG-10KG. The opening of the KG gates is controlled by a counter TK, and of the RG gates by a counter TR which for addition are stepped together by P9 pulses to enter the augend from the keys into the accumulator, lowest order (1K) first. For multiplication and division the stepping of TK may be effected independently, under control of counter CC. Addition.-In the rest state TR is held at state T0 by the potential on start line ST2, TK is at t1 and CC is switched off by signal ST1. On depression of a key the ST signals allow CC to step to C1 and the next P9 pulse from PG, which is freely running, steps TR to T1. Assuming the depressed key is decimal 4 in the order 1K, the next P5 pulse will pass gate 1KG to the K line to pass gate K91 where it sets KC to energize output KA (the signal A is present at this time see below). Gate G6 is now enabled, since M and + signals are generated for additions, and Y is generated by unit MK when no multiplier key is depressed. The Z input of G6 consists of all nine pulses generated by PG, and hence the last four of these will pass or gate G10 to the H line, and 1RG being enabled by T1 will be added in to the count in 1R. Any carry generated will set CS, which being reset by the next P0 pulse will produce a pulse for entry into the next order (TR and TK being advanced to T2 and t2 at P9). The enabling of 2KG, 2RG; 3KG, 3RG &c. continues in turn, adding in the entered augend to the accumulator. At t11 BA is set to disable KG1 and prevent any further entry into the accumulator. Subtraction.-When the subtraction key is operated the control signals M and S are generated, so that gates G7 and G8 may be enabled. On operation of a digit key the next P0 pulse passes G7 to 1R (this is the fugitive 1 involved in subtraction by addition of 9's complements). Subsequent pulses in this group pass G8 (since KB signal is present) until the pulse on the K line from 1K sets KC to disable G8; thus the 9's complement of any entered digit is added into 1R. This cycle is repeated for higher orders, KC being reset after each cycle by the P9 pulse. Multiplication.-For this the decimal order keys are made key-set, and the start signals ST are controlled by the multiplier keys MK. Signals M, + and X are generated. The multiplicand is entered on the left-hand side of the keyboard (orders 10K, 9K &c.) and these keys are set without starting the operation. A multiplier digit is depressed, when the multiplicand is added in to orders 10R &c. of the accumulator, as in " addition " above. At the end of this operation CC is stepped from C1 to C2 over gate CG2 and BC is switched. The operation is repeated since PG continues to run, until CC is counted up to the value of the multiplier digit +1, when MK will deliver a signal MR to stop PG over gate SG2. The MR signal also passes gate TG5 to step TK, so that on the entry of the next multiplier digit the multiplicand will be added in one order lower. Division.-The dividend is entered into the accumulator (10R, 9R &c.) and the divisor into the keyboard (10K, 9K &c.); division is by subtraction until the accumulator goes " negative," when the divisor is added back and shifted, the process being repeated. The quotient is built up in the left-hand side of the accumulator. Signals D and + are generated; the operation is described in detail in the Specification. Gates 11GB &c. are used to detect 9's in the stages 11R, 10R &e. in turn and advance CC accordingly. Checking multiplication results may be effected by depression of a key which divides the product standing in the register by the multiplicand registered in the keyboard and displays the recalculated multiplier digits.