Patent GB-1025529-A (GB)
Title: Character recognition apparatus
IPC: G06K9/64
Filed: 1962-12-20
Abstract: 1,025,529. Automatic character reading. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 20, 1962 [Dec. 22, 1961], No. 19129/65. Divided out of 1,025,528. Heading G4R. In a character reading apparatus the character is scanned to produce a set of digital signals representing black or white areas which are applied to probability circuits, one for each possible character, each probability circuit being responsive only to those signals which have a very high probability or a very low probability of being produced by scanning the corresponding character, so that an output signal is obtained indicative of the probability that the set of signals would be obtained by scanning the corresponding reference character, the outputs being compared to identify the character. In the form of Fig. 1 (not shown) a magnetic character 42 is passed first under a magnetizing head 44 and then under a row of twenty sensing heads 46 scanning a broad area to allow for lack of vertical register. The number of channels is reduced at 50 by OR gating the top and bottom ten together in pairs and after amplification at 51 the signals are rectified, clipped and integrated at 52 to eliminate noise signals. The D.C. signals when present set triggers in a buffer store 55, the triggers being sampled seven times during the passage of a character and the corresponding signals are stored in the columns of a register matrix 56, Fig. 2 (not shown). The timing circuit 54 is started by two " black " signals occurring at the outputs of the quantizing circuits 52 so that the character pattern is always stored against the right-hand edge of the matrix. Its vertical position is indeterminate so that the pattern must be vertically shifted and the match signal found for each of the ten possible vertical positions. A vertical roll is applied after the signals are stored and the match signals for each position are stored in a delay line memory 60. The partial statement circuit selects those matrix positions which are reliably "1" or " 0 " and also various combinations, found by previous trial to be reliably " 1 " or " 0 " for each character. The combinations are obtained by AND and OR gates as shown in Fig. 6, (not shown) every input being applied to a trigger 70, 71 etc. The probability resistor network 59 is as shown in Fig. 3 (not shown). Since only probabilities of approximately one are used all the resistors are the same value. Outputs for the fourteen possible characters appear on leads C0-C13, there being a different output at each roll position of the pattern in the register. The ten outputs for each character network are applied to a delay line, the best match giving the least signal. The outputs from ten tappings of the delay lines are applied to an OR gate which passes the smallest current. After amplification this is applied to a comparator. This consists of a matrix of 14 x 14 bi-stable cores, each core being connected to compare one of the outputs with another of the outputs. The cores are all biased so that for one signal to be picked as less than any other it must be less by at least the value of the bias signal. That is if the smallest signal is not less than the next smallest by a certain amount no output is given. Also all signals are compared with a certain predetermined maximum signal so that unless the match is good enough to produce a signal less than the chosen maximum no output is produced.