Patent GB-1357450-A (GB)
Title: Transmission systems
IPC: H04J3/06
Filed: 1971-06-15
Abstract: 1357450 Multiplex pulse code signalling PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd (Philips Gloeilampenfabrieken NV) 15 June 1971 28031/71 Heading H4L In a system of the type disclosed in Specification 1,261,447, an improved frame synchronizing device is provided at the receiver. Transmitter.-As shown in Fig. 1, the system provides five channels C1 to C5 including one synchronizing channel, the input signals being delta-modulated at 1 to 4 respectively, and the channels combined in time division multiplex on transmission path 20 by distributer 6 controlled by clock pulse generator 10. The synchronizing signal consists of a pseudo-random code repeating after 30 bits, one bit being transmitted per frame and is generated at 5 under the control of generator 10. As generated at 5 each bit lasts for the duration of a frame. Receiver.-The received signals are re-generated at 22 and the bit timing is extracted at 21 to provide clock pulses to control via a counter 26 the channel distributer 23. The demultiplexed channels C1 to C4 are then decoded in conventional manner at 27 to 30. A synchronizing device 31 comprises a local code generator 32, similar to generator 5, which supplies two outputs x, y of the synchronizing code relatively shifted by a predetermined number of bits of the code, as described, by one bit, the output x being used as a reference. Outputs x, y are supplied to modulo-2 adders (exclusive-OR) 33, 34, respectively, the other input to the adders being the combined input signal to the receiver. The outputs of the adders, 33, 34, which appear only when the two inputs differ, are supplied to two groups of AND gates P 1  to p 5  and q 1  to q 5  respectively which are opened in succession by channel distribution pulses a 1  to a 5 . The outputs of AND gates p 1  to p 5  are supplied to counters X 1  to X 5  respectively of a group Gx and the gates q 1  to  q5  are similarly connected to counters Y 1  to Y 5  of a group Gy all the counters being reset to zero by a signal RAZ at the start of a signal from output x. Each counter has an output for a predetermined threshold, e.g. the end position of the counter, and during a synchronizing code counts the number of anti-coincidences (errors) between 30 bits supplied by output x and y and 30 bits received through each of the channels C1 to C5. Logic circuit 36, Fig. 3 (not shown) receives the outputs x 1  to x 5 , y 1  to y 5  of the counters and controls the local code generator 32 and logic circuit 38, Fig. 3 (not shown) receives the outputs x 1  to x 4  and y 1  to y 4  to control the channel distributer 23. In operation, if all the counters have reached their end position on termination of a cycle of comparison, logic circuit 36 applies a signal to control circuit 37 which blocks a gate 41 so that the code generator 32 is stopped for the duration of two code bits after which a new cycle of comparison is made. If at the end of a code at reference output x one of the counters of group GY has not reached its end position, circuit 36 supplies a signal so that code generator 32 is stopped for the duration of one code bit, i.e. the y output will be transferred to output x. At the same time, logic circuit 38 supplies a signal via control circuit 39 if the counter corresponds to one of the information channels to shift the distributer 23 so that the channel corresponding to that counter coincides with the synchronizing channel C5. After the distributer has been shifted its normal operation is resumed and the system is assumed to be in synchronism. If the counter which does not reach its end position is in group GX the code generator is not stopped but the distributer is shifted as before. Modifications.-The number of outputs from the code generator at the receiver may be increased to reduce the time required to restore synchronism. The number of counters in each group GX and GY may be less than the number of channels and the channels arranged in groups for testing, Fig. 4 (not shown). When the multiplex frame includes a sub-frame a further pseudo-random code and similar apparatus may be used to synchronize the sub-frame. In order to shorten the time taken for testing for synchronism of the sub-frame, only part of the code may be used for each test. Satellite communication system.-In such a system in which communication is required between mobile stations and a fixed ground station, the sub-frame synchronizing signal may also be used to find the range of a mobile station. The ground station transmits the subframe sync.-code in a channel of the sub-frame and when the sub-frame has been synchronized as described at the mobile receiver, the subframe code generator at that receiver produces a code with a shift relative to the code transmitted by the ground station equal to the propagation time between the stations which is transmitted in a sub-frame of a second multiplex signal to the ground station. At the ground station the shift of the received code relative to the transmitted code, which is a function of twice tne distance between the two stations, is measured.