Patent GB-1454833-A (GB)
Title: High speed mos random access read/write memory device
IPC: H03K19/0185
Filed: 1974-01-25
Abstract: 1454833 Semi-conductor memory ADVANCED MEMORY SYSTEMS Inc 25 Jan 1974 [20 Feb 1973] 03612/74 Heading G4C A matrix type semi-conductor memory (Fig. 1) comprises a plurality of cells having dynamic storage nodes, arranged in rows and columns, there being additionally one control cell per column, a plurality of address buffers coupled to a plurality of X-decoders, one for each row, and a plurality of Y-decoders, one for each column, each Y-decoder when its column is selected providing two decoded clock signals C2<SP>1</SP>, C3<SP>1</SP>, the first for setting data sense lines and a data control line to the inverse state of the contents of cells in the column and the control cell respectively and the second for setting the cells to the states of the data sense line and each X-decoder when its row is selected coupling the associated data sense line to a read output line and a sensing circuit which compares the signals on the read output line and the data control line to provide an output signal representing the data stored in the cell at the junction of the selected row and column. As described the memory comprises a matrix with 32 cells in each of 64 rows there being an additional 32 cell control row, each cell comprising 3 FETs (Q1, Q2, Q3, Fig. 2, not shown). Preferably P channel metal gate field effect devices are used, a storage node being formed between the gate of one device (Q2) and one region of another device (Q3), the line linking these being insulated. In operation at time T0 clock C1 applied to the gates of devices Q4, Q5 goes low to pre-charge to low state data sense line D/S and data control line DC. When at time T2 decoded clock C2<SP>1</SP> applied to gate of the first cell device (Q1) in a selected column goes low, if the storage node is in its low state device (Q2) conducts to change the state of data sense line D/S. If the storage node is in its high state the state of the data sense line remains unchanged. At time T5 when clock signal T3<SP>1</SP> goes low device (Q3) is turned on and forces the storage nodes of the cells to their opposite state. The control cell which is also switched acts as a reference with which the cells in an addressed column may be compared to determine the stored information. The matrix may be automatically refreshed by sequentially addressing each column. Address buffer circuit (Fig. 5, not shown).- There is one buffer circuit for each of the bits of the address, device (Q33) in each buffer being coupled to a single voltage reference circuit designed to provide a signal close to the low state VDD on a line (36) to maintain device (Q33) generally on. At time T1 when C1 goes high and Cl goes low a line (34) is only coupled to voltage source (VSX<SP>1</SP>) if the associated address bit is low. Otherwise a device (Q32) remains on so that a line (32) is coupled to the high supply VSS and is consequently high and a further line (30) is held low. This results in devices (Q26, Q27) being turned on to provide a low signal representing the address bit on the line (40), an inverse signal also being provided on line (42). The outputs from the buffers are fed to decoders. Decoders.-A decoder circuit similar to that of Fig. 3 (not shown) is provided for each of the 64 rows so that in the selected row a device (Q76) is held on to turn on a device (Q77) and transmit the state of the data sense line to the read output line (R0). A circuit similar to that of Fig. 4 (not shown) is provided for each of the 32 columns to provide decoded clock signals C2<SP>1</SP>, C3<SP>1</SP> for the addressed column. If a write command is to be executed a signal (WC) turns on device (Q81) and the desired state is applied to write driver (WD), device (Q80) and the address device being turned on to transmit the signal to the drive/sense line. One bit of the address signal is also used to select write or left drivers 70, 72 (Fig. 1). Since the state of every cell in a column is inverted upon each application of a decoded clock signal C3<SP>1</SP> to that column, the incoming data must be exclusively ORed in write driver circuit (Fig. 10, not shown) with the data control signal DC from the data control cell in the addressed column before it is applied to the word line WD. Similarly the sensed data on output line R0 is exclusively ORed in a sense circuit (Fig. 11, not shown) with the data from the control cell to derive the correct output information. Voltage source circuit (Fig. 6, not shown).- This circuit receives a reference input voltage (VSX) and provides a variable reference voltage (VSX<SP>1</SP>) to maintain switching levels. Two devices (Q6, Q7) are coupled between power supply terminals (VDD, VSS) form a voltage divider with the divided voltage being applied to a line (20) connected to the gate of a device (Q8) in series with two devices (Q9, Q10). One of these (Q9) is maintained on by coupling its gate to the supply (VDD). The output voltage (VSX<SP>1</SP>) on line (22) is the sum of the voltage on line (20) and the threshold voltage of the device (Q8) which varies with processing and is consequently generally reflective of the threshold voltage of other field effect devices in the circuit. To minimize variations due to loading the gate of one device (Q10) is coupled to one region of device (Q9). Internal timing circuit (Fig. 8, not shown).- This provides a clock signal C2D delayed with respect to the clock signal C2 to provide a delay time within which the address cell may be read. An additional 3 device cell identical to the cells of the memory is provided, un-decoded clock signals C2, C3 being applied to this cell during every memory cycle. At time T0 when clock signal C1 is low a device (Q63) is turned on to pre-charge to a negative level a line (60). At time T2 when clock signal C2 goes low a device (Q60) is turned so that the line (60) switches to a positive level turning on a device (Q64) so that signal C2D goes to a low state at time T3. At time T4 when the clock C2 goes high, device (Q60) is turned off so that the signal C2D returns to its high state. The cell is refreshed by the signal C3.