Patent GB-1077424-A (GB)
Title: Improvements in secondary radar systems
IPC: G01S13/78
Filed: 1965-03-02
Abstract: 1,077,424. Secondary radar systems. SOCIETE NOUVELLE D'ELECTRONIQUE ET DE LA RADIO INDUSTRIE. March 2, 1965 [March 3, 1964], No. 8874/65. Heading H4D. The invention is concerned with improvements in "defruiting" devices in secondary radar systems of the type wherein an aircraft replies to a ground interrogation with position information pulses framed within two framing pulses 20.3 Ás. apart. Before reaching terminal 1 of Fig. 1, a reply V(n-1) passes through, a limiter, a circuit rejecting pulses less than .35 Ás. in width, an amplitude quantizer, a time quantizer, synchronized by radar clock pulses, and a store. A different store is provided for each interrogation and reply mode used. The store stores the quantized reply Vq(n-1) for one repetition period less 20.3 Ás. Thus at the output of the store, reply Vq(n-1) appears, for two consequentive synchronous replies, with the second framing pulse F2q(n-1) in synchronism with the first framing pulse V<SP>1</SP>(n) of the next unquantized reply V(n) (Fig. 2) appearing at input terminal 2. Reply Vq(n-1) is fed to a shift register R 1  with a shift time of 20.3 Ás. Thus when pulse F2q(n-1) is in the last stage of register R 1 , pulse F1q(n-1) is in the first stage. The Vq(n-1) output of register R, is shown in Fig. 2 and is in synchronism at the input of AND gate Po will reply V(n), also at the input of said gate. Thus for two synchronous replies, gate Po produces an output V<SP>1</SP>(n). To ensure that pulses F1q(n-1) and F2q(n-1) are 20.3 Ás. apart the outputs of the first and last stages of register R 1  are fed, together with pulse V<SP>1</SP>(n) to AND gate ET 1 . A pulse in synchronism with V<SP>1</SP>(n) is thereby produced which triggers a bistable device B1 into producing a pulse SP1 opening gate P 1  and allowing pulses Sn (i.e. pulses V<SP>1</SP>(n), slightly delayed by L 1 ) through. Opening pulse SP1 is normally terminated by a radar synchronizing pulse on terminal 3 via OR gate 0U 1 . A pair of asynchronizing replies will not produce an output from gate ET 1  and so will not be passed. The pulse from gate ET 1  triggers bi-stable device B 2  which feeds its thus produced pulse to a register R 2  having a shift time of 20.3 Ás. Thus the delayed output of the register R 2 , is further slightly delayed by L 2  and may be used to reset bi-stable device B 1  via OR gate OU 1  instead of the pulse on terminal 3. In the case of two synchronous replies each comprising two interleaved replies, Fig. 5a, the framing pulses F<SP>1</SP>1q(n-1) and F<SP>1</SP>2q(n-1) of the second reply cause a second output from gate ET 1 . This is applied via gate P 2 , opened by the output of device B 2 , to register R 2 , to reset all of its stages excepting the first one, to zero. Thus when the remaining first stage pulse reaches the output of the register, to reset device B 1 , and terminate the opening pulse SP1, both interleaved replies have passed through gate P1 as required. The output of register R 2  resets device B 2  via OR gate OU 2 . A circuit comprising invertor C, 20.3 Ás. delay L 3 , AND gate ET 2 , and the applied output of register R 2 , produces a pulse ET 2 , Fig. 6, which indicates a garbled reply and stops unnecessary working of decoding machinery &c.