Patent GB-1024359-A (GB)
Title: Semiconductor structures poviding both unipolar transistor and bipolar transistor functions and method of making same
IPC: H01L21/00
Filed: 1964-06-16
Abstract: 1,024,359 Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. June 16, 1964 [July 5, 1963], No. 24912/64. Heading H1K. In a unitary semi-conductor device comprising the functional equivalents of a unipolar transistor and a bipolar transistor, the channel of the unipolar transistor functional equivalent and the collector of the bipolar transistor functional equivalent each include a separate portion of an epitaxial layer having a uniform resistivity. As shown, the device is produced in an N-type silicon wafer 10 by diffusing boron through an aperture in an oxide mask to form a P-type " floating gate " region 12. A thin layer of material is removed from the surface of the wafer, using for example HC1 vapour, to reduce out-diffusion in subsequent operations. A layer 14 of high resistivity N-type silicon is now epitaxially deposited on the wafer by the thermal decomposition of SiCl 4  in a hydrogen stream. A second diffusion is used to produce an isolating P-type region 12a extending through epitaxial layer 14 and enclosing a part 14a of this layer. Two P-type regions now diffused into the layer 14 to form a gate region 16a for the unipolar transistor in the form of a rectangular ring, and a rectangular base region 16b for the bipolar transistor. Phosphorus is diffused into P-type region 16b to form an N+ type emitter region 18 for the bipolar transistor. The surface of the wafer is covered with a silicon oxide layer 28 and aluminium is vacuum deposited over windows in the layer and is alloyed to the semi-conductor to form ohmic contacts 21, 22, 23, 24 and 25 to the gate, source, and drain of the unipolar transistor and the emitter and base of the bipolar transistor respectively. A strip 27 of aluminium is simultaneously deposited over layer 28 to interconnect contacts 23 and 25. The collector contact of the bipolar transistor is produced by applying a contact 26 of goldcontaining antimony to the lower face of wafer 10. Alternatively a ring-shaped N+ type region can be diffused into layer 14 round region 16b simultaneously with the formation of emitter region 18 to form the collector contact of the bipolar transistor. The device may also be produced by epitaxially depositing a P-type layer on an N-type wafer and then diffusing arsenic into this layer except where the floating gate region 12 is to be formed. The N-type epitaxial layer is then deposited over the first layer and the remainder of the device fabricated as before. A plurality of integrated circuits each comprising two unipolar transistors and two bipolar transistors may be produced in a slice of grown single crystal silicon doped with antimony. The oxide layers are produced thermally and the epitaxial layer is doped by including arsine (AsH 3 ) in the gas stream. Conductive interconnections are provided on each circuit so that the first unipolar transistor drives the two bipolar transistors which are connected as a Darlington pair while the second unipolar transistor serves to bias the bipolar transistors. A resistor may also be included in the circuit. Germanium and III-V compounds, such as gallium arsenide, may also be used as the semi-conductor material, and the starting wafer may consist of a slice of crystal pulled from a melt of a section of a dendritic crystal.