Patent SG-11201901052W-A (SG)
Title: Minimum track standard cell circuits for reduced area
Inventor: XU JEFFREY
IPC: H01L27/118
Filed: 2017-09-14
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 22 March 2018 (22.03.2018) WIPO I PCT (10) International Publication Number WO 2018/053097 A1 (51) International Patent Classification: H01L 27/02 (2006.01) H01L 27/118 (2006.01) (21) International Application Number: PCT/US2017/051518 (22) International Filing Date: 14 September 2017 (14.09.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/266,523 15 September 2016 (15.09.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: XU, Jeffrey, Junhao; 13443 Moreton Glen, San Diego, California 92130 (US). BADAROGLU, Mustafa; 5775 Morehouse Drive, San Diego, California 92121 (US). YANG, Da; 5775 Morehouse Drive, San Diego, California 92121 (US). (74) Agent: TERRANOVA, Steven, N.; Withrow & Terrano- va, PLLC, 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, (54) Title: MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA 222(4)' l> 0\ © © 00 i-H o CJ o £ WHAVR "V-228, W'ACUVE 238 Wp0RT f""v- 210 •"v^-230, VV'ACTIVE ..I?"* WHAVR Fif* 9A a I Stasis &&$r\ (57) : Minimum track standard cell circuits for reduced area are provided. In one aspect, a minimum track standard cell circuit employs a first high aspect ratio voltage rail disposed over a first one-half track and configured to provide a first voltage (e.g., VDD) to the minimum track standard cell circuit. A second high aspect ratio voltage rail is disposed over a second one-half track substantially parallel to the first high aspect ratio voltage rail. The second high aspect ratio voltage rail is configured to provide a second voltage less than the first voltage (e.g., VSS) to the minimum track standard cell circuit. The minimum track standard cell circuit employs multiple tracks disposed between the first and second one-half tracks. The number of tracks can be limited based on particular factors. Minimizing tracks reduces area compared to conventional standard cell circuits. [Continued on next page] WO 2018/053097 A111|| |||||||| || |||||| ||||| ||| ||||| |||| 11| ||| ||||| ||||| ||||| ||||| ||||| |||| ||||||| |||| |||| |||| SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(Hi)) Published: — with international search report (Art. 21(3)) — before the expiration of the time limit for amending the claims and to be republished in the event of receipt of amendments (Rule 48.2(h))