Patent GB-977555-A (GB)
Title: Reversible analog to digital converter
IPC: H03M1/00
Filed: 1961-04-28
Abstract: 977, 555. Electric selective signalling systems. P. A. HOFFMAN, and T. T. EATON, [trading as HOFFMAN & EATON]. April 28, 1961 [April.28, 1960], No. 15427/61. Heading G4H. A reversible analogue-to-digital converter includes a first and second signal storage means and means for periodically coupling them in signal sharing relationship whereby successive portions of a signal initially stored on one storage means are successively transferred to the other. The Specification explains firstly how it is possible to produce a succession of voltages in a geometric progression by means of two capacitors, for example if a capacitor 24 Fig. 1a is charged to a potential E and then paralleled by an equal capacitor 26, the potential of each capacitor becomes 1/ 2 E, and if one of the capacitors is discharged and again paralleled with the other the common potential becomes 1/ 4 E, and so on, giving a geometric progression with common ratio 1/2, and secondly how, by means of a circuit shown in Fig. 3, including a unity gain amplifier 68, it is possible to transfer additively the charge from a capacitor 60 to a capacitor 66, by closing a switch 62, so that after the transfer capacitor 60 is completely discharged and capacitor 66 contains the algebraic sum of the two charges initially on the two capacitors. These two circuits are used in combination to build up a voltage corresponding to a binary number by summing and/or subtracting selected terms of the geometric series of voltages. A circuit, Fig. 13, using their two circuits can function either to convert a binary coded number into a corresponding amplitude significant voltage or to convert an amplitude significant voltage into a binary number. In both conversion processes a succession of voltages in G.P. is built up on a capacitor 809 (by repeated paralleling with an equal capacitor 807) and transferred selectively either additively or subtractively to a capacitor 817. In the analogue-to-digital conversion process the unknown voltage is first stored on capacitor 817 and then voltages E, 1/2E, 1/4E &c., are successively added or subtracted from it in such a way that the resulting algebraic sum tends to zero. Thus in each bit-period of the conversion process, and with a switch 816 closed, a comparator 821, via unity gain amplifier 815 and a lead 819, decides whether the potential across capacitor 817 is positive or negative and energizes either a relay 810 or a relay 813 accordingly to transfer the charge from capacitor 809 to the capacitor 817 either additively or subtractively in such a way as to attempt to change the sign of the potential across capacitor 817. At the end of the bit-period, all the charge on capacitor 809 having been transferred to capacitor 817, relay 808 is energized to transfer half the charge on capacitor 807 to capacitor 809 and the system is then ready for the next bit-cycle. The sequence of comparison results produced by the comparator then represents a binary coded number corresponding to the unknown analogue input voltage, the binary code being such that each "I" bit represents the addition of the associated denomination weight while each "0" bit represents the subtraction of the associated weight. This code is equivalent to the pure binary code. The reverse conversion is effected by controlling the addition or subtraction of successive terms of the G.P. sequence of voltages in accordance with the incoming bits, the final amplitude significant output being taken from capacitor 817.