baber/WOPTO huggingface dataset:
Patent TW-444048-B (TW)
Title: Oxidation process for preparing quinacridone pigments
Inventor: BAEBLER FRIDOLIN
IPC: C09B67/22
Filed: 1997-08-14
Granted: 2001-07-01
Abstract: A process for preparing a quinacridone of the formula I, wherein X and Y are independently 1 or 2 substituents selected from the group consisting of H, F, Cl, C1-C3alkyl and C1-C3alkoxy, by the oxidation of a salt of the corresponding 6,13-dihydroquinacridone of the formula II, which comprises an oxidation step in a liquid reaction medium essentially consisting of from 20 to 750 parts by weight of water and from 50 to 750 parts by weight of the alcohol per 100 parts by weight of 6,13-dihydroquinacridone, wherein the 6,13-dihydroquinacridone salt is oxidized with hydrogen peroxide in the presence of a quinone compound as catalyst in the temperature range from 50 DEG C to the reflux temperature of the reaction medium for from 5 minutes to 5 hours.
Patent TW-393829-B (TW)
Title: Programmable low-pass filter
Inventor: LIAU SHIA-BIN
IPC: H03H7/12
Filed: 1997-09-11
Granted: 2000-06-11
Abstract: A programmable low-pass filter includes a selectively switchable transfer circuit (21) for receiving a digital input signal (VIN), a second input for receiving timing control signals (CNT) and at least two outputs to which the input signal is selectively transferred according to the received timing control signals. An RC circuit includes a capacitor (23) coupled between an output (VOUT) and a reference potential and a resistor block (22) having at least two resistors coupled between the transfer circuit, with each output of the transfer circuit being coupled directly to a respective resistor. Thus, the input signal (VIN) is transferred by the transfer circuit (21) to its outputs according to the timing control signals (CNT) so that it is filtered using different RC time constants at different times during the waveform.
Patent TW-375824-B (TW)
Title: Protective circuit
Inventor: NORSTROM HANS
IPC: H01L27/06
Filed: 1997-10-16
Granted: 1999-12-01
Abstract: The present invention relates to a protective circuit for protecting an integrated circuit against electrostatic discharge, so called ESD. The integrated circuit is connected to a supply voltage via a Vcc-pad (2) and an earth pad (3). The protective circuit, which is particularly intended to protect a positively supplied circuit for radio frequency applications against both negative and positive voltage pulses, comprises an input pad (14) and at least one PNP-transistor (20), the input pad being connected to the integrated circuit, and the PNP-transistor being connected with its collector to the input pad, and its emitter connected either to the Vcc-pad or to the earth pad. The base of the PNP-transistor can be connected to its emitter either directly or via a resistor (24), or not to be connected.
Patent TW-388768-B (TW)
Title: Flame retardant resin composition and laminate using the same
Inventor: MIYAKE SUMIYA
IPC: C08L63/00
Filed: 1997-12-06
Granted: 2000-05-01
Abstract: A flame-retardant resin composition which comprises (A) 100 parts by weight of an unhalogenated epoxy resin having at least two epoxy groups in one molecule, (B) 20 to 205 parts by weight of a maleimide compound having at least one maleimido group in one molecule, (C) 20 to 65 parts by weight of a curing agent having an amino group and (D) a phosphorus compound in a proportion of 0.5 to 4.5 parts by weight in terms of phosphorus element per 100 parts by weight of a total of the components (A), (B) and (C), provided that the pro-portion of nitrogen element contained in the composition is 2.0 to 10.0 parts by weight per 100 parts by weight of the total composition. The above flame-retardant resin composition  has a high flame retardance without adding a halogen compound and does not deteriorate the charace-teristics of commercial products.
Patent TW-451157-B (TW)
Title: IC card terminal device and control method with multiple protocols
Inventor: KURIYAMA RYOUICHI
IPC: G06K7/00
Filed: 1998-01-08
Granted: 2001-08-21
Abstract: An IC card terminal device provides the function of: keeping one of the mentioned IC cards and transmitting the communication clock signal of the synchronous communication protocol to the kept IC card; determining if the kept IC card is applied with any one of the synchronous communication protocol and asynchronous communication protocol in terms of the outputted data of the kept IC card based on the mentioned clock signal; conducting subsequent processing of the kept IC card with the synchronous communication protocol when determining that the synchronous communication protocol is in use; and transmitting the communication clock signal of the asynchronous communication protocol when determining that the asynchronous communication protocol is in use.
Patent TW-438662-B (TW)
Title: Method of manufacturing molding and mixing device for manufacturing molding
Inventor: KATO MASAMI
IPC: B29C48/605
Filed: 1998-07-08
Granted: 2001-06-07
Abstract: A manufacturing technology by which clear colors and patterns can be brought out without a remarkable lowering of strength. Immediately before delivery to a metal mold, outer resin material 21 positioned on the main cylinder 11 inner wall side is put in the molten state, and inner resin material 22 positioned on the main screw 12 side is controlled to be from the softening temperature to the melting temperature both inclusive to be extrusion-molded as they are. For example, the temperature of a heater device for heating the main cylinder and the main screw is controlled.
Patent TW-431990-B (TW)
Title: Self-supporting container for fluid
Inventor: KUGE RAIZOU
IPC: B65D30/10
Filed: 1998-07-18
Granted: 2001-05-01
Abstract: It is an object of this invention to provide a self-supporting container for fluid, for holding a commodity such as a liquid, solid, powdery, or granular material, which can be more easily handled and used by making it light and of which cost and disposability are improved. This self-supporting container B for fluid is constituted of a cylindrical bag body 10 opened at both ends and a sheet 30 forming the bottom. The sheet 30 forming the bottom is heat-sealed at the periphery of the bottom opening of the bag body 10 to form the flat bottom face. The bag body 10 and the sheet 30 forming the bottom are formed with at least two multi-layered film having a thickness of 50-200 mu m. Further, a container 80 formed with at least two multi-layered film having a thickness of 20-120 mu m is formed with a sealing portion 81 at top end for displaying specific items, where a retainer 82 may be placed into the container 80.
Patent TW-403666-B (TW)
Title: Syringe type ampoule, carrier/ampoule unit, and manufacture thereof
Inventor: FORSBERG MIKAEL
IPC: A61J1/06
Filed: 1998-09-22
Granted: 2000-09-01
Abstract: A syringe type ampoule having (a) a barrel with a front end and a rear end defining an axis therebetween, the barrel having substantially constant cross-section between the front end and the rear end , at least the front end ending in an opening, (b) a sealer attached to the front end and sealing the opening, (c) at least one piston movably and sealingly arranged within the barrel and (d) a sleeve extending along at least a part of the barrel, the sleeve having a front part and a rear part, the front part being connected to the sealer. The barrel has a front end terminating in an edge surrounding the opening, the edge having an outer circumference substantially equal to the barrel outer circumference. The invention relates to methods and means for manufacture of pre-filled such ampoules or other ampoules.
Patent TW-388923-B (TW)
Title: Method for producing self-aligned T-gate FET with gate oxide sidewall protection
Inventor: LIN HUNG-JR
IPC: H01L21/28
Filed: 1998-11-02
Granted: 2000-05-01
Abstract: A method for producing a self-aligned T-gate FET with gate oxide sidewall protection comprises forming a protective layer on the sidewall of a gate oxide layer to prevent the sidewall of the gate oxide layer from being damaged by corrosion during the subsequent formation process of the T-gate, thereby avoiding a reduction in the performance of the MOS transistor. The present invention is carried out by a self-aligned process which uses planarization and forming a conductive stack layer on the polysilicon gate to obtain a T-gate conductive region, in order to reduce the parasitic resistance between the gate and the source/drain of the transistor. Furthermore, an air gap exists between the lower part of the stack conductive layer of the T-gate structure and an extension of the source/drain region, so that the parasitic capacitance between the gate and the source/drain can be reduced. Therefore, the present invention can be applied on the production of a high speed IC and a high frequency IC.
Patent TW-594778-B (TW)
Title: Interface for signal transmission between semiconductor devices
Inventor: SO BYUNG-SE
IPC: H04L25/02
Filed: 1999-02-24
Granted: 2004-06-21
Abstract: An interface for signal transmission between semiconductor devices, including a dummy transmission line for transmitting a first data applied to one end to the other end, a first driver for comparing the first data with an input second data and generating a first signal, a first transmission line for transmitting the first signal, a first receiver for comparing the first signal transmitted via the first transmission line with the first data transmitted via the dummy transmission line, and recovering the second data. a plurality of drivers for comparing an (n-2)th (n=3, 4, ...) signal with input n-th data and generating an (n-1)th signal, a plurality of transmission lines for transmitting the (n-1)th signal, and a plurality of receivers for comparing the (n-2)th signal to the (n-1)th signal and recovering the n-th data.
Patent TW-522161-B (TW)
Title: Finely divided rubber powders, process for the production thereof and use thereof
Inventor: GOERL UDO
IPC: C08L21/00
Filed: 1999-03-31
Granted: 2003-03-01
Abstract: This invention relates to pulverulent rubbers containing filler which remain free-flowing even after exposure to mechanical stresses and to a process for the production thereof, in which the rubber powder is obtained in two precipitation steps, and to the use of these powders for the production of vulcanisable rubber compounds.
Patent TW-418523-B (TW)
Title: Method for fabricating a ferroelectric memory device
Inventor: JUNG DONG-JIN
IPC: H01L29/788
Filed: 1999-04-23
Granted: 2001-01-11
Abstract: A ferroelectric capacitor with a ferroelectric film having a relatively larger amount of titanium consituent than zinconate constituent so as to improve ferroelectric characteristics. The method for fabricating the ferroelectric capacitor includes the step of heat treatment in oxygen ambient after forming a contact opening in insulating layer which covers already formed ferroelectric capacitor. Such heat treatment in oxygen amvient can minimize undesirable side effect of platinum electrode which oxidizes the ferroelectric film components.
Patent TW-415076-B (TW)
Title: Ferroelectric capacitor and method for fabricating the same
Inventor: JUNG DONG-JIN
IPC: H01L21/8247
Filed: 1999-04-29
Granted: 2000-12-11
Abstract: A ferroelectric capacitor with a multilayer ferroelectric film including relatively larger amounts of titanium content than zinconate content so as to prevent degradation of ferroelectric characteristics. First ferroelectric film is made of PZT formed on a lower electrode. Second ferroelectric film is formed on the first ferroelectric film and has larger amounts of titanium content than zinconate content. An upper electrode is formed on the second ferroelectric film and a protection layer is formed to cover the ferroelectric capacitor.
Patent TW-441127-B (TW)
Title: A quasi-unipolar transistor with buried channel
Inventor: DENG DUAN-LI
IPC: H01L29/78
Filed: 1999-05-04
Granted: 2001-06-16
Abstract: A quasi-unipolar transistor with buried channel side and low 1/f noise, comprising: a mainbody region which is formed of the first conductive impurity of low concentration implanted in a semiconductor substrate to form the base of the quasi-unipolar transistor; a drain region formed of the second conductive impurity of high concentration implanted in the mainbody region to form the drain/collector region of the quasi-unipolar transistor; a source region spaced with drain for a certain distance, which is formed of the second conductive impurity of high concentration implanted in the mainbody region to form the source/emitter region of the quasi-unipolar transistor; a channel region formed of the second conductive impurity of low concentration implanted in the mainbody region between the source region and the drain region to provide a low resistance conducting channel between the drain/collector and source/emitter; a gate oxide layer formed on the surface of the channel region of the semiconductor substrate; a gate electrode formed of the conductive material on the surface of the gate oxide on top of the channel region; and a bias voltage source to connect the gate electrode and the mainbody region to reduce the internal voltage of the quasi-unipolar transistor. This quasi-unipolar transistor with buried channel side further comprises an overlapped layer implanted between the channel layer and the semiconductor substrate to form a buried channel layer, not on the surface of the semiconductor substrate. This quasi-unipolar transistor with buried channel side can be disposed in a diffused well implanted with a mainbody region.
Patent TW-455830-B (TW)
Title: Method of, and apparatus for, driving a liquid crystal display device
Inventor: SURGUY PAUL WILLIAM HERBERT
IPC: G09G3/36
Filed: 1999-05-04
Granted: 2001-09-21
Abstract: This invention relates to a method of, an apparatus for, driving a liquid crystal display device incorporating anti-ferroelectric liquid crystal (AFLCD). The electro-optic response of AFLCs is only approximately symmetric about a zero applied voltage. Therefore although AFLCs exhibit memory, they are not truly polarity insensitive. Consequently in certain switching sequences a phenomenon known as ""flicker"" arises as a result of the asymmetry between transmission characteristics of AFLCD material when switched using a positive voltage and subsequently using a negative voltage. Previously one way in which this ""flicker"" has been avoided was to double the switching speed of driver circuitry. However, this proved to be complex and expensive and imposed an unrealistic requirement on currently available electronic circuitry. The invention overcomes the problem by providing a switching sequence whereby all colour fields are addressed according to a sequence of the type green, red, green, blue etc, charge balancing is achieved; and the requirement for doubling the switching speed is avoided.
Patent TW-408418-B (TW)
Title: Method of detecting the device damage caused by plasma/charge accumulation effect
Inventor: CHEN BOR-CHENG
IPC: H01L21/66
Filed: 1999-05-12
Granted: 2000-10-11
Abstract: A method of detecting the device damage caused by plasma/charge accumulation effect comprises the following steps: to form first the angle or arc shaped active region on the semiconductor wafer, then to define a gate oxide and gate pattern on the top of the above-mentioned active region and to form a detection device. Then, after processing plasma process on above-mentioned device, it could utilize electrical measurement to detect the device damage degree caused by plasma/charge accumulation effect. According to this invention, it could effectively detect the damage of the device caused by plasma/charge accumulation effect.
Patent TW-469408-B (TW)
Title: Computer keyboard detection method
Inventor: JANG YOU-CHIUAN
IPC: G06F9/44
Filed: 1999-06-01
Granted: 2001-12-21
Abstract: There is provided a computer keyboard detection method, which finds the short-circuit keyboard button and open-circuit keyboard button by utilizing the keyboard scanning code capable of being a close code and an open code in the processing buffer of the computer host, thereby surely eliminating the short-circuit and open-circuit problems in the computer keyboard. At first, a keyboard starting test graph corresponding to the buttons of the physical keyboard and arranged based on the distribution of the buttons of the physical keyboard is displayed on the computer display screen. Then, a standard scanning code data and keyboard matrix corresponding to the physical keyboard is established. Next, there are set a button excessive time and a specific ejecting test combination button to enable a user to terminate a keyboard test procedure at any time. When the user presses a corresponding button, the keyboard controller will read a signal change to produce a keyboard scanning code corresponding to the button and activate a hardware interrupt IRQ1 of the computer host, thereby using a self-established interrupt service routine to replace the conventional INT9H interrupt procedure. Then, the keyboard scanning code is directly sent into the buffer of the computer host for being compared with the standard scanning code data. Next, the current status of the button is displayed on the keyboard test graph on the display screen. Because the keyboard scanning code can be a close code representing that the button is pressed an open code representing that the button is raised after pressing down, it is able to determine, when the user presses buttons sequentially, the short-circuit and open-circuit relations between data lines by the button status of the keyboard test graph on the display screen and the distribution of the column data line and row data line in the keyboard matrix, cooperated with the buttons actually operated by the user, so as to find the short-circuit and open-circuit buttons in the computer board. The present invention directly processes the keyboard scanning code in the buffer to obtain both of the keyboard close code and open code, and thus can effectively solve the short-circuit and open-circuit problems of the keyboard.
Patent TW-411574-B (TW)
Title: Self-aligned etching process
Inventor: LIAN WAN-YI
IPC: H01L21/60
Filed: 1999-06-09
Granted: 2000-11-11
Abstract: A self-aligned etching process. It is sequential to form conductive layer and 1st insulating layer on substrate, then patterning 1st insulating layer and conductive layer to form plural stacks on preserved area. Then, forming spacer on sidewall of each stack, and forming same-shaped stop layer on substrate. Planarizing 2nd insulating layer on substrate, then removing portion of 2nd insulating layer, forming plural openings to expose stop layer surface between spacers, then removing exposed stop layer.
Patent TW-504869-B (TW)
Title: Outlet box for a data network
Inventor: PHILIPP GERD
IPC: H02G3/08
Filed: 1999-07-30
Granted: 2002-10-01
Abstract: An outlet box for a data network has a lower housing part (13) whose base (15) is divided into two flat channel surfaces (29, 31) on the outside of the base (15) which in each case proceed from opposite outer sides of the wall (16) of the lower housing part (13) and are aligned parallel to the base plane (11) and two quarter-cylinder groove-shaped channel surfaces (32, 33) which in each case tangentially adjoin the flat channel surfaces (29, 31) and whose cylinder axes (34, 35) are aligned parallel to the middle plane (12) and parallel to the base plane (11) and lateral sections (36, 37), which are situated on both sides of the middle plane (12) and parallel to the base plane (11). All the cylinder axes (34, 35, 38, 39) are situated at least approximately in the same plane (43). The wall (16) and a region of the groove-shaped channel surface (32, 33) respectively adjoined axially thereto are constructed such that they can be knocked out a rupture point in each case at the two ends of each groove-shaped bearing surface (38, 39) and (46, 47, 48, 49). It is thereby possible for two data cables strongly loaded bends. If required, two further data cables can also be fed past under the box without thereby necessitating additional mounting height. The outlet box can be used as a flush-type box with a low mounting height.
Patent TW-420875-B (TW)
Title: Camera module
Inventor: NAKASHIRO YASUO
IPC: H04N5/225
Filed: 1999-08-05
Granted: 2001-02-01
Abstract: The inventive camera module is to form a positioning reference surface P composed of the same flat surface on one side of the ceramic substrate 2 that the positioning reference surface P comprises the positioning reference surface portion of semiconductor chip, the frame member mounting surface portion for mounting and combining with the frame member 10, and a mirror face positioning reference plane that connects with the above mentioned frame member 21 to position it, and a reference plane connecting to the semiconductor chip 1 to position it in the positioning reference plane P with the same flat plane formed to one face of the ceramic base 2 is used in common to the reference plane connecting to the above mentioned mirror frame member to position it.
Patent TW-399120-B (TW)
Title: Turbine spline seal and turbine assembly containing such spline seal
Inventor: BAGEPALLI BHARAT SAMPATHKUMAR
IPC: F02C7/28
Filed: 1999-09-09
Granted: 2000-07-21
Abstract: A turbine spline seal (516) includes an elongated turbine seal member (526). The seal member has an elongated, imperforate, and manually-flexible first portion and a manually-rigid second portion lengthwise adjoining the first portion. The turbine assembly includes the turbine spline seal and also includes first and second turbine members (512 and 514). The first and second turbine members are spaced apart to define a fluid-path leakage gap (515) therebetween, and the seal member is placed in the gap. Each lengthwise edge (522 and 524) of the seal member engages a respective one of two opposing surface grooves of the first and second turbine members.
Patent TW-441186-B (TW)
Title: PLL circuit
Inventor: NIWA TAKAHIRO
IPC: H03L7/14
Filed: 1999-12-08
Granted: 2001-06-16
Abstract: A PLL circuit used in an apparatus for reading and writing data to a disk compensates for noise which causes a false clock signal or for missing clock signals which can be caused by a scratch or smudge on the surface of the disc. The PLL circuit includes a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal and generates a phase difference signal. A charge pump receives the phase difference signal and generates an output signal, which is filtered with by a low pass filter. The filtered signal is provided to a voltage controlled oscillator, which generates an oscillation output signal. A divider divides the oscillation output signal and generates the feedback signal. A time information generating circuit generates time information of the oscillation output signal, indicating the time period where it is presumed the reference signal is or should be received. A control circuit, using the time information, permits the output of the oscillation output signal when the reference signal is input during the presumed time period and maintains the output of the oscillation output signal when the reference signal is not received during the presumed time period.
Patent TW-468342-B (TW)
Title: Data transfer apparatus, data transfer system and recording medium
Inventor: UENO TAKAFUMI
IPC: H04L13/08
Filed: 1999-12-17
Granted: 2001-12-11
Abstract: A data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any interruption and to transfer continuous data on a general-purpose bus such as a PCI bus, and a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or the data transfer system. If it is supposed that a capacity of a write buffer memory 4 is CAPW, an input rate of continuously input data is T1, and a maximum assumed value of an interval of bus access permissions issued by a CPU 1 is TW, data omissions can be prevented by setting CAPW, T1 and TW at values that satisfy: CAPW ≥ TW x T1.