Patent GB-986148-A (GB)
Title: Synchronized signal pulse circuit
IPC: H03K3/027
Filed: 1962-02-23
Abstract: 986,148. Transistor pulse-shaping circuits. SPERRY RAND CORPORATION. Feb. 23, 1962 [March 24, 1961], No. 7076/62. Heading H3T. Fig. 1 shows in logical block form a circuit for producing in response to the actuation of switch 100 at an arbitrary time, output pulses in pushpull on lines 118b, 118c which commence in coincidence with one clock pulse and terminate with the next. The upper inputs to gates 102, 104 are at a " low " (negative) voltage level when the corresponding switch contact is not closed; closure of the switch applies " high " (earth) voltage to the corresponding input and the gates deliver a high voltage output only upon the coincidence of two low voltage inputs thereto. With the circuit as shown, gate 102 delivers a low-voltage output due to the highlevel input from switch 100, but when the switch is changed over to the position shown in broken lines, the output of gate 102 changes to high voltage as both inputs thereto then become low-level signals. The output of clocked bi-stable circuit 106 changes over due to the changed input thereto, but only when the next clock pulse is applied thereto, line 106b changing from high to low and line 106c changing from low to high. The negative-going and positivegoing pulse edges produced are delayed by respective delay lines 108, 114, line 108 introducing a delay greater than and line 114 introducing a delay less than the interval between successive clock pulses so that after inversion in circuits 110, 116 input signals which are both of the low-voltage kind are applied to gate 112 for an interval equal to the difference between the delays of circuits 108, 114 and embracing the clock pulse next subsequent to that producing the changeover in circuit 106. Circuit 112, which is similar to circuits 102, 104, consequently delivers a high-voltage output during this interval; this is applied to clocked bi-stable circuit 118 which upon the occurrence of the said next subsequent clock pulse changes output levels on output lines 118b, 118c until the arrival of the immediately ensuing clock pulse, when the output levels will be restored to their original values as by then the inputs to gate 112 will be of opposite kinds and the gate will be delivering a low-voltage output to bi-stable circuit 118. Fig. 3 (not shown) presents the waveforms occurring at selected points in the circuit and by reference thereto it may be shown that contact bounce at switch 100 does not produce spurious output pulses on lines 118b, 118c though it might alter the precise clock-pulse period with which the output pulse coincides. It may also be demonstrated that no output pulse is produced when the switch is restored to its full-line position; during the interval due to the difference between the delay times of circuits 108, 114, both inputs to gate 112 will be of the high-voltage kind and the output from gate 112 will consequently remain at the low-voltage level. Fig. 2 shows the schematic circuit diagram. Gates 102, 104, 112 are similar and also similar to inverter circuits 110, 116 which however are provided with a single input only. The two clocked bi-stable circuits 106, 118 are similar, each comprising a diode gate 200, 202 which passes the input level only upon the application of clock pulses as shown, the diode gate output then being applied to a bi-stable circuit comprising reciprocally coupled transistors T2, T3 or T6, T7, having diodes D10, D11 in the cross-coupling in one direction. The output from circuit 106 on line 106c is applied as an input to gate 104. This ensures that contact bounce at the switch does not cause an intermittent output from circuit 106, since once the circuit has switched over, a high-level input is applied to circuit 104 from circuit 106, thus ensuring that both inputs to circuit 102 remain at a low level even if further contact bounce occurs provided that contact is not made with the upper contact of switch 100.