Patent GB-1155849-A (GB)
Title: Data selection systems
IPC: G06F12/04
Filed: 1966-11-01
Abstract: 1,155,849. Digital data stores. INTERNATIONAL BUSINESS MACHINES CORP. 1 Nov., 1966 [14 Dec. 1965], No. 48809/66. Heading G4C. A stored mask and a counter select byte positions in a multi-byte word store used for communication between a central processor and a byte channel. Data passes between a computer memory and input/output devices (e.g. magnetic drum, disc, tape or card reader) via a one-word assembly register 26 under control of a programmed channel command word (Fig. 1). Each data word has 8 bytes, each byte having 8 data bits and one parity bit. The channel command word supplies the word portion of an initial data address to a data word address register 15 to address the memory, and the byte portion of the address to preset a byte counter 17. It also supplies a count field to a count register 16, an 8-bit mask to a byte mask register 19, and a flag bit to a bit-register 18. Input to computer.-If the flag bit at 18 is 0, successive input bytes arriving at 28 are passed by AND gates 22 into respective byte positions of assembly register 26, the byte positions of the register used for this purpose being those corresponding to a bit 0 in the mask register 19, one bit position in the latter corresponding to each byte position in register 26. This is done by advancing the byte counter 17 from its preset value by means of a step generator 29 to mark successive output leads of the counter until the marked lead corresponds in position to a 0 in mask register 19 when a match decoder 33 (utilising exclusive-ors) sets a match trigger 31 to inhibit further counter advance. The mask register 19 and byte counter 17 enable the appropriate set of AND gates 22 to pass the input byte to the appropriate position of the assembly register 26. At the same time, a corresponding bit position of a mark B register 23 is set to 1. Then the input equipment resets the match trigger 31 to allow the byte counter 17 to advance further. The speed of the byte counter 17 is such that all bytes are allocated to some position in register 26. When byte counter 17 advances from 7 to 0, the count register 16 is decremented by 8, and the contents of the assembly register 26 and mark B register 23 are transferred to a buffer register 42 and a mark A register 43. The bytes of the storage word addressed by register 15, which correspond to 1 bits in the mark A register, are replaced by the corresponding bytes of the buffer register 42, the other bytes being rewritten unchanged. The address register 15 is incremented by one, and operations repeat until the count register 16 holds zero. However, if the flag bit at 18 is 1, one input byte corresponds to each byte position in assembly register 26 and those bytes corresponding to byte positions having a 1 in mask register 19 are discarded. This is achieved by causing each pulse from generator 29 to not only advance byte counter 17 but also, via AND 46, to set the match trigger 31, thereby inhibiting further counter advance until a byte has been supplied and the trigger 31 reset by the input equipment. Output from computer.-A word is read from the computer memory via buffer register 42 to assembly register 26. The byte counter 17 is advanced rapidly as in the first input mode, the flag bit at 18 being 0, until it reaches a 0 in the mask register 19 when the counter 17 is inhibited as in the first input mode. The byte counter 17 gates the corresponding byte in assembly register 26 to an output bus via AND gates 47. The output equipment then resets trigger 31 to allow the counter 17 to advance again. Otherwise, the output mode is like the first input mode.