Patent GB-1139055-A (GB)
Title: Magnetic logic circuit
IPC: H03K17/82
Filed: 1966-06-17
Abstract: 1,139,055. Associative stores. INTERNATIONAL STANDARD ELECTRIC CORP. 17 June, 1966 [19 June, 1965], No. 27100/66 Heading G4C. [Also in Divisions H1 and H3] A logic device comprises a block 1 of square loop ferrite having one or more write conductors 4a, 4b and a read conductor 5 passing through one hole and an interrogate conductor 6 passing through an orthogonal non-intersecting hole, interrogation being by coincident pulses on the interrogate conductor 6 and the, or one of the, write conductors. Write-in is by a pulse on the, or each, write-in conductor and a coincident pulse in wire 6 which produce a resultant cross flux in the material between the two holes. An interrogate pulse in 6 of the same direction as for write-in accompanied by a second input of polarity opposite to that of the first input produces a substantial output B(O), (Fig. 3a), while if the polarity of the second pulse is the same as that of the first input pulse a much smaller output B(L) results. A wordorganized associative storage matrix comprising four such devices is shown in Fig. 4, each device being provided also with an associative interrogate conductor 13 and an associative reading conductor 14. Fig. 5 shows a block diagram including the switching circuits of a storage matrix 20. Normal operation.-An address when applied at 32 (Fig. 5) to decoding circuit 21 produces signals which operate on a selecting matrix 22 so that one of the m rows of writing conductors 4a is acted upon in response to that address (subject to a writing instruction 35). The information 31 to be stored is applied through a selecting network 24 to digit generators 25 which apply information pulses in parallel to column writing conductors 4b. The network acts as a filter to exclude an optional number of the n bits of the information 31. The information is written in row-wise fashion by coincidence of row and column pulses subject to the writing instruction 35 by which the devices 22 and 25 are made effective. To read-out the address 32 is applied to selecting matrices 23 and 22 to pulse the interrogate conductor 6 and the conductor 4a coincidentally, the outputs being fed-out through read-out conductors 5 and being available at 29. Associative Operation.-If interrogation is not followed by write-in, a random number-pof the n bits input at 31 is compared with the same points of all the stored words. Any row in which the comparison results in agreement is marked in device 27 which stores the information as to which rows have been worked, as a q-out-of-m code and converts this to q individual l-out-of-m codes applicable successively (via 28), subject to instruction 39, to the selecting matrices 22 and 23 in coincidence. Read-out signals are taken off at 29 as in a normal operation. When writing is to be effected after the associative interrogation, the l-out-of-m codes appearing at output 28 of device 27 are applied successively to matrix 22 for selecting writing conductors 4a the address portion being blocked by 24 while writing into a row and the information associated with that address being written into that row.