Patent UA-103541-U (UA)
Title: Shaper single series of three packs of pulses
Inventor: KOROBKOV MYKOLA GRYGOROVYCH
IPC: H03K3/78
Filed: 2015-05-22
Abstract: Shaper single series of three packs of pulses comprising: two reversible binary counter. Each meter has input supply pulse synchronization input mode debugging on the summing / subtraction, counting mode entry permit, entry permit simultaneous parallel loading inputs and supply data, asynchronous input settings in the zero state, the output overflow; inverter. Shaper has first and second elements OR; chain consisting of series connected resistor and capacitor; synchronous D-flip-flop with asynchronous input settings in the zero state, the first and second elements two-input I. The common point connected series resistor and capacitor connected to the information input of D-flip-flop, with one input of the first and second element two-input I. Out of the first element and with two-input 'asynchronous disconnected from the input install D-flip-flop in the zero state; a second input of the second element is connected to the output of the first OR element, one of the inputs is connected to the output of D-flip-flop. Exit overflow of the second counter is connected to its input permission mode boot. Inputs of parallel data loading meters form the inputs to programming generator set timing pulses on the output of the shaper. The output of the second element is connected to the input of asynchronous installation of meters in the zero state. Clock inputs of the first and second counters are interconnected, creating shaper input - input supply continuous periodic sequence of pulses from the output of an external oscillator. Clock input D-trigger input supply creates impulses run. In shaper introduced: the third element OR, two-input NAND element; first, second, third and fourth JK-flip-flops with asynchronous input settings in the zero state. The first and second JK-triggers create recurring unit (three meter), which has three classes of transitions 00-11-10-00 sequence. The first trigger has a direct entrance K and two direct inputs J, and united by the second trigger has direct input J and K inputs of two straight, united by I; inverted output of the first JK-flip-flop is connected to one input of the second JK-K flip-flop. Inverted output of the second JK-flip-flop is connected to one input of the first J JK-trigger input K J and the second input of the first JK-flip-flop is connected to the input J and K second input of the second JK - this. The second has a trigger inverted input inputs and two K J, and united by one of them inverted, and the second straight third JK-flip-flop has one inverted input J and K inputs of two, joined in and one of them inverted, and the second straight. Inverted output of the second JK-flip-flop is connected to the direct input of the third JK-K flip-flop, invers out third JK-flip-flop is connected to the direct input of the second JK-J trigger inverse input K and J inverse input of the second JK-flip-flop connected inverted input with inverted J and K input of the third JK-flip-flop, creating entry permit regime transition (counting) the third count, which is connected to the output of the second overflow counter. The third input of the first OR element connected to direct the third JK-flip-flop. Exit overflow of the first counter is connected to the first input NAND element and the third element OR. The second input NAND element is connected to an inverted output of the first JK-flip-flop and a second input of the first element I. The output of NAND element is connected to the input mode permits counting of the first counter; the second input of the third OR element connected to direct the first JK-flip-flop. The output of the third OR element connected to the input of the second input element OR and authorization regime counting of the second counter. Inputs of parallel load data inputs form the first counter programming shaper for the specified number of pulses per pack. Inputs second parallel data download counter inputs form shaper programming on a given length of the pause between pulses packs. Clock inputs JK-flipflops connected to the input shaper, asynchronous inputs in a zero installation JK-flipflops connected to the output of the second element I.