Patent GB-1332470-A (GB)
Title: Data processor system
IPC: G06F9/48
Filed: 1970-12-18
Abstract: 1332470 Data processing systems WESTERN ELECTRIC CO Inc 18 Dec 1970 [23 Dec 1969] 60227/70 Heading G4A A real time data processing system, e.g. controlling a telephone switching network or manufacturing process, includes a memory in which a plurality of locations are allocated to timing lists and a further location is allocated to a pointer, the lists being processed one at a time to recognize timing conditions in the operation of the system and the pointer being altered after processing each list to point to the next list in a predetermined sequence. In the described exemplary embodiment, a memory block is allocated to a head cell table containing 60 head cells each defining a corresponding one of 60 timing lists by specifying the first and last of the service circuit registers making up the list, intermediate registers in the list being linked to each other by addresses stored therein. An executive program activates a timing program at one second intervals to examine the timing list defined by the head cell which is pointed to by the present pointer word PP in memory, PP being incremented when the list has been processed so that the lists are processed at one second intervals, each list being processed at one minute intervals. When the executive program determines that a service circuit requires timing, e.g. to time a call, a task program stores timing interval T1 and time out return data TR in a corresponding service circuit register in the memory. The timing interval word T1 in minutes M and seconds S represents the time for which the register is to remain on a timing list. S is added to PP to form a word RPP which is stored in the register and serves as a pointer to the head cell defining the timing list to which the register is to be added, i.e. that list which will be processed S seconds after the next list to be processed. Insertion of the register to the end of the list pointed to is performed by conventional programming techniques with appropriate up-dating of the link addresses in the listed registers and the head cell, and a GPTC word in the newly added register is set to M representing the number of list processing operations to be performed on that register. The timing program, in examining a list, tests the GPTC word in each register, decrementing it if it is not zero. If the GPTC word is found to be zero, the timing program stores its own return address and transfers control to the instruction atthe address specified by TR in that register to enable the register to be updated, after which the timing program resumes processing of the list. A register can be removed from a list, e.g when a subscriber flashes the switch-hook to request operator assistance during a call, while saving any unexpired time. The displacement RI between the head cell of the list containing the register and the head cell of the next list to be processed is calculated from RI = RPP-PP + 1 to indicate the remaining seconds of the timing interval and the remaining minutes are transferred from GPTC to another word AC in the register before the register is removed from the list. Timing which has been interrupted in this way can be resumed by transferring the contents of AC back to GPTC in the relevant register and adding PP to RI to calculate the appropriate head cell defining the timing list to which the register is to be added.