Patent GB-727596-A (GB)
Title: Improvements in or relating to electronic computers
IPC: G06G7/163
Filed: 1952-06-30
Abstract: 727,596. Electric analogue calculating systems. SOC. D'ELECTRONIQUE ET D'AUTOMATISME. June 30, 1952 [June 30, 1951], No. 16475/52. Class 37. Analogue computing apparatus for producing one or more electrical output voltages each of amplitude proportional to the product (or quotient) of the amplitudes of a corresponding pair of a plurality of electrical input voltages comprises a variable gain electronic amplifier whose input is supplied with a signal comprising an impulse sequence of amplitude proportional to the magnitude of the multiplicand (or dividend) and whose gain is adjusted proportionately to the value of the multiplier (or divisor) during the intervals between the impulses of the multiplicand (or dividend) sequence, the output product (or quotient) voltage being derived from the amplifier output at instants in phase with the impulses of the input sequence. Fig. 1 shows a device for multiplying or dividing positive quantities wherein two variable continuous input voltages are applied to terminals 61 and 7<SP>1</SP> of electronic subdividing circuits 8, 9 (which may comprise e.g. degenerative pentode amplifiers unblocked by pulsing the suppressor grids) respectively controlled by uniform trains of pulses 10 and I2 (Fig. 6, not shown) mutually phase displaced in time, to produce corresponding amplitude modulated pulse trains similarly displaced in time, which are mixed at the input of a variable gain amplifier, e.g. a variable mu pentode (Fig. 2, not shown), or a variable mu heptode (Fig. 3, not shown). The resultant composite output pulse train is connected to the output terminal through an output subdividing circuit 12 controlled by pulse train I2, and also to a subdividing circuit 18 controlled by pulse train I0. A variable continuous voltage applied to terminal 26<SP>1</SP> is similarly converted by a subdividing circuit 27 controlled by pulse train I0 to an amplitude modulated pulse train which is mixed with the correspondingly time-phased pulse train from subdividing circuit 18 at the input of an amplifier 24 energizing a low-pass filter 29, at whose output a quasi-continuous voltage is developed which controls the gain of amplifier 1 by biasing the pentode control grid or the second heptode control grid. Postulating a pulse amplitude Ue on terminal 7 representing a signal X on terminal 7<SP>1</SP> a pulse amplitude Us at the output of subdividing circuit 12, and an amplifier gain K controlled by a voltage Vk; where UVk is a parastic D.C. component. The latter is eliminated by applying the amplifier output to a subdividing circuit 31 controlled by a pulse train I 1  time-phased intermediately of pulse trains I0 and I2 (Fig. 6, not shown) so that the circuit is open only when no input pulses are arriving at the input of amplifier 1. The resultant pulse train, amplitude modulated according to UVk, energizes an amplifier 33 and low-pass filter 34, which developes a quasicontinuous voltage applied to the output of amplifier 1 in such sense as to cancel out the parastic D.C. component. Then postulating a pulse amplitude Ur on terminal 26 representing a signal Y on terminal 26<SP>1</SP>, and a pulse amplitude Uo on terminal 6 representing e.g. a unity reference signal on terminal 6<SP>1</SP>, and the amplitude of the output pulse train derived from subdividing circuit 12 controlled by pulse train I2 is given by Us=YX. Interchanging the input signal Y and the unity reference signal The low-pass filter 29 may immediately follow the subdividing circuit 18, in which case the subdividing circuit 27 may be omitted. Errors are reduced by making the gain of amplifier 24 large and the subdividing circuits may comprise pulse controlled degenerative amplifiers of gain (-1). In a modification (Fig. 4, not shown) for multiplying algebraically positive and negative quantities X and Y, voltages representing constant coefficients a and b are respectively added to the X and Y signals from preset potentiometers energized from a positive reference voltage of e.g. unity, so that Us=(bŒX) (aŒY)=abŒaXŒbYŒXY and a voltage representing the terms - ab#aX#bY is derived from three preset potentiometers energized respectively from the reference voltage, and the X and Y signals in negative sense, which voltage is mixed with that applied to the output subdividing circuit, so that the resulting pulse train amplitude is given by Us=ŒXY. The inputs to the subdividing circuit supplying the parasitic D.C. correcting amplifier and low-pass filter is corrected for the additional a and b signals combined with the input signals X and Y by adding in voltage terms #bY-abEo derived from the preset potentiometers. In a further modification (Fig. 5, not shown), a single variable is similarly algebraically multiplied by a sequence of variables X 1  ... X n-1  whose representative signals are subdivided into corresponding amplitude modulated pulse trains cophased in time with corresponding controlling pulse trains I 2  ... In which are respectively time-displaced over the intervals between successive Io pulses, and also control the output subdividing circuit to successively develop amplitude modulated product pulse trains corresponding to YX 1 ... YX n-1 . The controlling pulse trains are derived from e.g. a multivibrator sequentially operating a chain of flip-flop circuits to produce successive trains of identical frequency but mutually displaced in time.