Patent GB-1358206-A (GB)
Title: Surface-controlled field effect semiconductor device
IPC: H01L29/00
Filed: 1972-02-07
Abstract: 1358206 Transistor data storage INTERNATIONAL BUSINESS MACHINES CORP 7 Feb 1972 [2 March 1971] 5510/72 Addition to 1317493 Heading H3T [Also in Division H1] In a surface controlled semi-conductor device of the kind described in Specification 1,317,493 a P-type substrate 1 has two diffused or implanted N+ doped source and drain zones 2, 3 separated by a channel zone, which are covered by a thin oxide insulant 4 coated over the channel with doped poly crystalline semi-conductor material, e.g. Si forming gate 5 and the source and drain zones have metal or doped poly crystalline contacts 6, 7 (Figs. 1a, 1b). Voltages of, e.g -3 are applied to substrate, + 6 to drain, and Ov to source. A connection 8 is established between gate 5 and a zone 10 in the channel zone and a connection 9 between the gate and a zone 11 outside the channel doped oppositely to the substrate. Positive pulse on gate 5 establishes N-conductive channel between source and drain, and a PD is tapped off connection 8 to the gate to maintain conductivity after cessation of the initial pulse, and for storage state "0" a voltage OV is applied to the gate whole for state "1" a voltage is applied such as to maintain drain-source conduction. If gate 5 voltage exceeds that of N-doped region 10 the barrier layer 5-10 is biased forward and 10-1 is biased backwards, while if it is in defect barrier 5-10 is biased backwards, and a persistent barrier is maintained by opposed biasing of diodes 12, 13 at the connections between 5-10 and 10-1 (Fig. 2, not shown). The connection 9 stabilizes a gate zero voltage for storage state "0". Diode 14 between P-doped connection 9 and N-doped region 12 is forward biased, and diode 15 between N-doped regions 11 and substrate 1 is backward biased. When gate 5 is +ve biased for channel conduction, diode 14 is biased forward and reduction of gate potential to that prevailing in the channel zone is prevented by positioning the contact between connection 9 and region 11 outside this zone. In a modification (Figs. 4a, 4b, 5, not shown) the gate to substrate connection is disposed in a predefined position relative to the drain zone, in its depletion region, so that region 18 is held at zero potential. The drain zone is enlarged laterally over the channel zone, and positive charges accumulating on the gate when it is biased OV are eliminated and losses by isolation currents when it is positively biased are compensated. In a further modification (Fig. 6) gate 5 is split into two interconnected sections separated by a zone in which no electrons can assemble under the field effect of the gate and which consequentially has high resistance to reduce the drain current. Data storage.-Storage values are written in (Fig. 3, not shown) from a control FE-whose drain is connected to the gate of the storage FET, gate connected to a word line, and source connected to a bit line. To write in "1" the word line voltage is raised to render the control FET conductive to allow a pulse on the bit line to reach the gate of the storage FET which holds after the bit line pulse ceases. To write in "0" the word line voltage is similarly raised to allow the bit line 0 potential to reach the gate. To read out, the control FET is rendered conductive by address pulsing the word line to detect the gate voltage of the storage FET via bit line BL.