baber/WOPTO huggingface dataset:
Patent JP-S59230169-A (JP)
Title: Direct current measuring circuit of dc converting device
Inventor: TAKAI AKIRA
IPC: H02M7/08
Filed: 1983-06-13
Abstract: PURPOSE:To measure a direct current with high accuracy and high stability without being influenced by an interphase reactor of the secondary winding side by forming the other by a delta connection in case other one of the primary winding of a stepdown transformer 1, or the secondary winding of a current transformer for detecting a current of each phase is a star shape. CONSTITUTION:A current in each phase of a primary side winding 11a of a star connection of stepdown transformer 11 whose secondary side is connected to a DC converting device with a reactor 2 is detected by current transformers 5-7. The secondary winding of the current transformers 5-7 forms a three phase bridge circuit of a delta connection through rectifiers 8a-8f, and an ammeter 9 is connected to its output side. In case of currents KIx, KIw, etc. being proportional to a DC current of this DC converting device flow to the ammeter 9, a current (kit), etc. being proportional to an energizing current by the reactor 2 different by 180 degrees in phase flow in the forward and reverse directions through the rectifiers 8a, 8c, etc., and do not flow to the ammeter 9. Accordingly, a direct current of the DC converting device is measured with high accuracy and high stability without being influenced by the interphase reactor. In this regard, even when the primary winding and the secondary winding bridge are formed by delta and star connections, respectively, the same result is obtained.
Patent JP-S5532176-A (JP)
Title: Logic comparing apparatus
Inventor: ICHINOMIYA YOSHICHIKA
IPC: G06F11/22
Filed: 1978-08-28
Abstract: PURPOSE:To divide the clock determining the comparison time into n clocks, respectively compare the respective divided standard and the input data and take out the compared data corresponding to the divided clocks as outputs. CONSTITUTION:The expected value from the terminal 17 is fed to FF 26, the time adjusting clock is given to the shift register 27, the output of 2m time slot is generated at a primary step thereof and at 2m+1 time slot of the next step output, the clocks divided in space are generated. According to the clock, the expected data in which one time slot phase is shifted from FF 19, 26 is obtained. The comparison of 2 time slot of output of the comparison circuits 12, 13 in which standard voltages are compared is carried out by the NAND gate 21, 22 and the comparison of 2m+1 time slot is carried out by the comparing NAND gate 28, 29. The control signal of the terminal 31 is added to FF 32, 33 to convert 2 time slot into an effective signal by the shift of one time slot and the respective signals are added to the comparing control AND gate 36, 37 to take out output corresponding to the divided clock.
Patent JP-S58222676-A (JP)
Title: Ghost eliminating circuit
Inventor: ITOU YUUJI
IPC: H04B1/10
Filed: 1982-06-21
Abstract: PURPOSE:To constitute a circuit not requiring an operational amplifier and a comparator with high speed and high gain, by using a CCD delay line for a shift register. CONSTITUTION:An error signal being a difference between an output signal and a reference signal is inputted to a CCD shift register 51 while being kept as an analog signal. The CCD shift register 51 shifts sequentially error signals within the range of equalization. After inputting the error signal having a required bit number, a tap gain correcting circuit 7 reads out successively each tap gain from a tap gain memory 6, corrects it according to the error signal written in the CCD shift register 51 and inputs the result to the tap gain memory 6 again.
Patent JP-2000299623-A (JP)
Title: Semiconductor integrated circuit device
Inventor: YABUKI SHINOBU
IPC: H03K3/037
Filed: 1999-04-13
Abstract: PROBLEM TO BE SOLVED: To accelerate a microprocessor or the like and to shorten the machine cycle of a computer system or the like by providing a flip-flop(FF) operable at high speed. SOLUTION: An FF 1, the basic element of a sequential circuit for the microprocessor or the like, is composed of an input part IP provided with a P channel MOSFET P1 provided between a power supply voltage VCC and an internal node n1 for receiving a pulse reset signal CR at the gate thereof and N channel MOSFET N1 and N2 serially provided between the internal node n1 and a ground potential VSS for respectively receiving input data D and a pulse clock signal CQ at the gates thereof and a feedback part provided with an inverter V1 provided between the internal node n1 and a non-inverted output terminal Q,  a P channel MOSFET P3 provided between the power supply voltage VCC and the internal node n1 for receiving a non-inverted output signal Q at the gate thereof and N channel MOSFET N4 and N5 serially provided between the internal node n1 and the ground potential VSS for respectively receiving the non-inverted output signal Q and the pulse reset signal CR at the gates thereof.
Patent JP-S5533217-A (JP)
Title: Control system for store information
Inventor: ITOU SEIKI
IPC: G06F15/00
Filed: 1978-08-31
Abstract: PURPOSE: To make it possible to control a volume of information easily by making customer's-order processing, cash management, commodity management, and another-store information processing possible by connecting several POS terminals to a host computer.  
     CONSTITUTION: To host computer 12, POS terminals 5 are connected through control parts 2 and 3 of dual constitution. Each POS terminal equipped with several item keys and function keys to simplify input operations for order processing and sales processing. Controlled by the control parts of dual constitution, POS terminals are high in reliability. Input data are collated with data in the master file of the host computer and the contents of the master filter are rewritten. To control parts, journal printers 7 and 8 floppy discs 9 and 10 are connected for recording input- output processes. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-S63271224-A (JP)
Title: Optical beam scanner
Inventor: HAKAMATA ATSUSHI
IPC: H04N1/04
Filed: 1987-04-28
Abstract: PURPOSE:To increase practically a light quantity on a face to be scanned and to shorten time required up to the usable state of a device such as a laser printer by controlling the modulation efficiency of an optical modulator at an almost maximum value if the quantity of an optical beam is not reached to a usable level. CONSTITUTION:At the time of detecting a laser beam deflected by a deflector 7, a photodetector 10 inputs a detecting signal corresponding to the quantity of the laser beam to a control circuit 11. At the time of receiving the light quantity detecting signal, the control circuit 11 detects whether the light quantity indicated by the detecting signal is reached to a usable level or not, and when the quantity is not reached to the level, the control device 11 controls the optical modulator 3 through a driving device 4 so that the modulation efficiency of the optical modulator 3 is almost maximized. When the quantity is reached to the usable level, the control device 11 controls the modulation efficiency of the modulator 3 on the basis of a light quantity control signal Vin obtained from the external while restricting the minimum value of the light quantity. Consequently, the incident light quantity upon a face to be scanned is increased and the time required up to the usable state can be shortened.
Patent JP-H043147-A (JP)
Title: Radioactive image information reader
Inventor: ISHIKAWA HIROMI
IPC: G03B42/02
Filed: 1990-04-20
Abstract: PURPOSE:To obtain the compact and inexpensive device by scanning a medium to an approximately arc shape in the direction approximately orthogonal with a sub- scanning direction and photoelectrically reading reflected light. CONSTITUTION:A light beam emitted by a light source 12 is so focused by an ordinary imaging lens 14 as to be imaged on the radioactive image state recording medium, such as accumulation type fluorescent material sheet 26 which is sub-scanned and transported while the medium is held to the prescribed approximate arc shape; thereafter, the light beam is deflected by a prescribed angle in the direction approximately orthogonal with the sub-scanning direction by an optical deflector 16 and the main scanning is executed. The light carrying the radioactive image information obtd. by the irradiation with the light beam is condensed by a light guide 18 which extends in proximity along the approximately arc-shaped main scanning curve 28 and has an approximately arc-shaped incident end face and a reflecting mirror 22 which is disposed in proximity to the light guide so as to face the same and has an approximately arc-shaped reflecting surface. This light is photoelectrically converted by a photodetector mounted at the exit end face of the light guide 18, by which the radioactive image information is read. The compact and inexpensive device is obtd. in this way.
Patent JP-S60250113-A (JP)
Title: Grid type dust cleaner with rake
Inventor: HANAMOTO TOSHIKAZU
IPC: E02B5/08
Filed: 1984-05-25
Abstract: PURPOSE:To ease the competitive action of a rake and a grid as well as prevent the imperfect raking operations of the inverter of a rake by providing an expansive device and a pinion to an arm fitted with a rake and also rack to be engaged with the pinion in parallel with the grid. CONSTITUTION:When a chain 9 is turned counterclockwise, a rack 20 is engaged with a pinion 25, and a rake 17 is vertically moved under the guidance of the rack 20. When the rake 17 is lowered, it is separated from the grid 2, and also when the rake 17 is raised, it is run in a creeping manner on the face of the grid 2. In the lowest position where the rake 17 is inversed from the lowering process to the raising process, a curved rack 21 close to the grid 2 allows the grid 2 to run on the track of the rake 17, as shown by arrow F, from the lowest position. An expansive device 28 comes to pressingly contact with the rake 17 regulatively according to the amounts of the residue to be raked up.
Patent JP-H07289063-A (JP)
Title: Grain culm conveyor with safety function
Inventor: NOMURA HIROHISA
IPC: A01F12/16
Filed: 1994-04-20
Abstract: PURPOSE:To provide the apparatus capable of directly restarting operations by equipping a conveyor with a safety function without being deformed or distorted even when a conveying passage is clogged with grain culms. CONSTITUTION:This grain culm conveyor with a safety function is obtained by retreating a nipping and holding rail (2) by pushing back force with the grains culms, extending and opening a conveying passage (4) and maintaining an extended and opened state thereof in an abnormality in which the amount of the grain culms conveyed through the conveying passage (4) exceeds the limit in a grain culm conveyor having the nipping and holding rail (2), installed opposite to a conveying chain (1) and urged with a spring (3) so as to constitute the conveying passage (4).
Patent JP-H07135376-A (JP)
Title: Composite printed-circuit board and its manufacture
Inventor: ITSUATSUKU KOOHEN
IPC: H05K1/02
Filed: 1994-04-20
Abstract: PURPOSE: To provide a printed circuit board excellent in heat conductivity. CONSTITUTION: A compound printed circuit board 10 includes a metal substrate printed circuit 12 and an insulation substrate printed circuit 14. The metal substrate printed circuit board 12 has the first layer 32 consisting of a heat conductive metal with high thermal conductivity and the second layer 28 closely adjacent to the first layer and consisting of a heat conductive and an electric insulation material. The second layer 28 has a top surface forming a conductive wiring 26. The insulation substrate printed circuit 14 forms a surface integrated with the metal substrate printed circuit 12. The insulation substrate printed circuit 14 also comprises the first layer 32 made of insulation material and a metal foil arranged closely adjacent to at least one face of the first layer, and has the second layer forming the conductive wiring 36.
Patent JP-2000297193-A (JP)
Title: Saponified ethylene-vinyl acetate copolymer and laminate
Inventor: ASANO KUNIYOSHI
IPC: C08L29/04
Filed: 1999-04-14
Abstract: PROBLEM TO BE SOLVED: To provide a saponified ethylene-vinyl acetate copolymer blend which is excellent in fabricability and gas barrier properties by mixing at least two water-alcohol solutions of saponified ethylene-vinyl acetate copolymers different from each other in ethylene content and/or degree of saponification to form a dope and bringing the dope into contact with a coagulating liquid to precipitate the copolymer blend. SOLUTION: At least two water-alcohol mixed solutions of saponified ethylene-vinyl acetate copolymers different from each other in ethylene content (by 3-25 mol%) and/or degree of saponification (by 25 mol% or lower), each copolymer satisfying expression I, are mixed at 40-110 deg.C to give a dope, which is brought into contact with an aqueous alcohol-containing coagulating liquid satisfying expression II at -10 to 40 deg.C to precipitate the objective saponified ethylenevinyl acetate copolymer blend. In the expressions, X is the ethylene content (mol%); Y is the water content in a solvent of the water-alcohol solution; M is the alcohol content in the coagulating liquid; (y) is the water content in the solvent of the dope; and Z is the content of saponified ethylene-vinyl acetate copolymers in the dope.
Patent JP-H05301051-A (JP)
Title: Production of molybdenum-contg. fluidized bed catalyst
Inventor: SOMEYA MASARU
IPC: C07C27/12
Filed: 1992-04-24
Abstract: PURPOSE:To produce a fluidized bed catalyst with high Mo content by adding Mo oxide of specified compsn. to the slurry in the production process of the fluidized bed catalyst containing Mo. CONSTITUTION:This Mo-contg. fluidized bed catalyst is prepared by spray granulating a slurry containing Mo salt and calcining. In this process, Mo oxide (e.g. MoO3) expressed by MoxOy (with 1 to 3 of y/x) is added to the slurry. The Mo oxide added to the slurry has <=50mum particle size which is smaller than the particle diameter of the catalyst. The add amt. of the Mo oxide is preferably 10-50wt.% of the Mo content in the slurry. Thereby, the fluidized bed catalyst with higher Mo content can be obtd.
Patent JP-H01277344-A (JP)
Title: Information recording medium
Inventor: OGINO NOBORU
IPC: G11B7/24021
Filed: 1988-04-28
Abstract: PURPOSE:To reduce the deviations of eccentricity values and coaxial degrees of two boards and to attain sure access even at the time of simultaneously executing information processing on both the faces of a board by positioning both the boards by laser beams so that a boundary between a circular mirror face part and an information recording part of one board coincides with that of the other board and sticking both the boards to each other. CONSTITUTION:The circular mirror face parts 7 having the same radium around a rotational center hole 5 are formed on 1st and 2nd boards 2, 3 adjacently to the information recording parts 8a and both the boards 2, 3 are positioned by using a laser beam a' so that the boundaries 14 between the mirror face parts 7 and the recording parts 8a coincide with each other and stuck to each other. Thereby, the coaxial degrees of the 1st and 2nd boards 2, 3 are logically '0' and the eccentricity values of the 1st and 2nd boards 2, 3 at the time of mounting them on a medium rotating means such as a turn table can be uniformed. Even when information processing to the information recording parts 8 of both the boards 2, 3 is simultaneously executed, sure access can be attained.
Patent JP-S5230336-A (JP)
Title: Information writing device of magnetic pulse
Inventor: HIROSHIMA MINORU
IPC: G11C11/14
Filed: 1975-09-04
Abstract: PURPOSE: In a memory which performs writing and erasing of magnetic pulse with a signal wire, operational margin in supply timing for writing pulse is expanded, and stabilized writing can be achived if the erasing pulse is applied before each writing. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S62263668-A (JP)
Title: Semiconductor integrated circuit device
Inventor: SAEKI AKIRA
IPC: H01L27/11
Filed: 1986-05-12
Abstract: PURPOSE:To obtain an extremely high resistance by making the resistance of insulator in which an impurity is introduced. CONSTITUTION:Resistances R1, R2 can be formed, e.t., by introducing arsenic with the conditions of approx. energy 80 keV and dose 15/cm<3> in an interlayer insulating film 12 by ion implantation. In comparison with the resistivity, e.g., approx. 10<20>OMEGAm or more of the interlayer insulating film 12 before the impurity is introduced, the resistivity of the impurity introduction region is, e.g., approx. 10<15>OMEGAm. The resistivity is extremely high compared to the resistivity of an intrinsic polycrystalline Si approx. 10<4>-10<5>OMEGAm. This can make the resistances R1, R2 high and the current from power source electric potential Vcc to a grounding wire via the R1 or the R2 at the time of stand-by can be reduced to, e.g., approx. 1muA or less.
Patent JP-S5632558-A (JP)
Title: Electrical insulating polyurethane coating material
Inventor: SUZUKI AKIRA
IPC: C09D175/00
Filed: 1979-08-23
Abstract: PURPOSE: The titled composition for an insulated wire, having improved solderability at a low temperature without deteriorating the coating property, and comprising (A) a specific bifunctional isocyanate (NCO) compound instead of a trifunctional isocyanate compound and (B) a polyester-polyol.  
     CONSTITUTION: A coating material prepared by incorporating (A) a blocked diisocyanate compound obtained by blocking the free NCO groups of a diisocyanate compound which is prepared by adding about 2 moles toluylene diisocyanate to one mole a monoalkylene glycol, e.g. ethylene glycol, with a compound having a phenolic hydroxyl group, e.g. phenol, with (B) a polyester-polyol, e.g. Desmophen 600 (trade name, manufactured by Bayer) at substantially an equimolar ratio of the blocked NCO groups in the component (A) to the OH groups in the component (B), and dissolving the mixture in a solvent, e.g. a phenol. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H07308534-A (JP)
Title: Oil mist removing device
Inventor: HONDA MASAAKI
IPC: F24F7/06
Filed: 1994-05-20
Abstract: PURPOSE:To provide an oil mist removing device which is continuously used for a long time and also by which fine particles of oil are effectively removed to prevent the environmental pollution. CONSTITUTION:An oil mist removing device 1 is arranged in an exhaust route A through which soot contg. fine oil particles or the like is exhausted, and provided with a body 3. To the body 3, a soot introducing pass 19 and a soot discharging pass 21 are connected so as to make them communicate with each other through the 1st connecting chamber 20 and the 2nd connecting chamber 22 respectively. In the body 3, blade plates 10 which are rotated together with a rotating shaft 11 by a motor 12 and on which the fine oil particles are stuck are installed. Further, a washing means 30 for washing the blade plates 10 and the like and a treated liquid discharging means 40 for discharging the separated oil and the washing liquid after use are installed.
Patent JP-S60252748-A (JP)
Inventor: TAKEDA KIYOSHI
IPC: D06M101/16
Filed: 1984-05-25
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H05299521-A (JP)
Title: Manufacture of semiconductor device
Inventor: MIYAJIMA MOTOMORI
IPC: H01L21/316
Filed: 1992-04-24
Abstract: PURPOSE:To completely remove the SOG film on the thickly formed part of a wafer, and both formation of the aperture part on the lower wiring layer without giving an adverse effect on the lower wiring layer and the removal of the interlayer insulating film on a removalregion are simultaneously performed in the semiconductor device manufacturing method containing a substrate surface flattening process. CONSTITUTION:This is a semiconductor device manufacturing method in which a lower wiring layer 1, which is formed on the substrate 51 of a wafer 11, is coated, an aperture part 22 is formed on the interlayer insulating film 20 on the lower wiring layer 15 after a flattened interlayer insulating film 20, containing at least a SOG film 17, has been formed, and then an upper wiring layer 23 which is connected to the lower wiring layer 15 through the intermediary of the aperture part 22 is formed. This manufacturing method contains a process in which an SOG film 17 is formed on the surface of a substrate 51 and the surface of the substrate 51 is flattened, and a process in which the SOG film 17 on the circumferential region of the wafer 11 is selectively removed by etching using the mask formed on the SOG film.
Patent JP-S5332957-A (JP)
Title: Treatment of wastewater and apparatus therefor
Inventor: SHINODA KAZUICHI
IPC: C02F1/52
Filed: 1976-09-07
Abstract: PURPOSE: To treat wastewater by a simple method, by treating wastewater according to batchwise system simultaneously with dehydration treatment by one step of agglomerates formed in wastewater. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-S59230968-A (JP)
Title: Thin metal wire feeding system
Inventor: FURUI YOSHIYUKI
IPC: B65H49/34
Filed: 1983-06-15
Abstract: PURPOSE:To eliminate the need of a clamp at the end of winding of a thin wire, obtain stabilized signals when said thin wire is vibrating, and obtain the control of feed corresponding to the amount of consumption by detecting the conducting condition between a metal bar for detecting the excessively delivered amount of the thin metal wire and a metal plate which is always brought in contact with the thin wire. CONSTITUTION:Instead of connecting the winding end of a thin metal wire, the winding end is always brought in contact with a metal plate 21 connected to zero volt, and a NOT circuit 22, a one-shot circuit 23 and an OR circuit 24, which stabilize the instability caused by the vibration that occurs when the thin metal wire 2 is brought in contact with a metal bar 4, are added. When a signal enters the input terminal 23a of the circuit 23, the low level of this signal is zero volt at which the thin metal wire 2 is in contact with the bar 4, while the high level is E volt at which they are separated from each other. Triggering occurs due to the falling of output signal from the circuit 23, one-shot signal for a time t1 is outputted and, where the signal is vibrating, triggering occurs again making the output width extended and stabilized. The output signals from the circuit 22, 23 to the circuit 24 provide a command on the rotation of a motor 9 to an amplifying section 16 only when the output signals are at the hatched lines in the figure, controlling the feeding of the thin metal wire.
Patent JP-S5732181-A (JP)
Title: Solid state image pickup device
Inventor: MATSUNAGA MASAYUKI
IPC: H04N5/335
Filed: 1980-08-06
Abstract: PURPOSE:To suppress the reduce of amount of signal charge by supplying signal charge from a source provided in a unit cell without using charge obtained from photoelectrical conversion made by incident light as the signal charge. CONSTITUTION:When an optical image is projected on a device, a photoconductive film causes polarization according to its light intensity distribution and the potential of a metallic electrode rises to form a channel near the insulating film interface of a semiconductor substrate. Then, when a transfer electrode 18 is turned on, charge which corresponds to the polarization of the photoconductive film is transferred to a vertical-transfer-charge transfer element 16. As well as the operation of an interline type charge transfer element area sensor, the signal charge is transferred through the charge transfer element 16 and a horizontal-transfer-charge transfer element 20 successively and then amplified by an output transistor 21. At this time, after the charge is transferred to the charge transfer element 16, the potential of a transparent electrode is held negative for a certain time to depolarize the photoconductive film.