Patent GB-882751-A (GB)
Title: Error detection system
IPC: G06F7/50
Filed: 1959-08-05
Abstract: 882,751. Checking arithmetic operations. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 5, 1959 [Aug. 5, 1958], No. 26810/59. Class 106 (1). The arithmetic section of a digital computer includes a register which stores at least a part of the answer of an operation and the parity of digits in the register representing the answer is compared with the expected parity which is computed from the parities of the operands and the parity of digits entering or leaving the register during the operation. The section includes A and B registers and an accumulator register each, as shown, comprising flip-flops and having a capacity of fifteen bits plus sign and parity bits. A parity bit is the bit necessary that there should be an odd number of binary ones in the register. Bits 1 to 14 are shown as stored in representative bit-X flip-flops 13, 23 and 33. An adding circuit has sixteen stages 20, 30, 40 and is of the ripple type in which the sum digit of an order is shifted to the right, this being compensated by a subsequent shift to the left in addition or subtraction. There is also a carry storage register comprising sixteen flip-flops of which the first fourteen are characterized by flip-flop 53 and flip-flops 54 and 55 receive respectively the carries from the bit-15 adder 40 and the input to the adding circuit. These serve as modulo-2 counters of the carries from each stage of the adding circuit. Summing circuits 56, 57 develop an indication of whether the sum of all the carries are odd or even and the output of circuit 56 is applied to a flip-flop 63, delay 61 ensuring that the summing circuits operate only when an arithmetic operation has finished. Addition.-The augend is entered into the accumulator, the addend into the A register, together with appropriate parity bits. A " start add " pulse is applied to gate 65 which, if the A register parity flip-flop 11 is set at 0 passes the signal to the accumulator register parity flip-flop 21 to switch it. If the total number of carries during the addition operation is odd an " end add " signal is gated through gate 68 to switch the accumulator parity flipflop. Comparison of the actual parity of the accumulator digits with that of the expected parity, now set in parity flip-flop 21 may be made in the circuit shown in Fig. 4. A signal on line 123 appears as an output from sum circuit 126. If the sum of the digits in the accumulator flip-flops 22 to 24 is even (odd) and the parity flip-flop 21 registers a computed parity 0 (1) then the output of circuit 126 is zero and an error is indicated. Subtraction.-This is identical with addition, the ones complement of the subtrahend being entered into the A register and the minuend into the accumulator. Multiplication.-The multiplicand is entered into the A register and the multiplier into the B register, the product expanding from the accumulator into the latter as the operation proceeds. Flip-flop 76 counts the one bits shifted into the B register since its complement input is connected to the 1-output of the bit-15 adder 40. Initially the accumulator parity flip-flop 21 is set at 0, and the B-register parity flip-flop 31 and flip-flop 76 set at 1 by a " start multiply " signal on line 83. If an even number of one bits is shifted into the B- register the 0 output of flip-flop 76 is gated to flip-flop 31 to reset it to zero by an " end multiply " signal on line 84. The " start multiply " signal is also gated to set the parity flip-flop 21 at 1 if the parity of the operands in either or both the A and B registers is odd. The carries during multiplication are counted by flip-flop 63 and the outputs of flip-flops 63 and 76 are summed in circuit 75. If the sum is 1, indicating that an odd number of one bits have either been shifted from the accumulator or carried during the operation and " end multiply " signal on line 84 is gated to the parity bit flip-flop 21 to switch it. The comparison with the answer in the accumulator is made as for addition. Division.-Initially the dividend is in the accumulator and B register, the divisor in the A-register, but the quotient digits produced by successive subtraction are entered into the B- register from the sign-bit adder 20 to bit-15 flip-flop 34 and the dividend is concurrently shifted left. The " start divide " signal on line 85 sets the parity flip-flop 31 to " 1 " and thereafter ones entering the bit-15 flip-flop switch flip-flop 31. To determine the parity of the remainder standing in the accumulator at the end of the operation: (a) if the B register parity flip-flop 31 initially contains a zero flip-flop 21 is switched by the " start divide " signal gated to flip-flop 21 by the 0-output of flip-flop 31-this is necessary since the number of ones shifted into the accumulator will be odd; (b) the gate 60 through which " carry 1 " signals pass to carry storage flip-flop 55 is closed-this ensures that overflow from the accumulator to the bit-15 flip-flop 34 is neglected since the partial quotient operation is performed an even number of times; (c) the carries generated within the adder during the operation are counted by flip-flop 63 and the " end divide " signal is gated to switch flipflop 21 if flip-flop 63 registers " 1 "; and (d) carries from the sign-bit adder 20 are accounted for by gating the " end divide " signal through gate 69 to switch flip-flop 21 if flip-flop 31 registers " 0." If a correction of the remainder is necessary to change it from negative to positive by adding the divisor once, the carry from the sign-bit adder is prevented, by closing gate 90, from reaching bit-15 flip-flop 34, but various corrections are effected by the " end divide correction " signal on line 87, in order that the setting of flip-flop 21 shall reflect the true expected parity of the accumulator. A check is then made by counting the number of one bits in the accumulator and B-registers.