Patent GB-1523752-A (GB)
Title: Dynamic semiconductor data stores
IPC: G11C11/401
Filed: 1975-08-18
Abstract: 1523752 Dynamic semi-conductor store SIEMENS AG 18 Aug 1975 [28 Aug 1974] 34225/75 Heading H3T In a dynamic semi-conductor store a correcting voltage is applied via a compensation capacitor to raise the voltage on a bit line to substantially equal the mid-potential between the voltages representing the binary states "1" and "0", the coupling between the compensation capacitor and the associated bit line being under the control of a respective compensation-selector line. When a word line 35 is energized an error voltage is placed on bit lines 20 via the stray capacitance 36. To avoid any influence on the evaluator circuit 2 which includes a flip-flop a similar correcting voltage is applied to the bit line 10 connected to the other input 27 of the flip-flop. It is said to be known to use a capacitor 11 grounded at one end (not shown) and coupled via a FET 12 under the control of a compensation-selector line 16. To reduce the circuitry pulse train signals are herein applied to the further terminal 111 of the capacitor. Read out commences with a signal applied to 231 to turn FET 23 on, equalizing the voltages on the bit lines 10, 20. The value, U ref , reached being in general asymmetrically placed between the "1" and "0" levels. Both compensation selector lines 16, 46 are energized and so both capacitors 11, 41 are charged to U ref . The FET 23 is turned off to enable the flip-flop, and then the lines 16,46 are deenergized leaving the capacitors 11, 41 still charged. The required word line 35 and the opposite compensation selector line 16 are energized, capacitive coupling causes the voltage on bit line 20 to rise by same amount, a pulse is then applied to the capacitor 11 at terminal 111 causing the voltage on bit line 10 to rise substantially to a level halfway between "0" and "1". A signal is applied at terminal 241 to energize the flip-flop which takes up a condition corresponding to the data stored in element 3 and which was coupled to bit line 20 via transistor 32 when the word line was energized. The read out phase is ended by deenergizing the flip-flop, the unused bit line 10 is thereby discharged to zero via the flip-flop at this instant. Instead of a separate pulse supply to the capacitor 11, this can be connected to the compensation selector line 16 (Fig. 4, not shown). In this arrangement it is preferable to charge the capacitors 11, 41 from the bit lines 10, 20 before the transistor 23 is turned on to equalize the bit line voltages. The requirement for two pulses on the compensation selector lines during readout can be reduced to one by using an FET (14, Fig. 6, not shown), as the compensation capacitance; itself possessing parasitic capacitance (15). In this arrangement the bit lines (10, 20) are connected via the FET (23) to have equal potential, and following the turn off of the FET (23) the compensation selection line (16) and word line (35) are energized, and following the rise of the opposite word line (10) to the middle voltage between "0" and "1" the flip-flop is energized via a terminal (241) to take up the state corresponding to the voltage in the storage element (32). Formulae are given for the ratio between the compensation capacitor 11 and the stray capacitance 101 of the bit line 10 not connected with the storage element to be interrogated. It is stated that a metal-gate technique of construction is of particular advantage.