Patent SG-11201805857U-A (SG)
Title: High voltage logic circuit
Inventor: CHOI PILSOON
IPC: H03K19/20
Filed: 2017-02-16
Abstract: HighVoltage System (e.g. Stepping Motor) GaN+ MOS High voltage output Logic level () INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 24 August 2017 (24.08.2017) WIPO I PCT (10) International Publication Number WO 2017/142482 Al (51) International Patent Classification: H03K 19/20 (2006.01) H01L 29/16 (2006.01) H01L 21/18 (2006.01) H01L 29/20 (2006.01) H01L 21/335 (2006.01) H01L 29/68 (2006.01) H01L 21/8258 (2006.01) H01L 29/772 (2006.01) H01L 27/06 (2006.01) H03K 19/0175 (2006.01) H01L 27/085 (2006.01) H03K 19/094 (2006.01) H01L 27/092 (2006.01) (21) International Application Number: PCT/SG2017/050070 (22) International Filing Date: 16 February 2017 (16.02.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/296,702 18 February 2016 (18.02.2016) US (71) Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY [US/US]; 77 Massachusetts Avenue, Cambridge, Massachusetts 02139 (US). NANYANG TECHNOLOGICAL UNIVERSITY [SG/SG]; 50 Nan- yang Avenue, Singapore 639798 (SG). (72) Inventors: CHOI, Pilsoon; c/o Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Mas- sachusetts 02139 (US). BOON, Chirn-Chye; c/o Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (SG). PEH, Li-Shivan; c/o Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts 02139 (US). (74) Agent: VIERING, JENTSCHURA & PARTNER LLP; P.O Box 1088, Rochor Post Office, Rochor Road, Singa- pore 911833 (SG). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). [Continued on next page] (54) Title: HIGH VOLTAGE LOGIC CIRCUIT 11111111111111011101111111111101011111011101011111010111111101011111111111110111111 Logic supply voltage (e.g. 3.3V) High supply voltage High 304 (e g • 30V) voltage 5 302 driver 300 Digital Logic Circuit (e.g. Microcontroller) Single chip W O 20 17 / 14248 2 Al Figure 3 (57) : A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semi- conductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input. WO 2017/142482 Al 1#11101M011111 11111111ME301011101011111010EMEMOIS Published: — with international search report (Art. 21(3))