Patent GB-1237977-A (GB)
IPC: H04L25/03
Filed: 1969-05-08
Abstract: 1,237,977. Adaptive equalizers. NORTH AMERICAN ROCKWELL CORP. 8 May, 1969 [24 June, 1968], No. 23495/69. Heading H4R. In an adaptive equalizer digital values of the most recently received signals, e.g. d i-1  d i-2  &c., are modified by the impulse response of the transmission channel sampled at data rate, e.g. h 0 , h 1 , h 2 , &c., and the actual digital signal received, x i  is modified in accordance with the expression to determine a corrected value x ic  for the received digital signal from which the most likely digital value can be estimated. From the estimated digital value the error in the corrected received digital signal can be calculated and used to adjust the impulse response values used on subsequent computations. As described, Fig. 4, the received signal, which may be a multilevel signal, is sampled and converted to digital form and fed to the input gate 47. The impulse response of the transmission channel is stored in a shift register 42, each sample value being stored as an 11 bit number, and the values of the previously received signals is stored in the shift register 43, each stage storing a number of bits equal to the data bits encoded in each transmitted data symbol, e.g. 4. In addition a shift register 44 is provided to store one impulse response value with an extra three digit positions used during the computation, and a further stage 45 is provided to store the digit value currently being operated upon. During operation initially the input signal is fed from the A to D converter 41 into the accumulator 46, then the previously received digital values from shift register 43 multiplied by the appropriate sample of the channel impulse response from register 42 are fed, with negative sign, into accumulator 46 to be subtracted from the input signal sample value. When the six prior digital values have been fed into the accumulator the resulting signal is sampled and stored for further use in the temporary register 48 and also fed to the slicer 52 which determines the most likely digital value for the last received digital signal, this is fed into the shift register 43 and the oldest value therein is eliminated. The value from the temporary store is then shifted back into the accumulator 46, via gate 47, and the just determined digital value multiplied by the appropriate channel response sample is subtracted therefrom in order to obtain the residual value or error in the corrected value of the received digital signal. The sign of this residual value is determined and transferred to the updown counter 49 to increment one sample of the channel impulse response in a direction which tends to reduce the value of the residual value. One sample of the impulse response is incremented on each frame, relating to one input signal sample, the samples being treated sequentially. The multiplication of the impulse response value by the stored data signal is accomplished by utilizing a shift register 44 having three more stages than there are digits in the impulse response sample. Initially the response sample is in the left most stages of the register and is added or subtracted from the value in the accumulator according as the first digit of the data signal is plus or minus one. The response sample is then shifted one stage to the right and added or subtracted according to the value of the second digit of the data signal, similarly for the third and fourth digits of the data signal. For slicing the corrected value of the digital signal to determine the most likely digital value for the received signal an operation similar to successive approximation a to d conversion is carried out using the same shift and add operations as have been described above. Since the slicing comparison levels are derived from the stored impulse response a.q.c. is provided.