Patent GB-1447535-A (GB)
Title: Digital diversity combiner
IPC: H04L1/06
Filed: 1973-11-14
Abstract: 1447535 Diversity combiner INTERNATIONAL STANDARD ELECTRIC CORP 14 Nov 1973 [28 Nov 1972] 52776/73 Heading H4L In a diversity combiner of the predetection maximal ratio (or "ratio squared") type and suitable for phase shift keyed (PSK) digital data signals, the signals received from the various diversity paths are resolved into inphase and quadrature components, these quadrature components are digitized for subsequent weighting and then combining by digital techniques. The need for phase locked loops, voltage controlled crystal oscillators and other analogue components is thereby eliminated. Modulated RF signals on the N different paths of a space or angle diversity system are received at antennae 1 of separate channels, one for each path, and first passed to a down converter 3, the converter for each channel producing a modulated signal at a common IF. The IF signals are then passed to a "demodulator unit", in which in-phase and quadrature signals are produced by means of two balanced mixers to which the IF signals are applied and which respectively receive a signal from the IF oscillator directly and a signal from the IF oscillator phase shifted 90 degrees (Fig. 2, not shown). These in phase and quadrature signals are then converted to digital form using conventional A-D converters (Fig. 3, not shown). The digitized in-phase and quadrature signals pass to a channel control unit 8 in which the average values of the in-phase and quadrature signals are evaluated, after "dehopping" by reference to the data output d k  to remove the effect of modulation on the average, and these values are used to control a multiplier 10 to weight the in-phase and quadrature signals from the demodulator unit 7. The weighted in-phase and quadrature signals are passed to a digital combiner 11 wherein all in-phase and quadrature signals are respectively added in pairs until all channels are combined. The most significant bits of the digital outputs from the combiner 11 (which are the sign bits and thus represent the input in binary form) are applied to a digital circuit 12 which inter alia produces an output signal representing the transmitted data. To keep the strongest signals within the operating range of the A-D converters a common AGC voltage is applied to all the IF amplifiers, the amount being determined in unit 14 by the maximum of the maximal ratio weights at all the units 8. In order to bridge fades (of up to 10 sees. or more) a clock recovery circuit 13 is provided and the clock is corrected whenever the combined signal (from unit 11) is strong enough to accurately determine the clock phase error. Appropriate logic arrangements including full and half adders and complementors in standard chip form are described to serve as the weight averaging circuitry 9 (Figs. 4A, 4B, 4C, not shown) and multiplier 10 (Figs. 5 and 6, not shown). An assembly of tiers of full adders provides the combiner circuit 11 (Figs. 7A, 7B, not shown). Clock signals for controlling the A-D converter operation and all the logic operations are derived from the clock circuitry 13 which incorporates a 32 MHz oscillator 16, the output of which is divided down through several stages to 1 MHz. Signals from the combiner 11 are applied to arrangements of registers, adders and selectors in unit 15 (Figs. 8A, 8B, not shown) operated in accordance with the clock. If the output from the final register of the arrangement exceeds a given threshold or is below another lower threshold the clock is too fast, or too slow respectively and clock pulses must be deleted or added using appropriate logic (Fig. 8B). AGC must be applied to all channels in accordance with the strongest channel signal, and to achieve this, appropriate logic circuitry for selecting the strongest signal and converting it to analogue form is provided (Figs. 9A, 9B, not shown).