Patent SG-11201805988V-A (SG)
Title: Providing scalable dynamic random access memory (dram) cache management using dram cache indicator caches
Inventor: VAIDHYANATHAN NATARAJAN
IPC: G06F12/0893
Filed: 2017-02-01
Abstract: LWAY (0) 40(0) 136(C) 140(C • .1_ WAY ADDRESS : DATA , • 1 28 DRAM CACHE MANAGEMENT CIRC I LOAD BALANCING CIRCUIT RAM CACHE I115 INDICATOR CATOR CACHE YSTEM MEMORY DRA MEMORY LINE [ MEMORY LINE 116 MASTER TABLE 120(0) 110 134 138(0) COMPUTE UNE 1303'(0) 40' 0136'(0)' 140'(C) 122(0) 122(Z) 112 CACH MEMORY READ REQUEST READ' 26 ADDRESS HIGH-BANDWIDTH MEMORY DRAM CACHE (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 31 August 2017 (31.08.2017) WIPO I PCT (10) International Publication Number WO 2017/146882 Al 1111111111111101110111111111110101111101110101111111111H1101011111111111110111111 (51) International Patent Classification: GOOF 12/0893 (2016.01) (21) International Application Number: PCT/US2017/016005 (22) International Filing Date: 1 February 2017 (01.02.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/298,088 22 February 2016 (22.02.2016) US 15/228,320 4 August 2016 (04.08.2016) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventors: VAIDHYANATHAN, Natarajan; 5775 More- house Drive, San Diego, California 92121 (US). HEDDES, Mattheus, Cornelis Antonius Adrianus; 5775 Morehouse Drive, San Diego, California 92121 (US). VERRILLI, Colin, Beaton; 5775 Morehouse Drive, San Diego, California 92121 (US). ( 74 ) Agent: TERRANOVA, Steven, N.; WITHROW & TER- RANOVA, PLLC, 106 Pinedale Springs Way, Cary, North Carolina 27511 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Decl arations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.1700) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17 (iii)) [Continued on next page] (54) Title: PROVIDING SCALABLE DYNAMIC RANDOM ACCESS MEMORY (DRAM) CACHE MANAGEMENT USING = DRAM CACHE INDICATOR CACHES PROCESSOR-BASED SYSTEM 106 MEMORY WRITE REQUEST FIG. 'I 120(X) (57) : Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in high-band- width memory. The DRAM cache management circuit comprises a DRAM cache indicator cache, which stores master table entries that are read from a master table in a system memory DRAM and that contain DRAM cache indicators. The DRAM cache indicators enable the DRAM cache management circuit to determine whether a memory line in the system memory DRAM is cached in the DRAM cache of high-bandwidth memory, and, if so, in which way of the DRAM cache the memory line is stored. Based on the DRAM cache indicator cache, the DRAM cache management circuit may determine whether to employ the DRAM cache and/or the system memory DRAM to perform a memory access operation in an optimal manner. W O 20 17 / 14688 2 Al (0) (X) 118(0) 118(M) WO 2017/146882 Al 1#1101M011111 1111NMEM3010111111011111111111111111111111111111111111 Published: — with international search report (Art. 21(3))