Patent GB-938954-A (GB)
Title: Circuit characteristic compensating system
Inventor: MACINTYRE ROBERT MARSH
IPC: H03F3/40
Filed: 1960-01-27
Abstract: 938,954. Electric selective signalling systems. THOMPSON RAMO WOOLDRIDGE Inc. Jan. 27, 1960, No. 2999/60. Class 40 (1). [Also in Group XL (c)] A system for compensating for changes in the characteristic of a circuit comprises sensing means responsive to the output of the circuit at the time when that output should have a predetermined value to provide an error signal representing in magnitude and polarity the magnitude and sign of any error in the output of the circuit, and first and second switching means opened by error signals of the two polarities respectively to pass charging and discharging currents from two sources of potential (one negative, one positive) to an electrical energy storage means and a connection from the storage means to the circuit by way of impedance means adapted to apply a compensating signal to the circuit such that its output assumes the predetermined value. In an embodiment, circuit 100, Fig. 1, has a characteristic requiring compensation. It receives input signal I via switch 10I or a reference signal RR via switch 10R, the switches being operated alternately by control signals. When the reference signal R1 is applied to the circuit 100 the output is applied to a detector 200 simultaneously with a second reference signal R2 via a gate 10G. The difference output is applied via switch 201 to compensation signal generator 300, described below with reference to Fig. 3, which is coupled to a compensating circuit 400 which in turn controls the circuit 100 so as to correct any error. Switch 202 provides for shortcircuiting detector 200 during signal periods. The arrangement may be used for compensating for drift in an operational amplifier (see Group XL (c)), using a compensation signal generator 300, Fig. 3, of the type disclosed in Specification 905,953. In this a capacitor 330 is charged from a positive source and discharged from a negative source under control of a pair of transistor switches, to a potential corresponding to any drift in the amplifier 100, and a compensating potential fed to the input of the amplifier. Current weighting in a digital decoding circuit. Current switches 100-N &c., Fig. 4, correspond to the N digits of a binary number stored in a register 600. As shown, the currents from switches 100-N, 100-N-1, and 100-N-2 are to be adjusted, and for this purpose each is coupled to an associated compensating circuit 400-N &c. each of which is fed from a corresponding compensating signal generator 300-N &c. of the type described with reference to Fig. 3. Circuits 300-N &c. receive input signals through associated switches 20-N &c. each of which receives the output signal of a detector 200 coupled to the combined output of switches 100-N &c. Detector 200 also receives the output signal of an operational amplifier 110 which receives input reference signals RN &c. corresponding to the desired current weightings, via switches 10-N &c. The operation of the circuit is controlled by signals from a control circuit 700. Thus, if, e.g., current switch 100-N is turned on, weighting reference signal RN is applied via switch 100-N and operational amplifier 110 to detector 200 which produces a difference output indicative of the difference between the output current from the current switch 100-N and the desired reference current RN. This difference output is the applied through switch 20-N to compensation signal generator 300-N which produces a corresponding change in level of its output signal, and this is fed over compensating circuit 400 to correct the output from current switch 100-N. Regulating the bias level of a circuit. Circuit 100, Fig. 5, includes an amplifier A having a bias level adjusted by a network comprising resistors R5, R6 which so bias the amplifier that a digital register 600 does not receive an input control signal until the output of detector 200 reaches a predetermined level; e.g. one half the least significant digit value of register 600. This value is applied from source RB to operational amplifier 110 which feeds one input to detector 200; this obtains a comparison input comprising the analogue equivalent from digital register 600 via decoding network 120. The difference output from detector 200 is fed via switch 201 to compensation signal generator 300, of the type described with reference to Fig. 3, which generates the required bias level for application to register R6. Adjustment of the voltage reference level of a circuit. The difference between the current originating from source 100, Fig. 6, via current switch 120 and that derived from an external reference source 105 via operational amplifier 110 is obtained in detector 200 and applied to compensation signal generator 300 which varies the reference level of source 100 until the two currents are substantially equal. Circuit performing digital to analogue conversion and vice-versa. In digital to analogue conversion digital input signals are applied to a register 600, Fig. 8, and converted to equivalent analogue signals through a decoding circuit 100-3. This controls detector 200 which also receives signal from an input amplifier 100-1. Output signal from detector 200 is applied to control control circuit 350 which selects one of a plurality of output signal generators 30-1 to 30-N. The selected output signal generator is caused to increase or decrease its signal output value until it corresponds to the analogue equivalent of the digital input signal, signals from the chosen one of the generators 30 being applied through the corresponding one of switches 40-1 to 40-N to the input circuit of amplifier 100-1. The detector 200 produces a signal indicative of any difference between the analogue equivalent to the digital input and the output of the chosen circuit 30, which is effective to change the level of the output signal until it is equal to the analogue equivalent of the digital input to circuit 600. In analogue to digital conversion any one of a plurality of input signals I1 &c. may be applied to the input amplifier 100-1 through corresponding input switches 10-1 &c. In addition switches 50-1 to 50-4 are provided for the application of reference signals R1 to R4 to amplifier 100-1. The input signal remains applied to amplifier 100-1 during the time that register 600 is changed in state through a control circuit 650 which receives from detector 200 an output signal indicating the difference between the input signal level and the analogue equivalent of the setting of the register 600, derived from decoding circuit 100-3. Circuit 650 is biased from compensating circuit 400-4 so that no change is made in register 600 until the difference between the input signal to amplifier 100-1 and the analogue equivalent of the digital setting of register 600 is greater than the least significant digital value, in analogue terms. Compensation signal generators 300-1 to 300-4, each of the type described with reference to Fig. 3, are provided for each of the compensating operations to be performed, being associated with corresponding compensating circuits 400-1 to 400-4. Circuits 300-1 and 400-1 adjust the input amplifier 100-1 at the time a true reference signal R1 is applied; circuits 300-2 and 400-2 control the value of the source 100-2 at the time true reference signal R2 is applied, while circuits 300-3 and 400-3 adjust the operating conditions of decoding circuit 100-3 at the time a reference signal R3 is applied to amplifier 100-1, to adjust any one of a plurality of weighting circuits within decoding circuit 100-3. Circuits 300-4 and 400-4 provide adjustment of a bias control circuit 650 upon application of a reference signal R4. The invention may also be applied to correcting the frequency of oscillators (see Group XL (c)).