baber/WOPTO huggingface dataset:
Patent JP-S58144915-A (JP)
Title: By-pass device for alarm device
Inventor: HASEGAWA MASAKAZU
IPC: G05B23/02
Filed: 1982-02-23
Abstract: PURPOSE:To enable the detection for a wiring disconnection when the trip point of an alarm device is tested, by controlling the duty with which the output of the alarm device is validated by means of a by-pass device and therefore by holding a load relay in a non-energized state regardless of the output of the alarm device. CONSTITUTION:When a by-pass switch 7 is turned toward (b) when a test is performed, a driving circuit 12 turns on and off a transistor TR13. A variable signal is fed to a comparator 2 from a test signal generator 10. Then a TR3 repeats intermittently ON and OFF in case the output of the comparator 2 is set at H, and the input of an output detector 9 is turned into a pulse signal. No pulse signal emerges at the input of the detector 9 regardless of ON or OFF of the TR3 in the case of a disconnection of the wiring between an alarm device 1 and a relay 5, a disconnection of the coil of the relay 5 and the omission of a power supply 4 respectively. This means that the trip point of the comparator 2 gets apparently out of the request value. Thus an inspector is urged to study the factor of the fault.
Patent JP-H03234619-A (JP)
Title: Manufacture of thermosetting resin decorative board
Inventor: NAKAGAWA HITOSHI
IPC: B32B33/00
Filed: 1990-02-13
Abstract: PURPOSE:To reproduce the recesses and projections of a shaped film with a high fidelity and permit the shaping of fine emboss, such as precision ten thousand lines, on that surface under lustered condition by a method wherein a thermoplastic resin film, provided with specified properties, is used between thermosetting resin impregnated paper and the shaped film or the like. CONSTITUTION:When thermosetting resin impregnated paper is pinched between hot plates and hot press molding is effected at a temperature Tp together with a base material laminated in accordance with necessity, a thermoplastic resin film and a shaped film or an embossing plate, whose thermal deformation temperature Tt (under the load of JIS-K-7202, 4.6kg) is lower than the temperature Tp and provided with a surface luster degree after hot-press molding (HIS-Z-8741, 75 deg. mirror luster) of 30-100, are superposed sequentially on the surface of the thermosetting resin impregnated paper to mold through hot-press molding together. Thereafter, the thermoplastic resin film is removed from a mold together with the shaped film or the embossing plate, then, recesses and projections, corresponding to the pattern of a disired fine emboss, can be shaped on the thermoplastic resin layer on the surface of the shaped film or the embossing plate.
Patent JP-S62188219-A (JP)
Title: Vapor growth unit
Inventor: KANO TSUNEO
IPC: H01L21/31
Filed: 1986-02-13
Abstract: PURPOSE:To enable a film to grow on a wafer with a uniform thickness and without any variance in thickness distribution over the wafer, by controlling the temperature distribution in the wafer. CONSTITUTION:Each of heaters 9 is driven by a temperature control command given by a temperature controller 10 and the center of a semiconductor wafer 3 is heated by the heater. During the heating, the periphery of the wafer 3 is not heated by the heater 9 because it is contacted with the peripheral edge 4 of a screen 4a. Consequently, the semiconductor wafer 3 has a higher tempera ture in the central region than in the peripheral region thereof by the driving of the heater 9. The peripheral region of the wafer 3, having a relatively low temperature than the central region thereof, delays reacting with a reaction gas consumes less gas. Thus, the gas is allowed to flow to the center of the wafer. As a result, a higher concentration of the gas is held in the central region than in the peripheral region of the wafer 3 and the central region reacts with gas having such higher concentration.
Patent JP-S59187411-A (JP)
Inventor: RONARUDO ERU NOIMIYURAA
IPC: B23C5/22
Filed: 1984-02-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H04269504-A (JP)
Title: Manufacture of building board
Inventor: YAMAGUCHI TSUTOMU
IPC: B27D5/00
Filed: 1991-02-25
Abstract: PURPOSE:To increase the assembly accuracy of woody pieces, assemble the woody pieces of different colors and upgrade the design properties. CONSTITUTION:A plurality of color coated woody pieces 1 are disposed in the flat plate shape. The same are assembled by pressing from the four sides by a piece assembly device to form a piece assembly 2. Then, the piece assembly 2 is bonded with a base 3 like a veneer actually processed.
Patent JP-S59156157-A (JP)
Title: Constant-current circuit
Inventor: KOUNO MICHIO
IPC: H02M3/28
Filed: 1983-02-24
Abstract: PURPOSE:To simplify a constant-current circuit and to reduce the cost by commonly controlling the outputs of a plurality of resonance type constant-current converters by a control circuit. CONSTITUTION:Resonance type constant-current converters CONVa-CONVm respectively convert DC inputs inputted from input terminals IN1-INm via an inverter 1 into AC, and the output of the inverter 1 is inputted through a transformer T to a resonance circuit 2. The output of the circuit 2 is outputted through a rectifier 3 and a smoothing circuit 4. The output current is detected by an output current detector 9, and the output is inputted to a controller CONT. The controller CONT compares by an operational amplifier AMP the input with the reference voltage, and controls the conductivity of a transistor Tr in response to the compared result. A V/F converter 7 controls the frequency of the inverter 1 in response to the output of a current/voltage converter 8.
Patent JP-H07240566-A (JP)
Title: Printed-wiring board and its outward-form working method
Inventor: ANDO MASATOSHI
IPC: H05K3/00
Filed: 1994-02-28
Abstract: PURPOSE:To provide a printed-wiring board which can be separated easily without using a jig for exclusive use when a product and a throwaway board are separated in the printed-wiring board which is composed of the product and of the throwaway board and to provide its outward-form working method. CONSTITUTION:A slit 3 is formed between a product area 1 and a throwaway- board area 2, and the product area 1 and the throwaway-board area 2 are connected by connection parts 4. When the connection parts 4 are arranged individually in two places in which a straight line A-A' passing the center of gravity 5 of the product area 1 and the slit line 3 are crossed, the product area 1 and the throwaway-board area 2 can be separated easily without using a jig for exclusive use when a turning force which uses the connection parts 4 as an axis is applied to the product area 1.
Patent JP-H08203920-A (JP)
Title: Compound semiconductor heterojunction bipolar transistor
Inventor: SUGAWARA HIROHIKO
IPC: H01L21/331
Filed: 1995-01-26
Abstract: PURPOSE: To enable the second emitter layer part to be easily and locally formed on the first emitter layer part leaving a surface inert region intact by a method wherein the fourth emitter layer part of lower carrier concentration is provided on the upper part of the first emitter layer part. CONSTITUTION: Within the title bipolar transistor provided with a semiinsulating substrate 1, a collector layer 2 formed on the substrate 1, a base layer 3 and an emitter layer 4 having the first emitter layer part 41 and the second emitter layer part 42 furthermore, a collector electrode 52 on the external collector region 24 of the collector layer 2, a base electrode 53 on the external base region 34 of the base layer 3 and an emitter electrode 54 on the second emitter layer 42, the first emitter layer 41 is provided with the third emitter layer part 43 forming a heterojunction and the fourth emitter layer part 44 formed on the emitter layer 43 and in lower carrier concentration than that of the third emitter layer 43.
Patent JP-S60173590-A (JP)
Inventor: ASOU SATOSHI
IPC: G09G5/02
Filed: 1984-02-20
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0323328-A (JP)
Title: Fuel feed control device for engine
Inventor: DANNO YOSHIRO
IPC: F02D23/00
Filed: 1990-02-09
Abstract: PURPOSE:To improve fuel consumption and durability of a catalyst by providing a fuel limit means to control the feed of fuel from a fuel feed device in priority to an output from a fuel fundamental amount set means when it is decided that load information is brought into a state in which a load is reduced to a value lower than a set value. CONSTITUTION:In running of an engine E, a controller 29 inputs output signals from an airflow sensor 16, a number of revolutions sensor 17, an intake air temperature sensor 18, and an atmospheric pressure sensor 19, and computes a fundamental injection amount from intake air amount information and information on the number of revolutions of an engine. An atmospheric pressure correction factor, an intake air temperature correction factor, and a target air-fuel ratio are computed, and through correction of a fundamental injection amount based on the computing results, a fuel injection amount is calculated, and drive of an electromagnetic type fuel injection valve 9 is controlled. In this case, from intake air amount information and intake air temperature information, load information by means of which the load state of an engine is indicated is calculated. When the load information is brought into a state in which a load is reduced to a value lower than a set value, fuel limitation, e.g. fuel cut, is executed.
Patent JP-H03233656-A (JP)
Title: Loading device
Inventor: KANO JUICHI
IPC: G06F13/00
Filed: 1990-02-08
Abstract: PURPOSE:To shorten the loading time of a communication control equipment by utilizing a storage device which data can be accessed from both a data processor and the communication control equipment. CONSTITUTION:A storage device 20 is provided so that the data can be accessed from a data processor 1 and a communication control equipment 10, and the data processor 1 stores information, which is required for generating the system of the communication control equipment 10, into the newly provided storage device 20 and applies a loading instruction to the communication control equipment 10. Corresponding to this loading instruction, the communication control equipment 10 reads out the information, which is required for generating the system of the equipment 10 itself, from the storage device 20 and finishes loading. Thus, at the time of loading, the time for the data processor to read out the information from the storage device can be saved.
Patent JP-S61191715-A (JP)
Title: Method of building underground continuous wall in pile support building having underground floor and cast-in-place concrete pile
Inventor: AIDA JUNRO
IPC: E02D5/18
Filed: 1985-02-18
Abstract: PURPOSE:To reduce a cost, by a method wherein a reinforcing cage for an underground continuous wall and a reinforcing cage for a cast-in-place concrete pile are erected after partition are installed so that concrete is prevented from entering around a post-construction underground body part. CONSTITUTION:A reinforcing cage 7a for an underground wall is overlapped with a reinforcing cage 8a for a cast-in-place concrete pile for integral formation to form a reinforcing cage 9a, and partitions 10 and 11 are installed so that concrete is prevented from entering around a joint between post-construction underground body parts. After the reinforcing cage 9a is erected in an excavated hole 9, concrete is placed. This enables building of a concrete pile simultaneously with placing of concrete for a continuous wall, resulting in possibility to eliminate a work to refill with excavated soil and reexcavate a ground after formation of the concrete pile. Further, this enables reduction of the degree of need for reinforcement of an underbeam.
Patent JP-H06245500-A (JP)
Title: High-voltage power supply circuit
Inventor: DOI YOSHIAKI
IPC: H02M7/48
Filed: 1993-02-19
Abstract: PURPOSE:To provide a high-voltage power supply circuit, which can readily suppress the load fluctuation of the output voltage with the small scale and the low loss and to apply the high-voltage power supply circuit to for a traveling-wave tuber. CONSTITUTION:A high-voltage power supply circuit has a feedback-voltage control means. The feedback-voltage control means has a bleeder circuit 8, whose one end is connected to a bleeder resistor 18, and a capacitor 7 for peak charge. The bleeder circuit 8, which is connected to the bleeder circuit resistor 18, is turned ON and OFF in association with the ON/OFF of an anode power supply 4. When the anode power supply is ON, the bleeder resistor 18 is energized, and the feedback voltage is decreased. The capacitor 7 for peak charge feeds back the voltage, which is higher than the feedback voltage, when the anode power supply 4 is OFF.
Patent JP-S60175474-A (JP)
Title: Dither mechanism
Inventor: HOUJIYOU TAKESHI
IPC: G01C19/00
Filed: 1984-02-20
Abstract: PURPOSE:To increase the length of a flexible portion by planting two fixing pins on a base of a laser gyro, inserting a thin flexible member, a spacer and a thick flexible member to the pins, integrally coupling them, thereby comparing the size of the entire dither mechanism. CONSTITUTION:Two fixing pins 12-1, 12-1' having threaded holes are planted to a base 13 of a laser gyro. The holes 14-1, 14-1' of thin disc-shaped flexible members 12-2, 12-2' and holes 16-1, 16-2 of thick disc-shaped flexible members 12-3 are inserted to the pins 12-1, 12-1'. In this case, the member 12-3 is interposed between the thin flexible members 12-2 and 12-2', and a spacer 12-4 is interposed therebetween. Thereafter, screws 12-5, 12-5' are screwed into the threaded holes of the pins 12-1, 12-1', thereby integrally coupling the members.
Patent JP-S61189885-A (JP)
Inventor: JIEROOMU ETSUCHI REMERUSON
IPC: B23K26/00
Filed: 1985-02-18
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H03234118-A (JP)
Title: Logic circuit
Inventor: ANDO KOICHI
IPC: H03K19/08
Filed: 1990-02-08
Abstract: PURPOSE:To discharge a load capacitance at a high speed and to shorten the falling time of an output signal by supplying all of discharge current from the load capacitance of the next stage flowing through an N-channel MOS transistor(TR) group to generate a logic to the base of a bipolar TR used for pull-down. CONSTITUTION:An inverting circuit 7 is provided, which receives the output signals of logic circuits 1-6 as input signals and the output terminal of the inverting circuit 7 is connected to the gate of an N-channel MOS TR 6. The drain terminal of the N-channel MOS TR 6 is connected to the base of a N- channel MOS TR 4 at pull-down side and the source of the N-channel MOS TR 6 is connected to ground. Thus, the base current of the N-channel MOS TR 4 is increased to attain high speed operation with high speed charge/ discharge utilizing high current amplifier capability of the N-channel MOS TR 4.
Patent JP-S60177505-A (JP)
Inventor: NAKAO KENICHIROU
IPC: C21D1/26
Filed: 1984-02-22
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S62187632-A (JP)
Title: Installation structure for garnish
Inventor: TAMURAYA MAKOTO
IPC: F16B5/12
Filed: 1986-02-14
Abstract: PURPOSE:To facilitate the installation of a garnish in a car body, to which the garnish is installed with a clip by allowing the movement of the clip against the garnish whereby making the garnish withstand external force for separation. CONSTITUTION:A garnish 1 which is a resin molded product, is formed with both a garnish main body 5 exposing to a cabin interior and a folded section 5 where both width ends of the main body 3 are bent inward, while being installed on a car body panel 11 by a clip 9. the clip 9 is composed of a lock head 15 to be engaged with a mounting hole 13 on the car body 11 and of mounting legs 17a and 17b extending from the base of the lock head 15 to both sides along the direction of the width of the garnish 1. And the mounting legs 17a and 17b are provided with a bent section 23 in a projection form which restricts the movement of the garnish 1 in the longer direction a preset range, and with both No.1 and No.2 faces 29 and 31 to respective upper and lower surfaces of edge sections.
Patent JP-H08223248-A (JP)
Title: Polling processing system
Inventor: SAITO YOSHIYUKI
IPC: H04L29/08
Filed: 1995-02-20
Abstract: PURPOSE: To improve the processing efficiency through the processing of another channel without being monopolized by channel processing by setting an interval from the reception of polling by a secondary station side till a reply is returned in the case of the polling from a primary station to the secondary station to relieve an overhead due to consecutive idle polling. CONSTITUTION: A primary station 10 is connected to a secondary station 12 and polling is made between the primary station 10 and the secondary station 12. The primary station 10 is controlled by a polling circuit 11 of the primary station and the secondary station 12 is controlled by a polling circuit 13 of the secondary station. Then the primary station 10 sends an RR.P to the secondary station 12 and awaits a reply from the secondary station 12. If no transmission data are in existence in the secondary station 12, the secondary station 12 returns an RR.F to the primary station 10 after a designated time interval. When the data to be sent are produced in the secondary station 12 during the interval, the secondary station 12 stops the interval and sends the data immediately.
Patent JP-H02209765-A (JP)
Title: Semiconductor device
Inventor: MOTONAMI KAORU
IPC: H01L27/10
Filed: 1989-02-09
Abstract: PURPOSE:To connect a plurality of capacitors in parallel by providing a field effect transistor, the capacitors, and data wirings electrically coupled to an impurity diffused region. CONSTITUTION:A plurality of impurity diffused regions 103a, 103b having conductivity are formed at a predetermined interval on a surface region partitioned by an interelement isolating oxide film 102, and a polycrystalline silicon gate electrode 105 is formed on a semiconductor substrate 101 between the regions 103a and 103b through a gate oxide film 104 to constitute a FET T. Polycrystalline silicon capacitor electrodes 107a, 107b are formed on the substrate 101 to be electrically coupled to the region 103a, capacitor insulating films 106a-106c and a second polycrystalline silicon capacitor electrode 108 are formed on the electrode to constitute capacitors Ca-Cc. Further, the FET T and FET T are operated according to the states of the signal of data wiring 112 and the signal of the electrode 105 to store charge to become information in the capacitors C-C.
Patent JP-S62193332-A (JP)
Inventor: AUGER ROBERT
IPC: H04N7/32
Filed: 1987-02-14
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63197529-A (JP)
Title: Dispersant and dispersion solution containing same
Inventor: KARA YONOSUKE
IPC: C09D7/45
Filed: 1987-02-13
Abstract: PURPOSE:To enhance effect of dispersion to inorganic pigments by using, as a dispersant, a reaction product of polyester with acyl as an end hydroxyl group and containing esterified carboxyl and polyethylene-imine. CONSTITUTION:A dispersant is prepared by a reaction product comprising polyester with acyl as an end hydroxyl group shown by formula I (n shows 1-20, and m shows 0.1-10) and containing esterified carboxyl, and polyethylene- imine. As the reaction product of polyester with acyl end shown in formula I and polyethylene-imine, salt or amide or else a mixture of both, the preferred. The acid value of acyl end is preferably 10-120, while the average molecular weight of polyethylene-imine is preferably 300-10,000. The dispersant thus prepared is effective for giving damages to adhesiveness of a coating film with metal when used for coating metals with ink or coating material.
Patent JP-H06244981-A (JP)
Title: Mis-communication prevention system
Inventor: MIZUSHIMA MICHIKO
IPC: H04N1/00
Filed: 1993-02-19
Abstract: PURPOSE:To prevent transmission to a wrong destination by making transmission while collating an entered destination telephone number and information with a number and information registered in advance. CONSTITUTION:Registration data corresponding to a destination telephone number entered by a key entry section 7 are retrieved from a memory 5 and an entered name and a name registered in the memory 5 are collated and when it is discriminated to be correct, an original is read and sent to the destination. It is prevented that an important document or the like is sent to a wrong destination due to an entry error or a confirmation error or the like caused in a conventional facsimile equipment. Furthermore, even when a destination facsimile equipment is any equipment or a sender facsimile equipment only, mis- communication is prevented.
Patent JP-S58148335-A (JP)
Title: Defrosting control circuit of air conditioner
Inventor: NODA YOSHIYUKI
IPC: F25D21/02
Filed: 1982-02-26
Abstract: PURPOSE:To positively detect the degree of frosting to an outdoor heat exchanger by detecting a current variation value of a compressor current by a current detection circuit when a blower for the outdoor heat exchanger is stopped for a predetermined period of time or is driven at a low rotational speed. CONSTITUTION:During a room heating mode operation, the outdoor blower 4 is stopped for a predetermined period of time, and the variation of the current of the compresser 1 flowing to a current transformer 20 immediately before the stoppage of the outdoor blower 4 and the restarting of the operation, is measured. The quantity of frosting is estimated from the variation width DELTAA to carry out a defrosting control. That is, defrosting is prohibited during a time T1 from the starting of the heating mode operation, and thereafter the current sampling is carried out in a period T2 to continue the heating operation until the operation reaches the quantity of frosting requiring defrosting, that is, the current variation width DELTAA becomes smaller than the preset value Ax. Therefore, it is possible to set the quantity of frosting upon entering the defrosting operation at a substantially constant value, and hence the defrosting operation can be carried out by the time control.
Patent JP-H07240462-A (JP)
Title: Method for repairing open circuit
Inventor: KAWAI SATORU
IPC: H01L21/768
Filed: 1994-03-01
Abstract: PURPOSE:To provide a method for repairing open circuit in which the surface of a substrate can be protected against contamination without increasing the manufacturing cost and the reliability, e.g. mechanical strength, after repair can be enhanced without complicating the process. CONSTITUTION:The method for repairing open circuit comprises a step for forming an amorphous transparent conductive film 5 on the entire surface in order to fill an open-circuited part 4 of a wiring 1 formed on a substrate, a step for crystallizing the conductive film 5 through local heat treatment, and a step for removing the conductive film 5 by etching except the crystallized conductive film 8 at the open-circuitted part 4.
Patent JP-S59158098-A (JP)
Inventor: UINFUIIRUDO WAIMAN SARISUBERI
IPC: G21B1/00
Filed: 1983-02-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。