baber/WOPTO huggingface dataset:
Patent JP-H08233887-A (JP)
Title: Apparatus for evaluating electrostatic discharge and apparatus for testing electrostatic discharge
Inventor: HARADA TAKASHI
IPC: G01R31/30
Filed: 1995-02-23
Abstract: PURPOSE: To provide a supporting tool which facilitates the specification of a circuit causing a malfunction, quantifies the influence of the malfunction and gives countermeasures for improving electrostatic immunity in a short time. CONSTITUTION: A part of a sample 2 to be measured is hit by a discharge gun 3, thereby discharging electricity. The electricity necessary for the discharging is supplied from a power source 4. The size and timing of the discharging are controlled by a control part 5. When static electricity is discharged, an impulse current flows at the surface of a metallic frame or metallic case, and a magnetic field is generated. The intensity of the magnetic field generated in the vicinity of the sample 2 is detected by a loop probe 6. The using loop probe 6 is a probe having a known calibration coefficient which is a ratio of the intensity of the magnetic field penetrating the surface of the loop and an output voltage.
Patent JP-S58153294-A (JP)
Title: Semiconductor storage device
Inventor: HIDA YOUICHI
IPC: G11C11/408
Filed: 1982-03-04
Abstract: PURPOSE:To reduce the bad influence on a memory cell under the non-selected condition, by installing a transistor whose one of the two main electrodes is connected to a word line and the other is connected to a voltage generating source which generates a prescribed voltage lower than the earthing voltage and whose gate is connected to a control signal source. CONSTITUTION:In a 2-bit memory cell, for example, one of the main electrodes of each transistor 21 and 22 of a pull-down circuit 20 is connected to a terminal 32 which is connected to a voltage generating source which generates a fixed voltage VN lower than the earthing voltage and another pull-down circuit 31 is also connected in the same way, and then, a clock signal 4' changes the ''0'' level into a high impedance without changing the timing. When this arrangement is used, the voltage of the word line of memory cells under the non-selected condition can be set to a fixed voltage lower than the earthing voltage and the influence of noises of memory cells under the selected condition can be reduced without changing the threshold voltage of switching transistors of the memory cells.
Patent JP-S61196075-A (JP)
Inventor: NOOBAATO HAAN
IPC: E04H6/42
Filed: 1986-02-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H03238859-A (JP)
Title: Semiconductor device
Inventor: ISHIHARA HIROYASU
IPC: H01L29/786
Filed: 1990-02-15
Abstract: PURPOSE:To take out ability of each MOSFET at its maximum by providing a gate electrode of a second MOSFET in contact with an upper surface and a side surface of a gate electrode of a first MOSFET and by connecting it to the gate electrode of the first MOSFET electrically. CONSTITUTION:A first MOSFET is formed on a substrate 1, whose gate electrode is formed of a first conductive substance layer 3, gate oxide film of a first insulating film 2, and source and drain of a first impurity region 4a and a second impurity region 4b, respectively. A second MOSFET is formed thereafter whose gate electrode is formed of a second conductive substance layer 5, gate oxide film of a second insulating film 6, and source and drain of a third impurity region 8a and a fourth impurity region 8b, respectively. Thereby, it is possible to change a gate length of the first MOSFET and the second MOSFET and a material of the gate electrode, thereby allowing to make the most of ability of a MOSFET.
Patent JP-H01211978-A (JP)
Title: Semiconductor device
Inventor: YAMANAKA KAZUO
IPC: H01L29/68
Filed: 1988-02-19
Abstract: PURPOSE:To optimize cost performance, by specifying the relation between the cell interval and the cell dimension of an insulating gate type bipolar transistor constituted of a plurality of polygonal cells, and defining the reference of unit pattern design. CONSTITUTION:In the title semiconductor device, the relation between the cell dimension and the cell interval of an insulating gate type bipolar transistor(IGBT) is set in an optimum value. The cell interval UGM and cell dimension (w) of the insulating gate type bipolar transistor constituted of a plurality of polygonal cells is set in a range less than or equal to 20% of the relation shown by eq.I. Thereby, the reference of design is clarified, the accuracy of design is improved, the design is facilitated, the operating area can be reduced, and the cost performance is optimized.
Patent JP-S55128238-A (JP)
Title: Electron lens device
Inventor: MATSUI ISAO
IPC: H01J37/14
Filed: 1979-03-28
Abstract: PURPOSE: To improve vacuum exhaust characteristic of the device without worsening characteristics in the electron lens system, by arranging at least one of the lenses in a plurality of stages in the periphery of a hollow conductor and forming an exposure surface area as narrowly in the vacuum as possible.  
     CONSTITUTION: Condenser lenses C1WC3 in a plurality of stages are provided in an outer cylinder 7. Only the lens C1 is exposed in the vacuum. The lenses C2, C3 are arranged out of the vacuum by sealing both ends of a hollow metallic conductor 12 with O-rings 10, 11. For the hollow metallic conductor 12 is used a thin-thickness pipe made of SUS, phosphorus bronze. For the C1 lens the hole diameter of which is smaller than the diameter of the thin-thickness pipe 12, an O-ring 9 is arranged in the gap between upper and lower magnetic poles through a guide ring 8 to cause the lens to endure the vacuum, thus to provide a surface area as narrowly exposed in the vacuum as possible. In this way, residual gas molecule can be reduced thus to improve the vacuum exhaust characteristic. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-H06247955-A (JP)
Title: Production of p-methylbenzylsuccinic anhydride
Inventor: IWANE HIROSHI
IPC: C07D307/60
Filed: 1993-02-24
Abstract: PURPOSE:To produce p-methylbenzylsuccinic anhydride useful as a raw material for 2,6-naphthalenedicarboxylic acid in high yield and selectivity. CONSTITUTION:p-Xylene is made to react with maleic anhydride in an excessive amount of the p-xylene. In the process, the reaction is carried out while keeping the maleic anhydride concentration in the solution at <=6wt.%.
Patent JP-2000233487-A (JP)
Title: Plate-making device for thermosensitive stencil plate
Inventor: OKADA TOMIYUKI
IPC: B41C1/055
Filed: 1999-02-15
Abstract: PROBLEM TO BE SOLVED: To conduct the control of histogram so as to make colors in a overprinted area to be proper colors in the plate-making unit for a thermosensitive stencil plate for a multicolor-multiple plate. SOLUTION: Inputting operation is implemented regarding the hue of ink used in a multicolor-multiple plate printing, printing density, and sampling colors corresponding thereto, and one having the most deep printing density thereof is set on a color separation circuit 36 as histogram formation sampling color. A histogram formation circuit 34 constituting an application energy control means 33 is initialized to obtain a histogram data HD of the histogram formation sampling color while reading a manuscript to subsequently be stored once in a memory 37. When plates for all colors are made, an energy control circuit 35 makes the plates while histogram control is being carried out on the basis of an application energy control signal S in accordance with the histogram data HD stored in the memory 37 and binary-coded data D3.
Patent JP-S54127694-A (JP)
Title: Silicon optical electromotive force element source
Inventor: MUROZONO MIKIO
IPC: H01M14/00
Filed: 1978-03-27
Abstract: PURPOSE: To obtain a silicon optical electromotive force element source which gives an easy control to the output voltage by making use of the forward characteristics of the diode composed of the II-VI group compound semiconductor or the III-V group compound semiconductor.  
     CONSTITUTION: One or plural units of diode 12 composed of the voltage controlling compound semiconductor (II-VI or III-V group) and featuring the fixed forward characteristics is/are connected to silicon optical electromotive force element 11 featuring the fixed area and the serial connection number. 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-S63265096-A (JP)
Inventor: YAMAI JUNICHI
IPC: E06B9/32
Filed: 1987-02-20
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H07244293-A (JP)
Title: Light valve device and display device using this device
Inventor: WADA MITSUHIRO
IPC: G02F1/1335
Filed: 1994-03-07
Abstract: PURPOSE:To reduce the size and weight of a display device and to improve a contrast by arranging a layer contg. dichromatic dye to at least either of the light incident surface and exit surface of an optical modulating means. CONSTITUTION:A GH liquid crystal panel 19 is optically coupled via a transparent body 15 to an exit side glass substrate 12 of a polymer-dispersed liquid crystal panel 14. This GH liquid crystal panel 19 is formed by sealing a GH liquid crystal layer 18 between two sheets of glass substrates 16 and 17. The GH liquid crystal 18 is prepd. by dissolving the black dichromatic dye 10 of an azo type and positive type into a nematic liquid crystal 9. Common electrode 7, 8 consisting of transparent conductive films are formed on the GH liquid crystal layer 18 side of the glass substrates 16, 17. The molecules of the nematic liquid crystal 9 are perpendicularly oriented by impressing electric fields thereto by these common electrodes 7, 8. Since the molecules of the dye 10 are oriented approximately parallel with the molecules of the nematic liquid crystals 9, the molecules of the dye 10 are also oriented nearly perpendicularly to the glass substrates 16, 17.
Patent JP-H0622637-A (JP)
Title: Device for treating threshed waste culm of combine
Inventor: SHINOZAKI EIJI
IPC: A01F12/52
Filed: 1993-02-25
Abstract: PURPOSE:To receive a discharged material from the end of a selecting device and one from the end of a threshing chamber in a treating chamber and to treat the discharged materials together. CONSTITUTION:In a combine wherein the total amount of a grain which is to be threshed supplied to a feed opening 6a at the starting end of a threshing chamber 6 internally holding a threshing cylinder 7 with a shaft, is threshed while being transported by the revolution of the threshing cylinder 7 backward in the direction of the shaft of the threshing cylinder, the threshed grain is dropped from a threshing net 8 downward and the threshed waste culms are discharged from an exhaust port 6b at the end side of the threshing chamber, a selecting device S is installed below the threshing chamber 6, the threshing cylinder 7 is extended from the rear end of the selecting device to the back and a treating chamber 11 for receiving a discharged material from the selective device S and one from the threshing chamber is laid in such a way that a cutter 9 in the treating chamber 11 faces the lower part of the end of the threshing cylinder 7.
Patent JP-H01209752-A (JP)
Title: Semiconductor integrated circuit device
Inventor: SASE RYUICHI
IPC: H01L25/18
Filed: 1988-02-17
Abstract: PURPOSE:To make switching noises small, by providing a plastic IC with a metal lead of a structure wherein the lead is branched into a plurality of leads in seeling plastic, the leads of the metal lead part are bonded, and said metal lead part and a piece of a metal lead part outside the sealing plastic form a unitary body. CONSTITUTION:An inner metal lead 2 for GND at the end pin of a plastic IC is branched into parts 2 and 7. At the same time, e.g., on a mask pattern, a GND line is branched into a GDN line 11 for an output circuit system and GND lines 12 for an input circuit system and an inner circuit system. Therefore, even if switching noises are inputted into a GND pad 5 of the output circuit system, only the small noise is inputted in a GND pad 9 in the input circuit system. When the length of the metal lead 2 from a mounting point 10 on a board to the branching point of the inner metal lead is l1 and the length to the tip of one inner metal lead 2 is l2, the noise that is inputted in the GND pad 9 in the input circuit system is expressed by vl1/l2. Therefore, the GND noise v' in the input circuit system can be made very small by adjusting l1.
Patent JP-S54128456-A (JP)
Title: Method and apparatus for manufacturing weldment
Inventor: URAYAMA TAKESHI
IPC: B23K11/02
Filed: 1978-03-30
Abstract: PURPOSE: To easily correct the wart, burr, etc., of the weld zone, and to efficiently manufacture the weldment, by squashing the undesirable projection of the weldment, formed in the weld zone, using the mutually slidable specified leveling jig.  
     CONSTITUTION: The outer conductor 1 of large diameter made of tungsten wire and the inner conductor 2 made of nickel plated iron wire are butt welded to form the weldment 9a for use of the semiconductor, having the wart or burr 3a; this weldment 9a is inserted from the entry 8a into the clearance 8 of the jig, parallelly to the axis of the roller 6. Then, the weldment 9a is bitten into the clearance 8 formed between the leveling plane 7 of the rotating roller 6 and the leveling plane 5 of the jig 4, and is gradually moved toward the exit 8b while rolling. Hereupon, since the clearance 8 is gradually narrowed toward the exit 8b, the undesirable projection like as burr, etc., formed in the weld zone 3a is gradually squashed, and the weldment 9b, whose weld zone 3b is made into a diameter approximately equal to the diameter of the outer conductor 1, can be manufactured. 
     COPYRIGHT: (C)1979,JPO&Japio
Patent JP-H10231565-A (JP)
Title: Sound insulating panel
Inventor: TANAKA YOSHIHIKO
IPC: E04B2/00
Filed: 1997-02-20
Abstract: PROBLEM TO BE SOLVED: To provide a sound insulating panel by which sound insulating performance is improved and execution of work is facilitated. SOLUTION: A sound insulating panel is composed of an exterior wall panel 11 having an inner board material 23 provided on an outer board materior 15 through a first sound absorbing material 19, and an interior wall panel 12 disposed so as to stride over an adjacent range between the respective exterior wall panels 11. The outer board material 15 has an outer circumferential side inner surface as a fixed surface 15A to a column 10, and the inner board material 23 is jointed with the outer board material 15 at intermittent joint points. In the meanwhile, the interior wall panel 12 is provided with a second sound absorbing material 35 integrated with a board material 32 to hold the column 10.  The interior wall panel 12 is fixed on a reinforcement frame 20 provided inside the exterior wall panel 11, and in the condition where it is fixed to the reinforcement frame 20, the board material 32 of the interior wall panel 12 is kept in a noncontact state with the column 10.
Patent JP-H05235348-A (JP)
Title: Semiconductor device
Inventor: HIROTA MASAKI
IPC: H01L27/088
Filed: 1992-02-24
Abstract: PURPOSE:To provide a semiconductor device having a simple circuit for overheat protection. CONSTITUTION:A capacitor 2, whose capacitance varies with temperature, is used to vary the gate-source voltage of a MOSFET 1 so that an overheat protective function may be achieved. Specifically, if a predetermined temperature is reached, the capacitance of the capacitor 2 abruptly increases to lower the gate voltage of the MOSFET 1. As a result, the MOSFET is turned off, and thus temperature is lowered.
Patent JP-S60182667-A (JP)
Title: Manufacture of unit cell of fuel cell
Inventor: UMIGA NOBUYOSHI
IPC: H01M8/02
Filed: 1984-02-29
Abstract: PURPOSE:To obtain a unit cell uniformly containing phosphoric acid and matrix by compressing by stages to form one body a pair of carbon fiber plates and a matrix containing phosphoric acid which is interposed between the plates between two rollers with shearing force applied. CONSTITUTION:An upper roller 3a rotates counterclockwise and a lower roller 3b rotates clockwise and a unit cell 1 is compressed from upper and lower directions. The rotating speeds of both rollers 3a and 3b are different, for example, when a 60cm long unit cell passes between the rollers, an about 1cm shear in length comes out. A unit cell 160% thicker than ultimate thickness is passed between rollers 3a and 3b to compress and give shearing force and a matrix 1b between carbon fiber plates 1a and 1b is subjected to the excess flow to make thickness uniform. After decreasing the distance between rollers 3a and 3b and rotation of rollers is reversed, the unit cell is passed again. If this process is repeated several times to obtain desired thickness, the matrix 1b is uniformly interposed between the carbon fiber plates 1a and 1b.
Patent JP-S53120381-A (JP)
Title: Plating thickness measuring method
Inventor: KURIO ISAMU
IPC: G01B21/08
Filed: 1977-03-30
Abstract: PURPOSE: To perform the measurement of plating thickness from the state wherein the spacing of monitor patterns formed opposedly by maintaining specified spacing is narrowed by plated metal. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-H05235921-A (JP)
Title: Input phase margin warrant circuit
Inventor: KAWASAKI WATARU
IPC: H04L7/02
Filed: 1992-02-24
Abstract: PURPOSE:To provide the input phase margin warrant circuit fetching normally inputted data even under bad conditions of vibration, temperature and humidity or the like. CONSTITUTION:The operation that a data fetch state detection means 12 detects whether or not input data fetched to a data latch means are normally fetched with a data fetch clock signal and a clock timing variable means 13 changes a phase of the input clock signal when not normally fetched and outputs a data fetch clock signal to the data latch means is repeated to obtain the data fetch clock signal by which the input data are normally fetched to the data latch means 11.
Patent JP-H03129357-A (JP)
Title: Electrophotographic sensitive body
Inventor: IGUCHI YASUSHI
IPC: G03G5/06
Filed: 1990-02-17
Abstract: PURPOSE:To provide a high sensitivity and excellent repetitive characteristics and to prevent the deterioration against the exposure to light by incorporating specific bisazo compds. as the charge generating material of a charge generating layer into this layer and incorporating specific hydrazone compd. as the charge transfer material of a charge transfer layer into this layer. CONSTITUTION:This photosensitiv body has a photosensitive layer 4 which contains at least one kind of the bisazo compds. expressed by formula I as the charge generating material of the charge generating layer 2 and at least one kind of the hydrazone compds. expressed by formula II as the charge transfer material of the charge transfer layer 3. In the formulas I and II, R1 denotes a halogen atom, an alkyl group or the like, R2 denotes an alkyl group which may be substd.; R3 denotes a hydrogen atom, cyano group, etc.; R4 denotes a hydrogen atom, halogen atom, etc.; A denotes an aryl group, heterocyclic group which may be substd.; R5 denotes an alkyl group, aryl group which may be substd.; R6 denotes a hydrogen atom, halogen atom, etc.; n denotes 0 or 1. The photosensitive body which has the high sensitivity and excellent repetitive characteristics and is less deteriorated in the electrophotographic characteristics against the exposure of light is obtd. in this way.
Patent JP-S63205325-A (JP)
Title: Thermoplastic elastic tape
Inventor: YAMADA SHIYOUICHI
IPC: C08L75/00
Filed: 1987-02-19
Abstract: PURPOSE:To make it possible to form a thermoplastic elastic tape provided with properties as a tape and easy processability and being excellent in hue, hand and heat resistance, by mixing an aromatic vinyl compound/conjugated diene block copolymer with a thermoplastic polyurethane and an inorganic filler. CONSTITUTION:This thermoplastic elastic tape contains 5-94wt.% aromatic vinyl compound/conjugated diene block copolymer (A), 5-94wt.% thermoplastic polyurethane (B) and 1-50wt.% inorganic filler (C). It is preferable that component A has a weight-average MW of 10,000-800,000 and contains styrene as the aromatic vinyl compound and 1,3-butadiene or isoprene as the conjugated diene. It is particularly desirable that component B is of an adipate ester type and has an MW of about 5,000-500,000. Examples of component C which can be particularly desirable include carbonates such as calcium carbonate, clays, and silicic acids.
Patent JP-H04330242-A (JP)
Title: Chemical-spraying robot
Inventor: MIYAKE YASUHIKO
IPC: B25J5/00
Filed: 1991-02-07
Abstract: PURPOSE:To obtain the title robot capable of automatically and simply carrying out operation of drenching plant foot of a crop and applying drug without wasting thereof, having a specific constitution. CONSTITUTION:A self-propelled base 2 provided with a chemical tank 3, a chemical-spraying nozzle 4 and a crop perceiving sensor 5 is equipped with a single pulse generating circuit and a relay circuit with a timer. When the crop perceiving sensor 5 detects a crop, single pulse is generated from the single pulse generating circuit, the relay circuit with a timer is started by the single pulse, self traveling is stopped according to a set time, a chemical is applied from the chemical spraying nozzle 4, self-traveling is repeated and the chemical is intermittently applied.
Patent JP-S60205124-A (JP)
Inventor: HAINRITSUHI RANBUREHITO
IPC: F23D14/32
Filed: 1985-02-27
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S59185099-A (JP)
Title: Nonvolatile semiconductor memory
Inventor: IWAHASHI HIROSHI
IPC: G11C29/00
Filed: 1984-02-28
Abstract: PURPOSE:To attain easily the partial rewrite of a memory cell array in a short time by providing a spare decoder using a nonvolatile semiconductor memory element having the capacity for write of address data and a spare memory cell to a part of the memory cell array. CONSTITUTION:In rewriting the storage content of the memory cell of a row line R0, the input of address data A0-Ai is set to 0, the input of A'0-A'i is set to a high voltage, the input of R/P'i is set to 0 and the input of R'/P1 is set to a high voltage and a program pulse of high voltage is impressed to a power supply terminal 16, then the address of A0-Ai=0 is assigned to the row line R'i, and in bringing the state to the read state by setting as A0-Ai=0, A'0-A'i=1, R/P'1=1 and R'/P1=0, then the row line R'1 is selected, a write voltage Vp is impressed to the write circuit of a space row buffer circuit 13, then an input data is written to the memory cell of the row line R'1. When the address designation of A0-Ai=0 is performed to a memory cell array 10, a spare row decoder 11 and a spare row buffer circuit 13 select automatically the row line R'1.