Patent GB-789207-A (GB)
Title: Electronic digital computing machines
Inventor: JOHNSTON ANDREW ST
IPC: G06F15/78
Filed: 1953-03-24
Abstract: 789,207. Digital electric calculating and storage apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. March 23, 1954 [March 24, 1953], No. 8154/53. Class 106(1). In an electronic digital computing machine operating in the series mode with instruction words containing at least two storage address location signals, means are provided whereby the machine can bo caused to operate so as to use each of said address location signals in turn, or alternatively to utilize only one of said address location signals and to disregard the other or others. The machine described uses 34-digit binary numbers and instructions, Figs. 14A and 14B, each allowing a two-digit gap or pause between consecutive words, and comprises a store S, Fig. 1, used for both numbers and instructions, a control unit CL, an arithmetic unit AU including an add/ subtractor and input and output units. Machine operation usually follows three general stages, firstly an instruction is transferred from the store to an instruction register ISR secondly the order specified by the control digits "CF," "TFA," "AF," "TTA," of the instruction is obeyed and if this involves transferring a number to or from the store it goes to or comes from the store position with address A1 and thirdly, the next instruction is passed from address A2 of the store to replace the present instruction in the register ISR. Under certain conditions, namely when the " control function " CF digits specify a conditional transfer, in which circumstances the order specified must not involve the store, the first two stages above occur and the store location of the next instruction to be fed to the register ISR, stage three above, is selected from either address A1 or address A2 depending upon whether or not the condition specified by the CF digits is satisfied respectively. Store. The store consists of eight tracks on a magnetic drum, each track being divided notionally into 128 sectors numbered 0 to 127, each of which just accommodates one word of 32 digits and a 2-digit space. The drum also carries a " clock-pulse " track and an " address " track, each sector of which has recorded on it, in digit periods 2 to 8 inclusive, the number of the next sector to pass the reading/writing heads. The speed of the drum motor is controlled by a frequency discriminator FDC which compares the clock pulse frequency with a standard of approximately 333.3 kc/s. Pulse generators. The sinusoidal pulses from the clock pulse track are amplified and shaped (Fig. 11A, not shown) to produce the clock pulses, Fig. 14C, which are further shaped to produce the "reset" and "strobe" pulses, Figs. 14D, 14G. The other control pulses used in the machine are generated by a series-chain of unit delays from a single pulse in each digit period 32 of the address track (Fig. 11A, not shown). Instruction register and delay chain. An instruction from the store passes on lead 101, Fig. 11B, through a gate 240 and circulates through a closed loop of four unit delays 243, 244, 245, 246, a 30-digit magnetostriction delay line and its associated driving amplifiers &c. 271 ... 274 and a gate 265 which is only closed when it is desired to enter a new instruction into the loop, and is available for use in the machine at any of a series of tapping points PI1, PI2 ... PI23, on a delay chain. Staticizors and triggers. The CF group of control digits is registered on a staticizor consisting of 3 trigger units, Fig. 11C (part). Each trigger 280 consists of two threshold-two gates feeding a unit delay, the output of which is fed back to the second gate, which is always open except at digit time 32 when an inverse 32 pulse, denoted by 32, closes it for one digit period. Thus if a pulse is entered, via the first gate, into the delay it continues to circulate and is continuously available from the delay as a series of pulses until the next digit time 32, when the second gate closes. An inverse output is also available via an inverter 281. The inputs to the three triggers constituting the CF staticizor are from the tapping points PI20, PI21 and PI22 on the delay chain. Thus the input to trigger 280, i.e. the 32 pulse from the PI20 tapping, is digit 13 of the instruction word since the output at PI20 is delayed by 19 units. Similarly the other two triggers receive, simultaneously, digits 12 and 11 of the instruction word circulating in the instruction register. The other three groups of control digits TFA, AF and TTA are similarly staticized with the exception that the potentials controlling entry to the staticizors are functions of a coincidence waveform C and the potentials for clearing the staticizors are functions of the waveform C and also of the digits staticized and the four staticizors together constitute the staticizor STR in Fig. 1. Beat unit and coincidence circuit. The coincidence circuit compares the word number of one of the addresses Al and A2 of the present instruction with the word numbers coming from the address track, the particular one of the addresses A1 and A2 used being determined by the beat unit. The word numbers of the two addresses A1 and A2 are applied simultaneously commencing at digit time 2 of the machine cycle from tapping points PI2 and PI14 to the gates 315 and 316, Fig. 11D, respectively, one of which is always open, from where one word number passes via a unit delay to a gate 327 of a non- coincidence trigger by two paths. The complete instruction is, of course, applied to gates- 315 and 316 and thence to gate 327 but all digits other than the address word numbers may be ignored since gate 327 is controlled by a trigger 325 which is on for only 7 digits of each machine cycle, commencing at digit 3. The word numbers from the address track are also applied to gate 327 via a delay 320 with the result that if any of the digits of the word number from the delay 318 are different from corresponding digits of the word number from the delay 320 the trigger 327 is set on, and is set off again at machine time 34. Thus during each machine cycle the word number of one of the addresses A1 and A2, depending upon which of the gates 315, 316 is open, is compared with the word number coming from the address track, and every time a non-coincidence is detected, trigger 327 is set on. In the event of coincidence, trigger 327 is not set on and its inverted output opens a gate 330 to allow a coincidence trigger 321 to be set on by a 34 pulse, and produce a coincidence output pulse train C. Also in the event of a coincidence a beat trigger 305 normally changes its state. Thus suppose trigger 305 has been " on," i.e. that a pulse has been circulating through the delay 308 and the gate 306, and suppose a coincidence is detected. The inverted output from trigger 327 will open a gate 311, and allow a 34 pulse to pass from a normally open gate 313 to an inverter 310 and then to gate 306 which is therefore closed, thus breaking the circulation and the trigger 305 is set " off." Normally when an instruction has just run into the instruction register, the beat trigger is on, i.e. a B signal is present, and the coincidence circuit commences to compare word numbers from the address track with the word number of the address A1. When a coincidence is detected a C signal lasting for one word period appears from the coincidence trigger 321, the beat trigger 305 changes its state, thus closing gate 315 and opening gate 316, and the coincidence circuit now compares the address A2 with the address track. Under certain conditions, the waveform #TC.B is zero at time 34 so that at the first coincidence the state of the beat trigger remains unchanged. In these circumstances a new instruction from the store location represented by address A1 would flow into the instruction register and its Al address would be compared with the address track. Track selector. The track selecting digits of that one of the addresses A1 and A2 with which coincidence is being sought are staticized on a three-trigger staticizor (Fig. 11F, not shown) similar to that used to staticize the CF digits (Fig. 11E, not shown), and the six outputs, which in this case are arranged to be continuous steady potentials, are used in different combinations of threes to control six track selecting gates (Fig. 13, not shown). X, D and. R registers. The X and D registers, Fig. 12C, both consist basically of a 34-digit magneto-striction delay line 430, 443, through which a registered word circulates, the two controlling gates for each of the registers being controlled by various combinations of the outputs g, h, i, and #g, #h, #i, from the staticized TFA digits of the instruction. The R register is similar to the X and D registers but it has a 30-digit delay 458 instead of a 34-digit delay, the registered word passing from the delay line either through delay 464, gate 470, delay 468 and delays 468 and 469 back to the input of the delay line or through delays 464, 465, gate 466 and delays 468 and 469 back to the delay line, depending upon the state of a shift trigger 474. Thus it is possible to shift the word in the R register one digit per cycle. The ACCI and ACC2 registers. The ACCI register consists of a 30-digit delay line 484, Fig. 12A, and a controllable shift SH1, the circulating path being from a delay 491, via gates 494, 499 and a delay 500 to a gate 525 and into the delay line and back to the delay 491 by one of three possible routes through the shift SH1 network, the routes being (a) via gate 487, including no delays, (b) via a delay 485 and either gate 488 or gate 489, including one delay, and (c) via delay 485, delay 486 and a gate 490, including two delays. It is also possible for the circulating loop of the ACC1 register to include an accumulator register ACC2, Fig. 12B (part). Thus since the leads 121 and 122 which control gates 494, 493, Fig. 12A, come from either side of an inverter 498, Fig. 12B, only one of the gates 494 and 493,