Patent GB-951082-A (GB)
Title: Improvements in or relating to electrical signalling systems
Inventor: MOFFETT ROBIN HENRY
IPC: H04L7/04
Filed: 1959-09-12
Abstract: 951,082. Multiplex pulse code signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Sept. 11, 1960 [Sept. 21, 1959], No. 32116/59. Heading H4L. In a time division multiplex pulse code modulation system a characteristic multielement synchronizing signal occupies one channel position in each frame and the nature of the synchronizing signal received is tested during each frame and the operation of the receiver is modified unless the synchronizing signal varies in a predetermined manner over a succession of frames. As described the system comprises twenty-four speech channels using 7-digit binary code a further code digit being used for other signalling purposes, and a separate channel comprising all 1's and all 0's in alternate frames is used for synchronizing. At the receiver the incoming pulse signals are supplied via line RL1 and timing pulses are generated in known manner at SG1. The dividers DA, DB produce an output pulse for each eight input pulses applied at the left-hand side and may be set to specific counts by inputs applied to the top. Channel selector SC1 is a twenty-five stage ring counter driven by pulses applied from the divider DB to apply potential in turn to twenty-five output leads controlling gates S1, S2, S3 and 1 to 24. The channel selector may be set to the synchronizing channel 0 via input leads at the top of SC1 and produces an output pulse once per cycle over the output lead at the top. During the synchronizing channel, potential on the lead O from SC1 will open gates Sl, S2 and close gate S3 so that a continuous train of timing pulses is passed to gate a, and line pulses are passed to a shaper SH where all 1's are converted into narrower pulses similar to and in synchronism with the timing pulses. Gate a is arranged so that timing pulses pass only when the incoming signals are O's, and gate S3 prevents the operation of bi-stable device C during the synchronizing channel. When gate S3 is open it allows output pulses from the divider DB to change over bi-stable device C at the end of each channel period, whereby decoders D1 and D2 are used alternately for successive information channels. The divider DB also controls a bi-stable device D operating a gate P for extracting the separate signalling pulses from the input RLI which are distributed by twenty-four additional gates controlled by the channel selector. Normally, bi-stable device B is in the reset condition so that gate l is open and gates b, c, h and i are closed, bi-stable device A being changed over at each frame by a pulse from SC1. In the position of A in which gates e and g are open, the synchronizing signal is all 0's and pulses are passed via gates a, e, to the gate h but produce no effect since gate h is closed. When the synchronizing signal is all 1's, gates d,f are opened by A and synchronizing pulses are passed via gate f to the closed gate h. If the synchronizing signal is mutilated a pulse will be passed through gate d or g depending on the position of bi-stable device A, to flip-flop MS1 which will hold gate j open for about two channel periods so that flip-flop MS2 will open gate k for rather more than two frames. During the next two synchronizing periods any mutilation will cause bi-stable device B to operate to close gate l and open gates b, c, h and i. If the signals are correct the original conditions are restored when flip-flop MS1, MS2 have reset. Otherwise the pulse which operates device B passes through gate l, resetting the channel selector SC1 and setting the divider DB to zero. When device B operates, a test is made for a sequence of eight signal elements of the same kind which when found is treated as a synchronizing signal. It is then checked against the next synchronizing signal which should be eight elements of opposite type, the tests being repeated until the correct sequence is found. For example, if device A is in the position in which gates d and f are open and the next pulse is 0, a pulse from SG1 passes through gate i and sets the dividers DA, DB to position 1, and also passes through gate b to change over device A so that further 0's will cause pulses to pass via e and h to operate divider DA. If any pulse within the next seven is a 1, the testing operation is continued by the resetting of dividers DA, DB. Similarly, if the next pulse after the operation of device B is a 1, a pulse is passed via gates f and h to divider DA. Thus a sequence of eight 1's or eight 0's will operate divider DA and reset the bi-stable device B to stop the testing operation. A suitable transmitting apparatus is described, Fig. 2 (not shown).