baber/WOPTO huggingface dataset:
Patent JP-2000044398-A (JP)
Title: Production of silicon carbide single crystal and silicon carbide single crystal obtained thereby
Inventor: OKAMOTO ATSUHITO
IPC: C30B29/36
Filed: 1999-05-20
Abstract: PROBLEM TO BE SOLVED: To block the micro pipe defects in the silicon carbide single crystal substrate but not to block the micro pipe defects in a new growth layer. SOLUTION: At least one of the micro pipe defects opened on the surface of a substrate crystal (namely silicon carbide single crystal) is coated with a coating material 5. The coated single crystal is heat-treated so that the inside of the micro pipe defect may be saturated with silicon carbide vapor. Thus, the micro pipe defect 6 in the substrate crystal 1 can be blocked inside the substrate crystal, not in the growing layer that newly grows on the substrate crystal.
Patent JP-S5567436-A (JP)
Title: Ejecting device for molding in injection metal mold
Inventor: MURAKAMI SEIICHI
IPC: B29C45/40
Filed: 1978-11-15
Abstract: PURPOSE: In an ejector mechanism of replaceable molds, to provide an easily replaceable pin by preparing a rear part of the ejector which can be simply removed and giving greater diameter to the ejector hole of a mold than the rear part of the ejector pin.  
     CONSTITUTION: Replaceable mold parts 3, 4 for moldings are provided in a metal mold body 1 of a fixed part and a metal mold body 2 of a movable part so that the molds may be shifted easily to others. An ejector pin 5 is fitted to an ejector plate 6 at the enlarged head 51 by a spring 9 through an ejector hole 8 of the metal mold body so that the pin may be freely replaced. The ejector hole 8 of the metal mold body has a diameter through which the enlarged head 51 of the ejector pin can go. When molds are to be replaced the ejector pin can be removed without disassembling the mold bodies. If the diameter of a pin is within an ejector hole the mold  part can be replaced even if the location of the pin deviates a little. 
     COPYRIGHT: (C)1980,JPO&Japio
Patent JP-S63305542-A (JP)
Title: Package for pin grid array
Inventor: YAMASHITA TSUTOMU
IPC: H01L23/50
Filed: 1987-06-06
Abstract: PURPOSE:To decrease the number of pins by making internal pin members, to which external leading-out pins are disposed in a coaxial manner through insulating members in themselves, longer than external pin members and conducting each pin member with a wiring layer formed to a substrate intermediate layer. CONSTITUTION:A printed substrate has a substrate upper layer 27, a substrate lower layer 30 and a substrate intermediate layer 29, which is arranged between the layer 27 and the layer 30 and to which a wiring layer 28 is shaped. A first pin member 31 in external leading-out pins takes a cylindrical shape, and an insulating member 34 consisting of a cylindrical heat-resistant insulating resin is press-fitted to the first pin member 31. A ring-shaped second pin member 32 is press-fitted to the insulating member 34, and the first pin member 31 and the second pin member 32 are disposed in a coaxial manner through the insulating member 34. The lengths or positions of the lower edges of the first pin member 31, the second pin member 32 and the insulating member 34 differ: the first pin member 31 is largest, and the second pin member 32 is shortest. Accordingly, the number of the pins in the substrate can be decreased.
Patent JP-H01310645-A (JP)
Title: Display method for ultrasonic diagnosing picture
Inventor: HOSHI KAZUYA
IPC: A61B8/00
Filed: 1988-06-08
Abstract: PURPOSE:To easily observe an ultrasonic diagnosing picture and to improve the ease of diagnosis by providing a look-up table in each diagnosing picture on a display picture and correcting each diagnosing picture with referring the correspondent look-up table. CONSTITUTION:The look-up tables to modes 1, 2 and 3 exist in memories 11, 12 and 13. When the data of the modes 1, 2 and 3 are assumed to be 256 gradations, the memories 11, 12 and 13 respectively have 0-255 addresses and luminance data are stored to the respective addresses. The data of the mode 1 are inputted to the address terminal of the memory 11 and correspondent data are read from the memory 11. The data of the mode 2 are inputted to the address terminal of the memory 12 and correspondent data are read from the memory 12. Then, the data of the mode 3 are inputted to the address terminal of the memory 13 and correspondent data are read from the memory 13. The data to be read from the memories 11, 12 and 13 are sent through an adder circuit 20 to a display part.
Patent JP-H10315423-A (JP)
Title: Decorative sheet and decorative plate trapping formaldehyde and having antibacterial properties
Inventor: KURODA SEIJI
IPC: B32B27/18
Filed: 1997-05-14
Abstract: PROBLEM TO BE SOLVED: To make a decorative plate have a function of trapping formaldehyde and antibacterial properties in the case when a urea adhesive is used for adhesion to a base, by providing a base sheet with a formaldehyde trapping layer, a decorating treatment layer and a surface protection layer and by adding an inorganic antibacterial agent to the surface protection layer. SOLUTION: A decorative plate 10 has a constitution wherein a decorating treatment layer 3 constituted of a solid ink layer 3a and a pattern ink layer 3b is formed on the surface of a base sheet 2 provided on the surface of a base 7 with an adhesive layer 6 interlaid and wherein a surface protection layer 4 formed of hardening resin coating to which an inorganic antibacterial agent is added is laminated on the decorating treatment layer and a decorative sheet 1 having a formaldehyde trapping layer 5 laminated is stuck on the lower side. This plate has properties of trapping formaldehyde released from the base 7 and antibacterial properties in the surface thereof.  For the inorganic antibacterial agent 8, a silver-series inorganic antibacterial agent prepared by making silver ions borne on various inorganic substances, e.g. an antibacterial zeolite composition whereon the silver ions are made borne by ion exchange, is used.
Patent JP-S63304724-A (JP)
Title: Error correcting device
Inventor: KAWASE TAKEO
IPC: H03M13/00
Filed: 1987-06-05
Abstract: PURPOSE:To contrive the improvement of the economical efficiency by forming a hardware for a 1st correcting means so as to correct a small-sized error generated frequently at high speed and realizing a 2nd correction means by means of a software to correct a large error generated rarely. CONSTITUTION:When an error word in a word group stored in a storage circuit 11 is less than the set word number, the 1st error correction means 14 to correct the error word and the 2nd error correction means 15 correcting the error word when the 1st error correction means 14 cannot correct the error word are provided. The 1st error correction means 14 uses the Peterson's method as the algorithm with the hardware not employing any microcomputer and the 2nd correction means 15 uses the Euclidean algorithm as the algorithm with the software as the microcomputer application. Thus, the error correction device with excellent economical efficiency being able to be manufactured with low cost is obtained.
Patent JP-H08303882-A (JP)
Title: Method of operating heat pump using new alternative refrigerant gas hfc
Inventor: OGURI YORIYUKI
IPC: F25B13/00
Filed: 1995-04-28
Abstract: PURPOSE: To achieve operations of cooling, refrigerating and freezing using a heat pump into which an alternative refrigerant gas HFC(fluorocarbon containing hydrogen) is injected singly or in a mixture. CONSTITUTION: An air-cooled condenser 2A is provided with an air-cooled condenser 2B additionally and the condensing temperature of a refrigerant is set to a low temperature within the atmospheric temperature plus 5 deg.C to perform an operation. A water-cooled condenser 2C1 is provided with a water- cooled condenser 2C2 additionally and the condensing temperature of the refrigerant gas is set to a low temperature, by 1 deg.C or higher than the temperature of cooling water being sent to the water-cooled condenser.
Patent JP-S6121856-A (JP)
Inventor: INAGUMA TOSHIAKI
IPC: B65G47/61
Filed: 1984-07-06
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H037440-A (JP)
Title: Multiplexing transmission system
Inventor: TANUMA HIROSHI
IPC: H04B10/00
Filed: 1989-06-05
Abstract: PURPOSE:To prevent the deviation of synchronization between signals by multiplexing a horizontal synchronizing signal, a vertical synchronizing signal and a display signal. CONSTITUTION:A multiplex section 5 multiplexes a horizontal synchronizing signal HSC, a vertical synchronizing signal VSC and a display signal DIP and a reproduction signal output section 11 demultiplexes and reproduces the multiplex signal based on a multiplex signal VHSI, a horizontal synchronization enable signal HSEN and a vertical synchronization enable signal VSEN. Thus, an optical interface is constituted of a couple of optical module and optical fiber, since the horizontal synchronizing signal, the vertical synchronizing signal and the display signal are sent and received by one and the same optical module (having same switching characteristic), the deviation of synchronization among the signals is prevented.
Patent JP-H05330412-A (JP)
Title: Integrated control device for vehicle
Inventor: IKEDA TOSHIFUMI
IPC: G01S15/931
Filed: 1992-06-02
Abstract: PURPOSE:To ensure safety by suitably controlling the operation of an automatic braking device or an automatic steering device when a device related to the running stability of a vehicle fails at the time of mounting the device related to the running stability of a vehicle and the automatic braking or steering device. CONSTITUTION:A vehicle is provided on condition of including a device such as ABS, 4WS, 4WD or the like related to the running stability of a vehicle and an automatic braking device or an automatic steering device which is adapted to detect the dangerous state of the vehicle and automatically take an escaping action. Failure detecting means 56-58 are provided for detecting the failure of the device such as ABS, 4WS or 4WD. When the device such as ABSm 4WS or 4WD fails, the operation of the automatic braking device or the automatic steering device is regulated by a regulating means 53 for receiving signals from the detecting means. The regulation inhibits quick braking caused by the operation of the automatic braking device or the like.
Patent JP-H11338474-A (JP)
Title: Sampling method, sampling device, and reference sound generator
Inventor: TAKI YUJI
IPC: G10H7/02
Filed: 1998-05-22
Abstract: PROBLEM TO BE SOLVED: To reduce a memory using amount, and to enhance capacity. SOLUTION: A computor 1 substitutes zero for a work area-set (n) of a RAM 2, and then makes a value of (n+1) get the (n) again. The CPU 1 calculates a function S(n) to be stored in the RAM 2 as a sample data in the (n). The CPU 1 determines whether the S(n) stored in a RAM 2 memory satisfys S(n)<ε or not, and processing is continued when the S(n)<ε is not satisfied. When the S(n)<L is satisfied, the CPU 1 determins again whether the S(n) is larger than the last S(n-1) or not. The CPU 1 finishes the processing when the S(n) is lager than the S(n-1).
Patent JP-S621323-A (JP)
Title: Oscillation circuit
Inventor: SAITO MITSUMASA
IPC: H03L7/187
Filed: 1985-06-27
Abstract: PURPOSE:To generate an oscillation output from a VCO (voltage controlled oscillator) within a prescribed frequency band with high accuracy by selecting a designated voltage to a reference voltage being an object to be adjusted and adjusting the oscillation element of the VCO so as to make the frequency of the VCO as a reference value. CONSTITUTION:An output S2 of the VCO 14 is frequency-divided by a programmable frequency division circuit 15, the result is supplied to a phase comparator circuit 13 to obtain the 1st difference output S4 with a reference oscillation output S1. The 1st difference output S4 controls a control voltage generating circuit 16 to obtain a control voltage VC thereby locking the oscillation frequency of the VCO 14 to the reference oscillation output S1. In the oscillation circuit, the 2nd difference output COD 3 being a difference between the control voltage VC and a designated voltage corresponding to an input signal COD 2 from the designated input means 24 is obtained by a comparing means 23 to control the frequency division ratio of a programmable frequency division circuit 15 based on the difference output COD 3, thereby locking the control voltage VC to the designated voltage.
Patent JP-S5265530-A (JP)
Title: Adhesive composition
Inventor: HORIGUCHI KOUICHI
IPC: C08L33/00
Filed: 1975-11-26
Abstract: PURPOSE: An adhesive composition having improved adhesivity, preventing the lowering of the adhesive force under wet condition and keeping the advantages of an aqueous dispersion of metal-containing ethylene copolymer, by the addition of a particular amount of phenolic resin. 
     COPYRIGHT: (C)1977,JPO&Japio
Patent JP-S6033341-A (JP)
Title: High magnetic permeability alloy excellent in wear resistance property
Inventor: NOZAWA YASUTO
IPC: C22C38/00
Filed: 1983-08-02
Abstract: PURPOSE:To enhance the wear resistance property of an alloy without deteriorating the magnetic characteristics thereof, by adding and containing a specific amount of Ru in an Fe-Co-Si soft magnetic material. CONSTITUTION:As a high magnetic permeability alloy for a magnetic head material, 0.05-3.0atom% of Ru is contained in an Fe-Co-Si alloy containing 16.5- 20.0atom% Si and 11.0-16.0atom% Co. By this method, wear resistance property of the Fe-Co-Si soft magnetic alloy is enhanced without deteriorating the magnetic characteristics thereof. In addition, if at least one of metals selected from a group consisting of Ti, V, Nb, Ta, Cr, Mo, W and Cu is added in a sum total of 2.0atom% or less, wear resistance property can be further enhanced without excessively deteriorating magnetic characteristics.
Patent JP-H04365393-A (JP)
Title: Manufacture of printed wiring board and manufacture of dry film for printed wiring board
Inventor: MAEZAWA SATOSHI
IPC: G03F7/004
Filed: 1991-06-13
Abstract: PURPOSE:To provide a manufacturing method for improving yield and productivity without any defect in a conductor pattern and without any through-hole in a method for manufacturing a printed wiring board which is used for electronic equipment. CONSTITUTION:Both edge portions are exposed when laminating a dry film 11, and the dry film where the exposed portion is subjected to splitter machining/division is used, thus enabling both edge portions of the dry film 11 to be exposed and cured previously and squeeze-out of a sensitized resin layer 11a to be controlled when performing heating and pressurization at the time of lamination. Also, wrinkles can be prevented without losing a pressure balance of a heat roll 15, a smooth lamination can be executed, and generation of defects, for example, through-holes can be prevented.
Patent JP-H036527-A (JP)
Title: Liquid crystal display element
Inventor: WAKEMOTO HIROBUMI
IPC: G02F1/1337
Filed: 1989-06-02
Abstract: PURPOSE:To eliminate reverse twist defects and to obtain high image quality by constituting at least either of the oriented films provided on the surfaces of upper and lower substrates of a high polymer orienting agent contg. a chiral group. CONSTITUTION:At least either of the oriented films provided on the surfaces of the upper and lower substrates consists of the high polymer orienting agent contg. the chiral group. The method for introducing the chiral group into the high polymer to be used as the oriented films is, for example, a method for polymerizing a monomer having the chiral group to a high polymer by a polymn. reaction, such as addition polymn. or condensation polymn., a method for dispersing a compd. having the chiral group in a high polymer matrix, etc. The generation of the reverse twist defects is obviated in this way and the high contrast and high image quality are obtd.
Patent JP-S5933668-A (JP)
Title: Information recording device
Inventor: HOSHINO ISAO
IPC: G11B19/28
Filed: 1982-08-17
Abstract: PURPOSE:To fix a pitch in the diameter direction of the information which is written spirally, by connecting one of two control systems which control revolutions of two motors to the other one in a subordinate way. CONSTITUTION:A reference signal 101 for rotational frequency of a main shaft motor 3 is applied to a revolution control part 10 of the motor 3 which drives a disk 1. Then the part 10 supplies a driving signal to the motor 3 so that the difference is set at zero between a rotational frequency detecting signal 102 generated from a tachogenerator 4 in response to the rotational frequency of the motor 3 and the reference signal 101. While a reference signal 105 for rotational frequency of a feed motor 5 of a diameter direction feed system is applied on the basis of the signal 102 of the motor 3. The signal 102 is applied to an arithmetic part 11 together with a track pitch reference signal 104. Then the value obtained by dividing the product of a track pitch and the rotational frequency of the motor 3 by the conversion factor of a motion converting mechanism 8 and the deceleration ratio of a decelerating mechanism 7 is defined as the reference signal 105 of the motor 5 and applied to a revolution control part 12.
Patent JP-S62297992-A (JP)
Inventor: MATSUI MAKOTO
IPC: G07G1/12
Filed: 1986-06-18
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H036920-A (JP)
Title: Semiconductor integrated circuit
Inventor: OKADA KEISUKE
IPC: H03K17/16
Filed: 1989-06-02
Abstract: PURPOSE:To decrease a through-current by connecting plural semiconductor elements having a threshold level in series between a power supply and a semiconductor element section realizing an inverter function or varying a threshold voltage of the semiconductor element group itself realizing the said inverter function. CONSTITUTION:Semiconductor element groups 20, 30 comprising plural N- channel semiconductor elements 2 connected in series are connected to a semiconductor element group 1 comprising a P-channel semiconductor element 5 and an N-channel semiconductor element 2 realizing an inverter function. pcs. of n1, n2 of the N-channel semiconductor elements constituting the N-channel semiconductor element groups 20, 30 are selected to satisfy the relations of VDD-n1XVTNO>3.4V and n2XVTNO<0.5V, where VTNO is the threshold voltage of the individual N-channel semiconductor elements 2. Thus, the range of the input voltage where a through-current (i) flows is decreased, resulting that the through-current at a change in the input voltage Vin is decreased.
Patent JP-H06348689-A (JP)
Title: Document preparing device and numerical formula conversion method
Inventor: MORI TOMOTAKA
IPC: G06F17/22
Filed: 1993-06-14
Abstract: PURPOSE:To provide a document preparing device and a numerical formula conversion method capable of easily and quickly converting a desired numerical formula or the like. CONSTITUTION:When a 'numerical formula conversion' key 44c is pressed, the numerical formula analysis information storage area 20d and the numerical formula conversion table information storage area 20e of a ROM 20 are referred to and a mode for performing a numerical formula conversion control processing to unconverted information among the information of a prepared or edited and proofread document or the like is set.
Patent JP-S62298368-A (JP)
Inventor: NAGASE TOSHIO
IPC: A61M1/10
Filed: 1986-06-18
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H11333298-A (JP)
Title: Preparation of photocatalytic reaction film and photocatalytic reaction film
Inventor: KUBOTA NOBUHIKO
IPC: A61L2/16
Filed: 1998-05-22
Abstract: PROBLEM TO BE SOLVED: To highly increase photocatalytic reaction surface area, raise retention property of a photocatalytic reaction film and raise photocatalytic reaction efficiency by arranging a soft layer on a surface to be treated, disposing a photocatalyst particle on the soft layer and forcing a part of the photocatalyst particles to intrude into the soft layer. SOLUTION: Excluding the case wherein a surface to be treated of a structural material 1 can be easily dissolved, i.e., in the case of a structural material 1 made of an ordinary metal, a soft layer is formed by coating e.g. a cold setting adhesive, a photosetting adhesive or a tacky agent. Photocatalyst particles 3 are disposed to form a layer by spraying, on the soft layer 2 through a spray nozzle 4, the photocatalyst particles 3 borne on an air current. In this case, the photocatalyst particles 3 having relatively large particle diameters (e.g. approximately 0.1-2 mm) are employed and the particles 3 are carried on the soft layer 2 in such a manner as to be forced to partially intrude into the soft layer 2 on account of kinetic energy at the time of spraying. Thus, the photocatalyst particles are disposed on the hole surface of a matter to be treated.
Patent JP-S5366266-A (JP)
Title: Semiconductive type shunt circuit
Inventor: KAWASAKI KIKUO
IPC: G01R15/14
Filed: 1976-11-25
Abstract: PURPOSE: To stably distribute at the shunt ratio, preliminary set up input current, with a simple construction, indifferent to the characteristics of shunt output load and without affected by the external condition, such as temperature etc., by using transister, having the same base potential and voltage characteristics. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-S6033061-A (JP)
Title: Frequency analyzing method
Inventor: KUGE KATSUTAROU
IPC: G01R23/16
Filed: 1983-08-04
Abstract: PURPOSE:To obtain analytic result close to a logical value by reprocessing the data of a digital frequency analyzer through a general computer. CONSTITUTION:Analytic data are transferred from the digital frequency analyzer 1 to the general computer 2 for reprocessing. Then, a check on the (N number of) analytic data is started with the lowest-frequency data in increasing order. Then, M pieces of data Dn-M- before the (n)th data Dn and M pieces of data up to Dn+M after the (n)th data Dn are extracted to check whether Dn is a peak value or not. When the peak value Dn is found, data which decreases about Dn is obtained, subsequent data are regarded temporarily as 0, and the number Z of data when so is stored. Then, specific arithmetic is carried out to obtain a result Dn. The Dn and its frequency fn are outputted as temporary analytic data. This arithmetic is repeated until n=N and ended when n=N. Thus, an analytic value close to a logical value is obtained.
Patent JP-H11338943-A (JP)
Title: Card issuance system and recording medium
Inventor: TAKASAKI MIYUKI
IPC: G06Q40/00
Filed: 1998-05-22
Abstract: PROBLEM TO BE SOLVED: To make easily and quickly issuable an IC card by using the terminal of a POS or the like of a nearby shop, by preserving the various kinds of information from a head office in the terminal of the POS or the like at all times, executing the initialization of the IC card and the issuance processing of writing the various kinds of the information based on the preserved information when a customer brings the IC card, attaining a usable state, transferring the various kinds of the written information to the head office and registering them. SOLUTION: This card issuance system is provided with a means for downloading the information required for card issuance from a management host at all times, a card reader-writer 14 for reading the information from the card 5 and writing the downloaded information to the card and a means for writing the pertinent information required for the card issuance downloaded based on the information read from the card when the card is inserted to the card reader-writer to the card.