Patent GB-1285222-A (GB)
Title: A pcm-tv system with bandwidth compression
IPC: H04N7/56
Filed: 1969-06-26
Abstract: 1285222 Television bandwidth compression POST OFFICE 26 June 1969 [26 June 1968] 12139/72 Divided out of 1285221 Heading H4F Television bandwidth compression is effected by storing the lines of picture information over one frame period, comparing each new line of picture information with the corresponding stored line, and generating an output comparison indication in the event that the new and stored lines differ in information content by a predetermined amount. In response to this output comparison indication the stored line is replaced by the new line in the memory, and the new line is transmitted together with an indication of the position of the new line in the frame. As described, the video information is converted into digitally encoded video before it is stored and compared, and a different digital code word is generated (and transmitted if necessary) for each horizontal sync. pulse within a vertical frame. Thus only changes in the television picture are transmitted, the transmitted lines being stored in their correct positions in a memory at the receiver which always contains an entire frame of information. Frame code words identifying the start of each frame are also transmitted. The television constants are the same as those described in parent Specification 1,285,221 except that each horizontal code word has an extra 10 bits added to the 60 bits to identify each individual line. Transmitter, Fig. 2.-A standard TV waveform, with or without colour bursts &c., is supplied to terminal 400 and fed via a delay 416 to TV-PCM circuitry 418. The sync. and equalizing pulses are extracted, 402, and applied to a horizontal sync. and equalizing pulse timing generator 404 (Fig. 4, not shown) which provides one output spike on lead 406 corresponding to the first equalizing pulse within every frame, and a series of horizontal spikes on lead 408 corresponding to the horizontal sync. pulses within the frame. The horizontal and equalizing spikes from timing generator 404 are applied to a timing circuit 410 (Fig. 5, not shown) which distributes clock pulses to the other parts of the transmitter as shown, and provides a group of 60 clock pulses to the equalizing unique word generator 414 following each equalizing spike, and 70 clock pulse to the horizontal unique word generator 412 after each horizontal spike. The equalizing and horizontal spikes from generator 404 are also applied to the horizontal unique word generator 412 (see later). The output of the TV-PCM circuit 418 is applied to a redundancy removal circuit 420 which only transmits changed lines, and these together with the outputs of horizontal and equalizing unique word generators 412 and 414 are applied to a bit rate reduction circuit 422 which reduces the 64 megabit per second rate to 32 megabits per second resulting in a bandwidth compression ratio of 2 : 1. The output is modulated, 424, into a phase code and transmitted, 426. Horizontal unique word generator, Fig. 6, is different from the unique word generators of Specification 1,285,221 (which are the same as the equalizing unique word generator) in that it generates a 70-bit word, the last 10 bits being different for each horizontal spike during a single frame. The horizontal clocks from timing circuit 410 are accumulated by a binary counter 542 which is capable of counting up to 70. The output terminals from every stage of counter 542 are applied in parallel to a decoder 544, e.g., a matrix type decoder, having 70 outputs. The first 60 outputs are connected through manual switches 562 to OR circuit 560 and are thus the same for every horizontal unique word. The last 10 outputs are supplied to AND circuits 540, the other inputs of which are energized by outputs from a horizontal spike counter 550. This counter contains a number corresponding to the number of horizontal spikes applied at its input delayed one horizontal line, and is reset to zero by each equalizing spike, i.e., it contains a binary zero count when the first group of clock pulses is received by binary counter 542. Redundancy removal circuit, Fig. 7, includes a shift register type memory 600 (non-destructive read-out type) with a plurality of rows of storage elements equal to the number of horizontal sync. pulses per frame, and the number of bits capable of being stored in any single row is equal to the number of TV-PCM bits per horizontal line. Specially each row has 3680 storage bits, information being read in via lead 630 and read out via lead 632. The particular row into which the incoming information is written is determined by a read-in stepping relay 616, and a stepping relay 614 which is always one row ahead of relay 616 effects read out. In operation the TV-PCM data is applied to a pair of alternating shift register-type memories 596 and 598 each capable of storing a single line of bits, which are controlled by AND gates 604-610 which supply clock pulses to read-in or read-out (under control of flip-flop 612 in response to each horizontal spike) from the memories 596 and 598 alternately. The information read-out of memories 596 and 598 is fed via OR gate 602 to the input lead 630 of memory 600, but is only stored therein if clock pulses are applied to the read-in stepping relay 616. The TV-PCM data is also applied to an exclusive OR gate 594 which also receives a row signal from memory 600 which corresponds to the horizontal line presently being received (TV clocks are applied to relay 614). The number of output pulses from gate 594 during each line period is thus representative of the difference in picture content of that line from frame to frame, and these pulses are fed via AND gate 592 to a counter 574 which co-operates with a decoder 572 to provide an output when the counter reaches a certain predetermined level (depends upon the amount of picture degradation considered acceptable). The output pulse from decoder 572 indicating that the received line is non-redundant sets flip-flop 576 at some time between received horizontal sync pulses so that the next horizontal spike passes through AND gate 580 to set flip-flop 582. Thus flip-flop 582 provides an output gate whose leading edge is in coincidence with the horizontal spike directly following a non-redundant line, and is used to control the entry of the prior received line into the proper row of memory 600 (AND gate 618 is energized) and the transmission thereof to the bit rate reduction circuitry (Fig. 2) via AND gate 620. Also on lead 622 clock pulses are supplied to the bit rate reduction circuit during non-redundant TV-PCM on lead 626. Gate 618, although an AND gate, has an inhibit input terminal to which an inhibit pulse is supplied from the bit rate reduction circuit (see later). Although this redundancy removal circuit compares lines on a bit-by-bit basis, comparison may be made on a word-by-word basis, each word being 8 bits long. Bit rate reduction circuit, Fig. 9, which has a bandwidth compression ratio of 2 : 1 (i.e. convert input rate of 64 megabits per second into an output bit rate of 32 megabits per second). The circuit is arranged to be capable of providing the correct output data at the 32 megabit per second output rate even in those cases when the number of non-redundant lines occurring in a single frame period exceeds half of the total number of lines. The circuit includes a pair of shift register-type memory circuits 652 and 668 each capable of storing 70 unique word bits and 3680 picture data bits for half of the active picture lines in a single frame. These two memories are alternated in their read-write functions by flip-flop 664 and AND gates 656, 658, 660 and 662 in response to equalizing spikes. The non-redundant lines and associated horizontal unique words are passed via OR gate 650 to one of these memories. The horizontal unique word is gated into one of the memories by horizontal clocks which pass through inhibit gate 672 when a gate input (from the redundancy removal circuit of Fig. 7) is present and an inhibit input is absent (see later). The non- redundant line itself is clocked into the memory by the gated clocks received from the redundancy removal circuit via OR gate 670. Readout from the memories is controlled by a 32 megabit per second clock pulse generator 686. The horizontal unique words and the corresponding non-redundant lines are preceded in each frame period by the equalizing unique word. This word must be converted from 64 to 32 megabit per second rate and this is effected by a 60-bit storage memory 694 and a pair of stepping relays 692 and 696. The timing of this normal operation in which no more than half the active lines are non-redundant is shown in Fig. 10A. To provide proper operation where the picture content changes so much from one frame to the next that more than half of the lines are non-redundant a counter 676-decoder 678 arrangement and a multivibrator 674 which provides an output .pulse having a duration equal to the TV frame time are included. The counter is capable of counting up to the number of bit storage locations in each of the memories (e.g. 918, 750), and the decoder 678 responds to this count to trigger multivibrator 674. This only happens when more than half of the lines during one frame period are non-redundant (one of the memories 652 or 668 is full). The pulse from the multivibrator inhibits gate 672 and also gate 618 in the redundancy removal circuit (Fig. 7). Thus no information is written into either memory 652 or 668 for an entire frame, however flip-flop 664 is unaffected and the readout functions of the memories are unimpaired. This results in an irregular operation in which it takes two frame periods to transmit the non- redundant line information which would ordinarily be transmitted in a single frame period. The timing of this irregular operation is shown in Fig. 10B. Receiver which is described with reference to Figs. 11-16 (not shown) comprises a memory i