Patent GB-1485189-A (GB)
Title: Apparatus for controlling the transfer of data between the central memory and the peripheral units of a data-processing system
IPC: G06F13/12
Filed: 1975-01-30
Abstract: 1485189 Transferring data COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII-HONEYWELL BULL 30 Jan 1975 [1 Feb 1974] 4174/75 Heading G4A In apparatus controlling the transfer of data between a central memory MM (Fig. 10) and the peripheral members of a data processing system connected in groups to a peripheral controller PCU, groups of peripheral controllers are connected to an input/output controller IOC (Fig. 1), which includes groups of channel head units CHU, one for each PCU, connected to a channel control circuit CCC (one for each group of head units) which include a priority circuit for determining which channel head unit is to be serviced and which are connected to a channel control unit CCU (one for one or more channel control circuits) linked to a data management unit DMU and to a common bus, bus A, connecting the operational units of the data processing system. As described the main memory is connected to the central processing unit by an interface MIU. An address calculating stage ACU which converts segmented addresses into absolute addresses allows data and instructions to be transferred. It includes an associative memory which contains information relating to the eight most frequently used segments. The data management unit allows data to be transferred into and out of the main memory and carries out alignment operations on operands and instructions. The channel control unit CCU forms the interface between the central processing unit and the channels. Each channel head receives words from and transmits words to the channel control unit which has a buffer store used for input/output operations. Control unit RCU addresses microprogram words in a control store SCU which has four sets of microprograms, one set for each of four priority levels and one set controlling the central processor. The input/output controller which shares the control store SCU, central memory interface and certain logic units, for example ALU, with the central processing unit has assigned to it 33 storage locations in working store SPU, two registers in the data management unit, 32 address locations in the address calculating unit ACU (two addresses per channel), circuits in the control unit RCU for handling I/O interrupts and four firm wave blocks, each corresponding to one priority level. A two part area of main memory is also reserved for input/output operations, one part holding a physical channel table PCT and one part holding a logic channel table LCT. Requests coming from the channel head are examined by the CCC to provide a highest priority level signal, this signal being updated at each memory cycle, representing the number of the channel with the highest priority amongst the channels making requests at this level. The CCU selects the request of higher priority from completing CCCs and provides a signal representing the highest priority level and the number of the channel of highest priority. Input/output operations are performed using channel programs, the peripheral controller accessing a channel program by using pointers. A channel program includes a four word header containing the number of the channel associated with the prgram, the priority level of the program, the name of the semaphore to which messages are transmitted and main memory area for storage in case of a fault. The address of the first word is termed the channel program absolute address and is stored in the appropriate local channel entry. The channel program also includes a two word channel control entry containing channel order flags and addressing information. A channel program is carried out in three phases-(1) connection, in which the channel program is connected to the logic channel associated with it and queued with other connected logic channels in priority order, (2) execution, in which the peripheral controller carries out the channel orders contained in the program and (3) termination, in which the peripheral controller transmits an "end of event" signal to the input/output controller. To effect the program the input/output controller takes the first logic channel from the queue using the program absolute address which is stored in the logic channel entry associated with the program and initializes program pointers CMP, CWP to access the channel program stored in main memory to transmit the peripheral control unit logic channel number from the-header and the first channel control entry. After the order associated with the first channel control entry is effected the pointer is incremented and the next order is carried out. Channel orders may relate to for example data transfer, control operations, branching or testing. When a channel program is interrupted to allow another to run (this being effected by the peripheral control unit transmitting a signal containing the name of the logic channel associated with the new program) the pointers for the first program are stored in a special area in the logic channel entry. If a data transfer is interrupted the input/output controller also transfers the appropriate entry the absolute main memory address of the last octet transferred and the number of octets still to be transferred. Each cycle of the main memory involves at most transfer of four octets, masking signals being derived to transmit 1, 2 or three octets.