Patent GB-1151893-A (GB)
Title: Improvements in or relating to Analogue Computers.
IPC: G06G7/20
Filed: 1965-07-14
Abstract: 1,151,893. RMS computers. WAYNE KERR LABORATORIES Ltd., and R. CALVERT. 14 July, 1966 [14 July, 1965], No. 29900/65. Heading G4G. Analogue computing apparatus for determining the RMS of plural input variables comprises an A.C. energized transformer having interconnected secondaries 13, 14 providing outputs (referred to neutral 9) of ratio 1 to n. The winding 13 generating the lesser voltage is shunted by n adjustable tapped, e.g. resistive, potential dividers 15, 16, 17 &c. The tap on 15 is set to an input value d 1 , that on 16 to d 2  and so on; that on 17 being set to d n . Resistances 21, 22, 23 of magnitude R are series connected with each tap to transmit currents proportional to the settings thereof into the taps of n adjustable resistive potentiometers 31, 32, 33 &c. operating as current dividers. The taps of 15 and 31, 16 and 32, 17 and 33 &c. are ganged in pairs and the current dividers are shunted across first primary of output transformer 30. Since the currents through resistances 21, 22, 23 &c. are proportional to   d 1 /R , d 2 /R, d 3 /R &c., the corresponding currents in winding 37 are proportional to d 1 <SP>2</SP>/R, D 2 <SP>2</SP>/R,d 3 <SP>2</SP>/R &c.   so that the winding is energized by a total current proportional to # d<SP>2</SP>/R  A potential divider 40 across winding 14 has its tap connected over resistor 42 of magnitude R to the tap of a current divider 44 across a further primary winding 45 of transformer 30, closely coupled to winding 37 with turns ratio 1 to n. The taps of dividers 40, 44 are ganged to a setting d s  so that current propor-   tional to nd s /R flows in resistor 42, and for the   current in winding 45 to balance that in winding 37 for null of a phase-sensitive detector 45 connected to a secondary 47 of transformer 30, n<SP>2</SP>d s <SP>2</SP>/R balances # d<SP>2</SP>/R so that d s  denotes the RMS   value of input variables d 1 , d 2  . . . dn. The adjustment of dividers 40, 44 may be automatic for null in response to the secondary output of transformer 30. For determining standard deviation of input variables d 1 , d 2  ... d n  each denoting the modulus of the difference between an input value and a mean value, the potential dividers 15, 16, 17 are each replaceable by a modulus extraction circuit, e.g. of the kind set forth in Specification 1,004,815, providing an output voltage determined by the setting on a potential divider of two taps respectively representing the input variable and the mean value. In a modification (Fig. 2, not shown) an input transformer has n equal secondaries energizing corresponding first resistive potentiometers energizing second such potentiometers; the respective taps being ganged in pairs and adjusted by the respective inputs to produce output voltages corresponding to the squares thereof, which are series added and compared with a balance voltage derived from a further secondary having n<SP>2</SP> times the turns of the equal secondaries, feeding a pair of cascaded potentiometers with ganged taps. At null, the adjustment of the latter is a measure of the RMS value of the inputs. Null may alternatively be determined by comparing currents produced by the several potentiometer pairs in a current transformer through equal series resistances. In determining standard deviation for n<10 the sum of the squares may be divided by (n-1) by adjusting the turns ratio windings 13, 14 (Fig. 1) and 37, 45 to be 1 : (n-1) and in the modified circuit (Fig. 2, not shown) by adjusting the further secondary to have (n-1)<SP>2</SP> the number of turns on the equal secondaries.