Patent GB-950911-A (GB)
Title: Modular computer system
IPC: G06F15/16
Filed: 1962-02-02
Abstract: 950,911. Electronic computers. BURROUGHS CORPORATION. Feb. 2,1962 [Feb. 15, 1961], No. 4158/62. Heading G4A. A data processing system comprises modules (independently operating, self-contained units) communication between which is controlled by a switching interlock. Modules requesting access to other modules each specify to the interlock the address of the requested module and if all the requested modules are different the interlock permits the requests to be honoured at the same time. If simultaneous requests for access to the same module are made the interlock senses conflict, orders the requests in a predetermined priority, dependent on module of origin, honours the highest priority request and queues the rest. A later request for a module having a queue can jump the queue if of sufficient priority (is pre-emptive). A request is for the transfer of a data word either between the requestor and requested modules, or in the case of a "descriptor" request,between a requested memory module and the first free input/ output control module. If more than one such module is free the highest ranked of an arbitrary ranking receives the data word from the addressed memory module. In a first embodiment (Figs. 1 and 2) input/ output (i/o) control modules I1 to I4 are connected to various forms of i/o equipment and there are computer modules P1 and P2 each of which comprises an arithmetic unit. Any of these modules may generate requests for access to memory modules although the latter cannot do so. Only computor module P1 can generate a descriptor request. A request consists of three items: the address of the memory module to which access is required, in the embodiment there are eight memory modules and a three bit address on six lines is used; a signal positively specifying that a request is being made; and a signal specifying in which direction the data word is to be transferred, from requestor to memory or vice-versa. The address is converted in an address decoder into a marking of one out of eight lines, which is an input to cross-point control 80. If the addressed memory module is not busy and if the requestor has priority then cross-point control opens gates to transfer the word address to the memory address register of the module,whereupon the required transfer takes place. The interconnections are logically simple, comprising arrays of and gates which permit paths to be set up between different parts of requested and requestor modules at the same time. The three bit requested module address is also passed to a conflict detector which by means of and gates compares the addresses issuing in any cycle and issues signals on any of fifteen lines. A high level on one of these lines indicates a conflict, that access to the same memory module is required, and the line itself represents which pair of the six requestors is in conflict. In each of the i/o modules I1 and I4 is a five but address specifying the i/o equipment for which it is acting as buffer at that stage of the programme. The last two bits of the address specify the class of equipment: magnetic drum, tape, printer &c. Of highest priority is a magnetic tape; next is a magnetic drum and all other i/o equipment is classed as having equal but lowest priority. If two of the i/o control modules have equal priority then that module with the lower numerical suffix has the higher priority. Similarly P1 has priority over P2 but both are of lower priority than i/o modules. The bits specifying the class of equipment handled by the i/o modules are examined in a priority resolver 50 and six out of twelve lines are marked to specify the relative priority of every pair of the four i/o modules. These signals are combined in queue matrix 60 with the signals from detector 40 to mark one or more of six lines to indicate the module or modules whose requests are to be immediately honoured. The inverse of this marking is sent to a hold matrix 70. This operates to set a "hold" indicator in those modules represented by the input from queue matrix and also in those modules whose requested memory is busy. These actions are a continuing process for as soon as the requested data transfer takes place the request signal from the requestor module stops and the module address is cleared. This changes the state of the conflict detector 40 and thus the queue matrix 60. Accordingly the hold indicators are reset and the next module in the queue has access to the memory module. In a descriptor operation module P1 asks for data transfer from a specified address in a specified memory to the first free i/o module. Which module this is, is determined by i/o selector 90 which on receiving a signal that at least one of the modules is free examines the "busy" bits of modules I1 to I3. If all of these are busy I4 is selected otherwise that free module with the lowest suffix. Thereafter the clocks of the requested module and the selected i/o module are synchronized and transfer takes place. In a second embodiment any of the modules can act as requestor and demand access to any other module by means of intercommunicating buses (Figs. 22 to 28, only Fig. 27A shown). The queue matrix comprises an array of flip-flips. A set flip-flop in row a, column b, indicates that there is a conflict between module a and module b and that module a has the higher priority. A sampling pulse is applied to and gates Q1 associated with columns of the array and with the unset outputs of the flip-flops of the column. If, for example, gate Q1 is opened, this indicates that there is no module of higher priority than module 1 in conflict with module 1. Row 1 of the array is reset and the request of module 1 honoured. It is mentioned without further explanation that the circuits employ transistor-diode combinations.