Patent DE-3472500-D1 (DE)
Title: Method of making floating gate mos field-effect transistor memory cells
Inventor: KLINGENSTEIN WERNER DR DIPL PH
IPC: H01L29/788
Filed: 1984-04-19
Granted: 1988-08-04
Abstract: 1. A method for the production of storage cells comprising a MOS field effect transistor which has a floating gate, wherein firstly that part of the surface of a monocrystalline silicon body provided for the storage cell is covered by thermal oxidation with a first SiO2 -layer which forms a part of the gate oxide layer for the MOS field effect transistor which is to be provided with the floating gate, and in this first SiO2 -layer, at the location provided for the erasing zone of the storage cell, a window is formed which extends to the surface of the silicon body, wherein, in a further thermal oxidation process, the surface of the silicon body which is exposed in the window is then re-oxidised and simultaneously the still present oxide covering of the silicon body is additionally subjected to the oxidation process, wherein the surface of the oxide coatings present at the surface of the silicon body are covered with a first layer of polycrystalline silicon and from this polycrystalline silicon layer the floating gate is formed, wherein, following the formation of the floating gate, the latter is covered with a thermally produced oxide layer and to this oxide layer there is then applied a further polycrystalline silicon layer, which forms the basis for the control gate of the MOS field effect transistor which contains the floating gate, and from which the control gate is formed, and wherein finally by a doping process, in particular an implantation process, which is carried out using one of the two gates as a mask, the source- and drain zones of the MOS field effect transistor provided with the floating gate are formed, wherein, following the formation of the first SiO2 -layer (Gox*), the latter is covered with an implantation mask (L), which simultaneously defines the window (F) to be produced therein down to the surface of the silicon body (ST), and, limited by this implantation mask (L), an ion implantation into that region of the silicon body (ST) which is to be exposed through the window (F) is carried out using doping ions wich lead to the conductivity type provided for the source and drain zones, wherein, after the formation of the window (F) in the first SiO2 -layer (Gox*), the production process for the MOS field effect transistor with the floating gate (GF) is continued in the usual way, wherein that region of the surface of the, for example, p-doped silicon body (ST) which is in each case assigned to the storage cell to be produce, is framed by a thicker SiO2 -layer (Dox) (LOCOS-process) before the first SiO2 -layer (Gox*) is formed at the location of the storage cell to be produced, and where the thicker SiO2 -layer (Dox) is produced on a part of the surface which is doped to a higher level than the surface of the silicon body (ST) provided for the storage cell, characterized in that - a redoping is carried out in the region of the window (F) which is to be formed in the first SiO2 -layer (Gox*), so that the window region together with the drain zone of the storage transistor forms a common zone which has the conductivity type of the drain zone, - that the redoping is carried out by means of implantation, - that the redoping is carried out immediately following the formation of the first SiO2 -layer (Gox*),and - that the implantation is arranged to be such that the redoped zone within the window (F) which is formed as a result of this implantation acquires an effective doping concentration which is approximately double the effective doping below the thicker oxide layer (Dox).