Patent GB-1091011-A (GB)
Title: Digital timebase circuits
Inventor: ENDERSBY FRANCIS GEORGE
IPC: G01S7/12
Filed: 1963-01-14
Abstract: 1,091,011. Radar; transistor circuits. NATIONAL RESEARCH DEVELOPMENT CORPORATION. April 13, 1964 [Jan. 14, 1963], No. 1518/63. Headings H3T and H4D [Also in Division G4] A digital time-base circuit for a display includes a counter arranged to generate a digital output representing the amplitude of a signal for determining one co-ordinate of the deflection of the display and a digital-to-analogue converter to which the output of the counter is applied, and includes also a ladder network of equal resistive # sections controlled by switches actuated from successive stages of the counter. The invention is particularly applicable to a radar P.P.I. display wherein a digital computer predicts the aircraft position from past data and the output of the computer produces a marker, an operator feeding a correction into the computer, if necessary every time the target echo appears, the time-base and marker deflections being produced by currents proportional to northings and eastings in fixed deflection coils. The invention affords accurate registration of marker and echo. General arrangements, Figs. 1, 2.-Outputs from a digital register 1 control gate circuits G1 ... Gn and the outputs therefrom go to a digital counter 2. The gate circuits are fed from stages of a digital counter 4 having an input from an oscillator 5 incorporating an internal gate controlled by a timing signal applied at terminal 6; as each stage of counter 4 counts a " 1 " a pulse appears on lead 3 under the control of the appropriate gate circuit G. Counter 4 is re-set by a signal applied to terminal 7. Counter 2 feeds into a digital-toanalogue converter 8, the output of which affords current to a P.P.I. deflection coil 10; counter 2 is re-set by a signal applied to terminal 11. The stages of a computer store 12 are connected to corresponding stages of counter 2 via gates CG1 ... CGn controlled simultaneously by a signal from terminal 13. Register 1 gives the sine of the angle of aerial rotation in digital form and a signal at terminal 6 ensures that for the requisite time-base duration, T1 to T2, Fig. 2, the output from oscillator 5 feeds into counter 4; at instant T2 the gate in oscillator 5 is closed and counter 2 is re-set. An inter-scan timing pulse at terminal 13 operates gates CG at instant T3 and the output of store 12 is applied to counter 2, thereby producing a marker pulse output for coil 10. Counters 2 and 4 are re-set at instant T4. Currents for the orthogonal co-ordinate are produced similarly. Digital-to-analogue conversion, Figs. 3, 4.- A digital-to-analogue converter utilizes eleven stages, five of which are shown, Fig. 3. For each stage a switch (23 to 27) connects a resistor (28 to 32) to the junction (a to e) of a different pair of resistors of the #-section network. Closure of switch 23 produces a voltage at a which is halved at b, again at c and so on; when switch 24 only is closed the output voltage is double that when switch 23 only is closed &c. Thus closure of switch 23 represents a count of 1, switch 24 a count of 2, switch 25 a count of 4 and so forth. Each switch may be as shown in Fig. 4, a diode D1 constituting e.g. the switch 24 of Fig. 3 connecting resistor 29 to the junction of resistors 15, 16, 17. A method of setting-up the resistors of the converter for a given accuracy of conversion is given. Amplifier, Figs. 1, 2, 6.-Computer store 12, Fig. 1, produces the deflection current between times T3 and T4, Fig. 2; thus the delay in amplifier 9 must be less than one digit period. The circuit of amplifier 9 is shown in Fig. 6 and comprises a D.C. amplifier with a " virtualearth" connection. Transistor TA1 affords voltage amplification and transistors TA3, TA4 provide current gain; transistor TA2 reduces the effect of changes with temperature in the base to emitter voltage of transistor TA1 and also provides for initial setting-up in which the base voltage of the former is varied until the latter just conducts. The joining of the collectors of transistors TA3, TA4 assists in the compensation of reduction of current gain in the latter as its collector current increases. The current through the deflection coil has the same waveform as the voltage at the amplifier input; the additional 0À5 ohm resistor in the collector circuit of transistors TA3, TA4 is ultilized for monitoring the current waveform in the deflection coil. The over-all feedback reduces the delay arising principally from the relatively high input capacitance of transistor TA3 and high output resistance of the previous stage. Gain can be controlled by a variable resistance in series with the feedback resistance. The 560 ohm resistor across the deflection coil inhibits a damped oscillation at the beginning of the time-base.