Patent GB-1271665-A (GB)
Title: A system for generating the fourier transform of a function
Inventor: BERTHIER DANIEL
IPC: G06G7/19
Filed: 1969-07-11
Abstract: 1,271,665. Generating Fourier transform functions. COMMISSARIAT A L'ENERGIE ATOMIQUE. 11 July, 1969 [30 July, 1968], No. 35050/69. Heading G4G. The real and/or imaginary parts of the Fourier transform of a real function Z(t) known within the limits T is calculated by means of analogue circuits including a store, a multiplier and an integrator. The real part of the transform is given by and it is assumed that the frequency spectrum of the physical function Z(t) has a limited bandwidth such that Z(f) is zero outside the interval F 0 . The spectrum is not generated continuously, but as a series of discrete values Z(0), Z(f 0 ), Z(2f 0 )...Z(Kf 0 )...Z(pf 0 ) where p#F 0 /f 0  and the sampled function may be written where f 0  is the interval between successive sampling points and #(f-Kf 0 ) denotes the Dirac delta distribution (defined by #c(x)#(x)dx=c(o), whence #c(x)#(x-y)dx=c(y). It is not possible to improve the definition of the function Z(f) by decreasing f 0  beyond a limiting value 1/2T. Hence a value f 0  = 1/2T is used. We have, therefore and a similar expression for I z  with sin instead of cos. According to the invention analogue circuits are used to multiply Z(t) by the cosine function and to integrate this product, this operation being repeated for different valves of K. To this end, the function Z(t) must be stored after sampling at intervals #. The function is therefore represented by a series of values Z(-m#) ... Z(-K#) ... Z(0) ... Z(K#) ... Z(m#) where m is an integer between 0 and T/# and ##1/2F 0  (Shannon). In practice, the function Z(t) is known by Z*(t)=##Z(p#)#(t-p#) where # is the Dirac delta distribution (as above). It is proved in the Specification that if Z(t) can be known in this manner, the values of R z (K/2T) may be found by sampling Z(t) in accordance with Shannon's sampling thereon, by multiplying each value of Z(p#) by the value of the cosine function at the time p#, and by forming the sum of these products. The mathematical expression of this process is The Specification gives a detailed proof of this statement and shows that the necessary values of Z*(t) or Z(p#) may be obtained directly from known instruments which perform auto- and intercorrelations of time varying inputs. For purposes of explanation, we assume the function Z(t) to be sampled at N points with interval # where N is the integer immediately below 2T/# + 1 or, since 2T >> #, we can write N = 2T/# + 1. Taking f 0  = 1/2T, the lowest frequency of the cosine function (K=1) will be 1/2T=f 0  and, at the end of N points of cos(2#/2T)p#, we shall have The sampling of a complete period of the cosine function, using N=41 is exemplified in Fig. 7(a) where sampling of a half period using n = 21, is shown. If now K is increased from 1 to 2, the equation for R z  above may be written with (2p#) substituted for the last factor (p#). This is equivalent to reading out the values of the cosine function in increments of two at the addresses 0, 2, 4, 6 ... (Fig. 7b). The function is then read out in increments of 3 (K=3) and so forth up to K=n-1 where n=(N+1)/2. The appropriate modes of sampling where Z(t) is given as an auto or intercorrelation function are discussed in detail in the Specification, but do not substantially affect the process of the invention. The cosine functions generated in generator 3, Fig. 13, are compared in a comparator 14 with the amplitude of pulses from a pulse generator 13 controlled by a clock 9. The clock 9 also controls the cosine generator 3 and the source of signals representing Z(p#). The comparator delivers two opposite signals Q, Q which are respectively applied to the gates of two FET's 15, 16. Values of -Z(p#) and +Z(p#) are fed respectively to the FET's 15, 16 which conduct alternately. The resultant N products are summed for a value of K by the integrating circuit 5. The integrator includes a re-setting switch in the form of an FET 8 controlled by a voltage r. The successive values of the cosine function V 0 , V 1  ... V n-1  are read out in sequence by FET's T 0 , T 1 ...T n-1 , Fig. 14, controlled by diode matrices which decode the units, tens, hundreds states of the read out address. The read out programme is obtained by means of a binary divider 18, Fig. 15, which divides by n, a decimal binary counter 19, and AND circuits 20U, 20D, 20C which receive the outputs U K  (units), D K  (tens), C K  (hundreds) of counter 19 and clock pulses from clock 9. The logic states U K , D K , C K  represent the value of K which remains constant during n pulses. The AND circuits are connected to a binary accumulator 22 whose output U a , D a , C a  leads to a decoding matrix 27 which enables 0, 1, 2 ... 199 to be obtained from U a , D a , C a  and the FET's T 0 , T 1  ... to be controlled. The AND circuits 20 cause K to be added to the contents of the binary accumulator 22 on each clock pulse. Thus, for pulses 1 to (n-1), K= 1 and V 0 , V 1 , V 2 , V 3 ...V n-2 , V n-1  are obtained at S. For the pulses n to (2n-1), K=2 and V 0 , V 2 , V 4 ... V n-3 , V n-1 , V n-3 ...V 2 , V 0  are obtained at S. For pulses 2n to (3n-1), K=3 and V 0 , V 3 , V 6 ... V n-4 , V n-1 , V n-4 ...V 0  are obtained at S, and so on. Finally, for pulses between (n-2)n and (n-1)n-1, we have K=N-1 and V 0 , V n-1 , V 0 , V n-1 ...V n-1 , V 0  are obtained at S. To reduce spurious oscillations, the samples of Z(t) may be weighted by a time function of the form sin#p/#p using a variable gain amplifier. In a modification, instead of storing n samples V 0 , V 1 , V 2  ... and reading them out in sequence, use is made of an amplifier (Fig. 16) whose gain varies in accordance with the addresses 0, 1, 2 ... The resistor 24 is equal to R/x and resistor 25 equal to R/100; the gain is therefore |G| = x/100. The resistor 24 is varied to vary the gain and Fig. 17 shows a switched array of parallel resistors R/x to which the logic word 01110110 has been applied in order to generate x=76. The switches are in the form of FET's. Each logic word has an analogue V 0 , V 1 , V 2  &c.