Patent GB-1183084-A (GB)
Title: Threshold Gate Logic Circuits
IPC: H03K19/173
Filed: 1967-07-07
Abstract: 1,183,084. Logic circuits. R.C.A. CORPORATION. 7 July, 1967 [29 July, 1966], No. 31343/67. Heading H3T. [Also in Division G4] A logic circuit comprises a minority gate feeding a weighted input of a second gate, each gate also having the same binary control signal as second input and a bias signal as third input, the first gate also receiving a binary information signal. In Fig. 2, the first gate 10 receives a control signal C, an information signal x and a bias input O, and its minority output #R feeds the second gate 12 which receives the same signals C and O. The R input to gate 12 has twice the effect of the other inputs, either by being applied to two inputs as shown, or, in the case of a transistor gate, by having a series resistor of half the value of the other series input resistors. When C is O, R is 1 irrespective of the value of x. At gate 12 the doubled value of #R cancels the C and O signals and the minority output P is therefore y where y is an additional information input. When C changes to 1, R becomes #x and the C and O inputs to gate 12 cancel each other. #P then becomes equal to R and hence to x. Thus a signal x applied to the input of 10 has no effect on the circuit until C changes to 1, when x is stored in the gate 12. In a modification (Fig. 3, not shown), the y input is the majority (P) output of gate 12 so that this gate will continue to store whatever has previously been entered into it until C changes to 1 when it will store the x input. If the bias now changes to 1, gate 12 will hold its state irrespective of the x signal until C changes to O when x will be stored in gate 12. Fig. 4 shows four minority gates interconnected to form a bi-stable circuit triggered by a signal t. Gates 16 and 20 operate as in Fig. 3 to store the 2 signal in gate 20. When C becomes 1, #R becomes #x and at least one of the O and C inputs to gate 20 will also equal #x. In addition, P, V and W can never all be the same except transiently (as shown in U.S. Specification 3,403,267) so that the majority of the inputs to gate 20 will be #x. The output #P will therefore be x. A modified version of this bi-stable circuit (Figs. 5 and 6, not shown) uses two three-input and two five-input gates with the triggering signal t applied to all four and the majority outputs of the output gates fed back to their own inputs. In addition, the minority output of one output gate is fed back to the input of the other input gate (Fig. 6, not shown) and also optionally (Fig. 5, not shown) majority output of the other output gate is fed back to the input of the first input gate. A plurality of circuits as in Fig. 6 may be used as an accumulator for storing a plurality of bits in parallel in a data processing system. The circuit of Fig. 2 may be modified (Fig. 7, not shown) by obtaining the O and y inputs from a further minority gate having C 2 , x 2  and 1 inputs. When C 1  and C 2  are both 0 the output gate stores its previous information. If one C signal becomes 1, the corresponding x signal is stored in the output gate. With four input gates and two cross-coupled output gates (Fig. 8, not shown) one of four inputs x 1 -x 4  may be stored selectively. This may be extended (Fig. 9) to any even number of inputs, the output gates being interconnected in a ring. For an odd number of inputs the last gate is as in Fig. 2 (Fig. 10, not shown). In the circuit of Fig. 11, which may be used as one cell of a shift register, four inputs x 1 -x 4  are controlled by signals C 1 -C 4 , x 1  and x 2  may be the outputs of the cells to the left and right respectively (Fig. 12, not shown), x 3  a new data bit and x 4  the complemented output of gate 59 as shown dotted. C 1  and C 2  are then the shift right and left commands respectively, C 3  the load register command and C 4  the complement register command. If C 1  becomes 1, x 1  will be accepted and stored when C 1  goes back to 0. Another bit may be written in simultaneously with reading x 1 .