Patent KR-100265602-B1 (KR)
Title: Control signal precharge circuit for bit line sense amplifier
Inventor: LEE JAE-JIN
IPC: G11C7/00
Filed: 1993-05-31
Granted: 2000-09-15
Abstract: PURPOSE: A circuit for precharging a control signal of a bit line sense amplifier is provided to compose a precharging circuit so that a precharging potential of an RTO signal becomes the potential between a power voltage(Vcc) and a Vbip and a precharging potential of a /S signal between the Vbip and the ground potential in a conventional Vbip potential in a region not enabling a bit line sense amplifier. CONSTITUTION: The circuit for precharging the control signal is to reduce data access time and power consumption by maintaining an RTO signal to the potential between 1/2(Vcc) and Vcc and /S to the potential between 1/2(Vcc) and Vss in the precharging potential of the RTO and /S which are a control signal of a bit line sense amplifier and consists circuits C, D, E and F. The circuit C includes a dummy cell A, a similar bit line B, a word line for controlling a dummy cell, a precharging circuit G for precharging the similar bit line B, a transistor MN33 whose drain is connected to a node(N31) which is a similar bit line of a dummy cell of an upper end and which applies a low data to the node connected to the dummy cell of the upper end by that a gate is controlled by a signal S1 maintaining a logic high state for a constant time during a precharge operation is performed, and a transistor MP33 whose drain is connected to a node(N32) which is a similar bit line of a dummy cell of a lower end and which applies a high data to the node connected to the dummy cell of the lower end by that a gate is controlled by a signal S2 maintaining a logic low state for a constant time during a precharge operation is performed. The circuit C applies 1/2(Vcc) - V to the node(N31) and 1/2(Vcc) + V to the node(N32) by changing the potential of a bit line precharged by 1/2(Vcc) when a precharging operation is performed as the V which is a sensing margin, like time when a data of a real cell is transmitted to a bit line. The circuit D consists two transistors(MP34,MN32) to maintain the precharging potential of the RTO between Vcc and 1/2(Vcc). The transistor(MP34) is whose source is connected to the RTO and whose gate to the node(N31). The transistor(MN32) is whose drain is connected to the drain of the transistor(MP34), whose gate is controlled by a signal S3 having a logic high state when the precharging operation is performed and whose source is connected to the ground potential. The circuit E consists a transistor(MN34) whose source is connected to the /S and whose gate to the node(N32) and a transistor(MP32) to maintain the precharging potential of the /S between Vss and 1/2(Vcc). The transistor(MP32) is whose drain is connected to the drain of the transistor(MN34), whose gate is controlled by a signal S4 having a logic low state when the precharging operation is performed and whose source is connected to the potential of Vcc. The circuit F consists a transistor(MP35) which is connected with a diode structure between the RTO and the /S and a transistor(MN36) to make so that the difference of the precharging potential of the RTO and /S signal becomes Vtp + Vtn. The transistor(MN36) is whose drain is connected to the source of the transistor(MN35) and the /S and whose gate is controlled by a signal S5 which has a logic high state when the precharging operation is performed and connects the transistors(MP35,MN35) to the /S.