Patent GB-1485874-A (GB)
Title: Control system in a computer
IPC: G06F9/22
Filed: 1974-10-07
Abstract: 1485874 Microprogramming HONEYWELL INFORMATION SYSTEMS ITALIA SpA 7 Oct 1974 [10 Oct 1973] 43315/74 Heading G4A In a digital computer, macroinstructions are fetched from a main memory (not shown) and executed by means of microprograms of 20-bit microinstructions stored in a ROS (read-only store) 2, the function code of a macroinstruction being fed to an address register 25 of an auxiliary memory 20 holding 20-bit digital words, the first bit of the corresponding read-out digital word being 1 if the macroinstruction can be executed by a microprogram from ROS 2 (an "allowed" macroinstruction) and 0 if it cannot (a "forbidden" macroinstruction). If the macroinstruction is "allowed", the microprogram from ROS 2 fetches the remainder of the macroinstruction from main memory and executes it. In the case of a "forbidden" macroinstruction, a signal is fed via an OR gate 32 to circuitry which may start a supervisory software routine to execute the macroinstruction, or to halt the computer. The arrangement allows macroinstructions, e.g. from a program written for another machine, to be executed even though microprograms appropriate to those macroinstructions are not available in the subject machine. The read-out digital words from memory 20 are used in whole or in part to augment the microinstructions obtained from an output register 3 of ROS 2, each being fed to a decoding network 4 which produces microcommands D1-DN. The microcommands D1- DN are fed to a timing network TN where they modify timing pulses TC1-TCn from a timing circuit TC to produce timed microcommands CT1-CTn controlling, with other timing pulses T1-Tn, gates of the computer. The arrangement of the computer is such that first and second digital words are required to fetch and execute each macroinstruction. The first digital words may be used to modify a single instruction fetch microprogram so as to be suitable for variable format/length instructions. Bits 12-19 of a first (fetch) digital word hold the address in memory 20 of the corresponding second (execute) digital word which has a 'forbidden" function code (i.e. bit 0 is 0). To avoid the detection of the presence of the second ("forbidden") digital word on wire 33, read-out of bit 0 is masked by a timed microcommand resetting a flip-flop 30, the inverted output of which (logical 1) is fed to OR gate 32, thereby masking the readout of bit 0 from memory 20. Bits 4-19 of the second digital word are fed via a channel 26 and a set of gates 27 to an address register 5 of the ROS 2 where they provide the address of the first microinstruction of the second (execute) phase of the microprogram. Unused bits of a "forbidden" first digital word can be used as an extension of an "allowed" first digital word by being read out in the execute phase of the allowed digital word and having the "forbidden" bit masked by flip-flop 30 and gate 32 as for the second digital words. The different ways in which the microinstruction address stored in address register 5 may be updated from internal or external data sources are the same as in Specification 1,440,856.