baber/WOPTO huggingface dataset:
Patent TW-I230936-B (TW)
Title: Optical lens system comprising two more than half-spherical lenses
Inventor: BAARTMAN JAN PETER
IPC: G11B7/1374
Filed: 2001-04-09
Granted: 2005-04-11
Abstract: The invention relates to an optical lens system (39) which is suitable for use in an optical scanning device (15) for an optical disc player. The lens system (39) comprises a first lens or objective lens (45) and a second lens or auxiliary lens (47) which are mounted in fixed positions in a lens holder (61). The objective lens comprises more than one half of a first spherical lens body (67) having a first diameter (D1), and the auxiliary lens comprises more than one half of a second spherical lens body (69) having a second diameter (D2) smaller than the first diameter. The objective lens and the auxiliary lens are surrounded by, respectively, a first circular cylindrical inner wall (83) and a second circular cylindrical inner wall (85) of the lens holder having a diameter which is substantially equal to the first and the second diameter, respectively. Said inner walls can be provided in the lens holder in very accurate coaxial positions by means of conventional tools. In this manner, a very accurate centration of the objective lens and the auxiliary lens in the lens holder is obtained in a comparatively simple manner. In a preferred embodiment, the lens holder is further provided with an internal annular abutting surface (95) for a flat boundary surface (71) of the objective lens. Said boundary surface defines the position of an optical axis (73) of the objective lens because said optical axis is directed perpendicularly to the boundary surface. The abutting surface can be provided in an accurate perpendicular position relative to the center line (87) of the lens holder by means of conventional tools, so that the optical axis of the objective lens can be simply brought in an accurate position parallel to the center line (87) of the lens holder by positioning the boundary surface of the objective lens against said abutting surface.
Patent TW-541457-B (TW)
Title: Method and apparatus for predictive flash memory erase and write times
Inventor: JACOBS ROBERT A
IPC: G11C16/10
Filed: 2001-05-02
Granted: 2003-07-11
Abstract: A NOR-gate architecture memory with an erase and write time table. The memory processor creates an erase and write time table in a table block. The table contains the most recent times for erase and write operations for each data block in the memory. When a storage operation is initiated, the processor accesses the table and estimates the amount of time it will take to perform the data storage operation and then communicates that back to a host computer. Each data storage operation results in a new table being created that is written into the data block. To save erase and write operations for the table block, the new table is written directly after the most recent table unless there is not enough space. An erase and write operation is only performed on the table block if there is not enough space for the table.
Patent TW-539711-B (TW)
Title: Stabilizer mixtures
Inventor: GUGUMUS FRANCOIS
IPC: C08K5/3435
Filed: 2001-05-08
Granted: 2003-07-01
Abstract: A stabilizer mixture containing (I) one low molecular weight alkylated sterically hindered amine compound; and (II) one high molecular weight alkylated sterically hindered amine compound.
Patent TW-559579-B (TW)
Title: Method of polishing semiconductor wafers by using double-sided polisher
Inventor: TANIGUCHI TORU
IPC: B24B37/08
Filed: 2001-05-31
Granted: 2003-11-01
Abstract: This invention is to provide a method of polishing a semiconductor wafer using a double surface polisher for increasing the flatness of the semiconductor wafer by preventing a sagging by polishing at the outer peripheral part of the wafer. During polishing, a big difference between a frictional resistance acting on the surface of the silicon wafer W from an upper surface plate 12 side and that acting on the rear surface of the wafer from a lower surface plate 13 side is given comparing with conventional method. This is because a hard foam urethane foam pad 14 and a soft unwoven cloth pad 15 are used for providing different frictional resistance against the wafer W. Each wafer W thus turns in a wafer holding hole 11a at a speed of as high as 0.1 to 1.0 rpm. As a result, even if a defect occurs during the polishing, the turning of the wafer W will not stop. In addition, an unevenly polished amount is hard to occur partly at the outer peripheral part of the wafer. Thus, a sagging by polishing can be suppressed to increase the flatness of the wafer W. During this process, the semiconductor wafer is rotated with a part of the outer periphery (3 to 15 mm) thereof protruded beyond the polishing cloths thus to polish the surface to be polished. During polishing, the outer periphery of the wafer is polished while passing through the non-polishing region each time when the wafer is rotated by a predetermined angle. Accordingly, the contact area to the polishing cloth per unit time of the outer periphery of the wafer is reduced as compared to the central area of the wafer. Consequently, this suppresses the polish-sagging in the outer periphery of the wafer thus to increase the degree of flatness of the wafer.
Patent TW-501193-B (TW)
Title: Method of forming a pattern and semiconductor device produced by this method
Inventor: KIDO SHUSAKU
IPC: G03F1/00
Filed: 2001-06-26
Granted: 2002-09-01
Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.
Patent TW-513755-B (TW)
Title: Manufacture method of semiconductor device with self-aligned inter-well isolation
Inventor: YANG FU-LIANG
IPC: H01L21/28
Filed: 2001-07-04
Granted: 2002-12-11
Abstract: This invention provides a manufacture method of semiconductor device with self-aligned inter-well isolation, which includes the following steps: forming an embedded insulation layer and a semiconductor layer on a semiconductor substrate; growing a pad oxide layer on the semiconductor layer; forming a hard-mask layer on the pad oxide layer; forming an inter-well isolation region and an intra-well isolation region on the hard-mask layer, the pad oxide layer and part of the semiconductor layer; forming a shielding layer on the hard-mask layer to expose the inter-well isolation region; removing the semiconductor layer in the inter-well isolation region in a self-aligned manner; removing the shielding layer; and forming a insulation layer to fill the inter-well isolation region and the intra-well isolation region.
Patent TW-512502-B (TW)
Title: Method for forming a wafer level chip scale package, and package formed thereby
Inventor: ALVAREZ ROMEO EMMANUEL P
IPC: H01L23/28
Filed: 2001-08-14
Granted: 2002-12-01
Abstract: A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder deposits are then disposed on the gold layer and reflowed to form balls (405) on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405).
Patent TW-511316-B (TW)
Title: Diaphragm pump and anode stream recirculation system using such pump for a fuel cell
Inventor: YANG JEFFERSON YS
IPC: H01M8/04
Filed: 2001-08-15
Granted: 2002-11-21
Abstract: The present invention mainly relates to an anode stream recirculation system for a fuel cell. The fuel cell comprises an anode stream input terminal and an anode stream output terminal. The anode stream recirculation system comprises: an anode stream supply source; a switch device connected with the anode stream supply source; an adjustment device connected between the switch device and the anode stream input terminal of the fuel cell; and a diaphragm pump striding over the anode stream output terminal of the fuel cell and the anode stream input terminal of the fuel cell to form an anode stream recirculation. Furthermore, the diaphragm pump is installed with at least a sensor which is electrically connected to the switch device.
Patent TW-521305-B (TW)
Title: Method for master planning of semiconductor production
Inventor: CHEN SHOU-CHUNG
IPC: H01L21/00
Filed: 2001-08-16
Granted: 2003-02-21
Abstract: The present invention provides a method of master planning to estimate the productivity of semiconductor processing within a specific period. The method comprises: setting a plurality of cycles in the specific period wherein a multi-layered chip can be formed in each cycle; setting a plurality of reference period within a cycle wherein at least one processing operation is completed within a reference period to form one layer of the chip in a processing period; and comparing the reference period and the total time of the processing periods corresponding to a plurality of sequential processing operations. Wherein if the total time of the processing periods corresponding to the plurality of sequential processing operations is shorter than the reference period, the processing periods corresponding to a plurality of sequential processing operations are combined within the same reference period.
Patent TW-502321-B (TW)
Title: Method for forming dual gate electrode for semiconductor device
Inventor: LEE KWANG-PYO
IPC: H01L21/8238
Filed: 2001-08-17
Granted: 2002-09-11
Abstract: A method for forming a dual-gate for a semiconductor device includes an N-counter implantation process that implants an N-type impurity ion like phosphorous through an ultra low energy implanter to provide an in-situ boron doped polysilicon layer with a stable characteristic. The method includes: forming a gate insulation layer on a semiconductor substrate; depositing a P-type doped polysilicon layer on an upper part of the gate insulation layer; forming a photoresist film on one region of the doped polysilicon layer thereby leaving an adjacent region of the P-type polysilicon layer open for a MOS transistor region; forming N-type doped polysilicon layer by performing an N-counter implantation process at the open region of the NMOS transistor; depositing a tungsten nitride layer and a tungsten layer sequentially on the upper part of the N- and P-type doped polysilicon layers after removing the photoresist film; and forming a gate electrode of the PMOS transistor constructed by the tungsten layer, the tungsten nitride layer and the P-type doped polysilicon layer and a gate electrode of the NMOS transistor constructed by the tungsten layer, the tungsten nitride layer and the N-type doped polysilicon layer by performing the photo and etch processes.
Patent TW-531868-B (TW)
Title: Soldering type anisotropic conductive film
Inventor: SHIE GUAN-SHENG
IPC: H05K3/32
Filed: 2001-08-21
Granted: 2003-05-11
Abstract: A kind of soldering-type anisotropic conductive film includes a flexible material and plural conductive particles disposed on the flexible material. The flexible material, for example, can be a thermosetting material and the heating temperature for solidifying the flexible material is the first temperature. Each conductive particle disposed in the flexible material includes a conductive ball, a soldering layer and a flux layer. The soldering layer is disposed on the conductive ball surface to wrap the conductive ball. The flux layer is disposed on the soldering layer to wrap the soldering layer. The melting point of the soldering layer, for example, is the second temperature, which is higher than the first temperature.
Patent TW-I267087-B (TW)
Title: Sensor of a read-only memory device
Inventor: CHIU CHIH-KANG
IPC: G11C5/00
Filed: 2001-09-28
Granted: 2006-11-21
Abstract: This invention discloses a sensor to retrieve the data from a read-only memory (ROM) device. The value in the memory cell of a ROM is set according to the output current and the reference current from a comparison circuit. The output current from the memory cell is outputted to a current-transmission device with the reference current, and then the output current is inputted into a current differential sensor amplifier. The current differential sensor amplifier can compare the difference between the output current and the reference current, and the difference is amplified. If a memory cell is written, the transistor in the memory cell will gain the amount of current which is equal to the reduced amount of current from the power source to the output current, thereby the value of output current from a written memory cell is smaller than the value of the reference current. If a memory cell is not written, the transistor will gain no current, so the value of the output current is greater than the value of the reference current.
Patent TW-I266386-B (TW)
Title: Dual vertical cannel thin film transistor for SRAM and manufacturing method thereof
Inventor: HSIEH IN-CHA
IPC: H01L29/786
Filed: 2001-10-03
Granted: 2006-11-11
Abstract: Disclosed is a dual vertical channel thin film transistor for SRAM and a manufacturing method thereof. The thin film transistor is applicable to a substrate and comprises a gate layer formed on a surface of the substrate, a first insulation layer formed on the surfaces of the substrate and the gate layer, a semiconductor layer formed on the surface of the first insulation layer with the first insulation layer being exposed at two side edge portions on which source/drain are respectively formed and two side surfaces of the first insulation layer, which are substantially perpendicular to the source/drain, forming a channel respectively, a doped zone being formed between the channels, a second insulation layer formed on the surfaces of the channels and the doped zone with the source/drain on the two sides exposed, and a metal layer formed on the surfaces of the source/drain and the exposed surface of the first insulation layer. The above described double vertical channel thin film transistor for SRAM comprises a dual gate and offset structure, which can remarkably reduce leakage current and requires no additional mask to form the channel. Thus, the manufacturing costs can be reduced and the manufacturing steps can be simplified. Further, since the length of the channel can be reduced to the order of deep-submicrometer, the performance of the device can be substantially improved.
Patent TW-507325-B (TW)
Title: Silicon oxide liner for reduced nickel silicide bridging
Inventor: NGO MINH VAN
IPC: H01L21/336
Filed: 2001-10-04
Granted: 2002-10-21
Abstract: Bridging between nickel silicide layers (30) on a gate electrode (21) and source/drain regions (26) along silicon nitride sidewall spacers (24) is prevented by forming a relatively thick silicon oxide liner (23) on the side surfaces of the gate electrode (21) and adjacent surface of the semiconductor substrate (20) before forming the silicon nitride sidewall spacers (24) thereon. Embodiments include forming a silicon dioxide liner (23) at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers (24) thereon.
Patent TW-535423-B (TW)
Title: Image signal processing circuit
Inventor: DAIGI TOMOAKI
IPC: H04N7/01
Filed: 2001-10-24
Granted: 2003-06-01
Abstract: An image signal processing apparatus for converting an interlaced image signal to a progressive scanned image signal is provided. Image signals of three fields are acquired for each pixel by delaying each interlaced input image signal using two field memories connected in series. An intermediate signal is selected from the three signals, and intra-field interpolation or inter-field interpolation is performed using one of the signals depending on the selection result. Meanwhile, the difference between the image signals of the preceding and following fields is calculated. If the difference is not smaller than a reference value, the intra-field interpolation is automatically performed without selecting from the two interpolation methods. Such interpolated pixel values and the pixel values of the present field are alternately read at double speed. As a result, the progressive scanned image signal is obtained.
Patent TW-589442-B (TW)
Title: Transcritical vapor compression system, and suction line heat exchanger for regulating a high pressure of a refrigerant circulating therein
Inventor: SIENEL TOBIAS H
IPC: F25B9/00
Filed: 2001-10-25
Granted: 2004-06-01
Abstract: A suction line heat exchanger storage tank for use in a vapor compression system to increase the efficiency and capacity of the system. Carbon dioxide is preferably used as the refrigerant. The high pressure of the system (gas cooler pressure) is regulated by adding charge to or removing charge from the system and storing it in a storage tank. The suction line heat exchanger exchanges heat internally between the high pressure hot refrigerant fluid discharged from the gas cooler and the low pressure cool refrigerant vapor discharged from the evaporator. The high pressure is regulated by adjusting valves. A first valve allows excess charge from the system to enter the storage tank if the pressure in the gas cooler is too high. If the pressure in the gas cooler is too low, a second valve is opened to allow excess charge from the storage tank to reenter the system. By regulating the high pressure of the system, the evaporator inlet enthalpy can be controlled to achieve optimal efficiency and/or capacity.
Patent TW-521118-B (TW)
Title: Methods for retrofitting windows with switchable and non-switchable window enhancements and retrofitted windows produced thereby
Inventor: HARARY JOSEPH M
IPC: B32B17/10
Filed: 2001-10-25
Granted: 2003-02-21
Abstract: A method for retrofitting a window by combining the window with a switchable or non-switchable window enhancement. The method includes providing a window comprising at least one relatively transparent viewing pane with first and second opposed viewing surfaces, and optionally a frame portion adapted to support and position the viewing pane(s); providing at least one mounting means adapted for securing the enhancement to the window; and securing a window enhancement to the window with at least one mounting means so that the enhancement overlies at least a portion of the viewing pane, and wherein a gap is produced between the window and the enhancement equal in width to the thickness of the mounting means. The enhancement may be mounted on either the viewing pane itself, or alternately upon the frame portion of the window. If desired, the enhancement may be laminated to a relatively rigid substrate prior to application to the window. The invention is further directed to improved, retrofitted windows produced by the method of the invention.
Patent TW-I224574-B (TW)
Title: Temperature controlled container structure
Inventor: LIM SIM ENG LAWRENCE
IPC: B65D81/38
Filed: 2001-10-25
Granted: 2004-12-01
Abstract: This invention relates to a container structure (1) for transporting goods and in particular fluids. The container structure (1) includes a receptacle (2) for accommodating the fluid, and at least one pipe (3) positioned adjacent the receptacle (2) for receiving a temperature controlling substance. The pipe (3) preferably accommodates chilled glycol whereby the chilled glycol controls the temperature within the receptacle (2). The receptacle (2) and pipe (3) are preferably surrounded by an insulating layer to improve the thermal efficiency of the container. The container has a practical application in relation to the transportation of milk.
Patent TW-512438-B (TW)
Title: High power transistor with discontinuous polysilicon gate and its manufacturing process
Inventor: HUANG LIN-JUNG
IPC: H01L21/28
Filed: 2001-11-01
Granted: 2002-12-01
Abstract: A kind of high power semiconductor device, which is capable of decreasing the capacitance between the gate and the drain, and its manufacturing method are disclosed in the present invention. In the manufacturing process of high power semiconductor device, a lightly doped silicon epilayer with the same electric type as the semiconductor substrate is formed on the semiconductor substrate and is followed by forming a silicon oxide layer and a polysilicon layer, respectively, on the silicon epilayer. Then, the polysilicon layer is etched such that each gate region is provided with a discontinuous polysilicon gate structure. At last, the following manufacturing processes for the substrate region, the source region, the contact window, the metal interconnects and so on are performed.
Patent TW-I238342-B (TW)
Title: Method for information exchange
Inventor: WANG JR-MING
Filed: 2001-11-06
Granted: 2005-08-21
Abstract: The present invention provides a method for information exchange, which is used to transmit the added book mark information at the sending site to the receiving site through the network. The method includes the following steps: first, when the sending site uses application software, selecting the added book mark information to be transmitted; then, opening and automatically attaching the added book mark information in the information transmitting software; next, entering the receiving site in the receiving field of the information transmitting software; then, transmitting the added book mark information to be received by the receiving site through the network according to the previously entered receiving site. Thus, the added book mark information in the sending site can be rapidly and conveniently transmitted to the receiving site for information exchange.
Patent TW-I221433-B (TW)
Title: A holding chuck for a tire-wheel with a chatter-suppressing device
Inventor: FUKUI KATSUMI
IPC: B60C25/132
Filed: 2001-11-07
Granted: 2004-10-01
Abstract: A holding chuck has a clamping device for firmly holding the tire-wheel in the position aligned with a center axis of a holding chuck. Chatter-suppressing dampers are disposed on an intermediate plate fitted around the chuck. The dampers are disposed on circles concentric with the center axis of the holding chuck. Each of the dampers has a damping rod extending in the direction parallel to the center axis and abutting a rim of the wheel. A damper cover is disposed between the rim of the wheel and the dampers and fastened to the holding chuck. The damper cover has slot holes disposed on a circle concentric with the center axis of the chuck which allow the damping rods of the dampers disposed on only one of the concentric circles to extend therethrough and abut the rim of the wheel.
Patent TW-I243798-B (TW)
Title: Production of fine-grained particles
Inventor: TALBOT PETER CADE
IPC: C01F17/241
Filed: 2001-11-21
Granted: 2005-11-21
Abstract: A method of producing particles having nano-sized grains, the method comprising the steps of: (a) preparing a solution containing one or more metal cations; (b) mixing the solution from step (a) with one or more surfactants to form a surfactants to form a surfactant/liquid mixture and (c) heating the mixture from step (b) above to form the particles.