Patent GB-1162060-A (GB)
Title: Bilateral Transmission System in Pulse Code Modulation
IPC: H04L5/14
Filed: 1967-12-20
Abstract: 1,162,060. Multiplex pulse code signalling. INTERNATIONAL STANDARD ELECTRIC CORP. 20 Dec., 1967 [29 Dec., 1966], No. 57893/67. Heading H4L. In a time division multiplex P.C.M. communication system between two terminal stations, an independent clock pulse generator in one of the stations is used both for transmission and reception and in the other station a slave clock is controlled by the received signals to provide clock signals for transmission and reception. General description.-As described there are m channels V1 &c., one of which, Vm is used for synchronizing, and there are n digits per channel. Each digit time slot t1 to t8 is divided into eight basic time slots a1, a2 to d1 d2. Analogue signals LAn at the master station A, Fig. 2, are converted into time division multiplex and coded at CA under the control of the materer clock pulse generator HA. At station B the received signals are regenerated at RB, decoded at DB under the control of the slave clock HB and distributed over the channels LBn. At station B, the channels LBt are multiplexed and coded at CB under the control of signals from clock HB and at station A the signals are regenerated at RA and delayed by a phase corrector PC before application to the decoder DA. The decoder DA is controlled by clock pulses derived from clock HA via a delay HR which delays the pulses by an integral number of channel time slots which is somewhat greater than the transmission time from A to B and B to A. The phase corrector PC, which is controlled by a phase comparator PD comparing clock pulses from HA with pulses HJ derived from the incoming signal, compensates for fluctuations in this transmission time and introduces a delay to ensure that the received channel time slots coincide with those defined by the pulses from HR. Master station A.-A generator CU, Fig. 4, provides digit time slot signals (t1 to t8 each divided into basic time slots a1, a2 . . . d1, d2 and channel timing signals V1 to V24 (time base HA) and V<SP>1</SP>1 to V<SP>1</SP>24 (time base HR) shifted by one channel time slot with respect to signals HA. A regenerator RA receives the signals from station B and provides retimed message signals on its output 12 and on output 11 timing signals (HJ) consisting of pairs of pulses of duration t0/8 appearing in each digit time slot of duration t0, the first pulse I appearing at the start of a time slot t0 and the second P at time t0/2. The signals on output 12 are supplied to a variable delay consisting of a shift register VD with ¢digit time slot intervals whose outputs are gated (G1 to GP) under the control of a forward-backwards counter XC. The selected output is supplied via a manually adjusted delay AD to the decoder DA and demultiplexer. The phase comparator PD compares basic time slot signals b2, a2 with signals I and P and produces an output 13a or 13b according to the direction of the relative phase difference, causing the counter Xp to count up or down accordingly, the corresponding gate G1 &c. being opened at basic time slot b1. Incoming lines are multiplexed and coded at GR, a frame synchronizing code being introduced in channel time slot V24 at ES, and transmitted over line LAB. The framing code is also retimed for the delayed channel time slot V<SP>1</SP>24 and supplied to a framing detector FD in a channel synchronizing circuit FC, Fig. 11 (not shown). The detector FD also receives the signals from delay circuit AD and with correct operation the incoming framing signal will coincide with that from ES. If an error is detected over three successive frames a counter EC applies a signal via a circuit SC to stop the phase comparison at PD, the operation of decoder DA and also to advance counter XC by two positions. This delays the signals by one digit time slot and is repeated at each cycle until framing is restored.