Patent GB-1357656-A (GB)
Title: Analogue to digital converter
Inventor: HELLWARTH G A
IPC: H03K17/00
Filed: 1972-02-21
Abstract: 1357656 Analogue/digital converter INTERNATIONAL BUSINESS MACHINES CORP 21 Feb 1972 [6 April 1971] 7891/72 Heading G4H  In an analogue/digital converter of the multiramp type, to prevent errors due to for example switching transients, an initiating input signal results in the analogue inputs being applied to the integrator after a predetermined time delay. All the switches utilized in the converter are MOSFET switches. As described for a triple ramp analogue/ digital converter, in which the analogue input V x  at terminal 20 (Figs. 3, 5) is applied to the integrator 23 (which is biased by a voltage VR3) for a fixed time represented by the full count in a counter T1, followed by a first high value reference signal VR2 until a comparator 21 detects a level VA3 at the integrator output (during which time counter T2 is incremented), a second low level reference VR2 then being applied to the integrator until a second comparator 22 detects a zero integrator output (during which time counter T3 is incremented), the application of an initial reference voltage, the input voltage and the two reference voltages are each preceded by equal fixed delays. Before a conversion cycle switch 84 shorts capacitor 54 in the feedback loop of the integrator the reference voltage VR1 being applied via closed switch 28, buffer amplifier 26 and closed switch 27A to the integrator. At a start signal, switch 28 is opened, and auxiliary counter T3 is incremented by clock pulses from the same source 25 that increments the counters T1, T2 and a -reference voltage VR2 is applied to the integrator via switch 29. After a delay determined by counter T3, the switch 84 is opened so that the integrator output drops. When it reaches a predetermined level the output 72 from comparator 21 results in switches 28, 27B being closed and switches 29 and 27A being opened. The integrator input is then coupled via switch 27B to a voltage source VR4 close to the bias source VR3. After the predetermined delay the output from counter T3 results in switch 27B being opened and switch 27A being closed so that the reference level VR 1 is applied to the integrator until comparator 22 detects a zero output at the integrator when switch 27A is opened and switch 27B is closed for the predetermined delay. Switch 28 is also opened at this time and switch 30 is closed so that when the switch 27A is again operated the unknown analogue input is applied to the integrator for a full count of the counter T1. The overflow pulse from counter T1 results in the switches 27A, 27B being again switched over for the predetermined delay and in switch 29 being closed so that at the end of the delay the reference level VR2 is applied to the integrator until comparator 21 is triggered when the switches 27A, 27B are again switched over for the predetermined delay. The reference level VR1 is then applied to the integrator until the comparator 22 is triggered when the counts in counters T1 and T2 represent in digital form the unknown analogue input. Switch 28 is opened for the predetermined delay after which the reference voltage VR1 is applied to the integrator when it is in its reset state. A filter is included between the integrator and comparators to reduce errors due to interference. To prevent large transients from occurring on the reference voltages whilst the input signals to the buffer amplifier 26 are being switched, the reference voltages are clamped during transitions to auxiliary voltages having capacitors 38, 39 shunting to ground to store the charge due to switching transient currents. Resistor 43 is varied to calibrate the reference voltage and obtain the desired gain calibration for the converter, the auxiliary voltages being similarly adjusted by resistors 47. A bias potentiometer 63 in the integrator 62 is used to compensate for offset voltage and currents in both the buffer amplifier 26 and integrator amplifier 62. Potentiometer 61 adjusts the voltage VR4 applied during the constant duration of switching intervals. A drive gate circuit 40 controls the simultaneous operation of switches 27A, 27B to ensure that it provides constant "ON" resistance and operates at precisely controlled times. At the completion of each part of the cycle the resulting control signal 75 sets, at the next clock pulse, a latch 66 connected to an amplifier 68 applying opposite polarity output signals to gate drive amplifiers 69, 70 controlling switches 27A, 27B respectively. The bias signal applied to the integrator is compensated for as described in Specification 1,352,276. Bipolar input signals may also be processed as described in this Specification.