Patent GB-1108750-A (GB)
Title: Digital computer central processor
IPC: G06F9/38
Filed: 1965-07-06
Abstract: 1,108,750. Digital computers. CONTROL DATA CORPORATION. 6 July, 1965 [8 July, 1964], No. 28546/65. Heading G4A. A central processor for a digital computer has a multiplicity of arithmetic or logical function units 212, Fig. 4, which may operate simultaneously on separate instructions from a stack 198 while coupled to selected data transfer registers in groups 182, 184, 186 reserved by the instructions via a reservation system 4, 02 which provides means for designating when conflicts in the use of specified registers by more than one function unit exist and delays calculation or transfer of a calculated result until the specified registers are free. Time sharing processors.-The central processor forms part of a system having multiple input and output channels (1.02) (Fig. 1, not shown) and multiple time sharing processors (A-J) described in Specification 1,098,258. The ten functional units 212 (1.38-1.56, Fig. 2, not shown) perform BRANCH, INCREMENT (two), BOOLEAN, SHIFT, LONG ADD, DIVIDE, MULTIPLY (two) and ADD operations. The X Operand Register Group 1.82 comprises eight 60-bit registers, (XO), Fig. 3 (not shown), for temporary data storage during calculation (XI-X5) for receiving data from central memory 1.30 and (X6-X7) for transferring results to central memory. The A address register group 1.84 comprises eight 18-bit registers (AO-A7), Fig. 3 (not shown), for addressing the corresponding X operands. The B increment register group 1.86 comprises eight 18-bit registers (BO-B7), Fig. 3 (not shown), for use by the shift functional unit (1.48), Fig. 2 (not shown). Each instruction word register, Fig. 5 (not shown), comprises (a) a six-bit (fm) portion denoting a specific functional unit, and its associated register groups, (b) a three-bit (i) portion denoting the register within a group which is to receive the calculated result from the functional unit, (c) two-three bit (j) and (k) portions denoting the registers within a group or groups to contain the entry operands. Reservation designators (508-520) typically illustrated, Fig. 6 (not shown), comprise three 3-bit registers (5.08), (5.10), (5.12) associated with each of the ten functional units 2.12, denoted as F designators for indicating the specific registers in use by the functional unit for a calculation in progress or for receiving the calculated result. Two further 4-bit registers (5.14), (5.16) denoted as Q designators are used to reserve a register presently in use by one functional unit and contains the octal code of the requesting functional unit. Two associated one-bit read flags (5.18), (5.20) indicate when the results have been returned so that next operands may be read. The reservation system (scoreboard ) 4.02 is used to place the reservations and to control the subsequent operations. Instructions received sequentially from central memory 1.30 via the Instruction Stack 1.98 and line (1.80), Fig. 8 (not shown), are initially stored in U<SP>1</SP> register (5.98) the i, j and k portions being transferred to U2 register (6.02) which checks whether the required registers are free. The fm portion of the instruction is translated at (6.08), whereby the requested Functional Unit (6.16) is selected by U4 register (6.12) for immediate use, whereby a " Unit Busy " flip-flop is set or for reservation if the unit is already in use. A third input to a translate unit (6.20) determines the register group X, B or A, e.g. X only for add, multiply &c. or X and B for increment &c. Test for issue unit (6.30) has two inputs (6.28), (6.32) indicating that the requested functional unit (616) is free and that the register to receive the operand is not reserved, whereupon the unit control (6.36) sets the F, Q designators of the requested unit (616) to identify the required registers via lines (6.34), (6.38). The operation control system comprises a Test for Read unit (6.42), Fig. 8 (not shown), which checks if the entry operands have been entered into the selected registers, whereby the selected functional unit (6.16) is controlled via lines (6.50), (6.56) to read the operands and calculate. A Test for Store Operands unit (660) determines whether the resultant operand is required by another functional unit as on entry operand, as by inputs (6.64) and (6.66). Instruction and operation sequence.-In an example shown by timing chart, Fig. 11, BOOLEAN, DIVIDE, ADD and LONG ADD instructions are issued sequentially at 100 nano second intervals but the DIVIDE and LONG ADD calculations (X 4 = X 1 /X 2 ) and (X5 = X 0 + X 4 ) are delayed pending the availability of entry operands X 2  and X 4  not yet available in entry registers reserved for the result operand of the BOOLEAN calculation X 2  X 0  (log) X 1  and the DIVIDE calculation respectively. The ADD calculation (3rd instruction) X 0  = X 3  + X 6 , however, proceeds simultaneously with the DIVIDE calculation (2nd instruction) since the registers allocated to operands X 3  to X 6  have not been reserved by other units.