Patent DE-102006021959-A1 (DE)
Title: Power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component, a stack from a vertical junction field effect transistor and MOSFET, bridge circuit, and cascade circuit
Inventor: OTREMBA RALF
IPC: H01L29/739
Filed: 2006-05-10
Abstract: The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The power semiconductor device comprises vertical MOSFETs and insulated gate bipolar transistors as power semiconductor chip component (6), a stack from a vertical junction field effect transistor and the MOSFET, a bridge circuit, a cascade circuit made of stacked semiconductor chips, connecting elements (12) with circuit board segments (27) and through-contacts (25), and a bonding wire to a contact surface of a control electrode. The chip component has electrodes on its upper- and lower side with a large surface area. The electrodes extend almost along the entire chip component and are electrically connected over the connecting elements with external contacts (13). The chip component and the connecting elements are embedded in a plastic full package-housing, which has a compacted superimposed plastic layers (15, 16) with parallel and planar upper surfaces. On one of the upper surfaces, the connecting elements are arranged as a structured metal layer in a peripheral wiring layer and are electrically connected with the electrodes and the external contacts over the through-contacts that pass through one of the plastic layers. The metal layer is formed by means of a physical vapor deposition or by means of a galvanic or chemical deposition process, exhibits different layer thicknesses and comprises several connecting elements that are electrically isolated from one another. A further semiconductor chip and/or a passive component are arranged on the circuit board segments. The circuit board segment is intended as a chip-carrier. An upper region of the circuit board segment consists of a connection region for wire bonding. The lower sides of the power semiconductor device are plastic surfaces. An external flat-strip conductor protrudes out of the marginal sides of the plastic housings, which are embedded in a bottom plastic layer of the plastic housing. The second plastic layer encases the first layer of plastic and forms the outer contour of the plastic housing. The flat-strip conductor panel is made of a super SO or a TO 220 or TO 252 type of housing. The chip component is arranged in the lower plastic layer on a chip carrier with its lower-sided electrode and on a counter electrode with a large surface area exhibiting a smaller contact surface. The chip component is mounted on the chip carrier by means of diffusion solder, a soft solder or an electrically conductive adhesive. The circuit board segment with a lower thickness is covered by a second plastic layer. The thicker circuit board segment is held free of the second plastic layer. The connecting elements are embedded in a third plastic layer. Two b switches are arranged on the first plastic layer with the metal layer and two low-side switches are arranged on the circuit board segments and on the second plastic layer. A first semiconductor transistor is electrically connected with the flat-strip conductor over the first connecting element. The drain electrodes of the two high-side switches are mounted on the chip carrier and are electrically interconnected with one another. The two high-side switches are intended in a single semiconductor unit or are intended as separate power semiconductor chip components. An independent claim is included for a procedure for production of a power semiconductor device.