Patent GB-1027647-A (GB)
Title: Improvements in or relating to devices enabling the determination of the centre of a pulse train carrying information
IPC: G01S7/292
Filed: 1963-01-31
Abstract: 1,027,647. Pulse radar. SOC. NOUVELLE D'ELECTRONIQUE ET DE LA RADIOINDUSTRIE. Jan. 31, 1963 [Feb. 2, 1962; Dec. 4, 1962], No. 3996/63. Heading H4D. In apparatus for determining the centre of a pulse train carrying information repetitive over a number of repetition periods, sets of information are stored sequentially in a binary-notation manner in a number of memory circuits the first of which stores the sets of information of weight zero (corresponding to 2‹), the second those of weight one (corresponding to 2<SP>1</SP>) &c., and additional memory circuits produce a " beginning " condition which effects the start of storage and an " end " condition which effects the cessation of storage, the latter operation producing a shift of one rank of the stored data to effect a division by two. The invention is described as applied to a search pulse radar, input echo pulses to the apparatus being gated in range and being quantized in amplitude and duration. The memory circuits include planes of ferrite cores and the invention is stated to enable a smaller number to be utilized than hitherto. A beginning condition may be one in which at least three of five consecutive pulse repetition periods each contain an echo at the gated range, and the end condition one in which not more than one of five consecutive pulse repetition periods contains such an echo. In one embodiment, Fig. 1, the beginning condition is determined by a counter 1 and " correlation " planes 7, 8; when the counter reaches the corresponding count, e.g. three, a signal is produced and is stored in a further plane 9 to afford gate-opening signals for input data entry on line E to be stored successively in memory planes 11 to 14 in accordance with binary notation, access to the memory planes being regulated by AND circuits 25 to 28, OR circuits 2 to 5, gate circuits 39 to 42 and blocking circuits 47 to 50. Circuits 32, 33 afford respective Y and X addressing. The storage process is taken over fifteen radar pulse repetition periods; at the sixteenth period memory planes 11 to 14 are read out and applied to AND circuits 25 to 28 which are all conductive and cause the closure of gates 39 to 42 to prevent information restoration in memory planes 11 to 14. The end condition is determined by the operation of counter 1 in conjunction with correlation planes 7, 8; when there is but one echo in five consecutive radar pulse repetition periods a counter output is stored in plane 10, a bistable circuit 31 fed by trigger pulses at input C 1  changes state to effect the opening of gates P 2  and closing of gates P 1 ; at the reading of the memory planes 11 to 14 their contents pass via gates P 2  to OR circuits 2, 3, 4, the ensuing suppression of the highest rank digit effecting the division-by-two (for an odd number N this is taken to be (N-1)/2). Re-setting of the apparatus is effected at the same time as the output signal, corresponding to the centre of the pulse train, issues on line S. In a modification, Fig. 2, a bi-stable circuit is associated with each output of memory planes 11 to 14.