Patent GB-1141181-A (GB)
Title: A system for compensating time delay between signals
IPC: G11B20/20
Filed: 1966-03-18
Abstract: 1,141,181. Skew time delay compensation. FUJITSU Ltd. 18 March, 1966 [18 March, 1965], No. 12169/66. Heading G4C. A system for compensating time delay or skew between equidigitally correlated multitrack signals comprises input terminals for receiving the respective input signals, respective output-pulse generating means connected to said input terminals and having each a pulse release control lead, delay-responsive means connected to said input terminals for detecting the time delay between whichever input signal, from any of the tracks, leads and all the other input signals, there being no specific reference signal track or tracks for skew-determination, clock pulse generating means connected to said delay-responsive means for furnishing a clock pulse time-positionally controlled in accordance with said delay and arranged to compensate via the release control leads delay between said input signals by time shifting the output pulses. As shown (Fig. 1a), signals received with varying delay times at input terminals T1-T7 from a multitrack tape read head (not shown) are stored in respective flip-flops of a detector unit D (Fig. 1b not shown) for synchronous readout by a reading clock signal on a line C, this clock signal being timed as described below to follow the most delayed input signal with a slight further delay. The most advanced signal of a digit group, by way of one of gates G1-G7 and a corresponding one of flip-flops FF11-FF17, sets a further flip-flop FF20 which closes the gates G1-G7 to inhibit action by subsequent signals and initiates charging of a capacitor charging circuit CR1 connected to a buffer amplifier BA1, the output voltage Erot thereof increasing linearly with time. The outputs of the flip-flops FF11-FF17 are also connected through resistors R1-R7 (the resistance of which increases in equal steps from flip-flop to flip-flop) and a common connection line to first inputs of a plurality of differential amplifiers DA1-DA7 whereby a voltage Ep characteristic of the track having the most advanced signal is supplied thereto. The respective other inputs to amplifiers DA1-DA7 are connected in similar manner through corresponding resistors and flip-flops FF21-FF27 to the inputs T1- T7 whereby each said other input receives a voltage E1-E7 characteristic of the respective track and timed according to the time of arrival of the corresponding input signal, if any. The outputs of the amplifiers DA1-DA7 are fed to respective first inputs of further differential amplifiers DA11-DA17, the respective other inputs of these amplifiers being supplied with a voltage derived from the output Erot by sampling circuits S1-S7. These sampling circuits comprise respective gate circuits opened by respective ones of signals ES1-ES7 at times determined by the times of arrival of the signals (if any) at the respective flip-flops FF21-FF27 for charging respective charging-discharging circuits according to the values Erot 1-Erot 7 of the voltage Erot at the corresponding times. The sampling circuits then discharge as shown in Fig. 3 for a general stage n (n = 1-7). The point where these discharge voltages equal the corresponding voltages En-Ep is detected by the differential amplifiers DA11-DA17 and corresponding pulses M generated which are differentiated to produce respective signals AC which are summed at G10 and the resultant differentiated by differentiating circuit DF10 connected to buffer amplifier to produce the required reading clock signal C. As well as reading out the signals stored in the detector unit D, the clock signals C reset the flip-flops FF11-FF27. In a modification (Fig. 4, not shown) separate clock signals C1-C7 are generated for each respective track.