Patent GB-1008251-A (GB)
Title: A device for learning and recognising patterns
Inventor: LEMAY CHRISTOPHER ARCHIBALD GO
IPC: G06K9/00
Filed: 1960-12-12
Abstract: 1,008,251. Automatic character reading. ELECTRIC & MUSICAL INDUSTRIES Ltd. Dec. 12, 1961 [Dec. 12, 1960], No. 42763/60. Heading G4R. A circuit for use in character recognition apparatus is arranged in one mode of operation to " learn " coded equivalents B of characterrepresenting signal trains A by storing the B values in successive addresses of a character store 16, Fig. 1, each equivalent B being recorded at one or more addresses as is necessary to distinguish the associated input train A from other input trains and there being numbers recorded in an associated store 8 having the same address leads which at each digit select the address for the next digit. When the address selected reads out a blank position in store 8 the character equivalent is read out of store 16. The characters may be scanned in a vertical raster having sample instants or by a group of photo-cells on to which the character is projected. In practice the scanning of a character may produce a signal train A of about ten bits. The circuit of Fig. 1 is designed to store five-bit character-equivalent groups B. The address leads are selected in pairs by a selector 3 the input to which is a binary number on leads 2. One of the output leads PO-PN is energized and an associated pair of gates 9 is enabled. In the learning process the signal. train A to be expected from scanning a character is applied serially at 68, setting two-stage unit 60 to reproduce the binary digits on lead 30. According as to whether the digit is " 1 " or " 0 " one or the other of the gates opens to pass a read/write pulse 32 to one or the other of the pair of first position address leads. The positive part of the read/write pulse 32 causes the contents of the selected position to be read out of the stores 8 and 16. This data is amplified at 12 and 17 and after being delayed at D3 and D6 is re-entered in the stores by the negative part of the read/write pulse under the control of gates 11 and 26. Learning.-The character equivalents B consisting of groups of five binary bits are applied at terminals 23 and the signal trains A expected on scanning the corresponding characters are applied successively at the input 68. The twostate unit 73 is reset to the " 0 " to open gates 72, 74. The binary digits of a character equivalent B are thereby applied via gates 24 to the input of store 16 and recorded at an address determined by the selector 3. The first bit of the expected signal train is applied to the line 30 and if it is " 1 " the read/write pulse will be applied to wire Poa. The read part of this pulse reads out the contents of that address in store 16 and applies them to a comparator 21 to which the character-equivalent bits group B at 23 is also applied. Gates in the comparator detect any dissimilarity to produce an output. The digits read out of the store 16 are applied to an OR gate 27 to ensure that the address is blank. If it is not the output from the gate 27 inhibits gates 24 and prevents the new B group entering the input. Supposing the address is blank, the B group applied to inputs 23 enters the store and the disparity between the input B group and the read-out causes the comparator 21 to apply its signal to gate 35. This gate is closed if the address is blank, a signal being passed to counter 14 via switch S1 only when two dissimilar B groups are compared. The counter 14 produces a group of parallel binary digits for each count which it enters into store 8 as a reference number. Whenever two dissimilar B groups are compared the counter steps on and the present value of the count is entered into store 8 via gates 13. If this reference number is subsequently read out it is applied to the input of the selector 3 via delays D2 giving one digit delay so that the reference number read out serves to direct the next digit of the A train to corresponding address. The presence of a reference number at an address of the store 8 prevents the B group in the same location of store 16 from being read out at 29. A reference number is detected by the OR gate 15 the output of which blocks gates 19. A blank address gives no such signal. Operation.-If the characters 1, 2 and 3, when scanned, produce the A trains as shown in Fig. 2a and the circuit is first to be " taught " the character " 1," the first address line to be selected is Poa since the first bit of the A train applied to input 68 is " 1." Since the store 16 is empty the gate 27 produces no inhibiting signal and the equivalent B group representing character 1 is entered from store 22 into the position Poa as shown in Fig. 2b. The comparator 21 produces an output indicating disagreement between the input B group and the blank position but the gate 35 is closed so that no signal reaches the gates 13 to connect the counter 14 to the store 8. Now the digit " 0 " the first digit of the A train expected from character " 2 " is applied to input 68 and the address lead Pob is selected for entry in store 16 of the character " 2 " B group concurrently applied to input 23. Now the character " 3 " B group is applied as before. The first digit of the A train being " 1," the address lead Poa is again selected. When the read-out pulse is applied the character " 1 " B group is read out and being compared at 21 with the input B group generates a disagreement signal. Also the OR gate 27 produces a signal since the output is no longer blank preventing the " 3 " B group being entered at address Poa of store 16. Gate 35 passes a signal to open gates 13 and the value " 1 " initially standing in the counter 14 is entered in position Poa of store 8 (8ee Fig. 2b). This value is also applied via delays D2 to selector 3 so that the output P1 is now selected. The counter 14 is also advanced to " 2 " by the delayed signal from gate 35. The next digit of the character " 3 " A train is now applied to input 68. This is "0," address lead P1b is selected and the character " 3 " B group is entered at this address in store 16. The character " 1 " B group is now re-applied to the input 23 the input 2 to the selector 3 being reset to " 0 " 's so that address lead PO is selected again. The first digit being " 1 " selects lead POa and the character " 1 " B group in this position of store 16 is read out and agrees with the input group at 23 so that no output is given by comparator 21. The gates 13 accordingly remain closed. The lead-out pulse on lead POa also reads out the " 1 " stored in store 8 and applies it to the selector 3 to select the next output P1. The next digit of the " 1 " group, being " 0 " selects P1b for the address occupied in store 16 by the character " 3 " group. Disagreement at comparator produces a signal which, passing through gate 35, opens gates 13 and enters the contents of the counter 14 (i.e. " 2 ") into the store 8 in position P1b The third digit of the " 1 " A train, i.e. " 0 " is now applied to the input 68 and at the same time the reference number " 2 " from the counter 14 being applied to the selector 3 selects the output P2 to energize the lead P2b. Since this position is blank in store 16, the character " 1 " B group is entered therein. The input to the selector 3 is now again reset to the zero condition and the character " 3 " B group is again applied to the input 3. The first digit selects lead POa and reads out the character " 1 " B group. The disagreement signal from comparator 21 is blocked by gate 28 since the OR gate 15 detects the presence of a number (1) at this position already which passes to the selector 3. The second digit of the " 3 " A train is now applied at 68 and since it is " 0 " the lead P1b is selected. The " 3 " B group is already stored at this location in store 16 so that the comparator registers agreement and no new characters are entered in either store. The third digit (" 0 ") selects lead P2b and reads out the " 1 " B group previously stored. This disagrees with the input " 3 " B group and comparator 21 generates a pulse which causes the counter to enter a " 3 " into store 8 at this address. The fourth digit (" 1 " ) selects leadP3a and causes the character " 3 " B group to be entered at this address. The first four digits of the character " 1 " A train are now applied successively at 68 and cause the character 1 tobe entered at the P3b address by similar steps and the process is repeated for all the remaining digits. Recognition.-The circuit will identify a train of bits A applied successively at 68. The switch S1 is now open and no B groups are applied at the input 23. The recognition process in effect successively eliminates the characters which may correspond to a given sequence of bits. The all-white spaces between characters are ignored and means are described for preventing a start until the character sequence appears from the scanner. The two-state unit 73 is set to block gates 72 and 74 and prevent entries being made in either store. In the recognition process the first digit of an input A train is applied to POa or POb accordingly as to whether it is " 1 " or " 0." No read out of store 16 is made if there is a next address " number at this address in store 8 because any " 1 " signal from amplifiers 12 will pass through OR gate 15 and close gates 19. If the input A train represents digit " 1," the number 1 is read out of store 8 and applied via gates 38 to the selector 3 to select the P1 lead. The next digit is " 0 " and lead P1b is selected. The read out of the B group representing " 3 " at this address is prevented by the presence of a " next address " number " 2 " at the corresponding position of store 8. The " 2 " in store 8 selects the lead P2 and the next digit of the input train being " 0 " selects lead P2b. The number " 3 " in store 8 prevents the " 1 " B group in store 16 being read out and selects the next pair of address leads. Of these the lead P3b is selected by the fourth digit " 0 " and the character " 1 " B group is read out since there is no