Patent GB-1189148-A (GB)
Title: Computer
IPC: G06F3/147
Filed: 1967-05-02
Abstract: 1,189,148. Digital calculators. CANON CAMERA CO. Inc. 2 May, 1967 [6 May, 1966], No. 20194/67. Heading G4A. A computer operating in binary-codeddecimal notion for performing addition, subtraction, multiplication and division, comprises an accumulating shift register having an addsubtract circuit, an indicating shift register, counters, and means for converting decimal digits into binary-coded form, the indicating register holding both operands simultaneously during multiplication. General.-In a desk calculator, decimal digits entered on a keyboard are converted to 8421- binary-coded form and inserted in an indicating register or an accumulator, both of which are shift registers with end-around shift. The contents of the indicating register are decoded and displayed, together with a decimal point at a position specified by a decimal point counter, and a circuit for subtracting one from the most significant is provided. The accumulator incorporates an add/subtract circuit. The keyboard includes the necessary operation keys. Addition and subtraction.-In the case of addition, assuming the augend has no less digits after the decimal point than the addend, the augend is entered into the indicating register, the number of digits below the decimal point being counted by the decimal point counter. Then the contents of the indicating register and decimal point counter are transferred to the accumulator and an auxiliary counter respectively, and the addend is entered into the indicating register. The number of digits below the decimal point of the addend is counted up by the decimal point counter and down by the auxiliary counter. If the auxiliary counter is then non-zero, the addend in the indicating register is shifted to high order, the shifts being counted up by the decimal point counter and down by the auxiliary counter, until the latter reaches zero, thus aligning the decimal points. The contents of the indicating register are added into the accumulator and the result then transferred to the indicating register. If the addend has more digits below the decimal point than the augend, operations are as before until the auxiliary counter reaches zero during entry of the addend digits below the decimal point. As subsequent addend digits are entered, the accumulator contents are shifted to high order concurrently, the decimal point counter continuing counting as before. After thus aligning the decimal points, addition &c. follows as before. Subtraction is similar. Complements.-A number in the indicating register can be converted to or from complement form by subtracting it from zero in the accumulator, the result being transferred from the accumulator to the indicating register. Multiplication.-The multiplicand and multiplier are both entered into the indicating register in that order, the number of digits in the multiplier being counted by a figure counter, and the number of digits below the decimal points of the multiplicand and multiplier combined being counted by the decimal point counter. The contents of the figure counter are copied into an auxiliary counter, then the figure counter is counted down to zero with concurrent shift to low order (with end-around shift) of the indicating register thus positioning the multiplicand at the low order end. The multiplicand is added into the accumulator the number of times specified by each multiplier digit in turn (from low order), the multiplier digit being decremented by one after each addition until it reaches zero, the additions for a given multiplier digit being followed by shift to high order (by one digit) of the multiplicand and decrementing by one of the auxiliary counter. The operation terminates when the auxiliary counter reaches zero. The result in the accumulator is transferred to the indicating register. Each decrementing of the auxiliary counter during the repetitive additions is accompanied by incrementing of the figure counter. After the multiplication, the multiplicand (in the indicating register) can be shifted back to the low order end with decrementing of the figure counter until the latter reaches zero, enabling a multiplier for a further multiplication using the same multiplicand to be entered without re-entering the multiplicand. The multiplicand was saved in the accumulator during display (in the indicating register) of the result of the previous multiplication. The result of a multiplication can be transferred back to the accumulator, and a further multiplication performed, to obtain the sum or difference of the two products. Division.-Initially, the dividend and divisor are in the accumulator and indicating register respectively, and shifted to high order leaving the most significant digit position empty. The divisor is repeatedly subtracted from the dividend in the aceumulator, with restoration on negative remainder, the remainder being shifted one digit to high order after completion of each quotient digit, the quotient digits being built up at the low order end of the accumulator. The auxiliary counter counts the number of quotient digits. Division terminates when the most significant quotient digit and the least significant divisor digit are overlaid. The quotient and remainder are transferred to the indicating register, the divisor being transferred to the accumulator. The above assumes no decimal points. Assuming decimal points, operation is as follows. The dividend is entered into the indicating register, the number of digits below the decimal point being counted by the decimal point counter. Then the dividend is shifted to high order in the indicating register but leaving the highest order digit position vacant, the shifts being counted in the decimal point counter. The dividend is transferred to the accumulator and the contents of the decimal point counter are transferred in complement form (on the register size) to the auxiliary counter. The divisor is entered into the indicating register, the decimal point counter and auxiliary counter being incremented for each digit below the decimal point. The divisor is then shifted to high order in the indicating register but leaving the highest order digit position vacant, each shift counting up the decimal point counter and auxiliary counter. Since the counter capacities correspond to the register lengths, the auxiliary counter now specifies the position of the decimal point in the quotient relative to the highest order quotient digit. The division proper now follows (see above). After the division the contents of the auxiliary counter (also modified during the division proper see above) are transferred to the decimal point counter to indicate the decimal point position in the quotient. The quotient in the indicating register can be cleared, and the remainder and divisor transferred back to the accumulator and indicating register respectively, permitting further quotient digits to be obtained in the same way.