Patent GB-1194775-A (GB)
Title: Electronic Navigational Bearing Computer Arrangement
IPC: G01S1/02
Filed: 1968-03-22
Abstract: 1,194,775. Radio navigation; phase discriminators. GENERAL DYNAMICS CORP. 22 March, 1968 [23 March, 1967 (2)], No. 14096/68. Headings H3A and H4D. In a TACAN type receiver wherein a backward stepping counter 66, Fig. 1., recycles at 135 Hz in synchronism with a pulsed 135 Hz signal, derived from a phase-locked loop 10 receiving and locking on to the 135 Hz component of the TACAN signal, and has its count read out on occurrence of the next North reference pulse, to give a bearing indication, logic circuits are provided such that an "unreliable bearing" indication is produced when the 15 Hz component of the TACAN signal is absent. The phase-locked loop 10 comprises a voltage controlled oscillator 40 having a basic frequency of 27À63 kHz. The output of said oscillator is frequency subtracted from that of a stable crystal oscillator 24 at 580À59 kHz in logic means 42 to produce a signal at 552À96 k. This signal is frequency-divided by 4096 in counter 44 to produce a reference signal at 135 Hz nominally in phase quadrature with the 135 Hz component of the TACAN signal. A phase detector 36 to which said component and said reference signal are supplied and the output of which controls the oscillator 10 thus produces no output when the two inputs are exactly in phase quadrature. The counter 44 and logic means 46 can thus produce square and pulse signals 135 Hz < 0 degrees, and 135 Hz < 180 degrees, respectively, Fig. 2, in phase-locked relationship with said component of the TACAN signal. A divide by nine counter 50 produces a clock signal at 61À44 kHz, Fig. 2, from the output of oscillator 40. A phase-locked loop 12 and logic AND circuits 32, 34 similarly produce signals 14 Hz < 0 degrees, 15 Hz < 0-39 degrees, 15 Hz < 20 degrees, 15 Hz < 90 degrees and 15 Hz < 180 degrees, Fig. 2. A second clock signal at 61À44 kHz is produced by logic means 28 and fed to one output of AND gate 88. With respect to the 15 Hz and 135 Hz components of the received TACAN signal four possibilities occur and the circuit of Fig. 1 can operate in a primary or secondary mode, according to the following table. The mode determines which clock output is fed to the counter 66 and which 15 Hz < 20 degrees is used to synchronize the counter 66 via OR gate 84. A mode detector circuit 14 is thus provided. For possibility (1) above phase detector 48 gives a positive " 15 Hz present " output, and phase detector 56 also gives a positive output resulting in no output from inverter 60. AND gate 62 is thus not enabled and its zero output is inverted at 64 to a positive signal which enables gates 68 and 80. The clock signal from counter 50 is thus passed via gates 68 and 70 to counter 66 which commences to count down from 4095. The counter would thus recycle at 135 Hz. The 135 Hz < 180 degrees output of AND gate 46 passes via gates 80 and 84 and each with pulse thereof passes via AND gate 82, enabled by the 15 Hz < 0-39 degrees signal, to reset counter 66 to 3868. On the scale of 4095 # 0 degrees and 0 # 360 degrees, 3868 # 20 degrees so that the counter is thereby synchronized. The #15 Hz present " signal part enables AND gate 74 such that when the next North reference signal appears, and during an interval between a change of count (as determined by inverter 76), AND gate 74 produces an output enabling transfer gates 78 and passing the count then in counter 78 and representing the bearing, into register 72. The register feeds its output via a digital to analogue converter 90 to a display 92. For possibility (2) above the only difference from the previous is that inverter 54 now gives a positive #15 Hz absent " signal, whereby AND gate 74 is no longer enabled and the transfer of the count in counter 66 no longer takes place on reception of the North reference signal. AND gate 96, however, is part enabled and a 3À75 Hz signal for divider counter 94 passes to the register after about 3 seconds of 15 Hz component absence as determined by the attainment of a count of four in a counter 98 receiving a 15/16 Hz signal from divider counter 94. The feeding of the 3À75 Hz signal to the register causes the bearing at display 92 to change and indicate an "unreliable bearing" state. For possibility (3) above the operations is the same as for possibility (2) above except that AND gate 62 has one input "line" from inverter 60. For possibility (4) above, AND gate 62 has both inputs "line" and so produces an output enabling AND gates 86 and 88. The clock signal now comes from logic circuit 28 and the 15 Hz < 20 degrees synchronizing signal for the counter 66, comes from gate 32. AND gate 74 is enabled as is possibility (1) above whereby a register 72 receives the count of 66 and a meaningful bearing indication is produced at 92. The phase discriminators 16, 36, 48 and 56 may comprise. Fig. 3, an input, to which the required sinusoidal component of the TACAN signal is applied, which input, via capacitor 152, feeds operational amplifiers 154 and 156 yielding signals in antiphase and in phase, respectively, with said component, and an input transistor 120 receiving the respective square wave from the respective phase locked loops. Switching transistors 116 and 118 are controlled by control transistors 126 and 128, respectively, which are in turn controlled by the output of inverter transistor 124 and by the direct output of transistor 120, respectively. Thus during the positive half-cycle of the square wave transistor 116 conducts and shorts the output of amplifier 154 to earth, whilst transistor 118 is blocked and the positive half-cycle of the output of amplifier 156 is fed to output 130. Alternately during the negative half-cycle of the square wave transistor 116 is now blocked and the positive second half-cycle of the amplifier 154 output is fed to the output 130. Similarly for an antiphase condition between the two input signals, the two negative half-cycles of the amplifiers' outputs are available at 130 and for an intermediate phase relationship a confirmation of the amplifiers' outputs appears at 130 having a D.C. component indicating said phase.