Patent GB-1207169-A (GB)
Title: Information processing system
Inventor: GOSHORN LARRY ARTHUR
IPC: G06F13/12
Filed: 1967-12-22
Abstract: 1,207,169. Digital computers; digital data storage. GENERAL ELECTRIC CO. 22 Dec., 1967 [22 Dec., 1966], No. 58448/67. Headings G4A and G4C. In an information processing system, a control word is obtained from a first storage location specified by an operand address portion of a command word, the control word having a first field specifying a block of storage locations, a second field specifying a beginning item in the block, and a third field specifying the number of words currently stored in the block, and the operand address portion is combined with at least the second field of the control word to specify a second storage location, and. in response to a list-availability condition in the control word a word is transferred between the second location and a peripheral buffer identified by a device code stored in a third location having a predetermined address relative to the first location. Peripheral devices (input, output and bulk storage) have respective lists in the computers' main memory. Each list consists of a list control word (at address Z say) immediately preceded by a word containing a device code and followed by the list proper which occupies addresses Z + 1 to Z + 2L. The list control word specifies L, and also contains a list full bit, a list empty bit, a field N giving the number of addresses currently occupied in the list proper and a field F. The occupied addresses are Z+1+(F+1) to Z + 1 + (F + N) inclusive, these addresses (excluding the Z portion) being taken modulo 2<SP>L</SP> so that the list is circular. A command (instruction) IDL causes transfer of a word from a peripheral device to the end of its list, i.e. the word is inserted at address Z+[1+F+ N + 1, modulo 2<SP>L</SP>]. Similarly a command ODL causes transfer of a word to a peripheral device from the beginning of its list, i.e. address Z+[1+F+1, modulo 2<SP>L</SP>]. In both cases, the operand address portion of the command specifies the address Z of the list control word, the identity of the peripheral channel, buffer and device (to control routing) is provided by the device code in the word preceding the list control word and the list control word is updated before being restored into main memory. The programme proceeds at the next but one command after the IDL, ODL command. However transfer and updating will not take place if it involves storing into a full list or removing from an empty list. In this case the programme proceeds at the command immediately after the IDL, ODL command. An IDL or ODL command may alternatively be activated in response to an interrupt. An interrupt module scans interrupt lines from the peripheral devices. When it detects an interrupt request it requests an interrupt of the central processor. When this is granted, the interrupt module supplies the address of an IDL or ODL command which is then dealt with as above, except that if it is not executed because it involves addition to a full list or removal from an empty list, the interrupt module is signalled and makes another interrupt request to initiate a subroutine for appropriate action. The arithmetic operations implied above are done as in Specification 1,207,167 which is referred to, apart from the decrementing of Z by one to get the address holding the device code which is done by adding all ones in the parallel adder and discarding high order carry. The present invention may be incorporated in the system of that Specification.