Patent GB-1214652-A (GB)
Title: Numerical display system
IPC: H03K21/08
Filed: 1967-11-21
Abstract: 1,214,652. Numerical display systems. NIPPON COLUMBIA CO. Ltd. 21 Nov., 1967 [28 Nov., 1966 (2); 25 Jan., 1967; 8 March, 1967], No. 52889/67. Heading G4H. A numerical display system comprises a plurality of indicators each capable of indicating a digit 0-9, and having corresponding input terminals t0-t9 connected together in sets, a shift register R, Fig. 4, having positions for a number of digits which are read out sequentially, the indicators being sequentially selected in synchronism with the stepping of the register to display the digits in the correct positions. The digits are stored in the register in binary coded form. Shifting is by pulses from a clock U, which also pass via gate Q1 to counter F. The output of the counter is applied to a series of decoders C1-Cn responding to different counts and connected via switches B1-Bn to select the indicators A1-An in turn. The register has a recirculating loop and the output is applied to a series of decoders D0-D9 responding to the digits 0-9 to apply signals to the corresponding terminal sets t0-t9. A decimal point code s may also be stored in the register, a decoder Ds responding to this code to apply a signal to the interconnected point terminals ts. The digits are repeatedly displayed on the indicators in sequence, and the circuit cycles with a rapidity sufficient to give a steady display. When the decimal point s is read out, the decoder Ds output also passes via inverter N2 to open gate Q1. The following shift pulse therefore does not pass to the counter F and the same indicator remains selected so that the following digit is displayed on it. The decimal point indicator is placed to the left of the digit indicators. The gate Q1 opens again and subsequent digits are displayed as before. Zero suppression.-Zeros to the left of the highest significant digit are suppressed by the arrangement shown in Fig. 6. The counter F selects the indicators Al-An in the opposite order, the highest significant indicator An first. At the end of the cycle a signal from decoder C1 selecting indicator A1 passes via gate Q2 to set a flip-flop H to disable all gates Ml-Mn inserted between decoders C1-Cn and switches B1-Bn. If, when the indicator An is selected the corresponding digit is a zero, the output from decoder DO, being inverted at N3, does not affect the flip-flop. Gate Mn remains disabled and no display appears on indicator An. If the next digit is also zero the same thing happens. If it is any other digit it causes the flip-flop to reset and subsequent digits are displayed. The indicators may be multicathode tubes having shaped cathodes, the selected one of which glows. The power for energizing the cathodes may be supplied through a transformer so that, if the counter F fails, the tube will not be damaged by the application of a prolonged heavy current. The transformers may be arranged in a matrix (Fig. 10, not shown) each being selected by signals on one column lead and one row lead. Indicator tubes.-The digit indicators may be enclosed in a single envelope and separated by screens. The screens may serve for the display of the decimal points.