Patent GB-1034814-A (GB)
Title: Improvements relating to data sorting devices
Inventor: LEMAY CHRISTOPHER ARCHIBALD GO
IPC: G06V10/75
Filed: 1962-04-13
Abstract: 1,034,814. Learning circuits. ELECTRIC & MUSICAL INDUSTRIES Ltd. April 5, 1963 [April 13, 1962], No. 14293/62. Heading G4R. A learning and recognising circuit for electric signal patterns comprises a store having a series of address positions in each of which may be stored an input pattern as associated output pattern and a corresponding address group selector number, which serves to select successive groups of addresses, the particular address being selected by comparator means comparing the successive stored input patterns with the applied input pattern. The device " learns " to associate one of a number of different input signal patterns, which are applied in parallel on terminals 4, Fig. 1 (not shown), with output patterns which are applied in the learning process on inputs 7. The device comprises a binary signal store 1 having three sections 1a, 1b, 1c, each being a matrix store of the thin magnetic film type which are interrogated by an oscillatory signal without affecting the stored data. The output is a continuous phasesignificant signal indicating which of the two binary states is stored at the corresponding position in the store. The terminals 4 are connected via gates 10 to the digit (column) wires of section la. The output from the sense wires are connected to equality gates 17 for comparison with the signals on terminals 4. This is in effect the read out from one address of the store section produced by energizing the corresponding address wire. The same address wires traverse all three sections of the store and are energized by selector 2 controlled by number store 21. The outputs of the comparison gates 17 are added at 44 to produce an analogue sum signal which is stored at 18 and 27, the latter being designed to retain only the largest values and to ignore lesser values, that is to detect the maximum. The value in store 18 is compared with the output of the adder 44 by differencer 19 which has an output applied to gate 48 indicating that the adder output is larger and an output passing to gate 38 indicating that it is smaller. Two-state unit 20 is set to " 1 " or " 0 " by these outputs. The terminals 7, which are energized only during the learning process are connected via gates 12 to store section 1c. The outputs of this section are connected via gates 29 to store 31 and to OR gate 9. The store 31 is connected to output terminals 5 and to comparison gates 24 for comparison with the input signals on terminals 7. The gates connect to an AND gate 25, the output of which, indicating identity, is applied to AND NOT gate 14 and OR gate 22 connected to an AND NOT gate 23 also receiving an input from terminal 8. The output of this gate enables gates 10 and 12. During a learning process the terminal 8 is energized to open gate 16 and gates 11 which also receive the outputs of counter 3 via gates 15. The counter signals pass via gates 11 to Section 1b of the store, the outputs of which pass to OR gate 26 and via delays 37 to the number store 21. The output of gate 26 is applied to AND NOT gates 42 and 13 and via inverter 40 and delay 51 to reset the stores 18 and 27 to half their maxima. The stores are accordingly reset when there is no output from the section 1b. Gate 9 is connected via AND NOT gate 42 and delay 5 to OR gate 38 and AND NOT gate 48. The output of gate 42 also passes via delay 35 to two-state unit 30 and via delay 36 to gate 34. Unit 30 is set to " 1 " by a signal on terminal 47 and then inhibits AND NOT gate 34. The output of gate 34 available on terminal 6, indicates that the output on terminals 5 is acceptable and serves also to reset store 31. The output of gate 9, delayed at 49 is applied via gate 13 to gate 14 enabling gates 15 and 16. The output of gate 16, delayed at 39, passes to the counter 3 to add one. If the signal stored in store 27 from adder 44 increases rise detector 28 (a differentiator) gives a signal opening gates 29 to enter the output of section lc into the store 31. The addresses are designated " 0, 0," "1, 0 " &c. as shown, the first digit being the number in store 21 and the second the state of unit 20. Learning process.-Inputs are applied to terminals 4, 7 and 8, at 4 the input, at 7 the desired associated output and at 8 a " learn " signal. The signal at 8, if gate 23 is open, enables gates 10 and 12 so that the inputs at 4 and 7 may be recorded in sections 1a and 1c at addresses selected by selector 2. The counter 3 stands at 1 and the first selected address is " 0, 0." There is no output from section 1c since the store 1 is empty. The signals at 7 are recorded. Gate 9 gives no signal. The comparison gate 25 gives no output and accordingly gate 22 gives no output so that gate 23 remains open and the pattern at 4 is recorded in section 1a. A comparison takes place after storing in gates 17 giving a score of four and the corresponding analogue signal from adder 44 is applied to stores 18, 27 and to differencer 19. Store 18 is initially set to half value so that the differencer 19 shows a rise. This causes the selector 2 to continue to select the address wire " 0, 0." Similarly, rise detector 28 detects a rise in the value in store 27 and allows the value in store lc to enter store 31. The output of store 31 and the input 7 are now compared in gates 24. The identity signal from gate 25 closes gate 14 against a signal from gate 9 through delay 49 and gate 13. New input patterns are now applied to terminals 4 and 7 which are compared with that stored at address " 0, 0 " in gates 17 and with that in store 31 in gates 24. The second comparison indicates lack of identity by the absence of an output from gate 25 so that gate 14 opens and a signal from OR gate 9 passing through delay 49 and gate 13 is applied to gates 15 so that the initial value " 1 " of the counter is entered in the section 1b of the store. A signal from OR gate 26 resets stores 18 and 27 to half value. The signal passing through gate 14 also passes via gate 2 and delay 39 to advance the counter to " 2." The comparison in gates 17 with the first pattern stored gives a signal from 44 less than the maximum. If it is less than half the differencer 19 leaves the two-state element 20 in its " 0 " condition. A signal indicating more than half sets element 20 to the " 1 " condition. Simultaneously, the number in section 1b is entered in number store 21 so that selector 2 selects a new address wire " 1, 0 " and " 1, 1." If the new pattern at terminals 4 resembles the first pattern by more than half the digits, it will be stored at position " 1, 1" if less than half, at position "1, 0," the pattern 4 being stored in section 1a and the corresponding output pattern 7 in section 1c. The address selector is reset to select " 0, 0 " again so that, for each set of patterns 4 and 7 applied, the circuit cycles through all the occupied address positions. The same data cannot be recorded twice and successive patterns are stored in the " 1 " or " 0 " positions of successive addresses depending on whether half their digits correspond with the previously stored pattern or less than half correspond. At each address position an input pattern from terminals 4 is stored at 1a and an output pattern from terminals 7 at 1c. Also for each pair of patterns except the last successive numbers are stored in section 1b. Recognising.-Initially the address selector will select address " 0, 0." When an unknown input pattern is applied to terminals 4 it is compared with the pattern stored at this address, stores 18 and 27 having been reset to half maximum value. If more than half of the digits correspond the differencer 19 sets the two-state unit 20 to " 1 " and a " 1 " from section 1b at address " 0, 0 " passes to number store 21. The selector 2 therefore selects address 1 " stores the output pattern in store 31 and the value of the match signal is stored in store 27. The input pattern is now compared with the pattern in address position " 1, 1 " and if a better match is obtained the detector 28 stores the new output pattern in store 31. The process continues, even if a perfect match signal is produced by adder 44 until the last stored pair is reached, there being no number stored in section 1b for this pair so that gate 26 gives no output and gate 42 opens to allow the address selector to be reset to " 0, 0." If the last comparison gives the best match the corresponding output will enter the store 31 as before. The resetting signal from gate 42 causes a signal to appear on terminal 6 indicating that the pattern in store 31 available at terminals 5 is the best match with the input pattern. Store 31 is reset through delay 43. If the input pattern changes during a recognition step the process is inhibited and resetting takes place to begin the recognition again. Alternatives.-The matrix store 1 may be replaced by a drum store if the patterns to be stored have a large number of bits. Alternatively, the number of bits may first be reduced by apparatus converting a large number of serial bits into fewer parallel bits each representing a combination of the initial data, e.g. features of a scanned pattern shape. Where a large number of patterns are stored the recognition process may stop when a maximum comparison signal is produced. The most common patterns may be collected together in the beginning of the store to reduce the searching time. If two stored patterns produce the same match score, an output is refused by comparing the contents of the maximum score store 27 with the output of adder 44. Equality lasting more than a predetermined time sets a twostate element which will prevent the output being taken. The two-state element is reset by a larger match signal if one follows.