Patent GB-1532435-A (GB)
Title: Device for supplying time signals
IPC: G01D15/26
Filed: 1975-12-04
Abstract: 1532435 Electronic timepieces G GRIMM 4 Dec 1975 49910/75 Heading G3T An electronic master clock arrangement for providing time signals to chart recorders such as in recording KWhr meters, has means for storing time signals during interruption of power supply connected to the recording meters and adding the number of pulses stored to the chart recorder input when the normal conditions are restored, whereby the chart will be located at the proper position with respect to time of day. The clock, Fig. 1, is normally energized from A.C. mains 41 via rectifiers and a battery 43 serves as an energy buffer which also tends to filter out disturbance signals from the supply. When the A.C. mains fails, the battery serves to supply the clock. The clock comprises a crystal controlled oscillator 1 followed by a frequency divider 2 which feeds 1Hz to a counters unit 5 including sees, mins, hours and days counters 6-9 respectively. From the counters content a de-coder driver 40 drives a liquid crystal time display 39. A recording period pulse generator 10 receives minute pulses from counter 7 and produces timing pulses at the desired recording period, e.g. every 3 mins. The timing pulses are normally passed by a changeover switch means 19, through an optical link 38 at output 14 of the clock, to a counter 15 of a chart recorder 17. When a detector 20 detects a failure of the A.C. supply, its output 24, Fig. 2, changes over the switched means 19 so that the timing pulses from generator 10 pass to a store 18 instead of to the recorder 17. In the store, the timing pulses pass directly and via a logic circuit to control input 32 and timing input 31 respectively, of an up-down counter 30. The counter 30 begins up-counting the number of timing pulses which occur during the interruption. When the interruption is cleared, a signal at an output 25 of the detector 20 resets a ring counter 28b to zero and opens an AND gate 26 to pass a pulse train at 1Hz, derived from the frequency divider output 3 via a pulse shaper 28a, to the ring counter. The latter produces a 5 sec. pulse train in line 29, which pulse train is fed to the counter intput 31 and the counter counts down accordingly. The pulse train is also passed by an AND gate 35 to the clock output 14 until when the number of pulses delivered by the ring counter 28b equals the number of time signal pulses originally stored by the counter 30 and the counter 30 is completely empty whereupon the AND gate 35 is blocked. Thereby the lag due to supply failure, in the feed advance of a chart in the recorder, is made up. Any timing pulses from the pulse generator 10, which occur when counter 30 is being emptied after the supply is restored, are not lost since they act to replenish the counter 30. In an embodiment Fig. 3 (not shown), when the supply is restored the pulses corresponding to the stored count are fed to the chart recorder in between normal timing pulses. SETTING Setting of the clock is described with reference to Fig. 5 (not shown). For forward setting additional pulses from a setting pulse generator (55) are fed via respective switching devices (54) to (57) to the inputs of counters 6, 7, 8, 9. For backward setting, pulses to particular counters are blocked by the switching devices.