Patent GB-946457-A (GB)
Title: Computer
Inventor: BAKER GEORGE THOMAS
IPC: G06F17/10
Filed: 1960-03-29
Abstract: 946,457. Digital electric calculating apparatus. TEXAS INSTRUMENTS Inc. March 29, 1960, No. 11076/60. Headings G4A and G4C. A data processing machine comprises a continuous recording surface divided into data blocks, each of said data blocks being divided into a first half and a second half; and means for reading a digital word out of the first half of said data blocks in a predetermined sequence and for recording the digital word currently applied thereto in the second half of each of said data blocks in said predetermined sequence. The invention is applied to the analysis of seismic data in analogue form which has been sequentially sampled and converted to binary digital data. This digital data is stored on a magnetic tape divided lengthwise into data blocks, each block storing an identification number in the first channel. The tape, Fig. 2, has 14 tracks, tracks 7 and 8 producing block and clock pulses, respectively. Each word is stored crosswise with the sign in track 9 and the odd and even binary orders in tracks 14-10 and 1-6, respectively. Each block has 64 channels and a pulse is generated in a reading head only when there is a change in magnetisation in the corresponding track from one channel to the next. Digital data is recorded initially only in the A section of a block, the B section being available as a large capacity store. Input-output unit 11, Figs. 3a, 3b. When the first channel of a data-block is passing under read heads 33 a block pulse sets channel counter 26 to zero and flip-flop FF48 to 1. The identification number in the first channel of the block is read, amplified at 30, converted to dual conductor system, and registered in time buffer 23. The word is retained in buffer 23 while the block is being processed, after which a command signal RT1 transfers it to information distribution unit 15 over the route 77, 80,81. To read out from a selected channel the number of the channel is set up in the lower 5 stages of unit 15. Command WT2 transfers it to the channel register 25 and command RMT clears read buffer 22. When channel counter 26 registers the same count as channel register 25 coincidence logic 27 enables the read amplifiers 30, and the word from the selected channel is registered in read buffer 22. Logic 27 also sets FF 87 to O to transfer the contents of read buffer 22 over route 75,80,81 to information distribution unit 15, after which blocking oscillator 83 sends a signal 'RMT completed' to control unit 14. Sequential reading of channels can be effected by command IT2 increasing the contents of channel register 25 by unity. When the channel counter 26 reaches a count of 31 coincidence logic 27 sets FF48 to O so switching the apparatus from reading to writing for section B. Recording a word in a selected channel is effected, with this difference, in substantially the same manner as reading, use being made of write buffer 24 and command signal WMT, FF 86 causing the command completed signal to be sent to the control unit. Reading from section B and recording in section A can be effected by reversing the tape, adjustments to the circuit being made automatically by means not shown. Printing. The word to be printed is registered in information distribution unit 15. A command WPT registers the word in write buffer 24 and switches FF72 to 1 so that the word passes through binary-octal switch 38 to printer 39. The word can be printed in either binary or octal code. Printer 39 returns FF72 to O to return a 'WPT completed' signal to the control unit. Paper tape reader. Digital data is stored on 6 tracks. The sprocket hole and seventh track are used for control purposes. A 12-digit word is stored by using two read positions. A command RPT sets read buffer 22 to zero, sets FF 37 to O, and starts the tape drive. The 6 digits from the first read position are registered in the upper 6 orders of read buffer 22. At the next read position the sprocket hole switches FF37 to 1 so that the 6 digits from the second read position are registered in the lower 6 orders of the read buffer. As FF37 is switched it sends signals PTW to the control unit which transfers the word from read buffer 22 to the information distribution unit 15, after which the end of the word transfer is signalled to control unit 14. The process repeats for successive words, a seventh track hole indicates the end of a block of words and causes the tape to stop. A signal 'RPT completed' is then returned. A digital-toanalogue conversion can be effected through apparatus 20. Arithmetic unit 12, Fig. 8. The addend and multiplier registers each have 12 stages. The accumulator has 24 stages and comprises both carry and sum registers. Transfer to and from the register is effected by command signals specified below in connection with the arithmetical operations. Addition. The command ADD causes the word in the addend register to be added to the word in the sum register, carry being stored in the carry register. A command EMC then empties the carry register into the sum register. A command CCR then clears the carry register. Multiplication. The multiplier is stored in the multiplier register and the multiplicand in the addend register. Beginning with the 2‹ stage each significant digit in the multiplier causes addition of the multiplicand to the accumulator with shift of the multiplier and sum registers to the right at each stage operation by commands SMR and SSR, respectively. Division. The divisor is stored in the multiplier register and the dividend in the sum register. The divisor is shifted left by command SML until the most significant digit appears in stage 2<SP>10</SP>. The number of shifts is used subsequently to determine the binary point of the quotient. The divisor is then transferred to the addend register via information distribution unit 15 and complemented, the result being added to the accumulator. The carry register is then emptied in such a manner that the carry from the 2<SP>10</SP> stage is transferred to the S stage, the S stage being at 1 or 0 according to whether the word stored is negative or positive. The carry register is then cleared. If the result of the operation is +ve 1 is entered into stage 2‹ of the multiplier register. The sum register is then shifted left by command SSL so that the bit stored in stage 2<SP>10</SP> is transferred to stage S. The multiplier register is also shifted left by command SML and addition again takes place. The process repeats with 1 being entered in the multiplier register each time until the contents of the sum register become negative. This time O is entered into stage 2‹ of the multiplier register and the addend register is complemented. The process repeats. When the number in the sum register again becomes positive the addend register is again complemented, and so on. The arithmetical operations are performed by parallel-adders, with carry effected by logical circuits (Figs. 9-12, not shown). Programming. Multiplication. When control unit 14 issues a command micro-programming results. Thus command MUL orders the multiplication of two binary numbers, one in the multiplier register, the other in the addend register. Fig. 13 shows the relevant microprogramming circuit. Command MUL sets FF 101 to 1 and starts oscillator 109 which supplies pairs of pulses to a magnetron type of distributer 109. Suitable inverters are provided to make the output pulses positive. With the distributer at position O the signs of the numbers in the addend and multiplier registers are set up in FF 116, FF 117, respectively. If the sign in the addend or multiplier register is -ve, lead CAD or CMQ, respectively, is energized so that when the distributer advances to position 1 the register concerned is complemented. If one of these registers is -ve but not both, then lead CSU is also energized via FF 127 when the distributer reaches position 12 to cause the sum register, which by then holds the product, to be complemented. At the same time, the multiplifer and/or addend register, if previously complemented, is arranged to resume its proper sign. The arithmetical process is as follows. In position 1 of the distributer, FF 130 combines with oscillator 109 to open AND gate 105. If then stage 2‹ of the multiplifer register is at 1 AND gate 136 is opened to energise ADD lead whereby the contents of the addend register are added to the accumulator. After a short delay leads SMR, SSR are energized to shift the multiplier and sum registers to the right. The distributer moves to position 2 and the process repeats. In position 12 the distributer switches FF 130 to O to stop addition and shift. In position 13 lead EMC is energized to empty the carry register and in position 14 the sign adjustments already described take place. In position 15 the circuits are restored to normal. Division, Fig. 14. Command DIV switches FF 152, FF 153 to 1. FF 152 connects the output of the 2<SP>10</SP> stage of the accumulator to the sign stage. FF 152 also starts the oscillator 109 to drive the distributer 110. In position O a test is made of the signs and if they differ FF 190 is set to 1 so storing a -ve sign for the quotient. If the divisor stored in the multiplier register is -ve, lead CMQ is energized to complement the divisor, while if the dividend in the accumulator is -ve, CSU is energized to complement the dividend. In position O a predetermined number is entered into counter 160a for subsequent determination of the binary point. Lead SML is then energized repeatedly to shift the multiplier register to the left until the most significant digit appears in stage 2<SP>10</SP>. At each shift the count in 160a is increased by 1. At each step the distributer is also advanced. If no divisor has been entered in the multiplier the distributer reaches position 10 without a significant digit being detected, and an alarm is given. Normally however a significant digit is detected,