Patent GB-762314-A (GB)
Title: Electrostatic memory system
IPC: G11C11/23
Filed: 1954-05-21
Abstract: 762,314. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 21, 1954 [May 26, 1953], No. 14984/54. Class 106 (1). In a method of or system for writing or storing information in a cathode-ray tube having a beam control grid, dielectric target and capacitatively. coupled backing-plate, the beam is turned on, a voltage pulse is applied to the backing-plate, and the beam is turned off before or after the backing-plate pulse is terminated to represent first and second information states respectively. In the storage tube shown in Fig. 2, binary digits are represented by charges on elemental areas of a dielectric target 3 capacitatively coupled to a backing-plate 6. The cathode beam, controlled by grid 4 and focused by electron gun 2, is caused to scan the areas by applying sawtooth or other voltages to deflection plates 5. As the beam bombards a target area, secondary electrons are emitted and attracted to a collector grid 7, such electrons being prevented from raining back on adjacent target areas by a barrier grid 8. The target assembly and associated grids may be constructed as described in Specification 762,294, [Group XL (a)]. The operations of the storage system shown, during writing, regeneration and reading, are described separately below. The operating cycle, Fig. 1, for each binary digit comprises 8 Ás. intervals of which the first three comprise a beam deflection period and the second three a period during which the beam may be disected on to the target. The electronic operation-control circuits, for which diagrams are given, include diode coincidence gates, pentode inverting gates, pentode and triode inverters and triode cathode followers. Writing.-During the 4th Ás. interval, a positive " beam on " pulse on lead 9, Figs. 1 and 2, applied through diode 10, charges condenser C12. The resultant positive potential on lead 11 is applied through cathode follower 13 to parallel diode coincidence gates A-D associated with different storage tubes. The tube shown is selected by applying a positive pulse over lead 17 to gate A which thus produces a positive output applied through inverters 19 and 21 and clipping circuit 23 to the control grid 4, thus switching on the beam. At the beginning of the 5th Ás. interval, a sharp positive pulse on lead 25 triggers a blocking oscillator 28 through circuit 26. The oscillator output pulse of just over 1 Ás. duration is applied through cathode followers 30, 32 and inverter 34 to bias negatively the backing-plate 6 (see bottom of Fig. 1). If a " 1 " is to be written a positive pulse is applied at 5 Ás. time from 42 to a gate and inverter 45 which is opened, through inverter 44, by a negative potential on line 43. The negative output from 45 passes through diode 46 and discharges condenser C12, thus switching off the beam while the backing-plate is negative and producing a positive charge on the target area being scanned. In the absence of the " one write " pulse on 42, the beam is switched off at 6 Ás. time, after the negative potential has been removed from the backing plate, by a " dash clamp " pulse on lead 40 which passes through diode 41, and no charge or " zero " is stored. Regeneration. The beam is switched on at the beginning of the 4th Ás. interval as for writing. A " 1 " or positive charge stored on the selected target area is neutralized, the number of primary electrons received being greater than the number of secondary electrons emitted, and a negative pulse is obtained from the backing-plate 6 and applied over lead 35 to amplifier 50 which produces an amplified and inverted pulse on lead 51. The amplifier (Fig. 5, not shown) comprises four cathode-coupled grounded-grid double triode stages followed by a pentode output stage and is designed to have a high recovery time from the backing plate pulse applied from inverter 34, the magnitude of pulses applied to the amplifier being limited by a bank of diodes 37 (only one shown); the amplifier also includes high-frequency filters to cut out spurious signals. The positive pulse on lead 51 allows a sharp " sample I " pulse to pass through gate and inverter 52 to inverter 55 and diode 57, thus charging condenser C58. The resultant positivepotential on lead 59 allows a " sample II " pulse, at the 5th Ás. time to pass through gate and inverter 60 and diode 62, thus discharging condenser C12 and switching off the beam at such a time as to re-write a "1." If, however, a " 0 " was stored on the target area, no signal is obtained from the backing plate and applied to the amplifier, lead 51 is at negative potential to close gate 52, and the beam is switched off at 6 Ás. time by the " dash clamp " pulse as in writing a " 0." Reading.-The output of cathode follower 13 is applied also through cathode follower 15 to output lead 16 so that a 2 or 3 Ás. pulse appears on the latter (see Fig. 1) according to whether a " 1 " or " 0 " is being written or regenerated. For a " 0," the 3 Ás. pulse opens gate and inverter 65 to allow a read clock pulse on lead 66, occurring during the 6th Ás. interval, to produce a negative output pulse on lead 67.