Patent GB-784989-A (GB)
Title: Electronic shifting register and storage circuit therefor
IPC: G11C19/18
Filed: 1954-03-02
Abstract: 784,989. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 2, 1954 [March 5, 1953], No. 6072/54. Class 106 (1). An electronic data storage circuit for a shifting register comprises a bi-stable vacuum tube or transistor trigger circuit, two series-connected diodes between an output of the trigger circuit and an output for the storage circuit, and a capacitor, connected to the diode junction, in series with a pulse source providing a bias which with the diodes controls the movement of date-representing energy to and from the capacitor. Fig. 1 shows a binary storage circuit in which a trigger circuit represented by switch 20 supplies one of two potentials (O and - V), representing " 1 " and " 0 " respectively; when switch 38 is in its lower position II, a 1-representing input potential will charge condenser 36 through diode 26, the charge not being affected by the subsequent movement of switch 20. When switch 38 is returned to the position I shown, the condenser discharges through diode 28 and resistor 32 and thus produces a positive pulse across output terminals 30, 34. The resistor 32 may be placed in series with a bias battery for charging the D.C. level of the output signal, or may be replaced by other load impedances connected between terminals 30 and 34. In the circuit shown in Fig. 3, the switch 38 is replaced by a pulse source 46 which produces the waveform shown in Fig. 4 B, and the diodes 26<SP>1</SP>, 281 are of the semi-conductor type. An additional pulse source 44 (synchronized with 46) produces rapid discharge of the condenser 36. In operation, with switch 20 in the " 1 " position, condenser 36 is charged in response to each negative pulse from 46, Fig. 4 A and B. When the output of 46 returns to the higher (zero potential) value, the condenser, if storing " 1," begins to discharge slowly, Fig. 4 A, but at time t after the negative pulse from 46, a negative-going pulse from 44, Fig. 4 C, causes the condenser to discharge rapidly through the low impedance path including a further diode 42. The output pulse is therefore as shown in Fig. 4 D. In a modification (Fig. 5, not shown), the pulses from 44 are timed and occur simultaneously with, though for shorter duration than, the pulses from 46. In the shifting register shown in Fig. 7, each stage comprises a bi-stable trigger circuit 50 and three storage circuits for left shaft, right shaft and read-out. Each trigger 50 may comprise a pair of cross-coupled triodes (Fig. 9, not shown) and is set into its " one " and " zero " conditions respectively by negative pulses applied to terminals S and R. Output terminal O 2  is at its lower potential in the " one condition and O 1  at its higher potential, Fig. 8 B and C. The left and right shift storage circuits comprise respectively diodes 62, 66, poled to respond to negative pulses, connected to each terminal O 2  (corresponding to the output of switch 20, Fig. 1), condensers CL, CR, output diodes 74, 76 and load resistors 60. The read-out storage circuits comprise diodes 64 and condensers C o  connected to output lines 78 which may be connected to the input lines 54 of another register which then provides the required output diodes (56) and load resistors. A read-out or shift operation is performed by applying a positive pulse to the appropriate bus 68, 70 or 72, and applying a short negative reset pulse on bus 52 connected to all the trigger terminals R. Suppose, e.g., that " 1 " has been entered on the appropriate line 54 into the stage " N " trigger (see Fig. 8 A to C), and is to be shifted right into stage " N + 1." A positive pulse, Fig. 8 I, is applied to bus 70, thus causing condenser C R  of stage " N " to be charged, Fig. 8 H, through diode 66. The triggers are reset by a clear pulse, Fig. 8 D, on bus 52, at time t after the commencement of the shift pulse. When the latter pulse terminates, the condenser C R  discharges and a negative output pulse, Fig. 8 J, is applied through diode 76 to 1 trigger terminal S of stage "N + 1." Fig. 8 E-G and Fig. 8 K-M show similar waveforms produced during left shift and read-out. Other shifting registers are described in which further sets of storage circuits are controlled by outputs 0, the clear bus 52 being then unnecessary, in which a single storage circuit for each stage controls a set of diode AND circuits and in which transistor trigger circuits are used. Fig. 12 shows a binary storage loop comprising a bi-stabled transistor trigger combined with storage circuit like that of Fig. 3, but including a limiting resistor 49 in series with diode 42. The pointcontact-type transistor 116 is triggered from a low condition or " 0 " state to a high condition or " 1 " state by a positive input pulse applied through switch 140 to the emitter electrode, and is reset by a positive pulse applied from terminal 112 to the base electrode. In the high conduction state, a relatively high potential is applied from the collector electrode to diode 26 of the storage circuit so as to charge condenser 36, after which the trigger circuit may be reset. When the condenser subsequently discharges under control of pulse generators 46, 44, the positive output at terminal 30 is fed back over line 142 so that, if switch 140 has been moved from input terminal 136 to the position shown, the transistor circuit is re-triggered to the " 1 " state. Reference is made to the feeding from a shift register into a logical adder circuit.