baber/WOPTO huggingface dataset:
Patent TW-508492-B (TW)
Title: Method and system for partitioning configured address space
Inventor: TSAI JAU-JIUE
IPC: G06F12/06
Filed: 2001-04-04
Granted: 2002-11-01
Abstract: The present invention provides a method for distributing and storing the configured address space, which can be applied in the current advanced computer system without modifying the BIOS or system software of the conventional computer system. To the microprocessor, all configuration data is existed in the north bridge control chip. However, some PCI bus related configuration data is actually stored in the south bridge control chip. Such a design can hide the influence caused by the advanced computer system introducing a high-speed private bus, and further satisfy the requirement of the advanced system having to partition the configured space distribution.
Patent TW-514700-B (TW)
Title: Stand alone plasma vacuum pump
Inventor: DANDL RAPHAEL A
IPC: H05H1/14
Filed: 2001-04-13
Granted: 2002-12-21
Abstract: A stand-alone plasma vacuum pump for pumping gas from a low-pressure inlet to a high-pressure outlet, composed of: a housing enclosing one or more pumping regions located between the inlet and the outlet; a plurality of permanent magnet assemblies providing magnetic fields that extend in the pumping region between the inlet and the outlet, the magnetic field forming magnetic flux channels for guiding and confining plasmas; elements disposed for coupling microwave power into the flux channels to heat electrons, ionize gas, and accelerate plasma ions in a direction from the inlet to the outlet; elements disposed for creating an electric in the magnetic flux channels to accelerate ions in the flux channels toward the outlet by momentum transfer; and a differential conductance baffle proximate to the outlet for promoting flow of plasma ions and neutral atoms to the outlet while impeding flow of neutral gas molecules in a direction from the outlet toward the inlet.
Patent TW-519798-B (TW)
Title: Communication test apparatus, communication test method, communication test program, and recording medium recording the program
Inventor: KURITA HIROYUKI
IPC: H04B17/00
Filed: 2001-04-24
Granted: 2003-02-01
Abstract: There is provided a communication test apparatus that can avoid a pause of a communication test for executing a signaling when executing the communication test, and reduce the time for the communication test. Because the communication test apparatus establishes the signaling on each EUT1, EUT2, and EUT3 in parallel, the time for the signaling is shortened to about 1/3. Also, since the communication test apparatus executes the communication test for EUT1, EUT2, and EUT3 of which the signaling is established, it is not necessary to make a pause of the communication test until EUT2 and the signaling are established after completing the test for EUT1. Also, because the communication test apparatus establishes EUT1, EUT2, EUT3 and the signaling while executing the communication test for EUT4, EUT5 and EUT6, there is no need to make a pause of the communication test until EUT1, EUT2, EUT3 and the signaling are established after completing the test for EUT4, EUT5 and EUT6.
Patent TW-490817-B (TW)
Title: A semiconductor device, an interposer for the semiconductor device, and a method of manufacturing the same
Inventor: SAITO TAKASHI
IPC: H01L23/498
Filed: 2001-05-09
Granted: 2002-06-11
Abstract: A semiconductor device, an interposer therefor and a method of fabricating the same are provided. The method comprises the steps of: forming an interposer having a lamination structure by sandwiching both surfaces of a wiring pattern thereof with polyimide layers; bending one end of a respective portion of this wiring pattern to project in one direction thereby forming an external terminal which has an exposed portion at one end thereof; connecting a semiconductor chip to the other surface of this interposer; then solder-bonding the exposed portion to an electrode of the mounting substrate. Thereby, allowing the external terminal having the exposed portion to intervene between the interposer and the mounting substrate, thereby allowing the same to absorb a thermal stress resulting from a differential thermal expansion coefficient between the semiconductor chip and the mounting substrate through deformation of the external terminal, thereby preventing breakage of interconnecting portions.
Patent TW-555860-B (TW)
Title: Vortex inhibitor and method for improving metal pouring process
Inventor: KOFFRON ROBERT J
IPC: F27D3/15
Filed: 2001-05-16
Granted: 2003-10-01
Abstract: A method and an apparatus for enhanced metallurgical processing of molten metal includes an enclosable ladle chamber (23) for reducing the escape of heat during transport of the ladle from a manufacturing vessel such as a furnace (13) to an intermediate processing (15) or refining station or during processing or transport to a receptacle vessel such as a tundish (17). The method comprises introducing a refractory body into the ladle chamber (23), the body having an adjusted specific gravity having a reduced steel ballast to refractory material ratio that is less than required for a specific gravity required to buoyantly support the body in the molten metal. Preferably, the ratio provides a specific gravity greater than the specific gravity required to buoyantly support the body entirely in the slag layer. The method includes enclosing the ladle (22) for example, with a lid (90) and maintaining said refractory body in said ladle until substantially termination of the discharge of the molten metal from the vessel. Preferably, the method also includes intermediate refining such as introducing a balancing composition to the ladle before enclosing. The ratio of steel ballast and refractory material used to achieve the preferred specific gravity may also be adjusted in conjunction with other temperature-resistant or corrosion-resistant changes to the refractory body. For example, high temperature alumina may be used as a refractory material in a higher degree than in previously known bodies, a high temperature cement may be used to join the refractory material and ballast components, and a non-wetting agent made of carbonaceous or siliceous material may reduce deterioration of the body during the extended period of steel and slag contact in the ladle.
Patent TW-I239096-B (TW)
Title: Method and apparatus for a direct strap for same level contact interconnections for semiconductor devices
Inventor: STETTER MICHAEL
IPC: H01L21/285
Filed: 2001-06-20
Granted: 2005-09-01
Abstract: A method and apparatus for forming a direct buried strap for a semiconductor device, in accordance with the present invention, includes forming a gate stack (106) on a semiconductor substrate (102), and forming a protective layer on sidewalls (108) of the gate stack. The protective layer extends horizontally (109) over a portion of the semiconductor substrate adjacent to the gate stack. A conductive layer (112) is formed over the protective layer and in contact with a gate conductor (107) of the gate stack and in contact with a diffusion region (104) formed in the semiconductor substrate adjacent to the gate conductor. A dielectric layer is formed over the conductive layer, and the dielectric layer is patterned to expose a portion of the conductive layer. The portion of the conductive layer which is exposed includes a portion of the conductive layer over the gate conductor and a portion of the substrate adjacent to the gate conductor. The exposed areas of the conductive layer are silicided to form a direct buried strap (120) and a silicided diffusion region (114) in the substrate. The direct buried strap electrically connects the gate conductor to the diffusion region in a same level of the semiconductor device.
Patent TW-577026-B (TW)
Title: Electronic device and method of manufacture the same
Inventor: USAMI MITSUO
IPC: H01L21/50
Filed: 2001-08-27
Granted: 2004-02-21
Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.
Patent TW-I254036-B (TW)
Title: Cleaning method for electronic component
Inventor: GOTO HIDETO
IPC: C11D11/00
Filed: 2001-10-09
Granted: 2006-05-01
Abstract: The cleaning method described above is characterized by allowing a cleaning agent comprising an oxidizing agent, a chelating agent and a fluorine compound to flow on a surface of a material to be treated at a high speed to thereby clean the above surface. according to the present invention, deposits adhering firmly to a surface of a material to be treated can readily be removed without damaging the material to be treated.
Patent TW-565798-B (TW)
Title: Pressing point coordinate detecting method for resistor type touch panel
Inventor: CHANG WEI-CHIH
IPC: G06F3/0354
Filed: 2001-10-12
Granted: 2003-12-11
Abstract: There is provided a touch point coordinate detecting method for resistor type touch panel. The pressing point coordinate has a plurality of switches. The pressing point coordinate detecting method is executed by selectively connecting and disconnecting the corresponding switches, which includes the following steps: a pressure sensing step for determining whether an external force is pressed on the touch panel; a pressure comparison step for determining whether the magnitude of the external force is in a predefined range; a X coordinate capturing step for detecting the X coordinate of the pressed point; and a Y coordinate capturing step for detecting the Y coordinate of the pressed point.
Patent TW-533414-B (TW)
Title: MRAM arrangement with select transistors of great channel width
Inventor: BOEHM THOMAS
IPC: G11C11/16
Filed: 2001-11-13
Granted: 2003-05-21
Abstract: The invention relates to an MRAM arrangement in which a select transistor (T) is assigned to a plurality of MTJ memory cells (1) and has an enlarged channel width. MRAM arrangement having a large number of MTJ memory cells (1) which are provided in the manner of a matrix in a memory cell array and are each located between bit lines (B1 to B4) and plate lines (PL) running in a first direction of the memory cell array, having digit lines (D1 to D4) which are arranged at a distance from the MTJ memory cells (1), are assigned to the latter in rows and extend in a second direction in the memory cell array, the second direction being substantially perpendicular to the first direction, and having select transistors (T) which are connected to the plate lines (PL), whose gate terminals are connected to word lines (W1 to W4) and which are located with their source-drain junctions between the plate lines (PL) and reference potential (ground), characterized in that in each case a select transistor (T) is assigned to a plurality of MTJ memory cells (1) in such a way that its channel width can be determined by the number of MTJ memory cells (1) allocated to it.
Patent TW-I234678-B (TW)
Title: Method for forming alignment layer
Inventor: CALLEGARI ALESSANDRO C
IPC: C23C14/48
Filed: 2001-11-27
Granted: 2005-06-21
Abstract: A method for preparing an alignment layer surface provides a surface on the alignment layer. The surface is bombarded with ions, and reactive gas is introduced to the ion beam to saturate dangling bonds on the surface. Another method for preparing an alignment layer surface provides a surface on the alignment layer. The surface is bombarded with ions and quenched with a reactive component to saturate dangling bonds on the surface.
Patent TW-533494-B (TW)
Title: Boron nitride/yttria composite components of semiconductor processing equipment and method of manufacturing thereof
Inventor: O'DONNELL ROBERT J
IPC: C23C16/44
Filed: 2001-12-04
Granted: 2003-05-21
Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a boron nitride/yttria composite containing surface and process for manufacture thereof. A process of coating a surface of a component of semiconductor processing equipment, the processing comprising: (a) optionally depositing a first intermediate coating on a surface of a component of semiconductor processing equipment; (b) optionally depositing a second intermediate coating on said first intermediate layer or on said surface; and (c) depositing a boron nitride/yttria composite containing coating on said component to form an outer erosion resistant surface.
Patent TW-I225942-B (TW)
Title: Optical device and liquid-crystal display apparatus
Inventor: YANO SHUUJI
IPC: G02F1/1347
Filed: 2001-12-11
Granted: 2005-01-01
Abstract: An optical device including a laminate of cholesteric liquid-crystal layers in which the wavelength ranges of selective reflection of circularly polarized light beams are out of visible light region and which are combined so that circularly polarized light beams transmitted through the cholesteric liquid-crystal layers to be left-handed and right-handed are inverted to each other. A liquid-crystal display apparatus including a vertically aligned liquid-crystal cell, polarizers disposed on opposite surfaces of the liquid-crystal cell, and one or two optical devices defined above and interposed between the liquid-crystal cell and either or each of the polarizers.
Patent TW-535168-B (TW)
Title: Selective polymer wrapping of radio active materials
Inventor: CHEN MUGUO
IPC: G21F9/30
Filed: 2002-01-14
Granted: 2003-06-01
Abstract: A selective polymer-wrapping process is disclosed which is capable of exclusively wrapping radioactive particles from solid waste streams at room temperature. Accordingly, separation of wrapped radioactive particles from unwrapped non-radioactive particles is facilitated. The method includes exposing radioactive particles or material, alone or in combination with other materials, to a precursor monomer solution that is capable of polymerizing due to the inherent radiation of the radioactive material, whereby the radioactive material is partially or totally encapsulated in the resultant polymer.
Patent TW-541630-B (TW)
Title: Manufacture of trench-gate semiconductor devices
Inventor: ZANDT IN T MICHAEL ANTOINE ARM
IPC: H01L21/331
Filed: 2002-01-23
Granted: 2003-07-11
Abstract: The manufacture of a vertical power transistor trench-gate semiconductor device in which the source regions (13) are self-aligned to the trench-gate structures (20, 17, 11) including the steps of forming a mask (61) on a surface (10a) of a semiconductor body (10), using the mask (61) to form the trench-gate structures (20, 17, 11), then using the mask (61) to form U-shaped section layers (62A, 62B) of insulating material whose base portion (62B) provides a gate insulating layer on the gate material (11), then removing the mask (61) and forming spacers (64) against well-defined steps provided by the upright portions (62A) of the U-shaped section layers, then using the spacers (64) to form the source regions (13).
Patent TW-568759-B (TW)
Title: Dispensable oil absorbing skin wipes
Inventor: SETH JAYSHREE
IPC: A45C11/00
Filed: 2002-01-30
Granted: 2004-01-01
Abstract: There is provided a package of multiple oil absorbing wipes suitable for wiping a users skin or hair. The wipes are arranged in an overlying arrangement and comprise an oil absorbing porous film-like substrate of a thermoplastic material having a transparency of less than 65 percent. The porous substrate changes transparency by at least 10 percentage points when loaded with oil. The porous substrate has an embossing pattern over from 1 to 50 percent of at least a portion of the of the wipe material surface area, which area is in contact with an adjacent wipe in the package.
Patent TW-550588-B (TW)
Title: Method and apparatus for biasing selected and unselected array lines when writing a memory array
Inventor: SCHEUERLEIN ROY E
IPC: G11C17/16
Filed: 2002-02-18
Granted: 2003-09-01
Abstract: A passive element memory array preferably biases selected X-lines to an externally received VPP voltage and selected Y-lines to ground. Unselected Y-lines are preferably biased to VPP minus a first offset voltage, and unselected X-lines biased to a second offset voltage (relative to ground). The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts. The area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, which further decreases power dissipation. When discharging the memory array, the capacitance between layers is preferably discharged first, then the layers are discharged to ground.
Patent TW-562934-B (TW)
Title: Method and apparatus for determining the instantaneous power of a sinusoidal signal
Inventor: VANREMMEN WILLIAM JOHN
IPC: G01R21/133
Filed: 2002-03-27
Granted: 2003-11-21
Abstract: A method and apparatus for determining the instantaneous power of a sinusoid signal is provided. Generally speaking, the apparatus of the present invention determines the instantaneous power of a sinusoid signal without the need for filtering. This is accomplished based on the trigonometric identity sin<2>x+cos<2>x=1. By first splitting the incoming signal into two signals so that the resultant signals are 90 degrees out of phase with each other, and subsequently squaring the split signals and adding the squared split signals, the AC component of the original signal is effectively removed, leaving a DC representation of the square of the amplitude of the original signal without any residual AC component. The square of the amplitude of the original signal is directly proportional to the instantaneous power of the original signal.
Patent TW-541737-B (TW)
Title: Cell frame for redox flow battery and redox flow battery
Inventor: NAKAISHI HIROYUKI
IPC: H01M2/08
Filed: 2002-04-10
Granted: 2003-07-11
Abstract: The present invention provides a cell frame for redox flow battery which can prevent electrolytic solution from leaking out of the cell frame and has excellent workability when assembling the redox flow battery. The cell frame 30 for redox flow battery consists of a dipole plate 21 and a frame rim disposing on the periphery of the dipole plate 21, and on both surfaces of said frame rim 31 are inner seal and outer seal which compress the diaphragm and seals the electrolytic solution. On both surfaces of the frame rim 31 are disposed inner seal slot 34 and outer seal slot 35 disposed with inner seal and outer seal for preventing the electrolytic solution from leaking outside, and in each slot 34, 35 is disposed an O-ring respectively.
Patent TW-I222583-B (TW)
Title: Contents recording/duplicating device and recording media storing program for recording/duplicating contents
Inventor: SATO MITSUHIRO
IPC: G06F21/62
Filed: 2002-04-11
Granted: 2004-10-21
Abstract: ontents file and package management file. Record th restricted information in terms of contents in any one or both of each file or the package so as to flexibly distinguish the endowing/referring unit using the restricted information in terms of the contents attribute or utilization condition.
Patent TW-538186-B (TW)
Title: Door hinge device
Inventor: KIM HEUNG-KEE
IPC: E05F5/10
Filed: 2002-04-12
Granted: 2003-06-21
Abstract: Disclosed is a door hinge device. The door hinge device comprises an oil accommodating body for accommodating viscous fluid, the oil accommodating body having a shape of a hollow sectorial cylinder which has a central angle of less than 180 DEG a hinge shaft disposed in the oil accommodating body and rotatably supported on a center portion of the oil accommodating body, the hinge shaft having integrally formed therewith a blade which is brought into sliding contact with an inner surface of the oil accommodating body and through which an oil passage is defined; and an oil flowing groove defined on the inner surface of the oil accommodating body, with which inner surface the blade of the hinge shaft is brought into sliding contact.
Patent TW-518286-B (TW)
Title: Method and related apparatus for addressing operations of a printer with single sensor
Inventor: LIN SHENG-CHIH
IPC: B41J23/02
Filed: 2002-04-25
Granted: 2003-01-21
Abstract: A method and related apparatus for addressing operations of a printer. The printer includes a sensor and a driving wheel for rotating to drive the printer into different states such as initial, paper-feed and printing states. The driving wheel has a rib with a first section and at least a second section corresponding to the different states of the printer. When the driving wheel rotates and the rib passes the sensor, the sensor is capable of sensing the rib to generate a rib sensing signal and sensing the first and the second sections to generate a section sensing signal. The method includes: determining the rotation position of the driving wheel only according to the sensing signal of the sensor.
Patent TW-I221593-B (TW)
Title: Instantaneous achievement learning system and method thereof
Inventor: YANG JR-JUNG
IPC: G09B7/02
Filed: 2002-06-19
Granted: 2004-10-01
Abstract: The invention discloses an instantaneous achievement learning system and method thereof, which learner can immediately understand the personal learning result by immediately displaying the learning result of learner on computer screen. Further treat the immediately displayed learning result as the next-stage learning objective in attempt to achieve the learning objective through training. Once learner reaches the learning objective, the new learning objective will be automatically shown and created and repeat such process continuously. New learning objective will continuously appear and the learner will also keep learning and training to achieve the new learning objective. By means of such processes and procedures over and over again, the learning effect can be easily demonstrated in short period of time and learner can attain the learning result with a certain degree in significantly short period of time.
Patent TW-580409-B (TW)
Title: Precise position controlled actuating method and system
Inventor: FARINA DINO J
IPC: A61M15/00
Filed: 2002-06-21
Granted: 2004-03-21
Abstract: A system for actuating a spray pump assembly comprises a reference platform, a motor, a drive transmission, a spray pump holder, a force coupler, a force transducer, and a system controller. The motor receives a power and control input, and produces a rotary drive output. The drive transmission receives the rotary drive output and produces a linear drive output. The spray pump holder secures the spray pump assembly. The force coupler couples the linear drive output to the spray pump, and applies a force to the spray pump. The force transducer produces a force signal proportional to the force applied to the spray pump. The system controller receives a set of test inputs and provides the control input to the motor as a function of the set of test inputs. The system actuates the spray pump mechanism according to an actuation profile defined by the set of test inputs.
Patent TW-570909-B (TW)
Title: Sputtering target for forming transparent conductive film of high electric resistance and method for producing transparent conductive film of high electric resistance
Inventor: TAKAHASHI SEIICHIRO
IPC: C23C14/34
Filed: 2002-06-26
Granted: 2004-01-11
Abstract: To provide a sputtering target for forming a transparent conductive film of high electric resistance which target is applicable to a DC magnetron sputtering apparatus and can form a transparent film of high electric resistance, and a method for producing a transparent conductive film of high electric resistance. The indium-oxide-based sputtering target for forming a high-electric-resistance, transparent conductive film having a resistivity of approximately (0.8-10)x10<-3> Omegacm contains indium oxide, an insulating oxide, and, in accordance with needs, an optional tin oxide.