Patent GB-983550-A (GB)
Title: Improvements in or relating to storage matrices
IPC: G11C8/02
Filed: 1961-03-07
Abstract: 983, 550. Electrical digital data storage apparatus. SIEMENS & HALSKE A.G. March 7, 1961 [March 7, 1960], No. 8373/61. Heading G4C. [Also in Division H3] Read and write functions of a saturable magnetic core matrix are effected with the use of single row and column wires half-write pulses being applied to one end of the wires and half-read pulses being applied to the other end of the wires, each wire when inactive being disconnected at both ends but being held at a potential equal to that of a half-write or read pulse. If the matrix wires are not driven directly but over a saturable cored transformer, the primaries of the driving transformers may be driven from one end or the other for reading or writing and both ends may be disconnected in the idle condition while the winding is held at the pulse potential. As shown in Fig. 1 a 4 x 4 matrix has four row and four column wires. By connecting one of the two transistors T1 and T2 and one of the two transistors T7 and T8 to conduct, a unique row wire is connected and is driven by a negative pulse from source XS. By connecting of two transistors T9 and T10 and one of two transistors T3 and T4 to conduct, a unique row wire is connected and is driven by a negative pulse from source XL. A half-write pulse from XS is always accompanied by a half-write pulse from a source YS similarly connected by transistor switches to the column wires. A half-read pulse from XL is always accompanied by a halfread pulse from a source YL similarly connected by transistor switches to the column wires. Choice of each pair of switches to select a row and column wire for coicindent current working of the matrix cores is effected by an address register AR. A clock pulse source T synchronises events. As shown for the top row wire alone, negative pulse potential is connected over a resistor to the wire to protect it from transients arising from the capacitance of the wire's diodes and transistor switches. As shown in Fig. 2 the driving circuitry may be applied to the primaries of saturable cored transformers U1 to U4 and U5 to U8, the secondaries being connected to drive the row and column windings. Each primary transformer winding is connected between two co-ordinate sets of driving wires one or other co-ordinate set being chosen to drive the windings depending on whether a positive read or a negative write pulse is required in the secondary. Thus if the transistors of a switch S are active one matrix is connected up by its terminal gating transistors for each co-ordinate of the matrix and, by command from an address register AR, one primary winding is pulsed in a sense to produce a half write pulse in its associated secondary winding and matrix wire. The write pulses are generated from source XS for one co-ordinate and YS for the other co-ordinate of the storage matrix. Similarly, if a read function is required the other primary winding drive matrices are connected up and pulse sources XL and YL pulse the selected primary windings in the opposite sense to produce the half-read pulses. In the arrangement shown in Fig. 3, instead of gating the transformer primary winding over rectifiers, two primary windings may be used of which one is connected as a cross point of one drive matrix and the other is connected as a cross-point of the second matrix. The drive matrix for half-write pulses (only one matrix co-ordinate drive arrangement being shown) is connected up by switch LS to pass a pulse from source IGS gate to the selected primary by address register sections TD. Similarly the read function is pursued by switch LS and pulse source IGL over the other drive matrix for the second primary windings.