Patent GB-955330-A (GB)
Title: Improvements relating to information handling apparatus
Inventor: FROGGATT ROBERT JUSTIN
IPC: G06F11/10
Filed: 1959-10-01
Abstract: 955,330. Digital electric calculating-apparatus. ELECTRIC & MUSICAL INDUSTRIES Ltd. Sept. 30, 1960 [Oct. 1, 1959], No. 33298/59. Heading G4A. An error correcting arrangement in data handling apparatus is based on the representation of numbers n in the "remainder code", in which a number is represented as an ordered set of residues to a plurality of relatively prime moduli. In the embodiment described, the means for providing residue-representing remainder signals in response to an input number is arranged to provide two remainder signals in excess of the number which is sufficient to determine uniquely any number in the number field and two combinations of the remainder signals, each sufficient to determine uniquely any number, are selected to determine the same number, thereby to indicate the correct output number. In the apparatus shown, the relatively prime moduli used are 55, 59, 61, 62 and 63, numbers from zero to 99, 999 being represented by their residues to these moduli, any three residues determining a number uniquely. Each decimal digit of an input number is coded in binary form and stored in one a set of buffer stores 5-9, the digits being read out sequentially to encoding devices 11-15 for the respective moduli. The outputs on channels 16-20 represent the various residues in binary coded form and are fed to elementary computers 26-30 each performing the same operations but to a different one of the five relatively prime moduli, the result of the operations being fed to buffer stores 31-35, outputs from which representing the same output answer as a residue with respect to the different moduli, lead to a decoding arrangement 36 which produces a correct output answer even if one of the inputs thereto is incorrect. Encoding devices, Fig. 2. The coding device 11, Fig. 1, for the modulus 55 is shown in detail in Fig. 2, the devices 12-15 being similar. The device shown is basically a binary multiplier comprising a multiplier store 41 containing the number ten in binary code, a multiplicand store 40 and a product store 42. A two-address store 81 stores fifty-five in binary form at 83 and the complement of fiftyfive with respect to sixty-four, called the "filler", at 82. The device is under the control of a timing unit 86, Fig. 1, adapted to count clock pulses and to produce four pulses on different output leads and then remain quiescent until a new initiating pulse is received. The various stores, gates and triggers are constructed of magnetic cores. To initiate a coding operation, a pulse is applied to a terminal 89, the first output pulse therefrom sensitising the first stage of a shift register 10 to transfer the 10<SP>4</SP> character of the input number to the multiplier store 40, Fig. 2. The second pulse from the timing unit 86 causes the contents of the store 40 to be transferred to the store 42, the third pulse from the unit 86 causing the contents of the store 42 to be transferred to the store 40 which thus now stores its original contents. The fourth timing pulse initiates a series of six sub-cycles, one for each stage of the store 41. In the first and second sub-cycles, corresponding to the 2<SP>5</SP> and 2<SP>4</SP> digits of the multiplier, which are zero, nothing of significance occurs. The third sub-cycle, corresponding to the 2<SP>3</SP> digit of the multiplier which is one, results in the contents of the store 40 being transferred to the store 42, to which is then added the "filler", no carry occurring, followed by the addition of the complement of the filler thereby producing a carry, which is suppressed at a gate 52. If the addition of the filler had produced a carry a gate 55 is inhibited to prevent the addition of the complement of the filler. The contents of the store 42 are now shifted one place to the left and the previous successive addition of the filler and filler complement are repeated. The net result of the third sub-cycle is that the 10' character of the input number has been multiplied by two, modulo fifty-five, and the product retained on the store 42. Sub-cycle four produces a further shift left so that the input 10<SP>4</SP> character is now multiplied by four. Sub-cycle five is controlled by the 2' stage of 41, which is one and results in the transfer of the contents of the store 40 to the store 42 followed by the addition of the filler, the conditional addition of the filler complement and a shift left, the net result of subcycles one to five being a multiplication by ten. The sixth sub-cycle produces an "end-of-cycle" pulse on a lead 96 which is fed to a counter 97, Fig. 1, which, when it has received pulses from all of the encoding devices 11-15, initiates the next cycle of the timing unit 86. This causes the counter 10 to transfer the 10<SP>3</SP> character from the buffer store 8 to all the encoding devices 11-15, in particular to the store 40 in the device 11. The pulses from the timing device 86 transfer the 10<SP>3</SP> character from the store 40 to the store 42, thus adding it to ten times the 10<SP>4</SP> character. When the counter 10 causes the transfer of the 10<SP>0</SP> character, a gate 98 is inhibited to stop the further operation of the coding units, the registers 40 of which then contain the residues of the input numbers with respect to the various moduli. These residues may then be read out to the buffer stores 21-25. Decoding device, Fig. 3. As shown, the buffer stores 31-35 for the various moduli are connected to groups of gates 100-104, six gates being provided for each channel. In a decoding operation, the contents of the stores 32-35 are transferred to multiplying circuits 110-113 and the contents of the store 31, which is the complement of the residue modulo 55, is then transferred to a complementer 105 and also to a store 107. The output from the complementer 105 is then added to the residues in the other channels in the circuits 110-113. The new remainders in the accumulators of the circuits 110-113.are then multiplied by 1/55. The remainder in the circuit 110 is now subtracted from all the channels, the result multiplied by 1/59, and the contents of the accumulator in the circuit 110 are transferred to the store 108. The next step is to subtract the quotient in the circuit 111 from the quotients in the circuits 111-113 to give remainders r d  and r. in the circuits 112 and 113. It is shown in the Specification, that if no error has occurred, these remainders should both be zero. The accumulators in the circuits 112, 113 are therefore tested, and if found to be zero, the correct output number can be derived from the three quantities contained in the stores 107, 108 and 109. If neither of the tests for zero is successful, this indicates that one of the first three channels (with moduli 55, 59 or 61) is functioning incorrectly and the decoder is caused to perform one or two further decode sequences omitting first one and then a second of these three channels.