Patent GB-1028642-A (GB)
Title: Coincident current memory
IPC: G11C11/06
Filed: 1963-06-26
Abstract: 1,028,642. Circuits employing bi-stable magnetic elements. SPERRY RAND CORPORATION. June 26, 1963 [June 27, 1962], No. 25385/63. Heading H3B. In a two-core-per-bit matrix the two bi-stable magnetic cores of each bit are set to different states and voltages are applied to a selected one of the Y column windings and a selected one of the X row windings, which two voltages are together sufficient to sense or read the selected cores by changing the stable state of one of the cores. A magnetic core matrix 100 comprises a plurality of horizontal selection windings X1 X2, X3 and a plurality of vertical selection windings 71, 72, 73 intersecting at 11, 12, 13; 21, 22, 23; 31, 32, 33, each intersection being provided with two cores 101, 102 wound so that at an intersection the respective horizontal and vertical winding each pass through both cores. The cores of each intersection, Fig. 2, are set so as to supply complementary information, i.e. if one core is set to have a positive remanence state the other core is set to have a negative remanence state, and so a voltage connected to any one of the X, Y selection windings sees a constant impedance since at each intersection one core is in a low impedance state and the other core is in a high impedance state. If the intersection 11 is storing a binary zero, the cores being in the states shown in Fig. 2, then to read out voltage sources are connected to selection windings X1, Y1 to supply half current pulses thereto. Thus only the cores at intersection 11 receive sufficient current to be switched and core 102 is switched to its positive remanence state. A positive pulse is induced in read out loop line 120 threading all the cores 102 and connected to input terminals 122, 126 of amplifier 124 across which is also connected a voltage detector (not shown). The input voltages to lines X1, Y1 are now reduced to a value such that quarter current pulses are supplied, at which time a half current writing pulse from the amplifier 124 delayed by network 129 is applied to line 128 which threads all the cores 102. The current at core 102 is now sufficient to return the core to its original state of negative remanence so that a zero is reregistered. In order to read out a binary one stored for example at intersection 12 voltages are applied to selection windings XI, Y2 so that core 101 switches to its positive state causing a voltage to be induced in winding 104 connected to input terminals of amplifier 108. As in the case of reading a zero the output from amplifier 108 to disc 112 is delayed until the voltages on the selection windings X1, Y2 have been reduced, so that the state of core 101 is returned to its original condition. The read-out information may be prevented from being written back and new information introduced into the cores by means of inhibiting gates 140, 170 and OR gates 150, 180. Thus to write new information into the storage cores 101 a write current is applied to terminal 138 during the write back period to close gate 140 preventing signals from amplifier 108 reaching line 112. At the same time the write current is applied to OR gate 150 and thence to line 112. The invention may be applied to three-dimensional matrices.