Patent GB-1495332-A (GB)
Title: Memory having non-fixed relationships between addresses and storage locations
IPC: G06F9/34
Filed: 1975-01-17
Abstract: 1495332 Memory systems PERIPHONICS CORP 17 Jan 1975 [26 Feb 1974] 2039/75 Heading G4A A memory system including a large computer store ACS (Fig. 1) and a smaller stack and map pointer memory SMPM which may be operated in any one of several modes, e.g. (1) direct-in which addresses from a central processing unit are translated by a predetermined amount to map into an equal number of memory locations, (2) mapping-in which an address from the central processing unit is used to access the smaller memory SMPN to derive the absolute address in the large store ACS, (3) SMPM mode when the small memory is itself accessed for reading/writing and (4) stacking-in which the same address from the central processing unit is successively translated into different addresses for the large store by the address location in the memory being incremented, includes circuitry for determining in which of a plurality of areas of address space an access address generated by the computer lies and circuitry for operating the system in the corresponding mode. Direct mode.-As described a part (up to 16 contiguous 4K blocks) in the computer address space is assigned to addresses in the "direct area", the first and last addresses being selected to lie on 4K boundaries so that by checking the four most significant bits of an address it may be determined whether or not the address is in the direct area. The address for the large store may be offset by some multiple of 4K with respect to the computer address in dependence on the address in the computer address space of the first valid block. Mapping mode.-The mapping area in the computer address space comprises a variable number of contiguous two page blocks, each page having 2,048 addresses, the boundaries of the area being multiples of 4K but in the store, the starting addresses of pages need not be on any boundary but can overlap each other. As in the direct mode a check is first made that the computer generated address is in the mapping area by comparing the four most significant bits with the start and end of the area. If a mapping mode operation is detected the complemented value of the four most significant bits of the address is added to the start address and the complement of the result is used together with the fifth most significant bit (indicating whether the required page 1 or page 2 in a block) to access the small memory (three '0' most significant bits being added in), which contains at this address the current starting address in the large store of the page containing the requested data. An 11 bit offset (the 11 least significant bits of the computer address) are added to derive the actual data. SMPM mode.-The SMPM area is a ¢K storage space which overlies one of four stacking areas (the SMPM mode having priority over the stacking mode) and comprises 512 addresses. It is defined by 6 bits representing its lower 1K boundary, a bit defining whether it is in the upper or lower half of a 1K address space defined by a hardware strap connection and an 8 bit address being used to access this area of the memory to read out or write in a byte. Consequently the memory, which may be high speed relative to the large store, may be used to hold a small frequently used program. Stacking mode.-The system may operate in one of three stacking modes, a fourth being disabled by being overlaid by the SMPM area, the mode determining whether a stack pointer accessed in the memory is incremented or decremented. Successive pairs of addresses from the computer access the same storage location in the memory since the low order bit serves, e.g. to identify an upper or lower byte in a write operation so that 8 different addresses (two in each stacking area) address the same memory location. Addresses in areas SI, SD, SAC result in "automatic increment", "automatic decrement" and "ascending stack check" modes respectively for the address stored in the memory, the disabled mode (in this embodiment the area SDC) corresponding to a "descending stack check" mode. The five most significant bits in the generated address represent a 2K block and a test is first made to see if the system is operating in the stacking/SMPM mode. Bits 9, 10 define the stack area in which the address lies and bits 1-8 are the word address for the memory, the lowest bit 0 being used to define whether a word or byte operation is to take place. Consequently bits 0, 9, 10 are fed to logic circuitry to determine the mode and whether incrementing/decrementing is to be by 1 (byte) or 2 (word), When an address in area SI is used to address the memory, a stack pointer at the location is read out and used to access the store ACS, the pointer then being incremented in a summer and restored in the memory. If an address in SAC is used, the stack pointer is first decremented and the decremented value is used to access the store, the original value of the pointer being re-stored in the memory, If the area SDC is not overlaid, addresses in its area result in the stack pointer without modification being used to access the store (since for a descending stack the pointer always points to the last location accessed). Control mode.-The system responds to a single address in the upper 512 addresses of the computer address space to operate in the control mode. The seven most significant bits are assumed to be "1", the least significant bits a "0" and 8 switches are set to define the values of the other 8 bits representing the control word address. The control word has 16 bits, the most significant bit, bit 15, when 0, indicating the system may only operate in the direct and control modes. Bit 14, when 0, disables the stacking modes. Bits 8-13 define the SMPM and stacking area. Bits 0-3 and bits 4-7 define respectively the first and last valid blocks in the mapping area. When the system is first turned on it can operate only in the control and direct modes so that an initialization program is operated to allocate the address space to the mapping and/or stacking function. An order of priority is established for the modes viz (1) SMPM mode, (2) stacking mode, (3) mapping mode and (4) direct mode. A block diagram of the memory system is given in Figs. 7-13 (not shown). It may be operated with more than one processor.