Patent GB-1289371-A (GB)
IPC: H04L25/49
Filed: 1970-04-15
Abstract: 1289371 Transistor pulse circuits INTERNATIONAL BUSINESS MACHINES CORP 15 April 1970 21 April 1969] 17935/70 Heading H3T [Also in Division G4] Signal recovery apparatus for reading bit signals recorded in a magnetic medium, comprises a transducer for producing readback signals from the magnetic medium, and means to feed the readback signals to a one-bit delay device and, with signals from the delay device, to a differencing circuit which feeds an amplitude detector circuit conditioned by a threshold voltage. In Fig. 1, binary data recorded in frequency modulated form as a transition at each bit cell boundary, and a mid-cell transition for each " 1 " bit, is read 12 from magnetic tape 10, linearly amplified 22, delayed by one bit period at 33 and subtracted from itself undelayed in a differential amplifier 37, the difference signal being band-pass filtered 42, full-wave rectified 44 and then thresholded at 43 when strobed by a clock pulse at 17 to produce a pulse for each " 0 " bit and no pulse for " 1 ", at 13. The threshold is obtained at 50 by averaging (using an integrator) the output of amplifier 22, and optionally similar outputs from other tape channels, and adding a low fixed value, or a fixed threshold may be used. A clock pulse is produced at 17 at each bit cell boundary in response to the output of the one bit delay 33, or its inverse, selected at reversing switch 53, the selected signal being supplied via a filter (or phase-lock loop) 67 to the gate pulse generator 68 which produces the clock pulses. Filter 67 passes the frequency corresponding to " 1 " bits. Each " 0 " bit pulse from output 13 reverses the reversing switch 53 via a toggle 70. The clock pulses (or the filter 67 output) are phase-compared at 64 with the filter 67 input, and a 180-degree phase error will reverse the reversing switch 53 again. Fig. 3 shows a modified version of the signal processing channel 14 of Fig. 1, in which the tape read head 12 and a differential amplifier 22a provide readback and phase-inverted readback signals 38a, 32a. The latter is one bit period delayed at 33, the readback signal and the phase-inverted delayed readback signal each being A.C. -coupled 95, 94 to a respective differential amplifier 97, 96 to supply each in the same and phase-inverted form via emitter-follower transistors 120-123 (for impedance reduction) to linear summers 124, 125. The filters 42a, 42b shown are tuned to the frequency corresponding to " 1 " bits. The summer outputs, which represent readback plus phase-inverted delayed readback, and phaseinverted readback plus delayed readback, respectively, are combined in a positive OR circuit 140 which passes the positive portions of each to line 91 for comparison (in a saturating differential amplifier 150) with the threshold from threshold generator 50, a pulse being produced at 13 for each " 0 " bit when strobed by a gate (clock) pulse at 17. As a modification, the threshold may be manually set. Fig. 5 (not shown) shows a more-detailed modified version of the clock channel 15 of Fig. 1 for use with the Fig. 3 circuit, the phase comparison being by ANDing the gate (clock) pulses with the inverted output of the reversing switch, and the reversing of reversing switch 53 being done by reversing a flip-flop in the " comparator " 64 block in response to each " 0 " pulse (via the toggle) and each pulse from the phase-comparison AND gate. Fig. 6 (not shown) shows a modification using two sample-and-hold circuits in place of the one bit period delay 33 of Fig. 1. In a given bit period, one of these circuits follows the output of the amplifier 22 of Fig. 1, and the other holds the value it had at the end of the previous bit period, the two circuits interchanging roles at the end of each bit period since a flip-flop controlling them is reversed by each clock pulse. A differential amplifier compares the outputs of the two circuits, the difference signal being thresholded to produce a pulse for each " 0 " bit when strobed by each clock pulse at the end of each bit period. The clock channel may be synchronized using the ORed-together outputs of the sample-and-hold circuits. Bits can be recorded using higher numbers of cycles per bit period. A preamble of all " 0 "s is recorded on the tape. Sync. signals may be recorded.