baber/WOPTO huggingface dataset:
Patent TW-346647-B (TW)
Title: MOSFET with self-aligned silicide and gate-side air-gap structure
Inventor: WU SHYE-LIN
IPC: H01L21/28
Filed: 1997-11-19
Granted: 1998-12-01
Abstract: A method for producing an MOSFET with a self-aligned silicide and gate-side air-gap structure, which at least comprises: forming a gate oxide layer on a semiconductor substrate; forming a polysilicon layer on the gate oxide layer; etching the gate oxide layer and the polysilicon layer thereby forming a gate structure on the semiconductor substrate; forming a first dielectric layer on the semiconductor substrate and the gate structure; forming a second dielectric layer on the first dielectric layer; etching the second dielectric layer thereby forming a first side wall gap on the side wall of the gate structure, a first portion of the first dielectric layer being existed between the gate structure and the first side wall gap, a second portion of the first dielectric layer being existed below the first side wall gap; forming a buffer layer on the semiconductor substrate, the gate structure and the first side wall gap; applying a first ion implantation penetrating the buffer layer and entering the semiconductor substrate thereby forming a first ion doping region as the drain and source; applying an oxidization process for converting the buffer layer into an oxidized layer, and driving ions into the semiconductor substrate, a second ion doping region being formed on a side of the first ion doping region due to ion diffusion; etching the oxidized layer thereby forming a second side wall gap on the first side wall gap; removing the first side wall gap thereby forming a gate-side air-gap between the gate structure and the second side wall gap; applying a second ion implantation thereby penetrating ions through the gate-side air-gap to form a third ion doping region on a side of the second ion doping region; and forming a third dielectric layer on the semiconductor substrate, the second side wall gap and the gate structure.
Patent TW-402694-B (TW)
Title: Color filter black matrix and method for producing the same
Inventor: JENG HUA-CHI
IPC: G02F1/1333
Filed: 1997-12-02
Granted: 2000-08-21
Abstract: The present invention relates to a mosaic black matrix, suitable for a color filter made by the method of electrodeposition. The black matrix has a light blocking film and a insulating film. The light blocking film can be made by metal thin film, metal/metal oxide thin film or photo sensitive black resin composition through photo-lithography process. The insulating film can be made by photo sensitive resin composition through photo-lithography process. The color filter employing present invention has the advantages such as that the color mixing between pixels can be avoided and the planarity of the color filter can be improved.
Patent TW-448152-B (TW)
Title: Iridium-catalysed carbonylation process for the production of acetic acid
Inventor: WILLIAMS BRUCE LEO
IPC: C07C51/12
Filed: 1997-12-27
Granted: 2001-08-01
Abstract: A process for the production of an acetic acid process stream comprising less than 400 ppm propionic acid and less than 1500 ppm water comprises the steps:- (a) feeding methanol and/or a reactive derivative thereof and carbon monoxide to a carbonylation reactor in which there is maintained during the course of the process a liquid reaction composition comprising: (i) an iridium carbonylation catalyst: (ii) methyl iodide co-catalyst: (iii) optionally one or more promoters selected from the group consisting of ruthenium, osmium, rhenium, cadmium, mercury, zinc, gallium, indium and tungsten; (iv) a finite amount of water at a concentration of less than about 8% by weight; (v) methyl acetate; (vi) acetic acid; and (vii) propionic acid by-product and its precursors; (b) withdrawing liquid reaction composition from the carbonylation reactor and introducing at least part of the withdrawn liquid reaction composition, with or without the addition of heat, to a flash zone to form a vapour fraction comprising water, acetic acid product, propionic acid by-product, methyl acetate, methyl iodide and propionic acid precursors, and a liquid fraction comprising involatile iridium catalyst, involatile optional promoter or promoters, acetic acid and water; (c) recycling the liquid fraction from the flash zone to the carbonylation reactor; (d) introducing the vapour fraction from the flash zone into a first distillation zone; (e) removing from the first distillation zone at a point above the introduction point of the flash zone vapour fraction a light ends recycle stream comprising water, methyl acetate, methyl iodide, acetic acid and propionic acid precursors which stream is recycled in whole or in part to the carbonylation reactor, and (f) removing from the first distillation zone at a point below the introduction point of the flash zone vapour fraction, a process stream comprising acetic acid product, propionic acid by-product, and less than 1500 ppm water and, (g) if the process stream removed in step (f) comprises greater than 400 ppm propionic acid introducing said stream into a second distillation column, removing from a point below the introduction point of the stream from (f) propionic acid by-product and from a point above the introduction point of the stream from (f) an acetic acid process stream containing less than 400 ppm propionic acid and less than 1500 ppm water.
Patent TW-379450-B (TW)
Title: Memory having plurality of threshold level in the memory cell
Inventor: TANAKA TOMOHARU
IPC: G11C11/56
Filed: 1998-01-26
Granted: 2000-01-11
Abstract: A multi-level memory characterized by comprising an electrically programmable memory cell (1) having at least an erased state, a first programming state and a second programming state, and a programming circuit (2, 3, 6, 7, 9) for programming data by repeating a programming operation by applying a programming voltage to the memory cell, a first programming verification operation for confirming whether or not the memory cell reached the first programming state after the programming operation, or a second programming verification operation for confirming whether or not the memory cell reached the second programming state after the programming operation, wherein the programming circuit repeats the programming operation and the first programming verification operation except for the second programming operation in a first period of the data programming, and repeats the programming operation, the first programming verification operation and the second programming verification operation in a second period after the first period of the data programming.
Patent TW-505563-B (TW)
Title: Metal sheet coated with polyester resin
Inventor: HAYASHI YOSHIO
IPC: B32B27/36
Filed: 1998-02-04
Granted: 2002-10-11
Abstract: To provide a metal sheet covered with polyester resin in which decorative design is given to polyester resin film with high strength and excellent formability by embossing the polyester film. A metal sheet is covered with nonoriented polyester resin layer or polyester resin layer comprised of resin with low crystallinity and crystalline polyester resin, in which uneven touch is given to the surface of the above-mentioned resin layer by embossing the surface thereof.
Patent TW-374205-B (TW)
Title: Ionized physical vapor deposition
Inventor: Sui xiao-lin
IPC: H01L21/205
Filed: 1998-04-22
Granted: 1999-11-11
Abstract: The present invention provides an ionized physical vapor deposition (ionized PVD) which is characterized in using a two-stage sputtering deposition to simultaneously obtain a good bottom coverage and a good sidewall coverage, and to produce a metal layer of better uniformity. While applied in manufacturing multiple interconnects, this method can provide a barrier layer of better step covering effect to fit into a copper-based metallization process in the future.
Patent TW-513622-B (TW)
Title: Photo-absorbing polymer composition capable of forming photo-absorbing film and photo-absorbing film together with its use as antireflection film
Inventor: KANG WEN-BING
IPC: G03F7/09
Filed: 1998-05-25
Granted: 2002-12-11
Abstract: Provided are a photo-absorbing polymer chemically combined with photo-absorbing pigment, which polymer has a high absorb-ability to the light having a specific range of wave length and is excellent in the adherence to substrates and in film formability, independent from resist, soluble of solvent for photoresist and non-fusing after baking; a composition containing the said polymer and capable of forming photo-absorbing films; and a photo-absorbing film as antireflection film etc, which is formed from the said composition. Photo-absorbing polymer is formed from copolymer comprising at least a repeating unit formed from monomer having keto group, preferably methylene on the side chain, and a repeating unit formed from monomer capable of absorbing the light having a specific range of wave length by combining, directly or through a linking group, organic chromophore groups on the main chain thereof. Said photo-absorbing polymer is dissolved in solvents such as alcohol, aromatic hydrocarbon, ketone or ester etc, coated upon the wafer, and then baked to form photo-absorbing film as antireflection film etc. A resist, for example in chemically amplified type is coated upon said film, exposed under far ultraviolet rays and then developed to form fine resist pattern which will not be influenced by standing wave.
Patent TW-385454-B (TW)
Title: A transformer
Inventor: SATORU ITO
IPC: H01F30/00
Filed: 1998-06-23
Granted: 2000-03-21
Abstract: This invention provides a transformer which whole volume can be used effectively and which does not deteriorate in power transmission efficiency even when the thickness of the transformer is reduced, has a superior heat radiating property, and can be manufactured at a low cost. A transformer is provided with a main core 32 made of a magnetic material, side cores 33 which are jointed with both end sections of the main core 32 and made of a magnetic material, and primary and secondary windings 34 and 33 which are wound around the main core 32. The main core 32 is composed of a center magnetic leg 36 and a pair of outer magnetic legs 37 which are respectively united with both sides of the center magnetic leg 36 and extended in the direction perpendicular to the leg 36. Winding grooves 38 are formed between the outer legs 37 on both sides of the center leg 36 and the primary and secondary windings 34 and 25 are wound around the center leg 36 through the grooves 38. A transformer is provided with a main core 32 made of a magnetic material, side cores 33 which are jointed with both end sections of the main core 32 and made of a magnetic material, and primary and secondary windings 34 and 33 which are wound around the main core 32. The main core 32 is composed of a center magnetic leg 36 and a pair of outer magnetic legs 37 which are respectively united with both sides of the center magnetic leg 36 and extended in the direction perpendicular to the leg 36. Winding grooves 38 are formed between the outer legs 37 on both sides of the center leg 36 and the primary and secondary windings 34 and 25 are wound around the center leg 36 through the grooves 38.
Patent TW-386313-B (TW)
Title: Solid-state relay
Inventor: MIYAMOTA YASUNORI
IPC: H01L27/088
Filed: 1998-06-29
Granted: 2000-04-01
Abstract: A solid state relay is composed a pair of a series connected LDMOSFETs and has a minimized output capacitance. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a lateral direction relative to the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. Each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on a supporting metal plate, a buried oxide layer on the silicon substrate, and a silicon layer on the buried oxide layer. The well region is diffused over the full depth of the silicon layer to have its bottom in contact with the buried oxide layer, so that the well region forms with the silicon layer a P-N interface only at a small area adjacent the channel. Because of this reduced P-N interface and the buried oxide layer exhibiting a much lower capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition.
Patent TW-388172-B (TW)
Title: Calibration pattern display system and system for calibrating display characteristics measuring device and method therefor
Inventor: HAMAGURI KENJI
IPC: H04N17/04
Filed: 1998-07-14
Granted: 2000-04-21
Abstract: A calibration system for a display characteristics measuring device comprises a calibration pattern display unit for displaying a calibration pattern having illumination characteristics essentially identical to the display device under measurement; an image reading unit provided in the display characteristics measuring device for reading the calibration pattern displayed on the display device for generating image data; and a calculation device for calculating the calibration data of the display characteristics measuring device based on the image data generated by the image reading unit.
Patent TW-373024-B (TW)
Title: Denitrification techniques employed on sinter production line
Inventor: MOU JIN-LU
IPC: C21C1/04
Filed: 1998-09-10
Granted: 1999-11-01
Abstract: This invention describes a novel denitrification technique employed on the sinter production line, characterized in that during the sinter process, a gluing assistant such as sugar will be added to enhance the granulation and agglomeration, to improve the ventilation, shorten the sinter time, to decrease chance of the nitrogen contained in the raw material converted into nitrogen oxide and finally to inhibit the discharge of nitrogen oxide out of the exhaust gas.
Patent TW-378272-B (TW)
Title: Detecting the open/grounded /shorted  state of each pin on a computer parallel port
Inventor: JANG YEOU-CHYUAN
IPC: G06F9/06
Filed: 1998-10-26
Granted: 2000-01-01
Abstract: The invention  concerns the detection of the open, grounded or shorted circuit status for each pin on a computer parallel port. A storage unit is built in the mainframe of the computer to store a test software, which can detect the transmission of the bi-directional signal on each pin of the parallel port (LPT)  through a module externally connected to the mainframe of the computer.
Patent TW-363885-B (TW)
Title: Grain milling machine
Inventor: MIYATAKE YOSHIKUNI
IPC: B02B3/06
Filed: 1998-11-11
Granted: 1999-07-11
Abstract: A kind of grain milling machine having a cylindrical body 24, a milling chamber surrounded by the rotating body 23, milling plates 27, 28 on the surface opposite to the milling chamber where hard diamond abrasive grains in polyhedral shape are distributed on the surface of at least one milling plate. Milling plate 17 is secured to one side of the cylindrical body 24, while milling plate 28 is secured to one side of the rotating body 23 and moves opposite to milling plate 27 so the skin of grains forcibly fed into the milling room 25 is crushed by the milling force between milling plates 27, 28. As such, the grain milling machine is able to maintain sufficient milling force and gives high quality performance without the need for complicated maintenance.
Patent TW-419399-B (TW)
Title: Post-lapping cleaning process for silicon wafers
Inventor: CHAI JING
IPC: B08B3/08
Filed: 1998-12-10
Granted: 2001-01-21
Abstract: A process for cleaning contaminants from the surface of a semiconductor wafer after the wafer has been lapped. The process comprises contacting the wafer with an oxidizing agent to oxidize organic contaminants which may be present on the surface of the wafer. The wafer is then immersed in an aqueous bath comprising citric acid into which sonic energy is being directed to remove metallic contaminants which may be present on the surface of the wafer. After being immersed in the citric acid bath, the wafer is contacted with hydrofluoric acid to remove a layer of silicon dioxide which may be present on the surface of the wafer. The wafer is then immersed in an aqueous bath comprising an alkaline component and a surfactant, and into which sonic energy is being directed.
Patent TW-374700-B (TW)
Title: Manufacturing method of a travel suitcase and the finished product
Inventor: HOU YI-SHUN
IPC: A45C5/04
Filed: 1999-02-09
Granted: 1999-11-21
Abstract: This invention deals with a sort of manufacturing method of travel suitcase and its finished product, consisting of a framework, a cover, a lower cover, an upper cover and a plurality of connection elements being the manufacturing method taking first a framework of proper length from a frame strip giving the framework a cover before disposing the upper and the lower cover on both ends of the framework and eventually loading the framework at a proper position by means of a plurality of connection elements for securing said upper and lower cover onto the framework and at the same time, making the cover against the outer wall of the framework, for forming the finished product of the travel suitcase of easy assembly, simplified production flow process, lowered cost and easy transfer.
Patent TW-510157-B (TW)
Title: Electronic apparatus structure
Inventor: WEINMEIER HARALD
IPC: H05K7/20
Filed: 1999-02-26
Granted: 2002-11-11
Abstract: An electronic apparatus comprises a housing (1), a backwall (7) and at least one printed circuit board (10) mounted in the housing and located in a substantially vertical position on the backwall (7), which is characterized in that: the backwall (7) is an independent part of the housing (1), enclosing the interior of the housing towards the back, and the printed circuit board (10) is connected to the backwall by fixing elements (13, 15) protruding from said wall (7) and engaging the printed circuit board (10).
Patent TW-514991-B (TW)
Title: Method of forming polysilicon gate and polycide gate with same height
Inventor: TZENG HUNG-HUEI
IPC: H01L21/28
Filed: 1999-03-19
Granted: 2002-12-21
Abstract: This invention discloses a method of forming polysilicon gate and polycide gate with the same height on the same wafer so that sheet resistance of the polysilicon gate can be reduced. Firstly, a gate oxide layer is formed on a semiconductor substrate, and a first polysilicon layer, a metal silicide layer and a dielectric layer are sequentially deposited. Subsequently, a first photoresist layer is employed to define a pattern for the polycide gate and the dielectric layer and the polysilicide layer are etched. After the first photoresist layer is then removed, a spacer is formed on the sidewall of the polycide layer and a second polysilicon layer is deposited. A second photoresist layer is employed to define a pattern for the polysilicon gate, and the first polysilicon layer and the second polysilicon layer are etched. Finally, the second photoresist layer is removed to complete forming polysilicon gate and polycide gate with the same height.
Patent TW-I221853-B (TW)
Title: A hardener for use in urea-formaldehyde and urea-melamine-formaldehyde based adhesives, an adhesive composition comprising said hardener
Inventor: ANDERSEN BJOERN
IPC: C09J161/28
Filed: 1999-03-25
Granted: 2004-10-11
Abstract: A hardener for use in urea-formaldehyde and urea-melamine-formaldehyde based adhesives comprises a polyvinyl acetate emulsion together with a metal chloride and an ammonium salt. The adhesive composition comprising a urea-formaldehyde or urea-melamine-formaldehyde resin, and the above hardener provides an increased curing rate, an acceptable viscosity, better adhesion and greater tolerance towards substrate type.
Patent TW-455767-B (TW)
Title: High speed synchronous memory device having dual port capable of improving graphic processing speed
Inventor: LEE HO-CHEOL
IPC: G11C7/10
Filed: 1999-04-01
Granted: 2001-09-21
Abstract: A high-speed synchronous memory device having a dual port which can improve a graphic processing speed is provided. In the synchronous memory device, a data input buffer buffers the data received through the first port and transmitting the buffered data to the memory cell array synchronously with a first clock signal. A first data output buffer buffers the data output from memory cell array and outputting the buffered data to the outside through the first port synchronously with the first clock signal. A register temporarily stores the data output from the memory cell array. A second data output buffer buffers the data output from the register and outputting the buffered data to the outside through the second port synchronously with a second clock signal. The second clock is different from the first clock and is not synchronized with the first clock. If need be, the same clock as the first clock can be used as the second clock.
Patent TW-417137-B (TW)
Title: Fluorescent display device
Inventor: TATEYOSHI SADAO
IPC: H01J31/15
Filed: 1999-04-17
Granted: 2001-01-01
Abstract: In the fluorescent display device connecting external wire and layout conductor near the sealing portion of exterior container, making the connection as stable and accurate. The exterior container is composed of substrate 2 sealed by sealing material 3 and the container 4. The substrate 2 is configured with wiring connector 11 and the insulating layer 10 thereon. The wiring connector 11 is connected with the anode 7. The insulating layer 10 is formed with an opening 14 near the sealing portion. There is Ag glue 15 on the wiring connector 11 in the opening 14 and having conductive particles 20 thereon. The inner terminal 16a penetrating the external wire 16 of sealing material 3 is contacted with particles 20 in the sealing material 3. The connection portion between wiring connector 11 and external wire 16 is in the sealing material 3 but the sealing material 3 entering between the wiring connector 11 and external wire is punctured by particles 20. The electric contact between the wiring connector 11 and external wire 16 can be stabilized.
Patent TW-442403-B (TW)
Title: Multi-chamber fluid supply
Inventor: HICKMAN MARK S
IPC: B41J2/01
Filed: 1999-04-28
Granted: 2001-06-23
Abstract: In accordance with the invention, an ink-jet printing system and fluid supply configuration are disclosed that utilize the advantages of reactive fluids while allowing for maximum flexibility in the design and architecture of the ink-jet printing system. The ink-jet printing apparatus comprises a printhead portion having at least one integral printhead portion, the printhead portion having at least two ejector portions; and at least one reservoir portion associated with the printhead portion, the reservoir portion having at least two reservoir chambers, each reservoir chamber for providing fluid to one of the at least two ejector portions, one of the chambers including a reactant fluid and the other chamber including at least one ink non-reactive with the reactant fluid.