baber/WOPTO huggingface dataset:
Patent TW-200626651-A (TW)
Title: Rubber composition and sealing material for plasma treating apparatus
Inventor: MAEDA ICHINOSUKE
Filed: 2005-12-20
Abstract: This invention proposes a sealing material for plasma treating apparatus. The sealing material contains a rubber composition of: (a) a crosslinking fluororubber: (b) a reactive fluorine-based compound, excluding the rubber (a), having a structure of divalent perfluoropolyether or a structure of divalent perfluoroalkylene, and at terminals or side chains, having at least two or more alkenyl groups that is capable of performing an addition reaction with a hydrosilyl group of an organic silicon compound (c); (c) a reactive organic silicon compound having two or more hydrosilyl groups in a molecule and being capable of performing an addition reaction with the alkenyl groups of the above compound (b); (d) a vulcanizing agent and an optional co-crosslinking agent; wherein relative to 100 weight by parts of the rubber (a), the total amount of the above compound (b) and the above reactive organic silicon compound (c) is 1 to 10 weight by parts. A sealing material for plasma treating apparatus can be formed by subjecting the composition to primary vulcanizing molding, followed by second vulcanizing molding in a vacuum oven to vulcanize the unreacted components in the molded articles obtained from the previous step such that the amount of unreacted components, accordingly the released gas, can be reduced. The sealing material thus produced will not easily become sticky to the associated parts even after prolonged use under high temperature condition, especially in the process of manufacturing semiconductor. As a result, the sealing material can be obtained at low cost without producing the problems such as formation of particles and pollution caused by the released gas.
Patent TW-200726313-A (TW)
Title: Display device and method for fabricating display device
Inventor: HSIEH CHENG-HSI
IPC: G02F1/167
Filed: 2005-12-29
Abstract: A display device includes a first structural substrate, having several pixel regions. At least one of the pixel regions has an emissive region and a reflective region. A wall structure is disposed on the first structural substrate and surrounding a periphery of the emissive region and the reflective region for separation the emissive region and the reflective region. A emissive structure is disposed on the first structural substrate at the emissive. A reflective displaying structure is disposed on the first structural substrate at the reflective region. A second structural substrate covers on the wall structure.
Patent TW-200725407-A (TW)
Title: Operating environment system and method for an improved efficiency of a workflow executed on a computer by a user
Inventor: YU CHIA-WEI
IPC: G06F9/445
Filed: 2005-12-29
Abstract: Disclosed is an operating environment system and method for an improved efficiency of a workflow executed on a computer by a user, the method being allowed to be executed on the operating environment system, comprising a plurality of soft applications and an integrated operating environment, comprising an action model module described in a data structure form, a plug-in component module monitoring the user's operating status and intercepting and transmitting an issued instruction, a command center module interpreting the possible action in response to the instruction based on the data structure and a service module directed by the command center module to execute the possible action.
Patent TW-200725744-A (TW)
Title: Method to define a transistor gate of a DRAM and the transistor gate using same
Inventor: LEE YU-PI
IPC: H01L21/336
Filed: 2005-12-30
Abstract: A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned layer of silicon nitride over the substrate so that at the location where the two trench capacitors are desired to be built, the substrate is exposed; then to build the two trench capacitors at the location of the exposed substrate. Form a layer of silicon oxide to cover the capacitors and make the layer of silicon oxide and the layer of silicon nitride at the same level. Layer of silicon nitride is removed afterwards, and a polysilicon layer is conformally formed on the substrate. A BF2 ion implantation is performed twice at different tilt angles on the polysilicon layer in order to define an undoped area between the two trench capacitors. Then remove the undoped area of the polysilicon layer so that part of the silicon substrate is exposed to serve as the predetermined location of transistor gate.
Patent TW-200632240-A (TW)
Title: Apparatus including 4-way valve for fabricating semiconductor device, method of controlling valve, and method of fabricating semiconductor device using the apparatus
Inventor: WON SEOK-JUN
IPC: F16K11/00
Filed: 2006-01-10
Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
Patent TW-200641367-A (TW)
Title: Method and apparatus for verifying planarity in a probing system
Inventor: GRUBE GARY W
IPC: G01R31/02
Filed: 2006-01-27
Abstract: An apparatus for determining a planarity of a first structure configured to hold a probing device to the planarity of a second structure configured to hold a device to be probed is disclosed. In one example of the apparatus, a plurality of moveable push rods are disposed in a substrate, which is attached to the first structure. In initial non-displaced positions, the push rods correspond to a planarity of the first structure. The second structure is then brought into contact with the push rods, displacing the push rods into second positions that correspond to a planarity of the second structure. In another example of the apparatus, beams of light are reflected off of reflectors disposed on the first structure and onto sensors disposed on the second structure. The locations of the reflected beams on the sensors are noted and used to determine the planarity of the first structure with respect to the second structure.
Patent TW-200709817-A (TW)
Title: Platform antibody compositions
Inventor: DAS TAPAN KANTI
IPC: A61K47/22
Filed: 2006-03-03
Abstract: The present invention provides novel compositions of human IgG2 antibodies comprising a chelating agent. The present invention also provides novel antibody compositions that exhibit improved chemical and/or physical stability. Also provided are methods of treating diseases and conditions with compositions of human IgG2 antibodies, including inflammatory diseases and neoplasia disorders.
Patent TW-200700404-A (TW)
Title: Anticancer compounds, intermediates and the method for preparation thereof
Inventor: TOKUDA HARUKUNI
IPC: A61P35/00
Filed: 2006-03-15
Abstract: The present invention provides a method for preparing easily and inexpensively 2-(1-hydroxyethyl)-5-hydroxynaphtho[2,3-b]furan-4,9-dione (abbreviated as "NFD") in an optically active form or a racemic mixture thereof in high yields. The present invention also provides 2-acetyl-2,3-dihydro-5-hydroxynaphtho[2,3-b]furan-4,9-dione which is useful as an intermediate for preparing NFD. The present invention also provides anticancer drugs comprising 2-(1-hydroxyethyl)-5-hydroxy-naphtho[2,3-b]furan-4,9-dione as an active ingredient. 2-(1-Hydroxy-ethyl)-5-hydroxynaphtho[2,3-b]furan-4,9-dione may be obtained in 4 or 5 steps from 5-hydroxynaphthalene-1,4-dione (also known as juglone) as a starting material, which is available at a comparatively moderate price.
Patent TW-200706296-A (TW)
Title: Magnesium wire for welding
Inventor: OISHI YUKIHIRO
IPC: B23K35/28
Filed: 2006-03-17
Abstract: This invention provides a magnesium wire for welding having excellent surface cleanness, and the manufacturing method of the same. The magnesium wire for welding of this invention is made by the shaving process conducted on the surfaces of the wire-drawn materials obtained after the wire-drawing process conducted on the mother materials, e.g., extruded materials formed by the pure magnesium or magnesium-based alloys. The lubricant used in the wire-drawing or the covered film can be effectively removed by the shaving process conducted after wire-drawing, and oxide happens to the wire-drawing can also be removed. Thus, the wire for welding is excellent in surface cleanness. The lubricant used in wire-drawing process had better be the oil-based lubricant or wet-type lubricant which are easily removed by washing or degreasing treatment.
Patent TW-200739921-A (TW)
Title: Manufacturing method of non-volatile memory and operating method thereof
Inventor: HSU CHENG-YUAN
IPC: H01L29/788
Filed: 2006-04-14
Abstract: An operating method of a non-volatile memory is described. The operating method contains a program step and an erase step. The program step is that a first positive voltage is applied on the control gate; a second positive voltage is applied on the select gate; a third positive voltage is applied on source region; and a 0 voltage is applied on drain region so as to use the channel hot electron effect to program the non-volatile memory. The erase step is that a fourth positive voltage is applied on the erase gate; a 0 voltage is applied on the control gate; a fifth positive voltage is applied on source region; and a 0 voltage is applied on drain region so as to use the F-N tunnel effect to erase the non-volatile memory.
Patent TW-200709588-A (TW)
Title: Continuous-time equalizer
Inventor: MARTIN AARON
IPC: H04B7/005
Filed: 2006-04-20
Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.
Patent TW-200719406-A (TW)
Title: Sealing part and substrate processing apparatus
Inventor: HAYASHI DAISUKE
IPC: F16J15/10
Filed: 2006-06-13
Abstract: A sealing part that is inexpensive and enable excellent durability to be secured without the need for a predetermined sealing space as would be required for a double sealing structure. A sealing part seals an inside of a reduced pressure vessel from an outside, in which a high-elasticity polymeric material-eroding eroding substance is present and which is comprised of a substrate processing apparatus carrying out predetermined processing on a substrate housed in the reduced pressure vessel. The sealing part has a radical sealing member and a vacuum sealing member. The radical sealing member is disposed on an inside side of the reduced pressure vessel and is resistant to the eroding substance. The vacuum sealing member is made of the high-elasticity polymeric material and is disposed on an outside side of the reduced pressure vessel. At least one refuge space is formed through at least part of the radical sealing member and at least part of the vacuum sealing member being separated from one another. The radical sealing member and the vacuum sealing member are fitted together.
Patent TW-200740437-A (TW)
Title: Quinoline derivatives as antibacterial agents
Inventor: ANDRIES KOENRAAD JOZEF LODEWIJK MARCEL
IPC: A61P31/04
Filed: 2006-06-27
Abstract: Use of a compound for the manufacture of a medicament for the treatment of a bacterial infection provided that the bacterial infection is other than a Mycobacterial infection, said compound being a compound of formula (Ia) or (Ib), a pharmaceutically acceptable acid or base addition salt thereof, a stereochemically isomeric form thereof, a tautomeric form thereof or a N-oxide form thereof, wherein R1 is hydrogen, halo, haloalkyl, cyano, hydroxy, Ar, Hot, alkyl, alkyloxy, alkylthio, alkyloxyalkyl, alkylthioalkyl, Ar-alkyl or di(Ar)alkyl; p is 1, 2, 3 or 4; R2 is hydrogen, hydroxy, mercapto, alkyloxy, alkyloxyalkyloxy, alkylthio, mono or di (alkyl )amino or a radical of formula ; R3 is alkyl, Ar, Ar-alkyl, Hot or Het-alkyl; q is 1, 2 or 3; R4 and R5 are hydrogen, alkyl or benzyl; or R4 and R5 together and including the N to which they are attached may form a ring; R6 is hydrogen, halo, haloalkyl, hydroxy, Ar, alkyl, alkyloxy, alkylthio, alkyloxyalkyl, alkylthioalkyl, Ar-alkyl or di(Ar)alkyl; or two vicinal R6 radicals may be taken together to form a bivalent radical of formula -CH=CH-CH=CH-; r is 1, 2, 3, 4 or 5; R7 is hydrogen, alkyl, Ar or Hot; R8 is hydrogen or alkyl; R9 is oxo ; or R8 and R9 together form the radical -CH=CH-N=.
Patent TW-200711538-A (TW)
Title: Circuit arrangement and method for operating at least one electric lamp
Inventor: FISCHER KLAUS
IPC: H05B41/285
Filed: 2006-07-11
Abstract: The present invention relates to a circuit arrangement for operating at least one electric lamp (EL) having an inverter having at least one first bridge transistor (T3) and one second bridge transistor (T4) which are arranged in series with one another, a first drive circuit (AS1) for the first bridge transistor (T3); a second drive circuit (AS2) for the second bridge transistor (T4); the first drive circuit (AS1) and the second drive circuit (AS2) being designed to drive the first bridge transistor (T3) and the second bridge transistor (T4) such that they switch alternately completely on and off during normal operation of the lamp (EL); and at least one protective apparatus (TS1; TS2); the at least one protective apparatus (TS1; TS2) being designed, in the case of a value for a reference voltage, which is correlated with the voltage across the bridge transistor (T3; T4) which has just been switched off, above a predeterminable limit value, to drive the bridge transistor (T4; T3), which has just been completely switched on, of the series circuit such that it is no longer completely switched on. It moreover relates to an operating method for at least one electric lamp using such a circuit arrangement.
Patent TW-200726332-A (TW)
Title: Circuit board and its production method
Inventor: BUSCH GEORG
IPC: H05K1/14
Filed: 2006-07-25
Abstract: A circuit board and its production method is provided, which facilitate an effective and cost-advantageous heat-removal of electrical members arranged on one side of the circuit board, the waste heat to be removed in electrical members is conducted to the other side of the circuit board. With respect to the circuit board, the purpose above is attained by the fact that the circuit board is provided with through-holes filled with soldering tin, the through-holes conduct the waste heat to be removed from one side of the circuit board to the other side. With respect to the method, the purpose above is attained by the fact that the through-holes for the removal of heat in the circuit board are pressed with soldering paste and in the following soldering process are filled with soldering tin.
Patent TW-200713945-A (TW)
Title: Method and apparatus for OVSF code generation
Inventor: YEH YEN-HUI
IPC: H04J11/00
Filed: 2006-08-09
Abstract: Methods and apparatuses for generating an OVSF code are disclosed. A proposed method for generating a current code chip of an OVSF code includes: determining a correlation factor between the current code chip and a preceding code chip of the OVSF code; and generating the current code chip according to the preceding code chip and the correlation factor.
Patent TW-200715779-A (TW)
Title: Restrictive reuse set management algorithm for equal grade of service on FL transmission
Inventor: Ji ting-fang
IPC: H04W16/12
Filed: 2006-08-11
Abstract: Systems and methodologies are described that facilitate restrictive reuse resource set management with equal grade of service on forward link transmission. User throughput over a resource reuse set can be estimated, and an iterative method can be employed to reallocate users with poor spectral efficiency to reuse sets exhibiting high throughput to optimize overall throughput in a wireless network or a portion thereof.
Patent TW-200810705-A (TW)
Title: A kind of constituting ingredients to improve the quality of noodles
Inventor: LEE LUNG-CHIH
IPC: A23L7/109
Filed: 2006-08-30
Abstract: A kind of constituting ingredients to improve the quality of noodles. The characteristics is added water which is dissolved 1 to 5% salt, 0.1 to 1.0% kansui and polyphosphate 0.1 to 0.5% mixed with Sodium Tripolyphosphate 40 to 70% and Tetrasodium Pyrophosphate 20 to 40% and Sodium Trimetaphosphate 10 to 25% and Sodium Hexametaphosphate 5 to 20% to wheat flour. Then mixing, rolling to sheet, noodle formation square or round strand, cutting to be one serve noodle. We can get fresh noodle that is improved quality.
Patent TW-200718278-A (TW)
Title: Organic electroluminescence display device
Inventor: JINNO YUSHI
IPC: H05B33/22
Filed: 2006-09-14
Abstract: To provide an organic electroluminescence display device wherein the generation of optical current due to external light can be inhibited and the variation of transistor property or the poor short due to the influence of back channel can also be prohibited. In the organic EL display device of the present invention, a light chopping film (70) of nonconductive material is formed on an insulation substrate (10), a back gate insulation film 11 is formed to cover the light chopping film (70), an active layer (33) is formed on the back gate insulation film (11), a gate insulation film (12) is formed to cover the active layer (33), and a gate electrode (31) is formed on the gate insulation film (12). The light chopping film (70) is disposed to interpose the back gate insulation film (11) so as to cover the active layer (33), and works to chop the external light paragating toward the active layer (33) through the insulation substrate (10).
Patent TW-200726552-A (TW)
Title: Tool uncramp device
Inventor: KITAURA ICHIRO
IPC: B23B31/117
Filed: 2006-09-18
Abstract: Tool uncramp device uncramps a tool clamped at a main shaft of a machine, and comprises a housing 2, an output shaft 11, a motor 3, a power transmission mechanism, and a gas cylinder 4. The output shaft 11 output necessary power when uncrampling the tool disposed at the housing 2. The motor 3 serves as a power source to provide power for driving output shaft 11. The power transmission mechanism transmits power from the motor 3 to the output shaft 11. The gas cylinder 4 serves as an auxiliary power source to provide auxiliary power to the power transmission mechanism.
Patent TW-200722934-A (TW)
Title: Method of patterning a positive tone resist layer overlaying a lithographic substrate
Inventor: FINDERS JOZEF MARIA
IPC: H01L21/027
Filed: 2006-10-04
Abstract: A single exposure method and a double exposure method for reducing mask error factor and for enhancing lithographic printing-process resolution is presented. The invention comprises decomposing a desired pattern of dense lines and spaces in two sub patterns of semi dense spaces that are printed in interlaced position with respect to each other, using positive tone resist. Each of the exposures is executed after applying a relative space-width widening to the spaces of two corresponding mask patterns of semi dense spaces. A factor representative for the space-width widening has a value between 1 and 3, thereby reducing mask error factor and line edge roughness.
Patent TW-200820423-A (TW)
Title: Method for preparing a trench capacitor structure
Inventor: LAI SU-CHEN
IPC: H01L27/108
Filed: 2006-10-25
Abstract: The present method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a buried bottom electrode positioned on a lower outer surface of the trench. A dielectric layer is then formed to cover the inner sidewall of the trench, and a plurality of deposition processes are then performed to form several polysilicon layers in the trench, wherein a diffusion process is performed by introducing a gas containing conductive dopants into the trench at the interval of these deposition processes to diffuse the conductive dopants into the polysilicon layers. A planarization and an anisotropic dry etching processes are performed to remove a portion of the polysilicon layers from the top portion of the trench to form a top electrode in the lower portion of the trench, a collar oxide layer is then formed on the upper sidewall of the trench, and the collar oxide layer is used as an implanting mask to perform an implanting process to implant conductive dopants into the top electrode.
Patent TW-200824061-A (TW)
Title: Chip package structure
Inventor: CHENG HUNG-HSIANG
IPC: H01L23/31
Filed: 2006-11-20
Abstract: A chip package structure including a chip pedestal, a chip, a plurality of leads, a plurality of wires and an encapsulant is provided. The chip pedestal has a first area. The chip has an active surface and a second back surface opposite thereto, and the chip is disposed on the chip pedestal through the second back surface. The leads are disposed around the chip, and each of the leads has an inner end and an outer end. The inner ends define a second area which is smaller than the first area. The leads are kept from the chip pedestal with a fixed gap. The wires connect the leads and the active surface of the chip. The encapsulant encapsulates the chip, the wires and the inner ends of the leads.