baber/WOPTO huggingface dataset:
Patent TW-434986-B (TW)
Title: Smoothing circuit of switching power supply
Inventor: UEKI KOUICHI
IPC: G05F1/613
Filed: 1998-11-10
Granted: 2001-05-16
Abstract: This invention is to provide a smoothing circuit of switching power supply that can reduce output noise and stably generate action without decreasing efficiency. Based on this and the explanation is shown in the following by using figure 1 as the reference. In a smoothing circuit for a switching power supply having a reactor and a capacitor, the circuit includes a resistor 7 connected in series to the capacitor 6, a MOSFET 8 connected in parallel to the resistor 7, and a control circuit 20 for turning the MOSFET on when the voltage at both ends of the resistor 7 is formed above the reference voltage 26 or below the reference voltage 27. Thus, the output waveform is changed from a triangular wave to a sine wave in order to reduce the harmonic components contained in the output ripple.
Patent TW-460605-B (TW)
Title: Chemical vapor deposition hot-trap for unreacted precursor conversion and effluent removal
Inventor: SCHMITT JOHN VINCENT
IPC: C23C16/44
Filed: 1998-11-03
Granted: 2001-10-21
Abstract: A hot trap converts unreacted organic metal-film precursor from the exhaust stream of a CVD process. The converted precursor forms a metal film on the surface of the hot trap, thereby protecting hot vacuum pump surfaces from metal build up. A cold trap downstream from the hot trap freezes effluents from the exhaust stream. The metal captured by the hot trap and the effluents captured by the cold trap may then be recycled, rather than being released as environmental emissions.
Patent TW-430827-B (TW)
Title: Resistors with low temperature coefficient of resistance and methods of making
Inventor: VENKATRAMAN CHANDRA
IPC: H01C17/075
Filed: 1999-05-11
Granted: 2001-04-21
Abstract: The present invention relates to a method of making a resistor having a low temperature coefficient of resistance which includes applying a first resistor layer and applying a second resistor layer over the first resistor layer, where either the first resistor layer or the second resistor layer includes a diamond-like material. The diamond-like material includes carbon, hydrogen, and a metal, and has a low temperature coefficient of resistance. The present invention also relates to a resistor.
Patent TW-429734-B (TW)
Title: Method of forming solder mask
Inventor: JENG JEN-HUA
IPC: H05K3/00
Filed: 1999-05-19
Granted: 2001-04-11
Abstract: A method of forming a solder mask for circuit board with a high layout density, comprises providing a substrate board having patterned wires on the surface thereof, in which the wires having a solder pad region for electric connection with other devices; coating a first green paint on the board covering the wires and the board and filling up the gap between the wires; pre-baking the paint; removing a portion of the first green paint to expose the surface of the wires and solidifying the green paint layer between the wires; coating a second green paint on the board covering the wires and the green paint layer between the wires; pre-baking, exposing and developing the second green paint; and removing the second green paint on the solder pad region of the wires to expose the surface of the solder pad region of the wires.
Patent TW-439204-B (TW)
Title: Improved-reliability damascene interconnects and process of manufacture
Inventor: CLEVENGER LARRY
IPC: H01L21/3205
Filed: 1999-07-31
Granted: 2001-06-07
Abstract: An improved-reliability conductive damascene structure in a depression within an insulator layer of a semiconductor substrate and its process of manufacture. The process comprises depositing a wetting layer having a first metal in contact with the insulator layer in the depression, uniformly depositing a barrier layer over the wetting layer, and depositing a conductive layer having a second metal over the barrier layer. The conductive layer deposition step is performed at a temperature below which the first and second metals diffuse through the barrier layer to create intermetallic compounds of the first and second metals.
Patent TW-432441-B (TW)
Title: Plasma display panel and manufacturing method thereof
Inventor: TOYODA OSAMU
IPC: H01J11/36
Filed: 1999-08-03
Granted: 2001-05-01
Abstract: The present invention provides a plasma display panel and a manufacturing method thereof. A protruding portion is disposed in a groove portion between partition plates, and a fluorescent body layer is formed on the protruding portion, thereby increasing the adhesion area of the fluorescent body and enhancing brightness. A discharge space is formed between a pair of opposing substrates. A plurality of strip-shaped partition plates partition the discharge space, and are arranged on the back side face or the front side face  of the substrates. At the same time, a plate-shaped protruding portion is disposed lower than the partition plates and is capable of increasing height of the forming area of the fluorescent body layer. The protruding portion surrounds the fluorescent body layer disposed in a thin elongate groove between the partition plates, and at least an area of the discharge portion or the discharge portion of the plasma display panel formed in the thin elongate groove between the partition plates. The fluorescent body layer is formed in the groove between the partition plates that has the plate-shaped protruding portion.
Patent TW-419749-B (TW)
Title: Method for etching double-layer oxide/nitride film
Inventor: YUAN TIAN-MIN
IPC: H01L21/311
Filed: 1999-09-06
Granted: 2001-01-21
Abstract: The present invention provides a method for etching a double-layer oxide/nitride film, in which the double-layer film of oxide/nitride film is used as a mask in forming a deep trench. The method according to the present invention comprises: providing a semiconductor substrate; forming a pad oxide on the semiconductor substrate; forming a nitride layer on the pad oxide layer; forming a mask oxide layer on the nitride layer; forming a photoresist layer on the mask oxide layer; patterning the photoresist layer to form an opening; etching the mask oxide layer by a magnetic enhanced reactive ion etching; and etching the nitride layer by a reactive ion etching.
Patent TW-432679-B (TW)
Title: Semiconductor memory device capable of easily controlling a reference ratio regardless of change of a process parameter
Inventor: KOHNO TAKAKI
IPC: H01L21/8247
Filed: 1999-09-15
Granted: 2001-05-01
Abstract: A semiconductor memory device comprises matrix memory cell banks, a reference cell bank device, and a sense circuit. The matrix memory cell banks and the reference cell bank device have deputy bit lines which are implemented by embedded diffused layers, respectively. Each of the matrix memory cell banks comprises a first set of memory cells. The first set of memory cells are for holding data. The reference cell bank device comprises a predetermined number of reference cell banks which are directly connected. Each of the reference cell banks comprises a second set of reference cells. The reference cells are for holding reference voltages. The sense circuit receives data voltages which are read out from the matrix memory cell banks and the reference voltages from the reference cell bank device to determine levels of the data voltages by comparing the data voltages with the reference voltages.
Patent TW-449747-B (TW)
Title: High speed sensing circuit for a memory device
Inventor: CHEN CHIEN-CHUNG
IPC: G11C16/28
Filed: 1999-10-08
Granted: 2001-08-11
Abstract: A sensing circuit for sensing the binary state of a memory cell includes a first transistor wherein the first spaced-apart region is connected to a first voltage source, and the gate is connected to a second voltage source, a second transistor wherein the first spaced-apart region of the second transistor is connected to the second spaced-apart region of the first transistor, and a third transistor wherein the first spaced-apart region is connected to the second spaced-apart region of the second transistor, the gate is electrically connected to the memory cell, and the second spaced-apart region is connect to a ground potential. The circuit also includes a circuit to generate a first current in response to one binary state of the memory cell and a second current in response to another binary state of the memory cell wherein a feedback circuitry is created between the circuitry to generate currents and the second transistor, and a circuit to produce output signals in response to the first current and the second current.
Patent TW-445734-B (TW)
Title: Cellular phone, flip, and hinge
Inventor: SAKUMA MASAO
IPC: H04W88/02
Filed: 1999-11-11
Granted: 2001-07-11
Abstract: A cellular phone has a flip connected to the main body of the cellular phone in a pivotable manner. The flip has an inner face and an outer face when the flip is closed with respect to the main body. The main body has a first antenna, and the flip has a second antenna. The second antenna is preferably a plane antenna formed on the outer face of the flip by, for example, vacuum evaporation. The center of mass of the second antenna is located further from the main body than the center of the flip when the flip is opened. A coupling antenna is provided in the inner face of the flip, and a radio signal is transferred from the second antenna to the coupling antenna by capacitive coupling. A resonator element which resonates with the second antenna is also provided in the inner face of the flip in a region other than the area corresponding to the second antenna which is formed on the outer face of the flip. A receiving circuit for demodulating the radio signal, and a switch circuit for switching the inputs to the receiving circuit between the first and second antennas may also be provided to the cellular phone.
Patent TW-468044-B (TW)
Title: Method of analyzing organic contaminant in gas
Inventor: SASAKI YASUSHI
IPC: H01J49/04
Filed: 1999-11-11
Granted: 2001-12-11
Abstract: A method of analyzing an organic substance existing as a contaminant in a moisture-containing gas at a high sensitivity of the ppt level using atmospheric-pressure mass spectrometry is provided. This method is comprised of the steps of (a) ionizing particles of a carrier gas at an atmospheric pressure (a primary ionization step); (b) colliding the ionized particles of the carrier gas with particles of a sample gas, thereby ionizing particles of an organic contaminant existing in the sample gas at an atmospheric pressure (a secondary ionization step); and (c) analyzing the ionized particles of the contaminant existing in the sample gas by mass spectrometry, thereby identifying the contaminant and finding a concentration of the contaminant. The sample gas contains moisture or water molecules. The carrier gas contains a component whose molecules have an ionization potential lower than that of water molecules and higher than that of the contaminant. The component of the carrier gas is selectively ionized in the step (a). An O2 gas, or a mixture of an Ar or N2 gas and a SiH4 gas is preferably used as the carrier gas, in which SiH4 gas is the component of the carrier gas.
Patent TW-448270-B (TW)
Title: Self-tapping screw
Inventor: KOENIG GOTTFRIED
IPC: F16B25/00
Filed: 1999-12-10
Granted: 2001-08-01
Abstract: Self-tapping screw having an at least partially non-round enveloping curve for the thread and having a penetrating section and a retaining section, it being the case that the penetrating section contains a plurality of successive thread stages which each have at least one thread turn and, along the thread stage, have essentially the same, aligned enveloping curve which runs either cylindrically or elliptically, the thread stages with an elliptical enveloping curve (elliptical thread stage) being combined such that the major axes of the successive elliptical thread stages, forming a stage group, are offset with respect to one another.
Patent TW-448550-B (TW)
Title: Circuit board and display apparatus and electronic equipment using the same
Inventor: ENDO KATSUMA
IPC: H05K1/18
Filed: 1999-12-13
Granted: 2001-08-01
Abstract: The object of the present invention is to improve the adhesive power of adhesion resin against a base board and to improve the electric connection reliability of a semiconductor chip and a wiring board in the circuit board of structure where the semiconductor chip is mounted on the base board through the use of adhesion resin. To achieve the object, in a circuit board, an input wiring 420a, an output wiring 420b and a dummy wiring layer 422 are formed on the IC chip mounting area of a base film 410 having insulating property and flexibility, and an IC chip 450 is mounted and formed through an anisotropic conduction film where conductive particles 21 are dispersed in adhesion resin 19. The dummy wiring layer 422 is insulated from the input wiring 420a, the output wiring 420b and the electrodes 450a and 450b of the IC chip, and several opening parts 422a are installed.
Patent TW-441033-B (TW)
Title: Method to form embedded memory and logic circuit in a single substrate
Inventor: JENG JR-SHIANG
IPC: H01L21/8242
Filed: 1999-12-14
Granted: 2001-06-16
Abstract: A method to combine the integrated circuit device of memory cell array and logic circuit array in a single chip or substrate is revealed. The present invention provides a method which comprises the embedded DRAM region in the substrate of the first transmission field effect transistor having the first gate, the source/drain, and the logic circuit region in the substrate of the logic field effect transistor having the second gate, the second source/drain. Secondly, deposit a dielectric layer on the surface of the transmission field effect transistor and the logic field effect transistor, polish the dielectric layer until the surface of the first gate and the second gate are exposed. Then, form a photoresist layer on the surface of the dielectric layer and the first gate, etch the dielectric layer until the surface of the logic field effect transistor is exposed, remove the photoresist layer. Finally, deposit a self-aligned metal silicide layer to the second gate, the second source/drain, and the first gate simultaneously.
Patent TW-531945-B (TW)
Title: RJ jack with integrated interface magnetics
Inventor: BERNSTEIN ELLIOT
IPC: H01R13/703
Filed: 2000-01-20
Granted: 2003-05-11
Abstract: An RJ jack includes a first housing having bottom, side, rear, front and top walls defining an interior chamber and an opening through the front wall through which a plug may be received into the interior chamber. A plurality of contact fingers extend from beneath the bottom wall to and over the front wall and into the interior chamber. The spacing between the contact fingers in the interior chamber is equal to the spacing of corresponding contacts in the plug with the spacing of the contact fingers extending beneath the bottom wall being substantially greater. A second housing is removably secured to the rear wall of the first housing, the second housing containing a plurality of magnetic elements. At least two guides for receiving light emitting devices are formed on the rear wall of the second housing. The top wall extends over the first and second housings and has a stopper for limiting movement of the plug within the chamber and a locking mechanism for releasably securing the plug within the chamber, and is transparent for transmitting light from the light emitting devices.
Patent TW-456063-B (TW)
Title: Lithium secondary battery
Inventor: KOBAYASHI KOUTARO
IPC: H01M10/42
Filed: 2000-03-30
Granted: 2001-09-21
Abstract: A lithium secondary battery capable of improving high temperature cycle life characteristic effectively without decreasing discharge capacity. Amorphous carbon powder with a specific surface area of 10.0 m<SP>2</SP>/g and a mean particle diameter of 7.0 μm is used as negative electrode active material and lithium manganate with a Li/Mn ratio of 0.58 is used as positive electrode active material. Since a surface area of the negative electrode active material layer is made large by setting the mean particle diameter of the amorphous carbon powder to 10 μm or less, the surface area of the negative electrode active material layer is sufficiently large that, even when inert coating is formed on the surface of the negative electrode due to manganese deposition caused by manganese elution from the positive electrode, high temperature cycle life characteristic can be improved without high temperature deterioration.
Patent TW-461147-B (TW)
Title: An antenna structure capable of receiving signals from the global positioning system and the global system for mobile communication simultaneously
Inventor: LIN HUEI-JEN
IPC: H01Q5/00
Filed: 2000-04-14
Granted: 2001-10-21
Abstract: This invention introduces an antenna structure capable of receiving signals from the global positioning system (GPS) and the global system for mobile communication (GSM) simultaneously. The structure mainly uses a cylindrical body made of dielectric material with a hole penetrating its center in the axial direction. The inner surface of this penetrating hole is covered with a conducting layer, which is connected to a grounded conducting layer covering one of the end surfaces of the dielectric body. Then, the penetrating hole is filled with an insulator with its central feeding pin sticking out of the two ends of the dielectric body. One end of the center pin away from the grounded conducting layer is connected to a helical antenna. The outer surface of the dielectric body is covered with one patch antenna. Therefore, the so formed antenna can not only receive the signals from the global positioning system (GPS) and the global system for mobile communication (GSM), respectively, but also effectively reduce the volume of the whole antenna and significantly lower the production and transportation costs.
Patent TW-562815-B (TW)
Title: Process for preparation of elastomer modified polymer compositions with enhanced rubber phase volume fraction
Inventor: WICHER JEROME
IPC: C08F2/01
Filed: 2000-04-15
Granted: 2003-11-21
Abstract: A process is provided to prepare elastomer modified polymer compositions based on styrenic monomer(s) using certain organic peroxide initiators to increase both rubber particle size and rubber phase volume fraction (gel content).
Patent TW-432141-B (TW)
Title: Assembling construction method for light partition wall
Inventor: LI WEN-WANG
IPC: E04B2/82
Filed: 2000-06-14
Granted: 2001-05-01
Abstract: This invention of assembling construction method of light partition wall includes the following steps. (1) To pre-set and fix square steel as strutting frame where the partition wall will be assembled later. (2) Then to erect the pre-burnt partition boards onto the strutting frames by putting the partition boards back to back to make the embedding and clipping possible through the big flutes on their backs. (3) To do the positioning by screwing and fastening them to the strutting frames. Then repeat the procedures to complete the partition wall erection. The method provides a time-saving and efficient construction work, besides a clean construction environment to insure no damage occurred to the rest parts in the site room.
Patent TW-476212-B (TW)
Title: One-button-triggered image processing unit
Inventor: LU KUANG-RONG
IPC: H04N1/00
Filed: 2000-07-12
Granted: 2002-02-11
Abstract: The present invention provides a one-button-triggered image processing unit with functions of image automatic processing. It comprises: an input button for inputting a trigger signal to activate the unit; a pre-scan module for using a predefined low resolution corresponding to the user-defined resolution to perform a pre-scan operation after the unit is activated, thereby obtaining a scanning image of a smaller area in a faster scanning speed; a target image calculation module for calculating the image area from the pre-scan; a target image data fetch module for obtaining all target image areas based on the calculated value; a scan module for performing a scan operation based on the user-defined resolution; a target image processing module for filtering out impurities and straightening the target image; and a crop module for taking out the target image. The present invention also provides another one-button-triggered image processing unit. The one-button-triggered image processing unit comprises: an input button formed on an input device for triggering the signal to activate the input device; a pre-scan module for using a predefined low resolution corresponding to the user-defined resolution to perform a pre-scan operation after the unit is activated, thereby obtaining a scanning image of a smaller area in a faster scanning speed; a target image calculation module for calculating the image area from the pre-scan; a target image data fetch module for obtaining all target image areas based on the calculated value; a scan module for performing a scan operation based on the user-defined resolution; a target image processing module for filtering out impurities and straightening the target image; and a crop module for taking out the target image.
Patent TW-548497-B (TW)
Title: Flexible wiring board, electro-optical device and electronic equipment
Inventor: FURIHATA HIROAKI
IPC: G02F1/13
Filed: 2000-07-24
Granted: 2003-08-21
Abstract: The invention provides a flexible wiring board which is of high productivity and low cost, while permitting a wiring pattern to be miniaturized, and to provide an electro-optical device and electronic equipment, each incorporating the flexible wiring board. A flexible wiring board 100 includes a first single-sided flexible board 10 and a second single-sided flexible board 20. The first single-sided flexible board 10 includes a first base body 12 having an insulative property, and a first wiring layer 14 formed in a predetermined pattern on the first base body. The second single-sided flexible board 20 includes a second base body 22 having an insulative property, and a second wiring layer 24 formed in a predetermined pattern on the second base body. The first and second single sided flexible boards respectively have insulating layers 16 and 26 covering the wiring layers 14 and 24, and the insulating layers are provided with contact sections C10 and C20 respectively. The first single-sided flexible board 10 and the second single-sided flexible board 20 are arranged so that the first wiring layer and the second wiring layer face each other, and are bonded through an anisotropically conductive adhesive layer 30.
Patent TW-557505-B (TW)
Title: Method for stripping copper in damascene interconnects
Inventor: GUPTA SUBHASH
IPC: H01L21/302
Filed: 2000-08-25
Granted: 2003-10-11
Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.