Patent GB-734789-A (GB)
Title: Improvements in or relating to calculating machines controlled by statistical record cards
Inventor: GUTTRIDGE ERIC JOHN
IPC: G06F7/52
Filed: 1952-11-01
Abstract: 734,789. Digital electric calculating-apparatus. POWERS-SAMAS ACCOUNTING MACHINES, Ltd. July 9, 1953 [Nov. 1, 1952], No. 27533/52. Class 106 (1). In an electrical record-card-controlled machine, calculating-apparatus comprises a non- counting register, a first counting register and a second counting register for results, each register including a trigger circuit for each digit registering position of each denomination, cycling selector gates for controlling entry of an amount in the non-counting register into the first counting register, transfer gates for controlling entry into the non-counting register of an amount in the first counting register, transmit gates connecting the cycling selector gates and second counting register to control entry into the latter of an amount in the non- counting register, and programme unit-gates arranged to control sequential operation of the transfer gates and selective operation of the transmit gates. General arrangement. The apparatus described is for multiplying a sterling'multiplicand and four-digit multiplier, sensed from fields MCF, MF of a record card, Fig. 1, and punching the product in a further card field PF, and consists primarily of Eccles-Jordan trigger circuits, diode gating networks and cam-. operated timing switches. The multiplifiersensing means MS, Fig. 2A, controls a decimal point selector DPS and a multiplier-coding-andconverting network MPC whereby the multiplier if it contains a decimal fraction, is multiplied by the power of ten necessary to convert it into a whole number, the multiplicand being divided by the same power of ten in the multiplicand-sensing coding and dividing network MCSC. This divided multiplicand is formed in two parts which are entered through selected gates DCG,DPG into non-counting register R and added in counting register CR1 during addition periods 1 and 2 of a calculation cycle, Fig. 11A. Subsequently, the amount in CR1 is entered in R (previously re-set), the amount in R is added into CR1 in such manner as to build up in CR1 partial products of the multiplicand, and selected amounts from Rare passed through gates TG to produce the required product in register CR2. This calculation is performed during four groups of five addition periods. Fig. 11A, each group corresponding to one multiplier digit, and is followed by a check calculation. If an error is detected, the setting of the relays which control the punching of the result is cancelled. The setting is cancelled also if certain over-capacity conditions are detected. A presettable switch enables different manners of rounding off to be selected. The sequence of operations is controlled by circuits (Fig. 2A, top) including programme gates PUG, and a pulse-generating multivibrator MU. Figs. 24 and 27 indicate the waveforms for an addition period and a complete cycle of operations respectively. Card-sensing. The sensing mechanism (not shown) is such that contacts MPS and MCS, Figs. 3 and 4, corresponding to sensed holes are maintained closed throughout a calculation and the subsequent checking operation. Decimal point selector. If there is a non- zero digit in any denomination of the multiplier the corresponding relay ER1 2 . . . 8, Fig. 3, is energized through the closed contact MPS. Each relay operates contact ERC2 to remove the earth potential on line ERE from zero-indicating line Z, and contact ERC1, whereby line ERE is connected to one of the lines DPS1, 2...5, which correspond respectively to 0,1 ... 4 multiplier digits to the right of the decimal point, i.e. to multiplication of the multiplier and division of the multiplicand by 10<SP>4</SP>, 10<SP>5</SP>... 10<SP>0</SP>. Coding, dividing and registering the multiplicand. Fig. 4 shows a network for coding one denomination of decimal fractions of pence or pounds. The output lines 1, 2, 4, 2* are connected to corresponding trigger circuits in register R, Fig. 5, through coincidence gates DCG selectively opened by DPS according to power of ten by which division is to be made, and pulse gates DPG. The right-most four denominations of R can register pounds or decimal pence as indicated but the sensed multiplicand can contain pounds only if the multiplier is a whole number (line DPS5, Fig. 3, marked) since no networks are provided for dividing pounds. Since division of pence and shillings produces multi-denominational values, the corresponding coding networks (Figs. 6 and 7 respectively, not shown) each comprise a plurality of groups of output lines for entry into a plurality of denominations of register R, and to avoid simultaneous entries into the same register trigger circuit the division of units of shillings is performed separately, the two stages of the division being controlled by pulses PSP, SSP, Figs. 5, 11A and 27, applied to the appropriate gates DPG. Counting registers or accumulators; register connections. The register CR2, Fig. 12, is similar to that described in Specification 727,507,. and comprises a carry-storing circuit CM for each denomination, any stored carry being transferred to the next denomination at the end of an addition period by applying pulses COP, Figs. 2A and 24. A carry connection from the left-most 10/- denomination, Fig. 12, enables the four right-most denominations to register pounds, the interpretation of the registrations being dependent on the condition of DPS, Figs. 2A and 3. The register CR1 is similar to CR2 but its denominations are coded, not as shown in Fig. 12, but as in the register R, Fig. 5. Each trigger stage of CR1 is connected to the corresponding stage of R through a gate CRITG similar to DPG but controlled by pulses MCSP, Fig. 27, so that the amount in CR1 is set up in R during the first two addition periods of each of the four multiplication groups, Fig. 11A. During each addition period the amount in R is added into CR1 by means of pulses DP1, DP2, DP4, DP2<SP>*</SP>, DP4<SP>*</SP>, Fig. 24, selectively applied through gates CSG, each controlled through a cathode follower CF4 by one stage of R. These pulses are applied to CR2 through gates TG which are controlled through cathode followers CF3 by the network MPC described below. Coding and converting the multiplier. The network MPC, Fig. 9, comprises -gates EDCG controlled by DPS, Fig. 3, and by waveforms MP1-MP4, corresponding respectively to the units, the tens, hundreds and thousands multiplier digit (see Figs. 11A and 27) so as to open, through cathode followers CF2, a selected one of gates DDCG during each group of addition periods, Fig. 11A. Each gate DDCG receives from gates. CDCG through cathode followers CF1 the combination of waveforms MC1, MC2, MC4, MC2<SP>*</SP> which corresponds to the value of one of the multiplier digits set up on contacts MPS, and has its output connected through CF3 to gates TG. The times of opening of the latter are thus determined by each of the four coded multiplier digits in turn. Reading out, de-coding and punching the product. Each registering trigger stage of CR2, Fig. 12, has a read-out triode (half of a double triode PT1 or PT2') associated therewith and the output of each such triode (positive if the corresponding stage is in the operative condition) is applied from a terminal such as TOP, Fig. 13A, to the control grid of a triode PT3. When earth is removed from the control grids of triodes PT3 by the opening of a normally closed cam-operated switch RO1, those triodes corresponding to operative stages of CR2 are therefore rendered conductive to energize solenoids S in their anode circuits; these solenoids are held by circuit HC including a cam-operated switch HCS, and control decoding and punch-setting mechanism (not shown) which may be as described in Speci. ficatioh 690,170. The outputs of the rightmost four denominations of CR2, Fig. 12, are read out only if they represent pounds, and the corresponding triodes PT3 are therefore controlled by the outputs of' DPS. The read out from the two denominations 10<SP>-1</SP>d, 10<SP>-2</SP>d (hot illustrated in Fig. 13) is controlled by the round-off switch as described below. De-coding farthings and rounding off. A multi-bank round-off switch (not shown) has positions 1-7 corresponding respectively to round-off to nearest, next higher or next lower farthing, to nearest, next higher or next lower penny, and no round-off (punching of decimal fraction). A diode network (Fig. 20, not shown) de-codes the decimal pence registered on the 10<SP>-1</SP>d, 10<SP>-2</SP>d denominations of CR2 to the next lower farthing and energizes a corresponding solenoid (FS). To enable the correct round-off to be obtained predetermined values are added into CR2 where necessary (i.e. for switch positions 1, 2, 4, 5) during the checking, operation prior to read out. Checking. A calculation cycle, Fig: 11A; is followed by a similar checking cycle during which the same calculations are repeated on the complement of the multiplicand set up in CR1 by applying complementary or reversing pulses CP, Fig. 27, to R during the first two addition periods. During the second addition period, a " fugitive one," Fig. 27, is added into CR2, except when a predetermined round-off value is to be added, so that at the end of the checking cycle all denominations of CR2 except 10<SP>-1</SP>d, 10<SP>-2</SP>d should register 0. If a non-zero digit is registered, indicating an error, upon opening of cam-operated error trip switch, ETS, Fig. 13A, a positive potential will be applied through cathode follower CF20 and gate GDCG to triode PT5 which will therefore conduct and energize error relay ETR which cancels the setting of the punches. Over-capacity detection. The punch setting is cancelled also by a relay OCR, Fig. 13A, if the capacity of CR2 may be exceeded or an incorrect registration may be made. The " over-capacity " conditions are detected by gates and a storage trigger circuit (Fig. 23, not shown) and include e.g. the case of the multip