Patent GB-1523653-A (GB)
Title: Electronic switching systems
IPC: H04Q11/04
Filed: 1975-09-04
Abstract: 1523653 Automatic exchange systems CSELTCENTRO STUDI E LABORATORI TELECOMMUNICAZIONI SpA 4 Sept 1975 [4 Sept 1974] 36402/75 Heading H4K In a TDM switching system the data on a plurality of incoming multiplex highways is supermultiplexed, and written cyclically into a memory which is then read acyclically so as to gate individual data items into pairs of buffers associated with a plurality of outgoing highways. The output buffers are paired so that signals may be written into one during a first time slot, these signals then being read out to the highway during the next slot while further signals are being written into the other buffer of a pair. Serial 8 bit PCM is used on the highways whereas 8 bit parallel working obtains within the system. The highways are of 32 channel type and are arranged in groups each of 32 highways. Fig. 1 portrays the overall system. The signals in each incoming highway group g 1 -g n  are supermultiplexed separately II(1-n) and stored in respective group memories RC(1-n). A computer controlled addressing circuit MI reads RC acyclically so as to transfer any data word therein to any one of the output buffers IN(1-n) associated with the outgoing highway groups g<SP>1</SP> 1 -g<SP>1</SP>n. Supermultiplexer, III, (Fig. 2) comprises two portions MX2, M1 and MX3, M2, each for handling half the highways f 1 -f 1,32  in the group g 1 . During each bit time slot, all the highways are scanned and the result recorded in a row of M1 and M2. Consequently by the end of a channel time slot, the full 8 bit PCM word on each of the highways in the group will have been recorded in a respective column of one of the memories M1 and M2. During the last half of the last bit time slot of a channel time slot, the memories are read column by column into eight-wire lines 7, 8 for transfer to a main memory, thereby clearing M1, M2 ready for recording the PCM words of the subsequent time slot. Main memory RC1 (Fig. 3) comprises four portions M3-M6, each of which records information in respect of 8 only of the 32 highways in the incoming group. M3 for example records data in respect of highways f 1,1 -f 1,8 . It is divided into 32 parts corresponding to the 32 channels in a frame of time slots. Each part contains the PCM words relating to highways f 1,1 -f 1,8  transmitted thereto by the supermultiplexer during its corresponding time slot. The memory is written into cyclically. It is addressed by a decoder MX4 that applies address signals over lead 14 to each portion M3-M6 simultaneously. The portions M3, M5 and M4, M6 are written into alternately under control of gates P1-P4 but they are all read-out simultaneously, choice as to which one shall have its output utilized being vested in multiplexer MX5. The main memories RC1-RC n  are read-out acyclically by the computer during time slots pertaining to the outgoing highways but in such a way that the serial data words (parallel bit coding still obtains, of course) are transferred on a cyclic basis into buffers IU. Thus during any one time slot of the outgoing highways (they are all synchronized) the computer reads RC such that the successive data words relate to the channels respectively of the first highway of group g' 1, the first highway of group g<SP>1</SP>2 ... the last highway of group g<SP>1</SP> 32 . Outgoing buffer IU1 (Fig. 4) comprises two portions, each in respect of half the highways f<SP>1</SP> 1,1  -f<SP>1</SP> 1,32  in the outgoing group g<SP>1</SP> 1 . Each portion has two memories M7, M8 and M9, M10. One memory M7 (M9) is written into during one time slot whilst its partner M8 (M10) which was filled during the previous time slot, is being read-out. Each memory contains a parallel coded data word in respect of every highway to which it is assigned, i.e. columns f 1,1 -f 1,16 . During a time slot each column is scanned and its parallel contents i.e. rows, are read out successively into a shift register RS1. The serial bits of each data word are then transferred into a relevant highway buffer in RP prior to transmission along the highway.