Patent GB-986216-A (GB)
Title: Improvements relating to position control arrangements
Inventor: OHLSEN GEOFFREY TURNER
IPC: G05B19/29
Filed: 1963-02-01
Abstract: 986,216. Electric selective signalling; comparators. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Jan. 29, 1964 [Feb. 1, 1963], No. 4308/63. Headings G4H and G4M. In a position control arrangement, each digit of two sets of non-binary (e.g. decimal) digits respectively representing desired and actual position is separately coded in binary form and compared with the corresponding digit of the other set to produce one or the other of two signals according to which of the two digits is the greater and neither signal if the two digits are equal. In the particular embodiment, the said signals from all the comparisons (one per decimal order, details in Fig. 4) go to NOR-gate circuitry EP (Fig. 5) which energizes one of three lines depending on whether the actual position is less than, greater than or equal to the desired position. These lines go to NOR-gate circuity SC (Fig. 6, not shown) to control four output lines to achieve the following operational sequence. Assuming the desired position is beyond the initial actual position, high speed forward travel is produced until the comparators all indicate zero difference when the drive is changed to high speed reverse. The output member thereupon slows down and reverses direction. When the comparators again indicate zero difference the drive is changed to low speed forward travel so the output member slows down and reverses direction to move forward. When the comparators again indicate zero difference, low speed forward drive is terminated and a brake applied (or friction alone relied upon to stop the output member). If the initial actual position is already beyond the desired position, the high forward speed stage is omitted. The signals representing actual position are produced by a set of commutators geared together so that each energizes one out of ten lines to represent one decimal order. The indications on these lines are then coded into binary form. The commutator pertaining to the least significant decimal digit leads its proper position by an amount sufficient to compensate for the non- zero distance that the brake or friction require to bring the output member to rest after the low speed forward drive is terminated. The lengths of the conductive segments of the least significant digit commutator are large enough to ensure that the full low speed is attained before the low speed drive is terminated, except for the case when the comparators indicate zero difference initially when the same function is performed by a delay element M (Fig. 6, not shown). Extra connections from the commutators, controlling a NOR-gate G18 (Fig. 5, not shown) are provided to prevent errors when the desired position is zero, since in this case during overshoot of the desired position the most significant digit commutator for example will register 9. Details of comparison (Figs. 4, 5): NOR-gate circuitry as in Fig. 4 is provided for each decimal order in the two numbers to be compared. Corresponding binary orders are compared in units Cu1 Cu2, Cu3, Cu4 giving outputs which are fed to NOR-gates GP, GN one of which gives a "1" output to indicate which of the two decimal digits is the larger (or both "0" if equal). The highest-order unit Cu receiving non-equal bits fixes the outputs of lower order units, irrespective of their inputs. The outputs PLE, NLE of the gates GP, GN in the Fig. 4 circuit for each of four decimal orders go to circuitry as in Fig. 5 which produces a "1" output on one of lines LP, LN depending on which number is the greater, or on line LZ if they are equal. In Figs. 4, 5, 1 indicates a NOR-gate and 1 an OR-gate. Specifications 954,252 and 978,975 are referred to.