baber/WOPTO huggingface dataset:
Patent TW-I239077-B (TW)
Title: NAND flash memory cell row and method of forming the same
Inventor: CHEN SHIH-CHANG
IPC: H01L21/8247
Filed: 2003-10-23
Granted: 2005-09-01
Abstract: A NAND flash memory cell row and method of forming the same. The memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, tunnel oxide, doping regions, and source/drain regions. The first stacked gate structure has an erase gate dielectric layer, a erase gate, and a cap layer. The second stacked gate structure has select gate dielectric layer, a select gate, and a cap layer. The control gates are located between the first stacked gate structures and between the second stacked gate structures and the first stacked gate structures near thereof. The floating gates are located between the control gates and the substrate, and it has a concave surface with pointed angle-shaped edge. The inter-gate dielectric layer is located between the control and floating gates. The tunnel oxide is located between the floating gates and the substrate. Furthermore, the doping regions are on the first stacked gate structure, and the source/drain regions are in the exposed substrate except the second stacked gate structures.
Patent TW-I222670-B (TW)
Title: Immersion lithography process and mask layer structure applied in the same
Inventor: CHANG VENCENT
IPC: G03F7/11
Filed: 2003-12-03
Granted: 2004-10-21
Abstract: An immersion lithography process is described as follows. A photoresist layer and a barrier layer are sequentially formed on a material layer, and then an immersion exposure step is performed to define an exposed portion and an unexposed portion in the photoresist layer. A solubilization step is conducted to solubilize the barrier layer on the exposed portion of the photoresist layer, and then a development step is conducted to remove the exposed portion of the photoresist layer and the barrier layer thereon. Since the photoresist layer is covered with the barrier layer, the chemicals in the photoresist layer do not diffuse into the immersion liquid to cause contamination. The barrier layer can be patterned simultaneously in the development step, and no extra step is required to remove the barrier layer. Therefore, the whole lithography process is not complicated.
Patent TW-I228764-B (TW)
Title: Nanoimprint method with uniform pressurization and method for protecting mold thereof
Inventor: HO YU-LUN
IPC: H01L21/30
Filed: 2003-12-31
Granted: 2005-03-01
Abstract: The present invention relates to a nanoimprint method with uniform pressurization and a method for protecting a mold thereof. The invented method is applied on a nanoimprint device with uniform pressurization, and comprises: setting a power source of the nanoimprint device at a position control mode in order to drive an external mask to advance, and enabling the external mask to drive a first carrying unit loaded with an imprint mold to advance towards a second carrying unit loaded with a moldable material layer; switching the power source to a pressure control mode when the imprint mold contacts the moldable material layer; enabling the power source to apply a pressure on the external mask so that the pressure transmits from the external mask to the imprint mold and the moldable material layer; enabling the power source to maintain at a pressure maintenance mode when the pressure reaches a predetermined value; maintaining the pressure maintenance mode for a specified period of time, and then enabling the power source to drive the external mask to advance in a reverse direction so that the imprint mold and the moldable material layer separate from each other and a mold release step is completed, thereby achieving an accurate control of speed, pressure and location with multiple stages, an uniform imprint control and an imprint depth control.
Patent TW-I249752-B (TW)
Title: Symmetrical inductor
Inventor: GAU JING-HORNG
IPC: H01F37/00
Filed: 2004-02-05
Granted: 2006-02-21
Abstract: A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line; and a fourth contact plug for connecting the second conductive segment with a second end of the fourth conductive segment, the fourth contact plug and the second contact plug being symmetrical to the line.
Patent TW-I249686-B (TW)
Title: Pattern-match method for detecting network intrusion
Inventor: HUANG NEN-FU
IPC: G06F17/22
Filed: 2004-03-17
Granted: 2006-02-21
Abstract: A pattern-match method for detecting network intrusion is described. The method includes the following steps. First, a W bytes string is taken as the entry address in a skip distance table and a skip distance is looked up in the table. Next, a rule hashing table is established from the patterns needing to be compared. Next, the W bytes string is searched in the rule hashing table and the search result corresponding to each pattern is returned. Next, the search result corresponding to each pattern is recorded in a rule status table through a MATCH flag.
Patent TW-I254321-B (TW)
Title: Method and device to disassemble a control-element of a boiling-water reactor
Inventor: HUMMEL WOLFGANG
IPC: G21C19/36
Filed: 2004-03-22
Granted: 2006-05-01
Abstract: This invention relates a method to disassemble a control-element (6) of a boiling-water reactor, in which two oppositely located control-element-blades (6a, c) are respectively separated from the other two control-element-blades (6b, d) along a cutting-line (S), which extends in the longitudinal direction and arranged in the vicinity of the longitudinal middle-axis (A), with a rolling-cutting method. In addition, this invention is also related to a device to perform such a method.
Patent TW-I258753-B (TW)
Title: Optical recording apparatus and related method
Inventor: CHEN HONG-CHING
IPC: G11B20/10
Filed: 2004-04-30
Granted: 2006-07-21
Abstract: The present invention discloses an optical recording apparatus and related method. The disclosed optical recording apparatus is for recording a plurality of information units on an optical storage medium in the form of a first type pattern and a second type pattern. Each of the information units contains a long run-length sync pattern. The optical recording apparatus contains a pickup head and a sync pattern select unit. The pickup head is for outputting a laser light onto the optical storage medium to record the plurality of information units on the optical storage medium. The sync pattern select unit is for selecting the type of the long run-length sync patterns. When selecting the type of at least one long run-length sync pattern, if the first type pattern with a run length longer than a predetermined length does not appear for a time longer than a predetermined threshold, the sync pattern select unit select the long run-length sync pattern of the at least one information unit as the first type pattern.
Patent TW-I260951-B (TW)
Title: Single-stage high power factor electronic ballast
Inventor: LIN RAY-LEE
IPC: H05B41/14
Filed: 2004-06-03
Granted: 2006-08-21
Abstract: The present invention discloses a single-stage high power factor electronic ballast comprising an electromagnetic interference (EMI) filter, a power factor correction (PFC) network and a resonant inverter. The PFC network comprises a PFC inductance and a PFC capacitor. The PFC inductance, electrically connected to the voltage source, saves or releases the power supplied by the voltage source. The PFC capacitor, electrically connected to the PFC inductance, saves or releases the power output from the PFC inductance. The resonant inverter, connected to the output of the PFC network, provides the resonant action associated with the load of the electronic ballast. Besides, the PFC inductance and the PFC capacitor can further save or release the power output from the resonant inverter. Furthermore, continuous current mode (CCM) used in the PFC can reduce EMI issues, achieve high power factor and lower conduction loss.
Patent TW-I340570-B (TW)
Title: Distributed dynamic channel selection in a communication network
Inventor: HERSHEY STEPHEN P
IPC: H04W16/10
Filed: 2004-06-11
Granted: 2011-04-11
Abstract: In one embodiment, a first node among a number of distributed nodes capable of forming or reforming a communication network between the nodes, each of the nodes including functionally similar components for forming or reforming such a network, includes a memory for storing values for variables for the node. The first node also includes one or more components collectively operable to: (1) spontaneously and independent of a centralized controller associated with the network, transmit a probe message to one or more of the other nodes for purposes of forming or reforming a network; (2) receive a probe message from a second node, the probe message including values for the variables for the second node; (3) compare the values for the variables for the first node to the values for the variables for the second node within the probe message to determine, independent of a centralized controller associated with the network, whether the first node should set itself to a new channel; and (4) if so, set the first node to the new channel.
Patent TW-I248099-B (TW)
Title: Chip-type solid electrolytic capacitor and method of producing the same
Inventor: KIDA FUMIO
IPC: H01G9/15
Filed: 2004-06-14
Granted: 2006-01-21
Abstract: A chip-type solid electrolytic capacitor comprises capacitor elements (1a, 1c). A cathode terminal (3a) comprising a plate-like conductor is interposed between cathode layers of the capacitor elements. The capacitor elements are bonded to each other by a bonding agent (5) such as a solder or a conductive adhesive. The cathode terminal is provided with a through hole (4a) formed at a portion to be brought into contact with each of the capacitor elements. Bonding surfaces of the capacitor elements are directly connected at the through hole.
Patent TW-I242977-B (TW)
Title: Voice calendar system and receiving and processing method of information
Inventor: HU MENG-SUNG
IPC: H04M11/00
Filed: 2004-06-30
Granted: 2005-11-01
Abstract: The present invention relates to a voice calendar system and receiving and processing method of information for processing the signal transmission between the Internet and telecommunication network, the voice calendar system comprises: a computer telephony integration (CTI) server connected to a telecommunication network for processing the telephone response of the telecommunication network and recording the telephone answer; an Internet server for processing the events in the calendar on the Internet, the events in the calendar comprises the informed message and setting time. The Internet sever responds to the setting time so as to inform the computer telephony integration sever to generate a telephone answer and play the informed message; and a communication network connected to the computer telephony integration sever and the Internet sever.
Patent TW-I289677-B (TW)
Title: Method and apparatus for testing a bridge circuit
Inventor: YEH BI-YUN
IPC: G01R31/28
Filed: 2004-08-20
Granted: 2007-11-11
Abstract: A method and an apparatus for testing a bridge circuit. The method includes inputting a first test clock to a first conversion unit for triggering the first conversion unit to transfer a test data to a second conversion unit according to rising edges of the first test clock, inputting a second test clock to the second conversion unit for triggering the second conversion unit to output an output data according to falling edges of the second test clock, and controlling the first test clock and the second test clock so that the rising edges of the second test clock are not synchronized with the rising edges of the first test clock. A frequency of the first test clock is an even multiple of a frequency of the second test clock.
Patent TW-I255124-B (TW)
Title: System and method of managing users based on IP
Inventor: CHA SHIH-CHAO
IPC: H04L9/32
Filed: 2004-09-03
Granted: 2006-05-11
Abstract: A system and method of managing user based on IP comprises of a client, an identification gate, a managing user service device, a supervisory control apparatus, and a server. A user sends out a request and a username from the client to access a network. When the identification gate receives the username, it compares the username with a user data of the managing user service device to confirm the authority of the user. If the user has the authority for accessing network, the identification gate lets the user access the network, and stores up an IP address of the client into the user data of the managing user service device. When the client sends out the request of access an application program, the supervisory control apparatus receives the request and the IP address of the client. It compares the IP address with the user data to confirm the user has the authority for accessing the application program. If the user has, the supervisory control apparatus lets the user access the application program of the server.
Patent TW-I354696-B (TW)
Inventor: TSUYOSHI MATSUDA
IPC: H01L21/321
Filed: 2004-09-30
Granted: 2011-12-21
Abstract: A first polishing composition is used in chemical mechanical polishing for removing one part of the portion of a conductive layer (15) positioned outside a trench (13). A second polishing composition is used in chemical mechanical polishing for removing the remaining part of the portion of a conductive layer positioned outside the trench and the portion of a barrier layer (14) positioned outside the trench. The first polishing composition contains a specific surfactant, a silicon oxide, a carboxylic acid, an anticorrosive, an oxidizing agent, and water. The second polishing composition contains colloidal silica, an acid, an anticorrosive, and a completely saponified polyvinyl alcohol.
Patent TW-I249826-B (TW)
Title: Connecting device using spiral contact
Inventor: YOSHIDA MAKOTO
IPC: G01R31/26
Filed: 2004-10-08
Granted: 2006-02-21
Abstract: The present invention provides a connection device which uses a spiral contactor which protects a deformation of the spiral contactor and a dust infiltration into the spiral contactor. An external connecting part 1a of an electronic component 1 and a first spiral contactor 40A arranged in an adapter board 30 are contacted via a small hole 21 defined in a protective sheet 20, when the electronic component 1 is mounted on a loading part 11A. Deformation and dust infiltration of the spiral contactor are protected, since the protective sheet 20, mounted on an upper part of the relaying substrate 30, protects the adapter board 30.
Patent TW-I257714-B (TW)
Title: Light-emitting device using multilayer composite metal plated layer as flip-chip electrode
Inventor: LIU CHI-WEI
IPC: H01L33/32
Filed: 2004-10-20
Granted: 2006-07-01
Abstract: The present invention relates to a light-emitting device using multilayer composite metal plated layer as flip-chip electrode, and more particularly to a LED using a transparent conducting layer and a metal with high index of reflection as a flip-chip electrode to enhance light-emitting efficiency. The device includes a transparent substrate; and a layer of group III nitride compound semiconductor die structure laminated on the transparent substrate and bonded with an interposer in a submount by flip-chip means. The device is characterized in having a flip-chip electrode composed of multilayer composite metal plated layers containing a current-spreading transparent conducting layer formed on a surface of a second type semiconductor layer; a metal reflective layer with high index of reflection formed on a surface of the transparent conducting layer; a barrier layer preventing metal diffusion formed on a surface of the metal reflective layer; and a bonding layer connected with an interposer and formed on a surface of the barrier layer. Furthermore, the device further includes an ohmic contact layer formed on the transparent conducting layer and an insulating passivation layer coated on the surrounding sides of the die structure to insulate a p/n interface and prevent generation of current leakage.
Patent TW-I263883-B (TW)
Title: Direct current linear voltage regulator circuit of motherboard
Inventor: JIANG WU
IPC: G06F1/26
Filed: 2004-11-26
Granted: 2006-10-11
Abstract: A direct current linear voltage regulator circuit for use with the motherboard according to the present invention is disclosed. The direct current linear voltage regulator circuit includes a regulating circuit having a regulating terminal, an input terminal and an output terminal disposed thereat. The input terminal is provided to receive a voltage from a source supply. The output terminal is connected to the load and in feedback relationship with the regulating terminal, thus resulting in a regulating voltage generated at the output terminal and, through the load, input into the regulating terminal. The regulating terminal is connected to a base of a transistor. An emitter of the transistor is connected to ground. A collector of the transistor is connected to an additional driving voltage via a resistor. With such arrangement, the direct current linear voltage regulator circuit of the present invention is one capable of carrying a heavier load over the prior art with allowing for the expanded voltage range from the source supply.
Patent TW-I291638-B (TW)
Title: System and method for providing backup service using a virtual backup service path
Inventor: LIN TZU-HOW
IPC: G06F12/16
Filed: 2004-12-07
Granted: 2007-12-21
Abstract: Provided are a system and method for using a plurality of virtual backup service paths to dynamically switch between storage devices based on a plurality of scenarios. In one example, multiple backup service groups are defined. Multiple scenarios that each reference at least one virtual backup service path are also defined. Each virtual backup service path may be defined by at least one network address identifying a storage device. One of the scenarios is selected based on a service level of one or more storage devices, and the virtual backup service path identified by the selected scenario is chosen as a backup destination for at lest one of the service groups.
Patent TW-I261839-B (TW)
Title: A method for programming multi-level nitride read-only memory cells
Inventor: LUNG HSIANG-LAN
IPC: G11C16/02
Filed: 2005-01-03
Granted: 2006-09-11
Abstract: A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride read-only memory cell are programmed in a time order according to their descending Vt values. For a nitride read-only memory cell that, in an erased state, exhibits a high Vt value, a data region that is to be programmed to a lowest Vt value is programmed first with remaining data regions programmed in a time order according to their ascending Vt values.
Patent TW-I265308-B (TW)
Title: Mirror device with anti-reflective layer and method for manufacturing the same
Inventor: CHEN WEI-HSIAO
IPC: G02B1/11
Filed: 2005-01-13
Granted: 2006-11-01
Abstract: The invention relates to a mirror device with anti-reflective layer and method for manufacturing the same. The method of the invention comprises: (a) forming an anti-reflective metal film on a first surface of a mirror material to be a mirror device; (b) defining a plurality of mirror units from the mirror device, each mirror unit having a mirror layer and an anti-reflective metal film unit, the anti-reflective metal film unit formed on a first surface of the mirror layer; and (c) defining an anti-reflective metal layer from the anti-reflective metal film unit, the anti-reflective metal layer formed on edges of the first surface of the mirror layer. According to the invention, the anti-reflective metal layer on the mirror layer can shield a bright area caused by fringe effect so as to decrease the bad influence of the fringe effect. In manufacture, the method of the invention follows the semiconductor manufacturing process, and has high precision and simple process.
Patent TW-I291813-B (TW)
Title: Method for detecting an error place, error detecting circuit using such method, error correction circuit, and reproduction device
Inventor: OKAMOTO MIYUKI
IPC: H03M13/00
Filed: 2005-03-04
Granted: 2007-12-21
Abstract: This invention provides a method for detecting a burst error contained in a data signal. A read unit (222) reads a data signal. A first estimating unit (226) estimates an error position accordingly to a BIS code contained in the data signal, and stores the estimated error position in a position memory unit (230). A second estimating unit (228) estimates an error position according to the characteristics of a bit series adjoining to a BIS code, and stores the detected error position in a position memory unit (230). A correcting unit (232) specifies a disappearing position according to the error positions stored in the error position memory unit (230) and performs a disappearing correction to the specified disappearing position. By estimating the error position according to the characteristics of the bit series adjoining to the BIS code in addition to estimating the error position according to the BIS code, a burst error detection miss can be suppressed.
Patent TW-I279761-B (TW)
Title: Driving circuit for liquid crystal device
Inventor: KAWAKAMI TAKUYA
IPC: G02F1/133
Filed: 2005-03-21
Granted: 2007-04-21
Abstract: The invention provides a driving circuit for a liquid crystal device having a reduced number of transistor elements by sharing transistors having identical logics among adjacent decoders. The driving circuit for a liquid crystal device capable of carrying out gradation display by applying gradation voltage corresponding to a display data to a liquid crystal element comprises a decoder circuit portion composed of a dynamic circuit for selecting the gradation voltage, the decoder circuit portion having a number of transistor elements 4 reduced by sharing transistors with identical logics constituting adjacent decoders. The voltage level corresponding to the display data causes all the analog switches to be set to an off status, so as to prevent overlap of output voltage during a timing of transition of the analog switch to the off status and a timing by which the analog switch is turned on according to a subsequent display data.
Patent TW-I257331-B (TW)
Title: Pallet formed by recycles
Inventor: HUANG JR-SHIAN
IPC: B09B3/00
Filed: 2005-05-05
Granted: 2006-07-01
Abstract: The invention is a kind of pallet formed by recycles. It is made through recycle process by discarded low-price plastic bottles and cans, through a crusher to crush these bottles and cans to form recycled plastic material, which is crushed into a volume for next process to form, then through a press forming machine to proceed process in a press forming way that finally produces pallet, such that it can greatly reduce the procurement cost for pallet and achieve the effect of environmental protection for recycles.