Patent GB-1136522-A (GB)
Title: Arithmetic apparatus
IPC: G06F7/52
Filed: 1967-07-27
Abstract: 1,136,522. Arithmetic circuits. INTERNATIONAL BUSINESS MACHINES CORP. 27 July, 1967 [31 Aug., 1966], No. 34495/67. Heading G4A. An adder loop is fed with its own output and the output of an adder tree simultaneously. Binary multiplication.-In Fig. 1, successive groups of 13 parallel bits of the multiplier in a register 31, each group having a bit in common with the or each adjacent group, are taken, low order group first, and decoded at 32. In the decoding, six 3-bit sub-groups of the group, each sub-group having a bit in common with the or each adjacent sub-group, are decoded separately and the results latched at 32 to select multiples of the multiplicand which is held in a register 30, as follows. Each of the 6 sub-groups causes the multiplicand to be entered into a respective one of 6 latch blocks 24-29 shifted n or n + 1 bit positions to low order in true or complement form, or causes zeroes to be entered. Here n is the bit position within the group of the highest order bit of the sub-group counting from high order and taking 0 as the position of the highest order bit in the group. The parallel outputs of the latch blocks 24-29 are applied as shown to an adder tree 21 consisting of carry-save adders CSA A, CSA B, CSA C, CSA D producing plural-bit carry and sum outputs C, S. The outputs of CSA C are latched therein and a latch block 43 is provided. The C and S outputs from the bottom of the tree 21 are passed to an adder loop 22 comprising carry-save adders CSA E and CSA F, both with output latching, and a latch block 51. The C and S outputs from the bottom of the tree 22 are passed back to its input with a 12-bit shift to low order, until the end of the multiplication when a carry-propagate adder 23 obtains the final answer. If the length of the multiplier is such that there is only one group, the adder loop 22 is by-passed, and the tree output fed straight to adder 23. Fig. 2 shows the Fig. 1 system used for multiplying the fraction parts of 64-bit floating-point operands to be multiplied. The multiplicand and multiplier register 30, 31 are each capable of holding two operands and are fed from registers 60, 61. Regarding the fractions as composed of 4-bit base-16 digits, the fractions are initially normalized, so that the highest order base-16 digit contains a 1 bit, by a digit shifter 68. The number of digit positions shifted is specified in a shift register 69 to modify exponent addition at 67. Multiplication of the normalized fractions occurs in adder tree 21, adder loop 22 and carry propagate adder 23 as before but since only half the double-length product produced is to be retained, a spill adder 71 at the end produce s  an extra carry at 72 into the carry propagate adder 23, if necessary, from the bits dropped. A post shift decoder 74 causes a post-shifter 75 to normalize the result in register 73. Timing signals enabling the decoder latches at 32 (Fig. 1), to be set are also successively delayed to enable the other levels of latches to be set in turn. Since there are four such other levels viz. at (a) 24-29, (b) 42, 43, (c) 50, 51, (d) 52, four sets of multiplicand multiples (or signals derived from them) can be proceeding through the Fig. 1 system at a time. Extra delays are inserted to compensate for differing wiring delays for the timing signals to a given level of latches. AND-INVERT logic for the Fig. 1 system is shown and described briefly. Binary division.-Floating-point binary division using the Fig. 2 system is described briefly, Specification 1,136,523 being referred to for more details.