Patent GB-1366401-A (GB)
Title: Three state logic device with appl'ions
IPC: H03K19/00
Filed: 1972-03-15
Abstract: 1366401 Logic circuitry BURROUGHS CORP 15 March 1972 [15 March 1971] 12004/72 Heading G4A [Also in Divisions H3 and H4] An electronic circuit 1 (Fig. 1) comprises two cross coupled NOR gates connected to operate as an RS flip-flop when a binary "1" is applied to one of the gates and a binary "0" is applied to the other gate and to hold its state when binary zeros are subsequently applied to both the gates. The application of binary ones to both the gates results in binary zeros at both the outputs. The circuit may be used in a transmission system in which there is a circuit (13...19, Fig. 2, not shown) as in Fig. 1 for each bit of parallel coded binary data to be transmitted. When no data is to be transmitted the inverted output of a strobe unit (38) keeps both inputs to each circuit (13...19) at "1" so that no output signals are applied to a detector (16). When data is available the inverted strobe output signal becomes "0" so that a binary bit from data source (30) is applied together with its complement to each circuit. This results in a "1" output on one of the outputs of each circuit, so that the detector (16), which may be an AND gate enables a gate (15) to transmit the data to, e.g. a random access memory to automatically start the memory cycle. The transmission system may be used in a computer system in which any of a plurality of processes (50-52, Fig. 4, not shown) or multi-plexors (53-55) requires access to one of a plurality of memory modules (56-64) controlled by memory control units (65-67). If, for example, the highest and next highest priority processors (50, 51) require access to the same memory module (e.g. module 61) they apply the appropriate address signal to their associated address compare circuits 77, 87 (Fig. 5A) in each control unit (there being one such circuit for each processor in each memory control unit). The compare circuit 77 of the second control circuit (66, Fig. 4, not shown) then enables AND gate 78 (associated with memory 61) the "request recognized" output from which is fed both via gate 81 to a flip-flop 82 providing an "access granted" signal and via an inverter 83 to inhibit AND gates such as gate 91 associated with lower priority processors so that flip-flop 92 associated with processor 51 is held in its reset state and the processor is, consequently, not granted access. Flip-flop 82 is connected to one input of read and write modules 71, 72 associated with the memory module 61 to permit transfer of information to or from the processor 50 to or from the memory module 61. All the outputs of flip-flops 82, 92 ... are connected to AND gate 100 so that input gates 81, 91 ... to flipflops 82, 92 ... are only primed when none of the processors are using the memory. The output of flip-flop 82 is also connected to prime AND gates 123, 126 (Fig. 5C) (associated with processor 50) in each of 14 address circuits 70 (there being a set of 14 address circuits for each memory). The 14 bit byte representing the address desired by processor 50 in module 61 is consequently fed by leads 73 (together with the inverse signal on leads 74) via AND gates 113, 114 ... 116 (Fig. 5B), enabled by the reset output of bi-stable 112 when the memory is idle, to 14 flip-flops 105, 106 each similar to the circuit of Fig. 1. The outputs from the flipflops are connected to memory 103. The set and reset outputs of each flip-flop circuit are connected together as one input to an AND gate 108 which when enabled triggers flip-flop 112 to inhibit the gates 113, 114 ... 116 so that the flip-flops hold their state until the flip-flop 112 is reset at the end of the memory cycle.