Patent SG-11201810111U-A (SG)
Title: Parity for instruction packets
Inventor: PLONDKE ERICH JAMES
IPC: G06F11/10
Filed: 2017-06-02
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , 111111111111 0 REHR 010 11111 0 01 01111111 010 1111110 1E110 111 011111 Organization International Bureau (10) International Publication Number 03 (43) International Publication Date .....•\"\"- WO 2017/222784 Al 28 December 2017 (28.12.2017) WIP0 I PCT (51) International Patent Classification: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, GOOF 11/10 (2006.01) CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (21) International Application Number: DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, PCT/US2017/035713 HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, (22) International Filing Date: MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, 02 June 2017 (02.06.2017) PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, (25) Filing Language: English SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (26) Publication Language: English (84) Designated States (unless otherwise indicated, for every (30) Priority Data: kind of regional protection available): ARIPO (BW, GH, 15/192,981 24 June 2016 (24.06.2016) US GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, (71) Applicant: QUALCOMM INCORPORATED [US/US]; TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, ATTN: International IP Administration, 5775 Morehouse EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, Drive, San Diego, California 92121-1714 (US). MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, (72) Inventor: PLONDKE, Erich James; QUALCOMM IN- TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, CORPORATED, 5775 Morehouse Drive, San Diego, Cali- KM, ML, MR, NE, SN, TD, TG). fornia 92121-1714 (US). Declarations under Rule 4.17: (74) Agent: CICCOZZI, John L. et al.; Muncy, Geissler, Olds — as to applicant's entitlement to apply for and be granted a & Lowe, P.C., 4000 Legato Road, Suite 310, Fairfax, Vir- patent (Rule 4.17(i)) ginia 22033 (US). — as to the applicant's entitlement to claim the priority of the =_ (81) Designated States (unless otherwise indicated, for every earlier application (Rule 4.17(iii)) — kind of national protection available): AE, AG, AL, AM, (54) Title: PARITY FOR INSTRUCTION PACKETS = (57) : Systems and method of error checking for instructions method of \ 1 -I50 error checking for instructions include an assembler for creating an instruction = = 1 -156 M EMORY GT N OR PROCESSOR 1- 152 packet with one or more instructions, determining if a parity of the instruction if instruction pack- = ORS ASSI 1110 I R packet matches a predesignated parity, and the parity of the = — I 4 et does not match the predesignated parity, using a bit of the instruction packet = = to change parity of the instruction packet to match the predesignated parity. The instruction packet with the predesignated parity is stored in a memory, and may ,408 - INSTRUCTION C 1CTIE eventually be retrieved by a processor for execution. If there is an error in the in- struction packet retrieved from the memory, the error is detected based on cam- paring the parity of the instruction packet to the predesignated parity. = = = 102a -/ 10212 1 102a\" ) 102d -1 — = —104 1 -110 — PROCESSOR ,.-114 11 P kRITY i CHECK t H t f 7r .. .... ,-112 G C IN el F XECLTT N B PIPELIN el N --.... It 11 Et1E42 1 B A l FIG. I © N C [Continued on next page] WO 2017/222784 Al MIDEDIMOMOIDEIROIDEMODIOHOHOINIDEMMOVOIMIE Published: — with international search report (Art. 21(3)) — before the expiration of the time limit for amending the claims and to be republished in the event amendments (Rule 48.2(h)) of receipt of