Patent ES-8601514-A1 (ES)
Title: Vector data processing system for indirect address instructions.
IPC: G06F17/16
Filed: 1984-09-25
Abstract: The vector data processing system comprises at least an A-access pipeline and a B-access pipeline between a main storage unit and vector registers. A write port (WA) and a read port (RA) selectively connected to the vector registers are associated with the A-access pipeline and a write port (WB) and a read port (RB) selectively connected to the vector registers are associated with the B-access pipeline. An additional read port (IA) is linked between the read port of the B-access pipeline and the address input side of the A-access pipeline. - When an indirect address load/store instruction is carried out for the A-access pipeline, an indirect address is generated from the vector registers through the read port of the B-access pipeline and the additional read port. It is therefore unnecessary to connect the additional read port directly to the vector registers. (Dwg.3/11) EPAB- EP-138451 B The vector data processing system comprises at least an A-access pipeline and a B-access pipeline between a main storage unit and vector registers. A write port (WA) and a read port (RA) selectively connected to the vector registers are associated with the A-access pipeline and a write port (WB) and a read port (RB) selectively connected to the vector registers are associated with the B-access pipeline. An additional read port (IA) is linked between the read port of the B-access pipeline and the address input side of the A-access pipeline. - When an indirect address load/store instruction is carried out for the A-access pipeline, an indirect address is generated from the vector registers through the read port of the B-access pipeline and the additional read port. It is therefore unnecessary to connect the additional read port directly to the vector registers.  (38pp Dwg.No.3/11) - EP-138451 B A vector data processing system  a mian storage unit (4), a plurality of vector registers (21), each including a plruality of elements for storing data; a plurality of data and address transmission means (27, 28), linked between said main storage unit (4) and said vector registers (21), for carrying out data transmission therebetween; and control means (29), for controlling the data transmission process from/to said main storage (4) based on indirect addressing; characterised in that; each of said vector registers (21) is divided into a plurality of independently accessible parts (BANK NO. 0 to BANK No.7); said data and address transmission means comprise at least first (27) and second (28) access pipelines (A, B) each comprising an address pipeline (AP-A, AP-B), data pipeline (DP-A, DP-B) and control pipeline (CP-A, CP-B); a plurality of write ports (WA, WB) are provided, each connected to one of said access pipelines (27, 28) and selectively connected to one of said ports of said vector registers (21); a plruality of read ports (RA, RB) are provided, each connected to one of said access pipelines (27, 28), and selectively connected to one of said ports of said vector registers (21); at least one indirect address read port (1A) is provided, linked between an address input side of said first (27) access pipeline and one (RB) of said read ports conencted to said second (28) access pipeline; and in that said control means  (29) is connected to said access pipelines (27, 28), said write ports (WA, WB), said read ports (RA, RB), and said indirect address read port (1A), for transmitting an indirect address from said vector registers (21) via said indierct address read port (1A) and said first (27) access pipeline to said main storage unit (4) and for transmitting data through said first (27) access pipeline, when receiving an indirect address load/store instruction, without operating said second (28) access pipeline. (25pp) USAB- US4665479 A A vector data processing system comprises a main storage unit and several vector registers each including elements for storing data. The vector registers further comprise interleaved banks. Several access pipelines, linked between the main storage unit and the vector registers, carry out data transmission between them. Write ports are each connected to one of the access pipelines and selectively to any one bank of the vector registers. Read ports are each connected to one of the access pipelines, and selectively to any one bank of the vector registers. An indirect address read port is linked between a first one of the access pipelines and the one of the read ports connected to a second one of the access pipelines. - A control is connected to the access pipelines, the main storage unit, the wirte ports, the read ports, and the indirect address read port, for transmitting an indirect address from the vector registers via the indirect address read port and the first access pipeline to the main storage unit and for transmitting data through the first access pipeline, when receiving an indirect address load/store instruction.