Patent ES-357982-A1 (ES)
Title: Turn off method and circuit for liquid crystal display element
IPC: G02F1/137
Filed: 1968-09-10
Abstract: To reduce the light scattering produced by a nematic liquid crystal display element and thus return the element quickly to its transparent state after it has been excited, the domains of the liquid crystal element are aligned, the alignment being done in such a manner that appreciable ion transit through the element is not caused. In Fig. 6 the liquid crystal is represented by non-linear resistor 16 in shunt with capacitor 18, the crystal being excited by applying a pulse 24 thereto causing capacitor 18 to charge. The capacitor retains its charge for a reasonable time interval to permit dynamic scattering to take place, diode 21 permitting such storage by preventing the capacitor discharging through the source of pulses 24, i.e. causing it to discharge through the liquid crystal itself represented by resistor 16. It is found that the liquid crystal still scatters light a considerable amount even when the voltage across the liquid crystal cell has decreased to zero. To reduce this light scattering, i.e. "turn off" the liquid crystal cell a P-type insulated gate field-effect transistor 26 is connected at its drain electrode 28 to the cell so that the source-drain conduction channel couples an erase pulse generator 30 to the cell, a gate pulse generator 34 of low internal impedance being connected to the gate electrode 36 of the transistor. In operation an erase pulse 40, Fig. 7, is applied to the source electrode of the transistor 26 concurrently with application of a gate pulse 42 to the gate electrode 36, a short interval before a following write pulse 20a occurs (one television frame after the write pulse 20, pulses 20 and 20a being equivalent to one television line time for a television type display-see later). The erase pulse is of high amplitude, i.e. greater than the domain alignment voltage threshold of the cell. The gate pulse is of greater duration than the erase pulse and reduces the impedance of the source-to-drain conduction path. Erase pulse 40 causes a high electric field to be produced across the cell which aligns the large domains, but the pulse is of such short duration that ion current does not flow through the crystal. After the erase pulse has terminated, the gate pulse is still present so as to provide a low impedance path from capacitor 18 through the transistor 26 and the low internal impedance of the erase pulse generator 30 to ground, thus eliminating ion-transit-induced turbulence. The liquid crystal cells may be arranged in a matrix to form a television type display, and in every frame interval a row of cells is simultaneously " addressed " by means of a row pulse, while pulses having amplitudes corresponding to the video information of respective elements of the row are applied to the cells. Erase circuits are connected to each cell, a single erase and gate pulse generator being used for each row of cells, Fig. 9 (not shown). In a further matrix arrangement, Figs. 10-12 (not shown), each display cell comprises a storage element, e.g. a capacitor, coupled across a nematic liquid crystal, and a fast reset circuit is connected across the crystal and capacitor of each cell for applying a fast reset pulse to the crystal through the capacitor.