baber/WOPTO huggingface dataset:
Patent TW-496069-B (TW)
Title: Control interface protocol for telephone sets for a satellite telephone system
Inventor: EDGAR CLEMENT B III
IPC: H04L1/18
Filed: 2001-01-04
Granted: 2002-07-21
Abstract: A control interface protocol governs communications in a satellite telephone system. The satellite telephone system comprises a radio antenna unit (RAU) and a plurality of desksets connected to the RAU. An interface bus connects the desksets to the RAU. The RAU and the desksets communicate with each other by packets. Each packet comprises a start of header (SOH) byte, an address number (ADDR) byte, a command (CMD) byte, an argument (ARG) and a block check character (BCC). The ADDR byte comprises a source and a destination address of the packet. All packets, except negative acknowledgment (NAK) packets from the desksets, are acknowledged by the RAU. The packets originating from the desksets are tagged with an address of the desksets. A packet to a specific deskset includes a destination address. A packet originating from the RAU to all desksets includes a first default address. A packet originating from the RAU to a deskset that does not have an address includes a second default address.
Patent TW-483156-B (TW)
Title: Structure of a material/noble metal substrate laminate and semiconductor memory element
Inventor: DUNCOMBE PETER RICHARD
IPC: C23C8/12
Filed: 1998-07-30
Granted: 2002-04-11
Abstract: The present invention discloses a method for forming a noble meat oxide film layer on a noble metal substrate by exposing a surface of the noble metal substrate to an oxygen-containing energy source. The oxygen-containing energy source may be chosen from a high-density plasma, a microwave plasma, a RF plasma and an ion bombardment produced by oxygen-containing ion beams or combinations thereof, with or without separatedly controllable substrate bias. The noble metal can be at least one member selected from Pt, Ir, Ag, Au, Ru, Pd, Os and Rh. The noble metal may also be formed as a noble metal alloy containing at least one of those noble metals. The invention also discloses a noble metal oxide film layer that is formed by exposing the surface of a noble metal substrate to an oxygen-containing plasma. The oxide-containing film layer formed typically has a thickness between about 0.4 and 10 nm, although lower and higher thickness may be obtained with variations in treatment conditions. The invention also discloses a novel method for depositing a high-permittivity material on a noble metal substrate by first exposing a top surface of a noble metal substrate to an oxygen-containing energy source for a sufficient length of time until an interface-enhancing layer is formed and then depositing a high-permittivity material on top of the noble metal substrate sandwiching the oxygen-containing layer. The invention also discloses a novel method for forming a DRAM capacitor by first exposing a top surface of a first electrode that is formed of a first noble metal material to an oxygen-containing energy source for a sufficient length of time such that an interface-enhancing layer is formed, and then depositing a high-permittivity material on top of the first electrode sandwiching the interface-enhancing layer. A final electrode is then formed with a second noble metal material on top of the high-permittivity dielectric material layer. The capacitor is formed on a pre-processed semiconductor substrate which has a conductive contact plug formed therein for providing electrical communication with the first electrode.
Patent TW-505953-B (TW)
Title: Dilute remote plasma clean
Inventor: BALISH KENNETH E
IPC: C23C16/44
Filed: 2001-02-08
Granted: 2002-10-11
Abstract: A method and apparatus for enhancing the etch characteristics of a plasma formed in a remote plasma generator. A plasma formed in a remote plasma generator (27) is flown through a tube (62) to a plenum (60) where it is diluted to form a plasma mixture before flowing the plasma mixture into a processing chamber (15). The plasma mixture is used to clean deposits from the interior surfaces of the processing chamber, or can be used to perform an etch step on a process wafer within the processing chamber. In one embodiment, a plasma formed from NF3 is diluted with N2 to etch residue from the surfaces of a processing chamber used to deposit silicon oxide glass. Diluting the plasma increased the etching rate and made the etching rate more uniform across the diameter of the processing chamber.
Patent TW-I242073-B (TW)
Title: Method for inspecting gaps between liquid crystal units
Inventor: AKADA TOMOHIRO
IPC: G01B11/06
Filed: 2001-02-23
Granted: 2005-10-21
Abstract: This invention relates to a method for inspecting gaps between liquid crystal units, which comprises using the polarizing angle configured to be theta1 of the polarizing lens to obtain the reflection intensity S1 of the liquid crystal units 15 under cross-nicol state; measuring the reflection intensity Ref1 of a reference piece; and using a different polarizing angle configured to be theta2 to obtain the reflection intensity S2 of the liquid crystal units 15 under cross-nicol state; measuring the reflection intensity Ref2 of the reference piece; obtaining the ratios of intensity as measured S1/Ref1, S2/Ref2; and obtaining the ratios of intensity as measured S1*Ref2/S2*Ref so as to offset background of the reflection intensities Ref1, Ref2 entering the reference piece, and thereby accurately obtaining the gap values between liquid crystal units.
Patent TW-535263-B (TW)
Title: (PF/dram/KP) method and structure of incorporating RUTILE TiO2 and other high k dielectrics in a deep trench storage cell of dram
Inventor: JAMMY RAJARAO
IPC: H01L21/334
Filed: 2001-03-20
Granted: 2003-06-01
Abstract: A trench capacitor structure comprising a buried electrode about a trench, said trench being formed in a semiconductor substrate, a node dielectric lining said trench at said buried electrode and trench electrode formed on said node dielectric, said node dielectric comprising a diffusion barrier and a high dielectric constant dielectric such as rutile phase TiO2 is provided. A method of fabricating such a trench structure is also provided, said method comprising (a) providing a semiconductor substrate having at least one trench formed therein, said at least one trench being defined by a trench wall; (b) forming a buried electrode in said semiconductor substrate about at least a portion of said trench wall; (c) forming a diffusion barrier on said trench wall over at least a portion of said buried electrode; (d) forming a dielectric material having a high dielectric constant, e.g., rutile phase TiO2, on said diffusion barrier; and (e) forming a first conductive layer on said high k dielectric, said first conductive layer forming a trench electrode.
Patent TW-498140-B (TW)
Title: Height adjusting
Inventor: KOGAMI MITSURU
IPC: F16B37/10
Filed: 2001-02-27
Granted: 2002-08-11
Abstract: This invention provides a height adjusting fixture to have a simple structure and facilitate adjustment of height. A holder 3 consists of a pair of division bodies 3a and 3b coupled through a hinge part 3c, and a female screw part 8a is provided on the division bodies capably of being threaded engaged with a stud 2. A cap 4 is engaged with a holder that an engaging protrusion part 9a of an elastic piece 9 situated at a holder is received by an engaging hole 10 formed in the cap and capable of relatively moving in the axis direction, so as to keep the division bodies in state of being closed and threaded engaged with the stud. Thus, engagement and disengagement of a holder with and from the stud are practicable by opening and closing of a pair of division bodies, and the cap is situated in a state to be engaged with the holder, and a state to close together the division bodies is held, and a work to assemble the holder to the stud at an arbitrary height is facilitated.
Patent TW-503430-B (TW)
Title: Color display tube
Inventor: DAIMON TOSHIHIRO
IPC: H01J29/50
Filed: 2001-03-21
Granted: 2002-09-21
Abstract: The present invention relates to a color display tube, wherein a vertical electrode plate 28 having three openings 30a, 30b and 30c formed in-line through which three electron beams pass respectively is provided only inside a focusing electrode 23 out of the focusing electrode 23 and a final accelerating electrode 24; and a horizontal electrode plate 29 that is substantially parallel to an in-line plane extending toward the focusing electrode 23 is formed at least one of above and below openings 31a, 31b and 31c at the bottom of a shielding cup 25, only inside the final accelerating electrode 24. By setting the height h of the horizontal electrode plate 29 optimally, it is possible to correct a horizontally-elongated distortion of a spot shape in the edge portions of a screen caused by a self-convergence magnetic field of a deflecting device. In this manner, a color display tube that achieves an image display with a high resolution can be provided.
Patent TW-492212-B (TW)
Title: Material for positive electrode and secondary battery
Inventor: TSUJIMOTO HISASHI
IPC: H01M10/0525
Filed: 2001-03-28
Granted: 2002-06-21
Abstract: Disclosed is a non-aqueous electrolyte secondary battery having an excellent preservation characteristic at a high temperature and charging/discharging cycle characteristic. A rolled body in which a strip-shape positive electrode and negative electrode are rolled with a separator in-between is provided inside a battery can. The positive electrode contains LixMn2-yMayO4 (where, Ma is at least one element selected from the group consisting of metal elements other than Mn, and B) and LiNi1-zMbzO2 (where, Mb is at least one element selected from the group consisting of metal elements other than Ni, and B). By replacing part of Mn and Ni with other elements, the crystal structure can be stabilized. Thereby, the capacity retention ratio after preservation at a high temperature, and a heavy load discharging power under a high electric potential cutoff can be improved. The mean particle size of particles of the above-mentioned oxides are preferable to be 30 μm and below so that an excellent charging/discharging cycle characteristic can be obtained.
Patent TW-508478-B (TW)
Title: Resist stripper composition
Inventor: YOON SUK-IL
IPC: G03F7/42
Filed: 2001-04-26
Granted: 2002-11-01
Abstract: The present invention relates to a resist stripper composition that is used to remove resists during manufacturing process of semiconductor devices such as large size integrated circuits, very large size integrated circuits, etc. The resist stripper composition comprises 3 to 10 weight% of an organic amine compound, 30 to 60 weight% of a solvent selected from a group consisting of DMAc, DMF, DM1, NMP, and etc., 30 to 60 weight% water, 1 to 10 weight% of an catechol, resorcin or a mixture thereof and 1 to 10 weight% of C4-6 straight polyhydric alcohol. The resist stripper composition of the present invention can easily and quickly remove resist polymer cured by hard baking, dry etching, and ashing, and side-wall resist polymers caused by lower metal film material due to reaction of etching and ashing gases, and is particularly useful for removing side-wall resit polymers caused by aluminum, aluminum alloy and titanium nitride film materials. In addition, it can minimize corrosion of lower metal film material during the resist removal process, and particularly, it minimize corrosion of novel metal film material applied in very large size integrated semicounductor manufacturing lines of 64 mega DRAM or more.
Patent TW-501268-B (TW)
Title: Simulated defective wafer and defect inspection program preparing method
Inventor: NODA TOMONOBU
IPC: G01N21/956
Filed: 2001-05-04
Granted: 2002-09-01
Abstract: A provisional inspection processing-program is prepared by using a simulated defective wafer having a simulated defect pattern that has the variations in height and plane shape with respect to a simulated normal pattern. An actual defect inspection is performed onto the simulated defective wafer by means of an actual defect inspection apparatus. The detected defect data is compared with a previously obtained simulated defect data of the simulated defective wafer to quantify a defect detection-sensitivity. After that, by changing the processing program parameters, the provisional inspection recipe is modified until a desired defect detection ratio is obtained. When the desired defect detection ratio is obtained, the processing program parameters at the time are decided as the processing program parameters adaptive for the defect inspection apparatus.
Patent TW-510968-B (TW)
Title: Information providing system, information providing method, information provider, information obtaining device, and recording medium
Inventor: ISHIOKA SHOGO
IPC: G06Q30/06
Filed: 2001-05-23
Granted: 2002-11-21
Abstract: The present invention aims to provide information in connection with the inspection and the manufacturing of circuit substrate to an assigning party and manufacturers for supporting smooth business trade. The mean of solution is an information providing method for providing the assigning party to assign the supply of a circuit substrate inspection device with information in connection with inspection device. The method includes the following steps: (1) acceptance of the substrate specification information indicating the required specification of the circuit substrate by the assigning party; (2) providing the accepted substrate specification information to manufacturers; (3) confirmation of the product information provided by the manufacturer by the manufacturer; (4) providing the confirmed product information to the assigning party. Thus, by means of the method, information of various manufacturers can be provided to the assigning party.
Patent TW-488078-B (TW)
Title: Semiconductor device and method of manufacturing same
Inventor: UENO SHUICHI
IPC: H01L27/108
Filed: 2001-06-05
Granted: 2002-05-21
Abstract: Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAXofP) renges from 1 x 10<SP>18</SP> to 1 x 10<SP>19</SP>, and the maximum value of the N type impurity concentration (MAXofN) of a source/drain region (31(32))is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.
Patent TW-472224-B (TW)
Title: Display device and angle adjusting device
Inventor: ANZAI MASATO
IPC: F16M11/10
Filed: 2001-06-11
Granted: 2002-01-11
Abstract: Disclosed is a display device that can be folded to be stored or carried when it is not in use. The display device comprises a pedestal that includes a planar pedestal main body to be placed on a placing object and a planar arm that is arranged in a standing manner with a specified angle against the pedestal main body, and a display portion that is installed to the arm in a swinging manner and has an image display portion. In the case where the center of gravity of the display portion is within a range of a projection surface of the pedestal, the swinging angle of the display portion can be optionally set. Moreover, the pedestal main body and the arm can constitute the same plane, and they are rotated so as to parallelly oppose to the display portion while keeping such constituted state, thus protect the display portion.
Patent TW-506082-B (TW)
Title: Lightly-insitu-doped amorphous silicon applied in dram gates
Inventor: SHIU JIA-FU
IPC: H01L21/8242
Filed: 2001-07-18
Granted: 2002-10-11
Abstract: The present invention forms a polysilicon layer by first forming then heat treating a lightly in-situ doped amorphous silicon layer, thus suppressing boron penetration and lateral diffusion between N+ impurity and P+ impurity.
Patent TW-591658-B (TW)
Title: Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory
Inventor: OKUDA YUICHI
IPC: G11C11/4076
Filed: 2001-07-18
Granted: 2004-06-11
Abstract: A variable delay circuit (101) is used to measure an optimum cycle number of a delay from an external clock till a data output, and a DLL circuit or the like is configured by locking at the cycle number to realize the clock generating circuit with a wide lock range independently of the performance of the variable delay circuit and a clock access time.
Patent TW-535177-B (TW)
Title: Capacitor
Inventor: SOMMARIVA HELMUT
IPC: C04B35/495
Filed: 2001-08-10
Granted: 2003-06-01
Abstract: This invention relates to a capacitor with two or more electrode-layers (1) located in pair oppositely and a dielectric-layer (2) respectively between the layers (1), in which the dielectric-layers (2) include a ceramic-material, which has at least two different components existent in separated phases, the components have a perovskite structure respectively, which has silver at the A-locations and niobium and tantalum at the B-locations, and the composition of a component A and the composition of a component B is selected respectively, so that TKepsilonA and TKepsilonB in a temperature interval have different signs. The suitable mix-ratio of the components can be realized through the stacking of the green-foils of components A and the green-foils of components B respectively in a suitable number.
Patent TW-548688-B (TW)
Title: Semiconductor light-emitting device
Inventor: KURAHASHI TAKAHISA
IPC: H01S5/343
Filed: 2001-08-31
Granted: 2003-08-21
Abstract: The present invention relates to a semiconductor light-emitting device used for optical transmission (particularly for IEEE 1394) and displays and the like. More specifically, an object of the present invention is to provide a semiconductor light-emitting device capable of emitting the light with a high efficiency by extending a distance from an active layer to a boundary having poor crystal quality due to Group V elements As and P exchange to suppress deterioration in crystal quality of the active layer. According to the present invention, a semiconductor light-emitting device capable of emitting the light with a high efficiency because a reflecting multilayer with a different material system from that of an active layer is formed on the substrate in order to achieve a high reflectance, however, the active layer is formed, after a reflecting multilayer formed with the same material system as that of the active layer is formed thereon, to lengthen a distance between the active layer and a material system exchange boundary.
Patent TW-502391-B (TW)
Title: Fabrication method for doped copper interconnect
Inventor: HUANG CHENG-LIN
IPC: H01L21/768
Filed: 2001-09-06
Granted: 2002-09-11
Abstract: A fabrication method for doped copper interconnect is provided to eliminate additionally formed copper protection layer or etch stop layer and diffusion barrier layer in copper interconnect fabricating process. Interconnect is formed by filling grooves or via holes or dual damascene structure with copper metal doped by at least one of the following elements: magnesium, silver, titanium, zirconium, tin, zinc, or carbon. Annealing the copper metal for diffusing the doping element into the surface of copper metal and to form an oxide layer that serves as copper protection layer, etch the stop layer and diffusion barrier layer. Thus, copper metal oxidation and photoresist poisoning are prevented and process is simplified.
Patent TW-535087-B (TW)
Title: Instructions supporting system, instructions peripheral device and instructions central device
Inventor: MATSUZAWA SHOHACHI
IPC: G06Q50/00
Filed: 2001-10-19
Granted: 2003-06-01
Abstract: The present invention is to support appropriate instructions of an instructions supporting system. An instructions peripheral devices 5 sends information of operational status of people who are in charge and present position to a position information processing device 1 and instructions device 2. When the instructions are sent, then the instructions device 2 will select and display, according to the present position of each instructions peripheral devices 5 and to operational status of people who are in charge, the instructions peripheral devices 5 that belongs to an article to be selected, of sending instruction. People who are in charge of instructions decide, according to the display, the instructions of the sending instructions.
Patent TW-507489-B (TW)
Title: Parts suction head having non-contact sealing structure
Inventor: KIM DONG-JUNE
IPC: H05K13/04
Filed: 2001-12-10
Granted: 2002-10-21
Abstract: The present invention aims to provide a parts suction head having non-contact sealing structure of a surface processing machine for precise adjustment of the rotation of the swivel spindle. The solution of the present invention is that the suction head for parts suction installed on a printed circuit base board consists of a moving block in which a plurality of first air-flow holes are made and a first hollow part being formed along the width of the moving block; a separator defining at least one second air-flow holes in a predetermined area thereof and in communication with the first air-flow holes for air flowing and a second hollow part being formed along the width of the separator; a swivel spindle inserted inside the second hollow part formed by the separator to maintain predetermined separation condition, the swivel spindle being connected with the second air-flow holes to form at least one third air-flow holes for air flowing, a third hollow part being formed along the width of the swivel spindle, one end of the swivel spindle being coupled to a ball spline part and a motor; and a flange installed on two ends of the moving block to seal the space between the separator and the swivel spindle.
Patent TW-I221428-B (TW)
Title: High speed finishing block
Inventor: WESOLOWSKI FRANCIS J
IPC: B21B13/00
Filed: 2001-12-31
Granted: 2004-10-01
Abstract: A multi-stand block for a rolling mill comprises a plurality of roll stands alternately arranged on opposite sides of a pass line along which a product is rolled in a downstream direction from an entry end to an exit end of the block. Drive shafts are provided on opposite sides of the pass line. The drive shafts comprise coaxial segments interconnected by couplings, with each roll stand being connected to a respective one of the line shaft segments. A block drive is connected to the line shafts at the upstream end of the block, and the couplings are selectively disconnectable to mechanically isolate any downstream line shaft segments and the roll stands connected thereto from the block drive.
Patent TW-522515-B (TW)
Title: Redistribution process
Inventor: WENG JAU-FU
IPC: H01L21/44
Filed: 2002-01-07
Granted: 2003-03-01
Abstract: A redistribution process comprises the following procedures. Firstly, a first titanium layer, a first copper layer and a second titanium layer are successively formed on the surface of a wafer. Next, the second titanium layer, the first copper layer and the first titanium layer are defined to form a patterned wiring layer. Thirdly, a patterned benzocyclobutene layer is formed to expose the second titanium layer. Fourthly, the exposed second titanium layer is removed to expose the first copper layer. Finally, a plural number of input/output contacts are formed on the benzocyclobutene layer and connect to the exposed first copper layer. In addition, the wafer contains multiple bonding pads and each input/output contact is connected to a bonding pad via the patterned wiring layer.