Patent GB-1344473-A (GB)
Title: Circuits for processing digital data
IPC: G11B20/14
Filed: 1971-01-28
Abstract: 1344473 Recording/reproducing digital data PACIFIC MICRONETICS Inc 28 Jan 1971 3403/71 Heading G4C A circuit for processing binary signals prior to recording includes means for modulo 2 counting the occurrence of signals of one polarity, the means having first and second states, timing means producing signals indicative of bit cell boundaries and midpoints, means having first and second states and changing state in response to control signals, and means for providing a control signal at the trailing boundary of a bit cell in which a binary signal is to be represented when the signal is of the one polarity and the modulo 2 counter is in its second state and when the signal is of the other polarity and the modulo 2 counter is in its first state, and at the mid-point of the bit cell when the signal is of the other polarity and the modulo 2 counter is in its second state, the state of the modulo 2 counter being in each case that neglecting the signal to be represented. The control signals set and reset a flip-flop, changes of state of which cause magnetic transitions to be recorded. The circuit includes a shift register 15 of JK flip-flops WL, WB, PA2, PA1, PA0, and PB, data being recorded from PA0. The data are shifted through register 15 by shift pulses denoting bit cell boundaries and generated by frequency division by circuit 22 from oscillator 21. Flip-flop WC acts as a modulo 2 counter of zeros passing through PA0, the flip-flop being set after an odd number and reset after an even number of zeros. Signals are recorded by transducer 11 in response to the state of flip-flop WT which changes state each time it receives a clock input at its terminal C. The clock signals are generated by a clock gating circuit 16 in response to signals generated by the remainder of the circuit. Two embodiments of circuit 16 are described one of which introduces a distortion to compensate for crowding distortion obtained on read out. In the simpler case and assuming PA0 stores a zero and WC is set (i.e. an odd number, e.g. 1, of previously recorded zeros) a clock signal is gated to WT at the end of the corresponding bit frame and WC is reset. If the next bit shifted to PA0 is also a zero a clock gating signal is not fed to WT owing to the state of WC which is however set at the end of the corresponding bit period. Thus a bit cell containing a zero which brings the total number of recorded zeros to an odd number is not terminated by a transition. If such a zero is followed by a one a transition forming clock signal is gated by circuit 16 to WT at a mid-point of the cell representing the one. If however the one follows a zero which brings the total number of recorded zeros to an even number a transition generating clock pulse is gated to WT at the end of the cell representing the one. Sequences of ones are represented by transitions at bit cell intervals, the transitions having a phase relative to the bit cell boundaries determined by whether the first "one" in the sequence followed an even or an odd number of previously recorded zeros. The clock gating circuit 16 is not described in detail but merely in terms of the Boolean functions of the signals generated by the various flip-flops and gates in the circuit.  A circuit for reproducing data recorded as above is described. The circuit includes a counter driven by an oscillator having a frequency greater than the bit rate, e.g. oscillator 21. The counter generates outputs at fixed counts denoting zones at particular times within a bit cell during which detected transitions are registered. The transition registering signals are fed to flip-flops which are connected in a decoding circuit for recovering the data. Apparent transitions at invalid times, e.g. at a bit cell mid-point when a transition occurs at the front edge of that bit cell, are suppressed.