Patent GB-1029516-A (GB)
Title: Improvements in or relating to translation circuits
IPC: H03M7/00
Filed: 1964-11-27
Abstract: 1,029,516. Translators. STANDARD TELEPHONES & CABLES Ltd. Nov. 27, 1964 [Dec. 4, 1963; Dec. 5, 1963; Dec. 7, 1963 (3); Dec. 13, 1963; Jan. 24, 1964], No. 48247/64. Heading H4K. [Also in Division G4] A translator has a pulse code combination applied in parallel form to the windings on a set of input ferro-magnetic cores with a number of coupling wires, each individual to an input pulse code combination, being threaded through a selection of input cores such that one wire is selected when its code combination is applied to the input windings. Each coupling wire also threads through a selection of output ferro-magnetic cores appropriate to the translation of the input code combination, so that when a coupling wire is energized due to the reception of its input code combination the energization causes output signals from windings on the output cores, which output signals form the required translation. Fig. 8 shows a translator incorporating a number of features introduced singly or in various combinations in Figs. 1 to 7 (not shown). In Fig. 8 the number of coupling wires threading the cores is reduced by splitting the input code combination into three parts, a to c, d to #f and x to #z, the input signal being applied in normal and complementary form, e.g. a b and c are positive and #a #b #c negative for input 111, and vice versa for input 000. For each group of input cores a wire is threaded through cores so that each wire el to en threads cores representing one possible input code combination. Each wire also threads a core S such that a pulse induced in the wire by an input to core S is cancelled, by pulses induced by the input code combination applied to cores Kel to Ken, in all wires except that corresponding to the received code combination. Thus the received code combination applied to inputs a to c results in one of transistor T being energized. Similarly a second part of the input code combination is applied to inputs x to z to energize one of transistors T<SP>1</SP> and the combined energization of one transistor T and one transistor T<SP>1</SP> results in the energization of one of the wires Sel to Sen which threads appropriate ones of the output cores in the three groups of output cores Kal to Kan, Kal<SP>1</SP> to Kan<SP>1</SP>, and Kal<SP>11</SP> to Kan<SP>11</SP>. Which particular translation is effective of the three available from the three groups of output cores is decided by the energization of inputs d to #f, pulses being applied from these inputs to all cores in two of the groups so as to oppose the pulse induced in the selected combination by the selected one of the wires Sel to Sen in all but the selected group of output cores. The output signal is available on wires k to q threading the output cores. If required, the output signal may be taken through a transistor having a pair of coupling wires threading the respective output core, the system forming a blocking oscillator. To ensure that all transistors required become conductive the supply to the blocking oscillators is via a further transistor Tr3, Fig. 4 (not shown) so that the core energization results in internal base charge storage in the corresponding transistors Tr, the selected transistors becoming conductive when the signal V is applied to transistor Tr3. In a further arrangement two groups of input cores and two groups of output cores are used, input information being applied in parallel to the two groups of input cores, and the output cores being rendered effective alternately, the reset pulse on one group of output cores causing the transfer of information from the input cores to the other group of output cores, Fig. 9 (not shown). Fig. 11 shows an alternative arrangement where instead of each input or output core being characteristic of an input or output digital position the input and output wires thread a selection of cores so that each core is characteristic of a part of the input, or output, code combination. In this arrangement the coupling wires between the input cores and the output cores are broken and arranged as a matrix so that by selection of cross-points to be connected in the matrix the translation may be changed. Fig. 13 shows a sequence switching arrangement in which input information is applied from source E to cores Kel to Ken. On occurrence of pulse T1 all input cores are reset via wire Sre and core Ks is operated and, as described above, only in the wire corresponding to the input code information is the pulse from Ks not cancelled by the resetting of the set input cores, thus causing the setting of the corresponding output cores Kal to Kan according to the translation set in matrix KB. After a delay V the pulse T1 is applied to the blocking oscillator transistors Tsl to Tsn. When pulse T1 ends the translation is complete and cores Kal to Kan are set correspondingly. The timing pulse T2 then occurs causing transistor Tr2 to conduct completing the loops SKl to SKn so that the T2 pulse on line Sra, when it resets the cores Kal to Kan, causes the setting of the input end cores Krl to Krn via loops SKl to SKn in accordance with the output information. The fed back information may determine the starting point for the following translation and the sequence repeated to furnish successively all possible code signals of a defined code. In an alternative arrangement the feedback loops between Kal-n fins Krl-n include blocking oscillators switched on by a timing pulse after a delay so that a single pulse " cycle " is detainable. A practical arrangement of the embodiment of Fig. 13 is described with respect to Fig. 12 (not shown), in which half cores are mounted on a panel on to which a wiring harness is placed, the cores being completed by a sheet of magnetic material or an assembly of half cores on a further panel. Also mentioned is a device, Fig. 15 (not shown), for converting between binary, twoout-of-five code, and decimal.