Patent FR-2790886-A1 (FR)
Title: Sequential addressing method for multiplexer inputs of data acquisition circuit, involves using basic computer with global reconfiguration of addressing as appropriate
Inventor: PITOT CHRISTIAN
IPC: G06F17/40
Filed: 1999-03-12
Abstract: The method involves using a basic computer for addressing the multiplexer stages, and utilizing parallel control circuits for the intermediate switching circuits. A periodic command is created and inputted to the basic computer, for the lowest level switching stage, in order to determine the successive computation cycles. The computer addressing configuration is adjusted at the end of the computation cycles, for the lowest switching level. The acquisition of data, is carried out by use of a multiplexer (2) comprising three switching stages between inputs and an output, which are addressed at the level of each stage by elementary computation units, in particular three, (11,12,13), connected in series with the respective stages of the multiplexer to ensure the addressing of lower stages. The device also comprises a reinitialization input, the computation units outputs controlling the switches of the multiplexer stages, and an overflow output. The elementary computation units (11,12,13) with controlled shunt circuits (14,15) constitute a global computation unit (10) for addressing. The addressing procedure comprises the use of lower-level unit (11,14) nearer to the input of multiplexer with controlled computational capacity or length of cycle, the provision of controlled shunt circuit (15) of the elementary unit (12) at the intermediate stage, a periodic ordering of computation for input to the elementary unit (11) of lower-level switching stage for defining successive cycles of computation, and an adjustment of the configuration of the global computation unit (10) starting with each cycle of computation of elementary unit (11) by an action on the length of cycle by control of the shunt circuit (14) of the lower-level stage, and also of the shunt circuit (15) of the intermediate-level stage. The successive reconfiguration of the global computation unit (10) for the addressing of multiplexer (2) is carried out by a sweep sequence of the inputs of multiplexer, which is defined by a set of instructions written in binary language. The instructions in binary language comprise words for the length of cycle adjustment with respect to the unit (11,14) for addressing the lower-level switching stage, and words for the activation or inhibition of the shunt circuit (15) for addressing the intermediate-level switching stage. The binary language code also comprises words for the activation or inhibition of the repetition mode or the maintenance of the length of cycle with respect to the unit (11,14). The binary language code also comprises a word for the end of a suite of instructions. The different words of the configuration code also comprises a word for the end of a suite of instructions. The different words of the configuration code are of variable length, where the words more frequently utilized are of shorter length. The addressing of multiplexer starts with logic 0 with the exception of word for the inhibition of the repetition mode, which is logic 1. The activation of the repetition mode is by the binary word 01, and the activation and inhibition of the shunt circuit (15) is by a four-bits binary word 0001. The acquisition of data, systematic and eventually repetitive, is carried out by use of a multiplexer (2) comprising a set of stages, in particular three, of switching between inputs and an output, which are addressed at the level of each stage by elementary computation units, in particular three, (11,12,13), connected in series with the respective stages of the multiplexer to ensure the addressing of lower stages. The device also comprises a reinitialization input, the computation units outputs controlling the switches of the multiplexer stages, and an overflow output. The elementary computation units (11,12,13) with controlled shunt circuits (14,15) constitute a global computation unit (10) for addressing. The addressing procedure comprises the use of lower-level unit (11,14) nearer to the input of multiplexer with controlled computational capacity or length of cycle, the provision of controlled shunt circuit (15) of the elementary unit (12) at the intermediate stage, a periodic ordering of computation for input to the elementary unit (11) of lower-level switching stage for defining successive cycles of computation, and an adjustment of the configuration of the global computation unit (10) starting with each cycle of computation of elementary unit (11) by an action