Patent GB-1089859-A (GB)
Title: Improvements in or relating to a receiver for a multi-channel time-division-multiplex communication system
Inventor: CHANDLER THOMAS WILFRED
IPC: H04J3/06
Filed: 1965-05-12
Abstract: 1,089,859. Multiplex pulse code signalling. GENERAL ELECTRIC CO. Ltd. July 20, 1966 [May 12, 1965], No. 20135/65. Heading H4L. In a receiver for a time division multiplex system wherein each frame comprises a group of pulse positions in respect of each channel for the transmission of primary information and further pulse positions similarly disposed in every frame for the transmission of secondary information, a cycle of the transmitted signal comprising one frame in which the secondary information comprises synchronizing information and two or more frames in which the secondary information comprises signalling information, means are provided responsive to the synchronizing information to phase the distribution of the primary information to the various receiving channels correctly and to isolate the signalling information from the frames carrying such information. The receiver described is used in a 24 channels P.C.M. system in which one frame comprises 24 groups of 8 time slots. The first 7 slots represent " primary " information and the eighth time slot is used for synchronizing or signalling, every third frame carrying the synchronizing signal. Synchronizing.-The received signal is supplied via an AND gate 1, controlled by locally generated digit-eight pulses, and inverter 4 to a non-coincidence gate 3. A locally generated synchronizing signal pulse sequence is supplied via inverter 5 to gate 3. A bi-stable circuit 7 triggered by frame frequency pulses from terminal 11 co-operates with a bi-stable circuit 8 to provide a frequency division by a factor of three so that the remaining input to gate 3 consists of a pulse of frame width once every three frames. The local synchronizing pulses from terminal 6 differ from the transmitted synchronizing pulses in that they have a duration of four digit time slots and are inverted in polarity with respect to the received pulses so that after further inversion at 5 they become disabling pulses for gate 3. The arrangement is such that if the local and received synchronizing pulses coincide in the "local" digit eight position every third frame there will be no output from gate 3, any output indicating an error. Any error pulse from gate 3 is supplied via an OR gate 12 and inverter 13 to an INHIBIT gate 14 and an integrator 15 the integrator 15 switching over a bi-stable circuit 16 after a predetermined number of successive error pulses or a predetermined number of successive absences of error pulses respectively. Thus gate 14 provides a " confirmed " error pulse after a predetermined succession of error pulses which is supplied via pulse stretcher 17 to inhibit a normally open gate 18 supplied with a bit-rate signal which controls the receiver timing. This retards the receiver timing by one digit-pulse, the circuit 15, 16 being arranged so that if the next check supplies an error pulse the gate 14 remains open, and the phase adjustment being continued until the local and received signals are in synchronism. A further check is provided by AND gate 21 which receives the locally generated synchronizing signal via inverter 5, bit-rate pulses from terminal 22, locally generated digit-one pulses and local frame synchronizing selecting pulses from bi-stable circuit 7. Gate 21 provides a bit-rate pulse for each digit-one pulse coinciding with a locally generated frame synchronizing pulse, which is supplied via an inverter 24 supplying a short enabling pulse to coincidence gate 23 whose other input is supplied from AND gate 1 via pulse stretcher 25. The pulse from stretcher 25 extends from the digit-eight position to overlap the next digit-one position, i.e. to coincide with the pulse from inverter 24, but is a disabling pulse for gate 23. If, however, the local synchronizing pulses as supplied by inverter 24 do not coincide with received synchronizing pulses an error pulse is supplied via OR gate 12 to put into effect the previously described search operation. Extracting the signalling information.-The received signal is also supplied via terminal 28 to AND gates 26, 27 controlled by locally generated digit-eight pulses from terminal 29. Gate 26 also receives signals from bi-stable circuits 7, 8 so that it is enabled for one of the non-synchronizing frames and gate 27 receives a signal from bi-stable circuit 8 so that it is enabled for the other non-synchronizing frame. An inverter 30 provides an enabling input to both gates when bi-stable circuit 16 indicates " no error."