Patent GB-993163-A (GB)
Title: Error detection system
IPC: H04L1/00
Filed: 1962-04-26
Abstract: 993,163. Computing check symbols. SPERRY RAND CORPORATION. April 26, 1962 [June 27, 1961], No. 16020/62. Heading G4A. In an error detection and connection system for digital data signals, a check signal group is generated by summing in a modular accumulator the products of the data signal sigits with predetermined weights in arithmetic progression. Method employed. According to the checking method described, a binary word m = mn m n-1  ... m 1  to be transmitted is provided with a parity bit p arranged to make the sum of the "1"s in the combination of m and p odd, and a check character c = c k  c k-1 ..... c 1 , so that the signals actually transmitted represent To determine the check character c, weights n, n-1 ..., 1 are assigned to the digits of the binary word m and the sum is formed in a modular accumulator where the modulus M = 2<SP>k</SP>, k being the least integer such that The check character c thus satisfies the congruence Thus for a 20-bit data word (n = 20), k = 6, and a mod 64 accumulator is employed. By the use of this method, a single error anywhere in the transmitted signals can be detected and corrected, two errors can be detected and three errors can probably be detected. By the use of an additional parity bit, the error detection capability is increased. Various modifications of the basic method are described, for instance the parity bit p may be computed from the check number c and data m instead of just from the data m;or the check number may be computed from the parity p and from the data m. Check number computing circuit. The Figure shows apparatus which, according to the state of a two-position switch 10 can function either (1) to compute a parity bit p and check number c for transmission with a data word m to a remote location (not shown) or (2) to receive a message from a remote location, re-calculate the parity but and check number, and compared these with the received parity bit and check number, providing an error signal if the calculated and received parity bit and check number are not the same. Operation as transmitter. Data signals from a local source are applied serially to a terminal 12 in synchronism with clock pulses applied to a terminal 80. The clock pulses are counted in a mod 2<SP>k-1</SP> counter 78 and each data "1" bit gates the value currently in the counter 78 into a mod 2<SP>k</SP> accumulator 108. Each data "1" bit also changes over a parity flip-flop 24. The data signals are transmitted to a remote location via a terminal 172 and as the last bit of data is transmitted a signal is applied to a terminal 174 to changeover a flip-flop 94 thereby cutting off the supply of clock pulses. At this time a distributer (not shown) scans terminals 137-150 to read out the parity bit from the flip-flop 24 and the check number from the accumulator 108 for transmission via the terminal 172. Operation as receiver. In operation as a receiver, contacts 10b-d are closed and contacts 10a, e are open. The data from a remote location is received on a terminal 188 and applied as described above to the parity flip-flop 24 and in the calculation of the check number in the accumulator 108. When the data word m has been received, the flip-flop 94 is changed over and the subsequently received parity bit p and check number c are compared with the computed parity bit and check number in an EXCLUSIVE OR gate 202, any inequality in the compared bits causing an error flip-flop 216 to be set.