Patent GB-1126601-A (GB)
Title: Improvements in or relating to apparatus for use in the automatic recognition of characters
IPC: G06V30/10
Filed: 1965-09-28
Abstract: 1,126,601. Character recognition; gated counters. SIEMENS A.G. 28 Sept., 1965 [29 Sept., 1964], No. 41101/65. Headings G4A and G4R. In a character recognition device adapted for characters positioned in a window in surroundings of similar brightness to the character, the character is scanned in columns and the scanning signal elements are compared with signals specifying the position of the window as it was in the last column not passing over a character, detection of no 0 in a given column causing 0s to replace Is in the preceding column as gated to recognition circuits, 0 representing a window element and 1 a character or surroundings element. The character may merge with the surroundings at the trailing edge, as in e.g. a photograph of meter readings sometimes. Referring to Fig. 2, a train of " ones " is established in a recirculating register YF during the most recent column of the scan which crossed the window but did not cross the character (details below), to correspond in time to the crossing of the window. During a given column, a " zero " scanning signal element (representing an empty part of the window) occurring concurrently with one of these window pulses resets (via a blocking gate GLO) a bi-stable SLO set at the column beginning. However, when scanning the first column of the surroundings after the character and window, only " one " scanning signal elements occur so the bi-stable SLO is not reset and enables a gate GFE to pass a signal, from a differentiator LD detecting the last of the window pulses, to set a bi-stable SFE. This enables a gate GLFE, and sets a bi-stable SSp via a gate GSpa at the beginning of the next column. Setting of bistable SSp enables gate GLFE, resets bi-stable SFE and allows itself to be reset at the beginning of the next column. The scanning signal elements were also passed through two onecolumn registers vR, R in series to a gate Gk leading to the recognition circuitry. When gate GLFE is enabled as above, window pulses are passed by it to block gate Gk. In view of the two-column delay in the registers vR, R, the effect is to delete the " ones " in the column of scanning signal elements preceding the first column which is entirely in the surroundings. In the above, the gate GSpa is enabled at the beginning of each column to allow the setting mentioned above, but if this is done only every other column, the " one" scanning signal elements in the first column entirely in the surroundings are also deleted. Producing the window pulses.-Referring to Fig. 3, a store ZS holds a number for each row (perpendicular to the scanning columns) of the scanning matrix. This number holds the number of consecutive " ones " in the row up to the present, is incremented as further " ones " arrive on line n from register vR (Fig. 2), but is not allowed to exceed a threshold value at which a unit LSZ (gates recognizing particular numbers) produces an output, and is set to zero if a " zero " scanning signal element is encountered. When an early column in the scan has been reached within the window, differentiators D10v, Dv set a bi-stable Sfo in response to the first " zero " scanning signal element and the disappearance of an output from the unit LSZ on crossing the upper boundary of the window. Bi-stable Sfo is reset in response to an output from the unit LSZ or a " one scanning signal element. While bi-stable Sfo was set, a counter Zf counted clock pulses. If this count comes within prespecified limits representing the window depth, a gate GF produces an output when the lower boundary of the window is reached in response to the appearance of an output from unit LSZ and of a " zero " to " one " change in the scanning signal. The number of sequences of consecutive " zeroes " in the scanning signal was counted by a ring counter VZW fed from line n via differentiator D10v and whenever an output from gate GF occurred the stage reached was marked to preset corresponding stages in a shift-register RZW at the end of the column. Register RZW is then shifted down using changes in the same scanning signal elements, delayed in register R and fed to the register RZW via a differentiator D10r. Whenever a "one" exists in the first stage of register RZW, a blocking gate GYF produces window pulses in response to " zeroes " from register R. The window pulses are stored in recirculating store YF, being deleted in response to the output of gate GF to make way for a new set each time a column is scanned which crosses the window but not the character. An output from gate GF also changes the threshold in unit LSZ to correspond to the minimum width of a character. Counter (Fig. 5).-Parallel 5-bit binary numbers are read non-destructively in turn cyclically, from respective storage locations at ZS and passed to logic which produces pulses to increment the stored value by one if an add pulse is received concurrently and reset the stored value to zero if an add pulse is not received. In the logic, each bit line from the store goes to a respective AND-gate and all higher-order AND-gates, UG &c. The AND- gates UG &c. feed blocking gates SG &c. each having a negate input, and also OR-gates leading to bit reset lines. The add pulses are fed to the AND-gates and the lowest-order blocking gate. Incrementing of any number above a predetermined value is prevented by an AND-gate G25 recognizing the number to block the add pulses. Two such AND-gates may be provided, being used alternatively.