Patent GB-1177405-A (GB)
Title: Calculating Machine with a Delay-Line Cyclic Store
Inventor: HILDEBRANDT VOLKER
IPC: G06F3/00
Filed: 1967-04-05
Abstract: 1,177,405. Calculator. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 5 April, 1967, No. 15567/67. Heading G4A. A calculating machine contains a circulating delay line, forming at least two main registers holding complete calculating quantities, and an adder, wherein the bit cells for binary coded digits in the main registers are contained in series in a bit-circulating channel, the cells and extractions therefrom and interchanges therebetween being determined by timing periods from the pattern of bit clock pulses where bits extracted from the channel can be fed into the first stage of a shift chain which extends the circulating path, and selected stages of which are connected to the inputs and the output of the adder. The delay line S, formed of a glass rod connected to piezo-electric transducers at each end, is fed by a writing amplifier SV and feeds a reading amplifier LV connected to a flip-flop FL. Data may be fed back to the input via gate H3 or may pass via gate H4 to a shift register SK the second stage F2 of which is connected via gate H6 to the writing amplifier SV. The delay line holds four main registers A, B, C, D, each of 16 digits in binary coded decimal form. If a binary coded decimal digit is represented by d, c, b, a and the first bit of the first digit in register A is A1a then the numbers stored in the delay line are held in the order A1a, B1a, C1a, D1a, A2a, B2a-D2a, A3a-D16a, A1b, B1b-D16b, A1c-D16d, thus separating the consecutive digits of any b.c.d. number by “ of the length of the delay. The timing arrangement comprises a 4MHz clock Q feeding counters Z1, Z2 via gates H1, H2. Normally, pulses pass H1 until counter Z1 counts to 60 whereon H1 is inhibited and H2 enabled to pass pulses to Z2, which can be preset by a control unit LW to count to a maximum value of from 0 to 8. If Z2 is preset to 4 a pulse T passes AND gate K11 every 64 timing pulses and acts to reset 1 and thus inhibit H2 and enable H1 and allows data to be read out of the delay line via gate H4 or written into the delay line via gate H6. Thus if Z2 remains preset at 4 a binary digit d, c, b, a is read out and Z2 must then be preset to 0 or 8 to read out another digit from the same register, or to 5, 6 or 7 to start reading out a digit from a different register. The pulse T also feeds a counter Z3 which normally counts up to four before emitting a pulse TST which indicates that a digit has been read out. Z3 can also be set to count to 3 if an idle time equal to 3 x 64 bits is required between the end of bit D16d and the beginning of the next A1a. The TST pulse enters a counter Z4 which emits a pulse TSP when it has counted 16 to indicate that all the digits in a register have been read out. Arithmetic operation.-A decimal digit may be entered into the stages F5-F2 of the shift register SK serially from the delay line via gate H4 or in parallel from a manual keyboard ZT. If a subtraction operation is to occur the gate H4 (illustrated in more detail in Fig. 2, not shown) passes the complement of the number from the delay line. Flip-flop F1 of the shift register is connected to an input of an adder as is flip-flop F5 while the output of the adder is connected to flip-flop F4. During an arithmetic operation one digit is stored in positions F5-F2 of the register and the other digit is fed in from the delay line. On the first shift the least significant bit of one digit is in F1 and the least significant bit of the other digit is in F5. These are combined in the full adder to give a result to be stored in F4 on the next shift. A correction circuit is included to take account of carriers in each b.c.d. from digit to digit. Shifts from F5 to F4 cannot take place during arithmetic operations. If no further multiplication is required the result can be fed from F2 back into the delay line. Alignment of decimal point.-A slide or knob on the keyboard is set to a position corresponding to the location of the decimal point and a binary number corresponding to the location is entered in a marker counter MZ, the decimal point remaining in the fixed position during calculation. During rotation of digits in the memory, digits are shifted to the next higher place until the number in the register corresponds to the place location of the decimal point. Output equipment can comprise line printers or indicator tubes, each digit being transferred in parallel to a register AR which can be connected to appropriate decoding circuitry.