Patent GB-1224801-A (GB)
Title: Methods of manufacturing semiconductor devices
IPC: H01L21/00
Filed: 1968-02-26
Abstract: 1,224,801. Semi-conductor devices. SONY CORP. 26 Feb., 1968 [1 March, 1967 (5)], No. 9240/68. Heading HlK. A semi-conductor substrate having a, surface on which either a raised portion or a recess is provided has two vapour deposited semiconductor layers of different conductivity types covering at least the surfaces of the raised portion or recess, and material is removed from the resulting structure to expose a cross-section of the deposited layer nearest to the raised portion or recess. Fig. 2E shows an N+Si monocrystalline substrate 21 having projections 22 formed by etching, with vapour deposited layers of P-type Si 23, N-type Si 24, N+-type Si 25, SiO 2  26, SiC 27 and polycrystalline Si 28 respectively formed thereon. The substrate 21 is ground and etched up to the line FF leaving discrete Si bodies isolated from a polycrystalline support 28 by insulating layers 26, 27. Electrodes are then applied to the exposed regions of the various layers to form an NPN transistor in each body 22-25. In Fig. 3C, N+, N and P type layers 33, 34, 35, respectively are vapour deposited on the surface of a P-type Si substrate 31, and the recess is finally filled by vapour deposited N+ type Si 36. The layers 33-36 are ground and etched down to the line DD and electrodes are applied as above to form a transistor isolated from the substrate 31 by a reverse-biased PN junction. Various modifications are described, the primary object being in each ease to increase the exposed area of the base region available for electrode application without increasing the thickness of the base region itself. All such modifications may be applied to both the configurations illustrated. In one such embodiment (Fig. 4, not shown) the side walls of the projection or recess are inclined to meet the surface at an angle other than 90 degrees. In another (Figs. 6, 7, not shown) the crystallographic orientation of the substrate is arranged so that more rapid crystal growth occurs during vapour deposition on the side faces of the projection or recess than on the face which is parallel to the main substrate surface. In another modification an alloyed surface region (89), Fig. 8 (not shown), is provided adjacent the exposed area of the base layer (83). The effective contact-making area of the base zone may also be increased by providing on the side walls of the projection or recess, but not on the face parallel to the main substrate surface, a diffused or vapour deposited layer of the same conductivity type as the base layer, this additional layer being situated immediately against the base layer itself (Figs. 9-12, not shown). Temporary masks of SiO 2  or SiC are used to define the zone over which this additional layer is formed. In a final modification diffused N + type emitter zones (134), Fig. 13 (not shown), are provided in a P-type substrate (131) prior to etching to define projections, each of which contains an N+ zone (134) surrounded by a part (135) of the P-type substrate. The base layer (136) and the remaining collector layers &c. are then vapour deposited and the substrate (131) is ground and etched down to a line (FF) to leave dielectric isolated individual transistors. The vapour deposition of Si in the various embodiments may occur from vapours of SiH 4  or SiHCl 3 , and Sb, As and P are referred to as dopants. Al may be used for ohmic electrodes and as the alloying material to increase the effective base contact area.