Patent GB-1458077-A (GB)
Title: Permanent storage charge-transferred and trapped memory
IPC: H01L27/105
Filed: 1974-05-24
Abstract: 1458077 Semiconductor memories ROCKWELL INTERNATIONAL CORP 24 May 1974 [4 June 1973 (2)] 23270/70 Heading H1K A memory structure comprising interfaces, where charge carriers can be trapped, located in an insulating layer on a semiconductor body is so constructed that packets of charge can be transferred through the body to beneath the interfaces by a charge transfer system of the CCD or BBD type. As described the interfaces are between a layer of silica thin enough to permit tunnelling and an overlying thicker layer of silicon nitride. The two phase system shown in Fig. 1 comprises a 100 orientated N-type silicon wafer with parallel channels 42 bounded by N+ inversion stopping regions 40. The interlaced and overlapping transfer electrodes, common to all channels, consists of four sets 30, 32, 34, 36 on different levels isolated from the wafer by insulation 24, those of set 34 forming MNOS trapping structures with each channel. Each channel has a diffused P + source region 44 which when forward biased feeds minority carriers into it. Alternatively the region is common to all channels and the first transfer electrode 30 divided to control transfer of charge into the respective channels, there being in both cases a corresponding P+ read out region common to the opposite ends of the channels. With suitable phasing of the control voltages the roles of source and read-out regions can be reversed or the source used to perform both roles. In operation charge packets representing digital or analogue information are introduced at the source and transferred to storage locations by phase control voltages in conventional manner. Alternatively potential wells are formed adjacent electrodes 34 and minority carriers generated selectively in them by illumination with a light pattern. Then a high negative writing voltage is supplied to electrodes 34 to cause electrons to tunnel through the oxide leaving a positive charge at the trapping interfaces dependent on the size of the charge packet. Information is read out by flooding the channel with charge by uniform illumination or preferably by applying such voltage to the electrodes as to form a continuous inversion layer to permit flow from the source diffusion, adjusting the voltages to restrict the charges to potential wells under electrodes 34, and simultaneously or subsequently reducing the voltage on 34 to saturate and spill charge from some of the wells leaving charges therein which are the complement of the stored information and then transferring these by charge coupled action to the output. Erasure is by application of a high positive potential to electrodes 34 causing tunnelling of electrons to neutralise the trapped charge. In one variant in which electrodes 30 are on the same level as electrodes 34 they also overlie storage sites, information being written into the sites under electrodes 30 and 34 on alternate cycles using four phase transfer voltages. In other variants the transfer electrodes are subdivided into sections controlling transfer and storage in selected channels only. The structures may be used as a short term CCD memory while long-term information is stored at the interfaces. In an important modification (Fig. 10) with improved transfer efficiency but reduced storage capacity the storage sites are located over side branches 270 (and optionally 271) of the channels information being brought as before to areas 234 of the channel and then transferred to the branch and stored in the overlying trapping interface by applying a gating voltage to electrode to open the branch, and a writing potential to electrode 260. Information is read out with the branches gated open until the residual charges have been transferred to the channels. Reference has been directed by the Comptroller to Specification 1,356,629.