Patent GB-1183158-A (GB)
Title: Data Processing System
IPC: G06F9/46
Filed: 1968-10-31
Abstract: 1,183,158. Data processing systems. INTERNATIONAL BUSINESS MACHINES CORP. 31 Oct., 1968 [13 Nov., 1967]. No. 51560/68. Heading G4A. In a data processing system, tasks are allotted to active units in accordance with a requirement vector for the task and a capability vector for each unit. The disclosed system is essentially as in Specification 1,158,889 (which is referred to) except regarding task allotment which is done as follows. A plurality of processors, and I/O channels share a common memory and each has an associated interaction controller, which communicate with each other over a common bus. Each controller has a unique 8-bit seizure code (having 4 ones and 4 zeros) and a unique index number. The index number has two octal digits each represented by an 8-bit byte consisting of (n + 1) ones followed by (7 - n) zeros, where n is the value of the octal digit. Each controller has a capability vector with a bit position for each class of processor operations and type and identity of I/O unit in the system, the bit being set to one if the processor or I/O channel associated with the controller has that capability, i.e. can handle that class of operation or is connected to that type or identity of I/O unit. Each task has an associated requirement vector with the same format as the capability vector, a bit being set to one if the corresponding capability is required for the task. Each controller also has a power vector which has n zeros followed by all ones, where n is a weighted sum of those bits of the corresponding capability vector which are set to one.. If a plurality of controllers apply bytes to the bus simultaneously, the bus effectively ORs corresponding bits. When a controller has control of the bus (see Specification 1,158,889) and wishes to allot a task, it applies a " task is being offered " signal to the bus, followed by the requirement vector serially by byte. Each controller whose processor or I/O channel is not busy ORs each byte on the bush with the corresponding byte of its capability vector and compares the result with the latter, dropping out of the sequence on inequality. Those controllers getting equality on every byte have the required capabilities and apply their seizure codes to the bus, then compare their seizure codes with the bus. Equality means only one of the controllers has the capability so this controller responds to equality by getting ready to receive task information. In the case of inequality, each controller still in the sequence applies its power vector to the bus serially by byte and compares the power vector bytes with the bush, dropping out of the sequence on inequality. Controllers not finding inequality have the minimum weighted sum of capabilities. These controllers apply their seizure codes to the bus and compare them with the bus. Equality means there is only one such controller, which then makes ready to receive task information. Inequality causes the controllers still in the sequence to apply their first index digits to the bus and compare them with the bus. Thosecontrollers getting equality apply their second index digits to the bus and compare them with the bus. The single controller now finding equality (i.e. that with the largest index number) makes ready to receive task information. The controller allotting the task compared the bus with zero at the time the seizure codes were first applied. Equality indicated no controller (whose processor or I/O channel is not busy) has the required capabilities. Inequality causes the task information to be applied serially by byte to the bus the next time it gives equality on comparison, with zero. The embodiment described in most detail dispenses with the uses mentioned above of the seizure codes.