baber/WOPTO huggingface dataset:
Patent JP-S62225489-A (JP)
Title: Stern pressure fluctuation reducing device
Inventor: SATO RYUICHI
IPC: B63H5/07
Filed: 1986-03-26
Abstract: PURPOSE:To mitigate the quick increase or decrease of the cavity volume and reduce the water pressure fluctuation by providing nozzles filled with a porous member at their opening sections on both broadsides of a stern section and feeding fine bubbles to a specific region of a propeller. CONSTITUTION:Nozzles 2 filled with a porous member such as sintered metal at their opening sections on both broadsides of a stern section 3 between the axis of a propeller 1 and a keel line 4 and on a stream line where water flows in toward the propeller 1 when a ship is cruising at a cruising speed, and fine bubbles are fed to a region A where the cavity volume change of the propeller 1 is violent. Accordingly, the quick increase or decrease of the cavity volume generated on propeller blades is mitigated, the water pressure fluctuation is efficiently reduced, the noise or erosion of the propeller can be prevented from occurring, and the hull vibration can be effectively reduced.
Patent JP-S63232450-A (JP)
Title: Manufacture of semiconductor device
Inventor: UMEZUKI AIICHIRO
IPC: H01L21/60
Filed: 1987-03-20
Abstract: PURPOSE:To prevent an internal wiring from being applied with excess presses due to pressure of a bump by depositing one part of a barrier metallic layer onto the side surface of the opening in a mask layer formed onto the barrier metallic layer as a bump formation region through plasma treatment, plating the side surface of the opening of the mask layer with a bump metal and shaping a measure-shaped bump. CONSTITUTION:A first opening 5 from which an internal wiring 3 is exposed is formed to an insulating film 4 coating the internal wiring 3 on a substrate 1. A barrier metallic layer 6 is applied onto the opening 5, and a mask layer 7 with a second opening 8 including the region of the first opening 5 is shaped onto the layer 6. One part of the barrier metallic layer 4 exposed to the second opening 8 is deposited onto the side surface of the second opening 8 through plasma treatment, and the base and side surface of the second opening 8 are plated with a bump metal and a measure-shaped bump is shaped and the internal wiring 3 is led out. Accordingly, application of excess presses to the internal wiring 3 to cause cracks is avoided in a bump electrode formed because the bump has a measure shape and is hollow.
Patent JP-S63231696-A (JP)
Inventor: KOSUDA MAKOTO
IPC: G07G1/06
Filed: 1987-03-20
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S56162505-A (JP)
Title: Frequency multiplying circuit
Inventor: MOCHIGURI SHIGEHARU
IPC: H04N7/035
Filed: 1980-05-19
Abstract: PURPOSE:To facilitate IC-implementation by simplifying circuit constitution, and to eliminate fluctuations of frequency even if an input waveform is distored, by using a differential couple of transistors and a constant current source to generate a sampling clock signal, etc., used for the character broadcasting of TV. CONSTITUTION:Transistor (TR) Q1 and Q2 are used in a differential couple, and a TRQ3 as a constant current source to constitute a differential amplifier. A signal (c) for bit synchronization is inputted to a transformer 9 from an input source 8 via a signal-source equivalent resistance R1 and a TRQ4. The transformer 9 resonates at the frequency of the signal (c) through a resonating circuit and its secondary side is connected to the TRQ3 via the TRQ1 and a capacitor C2. The collector of the TRQ2 is connected to an output terminal 12 via a load 10 having impedance Zl for the attenuation of the DC component and dominant wave component of an output signal, and a filter and limiter circuit 11. To the base of the  TRQ3, a clock line gate signal (f) from a terminal 13 is applied as a DC bias. In this constitution, a signal having a frequency double that of the signal (c) appears at a terminal 12.
Patent JP-H08259081-A (JP)
Title: Discharged paper loading device and image forming device
Inventor: FUTAGAWA JIRO
IPC: G03G15/00
Filed: 1995-03-24
Abstract: PURPOSE: To facilitate the confirmation and taking out of sheet sheaves loaded on the side of a discharged paper port on a discharged paper loading tray having a state where another discharge paper loading tray exists adjacently or a part of an image forming device body protrudes adjacently. CONSTITUTION: Drawing out plates 10A, 10B which can draw out sheet sheaves S1, S2, S3 loaded on discharged paper loading trays 2, 3, 4 toward a tip in a paper discharging direction are provided on the discharged paper loading trays 2, 3, 4 attached at fixed intervals in the vertical direction of an ascending and descending member 5. For instance, since a part of a compound machine body 1 protrudes adjacently toward the upside of the tray 2, a small-size of sheet sheaf S1 loaded on the side of a discharge port on the tray 2 is difficult in confirmation and taking out, but it becomes easy in the confirmation and taking out by drawing out it through the drawing out plate 10A.
Patent JP-H07281928-A (JP)
Title: Display device
Inventor: MIYABAYASHI HIROTAKA
IPC: G06F3/048
Filed: 1994-04-04
Abstract: PURPOSE:To directly output the initial state contents and the error contents to an external equipment by detecting the set initial state and its error, storing and displaying the programs the data, etc., and performing the communication with the external equipment to decide the output destination of the data. CONSTITUTION:A display device 100 performs the communication with an external equipment by a communication means 101 and sets an initial state by an initial state setting means 102. This initial state is detected by an initial state detector means 103, and the error of this detection data is detected by an error detector means 104. Then the error detection data are stored in a storage means 105. The initial state or the display data are shown on a display means 106. The output destination of the contents of the initial state or the error contents is decided by a data output destination deciding means 107. Thus the initial state contents and the error contents can be directly inputted to and outputted from the external equipment.
Patent JP-S60209614-A (JP)
Title: Valve apparatus for four-cycle engine
Inventor: ONDA TAKAMASA
IPC: F01L5/04
Filed: 1984-04-03
Abstract: PURPOSE:To raise the intake and exhaust efficiency of an engine, by increasing the effective volume of a combustion chamber by constituting an intake valve and an exhaust valve by a piston valve. CONSTITUTION:An intake valve 9 and an exhaust valve 10 are constituted respectively by piston valves 9a, 10a, and opening and closing of an intake port 7 and an exhaust port 8 is controlled by sliding the piston valves 9a, 10a in valve inserted chambers by shafts 14b, 15b turned at the half speed of a crankshaft via connecting rods 14c, 15c. When the piston valves are moved from the top dead point to the bottom dead point, the ports 7, 8 are opened on the side of the bottom dead point of the middle point of the stroke. By employing such an arrangement, the effective volume of a combustion chamber is increased and the intake and exhaust efficiency of an engine is raised since the piston valves do not project into the combustion chamber as different from the lift valves. Therefore, it is enabled to improve the performance of a four-cycle engine.
Patent JP-S56162860-A (JP)
Title: Semiconductor device
Inventor: WADA MASASHI
IPC: H01L27/105
Filed: 1980-05-19
Abstract: PURPOSE: To securely prevent the parasitic thyristor effect of a semiconductor device by forming a high impurity density layer on the surface of a substrate between the circuits in case that a circuit for generating a substrate current is integrated with a C-MOS.  
     CONSTITUTION: The C-MOS inverter of the first circuit 2 is formed by forming a p-channel MOS transistor having a p +  type source 22, a drain 23 and a gate electrode 24 in an n type well 21 formed on a p type substrate 1, forming an n-channel MOS transistor having an n +  type source 25, a drain 26 and a gate electrode 27 out of the well 21 and connecting them to one another. The nonvolatile memory cell of the second circuit 3 is formed of an n +  type source 31, a drain 32, a floating gate 33 and a controlling gate 34. A p +  type layer 4 is formed between the first and  the second circuits 2 and 3, and is connected to a power source VSS (ground potential). Thus, the substrate current can be effectively absorbed. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H07278973-A (JP)
Title: Roving guide for fine spinning frame
Inventor: KASAHARA TAISHI
IPC: D01H13/04
Filed: 1994-04-04
Abstract: PURPOSE:To prevent from generating fuzzes on a roving by suppressing friction resistance between the roving and a roving guide to a small value. CONSTITUTION:A supporting shaft 9 is extendedly installed between respective rows for winding rovings which are lined with two rows in one side and hung over a fine spinning machine frame on both left and right side. On the supporting shaft 9, a guide roller 17 formed with guiding dent on its periphery is arranged rotatably and movably in the direction of the supporting shaft 9 at a position corresponding to a roving releasing position of a roving bobbin B which lies on the both side of the supporting shaft. On the supporting shaft 9 a regulating material 19 is fixed on the both side clamping each guide roller 17. Each guide roller 17 moves along the supporting shaft in the range clamped by regulating materials 19 by receiving force in the direction of the supporting shaft 9 from the roving R corresponding to a variation of a roving path due to decrease of a wound diameter of the roving bobbin.
Patent JP-S51142621-A (JP)
Title: A motor driving control device
Inventor: KURIYAMA SHIGERU
IPC: H02P7/285
Filed: 1975-06-04
Abstract: PURPOSE: When controlling the speed of a motor by changing the conduction quantities of the transistor connected with the main circuit that contains the motor of vehicle driving, the use of the transistor within allowable losses prevents electric noises. 
     COPYRIGHT: (C)1976,JPO&Japio
Patent JP-H05274284-A (JP)
Title: Recognizing device for inter-processor communication
IPC: G06F15/177
Filed: 1992-03-25
Abstract: PURPOSE:To recognize whether or not communication is surely executed concerning the recognizing device of inter-processor communication. CONSTITUTION:A system is constituted in such a way that data which a first processor 31 announces to the second processor 32 and a memory address where data is stored are respectively stored in a data register for comparing 18 and an address register for comparing 15, the contents of the respective registers are compared with data and the memory address announced from the first processor and outputted to a memory by the second processor in a second comparator 34 and the first comparator 33, and inter-processor communication is judged to be normal at the time of coincidence.
Patent JP-H08265409-A (JP)
Title: Telephone set provided with automatic informing function
Inventor: TABUSE TOSHIAKI
IPC: G08B25/08
Filed: 1995-03-24
Abstract: PURPOSE: To provide a telephone set provided with an automatic informing function capable of calling a specific contact party by simple operation excluding key operation or the like. CONSTITUTION: The telephone set is provided with a hook detecting circuit 4 for detecting the off-hook of a hand set 1, an informed party registering memory 7 for registering the telephone number of an informed party, an automatic calling means 6, and a signal processing part 5 having a timer function. When any ten-key 8 is not depressed within a prescribed time after hooking off the hand set 1, the means 6 is driven and the telephone number registered in the memory 7 is automatically called.
Patent JP-H01239801-A (JP)
Title: Baking method for positive coefficient thermistor material
Inventor: TAKAGAKI MASAMI
IPC: H01C7/02
Filed: 1988-03-18
Abstract: PURPOSE:To obtain a sintered material of an object according to a baking method without working or the like by scattering ZrO2 powder having specific particle size between molded pieces, securing several superposed molded pieces with a tape, then aligning them in parallel, and baking them. CONSTITUTION:ZrO2 powder 4 having 50-100 meshes is scattered between molded pieces 3, a plurality of the superposed pieces 3 are secured with a tape 5, aligned and baked. For example, after temporarily baked powder having a predetermined composition is wet pulverized by a ball mill, 10wt.% of 5% PVA aqueous solution is added as a binder, wet mixed, and granulated. A molded piece of rectangular shape is obtained with the granulated powder under the pressure of 1ton/cm<2>, ZrO2 powder 4 having 50-100 meshes is scattered between the pieces 3, and the several pieces are so wound fixedly with the tape 5 that the powder 4 does not drop. The pieces 3 are so aligned on a ZrO2 plate in a sheath 6 made of cordierite that the part of the piece 3 in contact with the bottom of the sheath 6 is reduced, and baked at 1300 deg.C for 2 hours in the air to obtain a sintered material.
Patent JP-H03190162-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: KIN SEITAI
IPC: H01L21/822
Filed: 1990-03-15
Abstract: PURPOSE: To obtain a stack-trench merger type capacitor with increased capacitance of a capacitor by using the surface of a trench being formed on a semiconductor for the first electrode of the capacitor. CONSTITUTION: A field oxide film 101 is selectively formed on a first- conductivity type semiconductor substrate 100, a gate electrode 2 is formed on an active region via a gate oxide film 1, a second-conductivity type source region 3 and a drain region 4 are formed at both sides, a first-conductive layer 5 that is connected to the gate electrode is formed, a trench 10 is formed on the semiconductor substrate in the source region 3, and a second-conductivity type impurity doping region 13 is formed on the surface.  Then, a first insulating layer 6 is formed on the gate electrode 2 and the first-conductive layer 5, a second polycrystalline silicon layer 12b where the second-conductivity type impurity is doped is formed, a dielectric film 14 is formed on the inner surface of the trench 10, a flattened fifth conductive layer 18 with an etching rejection layer 16 and a fourth-conductive layer 17 is formed, thus obtaining a stack- trench merger type structure.
Patent JP-H05274048-A (JP)
Title: Temperature control system for sheet heater
IPC: B29C51/46
Filed: 1992-03-25
Abstract: PURPOSE:To immediately perform the changing operation of a molding condition and to prevent the occurrence of mis-setting by dividing upper and lower heater groups into plural blocks and controlling heating so that control temperature data of each block coincides with a measured temperature. CONSTITUTION:A function block A essentially consists of a heater assignment control part 3 and an assignment data storage part 4. The output of an input part 1 where arrangement and assignment information of heaters is inputted is led to the heater assignment control part 3, and the assignment data storage part 4 and a display part 2 are connected in both directions. A function block B consists of a system control part 5 and a temperature data storage part 6, and a function block C consists of a heater control part 7 which turns on/off each heater. Each output of the heater control output part 7 is connected to each heater of a sheet heating part 10 constituting a function block D. The sheet heating part 10 consists of an upper heater group 8 and a lower heater group 9, and an object 11 to be heated is inserted between both heater groups.
Patent JP-S61225921-A (JP)
Title: Synchronizing signal separation circuit
Inventor: MIYANO YUICHI
IPC: H03K5/00
Filed: 1985-03-30
Abstract: PURPOSE:To obtain an accurate frame synchronizing signal by detecting a synchronizing pattern from a data when the data comprised of the synchronizing pattern at every frame is inputted. CONSTITUTION:A digital data EFMI and a system clock PK are fed to a frame synchronizing pattern detection circuit 26, the frame synchronizing pattern is detected from the data EFMI synchronously with the clock PK and frame synchronizing signal SYNC is generated. The clock PK is fed to a frame counter 27 and when the clock PK is counted by nearly 1 frame, a window pulse WD is outputted mechanically from a gate signal generating circuit 28. The pulse WD is fed to an AND circuit 30 via an OR circuit 29. The signal SYNC is fed to the circuit 30 and when the period of generation of the pulse WD is coincident with that of the signal SYNC, the signal SYNC is outputted from the circuit 30. Thus, the accurate frame synchronizing signal is obtained.
Patent JP-S62226522-A (JP)
Inventor: SHOJI NOBUYOSHI
IPC: H01H50/00
Filed: 1986-03-27
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S54907-A (JP)
Title: Key telephone system of electronic type
Inventor: TONOMURA ZENSHI
IPC: H04M1/82
Filed: 1977-06-06
Abstract: PURPOSE:To enable to generate audible sound at terminal, even if the audio communication path is occupied, by using the pulse train in data from a central control unit to terminal units as a sound source.
Patent JP-S60210894-A (JP)
Inventor: MATSUURA SHIYUUICHI
IPC: H05K3/00
Filed: 1984-04-04
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60211290-A (JP)
Title: Air heating type evaporator
Inventor: HOSOI KAZUO
IPC: F28F17/00
Filed: 1984-04-04
Abstract: PURPOSE:To enable to promote the thawing of an air heating type evaporator by a method wherein the gas leading out of a heat exchanger in evaporating process is flowed through a connecting pipe for heating system into a heat exchanger in thawing process. CONSTITUTION:When thawing is difficult, a connecting pipe 15 for heating system is provided in order to connect a connecting pipe 12, which connects the inlet side pipe 6A of a heat exchanger 7A and the inlet side pipe 6B of a heat exchanger 7B and in which selector valves 11A and 11B are provided, with a connecting pipe 14, which connects the outlet side pipe 8A of the heat exchanger 7A and the outlet side pipe 8B of the heat exchanger 7B and in which selector valves 13A and 13B are provided. In addition, a path running from the connecting pipe 14 through the connecting pipe 15 for heating, the connecting pipe 12 and the valve 11B to the pipe 6B is made. Thus, the gas, which is produced in the heat exchanger 7A in evaporating process by vaporization and the temperature of which rises up to the atmospheric temperature, flows in the heat exchanger 7B in regenerating process, resulting in heating the heat exchanger 7B from inside so as to supply to the users while thawing the frost.
Patent JP-H01242761-A (JP)
Title: Ultra high strength steel having low yield ratio and its manufacture
Inventor: UCHIDA KIYOSHI
IPC: C22C38/46
Filed: 1988-03-23
Abstract: PURPOSE:To obtain the title steel having high safety by subjecting a low alloy thermal refined steel having specific componental compsn. to quenching and tempering under specific conditions and depositing a Cu phase into a martensitic structure. CONSTITUTION:The steel constituted of, by weight, 0.20-0.50% C, <=0.40% Si, <=1.20% Mn, 0.50-4.50% Ni, 0.50-3.50% Cr, 0.30-1.50% Mo, 0.05-0.30% V, 0.30-2.50% Cu, <=0.010% P, <=0.005% S and the balance consisting of inevitable impurities with Fe is refined. The steel ingot is rolled and is quenched from the temp. range of Ac3 transformation point or above into a martensitic structure. The steel is thereafter tempered at the temp. range of 400-650 deg.C to deposit a Cu phase into the martensitic structure. By this method, the ultra high strength steel suitable for a machine structure, etc., and having about <=95% yield ratio can be obtd.
Patent JP-S60210044-A (JP)
Title: Transmitting and receiving device of error correction code
Inventor: OOSHIMA GOROU
IPC: H03M13/00
Filed: 1984-04-03
Abstract: PURPOSE:To monitor the generating frequency of error correction pulses and to simplify the set of synchronization by applying scrambling to both data obtained before and after coding with a transmitter then descrambling both data obtained before and after decoding with a receiver respectively. CONSTITUTION:A transmission input data signal 100 of a transmitter of an error correction code transmitting/receiving device is added with the output of a scrambling circuit 1 by an adder 21 and supplied to a coder 2. The coder 2 performs the error correction coding. Then the output of the coder 2 is added with the output of the circuit 1 by an adder 22, and the output of the adder 22 is outputted to a transmission line 3 as a transmission output data signal 101. A reception input signal 102 fed from the line 3 is added with the output of a descrambling circuit 5 by an adder 23 and supplied to a decoder 4. The output of the decoder 4 is added with the output of the circuit 5 by an adder 24. Then a reception output data signal 103 is outputted. Then the synchronization timing of the circuit 5 is monitored by an error correction pulse fed from the decoder 4.
Patent JP-H05276135-A (JP)
Title: Parity addition system for multiplex system
IPC: H04J3/14
Filed: 1992-03-25
Abstract: PURPOSE:To prevent the generation of a parity error at a reception side even at the time of switching a multiplex system. CONSTITUTION:This system is equipped with parity arithmetic addition parts 10 and 11 of a present system and one or more than two preliminary systems. The parity arithmetic addition part 10 or 11 of the present system prepares a present parity signal based on the previously prepared parity signal and the present data signal, and the parity arithmetic addition part 11 or 10 of the preliminary system prepares the present parity signal based on the previously prepared parity signal and the present data signal. This device is equipped with a monitor control part which operates the switching control of the present/ preliminary systems of a multiplex system, and each parity arithmetic addition part is operated as the parity arithmetic addition part of the present system, the present and preliminary system, or the preliminary system, according to the switching control of the present/preliminary system by the monitor control part. And also, each parity arithmetic addition part is operated as the parity arithmetic addition part of the preliminary system at the time of applying a power source.
Patent JP-S51143714-A (JP)
Title: A method for manufacturing heavy fibers
Inventor: NAKAMURA KATSUTOSHI
IPC: D02J1/04
Filed: 1975-06-06
Abstract: PURPOSE: To manufacture a fiber of a high apparent specific gravity by removing microvoids contained in a weighted fiber to which added is a filler for obtaining a fiber used for a fishing net and so on of a high sinking speed. 
     COPYRIGHT: (C)1976,JPO&Japio
Patent JP-H08261191-A (JP)
Title: Water supply device of fixed delivery pressure
Inventor: CHOJI YUKIHIKO
IPC: F04D15/00
Filed: 1995-03-27
Abstract: PURPOSE: To simplify a control device and reduce a cost of manufacture, in a water supply device of fixed delivery pressure. CONSTITUTION: A device comprises a centrifugal pump 24 with a flow path of an impeller branching from the halfway, drive motor 28 of driving the centrifugal pump 24 and a control device 29 of controlling operation and stop of the centrifugal pump 24. Water, in the point of time delivered from the centrifugal pump 24, is controlled already to a fixed pressure, to eliminate also necessity for pressure reducing control by a pressure reducing valve or the like and to eliminate necessity for controlling also a rotational speed of the pump itself.
Patent JP-S52149999-A (JP)
Title: Display unit
Inventor: TAKESHITA YUTAKA
IPC: G09F9/00
Filed: 1976-06-09
Abstract: PURPOSE: Memory holding time is prolonged and power consumption is reduced by providing a capacitor in series to the counter electrode and segment electrodes of an electrochromic (EC) display unit. 
     COPYRIGHT: (C)1977,JPO&Japio