Patent GB-1233532-A (GB)
IPC: H01Q3/46
Filed: 1967-03-31
Abstract: 1,233,532. Aerials. MINISTER OF AVIATION SUPPLY. 1 July, 1968 [31 March, 1967], No. 14838/67. Heading H4A. [Also in Division G4] An electromagnetic wave aerial system includes a plurality of elementary aerials connected to signal paths including respective phase shift means, a separate operating signal being applied to each phase shift means to control the amount of phase shift, a plurality of operating signals being generated by means which forms two series of multiples and selectively adds a multiple from each series to form an arithmetical progression series of sums. In Fig. 2, an 8-bit binary number d# is gated to a register SA and applied to 8-bit comparators CUA1-CUA7 with or without shift to high order and/or ones-complementing as shown, for comparison with a binary counter CA driven by clock pulses from a gate CG#1. High order bits lost due to the shifts do not matter since they correspond to integral multiples of 360 degrees. The clock pulses also pass through gates PTGA1-PTGA7 until those are closed at equality in respective comparators CUA1- CUA7. Thus gates PTGA1-PTGA7 respectively pass numbers of pulses representing d#, 4d#, -4d#, 8d0, -8d#, 16d#, -16d#, the negative quantities being in ones-complemented form i.e. 255-n pulses to represent -n. The pulses for d# increment a binary counter SB preset with the binary number d# shifted left one position, to form 3d#. This is applied to a comparator CUB1, and in ones-complemented form to a comparator CUB2, and the contents of the register SA are applied with or without left shift and/or ones-complementing as shown to comparators CUB3-CUB8. These inputs to comparators CUB1-CUB8 are compared therein with a binary counter CB driven by clock pulses from a gate CG#2 to terminate, on equality, the passage of these same pulses through respective gates PTGB1-PTGB8 which thus pass numbers of pulses representing 3d#, -3d#, d#, -d#, 2d#, -2d#, 4d#, -4d# respectively. A similar arrangement then produces pulse trains for the same multiples of another number d#, using clock pulses from gates CG#l, CG#2. A matrix array of phase shifter units for electronic scanning of a radar aerial has column wires to which are applied the pulse trains from gates PTGA2-PTGA7, PTGB1-PTGB8 (some wires each adding the trains from a gate from each of these two sets) and row wires to which are applied the similar pulse trains relating to d#. Each phase shifter unit includes an 8-bit binary counter which counts any pulses applied to its corresponding row and column wires so that in fact the count represents md# + nd# where m and n are integers in the range -15 to 15 depending linearly on the position in the matrix. The three most significant bits in the counter are stored in silicon-controlled rectifiers to control respective p-i-n diode phase shifters, then the counter is reset to permit calculation of the next phase shift for new d#, d#. The resetting is to a non-zero number (a) to compensate for a non-planar phase front at the input face of the aerial matrix due e.g. to illumination of the aerial from a single horn, (b) to convert negative quantities from ones-complement to twos-complement form, (c) to round off the three most significant bits in the counter (by setting the fourth bit to 1). Fig. 2 also shows two ring counters RC6, RC4 to control the pulse train generation and phase shifter units respectively, under control of signals from a computer saying it is ready to supply d# and d# and requires advance to the next scan position, and interlocked so that only one ring counter can operate at a time.