Patent GB-1421568-A (GB)
Title: Supervision arrangement for a pulse code-modulation system
IPC: H04J3/14
Filed: 1973-08-13
Abstract: 1421568 Supervising pulse coders and decoders PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 13 Aug 1973 [16 Aug 1972] 38206/73 Headings H4L and H3H Means are provided for testing the common coder and decoder of a time division multiplex P.C.M. terminal station at the same time during a signalling or synchronizing time slot. As shown in Fig. 1, in a system comprising 32 channels, the 16th channel being used for signalling and the 32nd for synchronizing, the incoming signals are sampled by gates KS1 to KS32, converted to an 8-bit code at C and supplied via gating circuit TS1, where the signalling and synchronizing information is inserted, to the output A. The samples are quantized in accordance with a non-linear characteristic of the type consisting of a plurality of linear segments of differing slope, Fig. 2, and the first bit of a codeword indicates polarity, the next three bits denote the segment in which the amplitude sample is located and the last four bits indicate the position of this amplitude level within a segment. Each segment is divided into sixteen equal parts so that for low amplitude values the subdivision is finer than for large amplitude values. Incoming P.C.M. signals at E are supplied via gating circuit TS2, where the signalling and synchronizing signals are extracted, to a decoder D, the resulting amplitude samples being distributed by channel gates KE1 to KE32. A frequency of 125 Hz derived from the clock frequency of 4 kHz in clock pulse generator TG is supplied via gate TS8 to a four-stage counter Z in a test pulse pattern generator PG, the outputs of the counter stages being stored in the first four stages of a shift register SR under the control of receiver clock pulses of frequency 2048 Hz. To complete the test codeword of eight bits, the shift register includes four stages in which fixed values are stored so that in the test pulse pattern the first four bits are periodically changed by generator TG and the remaining four bits are fixed and define a given amplitude level (denoted by U 1  to U 8 , Fig. 2) in the middle of a segment. The output of shift register SR is supplied via gate TS3, which is enabled by pulse K16E for channel gate KE16, to the decoder D where it is converted into the corresponding analogue value. Gate KE16 is enabled after a delay TD equal to the decoding time and the said analogue value is supplied to a filter TP, stored for a short period, and passed to the gate KS16 on the transmit side. Gate KS16 is enabled by pulse K16S and simultaneously the gate TS1 is decoupled from the output A for the insertion of signalling information. The amplitude sample from gate KS16 is coded at C and supplied via gate TS4, enabled through delay TC by pulse K16S, to a store S under the control of 2048 kHz transmission clock pulses. The first four bits are stored in stages B1 to B4 of the store S and are compared at V with the contents of the counter Z, any difference causing alarm pulses to be supplied via gates TS5, TS6 to an integrator JG. To prevent false alarm, gate TS5 is blocked by pulse K16S delayed at TC and gate TS6 is enabled by a pulse Sp1 derived via gate TS7 from the third, fourth and fifth divider stages of clock pulse generator TG. When an alarm occurs, the alarm pulses are integrated and cut off gate TS8 so that clock pulses do not reach the counter Z. By this means the coding segment at which the error occurs can be detected. The counter Z may be provided with additional stages so that other amplitude levels may be checked.