Patent GB-727012-A (GB)
Title: Improvements in or relating to electric information storage circuits and to electriccalculating circuits
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: G11C19/20
Filed: 1949-11-25
Abstract: 727,012. Digital electrical. calculating-apparatus. STANDARD TELEPHONES & CABLES, Ltd. Nov. 24, 1950 [Nov. 25, 1949], No. 30269/49. Class 106 (1). An electrical information storage circuit comprises a chain of series-connected static electrical switches on which information is stored in the form of a pattern of operated and unoperated switches, means for progressing the pattern as a whole along the chain of switches and means for either (i) transferring some of the information to a second stepping chain and then the remainder to a third stepping chain, or (ii) combining the information with that from another chain and transferring the result to a further chain. In its first form the invention comprises a stepping chain P, Fig. 1, registering information in the form of a binary lumber which is progressed towards an auxiliary circuit A by stepping pulses from a pulse generator G. The auxiliary circuit directs a predetermined number of binary digits to a second stepping chain Q and then, under the control of a counter C, switches over to direct the remaining binary digits into a third stepping chain R. In the principal embodiment of the second form of the invention, a binary number is stored on a chain of series-connected coldcathode gas discharge tubes S35, S34 ... S1, Fig; 11A, with the lowest digit at the right-hand end. A fired tube represents a digit " 1 and an unfired tube digit " O ", and by supplying stepping pulses to all the cathodes simultaneously the number pattern can be stepped to the right, through tubes X2, X4 and X8, as described in Specification 663,574, [Group XXXIX]. By extracting the number pattern at various points and combining the results, various arithmetical operations can be performed. For example, assuming that the binary number 111 (seven) is to be multiplied by 1010 (ten): with the multiplicand set up on the storage chain thus:- the outputs from tubes X2 and X8 during the subsequent stepping operation would be equivalent to twice, and eight times the multiplicand respectively. By combining these outputs, with proper regard to carry-overs, the required multiplication (111 Î 1010=1000110) is achieved. The embodiment shown in Figs. 11A and 11B provides for calculations of the type: AB+C, the number C being registered on a further storage chain D8, D4, D2, D1. During the interval between each two stepping pulses a cycle of operations takes place under control of a plsue generator and counter causing various gates to be opened at times t1 ... t5, as indicated in the drawings. Tubes OA, OC and 2C in the trigger pairs OA/1A, 1C/OC and 2C/RC are conducting initially. Assuming a multiplier of 1010, as above, then at t1 a positive pulse blocks rectifier MR2 and, if the tube X2 is conducting, provides for the passage of a positive pulse to fire tube OA. After t1, therefore, the condition of the trigger pair OA, 1A indicates the value of the appropriate digit in the X2 partial product. At t2 the tube X8 is monitored in a similar way; the presence of a " 1 " digit, represented by the conducting state of the tube, causing reversal of the trigger pair 0A, 1A. At t3 the tube D1 is monitored and the resulting pulse, if any, applied to the trigger pair 0A, 1A as before. Each time the tube 0A fires, a positive pulse is transmitted from its cathode to reverse a second trigger pair 1C, OC, and each time the tube OC fires a pulse fires tube 2C in the trigger pair 2C, RC. The tube RC is fired at t1 to restore this last trigger at the beginning of each cycle. At t4 the tube 1A is monitored and, if in the conducting state, a pulse from its cathode fires an output tube OT which, in turn, fires tube S35 at the left-hand end of the storage chain. Thus at each step the corresponding digits of the numbers A, B and C, and also the " carry " (if any) from the last step, are registered and, in effect, summed by the three trigger pairs: 0A/1A, 1C/0C, and 2C/RC. If all the inputs total 1 only trigger 0A/1A is reversed, tube 0T is fired at t4 and the result digit 1 is entered at the L.H. end of the storage chain S35 ... S1. If the inputs total 10 (two), 0A/1A is brought back to normal and the tube 1C is fired so as to register a " carry " which will be fed back to 0A/1A for the next step. Similarly the trigger pair 2C/RC registers a carry of two when the sum of the inputs is 100 (four).. Other embodiments are adapted for division (Fig. 2, not shown), addition and subtraction (Fig. 4, not shown), and an adding or translating network, similar in principle to the arrangement of trigger circuits in Fig. 11B, but employing electromagnetic relays, is also described (Fig. 8, not shown). Specification 692,415 also is referred to.