Patent GB-1022897-A (GB)
Title: Program-controlled electronic digital computers
IPC: G06F12/08
Filed: 1964-06-19
Abstract: 1,022,897. Electronic digital computers. TELEFUNKEN PATENTVERWERTUNGSGESELLSCHAFT m.b.H. June 19, 1964 [July 17, 1963], No. 25460/64. Heading G4A. In a programme-controlled digital computer having a relatively high-speed store and a main store of lower speed, the address of an operand is found by adding the contents of a high-speed store location to a modification factor contained in the instruction. Instructions are of the form shown at 10 and contain the following parts: b, the function; k, the address of an operand contained in the high-speed store 1; i, the address of a high-speed store location the contents of which contain an address in the main store 2, +p, the modification factor; m, a single bit indicating the sequence of operations. One location in the high-speed store is reserved to contain the address of the next instruction. Fig. 2 shows typical sequences of operations in the main store H Sp and the high-speed store S Sp, the speeds of which are in the ratio of 1: 4. They are both magnetic core stores, the main store using cheaper store cores and having a greater storage capacity. The various stages are as follows: Read an instruction into the register 10 (LB); rewrite this instruction into the main store (SB). During this second halfcycle a high-speed store cycle is executed as follows: read a main store address from the high-speed store location i into the register 9 (LA), i being present in the high-speed store address register 3; rewrite this address into the location i (SA); transfer the modification factor +p into the computing register 14, add the address at present in the register 9 and store the result in the register 9 (M). The address now formed in the register 9 is transferred over line 17 to the main store address register 5. The operand is now read from the main store location into the register 10 (LO on the upper line). At the same time the second operand is read from the high-speed store location k, complemented if necessary or otherwise prepared, and rewritten into the location k (LO(K)SO). The first operand is rewritten into the main store (SO) and during this time the next instruction address is increased by 1 and rewritten into its high-speed store location (LZ Z SZ). The first operand is then transferred to the computing register 14, and the second operand, already prepared, is read into the register 9 again LO). The operation then takes place (R) and the result is written into the high-speed store location k (SE). During this operation the next instruction is transferred from the main store location to the register 10 (LB) so that there is no gap in the operation of the main store. The second line of Fig. 2 shows the sequence if the result is to be written into the main store, and the third line shows the sequence if the address i is to be modified before the instruction is rewritten into the main store. This is of use in programming loops. Whether modification takes place before or after the instruction is rewritten is determined the value of the bit m. The arithmetic unit 13 is used for the address modification and incrementing the address of the next instruction as well as for performing calculations. To ensure that no parts of the instruction are lost, two buffer registers 15, 16 each of 4 bits are provided to store the address k and the function b respectively.