Patent GB-1494505-A (GB)
Title: Data processing system
IPC: G06F7/00
Filed: 1974-12-12
Abstract: 1494505 Data processing HONEYWELL INFORMATION SYSTEMS Inc 12 Dec 1974 [13 Dec 1973] 53773/74 Heading G4A In a data processing system in which instructions are effected on data fields, each data field has an associated descriptor defining the characteristics of the data (e.g. its length, type of coding) at the execution of each instruction the descriptors being tested to determine whether the characteristics of the data are compatible with the instruction and the two or more items of data with each other, the instructions only being performed if the test is successful. A data file has one or more pages (100, Fig. 1, not shown) assigned to it, each page having a header (102) pointing to records (103-106) each having a record descriptor and data field. Each data field has an associated descriptor (108) which may be incorporated in the same page structure or individually addressable. Since a program may be utilizing the data in a different form, a descriptor (112) defines the attributes of the data anticipated by the program. Data processing system.-The system comprises four semi-conductor memory modules (301, Fig. 3, not shown) interfaced via a sequencer (302) to an input/output controller (320) controlling e.g. tape or disc stores and a CPU (300) the latter including a read only micro program store (310), a data management unit (306), an address control unit (307) and an ALU (312). A buffer (304) stores the most recently or most frequently used data in the form of pages, a directory (305) keeping an index of pages in the store (304), address control unit (307) including an associative store with the base addresses of the most recently used memory segments and their segment number. Operation.-An instruction in instruction register 500 (Fig. 5) which comprises an op code, a bit to indicate direct/indirect addressing and an address syllable in the first word and an address syllable and two general registers (to receive the addressed data) in the second word is used to access the first word of a data descriptor which points to the location of the segment containing the operand and the displacement within the segment. If tag bits (i.e. the bits 0, 1) are 01 a second word (part of the extended data descriptor) is fetched (either from main memory or the buffer store) and bits 36-38 are tested to determine whether a further word should be fetched, both these words being stored in working registers in the local store. The first word is transferred to register AC. The address syllable in a second instruction word is then used to access a second data descriptor, the second extended data descriptor being held in the register AD. The key fields (bits 48-55) of each of the descriptors are then transferred to registers AZ, AB and subsequently compared in calculator 516. If they are not equal a termination routine is branched to, which may for example correct a scaling point factor. If the second operand may be written into (indicated by bit 39 being "zero") bit positions 40-47 which indicate the type of coding of each of the words are tested to ensure that they represent a legal data type. If they do, a routine is effected via the control store to determine the data type of each operand, a branch operation to enable reformatting being performed if necessary, e.g. by a translation device such as a programmable read only memory, after which the instruction is executed. If required the read only memory may be used to return the result to the original representation.