baber/WOPTO huggingface dataset:
Patent JP-2000069564-A (JP)
Title: Radio base station device and pb tone transmission circuit
Inventor: HIRATA MASARU
IPC: H04W88/08
Filed: 1998-08-26
Abstract: PROBLEM TO BE SOLVED: To provide a radio base station device that can be applied even to a public network or an exchange that cannot transmit a PB tone. SOLUTION: A parallel I/O circuit 2 sets a tone color setting signal L2, a transmission channel setting signal L13 and a timing signal L3 under the control of a CPU 1. A timing generating circuit 3 transmits channel information and a timing enable signal L5 denoting an output timing of output data to a transmission data generating circuit 6 and transmits an address counter start pulse signal L4 to an address setting circuit 4. The address setting circuit 4 sets tone color information to high-order 4 bits of an address bus L6 for a PBROM. A PB tone storage circuit 5 outputs PB tone data L8 according to the address bus L6 for the PBROM and a PBROM enable signal L7. The transmission data generating circuit 6 receives the PB tone data L8 and the timing enable signal L5, applies speed conversion to the PB tone data by means of parallel/serial conversion and transmits the resulting data.
Patent JP-H03103992-A (JP)
Title: Calculating device for regular polygon vertex
Inventor: IIDA MASAHIRO
IPC: G06T11/20
Filed: 1989-09-19
Abstract: PURPOSE:To decrease the accumulation of an error at the time of calculating a coordinate of the vertex, and to obtain an exact coordinate of the regular polygon vertex by providing an even/odd deciding part, a vertex coordinate calculating part, and a code converting part. CONSTITUTION:An even/odd deciding part 1 decides whether a designated regular polygon is an even number of angles or an odd number of angles. Based on this decision, a vertex coordinate calculating part 2 calculates a coordinate of the vertex belonging to two adjacent quadrants of a plane orthogonal coordinate system in which the center of a circumscribed circle of a designated regular polygon is an origin, and a coordinate of the vertex belonging to one quadrant delimited by both coordinate axes of an orthogonal coordinate system in which the center of the circumscribed circle is the origin, when the number of angles of the designated regular polygon is an odd number, and when the number of angles of the designated regular polygon is an even number, respectively. Also, a code converting part 3 converts a code of the coordinate of the vertex calculated by the vertex coordinate calculating part and calculates a coordinate of the vertex belonging to the other quadrant. In such a way, the degree of an accumulation of an error becomes 1/2 or 1/4, and the coordinate of the regular polygon vertex can be obtained with high accuracy.
Patent JP-S60133136-A (JP)
Inventor: HARADA AKIHISA
IPC: E03F1/00
Filed: 1983-12-19
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0764899-A (JP)
Title: Memory access device
Inventor: TERAJIMA JUNICHI
IPC: G06F13/16
Filed: 1993-08-31
Abstract: PURPOSE:To make it possible to switch a memory bus with a valve close to the minimum memory access time of a memory by reducing the useless time of a bus cycle time. CONSTITUTION:This device is equipped with a memory 1 connected with a common memory bus B0, first and second processors 2 and 3 alternately connected with the memory bus B0 which write/read data in/from the memory 1, selector 4 which selects and switches the processors 2 and 3, and connects it with the memory bus B0, and control circuit 6 which controls the switching operation of the selector 4. At least one part of periods of bus cycles At and Bt of the processors 2 and 3 are superimposed, and the selector 4 is controlled so that each processor 2 and 3 can be switched and connected with the memory bus B0 in a period including a minimum access time Ct of the memory to which an access is performed which is generated in the bus cycles At and Bt periods.
Patent JP-S61108949-A (JP)
Inventor: RARII EI JIEFUAAZU
IPC: G01N21/64
Filed: 1985-10-29
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H1184324-A (JP)
Title: Method, device and system for modulating light in wavelength division and multiplexing
Inventor: KIYONO MINORU
IPC: H04B10/25
Filed: 1997-09-05
Abstract: PROBLEM TO BE SOLVED: To easily execute the light modulation of an optional optical carrier included in wavelength divided and multiplexed light by selectively modulating the optical carrier to be selected which is selected from the plural optical carriers according to a modulation signal. SOLUTION: This device is provided with optical wave guide structure 2 to which the wavelength divided and multiplexed light(WDM light) is guided and a selection and modulation unit 4 acting on the structure 2. Then, the plural optical carriers having different wavelength are included in the WDM light. By the unit 4, the optical carrier to be selected is selected from the plural optical carriers and selectively modulated according to the modulation signal because the modulation signal is supplied. For example, when the wavelength of the optical carriers are respectively λ1 , λ2 ,..., λn and the wavelength of the optical carrier to be selected is λ2 , only the optical carrier to be selected is modulated and modulated light thus obtained is outputted.  Besides, the optical carriers other than the optical carrier to be selected are passed through the unit 4 as they are.
Patent JP-H0983924-A (JP)
Title: Still picture file system
Inventor: NOGUCHI ISAO
IPC: H04N5/78
Filed: 1995-09-20
Abstract: PROBLEM TO BE SOLVED: To control plural effects in parallel by the unit of the field with ease and at high speed in the program reproduction of a still picture file system. SOLUTION: Still picture data is transferred to a picture memory device 104 by a transferring device 105 and given a picture effect by a picture effect device 106 to be outputted to a display 107. Voice data on a voice data recorder 108 is reproduced and outputted by a voice reproducing device 109. By a vertical blanking signal from a timing generator 101, a timer 111 times a present time and an execution means 114 is driven interruptedly at each field. At this time, a register means 113 decomposes contents in a control file to the processings of the unit of the field and each processing is arranged in the order of executing times and managed by a control information holding means 112. Then a processing having the execution time is equal to the present time is executed in order for each field by an execution means 114.
Patent JP-S61117030-A (JP)
Title: Fastening controllier for fastener parts
Inventor: MARUI KOREHITO
IPC: B25B23/14
Filed: 1984-11-14
Abstract: PURPOSE:To eliminate variations in fastening torque, by making a fastener part perform its fastening work by high speed rotation of a bit in time of its fastening start, while changing the rotation to low speed at a time when a seat surface of the said fastener part seats itself on a work. CONSTITUTION:A decelerating device, branching off turning power from now on into two high and low speed systems, is connected to a motor directly. A clutch device, switching power from the said decelerating device, is connected to one side high speed system of this decelerating device, and a bit 52 is connected to the same center line of this clutch device. And, when the bit 52 clamping a fastener part receives a thrust, a drive shaft 26, where the turning power is transmitted from the said clutch device, is set up there. In addition, a rotation transmitting member, which is solidly rotatable with the other side low speed rotational system and has a one-way clutch 41 installed in free of engagement with the said clutch device, is installed in the other side low speed rotational system of the said decelerating device. Therefore, when a seat surface of the fastener part seats itself on a work, bit rotation comes to low speed so that there is no influence of inertia force.
Patent JP-S61120666-A (JP)
Title: Painting method
Inventor: ASADA KOSHIROU
IPC: B05D7/14
Filed: 1984-11-15
Abstract: PURPOSE:To enhance the close adhesiveness between paints, in forming two layers or more of paint films to an article to be painted, by gradually increasing and decreasing the spray amounts of paints by allowing the same to correlate to each other. CONSTITUTION:At first, a paint A is sprayed onto an article 1 to be painted, to which electrodeposition painting was applied preliminarily, to form a paint film 2 only comprising the paint A. Next, the spray amount of a paint B is gradually increased simultaneously while the spray amount of the paint A is gradually decreased to form a mixed paint film 3 of both paints A, B. Then, the paint B is sprayed to form a paint film 4 only comprising the paint B and these films are baked. In this paint film constitution, the close adhesiveness between both paint films is enhanced as compared with such a case that the kinds of two paints are almost perfectly changed at the interface of two paint films.
Patent JP-S60132706-A (JP)
Inventor: WATANABE YOSHIO
IPC: B28C5/42
Filed: 1983-12-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63232150-A (JP)
Inventor: NITO HITOSHI
IPC: B65D33/00
Filed: 1986-10-11
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60133693-A (JP)
Inventor: TASHIRO TOYOHIKO
IPC: H05B37/02
Filed: 1983-12-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H09120688-A (JP)
Title: Semiconductor memory device
Inventor: CHIYOU TOUSHIYU
IPC: G11C17/00
Filed: 1996-09-12
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of stabilizing the threshold voltage value of a cell not selected. SOLUTION: String selective transistors 1, 2 are bonded among bit lines BL1 , BL2 and cell transistors 11 -1n , 21 -2n and ground selective transistors 3, 4 are combined among a common source line CS and the cell transistors 11 -1n , 21 -2n . The drain/source voltage of a cell transistor not selected is stepped up by a capacitor-coupling, passing voltage applied to a word line not selected at the time of programming is minimized, and stress by passing voltage is reduced by fitting program inhibition lines PIL1 -PILn and a large number of capacitors CPi connected among the program inhibition lines PIL1 -PILn and the corresponding source/drain regions of the cell transistors 11 -1n , 11 -2n . Accordingly, the performance and reliability of a semiconductor memory device are improved.
Patent JP-H0289398-A (JP)
Title: Case seal type hybrid integrated circuit device
Inventor: ISHIHAMA KAZUHARU
IPC: H01L23/02
Filed: 1988-09-27
Abstract: PURPOSE:To avoid deterioration of circuit characteristics, to maintain position accuracy high, and to lighten it by fixing a printed wiring board to a metallic case by soldering, etc., and coating only the outside surface of this printed wiring board with resin so as to seal a hybrid integrated circuit board. CONSTITUTION:In a printed wiring board 3, a through hole 7 is provided at a position conforming to the external terminal 2 of a hybrid integrated circuit board 1, and the external terminal 2 is led out to the outside of this hybrid integrated circuit device through the through hole 7. This external terminal 2 is fixed by solder 4. Also, at the outside of the printed wiring board 3 is formed a wiring pattern 8 which connects through holes for signal terminals with each other and connects grounding lands 9 formed at the ends with through holes for grounding terminals. And after setting this printed wiring board 3 in a metallic case 1, and fixing the printed wiring board 3 to a metallic case 5 by solder 4, the outside surface of the printed wiring board 3 is coated with silicon resin 6, whereby a hybrid integrated circuit device is completed.
Patent JP-S63102119-A (JP)
Inventor: AOYAMA YOICHI
IPC: H01H9/30
Filed: 1986-10-11
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60136641-A (JP)
Title: Balancer device of reciprocating engine
Inventor: MITADERA TAKASHI
IPC: F02B77/00
Filed: 1983-12-23
Abstract: PURPOSE:To offer a compact balancer device by providing a crank shaft with a rotor bearing eccentric to the crank shaft axis and also providing around the rotor bearing with a reciprocating portion bearing eccentric to the rotor bearing and making the reciprocating portion bearing support a counterweight to perform an opposite reciprocating motion to the piston. CONSTITUTION:On the outer portions of crank webs 7, 7 of a crank shaft 5 eccentric pins 11, 11 are provided adjacent to and in a body with each web 7, and on the outer periphery of each eccentric pin 11 a rotor bearing 12 is formed. On each rotor bearing 12 an eccentric plate 13 is rotatably bearing supported and on the outer periphery of said eccentric plate 13 an reciprocating portion bearing 14 is arranged. To the reciprocating portion bearing 14 a counterweight 15 is supported and the counterweight 15 is slidably fitted to a guide pin 16 provided in parallel to the shaft center axis of a cylinder 1 and is guided so as to make reciprocating motion.
Patent JP-S62101712-A (JP)
Title: Self traveling working device on supporter
Inventor: KITAMURA MORIO
IPC: E02D7/00
Filed: 1985-10-29
Abstract: PURPOSE:To obtain a crane to be moved on the upper end of an existing pile by a method in which a clamper is provided through a rotator on both ends of a bendable and expandible boom member, and a hanging part is attached to at least a boom arm. CONSTITUTION:Expandible boom arms 32a and 32b are connected with a joint 31 in a freely bendable manner to form a boom member 30, and clampers 12 and 22 are attached through rotators 11 and 21 to both ends of the boom part 30. A hanging part 24 is provided to at least a boom arm 32b to form a crane device. During moving period, disengagement of the pile P from the clampers 12 and 22 and also turning the rotators 11 and 21 allows the crane device to move. Also, when an oil-pressure cylinder is operated under a condition that one clamper is fixed to the pile P and the other clamper is separated, the crane operation can be permitted.
Patent JP-2000208103-A (JP)
Title: Flat light source and liquid crystal display device using it
Inventor: TSUCHIYA MASASHI
IPC: H01J61/30
Filed: 1999-08-30
Abstract: PROBLEM TO BE SOLVED: To attain an emission with high luminance and reduce the cost by providing at least a pair of discharge electrodes on the inner surface of a sealed vessel having a translucent front plate, covering the surfaces of the discharge electrodes with dielectric layers, and setting the specific dielectric constant of the dielectric layers within a specified range. SOLUTION: A translucent front plate 10 consisting of soda glass and a shallow dish-like insulating substrate 21 consisting of soda glass or ceramics are integrally sealed in the airtight state by a low-melting point glass to constitute a flat sealed vessel 1. A pair of parallel discharge electrodes 40, 41 are provided on the inner surface of the front plate 10, and the respective surfaces are covered with dielectric layers 51, 52 provided by thick film printing. As the dielectric layers 51, 52, a glass paste mainly composed of lead glass and having a specific dielectric constant ranging from 8 to 40 is used. The dielectric layers 51, 52 are printed only on and near the discharged electrodes 40, 41, whereby the light transmissivity of the front plate 10 is enhanced to improve the light taking-out efficiency.
Patent JP-H0666532-A (JP)
Title: Product inspection support system
Inventor: ATONO YOSHIFUMI
IPC: G06T1/00
Filed: 1992-08-19
Abstract: PURPOSE:To re-inspect a product quickly and efficiently and to relieve the load of an inspector by comparing an actual image data with a reference image data and then determining a part of the product to be re-inspected based on the comparison result. CONSTITUTION:The image of a product (for example, a lead frame) 14 which is carried 12 is taken by a CCD camera 10 and an actual image data which is the voltage data for each pixel constituting the image inside a visual field 16 is generated and is stored in a memory 20a. An MPU 22 compares the actual image data of the memory 20a with the reference a image data which is stored in a memory 20b and then determines and displays a part to be re-inspected of the product 14 based on the result, thus immediately observing the actual image of the part to be re-inspected, performing visual re-inspection quickly, and at the same time relieving the load of an inspector, and preventing inspection mistakes. Also, a further accurate re-inspection can be made by enlarging and displaying 26 the actual image of the part to be re-inspected based on the enlarged actual image data which is stored in a memory 20f.
Patent JP-S6484350-A (JP)
Title: Compression/extension processing lsi
Inventor: MURAYAMA MASAYOSHI
IPC: G06F12/00
Filed: 1987-09-28
Abstract: PURPOSE:To make it possible to use a facsimile equipment, etc. as well by providing the title LSI with on EOL flag generating means for outputting an EOL flag and a compression code forming means for coupling all '0' bits. CONSTITUTION:The LSI is provided with the EOL flag generating means 22 for outputting an EOL flag when an EOL code is outputted based on a shortest code control flag LINER in a setting register 24 in a shortest code length restricting mode and the compression code forming means 1 for generating all bit -0' code data at the time of ending the formation of the final compression code of a line and coupling all '0' bits to a part less than the previously determined data length in the final compression code. Thereby, the size of the compression/extension processing LSI is not increased. The compression/ extension processing LSI to be used also by a device having no memory area by one page of a facsimile, etc., can be obtained by adding an external circuit.
Patent JP-H0798341-A (JP)
Title: Comparator switching circuit
Inventor: HODAKA KAZUO
IPC: G01R19/165
Filed: 1993-09-29
Abstract: PURPOSE:To provide a comparator switching circuit requiring no exclusive terminal for switching the outputs of two kinds of comparators having different polarities. CONSTITUTION:When the value of the reference voltage Vref is changed between a power source Vdd and the ground and the output of an inverter 19 is changed to a high or low level in response to the value of the reference voltage Vref, the proper output of the first or second comparator 17, 18 is sent out from a multiplexer 20. No exclusive terminal is required for switching the outputs of the first and second comparators 17, 18.
Patent JP-H0986662-A (JP)
Title: Wood supplying device
Inventor: KUROKAWA TAKASHI
IPC: B65G57/09
Filed: 1995-09-21
Abstract: PROBLEM TO BE SOLVED: To improve productivity by successively cutting out the first/second woods into a set condition, and transfer-loading the wood in this set condition on a supply conveyer of a machining device. SOLUTION: The first supply part 13 supports sideways a plurality of the first woods 5 transversely fed, and the second supply part 14 supports sideways a plurality of the second woods 6 transversely fed. By the first/second cut out mechanisms 15, 16 respectively provided in carry out ends of these first/second supply parts 13, 14, the first/second woods 5, 6 are successively cut out to be placed in a set condition that the second wood 6 is interposed between a pair of the first woods 5. Wood 7A in this set condition is transfer loaded by a transfer loading mechanism 17, on a supply conveyer 11 of a machining device. Accordingly, the wood, automatically built in the prescribed set condition, can be continuously supplied to the machining device. In this way, a rate of operation of the machining device can be improved, and productivity is improved.
Patent JP-H1189277-A (JP)
Title: Controller of reluctance motor
Inventor: KITAJIMA YASUHIKO
IPC: H02P25/08
Filed: 1997-09-08
Abstract: PROBLEM TO BE SOLVED: To control the coil current of a reluctance motor accurately and independently without using a current sensor. SOLUTION: A controller is equipped with a current command value operating circuit 1 which operates the current command value to each exciting coil of a reluctance motor 5 from the angle of rotation of a motor detected with an angle-of-rotation sensor 6 and a torque command value; a voltage command value operating circuit 2 which operates the voltage command value to each exciting coil from this current command value, the angle of rotation of the motor, and a motor parameter; a PWM pulse command value making circuit 3 which makes a PWM pulse command value, based on this voltage command value; and a power converting circuit 4 which generates a PWM pulse signal in accordance with this PWM pulse command value, and performs current application to each exciting coil.
Patent JP-S61123175-A (JP)
Title: Manufacture of hetero-junction bipolar transistor
Inventor: TSUDA KUNIO
IPC: H01L29/73
Filed: 1984-11-20
Abstract: PURPOSE:To form the surface of an external base as a high-concentration impurity layer, to inhibit the contact resistance of a base to a low value even when an element area is reduced and to obtain a bipolar transistor having high performance and the high degree of integration by implanting the ions of impurity elements of two kinds or more to shape the external base. CONSTITUTION:An n<+> type GaAs layer 12 and an n type GaAS layer 13 as collector layers, a p type GaAs layer 14 as a base layer, an n type AlGaAs layer 15 as an emitter layer and an n<+> GaAs layer 16 functioning as a cap layer for easily taking the ohmic contact of an emitter are grown on a GaAs semi-insulating substrate 11 in an epitaxial manner in succession. A mask is shaped into an emitter region, the unnecessary layer 16 is removed, Mg ions are implanted first, and Zn ions are implanted. A p<+> type external base 17 is formed through flash annealing by infrared rays after Zn ions are implanted. Sections up to the layer 12 are etched, sections up to the substrate 11 are mesa- etched for isolating elements, and a collector electrode 19, an emitter electrode 18 and a base electrode 20 are shaped. Accordingly, a fined bipolar transistor having high performance and the high degree of integration is acquired.
Patent JP-H1165771-A (JP)
Title: Electrode substrate for touch panel and manufacture of the same
Inventor: ARAI YOSHIHIRO
IPC: G06F3/041
Filed: 1997-08-25
Abstract: PROBLEM TO BE SOLVED: To provide an electrode substrate for a touch panel with excellent resistance against damage due to friction and weatherproofness, and with an excellent uniformity in full light beam trasmissivity and surface resistance (sheet resistance), and to offer a method for manufacturing an inexpensive electrode substrate for a touch panel with excellent productivity. SOLUTION: In this substrate, a transparent conductive whose thickness is more than 0.2 μm, and whose surface resistance is 200-3000 Ω/square is placed on a transparent insulating substrate, wherein the transparent conductive layer includes 60-95% by weight, against the whole weight of the transparent conductive layer, of conductor particulates whose diameter is 0.03-0.3 μm. And in a method for manufacturing this substrate, an electrode pattern is formed by a roll printing method on the transparent insulating substrate by using conductive ink in which 20-40% by weight of conductor particulates whose diameter is 0.03-0.3 μm and 2-10% by weight of binder resin is scattered, and then this substance is between in atmospheric temperature which is less than 150 deg.C.