Patent GB-1470104-A (GB)
Title: Stored programme electronic computer
IPC: H03M11/20
Filed: 1974-04-22
Abstract: 1470104 Data processing system ING C OLIVETTI & C SpA 22 April 1974 [24 April 1973] 17545/74 Heading G4A A data processing system includes a main memory storing program instructions and is arranged in response to a program altering instruction selectively to delete an instruction from and insert an instruction into the main memory and to shift the other instructions in the memory to fill up the resulting gap or to make room for the new instruction respectively. General.-The system includes a central control unit including an arithmetic and logic unit, timing and routing circuits, and a high speed scratch pad memory having 16, twelve bit registers addressable in groups of 4 bits. The central unit is connected to peripherals including a keyboard, a control console, card readers, tapes &c., and to a random access memory (RAM) storing data and program instructions in 240 sixty bit registers, each register storing a floating point data item or five 12-bit instructions, and a read only memory (ROM) storing microprogram sequences. Two microprogram sequences DDE and LDE transfer data from the scratch pad to random access memories and vice versa respectively four bits at a time. Program modification.-Two "pointer" registers in the scratch pad memory SP16 identify the highest ordered group of four bits in the program instruction to be deleted and the highest ordered group of four bits in the following instruction. When the instruction is cleared successive use of sequences DDE and LDE move following instructions to close the gap, the instructions being transferred via a register in the scratch pad memory. Inserting an instruction is similar except that the two pointers identify the same instruction, i.e. the first instruction to be moved. The instruction is moved into the scratch pad and replaced by the new instruction, set up in a scratch pad register. The pointers are advanced to the next instruction and the process continues through to the end of the program. Jump instruction.-Two types of jump instruction are described. In the first a jump instruction contains a "jump-to" address which is transferred to a scratch pad register which subsequently acts as a program counter to replace a further scratch pad register which normally fulfills this function. In the second a jump instruction contains a label which is transferred to a scratch pad register and the RAM is searched for the label, the comparisons being performed in the logic unit. Label instructions have a special op code part identifying it as a label while the remainder of the instruction is the label. Eight double "program level" registers and a "booking" register are provided in the RAM to enable nested subroutines to be executed and to vary the label search procedure. The first program level register contains in the first half the origin of the program from which point label searches are started, generally the first location in the RAM, while the second half contains the current instruction address which is normally incremented. The booking register is used to specify a new origin when a subroutine jump occurs. On such a jump the contents of the first program level register are loaded in the second, the new origin from the booking register is loaded in the first half of the first level register, and a search is instituted for the label specified by the jump starting at the specified origin with the second half of the first level register being incremented as the search proceeds until the label is found whereupon the instructions are executed in sequence using the second half of the first level register as a program counter. The eight level registers allow nested subroutines to be executed, returns being made by discarding the contents of the first level register and pushing all the other registers up one register. Normally a return is made at the address following the jump instruction, although a number of instructions can be skipped.