Patent GB-899230-A (GB)
Title: Traffic measurement apparatus
IPC: H04M3/36
Filed: 1961-01-04
Abstract: 899,230. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Jan. 4, 1961 [Jan. 11, 1960], No. 364/61. Class 40 (4). In apparatus particularly for measuring traffic in a telephone exchange, a monitoring circuit provides progressively an indication of each of a number of equipment units in a specific condition, and the identity of such units is fed in code form to a recording circuit by way of a series of temporary or buffer stores sufficient in number to take up any accumulation of data which may occur during peak periods owing to the input rate exceeding the recording rate. As shown, 600 units are monitored, their condition being indicated by the potential on their sleeve leads 0-599. According to the position of a switch 3, a traffic usage register TUR or a peg count register PCR is employed to obtain data on a fixed basis or a random basis. The traffic usage register TUR includes a pair of synchronously operating cross-bar switches CB1, CB2 which connect leads 0-599 six at a time in succession to detectors UD and corresponding output leads L0-599 to pulse generators PG. Sequential gates UG direct the indications from the detectors in succession to the corresponding pulse generators so that a pulse is emitted on the appropriate lead for each unit in a specific condition. In the peg count register PCR detectors PD connected to the sleeve leads directly control pulse generators PG connected to the output leads L0-599. The encoder comprises transformer cores C0-11, of which C0-9 are threaded selectively by the leads L0-599 to provide the number of the corresponding unit in binary notation, C10 is threaded to provide a check on numbers containing an odd number of 1's and C11 is threaded by all the leads. Each indication received by the encoder is at once transferred by way of isolating diodes D0-10 to the first storage cell BS1, while the core C11 delivers a trigger pulse to set a bi-stable device MV1. Each of the series of storage cells BS1 ... BSn comprises magnetic cores M0-10 having square loop characteristics, with an advance winding, e.g. A2, threading all of them. When a pulse is applied to the advance winding the previously set cores are reset and the stored indication is transferred to the next cell. Associated with each cell is a bi-stable circuit, e.g. MV2, comprising a pair of transistors Q1, Q2, and a core driver, e.g. CD2, consisting of a transistor blocking oscillator Q3 for supplying the advance pulses. The bi-stable circuit indicates the state of the corresponding cell, being set when it is occupied and reset when it is unoccupied. Adjacent bi-stable circuits control an AND gate, e.g. G2, in such a way that if BS2 is occupied and the next cell is not then G2 supplies a negative bias to the oscillator Q3 and the core driver CD2 delivers first an advance pulse to the winding A2, and subsequently a reset pulse to the bi-stable circuit MV2 and a set pulse to the next bi-stable circuit. Thus an indication received from the encoder is transferred from cell to cell until it reaches the first unoccupied one, and a " queue " of indications is built up. When the last cell BSn is occupied the set condition of the bi-stable circuit MVn enables a reader control circuit 23 which delivers stepping pulses alternately over leads PA, PB to serial reader apparatus 25 comprising a two-phase magnetic core stepping switch. The stored indication is thus transferred in serial form by way of an output winding P threading all the cores to an amplifier 27, OR gate 31 and converter 33. At the same time pulses are directed periodically over lead S to an amplifier 29 and may serve for synchronizing. The circuit MVn is reset when the transfer is complete. The pulses received by the converter 33 go alternately through writing amplifiers 35, 37 either to a magnetic tape recorder 39 or to a remote processing centre according to the position of a switch 38.