Patent GB-1339073-A (GB)
Title: Digital graphic display apparatus system and method
IPC: G05B19/41
Filed: 1971-04-19
Abstract: 1339073 Graphic display Z TARCZY-HORNOCH 19 April 1971 [24 Feb 1970] 22928/71 Heading G4H [Also in Division H4] A graphic display device arranged to receive data over a transmission medium having a limited band width, in, for instance, ASCII characters, the characters indicating length and direction parameters stores at least one character and identifies any changes involved when receiving further characters. Data characters serially received are converted to parallel in SPC unit 6 (Fig. 2) and are fed to 'decoder D8 producing a 1-out-of-10 signal on lines 0-9 and a clock signal on clock start line CS. A signal on lines 0 to 6 inclusive may indicate an update of the previous memorized direction by 3, 2, 1, 0, - 1, - 2, - 3 quanta respectively, 7 may mean change the state of trace memory TM determining whether a pen is on paper or whether a cathode-ray tube displays a signal, and 8 and 9 may increase or decrease the memorized length by one quantum respectively. The ten lines feed AND gates 55-63 fed via AND gate 52 from the CS pulse on line 38. A clock UC51 feeds a counter MNC 66 having a variable modulus via a delay D65. The CS pulse feeds a one-shot 50 allowing a single pulse from clock UC to pass AND gate 52. The counter MNC has three inputs 68, 69, 70 setting its modulus to 9, 3, 1, respectively, the inputs being provided by a length modulus memory 107 (Fig. 8). The inputs 0-2, 4-6 feed one-shots 73-78 having varying pulse output times of length corresponding to the numbers in the oneshots, e.g. if counter MNC is set to a modulus of 9, OS3 allows 3 pulses to pass, OS2 two pulses and OS1 one pulse. If set to a modulus of 1, 27, 18, 9 pulses pass respectively. A length and memory generator 16 (Fig. 8) receives signals LS, +, - from the control logic 10, derived from length signals 8, 9, and supplies modulus signals 1, 3, 9 to the control logic. Signals +, - on lines 93, 94 are fed to a reversible counter or length memory 107 which determines how many pulses should be generated at C2 to control the length of the line segments to be displayed. The length generator contains a clock 100, a control flip-flop 102, a delay 110 and a modulo N counter MNC containing two shift counters. The LS sets flip-flop 102 so that gate 101 passes clock pulses to counter 104 and delayed clock pulses C2 are passed until counters 104, 106 have the same count as counter 107, when one of gates 113, 114, 118 resets flip-flop 102 to stop the clock pulses and reset counters 104, 106 so that 1, 3 or 9 pulses are supplied on C2. The direction memory (Fig. 9) has two reversible modulo 3 counters 125, 126, a one-outof-nine decoder containing AND gates 140- 148, a reversible modulo 2 counter 127, a reversible modulo 4 counter 128 and a reversible modulo 8 counter 160. Counters 125, 126 indicate one of 9 possible directions in an octant (Fig. 5). Counter 128 determines the quadrant, while counter 160 which has an output signal on only one of its outputs 0-9 provides a signal J or X.Y for use in the pattern generator.  The pattern generator (Fig. 10) receives inputs A, B, A, B from the length memory and generator and logically combines them. Signals 01-22 (Fig. 5) produced as signals A, B, A, B are varied as the counters are incremented to enable one of AND gates 212-219 so that logic signals are fed to gate 221 to be combined with signal J from the direction memory. The signal from gate 221 is combined with the C2 clock pulses from the length memory and generator and combined with the X.Y and K, L, M, N signals from the direction memory to produce signals on one of the ŒX or ŒY lines which are fed to the display.