Patent GB-677575-A (GB)
Title: Improvements in or relating to electrical pulse code signalling systems
IPC: H03M1/00
Filed: 1950-03-23
Abstract: 677,575. Pulse code modulation systems. GENERAL ELECTRIC CO., Ltd., IMM, R. C., and STENNING, L. C. March 12, 1951 [March 23, 1950], No. 7366/50. Class 40 (v) In a pulse code modulator, a first counting means determines the number, N1, of times a first reference level is contained in a signal sample amplitude and a second counting means thereafter determines the number, N2, of times a second smaller reference level is contained in the difference between the sample and the sum of the first-counted reference levels. Groups of pulses, representing the numbers N1, N2, are transmitted in succession, the groups being respectively transmitted in periods following the counting periods, and the counters being restored in the intervals between counting operations. In the embodiment described, the coding is performed on the interlaced samples of twelve channel signals having a recurrence frequency of 6.6 kc/s. and each number N1, N2, is represented by a group of two ternary digit pulses, the ternary digits 0, 1, 2 being represented by zero, positive and negative pulses, respectively. Thus eightyone different amplitude levels are available by the transmission of four digit pulses, e.g. positive, zero, negative, positive=1021 on the ternary scale=34(27+0+6+1) on the decimal scale. This example is shown in pulse form in graph M, Fig. 2, and the coding thereof in the other graphs, T being a channel period of approximately thirteen microseconds. Each signal sample from circuit 1, Fig. 1, is applied to a pentode Miller integrator storage circuit 3, which is previously charged to an amplitude level of eighty units from the waveform generator 10, and being then discharged to signal sample potential. A reference pulse generator 5 feeds negative pulses, graph A, having a recurrence frequency of 1.28 Mc/s., to to two discharging stages 6, 7. The waveform generators 10, 4, locked to pulses A through a frequency divider 11, produce the waves of graphs B, C, respectively, which control the emission of pulses from the discharging stages 6, 7, respectively, alternately during each quantizing period T. Each pulse from stage 6 causes the condenser of integrator 3 to be discharged by nine reference amplitude levels and each pulse from stage 7 by one reference level. The multivibrators 8, 9 interrupt the trains of discharging pulses from circuits 6, 7 respectively when the potential across the storage circuit 3 is less than nine or one reference levels respectively. The pulses from stage 6 are counted by a ternary counter 12 comprising the nine-unit stage 13 and 27 unit stage 14, while those from stage 7 are counted by the single-unit stage 15 and three-unit stage 16. The digits registered by stages 13 ... 16 are converted, in time sequence, into pulses by gating circuits 17 ... 20. The gating pulses are shown in graphs D ... G, respectively, and are derived from the waveform generators 10 and 4. The counter re-setting pulses, graphs H, J, respectively, are also supplied from generators 10 and 4. In the example quoted above, the signal sample amplitude of 34 units results in the three nine-unit pulses, graph K, being counted in stages 13, 14, giving rise to the positive code pulse (27), graph M, and a zero code pulse (0), while seven single unit pulses, graph L, counted in stages 15, 16, result in a negative code pulse (6) and a following positive pulse (1), graph M.