Patent GB-1454198-A (GB)
Title: Multi-level information processing system
IPC: G06F11/16
Filed: 1974-07-15
Abstract: 1454198 Data processing BURROUGHS CORP 15 July 1974 [15 August 1973] 31162/74 Heading G4A A multi-processing system comprises a plurality of memory modules 30a (Fig. 1), a plurality of central processing modules, 20, a plurality of input/output modules 10 and means associated with the modules for detecting and reporting modular errors. As described the central processing modules communicate with the memory modules via a communication unit. A maintenance diagnostic unit 26 permits identification and repair of faults. Central processing module.-A programme section (42, Fig. 4, not shown) is responsible for separating code strings into operations which are placed in queues for the execution section (44), the latter including an execution unit (62) and input queues (64). The execution section performs all arithmetic and logic operations on a first in-first out basis. The module also ineludes a storage section (46) including a storage unit (66), a stack buffer (50) and an associative memory (52). Implicit operations are placed in a queue (70) by either the programme section or the execution section. A programme buffer (48) in the programme section comprises an array of I.C. chips for 32 words of 60 bits, words being placed alternately in odd and even divisions of the buffer, parity being checked in each syllable. Programme operators in the programme code strings are fetched from memory 30 in multiword segments and held in the programme buffer. They are extracted singly and separated into one or more micro-operators which are queued for processing in execution units (62). The control unit requests the data required for execution from store (66) and forwards directly to the unit (62) literal values in the code string. Results may be stored locally or fed via a communications unit 68 to main memory 30. Processing speed is increased by storing for example frequently referenced variables in buffer memory areas within the processor to reduce the time spent waiting for completion of data transfer. The communication unit provides the interface between the central processing modules and the main memory on a priority basis, the stack buffer being given first priority, the storage unit being given second priority and programme buffer requests being given third priority. Input/output sub-system.-This controls the transfer of data between main memory and storage in the peripherals (which operate independently of the central processing modules via input / output modules). The input / output modules are queue driven from a map of input/ output requests in main memory, a requesting central processing module first altering the map and the input/output module then trailing the same path to initiate the input/output request. A special purpose hard-wired multiprocessor services the map. The requesting module (a) constructs requests which explicitly define the required operation, (b) stores the requests in memory and (c) informs the input/output modules capable of servicing the job of the storage locations. All control work flow between main memory and the peripherals is via a memory interface unit, translator and one of four sub-sections. All data flow is between a data transfer sub-section and/or the interface unit without using the translator. Error detection is effected on all data transferred. Input/ output errors detected by an input/output module and a peripheral controller are processed by the input/output module. They are sorted into two categories (1) channel or request related faults and (2) module or non- request related faults. Memory modules.-Each memory module comprises a memory control module controlling one or more memory storage cabinets, each cabinet including two independently addressable memory storage units. The storage units comprise a core memory stack operated in three modes, read/restore, clear/write and read/ modify / write. By allocating consecutive addresses to different storage units a second unit may be prepared for a memory cycle whilst the first unit is transferring a word. All words used by software are 48 bits with an additional three tag bits and an odd parity bit to make a 52 bit word fed from a requestor. All words in a memory storage unit are 60 bits, 7 check bits and an odd parity bit being added to the requestor word. Whether or not a requesting module may access a particular memory module depends on the setting of an associated bit in a requestor inhibit register. A memory address consists of 20 bits the first six of which designate a memory segment and are compared with the contents of two limit registers which specify the highest and lowest address available in the memory module, these registers being set during system initialization. When an access is permitted, a control word indicating, e.g. read or write is transferred to the error detection circuits. If a parity error is detected it is transferred to a fail register. The memory control module transmits an interrupt signal FAL1 to the requestor for the following errors (1) control word parity wrong, (2) illegal operation code, (3) wrong module addressed, (4) data strobe errors, (5) two bits in error and (6) internal error, An interrupt signal FAL2 is set if a one bit error occurs. A disc file sub system provides an extension of main memory. A main memory buffer register is used by the memory control unit as a temporary store for words transferred to and from the memory storage unit. It acts as a source of data for error code checking logic which if necessary generates a correction signal to complement a single erroneous bit. Maintenance diagnostic unit.-This is used in conjunction with a dedicated magnetic tape in offline testing of modules. When a faulty module has been identified by on line diagnostic programmes the cause of the trouble is traced to circuit level by the diagnostic unit which is connected to all modules by dedicated cables.