baber/WOPTO huggingface dataset:
Patent JP-2000028374-A (JP)
Title: Onboard navigation system
Inventor: ASAINA TAKUMI
IPC: G09G5/36
Filed: 1998-07-13
Abstract: PROBLEM TO BE SOLVED: To eliminate the degradation of an image quality and to use a plurality of video sources without increasing a cable and a connector in an on-vehicle navigation system in which a display device and a navigation apparatus body are provided. SOLUTION: In a display device 2, a digital interface control part 21 which interfaces image data to he sent from a navigation apparatus body 1 is provided, a frame buffer 22 which displays the image data received by the digital interface control part 21 is provided, and a control processing part 25 is provided. In the navigation apparatus body 1, a frame buffer 14 which stores plotted data is provided, and a digital interface control part 17 which reads out the plotted data so as to be transferred to the display device 2 is provided. The digital interface control part 21 and the digital interface control part 17 are connected by a digital line 3.
Patent JP-S6175231-A (JP)
Title: Connection propriety inspector for assembly link shaft
Inventor: SUGIYAMA SADAKAZU
IPC: G01M13/00
Filed: 1984-09-20
Abstract: PURPOSE:To reduce the inspection time, by judging the connection propriety of an assembly link shaft based on the servo motor current when a moving command is applied to a positioning servo mechanism to move the assembly link shaft mounted at a moving section of a moving mechanism. CONSTITUTION:When a start switch 30 and a switch 33 are turned ON to start a servo unit 18 and a timer relay 34, a slide base 17 soft starts in the direction B, to shift the shaft 3 of the assembly link shaft comprising a final drive side 1, a surclip 2 and a drive shaft 3 by a value equivalent to play. Unless the movement of the shaft surpasses the play, the motor current (i) exceeds the limit value with increased driving force of a motor 15 but it is continued to be held within the limit value with the action of a current restricting circuit 25 or the like. When the output voltage Vx of a current detection amplifier 31 is larger than a reference value Vr of a decision device 32 at the expiration of the limit time of a relay 34, the connection is judged to be good. When the shaft 3 moves beyond the play value, the voltage Vx becomes smaller than the value Vr, it is to be bad.
Patent JP-H1118837-A (JP)
Title: Brush for applying hair treatment composition
Inventor: NAKANISHI FUMIO
IPC: A46B5/00
Filed: 1997-07-07
Abstract: PROBLEM TO BE SOLVED: To provide a brush hardly sticking a hair treatment composition to a cheek and a ear and capable of easily applying hair dye to a hair line, sideburns, etc., by providing an attachable and detachable brush part at a tip part in a direction opposite to the grasping handle of a brush pedestal. SOLUTION: A connection part 7 is erected in a direction oblique to the upper surface of the brush base 3 from the center of the tip part of the base 3 to connect the base 3 to a brush handle 5 with the part 7. Then, a nearly- waveformed finger fitting surface 6 forming recesses 6a, 6c and 6d is provided on the lower surface of the handle 5. In addition, plural brush teeth 4 are provided so as to array on the lower surface 3b of the pedestal nearly in parallel with a long edge. In addition, an attachable/detachable brush 2 is provided at the tip part 3c in a direction opposite to the part 7 of the pedestal 3. Thereby, at the time of applying the hair line and the sideburns with the brush 2a, the skin of a forehead, ears, cheeks, etc., is prevented from being made dirt with hair dye by the teeth 4.
Patent JP-H0646422-A (JP)
Title: Catv network monitoring system
Inventor: SASAKO HARUNO
IPC: H04L12/44
Filed: 1992-07-24
Abstract: PURPOSE:To shorten the faults holding time of an entire network in a short time when these faults occur and then to control the errors caused by the burst noises specific to a CATV in a CATV network monitoring system of a tree constitution. CONSTITUTION:The ordinary monitor polling is successively applied to the communication controller 3RF-MODM 4a, 4b and 4c and the status monitor units 5a, 5b and 5c from a control processor 1 in the timing of a monitor polling timer 6. If the answer data on a certain status monitor unit is not obtained, the address of the monitor unit is stored in a storage 2, then the processor 1 gives a retransmission request to the address stored in the storage 2 with an interruption applied to the monitor polling in the timing of an interruption timer 7. Thus a fault judgement is conducted.
Patent JP-2001021355-A (JP)
Title: Surveying device and surveying method in pipe jacking method
Inventor: INABA TOMIO
IPC: G01C15/00
Filed: 1999-07-12
Abstract: PROBLEM TO BE SOLVED: To provide a surveying device capable of efficiently realizing highly precise surveying, and suitable to be used for a pipe jacking method. SOLUTION: This surveying device S is provided with a device main body 10 arranged so as to be freely revolvable in a horizontal direction in a set state, a measuring function part 30 arranged so as to be freely resolvable in a vertical direction in the device main body 10, an optical range finding part 33 arranged in the measuring function part 30, a reflecting part 34 for range finding arranged in the measuring function part 30 in a vertical face in which the collimation direction of the optical range finding part 33 is included, an angle measuring light irradiating part 38 arranged in the measuring function part 30 for irradiating light beams for angle measurement to the same direction as the collimation direction of the optical range finding part 3,  and an angle measuring light receiving part 36 arranged so as to be made adjacent to the angle measuring light irradiating part 38 in the measuring function part 30 for receiving the light beams for angle measurement.
Patent JP-H1139160-A (JP)
Title: Programmable controller
Inventor: KUSAKABE HIROYUKI
IPC: G05B19/05
Filed: 1997-07-24
Abstract: PROBLEM TO BE SOLVED: To provide a programmable controller which can execute a program at a high speed. SOLUTION: When word addresses for one circuit are stored in a 1st word address buffer 10 for every instruction, a coincidence flag 13 is set if any word address is coincident with one of those preceding word addresses for one circuit. A data memory control circuit 12 fetches from a memory 1 the data on the word address to which no flag 13 is set and then fetches data on other word addresses from a 2nd data buffer 16 which stores the preceding data for one circuit. As a result, the access frequency to the memory 1 can be decreased.
Patent JP-H0861553-A (JP)
Title: Fluid control valve
Inventor: SAWARA SHIROKI
IPC: F16K37/00
Filed: 1994-08-23
Abstract: PURPOSE: To provide a fluid control valve whose opening/closing condition can be distinguished easily, quickly, and accurately so that risk of misjudgement is precluded. CONSTITUTION: At the peripheral surface of a bonnet 18 a valve opening/closing condition display part 41 is formed, which is concealed by a handle 23, when a disc (valve seal member) 30 mounted at the tip of a valve rod 20 comes in tight attachmemt with a valve seat 16 so that the gas flow-path 12 is shut, and which is exposed to become visible when the disc 30 is separated from the valve seat 16 so that the gas flow-path 12 is opened.
Patent JP-S6442166-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: MIURA KENJI
IPC: H01L21/8242
Filed: 1987-08-10
Abstract: PURPOSE:To improve the isolation characteristics on a groove side surface by restricting a leakage current flowing along the groove side surface by locating an impurity distribution across a semiconductor substrate in the order of a high concentration layer, a low concentration layer, and a high concentration layer from the surface side. CONSTITUTION:A high concentration semiconductor substrate 100 includes thereon an epitaxial growth low concentration layer 101 containing the same polarity impurity as that of the substrate and a higher concentration layer 102 provided on said low concentration layer and containing the same polarity conductive impurity as that of the substrate on a principal surface region of the substrate. Since an impurity distribution is provided as p/p<->/p<+>, there is a potential barrier against electrons between p/p<->, allowing a reverse electric field to those electrons to be generated therebetween. For this, there is a reduction in rate of electrons, produced upon alpha-ray incidence, reaching the substrate surface, thus improving soft error resistance. Additionally, there exist the high concentration layer on the semiconductor substrate surface, threshold voltage of a parasitic MOSFET formed on the groove side surface can be considerably high, thereby restricting a leakage current flowing along the groove side surface assurance of good isolation characteristics on the groove side surface.
Patent JP-H0644016-A (JP)
Title: Plotting device
Inventor: HASHIMOTO NAOKI
IPC: G06F3/12
Filed: 1992-07-24
Abstract: PURPOSE:To obtain an plotting output corresponding to the necessity of a user by providing a means for selecting whether a bit image is generated or a preferential bit image is generated in an OR-processing. CONSTITUTION:A storage means 11 stores the bit image. An input means 12 receives plotting information transmitted from a host computer and a transmission means 13 transmits inputted plotting information as input bit data. An OR-processing means 14 OR-operates held bit data which is previously held in the storage means 11 and input bit data and obtains processing bit information. A preferential write processing means 15 preferentially writes input bit data as against held bit data so as to obtain processing bit information. A processing selection means 16 selects the OR-processing means 14 and the preferential write processing means 15.
Patent JP-S5896748-A (JP)
Title: Measuring device for semiconductor device
Inventor: SAKAMOTO TETSUYA
IPC: G01R31/26
Filed: 1981-12-04
Abstract: PURPOSE:To perform the measurement of a semiconductor device in stable condition by a method wherein the sample is pressed to be fixed by a press lever before leads and contact pieces of jigs are to come in contact mutually, and fixation by pressing is released before both are separated after measurement. CONSTITUTION:When a jig 6 stopped at the measuring position and the jigs 2, 3 come down, because the lower edge of the press lever 8 is positioned lower than the lower edges of the contact pieces 2, 3 by the interval l, the lower edge of the lever 8 comes in contact with the sample before the respective contact pieces come in contact with the leads 1a, 1b of the sample 1, and after the sample 1 is pressed to be fixed by a spring 10, the contact pieces 2, 3 come in contact with the leads 1a, 1b. Accordingly contact can be performed normally even to the deformed lead, and an electric test can be performed. Because action is performed in reverse order thereof after measurement, the sample 1 does not jump out from a groove 6a of the jig 6, no hindrance is applied to after work, and precise measurement can be performed and enhancement of workability can be obtained.
Patent JP-H1145595-A (JP)
Title: Error correcting circuit for multilevel cell
Inventor: MATSUBARA HIROYUKI
IPC: G11C29/42
Filed: 1997-07-24
Abstract: PROBLEM TO BE SOLVED: To provide an error correcting circuit which can correct further more error patterns compared with the conventional error correcting circuit for mutlilevel cell. SOLUTION: Four-level information signals or parity signals read in parallel from plural memory cells 1 are each converted to two bit data and parity bits by plural AD converters 2. In these data and parity bits of each two bits, the bits on two sides are supplied to a syndrome calculating circuit 30 and a syndrome calculating circuit 31 to calculate syndromes. Syndrome decoder circuits 40, 41 output decoder values based on the syndromes inputted from the syndrome calculating circuits 30, 31. Correcting circuits 50, 51 apply exclusive logic sum calculation to the decoder values and the data inputted from the AD converter 2 to correct errors.
Patent JP-H0752047-A (JP)
Title: Accurate electrodeposition method for abrasive grain
Inventor: NOBUHARA MASAKI
IPC: B24D3/06
Filed: 1993-08-10
Abstract: PURPOSE:To provide an electrodeposited tool of which the discharge route of chips is insured and working efficiency is high by optionally controlling the electrodeposited positions of individual abrasive grains. CONSTITUTION:A dielectric substance 14 having sticking force and polarizing in the voltage impressed condition is spread on the surface of a tool base metal 13 in a decided pattern, and a dielectric substance 16 polarizing in the voltage impressed condition is spread on the surface of abrasive grains 15. When voltage is impressed between both substances, both are polarized, reverse charges are faced and attracted to each other, and hence individual abrasive grains are attracted and stuck to the dielectric substance 14. Next, a plating layer is formed on the surface of the tool base metal by electrolytic plating or electroless plating so as to fix the abrasive grains.
Patent JP-2001025436-A (JP)
Title: Rice cooker
Inventor: KANETANI SADAO
IPC: A47J27/00
Filed: 1999-07-13
Abstract: PROBLEM TO BE SOLVED: To suppress contamination on the surfaces of a main body and a lid body, and facilitate the maintenance and the cleaning of the contamination by forming the main body wherein the upper opening is covered by the lid body, and an internal pot is housed inside, of an upper frame, an external wall made of a magnetic metal material, and a bottom plate. SOLUTION: When cooking a rice, an internal pot 3 in which water and rice of specified amounts are contained, is housed in a rice cooker main body 1, and the upper opening is closed by a lid body 2. Then, a control panel 9 is controlled, and the internal pot 3 is heated by energization-controlling an induction heating coil 4 by a control section 14. Steam generated at this time is discharged from a steam discharging device 17. Then, a lid heater 20 and a body heater 34 are heat-controlled by the control section 14, and cooked rice is kept warm. In this case, the external wall 32a of an upper case 32 and the upper plate 36 of a lid case 35 in the main body case 3 are respectively formed of a base material comprising a non-magnetic metal material on the external surface of which a resin layer is coated.  Further, a cover member 43 made of the same base material is arranged on the upper surface of the steam discharging device 17.
Patent JP-2000025803-A (JP)
Title: Outer lid for can
Inventor: MATSUNO ICHIRO
IPC: B65D51/18
Filed: 1998-07-14
Abstract: PROBLEM TO BE SOLVED: To prevent positively mischief to remove an outer lid when the lid is being kept at unopened state and further enable a cut removing operation for a second skirt section to be easily carried out. SOLUTION: A holding piece 24 separately removed by breakage of a breakage starting score 18 is arranged at a cut starting section 17 of a second skirt part 13 provided at an outer lid 5 and cut removed through a score 12 when the lid is opened. An inner surface of the holding piece 24 is provided with a protrusion 26 for forming a clearance between it and a can barrel 2 to cause a user's finger to be hooked there. An outer surface of a second skirt 13 extending along an upper side of the breakage starting score 18 is provided with a protrusion 25 projected outwardly from the outer surface of a holding piece 24 having a finger tip engaging clearance formed by a protrusion 26.
Patent JP-H1023462-A (JP)
Title: Scanning converter
Inventor: MIZUNO TAKASHI
IPC: H04N5/44
Filed: 1996-07-08
Abstract: PROBLEM TO BE SOLVED: To avoid flicker, blur and crushing included in a scanning converter. SOLUTION: Respective analog signals of R, G, B inputted from a connector 22 are inputted to an A/D converter 20A and converted into digital signals synchronously with a clock signal CLK outputted from a synchronization controller 20B. The digital signals are inputted to memories 20F, 20G in each line and inputted to an adding/shifting circuit 20J together with outputs from line buffers 20H, 20I. The circuit 20J successively inputs three continuous horizontal scanning line R, G, B signals, executes weighted mean processing based on prescribed weight in each horizontal scanning line and prepares an NTSC field signal.  The field signal faithfully reflects the R, G or B analog signals to be original information by executing maximum weighting for the corresponding R, G or B signal, and since prescribed weighting for the R, G and B signals on a line before and after the signal concerned is also executed, prescribed correlation can be obtained.
Patent JP-H1018207-A (JP)
Title: Block made of inorganic waste material for effective use thereof
Inventor: YAMAMOTO KIMIJI
IPC: E01C5/06
Filed: 1996-07-08
Abstract: PROBLEM TO BE SOLVED: To effectively use a large quantity of inorganic waste material, by sticking wooden or plastic decoration boards on the surface of a block made of inorganic waste materials solidified by cement, with an adhesive. SOLUTION: Incinerator slag of rubbish, human waste, and sewage sludge and various industrial wastes are crushed and the size is adjusted as concrete aggregate and then the material is solidified with cement to form blocks. Wooden or plastic decoration boards are stuck on the surface of the block with an organic or inorganic adhesive to completely cover the block surface. The thickness of the decoration board is the same with the size usually used but it is preferable that a board as thin as possible is used if the strength is guaranteed. The inorganic wastes are charged in a structure like a pavement in order to dispose them and effectively use a large quantity thereof.
Patent JP-2000032365-A (JP)
Title: Error rate detecting circuit and reception terminal equipment
Inventor: SAWAMURA HIROYUKI
IPC: H04N5/44
Filed: 1998-07-14
Abstract: PROBLEM TO BE SOLVED: To detect and measure the bit error of a transmission error caused by a transmission line during the operation of digital broadcasting and digital data transmission. SOLUTION: This equipment is provided with an error correcting circuit 1 for performing the error correction of a digital stream signal, corrected bit number detecting and holding circuit 2 for detecting and holding the number of corrected bits, reference bit number table circuit 3 for holding the reference number of bits to be calculated at every unit time, division circuit 4 for dividing the number of corrected bits with the reference number of bits, and output circuit 5 for outputting the divided result of the division circuit 4.
Patent JP-H1135524-A (JP)
Title: Cross linkable compound and material for ocular lens produced therefrom
Inventor: HIRATANI HARUYUKI
IPC: C08F290/06
Filed: 1997-07-24
Abstract: PROBLEM TO BE SOLVED: To obtain the subject new compound excellent in surface wettability and transparency and having proper hardness and oxygen permeability. SOLUTION: This compound is expressed by formula I [Z<1> and Z<2> are each a group expressed by formula II (R<3> is a 1-10C alkylene), etc.], e.g. the compound expressed by formula III. The compound expressed by formula I is obtained by, e.g. subjecting trimellitic acid anhydride chloride and the first monomer having a hydroxy group and a polymerizable unsaturated double bond to esterification in the presence of a tertiary amine in a solvent, such as benzene, at room temperature or below to synthesize trimellitic anhydride having a polymerizable unsaturated double bond expressed by formula V (Z<3> is a group expressed by formula II, etc.), and subjecting this anhydride and the second monomer having a hydroxy group and polymerizable unsaturated double bond to esterification in the presence of a tertiary amine in a solvent, such as ethyl acetate at about 50 deg.C.
Patent JP-S58100435-A (JP)
Title: Manufacture of semiconductor device
Inventor: ONO TOSHIHIKO
IPC: H01L21/316
Filed: 1981-12-10
Abstract: PURPOSE:To enhance sharply the dampproof property of the device by a method wherein a protectively insulating film consisting of a glass layer is formed directly on a wiring and the wiring formed face according to the bias sputtering method. CONSTITUTION:A high pure quartz (SiO2) plate 11 is fixed on the first electrode 9 of a parallel plane type sputtering device, and a semiconductor substrate 12 to be processed is fixed on the second electrode 10. Argon (Ar) gas is flowed in from a gas introducing port 6, and the inside of a reaction vessel 8 is held in the Ar atmosphere. The first electrode 9 is earthed G, a high-frequency voltage RF is applied between the first electrode 9 and the second electrode 10, and the sputtering process is performed applying a DC negative bias voltage B to the second electrode 10. Accumulation of the protective film 13 consisting of SiO2 is advanced, steep step parts 3 formed on the sides of the wiring 1 are buried gently, and no dislocation is generated in the step parts of the protectively insulating film 13.
Patent JP-S6091777-A (JP)
Title: Contrast adjusting circuit
Inventor: OOSAWA MICHITAKA
IPC: H04N5/57
Filed: 1983-10-26
Abstract: PURPOSE:To eliminate oscillation/vibration or the like and to quicken the response speed by performing independently contrast adjustment from an image pickup signal period. CONSTITUTION:A black level of a video signal is clamped to a value at a clamp circuit 5. The signal is inputted to an attenuation circuit, attenuated in response to the resistance ratio of resistors 2, 3 and outputted to an output terminal O. The black level signal of the video signal is attenuated in response similarly to the value of the resistors 2, 3. Thus, the black level signal of the video signal appearing at a terminal F is a value proportional to the resistance value of a variable resistor 3. In increasing/decreasing the voltage level of the black level signal in response to the output of a contrast adjustment power supply 7, the contrast is adjusted. since the voltage level of the black level signal is proportional to the resistance value of the variable resistor 3, the output of the contrast adjustment power supply 7 and the value of the black level signal are compared and fed back to the variable resistor 3 so as to change the resistance value.
Patent JP-S6091290-A (JP)
Inventor: ISHIDA TAKAYUKI
IPC: G21C17/00
Filed: 1983-10-26
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H0926412-A (JP)
Title: Ultrasonic flaw detector
Inventor: SUGANUMA RYOSUKE
IPC: G01N29/44
Filed: 1995-07-12
Abstract: PROBLEM TO BE SOLVED: To effectively detect the surface of a sample by comparing a fetched echo digital signal with a reference signal. SOLUTION: A sample 3 is immersed in water 2 contained in a vessel 1, a ultrasonic vibrator 4 is mounted on the surface of the water 2, a transceiver 5 is connected to the vibrator 4, a wave detector 6 is connected to the transceiver 5, an A-D converter 7 is connected to the detector 6, and further a waveform memory 9 is connected to the converter 7. A CPU 9 is connected to the memory 8, further an image memory 10 is connected to the CPU 9, a display unit 11 is connected to the memory 10, a timing controller 12 and a memory controller 13 are connected to the CPU 9, and a timing signal is output from the controller 12 to the transceiver 5, converter 7 and controller 13.