Patent GB-1332329-A (GB)
Title: System for transmitting data via a channel
IPC: G11B20/14
Filed: 1970-11-04
Abstract: 1332329 Digital data storage GENERAL DYNAMICS CORP 4 Nov 1970 [14 Nov 1969 (6)] 52439/70 Heading G4C Binary data comprising a plurality of bits A-D, Fig. 1 is serialized at 16, converted at 18 into 2-bit binary-coded ternary digits (terts), each tert then being recorded as positive, negative or zero magnetization on a magnetic tape from which it may subsequently be recovered and reconverted to binary form utilizing timing signals derived from the recorded data. Each input word of four bits is encoded into a word of four binary coded terts having the values 10, 00, 01 representing +, 0, - respectively, and each ternary word has zero average level. A frame word (FW) is inserted every few hundred data words for synchronization. The arrangement is duplicated for each. of N tape tracks. Playback.-Detector 32 provides binarycoded terts to word shift registers 34 followed by ternary to binary converter 36. The fundamental frequency of the ternary signal is derived at 42 using a peak detector, tank circuit, and tuned amplifier followed by a slicing circuit which detects zero crossings, and cascaded delays at the start, centre and end of each tert period. Outputs from registers 34 are applied to a ladder network 200, Fig. 11 which provides a zero output Z when a valid word is completely located in the registers. A word rate generator 214 divides the start of tert pulses r, by 4 to produce word time pulses and these are gated at 218 with the Z pulses at the end of tert times r 3  and are passed to a good word counter 222. If the Z and WT pulses do not coincide, gate 224 feeds a bad word pulse to a counter 224. Bistable 234 is set when 7 successive good words have been detected and is then not reset until 3 successive bad words have been detected. If bistable 234 is set when a frame word occurs, bi-stable 232 is set to indicate a synchronized condition. If synchronism is lost, the bad word status of bi-stable 234 causes the bad word pulses to clear counter 214 so that a word time pulse is produced in successive tert times until synchronism is regained. After reconversion to binary form at 36, Fig. 6, retiming circuits 38 compensate for tape jitter and skew. The word time pulses from Fig. 11 propogate through a chain of bi-stables, Fig. 14 (not shown) and shift words through four shift-registers in parallel, emergence of a WT pulse from the end of the chain initiating read-out of the word in the last group of register stages on occurrence of the next crystal-controlled word-rate clock pulse. To compensate for skew, the supply of word-rate clock pulses to the jitter-compensating registers for any data channel is inhibited when a frame word is located in that register, and remains inhibited until a frame word has been present in every channel for 3 word times. Error correction.-The words in channels 1-N are summed modulo 18, the result is subtracted from 18, by addition of the 2's complement of 18, to provide a 5-bit-modulo 18 word, the lowest 4 bits of which form a check word which is recorded in an additional channel. A second check word based on channels alternating with those used for the first check word may be provided. On play-back, the binary words are converted to modulo 18 and summed, any word indicated as being erroneous by the absence of a corresponding valid word pulse being omitted from the sum, and the difference between the sum and 18 is gated out as a corrected word for the erroneous channel.