Patent GB-981400-A (GB)
Title: A phase-modulation data transmission system
IPC: H04L27/233
Filed: 1961-08-10
Abstract: 981,400. Phase-shift signalling systems. WESTERN ELECTRIC CO. Inc. Aug. 10, 1961 [Aug. 15, 1960], No. 28878/61. Headings H4L and H4P. In a data transmission system which may be either a twinplex or a single channel system in which successive bits are coded in pairs (dibits) and the four possible combinations of binary digits are transmitted as corresponding phase shifts of a carrier, the carrier is given an additional 45 degrees phase shift between each dibit to simplify the transmission of synchronizing and phase reference information, and a pair of ringing circuits resonant at the carrier frequency are excited alternately by the phase shift signals, the oscillations so produced being amplitude modulated in such manner that the phase transitions occur at minimum carrier amplitude in order to suppress transients, and then combined for transmission. As shown in Fig. 1, binary signals in serial form are supplied to serial-to-parallel buffer 10 which transmits successive pairs of digits in parallel via logic circuit 12 alternately to ringing circuits 13, 14 tuned to the carrier frequency, the ringing circuits being excited in an appropriate odd multiple of 45 degrees phase shift relative to the last phase used. The logic is such that the ringing circuit 13 can only be excited in one of four phases representing the four possible combinations, spaced 90 degrees apart, by phase set No. 1, and ringing circuit 14 can only be excited in one of four phases spaced 90 degrees apart and spaced 45 degrees from those of phase set No. 1, by a phase set No. 2. The two separate output waves are amplitude modulated by a raised cosine wave at half the transmission rate in respective modulators 15, 16 so that the carrier is at minimum amplitude at the intervals during which phase changes occur, the ringing circuits being activated at this instant. The outputs of modulators 15, 16 are added at 17 to form the output signal on line 18. The required timing signals are provided by timing circuits 11. At the receiver, Fig. 2, the incoming phase modulated signals are supplied to a delay line 20 providing a delay of one dibit interval and also to 0 and 90 degrees demodulators 21, 22, and synchronizing signal recovery circuit 23. The delay line provides two outputs in quadrature which are supplied respectively to demodulators 21, 22, as a phase reference signal, the simultaneous outputs of the demodulators always differing in phase by 90 degrees. The outputs of demodulators 21, 22 are integrated respectively at 24, 25 and since an integral number of quarter cycles of carrier wave at each particular phase are arranged to occur in each dibit interval the output of each integrator is either positive or negative at the end of each dibit interval. The polarity of these outputs is sampled to recover the individual signal bits which are converted to serial form at 28 for application to the output terminal. The timing circuits, the serial to parallel registers, logic circuitry for determining the phase to be imparted to the carrier and remembering the phase previously employed, and the ringing circuits and modulators of Fig. 1 are described in detail and a more detailed block diagram of a receiver is included. Specification 981,399 is referred to.