Patent GB-1516973-A (GB)
Title: Analogue storage circuits and systems
IPC: G11C27/04
Filed: 1974-08-10
Abstract: 1516973 Electric analogue stores SOLARTRON ELECTRONIC GROUP Ltd 8 Aug 1975 [10 Aug 1974 7 Sept 1974] 35328/74 and 39186/74 Heading G4G An analogue storage circuit comprises a charge-coupled device 12 through which an analogue signal may be shifted with some attenuation, a circuit 54 which is characterized by providing as an output one of a set of discrete levels which is nearest to its input signal the spacing of the discrete levels being just more than twice the maximum attenuation in device 12, the circuit 54 being arranged to receive as an input the output of the device 12 and to deliver an output back to the input of the device 12 whereby an analogue signal can be introduced at the input of either the device 12 or of circuit 54 and stored in a circulating manner without loss of value except in the first approximation in circuit 54. Shifting through device 12 is by means of three-phase signals # 1 , # 2 , # 3  derived from an oscillator 30 driving a three-stage shift register 33 through which one bit is circulated under the overall control of a circuit 38. During a slight overlap of successive three-phase pulses the input 14 is sampled and preceding inputs are shifted one space through device 12. The output of device 12 is fed to circuit 54 via a variable gain amplifier 22. In Fig. 1 the circuit 54 consists successively of a sample and hold circuit 56 an A to D converter 61 and a D to A converter 65 with an output connected via amplifier 68 back to input 14. In use, data is fed in at 46 with a switch 44 contacting 45 and a start signal applied at 40 to circuit 38 to start the circuit 28. The first # 3  pulse detected over line 58 starts the sample and hold circuit 56 and the next # 2  pulse actuates converter 61 over line 62. The resolution of converter 61 is arranged to be just over twice the maximum attenuation of a circulating signal. When the circuit 38 detects that device 12 is full the switch 44 is reversed preventing further inputs entering at 46 and permitting circulation of the stored charges. Fig. 4 shows in detail an alternative form of circuit 54. In this circuit there are emitter coupled pairs of transistors such as TR6-1, TR7-1 fed by constant current circuits such as TR8-1, one such group of transistors for each discrete output level. The collectors of the TR6 transistors are connected to a potential divider chain R1 to R9 the interconnections of which define the discrete output levels. With a minimum input at 73 all the TR7 transistors are on, feeding maximum current through a resistor 85, and all the TR6 transistors are off. As the input voltage increases successives ones of the TR6-TR7 circuits charge states causing a discrete drop in current through resistor 85 with a consequential discrete drop in output voltage at 66a. To provide a sharply defined staircase characteristic positive feedback between output 66a and input 73 is applied via an f.e.t. 75. Fig. 7 (not shown) shows a modified circuit in which there are emitter coupled pairs for each discrete output level, these controlling further pairs of transistors acting as differential amplifiers which, as the input voltage varies, are rendered operative or inoperative as negative feedback paths. In Fig. 6 (not shown) further similar analogue storage channels are provided to operate on the difference between the true values of inputs and the values assigned by circuit 54 in a manner analogous to the main drain, output values of the channels being combined for read-out with adjustments according to significance.