Patent GB-850700-A (GB)
Title: Improvements in or relating to circuits for sampling oscilloscopes
Inventor: CHAPLIN GEORGE BRIAN BARRIE
IPC: G01R13/34
Filed: 1957-12-03
Abstract: 850,700. Transistor circuits; cathode ray tube oscilloscopes. UNITED KINGDOM ATOMIC ENERGY AUTHORITY. Dec. 2, 1958 [Dec. 3, 1957], No. 37642/57. Classes 40(6) and 40(7). A time base circuit, more particularly for a sampling oscilloscope, comprises a transistor arranged in a trigger circuit and having a step wave generated across a capacitor connected to one of its control electrodes and sawtooth wave generated at another control electrode, the transistor being rendered conducting when the instantaneous amplitude of the sawtooth wave attains a predetermined relation to the step wave amplitude, so as to cause an incremental change of voltage to occur across the capacitor to produce the next step and also to cause a fast edged pulse to be produced. The sampling oscilloscope described samples successive portions of successive input waves to provide a Y deflection and also generates a step wave for providing the X deflection, so that the wave form being examined is drawn as a succession of dots obtained from successive input waves. The step wave is generated in a circuit 2 providing an output at X 1  each step being produced in response to the output of a pre-pulse unit 1 triggered by the wave to be examined or by a separate source of pulses. At each step the generator 2 also produces an output pulse which is applied to a sampling pulse generator 3 feeding its output to a sampling circuit 5. The sample of the input wave applied to the input terminal is amplified in a circuit 6 and fed to a memory circuit 7, 8 which provides the Y deflection, maintaining the deflection constant until the next sample is taken. The input for the sampling pulse generator 3 is provided when a sawtooth stroke generated in circuit 2 in response to the prepulse reaches the value obtained by the step wave so that at each step the sampling pulse delay with respect to the prepulse is increased. When the desired number of steps has been produced the amplitude of the step wave is sufficient to operate a resetting circuit 4 which restores the step wave to its initial value. The step wave and delayed sampling pulse generator 2 comprises a capacitor C3 which, when diode D2 is rendered non-conducting by a prepulse derived from unit 1, charges substantially linearly through a resistor R3. When the capacitor voltage exceeds that across a capacitor C2 connected to the emitter, the transistor conducts in an avalanche manner discharging a capacitor C4 into capacitor C2 increasing its voltage incrementally. The current through capacitor C4 triggers a blocking oscillator circuit J6, the resulting output pulse causing a capacitor C3 to discharge through a diode D4. Instead of charging capacitor C2 through transistor J2 it could alternatively be charged by a subsequent trigger circuit. The prepulse applied to unit 2 is obtained from a blocking oscillator circuit 1 which operates in response to input pulses applied to the base. These pulses cause the transistor to operate initially in an avalanche mode during which time a first transformer TR1 is effective. Subsequently a second transformer TR2 becomes effective to maintain the transistor conducting. A diode D1 catches the collector voltage at -12 volts and a capacitor C1 causes a voltage to appear across the transformer before the catching is effective and may be adjusted to provide an overshoot. A capacitor C11 slows the rise time to ensure triggering. The sampling pulse amplifier 3 comprises an avalanche mode transistor J3 feeding the sampling unit 5. The sampling unit 5 receives its signal input through capacitor C7 and resistances R11 and 12 adapted to maintain the D.C. attenuation equal to the A.C. attenuation and its sampling pulse input via a winding on transformer TR6, the sampling pulses being prevented from reaching the signal input circuit by means of a neutralizing capacitor C8. It is suggested that both the input and the sampling pulse could be applied to the emitter and also that C8 could be connected to earth. The sample obtained from the collector is amplified in a circuit 6 and applied to an amplifying memory unit 7, 8. The sample amplifying memory unit 7, 8 receives a pulse from unit 2 at the commencement of each step. This pulse renders a transistor J8 conducting so that a capacitor C10 is discharged through a diode D14. A diode D6 is cut off so that a capacitor C9, connected in "Miller" fashion to a transistor J7 is charged by the sample obtained from the amplifier 6 to an extent dependent upon the sample amplitude. When transistor J8 cuts off the capacitor C9 discharges into capacitor C10. The charge which is transferred being increased by a factor (1 + α<SP>1</SP>) times the charge in C9 due to the amplifying action of transistor J7. The voltage across capacitor C10 constitutes the " Y" output and remains constant until the next sample is taken. The memory circuit could be replaced by a diode arrangement such as that illustrated in Fig. 3 (not shown). In an alternative arrangement shown in Fig. 4, the number of functions performed by some of the transistors is reduced. In the step wave and fast pulse generator 2<SP>1</SP> the functions of the emitter and base of the main transistor J10 are reversed, the step wave being applied to the base electrode from capacitor C2<SP>1</SP> through an emitter follower transistor J9 while the sawtooth wave is generated at the emitter. This sawtooth wave is generated by applying pulses from the blocking oscillator 1<SP>1</SP> through R15 to capacitor C14. A diode may be connected across R15 to by-pass emitter current when the transistor is non-conducting. When transistor J10 (corresponding to J2 in Fig. 1) becomes conducting a pulse is produced across resistor R16 which is applied to the sampling pulse amplifier 3<SP>1</SP>: Transistor J11 (corresponding to transistor J6 in Fig. 1) produces pulses in its output transformer which cause transistor J12 to discharge capacitor C2<SP>1</SP> in closely controlled steps, the transistor being isolated from capacitor at other times by a low leakage silicon diode D8. To prevent transistors J10 from being retriggered by the continued application of a pulse from circuit 1<SP>1</SP>, a further pulse is applied to the base emitter path of transistor J10 from a winding on the output transformer of J11 through a diode D17. The reset circuit 4<SP>1</SP> includes an additional transistor J13 in parallel with the blocking oscillator transistor J4<SP>1</SP> to assist in resetting the voltage across the sawtooth capacitor C2<SP>1</SP>. Diodes D5<SP>1</SP> and D11 prevent leakage current in transistors J4<SP>1</SP> and J13 effecting the charge on capacitor C2<SP>1</SP>. The sampling circuit 5<SP>1</SP> comprises a network C18, R22 to remove a dip in the frequency response characteristic by preventing the secondary winding of transformer TR6<SP>1</SP> from resonating with the emitter base capacitance of transistor J5<SP>1</SP>. In the circuit above the unit 5<SP>1</SP> and possibly 3<SP>1</SP> are mounted in a probe. If two probes are provided and gated by pulses derived from the prepulse unit 1, two wave forms may be displayed simultaneously, successive dots being obtained from alternate input wave forms. In addition, by controlling the bias applied to appropriate points in the circuit the characteristics of the waves may be measured.