baber/WOPTO huggingface dataset:
Patent TW-464764-B (TW)
Title: Measurement circuit of chip capacitance
Inventor: FAN JEN-TENG
IPC: G01R31/26
Filed: 2000-06-14
Granted: 2001-11-21
Abstract: A kind of measurement circuit for chip capacitance includes the followings: the measurement circuit, which is composed of three pairs of completely matched PMOS and NMOS respectively belonging to two symmetric circuits such that the chip capacitance to be measured is obtained by using the measurement circuit to measure the difference of averaged charging current for the capacitors on both left and right sides; one power supply, which supplies a constant voltage source to the measurement circuit; one current measurement apparatus, which measures the current value flowing from power supply into measurement circuit; and one signal generator, which provides one set of three-phase non-overlapped clock signals for the measurement circuit. Thus, chip capacitance measurement circuit is capable of effectively suppressing the measurement error caused by the reverse current with different magnitudes, which is generated due to MOS transient phenomenon, flowing back to the current measurement apparatus; additionally, measurement accuracy of chip capacitance is increased.
Patent TW-589311-B (TW)
Title: Neurotrophic pyrrolidines and piperidines, and related compositions and methods
Inventor: KANOJIA RAMESH
IPC: A61K31/445
Filed: 2000-09-18
Granted: 2004-06-01
Abstract: This invention provides compounds having the following general structures. This invention also provides pharmaceutical compositions comprising same and methods of using these compositions to treat and prevent disorders characterized by neuronal damage.
Patent TW-500948-B (TW)
Title: Liquid crystal display device
Inventor: NAKAJIMA TAKESHI
IPC: H01L21/336
Filed: 2000-07-31
Granted: 2002-09-01
Abstract: The purpose of the present invention is to obtain a liquid crystal display device having a horizontal electric field manner, the display characteristic with wide view angle and easy manufacture with low production cost by decreasing defects called as load traces. The load traces are display defects caused by loading on the display face and can be recognized for a long time even after the load is removed. The solving means is described as follows. The front ends of a pixel electrode 10 and a counter electrode 11 are provided with bending portions 10a and 11a, which are bent toward the direction opposite to the alignment direction of a liquid crystal to a source wiring 12. The angle θ e from the bending portions 10a and 11a to the source wiring 12 is set in the range 1 DEG < θe < 90 DEG. Thus, the electric field direction at the top ends of the pixel electrode 10 and the counter electrode 11 can be controlled to the direction where the liquid crystal is required to rotate. In addition, because the liquid crystal rotating in the opposite direction can be quickly returned to the correct rotation direction by loading, the load traces can be quickly decreased to raise the display quality. Furthermore, since a protective plate to prevent loading on the display face is not necessary, the production cost of the liquid crystal display device can be reduced.
Patent TW-449929-B (TW)
Title: Structure and manufacturing method of amorphous-silicon thin film transistor array
Inventor: CHEN JR-HONG
IPC: H01L21/461
Filed: 2000-08-02
Granted: 2001-08-11
Abstract: There are provided a structure and a manufacturing method of amorphous-silicon thin film transistor array. The structure comprises a substrate, a gate electrode, a gate insulation layer, an amorphous-silicon active layer, a n+ amorphous-silicon layer, and a metal layer for defining a source electrode and a drain electrode. This structure simplifies the photolithography process and uses less mask steps to manufacture. Furthermore, it is able to avoid the opening of the second metal layer and the short circuit problem in the first metal layer and second metal layer caused by the photoresist residual and particle contamination. The manufacturing method combines the standard back-channel-etching simplified mask process and the two-step exposure technique for manufacturing. The two-step exposure technique utilizes two exposure pattern, one being a fully exposed pattern and the other one being a partially exposed pattern, to perform a two-step exposure process. The partially exposed pattern continues to perform an oxide plasma etching. The manufacturing method is provided with the feature of island metal mask structure, which is able to protect the active layer from being damaged by the plasma in the plasma process.
Patent TW-493343-B (TW)
Title: Broadcast reception apparatus, broadcast reception system, and portable information terminal
Inventor: ITO TAKESHI
IPC: H04N5/44
Filed: 2000-08-29
Granted: 2002-07-01
Abstract: Data of a data broadcast received by a television receiver (10) is reproduced at a desired time by a portable information terminal (14) powered by a secondary battery (84). The television receiver (10) has a slot (18) having a data transmitting terminal and a battery charging terminal therein. When the portable information terminal (14) with the secondary battery included therein is inserted in the slot (18), the secondary battery is charged through the battery charging terminal, and data supplied through the data transmitting terminal is stored into a data storage in the portable information terminal (14). The data stored in the data storage can be reproduced on a liquid-crystal display unit (12) of the portable information terminal (14) while the portable information terminal (14) is being carried by the user.
Patent TW-486448-B (TW)
Title: Process for producing fluorinated silicon compound
Inventor: FUKUMURA KOUKI
IPC: C07F7/08
Filed: 2000-09-15
Granted: 2002-05-11
Abstract: There is disclosed a convenient and efficient process for producing a fluorinated silicon compound which comprises reacting a silicon compound having at least one group selected from the group consisting of a hydroxyl group, an alkoxy group, and an aryloxy group bonded to silicon atom, with a compound represented by the formula (1): wherein R1, R2, R3, and R4 may be the same or different, and each represents a substituted or unsubstituted, saturated or unsaturated alkyl group, or a substituted or unsubstituted aryl group; and R1 and R2 or R3 and R4 can bond to form a ring having one or more nitrogen atoms or having one or more nitrogen atoms and other hetero atoms; or R1 and R3 can bond to form a ring having two or more nitrogen atoms or having two or more nitrogen atoms and other hetero atoms, to fluorinate the groups.
Patent TW-463236-B (TW)
Title: Microlithography process to prevent curved pattern
Inventor: HUANG JIUN-REN
IPC: H01L21/027
Filed: 2000-11-22
Granted: 2001-11-11
Abstract: A microlithography process to prevent curved pattern is disclosed, which comprises: first, provide a wafer, form a first photoresist layer on the wafer. Next, patternize the first photoresist to form the first photoresist line along the first direction in parallel. Then form a second photoresist layer on the wafer. Patternize the second photoresist to form the second photoresist line along the second direction in parallel, wherein the first direction and the second direction are coplanar and are mutually perpendicular.
Patent TW-486795-B (TW)
Title: Fabrication method for a matrix strip as a chip support element and for semiconductor packaging elements with the matrix strip
Inventor: LIOU SHING-JENG
IPC: H01L23/32
Filed: 2001-04-18
Granted: 2002-05-11
Abstract: A matrix strip used as a chip support element has a first surface and a second surface and is constituted by a plurality of leadframes arranged in a matrix, connection portions disposed between the adjacent leadframes, and side portions. In addition, each leadframe has a chip pad and each connection portion is provided with at least an E-pin hole passing through the matrix strip. Fabrication method for semiconductor packaging elements with the matrix strip includes the following steps: providing the matrix strip having the first surface and the second surface and constituted by a plurality of leadframes arranged in the matrix, connection portions disposed between the adjacent leadframes, and side portions, in which each leadframe has a chip pad and each connection portion is provided with at least an E-pin hole passing through the matrix strip; adhering a tape to the second surface of the matrix strip, and placing individually the semiconductor chip onto the chip pad in order that the chip can be supported by the corresponding chip pad of the leadframe on the first surface of the matrix strip, and the semiconductor chip can electrically connect to the leadframe; encapsulating respectively the semiconductor chip such that the encapsulant can cover each semiconductor chip and the leadframe, but the second surface of the matrix strip remains uncovered; passing a plurality of E-pins through the E-pin holes from the first surface of the matrix strip in order to push the tape away from the second surface of the matrix strip; and conducting the singulation operation to form the individual semiconductor packaging element. Because the tape adhered to the matrix strip is pushed away by passing the E-pins through the E-pin holes to generate the air gap between the contact surface of the tape and the matrix strip, which further helps the detachment of the tape, the manufacturing process becomes much easier. Besides, it does not increase the difficulty during the manufacturing operation to add the E-pin holes in the matrix strip, so the production cost will not be changed.
Patent TW-511203-B (TW)
Title: Erase method of flash memory
Inventor: JOU MING-HUNG
IPC: G11C16/34
Filed: 2001-04-20
Granted: 2002-11-21
Abstract: An erase method of flash memory is introduced. It comprises the following steps. First, give the memory cell gate a bias Vg and source/drain a bias Vd to execute erase operation. The Vd follows the time to increase from a initial value to a preset value and the verification step is not applied during this period. Then check each cells are already erased or not. If the answer is yes, finish the erase operation; otherwise, proceed at least one time of erase-verification step till all of the cells being erased. Where each erase-verification step comprises a erase step with a raised bias Vd and a verification step later.
Patent TW-511444-B (TW)
Title: Housing for monitor
Inventor: FUJIMOTO YOSHITAKA
IPC: H04N5/64
Filed: 2001-05-02
Granted: 2002-11-21
Abstract: The object of the invention is to solve a problem of a conventional housing for a CCTV monitor that has caused trouble from the standpoints of the safety and the convenience because the monitor receiver itself has a considerable weight resulting in requiring the housing made of joined stiff metallic plates by welding or the like, suspended from a beam of a ceiling or a steel skeleton of a station office or a platform and supported at a prescribed height and resulting in requiring a stepladder in the case of maintenance of the monitor. To solve the problem, the present invention is characterized in comprising a stationary side housing main body consisting of an upper plate, left and right side plates and a back plate that are joined together, a moving base that is supported movably in the vertical direction with respect to the stationary side housing main body, and a support mechanism that supports the moving base movably in the vertical direction with respect to the stationary side housing main body.
Patent TW-577787-B (TW)
Title: Polisher
Inventor: UENO MAKOTO
IPC: B24B29/00
Filed: 2001-07-12
Granted: 2004-03-01
Abstract: To provide a polisher capable of polishing a coated surface smoothly with a simple and easy operation. The polisher including a base member which is rotatably driven by a driving device and having a mounting surface which is orthogonal to a rotational axis thereof, a resilient member attached to the base member, and a polishing member attached to the resilient member, and wherein the resilient member has grooves, each groove being opened to the side of the polishing member and extending from the center of the resilient member in a direction of a peripheral edge thereof, and open edges of each groove are straight lines extending from the center of the resilient member toward the peripheral edge thereof.
Patent TW-I246075-B (TW)
Title: Optical recording medium and process for producing an optical recording medium
Inventor: OHNO TAKASHI
IPC: G11B7/243
Filed: 2001-07-31
Granted: 2005-12-21
Abstract: An optical disc having excellent recording/retrieving characteristics and capable of improving the surface properties of the reflective layer without reducing the thermal conductivity, the reflectivity and producibility. An optical recording medium for recording and/or retrieving information by irradiation of light, which comprises a substrate, and an interlayer, a reflective layer containing a metal as the main component and a recording layer, formed in this order on the substrate directly or via another layer made of a resin or a dielectric material, wherein as observed from a light-incoming direction, the reflective layer is located in front of the interlayer, the interlayer contains the same metal as the metal constituting the main component of the reflective layer and also contains oxygen and/or nitrogen, and the interlayer has a content of the metal smaller than the reflective layer.
Patent TW-I244486-B (TW)
Title: Novel anti-inflammatory androstane derivative
Inventor: BIGGADIKE KEITH
IPC: A61P/
Filed: 2001-08-03
Granted: 2005-12-01
Abstract: According to one aspect of the invention, there is provided a compound of formula (I) and solvates thereof. There are also provided compositions containing the compound, processes for preparing it, and its use in therapy.
Patent TW-495642-B (TW)
Title: Automatic flash light device of digital camera and method of the same
Inventor: TZENG LI-WEN
IPC: G03B15/03
Filed: 2001-10-17
Granted: 2002-07-21
Abstract: The present invention is an automatic flash light device of digital camera and method of the same, wherein a variable reference voltage signal is provided based on the multiplied product of the analog gain, digital gain and Gamma value of digital camera, so as to sense the brightness of light during generating the flash light for proceeding photographing, and to stop the flash light when the voltage signal representing the brightness of light is larger than the variable reference voltage signal, so that the same flash light exposure effect can be obtained whatever gain setting is.
Patent TW-567467-B (TW)
Title: Magneto-optical recording medium and method of reproducing the same
Inventor: TANAKA TSUTOMU
IPC: G11B11/105
Filed: 2001-10-26
Granted: 2003-12-21
Abstract: A magneto-optical recording medium comprising four magnetic layers including a mask layer, a reproduction layer, an intermediate layer and a recording layer, wherein the reproduction layer and the recording layer each have a direction of easy magnetization extending in a layer stacking direction at room temperature, the mask layer and the intermediate layer each have a direction of easy magnetization extending in an in-plane direction at room temperature, the mask layer, the reproduction layer, the intermediate layer and the recording layer have Curie temperatures Tc1, Tc2, Tc3 and Tc4, respectively, which satisfy relationships of Tc3 < Tc2, Tc3 < Tc4 and Tc3 < Tc1, and the intermediate layer is a rare-earth-rich magnetic layer.
Patent TW-I226439-B (TW)
Title: Plating bath analysis
Inventor: SONNENBERG WADE
IPC: G01N27/48
Filed: 2001-11-02
Granted: 2005-01-11
Abstract: Disclosed are methods for determining the quantity of leveler in an electroplating bath in the presence of other organic additives, such as accelerators, brighteners and suppressors. Such methods are fast, work over a broad concentration range of components and can be performed in real-time.
Patent TW-530359-B (TW)
Title: Methods of positioning components using liquid prime movers and related structures
Inventor: RINNE GLENN A
IPC: H05K1/02
Filed: 2001-11-09
Granted: 2003-05-01
Abstract: A liquid prime mover can be used to position a component on a substrate. For example, a liquid material can be provided on the substrate adjacent the component such that the component has a first position relative to the substrate. A property of the liquid material can then be changed to move the component from the first position relative to the substrate to a second position relative to the substrate. Related structures are also discussed.
Patent TW-I236622-B (TW)
Title: Handling conditional processing in a single instruction multiple datapath processor architecture
Inventor: REDFORD JOHN L
IPC: G06F/
Filed: 2001-11-09
Granted: 2005-07-21
Abstract: A processor enable (PE) state of a datapath during conditional processing is maintained by saving a current PE state of the datapath as an indication thereof before the conditional processing, and manipulating the indication during the conditional processing to reflect changes in the PE state of the datapath that may occur during the conditional processing. Where the conditional processing block is an if-then-else processing block, the PE state is saved during if-processing by storing the indication as a value representing the current PE state, and the manipulating includes changing the value based on the PE state during the if-processing. The PE state is inverted, or not, prior to performing the else-processing based on whether the if-processing changed the PE state of the datapath. At the end of the conditional processing block, the saved PE state of the datapath is restored based at least in part on the value. An instruction set and an SIMD processor for carrying out these steps are also provided. The instruction set also includes instructions that combine one or more of the PE saving and manipulating steps with a branch operation.
Patent TW-523419-B (TW)
Title: Game device management system, game device, control method, and software recording medium
Inventor: OKADA MASAHIRO
IPC: A63F13/73
Filed: 2001-11-12
Granted: 2003-03-11
Abstract: This invention provides a technique for managing remotely a game device without installing special equipments in a game center and the like. This invention is a license management system for a game device comprising a game device as a license object and a management device. The management device includes an input means; an encryption means for encrypting the information inputted from the input means; and an output means for outputting the encrypted information. In addition, the encryption means encrypts at least the inherent identification information of the game device of the license object and the license condition information. The game device includes: an input means for inputting the outputted cryptogram information; a cryptanalysis means for cryptanalyzing the inputted cryptogram information; a control means for controlling the execution of game program; a memory means for memorizing its own inherent identification information; and means for memorizing an internal information. The cryptanalysis means cryptanalyzes the encrypted inherent identification information of the game device and the license condition information, then the control means can license the execution of the game program when the cryptanalyzed inherent identification information of the game device and the memorized own inherent identification information has a predetermined corresponding relationship, and the cryptanalyzed license condition information and the internal information has a predetermined corresponding relationship.
Patent TW-527741-B (TW)
Title: Cover for secondary battery
Inventor: HAYASHI TOSHIHARU
IPC: H01M50/186
Filed: 2001-11-14
Granted: 2003-04-11
Abstract: By using a rivet which serves also as a terminal member, and a sealing member which serves also as an insulating member, a terminal member and an insulating member can be omitted, thereby forming the lid from only three parts i.e. the body, rivet and sealing member. The sealing member includes a cylindrical portion and a flange portion which are separate members. The cylindrical portion is formed by cutting a fluororesin tube. The flange portion is formed by punching a polypropylene resin sheet. Thus, the number of parts can be reduced to four, so that it is possible to reduce the parts cost and manufacturing cost compared to conventional lids.
Patent TW-541412-B (TW)
Title: Method for manufacturing a fuse for detonation by teeming
Inventor: CHEN CHING-SHR
IPC: C06C5/00
Filed: 2001-11-20
Granted: 2003-07-11
Abstract: This invention is related to a method for manufacturing a fuse for detonation by teeming, particularly to one for detonating a plurality of ammunition cans arranged in matrix, by igniting a bottom of an ammunition can with fire to detonate explosion of a propeller so as to fire bullets. The fuse is made by mixing fuse materials with water to assume a fluidic state, which is them teemed into and solidified at a bottom of the ammunition can, characterized in that: the fuse material is mixed by 20-30% of fir charcoals, 5-15% of hemp charcoals, 15-25% of starch paste, 40-60% of potassium chloride and water, so as to ensure steady ignition.
Patent TW-531792-B (TW)
Title: Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
Inventor: PATON ERIC N
IPC: H01L21/285
Filed: 2001-12-06
Granted: 2003-05-11
Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance nickel silicide region (56, 58). Unreacted nickel (54) is removed. A dielectric layer (60) is then deposited over the high resistance nickel silicide regions (56, 58). In a second temperature treatment, the at least one high resistance nickel silicide region (56, 58) and dielectric layer (60) are reacted at a prescribed temperature to form at least one low resistance silicide region (64, 66) and process the dielectric layer (60). Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel (54) between nickel silicide regions (56, 58) is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions (56, 58) and the dielectric layer (60) are conveniently combined into a single temperature treatment. In other embodiments, the second temperature treatment is performed prior to, and separate from, the depositing and processing of the dielectric layer (60).
Patent TW-518703-B (TW)
Title: Characterizing semiconductor wafers with enhanced S parameter contour mapping
Inventor: LAUREANTI STEVEN J
IPC: G01R31/28
Filed: 2001-12-19
Granted: 2003-01-21
Abstract: A system, and methods of its use, for characterizing semiconductor wafers with enhanced S parameter contour mapping employ small signal scatter parameter measurements of a representative sample of die to create a contour map of a wafer surface. Those die which fail to meet performance specifications are marked as bad die before the wafer is sent to a back-end process, where the unmarked good die are extracted and assembled into working products. By using enhanced S parameter mapping for characterizing the die, only those die marked as bad die need be discarded. Thus, instead of scrapping an entire wafer die lot based on the failure of a single die from that wafer, the wafer sort yield may be dramatically increased. The increase in wafer sort yield in turn, increases total production yield.