Patent GB-1208017-A (GB)
Title: Improvements in or relating to recording systems, particularly for ultrasonic inspection apparatus
IPC: G01N29/06
Filed: 1967-09-28
Abstract: 1,208,017. Selective signalling. MAGNAFLUX CORP. 28 Sept., 1967 [30 Sept., 1966], No. 44279/67. Heading G4H. [Also in Divisions H3-H5] In a system for recording peak signal amplitude the signal is applied to a multi-level amplitude discriminator whose output is at one of a number of progressively different discrete levels and this output is recorded as a visible marking at a corresponding one of a number of discrete tonal intensities. For recording ultrasonic echo signals from flaws in a workpiece 11 (Fig. 1), probe 13 and recorder stylus 27 are moved in synchronism to provide a type C scan. Gate 39 opens after a transmission pulse to pass echo signals to gate 41, which is opened by a " tracking gate " signal (initiated by the front surface echo from workpiece 11) to pass flaw echo signals to recording circuit 42 and optional monitoring oscilloscope 44. Motor control unit 24 provides signals for inhibiting recording (to prevent burning of recording paper 28) when probe 13 is stationary. In the recording circuit 42 (Fig. 2), the gated flaw echoes are bottom-clipped, amplified and applied to a ten-level discriminator 70 comprising ten bi-stable trigger circuits arranged to be triggered by different input levels. The discriminator output, on one of ten levels corresponding to the peak amplitude of the flaw echoes in one transmission period, is applied directly or via inverter 73 to stylus energizing amplifier 72. In each transmission period the discriminator bi-stables are reset either by the leading edge of the flaw echo signal (detected by " strobe reset pulse generator " 82) or, if no echo signals are received, by a signal from logic units 86, 87 and from " edge-sensing control " unit 78 which detects the absence of the tracking gate signal (e.g. when the probe 13 moves off the workpiece edge). Loss of the tracking gate signal also controls stylus amplifier 72 so that the workpiece edge is clearly delineated in the recording. The amplitude discriminator (Figs. 4, 5) comprises a potential divider chain 107-120 applying bias voltages to first inputs of bistables 91-100. The gated echo signals are applied at 104 to the second inputs of the bi-stables and determine the number triggered and hence the output voltage on summing resistor 102. Each bi-stable comprises a longtailed pair differential amplifier 133, 134, controlling the switching of tunnel diode 132 and of output transistor 144. Transistor 139 provides current regulation. The reset pulses are applied on line 106. The strobe reset pulse generator (Fig. 6) comprises a high-gain amplifier 193, 198, 200 fed with the gated flaw echo signals from adjustable bottom-clipping circuit 66 (essentially components 157-163) via emitter-follower stage 156. The high-gain amplifier saturates at about 5% of the full echo amplitude to produce a square output pulse which is differentiated by network 202, 204 to provide a reset pulse on line 216, coincident with the leading edge of the flaw echo, for resetting the discriminator bi-stables via NOR gate 83 (Fig. 2). The emitter-follower output is applied also through amplifier stages 174, 183, 187 to stylus energizing amplifier 72 (detailed in Fig. 8, not shown) having variable gain for selection of the grey tone range recorded. The edge-sensing control (Fig. 9) comprises inverting stage 343 supplying the tracking gate signal to a uni-junction transistor timing circuit 374, 377, 378 and to a bi-stable circuit 349, 350. If the tracking signal is present it passes via inverting stage 343 to line 85 and hence to logic units 86, 87 (Fig. 2), it holds the timing circuit inoperative and it " sets " bi-stable 349, 350. If the tracking signal is absent, the timing circuit fires and supplies via inverter 370 a pulse which ensures that the bi-stable is left " reset "; a signal is then applied via line 382 and stages 384, 387 to the stylus energizing amplifier 72 for recording the workpiece edge. Circuit details of the logic units 83, 86, 87 are given (Fig. 7, not shown).