Patent KR-970009785-B1 (KR)
Title: Unintentional dividing cluck generator
Inventor: KWAK JAE-BONG
IPC: H03K21/00
Filed: 1994-11-29
Granted: 1997-06-18
Abstract: The division clock generating circuit dividing a reference clock to generate 1/N output clock (herein, N is a natural number more than two.), includes: a division clock setting unit generating a first select signal, which sets an output clock divided into an even/odd number in response of division set data to be applied, and a second select signal, which sets a set division value; the first odd clock generating unit, which includes plural delay elements having respective reset terminals and formed in a form subordinately connected to each other, Nth plural delay elements of a reverse clock in response of the first transition of a reverse clock of the reference clock, and respectively outputs the first logic level during a period upto the Nth second transition of the reverse clock in response of the first transition of the reverse clock of the reference clock, and  respectively outputs the second logic level that is a logic level opposite to the first logic level during the same period as the first logic level in response of the Nth second transition of the reverse clock; the second odd clock generating unit, which includes plural delay elements having respective reset terminals and formed in a form subordinately connected to each other, and respectively outputs the second logic level during a period upto the Nth first transition of the reverse clock in response of the first transition of the reverse clock of the reference clock, and  respectively outputs the first logic level that is a logic level opposite to the second logic level during the same period as the second logic level in response of the Nth first transition of the reverse clock; the second selecting unit selectively outputting one of the first odd clock outputs provided from the first odd clock generating unit in response of the second select signal; the second selecting unit selectively outputting one of the second odd clock outputs provided from the second odd clock generating unit in response of the second select signal; the first reset unit commonly providing a gating signal, which is generated by mutually gating a signal obtained by buffering the output selected by the second selecting unit in a given time and a reset signal to be applied, to the reset terminal of each delay element in the first odd clock generating unit, for clearing the output clock of the first odd clock generating unit in a given period; the second reset unit commonly providing a gating signal, which is generated by mutually gating a signal obtained by buffering the output selected by the first selecting unit in a given time and a reset signal to be applied, to the reset terminal of each delay element in the second odd clock generating unit, for clearing the output clock of the second odd clock generating unit in a given period; an odd division clock latch unit set in response of the selected output of the first selecting unit and reset in the selected output of the second selecting unit to latch-output the odd to be output corresponding to the second select signal and reset terminals; an even clock generating unit, which includes plural delay elements having respective reset terminals and formed in a form subordinately connected to each other, respectively outputs the first logic level during a period upto the first transition of the even time of the reverse clock in response of the first transition of the reverse clock of the reference clock, and respectively outputs the second logic level that is a logic level opposite to the first logic level during the same period as the first logic level in response of the first transition of the even time of the reverse clock; an even selecting unit selectively outputting one of the first even clock outputs provided from the even clock generating unit in response of the second select signal; an even reset unit commonly providing a gating signal, which is generated by mutually gating a signal obtained by buffering the output selected by the even selecting unit in a given time and a reset signal to be applied, to the reset terminal of each delay element in the even clock generating unit, for clearing the output clock of the even clock generating unit in a given period; an even division clock latch unit inputting the selected output of the even selecting unit to latch-output it; and an arbitrary division clock output unit selectively selecting one of odd division clock provided in the odd division clock latch unit and even division clock provided in the even division clock latch unit in response of the first select signal.