baber/WOPTO huggingface dataset:
Patent JP-H0874807-A (JP)
Title: Oil pressure control device for construction machine
Inventor: MITSUHASHI MAKOTO
IPC: B66C1/08
Filed: 1994-09-09
Abstract: PURPOSE: To maintain the amount of pressure oil which flows to a hydraulic actuator such as a hydraulic motor to a prescribed value so as to maintain its output condition in a constant condition even if load pressure of a hydraulic cylinder device for a working machine is fluctuated. CONSTITUTION: An oil pressure control device is provided with a control valve 22a for controlling the flow amount of a hydraulic cylinder 4a for working which is driven by oil discharged from a hydraulic pump 20, a flow amount compensation valve 40 for maintaining the flow amount of a hydraulic motor 3 to a constant value by controlling the differential pressure between front and rear throttle 41 to a prescribed value, and a variable throttle valve 28 for controlling a flow amount supplied to the hydraulic cylinder 4a. And also it is provided with a controller 27 for controlling the displacement volume of a variable volume hydraulic pump 20 so as to set the differential pressure between the maximum value of load pressure of a hydraulic cylinder 4a and the hydraulic motor 3 and discharging pressure of the hydraulic pump 20 to a referential value, and also for reducing the opening degree of the variable throttle valve 28 until the differential pressure extends the prescribed value of the flow amount compensation valve 40 in the case where the displacement volume of the variable volume hydraulic pump 20 is a maximum value and the differential pressure not extend a referential value.
Patent JP-S58115728-A (JP)
Inventor: NAYA EIZOU
IPC: H01H33/66
Filed: 1981-12-28
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2001040968-A (JP)
Title: Controller for motor-driven shutter for building
Inventor: KISHIMOTO KEISUKE
IPC: E06B9/88
Filed: 1999-07-29
Abstract: PROBLEM TO BE SOLVED: To provide a controller for a shutter for a building that enables the time set by each timer for use in control of the shutter to be set from an operating switch or a remote-control transmitter. SOLUTION: A shutter control part 10 comprises a mode changing means 10b for changing a mode between a normal operation mode in which a shutter curtain is opened and closed and a timer setting mode in which the stored timer period is varied; a signal conversion means 10c which converts a control signal from an operating part 12 into a numerical value only in the timer setting mode; a storage means 10d which stores the numerical value provided by the signal conversion means 10c; a timer control means 10e which controls the timer based on the numerical value stored by the storage means 10d; and a numerical value comparison means 10f which compares the set numerical value to see whether or not it is within a set range of time.
Patent JP-S6275268-A (JP)
Title: Automatic analyzer
Inventor: AKIYAMA OSAMU
IPC: G01N21/11
Filed: 1985-09-27
Abstract: PURPOSE:To prevent a squeeze tube from being damaged by stopping the operation of a squeeze pump by a sample detecting means when a sample is sucked to nearby the end of a tube on the side of the squeeze pump and storing a sample which is discharged from a nozzle in a waste liquid part during the discharging operation of the squeeze pump. CONSTITUTION:A sampler 1 is provided with sample containers 11 in odd columns and waste liquid containers 12 in even columns and a sample sucked by the operation of the squeeze pump 4 through a nozzle 2 is analyzed 6 through a light emitting part 17 and a detector 18 installed in opposition to each other across a flow cell 5 and then displayed 8. When the sample is sucked to nearby the end part of the side of the pump 4, a sample detecting means 9 detects the presence of the sample and outputs a squeeze pump operation stop signal to an operation control part 7 to stop the operation of the pump 4. The nozzle 2 is operated during the discharging operation of the pump 4 to discharge the sample to the respective waste liquid containers 12. Therefore, none of the sample enters the squeeze tube 13 of the pump 4 and the tube 13 is prevented from being damaged.
Patent JP-2001039456-A (JP)
Title: Container lid for wide-mouthed container
Inventor: SASO TAKAYUKI
IPC: B65D43/02
Filed: 1999-07-29
Abstract: PROBLEM TO BE SOLVED: To manufacture a large number of products with excellent productivity and at an inexpensive manufacturing cost without using any large die by providing a frame for engagement having an end to be engaged with and fixed to a mouth part of a wide-mouthed container, and a plate-like lid body which is hinge-connected to the frame for engagement and to close the mouth part of the wide-mouthed container. SOLUTION: A plate-like lid body 2 is continuous to a base part 1a of a frame 1 for engagement via a hinge connection part 3, and has a shape corresponding to a shape of a mouth part of a wide-mounted container. The frame 1 for engagement is of end-shape, and comprises a horizontal wall 5 and a perpendicular wall descending downward from an outer circumferential edge of the horizontal wall 5, and has a structure extended in a U-shape. The frame 1 for engagement is allowed to slide in the transverse direction of the wide mouth part of the container body to locate the horizontal wall 5 of the frame 1 for engagement on a horizontal flange, and to set the perpendicular wall opposite to a skirt part of the container body and abutted thereon, and thus, the frame 1 for engagement is mounted on the mouth part of the container body.  The lid body 2 is closed to overlap the frame 1 for engagement.
Patent JP-H1145148-A (JP)
Title: Ultrasonic touch panel
Inventor: TODA KOJI
IPC: G06F3/043
Filed: 1997-07-25
Abstract: PROBLEM TO BE SOLVED: To permit the precise detection of a touched position with low power consumption driving. SOLUTION: When electric signals are inputted to interdigital electrodes T0 and T1 , an SH wave is excited at a double layer structure part, propagated to the upper end face of a non-piezoelectric board 1, propagated to the double layer structure part later, converted into an electric signal having a phase θbase by an interdigital electrode R0 , outputted and respectively converted into electric signals Ej (j=x,..., 2, 1, 0, -1, -2,..., -x) having phases θj (j=x,..., 2, 1, 0, -1, -2,..., -x) by an interdigital electrode R1 . When a position Fj is touched between the interdigital electrodes T1 and R1 on the upper end face of the non-piezoelectric board 1, an electric signal E-j having a phase θ-j is outputted by the interdigital electrode R1 . At such a time, the touched position can be detected from the difference of θ base and θ-j .
Patent JP-H0664833-A (JP)
Title: Speed detection device for endless belt
Inventor: SAMEJIMA JUNICHIRO
IPC: B65G43/00
Filed: 1992-08-13
Abstract: PURPOSE:To prevent the occurrence of a slip between a belt and a speed detection roller and prevent the occurrence of the elongation, deformation, flaw or the like of the belt for ensuring the proper detection of the surface velocity thereof. CONSTITUTION:Regarding an image formation device where an endless belt is extended among a plurality of rolls, a speed detection roller 1 is fitted in such a way as pressed to the surface of an endless belt 11, and opposite rolls 2a, 2b and 4 are laid at a position off the speed detection roller 1 in the advance direction of the belt 11, or at a position orthogonal with the advance direction. Also, the speed detection roller 1 is positioned so as to come in contact with the endless belt 11 at a contact angle of theta.
Patent JP-H0497633-A (JP)
Title: Serial data receiver
Inventor: NAGAMOTO SHUNICHI
IPC: H04L7/10
Filed: 1990-08-15
Abstract: PURPOSE:To attain bit synchronization establishment with high accuracy and high stability by indexing a relation of phase between an inputted bit synchronization preamble signal and a block number based on a serial pattern of each logic value for blocks, 1-n obtained from logical discrimination through multi- point sampling input. CONSTITUTION:The receiver consists of an FM receiver 1, a multi-point sampling input means 3, a CPU 12, a data memory 13 and a data conversion means 14. Then multi-point sampling input is implemented for each unit block resulting from dividing one bit length of a preamble signal into 2n (n is a natural number) and logical discrimination is made for each block and the relation of phase between the preamble signal and the block number is introduced based on the arrangement pattern of logical values of blocks 1-2n to establish bit synchronization. Thus, even when a serial data has more or less noise, sure bit synchronization is taken and correct reception is attained.
Patent JP-2001045452-A (JP)
Title: Image communication system, image processor constituting the system and method therefor
Inventor: WATANABE MIKIO
IPC: H04W92/18
Filed: 1999-07-30
Abstract: PROBLEM TO BE SOLVED: To shorten transmission time of image data. SOLUTION: A transmission/reception system 80A consists of a portable telephone 40A and a digital still camera 1A. The portable telephone 40A selects an image to be sent and transmits data denoting its frame number to the camera 1A. The portable telephone 40A transmits a resize instruction to the camera 1A. The camera 1A conducts resize processing so as to reduce the quantity of the image data. The camera 1A transmits the image data whose resize processing is finished to the portable telephone 40A. The portable telephone 40A transmits the image data subjected to resize processing to a transmission reception system 80B via a network. Since the quantity of the image data is reduced through the resize processing, the transmission processing of the image data is finished in a comparatively short time.
Patent JP-H0264919-A (JP)
Title: Optical head structure
Inventor: HOSHINO SHUICHI
IPC: G11B7/09
Filed: 1988-08-30
Abstract: PURPOSE:To cause a photometric sensor to be simple, small in size and light in weight by deflecting one part of a detecting light to arrive at a photo- detecting element for tracking error detection, further reflecting the light, causing the light to cross the optical path of a detecting light for tracking error detection and arranging a photo-detecting element for tracking error detection in the optical path. CONSTITUTION:One part of the detecting light to arrive at a photo-detecting element 13 for tracking error detection is deflected by a deflecting means 15 and further reflected by a reflecting means 18. Then, the light is caused to cross the optical path of the detecting light for tracking error detection and a photo-detecting element 14 for focus error detection is arranged in the optical path. Accordingly, it is not necessary to arrange a photo-detecting means 14 for focus error detection with being separated only by the length of the optical path to reach the photo-detecting element. The deflecting means 15 can be fixed on the same substrate as the photo-detecting element 13 for tracking error detection. Thus, the photometric sensor can be made small in size and the assembly of respective parts and optical axis control can be easily executed.
Patent JP-S6277339-A (JP)
Title: Production of optically active 2-alkanol
Inventor: MASUDA KUMIKO
IPC: C07B53/00
Filed: 1985-10-01
Abstract: PURPOSE:To synthesize the titled compound having highly optical purity, readily and in high yield, by reducing an optically active 1,2-epoxyalkane which is readily obtained by microbial oxidation of an end olefin with lithium aluminum hydride. CONSTITUTION:An optically active 1,2-epoxyalkane[e.g., (+)-1,2-epoxyoctane, etc.,] shown by the formula I (R is 4-12C alkyl; star mark of C is asymmetric carbon atom) is reduced with lithium aluminum hydride, to give an optically active 2-alkanol[e.g., (+)-2-octanol, etc.,] shown by the formula II. USE:A raw material for synthesizing various ferroelectric liquid crystals.
Patent JP-H0766018-A (JP)
Title: Manufacture of high-voltage resistor
Inventor: TANAKA YOSHIHIRO
IPC: H01C17/06
Filed: 1993-08-31
Abstract: PURPOSE:To provide the manufacture of a high-voltage resistor, in which the division ratio of a resistance value is stabilized and workability is improved. CONSTITUTION:A connecting electrode 3d crossing a groove 1a for division, a high-voltage side electrode 3a and a low-voltage side electrode 3b arranged on both sides of the connecting electrode 3d, a leading-out electrode 3c disposed at a specified position between the high-voltage side electrode 3a and the low- voltage side electrode 3b and resistors 2a, 2b, 2c connected among each adjacent electrode are formed onto the surface of an insulating substrate 1 having the groove 1a, and the resistors 2a, 2b, 2c are trimmed, thus forming a resistance substrate 4. Accordingly, lead terminals 5 are mounted on the high-voltage side electrode 3a, the low-voltage side electrode 3b and the leading-out electrode 3c while a lead 6 is installed to the connecting electrode 3d as crossing the groove 1a, the resistance substrate 4 is divided at the position of the groove 1a, and a sheathing resin 7 is fitted around the divided resistance substrates 4a, 4b.
Patent JP-H0770655-A (JP)
Title: Apparatus for finish-annealing grain oriented silicon steel
Inventor: KOSAKA YUTAKA
IPC: C21D9/46
Filed: 1993-08-31
Abstract: PURPOSE:To restrain the development of moisture pattern and buckling strain at the lower end part of a coil by arranging small blocks and a spacer between the coil for grain oriented silicon steel strip and a base plate for laying the coil as upend state. CONSTITUTION:Plural small blocks 8 are arranged on the base plate 3 in an inner case 5 mutually in a fixed interval. The spacer 4 having many through holes is put on the small blocks and further, the coil 1 is laid on this spacer. By this method, the ventilation can sufficiently be secured, because atmospheric gas 9 has large free space on the surface of the base plate 3 after passing through the space part at the center of the base plate 3. Further, as the interval of the small blocks 8 is not wide, the small blocks can bear the coil dead wt. even at high temp.
Patent JP-H0884036-A (JP)
Title: Logarithmic amplifier circuit
Inventor: KIMURA KATSUHARU
IPC: H03F3/68
Filed: 1994-09-09
Abstract: PURPOSE: To obtain a wide dynamic range by a few rectifiers by providing the rectifiers with index characteristics or square characteristics and performing a logarithmic or root compression for the output current of the rectifiers by the transistor for which a diode connection is performed. CONSTITUTION: Each of rectifiers 121 to 12N+2 is connected with plural differential amplifiers 111 to 11N for which cascade connections are performed and the input terminals and the output terminals at the final stages of these differential amplifiers. The output current IRS1 to IRS( N+1) of these rectifiers is added in an adder 13 and the output current IRSSI is inputted in a transistor 14 for which a diode connection is performed. Each of the amplifiers 111 to 11N has a limiting characteristic and the amplifiers are saturated in order of the amplifiers at poststage as the input voltage VIN of a logarithmic circuit increases. Each of the ranges which are different one another of the input voltage range of each rectifier 121 to 12N+1 differential amplifier is charged, and an index characteristic or a square characteristic is obtained.  The adder 13 adds the output current of these rectifiers and the transistor 14 in a diode connection performs a logarithmic compression or root compression for the output of the adder 13.
Patent JP-S6276094-A (JP)
Title: Semiconductor device
Inventor: SAKUI YASUSHI
IPC: G11C11/34
Filed: 1985-09-30
Abstract: PURPOSE:To ensure stable circuit operation even when a large transient current flows to the chip inside by giving a source power voltage whose level is controlled in correspondence to its operating characteristic to a MOS transistor (TR) circuit section. CONSTITUTION:A circuit 1i (11, 12,... 1i,..., 1n) is a n stage of clock generating circuit. Voltages VDD and VSS are respectively drain and source power supply voltages supplied from a chip external terminal. No voltage VSS is fed directly to a source power voltage terminal 3 of the clock generating circuit 1i, a power voltage converting circuit, in this case a base bias generating circuit 2 in this case, is used and its output VBB is fed to a source power voltage terminal 3. A MOS TR Q1 as a switch element controlled by a clock phiS generated by the internal circuit and MOS TRs Q2-Q4 as level shift circuits are inserted in series between an output terminal of the base bias generating circuit 2 and the source power voltage terminal 3 of the clock generating circuit 1i.
Patent JP-S6371772-A (JP)
Title: Method for managing working state of bankbook certificate issuing machine
Inventor: MORITA TAKESHI
IPC: G06Q40/00
Filed: 1986-09-12
Abstract: PURPOSE:To make the operator of a bankbook certificate issuing machine know the working state of the machine, by causing a terminal controller to inform each terminal equipment of the working state of the bankbook certificate issuing machine in accordance with the storing content of a memory in response to the processing request of each terminal device. CONSTITUTION:When a terminal equipment WM1 makes a processing request of bankbook certificate issuance to a terminal controller TC, the controller TC checks whether a bankbook certificate issuing machine 3 is busy or not by referring to a memory 11 and, when the machine 3 is not busy, requests the issuing machine 3 to issue the bankbook certificate requested from the terminal equipment WM1 and informs the equipment WM1 that the certificate issuing process is started. When the issuing machine 3 operates, the controller TC stores data WAIT indicating that completion of the operation of the machine 3 is waited in the corresponding area of the memory 11. When another terminal equipment WM2 makes a bankbook certificate issuance processing request to the terminal controller TC thereafter, the controller TC checks whether or not the issuing machine 3 is busy by referring to the memory 11 and, when the machine 3 is not busy, causes the machine 3 to make the certificate issuing operation. When the machine 3 is busy, the controller TC holds the issuing request.
Patent JP-H0265127-A (JP)
Title: Production of semiconductor device
Inventor: TAKEI MICHIKO
IPC: H01L21/225
Filed: 1988-08-30
Abstract: PURPOSE:To thin a multi-crystal Si gate electrode and make a source region and a drain region shallow by depositing a B on whole the surface thereof by a non-bias ECR plasma CVD method and performing annealing in an oxygen- free condition. CONSTITUTION:A field oxide film 12 is formed in an element isolating region on an n-type semiconductor substrate 10 to form an oxide film 14 on an element region. A multi-crystal Si layer 16 is deposited on the oxide film 14. Layers 14, 16 are patterned in a specific shape to form a gate oxide film 15 and a multi-crystal Si gate electrode 17. Next, a super-thin film 18 of a B is formed by a non-bias ECR plasma CVD method. Next, the B is dispersed in the electrode 17 and the substrate 10 by annealing the semiconductor substrate 10 to form the P<+>-type multi-crystal Si gate electrode 17, a source region 20 and a drain region 22. Annealing is performed in an oxygen-free state.
Patent JP-S6195628-A (JP)
Title: Noise rejection and processing circuit
Inventor: UENO SAKUO
IPC: H04B1/10
Filed: 1984-10-16
Abstract: PURPOSE:To reject effectively impulse noise by sampling and A/D-converting a sound signal, D/A-converting the result, and restoring it into an original continuous wave by an interpolation filter. CONSTITUTION:The inputted sound signal (discriminator output) is subject to sampling, A/D conversion and D/A conversion normally, restored into an original continuous wave by an LPF and inputted to a sound amplifier. A signal superimposed on a pulse noise is subject to sampling, A/D conversion (while sampled pulse noise is rejected), correction by a filter DF and D/A conversion, restored into an original continuous wave (rejected pulse noise) by an LPFi, inputted to the sound amplifier, where the result is subject to noise rejection.
Patent JP-H0678700-A (JP)
Title: Apparatus for packaging rice cake and table for packaging rice cake
Inventor: OKI TAKEO
IPC: A23L7/10
Filed: 1992-07-23
Abstract: PURPOSE:To provide an apparatus for continuously and automatically packaging a package with rice cakes and to provide a table for packaging rice cakes suitable for this apparatus. CONSTITUTION:This invented apparatus is composed of a rice cake feeder equipped with a rice cake discharge nozzle 1 directed downward and with a package conveyor. This package conveyor is constituted by setting package holders 6 to a table 2 intermittently driven to rotate and its designed so that one of the intermittent stop positions of the holders 6 may come to a position right under the rice cake discharge nozzle 1. The package holders 6 are elevatably set at positions leaving equal intervals along the same circle and this apparatus is also equipped with an elevation mechanism for a package holder 6 corresponding to the one stop position, i.e., the position (A) facing the rice cake discharge nozzle 1.
Patent JP-S6195302-A (JP)
Title: Production of mirror
Inventor: USUBA YASUYUKI
IPC: B32B15/08
Filed: 1984-10-16
Abstract: PURPOSE:To obtain easily and efficiently a mirror by adhering a polyolefin (PO) sheet to the PO side of a film laminated with Al foil and PO film to form a laminated sheet then plating a metal to the Al foil to form a specular surface thereon. CONSTITUTION:The PO sheet 4 is superposed on the PO film 2 side of the laminated film 3 adhered preliminarily with the Al foil 1 and the PO film 2 and is pressed under heating to unite the film and sheet by which the laminated sheet is obtd. The metal is plated on the surface of the Al foil 1 of the laminated film to form the specular surface 5. The metal may be otherwise plated 5 to the laminated sheet formed by supplying the laminated film 3 to the extrusion-molded PO sheet 4 in such a manner that the PO side thereof contacts with said sheet by polishing rolls 6 and laminating and uniting the sheets while taking up the laminated sheet. The mirror obtd. in such a manner has good surface smoothness and excellent specular surface characteristic. The mirror is easily obtd. by using an existing installation.
Patent JP-H0883799-A (JP)
Title: Method for forming solder bump
Inventor: EBITANI TAKASHI
IPC: H05K3/34
Filed: 1994-09-12
Abstract: PURPOSE: To provide a method which can simply form a solder bum having a predetermined height on a connecting pad of the circuit board of a ceramic package, a module board, etc. CONSTITUTION: A method for forming a solder bump 19 on the connecting pad 2 of a circuit board or a module board 1 comprises the steps of printing cream solder on the pad 2 of the circuit board or the board 1, further allowing the solder to reflow, conducting at least one of the step of flattening the upper part, then printing the solder on the solder flattened at its upper part, and allowing the solder to reflow.
Patent JP-S6196538-A (JP)
Title: Optical card
Inventor: AOI TOSHIKI
IPC: G11B7/24012
Filed: 1984-10-16
Abstract: PURPOSE:To realize a pigment optical card having high contrast and a high S/N by providing a recessed part for voids on the substrate, and forming a void having >=0.01mm size between an optical recording layer and a protective layer. CONSTITUTION:A recessed part for forming a void 5 is provided on the record ing part forming surface of a substrate 2 consisting of an acrylic resin, etc. A recording layer 3 consisting of a pigment composition and a protective layer 4 consisting of a resin are laminated on the substrate 2. The voids 5 having >=0.01mm size are formed between the recording layer 3 and the protective layer 4. When the voids 5 having >=0.01mm size are formed between the optical recording layer and the protective layer 4, the contrast can be increased by 2 times as compared with the conventional one, and an optical card having a high S/N can be obtained.