Patent GB-1107809-A (GB)
Title: Data processing arrangements
IPC: G06F9/40
Filed: 1966-07-20
Abstract: 1,107,809. Digital data processor. WESTERN ELECTRIC CO. Inc. 20 July, 1966 [20 July, 1965], No. 32565/66. Heading G4A. A digital data processing arrangement comprises means for sequentially supplying source instructions 10, detector means 15 for inspecting each source instruction for the relative presence of a field containing any one of a class of monitored categories, storage means 20 containing a class list portion and a category expansion portion, first storage accessing means responsive to each new category incurred by said detector means for making a corresponding entry in the class list storage portion, and second storage accessing means responsive to each incidence of a monitored category noted by the detector means for augmenting the corresponding information included in the category expansion storage portion. The Specification refers to nested MACR# definitions and expansions and as an example refers to the following instructions which simulate an electrical circuit :- Initially the memory 20 contains the word FETCH in a MACR# Definition portion and an operation counter 12, which is generally advanced by " 1 " at the end of each operation to enable appropriate operations to commence, resides at 0000. The first instruction is read in to the detector 15 and counter 12 is advanced to 0001 to enable the detector which recognises the instruction as a data inputting statement supplying values for, and therefore defining the quantities GAIN 1, BNDWTH. No further handling is required so the counter is reset to 0000 and the next instruction read in GAIN 1 is recognized as previously defined so the third instruction is read. Detector 15 recognizes FREQ as undefined, translates the word in binary form to units 25, 30, 40, 45 and 50 and advances the counter. The comparator 25 searches the memory 20 to find that FREQ is not included in the MACR# definition portion. The counter is increased to cause unit 30 to place the name FREQ in a MACR# definition cell, the definer 35 inserts a first created symbol 001, supplied by a generator 38 in a MACR# definition storage area. A FERH MACR# redefiner 40 inserts the created symbol 001 in a MACR# expansion storage location (memory address 1000, Fig. 43) and writes the name FREQ into the next memory location and also redefines FETCH by inserting in the following cell the address 1000. Unit 45 places a second created symbol 002 in the store. Unit 50 writes 002 in location 2000 and in the following cell writes the computer instruction or instructions denoted by W#RK 1. Continue Test 55 then senses that more instructions are to be compiled and resets the counter to 0000. BNDWTH has been previously defined so AMP GAIN 2 is read. This is previously undefined so the above process is repeated causing symbols 003, 004, GAIN 2 and W#RK 2 to be written in the same manner as 001, 002, FREQ and W#RK 1 as shown in Fig. 4B. With the final word FREQ is recognized as an undefined variable but as also contained in the MACR# definition storage, so the counter is advanced to 0110. Unit 45 inserts symbol 005 in the MACR# definition storage and places address 2000 associated with the FREQ name in the MACR# definition storage. Unit 50 then places 005 and W#RK 3 in addresses 3500, 3501 and address 3500 in a location below the cell containing the variable name FREQ. The source instructions are now compiled so unit 55 causes activation of the FETCH Readout unit 60 for extracting the W#RK items from memory. This is done as shown in Fig. 5 in combination with Fig. 4B. FETCH is followed by address 2500 so that address is located and contains 003. 003 is searched for and is followed by address 1000. Address 1000 contains 001 but when 001 is found it is followed by a blank cell or NULL. However, address 1001 contains FREQ and the FREQ name is followed by address 3500 which contains 005. This definition is followed by address 2000 which contains 002 which gives another NULL. However 2001 contains W#RK 1 which is read out. Going back to an unfinished step address 3500 is followed by W#RK 3 which is read out and following from address 2500 gives W#RK 2 as shown.