Patent GB-1066600-A (GB)
Title: Improvements in or relating to means for controlling tape write or read operations
IPC: G11B15/02
Filed: 1964-06-23
Abstract: 1,066,600. Digital data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 23, 1964 [June 28, 1963], No. 25911/64. Headings G4C and G5R. The main purpose of the invention is to reduce access time in a computer magnetic tape memory by reducing the average interrecord gap. This is done by continuing tape movement for a short period after access in the expectation that another access is imminent. The computer controls transfer of blocks of data between a magnetic tape and the computer by providing " write," "read," "end write" and "end read" signals on lines 10, 11, 12, 13 respectively (Fig. 1). Signals on lines 10, 11 set write and read latches 21, 22 respectively. Tape writing is performed when signals occur on both the set output line 101 of latch 21 and one of lines 16, 17 of Fig. 1 (Fig. 3, not shown). Tape reading is performed when signals occur on both the set output line 102 of latch 22 and line 18 of Fig. 1 (Fig. 4, not shown). The tape moves when a go signal is provided on line 14 (Fig. 1), in a direction specified by a two-state forward/backward signal, and is braked in the absence of the go signal (Figs. 2, 5, not shown). When writing a block on to tape, a continuous read and check is performed and since this will end later than the writing, a time period E is provided after the end of writing the block. The end of period E in the case of writing, and the end of reading in the case of reading, are signalled to the computer on line 29. All time intervals are specified by a counter 48 fed with clock pulses from an oscillator 66 and provided with an AND gate matrix 71 to produce output signals. Assuming that the tape is stationary and a write command (line 10) is given, write latch 21 is set together with go latch 44 (via OR 42) and clock pulses are passed to counter 48 via AND 37. After a start write delay period D (3À5 ms.) counter 48 sets latch 27 to produce a signal on line 17 to initiate writing (and via OR 24 to terminate pulse feed to counter 48). After writing has been completed, the counter 48 is reset and latch 23 is set to enable AND 73 so that counter 48 receives pulses and times out period E (1À1 ms.). After period E, counter 48 resets latch 23 thereby terminating pulse-feed and producing a pulse on line 29 which signals the computer for the next instruction, resets the counter 48 and resets all remaining latches (see Fig. 1-L = latch) except move control latch 41 which it sets and go latch 44. Latch 41 controls AND 37 via OR 77 to let. pulses from oscillator 66 reach counter 48, so that the latter starts to time out period A (0À7 ms.) followed by period B (1À0 ms.), and also automatic write delay period G (2À6 ms.) and automatic read delay H (2À0 ms.) which begin at the beginning of period A. If a write or read instruction is received during period A or B, counter 48 sets latch 82 or 68 at the end of period G or H respectively and this enables writing or reading to take place and terminates (via OR 24) pulsefeed to counter 48. If an instruction occurs during period A, a signal via OR 42 and inverter 39 blocks ANDs 87 and 80 thus preventing resetting by counter 48 of go latch 44 and move control latch 41 which would otherwise occur at the ends of periods A and B respectively. If an instruction does not occur during period A but does occur during period B, go latch 44 is reset at the end of A and then set (via OR 42 and AND 98) by the arrival of the instruction. Resetting of move control latch 41 at the end of period B in the absence of an instruction on the other hand closes AND 37 via OR 77 to terminate pulse-feed to counter 48, and triggers SS 92 to provide a stop delay period C of 2À7 ms. during which no new instruction may set go latch 44. An instruction occurring during or after period C sets latch 21 or 22, and after C has ended is passed to set go latch 44. If it is a write instruction, a start write delay period D starts as explained above. If it is a read instruction, AND 37 begins counter operation as in the case of a write instruction but the counter defines a start read delay F (of 2À0 ms.), an output from the counter after this interval passing through AND 66 to set latch 68. This produces a signal on line 18 to permit reading to begin. Period B is the maximum period during which, due to inertia, the speed of the tape does not fall significantly following the termination of the go signal at the end of period A (in the absence of an instruction). Abolition of the periods C and E is mentioned. A backhitch operation may be used to maintain the interrecord gap constant despite a stop during its generation.