Patent GB-925707-A (GB)
Title: Improvements in or relating to memory devices
IPC: H04Q3/00
Filed: 1959-10-02
Abstract: 925,707. Automatic exchange systems. PHILIPS ELECTRICAL INDUSTRIES Ltd. Oct. 2, 1959 [Oct. 7, 1958], No. 33480/59. Class 40 (4). Magnetic core storage matrices record the busy condition of links in a switching network which has a number of alternate paths from any one inlet to any one outlet over switching stages, each link between stages being such that it always provides an nth alternative path regardless of the inlet and outlet concerned, each row of a storage matrix storing the busy states of the alternative links between two switching stages available to any one inlet and the columns representing the number n of the alternative path provided by each link, a read-out pulse distributed over the row wires of the matrices containing the cores appropriate to the alternatives available to an inlet producing an output in the column wires of cores recording a free link so that coincidence of outputs on the column wires of each matrix representing the same numbered alternative path indicates that a complete through path is available. In the switching network shown in Fig. 1, switches A have five inlets and two outlets while the switches B, C, and D of subsequent stages have two inlets and two outlets. Any inlet of a switch can connect with any outlet. The A and B switches are divided into two groups in which the A switches of each group have access to any outlet of the B switches of the same group. The C and D switches are similarly linked. The links between the C and D switches are such that outlets of the B switches of the first group of A and B switches are connected to first inlets of all C switches, while outlets of the second group are connected to second inlets of all C switches. The links numbered 1 provide a first path between network inlets and outlets while links numbered 2 provide a second path. The storage matrix foi links between A and B switches is shown in Fig. 2 where a row wire is provided for each A switch and each core of the row in order corresponds to an outlet from the switch. The column wires 5 and 8 link with cores all representing first paths and second paths, respectively. The storage matrix for links between C and D switches is similarly arranged, the column wires 7 and 10 being linked with first and second paths respectively. The storage matrix for links between B and C switches has a row wire for the first outlet links of each group of A and B switches and a row wire for the second outlet links of each group, the column wires 6 and 9 being linked with first and second path cores respectively. The row wires are interconnected such that connection of potential across an AB row wire and a CD row wire corresponding to a wanted path between an A and a D switch also causes current to flow in the B.C. row wire pertinent to the first and second path links between switches B and C available to the wanted path. If, to represent an idle link, the cores are set to " 0 ", current produced by the interrogating potential switches the cores to " 1 " and produces output on the column wires 5, 6, 7, for first paths and 8, 9, 10 for second paths. Coincidence of read-out pulses on these sets of column wires is detected by coincidence circuits C1, C2, the state of which is scanned by equipment 13. Should any of the links be busy, one or more of the associated cores will be at " 1 " and will not read out a pulse and inactivity of either or both circuits C1, C2, will indicate the busy state of the paths. To record the state of links where 50 A switches have 100 inlets each and 10 outlets, while B and C switches have 10 inlets and 10 outlets, the storage matrices of Fig. 3 are used in conjunction with registers Y, Z, U and V. Registers Y and Z control the AB link matrix to select the row wire particular to the required A switch. While registers U and V control the CD matrix to select the row wire particular to the required D switch. Each matrix has ten column wires corresponding to the first to the tenth alternative routes over the network for any given connection. Outputs in column wires are amplified at P, Q and R before being applied to the three input coincidence circuits C1 to C10. Outputs in the column wires prime half-erase generators U, V, and W, and whenever a complete set of idle links is found by scanner 13 the half-erase generators of the column wires associated with the idle path are fired by means not shown. Subsequently all other primed half-erase generators are fired together in coincidence with a half-erase pulse applied over the selected row wires so that those cores of idle but unwanted links are restored to " 0." The half-erase generators may employ saturable cores and transistors as described in Specification 925,706 and may be used as gates in the coincidence circuits C; they may also be used in a trigger circuit to provide the halferase pulse over the row wires, and may be used to form a stepping circuit for the scanner 13. Specifications 849,873 and 917,119 also are referred to.