Patent GB-1160591-A (GB)
Title: A Time Division Telephone Switching System
Inventor: PINET ANDRE
IPC: H04Q11/04
Filed: 1966-08-01
Abstract: 1,160,591. Automatic exchange systems. A. PINET, J. B. JACOB, and E. ESCLANGON. 1 Aug., 1966 [30 July, 1965], No. 34496/66. Heading H4K. A PCM, TDM, exchange has subscriber groups terminated in so-called modem sets 1<SP>1</SP>to 1 n  which encode/ decode and multiplex/demultiplex with respect to associated outgoing and incoming highway pairs termed network line pairs 15 1 , 16 1 , to 15 n , 16 n , intermediate highway pairs 21 1 , 21 2 , to 21 n-1 , 21 n , termed junction line pairs being used to link the group highways; control of the exchange being governed by a computer 4 which conducts search for lines in a calling condition, seizes idle channels over the highways and controls the cross-points between the highways; control being delegated for call supervision to a call processor termed a multiregister 3 which has two synchronous circulating stores parallel sections of which constitute a number of call processing registers, one of the stores being used for exchange equipment addresses and the other for call processing data, and each such circulating store having an input buffer and an output buffer comprised by separate further circulating stores and enabling interchange between the computer and the multiregister; the multiregister supervising individual subscribers' lines, as directed by a modem set address and a time slot, by way of supervisory lenses 17 1  to 17 n  from each modem and, in accordance with a record of loop conditions so detected, modifies call processing data. As shown in Fig. 1, the synchronous circulating address and processing data stores comprise an operations store 32 with. processing done in a wired logic network 34 having selective access to the supervisory buses 17. A tone generator 6 producing dial tone, lensy tone, a ringing signal, ringing tone, and a tone called waiting or standby tone, is selectively gated to an intermediate highway pair according to an address from the operations store, the particular tone being selected according to a call phase code presented by the logic network 34. A circulating store associated with each intermediate highway pair circulates a code which repetitively gates the associated tone in the time slot of a connection, Fig. 7, not shown. The input and output buffers, shown in Fig. 1, as transfer stores 31, 33, have a circulating time of 128 (Ásec. which is one exchange multiplex cycle, and receive and send call processing data and associated line and highway addresses separately in accordance with the separate parallel storage provided in the operations store 32. The multiregister 3 signals the computer 4 over circuit 37 when it is ready to receive a message in its input buffers and when it has a message compiled for forwarding to the computer. The computer over circuit 36 signals the multiregister 3 when it has completed transmission or reception of a message. The logic network 34 monitors the buffer stores 31, 33 to see if they are in a circulating state and governs transfer from the buffers into the call register sections of the operations store. The buffers are detailed in Fig. 3, not shown. In an exchange multiplex cycle of 128 Ásec. there are 16 time slots of 8 one-microsecond bits corresponding to the 8 bit PCM coded channels on the highways. The recirculating stores in the operations store 32 have an overall loop delay of 25 exchange cycles each span of a cycle constituting a register available for a call processing function as instructed from the computer 4. The recirculating store handling call processing data comprises a 3070 Ásec. magnetostrictive delay line the input to which contains an adder/ subtractor/no change circuit introducing a 1 Ásec. delay, and the output of which has a bit resynchronizing circuit introducing a 1 Ásec. delay. The circulating loop between write-in and read-out points is padded out with a 128 Ásec. magnetostrictive delay line measuring the length of a register so that a register can be read out to the logic network, be processed in one exchange cycle according to supervision data obtained from loop inspection, and the register content be modified accordingly in the following exchange cycle. The logic network 34 deals with alternate registers so that it takes two cycles of the store, which is 50 exchange cycles, to process all registers. The recirculating store carrying address data is similarly provided except that it has no adder/subtracter. These stores are detailed in Fig. 4, not shown. Numbering the time slots of an exchange cycle t1 to t16, and the bits in each time slot #1 to #8, the contents of a call processing register (which spans one exchange cycle) are arranged as follows: In bits t1#5 to t1#8 a record is kept of the number of whole digits received from a dialling subscriber (or if a register is used for sending off the number sent). In #1 to #4 and #5 to #8 of each of time slots t2 to t6 received digits are accumulated with a total capacity of ten digits. The bits in slots t7 to t9 and the first two bits of t10 are used as timing clocks. In slot tlO in bits #3 to #6 a record of the state of the line loop of the calling subscriber, as detected in the last three consecutive interrogations, is kept, bit #3 to #6 in slot t11 recording the same data in respect of the called line. Slot t12 is used for registering call start and end times, release and connection codes, and fault data. Slot t13 contains parity bits while slot t16 from #1 to #7 records the call phase code. The position of the address data in the address circulating store is such as to span slots t(i- 1) and t(i) where t(i) is the time slot of the connection being processed. In t(i - 1)#2 to t(i - 1)#4 the address of the intermediate highway pair is registered. In bits #5 to #8 of t(i - 1) the address of the calling line modem-set is register, the address of the called line modem-set being registered in bits #5 to #8 of t(i). The logic network 34 comprises a gating circuit which selects the circulating delay line store associated with each intermediate highway pair as described above for the connection of tones, and comprises a register for the calling line modem-set address or the called line modem-set address, one or the other such address being gated to the register according to the phase code of the call processing step. Calling or called line address selection is effected by a counter set to a datum state by the appearance in #2 to #4 of t(i - 1) of any intermediate highway pair address, all zeros in such an address being forbidden. The counter from its datum state provides separate windows for the calling and called modem-set addresses received from the operations store register, and the phase code determines which window is open. This is detailed in Fig. 6, not shown. The logic network further comprises a register for the phase code and a decoder to provide separate leads for the 256 possible call sequence states referred to as call phases. Also in the logic network is a fourbit register which from an analysis of the first one, two or three digits dialled, indicates the total number of digits to be expected for a call; a four-bit register for current and last three determined line states, and a three-bit timer which is set up by the current phase code to time out various conditions. Time out condi - tions relate to impulse and interdigital pause discrimination, release, and busy tone connect if dialling is not forthcoming after 15 seconds. Processing is effected by the wired logic of a socalled programmer which modifies the call processing data and phase code in accordance with loop changes signalled over the supervisory buses. A change of loop state is signalled if the currently detected state and at least two out of the preceding three records of loop state record a change.