Patent GB-1346608-A (GB)
Title: Dual single sideband transmission system
IPC: H04L27/02
Filed: 1971-08-26
Abstract: 1346608 Digital transmission; amplitude modulation PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 26 Aug 1971 [29 Aug 1970] 40090/71 Heading H4P A synchronized transmission system has two pilot carriers for transmitting clock pulses and dual single sideband channels on either side each modulated by a coder converting binary pulse signals into multi level signals which feed a low pass filter and single side band modulator connected in cascade. The outputs of the single side band modulators are applied to a combining device producing dual single side band signals. The ratio of clock frequency and frequency difference of pilot carriers is an integer. At the receiver modulation is performed by dual single side band demodulators controlled by local carrier signals of differing frequency derived from the pilot carriers, the demodulators feeding decoders clocked by recovered pulses. At the transmitter binary pulse signals from source 3 through series-parallel converter 27 controlled by multiplied clock pulses from oscillator 7 at 40 kHz are modulated at 4 into a frequency band of 60-108 kHz then combined with pilot signals at 5. Clock pulse generator 2 comprises oscillator 7 of frequency say 24 kHz whose output line incorporates a frequency multiplier 8. Series parallel converter 27 includes AND gates 28, 29 which receive signals 3 directly through AND gate 28 also through delay 30 controlled by output pulses from frequency multiplier to AND gate 29, alternate information pulses being routed through pulse wideners 31, 32 to coders 19, 20. Each coder comprises a modulo-2 adder 33 applied to a difference producer 34 and delay network 35 of two clock periods which has inputs to adder 33 and producer 34. Modulator 4 is fed through low pass filters 21, 22 and comprises single side band modulators 23, 24 receiving carrier signals 25, 26 at frequencies of say 87, 81 kHz. By suppressing spectral components above 12 kHz in 1.p. filters 21, 22, signals occur at the output suitable for single side band modulation at 23, 24 each comprising a cascade circuit of a push-pull modulator 36, 37 and single side band filters 38, 39, the pass bands of which are 87-99 and 69-81 kHz respectively. These are passed to combining device 5 emitting dual side band signals with a frequency space of 6 kHz for transmission of pilot signals of say 81 and 87 kHz providing carrier and clock signals. These are derived from oscillator 9 directly at 81 kHz and indirectly by mixing through ¸4 divider 40 from oscillator 7 through filter 42 providing 87 kHz; clock signals of 24 kHz may be recovered by multiplying the difference frequency by 4. To avoid cross talk only a portion of the upper side band of modulator 37 located in the band 87-99 kHz is fully suppressed in filter 39. It is stated that due to simplicity of filter construction noticeable phase shifts are not introduced and that four speech channels can be transmitted between 60-69 and 99-108 kHz bands. At the receiver, Fig. 2, two single side band demodulators 43, 44 in parallel are controlled by carriers of 87, 81 kHz and decoders 47, 48 by clock pulses of 24 kHz. Clock pulses plus carriers are recovered through filters 15, 16 mixer 49 and output filter 50 through x 4 frequency multiplier 51. Demodulators 43, 44 are constituted by input band pass filters 52, 53 push pull modulators 54, 55 followed by 12 kHz 1.p. filters 56, 57. Filters 52, 53 select side bands of 87-99 and 69-81 kHz which provide ternary pulse signals limited to a band of 0-12 kHz after demodulation from the outputs of 1.p. filters 56, 57. These are converted at 47, 48 by means of twophase rectifiers 58, 59 into binary pulse signals which are regenerated at 60, 61 controlled by clock signals and pass to a parallel/series converter comprising a OR gate 63 fed directly also through a delay 64 comprising a shift register. Alternate bits are interleaved at 63 and passed to a receiver 13. In Fig. 7 (not shown) based on Specification 1,346,607 coders 19, 20 are arranged to convert into seven levels, and comprise a code converter (70-72) providing a ternary pulse series which can be multiplied by factors of 2 or 3 giving - 3, to + 3 levels derived from the output of a linear adder (75). At a coresponding receiver, Fig. 8 (not shown), decoder 47 is provided with a twophase rectifier 58 and level separator (76) and pulse group former (77) connected to a series/ parallel shift register (64) controlled at 96 kHz. A single side band modulation method described in Specification 1,143,758 may be used alternatively; it is possible to convert binary signals to ternary by using a digital filter as disclosed in Specification 1,143,758. Two independent information signals each of 24 kHz may be transmitted by applying these to channels 17, 18 which are not then commoned at the input.