Patent GB-983515-A (GB)
Title: Improved information transfer apparatus
IPC: G06F11/10
Filed: 1962-05-09
Abstract: 983, 515. Sorting digital data. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 9, 1962 [June 5, 1961], No. 17830/62. Heading G4M. An information transfer apparatus includes means to direct each group of a series of successively received groups of binary coded bits to one of two output channels in accordance with the parity of the group. The apparatus is used to sort a parallel by bit, serial by character computer output, each character being represented by seven bits including a parity bit, into data characters having odd parity and instructional or special characters having even parity. Several different error checks are made. In one form (Fig. 2a) the characters are fed through the apparatus in groups of two or more of the same parity. The apparatus will stop and emit an error signal if it finds a lone character of one parity. A character in a register 308 is transmitted by an AND gate 309 at time 1 of a clock 307 to a parity checker 312 which forwards a signal to one or other of two AND gates 315, 316 according to the parity of the character. At time 2 the AND gates 315, 316 are enabled, and the one receiving the signal trips its associated relay T1 or T3 through its change contact. At time 3 an AND gate 327 is enabled, and if the 1 outputs of the triggers T1. T3 are both up a trigger 328 is operated to indicate an error. In this case the apparatus stops and an error signal is emitted. If an error has not occurred only one trigger T1 or T3 at most-say T1-can have its 1 output up, this indicating that the character in the register 308 is of even parity. At time 4 a pair of AND gates 321, 322 are enabled, but as triggers T2, T4 still have their zero outputs up, neither gate is opened. At time 5 a buffer register 314 is reset, a pair of AND gates 318, 319 are enabled but do not open, and an AND gate 329 is enabled to reset the triggers T1-T4, if an error has occurred and trigger 328 has been reset. At times 6 an AND gate 311 is opened, and the character in the register 308 is passed to the register 314. At time 7 the register 308 is reset and a new character entered. If this new character is of odd parity the trigger T3 is tripped and an error signal is emitted at time 3. If it is even the trigger T1 is tripped to bring its zero output up, this tripping the trigger T2 so that its one output is up and its zero output down thus blocking the AND gate 315. The one output of the trigger T2 enables the AND gates 319 and 322 and at time 4 the AND gate 322 is opened to allow the first even character to pass on to its respective output bus. Further even characters can then be fed sequentially through the apparatus. The even parity of each number is checked at time 1; nothing happens at times 2 or 3, the previous character is fed out through gate 322 at time 4, buffer register 314 is set at time 5, the character in register 308 is fed to register 314 at time 6 and register 308 is reset and fed a further character at time 7. When an odd character enters the register 308 the trigger T3 is tripped at time 2 to bring its one output up. As the trigger T1 has been set with its one output down by the passing of two or more even characters an error signal is not emitted at time 3 when AND gate 327 is enabled. If there had been only one even character before an odd character both triggers T1, T3 would have had their one outputs up and an error signal would have been emitted. At time 4 the last even character is passed through the AND gate 322 to its output bus. At time 5 the buffer register 314 is reset and AND gate 319 is operated to reset the trigger T2. At time 6 AND gate 311 is opened to pass the odd character to register 314 and at time 7 a new character enters the register 308. As trigger T3. still has its one output up, if this new character is even the one output of trigger T1 will also be up at time 3 causing an error signal to be emitted. If the new character is odd the zero output of the trigger T3 will come up causing trigger T4 to switch blocking the AND gate 316 and enabling AND gate 321. A series of odd characters can then be fed through in a manner similar to that of the even characters but gated at time 4 through AND gate 321 to the data output bus. In a second embodiment (Fig. 3) even parity characters are checked to see that they are instruction or special characters while odd parity characters are fed to the data output bus without a check. A character is fed into a register 8 and passed at time 1 of a clock 7 to a parity checker 12 and a special character or instruction checker 13 through AND gates 9 and 10 respectively. A pair of AND gates 15, 16 are also enabled at time 1 to pass an odd or even output from the parity checker to a trigger 17. The trigger has only one output which is up on even parity and down on odd. This latter output is fed to a pair of AND gates 18, 19. At time 2 the AND gate 18 is enabled and if the parity checker indicates even parity while the instruction or special character checker indicates by its not valid output that the character is not an instruction or special character an error is signalled. At time 3 AND gates 31, 22 are enabled and according to the previous setting of a trigger 20 the previous character already in the buffer register 14 is fed out on the data bus or the instruction or special character bus. At time 4 the  buffer register and the trigger 20 are reset. This ensures that the trigger output "select data" is up. At time 5 AND gate 19 is enabled, and if the trigger 17 is set at even parity, and the instruction or special character checker indicates that the character is a valid instruction or special caracter the trigger 20 is tripped to enable AND gate 22 and block AND gate 21. At the same time an AND gate 11 is opened to pass the character in the register 8 to the buffer register 14. Thus unless an error has been detected the character has been fed to the buffer register 14 and the trigger 20 is set to enable one or other of the AND gates 21, 22 to pass the character to its respective output bus at time 3 of the next cycle of operations which is a repeat of the above. Any characters which have even parity but which are not recognised as instructions or special character are sent out on the data output bus while an error signal is given. In a third embodiment (Fig. 4 not shown) in which the even parity characters are preceded by an instruction leader the apparatus checks that a special character or instruction is directly preceded by an instruction leader. Separate checkers check for special character instructions and for instruction leaders. If the character after an instruction leader is recognised as a special character it is sent out on the special character or instruction bus as would be an instruction, and also an extra signal indicating a special character is sent out on an addition output line.