Patent GB-1518712-A (GB)
Title: Channel selecting apparatus
IPC: H03J7/06
Filed: 1976-08-16
Abstract: 1518712 Tuning arrangements for TV receivers SONY CORP 16 Aug 1976 [28 Aug 1975 29 Aug 1975] 34012/76 Heading H3Q In a channel selecting apparatus for a television receiver having an electronic tuner 100, Fig. 1 an address selector 70 is actuable by S1 to S16 for selectively activating each of addresses in a memory 50 so as to effect read out of a channel identifying digital code corresponding to the required channel, a D/A converter 90 converts the digital code read out of the memory into an analogue control signal for the tuner and an automatic fine tuning AFT circuit 120 is reponsive to a detected deviation of the established receiving frequency from a correct receiving frequency for the channel identified by the digital code then being read out of the memory to modify the channel identifying digital code converted by the converter 90 in a sense for removing the deviation. To programme the memory 50 a mode change switch 61 is switched to position a and operation of address selection switch S1 selects by, address counter 71, one of sixteen memory units (51, -5116 Fig. 2, not shown) of the memory 50. A counter 40 is reset by circuit 77, 45, 44 and 48. A sweep generator 30 alters the count in the counter 40 under control of coarse up and down switches 31 CU. 31 CD or fine up and down switches 31 FU, 31 FD until the required television channel picture is tuned. The AFT is disabled during operation of switches 31 by output of NAND circuit 36 but the AFT takes over final tuning control by fine tuning pulses from a frequency divider 35 under control of signals ED and EU from the AFT circuit 120 when these switches are released. Pulses for fine up and down counting of the counter 40 are obtained from a timing counter 20 via the frequency divider 35. The digital output B I to B14 of the counter is then read into the memory 50 together with a digital representation of the selected band from band memory 84, as selected by switches SL, SH, SU for lower VHF, higher VHF and UFH bands on operation of a write switch 62. The D/A converter 90 includes a pulse-width modulator (Fig. 3 not shown) which includes exclusive OR circuits (90-914) OR circuit (93) and a flip-flop (94) and produces a chain of pulses with the width of each of the pulses being dependent on the absence of coincidence between the channel identifying code B1-B14 (Fig. 4C, not shown) and a circulating digital code A1-A14 (Fig. 4B, not shown) from the timing counter 20. The output pulses P w  (Fig. 4E, not shown) of width depending on these codes is fed via a LPF 92 to a variable capacitance diode of the electronic tuner 100. Selection of a stored channel is obtained by switching mode change switch 61 to position b and operating a required switch S1-S16. The digital code corresponding to the addressed memory unit of memory 50 is then read into the counter 40 and the corresponding output from the D/A converter 90 tunes the electronic tuner 100 to the selected channel. Neons N1-N16 indicate the channel selected. If the tuning deviation, as corrected by AFT circuit 120, is more than a predetermined amount, determined by a counter 133, a signal P M  from a memory rewrite circuit 130 operates instruction circuit 65 to write in the corrected binary count of the counter 40 into the memory unit of the selected address. The AFT circuit 120 include transistor differential amplifiers (122 and 123, Fig. 5, not shown). AFT is delayed in commencing for a time after power supply is first applied or after a selected one of the switches S1-S16 is closed by output from transistors 46 or 77 which triggers a monostable multivibrator 142 to provide an inhibit pulse PG for 10mS. Also when the power supply is turned on address counter 71 resets to address the first memory unit (51) in memory 50. The memory units are of non-volatile cells, such as MNOS elements which hold their contents unchanged when memory 50 is disconnected from a power supply. The channel selecting apparatus can be formed as an integrated circuit. In a modified memory refreshing operation a buffer stores the channel identifying code being read out of a selected memory unit and when its contents differs by a predetermined amount from the contents of the counter 40 as modified by an AFT operation the memory refreshing operation is effected. A D/A converter consisting of switching elements and weighted resistors may be used instead of converter 90.