Patent GB-1509393-A (GB)
Title: Method and device for communication of information
IPC: G06F9/46
Filed: 1975-04-23
Abstract: 1509393 Data processing system COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL 23 April 1975 [25 April 1974] 16914/75 Heading G4A In a data processing system including a central processing unit and a main memory, each process which can be executed has, in main store, a process control block containing data relating to the process, a ring number representing the privilege level of the process and an asynchronous ring number, a trap being introduced so that a process A can warn a process B of an event only if the privilege ring number is greater than the asynchronous ring number Central processing unit.-This comprises a main memory synchronizer (109, Fig. 1, not shown), a buffer store (110), reproducing a selected region of main memory, a computing unit (111), emulators (104), a read only store (130), an address control unit (131) and an associative memory (132) storing the most recently employed addresses in main memory. Peripheral sub-systems.-The peripheral control unit (106) is a microprogrammed processor commanding input/output devices (108) (which may be discs or tapes) to perform, e.g. arithmetical, logical, transfer or branching operations. It also resolves access conflicts between input/output devices connected to it. Main memory.-The main memory comprises four modules for storing data in capacitive MOS stores with automatic refreshing. A zone is reserved for hardware and firmware bounded by an address held in a boundary address register. Process control block.-Each process has an associated part of main store assigned to it called the process control block (400, Fig. 4, not shown) which contains the content of registers used by the process and the state of the process. It also includes two segment table words (STWA) containing the addresses of segment tables (one table for segments of up to 2<SP>22</SP> octets in size) and one table for segments up to the 2<SP>16</SP> octets in size). The segmentation defines more addresses than there are in main memory, an auxiliary (disc or drum) memory being used to provide a virtual memory system with segments not in main memory being transferred when requested. All processes employ a segmented address (logical address) consisting of a segment number and a relative address within the segment. System base.-The system base (Fig. 6, not shown) is an absolute zone of main memory accessed using the boundary address register and containing the logical name JP of the currently executing process. Using the logical name the process control block of the current process is accessed via a J table and a P table (Fig. 5, not shown). Ring system.-Procedure and data segments are grouped in a hierarchy of four classes 0, 1, 2, 3 of rings, with ring 0 being the most highly privileged. Each procedure has minimum and maximum ring numbers. The procedure has free access to data in a relatively outer ring but not to data in a relatively inner ring. A procedure can branch to a procedure in a relatively inner ring but not a procedure in a relatively outer ring. Data segments have two ring values RD for reading and WR for writing, the ring number of a procedure being checked with the ring number of the segment containing the referenced data at each instruction. Procedure calls.-Procedure calls are used to pass from one procedure to another and utilize stack segments in the store, these being dynamically assigned to each procedure. A stack comprises three zones-(1) a working zone for storage of variables, (2) a save area for storage of the contents of registers and (3) a communication area for transmission of parameters between procedures. Each procedure call results in the creation of a stack, different stack segments being used for each protection ring per process. The process control word contains three base words designating the start of the stack segment for rings 0, 1, 2. Management and synchronization of processes. -A process is in one of four states, in execution, ready, waiting or suspended, its process control block containing a state zone defining its state. Processes in the ready state are in competition for access to the CPU. Processes in the waiting state may for example be waiting for the transmission of a message by a semaphore to indicate that a specific event has occurred, e.g. the availability of resource. Suspended processes are not active and cannot receive notification of events via semaphores. A distributer commands the movement of processes between states by employing a series of queues for ready and waiting processes (Figs. 8, 9, not shown). A G table pointer in the system base points to a G table (801), the zero entry of which G0 addresses a G0 segment (802) which contains the queue entries of ready processes and the queue entries of waiting processes with the semaphore to which they are linked. In system base is an entry identifying the head of the ready queue. A free process queue connecting processes not in ready or waiting queues may be employed to lengthen a particular queue. The other G segments are semaphore description segments from which the addresses of semaphore is mainly developed. Processes are queued according to their priority level (indicated by the priority byte in their process control block) there being 16 levels, processes at the same level being queued on the first in-first out basis. When a process is waiting on a semaphore the logical name of this semaphore is held in a process main word in the process control block. The distributer manages processes and controls the writing into the process control block of a process all the information relative to the process contained in registers or working memories when a process is interrupted (roll out operation) and extracts from the process control block all the relevant information when a process takes control of the CPU (roll in operation) with time accounting registers being updated. Command unit (Figs. 13a-13c, not shown). The command unit forms part of the CPU and comprises a command store unit, an interface adapter, control store loader and a control and load unit. The command store is formed by the combination of a programmable read only store having bipolar integrated circuits and a random access memory. Micro-commands from the control store are 84 bits long and comprise 6 fields for sequencing, branching, constant generation/ designation, data, micro operations and control. The micro instruction is decoded in a decoder comprising a matrix of impedance coupled lines to provide control signals on a plurality of lines to units of the central processing unit.