Patent GB-1380461-A (GB)
Title: Distribution system for sampling elements
IPC: H04M3/62
Filed: 1972-03-16
Abstract: 1380461 Automatic exchange systems COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 16 March 1972 [17 March 1971] 12250/72 Heading H4K In an arrangement for scanning groups of different equipments, e.g. junctors, digit receivers and operators' desks, at respectively different rates, a single address register is used to designate simultaneously one equipment from each group and logic circuitry is provided for distinguishing the co-designated equipments. The logic incorporates time constant circuits for preventing designated equipments from responding improperly to pulses generated by another equipment in the course of the subscanning cycle organized by the logic. The latter compares the current condition of an equipment with its previous condition on a last look basis so as to control the equipment and/or update a memory. The memory ME utilizes magnetic cores and has a capacity of 1024 words. It is divided into four columns of 32 zones each and each zone incorporates 8 cores that are scanned serially during a read-out process. The 128 memory zones are allocated on the basis of 96 to the junctors, 16 to digit receivers and 8 to operators' sets. The receivers and sets only utilize three of the available 8 cores in their respective zones, these three cores not necessarily being successive so that means are provided for causing the serial core scanner to skip unused cores in order to speed-up the scanning process. The scanner and logic ensure that there is no delay, i.e. no dead time, between successive interrogations of an equipment/memory zone. General layout.-The equipments are arranged in four sets corresponding to the four columns of memory. In the figure the outputs from these sets are depicted by the lines LG0, LG1, LG2 and LG3 of which the first three terminate on a junctor logic unit OT1, while the last LG3 terminates on a receiver logic unit OT2 and an operator logic unit OT3. The equipments themselves are marked by the outputs of decoders DT1, DT2, DT3 of which DT1 is concerned with the three sets of junctors while DT2, DT3 are concerned with the single set formed by the receivers and the operators. A scanner, shown generally at BC, has outputs L which are effective to address a particular zone in the memory ME and also to address simultaneously one equipment from each group via a distribution frame MR and output buses Y1, Y2, Y3. The logic units OT are connected to logic circuitry BL via time constant circuits BI which effect the previously mentioned interference suppression capability. The logic circuitry compares new data from an equipment and old data from memory, performs an appropriate control operation and then enables the scanner to interrogate the next equipment. The scanner consists of an n stage flip-flop binary counter EL which scans the cores of a zone successively or in skip fashion as dictated by an AD circuit under logic circuitry BL's control, and also an N stage flip-flop binary counter DA which scans the memory zones and equipments. In the example n = 3 and N = 7. The last two stages of DA are connected to a gate RB which is opened or closed by a logic circuitry controlled bi-stable BF so as to discriminate between the simultaneously designated equipments. Operation.-Initially the scanner is set so as to designate the three equipments referenced O at the outputs of the decoders DT. At this time, BL commands BF to inhibit via diodes d 1 , d 2  the output, of gate RB so that the markings provided by the address scanner on its other leads L, i.e. those marked L1 are effective to interrogate the memory zone corresponding to the " 0 " operator set. The cores of this zone are scanned by counter EL so as -to read out their contents to unit LT3 in the logic circuitry BL. (If necessary LT3 causes EL to skip unused cores using the skip control circuit AD). At the same time LT3 is supplied with the current state of the designated operator set and performs any necessary control functions. Thereafter LT3 resets counter EL so that it cannot step-on scanner DA and enables gate RB. This allows addressing of a zone on the same row as that for the O operator but in a different column. The new zone corresponds to the O junctor. Unit LT1 acts in a similar way as LT3 in order to process the date except that it cannot control EL which therefore steps-on DA when it resets itself after scanning all eight cores in the zone. With DA in its second position the O receiver is still designated at DT2 but a second row of memory is indicated at L1. On this occasion unit LT2 is utilized rather than LT3 but the operations are similar and of course the process repeats for the remaining rows of memory.