Patent EP-0037965-A2 (EP)
Inventor: FASANG PATRICK PAD
IPC: G06F11/27
Filed: 1981-04-01
Abstract: 1. A device for testing a digital electronic circuit by means of test circuits (3, 5) which are incorporated into this circuit, where a first integrated test circuit (3) is provided to generate a pseudorandom test pattern, - where the first integral test circuit (3) is connected to the inputs of the circuit (2) to be tested, - where the first integral test circuit (3) has input signal inputs (Z1A ...Z8A ) and control signal inputs (B1A , B2A ), a number of series connected storage elements (41...48) and means (61...68, 71...78) which serve to adapt the logic level of input signals to the inputs of the storage elements (41...48), which means (61...68, 71...78) connect an output of at least one storage element (41...48) to the input of another storage element (41...48), - where a second integral test circuit (5) is provided to analyse a parallel input word, - where the second integral test circuit (5) is connected to the outputs of the circuit (2) to be tested and has a number of series connected storage elements (141...148) and means (161...168, 171...178) which serve to adapt the input signals for these storage elements (141...148) and which connect the output of at least one storage element (141...148) and the input of a further storage element (141...148), - where a decoder (6) is provided, of which inputs (Q1B ...Q8B ) are connected to outputs of the second integral test circuit (5) in order to receive input signals comprising of a predetermined combination of logic levels in the event that the circuit (2) to be tested is fault-free and which comprise a combination of logic levels which differs from the predetermined combination in the event that the circuit (2) to be tested is faulty, and - where the second integral test circuit (5) has a number of input signal inputs (Z1B ...Z8B ), where a first group of these input signal inputs (Z1B ...Z8B ) is connected via switches (22) to outputs of the circuit (2) to be tested, and a second group of these inputs (Z1B ...Z8B ) is supplied, via switches (22), with input signals which represent a first logic value, e.g. "1", characterised in that - an output of the decoder (6) serves to emit a first output signal in the event that the circuit (2) to be tested is fault-free and to supply a second output signal in the event that the circuit (2) to be tested is faulty, - that at least one status indicator (7 or 8) is provided, which is connected to the output of the decoder (6) in order to indicate the status of the circuit (2) to be tested, - that means (20, 40) are provided which serve to control the first integral test circuit (3) and the decoder (6) in dependence upon a main clock signal (c), - that the control means comprise a control circuit (20) and a clock control circuit (40) which is controlled by a clock control pulse (p) from the control circuit (20), - that the clock control circuit (40) supplies the decoders (6) with an end-of-test signal (w) when a predetermined number of clock pulses of the main clock signal (c; c') have occurred, where the end-of-test signal (w) indicates the end of the testing of the circuit (2) to be tested, - that the control circuit (20) forms a release signal (e) which controls the first integral test circuit (3) and the second integral test circuit (5), where the release signal (e) comprises a sequence of a predetermined number of pulses, - that the control circuit (20) also produces the end-of-test signal (w) at the time of the occurrence of the last pulse of the sequence of a predetermined number of pulses, - that the end-of-test signal (w) is fed to a blocking device (32) in order to emit to the respective status indicator (7; 8) that item of information which is currently present in the decoder (6), - that the first integral test circuit (3) has a plurality of input signal inputs (Z1A ...Z8A ) which are sub-divided into a first group and a second group, - that first input signals, which represent the logic value "0", are fed to this first group of inputs and second input signals, which represent the logic value "1", are fed to this second group of inputs, - that outputs (Q1B ...Q8B ) of the second integral test circuit (5) emit non-inverted output signals, - that each output of a first group of outputs (Q3B , Q8B ) of the second integral test circuit (5) is connected via an individual inverter (24, 25) to the decoder (6), where this first group of outputs (Q3B , Q8B ) emits output signals having a first logic level in the event that the circuit (2) to be tested is fault-free and - that the outputs of the inverters (24, 25) and a second group of outputs (Q1B , Q2B , Q4B , Q5B , Q6B and Q7B ) of the second integral test circuit (5) are connected to corresponding inputs of the decoder (6), where each output of the second group has a second logic level in the event that the test circuit (2) to be tested is fault-free.