Patent GB-736144-A (GB)
Title: Binary automatic computer
IPC: G06F9/30
Filed: 1951-08-15
Abstract: 736,144. Digital electric calculating-apparatus; electric digital-data-storage apparatus. REMINGTON RAND, Inc. Aug. 15, 1951 [Aug. 16, 1950], No. 19239/51. Class 106 (1). An electronic binary digital computer includes a memory and an information processing device which are interconnected, and are synchronously operated under control of impulses emanating from a tapped delay line through which a single impulse is continuously recirculated. General arrangement. In the electronic computer described, words (numbers and instructions) are represented by series-mode binary pulse trains stored. in a main mercury tank memory. Words are entered in octal form from a keyboard or magnetic tape under control of electromagnetic relays, and passed to the memory through translating apparatus. Results are translated into octal form and recorded on magnetic tape, printed by a typewriter or used to operate control relays. The computer includes also the following registers each comprising a one-word-delay circulation network: a " T " register, Fig. 52, which counts the number of major cycles of computer operation; a control counter register CC, Fig. 50, which stores a number representing the main-memoryaddress of the next instruction, which number is normally periodically increased by one; a control register CR, Fig. 50, which stores current instructions for distribution to the elements of a staticizer SR, Fig. 51 (called " static register "); an " R " register, Fig. 53, for storing a multiplier or quotient; an " L " register for storing a multiplicand or divisor; an accumulator or " A " register including adding and subtraction circuits; and an input/output intermediate storage register, Figs. 64 and 65 (called " synchronizing register "). Words are passed to and from the different portions of the computer via lines HSB1 (called " first information bus "), Fig. 50, amplifier HSBA (" highspeed bus amplifier ") and lines HSB2 (" second information bus "). The registers and other parts of the computer are controlled by crystal diode coincidence gates to which control potentials are applied over the lines 100-414 shown in Fig. 51 from a diode matrix " function table " the input potentials to which are controlled by the staticizer, a rotatable multiplearm five-position function switch FS and timing circuits described below. Timing control pulses are supplied from a pulse generator PG, Fig. 50, and a cycling unit CU. Two mutually checking computers may be arranged for synchronous operation. A normal cycle of operations comprises four steps α, #, γ, #, Fig. 53, described below under " Normal operating sequence," controlled by a four-state operation-stepping counter (called " cycle counter "). Word code. A word length or minor cycle comprises 42 pulse times P0-P41, Fig. 1. A 30-digit binary number plus a sign may be accommodated in positions P7-P37 (negative numbers being represented in complementary form with a pulse or " 1 " in the sign position), or two 14-digit instructions in positions P22- P35 and P7-P20 respectively. A " gain control " pulse GCP may be inserted in position P41 for ensuring proper operation of certain circuits. In an instruction, digits L1-L5, Fig. 2, define the function to be performed, digits L6-L9 define one of sixteen memory channels, and digits L10-L14 one of 32 words within that channel. There are 18 types of instruction described below under " Classification of instructions." Timing pulse generator. Timing or clock pulses of 0.05 Ás. at a frequency of 4 Mc/s. are generated by the arrangement shown in Fig. 3 comprising an oscillator circuit 337, controlled by a crystal 335 in a thermostatically controlled oven, and supplying a sinusoidal wave to the control grid of valve 340 to produce sharp anode current surges and apply positive-going pulses through a transformer 341 to the timing pulse line 342, the pulse amplitude being stabilized by feed-back circuit 343, 344. A switch 338 enables the timing pulses to be supplied from a second associated computer. Cycling unit; pulse-shaping circuits. The cycling unit, Figs. 4 and 58, includes a one-word delay path in which a single pulse is circulated and applied singly and in combination from tappings such as t<SP>1</SP>2 on a delay line 360 to amplifying and shaping circuits to provide timing control potentials and pulses such as t2, Fig. 10. The prefix " t " denotes absolute time which is defined by the clock gate in the amplifier HSBA described below, the " p " time, Fig. 1, depending on the point of application of the '` t " pulse relative to a circulating word (t2 corresponding to p37). The circulation path of the cycling unit includes, in addition to the delay line 350, Fig. 4, having phase-shift compensating networks 352, Fig. 5, a " split load " line terminating circuit, including crystal diodes 354, 357, normally conductive valve 353, cathode follower 358, a clock gate comprising diodes 359, 360, the latter having timing pulses TP applied thereto from line 342, Fig. 3, a valve 361 driving a pulse-forming circuit 362, a normally conductive valve 363 and a delay line driving valve 351 controlled by a clearing switch 378. Circuits similar to 362 (PFR, Fig. 50) are used throughout the computer to convert a narrow input pulse from a clock gate into an output pulse of such width (0.25 Ás.) that consecutive pulses (in a word) merge into one another and there is no return to zero. A pulse is introduced into the cycling unit by operating a switch 365 so as to reduce the grid bias on a valve 368 so that the next positive-going pulse TP causes conduction and produces a negative anode pulse which switches over the two-state trigger circuit 364 (called " flip-flop ") to send a negative pulse to the valve 369. The resultant positive anode pulse, the length of which is controlled by network 370, is inverted in valve 372 and cuts off valve 373 thus raising the potential of the junction point of clock gate diodes 374, 375 and applying a positive pulse to valve 361. Main memory. This comprises a mercury tank 331, Fig. 14, having eighteen channels defined by pairs of quartz crystals such as 153, 178. Sixteen channels are used for information, each containing 32 words, one channel (crystals 273, 272) is used for temperature control and one is spare. The information recirculation circuit comprises a four-stage tuned amplifier 150, full-wave rectifier circuit 151, gate 167, compensating delay line 155 and crystal-driver valve 177. The amplifier 150 is provided with delayed automatic gain control. When selected words are to be read out of a selected channel, a signal from a staticizer-controlled selector gate 333 opens gates 158, 179 and inhibits gate 167, so that the information is sent over line 166 to gate 300, Fig. 51, and line HSB and is returned over lines HSB2 and 182 to valve 177. When new information is to be introduced, gate 300 is inhibited. For automatic temperature control, a coincidence gate 332a applies a pulse TP at the beginning of each minor cycle to a crystal driver valve 271. The pick-up circuit comprises an amplifier 274 (similar to 150), rectifier circuit 275, amplifier valve 276, compensating delay line 278, an unbalanced trigger circuit 282 (called " delay flop ") having a restoring period less than one minor cycle, and a peak detector gate 285. A lengthened pulse, whose amplitude depends on the degree of coincidence between the pulse from the tank and the pulse TP applied directly to the gate 285, is then applied' to a circuit 332 which controls the amount of current through control heater 315 accordingly. A main tank heater and control switches and relays are also provided (Fig. 18, not shown). Amplifier HSBA. The input from the memory via gate 300, Fig. 51, is supplied to clock gate driver valve 225, Fig. 19, through normally conductive valve 256, adjustable compensating delay line 257, valve 258 and coupling diode 259. Other HSB1 inputs are supplied through a similar circuitincluding diode 224, and external inputs through gate 414 including diode 262. The clock gate, comprising diodes 226, 237, 238, is inhibited by a " time-out " signal TO applied from a trigger circuit 550, Fig. 51, described below under " Normal operating sequence," during gate-switching portions of an operating cycle. The clock gate output is passed through a pulseforming circuit 241 and cathode follower 242 to parallel-connected normally conductive valves 243, 244, whose output is passed through valves 245, 246 and driver valves (not shown) to the various lines HSB2, and through valve 249 for comparison with the information circulating in the associated computer as described below under " Comparing and verifying circuit." " T " register. This comprises a circulation path into which " one " is added (pulse P7) through gate 413, Fig. 52, for each useful major cycle of computer operation. The register contents may be sent via amplifier HSBA to the " A " register through gate 411 (instruction W). The path includes a 39-pulse-time delay line 500, Fig. 23, valve 501 controlled by clearing switch 502, clock gate driver valve 503, pulse-forming circuit 506, cathode follower 507, unit adder valve 509, short delay network 513, inhibiting gate 517- 519, valve 522, delay line 523, lineterminating circuit 524, clock gate driver 525, pulse-forming circuit 528, cathode follower 529 and delay line driver valves 530, 531a. A P7 pulse is introduced through coincidence gate 413 only when a " stop " trigger circuit 555, Fig. 51, is in the " start " condition, and when a negative pulse is received from the highest stage of a " time selector " counter, described below, once every major cycle. The P7 pulse is sent through a unit delay circuit comprising clock gate driver 535, pulse former 538 and cathode follower 539 to unit adder valve 540. If adder valves 509, 540 are cut off simultaneously rendering diodes 499, 543 non-conduct