Patent GB-1195272-A (GB)
Title: Active Element Memory
IPC: G11C11/411
Filed: 1967-06-27
Abstract: 1,195,272. Transistor switching circuits. TEXAS INSTRUMENTS Inc. 27 June, 1967 [28 June, 1966], No. 29521/67. Heading H3T. [Also in Division G4] A digital electric memory includes two crosscoupled multi-emitter transistor means which may have their states changed by stopping flow of current through all the emitters except one on each transistor means and applying different voltage levels to the other two emitters. Each flip-flop may comprise multi-emitter transistors (Fig. 4) or a series of transistors having separate emitter connections but with their bases and collectors connected in parallel, the cross coupling being as shown in Fig. 4. All the emitters but one each of a flip-flop pair are connected to addressing elements which apply a " 1 " or open circuit level to the said all but one emitters of the addressed flip-flop, maintaining the emitters of other pairs at a " 0 " or earth potential level. The remaining emitter of each flip-flop is connected to a readwrite circuit held at a potential higher than the " 0 " level so that current normally does not pass through this emitter. When a flip-flop is addressed the current in the conducting transistor of the flip-flop passes through the said remaining emitter to the write circuit, and the potentials applied to the remaining emitters of each transistor can be adjusted by the write circuit to switch the flip-flop to store a # 1 " or a " 0." Individual flip-flops are addressed by circuits 110, 111, 112, a " 1 " or open circuit applied at A switching off transistor 138 to render transistors 140, 142, 144 conducting and transistor 146 nonconducting to give a " 1 " at A and a " 0 " at A. A " 0 " input renders 138 conducting 140, 142, 144 nonconducting and 146 conducting. The address units and the read-write unit 100 have selected transistor bases connected to a switchable voltage supply P operated by control circuit 116 when a read or write operation is required. For a write operation " 0 " or " 1 " level is applied to terminal 160 after the P voltage is supplied. Then a " 1 " pulse is supplied to the write-read terminal 162. For a " 0 " input transistor 164 would conduct and transistors 166, 168 would not conduct and transistor 170 would not conduct while transistors 172 and 174 would and transistor 176 would not. At the same time transistor 188 would conduct and transistor 182 would not leaving write line 134 at a high potential. Read line 136 would be at a potential corresponding to the sum of the base-emitter voltage drop through the transistors 192, 194. Thus emitter d of transistor 122 will be at a lower potential than emitter d of transistor 120 and transistor 122 will conduct causing the flip-flop to store a " 0." If a " 1 " is applied to terminal 160, 164 will not conduct and 166, 168 will, when the write-read pulse is applied. Write line 134 is reduced to a low potential level transistors 170, 172, 174, 176, 188, 182 operating as before. The new level is lower than that of line 136 so transistor 120 now conducts and a " 1 " is stored. If a " 0 " is stored, during readout the current flowing in line 36 renders transistors 192, 195 conducting so a " 0 " is read at the output. If a " 1" is stored no current flows through line 136, so transistors 192, 195 do not conduct and a " 1 " is read at the output.