Patent GB-761522-A (GB)
Title: Electronic digital serial adder
IPC: G06F7/50
Filed: 1954-12-14
Abstract: 761,522. Digital electric calculating-apparatus. NATIONAL CASH REGISTER CO. Dec. 14, 1954 [May 14, 1954], No. 36103/54. Class 106 (1). In an electronic series-mode adder, two input pulse trains each comprising groups of signals representing digits in binary-coded form are fed into a logical network associated with a binary register and controlled by groups of timing pulses so as to produce a sum pulse train in the same coded form. In the arrangement shown, Fig. 1, decimal numbers are represented by groups of four binary digits and the operations are controlled by groups of four successive timing pulses P1-P4 produced by a pulse period counter 14 into which clock pulses are fed from a source 12. The counter 14 comprises two trigger pairs associated with an auxiliary logical - network 13. The two input pulse trains Sa, Sb are applied to the main logical network 11 which is associated with three trigger pairs S1-S3. The anode (control) potentials of the valves of each trigger pair, Fig. 3, are limited by clamping diodes 20, 21 and the clock pulses C are applied to the grids through differentiating circuits 24, the positive pulses produced thereby being blocked by diodes 25 so that the triggers are set by negative pulses occurring at the ends of the clock pulses. The operation during the successive pulse periods in which the pulse values are respectively 1, 2, 4, 2, is as follows :- Period P1. At the beginning of this period, the tens carry digit from the sum of the two preceding decimal digits, if present, is registered by the trigger S 1. At the end of this period, the logical network, under the control of the two input signals, sets the trigger S1 to register the second binary digit of the partial sum and, under the additional control of the trigger S1, sets the trigger S2 to register the first binary digit of the partial sum which equals the first binary-coded digit of the final sum. Period P2. The input signals and the state of the trigger S2 again determine the new settings of the triggers S1, S2 which assume statse representing respectively the third and second binary digits of the partial sum. The registration of the first binary digit is transferred to the trigger S3. Period P3. The operation is similar to that during period P2, the triggers S1, S2 and S3 being set to register the fourth, third and second binary digits of the partial sum respectively. Moreover, the existing setting of the trigger S3 is read out as the first binary-coded sum digit this being unaffected by the input signals during period P4 in which a pulse has the value 2. Period P4. The logical network, under the control of the input signals and the three triggers, which initially register the fourth, third and second true binary digits of the partial sum, sets the three triggers to register the tens carry digit (S1), the fourth binary-coded digit (S2) and the third binary-coded digit (S3), and produces an output corresponding to the second binarycoded digit. Following period P1. As mentioned above, account is taken of the tens carry digit registered by the trigger S1 in forming the first two binary digits of the partial sum of the next decimal order, which digits are then registered in the triggers S1, S2. The initial state of the trigger S3 is read out as the third binary-coded sum digit and the setting of the trigger S2 is transferred to the trigger S3 which finally registers the fourth binary-coded sum digit. Following period P2. The initial state of the trigger S3 is read out as the fourth binary-coded sum digit. Thus the binary-coded sum pulse train is delayed by two pulse periods relative to the input pulse trains. The logical equations determining the operation of the logical network are derived and components of the network, formed from diode gates, are shown. The network is simplified by the fact that the logical equations for the pulse periods P1, P2 and P3 are similar. The output portion of the network described actually produces the logical negative of the sum waveform which is then inverted by an amplifier.