Patent GB-1354919-A (GB)
Title: Time division switching systems
IPC: H04J3/20
Filed: 1971-12-15
Abstract: 1354919 Automatic exchange systems WESTERN ELECTRIC CO Inc 15 Dec 1971 [21 Dec 1970] 58210/71 Addition to 1323231 Heading H4K In a TDM system wherein each line is provided with a storage device which is chargeable by speech signals and which is periodically connected to a first bus common to a group of lines, two-way communication between two storage devices pertaining to different groups is effected by sampling, storing and comparing their charges during a time when both are connected to their respective buses and charging one whilst discharging the other until monitor signals received over respective second common buses indicate that each storage device has been charged to the level of the sample charge stored previously for the other storage device. The length of the time slot is hence dependent on the amount by which one speech sample level exceeds the other, as in the parent Specification 1,323,231. Detailed description.-In Fig. 1 subscribers 101 are grouped on common buses 124 and trunks 103 are grouped on common buses 126. Details of active subscribers and trunks are maintained in a central control 140 and their line gates 110, 111 are controlled by outputs A, B. It is assumed signals are to be exchanged between subscriber 101-1 and trunk 103-n during a time slot. The information signal from subscriber 101-1 is applied to filter 102-1 and stored on capacitor 107-1 and the information on trunk 103-n is stored on capacitor 108-n. Between times t o  and t 1 a signal 200 is sent over lead 620 from the control 140 to memory 150 which signal causes the respective addresses of the subscriber and trunk to be transferred to control 140 where they are decoded. A signal A 1  is then applied to gates 110 and a signal B n  to gates 111. The opening of gates 110-1b and 111-nb causes the voltage on capacitors 107-1 and 108-n to be sampled by respective sample and hold circuits 134, 136 where the voltages are stored on respective capacitors during a time interval t 2 -t 3  under control of a sampling control signal applied on lead 629 from control 140. These sample signals are stored for the remainder of the time slot. The stored signals are compared by comparator 160 which is responsive to the polarity of the voltage difference between signals stored in circuits 134, 136, and its output is applied to a bi-stable device 162 to determine the state thereof. Assuming the output of circuit 134 to be more positive than that of circuit 136, bi-stable device 162 is placed in the zero state upon receipt of a select pulse 204a supplied from control 140 at input T so that a negative current source 122 and positive current source 123 can be enabled from gates 173 and 177 just after t 3 . A start signal is supplied by control 140 at time t 3  to bi-stable devices 168, 170 whose high, one, outputs are applied to gates 173, 175 and 177, 179 respectively. Hence just after time t 3 , constant current sources 122 and 123 apply current signals to buses 124b, 126b to alter the charges on capacitors 107-1 and 108-n. During the time interval t 3 -t 5  the charge on capacitor 107-1 is reduced, the charge on the capacitor being constantly monitored via gate 110-1a and being compared with the sample signal from capacitor 108-n stored in circuit 136, by a comparator 139. When the signal in capacitor 107-1 equals the stored signal gate 169 is enabled resetting bi-stable device 168 thereby closing gate 173 and terminating the current flow to the capacitor. In a time interval t 3 -t 6  capacitor 108-n has its charge increased to the value of the sample signal from capacitor 107-1 stored in circuit 134 by an equivalent process. A signal indicating that both storage capacitors have been charged as required is sent to control 140 via OR gate 196 and lead 633. Gates 110, 111 are closed and the next time slot is initiated. A quench signal is also applied to gates 113, 114 between times t 7  and t 8  to remove any residual charges remaining on the buses 124, 126 at the end of the time slot. Had the output from circuit 136 been more positive than that from circuit 134, constant current sources 120, 121 would have been used in like manner to charge capacitors 107-1, 108-n to the respective sample levels. Circuitry.-Figs. 3-6 (not shown) illustrate circuits that may be used for the constant current sources, select memory, sample and hold circuits, and control respectively. The constant current circuits employ transistor circuitry, the control 140 a series of monostable multivibrators (delay flops), and the sample and hold circuits each include ordinary transistors, an IGFET, an operational amplifier and a capacitor on which the sample signal is stored. The select memory is only shown in block form.