Patent GB-737864-A (GB)
Title: Improvements in or relating to digital computors
Inventor: WILLIAMS FREDERIC CALLAND
IPC: G06F3/06
Filed: 1949-06-22
Abstract: 737,864. Digital electric calculating-apparatus; electric digital-data-storage apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. June 21, 1950 [June 22, 1949], No. 16592/49. Class 106 (1). An electronic digital computor comprises a main high-speed store which is directly associated operationally with the computing elements of the machine and in which data words are immediately accessible, a subsidiary store having a digit signalling speed identical with that of the main store, means for effecting continuous synchronization of the digit signalling periods of the main and subsidiary stores, and a direct signal channel for the transfer of data words between the stores. General arrangement. In the complete computor illustrated in Fig. 1, an electrostatic C.R.T. store 12, e.g. as described in Specification 657,591, and a subsidiary magnetic drum store 11, e.g. as described in Specifications 707,634 and 707,635, are connected by gates opened for data transfer by a control unit 15 operated by the main control unit 14 which controls also the transfer of data between the store 12 and the computing unit 13. The normal operation, utilizing words (instructions and numbers) in store 12, is as described, e.g. in Specifications 705,479 and 734,341. The unit 14 comprises staticizors ES, Fig. 2, set up by a " present instruction " stored on one line PI of a control tube 20 and transmitted thereto from the main electrostatic store 21, having been selected by a " control instruction " stored on line CI. An instruction is normally obeyed in a " bar " comprising four (alternate " action " and " scan ") " beats " each comprising the time required to scan a C.R.T. having 32 lines containing 40 binary digits each. Instructions are normally 20 digits long and stored two per line, e.g. as described in Specification 731,341, and comprise main store address digits and 5 function digits f. A data transfer operation according to the invention is effected when digits f are all 0. The outputs from staticisors ES then operate a transfer control unit 24 to open a gate 23 so that a selected 40-digit " magnetic instruction is passed from the main store to staticisors MS. This instruction comprises a magnetic address (selecting one of 64 tracks on the drum), a main store address (selecting one of two pairs O and I of C.R.T's, T0 and T1, Fig. 3), and a function portion comprising the following digits: (1) D, controlling direction of data transfer (1 for outwards from C.R.T. store); (2) S/T, 1 or 0 according to whether both or one of tubes T0, T1 are involved; (3) G, 1 or 0 according to whether data transfer occurs during action or scan beats-effective only if S/T=O; (4) R, 1 or 0 according to which tube, T1 or T0, is scanned during scan beats (the tubes being scanned alternately and the normal sequential regenerative scanning being prevented during a transfer operation); and (5) Ch, normally 0, and 1 for a check operation described in Specification 737,863. Transfer control unit. The unit 24, Fig. 2, comprises trigger circuits Fw, W and T, Fig. 4, whose outputs (see Fig. 5 (c), (d), (e)) are mixed in unit 46 to produce a control voltage, Fig. 5, (f), which suppresses the prepulses, normally released at the end of every four beats, until the data transfer operation is completed. The f-digit staticisor outputs, Fig. 2, are applied to an input gate for trigger FW, so that when all the digits f are 0 it is switched over by a negative pulse occurring during beat A2 and is reset at the end of beat S3, Fig. 5 (c), by pulses produced by differentiating the counter waveform C0 described, e.g. in Specification 731,341. If digit D=1, waveform D1 is negative and opens gate 41 so that the output of trigger FW, Fig. 5 (c), switches over trigger W which is reset after an adjustable delay introduced by a phantastron circuit, the differentiated output then switching over trigger T (see Fig. 5 (d) and (e)), which is reset after a delay of 64 beats introduced by a sanatron circuit. If D=0, waveform D0 is negative and opens gate 42 so that trigger T is switched over during the beat S3 following the operation of FW, (see Fig. 5 (b), (c) and (g)), the gate 41 to trigger W being closed. The data transfer operation is effected during the T delay period under control of the trigger output waveform, the previous W - delay for outward transfer from C.R.T. store allowing time 'for relays in the magnetic writing head selection circuit 35, Fig. 3, to be set up. Transferring data from electrostatic to magnetic store. The output of a pair of C.R.T'S, selected by the store address digit set up on staticisors MS, Fig. 3, is passed to a gate 32 supplied, when D=1, through a gate voltage generator 39, with a " J " voltage waveform from a generator 40, described below, this waveform being as shown in Fig. 10 (b), (c) or (d), during a transfer period, according to the values of digits G and S/T. The order in which the pair of tubes is scanned is controlled by the R digit staticisor output through tube selection control unit 30, which applies blackout waveforms alternately to the tubes, so that if S/T=0 the tube whose output is allowed through the gate 32 is determined by digits G and R. The gate output is passed to the magnetic storage system comprising a waveform generator 33, write unit 34 (controlled by the inverted J waveform from 39), selection circuit 35, controlled through unit 38 from the tracks address portion of staticisors MS, and magnetic recording heads 36 one of which impresses the data to be transferred on to the surface of drum 37. At the end of the transfer, trigger T, Fig. 4, is reset and the normal scanning sequence of the electrostatic store is resumed. Transferring data from magnetic to electrostatic store. The reading heads 111, Fig. 11, for the drum 37 are connected to single-valve " pre-amplifiers arranged in groups 112 of sixteen. The output of one amplifier in each group is selected by a decoder 113 controlled by four of the track address digit outputs from staticisors MS, Fig. 2, and the group is selected in a " post-amplifier " 114 by a similarly controlled decoder 115. Thus an output from a single track is passed to a read unit 116, described in Specification 707,634, and a gate 117 controlled by generator 118, similar to generator 39, Fig. 3, and operative when D=0. The gate output is supplied to the selected tube or pair of tubes and an erasing waveform 119 is supplied to the usual regenerative circuits via generator 118 and line 110. Circuit details; Y-scan and J voltage waveform generators. The circuit for generating the Y-plate voltages for the C.R.T. stores comprises stages like that of Fig. 19 normally operating as described in Specification 682,156. When voltage T1, Fig. 5, and Fig. 10 (a), is positive, and the inverted voltage T0 negative, the halver waveforms Ha, Hs (positive during action and scan bears respectively) are passed through cathode followers V191, V194 to the suppressor grids of valves V192, V193. Thus, during action beats, valve V192 conducts, and the output applied through cathode follower V 195 to terminal 195 depends on the input on terminal 192 from a line selection staticisor. During scan beats the output depends on the counter waveform applied to valve V193 from terminal 193. A typical output waveform is shown in Fig. 9 (a). During transfer operations, however, voltage T0 is positive so that valve V193 is always conducting, thus producing the output shown in Fig. 9 (b). This enables corresponding lines of two tubes T0, T1, Fig. 3, to be scanned during successive beats. The " J " waveform generator 40, Figs. 3 and 11, comprises valves V201-V203, Fig. 20, having a common anode output circuit fed to cathode follower V204. The T0 voltage is applied to the suppressor grids so that the valves are operative only during transfer operations. If digit S/T = 1, voltage S/T0 applied to the control grid of valve V203 will be positive, thus producing a negative output waveform, Fig. 10 (b). If S/T=0 and G=1, voltage G0 will be positive thus allowing halver waveform Ha through the diode gate shown to the control grid of V202 and producing the output waveform of Fig. 10 (d). Similarly, if S/T=0 and G=0, valve V201 will provide the waveform of Fig. 10 (c). In the Specification, circuits are described and shown also for the triggers and gates of Fig. 4, and the units 30, 39, Fig. 3, and 113, 118, Fig. 11. Specification 734,073 also is referred to. Specifications 645,691 and 734,071 also are referred to in the Provisional Specification.