Patent GB-1033874-A (GB)
Title: Improvements in or relating to electronic digital computer systems
IPC: G06F13/18
Filed: 1965-03-11
Abstract: 1,033,874. Digital computers. NATIONAL CASH REGISTER CO. March 11, 1965 [April 16, 1964], No. 10362/65. Heading G4A. A digital computer system includes a data processor, at least one peripheral unit, and a memory directly accessible by the peripheral unit independently of the data processor when the memory is not being used by the data processor, the initiation of a new processor cycle being inhibited if the data processor requests access to the memory for the same period as the peripheral unit. Apart from differences in the timing control arrangements the computer system is similar to that of Specification 940,636, and includes a main memory 9 (Fig. 1, not shown), auxiliary memory 13 including jump registers, parallel arithmetic unit 11, programme control system 10, clock source 20, a processor timing control circuit 22 and timing control cicuits 24, 26, 28, 30 for the individual units 0, 1, 2, 3 of the memory 9. Each of the timing control circuit includes an electric delay line having a 6Ás delay corresponding to an operating cycle, a pulse from a generator 505 (Fig. 2, not shown) being transmitted along the delay line 40 and the appropriate delay line 42 &c. when a timing cycle is initiated. A fresh operation of the pulse generator 505 is inhibited until the former pulse has reached the end of the delay line 40 by means of diodes 502 connected at frequent intervals along the delay line 40. If the processor is operating with a peripheral unit, a single shot circuit 506 is triggered when a pulse reaches the end of the delay line 40, thereby inhibiting the generator 505 for an additional predetermined time. When a peripheral unit P-1 or P-2 (Fig. 3, not shown) requests access to the main memory 9, a corresponding flip-flop P1 or P2 is set, a further flip-flop P1F2 or P2F2 being triggered to indicate the direction of data transfer. Each peripheral unit may include one or more storage devices such as tape handlers which share the use of the memory address and access register associated with the unit. Assuming that a request is made by peripheral unit P-1, a control flip-flop CN1, Fig. 2, is set, thereby causing a flip-flop JM1 to be set towards the end of the cycle, the set flip-flop JM1 initiating a P-1 memory cycle during the next operating period T2, and causing a pulse to travel along that one of the delay lines 42 &c. corresponding to the selected memory part. A new processor memory cycle is inhibited if requested whenever a peripheral unit request is present by supplying a signal to prevent operation of the pulse generator 505. If the computer is performing a cycle not requiring access to the memory, however, this cycle can proceed. A 0À5 Ás delay circuit 515, Fig. 2, prevents a peripheral unit cycle being initiated if the peripheral circuit request occurs close to the end of a cycle. If a peripheral unit requests a memory cycle when the memory is not being used, as indicated by arrow 803 (Fig. 4, not shown), the desired memory cycle is initiated immediately, even though the current processor cycle has not terminated. Peripheral unit P-1 is given priority over unit P-2 so that if both units present a memory request during the same cycle, the request from unit P-1 is dealt with first, this priority being achieved by the arrangement of signals supplied to AND gates 519, 520, Fig. 2.