Patent GB-1416057-A (GB)
Title: Graphic data display assembly
IPC: G09G1/00
Filed: 1973-09-21
Abstract: 1416057 Cathode-ray tube displays COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 21 Sept 1973 [21 Sept 1972] 44330/73 Heading H4T In a cathode-ray tube display system in which a computer 2 supplies successive binary data words specifying successive points on the display (e.g. for curve tracing) via a memory 3 and D/A converter 4 to control deflections of the beam of the tube 1, comparators 26 and 36 compare, respectively, the first and second most significant digits 31, 32 of the instantaneous output word (indicative of the present position of the beam) with the first and second most significant digits 21, 22 of the subsequent input word (indicative of the position to which the beam is next to be deflected) and depending on the comparisons " 0 " or " 1 " output(s) are produced by comparators 26 and or 36 which on the occurrence of the transfer of the input data to the output of memory 3, as signalled by a pulse on conductor 7, operate or do not operate respective trigger circuit(s) 27, 37 feeding respective delay means 28, 38 producing output pulse(s) which act via an OR gate 8 to block subsequent transfer of new input data to the output of memory 3 for the duration of such pulse output(s) during which period the beam is blanked. The invention is particularly concerned with optimizing the time required to produce beam deflections which are effected with a blanked beam, e.g. deflections necessary to deflect the beam over a path which is not to be displayed particularly that required to deflect the beam between the end of a trace and the commencement of that trace during image "refresh" operation such time being dependent on the magnitude of the step voltage deflection required to produce it because the " settle-down " time of associated amplifiers is dependent on the latter. Therefore, delay means 28 produces a delay T equal to the time required for the maximum possible spot movement and delay means 38 produced a delay equal to T/ 2  + t where t is the amplifier " settle-down " time. In operation if the two inputs to either of the comparators are similar (i.e. both " 1 "'s or " 0 "'s) a " 1 " output results whilst if the inputs are not similar a " 0 " output is produced. Inequality of the inputs to comparator 26 (" 0 " output) indicates that the movement of the beam represented by the input data is greater than half the maximum possible deflection and requires more than T/ 2  for its implementation. In this case OR gate supplies an output pulse of duration T. If however the inputs to comparator are similar the input data is representative of a beam movement of less than or equal to the maximum possible deflection and trigger 27 does not operate so that no pulse is produced by delay means 28. Likewise inequality of the two inputs to comparator 36 (which have half the " weight " of the inputs to comparator 26) results in OR gate 8 supplying a pulse duration T/ 2  + t whilst equality of the inputs do not result in the production of an output pulse from gate 8. Thus inequality in the respective inputs to both of the comparators results in the maximum delay T whilst equality in both such inputs, indicative of no change or of a very small change in beam position does not result in the production of an output from OR gate 8 and the trace, therefore, is uninterrupted. Additional comparators connected to the digits of lower weights and controlling respective delay means producing delays T/ 4  + t, T/ 8  + t &c. may be employed.