Patent GB-1259529-A (GB)
IPC: H04N21/434
Filed: 1969-12-22
Abstract: 1,259,529. Redundancy reduction. WESTERN ELECTRIC CO. Inc. 22 Dec., 1969 [23 Dec., 1968], No. 62291/69. Heading H4L. In the video digital data transmission redundancy reduction system described in Specification 1,218,529, the buffer memory in which are stored video signals from the previous frame can become rapidly overloaded by a rapidly changing viewed scene and subsequently transmitted such that even large changes in the scene from frame to frame will not be stored due to the increased variable difference threshold. The reproduced scene at the reproducer is correspondingly degraded. To overcome this a plurality e.g. three of, such transmission systems are used, 70, 80, 90 each viewing a different scene. On the assumption that at any given time only one e.g. 70 of the systems will be viewing a rapidly changing scene, the outputs of each forward-backward counter 23-representing the " fullness " of the buffer memory-are fed to inputs 73, 83, 93 of control logic 44. The " fullest " buffer memory could be detected and connected via a time division multiplex switch 30 to the transmitter 33 and high capacity transmission channel 34 and the buffer memory rapidly emptied such that the difference threshold is lowered. One of the other buffer memories would then be the " fullest " and be connected in turn to the transmission channel, generators 55 transmitting a code defining, at the receiver, the buffer memory being read out. If however one of the video signals is from a picture which does not change for long intervals, the buffer memory will accumulate very few words over a large number of frames. These large number of frames will not be transmitted and an undesirable delay will arise at the reproduced display between the contemporary scene and that being displayed. Synchronization may also be lost. A second forward backward counter 25 is thus provided in each data compressor to determine the number of frames giving rise to the buffer memory contents. The control circuit 44 then preferentially couples that buffer memory storing data arising from the greatest number of frames, to the transmission channel via the T.D.M. switch, this selection criterion taking precedence over that depending on the " fullness " of the buffer memory. When the number of frames determined for all the compressors are the same, the " fullness " criterion is applied. If both the " fullness " and frame numbers are equal for all the compressors, compressor 70 is arbitrarily coupled for transmission. The control logic circuit performs a second function of detecting the average use made by a particular compressor of the transmission channel. If the use is found to differ significantly from a predetermined value, the value of the difference threshold which consecutive frame corresponding picture elements must show to warrant the updating of the frame memory 19 and storage of the new element data in buffer memory, is accordingly changed by changing threshold circuits 61/63. If compressor 70 is being under transmitted, the threshold is too high (too little fullness of buffer memory) and control logic 44 applies a signal to input 75<SP>1</SP> of three-stage shift register 55. The register is shifted to the left, removing the enabling pulse from the gate of highest threshold circuit 63, to that of the medium threshold circuit 62. Conversely a signal is applied to register input 75<SP>11</SP> if the compressor 70 is being over transmitted. The control logic circuit is shown in detail in Figs. 5 and 6, the detection of the numbers of stored frames and words being carried out in Fig. 5 and the adjustment of the threshold values in Fig. 6. Thus the frame number signals G1, G2, G3 from compressors 70, 80, 90 respectively are applied on respective lines 74, 84, 94 to difference circuits 521, 522, 523. Circuit 521 for example gives a 1 output if G1 is equal to or greater than G2 and a 0 if G1 is less than G2. The relations between G1, G2 and G3, the corresponding action to be taken are numerized in the following truth table. The connections to inhibited gates 525/527 ensure the correct actions, one of the selection signals C1, C2, C3 appearing at the outputs of OR gates 511/513 and eventually as corresponding bi-stable output pulses, on T.D.M. switch control wires 31, the timing of the selection signal in every N words read out of buffer 20 as controlled by gates 513, 533, 535 and pulses # B , derived from word read out pulses # w  via a " divide-by-N " circuit 548. The last condition of the truth table is fulfilled by AND gate 524 giving an output which enables gates 508/510. The output from difference circuits 501/503 detecting the differences in the buffer " fullnesses " in the same manner as the circuits 521/523, are allowed to form the selection signals C1, C2, C3. If both frame numbers and fullnesses are all equal, AND gates 504 and 524 both give outputs such that gate 514 produces a selection signal C1 for compressor 70. The read out pulses # W  are fed to the buffers on lines 72, 82, 92. Since the selection signals define the use of the transmissions channel by a compressor, they are fed on lines 551/553 to the threshold adjustment circuitry of Fig. 6. Counters 611, 621, 631 count the signals C1, C2, C3 occurring during the time needed for the transmission of K blocks of N words as defined by the reset/read out pulses applied to the counters from " by-K" dividers 540. The " use " counts B1, from the counter 611 written into store 612, added in circuits 613, to a " cumulative use " count A 0  obtained from all the previous K blocks. The sum (B 1  + A 0 ) is multiplied by a " decay weighting " factor D of about 0À96 to produce an updated value of A 0  i.e. A(1) for use in the next K blocks. The " cumulative use " counts A(1), A(2), A(3) are thus dependent on the uses in previous K blocks but with the weight of influence decaying with time. The average use of all the compressors is determined by summer 660 and " divide-bythree " circuit 661. This average is compared with A(1) &c. in comparators 641/643 and if the differences are greater than a value #, corresponding quantizers 651/652 produce shift left or shift right signals for the respective shift registers 55, depending on the sign of the difference.