Patent GB-1372797-A (GB)
Title: Communication apparatus
IPC: H04M11/06
Filed: 1972-11-02
Abstract: 1372797 Digital transmission; traffic control COLLINS RADIO CO 2 Nov 1972 [16 Dec 1971] 50568/72 Heading H4P A store and forward system arranged in the form of a loop, which may mesh with similar loops, comprises a control station and a plurality of message store and forwarding stations actuable to store an address and transmit a call message followed by a connect message on receipt of a call signal. All connect messages pass through a control station which issues poll signals after passage of connect signals. Loop, e.g. 86 connects loop terminators LDT, one 84 being connected, in the case of a single loop to a control station (ELC, Fig. 2, not shown), which forms in the case of an interconnected system, part (LDT) of a master group unit MGO which stores data temporarily prior to transmission from one loop to another. An MGU is two separate units; one may call on a local loop and the other may call on an intermediate loop. When a call is received on one loop, it is stored: a "connect" is returned to the caller and the other unit calls the following node. MGU 78 is one of a number connected to a unit RGT 74 which sets as a distributor. It may provide outputs at different speeds and includes synchronization by received clock signals. Messages may be passed to other RGTs e.g. 122 for distribution or direct to master group units, similar to MGUs but which do not have to function through LDTs. When one station, e.g. 104, e.g. having a teleterminal wishes to communicate with another e.g. 108, on the same loop, an address TTY 112  from the terminal is placed in a buffer store in SCU 100 which awaits a single pit select poll on the loop from MGU 78. After a connect message is circulated on loop 86 MGU 78 sends a new poll which advances the first SCU having information to transmit which adds the address of TTY 112 the whole being circulated round the loop until SCU 108 responds, which checks whether TTY 112 is busy; if so the response portion of the message is changed. If not busy 108 responds and SCU 100 sends a connect to 108 which returns an acknowledge if the parity is connect thus priming SCU 100 to receive select and connect clock signals, which on receipt places the devices in communication; SCU 100 then transmits blocks containing a select call plus data message one at a time, awaiting a correct reception signal before sending a further block. In an alternative arrangement a correct reeption signal is not awaited before further transmission. The term "in communication" means that transmission of blocks takes place between terminals but does not include a "hard line" connection. If however 104 wishes to communicate with say STN 120, a call address is stored in MGU 78. When the next poll is received on loop 78 an attempt is made to reach a particular MGU in MGC 64; if busy MGU 78 will try later. If free an address will be transmitted and a select call will be placed on loop 114. During this time there is no direct communciation between 104 and 78.  If station 120 responds the connect message from MGC 64 is circulated and stored in the SCU of SG 116 and a connect clock is sent, one link at a time to 104 which remain in communication for the transmission of signals until a disconnect signal is transmitted.  Loops may operate at different speeds and formats, e.g. word lengths from each other. In an alternative arrangement loops may operate in time slot manner. Biphase modulation may be used providing bit synchronization. Loop terminators may include a phase locked loop. Alternatively an asynchronous mode may be employed.  A character may comprise a message portion of 40 or 1024 bits preceded by a start bit, an operand of 7 bits and an address of 24 bits and followed by a check portion of 24 bits and a response portion of 8 bits. A "directory enquiry" unit may be incorporated in the system as part of a processor to provide addresses, previously unknown which processor may also store undeliverable messages and monitor call charges. Such processor may be duplicated with automatic changeover on failure of one.