Patent GB-1156521-A (GB)
Title: Improvements in or relating to Arrangements for Effecting Data Transfer between Two Data Processing Systems
IPC: G08G1/08
Filed: 1966-06-22
Abstract: 1,156,521. Traffic light control. SIEMENS A.G. 22 June, 1966 [23 June, 1965], No 27810/66. Heading G4Q. In an arrangement for controlling repeated operations in accordance with predetermined plans, e.g. controlling the switching of traffic lights, the control is exercised by a first data processing system spg to which data, e.g. changed plans, can be transferred from a second data processing system R. The arrangement described is concerned with the control of two traffic intersections, the first with lights Sg 1 , Sg 2  and the second with lights Sg 3  and Sg 4 , each in accordance with one of four signalling plans. Each data processing system R, spg is provided with a core type store ASP, asp, a control section StW, stw and a computer RW, rw. The lights Sg 1 -Sg 4  are controlled by switching circuits sch operated from the control section stw in response to signalling plans held in store asp. Information read-out.-Each second an operation control section ost 1  is triggered so that the contents of specified storage cells in store asp are extracted and fed via a read/write register 1sr 1  for evaluation in stw. First the three decimal digit address for cell, e.g. Z 1 , is fed via a converter u 1  to an address register ar 1  and at the same time a readout/write in command or both is fed to the section ost 1  via converter u 2 . This starts a counter chain in ost 1  and via time pulse switch ts 1, three pulses of a pulse train are fed to ar 1  to read in the address. This acts to prepare amplifier switches VS 1  and VS 2  for the appropriate columns and vanes if the core store ke. Assuming a read command this acts via timing switch ts 2  to reset the register 1sr 1  to zero and via switch ts 3  triggers a pulse generator tg 4  which via switches VS 1  and VS 2  applies partial current pulses to the columns and rows defined by the address register. Additionally switch ts 4  provides scanning pulses ta to switch VS 3  and the content of the addressed cell is fed to register 1sr 1 . Following the read-out pulse a write-in pulse ts appears and controls switches VS 1 , VS 2  to produce partial current in the addressed rows and columns in the opposite direction to that for read-out. In addition timing pulse ti via switch VS 4  produces in certain columns a reverse excitation in accord with the information in register 1sr 1  so that the content of the register is written back into the addressed cell. Immediately following the cycle the information stored in 1sr 1  is transferred to a buffer register pr 1  and thereafter the information is transferred to control section stw for evaluation. Evaluation.-Each signalling plan is stored in 3 cells in the store asp, i.e. one time cell and two signal cells. Each second all the plans are read out into register 1r 1  of control section stw for evaluation and possible action under the control of operation control section ost 2 . When the content of the first time cell is fed into in the information T 1  in the first two columns sp 1  and sp 2  indicative of time cell and signal plan 1 in operation produces the appropriate control operation in ost 1  whereby the content of 3rd column sp 3  indicative of real time is fed to a computer rw which adds "1" to the content and stores the result in register zr 1 , the content of the 4th column sp 4 , indicative of plan duration is compared in vg 2  with the content of zr 1  and if coincidence occurs restores the register zr 1  to zero, the content of the fifth column sp 5  being the address of the first associated signal cell Z 21  is fed into read-out register ar 3  and the previous address Z 1  in register ar 3  is transferred to write-in address register ar 4 . Finally the contents of columns sp 1 . sp 2 , sp 4 -sp 6  and register ar 1  are read into appropriate columns of register sr from which they are read back into cell Z 1  corresponding to the address in ar 4 . At the same time the content of cell Z 21  determined by the address in ar 3  is read into register 1r 1 . The SO in the first two columns programs control section ost 2  to compare the contents of columns sp 3  (green time) and sp 4  (red time) with the actual time stored in zr 1  in comparators Vg 3  and Vg 4  and if coincidence occurs to change over the associated traffic lights, in this case Sg 1  defined by a in the last column Sp 6 . In addition the address in column Sp 5  is entered in register ar 3  and that in ar 3  transferred to ar 4 . Thereafter the content of register 1r 1  is passed to sr and written back in cell Z 21  and the content of cell Z 22  is read into 1r 1  and similarly processed, in this case for light Sg 2 . When this information is written back into the store asp the contents of cell Z 2  (see Col. 5, Z 22 ) is read into 1r 1  but since the "0" in the second column indicates that it is associated with a plan which is not in use, the section ost 2  is controlled to add "1" to the actual time column and feed column 6 to read out register ar 3  so that the associated signal cells are passed over and the next time cell Z 3  read out. Information on traffic density &c. is fed to the store ASP of the computer R by means of operational control section ost 3  which is triggered every 5 sees. to affect data transfer from a series of counters Za 1 -Za 4  which are set by traffic strips bo 1  to bo 4  at the controlled junctions. A further operation control section ost 4  is provided in the control section stw to which is permanently allocated a number of transfer cells Z 951 -Z 000  in the store ASP of the processing system R. When data has to be transferred between the systems, i.e. when a plan has to be changed, information regarding the transfer is inserted in one of these cells, e.g. cell 955. Column sp 2  of the cell stores the direction of transfer, i.e. ASP-asp, column sp 3  the time at which transfer is to take place, sp 4  and  5  the read-out and read-in addresses respectively and sp 6  the block length (in cells) of the data to be transferred. Associated with ost 4  is an actual time register which is stepped forward each time the transfer cells are cycled. When its stored time agrees with that in column sp 3 , decoder dc 3  controls ost 3  to feed the contents of columns sp 4  and sp 5  into the read-out and writein register ar 9 , ar 10  in accordance with the transfer direction. The data is transferred first to register slr 2  where it is issued to cells Z 3  and Z 4 . Comparator vg 6  checks the block length.