Patent GB-974094-A (GB)
Title: Improvements in or relating to multiplexing devices
IPC: G08C15/08
Filed: 1961-05-30
Abstract: 974,094. Time division multiplex systems. SOC. DE PROSPECTION ELECTRIQUE SCHLUMBERGER. May 30, 1962 [July 19, 1961], No. 20886/62. Heading H4L. In a time division multiplex telemetering system in which the signals provided by a number of data transducers are sampled in turn to form a composite wave train for transmission either by line or radio system, means are provided for removing the switching transients and the D.C. pedestal components of the signals before the composite signal is transmitted. A flip-flop 12, triggered from a freerunning multivibrator 11, supplies output pulses at half the trigger frequency to a binary counter 13. The counter operates in conjunction with a matrix 14 and provides on lines A1, A2 ... An a series of sampling pulses 3D, 3E, 3F, Fig. 3. The outputs of multivibrator 11 and flip-flop 12 are also applied to a pair of AND circuits 16, 17 which are connected to an OR circuit 18. The OR circuit produces a square positive pulse 3B during the second and third quarters of each sampling pulse. AND circuit 16 also triggers, via a multivibrator 19, a signal generator 20 which produces a single sinusoidal cycle 3C during the second and third quarters of each sample pulse. The output of the signal generator is applied in common to the input of data transducers 32a, 32b, 33 and appears at the output of each transducer modified in amplitude in accordance with the physical condition being sensed by that transducer. Each transducer signal, e.g. that supplied from unit 32a is applied to a switching circuit including a transistor 34a, a coupling diode 37a and a control diode 36a which is connected to a circuit 15a in which the sampling signal for that switching circuit is inverted. Diode 36a normally conducts and transistor 34a and diode 37a are normally cut-off but on receipt of a sampling pulse the conditions are reversed and the output signal from transducer 34a is developed across a resistor 38 which is commonly connected to each channel. The composite signal 4A developed across resistor 38 comprises in each time space allocator to a channel, a D.C. pedestal signal determined by the voltage drop across the various switching components allocated to the channel and in the second and third quarters of this time space the A.C. transducer signal. The D.C. component may vary between channels, i.e. between A1 and A2 and introduce a switching transient. The signal across resistor 38 is applied via an amplifier 40 and coupling condenser 43 to the input of transmitter 41 and to a gate circuit 44. The gate is controlled by the output pulses from OR circuit 18 after inversion in circuit 48 and acts to open the gate and hence earth the input to the transmitter during the last and first quarters of each channel time space. During this period the condenser adjusts its D.C. voltage drop 4B from the D.C. pedestal voltage present in the previous channel period to that present in the following period. The resultant signal 4C applied to the transmitter is free of pedestal components and switching transients. One channel, switched by sampling pulse An is provided for synchronization purposes, the synchronizing signal being provided by an oscillator 39 triggered by the output of the OR circuit. In a further arrangement, Fig. 5, (not shown), in which the system includes high and low level transducers means are provided for forming a composite signal from the low level circuits and amplifying this before combination with the high level signals.