Patent GB-893354-A (GB)
Title: Improvements relating to data handling apparatus
Inventor: FROGGATT ROBERT JUSTIN
IPC: G11C17/02
Filed: 1957-04-30
Abstract: 893,354. Programming arrangements for electronic computors. ELECTRIC & MUSICAL INDUSTRIES Ltd. April 24, 1958 [April 30, 1957], No. 13798/57. Class 106 (1). Instruction numbers each identifying a composite instruction or microprogramme for data handling are stored in rows of a main storage matrix M1 using magnetic cores, the number of the instruction currently being carried out always appearing in row 1. At the end of each operation an " operation finished " signal inserts a bit into shifting register R2 and sets the cores of row 1 of matrix M3 of magnetic cores to state 1, the subsequent re-setting of columns of M3 by R1 causing a sequence of bits on each of a number of wires laced through the cores. These wires continue as row wires through matrix M2 of magnetic cores so that the sequences form an output instruction from M2 which may act through line L6b to read the current composite instruction number from row 1 of M1, which number is passed through read amplifiers RA to the arithmetic unit. Here 1 may be added to it by a signal on line L7 to get the next instruction number which by opening gate G1 is written by write-drive unit D1 on to row 1 of M1, and which passes to the instruction decoder for obtaining the address of the new composite instruction. This address is obtained from digits 8-15 or 16-23 of the 36 digit output on line L8 which digits are set up in static register SR1 or SR2 and transferred on line L5a-L5h to pairs of cores e1a-e8b of matrix drive unit D2 by a signal on line L11e or L11f, e1a-e8a registering " 1 " 's and e1b-e8b " 0 " 's. To each combination corresponds a row in M1 selected by the use of 256 cores f1-fm, each with 1 drive and 7 inhibit windings energized through transistor amplifiers H1-H16 from the output of cores e when the latter are reset by " a " pulses; the setting of one of the cores f1-m through its corresponding transistor amplifier J allows a core-selection pulse from M2 on line L21 to be transmitted to the corresponding row of cores in M1. This core selection pulse is initially -ve-going and resets all " 1 " cores in the row to " 0 " giving an output on the corresponding column read amplifiers RA, thus registering the new composite instruction in the arithmetic unit AU; it is written in its row of M1 by opening gate G2 and hence re-entering the word in write-drive unit D While still in the unit AU, the instruction number may be modified in accordance with its first three (modifier) digits by unit MU, it is then passed to the instruction decoder. Digits 3-7 are set up on cores g1-g5 and transferred at the next " a " pulse to pairs of cores h1a-h5b in a similar manner to SR1 or SR2 acting on cores e1a-e8b, and according to the combination set up these act to set one and only one of the 32 cores j1-jr which on being reset by a signal on L11h sets up the composite instruction or microprogramme by switching to state 1 a series of cores in M2 through which the corresponding decoded function line is laced. All the above operations have been effected by the signals obtained from M3 by shifting register R2 and passed unchanged through M2; when the bit reaches the end of R2 it is passed by the next " a " pulse to shift register R1 which re-sets column by column the cores set by the selected microprogramme wire, thus giving a sequence of bits on each row wire of M2, each set of parallel bits constituting a step in the complex instruction now carried out. If at the end of a micro-programme subsequent instructions are to be conditional on the result of a test on one digit of the number stored in unit AU, the digit is registered by one of the pairs of cores K1-4a, b depending on the particular line in L13 energized from the matrix M2, the " a " core of the pair being set if the digit is " 1 " and the " b " if it is 0. At the next " a" pulse a new microprogramme may be set up by an output on one of the lines L15 and a bit inserted into R1 to step it out, if core pair K1 or K2 has been chosen. If K3 or K4 has been chosen then depending on the result of the test either a " normal or an " alternative " sequence pulse is transmitted to M3, to set the cores of either row 1 or row 2 of M3. The " normal " sequence pulse initiates the " next " instruction as described above; the " alternative " sequence when read out of M3 in the same way modifies the previous instruction number to obtain the address in M1 of a " branch " instruction. Specifications 893,353 and 893,355 are referred to.