Patent GB-1397317-A (GB)
Title: Distortion-correction systems for pulses derived from  magnetic layer stores
IPC: G11B20/10
Filed: 1972-08-24
Abstract: 1397317 Data storage timing system SIEMENS AG 24 Aug 1972 [27 Aug 1971] 39372/72 Heading G4C A digital circuit, for use with a magnetic recording medium on which data are recorded in the form of magnetic transitions, to compensate for time displacements of signals read from the medium caused by a change in the frequency of the transistions, includes a shift register for storing a sequence of signals read from the medium, a circuit arranged to detect for each signal the sizes of the intervals between the signal and the succeeding and preceding signals, and three delay circuits having different delay prriods, the arrangement being such that a signal, for which the interval between it and the preceding signal is longer than the interval between it and the succeeding signal, is fed to the longest delay circuit, a signal, for which the interval between it and the preceding signal is shorter than the interval between it and the succeeding signal, is fed to the shortest delay circuit, and a signal for which the two intervals are equal is fed to the intermediate delay circuit. When data recorded on a magnetic medium in the form of magnetic transition having two frequencies, e.g. phase modulated or two frequency recorded data, are reproduced a change in the frequency of the transitions causes the reproduced pulses to be phase displaced. The Specification states that pulses at each end of a high frequency sequence lying between two low frequency sequences are displaced away from the centre of the high frequency sequence. The reproduced signals are stored in a shift register SCH and for each signal the intervals between it and the preceding and succeeding signals are checked. If the intervals are equal a circuit SA1 produces an output, if the first interval is longer than the second a circuit GR produces an output, and if the second interval is longer than the first circuit KL produces an output. The lengths of the two intervals for each signal indicate whether a frequency change has occurred. Thus if the two intervals are equal no frequency change has occurred and no correction is required. The signal is thus passed from the shift register to a delay circuit with a period t 0 . However if either interval is longer than the other a frequency change has occurred and correction is required, the signal being fed from the shift register to one of two delays having periods t 0+x , and t 0-y  respectively depending on which interval was the longer. The delay circuits may be counters driven by pulses used to shift date through the shift register and arranged to produce an output at a predetermined count. The values x and y may be equal. It is stated that the delay periods may be adjustable in accordance with, e.g. the speed of the recording medium, and the direction of motion of the recording medium. The delays may be changed by changing the predetermined number or the frequency of the shift pulses. The Specification describes, Fig. 3 (not shown), a circuit consisting of gates and flip-flops for determining the relative sizes of the two intervals for each signal and for delaying the data signals accordingly.