Patent GB-1403602-A (GB)
Title: Data processing systems
IPC: H04L12/403
Filed: 1972-10-06
Abstract: 1403602 Electric selective signalling INTERNATIONAL BUSINESS MACHINES CORP 6 Oct 1972 [29 Oct 1971] 46162/72 Heading G4H In a data processing system wherein a master station is linked by cable to m terminals TJ i  divided into two groups GT1 i , GT2 j  (i, j = 1, ..., N # m) accessed by respective channels CC1, CC2, control is exercised by the transmission of a bit-serial cyclic word SCV POLL, each terminal of a group being timed to the same word but only when presented in a phase unique to that terminal. When the master station receives a polling request (e.g. from GT1) it sends out a preliminary configuration message CNFG POLL to establish a service polling relationship between a group of sequential terminals which can then exclusively access a shared facility in response to the SVC POLL transmission for that group. CNFG POLL consists of two parts: an n-bit MASTER part (2<SP>n</SP> # N) and a "feedback shift code" part, one bit of which is added to the signal by each polled terminal having an ACCEPT LATCH set. In the Ayth such terminal (Fig. 5), a counter 20 is preset to -n and then incremented to 0 by the detection of each MASTER bit. At a count of 0, feedback shift circuits 28 are activated and their output is compared in 36 with the feedback shift code bits received at 14. If there is a mismatch, an ERROR signal is sent back to the MASTER station. If not, then the shift code bits are transmitted to the cable (where they tag on behindthe MASTER bits), circuits 28 adding the Ayth bit to the signal. At this point counter 20 reads Ay and circuits 28 contain the first Ay bits CSy of the cyclic feedback shift code. When all the terminals of the subgroup have been configured by establishment of their states Ay and CSy, the subgroup is eligible to participate in the service polling procedure, which begins with the transmission of N master bits and continues with the selective addition by each terminal of an appropriate bit. In terminal Ay (Fig. 6), Ay and CSy are used to preset a counter 109 and feedback shift circuits 111. 109 is counted down to 0 as the first Ay bits are detected (these are in effect ignored by the terminal), whereupon bit (Ay + 1) is stored in a latch 126 and the next N bits received via 14 are compared in 129 with the output from 111. If there is no mismatch (i.e. if no previous terminal has already requested service) and if the terminal does not itself require service, then bit (Ay + 1) is added to the end of SVC POLL as it passes downstream. Thus each terminal ignores progressively more bits at the beginning of SVC POLL and compares progressively shifted states of the feedback shift code. The first terminal to require servicing will fail to append its (Ay + 1) bit to the end of SVC POLL and channel cc1 will return to the idle state at time (Ay+N) to prevent all subsequent channels from accepting service. Since the first Ay bits of SVC POLL are ignored by terminal Ay, the master station can effectively exclude the first m terminals from the service poll process by transmitting the complements of the first m bits of an (m + N)-bit SVC POLL word; each of the first m terminals will detect a mismatch and will fail to appropriate the shared facility, but the rest of the terminals will react as before.