Patent GB-1049589-A (GB)
Title: Selection system for electrical circuits or equipment
IPC: H04Q3/545
Filed: 1964-12-30
Abstract: 1,049,589. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. Dec. 30, 1964 [Dec. 30, 1963], No. 52822/64. Heading H4K. In a system in which, on seizure, junctor circuits or the like are allocated a supervisory storage section in one of a number of storage matrices, each matrix giving service to a group of junctors, storage sections in each matrix are provided to record a demand from a supervisory storage section for service from a common circuit such as a marker, the aggregate of such storage sections in all matrices serving the junctor groups comprising a storage chain in which demands for connection to a common circuit are queued. As shown in Fig. 1, the matrices BM1 to BMn each provide a storage capacity of 250 sections to serve a group of 384 junctors which in turn serve a group of 2000 subscribers. Each storage section comprises a row of ferrite cores to store the busy/idle condition of the section, the identity of the junctor being served, an indication of the sequence state of the junctor, and a record of the loop conditions on both the calling and called sides of the junctor. A distributer DA and a scanner for each matrix such as EXM give sequential or selective access to the matrix rows, the data of each supervisory store being set up on bi-stables in a register such as RLE for examination by a local logic circuit CLI. Data is processed centrally by logic circuit CLC which may be a programme controlled data processor. Each matrix, for each common circuit that is required by the supervisory stores, has a storage row such as CT1 which with the corresponding storage rows in the other matrices forms a queue storage chain for demands for connection to the common circuit. The only such common circuit shown is the marker MQ which gives service to the queue formed in stores CT1. Stores CT2, CT3 provide queue storage chains for other common equipment such as may be needed for automatic message accounting, call charging &c. In a supervisory store the state of cores to1, to2 indicate the common circuit from which service is required and the state of core to3 indicates whether the request for service has been allocated a place in the appropriate queue storage chain. In each compartment of the queue storage chain cores toi and toj indicate whether the compartment is empty or whether it is occupied by the matrix and row identity of a supervisory store in need of service and, in this latter case, whether the compartment is or is not first in the queue for service. The local logic circuits CL1 of each matrix are controlled by pulse cycles t0, t1 t2 and t4, and t0<SP>1</SP>, t1<SP>1</SP>, t2<SP>1</SP> and t4<SP>1</SP>, the second cycle reading and writing from an addressed supervisory storage section in pulse times t0 and t4, and in pulse times tl and t2 effecting transmission and reception of data to the central logic circuit CLC. The first cycle of pulses governs the same functions for the queue storage sections such as CT1. During a sequential scanning of supervisory circuits by distributer DA the detection of a request for service unaccompanied by a position in a queue store (as made manifest on cores to1, to2, to3) causes a signal to be sent from the local logic circuit CL1 to the central logic circuit CLC which responds by stopping the scanning of DA to preserve the identity of the calling store. The pulse cycle t0<SP>1</SP>, t1<SP>1</SP>, t2<SP>1</SP>, t4<SP>1</SP>, is suppressed until the central logic circuit programme allows it to give attention to the supervisory store when the cycle is allowed to recommence so that the core to3 may be switched to indicate that the calling store is being given a place in the queue. By employment of the scanners EXM the central logic circuit CLC causes simultaneous read-out to staticizing circuits RLE of the queue storage chain compartments of all matrices. A scanner EXB is then employed to examine each compartment of the chain in search of the first free one upon discovery of which the identity of the calling store as indicated by the held condition of DA is recorded and the central logic circuit retires under control of its programme. Each queue storage chain has a pair of bi-stable circuits to indicate that at least one supervisory store is queueing or that the queue is full. If the queue is empty as indicated by these bi-stable circuits, then CLC does not scan but takes a predetermined first storage chain compartment. If the queue is full then CLC retires without switching core to3 in the supervisory store, scanning being resumed in anticipation of a free storage chain compartment being found on the next scan. When one of the common equipment facilities, such as marker MQ, becomes idle its state is detected by CLC which consults the queue storage chain associated with the equipment. Such consultation is effected by staticizing the storage chain compartments of all matrices and scanning by EXB in search of that compartment marked by cores toi, toj, as first in the queue. The supervisory store identity in that compartment is then used to connect that supervisory store to the common equipment for the requested service. The next compartment in the storage chain is marked as first for service and the data of the served compartment is cleared. Since the central logic circuit CLC handles all transactions on a one at a time basis connections between itself and circuits such as the marker MQ, and matrix store logic circuits such as CLI, can be effected as shown in Fig. 8 by the use of buses BO1, BO2. For MQ to supply data to CLC it is gated to BO1 and CLC is gated to BO2 and vice versa if CLC transmits to MQ.