Patent GB-1494629-A (GB)
Title: Time division switching system
IPC: H04Q11/04
Filed: 1974-12-19
Abstract: 1494629 Automatic exchange systems WESTERN ELECTRIC CO Inc 19 Dec 1974 [21 Dec 1973 (3)] 19871/77 Divided out of 1494628 Heading H4K In a t.d.m. system wherein each connection is allocated a unique time slot in a repetitively recurring series of time slots, a port pulser memory means is provided for associating each line switch (port) currently serving an interconnection with the time slot to which said interconnection is assigned, the arrangement being characterized by means effective during each occurrence of a slot for applying signals identifying said slot to said port pulser memory means, and means responsive to the receipt of said slot identity signals by said port pulser memory means for closing the line switches currently associated with said slot. The invention is applied to a program controlled PBX having a single common speech bus utilizing a frame of 64 time slots and a supervision superframe of 64 frames, the parent Application claiming the supervisory frame arrangement. The port pulser memory means is a contents addressable store having one location for each line switch (port) of the system, the slot allocated to the interconnection being stored in each location corresponding to a switch to be operated for the interconnection. Most of the circuits are in integrated circuit form. General description.-In order to describe the operation of the system let it be assumed that the system advances from (supervision) frame 1 to (supervision) frame 2 and that frame 2 and the corresponding time slot 2 are in an idle condition and not serving a call. In this case, and "idle" status word is currently stored in the slot 2 word of the SAM memory 301. The slot counter 303B applies a 2 over conductor 310 to input 310 of the SAM memory to read out the "idle" status word for slot 2 to path 317 which extends to the JUMP ADDRESS input of the processor, and the receipt of the "idle" status word places the processor under control of the program subroutine "idle". The system scans idle ports for service requests. For the currently described call, the processor now applies signals over path 307 to advance the port address counter (PAC counter) 314 one position. This counter has a position representing each port or line circuit and is used to detect service requests. When the PAC counter 314 is incremented one position, its contents are transferred to the port address buffer 309 which receives the port address, temporarily stores it, and applies this information over bus 320 to the line switch controller 316. The receipt of this information causes the controller to interrogate the corresponding line circuit to determine its current on-/off-hook status. This status is returned over conductors 322 to the controller which passes it via path 321 and the compare bus 308, to the compare input of the processor 304. If the port is idle or on-hook, the PAC counter 314 is again incremented by a signal from the processor on path 307, and the next port is interrogated. This process continues until the end of frame 2 or, until a port is found that is in an off-hook status. An off-hook status may represent a valid service request, or a line currently in a talking condition; it may also represent a line fault. The memory 305 i.e. the busy idle memory (BIM) portion of this memory, is used to determine whether a detected off-hook condition of a port represents a new service request. The port number currently in the port address buffer 309 is now applied over path 320 to the lefthand input of the memory 305 and steered to the BIM memory by means of the processor gating signals. The receipt of this port number causes the memory to read out information indicating the current busy-idle state of the port, and to apply it over path 323 and via compare bus 308 to the COMPARE INPUT of the processor. If the BIM indicates that the port is busy, this means that the port is currently involved on another call in another time slot, and the scanning of the ports continues under control of the PAC counter 314. If the information received from the BIM memory indicates that the port was idle on the last scan, the current off-hook state of the port may represent a new service request. Since it may also represent a transient condition it cannot be definitely determined during this occurrence of frame 2 whether the current off-hook state of the port represents a valid service request. To assist in such a determination, a busy indication is written into the word of the BIM memory that is associated with the currently scanned port, which is assumed to be port 8. The processor now applies signals over path 302 to erase the "idle" status word in the slot 2 portion of the SAM memory and in its place write a "hook check" status word. A 2 representing frame 2 and slot 2 is written into the talk slot portion for port 8 of the port address memory (PAM memory) 313. The port 8 address information is supplied to the left input of the memory from the port address buffer 309; the 2 is supplied to the top input of the TALK SLOT portion of the memory by the frame address buffer 326 which stores the current frame number. This frame nimber is received by the buffer from the frame counter 303A via path 306. This completes all of the work that can be performed during this occurrence of frame 2. The comparator 303 detects the last microsecond assigned to frame 2 when both the frame and the slot counters are in their 2 position. The comparator then generates output signals which perform a number of control functions included among which is the advance of the frame counter one position to frame 3. The system then performs work for frame 3 and so on until the system returns to frame 2 and the "hook check" status word currently stored in the slot 2 portion of the SAM memory is applied via path 317 to the JUMP ADDRESS input of the processor 304. This places the system under control of the "hook check" subroutine. On this next occurrence of frame 2, the frame number of 2 is applied to the TALK SLOT portion of the PAM memory to cause the memory to perform a content addressable search for the identity of the port or ports currently associated with frame 2 and slot 2. As a result an 8 is applied over path 325 to the port address buffer 309, and thence over path 320 to the line switch controller 316. This information causes the controller to determine the current supervisory status of port 8 and to return this information over paths 321 and 308 to the processor 304. If the port is onhook at this time, the processor concludes that the prior off-hook state did not represent a valid service request. It then erases the busy indication of port 8 in the BIM memory and erases the association between port 8 and slot 2 in the TALK SLOT portion of the PAM memory 313. If port 8 is in an off-hook condition, the processor proceeds with the work functions required to connect the calling line to an originating register 329-A, 329-B. The first function required at this time is to change the status of the slot 2 portion of the SAM memory from "hook check" to "register request". This is done under control of a 2 applied to the right side of the SAM memory on path 306 from the frame counter 303A and under control of the "register request" status word applied to the upper input of the memory over path 302 from the processor 304. These two items of information together write the new status word of "register request" in the slot 2 word of the SAM memory. On the next occurrence of frame 2, the "register request" status word is read out of the SAM memory and is received by the processor. The system then selects a register by applying a signal to the permanent address memory 315 which applies the port number of a first register to the port address buffer 309. This port number is applied by the buffer to bus 320 which causes the controller 316 to determine the busy-idle status of the first register 329-A, 329-B. If this register is idle, it is seized for use on the call. If it is busy, the port address of the next register is derived by applying the port address of the first register to the hunting address memory (HAM memory) 305 and by gating out the port number of the next register over path 325 and into the port address buffer 309. In this manner, a plurality of originating registers may be tested in succession until an idle one is found. When an idle originating register is found, this information is applied to the processor 304 over paths 321 and 308 and the processor performs a write operation in the PAM memory 313 to associate the port number of the register with frame 2. This is done by applying the port number of the register to the left side of the PAM memory on path 320 from the port address buffer 309, by applying the frame number of 2 from the frame address buffer 326 to the upper input of the talk slot field, and by applying the other gating signals required from path 307 to cause the memory to perform the required writing operation. At the same time the processor changes the call status word for frame 2 in the SAM memory from "register request" to "dial tone", and the calling party hears dial tone which is supplied to the time division bus (TDB) from tone generator 328. The tone generator is connected at its input to bus 317 which receives the call status for each call served by the system as the slot counter advances the SAM memory once each microsecond from slot to slot, and the call status words cause the generator to apply the required tones to the time division bus. Upon hearing dial tone, the caller dials the called station digits, which are received and registered in known manner. The call status in the SAM memory is changed to "dialling" when the first dial pulse is detected, to cause the tone generator 328 to remove dial tone from the time division bus during time slot 2. A plurality of occurrences of frame 2 occur while the called number is being dialled and during ea