Patent GB-1280827-A (GB)
Title: Improvements relating to apparatus for synchronizing a clock with a received signal
Inventor: GRIFFITHS JOHN MICHAEL
IPC: H04J3/06
Filed: 1968-10-28
Abstract: 1280827 Multiplex pulse code signalling POST OFFICE 20 Oct 1969 [28 Oct 1968] 51072/68 Heading H4L In a time division multiplex P.C.M. system means are provided for correctly timing a locally generated synchronizing signal in relation to the incoming signal. The arrangement described uses a ternary code and the appearance of an excluded code group not normally used for signalling indicates loss of synchronism. As described a three-digit ternary code is used in which the word 000 is excluded so that its occurrence as a word indicates a phasing error, but its occurrence as parts of two consecutive words is taken to indicate that phasing is correct. These two indications, "all zero word" and "out of word all zero group", are given weightings of + 3 and - 1 respectively and the cumulative weight is stored. In normal conditions the cumulative weight tends to be of decreasing positive value which is not allowed to fall below zero but if synchronism is lost a positive value is stored and at a threshold value of + 7 the local clock phase is shifted by one digit, this being repeated until synchronism is restored. As shown, the input digital data is supplied via terminal 1 to a three zero detector 3 comprising bi-stables B1S1, B1S2, B1S3 and a NAND gate NG1 followed by an inverter 1NV1, the bi-stables being clocked at digit rate by signals derived at 4 from the incoming signals. A distributor 2 is also driven by the clock 4 and is controlled through a divide-by-three circuit 5 by pulses which delineate word intervals. The output of 1NV1 is supplied to an input of NAND gates NG2, NG3 which are also connected respectively to oppositely phased outputs of circuit 5, the outputs of gates NG2, NG3 being inverted to indicate an all zero word or an out of word all zero, respectively. The inverted outputs of gates NG2, NG3 are supplied to a cumulative weight store 8, Fig. 2 (not shown), to amend the weight stored by + 3 or - 1 respectively, within the limits + 7 and 0. The inverted output of NG2 is also fed to a NAND gate NG4 together with a signal a from store 8 which indicates that the weight stored is greater than or equal to four. The output of gate NG4 is supplied via an inverter 1N4 to a NAND gate NG6 whose other input is a "STATE STORED" signal from a divider state store 11. The divider 5 may be in three different states 1, 2 or 3, which related to the Q outputs of bi-stables B1S4, B1S5 are 01, 10 and 11 respectively and the "STATE STORED" signal is 1 for state 1 and 0 for states 2 and 3 this being derived via NAND gates NG8 to NG11. When an all zero word is detected the output of NG4 is 0, divider 5 is in state 3 and the output of NG5 becomes 1 so that on the next clock pulse the Q output of B1S4 is set to 1. NG6 inverts the output of divider state store 11 and NG7 inverts the output of NG6 whereby the Q output of B1S5 is set to 1 on the next clock pulse or changes to 0 according to whether store 11 is storing state 2 or state 1. Thus the divider steps either from state 3 to state 3 again or on to state 2 on the next clock pulse so that it is set to the last state stored at 11  via the gates NG8, NG9.