Patent GB-1533171-A (GB)
Title: Line switching arrangements for interconnecting data transmission channels
IPC: H04L12/00
Filed: 1976-01-19
Abstract: 1533171 Data transmission; switching arrangements WESTERN ELECTRIC CO Inc 19 Jan 1976 [20 Jan 1975] 2049/76 Heading H4K A common control line switching arrangement for interconnecting data transmission channels has a plurality of interface circuits for applying received data signals to an associated intra-arrangement channel, switch means for interconnecting intra-arrangement channels to provide a data communication path through the switching arrangement, and a common control circuit including means for sending control data signals to the interface circuits by way of the intra-arrangement channels, means in each interface circuit being responsive to the control data signals for controlling the application of received data signals to the associated intra-arrangement channel. As shown, a switching arrangement is connected to data subscribers by two-way loops, e.g. loop 102 operating at 56 kilobits per second or loop 103 operating at 9.6 kilobits per second, and to similar switching arrangements by way of a multiplexer/demultiplexer 115 and a two-way transmission line 101, e.g. operating at 1.54 megabits per second. The loop 102 is connected to an office channel unit 106 which assembles data from a subscriber into 8 bit bytes and inserts a control bit in the eighth bit position, the control bit being '0' when the subscriber is "on-hook" and '1' when "off-hook". In the opposite direction, unit 106 receives a stream of bytes from transmission path 116, strips the control bits therefrom and passes the information bits to the subscriber. A unit 107 performs corresponding operations for a 9.6 k.b.s. subscriber. Trunk circuits 111 and 112 receive and distribute data bits to the multiplexer/demultiplexer 115. A crossbar switch (not shown) in link and connector circuit 157 (i.e. an intra-arrangement channel) provides the switching interconnections which are determined by marker/decoder circuits 155, 156, 161. Digital line circuits 108 and 109 (constituting the interface circuits), trunk circuits 111 and 112, and a common control including the marker circuit 156 and a digital register sender circuit 110, are also connected to the link and connector circuit 157, the circuits 108 and 109 being connected by respective two-way paths 116, 117 to units 106, 107 and the trunk circuits being connected by respective two-way paths 143, 144 to the multiplexer/demultiplexer 115. The register sender 110 accepts inband digital address signals that control the switch and sends inband digital data dial tone and call-progress codes to a subscriber and to trunk circuit 111, 112, and line 101 for interchanging data between the line and trunk and intra-arrangement channels. The register sender also sends a "not ready" call progress signal to a calling subscriber when the called subscriber, although "on-hook", is not ready to receive a call. The precise way in which the various control operations are effected is described with reference to Figs. 2 to 30 (not shown) which also illustrate in schematic form the various circuits constituting the switching arrangement, the operation being such that data on the subscriber line is prevented from garbling supervisory data being interchanged between the various units of the switching unit, whilst the subscriber is prevented from monitoring the supervisory data which could institute improper operations in the subscriber equipment.