Patent UA-83310-U (UA)
Title: Reversible shift register
Inventor: KACHURIN MYKOLA YAKOVYCH
IPC: G11C19/00
Filed: 2013-03-26
Abstract: A reversible shift register comprises a group of n state flip-flops, first OR gate, first and second AND gates in each bit, combinatorial binary adder SM of number of uncompressed binary code units, first DC1 and second DC2 decoders for transformation of position binary code of units number to unitary code of units, second OR gate in each bit, except for last one, third OR gate in each bit, except for first one, fourth and fifth OR gates which outputs are connected to corresponding complemented control input of first DC1 and second DC2 decoders, nullification and synchronization inputs of shift register connected correspondingly to nullification and synchronization inputs of all state flip-flops, uncomplemented data input of reversible shift register connected to first input of first AND gate in first bit. First input of first AND gate in each digit, except for first one, is connected to true output of previous bit flip-flop. The true output of state flip-flop of last bit is an output of reversible shift register in right shifting, third inputs of both AND gates in each bit, except for first one, are connected to control bus of shift register mode of operation (shift/code compression) and to first inputs of fourth and fifth OR gates. Second inputs of first AND gates in each bit are connected to right shift bus and to second input of fifth OR gate. Second inputs of second AND gates in each bit are connected to left shift bus and to second input of fourth OR gate. Complemented data input of reversible shift register in left shifting is connected to first input of second AND gate in last bit. First input of second AND gate in each bit, except for last one, is connected to true output of next bit flip-flop. True output of first bit state flip-flop is an output of reversible shift register in left shifting, wherein true outputs of flip-flops of all bits are connected to corresponding inputs of combinatorial binary adder SM of number of uncompressed binary code units, which outputs are connected to corresponding inputs of DC1 and DC2 decoders. Outputs of second OR gates in each bit, except for last one, are connected correspondingly to third input of first OR gate in this bit. Second input of second OR gate in each bit, except for last and second-to-last one, is connected to output of second OR gate in next bit Second input of second OR gate in second-to-last bit is connected to output n of DC1 decoder and to third input of first OR gate in last bit. Outputs of unitary code of first decoder DC1 are connected to corresponding first input of third OR gate in each bit, except for last one. Outputs of unitary code of second decoder DC2 are connected to corresponding first input of third OR gate in each bit, except for first one. Output of units number n of second decoder DC2 is connected to fourth input of first OR gate in first bit and to second input of third OR gate in second bit. Second input of third OR gate in each bit, except for first and second one, is connected to output of third OR gate in previous bit. Outputs of first and second AND gates in each bit are connected correspondingly to first and second inputs of first OR gate in this bit. For state flip-flops CDR-flip-flops are used. Output of first OR gate in all bits is connected to D-inputs of CDR-flip-flops.