Patent GB-1137705-A (GB)
Title: Oscillator
IPC: H03G3/34
Filed: 1966-04-12
Abstract: 1,137,705. Oscillators; band-pass filters; telegraphy. INTERNATIONAL BUSINESS MACHINES CORP. 12 April, 1966 [15 April, 1965], No. 15815/66. Headings H4P and H3T. A free-running generator of triangular waves comprises a capacitor-integrator capable of being charged with potentials of opposite polarities, switching means for reversing the polarity if the charging potential reaches a predetermined level, and selection means for varying the value of each charge potential so as to vary the duration of the cycle. The invention is described as applied to a frequency-shift data transmission system, the oscillator frequency being shifted to transmit " 0 " and " 1 " signals. Some of the individual circuits are described in other specifications as indicated below. Frequency-shift data transmission system (Fig. 1).-A transmitting unit 1 and receiving unit 2 are connected to similar remote units via a line 3. Data in binary form are entered at 5 to cause an oscillator 4 to produce triangular waves at one or another frequency (e.g. 1000 c/s. or 2200 c/s.). When line 8 receives a " Request Send " signal it starts the oscillator at its lower frequency, corresponding to a logical " 1 " with no input at 5. A filter 9 converts the triangular output to sine waves which go to a Line Driver Terminator 6 and thence to the line 3. The filter output is also taken via a limiter 10 to a Request to Send circuit 11 which turns-off the oscillator when all the data have been transmitted. At the receiver, a filter 20 eliminates noise outside the frequency band used, and the signals go to a limiter 21 and discriminator 22 giving a voltage output at the " 1 " or " 0 " level. A circuit 23 delays the output so that it can be determined whether the signals represent data or noise. A threshold circuit 25 rejects signals below a certain level and feeds a Clamp Timing circuit 26 with two time delays in series. The first delay turns off after one half-cycle of the lower transmitted frequency and the second (via the unit 23) clamps the output line 24 to the " 1 " level for 4 ms., thus rejecting noise of high amplitude but short duration during periods of no-data transmission and also the turn-on transients of the oscillator. Circuit 23 has a delay time which is longer than the first delay of circuit 26. The latter also supplies a monitor (not shown) via terminal 640 to show when line 24 is clamped. A Clear to Send circuit 7 is turned on by the Request Send signal on line 8. This energizes terminals 303, 308 which (by means not shown) prevent data from being applied to line 5 for a predetermined time until the oscillator has become stable. The delay means in circuit 26 of the remote receiver responds to the oscillator output " 1 " and prepares the receiver. Messages are arranged to begin with a logical " 0 ". Oscillator 4 (Fig. 2a).-Point 75 is switched between -12V and ground according as transistor 61 or 72 conducts. A potential divider 77, 78 applies a fraction of this voltage to the base of transistor 41, and an integrating circuit 81, 82 causes the base of transistor 40 to follow this more slowly. Thus when transistor 72 is turned on, transistor 41 will conduct as its base is positive, and transistor 50 will be off. After a time, the base voltage of transistor 40 will have risen sufficiently for it to conduct, and the current from a constant-current transistor 43 will thus divide between 40 and 41, which form a differential amplifier. The collector of 41 then becomes less negative and 50 conducts. This turns on transistor 60 which in turn switches on transistors 61 and 64, the latter switching off 72 and bringing point 75 to -12V. Transistor 41 is now cut off and the current from 43 is all diverted through 40. As the base potential of 40 falls, current starts to flow through 41 until 50 is turned off. Then transistors 60, 61 and 64 are cut off, switching on 72 to bring point 75 to ground potential. The potential divider 77, 78 limits the voltage swing at the base of 41 so that the amount by which capacitor 82 charges and discharges is held to about 12% of the possible range; this improves the linearity of the triangular waves produced. The oscillator frequency is changed by applying a negative signal at 5 to turn on transistor 103 and hence 113 also. This reverse biases diodes 98 and 101 and holds transistors 91 and 92 in a cut-off state. The latter are otherwise switched on and off in synchronism with transistors 61 and 72 respectively so that point 94 changes voltage in step with point 75 and adds a charging resistor 90 in parallel with resistor 81. The oscillator is stopped by a signal from transistor 144 in the Request to Send circuit (see below) which cuts off transistors 61, 72, 91 and 92 by forward biasing diodes 147-150. The oscillator may operate at frequencies of the order of 1-2 kc./s., e.g. 1000 c/s. and 2200 c/s. The output is taken from point 85 via an emitter follower 160 to the filter 9. It is arranged that the oscillator is always turned off at the same point in its cycle-see Request to Send circuit below. Filter 9 and Limiter 10 (Fig. 26).-Triangular waves from the oscillator 4 are passed to a shaping circuit comprising resistor 183 and diodes 178, 181 which converts them to sine waves as in Specification 1,123,079. The output is amplified by transistor 166 and taken to the limiter 10 which comprises a transistor 192 with shunt negative feedback operating like a single stage of the circuit of Specification 1,137,710. The limiter converts the sine waves to square waves which are passed to the Request to Send circuit 11 via a capacitor 200. The sine waves from the collector of transistor 166 go to the Line Driver Terminator 6 for outward transmission. Request to Send Circuit 11 (Fig. 2b). PNP and NPN transistors 130 and 131 form a bistable pair. A negative " turn-on " pulse at 8 is applied via diode 136 to turn on both transistors, thus turning-off transistor 144. The positive pulse at the collector of 144 (a) removes the forward bias from diodes 147-150 in the oscillator 4 and permits it to oscillate, and (b) passes via capacitor 650 to control the Line Clamp Timing Circuit 26 (see below). When line 8 returns to its positive level the bi-stable transistors are not turned off until a positive pulse is received from Limiter 10 via diode 140. This ensures that the oscillator is always turnedoff at the same point in its cycle, so that the switching transients are predictable. Line Driver Terminator 6 (Fig. 2c, not shown). This couples the transmission line 3 to the transmitter and the receiver, and is the same as in Specification 1,137,706. Clear to Send circuit 7 (Fig. 2c, not shown).- The input 8 which also energizes the Request to Send Circuit 11 is applied to a two-stage amplifier (270, 280), delay circuit (283, 284) and three further stages (290, 300, 304) to a " Clear to Send " Terminal 303, and its inverse 308. These hold-off the data input to terminal 5 until the oscillator has become stable. Band-pass Filter 20 (Fig. 2d).-Signals received from a remote transmitter pass through the Line Driver Terminator 6 to a lowpass filter 320-323 which rejects frequencies above 2500 c/s. The series inductor precedes the shunt capacitor 322 so that its resistance will merely be added to the input impedance and will not lower the Q of the circuit. After a two-stage amplifier 326, 331 with negative feedback through resistor 335 the signals pass through a high-pass filter 342-344 which rejects frequencies below 700 c/s. The wanted signals (1000 c/s. and 2200 c/s.) are then applied (a) through Limiter 21 to Discriminator 22, and (b) through Line Clamp Threshold 25 to the Line Clamp Timing Circuit 26. Limiter 21 (Fig. 2d).-This is a three-stage limiter as in Specification 1,137,710 to provide constant-amplitude square-wave signals for the Discriminator 22. Discriminator 22 (Figs. 2e, 2f, not shown).- This is as in Specification 1,137,707 and provides voltage levels representing " 1 " and " 0 " for the lower and higher input frequency signals respectively. Delay circuit 23 (Figs. 2g, 2h).-This is included between the Discriminator 22 and the data receiving equipment (not shown) attached to terminal 24. It delays the signals, long enough for the Line Clamp Timing circuit 26 to clamp the output when the signals represent noise instead of data. The circuit is as in Specification 1,137,708. Line Clamp Threshold Circuit 25 (Figs. 2e, 2f, not shown).-This is the same as the variablegain amplifier of Specification 1,137,709, the gain being low for small signals and high for large signals. The amplifier is followed by a Schmitt trigger to give an output only when the threshold is exceeded. Line Clamp Timing Circuit 26 (Figs. 2g, 2h).-Antiphase square waves from the Schmitt trigger of unit 25 are differentiated by 577/578 and 580/581 respectively and the spikes rectified by diodes 579, 582 so that transistor 585 receives negative spikes at twice the frequency of the input data signals. These spikes are passed via transistor 592 to a circuit 596/597 having a time constant of 1/2 ms. As long as signals are coming in, transistor 592 is turned on and off repetitively and capacitor 596 maintains a steady potential at the cathode of diode 601 to hold it off. When the signals cease, capacitor 596 discharges, diode 101 conducts and transistor 600 is cut off. This transistor is followed by a similar circuit 615/616 having a time constant of 4 ms. This time therefore elapses after the receipt of data before the clamp is removed from the output terminal 24 leading to the data processing apparatus, so that the circuit and line conditions become steady before data are recorded. When transistor 600 is turned-off, transistor 620 will be turned on after 4 ms. and will cut off transistor 626, applying a positive potential via diodes 629, 630 to turn off the bi-stable circuit 490/491 in the Delay Circuit 23. The reverse occurs when data are