Patent GB-1215283-A (GB)
Title: System for the selective operation of relays
Inventor: LUCAS PIERRE
IPC: H04Q3/545
Filed: 1969-01-08
Abstract: 1,215,283. Automatic exchange systems. P. LUCAS, C. ABRAHAM and R. FABRE. 8 Jan., 1969 [9 Jan., 1968], No. 1191/69. Heading H4K.  Relays are grouped to be operated or released selectively by associated group control circuits on command from one or other of two processors, the single winding of each relay having a centre tap connectable to earth over a selfholding contact with one end of the winding connected to battery while the other end is connected selectively by the associated group control circuit for the purpose of operating or releasing the relay, each group control circuit registering the order to connect or disconnect and the identity of the relay involved in order to establish a unique path to the relay, a timing function being started to be cancelled by correct execution of an order or to establish an alarm condition if, within a time limit, the order has not been carried out. The group control circuits are referred to as signal distributors and one such distributor is associated with each of 48 groups of 16 relays each. One such distributor 10 and associated relay group 20 is shown in Fig. 2, each processor having individual access to the distributor over a switching circuit 2. A seizing circuit 100 in each distributor has a terminal circuit for each processor. When a processor compiles an order to control a relay it sends a reservation signal to its terminal circuit in the appropriate distributor and receives in return an availability signal, if the distributor is free. The distributor busies itself against intrusion from the other processor and receives a seizing signal along with the control order (connect or disconnect), the address of the relay, and a parity bit. The seizing signal precipitates a three stage process in which the distributor is first set to normal; secondly the relay address is gated to control circuits 400, the control order is gated to order register 300, and the parity bit is gated to fault circuit 700; while thirdly and providing the parity check is successful an eight stage sequence circuit termed a programmer is started to supervise implementation of the order. If the parity check fails, a fault signal is sent back to the processor. A warning circuit 800 including a slow-to-release relay, if not reset at least 30 milliseconds after seizure of the distributor produces an alrm condition to indicate that the programmer has failed to proceed with the order. The relay address comprises two co-ordinate portions which are separately decoded to operate one out of a group of q reed relays and one out of a group of r reed relays. The group of r relays has contacts which select sets of contacts in a relay tree. The group of q relays prepare an operate path for one of a corresponding group of relays having contacts in each of the sets of the relay tree chosen by the r groups relays, Fig. 7, not shown. The programmer confirms operation of one of the group of q relays before advancing to operate the corresponding relay in the corresponding group in the contact tree, and confirms operation of that relay also before advancing to obtain the order, connect or disconnect, from register 300. The relay to be controlled is now connected through the control circuit 400 to a test circuit 500 via which the relay is earthed (to operate) or connected to battery (to release), and correct operation is signalled to a test analysis circuit 600. The test circuit 500 is shown in Fig. 8, where an order to connect appears as a potential on terminal 57 causing transistor 512 to cut-off, 511 to switch on and connect earth over diode 522 to terminal 56 to which the selected relay is connected over circuit 400. The current drawn over diode 522 switches transistor 521 to conduction and cuts off 523 to signal over terminal 59 the successful application of operate current. When the selected relay operates it completes its hold circuit and the diode 522 ceases to take current. This change of condition is relayed over the terminal 59 to the test analysis circuit 600 which recognizes completion of the order and signals the programmer to advance. If a delay circuit 900, a counting circuit in fact, times out a period within which relay response should occur but has not been detected, the fault circuit 700 is signalled to report back to the processor which sets about releasing the distributor. A disconnect order is similarly effected; a signal on terminal 58 cutting off 533 to switch on 534 and 531 whereby battery is connected to terminal 56. Current in the circuit switches off 541 to switch on 543 and 544 to signal application of release current and by cessation of such current to signal, release of the relay to the analysis circuit 600. Circuit 600, when satisfied that the order is effected, advances the programmer to proceed to a phase in which the distributer is reset to make it available for the receipt of further orders. By using a number of decorders and corresponding groups of r relays in the relay contact trees of the control circuits 400, more than one relay in a group 20 can be operated in response to a single order.