Patent GB-1329927-A (GB)
Title: Digital video receivers
IPC: H04N7/34
Filed: 1972-06-20
Abstract: 1329927 Display WESTERN ELECTRIC CO Inc 20 June 1972 [25 June 1971] 28724/72 Heading H4F  In a digital video receiver for an n-bit pulse coded modulation video signal, the displayed light intensity on the display cathode ray tube is linearly related to the amplitude of the decoded video signal, the display being a "half tone" type produced by gating a constant intensity linearly scanned electron beam with variable duty cycle pulses, the duty cycle being varied in successive Nyquist intervals according to the decoded value of the corresponding successive n-bit video signal words. The necessity for gamma correction is thus removed. The receiver shown in assembled Figs. 1, 2, 3 is designed to receive two modes of coded video information: (a) Where the amplitude of every video sample (lasting a Nyquist interval) is expressed as a 7-bit binary coded word at 14 Mb/s. (b) Where the samples are expressed as successive 3-bit binary coded differentially pulse coded modulation words at 6 Mb/s. The serial to parallel converter for mode (a) is shown in Fig. 2, whilst a 3-bit to 7-bit, serial to parallel converter for mode (b) is shown in Fig. 1. A detector 11 detects which mode is operative and accordingly enables gates 59, 52/  58 for mode (a) and gates 61, 62/68 for mode (b). For mode (a) assume two successive words a 1  (0001100) and a 2  (0001110). The frame and sync. bits of the words are detected at 14 and used, by means of 14 MHz clock 15 and "by 7" divider 16, to give signals alternately switching over shift register stores 12 and 13 from read-in to readout and vice versa. Word a 1  is thus serially read into register 12 using the shift pulses from clock 15, whilst the previous word is read out in parallel from register 13. Word a 2  is then read into register 13 and word a 1  read out in parallel via enabled gates 22/28, OR gates 42/48, enabled gates 52/58 and further OR gates to a set of multi-input AND gates 101/107. A phase locked clock 60 produces a train of trigger pulses at such that the tandem connected bi-stable circuits, 71, 72, 73, 74, 75, 76, 77 each go through 2<SP>6</SP>, 2<SP>5</SP>, 2<SP>4</SP>, 2<SP>3</SP>, 2<SP>2</SP>, 2, 1 cycles respectively, e.g. see Fig. 5, in the Nyquist interval, during which the word a 1  (0001100), presents a 1 at gates, 104, and 105. The pulse trains presented to gate 104 are shown in Fig. 5 whence 8 pulses per Nyquist interval are produced and the pulse trains presented to gate 105 are shown in Fig. 6 whence 16 pulses per Nyquist interval are produced. These pulses sum in OR gate 108 to give 24 pulses which are converted to electron beam gating pulses by monopulse circuit 109. In the next Nyquist interval, word a 2  causes enablement of gates 104, 105, 106 such that a total of 56, (8 + 16 + 32), gating pulses are fed to the cathode ray tube, giving a correspondingly brighter spot. For mode (b), registers 112 and 113 act in a similar manner to register 12 and 13, alternately reading in and reading out. The read out parallel 3-bit differential words are converted to 7-bit parallel words in accumulator 110. Instead of increasing the number of unit width pulses per Nyquist interval to increase displayed brightness, only one gating pulse per interval may be used, of variable width. For this (Fig. 8, not shown), gates 101/107 are replaced by logic gates having the truth table: Whereby only one of these gates produces a pulse in any one interval at a position within the interval such that by using it to reset a bi-stable, set by a start of interval signal, the variable width gating pulse is produced.