Patent GB-1317213-A (GB)
Title: Analog computer
IPC: G06G7/75
Filed: 1970-07-09
Abstract: 1317213 Optimizing computers FIRESTONE TIRE & RUBBER CO 9 July 1970 [10 July 1969] 33488/70 Heading G4G An analogue computer for evaluating a function of several variables comprises means for generating voltages corresponding to the variables and multiplying means for multiplying these voltages by fixed voltages representing constant coefficients, the variable generators being in the form of integrators of adjustable ramp rate the output of which is determined by the closure of a switch in the input circuit which establishes a "hold" condition. As described, the invention is applied to the evaluation of a property or response Y A  of a rubber blend having variable ingredients, e.g. x 1 , x 2 , whose influences are known and uniquely determined for the particular response and are represented by "influence" coefficients a in the equation for the response: The equation contains linear, curvature and interaction terms, all with appropriate coefficients. Other responses Y B ,Y C  ... for the same ingredients may be respresented by similar equations with the same variables but different influence coefficients, and the number of ingredients may exceed two. Thus, for eight different responses Y A  ... Y H  dependent upon n ingredients we have the array of equations: where i, j run through 1 to n. In the equations, the responses Y A  &c. are the deviations from "standard" (or expected) responses a 0  &c. and the coefficients a may therefore be either positive or negative. The variables are the same for all the equations and are generated in n ramp generators the outputs of which are fed to eight coefficient potentiometer arrays in each of which the variables are multiplied by influence coefficients appropriate to a particular response. These arrays also contain multiplying and squaring circuits for forming the variable parts of the second order terms. The positive and negative terms of each equation are fed to respective bus-bars, and the voltages on the bus-bars screened to give the response Y. The various responses Y may be fed, e.g. in pairs, to a visual display which facilitates convergence to desired values by manual adjustment of the variables (Fig. 2, not shown). The generator for a single ingredient variable is shown in Fig. 4 and consists of a ramp generator (integrator) 23 fed either from its own constant voltage source through potentiometer 29 or from a voltage source common to the n-generators through a potentiometer 47. These potentiometers determine the ramp rate. The integrated voltage rises from a negative to a positive value and is fed to a comparator 36 which also receives a voltage from potentiometer 40 determining the upper limit of the ramp. A switch 35 enables the integrator to be re-set manually or automatically upon attainment of the upper limit. The lower limit is determined by the potentiometer 32. The input of the ramp generator also includes a HOLD switch which may be operated from the output unit 5 through a variety of logic circuits whenever one value of Y or a chosen combination of values of Y lie between certain limits. To this end, a value, e.g. Y C  may be fed to a pair of comparators 131, 133, Fig. 5 which operate switches 132, 134 and cause a lamp 148 to light whenever Y C  lies within the chosen limits. The acceptable value Y C <SP>1</SP> may be fed together with acceptable values of other chosen responses Y<SP>1</SP> to a logic circuit which incorporates an AND channel and causes energization of the HOLD switches in the function generators whenever a chosen number of responses are simultaneously between the limits. The outputs of the integrators may be fed to a cyclical switch (Fig. 7, not shown) which, in the HOLD condition, connects each one in turn to a recording voltmeter. The logic circuit may also include two OR channels which can be set to specify alternative combinations of Y for the HOLD condition. Thus, for example, if all eight responses Y A  ... Y H  do not lie within the required range, two other more restricted combinations may be applied. The complete automatic search combination in logic rotation could be, e.g. In addition, the logic circuitry may contain three special high-low limit channels which cause operation of the HOLD switch whenever three chosen responses Y have values U, V, W lying within relaxed limits. The lower half of Fig. 5 shows a selector 192 for applying a chosen output Y to comparators 193, 194 which determine the relaxed limits. The signal U is applied together with signals V, W to an AND circuit 201 which responds to U.V.W or (with the aid of manual switches) to any of the combinations U.V+W, U+V.W, U.W+V, U + V + W. The logic modules are provided with inhibit switches which prevent the integrators from going to HOLD even though the relevant conditions are satisfied, whereby further search may proceed under these conditions. In the automatic search condition using common ramp rate potentiometer 47 for, e.g. five integrators (five variables), the ramp rate for x 4  is set five times faster than the rate for x 5 , the rate for x 3  five times faster than the rate for x 4  and so on, this beingdone by choiceofresistors 49. This causes a successive sweeping of all the ramp voltages to provide all combinations of x 1  ... x 5 . Fig. 9 shows an automatic search circuit in which a perturbing signal repeatedly applied to the integrators in order to adjust the variables x to produce a desired response Y. The circuit is mainly confined to the integrator for x 1  and the integrator 22 for this variable is shown connected in normal fastion to the coefficient potentiometer array 3. During search, the switch 223 is changed over whereby integrator 22 is connected to the potentiometer array 3 through two unit-gain inverting amplifiers 225, 226 which leave the output of the integrator unchanged. To set up the circuit, an additional (calibration) potentiometer in the array 3 is adjusted until a desired response Y is obtained at the output of amplifier 228. Potentiometer 229 is adjusted to bring this output to zero. If now the calibration potentiometer is removed, the output of amplifier 228 will indicate the error E or difference between the actual and desired values of Y. The rest of circuit 236 A is designed to generate the absolute error multiplied by an arbitrary weighting factor W so that the output on line 240 is |WE|. The sum of the errors generated by all variables x is further weighted by amplifier 241 and # |WE| is differentiated in circuit 247. A comparator 248 determines the sign of the derivative and closes relay contacts 248A, 248B if the error is decreasing. A square-wave perturbing signal generated by circuit 258 is fed throughout the search to the amplifiers 226 in the x generators 222 by the scanning switch 252. The same scanning switch supplies the perturbing signal to the inputs of the x integrators 22, 57, 58, 59, 60, but only during those periods when the error is decreasing (contacts 248A closed). The integrators (which operate in the HOLD mode between pulses) can therefore only operate to change the output value in a sense which will decrease the absolute error in Y. The minimum error is fed through contacts 248B to a readout circuit 245. The Fig. 9 circuit may be used to automatically adjust x i  for a constant Y whilst another variable x j  is manually varied. The two x values may be fed to an XY plotter to produce an equal-response contour.