Patent GB-1105583-A (GB)
Title: Error detection and/or correction of digital information
Inventor: HELM HARRY ARTHUR
IPC: H04L1/00
Filed: 1965-02-26
Abstract: 1,105,583. Error checking and correcting arrangements. WESTERN ELECTRIC CO. Ltd. 20 Feb., 1965, No. 50583/67. Divided out of 1,105,581. Heading G4A. An error detecting and correcting system for data transmission comprises means for generating for the data characters of a message two check characters, each check character being generated by an interative operation on the data characters, means at the receiver for operating on the received data and check character to produce two corresponding error characters and means for operating on the respective error characters so that if identical outputs are produced by the operating means an error correction is effected. The system is such that all single character errors in a message can be corrected and all double and most multiple errors exceeding two can be detected. The operation of the system depends on the particular properties of the Bose-Chaudhari " codes employed therein. At the transmitter, Fig. 1, a message to be transmitted consisting of any number up to a predetermined number of characters dependent on the particular code employed is applied via a commutator 12 to transmitting equipment 112 and to two linear sequential networks 17, 18 which each perform iterative operations and consist only of storage elements, gates and modulo-2 adders, the networks 17, 18 being effective to calculate two check characters Y1, Y2 which are appended by the Commutator 12 to the data characters for transmission by the equipment 112. The network 17 is effective to add, modulo-2, each successive code character applied thereto to the previous output of the network transformed by a linear operation A, (suitable circuits for 4-digit characters being shown in Figs. 3A, 3B, 5A, 5B, not shown). The network 18 is generally similar but performs the linear operation A<SP>2</SP>. At the receiver, Fig. 2, the incoming data characters are applied to a shift register 29 and to networks 31, 33 identical to the networks 17, 18 and effective to calculate check characters Y1, Y2 for the received data. The received check characters Y<SP>1</SP> 1 , Y<SP>1</SP> 2 , are then added modulo-2 to the corresponding recalculated check character Y 1 , Y 2 , the sum being zero if no transmission errors have occurred. If there is an error in the i'th character, the sums are non-zero and this is detected at 39 to produce an error signal. It it shown in the Specification that the values of these sums uniquely determine in the case of a single data character being in error, both the location of the erroneous character and the amount of error therein. For this purpose respective sums are applied to linear sequential networks 37, 38 which perform the inverse linear operations to networks 31, 33. The iterative operations of the networks 37, 38 are performed in synchronism with the stepping out in reverse order of the data characters from an output shift register 41, a comparator 239 detecting when the outputs of network 37, 38 are equal, this output being the amount of error in the character then being stepped out of the shift register 41. The erroneous character is corrected by the modulo-2 addition at 243 of the output of the network 37, an error indicating circuit 47 being reset since an error has been corrected. In the ease of multiple errors equality is never detected at 239 and the circuit 47 is not reset. If one of the received check characters is in error and not a data character, the output of one of networks 31, 33 is zero and the output of the other is the amount of the error. In a modification (Fig. 6, not shown) means are provided to correct and retransmit the check characters is well as the data characters.