Patent GB-1476251-A (GB)
Title: Multiplexed data modem
IPC: H04L27/233
Filed: 1974-05-09
Abstract: 1476251 Twinplex systems; telegraphy MILGO ELECTRONIC CORP 9 May 1974 [10 May 1973] 20476/74 Headings H4M and H4P In a method of transmitting digital data from two independent data sources via a single transmission link to a receiver having two data utilization devices, the data bits from each source are received by the transmitter in n bit groups and combined to form serial groups of 2n bits, each serial group being grouped into two equal length sub-groups each of which is encoded. A single carrier oscillation is modulated for transmission, in accordance with the encoded sub-groups, in successive modulation intervals either as differential phase modulation or as a combined differential phase modulation and amplitude modulation. One of the subgroups of each pair is identified by a predetermined extra phase shift of the carrier. During demodulation at the receiver, the extra predetermined phase shift is detected and compensated for, so that the sub-groups can be separated. At the transmitter (Fig. 4) data streams A and B are fed to three stage shift registers 32, 34 from which groups of three consecutive bits are transferred at intervals via a transfer gate 33 to a six bit shift register 36 in an interleaved manner. The contents of register 36 are fed serially to set the flip-flops 48, 46, 44. The contents of the flip-flops 48, 46 are combined through a set of logic gates 52-60 and used to set either the 90 or 180 degree stage or both of a binary adder 68 in accordance with the particular binary word stored in 48, 46. Flip-flop 44 controls an amplitude modulator 62; thus the three bits in the flip-flops 44-48 will be represented by the phase and amplitude of the transmitted signal. The transmitted signal is delivered from frequency translator 83 which divides it to a frequency suitable for transmission over telephone lines. The binary adder 68 receives inputs from storage registers 70 representing the phase of the the preceding transmitted signal and also incorporates a 45 degree stage controlled from the clock to the system, suitably divided down to provide a pulse for each alternate group of three digits, so that a 45 degree phase shift will be added to identify these. The output from the adder 68, representing in binary sum from the required phase angle for the signals to be transmitted is applied to a logic circuit 74 controlling a phase shifting circuit 76 which operates on the output from an oscillator 80. Synchronism is established by using this oscillator to enable a multivibrator 82 operated from a divided clock signal and used to control the logic gates 74 and ultimately the sampling rate from the flip-flops 48-44. At the receiver (Fig. 6) signals received at an input terminal 84 are applied to a frequency translator and squaring circuit 86 which operates in accordance with a high frequency clock from a source 90 and provides an output controlling a derived clock and timing control 94. The clock source 90 also controls a high speed binary counter which has output stages 104d, 104c, 104b, 104a corresponding to 180, 90, 45 and 22À5 degree phase angles respectively, the first two, 104d, 104c controlling a register 108. Other counter stages corresponding to smaller angle increments are included. The counter output is advanced or retarded to phase lock it to the received data signals applied to the gate 92 from circuit 86 and to the 45 degree phase angle additions for each alternate transmitted signal from appropriately controlled circuit 140. Should this circuit apply the 45 degree addition in the wrong phase, this situation is detected by comparing the outputs from the gates 92 and 130 (comparing the derived clock 9 and 48 degree addition) to determine whether flip-flop 132 is operated repetitively. If it is the phase condition is wrong, circuitry 142-154 detects repetitive operation of the flip-flop 132 and acts to change the phase of the clock applied to the circuit 140. The presently received, appropriately corrected binary signals representing the present phase shift are stored by register 108 and compared with the immediate past signals held in register 110 by subtractor 112. The output from this, representing the differential phase shift, is fed to logic decoding circuit 118, together with the output from level detector 88 to which the input at 84 is applied. By means of appropriate registers and gating circuitry, the two original independent data signals are recovered from the decoded sequence.