Patent GB-1003921-A (GB)
Title: Computer cycling and control system
IPC: G06F9/38
Filed: 1962-02-26
Abstract: 1,003,921. Electronic digital computers. SPERRY RAND CORPORATION. Feb. 26, 1962 [March 24, 1961], No. 7406/62. Heading G4A. Instructions called up in sequence from memory are passed to an instruction register capable of containing more than one instruction, so that the calling up of operands, modification of addresses, and other operations involved in the carrying out of instructions, may take place in respect of some instructions, while another has the use of the arithmetic unit. Fig. 1 shows schematically the arrangement for a parallel mode computer in which data and instructions words consist of 12 binary-coded decimal digits. Five digits (M) specify the memory address of an operand, two (B) one of a hundred registers used as a modifier, two (A) one of the registers regarded as an accumulator, and two (I) one of a hundred instructions. Simple instructions (e.g. involving addition) take one minor cycle to execute (not counting the time taken in " preliminaries " while the arithmetic operations of earlier instructions are being carried out), each minor cycle comprising eight bit periods. Normally, therefore, instructions are withdrawn from memory over a highspeed bus HSB at each minor cycle, and registered in IR1. The address of the instructions are derived from the contents of instruction counter 104, which is read out into B-adder 139 and returned, increased by one, as well as addressing the memory via decoder 141. The B digits are sent to register 118 to select the modifier. In the next minor cycle the instruction in IR1 is transferred to IR2, a second instruction register constituted by 107, 107a and and 108, the M digits being sent to the B-adder and modified by addition of the last five digits of the contents of the register previously selected and fed to the B-adder via gate 133; this modified address is also sent to 141 to select the operand. IR1 is cleared, the instruction number N in 104 is updated and sent to 141 for reading the next instruction into IR1. In the next minor cycle the I digits of the first instruction are transferred from 107 to 109, where they act through 148 to produce the necessary signals (shown encircled) for controlling gates (some of which are shown in Fig. 1); they also through encoder 110 provide the necessary control signals for the arithmetic unit 131. The A digits are sent via the B-adder and gate 115 to the register selector 118, and the contents of the selected A-rogister is sent to the arithmetic unit together with the selected memory word. The A-register number is also sent to register 113; this is so that if the next instruction requires the contents of the same A-register, the calling-up of this may be delayed until the new operand is available, comparison being effected by unit 142 which through 148 produces the necessary signals for this " holdup." If no " hold-up " is necessary the second instruction is transferred to IR2 and the third called up to IR1; however, delay may occur at this point if the arithmetic operation requires more than one minor cycle for its implementation, and in this case further call-up of instructions is deferred. However, on completion of the arithmetic operation what is described as " full overlap " is resumed; in a further minor cycle the result of the calculation on the first instruction is sent to the A-register specified by register 113, the second instruction controls the arithmetic unit, the third is modified by the B-adder and transferred to IR2, and a fourth read into IR1. In the event of the result of the first calculation being required as an operand for the second instruction, it is also fed directly back to the arithmetic unit. Double length working is possible for greater precision, in this case the half words are handled by the arithmetic unit in turn, and the operation is described in detail. In the case of jump instructions, these when recognized from 107 cause the contents of 108 to be routed via the B-adder to instruction counter 106. Previous instructions are completed, and the following instruction is cleared from IR1 if the jump is unconditional; the contents of 104 and 106 are then interchanged so that a new sequence of instructions addressed by 104 commences. If the jump is a conditional one, new instructions in the original sequence continue to be called up until the test for jump is completed, when if it takes place some delay will occur before the new sequence of instructions replaces the original sequence ones not now required. The modification of the modifier used in adding to the M-digits in the B-adder before calling up an instruction for indexing purposes is described. Logical circuits for all the major units are described and shown schematically; the memory is built up from units each comprising a magnetic core matrix with 60 planes (one for each bit of word) and 50 x 50 word positions. Specifications 769,384, 933,066, 986,148 and 1,003,923 are referred to.