Patent GB-978657-A (GB)
Title: Data processing system
IPC: G06F11/10
Filed: 1962-05-29
Abstract: 978, 657. Computing check symbols. RADIO CORPORATION OF AMERICA. May 29, 1962 [May 31, 1961], No. 20661/62. Heading G4A. A computer comprises means for generating a parity bit during the transmission of a word in parallel along a bus. The necessity for separate parity generators in various subsystems of the computer is thus obviated and the arrangement is also of use in masking and merging operations. The arrangement described comprises a high speed core matrix memory 30 having an address register 38 and an input-output register 44, an arithmetic unit 94, a program sequence generator 32, an instruction register 50, a parity generator 60 and various other units. Data is transmitted in the form of words composed of 28 binary bits in parallel, each word comprising nine 3-bit octal characters and one parity bit. An instruction comprises a plurality of words, the first word including 24 bits representing an operation, 3 "tag" bits whose function is not described, and a parity bit, subsequent words of the instruction each containing (i) a 19-bit memory address, together with (ii) eight index bits for address modification and (iii) a word parity bit. In operation, the sequence generator 32 addresses the memory 30 via a decoder 42, the addressed word being read out via the register 44 to the instruction register 50, an instruction decoder 52 producing "machine instructions" for the various units in the computer. The sequence generator 32 addresses another word, generally the next in sequence, in the memory 30, thereby causing to be read out the second word of the instruction, which comprises a 19-bit address partial word and an 8-bit index partial word. This second word which has its parity bit removed by gates 46, is applied via a bus 48 to gates 58 to which are connected a mask generator 62 which inhibits certain of the gates so that only the 19-bit address partial word is applied to the parity generator 60. The resulting address parity bit plus the 19-bit address is applied over a 20-conductor bus 64 to an X address register 54, the eight index bits of the second instruction word being applied to an X index register 56 connected to an index control circuit 70 which produces machine instructions for the arithmetic unit 94. The third instruction word is similarly treated and causes an address to be supplied to a Y address register 76, index bits being supplied to a Y index register 86. The above operations form a "load machine" routine, which is followed by an "execute instruction" routine in which X and Y address registers 54, 76 address the memory for data operands. In one type of instruction, a succession of operations, e.g. additions, may be performed by modifying the addresses in the register 54, 76 by means of an address modifier 99. Another type of instruction may require the contents of the X address register 54 to be combined with the 8 bit contents of a "Q register" (bottom left of Fig. 1), the contents of the register 54 being supplied via gates 98 which cancel the parity bit, to the first nineteen wires of the bus 48. Simultaneously, the contents of the Q register is applied to the next eight wires of the bus 48, and the parity generator 60 generates the correct parity bit on the 28th wire of the bus 48, the complete 28-bit word being passed via gates 96 to the memory register 44. The data transmission buses have sufficient individual wires to transmit data simultaneously in true and complement form. The parity generator 60 (Figs. 4-7, not shown), comprises a treearrangement of "none" gates. Specification 977,317 is referred to.