baber/WOPTO huggingface dataset:
Patent JP-H01204176-A (JP)
Title: Program input system for betting machine and program input switch mechanism used to said input system
Inventor: OHASHI YUJI
IPC: G06Q50/34
Filed: 1988-02-09
Abstract: PURPOSE:To ensure the highly efficient sale of tickets by displaying betting enable programs and also completing a program input action just with a single switch operation. CONSTITUTION:A switch input means 1 consists of plural switches corresponding in 1:1 to all programs and a switch display means 2 displays switches corresponding in 1:1 to each of the switches forming the means 1. Furthermore, a switch control means 3 controls the switches so as to change dynamically the display of the means 2 and at the same time decides the acceptance of input information given from the means 1. As a result, the purchasable programs are discriminated from the unpurchasable programs for each switch of the means 1 for display. Thus the input of the unpurchasable programs are avoided and at the same time the input of a program is possible just with a single switch operation. Then the tickets are sold with high efficiency.
Patent JP-S59153641-A (JP)
Title: Sound reproduction device mounted on car
Inventor: ISHIKAWA SEIICHI
IPC: B60R11/02
Filed: 1983-02-21
Abstract: PURPOSE:To realize listening to always well-balanced reproduced musical sound by letting at least a signal in low compass of musical signal make automatic adjustment and amplification correspondingly to a traveling speed of a car and engine speed. CONSTITUTION:Parallel circuit of HPF5 and LPF6 is interposed between a deck 1 and a tone quality adjustment amplifier 2 of the captioned device which sends out a musical signal reproduced by a cassette tape deck 1 to a speaker 4 through the tone quality adjustment amplifier 2 and an electric power amplifier 3. An automatic amplification degree controller 10 is connected in series to LPF6. Electric signals from electric circuits 7, 8 detecting an engine speed and traveling speed of a car are inputted to an adder 9 through amplifiers 11, 12, and an automatic amplification degree controller 9 is controlled according to d.c. voltage added here. To be exact, in case the engine speed and car speed are raised, control is made so as to raise the amplification degree of the signal in low compass of the musical signal according to a condition of operation at that time.
Patent JP-H02245029-A (JP)
Title: New polyimide-siloxane and its manufacture
Inventor: CHIYUN JIEI RII
IPC: C08J5/18
Filed: 1990-02-07
Abstract: PURPOSE: To obtain a polyimidesiloxane excellent in dissolution characteristics and a balance between heat resistance and the upper limit service temperature and useful for electronic components such as integrated circuits by selecting a reaction product among an organic acid dianhydride, a difunctional siloxane monomer and an aromatic diamine.  
     CONSTITUTION: This polyimidesiloxane is a perfectly imidized reaction product among an organic acid dianhydride (e.g. 4,4'-oxydiphthalic anhydride), a difunctional siloxane monomer (e.g. α,ω-diaminopolysiloxane represented by formula II (wherein R's, which are independent of each other, are 1-12C divalent aliphatic groups; R 1  to R 4 , which are independent of each other, are 1-12C monovalent aliphatic groups, 6-10C aromatic monovalent groups, vinyl groups, hydroxyl groups or the like)) and an aromatic diamine represented by formula I (wherein X is H, a halogen or a phenyl); Z is -O-, -S-, -SO 2 -, =CO, =C(CX 3 ) 2  or a single bond; and Ar' is a 6-10C aromatic group) (e.g. 2,5- diaminobenzotrifluoride). 
     COPYRIGHT: (C)1990,JPO
Patent JP-H04211089-A (JP)
Title: Condensed thiazole compound
Inventor: AONO TETSUYA
IPC: A61P25/28
Filed: 1991-02-22
Abstract: PURPOSE:To provide a novel condensed thiazole compound having a lipoperoxide production-inhibiting activity and a lopoxygenase-inhibiting activity and useful as an agent for preventing and treating diseases such as cancers, arterial sclerosis, hepatic diseases, cerebrovascular disorders, inflammation, etc. CONSTITUTION:A compound of formula I (A is a bond, CH2; R<1> is H, aliphatic group, the acyl group of a carboxylic acid, the acyl group of a sulfonic acid; R<2> is H, aromatic group or aliphatic group) [e.g. 3-(2,3-dimethoxycinnamoyl) amino-delta-valerolactam] is reacted with a sulfide compound such as phosphorus pentasulfide, and the reaction product is, if necessary, subjected to the conversion reaction of R<1> to provide the objective condensed thiazole compound of formula II [e.g. 2-(2,3-dimethylstyryl)-4,5,6,7-tetrahydrothiazolo[5,4-b]pyridine].
Patent JP-2000226447-A (JP)
Title: Production of copolyester
Inventor: KIMURA HISASHI
IPC: C08G63/78
Filed: 1999-02-05
Abstract: PROBLEM TO BE SOLVED: To provide a process for producing polyesters copolymerized with phenylenedioxydiacetic acid which is an effective dicarboxylic acid component for improving the gas barrier properties of polyethylene terephthalate with a good industrial productivity and in accordance with the charge ratio of the phenylenedioxydiacetic acid. SOLUTION: In the process for producing copolyesters by using a feedstock containing terephthalic acid, phenylenedioxydiacetic acid and ethylene glycol, a feedstock slurry obtained by adding the phenylenedioxydiacetic acid to a slurry in which the terephthalic acid has been dispersed in the ethylene glycol to form a slurry is subjected to an esterification reaction and polymerized by a successive polycondensation reaction.
Patent JP-S61188947-A (JP)
Title: Wiring forming method of semiconductor device
Inventor: HORI MINORU
IPC: H01L21/302
Filed: 1985-02-18
Abstract: PURPOSE:To form wirings of high reliability by forming a double layer made of polysilicon of lower layer and metal of upper layer to become a wiring layer on a substrate, and patterning the metal by an isotropic etching and polysilicon an anisotropic etching. CONSTITUTION:A substrate 4 in which a contacting hole is opened is prepared at the desired position. Then, a double layer made of polysilicon of lower layer 5b and aluminum or aluminum alloy of upper layer 5a to become a wiring layer 5 is formed on the substrate 4. A patterning for wiring is then performed, the aluminum or aluminum alloy of the layer 5a not placed with a photoresist film is then isotropically etched by phosphoric acid, and the polysilicon of layer 5a of the position not placed with a photoresist film is anisotropically etched. Thereafter, the photoresist film is removed, and after the patterning is finished, a protective insulating film 3 is formed by a CVD method and the like.
Patent JP-S58146305-A (JP)
Inventor: INAGAKI TADAAKI
IPC: A43C9/00
Filed: 1982-02-24
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63196527-A (JP)
Title: Production of inner olefin
Inventor: SUZUKAMO TAKEO
IPC: C07C5/25
Filed: 1987-02-10
Abstract: PURPOSE:To improve catalytic activity and to obtain the aimed compound with a small amount of catalyst and efficiently in producing a stable inner olefin, by isomerizing an olefin, by using a solid basic catalyst obtained by treating alumina with an alkali metal at a specific temperature. CONSTITUTION:In producing a stable inner olefin by isomerizing the double bond of olefin, hydrous alumina especially hydrous alumina of gamma-, x- rho-type having large surface area is heat-treated with >=equivalent based on water mol amount of the alumina, preferably 1.01-2 equivalents based on the alumina of an alkali metal in an inert gas atmosphere at 180-350 deg.C, preferably 200-300 deg.C to give a solid basic catalyst. The solid basic catalyst is used and the aimed compound is obtained with an extremely smaller amount of catalyst than by a conventional procedure, in a remarkably high efficiency, in high yield, safely, industrially and advantageously without causing by-products such as polymers, etc., and danger such as ignition, etc.
Patent JP-S62187544-A (JP)
Title: Method for housing core into metallic mold for casting
Inventor: OIKAWA KEIICHI
IPC: B22C9/10
Filed: 1986-02-12
Abstract: PURPOSE:To maintain the dimensional accuracy of a core formed with notches in a core print part and to eliminate the generation of flash as well as to improve productivity by imposing the above-mentioned core on a lower mold, mating an upper mold with the core print part deformed by the heat of the metallic mold and dividing the core to the plural cores from the notches thereby decreasing the rate of deformation. CONSTITUTION:The core 14 supported to the core print part 18 having the notches 12 is imposed on the lower mold 15 based on a projection 19 thereof. The mold 15 is kept heated during a casting operation stage and the core print part 18 is deformed and warped by the heat thereof. The upper mold 16 together with a horizontal core 17 is then mated with the mold 15 and when the molds are closed, the core print part 19 is pressed by the top surface of the space part 21 of the core 17 and therefore, the deformed parts are corrected and bending stresses are concentrated to the notches 12. Cracks are, therefore, generated in the notches 12 and the core print part 18 is broken from the notches 12. The thermal deformation is thus decreased in the individual core print parts 18 and since the clearance S' in the space part 21 for housing the core print parts 18 is small, the flashing of the product is prevented.
Patent JP-S63195877-A (JP)
Title: Data recording and reproducing system
Inventor: HIRANO HIROYUKI
IPC: G11B20/18
Filed: 1987-02-10
Abstract: PURPOSE:To make data recording efficient by rerecording data having errors more than a reference value in a recording medium after completing the recording of a series of data. CONSTITUTION:Recording data outputted from a host computer 2 are inputted to a driving device 1 through an adaptor 3 and recorded in an optical disk 21. After ending the recording of data for one sector, the data are verified and checked and its error is checked by an error correcting circuit 17. When the error exceeds the reference value, data stored in a buffer memory 32 are transferred and recorded to/in an external memory 33 without executing retrying operation. After ending the recording of a series of data, the data stored in the memory 33 are stored in a buffer memory 14, rerecorded in an optical disk 21 and verified and read out.
Patent JP-S53114496-A (JP)
Title: Gas detecting element
Inventor: KUBOTA KAZUNARI
IPC: G01N27/16
Filed: 1977-03-16
Abstract: PURPOSE: To improve the drawback of low oxidation activity of Pt catalyst and enlarge bridge output by adding W as co-catalyst to Pt catalyst for gas detecting element in a catalytic combustion system heat wire type gas detecting device. 
     COPYRIGHT: (C)1978,JPO&Japio
Patent JP-H09221938-A (JP)
Title: Air intake and exhaust system of building
Inventor: ARIMA YUJI
IPC: E04H12/28
Filed: 1996-02-16
Abstract: PROBLEM TO BE SOLVED: To provide housing air intake and exhaust system excellent in ventilation efficiency of a housing even while having simple and economical construction, capable of lowering noises caused by air intake and making it possible to control the leakage of noises in the housing to the outside. SOLUTION: An upper side joint section 4 connecting between an upper space of a housing 1 and an intake space of an external cylinder body 7 is provided to a smokestack 3 provided to the housing 1 having a combustion device therein and having an internal cylinder body 8 exhausting combusted exhaust-gas from the combustion device 2 inside the external cylinder body 7. Then, a lower side joint section 5 jointly connecting between a lower space of the housing 1 and the inside space of the external cylinder body 7 is provided, and an opening section 6 linking the inside of the external cylinder body 7 with the atmosphere is provided to the lower part of the external cylinder body 7.  Then, a partition wall 10 dividing a space between the external cylinder body 7 and internal cylinder body 8 into up and down parts is so provided that it is positioned downward from the upper joint section 4 and that it is positioned upward from the lower side joint section 5 and opening section 6.
Patent JP-S60171741-A (JP)
Title: Manufacture of semiconductor device
Inventor: KURITA KAZUYUKI
IPC: H01L21/3205
Filed: 1984-02-17
Abstract: PURPOSE:To reduce danger of generation of disconnection of a metal wiring at the upper layer of a semiconductor device by a method wherein a second interlayer insulating film is formed on a polished and flattened amorphous silicon layer, and the second wiring layer is formed thereon. CONSTITUTION:Electrode contact windows are formed at the desired positions of a field insulating film 2 to cover the surface of a silicon layer 1 formed with elements, and after electrodes 3 consisting of an aluminum film are formed at the places thereof, a PSG layer 4 is formed as a first interlayer insulating layer. Then an amorphous silicon layer 5 is grown, and polished using an abrasive to expose the PSG layer 4 on the electrodes 3, and the first interlayer insulating layer 4 is left to uniform thickness on the electrodes 3 at the whole surface of a wafer. Then a PSG layer 6 is formed as a second interlayer insulating layer, and after an electrode and wiring contact window is formed at the desired region, a second layer electrode and wiring 7 consisting of an aluminum film is formed on the second interlayer insulating film 6. A PSG film 8 is formed finally.
Patent JP-S61185445-A (JP)
Inventor: MUSA GIICHI
IPC: B32B5/18
Filed: 1984-02-17
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63196183-A (JP)
Title: Picture display device
Inventor: WATANABE TSUTOMU
IPC: H04N5/68
Filed: 1987-02-10
Abstract: PURPOSE:To always display a picture with superior picture quality even immediately after applying a power source switch, by detecting the fact that an electron beam is generated in a temperature limited area by detecting the quantity of the electron beam which flows in a vertical focusing electrode, and delaying the output of the picture until the period of a spatial charge limited area by a detected output. CONSTITUTION:The electron beam from a wire cathode 2 flows in the vertical focusing electrode 3, and is inputted to the power source terminal 52 of the vertical focusing electrode in a circuit 51. A CPU60 judges whether an area is the temperature limited area or the spatial charge limited area based on a difference between the quantities of the electron beams of the front end and the rear end. When it is the spatial charge limited area, a signal to control the driving of a circuit 6 which controls the intensity of emitted light by controlling the quantity projected on a screen 9 is outputted. A control driving circuit 63 controls a voltage supplied from a beam flow controlled electrode driving power source terminal 64 with the signal from a D/A converter 62, and delays the picture output time of the picture appearing on the screen until the operating state of the wire electrode 2 arrives at the spatial charge limited area. In such a way, it is possible to set the stable luminance state of the picture appearing on the screen from the first.
Patent JP-S59153887-A (JP)
Title: Pretreating apparatus
Inventor: FUJIWARA KIYOSHI
IPC: C23G3/00
Filed: 1983-02-22
Abstract: PURPOSE:To reduce pollution of circulating washing water due to liquid chemicals in the pretreatment of metallic articles such as defatting or washing by discharging the washing water produced immediately after defatting and having a high concn. of a defatting liquid chemical, while circulating the washing water produced in the succeeding stage only for use. CONSTITUTION:A metallic article to be treated on the surface by such as plating is passed from A to B through a pretreating chamber 1. An alkaline defatting liquid heated by a heater 7 is passed through a forward circulating passage (a) by a pump P1 and ejected from a nozzle 5. The liquid is returned to a vessel 2 after defatting the metallic article from a discharge port 6 through a backward circulating passage (b). The washing water in the tank 3 is then circulated by a pump P2 through a forward circulating passage (c) and ejected from a nozzle 5 to wash off the defatting liquid attached to the metallic article and the pretreating chamber 1. The washing water having high concn. of the defatting liquid is discharged to a drain channel 10 through a valve Vs. The washing water produced in the succeeding stage being polluted to less degree is circulated together with fresh water through the tank 3, 4 via circulating passages c, d, e, f, respectively. Thus, the consumption of the washing water is saved as a whole.
Patent JP-S60211283-A (JP)
Inventor: ROODERITSUHI BUIRUHERUMU GUREE
IPC: B01D53/26
Filed: 1985-02-15
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H01204645-A (JP)
Title: Accelerating pulse wave meter
Inventor: TAKAHASHI MASAKI
IPC: A61B5/02
Filed: 1988-02-10
Abstract: PURPOSE:To form constant judgement on a measured result at all times and greatly reduce a measuring time by conforming the peak value and position in time of the first crest of each wave form between the measured result of an accelerating pulse wave form and a corresponding reference wave form and outputting same. CONSTITUTION:As a measuring finger is inserted, a light emitted from a light emitting element 2 transmits the finger tip and is absorbed into a light receiving element 3. The changing quantity of the resistance value of the light receiving element 3 is converted into a voltage value by a voltage converter 4 and this voltage wave form is made an accelerating pulse wave wave form by a secondary differentiator 5 and, after arithmetically processed by a computing element 9, outputted from an output device 10. At this time, the accelerating pulse wave wave form is compared with a model wave form by a wave form comparator 6 and the pattern to which the accelerating pulse wave wave form belongs is recognized by a recognizer 7, and a reference wave form corresponding to this pattern is outputted from a reference wave form memory 8 to the computing element 9. The computing element 9 carries out arithmetic processing so as to conform the peak value (a) of the first crest of the reference wave form with the peak value of the first crest of the accelerating pulse wave form while to conform the positions of peaks of each crest with respect to a time base, and outputs the result from the output device 10.
Patent JP-H10229164-A (JP)
Title: Semiconductor integrated circuit device
Inventor: YASUKAWA TSUGUMASA
IPC: H01L27/04
Filed: 1997-02-13
Abstract: PROBLEM TO BE SOLVED: To fully supply power to cell column regions without increasing the area of a chip, by a method wherein power supply wirings, which are connected with the cell column regions, are extendedly provided in a form that bridge- shaped wirings, which pass through the upper part of macro block from an I/O cell region, are electrically insulated from the macro block. SOLUTION: Power supply wirings 10D to 12D led out from the lower side of a chip pass through the upper part of a macro block 1 as power supply wirings 10E to 12E without being connected with a power ring of the macro block 1 and are further connected with cell columns 2 to 4 via power supply wirings 10C to 12C. That is, in the Al multilayer wiring structure of the chip, the wirings 10D to 12D are wired in the first layer, and the wirings 10E to 12E are wired on the macro block 1 in a form that the wirings 10D to 12D are replaced with the wirings 10E to 12E in the third layer. The wirings 10E to 12E, which are the third layer wirings, are connected with power supply wirings 10B to 12B within the cell columns 2 to 4, and a power supply is directly made to the cell columns 2 to 4.
Patent JP-H10229310-A (JP)
Title: Stabilized current mirror circuit
Inventor: YUASA TACHIO
IPC: G05F3/26
Filed: 1997-02-13
Abstract: PROBLEM TO BE SOLVED: To make an input output characteristic more stable, even in the presence of dispersion in the manufacture process or the like. SOLUTION: This circuit is provided with a current mirror circuit 10, having an input side nMOS transistor(TR) 11 and an output side nMOS TR 12, an error amplifier circuit 30 whose output current I3 decreases from a prescribed value with respect to the increase in an output level of the output nMOS TR 12 from a prescribed voltage, a current mirror circuit 20 having an output pMOS TR 12 connected in series with an input side pMOS TR 22 and the output side nMOS TR 12 to which the current I3 is supplied, and an nMOS TR 42 connected between an output side pMOS TR 21 and the output side nMOS TR 12. An nMOS TR 41 connecting to the input terminal provides a bias, by which the nMOS TR 42 acts as a norator to a gate of the nMOS TR 42.
Patent JP-H11226951-A (JP)
Title: Device for manufacture of prepreg
Inventor: MATSUZAKI TAKASHI
IPC: B29K61/04
Filed: 1998-02-12
Abstract: PROBLEM TO BE SOLVED: To provide a prepreg manufacturing device which is capable of shooting troubles such as the stoppage of an operation at an installation due to the winding to a paper base material prepreg around the surface of a roll or the meandering of the prepreg as a result of the transfer of resin from the prepreg fed out of a drying chamber. SOLUTION: A paper base material is impregnated with phenol resin and at the same time, is dried to manufacture a paper base material prepreg. This prepreg is passed through a space between the rolls of a meandering adjuster. In this prepreg manufacturing device of such a construction as described, each of the rolls of the meandering adjuster is of a dual structure comprising an outer roll 9 and an inner roll 11, and a space through which cooling water or cooling gas passes is formed between the rolls 9, 11 of the dual structure. The surface of the roll 9 is treated.
Patent JP-H05226610-A (JP)
Title: Manufacture of semiconductor storage device
Inventor: TANAKA HIROYUKI
IPC: H01L21/8246
Filed: 1992-02-17
Abstract: PURPOSE:To materialize a capacitor having a large accumulation of charge by forming a charge accumulation layer by utilizing an unevenness of a pattern edge due to the interference of incident and reflected exposure lights. CONSTITUTION:Photo resist is applied onto the surface of a silicon substrate 101 having a base structure and is prebaked and patterned. Due to the interference of cast or reflected exposure light, a resist film 111 has such a pattern edge as to have a first uneven surface 112. Nextly, an SOG film 113, an intermediate insulating film, is applied to the whole surface and is baked and etched to expose the surface of the resist film 111. Then, a second uneven surface 114 is transferred to the SOG film 113. And, the resist film 111 is removed and the SOG film 113 is solidified by baking. Then, by depositing polycrystalline silicon on the whole surface by CVD and then by patterning it, a charge accumulation layer 115 which has a larger surface area and has A fourth uneven surface 117 corresponding to a third uneven surface 116 formed by transferring the second uneven surface.