Patent GB-1398519-A (GB)
Title: Time division multiplex telecommunications systems
IPC: H04J3/00
Filed: 1971-11-25
Abstract: 1398519 Automatic exchange systems POST OFFICE 24 Nov 1972 [25 Nov 1971] 54739/71 Heading H4K In a TDM switching network having a plurality of incoming and outgoing PCM highways which are terminated on respective stores, time slot interchanging is effected by reading- out acyclically the incoming store and correspondingly writing-in acyclically the outgoing store, both operations being performed in parallel data bit mode. The PCM signals may represent either speech or data. Each incoming (or outgoing) highway of a group of such highways incorporates a unique delay which assists in the serial/parallel (or parallel/ serial) conversion process. A plurality of concentrators are connected to a main switching unit over a set, e.g. A-D, of 32 channel 4-wire highways which are terminated by respective bit and frame aligning circuits 20. The latter also serve to extract supervisory data from the first and 16th time slots of each frame and pass this to a common control 24. The circuits 20 are each connected by a GO highway to one of the serial parallel converters 22-202, which can accommodate up to eight highways each, and, by a return highway to one of the parallel serial converters 33-303 (Fig. 3). The parallel 8 bits output from the S-P converters are stored in unique bit positions of associated information stores 26-206 which can each accommodate on a random access basis the 256 bits pertaining to one frame in a group of 8 highways. The control circuit armed with calling and called subscriber addresses seeks a free slot on a highway extending to the called party's concentrator, say slot Y on highway K, and then hunts for a free slot on tandem highways e.g. 27 and 300, interconnecting the stores (26 say) and 301 on which the calling and called parties are currently terminated. The hunt is effected by comparing the free/busy condition of like numbered slots on the two highways and choosing the first fully free one, Fig. 7 (not shown). The relevant data is inserted in control memories 29, 306 and 309 for permitting read-out, write-in and cross-point switching respectively of a parallel bit data word from store 26 to store 301 via a cross-point at the junction of highways 27 and 300. In the example considered a connection for speech in the opposite direction is also set up via store 206, highway 207, cross-point, highway 30, store 31 and terminating circuit 20. In order to ensure that the incoming channels are properly supermultiplexed it is ensured that the frames of all incoming highways are synchronized to each other. Blocking in the network is avoided by providing twice as many time slots therein as there are channels connected thereto. Serial/parallel converter and incoming store (Figs. 4, 5).-The eight incoming highways 21-0 to 21-7 which terminate on a same converter are provided with respective delay circuits 45 which have a progressively increasing delay of 0 to 7 bits duration. Each highway threads a respective column of matrix 40 which has eight rows 0 to 7 corresponding to the eight bits of each time slot on a highway. The array is scanned using binary/decimal converter 43 such that during a first bit period simultaneously the first bit 0 of a time slot x on highway 0, the last bit 7 of a time slot x-1 on highway 1, the penultimate bit 6 of time slot x-1 on highway 2 ... and the second bit 1 of time slot x-1 on highway 7 are transferred into respective rows in store 26. The bits are associated with the other bits of their respective channels such that they can be read-out in parallel over highway 27 by means of the address generator 200. Another arrangement in which the incoming frames of the different highways are not aligned and in which a certain amount of blocking is permitted is depicted in Figs. 9, 10. Each highway 21 is terminated in a respective clock extractor 91, bit aligner 92 and slot aligner 93. Each of the latter is connected via a respective unique delay line 45 (Fig. 10) to a respective shift register 94. When the latter is filled with the eight bits from one channel, an address generator, associated with the highway to which that channel belongs, enables the multiplexer 96 0 -96 7  to read-out the contents of the register in parallel to storage positions 50 similar to the rows of store 26 in Fig. 5. The delays 45 0 -45 7  are similar to the delays 45 of Fig. 4, but their effect is to stagger the filling of the shift registers 94 so that the latter may be read-out individually without causing any intermingling of the bits from the different channels. An identical 7 input/output highway system (not shown) is multipled to the supermultiplex highways 27 and 30 as indicated by the multiple signs 2 on these highways in Fig. 9.