Patent GB-835036-A (GB)
Title: Improvements in or relating to computer circuits
IPC: G06F7/50
Filed: 1956-11-21
Abstract: 835,036. Parallel adders and subtractors. PHILCO CORPORATION. Nov. 21, 1956 [Nov. 21, 1955], No. 35579/56. Class 106 (1). In an electrical computer circuit comprising an adder and/or subtractor adapted to combine two sets of digits to produce two alternative results, one result or the other is selected in dependence on the presence or absence of a carry or borrow condition at a further adder and/or subtractor. In the binary parallel adder.subtractor shown, Fig. 1, the numbers are obtained from registers 12, 14 and the result sent to register 16, each register comprising a bi-stable Eccles-Jordan type circuit for each digit. The circuit stages are arranged in four groups 21, 22a, 22b, 23a, 23b and 24a, 24b for dealing with binary denominations 1-3, 4-6, 7-10 and 11-15 respectively. The circuits 22a, 23a, 24a each function as if the carry input from the preceding group were " 0 " (see, e.g., arrow 40), and circuits 22b, 23b, 24b each function as if the carry input were " 1." The actual carry from the preceding group, when determined, gates the result (sum or difference) and carry outputs from one of the pair of circuits, such as 22a, 22b, to register 16 and to output control gates for the next group respectively. For example, if the carry output from group 21 is " 1," line 38 is energized which opens the three gates 60 so that the result outputs on multi-line 50 from 22b are passed to buffer 58 and output gates 18b, and also opens gates 86 and 92 whereby the carry output from 22b is used to select outputs from one circuit of the next group. If the carry output from 22b is e.g. " 0," the energizing signal on line 52 is passed via gate 86 and buffer 80 to result output gates 74 and carry output gates for circuit 23a. A signal 19 controls the transfer of the result through gates 18a-18c! to register 16 from which it may subsequently be transferred to 14 with a left or right shift. A final carry of " 1 " from group 24a, 24b will produce an output from buffer 20. Addition or subtraction is selected by applying an energizing signal to line 32 or 34. Fig. 2 shows the first two stages of group 21 or of one of the circuits 22a, 23a, 24a. Each stage comprises transistors which when energized by negative potentials applied to their bases provide low impedance emitter-collector paths whereby output lines may be short-circuited to earth. In the lowest stage, transistors receive the digit inputs from 12 and 14 on separate " 0 " and " 1 " lines 126, 124 and 130, 128, respectively. Thus, if transistors 134 and 140, or 138 and 144 are energized (inputs 1, 1 or 0, 0) the result output line 154 is connected to earth (indicating " 0 ") ; for other input combinations, line 154 will be substantially at the negative potential - Vcc, to indicate a sum or difference digit of " 1." The carry outputs are similarly obtained on line 162 (corresponding to " 0 ") and inverted on line 160 (corresponding to " 1 "), the emitter-collector paths being connected through transistors 148, 150, energized for subtraction and addition respectively, and further transistors 136, 142, 146 controlled by the digit inputs. The next stage (Fig. 2, left) and succeeding stages are similar but more elaborate since the carry input may be " 0 " or " 1," the result and further carry outputs being obtained on lines such as 172 and 174, 176 respectively. The lowest stage of circuits 22b, 23b, 24b differs from that shown in Fig. 2 (right) in that a carry input of " 1 " is assumed (Fig. 2A, not shown). The gating circuits, Fig. 1, also may comprise transistors. The pair of circuits such as 22a, 22b in a group may be combined into a single circuit (Fig. 4, not shown). The transistors may be replaced by other circuit elements, e.g. magnetic cores or neon tubes. Reference is made also to circuits for addition or subtraction only, and to radices other than binary.