baber/WOPTO huggingface dataset:
Patent TW-417212-B (TW)
Title: The method of improving the effect of short channel in transistor
Inventor: HUANG JEN-MING
IPC: H01L21/335
Filed: 1997-10-28
Granted: 2001-01-01
Abstract: This invention provides a kind of method of improving the short channel effect in transistor comprising the following steps: (a) to form a gate electrode on the semiconductor substrate; (b) to form a sidewall layer containing ions on the above-mentioned sidewall of the gate electrode; (c) apply ion implantation step which forms the ion implantation region on the surface of the semiconductor substrate beside two sides of the above-mentioned gate electrode; (d) apply an annealing step which is used to diffuse the ions in the above-mentioned ion implantation region and the sidewall layer containing ions toward the semiconductor substrate underneath the above-mentioned gate electrode and forms shallow ion implantation diffusion region; which characteristic is within the above-mentioned step (a) (b), further comprising the step of forming silicon nitride sidewall layer on the sidewall of the above-mentioned gate electrode.
Patent TW-359863-B (TW)
Title: Multi-chip stack package
Inventor: PENG JIAN-TUO
IPC: H01L21/60
Filed: 1997-11-28
Granted: 1999-06-01
Abstract: Two IC chips are stacked on a substrate. The lower chip is directly ball solder coupled to the corresponding circuit terminals on the substrate by circuit terminals. The circuit terminals of the upper chip face upwards and coupled to the corresponding circuit terminals on the substrate by wire bonding. Therefor, while increasing the limited substrate area, the amount of circuit I/O terminals can be doubled. The plated through hole (PTH) of the present invention is designed on the periphery of the encapsulation for stack packaging of the chips having fewer I/O terminals. In one embodiment, the extended I/O terminal is designed into a longitudinal shape for solder connection to the circuit, without the need of using solder balls as required in a conventional ball grid array (BGA).
Patent TW-418538-B (TW)
Title: Semiconductor memory
Inventor: SAKUI KOJI
IPC: H01L29/792
Filed: 1998-01-26
Granted: 2001-01-11
Abstract: In the conventional semiconductor device, it is difficult to prevent an erroneous write to the write-inhibit unit due to the low charge voltage of the channel in NAND unit. Therefore, the present invention provides a semiconductor memory device which is stepped up in write inhibit potential after the channel of a NAND cell kept in a floating state is stepped up in potential by its capacitive coupling with a word line, moreover enhanced in error write margin, and improved in reliability. Transistors Q2, Q3, and Q5 are set non-conductive when data are written in, and a bit line and a data latch circuit 14 are separated from each other. In this state, a bit line BL is charged up to a pre-charge voltage VPRE higher than a power supply voltage, and the channels of all cell transistors which form selection NAND cells are charged up to the pre-charge voltage VPRE. Therefore, a semiconductor memory device of this constitution can be stepped up in write inhibit potential and enhanced in error write margin after the channels of cell transistors and word lines are capacitively coupled together.
Patent TW-365696-B (TW)
Title: Method of manufacture of DRAM on silicon on insulator (SOI) wafer having 2D trench capacitor insulation
Inventor: JI MING-HUA
IPC: H01L21/8242
Filed: 1998-02-02
Granted: 1999-08-01
Abstract: Method of manufacture of dynamic random access memory using silicon on insulator, including a two-dimensional trench capacitor structure to increase signals of the random access memory cell and the use of a polycrystal silicon memory node structure connecting the on-insulator silicon to the substrate of a semiconductor for the elimination of a floating substrate effect. First, the two-dimensional trench is formed through the on-insulator silicon and the insulation layer beneath it to the semiconductor substrate for forming a vertical trench; and then conduct reactive etch to laterally remove the insulation layer of fixed volume exposed in the vertical trench, forming thus the side of said two-dimensional trench. The polysilicon layer deposited by the two-dimensional trench remains in the two-dimensional trench capacitance, being used as a memory node structure and at the same time, it is connecting the on-insulator silicon to the semiconductor substrate.
Patent TW-384325-B (TW)
Title: Flexible spun-bonded nonwoven fabric
Inventor: YUASA HARUO
IPC: D04H3/11
Filed: 1998-03-27
Granted: 2000-03-11
Abstract: The present invention relates to a flexible spun-bonded nonwoven fabric using spun-bonded nonwoven fabric containing one or more layers comprising continuous long filament of a thermoplastic resin and partially hot-melting the fiber for increasing the flexibility and bulkiness that is suitable for medical materials and hygienic materials. This flexible spun-bonded nonwoven fabric is produced by partially hot-pressing a thermoplastic resin fiber having circular cross section, whose average fiber diameter is within the range of 10 to 50 micron and has 10 to 70 g/m<2>. The fiber constituting the nonwoven fabric is less than 3 per cm and non-crimp or crimp numbers and the fiber of non-heat pressing part has arc-like form and the shortest distance between heat pressing parts is above 0.5 mm and a ratio of the thickness (t1) of the pressing part to the thickness (t2) of the non-pressing part is between 12 and 100 and the bending resistance is below 70 mm. The spun-bonded nonwoven fabric may be a laminated nonwoven fabric obtained by laminating melt blow nonwoven fabric to spun-bonded nonwoven fabric or a laminated nonwoven fabric interposing melt blow nonwoven fabric between two layer spun bonded nonwoven fabrics.
Patent TW-422815-B (TW)
Title: Oxidation and corrosion resistant flexible graphite composite sheet
Inventor: MERCURI ROBERT ANGELO
IPC: F16J15/34
Filed: 1998-03-30
Granted: 2001-02-21
Abstract: Flexible graphite sheet is made by compressing a mixture of fine particle of intercalated, exfoliated, expanded natural graphite with fine particles of intercalated, unexpanded, expandable particles of natural graphite admixed with small amounts of a phosphorous bearing compound, the unexpanded particles being more finely sized than the expanded particles. The resulting sheet of flexible graphite exhibits improved fire retardant and sealability properties and additionally resistance to oxidation and corrosion.
Patent TW-468273-B (TW)
Title: Semiconductor integrated circuit device and method for manufacturing the same
Inventor: WATANABE KOUZOU
IPC: H01L21/8242
Filed: 1998-04-02
Granted: 2001-12-11
Abstract: The object of the present invention is to provide a semiconductor integrated circuit technique by which the degree of integration of a DRAM can be improved by making the memory cells of the DRAM finer and the operating speed can be increased. In the method for manufacturing semiconductor device in accordance with the present invention, gate electrodes (7) are first formed on the main surface of a semiconductor substrate (1) with gate insulating films (6) in between; then silicon nitride films (8) are formed on the upper surfaces of the electrodes (7); and first side-wall spacers (14) composed of silicon nitride and second side-wall spacers (15) composed of silicon oxide are formed on the side faces of the electrodes (7). Next, in a selected MISFET Qs in the memory cell area of the DRAM, connection holes (19 and 21) are opened against the first side-wall spacers (14) in a self-aligning manner and connecting sections of conductors (20) and bit lines BL are formed. In N-channel MISFETs Qn1 and Qn2 and a P-channel MISFETs Qp1 in the other area of the DRAM than the memory cell area, high-concentration N-type semiconductor areas (16 and 16b) a high-concentration P-type semiconductor area (17) are formed against the second side-wall spacers (15) in a self-aligning manner.
Patent TW-390093-B (TW)
Title: A method of HSYNC synchronization
Inventor: OVERALL GARY SCOTT
IPC: G06K15/12
Filed: 1998-04-03
Granted: 2000-05-11
Abstract: A method of achieving line-to-line synchronization having a high degree of synchronization accuracy. Synchro-nization is performed by a specific high-speed block of logic which signals the beginning of scans to a PELCLK-based logic at pel boundaries, and provides sub-pel shifting as it passes data between the pel generation logic and a laser control signal. The synchronization error is made as small as propagation delays through a single multiplexer element. Such delays can be controlled to values less than 1/2 ns. The need to stop and restart the clocks is eliminated. All complex pel generation logic is clocked with the relatively low frequency PELCLK without regard to the synchronization task.
Patent TW-473481-B (TW)
Title: Methods of making water-soluble chitosans
Inventor: CHEN RUNG-HUEI
IPC: C08B37/08
Filed: 1998-05-12
Granted: 2002-01-21
Abstract: This invention relates to the methods of making water-soluble chitosans. This invention comprises of but is not limited to, the followings: (a) method 1 is characterized by using 2 to 8 M urea to react with chitosan-acidic aqueous solution at 40 to 60 DEG C for 0.1 to 24 hour. (b) Method 2 is characterized by employing the ultrasonic irradiation to treat urea-chitosan-acidic aqueous solution for 0.1 to 24 hour at 20 to 60 DEC C. (c) Method 3 is characterized by employing the mechanical shearing with the shear rate of 2600 to 26000 sec<SP>-1</SP> to treat chitosan-acidic aqueous solution at 50 to 60 DEG C for 0.1 to 24 hour. (d) Method 4 is characterized by using the ultrasonic irradiation of 100 to 1000 watts to treat chitosan-acidic aqueous solution at temperature below 40 DEC C for 0.1 to 24 hours. (e) Method 5 is characterized by first using the mechanical shearing then applying the ultrasonic irradiation to treat chitosan-acidic aqueous solution within appropriate temperature ranges for 0.1 to 24 hours. Alternatively, the ultrasonic irradiation is conducted before the mechanical shearing. The treatments methods described above will break the crystalline region of the chitosan molecules. The chitosan-acidic aqueous solution is subsequently dialyzed or ultrafiltrated, neutralized to obtain water-soluble chitosan solution. The water-soluble chitosan solution can be used directly or crystallized, spray-dried or lyophilized to prepare powdery products.
Patent TW-386255-B (TW)
Title: Method for self-aligned silicide process
Inventor: LIN JIAN-TING
IPC: H01L21/28
Filed: 1998-05-18
Granted: 2000-04-01
Abstract: A method for self-aligned silicide (salicide) process is provided. The method executes the secondary selective epitaxy process after forming polysilicon gate and source/drain, so as to form amorphous silicon on the polysilicon gate and source/drain. Then, metal barium is doped, such that the metal deposited on the substrate and the amorphous silicon of the selective epitaxy on the substrate perform a silicidation reaction process, so as to avoid generating junction current leakage caused by narrowing shallow junctions of elements. Furthermore, the silicidation reaction process requires only one annealing process to form low-resistive silicide, without the need of secondary annealing process.
Patent TW-472074-B (TW)
Title: Process for hydrophobicizing particles, and their use as fillers in polymer masterbatches
Inventor: KOSHKI AHTI AUGUST
IPC: C08K3/00
Filed: 1998-05-21
Granted: 2002-01-11
Abstract: Particles are hydrophobicizing by treatment with a compound containing amino and silane groups, followed by treatment with a silane compound containing a hydrophobic group. The invention is particularly useful for treating hydrophilic mineral particles. The treated particles can be used, for example, as fillers in polymer masterbatches.
Patent TW-399361-B (TW)
Title: Method of and device for controlling pulse width modulation inverter
Inventor: KOYAMA MASATO
IPC: H02M7/5395
Filed: 1998-06-16
Granted: 2000-07-21
Abstract: The high harmonic frequency of exporting voltage of known pulse width modulation inverter always change irregularly. Therefore, it can easily have terrible electromagnetic noise while AC motor's original high harmonic frequency. The pulse width modulation inverter is capable of dispersing the high harmonic frequency of exporting voltage into a pre-determined range without changing the pulse width. Pulse width is determined by the pulse modulation. In addition, it will be formed by changing the exporting voltage with time.
Patent TW-414980-B (TW)
Title: Semiconductor structure having common gate, source area and well region, and method of manufacturing thereof
Inventor: JUANG YUAN-CHI
IPC: H01L21/335
Filed: 1998-07-24
Granted: 2000-12-11
Abstract: A semiconductor structure having a common gate, a source and a well, and a method of manufacturing such semiconductor structure are provided. The method comprises forming a spacer on only one sidewall of a gate in a conventional MOS transistor, while not on the sidewall adjacent to source area in the conventional MOS transistor. A salicide thus covers the gate, the source area and a dopant region near the source area whose ion impurities having the same type as those of well region. A dielectric layer is formed on the whole surface. A tungsten plug is formed in the dielectric layer on the source region and the dopant region which has the same ion impurities type as those of the well region. The tungsten plug is used for connecting the gate, the source area and the well region of the MOS transistor.
Patent TW-393619-B (TW)
Title: Method for organizing a real figure by beehive unit
Inventor: NGAN KA-HAM
IPC: G06F3/00
Filed: 1998-08-19
Granted: 2000-06-11
Abstract: The present invention relates to an unique beehive unit; through the strong computing and storing ability of a computer and the program developed from this invention, the figure is divided into hexagonal pixels and compounded to beehive units with all kinds of shapes, and the beehive unit component is used to restore a complete figure required. After the required figure is organized by the unit of beehive form. Selecting the corresponding beehive units with all kinds of colors (e.g. Ceramic tile or glass, etc.) prepared beforehand by mechanical or manual way, or directly painting the color on the base plate with beehive units to complete the real figures.
Patent TW-440638-B (TW)
Title: Low wet pressure drop limiting orifice drying medium and process of making paper therewith
Inventor: TROKHAN PAUL DENNIS
IPC: D21F7/08
Filed: 1998-09-18
Granted: 2001-06-16
Abstract: An apparatus for drying a cellulosic fibrous structure. The apparatus comprises a micropore medium having pores therethrough. The pores are the limiting orifice in the air flow used in the drying process. The micropore medium has a relatively low wet pressure drop therethrough. This relatively low wet pressure drop advantageously reduces the energy costs used in drying, and/or allows for greater drying to be obtained at constant energy costs.
Patent TW-411316-B (TW)
Title: Biaxially oriented polyester films and their production methods
Inventor: EGASHIRA KENICHI
IPC: C08J5/18
Filed: 1998-10-08
Granted: 2000-11-11
Abstract: Disclosed is a biaxially oriented polyester film that is 7.0 Gpa or more in either the Young's modulus in the machine direction (YmMD) or in the transverse direction(YmTD), and in the range of 55 DEG or more and 85 DEG or less in the circumferential half-width of the diffraction line from the crystal plane in the direction of the polyester's backbone chain that is determined through crystal orientation analysis by wide angle X-ray diffractometry performed while rotating the polyester film around its normal. The film is high in rigidity in all directions within the film plane, high in tear resistance, high in dimensional stability, and resistant to deformation under load, and have very great industrial advantages as material for high-density magnetic recording media, with wide applicability as material for electrostatic capacitor, heat transfer ribbon, and base paper for thermosensitive stencil printing.
Patent TW-432054-B (TW)
Title: Novel trisaryl-1,3,5-triazine ultraviolet light absorbers
Inventor: JAKIELA DENNIS J
IPC: C08K5/3492
Filed: 1998-11-20
Granted: 2001-05-01
Abstract: The present invention relates to novel bondable trisaryl-1,3,5-triazines containing active (acidic) hydrocarbons and the use thereof as an ultraviolet light absorber. The presently claimed compounds are particularly useful, either alone or in combination with other additives, including other ultraviolet light absorbers and stabilizers, in stabilizing polymers and other materials from degradation by environmental forces such as actinic radiation (ultraviolet light), oxidation, moisture, atmospheric pollutants and combinations thereof.
Patent TW-402791-B (TW)
Title: Manufacture method of the metal-oxide semiconductor transistor
Inventor: HUANG SHIOU-WEN
IPC: H01L21/8234
Filed: 1998-12-14
Granted: 2000-08-21
Abstract: This invention provides a manufacture method of the metal-oxide semiconductor transistor. Once the source/drain region of the metal-oxide semiconductor transistor in the logic circuit region is completed, the purpose is to form the doping region with local pocket structure below the LDD structure of the logic circuit region on the substrate, and form an insulating layer above the whole base. Then, a portion of the insulating layer is peeled off to facilitate the peel-off of the spacer in the sidewall of the gate electrode. After the spacer in the sidewall of the gate electrode is peeled off, the local doping process is performed in the region exposed by the spacer to form the doping region with local pocket structure below the LDD structure.
Patent TW-392111-B (TW)
Title: Sharing system for sharing peripheral device via network
Inventor: YANG JE-JU
IPC: H04L29/12
Filed: 1998-12-16
Granted: 2000-06-01
Abstract: This invention provides a sharing system for multiple users to access network peripherals via network. The system comprises a computer system for transmitting messages, at least one terminal connected to the computer network for emitting or receiving the messages, and at least one server computer connected to the computer network for emitting or receiving the messages. Each terminal has a search program to find peripherals connected to the network. However, each server computer is provided with at least one peripheral device and a peripheral service program. The peripheral service program is used for the terminals , connected to the computer network ,to generate status message of all peripherals connected to the server computer, and is employed to provide a connection service between the terminal and the server.
Patent TW-405082-B (TW)
Title: Resolution refinement technique for incremental encoders
Inventor: KIM JIN-K
IPC: G06F3/033
Filed: 1999-04-27
Granted: 2000-09-11
Abstract: The present invention proposes a method for improving the resolution of an incremental encoder, utilizing a simple principle of trigonometric functions to construct pseudo signals, and implement the desired resolution without changing the hardware. Firstly, the parameters of the pseudo signals are prepared by deciding the resolution refinement time n, calculating the crossing interval and the crossing coordinates, the tangent values of each crossing and the coefficients of the pseudo signals. The pseudo signals are thus driven and all the parameters are stored. Next, the encoder receives input signals from sensors and reads the parameters stored in the memory. The values of those desired pseudo signals are then calculated and the corresponding crossing is decided by comparing the values of those signals. When the corresponding crossing is decided, the displacement or the position of the mouse can be obtained with a predetermined process. Then the information of the movement of the mouse is transmitted to the personal computer, and the encoder prepares to treat with the next signals.
Patent TW-419729-B (TW)
Title: Method of a salicide process in integrated circuit
Inventor: LIOU LU-MING
IPC: H01L21/28
Filed: 1999-01-26
Granted: 2001-01-21
Abstract: The present invention discloses a method of a salicide process in integrated circuit to produce a multilayer spacer to prevent short circuit between the gate and the source/drain due to salicide bridging. The method comprises: sequentially depositing at least three layers of dielectric layer on a semiconductor substrate formed with a polysilicon gate; forming a spacer by isotropic and anisotropic etching, in which the isotropic etching will cause the material of a dielectric layer to form forward and lateral recesses; sputtering a Ti, Co or Pt metal film and, forming a discontinuous salicide on the surface of the gate and the substrate after thermal treatment.
Patent TW-423261-B (TW)
Title: Recording and reproducing apparatus and terminal apparatus
Inventor: MATSUMOTO YOSHIO
IPC: G11B27/11
Filed: 1999-02-01
Granted: 2001-02-21
Abstract: A recording and reproducing apparatus has a communicating unit, a reading unit, a storing unit, a control unit, and an output unit. The communicating unit transmits and receives data to/from an information center in which a plurality of additional information have been stored. The reading unit reads out recorded data from a recording medium on which a plurality of data and index data of a plurality of data have been recorded. The data read out from the recording medium by the reading unit is stored in the storing unit. The control unit reads out the additional information corresponding to the recording medium from which the data is read out by the reading unit from the information center by the communicating unit and writes the read-out additional information into the storing unit as additional data of the recording medium which is read out by the reading unit. The output unit outputs the data stored in the storing unit and the additional data.
Patent TW-423255-B (TW)
Title: Method and apparatus for providing and monitoring coupons via a network
Inventor: WILLIAMS CHRISTOPHER D
IPC: H04N7/16
Filed: 1999-03-26
Granted: 2001-02-21
Abstract: The present invention provides a method and apparatus for targeting specific audiences for coupon distribution. In one embodiment, users of an entertainment network are monitored to determine specific preferences. Alternatively, the users may be surveyed to determine preferences. A preference profile is determined based on the preferences. Coupons are distributed only to the users that fit a coupon distributor's chosen preference profile. The coupons may be delivered in a variety of ways. For example, coupons may be downloaded to a user's system automatically or on demand. Alternatively, coupons may be mailed to the user automatically or on demand. The coupons may then be redeemed by the user. Coupons are provided and monitored such that each coupon may be redeemed a predetermined number of times.
Patent TW-437174-B (TW)
Title: Delay-locked loop which varies the number of delay blocks and method for driving the delay-lock loop
Inventor: LEE SANG-BO
IPC: G11C11/4076
Filed: 1999-03-30
Granted: 2001-05-28
Abstract: A delay-locked loop in which the number of delay blocks is varied and a method for driving the same are provided. The delay lock loop includes a phase detector, a charge pump and a variable delay circuit. The variable delay circuit controlling the phase of a feedback signal includes delay blocks increased or reduced by cutting of a fuse corresponding to a reference clock signal. The number of delay blocks is varied by cutting of the fuse, to thereby simplify phase control of the phases of the reference clock signal and the feedback signal, and increase the operating frequency region of the adopted reference clock signal. The operation speed of a device such as a DDR, a rambus DRAM (RDRAM) or a merged memory with Logic (MML) employing the delay lock loop is improved.