Patent IE-48664-B1 (IE)
Title: Circuit arrangement for regenerating an isochronous data signal
IPC: H04L7/033
Filed: 1979-11-29
Abstract: 1. A circuit arrangement (8) for regenerating an isochronous data signal which consists of data (Fig. 3, signal a) and data timing (Fig. 3, signal b) having the timing frequency fD and which is scanned in a transmitter by a scanning signal (Fig. 3, signal c) which is plesichronous for same and which has a higher timing frequency fA , is transmitted by way of a line (4) as a sequence of scanning elements (Fig. 3, signal d) with this frequency (fA ) and is received by a receiver (5), in which respect this receiver has the following units : - a regenerator circuit for regenerating the scanning elements (Fig. 3, signal f), - a detector for determining data transitions of the scanning elements (Fig. 3, signal h), - a regenerator for the data timing (Fig. 3, signal g) ; and in which respect the circuit arrangement (8) which is connected to the receiver (5) has the following units : - a frequency generator circuit consisting of a controllable oscillator (14) for generating a timing signal having the timing frequency f1 of a first divider (15) with a constant ratio of division for generating a first timing signal (Fig. 3, signal i) having the timing frequency f2 , and of a second divider (16) with a controllable ratio of division for generating a second timing signal (Fig. 3, signal k) having the timing frequency f3 , in which respect the timing frequency f2 corresponds to the higher timing frequency fA and the timing frequency f3 corresponds to the timing frequency fD and in which respect the timing frequency f1 corresponds to the least common multiple of the data timing frequency (fD ) and of the frequency (fA ) of the scanning signal, as well as of a first phase comparator (13) for comparing the data timing (Fig. 3, singal g) with the first timing signal (Fig. 3, signal i) for generating a control singal for the oscillator (14), - a control input (21) of the second divider (16) for the input of control signals, by reason of which individual timing segments of the second timing signal having the frequency f3 are in each case variable in length by a fixed amount, - an output circuit (28) in which the second timing signal scans the regenerated scanning elements (Fig. 3, signal f) and at the output (9) of which (28), upon correct scanning phase relationship, the regenerated data signal is tappable ; characterised - by a scanner (22) which is connected to the outputs of the dividers (15, 16) and which scans the second timing signal (Fig. 3, signal k) in relation to the first timing signal (Fig. 3, signal i), whereby there ensues at its output (23) a master signal (Fig. 3, signal m), flanks of which designate the points in time at which data transitions of the scanning elements are to be expected, - by a second phase comparator (25), a first input (23) of which is connected to the scanner (22), a second input (11) of which is connected to the detector for determining the data transitions of the scanning elements, and the output (20) of which is connected to at least one control input (21) of the second divider (16), and which within a predetermined phase region constantly checks whether the data transitions of the scanning elements (Fig. 3, signal k) occur in-phase with the master signal flanks (Fig. 3, signal m) and which, upon each phase deviation, delivers a control signal to the second divider (16).