baber/WOPTO huggingface dataset:
Patent JP-H09293735-A (JP)
Title: Manufacture of field effect transistor
Inventor: NAKAJIMA SHIGERU
IPC: H01L29/47
Filed: 1996-04-24
Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method with which a field effect transistor, having large gate breakdown strength and short gate length, can be manufactured uniformly in a simple manner. SOLUTION: This manufacturing method contains a process in which a recess is formed by etching on a GaAs compound semiconductor substrate (1) before formation of active layers 4 and 4c, a process in which active layers 4 and 4e are formed by ion implantation after formation of the recess, a process in which gate electrodes 7, 7a and 7e are formed in the recess, a process in which source high density regions and drain high density regions 8, 8a and 8e are formed on the position which is not deeper than the active layers 4 and 4e from the surface of the semiconductor substrate (1), and a process in which source electrodes 11, 11a and 11e and drain electrodes 12, 12a and 12e are formed on the source high density regions and the drain high density regions 8, 8a and 8e.
Patent JP-H02289989-A (JP)
Title: Monolithic storage device
Inventor: HORI RYOICHI
IPC: G11C11/401
Filed: 1990-04-20
Abstract: PURPOSE:To enable a monolithic storage device, which has a memory array divided into at least four blocks, to operate in a short-access-time mode by outputting a larger number of data than divided blocks at constant intervals by a continuous output means. CONSTITUTION:The memory array 100 is divided into four blocks 100 (1) - (4), input/output data lines I/O(1) - I/O(4) are provided corresponding to the respective blocks, and a selecting circuit 5CA which sends out one output from each block to the input/output data lines corresponding to the respective blocks in response to the same array address and a parallel/series converting circuit 3CA which sends signals on the input/output data lines I/O(1) - I/O(4) in series are provided. The access time in continuous mode, i.e. the time from the input of the array address to the output of data is therefore determined by the operation speeds of a buffer circuit 4C'S, a control circuit 5ZS, and an amplifying circuit 7CS. Consequently, the monolithic storage device can operates in the short-access-time mode.
Patent JP-S62261762-A (JP)
Inventor: TEO MATSUKU
IPC: F16J15/32
Filed: 1987-04-24
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S63269684-A (JP)
Title: System for encoding color picture data
Inventor: MAEDA MITSURU
IPC: H04N19/196
Filed: 1987-04-28
Abstract: PURPOSE:To reduce visual deterioration, by encoding mean values of the distribution constitution and each distributing area of color picture data in accordance with the presence/absence of an edge. CONSTITUTION:An edge detecting means 8 which detects the edge of color picture data in a block, a producing means which produces a code word of fixed length indicating that the edge is detected in a block, means 9 and 10 which respectively calculate mean values of information indicating the distribution constitution of color picture data in blocks and mean values of color picture data in each distributing area in accordance with the edge, and encoding means 11 and 12 which respectively code the mean values of the information indicating distribution constitution and color information into code words of different bit length according to the presence/absence of the edge, are provided. Therefore, brightness information and color information can be coded efficiently in accordance with the degree of the edge and, at the same time, the resolution can be compressed and preserved efficiently. As a result, a decoded picture is matched with the visual property of human beings.
Patent JP-S5728265-A (JP)
Title: Current detecting circuit employing silicon bidirectional switching element
Inventor: KOBARI YOSHIO
IPC: G01R19/165
Filed: 1980-07-29
Abstract: PURPOSE:To accomplish a quick and accurate detectin of current peak value while minimizing effect due to temperature changes and secular changes in the circuit elements. CONSTITUTION:When current to be measured is limited, the voltage across a resistance 11 is so low that a silicon bidirectional switching element (BDT) 21 is off and it is applied between terminals of the BDT21. As the voltage applied to the BDT21 exceeds a switching voltage with the increase in the current being, the BDT21 conducts causing the current to pass mostly through a variable resistor 12, a resitance 13 the BDT21 and a rectifier bridge 16. And the output of the bridge 16 operates a photocoupler 17 regardless of the polarity of the current to be measured. This enables on/off operation of the BDT with a limited variation in charcteristics thereby reducing effect due to temperature changes and secular changes thereof.
Patent JP-S60248981-A (JP)
Inventor: TAKAOKA DAIZOU
IPC: F26B21/04
Filed: 1984-05-22
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H01274212-A (JP)
Title: Mobile vehicle guidance facility
Inventor: ISHIDA HIDEO
IPC: G05D1/02
Filed: 1988-04-26
Abstract: PURPOSE:To easily change a travel path by changing the selection information of automatic travel, and information for the number of detection of a guidance part. CONSTITUTION:A mobile vehicle A is provided with a pair, right and left, driving wheels 1L and 1R, and an idle wheel 2 of caster type, and is constituted in such a way that steering, etc., can be performed freely. And a grid shape frame body L is provided on the ceiling side of the travel path by forming a grid point at every setting interval in a longitudinal and a lateral directions. And slit light projectors 3 which project two beams of slit light B1 and B2 toward the ceiling, and image sensors 4 as an image pickup means which image-pick up the projecting part of the frame body L from a direction different from a projecting direction are mounted on both end parts of the front and the rear sides of a vehicle, respectively. In such a way, steering control is performed based on image pickup information so that the automatic travel can be performed along one of plural guidance parts being set along the progressing direction of the vehicle in guidance for travel of grid shape, and also, the discrimination of a position can be performed. As a result, it is possible to change the travel path based on the selection information of the guidance part.
Patent JP-H043460-A (JP)
Title: Semiconductor device
Inventor: SHIMIZU MICHIKO
IPC: H01L27/04
Filed: 1990-04-20
Abstract: PURPOSE:To suppress temperature rise of an operating element by providing steps on the surface of a semiconductor substrate, and providing an electronic element at a position adjacent to the lower side of the step. CONSTITUTION:A resistance element 2a is disposed on a higher step on the surface of a silicon substrate 1 having steps, a resistance element 2b is disposed on a lower step. Insulating films 3 are provided between the substrate 1 and a resistance element 2, between the elements 2a and 2b, on the elements 2a, 26. The entire element 2b generates heat. The generated heat is transferred to the film 3 by conducting to flow to the substrate 1 by high thermal conduction. Since the film 3 has low thermal conductivity, the heat to be transferred laterally at the film 3 is small, and more heat is transferred to the substrate 1 of the part opposed to the element 2b. In this case, since the side of the element 2b is opposed to the substrate 1c in addition to the conduction of the heat from the lower part 1b of the element 2b, the heat flows also from the side of the element, thereby providing an effect of preventing the temperature rise of the element 2b.
Patent JP-S5627428-A (JP)
Title: Error detecting circuit for bilateral bus
Inventor: INOUE RIYUUICHI
IPC: G06F3/00
Filed: 1979-08-14
Abstract: PURPOSE: To realize reduction in hardware by making a comparison between the output of one logical unit connected to a bilateral bus and that of the other logical unit isolated from the bilateral bus via a gate circuit.  
     CONSTITUTION: Logical unit BALU1 consisting of an arithmetic logical operating circuit and RAM and BALU3 isolated from bilateral bus 101 via gate circuit 2 are provided. When BALUs are read, data in BALU1 are input to comparing circuit 4 by way of bus 101 and data in BALU3, on the other hand, are input to circuit 4 by way of data bus 102. In the constitution like this, circuit 4 compares the contents of bus 101 to those of bus 102 and, when the both disagree, generates a comparison error. Thus, errors of BALUs with the bilateral bus and those of the bilateral bus are detected. 
     COPYRIGHT: (C)1981,JPO&Japio
Patent JP-H07311708-A (JP)
Title: Memory card
Inventor: NIWANO HIROYUKI
IPC: G06F12/00
Filed: 1994-05-18
Abstract: PURPOSE:To provide a nonvolatile memory card where a large capacity of data can be accessed in a short time. CONSTITUTION:This memory card stores write data D0-D7 according to externally supplied successive addresses A0-A9, and has an address decoder 2 which generates enable signals CE0-CE3, memory block select signals A6-A9, and in-block address signals A0-A3 according to the externally supplied addresses A0-A9 and plural memory devices DV0-DV3 including buffers rb0-rb3 which temporarily store the write data in addresses indicated by the in-block address signals and nonvolatile memories rm0-rm3 which have plural memory blocks capable of storing a specific capacity of data; and, the write data are stored in one of the buffers of the memory devices DV0-DV3 selected in order according to the enable signals and the memory devices transfers the specific capacity of data stored in the buffers to the memory blocks corresponding to the memory block select signals.
Patent JP-H05278378-A (JP)
Title: Magnetic recording medium and discrimination thereof
IPC: B42D15/10
Filed: 1992-03-30
Abstract: PURPOSE:To provide a magnetic recording medium having high forgery preventing effect. CONSTITUTION:A magnetic layer 3 is provided on a substrate 2 and a magnetic shield layer 4 is partially provided thereon and a printing layer 5 having the same thickness as the magnetic shield layer 4 is provided to the part not provided with the magnetic shield layer 4 of the magnetic layer 3 and a concealing layer 6 is further provided on the layers 4, 5. The magnetic data of the magnetic layer 3 at the part where the magnetic shield layer 4 is not present is read by a first magnetic head 7 and bias is applied by a second magnetic head 9 to read the magnetic data of the magnetic layer 3 at the certain part of the magnetic shield layer 4 and both magnetic data are compared to judge genuineness to discriminate a magnetic recording medium.
Patent JP-S59227338-A (JP)
Title: Device for absorbing level difference in nut tightening
Inventor: SHIMURA TAKAFUMI
IPC: B23P19/06
Filed: 1983-06-09
Abstract: PURPOSE:To enable an automatic nut tightening machine with retightening function, to tighten a nut even the tightening face of the nut is different, by providing the machine with a guide pin movable along the axis of a box bit and with a detector for detecting a relative position between the guide pin and the box bit. CONSTITUTION:A box bit 7 is lowered so that a guide pin 14 enters into the threaded portion of a nut T held by a catcher 10, and the nut N comes to be held on the box bit by vacuum suction. The box bit 7 is rotated clockwise by means of a bit holder 15, so that the guide pin 14 is applied on a screw S and withdrawn inside the box bit 7, while the nut N is tightened onto the screw S. The withdrawal of the guide pin 14 causes a detecting pin 17 abutted on the guide pin 14 to retreat, so that a detecting ring connected to the detecting pin comes close to a deector 21. When the guide pin 17 is withdrawn by a distance l, the detector 21 detects the detecting ring 18. If such a distance l is a given value, the nut is tightened with set torque.
Patent JP-S63269413-A (JP)
Title: Superconductive member and its manufacture
Inventor: SHIODA TAKAO
IPC: C30B29/22
Filed: 1987-04-27
Abstract: PURPOSE:To reduce the production cost by providing a Cu2O mono-crystal layer on a copper substrate and providing an oxide superconductor layer on it. CONSTITUTION:A Cu2O layer is provided on a copper substrate, and an oxide superconductor layer is provided on it. The surface of the copper substrate is oxidized to form the Cu2O layer, then an action to remove the surface section of this Cu2O layer is repeated to form the Cu2O mono-crystal layer, and the oxide superconductor layer is formed on this Cu2O mono-crystal layer. Plasma may be used to oxidize the copper substrate and remove the Cu2O layer. The production cost is thereby reduced, and the production efficiency is improved.
Patent JP-2000292921-A (JP)
Title: Photosensitive resin composition and manufacture of resist pattern by using the same, and electric circuit board each by using the resit pattern manufacturing method
Inventor: YOSHINO TOSHIZUMI
IPC: G03F7/032
Filed: 1999-04-12
Abstract: PROBLEM TO BE SOLVED: To provide a photosensitive resin composition superior in pressure cooker test(PCT) resistance, developability, close adhesiveness, heat resistance, TCT performance, flexibility, and mechanial characteristics, and to provide a method for manufacturing the resist pattern. SOLUTION: This photosensitive resin composition comprises a photosensitive resin (A) obtained by adding a saturated on unsaturated polybasic acid anhydride (c) to an ester formed by reacting an epoxy compound (a) with an unsaturated monocarboxylic acid (b), and an epoxy hardening agent (B) represented by formula I and a photopolymerization initiator (C), and the resist pattern is manufactured by laminating this photosensitive resin composition on a substrate and imagewise irradiating it with activated rays, photocuring the exposed parts and, erasing the unexposed parts by development. In formula I, each of R1, R2, R3, R4, R5, and R6 is, independently, H or a halogen atom, or a 1-20C alkyl group or the like and (n) is an integer of 0-3.
Patent JP-S5729164-A (JP)
Title: Computer system
Inventor: BABA EIJI
IPC: G06F12/00
Filed: 1980-07-29
Abstract: PURPOSE:To set the number of protection blocks optionally by suppressing the writing of written data supplied from a data bus when a write inhibition signal is supplied via a write inhibition signal bus. CONSTITUTION:A CPU1 selects a storage device 5 on the basis of a write and read address supplied via an address bus 2, and indicates the reading and writing of data by a write and read signal supplied via a control signal bus 3. In this case, when write and read addresses from the CPU1 are included in protection addresses preset for memory protection, an address comparator 18 supplies a write inhibition signal to a write inhibition signal bus 19, and this signal is used to send the indication of the write inhibition of written data to the device 5. Consequently, the device 5 suppresses the writing of the written data by a write and indication signal supplied from the CPU1 via the bus 3 when the write and read indication signal shows the indication of writing.
Patent JP-S5533902-A (JP)
Title: Removal method of balance plug weight and construction
Inventor: ISE MASAYOSHI
IPC: F16F15/32
Filed: 1978-08-28
Abstract: PURPOSE:A removal method where the weight is made to be removed by such  means that, a security condition of the weight be eliminated by pressurizing top end  of the weight to compress and deform a material of high ductility in the point end of the weight, then with a reverse turning made to that when inserted. CONSTITUTION:In a turbine rotor 1, to a screw hole 2 is detachably installed a balance plug weight 30. In this case, in a center of the weight 30 is constructed a screw hole 9 to the bottom end of which a butt piece 8, tapered with its point end made to a smaller diameter and made of highly ductile material, is screwed. The butt piece 8 is formed into such dimension with the point end of the butt piece 8 hitting to mate with a screw hole bottom 2b when the weight 30 is screwed into the screw hole 2. At this time, a fine clearance d is made to be constructed between a flank 2a facing a hole opening side of the screw hole 2 and a flank 30a of the weight 30 facing the former flank 2a. For a release of security of the weight 30, a force 11 is applied to the weight 30 to deform the butt piece 8 performing the removal.
Patent JP-S62263378-A (JP)
Inventor: TANAKA KOJI
IPC: D04H3/007
Filed: 1986-05-06
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H043494-A (JP)
Title: Forming method of via of multilayer ceramic board
Inventor: INOUE SADAO
IPC: H05K3/46
Filed: 1990-04-19
Abstract: PURPOSE:To improve the electrical connectability of a via by using copper powder, to which copper oxide is added as a conductor. CONSTITUTION:A substance, in which copper oxide is added to copper powder, is employed as a conductor 4 filled into a via hole 3. The grain size of the copper powder is selected in approximately 1.1mum on an average. The fill of copper oxide is selected at 10-20wt.%. When the via hole 3 is filled with the conductor 4 constituted in said manner, alumina powder is also filled simultaneously. The grain size of the alumina powder is chosen in 0.3-3mum, and fill thereof is brought to 5-10vol.%. When the via hole is filled with the conductor 4, a protective film 10 is disposed on a surface different from the disposing surface of the mask film 2 of a green sheet 1 so as to close the via hole 3. The upper section of the conductor 4 is filled with copper paste 4a. The copper paste 4a is filled in the thickness of approximately the half of the thickness (approximately 38mum) of the mask film 2. The copper paste 4a is filled by using a rubber squeegee 7 in the same manner as the filling of copper powder.
Patent JP-H07293643-A (JP)
Title: Overrunning type tooth form flexible intermeshing gear device
Inventor: ISHIKAWA SHOICHI
IPC: F16H1/32
Filed: 1994-04-19
Abstract: PURPOSE:To increase strength and abrasion resistance by using spur gears for a rigid internal gear and a flexible external gear and making the tooth forms protruded and recessed, respectively, so as to carry out the.overrunning intermeshing. CONSTITUTION:The number of teeth for a flexible external gear is larger by two than that for a rigid internal gear, and spur gears are used for both gears. In the case of a tooth form induction method, point 'A' is a limiting point of upper intermeshing on a moving locus 'L', and point 'B' is a limiting point of lower intermeshing, taken on a protrude a curve of locus for the rigid internal gear. Curve 'AC' obtained by similarly converting the curve of the locus 'AB' with a reduction ratio X, the point 'A' being the original point, is taken as a protruded tooth form of the flexible external gear. Then, curve 'AD' obtained by similarly converting the curve 'AB' with an enlargement ratio (1+lambda), the point 'A' being the original point, is taken as a recessed gear form of the rigid internal gear. Mutual intermeshing of the rigid internal gear and the flexible external gear starts from a position of contact point between point 'C' and point 'D', and terminates as the intermeshing at the point 'A'. Accordingly, the overrunning type intermeshing is obtained, so that lubricating oil film retention between the tooth surfaces is enhanced and tooth surface abrasion is prevented to raise the allowable transmission torque.
Patent JP-S59231221-A (JP)
Title: Electromagnetic spring clutch
Inventor: SUZUKI KAZUYOSHI
IPC: F16D27/105
Filed: 1983-06-10
Abstract: PURPOSE:To stabilize the transmission of torque and reduce noise by eliminating the eccentric state of an armature by forming the both frictional surfaces of the armature and an input revolution body into tapered frictional surfaces. CONSTITUTION:An armature 5 is arranged in retreatable ways in the axial direction with respect to the recessed tapered frictional surface 1a of an input pulley 1 and has a projected tapered frictional surface 5a opposed to the recessed tapered frictional surface 1a. Said projected tapered frictional surface 5a can be attached onto the concaved tapered frictional surface 1a when an exciting coil 2 is excited. Since the both frictional surfaces 1a and 5a are formed into the tapered recessed and projected surfaces respectively, a transmission torque can be stabilized, preventing the armature 5 from being set into eccentric state wth respect to the input pulley 1. Further, the contact between the armature 5 and the armature guide part 7b of a cover 7 is suppressed, and generation of noise is prevented.
Patent JP-S62260724-A (JP)
Title: Production of ferromagnetic fine powder for magnetic recording
Inventor: NAKADA KAZUO
IPC: C01G49/00
Filed: 1986-05-07
Abstract: PURPOSE:To obtain the titled ferromagnetic fine powder consisting of highly dispersible hexagonal ferrite crystal particles having improved perpendicular orientation property, by adding a phosphorus compound to a ferrite precursor prepared by heat-treating a basic aqueous suspension containing a metal compound, e.g. Ba, etc., and an iron compound, treating and firing the resultant blend. CONSTITUTION:An aqueous solution containing one or more metal compounds (Ma) of Ba, Sr and Pb, an iron compound and, as desired, one or more of Co, Ti, Mn compounds, etc., as a substitution element (Mb) for controlling coercive force in respective specific amounts is prepared. The molar ratio of the above-mentioned Ma component is 1/4-1/12 based on the Fe+Mb components. An solution of NaOH, KOH, etc., is brought into contact and blended with the above-mentioned aqueous solution of the metal compound to afford a basic aqueous suspension, which is then put in, e.g. a reaction vessel equipped with a heating device, and treated by reaction while heating at 60-250 deg.C, preferably 100-200 deg.C to give a plate particulate hexagonal ferrite precursor. A phosphorus compound, e.g. orthogphosphoric acid, is added to the resultant hexagonal ferrite precursor and fired at 650-950 deg.C to afford the above- mentioned ferromagnetic fine powder for magnetic recording.
Patent JP-S61263134-A (JP)
Title: Method of measuring semiconductor
Inventor: YAMANADA OSAMU
IPC: H01L21/66
Filed: 1985-05-16
Abstract: PURPOSE:To shorten time required for inspection when the electrical characteristic of unit elements on a semiconductor wafer is inspected, by a method wherein the electrical characteristic of the whole of lines is measured with respect to each line and each column and an assumption is made from the measurement that a separate circuit element located at a crossing position of an abnormal line and an abnormal column is abnormal. CONSTITUTION:When it is assumed that separate circuit elements are diodes and that a reverse voltage resistance characteristic is to be inspected, P-N junctions are connected in series sequentially, and an N pole is connected to the P pole of an adjacent element, while a P pole is connected to the N pole of an adjacent element on the opposite side. The diodes in the number of (m) are connected in series in this way, and two terminals are obtained. The reverse voltage resistance characteristic is examined by applying a voltage to said terminals. The examination is conducted with respect to both lines l and columns (k). When an abnormal result of measurement is found out with respect to an i-th line li and also with respect to a j-th column kj, it can be concluded that there is some abnormality in an ij-th separate circuit element whereat abnormal line and column intersect each other. Then it is only required to examine the characteristic of the ij-th element afresh.
Patent JP-S585005-A (JP)
Inventor: MISHIERU EETSUMAN
IPC: H01L47/02
Filed: 1982-06-17
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。