Patent GB-1397617-A (GB)
Title: Input-output controller for a data processing system
IPC: G06F13/00
Filed: 1972-07-28
Abstract: 1397617 Data processing system INTERNATIONAL BUSINESS MACHINES CORP 28 July 1972 [11 Aug 1971] 35355/72 Heading G4A An input/output control unit for use in a data processing system includes interface circuits arranged to be connected to a processing unit of a first or a second type, an indicator circuit settable to indicate the type of processor to which the control unit is connected, and means responsive to the indicator and to a predetermined operating condition within the control unit to execute a first sequence of instructions compatible with a processor of the first type or a second sequence of operations which includes operations which may be initiated in the controller by a processor of the first type in response to the first sequence of instructions but not by a processor of the second type. Gen ral.-The unit 33 is used to connect a number of I/O devices 34, e.g. magnetic tapes, to a central processing unit (CPU). As described two CPUs A and B are connected to the control unit via respective channel processors, logic circuits 30, 31, and a priority-resolving switch 32. The control unit includes a microprogram-controlled processor 41 and a pluggable indicator 45 to indicate the types of processors A and B. The unit is arranged in response to an error condition to perform sequences of operation to enable the processor to recover the error by retry. Type I.-In response to an error a " DISCONNECT IN" signal is fed to the CPUs. Error signal EA sets latches 44 and 53 via AND gates 43 and 47, enabled by type I indicating signals from indicator 45 and error signals from OR 50. The " DISCONNECT IN " signal is fed to the CPUs via ANDs 55 and a type I processor responds to the signal by causing the control unit to be selectively reset and the failed operation to be retried. Type II.-A type II processor cannot respond to a "DISCONNECT IN" signal. In response to an error OR 50 causes trap circuit 59 to force microprocessor 41 to a particular program instruction while the error signal from OR 50 is simultaneously fed via AND 101, enabled by a type II signal from indicator 45, to latch ERRL. The latch, which is an internal latch in the microprocessor 41 causes a microprgram to be executed which selectively resets the control unit (an operation similar to that performed in type I operation but in that case under control of the CPU) and sets flags indicating an error. The control unit then waits for a further CPU command which is rejected with an indication that the rejection was due to an error. The type II CPU responds to the error indication by causing the failed operation to be retried. Microprogram processor.-The Specification describes the microprogram controlled processor 41 and gives details of suitable microprograms. The processor includes a read only program store accessed by means of an address register whose contents are normally incremented or decremented but may be modified in order to handle branch (conditional or unconditional) instructions. A local memory is also provided and the arithmetic and logic unit performs parity checks on address and other data signals.