baber/WOPTO huggingface dataset:
Patent TW-463109-B (TW)
Title: A system, method and article of manufacture for utilizing a transaction interface in a mobile communication network
Inventor: GERSHMAN ANATOLE VITALY
IPC: G06Q30/00
Filed: 2000-03-06
Granted: 2001-11-11
Abstract: A system is disclosed that facilitates web-based information retrieval and display system. A wireless phone or similar hand-held wireless device with Internet Protocol capability is combined with other peripherals to provide a portable portal into the Internet. The wireless device prompts a user to input information of interest to the user. This information is transmitted a query to a service routine (running on a Web server). The service routine then queries the Web to find price, shipping and availability information from various Web suppliers. This information is then available for use by various applications through a transaction interface.
Patent TW-449944-B (TW)
Title: Feedhorn
Inventor: DOU YUANZHU
IPC: H01Q5/55
Filed: 2000-04-20
Granted: 2001-08-11
Abstract: This invention is to provide a feedhorn (also called horn-type or trumpet-shaped feed unit) which can accurately receive radio waves from a plurality of neighboring satellites and can be made easily at a low cost. A feedhorn (1) comprises: at least first and second waveguides (4, 5) in positions so as to face each other over a center line (A), each having an axis (B) parallel to the center line; and first and second horns (6, 7) on extension lines of the axes. The outer ends of the first and second horns have aperture end faces (6a, 7b), respectively. Each of the aperture end faces of the first and second horns is tilted toward the center line by a predetermined angle so that the first and second horns are perpendicular to the travel directions of radio waves transmitted from at least two broadcasting satellites (S1, S2) orbiting around the earth and reflected by an antenna (3) on the ground.
Patent TW-464889-B (TW)
Title: Niobium powder, its sintered body, and capacitor comprising the same
Inventor: NAITO KAZUMI
IPC: C22C32/00
Filed: 2000-07-14
Granted: 2001-11-21
Abstract: There is provided a niobium powder containing nitrogen with an amount in a range from 500 ppm to 7,000 ppm by weight. The average particle diameter ranges from 0.2 μm to 3 μm. The present invention also provides a capacitor having a sintered body produced by sintering such a niobium powder, a capacitor having small leakage current ratio, a sintered body for capacitor, a niobium powder for the same and the capacitor.
Patent TW-526270-B (TW)
Title: Fe-Cr-Ni alloy for electron gun electrodes and Fe-Cr-Ni alloy sheet for electron gun electrodes
Inventor: ONO TOSHIYUKI
IPC: C21D8/02
Filed: 2000-09-02
Granted: 2003-04-01
Abstract: This invention is to provide an Fe--Cr--Ni alloy for electron gun electrodes to be applied in processing, having superior drawing properties that have been more stricker in recent years, in particular, which generate no cracks in drawing. An Fe-Cr-Ni alloy for electron gun electrodes, comprises: 15 to 20% Cr; 9 to 15% Ni; 0.12% or less C; 0.005 to 1.0% Si; 0.005 to 2.5% Mn; 0.03% or less P; 0.0003 to 0.0100% S; 2.0% or less Mo; 0.001 to 0.2% Al; 0.003% or less O; 0.1% or less N; 0.1% or less Ti; 0.1% or less Nb; 0.1% or less V; 0.1% or less Zr; 0.05% or less Ca; 0.02% or less Mg by weight; balance Fe and inevitable impurities; which is characterized at that: when the alloy is rolled into a sheet with a thickness in the range of 0.1 to 0.7 mm, the surface portion of the sheet includes groups of lining inclusions. The number of groups with widths of 10 μm or more and less than 20 μm and with lengths of 20 μm or more is 20/mm<SP>2</SP> or less, and the number of groups with widths of 20 μm or more and with lengths of 20 μm or more is 5/mm<SP>2</SP> or less.
Patent TW-500767-B (TW)
Title: Preparation method of mixture of polyvinylimidazole and silica
Inventor: YANG JENG-GAN
IPC: C08L83/00
Filed: 2000-09-06
Granted: 2002-09-01
Abstract: This invention provides a preparation method of mixture of polyvinylimidazole (PVI) and silica: vinylimidazole and [3-(methacryloxy)propyl]trimethoxysilane are copolymerized to from a modified polyvinylimidazole which is employed to prepare the mixture of polyvinylimidazole and silica by hydration and condensation reaction with water and tetramethoxy-silane. According to experimental analysis, covalent bonds are formed between the modified polyvinylimidazole and silica in the prepared mixture of polyvinylimidazole and silica.
Patent TW-457614-B (TW)
Title: Integrated circuit device having an internal state monitoring function
Inventor: LEE YUN-SANG
IPC: H01L21/66
Filed: 2000-09-27
Granted: 2001-10-01
Abstract: An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.
Patent TW-471052-B (TW)
Title: Silicon focus ring and its manufacturing method
Inventor: TAMURA KAZUYOSHI
IPC: H01L21/302
Filed: 2000-10-31
Granted: 2002-01-01
Abstract: The object of the present invention is to provide a silicon focus ring which can prevent defects caused by impurities such as heavy metal or the like. This is a focus ring consisting of single crystal silicon used in a plasma device, and herein the concentration of oxygen between lattices contained in that focus ring is not less than 5x10<SP>17</SP> atoms/cm<SP>3</SP> and not more than 1.5x10<SP>18</SP> atoms/cm<SP>3</SP>. In manufacturing the focus ring used for the plasma device, this focus ring is manufactured by growing the single crystalline silicon, where the concentration of oxygen between lattices is 5x10<SP>17</SP> atom/cm<SP>3</SP> and not more than 1.5x10<SP>18</SP> atoms/cm<SP>3</SP>, by Czochralski method, and the single crystalline silicon is processed into annular form.
Patent TW-473892-B (TW)
Title: Semiconductor device tester
Inventor: YAMADA KEIZO
IPC: G01R31/02
Filed: 2000-11-06
Granted: 2002-01-21
Abstract: Current produced in a sample 5 by irradiating the sample with parallel electron beam 2 is measured by an ammeter 9. The measurement is repeated while changing acceleration voltage of electron beam 2. An information related to a structure of the sample 5 in a depth direction thereof is obtained by a data processor 10, on the basis of a difference in transmittivity of electron beam 2 into the sample 5 due to the difference of acceleration voltage.
Patent TW-515131-B (TW)
Title: Isolator
Inventor: KIM CHANG SIK
IPC: H01P1/36
Filed: 2000-12-12
Granted: 2002-12-21
Abstract: An isolator is disclosed, in which a ferromagnetic sheet is placed into a shielding resin case together with garnet ferrite and an internal terminal sheet (with strip lines extending therefrom). Thus the leakage magnetic flux shielding effect is reinforced, and the bulk of the isolator is made compact. The constitution is as follows. That is, the internal terminal sheet (with the strip lines extending therefrom), a garnet ferrite, a plurality of insulating films and a ferromagnetic sheet are inserted into a shielding resin case in the cited order. Further, this structure is inserted into between upper and lower cases, and three dielectric devices and a chip resistor are disposed on a PCB and around the lower case, while a connecting terminal part with input/output terminals connected to the PCB electrodes is formed on the PCB.
Patent TW-516031-B (TW)
Title: Voltage boost level clamping circuit for a flash memory
Inventor: AKAOGI TAKAO
IPC: G11C16/30
Filed: 2001-01-18
Granted: 2003-01-01
Abstract: A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
Patent TW-I232807-B (TW)
Title: Microinject head with driving circuitry and the manufacturing method thereof
Inventor: CHEN CHIH-CHING
IPC: B41J2/14
Filed: 2001-01-19
Granted: 2005-05-21
Abstract: This invention is to provide a microinject head with driving circuitry and the manufacturing method thereof. Microinject head utilizes bubbles as virtual valve to eject fluid, comprising a manifold, at least one fluid chamber, at least a pair of first bubble generating member and second bubble generating member, one or above orifice, and a driving circuitry, in which the driving circuitry controls one or more pairs of first bubble generating member and second bubble generating member at the same time to eject the fluid in the corresponding fluid chamber through the corresponding orifice, so as to achieve the effect of ejecting fluid. Moreover, since the driving circuitry and bubble generating members are integrated in the same substrate, not only the number of processing steps is reduced, but also a structure with fewer circuit components and connecting circuit can be obtained.
Patent TW-503493-B (TW)
Title: Copper pad structure
Inventor: HOWELL WAYNE J
IPC: H01L21/3205
Filed: 2001-01-31
Granted: 2002-09-21
Abstract: A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.
Patent TW-I287706-B (TW)
Title: A method of creating a prototype data processing system, a hardware development chip, and a system for debugging prototype data processing hardware
Inventor: BATTALINE ROBERT P
IPC: G06F11/22
Filed: 2001-04-19
Granted: 2007-10-01
Abstract: A method for creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.
Patent TW-530098-B (TW)
Title: Dielectric films and related method
Inventor: WICKBOLDT PAUL
IPC: C23C16/46
Filed: 2001-08-22
Granted: 2003-05-01
Abstract: Disclosed is thick adherent dielectric films deposited on plastic substrates for use as a thermal barrier layer to protect the plastic substrates from high temperatures which, for example, occur during laser annealing of layers subsequently deposited on the dielectric films. It is desirable that the barrier layer have properties including: a thickness of 1 mum or greater, adheres to a plastic substrate, does not lift-off when cycled in temperature, has few or no cracks and does not crack when subjected to bending, resistant to lift-off when submersed in fluids, electrically insulating and preferably transparent. The thick barrier layer may be composed, for example, of a variety of dielectrics and certain metal oxides, and may be deposited on a variety of plastic substrates by various known deposition techniques. The key to the method of forming the thick barrier layer on the plastic substrate is maintaining the substrate cool during deposition of the barrier layer. Cooling of the substrate may be accomplished by the use of a cooling chuck on which the plastic substrate is positioned, and by directing cooling gas, such as He, Ar and N2, between the plastic substrate and the cooling chucks. Thick adherent dielectric films up to about 5 mum have been deposited on plastic substrates which include the above-referenced properties, and which enable the plastic substrates to withstand laser processing temperatures applied to materials deposited on the dielectric films.
Patent TW-490749-B (TW)
Title: Formation method of lateral double-diffused metal oxide semiconductor transistor
Inventor: HUANG JR-FENG
IPC: H01L21/28
Filed: 2001-05-18
Granted: 2002-06-11
Abstract: This invention provides a formation method of lateral double-diffused metal oxide semiconductor transistor (LDMOS). Firstly, a first N type epitaxial layer is formed on a semiconductor substrate, in which the dopant concentration is ranging between 5E11 ions/cm<SP>2</SP> and 5E12 ions/cm<SP>2</SP>. A second N type epitaxial layer is then formed on the first epitaxial layer, in which the dopant concentration is ranging between 5E12 ions/cm<SP>2</SP> and 5E13 ions/cm<SP>2</SP>. After the formation of field oxide layer, a layer of gate oxide layer is formed on the substrate followed by forming a polysilicon layer on the gate oxide layer. Gate electrodes are formed through lithography and etching techniques. Subsequently, a P type well is formed, an N type doped region of source/drain is formed and finally a P type doped region of source/drain is formed by lithography and ion implantation techniques.
Patent TW-493085-B (TW)
Title: Lightning optical device and projection video device using the same, and integrated type image device
Inventor: YAMAMOTO YOSHIHARU
IPC: H04N9/31
Filed: 2001-05-23
Granted: 2002-07-01
Abstract: The lighting optical device has: light sources which emit plural different color lights 207, 208, and 209, plural rotating optical scanners 102, 103, and 104, and plural scanning lenses 109, 110, and 111. The optical scanners have spiral reflecting surfaces 102, 103, and 104 formed on the outer periphery of columnar bodies. The respective color lights are made incident on the respective reflecting surfaces parallel to the axes of rotation, and their reflected color lights are enlarged by the scanning lenses to scan a lit area with the plural different color lights in order. Accordingly, the lighting device can enhance the scanning linearity, reduce the noise, and decrease costs and power consumption.
Patent TW-527728-B (TW)
Title: Semiconductor storage device using single channel transistor to transport voltage for selected word line
Inventor: NAKAMURA HIROSHI
IPC: G11C16/06
Filed: 2001-06-08
Granted: 2003-04-11
Abstract: A semiconductor memory device disclosed in the present invention comprises a memory cell array, in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The above-mentioned row decoder circuit includes a plurality of first transistors of a first conductivity type, in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.
Patent TW-I317285-B (TW)
Title: New use and kit for remedies for cancer
Inventor: TOSHIHIRO NOGUCHI
IPC: A61K31/7048
Filed: 2001-07-24
Granted: 2009-11-21
Abstract: A medicament for treating cancer for use in combination therapy with an anti-HER2 antibody, which comprises amrubicin or a pharmaceutically acceptable salt thereof as an active ingredient.
Patent TW-521186-B (TW)
Title: Sequencing method for accessing shared system resources and its bridging system
Inventor: LIN JEN-RUNG
IPC: G06F13/16
Filed: 2001-07-26
Granted: 2003-02-21
Abstract: The present invention provides a sequencing method for accessing a shared system resource and its bridging system, which enables an increased transmission rate and ensures correctness of the executing result when a plurality of master controllers need to access the shared system resource. The sequencing method includes providing each transaction with a transaction identification value and a master identification value. The present invention assigns each master controller with different access priority, and provides a higher rate in accessing the shared system resource when the correctness of the executing result is ensured.
Patent TW-530518-B (TW)
Title: Bending wave loudspeaker
Inventor: AZIMA HENRY
IPC: H04R7/04
Filed: 2001-08-03
Granted: 2003-05-01
Abstract: A loudspeaker comprising a panel which is sufficiently stiff to support bending waves, the panel having a boundary, a transducer mounted to the panel to apply bending wave energy in the form of dispersive travelling waves thereto at a first location in response to an electrical signal applied to the transducer to cause the panel to vibrate and radiate an acoustic output, the loudspeaker having a frequency range extending from a lower frequency to a higher frequency and the panel having a stiffness giving a coincidence frequency above the lower frequency, and comprising means on or associated with the panel at a second location to attenuate travelling bending waves in the panel to prevent or at least substantially to moderate panel resonance.
Patent TW-497151-B (TW)
Title: Method for producing semiconductor with increased threshold voltage uniformity of transistor
Inventor: JUANG CHIAU-SHUEN
IPC: H01L21/28
Filed: 2001-09-21
Granted: 2002-08-01
Abstract: A semiconductor production method with an increased transistor threshold voltage uniformity comprises: providing a substrate; placing the substrate in an oxygen-containing first gas for driving in dopant ions; placing the substrate into the first gas in a first initial temperature and heating the substrate at a first rate of temperature increase to a first final temperature, in which the first initial temperature has to be sufficient to making oxygen difficult in entering the substrate; placing the substrate in an oxygen-containing second gas to perform an oxidation treatment to form a sacrificial oxide layer; and placing the substrate into the second gas at a second initial temperature and using a second rate of temperature increase to perform a heating to a second final temperature, in which the second rate of temperature increase must be sufficient to accelerate the rate of formation of the sacrificial oxide layer and stop the escaping of the doped particles. The invented method can effectively reduce the concentration of the doped particles neutralized by oxygen so that the threshold voltage is kept within the specification.
Patent TW-548654-B (TW)
Title: Read only memory sensing circuit and the sensing method
Inventor: SHIAU MING-CHUEN
IPC: G11C16/00
Filed: 2001-10-15
Granted: 2003-08-21
Abstract: The present invention provides a new read only memory (ROM) sensing circuit and the sensing method, which can be operated at a high-speed and satisfy a low power consumption requirement. For the sensing method, when the data stored in the memory is in a logic high level, the process that pulls up the output terminal OUT to the first voltage level is divided into two stages. In the first stage, the output terminal OUT is pulled up to a voltage level obtained by subtracting Vt from the first voltage (where Vt is the threshold voltage of transistor). In the second stage, the output terminal OUT is pulled up from a voltage level obtained by subtracting Vt from the first voltage to the voltage level of the first voltage. Additionally, in order to effectively shorten the required time of the first stage, a dual path structure composed of the first and the second current supply path is designed in the first stage, in which the first current supply path provides the supply earlier than the second current supply path. While in the second stage, only the second current supply path is reserved.
Patent TW-520520-B (TW)
Title: Packaging structure and method of field emission display
Inventor: SHIAU MING-JIUN
IPC: H01J1/30
Filed: 2001-11-28
Granted: 2003-02-11
Abstract: There is provided a packaging structure of field emission display. In the present structure, glass bars are placed at positioning locations on the anode plate and cathode plate in the way of process positioning. Then, the anode plate and cathode plate are aligned and sealed, so that the glass bars on the anode plate and cathode plate are separated by a gap of equal distance. Glass adhesive is applied to the gap between two glass bars. Then, a thermal process is performed to make the glass adhesive be melted into glass, thereby completing the package.
Patent TW-594564-B (TW)
Title: Processor stalling
Inventor: ROTH CHARLES P
IPC: G06F9/38
Filed: 2001-12-05
Granted: 2004-06-21
Abstract: In one embodiment, a programmable processor includes a pipeline having a number of stages. A stall controller is adapted to pre-detect a hazard condition within one of the stages of the pipeline and synchronously stall another stage of the pipeline. The stall controller generates additional stall signals in order to stall other stages in the pipeline.
Patent TW-I229142-B (TW)
Title: Magnetron sputtering system and photomask blank production method based on the same
Inventor: WATANABE MASATAKA
IPC: C23C14/35
Filed: 2001-12-24
Granted: 2005-03-11
Abstract: The present invention provides a magnetron sputtering system, which ensures a formation of a desired thin film, using a thick target. In the sputtering process, a portion of the target does not have erosion free portions. The present invention provides a magnetron sputtering system 8 comprising a chamber 10 for sputtering, a target electrode 5 installed inside said chamber, a substrate electrode 6 installed in the chamber opposite to the target electrode, a ring-shaped magnet 2 installed so as to enclose the side surface of the target electrode, and a semi-circular disk shaped magnet installed opposite to the target-mounted surface of the target electrode, wherein the semi-circular disk shaped magnet 1 is rotated in the circumferential direction of the target electrode and is magnetized in the direction perpendicular to the target electrode. This ensures a specific magnetic field component to be generated over the thick planar target surface 3.