Patent GB-1366001-A (GB)
Title: Virtual storage system
IPC: G06F12/10
Filed: 1972-06-28
Abstract: 1366001 Virtual storage systems INTERNATIONAL BUSINESS MACHINES CORP 28 June 1972 [29 June 1971] 30204/72 Heading G4A A virtual storage system (described in detail in Figs. 10-24, not shown) comprises a relatively slow access main store (14), a relatively fast access buffer store (12) and registers (220- 223), each associated with a different section of the fast store, the stores being addressed from a central processor unit (10) using an address having a real part and a virtual part, a section of the fast store being addressed only if a predetermined part of the real address coincides with the contents of the register associated with that section. As described the slow access store holds data as quad words with four quad words to a block, sixteen blocks to a sector and four sectors to a page. The fast access store comprises sixteen frames each holding one sector i.e. sixteen blocks of data. In a fetch operation a line (792) is energized and a 32-bit address from the CPU (10) is fed via gates (802) to an address register (125). The address comprises a virtual part in bit positions 8-19, bits 8-11 representing the segment and bits 12-19 representing the page, and a real address in bit positions 20-31, bits 20-21 representing the sector, bits 22-25 representing the blocks, bits 26, 27 representing, one of the quad words and bits 28-31 representing the byte. Bits 8-19 are compared in comparators (120-123) with the sixteen virtual addresses stored in associative stores (100-103), resulting in a signal on one of sixteen leads (130 -133). Sixteen link registers (210-213) store 4 bit words representing the addresses of data stored in the associated frame of the buffer store, these words being coded into a signal on one of sixteen leads for comparison with the outputs from the comparators (120-123) resulting in an output signal from one of sixteen OR gates (324, 413, 445, 475). If bits 20, 21 of the real address coincide with the bits stored in sector address register 220-223 associated with the same frame of the buffer store (i.e. if data from the requested page and sector is stored in the buffer store) one of sixteen AND gates (360- 363) is enabled to feed a signal to an encoder (500) to derive a four bit word which is fed to the "frame" section of a buffer address register (502) and duplicate buffer address register (504). The output from the enabled AND is also used to derive a "compare" signal and is fed together with the "compare" signal to an activity list (521). The activity list is in the form of a push down stack and includes an encoder which responds to the signals on its input leads to put the address of the data being used to the top of the stack and a decoder to provide a signal on its output lead corresponding to the address of the data which has remained in the buffer store unused for the longest time. When comparison is achieved and data is stored in the addressed location, a "block valid" signal is generated and bits 22-27 of the real address are entered into the buffer address register (502), the frame block and quad word data stored therein being decoded to address the buffer store and read out data via gates (810) to the CPU. The main store is not addressed since the combination of a "compare" signal and a "block valid" signal inhibits an OR gate (518) to inhibit an AND gate (515) through which the address from the CPU is fed to the main store address register (816). If no data is stored a "block not valid" signal is generated and bits 22-27 of the real address are entered into the duplicate buffer address register (504). Gates (575, 824) are enabled (since an AND gate (159) is enabled to generate a signal on a lead (174)) and consequently the main store address register (816) receives bits 20-31 of the real address from the CPU (10) and bits 8-19 of the real address from the associative store (100-103) since one of the AND gates (170- 173) is enabled. Data is read from the main store on a bus (583) to the CPU. If comparison is not achieved the output of the activity list (521) corresponding to the register holding the oldest unused data is energized the output from the enabledcomparator (120-123) being encoded in encoder (180) and entered into the enabled address register (210-213), the sector bits from address register (125) being entered into the associated sector address register (220-223). The enabled output of the activity list is also encoded by encoder (522) into a four bit word representing the associated frame, this word being entered into the frame section of duplicate buffer address register (504). With no comparison gate (524) is enabled so that the signal on lead (174) is generated to control the addressing of the main store. When the main store is read out the buffer store also receives the data and stores it at the address specified by the duplicate buffer address register (504). The register (504) has a counter (550) into which the two quad word bits from the address register (125) are entered. The counter is incremented each time a store operation takes place so that one block of data i.e. four quad words are sequentially transmitted from the main store to the buffer store, starting with the requested quad word. A store request on lead (791) results in address bits 20-31 being fed via gate (805) to the main store address register (816). Gates (170-173) are also primed so that the output signal from the comparator (120-123) associated with the register (100-103) holding the virtual address fed from the CPU enables one of the AND gates (170-173) to feed the real address bits 8-19 to the register (816). Data on data bus (822) is consequently stored in the main store of the specified address. The data is also fed to buffer store if and only if the specified address in the buffer store holds valid information (since output gates (514) from the duplicate buffer address register (504) are only enabled in a "fetch" operation). Thus data from the CPU is only stored in the buffer store as an updating operation of valid data. The "block valid" signal is derived from a matrix which indicates the presence of absence of information in each of the blocks of each frame of the buffer store. The matrix comprises one flip-flop for each block in each frame, each being set when data is stored at the associated address. This is effected by a decoder (699) receiving bits representing the block and quad word to derive a signal on one of sixteen leads, each signal being fed to sixteen AND gates, one of which is enabled in dependence on the frame of the buffer in which the data is to be stored. The state of the flip-flops are examined in a fetch operation to determine whether the address block has data therein to generate the "block valid" or "block not valid" signals.