baber/WOPTO huggingface dataset:
Patent JP-H0897177-A (JP)
Title: Substrate processing device
Inventor: MURAOKA YUSUKE
IPC: H01L21/677
Filed: 1994-09-28
Abstract: PURPOSE: To prevent contamination by a holding arm with a small installation area. CONSTITUTION: A substrate processing device 1 performs multiple substrate processes and is provided with a substrate washing part 5, a substrate carrier robot 7 and an arm washing/drying device. The substrate washing part 5 has multiple washing tanks 12b for processing a substrate. The substrate carrier robot 7 has a holding arm 9 for holding the substrate, and carries the substrate to the substrate washing part 5. The arm washing/drying device is provided at a water washing part 5b of the substrate washing part 5 and washes and dries the holding arm 9.
Patent JP-H1173976-A (JP)
Title: Cell of solid electrolyte fuel cell and its manufacture
Inventor: YAMASHITA AKIHIRO
IPC: H01M8/02
Filed: 1997-08-29
Abstract: PROBLEM TO BE SOLVED: To provide a cell of a solid electrolyte fuel cell with low internal resistance and high power-generating capability. SOLUTION: A cell of a solid electrolyte fuel cell is formed by electrically connecting a plurality of elements comprising a fuel electrode 2, a solid electrolyte 3, and an air electrode 4 arranged on a substrate 1 with an interconnector 5, and a dense air electrode 6 of a dense structure having pores smaller than that the air electrode 4 is arranged between the interconnector 5 and the air electrode 4. Thereby, the electrical contact area of the interconnector 5 with the air electrode 4 is increased, and the electrical resistance in the contact part of the interconnector 5 with the air electrode 4 is decreased significantly.
Patent JP-H0397698-A (JP)
Title: Formation of thin film
Inventor: UEDA TORU
IPC: C30B29/06
Filed: 1989-09-08
Abstract: PURPOSE:To grow the thin film of polycrystalline Si which has large and uniform grain sizes by depositing amorphous Si on the polycrystalline Si layer laminated on a substrate, then subjecting the same to a prescribed heat treatment. CONSTITUTION:The polycrystalline Si 3 having an orientation (110) is laminated at about 100Angstrom  by a reduced pressure CVD method on the Si substrate 1 formed with an insulating film 2. The deposition temp. is kept at 620 deg.C. The amorphous Si 4 is laminated at about 1000Angstrom  likewise by the reduced pressure CVD method on the polycrystalline Si 3 at <=550 deg.C deposition temp. and thereafter, the layers are subjected to the heat treatment for about 48 hours at about 650 deg.C in an electric furnace in which an N2 atmosphere is maintained. Two layers of the Si layers form the polycrystalline Si 5 over the entire part as the amorphous Si layer 4 of the 2nd layer crystalline with the polycrystalline Si layer 3 of the 1st layer as a nucleus by this heat treatment. The thin film of the polycrystalline Si having about 1mum grain size and the uniform grain size is obtd. on the substrate 1 by the above-mentioned procedures.
Patent JP-S60117283-A (JP)
Inventor: UIRIAMU ARUDEN KUROSURANDO
IPC: G02F1/1368
Filed: 1984-11-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6390265-A (JP)
Title: Picture reader
Inventor: IWATA MASAKATSU
IPC: G03G15/04
Filed: 1986-10-03
Abstract: PURPOSE:To read both of a sheet original and a stereoscopic original by setting the moving speed of the stereoscopic original so as to make the substantially central part of the stereoscopic original coincide with the relative moving speed of the sheet original and an optical system. CONSTITUTION:The moving speed of the stereoscopic original is set so as to make the substantially central part of the stereoscopic original coincide with the relative moving speed of the sheet original and the optical system. Namely, when the center of the original of size B4 passes a reading position, the outer diameter of a take up roller 22 is set so as to have the speed of a carrying sheet 13 with a reference speed vo. The moving speed of a carrying sheet 13 coincides with the reference speed vo in a half time of a B4 reading time tB4. Accordingly, in the first half of the reading, a read picture is extended and in the second half, the read picture is compressed and the extension and compression of the read picture is not generally produced.
Patent JP-2000068488-A (JP)
Title: Semiconductor integrated circuit layout method
Inventor: SHOJI KIMIKATSU
IPC: H01L27/02
Filed: 1998-08-20
Abstract: PROBLEM TO BE SOLVED: To provide, within a short time a method of designing a semiconductor integrated circuit which assures design and manufacture thereof with small chip area. SOLUTION: An IC chip 1 is constituted of a chip peripheral part 2 and a core macro part 3. The chip peripheral part is composed of a plurality of I/O buffers 21, which are used as the interface with the IC chip and external side thereof and a plurality of pads 22 to which the bonding wires are connected. On the core macro part 3, a CPU core block 31, a peripheral block 32, a random logic block 33 and a gate array block 34 are arranged. Each block is electrically connected with metal wires. The gate array block designed by the gate array system is made into layout and designed, together with the other blocks through the standard cell system or full-custom system.
Patent JP-H1081388-A (JP)
Title: Cartridge storage case
Inventor: ARAMAKI SATORU
IPC: B65D85/57
Filed: 1996-09-04
Abstract: PROBLEM TO BE SOLVED: To retain securely a cartridge stored in a case main body and reduce the number of parts and the manhours of assembly. SOLUTION: An elastically deforming section 30 is formed integrally on an upper case 22 of a case main body 21, and a pair of protruded sections 26 are formed integrally on a lower case 23 of the case main body 21. While the elastically deforming section 30 is brought into contact with a cartridge 10 stored in the case main body 21 from the thickness direction (up and down direction in the figure) of the cartridge 10 and elastically deformed, the cartridge 10 is clamped between the elastically deforming section and respective protruded sections 26. In that case, respective protruded sections 26 are fitted into a recessed channel 11 of the cartirdge 10 stored in the case main body 21.
Patent JP-H04115317-A (JP)
Title: Electronic equipment
Inventor: SHIMADA KAZUTOSHI
IPC: G06F1/16
Filed: 1990-09-06
Abstract: PURPOSE:To attain both of an information input system based upon the input of a coordinate and that based upon a keyboard by operating the I/O face of an equipment main body by an input pen and key operation. CONSTITUTION:A transparent plastic-made push-button plate 14 has a key hole 14a through which a key top 15 is inserted from its lower part and the I/O face of the apparatus is formed on the inside of a level-difference part slightly lower than the supper face of an upper case 1 and the plate 14 is pressed into the inside of the level difference part. A key rubber sheet 16 is arranged on the lower part of the key top 15 and the sheet 16 has a symmetrical mountain-like projection par 16a corresponding to the position of the key hole 14a. A key input part is formed on the plate 14 by holding the key top 15 between the sheet 16 and the plate 14. Since coordinates can be detected by pressing an optional point on a transparent tablet 30 constituting the I/O face 3, information can be inputted by the depressing operation of the key top 15 similar to the operation of a keyboard without using an input pen.
Patent JP-H07113809-A (JP)
Title: Carriage for double-deflecting member
Inventor: JIEEMUSU MITSUCHIERU HAMONDO
IPC: G01N37/00
Filed: 1993-09-21
Abstract: PURPOSE: To perform extremely flat orthogonal motion by supporting an intermediate carriage on a base part by plural deflection members among double deflection member carriages, and supporting an inside carriage by the other plural defection members so as to be suspended under the intermediate carriage. CONSTITUTION: A double deflection member carriage 12 has a base part 24, an intermediate carriage 22, an inside carriage 26, four outside deflection members 28 and four inside deflection members 29. The carriage 22 is supported by the four members 28 so as to separate from the base part 24, and the carriage 22 and the base part 24 are respectively a parallelogram, and form a first parallelogram structure body together with the members 28. The carriage 26 is supported by the four members 29 in the shape of being suspended from the carriage 22, and the carriages 26 and 22 are respectively a parallelogram, and form a second parallelogram structure body together with the members 29. Extremely flat horizontal motion can be performed by an adjusted integral structure of this member 12.
Patent JP-H04117214-A (JP)
Title: Circular saw blade
Inventor: WASHIO KAHEI
IPC: A01D34/73
Filed: 1990-09-06
Abstract: PURPOSE:To obtain a circular saw blade having shortened redressing time and improved cutting quality and work efficiency by providing the outer circumference of a flat circular saw body at regular intervals with plurality of teeth furnished with an outer edge having a prescribed clearance angle and forming a step having a specific length at the back of the outer edge part. CONSTITUTION:The objective circular saw blade 1 for bush cutter, etc., to cut weeds, bottom grass, shrub, etc., and driven by a motor, engine, etc., has the following structure. The outer circumference of a flat circular saw body 3 is provided, at regular intervals, with plurality of teeth 5 furnished with an outer edge part 15 having a prescribed clearance angle beta and a step 17 formed by contracting the rear part of the outer circumference 15 to a distance r2 which is shorter than the distance r1 from the grinding jig attaching hole 19 formed on the saw body 3 for grinding the teeth edge 11 of the teeth 5 to the outer edge part 15 by about several mm. The grinding width l of the outer edge part 15 can be shortened by this structure to enable the shortening of the redressing time and improve the work efficiency.
Patent JP-H1078221-A (JP)
Title: Gas meter having seismoscope
Inventor: NUKUI KAZUMITSU
IPC: F23N5/24
Filed: 1996-09-05
Abstract: PROBLEM TO BE SOLVED: To estimate earth quake-induced damages without judging the seismic intensity of an earthquake and cut off a shutdown valve or treat its return work accurately responding to the degree of the estimated damage. SOLUTION: In a gas meter having at least a seismoscope which detects an earthquake larger than a specified seismic intensity and a control means which cuts off a shutdown valve provided on a gas pipeline based on the output of the seismoscope, the control means measures an earthquake generation time interval which is continuously generated. When the measured generation time interval is longer than the first time after the shutdown valve is cut off by the control valve, the control means turns the operation to a first mode which returns the shutdown valve and turns the operation to a second mode which prohibits the return of the shutdown valve when the time interval is below the first time.
Patent JP-H0896717-A (JP)
Title: Gas discharge panel
Inventor: KANEHARA TAKAO
IPC: H01J11/24
Filed: 1994-09-29
Abstract: PURPOSE: To provide a gas discharge panel having sufficient brightness without dispersion in intensity of emission. CONSTITUTION: In a gas discharge panel, a stepped difference is provided between an upper surface in a side of a dielectric layer 21 of an X electrode 15 and an upper surface 21 similarly in a dielectric layer side of a Y electrode 17, on a back substrate 11. The electrode in either one of this X electrode 15 or Y electrode 17 is provided on the substrate, and the other electrode is provided in a groove 13 provided in the substrate 11. Here is set the groove 13 to a depth larger than a thickness of the other electrode. Further, a distance in a direction of arranging the electrodes, between the one electrode and the other electrode, is set to 0 (zero).
Patent JP-H04114487-A (JP)
Title: Visible ray semiconductor laser and manufacture thereof
Inventor: KIMURA TATSUYA
IPC: H01S5/00
Filed: 1990-09-04
Abstract: PURPOSE:To protect the surface of a crystal layer against oxidation and defects so as to remarkably improve the growth of the crystal layer in yield by a method wherein the crystal layer is manufactured through a single crystal growth process and an impurity diffusion process. CONSTITUTION:An N-GaAs substrate 1, an N-AlGaInP lower clad layer 3, an undoped GaInP active layer, a P-AlGaInP upper clad layer 5, an undoped AlGaInP/GaInP superlattice layer 6, an undoped GaInP band discontinuity relaxation layer 7, and an undoped GaAs contact layer 8 are successively laminated on an N-GaAs substrate 1. In succession, an SiNx layer 11 specified in width is formed in a stripe on the undoped GaAs contact layer 8, and impurities of Zn are diffused in vapor phase using the SiNx layer 11 as a mask so as to reach to the P-AlGaInP upper clad layer 5. Impurity diffused regions 91, 92, 93, and 94 of the undoped GaAs contact layer 8, the undoped GaInP band discontinuity relaxation layer 7, the undoped Al GaInP/GaInP superlattice layer 6, and the P-AlGaInP upper clad layer 5 where Zn is diffused are turned into P-type conductivity type. The impurity diffusion region 93 is disordered into a P-Al GaInP layer of quaternary mixed crystal.
Patent JP-S63159327-A (JP)
Title: Compatibility increasing method
Inventor: JIYAAKU BARUBE
IPC: A61K47/00
Filed: 1987-09-18
Abstract: Immunological reagents, consisting of a) antibody or fragment conjugates having both an anti-cell specificity and an anti-hapten specificity, and b) synthetic tracers containing at least two hapten sites and at least one site suitable to attach radioactive isotopes, paramagnetic ions, drugs, or toxins, are provided. These reagents are capable of binding to target cells in a specific way, and the tracer localizes preferentially on the membrane of antigen-bearing cells, even in the presence of excess antibody conjugate (affinity enhancement). These reagents are usefully employed, either in vitro or in vivo, to detect tumors, metastases, or other tissue injuries, when the synthetic tracer carries radioactive or paramagnetic compounds, and to kill target cells when the synthetic tracer carries radioactive compounds or drugs or toxins.
Patent JP-H0283426-A (JP)
Title: Fluid pressure detector
Inventor: UCHIDA YOKO
IPC: G01L19/12
Filed: 1988-09-21
Abstract: PURPOSE:To reduce not only the installation space of the title detector but also cost by arranging a diaphragm for measuring the fine pressure variation of a fluid in the fluid to receive the same in the same container of a fluid pressure detection part. CONSTITUTION:A partition membrane 33 is arranged to the other terminal part of gas piping to divide a gas part and a liquid part 34 composed of oil or the like and a diaphragm 35 is arranged to the end part of said piping 32 and a piezoelectric resistor element 36 is mounted to the outside surface of said diaphragm 35. A part of a partition wall 95 is constituted of a diaphragm 33 for measuring the pressure of a fluid and a diaphragm 90 for measuring the fine pressure variation of a liquid and, since a fine hole 92 is provided to the diaphragm 90, the diaphragm 90 generates no deformation to gentle pressure variation. Therefore, stationary or quasi-stationary fluid pressure is applied to the diaphragms 33, 35. When the pressure wave of the impact gas generated in the earth reaches the diaphragm 90, the diaphragm 90 is deformed and output is generated in a pressure sensor 91.
Patent JP-H04114511-A (JP)
Title: Cmos inverter
Inventor: OGATA KATSUHITO
IPC: H03K19/0948
Filed: 1990-09-05
Abstract: PURPOSE:To suppress the generation of noise without increasing the power consumption of a logic circuit by providing an output voltage level guarantee circuit in parallel to an inverse speed control circuit. CONSTITUTION:Since the current supply capacity of an N-channel MOS transistor Q3 is much larger than that of a P-channel MOS transistor Q4, a load circuit is mainly driven by a current supplied from the N-channel MOS transistor Q3 in an initial stage. The potential of the high level of an output signal rises to the potential (VDD-VTN) dropped from a power voltage by the threshold value voltage of the N-channel MOS transistor Q3 by the operation. Since the N- channel MOS transistor Q3 comes to an off state a small current flows only in a P-channel MOS transistor Q4 and the potential of an output terminal is gradually raised. Thus, the generation of noise can be prevented without increasing the power consumption of the logic circuit.
Patent JP-S59114453-A (JP)
Title: Method and device for measuring speed of explosion of gas medium
Inventor: MOORISU BUTONA
IPC: G01N25/54
Filed: 1983-12-13
Abstract: A method and a device for determining explosivity rate of a gaseous medium with a detecting filament which is heated in said medium by an electric current flowing therethrough. Said detecting filament is ignited through connection to a power supply and power supplied to said filament is regulated so as to maintain constant the resistance thereof. At some successive moments value of a quantity U significant for power supplied to said filament is taken into account. An exponential curve is extrapolated from such values; parameters thereof are identified and introduced in a process function adapted to deduce therefrom an estimation of the initial explosivity rate of said gaseous medium independently of the nature of the explosive gas(es) present therein.
Patent JP-H1081922-A (JP)
Title: Method for melting incineration residue of waste
Inventor: NAKAO TSUYOSHI
IPC: C22B13/00
Filed: 1996-09-05
Abstract: PROBLEM TO BE SOLVED: To recover heavy metals contained in an incineration residue of waste as metals by adding a carbon component to fused slag to reduce the heavy metals contained in the slag and recovering reduced heavy metals in a method for melting the incineration residue of the waste containing heavy metals. SOLUTION: The incineration residue of the waste such as trash is charged inside a furnace main body 2 composed of carbon brich from a charging port 10 at an upper part of an electric resistance system fusion furnace 1 to pile them on a covering layer 4. Thereafter, the incineration residue is melted at about 1500 deg.C by Joule heat generated between electrodes 3 to form a molten slag layer 5. Carbon bars 9 as a reducing agent are inserted in the slag at three points to metallize metallic components (oxides) in the slag by reduction and the reduced metals precipitate to a furnace bottom by gravity difference between the metals and the slag to form a metal layer 6. Further, fine carbon powder in place of the carbon bar 9 may be charged to the molten slag layer from a charging port different from the incineration residue charging port.
Patent JP-H10224376-A (JP)
Title: Path designation switch for digital signal two-way transmission
Inventor: SIMPSON ROBERT
IPC: H04L12/56
Filed: 1997-08-29
Abstract: PROBLEM TO BE SOLVED: To obtain a path designation switch especially applicable to an ATM switch and system. SOLUTION: A 1st type obtains consistency of cell transmission and accepts a variable bit transmission speed, and a 2nd type accepts some loss of a transmission cell. Each input cell is decided to be the 1st type or the 2nd type and when the capacity reaches a prescribed threshold level for a 1st buffer capacity, each input cell of the 1st type is loaded in the buffer and a state of selecting a flow control signal is set to block the input of cells of the 1st type. When the number of cells of the 2nd type in the buffer does not reach a prescribed threshold level, each input cell of the 2nd type is loaded in the buffer or the input cells reach a prescribed threshold level, each input cell of the 2nd type is aborted through the operation of control circuits 39, 40, 41.
Patent JP-S6297488-A (JP)
Title: Intersystem connection system
Inventor: KISHIGAMI TAKASHI
IPC: H04Q3/58
Filed: 1985-10-23
Abstract: PURPOSE:To attain an efficient intersystem connection by connecting key telephone systems with each other through extension lines, and performing the supervisions of the key telephone system and calls with each other using the key telephone system. CONSTITUTION:Key telephone systems 21 and 22 are connected with each other through one extension line among plural extension lines respectively and an intersystem connection equipment 27. The intersystem connection equipment 27 is equipped with two CPUs and a latch circuit corresponding to the key telephone systems 21 and 22, and enables the key telephone systems to perform a data communication between them by polling, and transmits and receives mutually the bits of information regarding in what state the key telephone systems are (whether in busy or not, or whether a call is requested or not, or whether the state of a power source is in normal or abnormal), and realizes the efficient intersystem connection eliminating the deviation between states of the key telephone systems.
Patent JP-H1079069-A (JP)
Title: Stopper device for coin mechanism part at automatic teller machine
Inventor: WATANABE HIROSHI
IPC: G07D9/00
Filed: 1996-09-05
Abstract: PROBLEM TO BE SOLVED: To miniaturize the cabinet of an automatic teller machine. SOLUTION: At a stopper device for the automatic teller machine, the fitting position of a stopper member 21 at the side face of a coin mechanism part 4 is made rear compared with an abutting surface with the front end surface of a supporting plate 6a. In addition, the member 21 is concretely constituted of a fixing piece and a stopper piece in a state orthogonal with it and is arranged to fix the fixing piece to the side surface of the part 4 and to abut the inner surface of the stopper piece on the surface 6a. In addition, the position of the stopper piece with respect to the part 4 is made adjustable by varying the fixing position of the fixing piece.
Patent JP-H1079514-A (JP)
Title: Method for manufacturing active matrix board
Inventor: IMAI NOBUO
IPC: H01L29/786
Filed: 1996-09-05
Abstract: PROBLEM TO BE SOLVED: To improve productivity by reducing manufacturing processes for an active matrix board which drive-controls a pixel electrode of a TFT(thin-film transistor) and to obtain good on-current with the TFT, while eliminating parasitic capacitance for application to a large liquid crystal display device of high precision. SOLUTION: In a TFT 17 of a positive staggered structure, a light-shielding film 28 is formed of an insulating light-shielding member, and offset areas are formed between a gate electrode 40 and a source electrode 33, and between the gate electrode and a drain electrode 34, respectively. With the gate electrode 40 as a mask, an exposed a-Si film 36 is doped with ion, and laser-annealed, for obtaining a low resistant n-type polycrystalline silicon 37. A short ring 43 is pattern-formed with the same mask as the gate electrode 40.