Patent GB-1132284-A (GB)
Title: Memory for a coherent pulse doppler radar
IPC: G01S13/532
Filed: 1966-02-17
Abstract: 1,132,284. Data storage. INTERNATIONAL STANDARD ELECTRIC CORP. 17 Feb., 1966 [17 Feb., 1965], No. 6970/66. Heading G4C. [Also in Division H4] The Specification describes a multiple matrix storage unit comprising, Fig. 1, p planes, each N having N = 2<SP>r</SP> lines - columns (where r is a 2 positive integer greater than zero), each said plane being divided notionally into two substores P and Q of N/2 lines each according to the parity (even or odd respectively) of the lines, and having an individual storage element at each cross-point of a line and a column, whereby p-digit binary signals may be stored, one digit to a plane; a separate access selector 6 and 5 for the lines of each sub-store, and a single access selector 7 for the columns of each plane; clock pulse generator means H (not shown) and O to provide selection signals PL, Pi and QL, Qi and A, B for driving the said access selectors to enable a specific storage element to be selected for storage of a signal digit therein or reading of a signal digit therefrom, and also to provide a controlling pulse T defining a repetition period for the operation of said storage unit; means 1, 2 for writing digits into the storage elements of each said sub-store, line-by-line, independently for each sub-store, means 3, 4 for reading destructively digits stored in the storage elements of said storage plane column-by-column; a control circuit 8 for each said storage plane under the control of said clock pulse generator and said controlling pulse for controlling the storage of incoming signal digits into said planes, and the reading of stored signal digits from said planes in alternative phases of operation during each repetition period, and including also control means (acting on gates 43, 44 with signal W) for effecting rewriting of a specified group of signal digits read out from the storage elements into those elements during a specified portion of the reading phase of the repetition period, whereby storage, reading and rewriting take place during one repetition period of said storage unit (and considering one plane only of said unit, conditions being identical for all said planes) in the following sequence: (phase 1) storage of digits in the line 2n-1 of the odd-line sub-store (n being a positive digit equal to, or less than, 2<SP>r</SP>). (phase 2) reading of digits from the column 2n -1 (modulo 2<SP>r-1</SP>) starting at the line 2n, progressively through odd and even lines, the storage elements, for the first N/2 lines being read without re-storage of the digits read therefrom, while the storage elements of the succeeding   (and final) N/2 lines are read with substantially immediate re-storage of the digits into the same storage elements; the procedure during the next repetition period being similar except that storage in phase 1 commences at the line 2n of the even-line sub-store, while reading (in phase 2) takes place from column 2n (modulo 2<SP>r-1</SP>) commencing at the line 2n + 1; and so on for alternate repetition periods. Each said access selector 5, 6, 7 comprises, Fig. 2, an N/2 position binary counter identifying a line (or a column, as the case may be) of the associated storage plane; and said control circuit 8, Fig. 3, comprises bi-stable elements, an N-position binary counter 20 and logic gates; a first bi-stable G thereof responding to said controlling-pulse T; a second bi-stable S responding to an " end-of-writing " signal A at the end of the line in which storage has been taking place, and defining the end of phase 1; a third bi-stable X controlling, by its initial positions in the particular repetition period, which of the said alternative sequences of operations will be performed in the said repetition period, and which, after the response of the said second bi-stable S responds in phase 2 alternately to successive clock pulses 4 to cause the reading in order of successive odd and even storage elements of the column selected for reading; a fourth bi-stable W responsive to a signal 6 from said N-counter 20 indicating " end-of-reading-without-rewriting " when the first N/2 storage elements of said selected column have been read, so as to provide a signal W to control re-writing of the digits read from the last N/2 storage elements back into their storage elements; said N-counter providing a second signal C when all N elements of the selected column have been read in order to reset said bi-stables G, S and W and said N-counter to the initial conditions; and means responsive to said " end-of-writing " signal A to control transfer to the counter of said column access selector of a number related to the number of the line then indicated (at end-ofwriting) by the counter of said access selector of the even-line sub-store and modified by a signal indicative of the state of said bi-stable X, thereby to define the number of the column selected for reading in phase-2.