Patent GB-1352987-A (GB)
Title: Secondary radar system for target identification
IPC: G01S13/78
Filed: 1972-09-14
Abstract: 1352987 Secondary radar; transponders INTERNATIONAL STANDARD ELECTRIC CORP 14 Sept 1972 [14 Sept 1971] 42623/72 Headings H4D and H4L A secondary radar system includes (a) an interrogator transmitting interrogations at a primary radar p.r.f. comprising at least two pulses P 1 P 3  enclosing at least one further pulse, the number and timing of such further pulses defining interrogation modes and (b) a number of transponders each capable of deciding at least one interrogation mode and replying with a delay t a  after the pulse P 3  of the pth received interrogation where p is individual to each transponder. In order to avoid overlapping of coded reply pulse trains from adjacent transponders within the radar beam width the interrogator transmits a cycle of interrogations including (a) a single synchronizing code, (b) a number (e.g. 16) of repetitions of a single interrogation code, (c) a single standard interrogation (e.g. IFF). Each transponder includes a counter preset to N-p which is enabled by decoding of code (a). After decoding of the pth code (b), a delay t a  ensues, followed by transmission of a coded reply signal. Interrogator, Fig. 7.-Interrogation codes generated in encoder IX are modulated on to a UHF carrier in transmitter 43 and are passed via switch 45 to an omni-directional antenna 46 for side lobe suppression and to a narrow beam antenna 47 whose main lobe rotates (actual or simulated). Received replies are detected in a gated receiver 48 and defruited. Decoding circuits 51 provide the encoded information to a PPI display 52 to identify targets. Generator 41 provides pulses of period T s  (the primary radar prp) and the leading edges of the square wave are synchronized with the primary radar pulses. The trailing edge of a sync. pulse operates bistable 53, enabling via OR gate 57 bi-stables 66, 61. 20 MHz pulses from clock 65 are divided by twenty by bistable 66 and divider 67 to provide 1Ás pulses to counter 68 which is preset to a value 48. After 80 clock pulses all the counter outputs fall to zero thereby setting bi-stable 61. The output of OR gate 63 now drops to zero sending an interrogation enable pulse to encoder IX. After a further 30 clock pulses all the counter outputs become high. NOR gate 73 is thus turned on enabling gate 74 whose output resets divider 67, resets bi-stables 53, 55 and resets counter 68 to 48. OR gate 57 now resets bi-stables 66 and 61. OR gate 63 now turns on removing the interrogation enabling pulse. At bi-stable 56 the change in the output of gate 74 causes the receiver 48 to be gated open. When the leading edge of the sync. pulse occurs bistable 55 is triggered via inverter 54. The counter 68 row operates as before but since gate 63 is held on by the Q output of bi-stable 53, no interrogation enable pulse is produced. After the 110 pulses have been counted bi-stable 56 is triggered removing the receiver gating signal. Thus receiver 48 is enabled only during the half-cycle following the transmission of pulse P 3 . Outputs 70A-70D, 71, 72 provide a binary number representing the time elapsed during the interrogation period which is used in encoder 1X to form the interrogation codes. The eighteen code cycle is controlled by counter 77 which counts interrogation codes and supplies one of three signals from OR gates 78, 79, 81 according to the count. A negative edge from gate 78 sets bi-stable 86a and resets 86c. This enables the synchronizing code memory 85a. At the next interrogation pulse 86a is reset and 86b set enabling memory 85b or 85c according to the position of switch 87. After a further sixteen pulses the IFF memory 85d is enabled and the cycle repeats at the next interrogation pulse. The memories 85a-85d supply thirty-two inputs to cascaded multiplexers 83, 84, representing the desired code. As the outputs 70A-70D, 71, 72 from counter 68 change, the inputs D 0 -D 15  of the two multiplexers are sequentially applied to the outputs W which pass via NOR gate 88, quantizing gate 89 (when the interrogation enabling pulse is present) to transmitter 43. Transponder, Fig. 6.-Received pulses pass from terminal 1 to set bi-stable 2, this applies an input to shift register delay line 3 which due to feedback from the first three elements via AND gate 4 passes a three-bit length pulse therealong. Outputs from the delay line feed gates 5s, 5y, 5x at points representing the P1-P3 spacing of the synchronizing and two interrogating codes. The second input to the gates comes from the receiver input 1. When the synchronizing code M 8  is recognized, the output from gate 5s sets bistable 15s which sets counters 18x, 18y to N-p. Also bi-stable 15s is reset via gate 17s and memory 34s is enabled through gate 20s. The next codes to be received will be either Mx or My. If Mx is received date 6x sets bi-stable 15x and counter 18x is advanced by one. Bi-stable 15x is reset through gate 17x. Each time a code Mx is received counter 18x advances until it reaches N. This turns on gate 20x enabling the memory 34x. Gate 20x also sends a pulse through NOR gate 22 to enable register 8 through bi-stable 9. Since this enabling of register 8 coincides with the pulse P 3  of the pth code bi-stable 7 is set by input 1 allowing a pulse to pass along the register 8 which produces a delay t a . The delayed output from register 8 sets bi-stable 12 which enables divider 13 which sends timing pulses for the reply code to encoder V. After a time slightly longer than the reply time period monostable 23 (triggered by gate 22) resets bi-stables 9, 12, resetting divider 13 and disabling counter 8. Thus since gate 22 is enabled by a pulse indicating recognition of a single synchronizing code or p interrogation codes, timing pulses for the appropriate reply code are produced after a delay t a  from the pulse P 3 . In the reply encoder V, the memories 34x, 34y, 34s feed NAND gates 35, whose outputs set the individual stages of a register 36. When the clock pulses are supplied from divider 13 register 36 feeds the appropriate reply code through quantizing gate 37 to the reply transmitter 38. If the transponder is situated such that it can receive more than one interrogator, recognition circuit III operates a second counting device IV or an alarm 33. Any received code supplies a pulse through NOR gate 28 to counter 29 and the clock inputs of bistables 31-1, 31-2, 31-3. Counter 29 is reset by a clock 30 which has a period equal to the interrogating station repetition period. The first pulse decoded triggers bi-stable 31-1 since gate 30-1 is enabled, the counter content being zero. This enables the gates 16x, 16y, 16s in the first counting device II. If a second pulse is received before the counter is reset, bi-stable 31-2 is triggered since the counter content is now one. This bi-stable enables gates 16<SP>1</SP>x, 16<SP>1</SP>y, 16<SP>1</SP>s in the second counting device IV which operates in the same manner as the first device II. If a third decoded pulse is received bi-stable 31-3 is enabled activating an alarm 33. Specification 1,305,683 (Division H4) is referred to.