Patent GB-789096-A (GB)
Title: Drive current generator for memory arrays
IPC: G11C11/06
Filed: 1955-07-01
Abstract: 789,096. Electric digital-data-storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 1, 1955 [July 2, 1954], No. 19065/55. Class 106 (1). [Also in Group XXXIX] In an arrangement permitting repetitive readout of information stored in a magnetic core memory matrix, Fig. 2, binary information from decoding units 11X, 11Y, for example crystal diode matrixes, is transmitted to the memory through driver units 12X, 12Y, Fig. 3, which function as temporary registers and comprise groups of bi-stable magnetic cores 30 each controlled in opposite respects by input and write windings 32, 33 and provided with output windings 34. Read-out of recorded information in the memory is effected by selectively pulse-energizing an input winding 32 in each driver unit over a valve or transistor 38 which has its cathode potential stabilized by a diode 40 and resistor 41. As a result, the magnetic condition of the associated core 30 is reversed from state b to state a and coincident induced pulses in the output windings of the two driver units drive the selected memory core 10 to binary zero state b. If a binary one is stored in core 10, reversal of its magnetic state induces a pulse in a read-out winding 20 which extends through all the memory cores in such a way as to minimise spurious induced voltages, and the write windings 33 in each driver unit are pulses simultaneously over valves 36. The selected cores 30 change over from state a to state band produce coincident output pulses which restore the memory core to the binary one condition. If, however, a binary zero is stored in core 10, the absence of a voltage in the read-out winding causes the write windings of the two driver units to be pulsed non-coincidently. In this case cores 30 are restored to state b without effect on the memory core which remains in the binary zero condition. To record new information, the memory is interrogated as previously described but the control circuit between the read-out winding 20 and the write windings 33 is disabled. The write windings are then pulsed non-coincidently which causes the interrogated memory core to be left in its binary zero state b whatever its original condition. The new information is then entered in the memory from the decoding units by a further input and write operating cycle of the drive units which in this case are coincidently pulsed. The drive units may be modified by the provision of windings 60, Fig. 5, inhibiting the write windings, and may be employed in a system for recording binary words comprising a stack of matrixes A, B-N, Fig. 4. The binary information is applied to the memories from decoding units 52, 55 over driver units 50 and 53A, 53B-53N having a common write-pulsing circuit 46. To read a selected word line in the memory, all the driver units have a core 30 pulsed simultaneously and produce coincident interrogating pulses in each matrix as previously described. The memory cores in the selected column are all driven to the binary zero magnetic state, and separate outputs are obtained from each matrix in read-out windings 20a, 20b-20n which are individually associated with the inhibiting windings 60 over valves 61A, 61B-61N. When the write windings are subsequently pulsed over circuit 46, a binary one condition is established in each and every core in the word line unless the response of any particular drive unit is inhibited by pulse energization of its winding 60 for a period in excess of the change-over time of the selected core 30 in driving unit 50. As a result, coincidence of output pulses to the associated matrix is destroyed and a binary zero is written into that part of the word line. Restoration of an inhibited core 30 in any driving unit 53A, 53B-53N is subsequently ensured by continuance of the write pulse after the inhibiting pulse terminates. Specification 766,189 is referred to.