Patent GB-1328061-A (GB)
Title: Data processing system
IPC: H03M7/42
Filed: 1972-01-07
Abstract: 1328061 Data processing systems INTERNATIONAL BUSINESS MACHINES CORP 7 Jan 1972 [8 Feb 1971] 767/72 Heading G4C To convert a variable-length (VL) coded bit stream into a fixed length code, a number of VL bits are entered into a first register to form an address to read-access a first memory containing a fixed length code. The VL code is preferably a modified Huffman code in which the code length chosen to represent each character is an inverse function of the probability of occurrence of that character, each VL code being such that it does not form a prefix of any other VL code, and the first N bits of VL codes of more than N bits form a prefix representing the length of that code, though more than one N-bit prefix may represent the same code length. In the embodiments described, the decoding procedure has three main features; (1) A VL code of not more than N bits reads out from a corresponding address in the first memory a word having a fixed length output code (ID) field and a control field representing the length of the VL code for controlling the shifting of the first, address register to leftjustify the next VL code of the bit stream. (2) The first N bits of a VL code having more than N bits address the first memory as in (1), but in this case the ID code read out forms a base address for a second memory, and the control field represents the number of bits by which the VL code length differs from N to control shifting of the ID base address by this amount (to the left (and entry of the remaining VL code bits as a displacement, the resulting address causing read-out from the second memory of the output ID code. (3) The VL code representing a character is dependent on the identity of the preceding character, and to decode such (dependent) codes, the ID code resulting from an independent decoding process as in (1) or (2) is used as part of an address for a third memory containing the output ID codes, the remainder of the address (most significant part) being derived from the output ID code of the preceding character. Detailed operation.-Independent decoding. A byte counter (50) is loaded from an input device according to the number of bytes in the VL stream. Decoding stages (1) and (2) are performed by primary and secondary processors under the control of pulse trains P, S produced by chained single-shot circuits, Figs. 15, 16 (not shown). P1 sets the length counter field L of the data register (20) of the first memory (12) to 7 to count the entry of a byte into the address register (10) of memory (12) under control of P2-P5. Pulse P6 causes a read-access of memory (12) at the address indicated by register (10) and decrements the byte counter (50). For a VL code of less than byte length there are a number of addresses containing the same corresponding ID code and control field since only the higher level bits of the byte-length address are relevant to that VL code. P7, P8 test for completion of the read-access continuously. P9 tests the C field of the memory data register (20) to determine whether the VL code is of more than byte length. If it is not, P10, P11 continuously repeat until the secondary processor has completed a previously initiated operation. P12 gates out the ID code from the data register (20) to an output device, P13 tests that the byte counter is not at 0, and P14-P17 repeatedly shift the address register one bit left, enter a new VL code bit and decrement the length field L of the data register (20) until the next VL code has been left justified in ths address register (10). The process then repeats from P6. For a VL code of more than byte length, the procedure is the same as above up to P9, but now the C field indicates a second decoding stage is required and a jump to P18, P19 is made to detect when the secondary processor is free. P20 gates the ID code from data register (20) to the address register (24) of the second processor and sets its busy status flip-flop. Pulses S1-S4 repeatedly shift address register (24) to the left, enter the next bit of the VL code and decrement the L field of the data register (20) until the remaining L + 1 bits of the VL code have been entered in register (24). S5 tests that the byte counter (50) is not 0 to initiate a new primary processor operation while S6 causes a read-access of the second memory (26) at the combined address indicated by its register (24). S7, S8 test for completion of the read-access, S9 gates out the ID code from the second memory data register (28), and S10 resets the secondary processor busy status flip-flop and tests the byte counter to produce an end of program signal if it is zero.  Detailed operation.-Dependent decoding. Steps P1-P9 are the same as in the independent operation, P10, P11 test that the secondary processor and a further, dependent processor are not busy. Assuming a VL code ofless than 9 bits, P12 gates the ID code from the primary processor data register (20) to the lowest bits of the dependent processor address register (314), sets the dependent processor status flip-flop and initiates operation of the dependent processor. For VL codes of more than byte length, P9 initiates S1-S6 as before, S7, S8 test that both the secondary and dependent processors are not busy, S9 gates the ID code from register (28) to register (314), and S10 resets the secondary processor status flip-flop, sets the dependent processor status flip-flop and initiates operation of the dependent processor which proceeds through steps D1-D2 as follows: D1 causes a read-access of the dependent processor memory containing a decoding table, at the address in register (314). D2, D3 test for completion of the read access. D4 gates the final ID code from the data register (352) and causes a read-access of a second table containing group codes 0-2 according to whether the ID code represents a vowel, a non-alphabetic character or a consonant. The group code is read into the high order bits of the address register (314) to form part of the address for the next VL code. D5, D6 test for completion of the group table read-access, and D7 resets the status flip-flop and tests the byte counter to produce an end of program signal if it is at 0.