Patent GB-786514-A (GB)
Title: Improvements in adders
IPC: G06F7/491
Filed: 1955-03-02
Abstract: 786,514. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION, March 2, 1955, [March 5, 1954], No. 6190/55. Class 106 (1). An electrical adder of the subtractive type for subtracting the value of one digit representation (the subtrahend) from the value of another (the minuend) previously supplied to the adder, comprises an input translator for converting each digit representation into a representation of its even component and an odd-even indication of the value of the digit, a minuend register for storing the even component representation of the minuend, a subtraction table device for producing an output in response to and representative of the difference between the values of the even component representations of the minuend and the subtrahend, and adjustment circuits for modifying said output to produce the correct answer under control of carry signals and the odd-even indications of the subtrahend and minuend. As described, the adder-which is basically a subtractor-forms part of a unit, Fig. 1, which could be the arithmetic unit of a general purpose computer, and which contains two main registers, a cyclical twenty-decimaldigit " arithmetic revolver " being part of a track on a magnetic drum and having the adder in its circulation path, and a ten-decimal digit " factor shifter " being a flip-flop stepping register having provision for cyclic shift. Data entering or leaving the unit from or to either the computer store or a record card reader/ puncher, always does so via the factor shifter, from where it is passed serially, for any desired number of times, to the adder, forming the subtrahend entry thereto. Addition is performed by complementing the subtrahend before entering it into the adder, multiplication by simple repeated additions alternated with denominational shifts, and division by simple repeated subtractions alternated with shifts and the " adding-back " of the number being subtracted. The card input equipment is as described in Specification 728,272 which is referred to. In the factor shifter each decimal digit is registered on seven flip-flops by a code shown in Fig. 11, which also shows the card punching code. In this chart the first four bits-a tetrad-of the seven bit code appear in the extreme right-hand column, and represent decimal numbers in an excess three code, the next two bits-a dyad-appear in the extreme bottom row, their main function being to indicate the sign, if any, of a number, and the last bit-a parity redundant bit-appears alongside each number. For example, the number 3 (unsigned) is represented as 0110001, the number +3 (or C) as 0110010 and - 3 (or L) as 0110100. Multi-digit decimal numbers in this code are transmitted serially by digits and parallel by bits, only the units denominationcoming first-being signed, the remaining digits being unsigned. Thus the dyad of the units denomination of a multi-digit decimal number determines the sign of the number. Adder. The adder, Fig. 9N, has one five-wire input lead 1012 to which is applied in serial interlaced form the tetrad and redundant bits of the digits of the minuend and subtrahend, the units digit of the minuend coming first. In respect of the units digits of the minuend and subtrahend, which are the only signed digits, means are provided for complementing the redundant bit before it enters the adder. Thus all digits entering the adder have redundant bits corresponding by the parity of the tetrad bits. The main units of the adder are an input translator, which translates incoming digits into an odd-even bi-quinary code, a subtraction table which subtracts the even components of two digits one registered in a minuend register and the other (the subtrahend) in the input translator, and an adjusting network comprising a 2-step adjuster which either passes a digit applied to it unmodified, or if a lead 1066 is marked, subtracts 2 from a digit passed by it, and a 1-step adjuster which either passes a digit unmodified, or if lead 1076 is marked, adds 1 to it, and which provides in a one out of ten code the current digit of the subtraction, any carry digit being stored in a ten-stage binary counter which also controls the adjusting network. The operation of the adder for any one denomination occurs in the following stages: (a) first the units digit (say 5) of the minuend is staticized on flip-flops in the input translator where it is converted into a bi-quinary odd-even code by a crystal diode matrix-in this code one lead of five leads weighted 0, 2, 4, 6 and 8 is marked (lead 4) together with one lead of two leads weighted 0 (even) or 1 (odd) (lead odd); (b) secondly, on the arrival of a III pulse, which always occurs between the arrival of corresponding digits of the minuend and subtrahend, the even component (4) of the minuend is registered on a flip-flop minuend register and the odd-even component is sampled at a gate 1094 causing a two-stage binary counter, which stores interdenominational carries, to advance or not (the counter remains in its initial state, say 00) ; (c) thirdly, the units digit (say 7) of the subtrahend is registered in the input translator and the subtraction table (a diode matrix) provides the difference of the even components of the two units digits together with a carry or nocarry (4-6=8 and carry 1); (d) fourthly, the odd-even component of the subtrahend is sampled by a D pulse at a gate 1092 and the binary counter further advanced if necessary (counter advances to 01); (e) the output of the 1-step adjuster, representing the required difference (8) is passed to an output converter (not shown) for conversion into a tetrad group of bits and a redundant bit; and (f) finally an E pulse clears the input translator and the minuend register and sets the binary counter to register whether or not there was a carry (counter set to 01). The adder is now ready to receive the next digits of the minuend and subtrahend. The adder has several modes of operation including a " Dim " mode, in which the number in the factor shifter, irrespective of sign, is subtracted from that in the arithmetic revolver, and " Aug mode in which the numbers in the factor shifter and arithmetic revolver are added, irrespective of sign, this being achieved by entering the nines complement of the number in the factor register into the adder (as the subtrahend) together with a " forced carry," and an " Idle " mode in which zero is continually subtracted from the number in the arithmetic revolver. The particular mode in which the adder operates is determined by control circuits, Fig. 1, which would themselves normally be controlled by the programme unit of a computer, and which enable the four basic arithmetic operations, addition, subtraction, multiplication and division to be performed, each operation taking into account the signs of the numbers involved. For each operation the adder is caused to go through a particular sequence of modes, for example, if a subtract (or add) operation is specified then first a resultant operation has to be determined; this is a sum if the sign of the arithmetic revolver is the same as the product of the signs of the factor shifter and the specified operation (addition having a positive sign and subtraction a negative sign) and otherwise is a difference. In both cases the number resulting after the addition or subtraction is initially given the sign of the number that was in the arithmetic revolver, but if a carry results from the highest denomination this sign number, together with theresult number, is complemented. For multiplication the digits of the multiplier, registered in the arithmetic revolver, are taken in turn, units denomination first, and registered in a digit counter where they control repeated additions of the multiplicand, which is in the factor shifter, to the second half of the arithmetic revolver register. An example of multiplication using a 5-digit factor shifter and a 10-digit arithmetic revolver is shown in Figs. 30A, 30B, which should be read from right to left. The first digit position of the arithmetic revolver is marked by a marker pulses and the sixth position (the beginning of the 2nd half) by a b pulse. Shift, in the arithmetic revolver is effected by altering the timing of the a and b marker pulses, the actual circulating path of the arithmetic revolver being of a fixed length. Shift is thus cyclic. Commencing at the lower right-hand end of Fig. 30B, the adder is operating in an Idle mode. At the first a marker pulse after a start signal, when a step counter is set to zero, the units digit 4 of the multiplier is transferred to the digit counter and the adder operates in a clear mode, clearing the units digit from the arithmetic revolver. During the period carry is suppressed. At the first b marker pulse the multiplicand (subtrahend) is added to the arithmetic revolver, there being a forced carry. This is followed by a " Pad " mode, during which nines are subtracted from the arithmetic register, and then by an Aug mode, successively until the digit counter is stepped to zero, when the step counter is advanced to 1 and the next a marker pulse is delayed by one digit, effectively shifting the contents of the arithmetic register one denomination in the direction of decreasing significance. This process is continued until the step counter reaches 5 (shown as 0 since the counter only counts up to 5) when the adder reverts to its Idle mode. In division the digit counter is initially set to 9 and stepped down by one for each subtraction of the divisor, in the factor shifter, from the dividend in the arithmetic revolver until carry from the highest denomination occurs when the multiplicand is added back once, the contents of the arithmetic revolver are shifted one denomination in the direction of increasing significance (the a marker pulse comes one digit earlier) and the number in the digit counter is subtracte