Patent GB-1153822-A (GB)
Title: Apparatus for Storing Electrical Pulses
Inventor: LAVIRON EDOUARD
IPC: H03K5/22
Filed: 1966-09-01
Abstract: 1,153,822. Recording electrical pulses. COMMISSARIAT A L'ENERGIE ATOMIQUE. Sept.1, 1966 [Sept.1, 1965], No.39142/66. Heading G1A. [Also in Division G4] A chain of random pulses are stored first in a buffer store before being distributed at a slower rate and according to their arrival times in the original pulse chain, to the channels of a multichannel analyser, discriminator or store for recording or counting purposes. This operation has application in the classification of pulses produced at a time-of-flight base, comprising a particle accelerator pulsating at 150 particle bursts per second and a scintillator-photo-multiplier system delivering a chain of pulses for each particle burst detected. The time distribution of' each chain of pulses is then stored by the buffer store to an accuracy of 10ns. Pulses d from the photo-multiplier occurring at intervals greater than 10ns, are shaped by a unit D, Fig. 2, into square wave form e, of width between 5 and 10ns. A distribution unit F is started by clock G which itself receives a start pulse from b. Those pulses occurring in the first 80ns are fed by the unit D to an 80ns delay line E 1  and in the second 80ns to 80ns delay line E 2 , This sequence is repeated throughout the time of a particle burst. The delay lines are sampled at points x spaced apart at 5ns intervals, Fig. 3 (not shown), and if square waves are detected at any points x, signals are gated through the corresponding ones of transmission gates Q 1 -Q 16  and Q 17 -Q 32  to switch the corresponding ones of trigger circuits H 1  -H 16  and H 17 -H 32  to their ONE state. A logic circuit J is provided to eliminate superfluous information, e.g. when two consecutive trigger circuits H record the presence of the same squarewave in a delay line. The output of this logic circuit is provided from 16 OR gates M 1 , M 3 . . . . M 31  each of which yields a pulse if a pulse d has occurred in the corresponding 10ns period during the first 160ns. At the end of this 160ns period, the information stored in triggers H 1  -H 32  can be transferred to the buffer store B. The buffer store is a magnetic thin film device of the matrix type. It is made up of 1024 elements, at which information bits may be stored, arranged in 64 rows and 16 columns. Each element represents a duration of 10ns and if a particular element is marked, it represents the fact that a pulse occured within this 10ns duration. The information stored in trigger stores H 1 -H 32  during the first 160ns, is written into the first row of 16 elements, the row selected being controlled through distribution unit P by line generator S and pulses being gated to the individual elements in the row through transfer gates N 1  -N 16  under the control of column generator R. After the contents of the trigger stores H of each delay line E 1 , E 2  have been transferred to the store, the triggers of each delay line in turn are reset ready to sample the next 80ns interval. Readout of the buffer store can only begin at least 10240ns after the start of the recording. The readout may be to a multi-channel analyzer or discriminator arrangement having e.g. 1024 or 4096 channels, and which can record only at 16 Ásecs per bit. The store B is arranged to be read out row by row, the elements in each row being interrogated simultaneously. Thus, the column reading unit comprises amplifiers V 1 -V 16  whose outputs if any are gated by gates W 1 -W 16  to storage trigger circuits X 1 -X 16 . Pulses from a clock BB are fed both to a distribution unit Y which controls the opening of transfer gates Z 1  -Z 16  in sequence so that the states of gates X 1  -X 16  are tested sequentially. Any trigger circuit X storing a marked element of the store B produces a pulse which is fed by the corresponding gate Z through an OR gate AA to the clock BB to stop the latter. The number reached by a register CC, which also receives clock pulses from BB is caused at this instant to be transferred to the "slow" analyzer connected at C. After the transfer, a pulse at bb<SP>1</SP> restarts the clock, which continues testing the trigger circuits X. After a line of points has been read, the triggers X are reset and a new line read. Thus the output of register CC is a sequence of numbers representing the 10ns periods in which pulses occurred. Thereby, pulses occurring at a particular time in each particle burst may be recorded in the same analyzer channel of the multi-channel analyzer connected at C. A simulator may be provided in the input to the buffer store, to provide checking of the elements in the store, of the input circuit and of operation.