Patent GB-1423504-A (GB)
Title: Integrated direct-coupled electronic attenuator
IPC: H03H11/24
Filed: 1974-03-01
Abstract: 1423504 Gating circuits; gain control; fade-over arrangements SIGNETICS CORP 1 March 1974 [13 April 1973] 9348/74 Headings H3T H4J and H4R An integrated direct coupled electronic attenuator circuit comprises first and second differential amplifiers each including a pair of transistors i.e. Q4, Q5 and Q6, Q7, Fig. 1 respectively, each transistor having an input control terminal and first and second output terminals. The first output terminals, i.e. the emitters, of each pair of transistors are tied together and at least one of the input control terminals receives an A.C. input signal. First and second switching means, i.e. transistors Q2, Q3 respectively, are provided for coupling a constant current source, i.e. transistor Q1 to the tied pairs of output terminals and include means for partitioning the constant current between the first and second differential amplifiers; load means are coupled to the second output terminals of the differential amplifiers for receiving current from the constant current source. Switching circuit.-In the embodiment of Fig. 1, the collectors of transistors Q4, Q6 are connected together and to the collector of a load transistor 9, while the collectors of transistors Q5, Q7 are connected to the respective bases, to the collector of a further load transistor Q10, and to output terminal F. The bases of transistors Q9, Q10 are connected together and to the emitter of a transistor Q8, the base of which is connected to the collector of transistor Q9; the transistors Q9, Q10 thus pass equal collector currents. A first input is applied to terminal A and is transmitted to output terminal F when transistor Q2 is biased conductive and transistor Q3 non-conductive: if the bias on these transistors is reversed, a second input is transferred from terminal B to output terminal F instead. Continuously variable attenuator: fade-over circuit.-The arrangement of Fig. 2 differs from that of Fig. 1 in that each of the transistors Q4-Q7 is provided with a separate load transistor Q9, Q10, Q13, Q14, all of which have their bases connected via a common line to the emitters of bias-controlling transistors Q8, Q15: in addition two further transistors Q11, Q12 have their bases biased from the common line, while their collectors are connected together and to earth via a resistor R4 across which the output is obtained. Transistors Q4-Q7 are provided with base circuit resistors R2, R3, R5, R6 respectively, while the collectors of transistors Q5, Q6 are connected to the bases of transistors Q4, Q7 respectively via resistors R1, R7. According as the differential bias on terminals C, D is varied, the output at terminal G from input terminal A is continuously increased or decreased, while that from terminal B is varied in the opposite sense. In both the arrangements of Figs. 1 and 2, frequency shaping circuits may be inserted between the emitters of transistors Q2 and Q3. Quadraphonic decoder.-Fig. 3 shows one of the two channels, the input consisting of a sum signal (Ch1+Ch2) plus a frequency-modulated difference signal F(Chl - Ch2). After amplification in preamplifier 10 the signals are separated by means of low pass filter 11 and bandpass filter 12. The sum signal is passed to muting amplifier 13 which comprises a circuit of Fig. 1 type in which the second input terminal B is connected to a reference voltage, while the difference signal is passed via a limiter 16 to a phase detector 18. The output of phase detector 18 passes via a low-pass filter 19 to an expander 24, which comprises a circuit of Fig. 2 type in which the B input comprises a reference voltage. The outputs from muting amplifier 13 and expander 24 are combined in matrix amplifiers 14, 26 to give the outputs Chl and Ch2 respectively. The output from low-pass filter 19 is also used to control voltage-controlled oscillator 21 which provides the second input to phasedetector 18: it also provides one input to amplitude detector 22, the second input coming from limiter 16. The output from amplitude detector 22 switches muting amplifier 13 on and off depending upon whether the difference signal is present. In the expander 24 the gainvarying voltage is obtained by rectification of the input (Fig. 5, not shown).