Patent GB-1153495-A (GB)
Title: Improvements in and relating to Semiconductor Devices
Inventor: LAMMING JACK STEWART
IPC: H01L21/331
Filed: 1966-07-25
Abstract: 1,153,495. Semi-conductor devices. ASSOCIATED SEMICONDUCTOR MFRS. Ltd. 25 July, 1966, No. 33424/66. Heading H1K. The base region of a transistor comprises a first high-resistivity diffused part 4, and a second lower-resistivity diffused part 7, the initial diffused depth of which is less than that of the part 4. On subsequent diffusion in of an emitter region 10 of opposite conductivity type to the base region, the diffusion front 8 of the base part 7 is pushed forward by the " emitter dip effect," to meet the collector-base PN junction 5 defined by the diffusion front of the high-resistivity base part 4. In the embodiment shown an NPN planar transistor is formed on a silicon substrate 1. The base region is formed in two boron diffusion steps, a subsequent phosphorus diffusion step producing the emitter region 10, and causing the required " emitter dip effect." Further embodiments having differing configurations of the diffused regions are described. In one form, two separate lower-resistivity baseparts (7), Fig. 14 (not shown), are diffused into the high-resistivity base-part (4). The emitter region (10) is diffused in such a position as to overlap the edges of both parts (7) and to cause the diffusion fronts (8) of the two parts (7) to advance to meet the collector-base junction (5) immediately below the emitter region (10). Another embodiment is described in which an epitaxial layer (22), Fig. 24 (not shown), of N- type silicon is deposited on to an N+ silicon substrate (21). A high-resistivity boron-doped P-type base region (Pp) having a rectangular frame-like shape in plan view is diffused into the epitaxial layer (22), and a shallower highresistivity boron-doped P-type base region (P 1 ) is then diffused in to fill the inside of the frame and to overlap the inner edges of the region (Pp). The low-resistivity boron-doped P-type base region (P 2 ) is next diffused in to a shallower depth than the region (P 1 ). The area into which the region (P 2 ) is diffused is identical to that of the region (P 1 ), with the exception of four strips (36), where the region (P 1 ) still extends to the upper surface (23) of the layer (22). Four phosphorus-doped N-type emitter regions (29) are then diffused in over the strips (36), causing the diffusion front of the base region (P 2 ) to advance to the collector-base junction (35) around each strip (36). Aluminium contact strips (40, 43) are then evaporated on to the emitter and base surfaces respectively, to form two interdigital contact structures (Fig. 23, not shown), to which leads may be compression bonded. The N+ substrate (21) of the collector region is mounted on a header part of an envelope surrounding the device. Several such transistors may be formed simultaneously in a single silicon wafer, which may then be subdivided into individual components. The boron diffusion stages are performed by firstly depositing a layer of boron trioxide glass on the silicon at 900‹ C. in a flow of dry nitrogen, and secondly " driving in " the boron dopant into the silicon body at a higher temperature in a flow of dry oxygen. The phosphorus diffusion process involves heating the silicon body to 970‹ C. in a flow of dry nitrogen which has previously passed over heated phosphorus pentoxide. Masks are applied prior to each diffusion stage, by oxidation or by deposition of layers of borosilicate or phosphosilicate glass. A method involving the use of photoresists and etches is used to shape the mask at each stage.