baber/WOPTO huggingface dataset:
Patent JP-H0224696-A (JP)
Title: Display control system
Inventor: SAITO TOSHIMITSU
IPC: G06F3/153
Filed: 1988-07-13
Abstract: PURPOSE:To eliminate unnecessary power consumption by turning off a display when operation is interrupted for a long time. CONSTITUTION:A timer interruption driver 2 is actuated by a timer at specific intervals of time and when the display is on, a counter is made to count repeatedly up to a constant value. If there is a key input through a keyboard 3 during the period, a keyboard interruption driver 4 is actuated to clear the counter 6. Therefore, when the system is used while normal key input is performed, the counter 6 does not reach the constant value, so the display is still on. If the key input is interrupted and the counters 6 reaches the constant value, the driver 2 turns off the display and a display flag 7 is turned off. During this period, the driver 6 does not make the counter 6 count up. Then when the key input is restarted, the flag 7 is on, so the driver 4 turns on for normal use.
Patent JP-H0465920-A (JP)
Title: Method for constituting error correction code
Inventor: WATANABE KAORU
IPC: H03M13/01
Filed: 1990-07-03
Abstract: PURPOSE:To allow one correction circuit to cope with plural transmission and recording media by forming a correction code in matching with plural different transmission and recording media with an extended correction code. CONSTITUTION:A transmission and recording medium 2 generates a code whose correction code length is longer than that of a transmission and recording medium 1 resulting in improving the correction capability. The correction code B of the medium 2 is formed by extending a correction code A, then even when the signal for the medium 2 is received by a circuit for the medium 1, the correction capability of the medium 1 is used to correct a bit error. For example, let a generation polynomial of the correction code of a satellite broadcast be GA=(X<7>+X<3>+1), then a generation polynomial of the correction code of a video disk is expressed in GB=(X<7>+X<3>+1)(X<7>+X<3>+X+1). One correction circuit copes with lots of kinds of transmission and recording media by using the generation polynomial in such a manner.
Patent JP-S57103325-A (JP)
Title: Wire bonding method
Inventor: SHIOKAWA KESAMI
IPC: H01L21/60
Filed: 1981-11-02
Abstract: PURPOSE:To enhance the reliability of a semiconductor device by preparing a fine Au wire having a free end, forming a ball at the free end by discharge machining, performing a wire bonding with this, and avoiding the oxidation of an aluminum wire provided with the semiconductor device in case of forming the ball. CONSTITUTION:An IC chip 2 is secured to the post 5 side of a package 1 having an external lead post 5, and the end ball 8 of a fine Au wire 7 inserted into a capillary 6 is contacted on the pad 4 of an aluminum wire 3 provided at the chip 2 to be bonded. At this time a ball 8 is produced by an arc discharge between electrodes 9 and 10 at the end of the fine Au wire projected from the capillary 6 prior to the contact, the capillary 6 is thereafter lowered to contact the ball 8 with the pad 4 to be bonded. Then, the capillary 6 is moved to allow the fine wire 7 to extend to the post 5 to be secured, and the fine wire is cut. Then, the capillary 6 is pulled up, and a ball 8 is then formed in advance for next treatment.
Patent JP-S6233415-A (JP)
Title: Manufacture of single crystal semiconductor film
Inventor: SUGAHARA KAZUYUKI
IPC: H01L21/263
Filed: 1985-08-06
Abstract: PURPOSE:To make it possible to single-crystallize the polycrystalline or amorphous semiconductor film of large area and high quality located on the first insulating film by a method wherein the single crystal semiconductor film, having the substrate of a longitudinal aperture part as a seed and the equal crystal axis distribution, is formed on the first insulating film while the polycrystalline or amorphous film is being melted successively. CONSTITUTION:When a laser beam 7 having specific power is scanningly applied to a thin oxide film 4 and a longitudinal tungsten film 5 from a longitudinal aperture part to the direction indicated by the arrow in the diagram, a polycrystalline silicon film 3 is melted and a melted part 30 is formed. Using the single crystal silicon substrate 1 of a longitudinal aperture part 6 as a seed, an epitaxial growth wherein the direction of crystal axle of said seed is taken over is generated continuously. As the direction vertical to the scanning direction the the temperature distribution in scanning direction of the melted part and the like of the polycrystalline silicon film 3 can be controlled on a thick oxide film 2 by the longitudinal tungsten film 5, the state of solidification and recrystallization is generated continuously from the solid-to-liquid interface of the melted part of the polycrystalline silicon film 3 on the region located under each longitudinal tungsten film 5 toward the region having no longitudinal tungsten film 5, and the appearance of a crystal grain boundary can be suppressed.
Patent JP-H0340534-A (JP)
Title: Ultrasonic transmitter and receiver
Inventor: YAMAGUCHI MASAKI
IPC: H04Q9/00
Filed: 1989-07-06
Abstract: PURPOSE:To improve ultrasonic transmitting/receiving sensitivity by using porous metal using a metal reducing the internal loss of an acoustic matching layer as a base material. CONSTITUTION:In the ultrasonic transmitter/receiver 10 for transmitting/ receiving ultrasonic wave in liquid or gas, a piezoelectric oscillator 11 is fixed on a base 12 and the acoustic matching layer 13 formed by the porous metal using aluminium as the base material is stuck to the other face of the oscillator 11. In this case, an acoustic load is air 14. The porous metal to be used is produced by a solubility difference method or the like for previously dissolving gas mainly consisting of a H2 or N2 component into melted metal and foaming the gas into the metal on the way of reduced pressure solidification. Thus, the sensitivity of the ultrasonic wave transmitting/receiving equipment 10 can be improved.
Patent JP-S6153718-A (JP)
Title: Amorphous silicon manufacturing device
Inventor: ORITSUKI RYOJI
IPC: H01L21/205
Filed: 1984-08-24
Abstract: PURPOSE:To form an amorphous silicon film in succession for a long time and to improve mass productivity by providing a translucent glass plate moving with a substrate between the substrate and a light source radiating ultraviolet rays. CONSTITUTION:After plural unit 8 are accomodated in a film forming chamber 10 of an amorphous silicon manufacturing device, an amorphous silicon film is formed on a substrate 1 on the unit 8. After the substrate 1 is supplied from a load chamber 11 connecting with this film forming chamber 10, the substrate 1 forming a film is accomodated into an unload chamber 12. The unit 8 accomodated in this film forming chamber 10 is mounted on a conveyor 13 and carried to an arrow A direction. After a transparent window 14 of quartz glass is provided in a predetermined space in the bottom of the film forming chamber 10, a mercury lamp 15 is also arranged facing the transparent window 14. After the substrate 1 is carried with the conveyer 13 and the ultraviolet rays 7 is irradiated to the film forming chamber 10 from the mercury lamp 15, the amorphous silicon film are formed in succession and mass productivity is improved.
Patent JP-S6153756-A (JP)
Title: Semiconductor device
Inventor: HIRASHIMA TOSHINORI
IPC: H01L27/02
Filed: 1984-08-24
Abstract: PURPOSE:To reduce parasitic capacitance between bonding pad and P type substrate by forming P type diffused layer at the N type semiconductor surface just under the bonding pad in view of connecting in series the junction capacitances by the P type diffused layer. CONSTITUTION:Dielectric capacitance C of insulating film 4, junction capacitance C3 between P type diffused layer 8 and N type layer 2 and junction capacitance between N type layer 2 and P type substrate 1 are connected in series between the bonding pad and P type substrate and parasitic capacitance CI can be related by the formula 1. Here, the parasitic capacitance CII of the existing case where there is no capacitance C3 is related by the formula 2. From such relatrelations, a relation 1/CII>1/CI can be obtained. Therefore, a parasitic capacitance can be made smaller by inserting a P type diffused layer 8 under the bonding pad.
Patent JP-S6153806-A (JP)
Title: Bipolar type integrated circuit
Inventor: ONO AKIHIKO
IPC: H03F1/32
Filed: 1984-08-24
Abstract: PURPOSE:To prevent a PNP transistor (TR) from being saturated and a substrate potential from rising owing to the formation of a parasitic TR by providing the PNPTR and an element which has diode characteristics. CONSTITUTION:Respective potentials at points A-D are based upon a source voltage Vcc. Namely, the potential VA at the point A is the base-emitter voltage (0.7V) of a PNPTR3 lower and the potential VB at the point B is about 0.35V lower when resistances 21 and 22 are equal in value. Further, the potential VC at the point C is the sum of VB and the base-emitter voltage (about 0.7V) of TR7 and about 1.05V lower, and the potential VD at the point D is the difference between VC and the base-emitter voltage (0.7V) of TR5 and about 0.35V lower. Therefore, the difference between the point VA at the point A and the potential VD at the point D is clamped to about 0.35V, and even if an output current I varies over a considerably wide range, the potential VD is prevented from rising above said potential, so that the TR3 is prevented from being saturated.
Patent JP-H0845748-A (JP)
Title: Mounting structure of printed coil transformer
Inventor: INAO KIYOHARU
IPC: H01F27/08
Filed: 1994-07-27
Abstract: PURPOSE:To enhance cooling efficiency of a power-supply transformer by a method wherein a heat dissipation resistance from winding heating parts to pin terminals is reduced using a printed coil transformer. CONSTITUTION:A transformer, which is constituted in a structure where a DC voltage Vin, to a primary winding n1 is turned off by a switching element Tr and a switching signal, induced in a secondary winding n2 is rectified, smoothed, and is fed to a load RL, and is used as a switching power supply, is one of a structure, wherein internal layer patterns 52 are laminated using an insulative resin, the internal layer patterns are allotted to the primary winding and the secondary winding and at the same time, a printed coil transformer 50 having pin terminals 53 which are connected with both ends of the primary and secondary windings and consist of an iron material, a heat sink 30 which is grounded to an AC ground of the switching power supply and at the same time, is mounted on the element Tr and a secondary side rectifying circuit, and a wiring pattern 12 for transferring heat between each terminal of this printed coil transformer and the heat sink 30 are provided on a mounting substrate 10.
Patent JP-2001004829-A (JP)
Title: Cholesteric liquid crystal film
Inventor: NISHIMURA RYO
IPC: G02B5/18
Filed: 1999-06-22
Abstract: PROBLEM TO BE SOLVED: To provide extremely excellent visibility and design property and a specific optical characteristic of a diffracted light having circular polarizability by setting the wavelength band width of cholesteric selective reflection in a specified range, and providing an area showing diffractive performance in a part of a film. SOLUTION: This cholesteric liquid crystalline film is formed of a film of single layer having a wavelength band of cholesteric selective reflection of 30-150 nm, which partially has an area showing diffractive performance. The wavelength band of cholesteric selective reflection means the wavelength range where the reflective index by selective reflection is 70% or more when a circularly polarized light in the same direction as the twisting direction of a liquid crystal molecule forming the cholesteric alignment is incident. When the wavelength band is out of this range, the cholesteric liquid crystal film itself is clear in color, but the selectively reflected light is not bright enough. There is the possibility of causing the reverse case, and the selective reflecting effect or coloring effect peculiar to the cholesteric alignment is deteriorated.
Patent JP-H06292173-A (JP)
Title: Video signal coding/decoding method
Inventor: SHIYUU TAN CHIYON
IPC: H04N19/136
Filed: 1992-07-02
Abstract: PURPOSE:To eliminate ringing phenomenon by performing smoothing processing on a detected edge part block. CONSTITUTION:Input frame data to a video signal encoder is digitized, and after that, it is divided into plural picture element blocks without being superimposed spatially (1). The size of the block is set at size of 8X8 picture elements to obtain proper processing adaptive level. The block is processed by performing motion vector evaluation (2) and motion compensation processing (3) at need, and applying DCT transformation (4). Quantization processing (5) is applied to such transformed data by using a quantized matrix and quantization step size decided by a data transfer speed controller 6, then, it is converted to a variable length code by performing runlength coding.
Patent JP-H0467741-A (JP)
Title: Bypass switching circuit
Inventor: KOBAYASHI AKIRA
IPC: H02J9/06
Filed: 1990-07-04
Abstract: PURPOSE:To realize uninterruptible bypass switching by turning the gate signal of a bypass side triac OFF when leading current of load has same polarity as the voltage thereby suppressing circulation current between a bypass power supply and an inverter. CONSTITUTION:A diode D1, a logic circuit 51, a resistor R2, a capacitor C1. and the like form an inverter output signal having 0 deg. phase. On the other hand, a 180 deg. phase signal is formed from the output signal of the logic circuit 51. Furthermore, a delay circuit 57 forms a 90 deg. phase signal from the 0 deg. phase signal outputted from an inverter 53. A bypass power supply OFF signal and the previously formed 180 deg. phase signal of the inverter output signal are fed to NAND circuits 61-63 and an inverter side switching element is turned ON in synchronization with the 180 deg. phase signal of the inverter output signal.
Patent JP-S5875950-A (JP)
Title: Encoding method for binary data
Inventor: WATANABE KENJI
IPC: H03M5/04
Filed: 1981-10-31
Abstract: PURPOSE:To perform recording at a source bit rate as it is without any increase in recording bit rate, by replacing a replacing data word based upon the value of DSV by a word complementary to said data word. CONSTITUTION:Respective one-word, (n)-bit data which are correlative with one another are rearranged corresponding one to one to one-word, (n)-bit data rearranged on the basis of a value (DSV) obtained by integrating binary levels 1 and 0 corresponding to +1 and -1 respectively. Further, said rearranged words are replaced by words complementary to the respective words with regard to every (m) correlative words (m=1, 2,...), and the resulting data are transmitted. For example, a color video signal is digitized by an A/D converter 2 and then recorded on VTR6 through DSV control encoding 3, inversion processing 4, and parallel-series conversion 5, and the data are reproduced through reverse operation.
Patent JP-H0835529-A (JP)
Title: Brake device
Inventor: TAKEMOTO TAKATOSHI
IPC: C04B35/83
Filed: 1994-07-27
Abstract: PURPOSE:To obtain a means for suppressing the variation of the frictional coefficient during the brake application by a brake device equipped with a frictional member consisting of a C/C composite. CONSTITUTION:As for a brake device having a plurality of frictional members consisting of the carbon fiber reinforced carbon composite material, a housing 2 into which the frictional member is accommodated has a sealed structure, and a decompression device 6 for decompressing the inside of the housing 2 or a gas feeding device 7 for the substitution with inert gas is provided.
Patent JP-S5877240-A (JP)
Title: Semiconductor device and manufacture thereof
Inventor: IMAI KAZUO
IPC: H01L21/762
Filed: 1981-11-02
Abstract: PURPOSE:To obtain a semiconductor device enabled to perform high speed action when the sides and the base of an Si region are to be isolated electrically in a porous Si oxide region obtained by oxidizing porous Si by a method wherein out of the Si region, the region coming in contact with the oxide only is made so as to have high impurity concentration. CONSTITUTION:Two groups of laminated films consisting of respectively an SiO2 film 61, an Si3N4 film 62, and a porous resist film 63 if necessary, are generated interposing an interval between them on the surface 48 of a P type Si substrate 41, and p type regions 64 of high impurity concentration are formed by diffusion, etc., in the exposed surfaces 48 making the laminated films thereof as the mask. After protons are implanted in the surfaces 48, a heat treatment is performed to form N type regions 65 coming in contact with the regions 64 posistioning under the two laminated films, the anode formation treatment is performed to the substrate 41, and a porous Si region 66 is made to be generated containing the regions 64 at the circumference of the regions 65. After then, P type impurities are introduced therein, a heat treatment is performed to make impurities to be diffused, the bases and the sides of the regions 65 are surrounded with P type layers 47 of high concentration, and then a heat treatment is performed to convert the region 66 into an oxide 43.
Patent JP-S5964904-A (JP)
Title: Oscillator
Inventor: HACHITSUKA HIROYUKI
IPC: H01P7/10
Filed: 1982-10-05
Abstract: PURPOSE:To facilitate the fine control of frequency by using a fine controllable screw to control the frequency and attaching a dielectric spacer at the tip of the screw as well as a dielectric resonator to the dielectric spacer. CONSTITUTION:A microstrip line is formed on a dielectric substrate 2 of ceramics, etc., and a semiconductor element 4 such a Gunn diode, etc. is connected to an end of the microstrip line. At the same time, a capacitor is connected to the other end, i.e. an output terminal of the microstrip line. Then such substrate 2 is bonded at a prescribed position of a metallic substrate 1. A dielectric spacer 11 is attached at the tip of a fine control screw 10 for frequency, and a cover 7 containing the screw 10 which fixes a dielectric resonator 5 to the spacer 11 is attached to the substrate 1. In this case, the screw 10 has a fine thread to reduce the shift degree per revolution as small as possible. Thus, the fine control of frequency is assured.
Patent JP-H0673014-A (JP)
Title: New pyrazole derivatives, their preparation and pharmaceutical compositions containing them
Inventor: FURANSHISU BARUTO
IPC: A61K31/5375
Filed: 1993-06-23
Abstract: The subject of the invention is pyrazole derivatives of formula I:   <IMAGE>  in which   - g2, g3, g4, g5, g6 and w2, w3, w4, w5 and w6 are identical or different and independently represent hydrogen, a chlorine or bromine atom, a (C1-C3)alkyl, a (C1-C3)alkoxy, a trifluoromethyl or a nitro group and g4 optionally represents a phenyl group;   - R4 represents hydrogen or a (C1-C3)alkyl; - X represents either a direct bond or a group -(CH2)x-N(R3)- in which R3 represents hydrogen or a (C1-C3)alkyl and x represents zero or one;   - R represents   . a group -NR1R2, in which R1 and R2 independently represent a (C1-C6)alkyl group; an optionally substituted, nonaromatic (C3-C15)carbocyclic radical; an amino(C1-C4)alkyl group in which the amino is optionally disubstituted by a (C1-C3)alkyl; a cycloalkyl(C1-C3)alkyl in which the cycloalkyl is (C3-C12); a phenyl which is unsubstituted or substituted one or more times by a halogen, by a (C1-C5)alkyl or by a (C1-C5)alkoxy; a phenyl(C1-C3)alkyl; a diphenyl(C1-C3)alkyl; a naphthyl; an anthryl; a saturated, 5- to 8-membered heterocyclic radical which is unsubstituted or substituted by a (C1-C3)alkyl, hydroxyl or benzyl; a 1-adamantylmethyl; an aromatic heterocycle which is unsubstituted or substituted one or more times by a halogen, a (C1-C5)alkyl or a (C1-C5)alkoxy; a (C1-C3)alkyl which is substituted by an aromatic heterocycle which is unsubstituted or substituted one or more times by a halogen, a (C1-C5)alkyl or a (C1-C5)alkoxy; or else R1 is hydrogen and R2 is as defined above; or yet again R1 and R2 constitute, with the nitrogen atom to which they are bonded, a saturated, 5- to 8-membered heterocyclic radical, the said heterocyclic radical being other than morpholinyl when w2, w3, w4, w5, w6, g2, g3, g4, g5 and g6 are all hydrogen;   . a group R2 as defined above when X represents -(CH2)xN(R3)-; . a group R5 when X represents a direct bond, R5 being represented by a (C1-C3)alkyl; a (C3-C12)cycloalkyl which is unsubstituted or substituted by a (C1-C5)alkyl; a phenyl(C1-C3)alkyl which is unsubstituted or substituted by a halogen or by a (C1-C5)alkyl; a cycloalkyl(C1-C3)alkyl in which the cycloalkyl is C3-C12 and is unsubstituted or substituted by a (C1-C5)alkyl; or a 2-norbornylmethyl;    or one of their optional salts. Application: therapeutic treatment of pathological conditions where cannabis is involved.
Patent JP-H0715146-A (JP)
Title: Multilayer printed wiring board with blind hole
Inventor: HARUTA YOICHI
IPC: H05K3/42
Filed: 1993-06-22
Abstract: PURPOSE:To achieve a plated blind hole which cannot be disconnected easily due to thermal shock, thermal expansion, moisture absorption, etc., and is highly, reliable by making the diameter of a blind hole provided at an insulation resin layer to be larger than that of the hole for the blind hole provided at the conductor circuit of an outer layer. CONSTITUTION:The conductor circuit of an outer layer and a conductor circuit 4 of an inner layer are electrically connected via a blind hole 7 through an insulation resin layer 1. In such K kind of multilayer printed wiring board, the diameter of the blind hole 7 provided at the insulation resin layer 1 is larger than that of the hole for the blind hole provided at the conductor circuit of the outer layer at a part in contact with the conductor circuit of the multilayer. Also, the distance between the inner-wall surface of the blind hole 7 provided at the insulation resin layer 1 at the part in contact with the conductor circuit side of the outer layer and the edge part of a fine hole provided at the conductor circuit of the outer layer is two times larger than the thickness of the insulation resin layer 1. Then, the inner wall surface of the blind hole 7 is made smoother.
Patent JP-2000010120-A (JP)
Title: Liquid crystal device and electronic appliance
Inventor: MURAIDE MASAO
IPC: G02F1/136
Filed: 1998-06-23
Abstract: PROBLEM TO BE SOLVED: To enable high-quality image display by relatively simple constitution using light shielding films with a liquid crystal device of a type provided with these light shielding film on the lower side of TFTs. SOLUTION: This liquid crystal device has a liquid crystal layer held between a pair of substrates and pixel electrodes 9a disposed in a matrix form on the substrate for the liquid crystal device. The island-shaped first light shielding films 11c consisting of a high melting metal lined up in a scanning line direction are respectively electrically connected via contact holes (18) to island-shaped scanning line pats 3a likewise lined up in the scanning line direction, by which one scanning line (300a) is formed. As a result, the resistance of the scanning lines is lowered.