Patent GB-1352276-A (GB)
Title: Analogue to digital converter
IPC: H03M1/00
Filed: 1972-02-21
Abstract: 1352276 Analog/digital converters INTERNATIONAL BUSINESS MACHINES CORP 21 Feb 1972 [6 April 1971] 7852/72 Heading G4H In analog/digital converters of the type in which bipolar input voltages V x  are received and their polarity determined by a polarity detector, errors arising due to incorrect operation of the detector at low voltage levels are eliminated by combining the input voltage with an offset voltage V 0  before digitization, the measured digitized value being compensated for the offset voltage V x . In the embodiment of Fig. 2, the unknown input voltage V x  is applied, either directly, via switch 22A, or indirectly, via an inverting amplifier 29 and switch 22B, in accordance with the output of polarity detector 28, for a time T, corresponding to a full count of a counter 2, to integrator 23 which has a voltage offset V 0 , greater than the error tolerance of polarity detector 28. After time T counters 1, 2 are preset to a negative value corresponding to the output voltage V 0  and additional counter stages ST, UT, used to determine if the polarity detector operates incorrectly or the capacity of the converter is exceeded, are set. A reference signal VR1 is then applied to the integrator, counter 2 being incremented until a first comparator 40 detects a voltage VT at the integrator output. A second reference signal VR2 is then applied and counter 1 is incremented until a second comparator 45 detects the integrator output is zero. Any overflow pulses from the counter 1 are applied to the counter 2. The counter outputs are then read out either directly, or if detector 28 detects a negative input signal, via exclusive NOR gates 35, 36. The additional stages ST and UT are read out via a decoder 38. If the polarity detector detects as negative a small positive voltage the effective input to the integrator is less than V 0  so that the final count is negative this being inverted (under the control of the output of detector 28) to produce the correct positive value. Similarly if the polarity detector detects as positive a small negative voltage, the effective input is again less than V 9  giving a negative final count but this is not inverted so that the correct negative value is fed out. Since in either of these conditions the stage ST is not reset by an overflow pulse from counter 2, its "1" output signal is used in conjunction with the output of detector 28 to give the correct output sign S to the count. If the input exceeds the capacity of the system the stage UT, reset by the first overflow pulse from counter 2 is set again by the second overflow pulse, stage ST remaining reset at this time. The outputs from the stages are then used to derive an output signal U indicating overflow. In another embodiment (Fig. 4 not shown) the invention is applied to a successive approximation analog/digital converter (55) in which the input is again applied, directly or after inversion, in dependence on the output of a polarity detector (50) to the converter (55) which also has an offset voltage V 1  applied. The digitized value is stored in an output register (58) from which a signal corresponding to the voltage V 0  is subtracted by applying a pulse to the appropriate bit level. As before the count in the register and the signal representing its polarity is read out either directly or via exclusive NOR gates (59) in accordance with the output of the polarity detector.