Patent SG-11201900829Y-A (SG)
Title: Method for manufacturing a semiconductor structure
Inventor: NGUYEN BICH-YEN
IPC: G02B6/136
Filed: 2017-07-27
Abstract: C) W O 18/0245 95 Al (D) (E) HG. 1 103\" 02' 01 110 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 08 February 2018 (08.02.2018) WIP0 I PCT D IV °nolo Imo oimIE (10) International Publication Number WO 2018/024595 Al 100 //A . 102 (B) 02 (51) International Patent Classification: GO2B 6/132 (2006.01) GO2B 6/136 (2006.01) (21) International Application Number: PCT/EP2017/068979 (22) International Filing Date: 27 July 2017 (27.07.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 1657575 04 August 2016 (04.08.2016) FR (71) Applicant: SOITEC [FR/FR]; Parc Technologique des fontaines, chemin Des Franques, 38190 Bernin (FR). (72) Inventors: NGUYEN, Bich-Yen; 110 S. Laurelwood Dri- ve, Austin, Texas 78733 (US). GAUDIN, Gweltaz; 77 Place de la Ruchere, 38920 Crolles (FR). (74) Agent: GRUNECKER PATENT- UND RECHTSAN- WALTE PARTG MBB; Leopoldstrasse 4, 80802 Mfinchen (DE). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: with international search report (Art. 21(3)) (54) Title: METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE (57) : The present invention relates to a method for manufacturing a semiconductor structure and to a photonic device, wherein the method comprising the steps of: providing a silicon nitride patterned layer (102) over a carrier substrate (101); providing a first layer of (A) -101 a conformal oxide (103) on the silicon nitride patterned layer (102) such that it fully covers said silicon nitride patterned layer; and planarizing the first layer of conformal oxide (103) to a predetermined thickness above the silicon nitride patterned layer (102) to form a planarizing 103 oxide layer (103'). After the step of planarizing the first layer of conformal oxide (103), the method further comprises steps of clearing the silicon nitride patterned layer (102) to form a 01 dished silicon nitride patterned layer (102 ) with a dishing height; and, subsequently, providing a second layer of a conformal oxide (104) on or over the dished silicon nitride layer (102').