Patent GB-1252293-A (GB)
IPC: H01L27/06
Filed: 1968-11-14
Abstract: 1,252,293. Semi-conductor devices. SONY CORP. 14 Nov., 1968 [14 Nov., 1967; 21 Dec., 1967], No. 54119/68. Heading H1K. Electrical connection to deep-lying layers in a semi-conductor structure is made through heavily doped polycrystalline regions which extend to the surface of the structure. Such regions are produced in otherwise monocrystalline structures by depositing semi-conductor material on to a monocrystalline substrate provided at selected regions with seeding sites for polycrystalline growth, so that the deposited material grows with both monocrystalline and polycrystalline portions. Diffusion into polycrystalline material is faster than into monocrystalline material so that deep and heavy doping may be affected in these connecting zones. Seeding sites may be deposits of sodium chloride, carbon, silicon dioxide, silicon monoxide, or of polycrystalline silicon or germanium. Seeding sites may be formed by roughening (e.g., sand-blasting) or scratching the semi-conductor surface. They may also be formed by alloying A1, In, Ga, Sb, P or As with the semi-conductor or by diffusing such impurities into the semi-conductor surface at very high concentrations. Fig. 1I shows part of an integrated structure containing a resistor formed in a P-type layer and an NPN transistor. As shown the N<SP>+</SP> regions 4, 4<SP>1</SP> are formed by diffusion, seeding sites 5 of polycrystalline silicon are deposited, and layer 6 is then grown. Impurities from the N<SP>+</SP> layers 4, 4<SP>1</SP> and from the bulk of the substrate 1 may be diffused into the grown layer during or after its growth. If insufficient N-type impurity diffuses into the polycrystalline material 8, diffusion of more impurities may be allowed by exposing the upper surface when the emitter 20 is being formed. The width of the collector electrode 24<SP>1</SP> (typically aluminium) may be less than, the same as, or greater than the width of the polycrystalline zone. In a variant, P-type impurity is diffused into the P- regions between devices during the formation of the resistor 15 and base region 14. If silicon oxide is used as alternative seeding material to silicon, diffusion from the N<SP>+</SP> layers into the polycrystalline material takes place round the edges of the seeding site. If an alloy zone or heavily diffused region is used as seeding site this will itself act as a diffusion source. In variant structures the N<SP>+</SP> layers may be replaced by a single epitaxial or diffused layer on the starting substrate. Fig. 2F shows a beam lead structure comprising a transistor and resistor. The starting material is an N<SP>+</SP> silicon substrate and the site for the collector connection is seeded with silicon. Contacts are platinum silicide with beam leads constituted by successive vapour deposited layer of titanium and gold and a final electrodeposited gold layer. Fig. 3 (not shown) depicts a diode in which connection from the top-surface electrode 7 to the low resistivity base layer is through a polycrystalline channel; the annular anode 4 is provided in the higher resistivity grown upper layer 3. Fig. 4G (not shown) depicts a structure like that of Fig. 1 but in which the devices are separated by heavily diffusion doped polycrystalline isolation walls 12. In operation the devices are isolated by applying a reverse bias across a contact on the polycrystalline wall and contacts on the devices such as one on heavily diffused region 25. Fig. 5 (not shown) depicts a structure comprising two double gate JUGFETs, the lower gate regions 4 of which are connected to the upper surface by annular polycrystalline regions 8. Fig. 6F shows a high capacitance diode in which the junctions are connected in parallel by a P-type diffused polycrystalline region 36A and an N-type diffused polycrystalline region 36<SP>1</SP>A. A structure may be designed to give a greater change of capacitance with applied voltage. Reference has been directed by the Comptroller to Specification 1,146,943.