Patent GB-1300421-A (GB)
Title: Improvements in or relating to data transmission arrangements
IPC: H04Q11/04
Filed: 1969-04-14
Abstract: 1300421 Automatic exchange systems MARCONI CO Ltd 10 April 1970 [14 April 1969] 19091/69 Heading H4K In a TDM, PCM exchange, routine operations e.g. line scanning and metering are handled by individual stored-programme controlled processors while overall control including the transmission of data between processors is vested in an executive stored-programme controlled processor. The exchange is of the type described in Specification 1,252,526. The control arrangement comprises three executive processors 301 (Fig. 7) whose majority output as determined by majority vote circuit 303 is buffered at 304. The individual processors of which there may be more than one of each type depending on traffic loads comprises a concentrator processor 305; line scanner processor 306; register processor 307; sender processor 308; interrogation processor 309 (interrogation is the process of injecting marks into a switching network during path finding); call supervisory processor 310 (the dotted link means that interrogation marks passed via the network and detected by call supervisory circuits are passed direct to this processor instead of via the executive processor as is necessary for all other data interchange); drum translator processor 311; metering processor 312; and primary route selective processor 313. The individual processors all conform to the design shown in Fig. 9. Therein, data in respect of the 32 channels in each exchange time frame are temporarily buffered in cyclic store 424 prior to read-out via 421 to the peripheral equipments involved or write-in to a call store 428. The contents of the latter are constantly monitored by a control circuit 436 which determines whether the data should be processed (429) by the microprogrammes available from local programme store 430 or whether access to the executive should be made. In the latter case a demand order and an indication of the priority of the demand are transmitted over the four-wire highway 409 whereafter the data is transmitted at the instigation of the executive. Data in either direction on 409 is buffered in a special section 432 of the call store 428, while scratch-pad memory for the processor 429 is provided by section 431. Within the processor parallel 8 bit transmission is used, conversion to the serial mode utilized on highways 409 and 422, 421 being effected by converters 433 and 425 respectively. The executive processors are each as shown in Fig. 8. Herein a demand order arriving over an incoming pair of a highway 409 is detected by an interrupt circuit 413 which passes the order and its priority on to a control circuit 410 during a permitted scanning period. Control 410 determines a data-block storage portion of relevant priority in call store 401 and causes a crosspoint in matrix 408 to be closed so that the 10 bit data from the peripheral processor can be received. The first bit indicates the demand order so that the executive knows that when this bit changes all.the data has been received. The last bit is a parity bit. With parity failure only one further attempt at transmission is made. Data reception at the executive may be interrupted from either end if higher priority orders occur. In its turn, as determined by the priority and the number of preceding items of same priority, the data is processed using microprogramme, and time slot stealing techniques (Fig. 10, not shown) preparatory to its return to the same or a different peripheral processor via the matrix 408. It may be noted that every Nth incoming or outgoing word is specially reserved for indicating whether a message is ended or is continuing, circuits 411, 412 being provided for monitoring this. As before parallel bit transmission is used within the processor. The programme store is of the read-only type. It is provided with an address-modification facility so that a same programme may be used for different data blocks in the call store simply by adding an increment, representing the stage which processing has reached, to the starting address of any block. An arithmetic unit, bus system and address units suitable for use in any of the processors is described with reference to Fig. 10 (not shown). With reference to Fig. 1 (not shown) it is briefly mentioned that the exchange is connectible to concentrators and PCM interexchange junctions as well as via PCM codes/ decoders to audio links extending to strowger exchanges.