Patent GB-1123241-A (GB)
Title: Electrical pulse processing
Inventor: DUERDOTH WINSTON THEODORE
IPC: G11C21/00
Filed: 1965-05-21
Abstract: 1,123,241. Transmission systems; multiplex pulse code signalling. H.M. POSTMASTER GENERAL. 18 Aug., 1966 [21 May, 1965], No. 21613/65. Headings H4L and H4P. A plurality of systems are described in which, by repeatedly recirculating one or two input pulse trains through a delay, either (a) with one input the pulse train is compressed, that is if the input pulse train comprises n pulses equally spaced by s pulse positions, the output pulse train will comprise n pulses occupying adjacent pulse positions, or (b) with one input the pulse train is expanded, that is if the input pulse train comprises n pulses occupying adjacent pulse positions, the output pulse train will comprise n pulses equally spaced by s pulse positions, or (c) of two input pulse trains applied simultaneously, one will be compressed and the other will be expanded. Compression or expansion may each result in a change in the serial order of the pulses. By means of additional delays a plurality of the above compressors can be used to multiplex a corresponding plurality of pulse-trains on to a single channel. Demultiplexing using expanders is also possible, and multiplexing and demultiplexing can be performed simultaneously using the same equipment. The specification examines mathematically the relationship which must exist, between n, s and d, where d is the duration of the delay employed, for compression and expansion to be possible, and concludes by tabulating a large number of possibilities up to n = 16 and s = 12. Compression.-In a first embodiment with n = 8 and s = 5, eight pulses I, II, III . . . VIII, Fig. 2, at time slots 1, 6, 11 ... 36, are circulated repeatedly around an eight-bit delay D1, Fig. 1, and at time slot 37 an output gate PCG1 is opened for a period of eight time slots, during which period circulation is inhibited, to produce the original eight pulses in adjacent time slots but in the order V, II, VII ... VIII, as shown in F Fig. 2. In a first modification (Fig. 3, not shown) the delay D1 is moved to the opposite section of the loop, i.e. between gates RG1, and DG1. With this arrangement the compressed output pulse train can be obtained earlier, during time slots 29 to 36, as shown at 01<SP>1</SP> in Fig. 2. Indeed, in the basic circuit the compressed pulse train could have been obtained (albeit in a different order) during any of the eight-bit periods starting on one of time slots 38, 39, 40 or 41. No later is possible if interference with a following input cycle of eight pulses is to be avoided. In a second modification (Figs. 4 and 5 not shown), the delay D1 is divided, between the two sections of the loop, and in a third modification (Figs. 5 and 6, not shown), the eight bit delay D1 is replaced by one of seven bits. A second embodiment (Figs. 16 and 17, not shown), in which n = 3 and s = 5, is described in which the serial order of the compressed pulses is the same as that of the input pulses. In a third embodiment Figs. 22 and 23, in which n = 10 and s = 6, two series connected loops are used. Expansion.- Figs. 9 and 10 with n = 8 and s = 5 show how if eight pulses i, ii, iii ... viii, are applied via a gate DG1 and repeatedly circulated around an eight-bit delay D1, an expanded pulse train i, vi, iii ... vi, at time slots 9, 14, 19 ... 44 can be gated out by appropriate clock-pulses. This arrangement is complementary to the compressor of Figs. 1 and 2, and can be modified similarly. Expanders complementary to the compressors described for (n,s) = (3,5) and (10,6) are also described (Figs. 18, 19 and 24, 25 respectively, not shown). Simultaneous compression and expansion.- By appropriate timing a single circulating loop can be used to compress and expand two independent pulse trains simultaneously. Such an arrangement, with n = 8 and s = 5, is described in Figs. 12 and 13, in which if an input pulse train of eight pulses i, ii, iii ... viii, occupying adjacent time slots is applied to an input terminal 15, and if an expanded pulse train of eight pulses I, II, III ... VIII, occupying time slots 9, 14, 19 ... 44 is applied to a second input terminal 16, then an expanded pulse train i, vi, iii ... iv, can be gated out at time slots 9, 14, 19 ... 44, and a compressed pulse train V, II, VII ... VIII can be gated out during time slots 37 to 44. A corresponding arrangement with (n,s) = (3,5) is also described (Figs. 20, 21, not shown). Multiplexing.-A plurality of slow speed p.c.m. channels I(A), I(B) ... I(E), Fig. 8, can be multiplexed on to a single change 0, by *delaying each channel by successively longer delays D(B), D(C) ... D(E) and then compressing each channel by any of the compressors described. Demultiplexing using expanders (Fig. 11, not shown), and simultaneous mutilplexing and demultiplexing (Fig. 15, not shown) is also described.