Patent GB-784496-A (GB)
Title: Digital computer
IPC: G06F15/78
Filed: 1954-02-02
Abstract: 784,496. Digital electric calculating-apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 2, 1954 [Feb. 5, 1953], No. 3070/54. Class 106 (1). [Also in Group XL (c)] In a device for adding digits represented by electrical input pulses timed to have numerical significance, comprising input storage devices each adapted to store a pulse having a particular numerical significance, the pulses are routed to the storage devices selectively by two groups of devices for entering true and complementary values respectively, and coincidence switches each responsive to output voltages from a particular group of storage devices selectively operate devices to manifest the sum of the digits. General arrangement. The computing arrangement described comprises a magnetic drum MD, Fig. 1, having " computer " tracks 11 and distributer tracks 12 associated with circuits 10 and 13. These circuits are controlled by timing pulses obtained from tracks 16 and circuits 14 (not described in detail) and by an operation selector 15, e.g. an automatic programme control unit or manually operable keys or switches. The circuits 13 may be connected to a general store which may be a further portion of the magnetic drum but, as particularly described, comprises manually settable data-input switches and a neon lamp output register. The tracks 11, 12 (A and B), Fig. 9, each have spaced reading and recording heads associated therewith whereby information is continually read, erased and replaced by the same or new information. The tracks 12A, 12B form an intermediate store between the input/output arrangements and the " computer regeneration " and " computer operation " tracks 11A, 11B. The latter have their normal reading and recording heads coupled through regeneration and arithmetic circuits to form " revolvers." Values are normally stored in the regeneration revolver except when a computation or other operation is taking place, and are transferred to this revolver at the end of an operation. As well as the four rules and left and right shifts, the operations which may be selected include a round-off (" half correction ") and right shift, and a test for all zeros in a stored computer value (" balance test "). Number representation; timing pulses. Numbers are represented in coded-decimal serial form on the drum tracks 11 and 12, Figs. 1 and 9, and associated circuits, each digit being represented by two magnetic spots, or corresponding timed pulses, in one of the quinary positions or cells QO-Q4, Figs. 3 and 38, and one of the binary positions or cells BO-B5. The eighth cell O provides a space between digits. The distributer tracks 12A, 12B, Fig. 9, comprise groups of 11 digit positions DG1-DG11 for storing a 10-digit decimal number plus a sign (9 for " + ", 8 for " - ") as indicated, while the computer tracks 11A, 11B can store either two separate 10-digit numbers or a 20-digit number in positions DG2-L to DC11-L (" lower computer ") and DG1-U to DG10-U (" upper computer "), the positions DG1-L and DG11-U normally containing zero. The signs of computer numbers are dealt with separately in the associated circuits. As indicated in Fig. 43, each cell contains a " A " point at the beginning and a " B " point in the middle, these points being defined by corresponding timed positive and negative A and B pulses. The number-representing signals (e.g. the zero signal, Fig. 43) obtained from the drum reading circuits comprise A pulses, while the signals employed in the computing circuits (e.g. QO AA) comprise mainly A-to-A pulses (see bottom of Figs. 38 and 43). Some timing signals, however, extend from B to B (e.g. QO BB). As well as the signals in Fig. 38, further signals are employed for defining the digit periods DG1-DG11 and the upper and lower computer periods (Fig. 39, not shown). Distributer. The main distributer track 12A, Fig. 9, forms with reading and recording heads 35, 36 and a regeneration circuit 37 a revolver for continually storing one factor in a computation. The same number is recorded on both tracks 12A, 12B but is read out one digit earlier from 12B owing to only a 10-digit spacing between heads 40, 41; the main and " 1-digitearly " distributers are employed for entering values into the lower and upper computer respectively. Computer revolvers. The computer regeneration revolver comprising the track 11A, Fig. 9, and regenerator circuit 25, has a 22-digit spacing between its reading and recording heads 20, 21, while the computer operation revolver has only a 21-digit spacing between its heads 30, 31 to allow for a 1-digit delay involved in adder 33. The lower computer values are read into the distributer from the normal read heads 20, 30 but the upper computer values are read by heads 24, 24A. Circuit details. The circuits 10 and 13 consist of a main computer chassis (Figs. 19-19S, not shown) and an auxiliary chassis (Figs. 40-40H) which comprise primarily crystal diode and " and " or circuits (called " switches " and " mixers "), indicated by groups of unshaded and shaded diodes respectively, double triode inverters and cathode followers. Fig. 28 shows a double inverter in which the anode 84 of the first triode is connected through RC circuit 85, 86 to the grid 87 of the other triode. A positive input at terminal 89 will thus produce a negative output at 97 and a positive output at 98 and 100. Positive resetting pulses may be applied to resetting terminals 93, 95. This inverter, represented schematically in Fig. 27, may be combined with a cathode follower 136, Fig. 35, to form a bi-stable circuit (called " latch unit " or " latch ") similar to those described in U.S.A. Specification 2,628,309. Normally the righthand triode section is conducting (indicated by " X "), but when coincident positive pulses are applied to diode switch 137, 138, the resultant positive pulse at mixer diode 139 and input terminal 142 (corresponding to 89, Figs. 27 and 28) causes conduction in the left-hand section, this condition being maintained by the positive output at 143 fed back to 142 through the cathode follower and mixer diode 140. The latch unit is reset by a positive pulse at terminal 144. In another form of latch unit, the anode output of each section of a double triode is connected to the grid of the other section through a cathode follower. The unit of Fig. 35 may be modified in that the feedback circuit through the cathode follower includes a diode switch whereby the latch unit is held " on " only so long as a positive voltage is applied to this switch and is subsequently automatically reset. Two units of this form are employed in the " A-to A gate generator," Fig. 42, which widens A pulses (zero signal, Fig. 43) into A-to-A pulses. The A-pulse input is applied through diode 165 to the input terminal of the latch unit comprising double inverter 166 and cathode follower 167. The switch 168, 169 in the feedback circuit is operative until a negative B-pulse (NBP) is applied to the diode 169. The output of cathode follower 167, which thus consists of A-to-B pulses, is applied to the input of latch unit 171, 172 which is held " on " for a full A-to-A period until the next negative A-pulse (NAP) is applied to diode 175 of switch 174, 175. The required A-to-A signal is thus obtained on line 173 as the output of cathode follower 172. Addition and subtraction. A number in the distributer may be added to or subtracted from a number in either the upper or the lower computer, the sum or difference being recorded in either of the tracks 11A, 11B, Fig. 9. Either the distributer or the computer value (but not both) may be entered into the adder 33 as a complement according to the signs of the two numbers and whether they are to be added or subtracted. The true and complement values are both entered in true series mode B-pulse form (see Fig. 38) but on separate lines 300, 301. Fig. 57 illustrates those portions of the adder which will be operative when the values 6 and 2 respectively appear on these lines. The adder comprises a series of input latches (such as 7-X, 7-W), one for each of the quinary values 0-4: and binary values 0 and 5, " double " latches (such as 7-M) for registering the fact that the binary or quinary portions of the two input values are the same, quinary carry and no-carry latches (such as " below 5 " latch 8-T), decimal carry and no-carry latches (such as 10-N), and result-registering output latches (such as 11-T, 11-R), the latches being connected through cathode followers (CF) and diode switches (SW). The input latches are connected to the lines 300, 301 through switches to which selective AA timing pulses are applied; e.g. the switches 6-N connecting the B5 latch 7-N to lines 300, 301 have B5AA and BOAA pulses applied respectively as indicated. In the example illustrated, the complement entry BOQ2 will operate B5 latch 7-N and Q2 latch 7-W through switches 6-N and 6-X (the nines complement of BOQ2 = 2 being B5Q2 = 7). The true entry B5Q1 will operate the B5 latch which has been already operated by the complement entry. However, this latch controls switch 6-S to cause operation of a "sample double true " latch 5-Q at B5A time (see Fig. 38). This enables the B5B pulse of the true entry to pass through switch 5-U and operate the " binary double " latch 7-M. The Q1 and Q2 latches, through switches 8-Y, will produce an output from the " 3 " cathode follower 9-Y. Assuming that the complementary addition is being performed in the lowest order, the carry latch 10-N is operated (to add " 1 " and produce the tens complement) and the consequential signal CI applied to switch 10-V causes the Q4 output latch 11-T to be operated to register the quinary result value Q4. The output from 9-Y also operates, through switch 8-Q, the " below 5 " latch 8-T. The latches 7-N, 7-M and 8-T supply a signal through switch 8-N and " 0 + carry " cathode follower 9-N to operate the BO output latch 1