Patent EP-0851561-A3 (EP)
Inventor: MENICHELLI STEFANO
IPC: G11C5/14
Filed: 1997-12-23
Abstract: A voltage multiplier circuit for integrated circuits, comprising
two mirrored sections driven by control signals (PH00, PH01, PH0_N;
PH10, PH11, PH1_N) generated by a logic circuitry which receives, as
input signals, an enable signal (en) and a clock signal (clk), wherein each
mirrored section includes N stages and each stage comprises a capacitor
(C00, C01, C02; C10, C11, C12, C13) having a lower terminal and an
upper terminal, the lower terminal is connected to a first switch (INV0,
PCH01, PCH03, PCH05; INV1, PCH11, PCH13, PCH15) that, in closed
condition, couples the lower terminal of the capacitor to the power supply
voltage (Vpp), said lower terminal of the capacitor being additionally
connected to a second switch (INV0, NCH00, NCH01, NCH02; INV1,
NCH10, NCH11, NCH12) that, in closed condition, couples the lower
terminal of the capacitor to ground voltage (GND), as far as the first stage
is concerned, or to the upper terminal of the capacitor of the previous
stage, the upper terminal of the capacitor is connected to a third switch
(PCH00, PCH02, PCH04, PCH06; PCH10, PCH12, PCH14, PCH16) that,
in closed condition, couples the upper terminal of the capacitor to ground
(GND), the upper terminal of the capacitor (CO3; C13) of the N-th stage is
connected to a last switch (PCH014; PCH114) that, in closed in condition,
couples the upper terminal of the capacitor of the N-th stage to the output
of the voltage multiplier; said control signals directly or indirectly drive
said switches such that, when the voltage multiplier is enabled (en = 1), at
a rate determined by said clock signal (clk), each mirrored section in
alternated times is switched over from a charging phase to a discharging
phase, so that while a mirrored section is in charging phase, the other one
is in discharging phase and vice versa; when a mirrored section of the
circuit is charging phase, the last switch (PCH014; PCH114) and all
second switches thereof (INV0, NCH00, NCH01, NCH02; INV1, NCH10,
NCH11, NCH12) are in open condition, while its first (INV0, PCH01,
PCH03, PCH05; INV1, PCH11, PCH13, PCH15) and its third switches
(PCH00, PCH02, PCH04, PCH06; PCH10, PCH12, PCH14, PCH16) are
in closed condition, so that all capacitors of this circuit section are parallel
connected between the supply voltage (Vpp) and ground (GND) and are 
charged up to a voltage corresponding to said supply voltage (Vpp), with
the upper plate at ground and the lover plate at the supply voltage (Vpp);
when a mirrored section of the circuit is in discharging phase, all its first
(INV0, PCH01, PCH03, PCH05; INV1, PCH11, PCH13, PCH15) and third
switches (PCH00, PCH02, PCH04, PCH06; PCH10, PCH12, PCH14,
PCH16) are in open condition, while its last switch (PCH014; PCH114)
and all its second switches (INV0, NCH00, NCH01, NCH02; INV1,
NCH10, NCH11, NCH12) are in closed condition, so that all capacitors
are serially connected with one another, the lower terminal of the
capacitor (C00; C10) of the first stage being connected to the ground
voltage (GND) and the upper terminal of the capacitor of the N-th stage
being connected to the output of the voltage multiplier; when the voltage
multiplier is disabled (en = 0), both mirrored sections of the circuit are in
charging phase.