Patent GB-735522-A (GB)
Title: Improvements in or relating to electrical circuits
Inventor: BRANCH MAURICE CHARLES
IPC: H03K23/82
Filed: 1952-07-07
Abstract: 735,522. Automatic exchange equipment. STANDARD TELEPHONES & CABLES, Ltd. July 7, 1952, No. 16985/52. Class 40 (4). [Also in Group XL (c)] In an electrical circuit arrangement for generating a pulse train under the control of a number register, the register is initially set to store one of a predetermined set of numbers, which setting results in the opening of a static electrical gate circuit through which pulses may be passed to an output circuit; pulses are then applied simultaneously to the gate circuit, and to the register, each pulse altering the setting of the register until the register stores a number which is not one of the predetermined set of numbers, whereupon the gate circuit is closed. In this way an output pulse train is produced which bears a predetermined relation to the initial setting of the register. As described, the register is initially set to store the complement with respect to fifteen of the number of output pulses required, the pulses applied to the register each step it on one, and when the register stores fifteen the gate is closed. Register (Fig. 1). This comprises a fourstage binary counter, forming the subjectmatter of Specification 735,515, [Group XL (c)], in which each stage consists of a triggered pair, e.g. L, M. In the normal condition L, N, Q, and S are discharging and the anode voltage of each is approximately - 30 volts. Thus, none of the gate tubes G1 to G4 can fire to the first impulse pulse, which fires M and extinguishes L. The second pulse fires G1, the output pulse of which fires L and O, but is ineffective on G2 (MR1 conducting). The third pulse fires M only. The fourth pulse fires G1, which fires L and G2, the output pulse from which fires N and R. Operation continues in like manner and the input pulses set the register tubes in accordance with the binary code for each successive digit. Initially a pulse train is sent into the register to cause it to store the complement with respect to fifteen of the digit to be re-transmitted under its control, i.e. the train is from fourteen to five pulses corresponding to digits one to zero. Out-pulsing gating circuit (Fig. 2). This comprises a cold cathode tube CT which functions as a gate, to the trigger electrode of which input pulses P are applied under the control of five coincidence circuits such as MR21, MR2. The individual rectifiers of these coincidence circuits are connected to the anodes of the counter tubes (L to T, Fig. 1) in such manner that if the register is storing a number between five and fourteen, inclusive, all the rectifiers of at least one coincidence circuit are non-conducting. In such circumstances the pulse P is passed via a decoupling rectifier such as MR12 to the trigger electrode of tube CT. As each pulse P is also applied to the anode of CT, this tube will then fire and give an output pulse from its cathode. This pulse is applied to the counter to step it on, and also operates a sender tube which delivers a 66 m.sec. pulse, for example a flip-flop circuit. When the counter has been stepped on to register fifteen, at least one rectifier of each coincidence circuit is conductive so that further pulses P are ineffective to operate CT. Control circuit for resetting counter and timing the inter-digital pause (Fig. 3). If it is desired to use the counter of Fig. 1 to time the inter-digital pause it is stepped by pulses X (Fig. 3), out of phase with the P pulses, the application of which is initiated in response to the first pulse passed by CT (Fig. 2), and is stopped when the counter is set to store four. Initially the tube B (Fig. 3) is discharging and a reset connection (not shown) may be provided to fire B and set the counter to zero when switching on initially. In normal operation, however, when the counter has been stepped through zero to store four, the tubes T, Q, O and M (Fig. 1) are non-conductive and rectifiers MR33 to MR36 are biased positively from the anodes of these tubes via terminals 8 to 11 respectively. The next P pulse is then applied via R9 and R10 to the trigger electrode of G5. The sole anode supply of G5 is the P pulse source, which is disabled during the initial insertion of the number into the counter, but is now enabled. G5 therefore fires and its cathode output pulse fires B and extinguishes A, and is also applied via terminal 5 (Fig. 3) and terminals 1 to 4 (Fig. 1) to the left-hand counter tubes thus setting the counter to zero. A number is then inserted into the counter, pulse supply to CT (Fig. 2) being disabled during this process, and enabled when re-transmission of the number is required. When CT commences to pass P pulses, they are applied from its cathode to terminal 6 (Fig. 3), so that the first pulse fires A. MR31 is thus rendered non-conductive so that G6 can fire to the next X pulse. G6 then passes the X pulses from terminal 7 (Fig. 3) to the drive input lead on the left of Fig. 1 to step the counter on through fifteen to four. In that condition the cycle is restarted, B firing and resetting the counter to zero ready for the insertion of the next number. The extra five X pulses used to step the counter from fifteen to four result in the counter reaching four 550 m.secs. after CT last fired, and the next P pulse 50 m.secs. later resets the counter to zero. Allowing 66 m.secs. for the last output pulse of the preceding digit, the interdigital pause is 634 m.secs.