Patent GB-1105694-A (GB)
Title: Calculating machine
IPC: G06F7/52
Filed: 1965-02-04
Abstract: 1,105,694. Electronic calculators. COMPUTRON CORPORATION. 4 Feb., 1965 [6 Feb., 1964], No. 4990/65. Heading G4A. An electronic desk calculator has a delay line store comprising a plurality of registers H.4120 arranged in interleaved fashion. The contents of the registers are displayed on a cathode ray tube. The calculator can perform the four rules and also accumulative multiplication and division. Each of the three working registers has an associated backing register called a " surrogate " register. Numbers are stored in the calculator in floating-point binarycoded decimal form. General arrangement.-The calculator. Fig. 1, has a cathode ray tube display 14 and a keyboard 12, Fig. 2, comprising ten digit keys 0-9, a decimal point key 102, positive and negative sign keys 116, 118, arithmetic operation keys 134-144, register selection keys 104-112, register exchange and transfer keys 120-126 and a clear key 114. Keys 128-132 control transfers to and from the surrogate register. The C.R.T. displays the contents of two 15-decimal-digit registers K, Q and a 30- decimal-digit register P. The calculator operates in a succession of " phases ", there being 64 possible phases controlled by the states of six flip-flops U, V, W (Fig. 5, not shown) and X, Y, Z (Fig. 6, not shown). Depression of a function key causes the calculator to enter a routine for that function, the routine consisting of a series of phases which may occur in groups or loops. Timing arrangements.-The calculator timing system (Figs. 14-17, not shown) comprises a chain of flip-flops T0-T12, P, K, fed by clock pulses Cp. A machine cycle, which lasts 30 ms, is divided into two half-cycles K and K corresponding to the state of a flip-flop. K, each half-cycle corresponding to 30 character periods. Each character consists of 4 bits, and may be a decimal digit or sign character. Each bit period, except one, is divided into 120 clock periods. The calculator has a magnetostrictive delay line memory, Fig. 20, of 480- bit length, which corresponds to a 240-bit working memory consisting of two 15-character registers K, Q and a 30-character register P, together with a 240-bit " surrogate " (backing) memory similarly divided. The recirculation time of the memory is one character period. The registers K, Q consist of 12 decimal digits, a sign character and two characters which together constitute a decimal point position indicator. The register P consists of 24 decimal digits, a sign character and two decimal point characters, there being three non-significant characters. Each character period is divided into bit periods each bit period except the first being divided into four quadrants each of 30 one microsecond clock periods. The first quadrant of the first bit period of each character, however, marks a dead period during which the generation of clock pulses is suspended until resumed upon the occurrence of a marker pulse derived from the memory. Flip-flops M, S, (Fig. 19, not shown), hold a " working " bit and its associated " surrogate " bit respectively, throughout the greater part of each bit period, the bits being recorded (after possible processing) in the next bit period. Each read character from the working memory is transferred to a one-character register D (Fig. 33, not shown) comprising four flip-flops D1-D4, these four flip-flops being scanned in the succeeding character period. Data read from the memory is returned thereto after a delay equal to one character period short of a full machine cycle unless it is transmitted via the D register in which case the registers are circulated unchanged. A further register E (Fig. 33, not shown) is provided to act as a temporary store. In each register two adjacent characters are employed jointly to store a 6-bit decimal point indicator capable of indicating up to 64 different point positions, the normal point position being immediately to the left of the most significant digit, the corresponding sign character being 111111 (= 63). Sub-operation phase groups; (1) Delay P. The register P is interdigitated by character with the registers K and Q in series. To perform an arithmetic operation between the K and P registers, the two registers must be aligned by shifting to P register leftwards, the sign character acting as a marker for the most significant digit in the P register. A delay number indicating the number of shifts required is held in the E register. To effect the shift, the content of E is first transferred to a storage in a part of the P register, the contents of the P register then being circulated via the D and E registers to provide a one-character delay, the delay number and decimal point being incremented at each memory cycle, this process continuing until the delay number reaches zero. (2) Advance-P. To advance the P register, i.e. shift to the right, a delay number of appropriate sign is entered in the E register, only the numerical digits P are shifted and at each shift step, the most significant digit is set to zero and all the other digits are shifted to the right, the least significant digit being lost. This process continues until the delay number reaches zero. Each shift step of the advance P operation is performed in two half cycles, in the first of which the K, Q, and P registers are all advanced one step by being directly recorded and, in the second of which the K and Q registers are delayed by two steps by being temporarily recorded in the D register. (3) Advance-Q. This is effected in two separate phases. If the advancement of the Q register is necessitated by an overflow into the sign character Sq, in a division process, Sq is decreased by one to correct the overflow and also the most significant digit if Q is filled with a " 1 " instead of a " 0 " (4) Add-to-P. This effects the addition of the content of the K register to the content of the P register. The commencement of the addition depends on whether the P register has been shifted. If the P register is shifted left by 12 places left, each digit of the K register is aligned with a digit of the P register. If the P register is left shifted by more than 12 places, the addition process starts only with the least significant digits of the P register which appears after Sp (the sign digit). If the addition of two binary-worded decimal digits results in a sum in the range 9-15, a carry must be propagated and 6 must be added to the sum, a flip-flop C (Fig. 43, not shown) indicating when this is necessary. In a similar way the content of K can be subtracted from P. (5) Augment Q. If the P register contains a negative number as the result of a subtraction, one of the digits of the Q register is augmented by unity, the particular digit incremented being determined by the content of the E register. (6) Controls are also described for complementing the P and Q registers by subtraction from zero. Arithmetic Operations.-(1) Add-subtract routine (Fig. 9, not shown). A flip-flop J is set to " 1 " for subtract and to " 0 " for add, the state of the flip-flop being reversed if a negative sign is detected in either K or P register. If the flip-flop J is left at " 1 ", the P register is complemented before addition takes place. (2) Multiply routine (Fig. 10, not shown). According to which key 138 or 142 is depressed, the calculator enters a clear and multiply or an accumulative multiply routine. A delay number is formed dependent on the values of the sign digits in the K, Q and P registers, thereby initiating an advance-P or delay-P operation. In the clear and multiply routine, the P register is cleared before the operative multiplication steps commence which is effected by repeated addition and shift. (3) Divide routine (Fig. 11, not shown). A clear and divide or accumulative divide operation may be selected according as a key 140 or 144 is depressed. Division is accomplished by repeated subtraction and shift, the quotient being built up by incrementation in the Q register. (4) Restore P routine. This routine is effective, after an arithmetic operation, to correct the sign digit of the P register, if this digit has been altered in the operation, and to shift it back to its standard position. In addition, the most significant digit in the P register is shifted to the left-most position (unless all the digits are zero). Number entry.-Depression of a P, Q, K and Q, or K register key 104, 106, 108, 110 causes flip-flops k and q (Fig. 46, not shown) to take states representing the required registers, thereby initiating clearance of the selected register, clearance taking place automatically if an arithmetic operation key is depressed. Operation of the " automatic K select " key 112 causes all numbers to be entered in the K register. The four flip-flops E1-E4 of the E register are effective to count the digits entered so that only up to 16 digits can be entered in any register. On entry to a register the register is first cleared, its sign digit made normal positive and the decimal point indicator made 63. The first digit is then placed in the most significant position and the decimal point indicator altered to indicate the shift of the decimal point one place to the right, this shift continuing with each digit entered until the decimal point key 102 is depressed to fix the decimal point. The E flip-flops mark the position next to be filled. If the first digit key depressed is the zero key, the decimal point is moved one place to the left for this and each subsequent zero entered, subsequent depression of a non-zero digit key causing the digit to be placed in the most significant position, further depression of digit keys causing no change in the decimal point position. The "enter digit " routine is described with reference to Fig. 13 (not shown). Number display.-The contents of the K, Q and P registers are displayed on a cathode ray tube 14, Fig. 1, there being four zeros of smaller size continuously displayed to the left of th