Patent GB-1073497-A (GB)
Title: Signal detection system
IPC: G11B20/14
Filed: 1966-01-21
Abstract: 1,073,497. Data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Jan. 21, 1966 [Jan. 22, 1965], No. 2779/66. Heading G4C. [Also in Division H3] A signal detector for detecting signals of the type in which a clock interval includes a clock pulse, a data pulse also being present or absent depending on the bit value, comprises a data detector receiving said binary signals and having a circuit whose cycle time is adjusted in dependence on the presence or absence of pulses on an output data line, an output clock line also being provided. In a first embodiment (Figs. 1-3, not shown), the input binary signals (b) are passed to a first timing circuit (11) in which each pulse resets a ramp generator via a transistor (26), the circuit producing a pulse on an output data line (d) whenever the ramp reaches a threshold set by a voltage applied (i) to a second transistor (28). In fact such a pulse is produced in each clock interval not containing a data pulse in the input, since there is sufficient time between two clock pulses for the threshold to be reached. Since two clock pulses without a data pulse between them tend to arrive at the input, which is from a dynamic magnetic store, displaced towards each other, a second timing circuit (12) similar to the first (11) is fed by the output data line (d) and on detecting a pulse on this line, raises the threshold in the first timing circuit (11) to an intermediate value, the threshold being dropped again as soon as a clock interval occurs without a pulse on the output data line (d). This compensates for displacement between two clock pulses, and between a clock pulse and a following data pulse. The input binary signals (b) are also applied through a delay (13, e.g. monostable multivibrator or capacitor) to a monostable multivibrator clock detector (14) which produces clock pulses on an output clock line (g), an output clock pulse being terminated by a delayed input clock pulse, the next output clock pulse starting a predetermined decay period later or when a pulse occurs on the output data line (d) whichever is the sooner. The decay period is less than the normal clock interval and greater than the maximum period between consecutive clock and data (input) pulses, so if the message starts with a clock pulse, the clock detector ignores input data pulses. During each output clock pulse (g) the threshold in the first timing circuit (11) is raised to a high level, over-riding control from the second timing circuit (12), thus compensating for displacement between a data pulse and the following clock pulse. The leading edge of each output data pulse (d) is in synchronism with the leading edge of an output clock pulse (g). In a second embodiment (Figs. 4, 5, not shown), the input binary signals (j) are delayed (31) by the pulse width and used to trigger a "data gate " (32), which is a monostable multivibrator with time constant adjustable by changing the voltage on the timing resistor or by gating another resistor in parallel with it. The message starts with a clock pulse so that in view of its time constant, the " data gate " (32) never responds to the input data pulses and produces pulses of sufficient width to gate (33) the input data pulses, through a single shot (36) which widens them to enable them each to gate (37) the following output clock pulse (m) to the output data line (o). The output clock pulses are obtained by gating (35) the input binary signals (j) with the inverted output of the " data gate " (32). The leading edges of the output data pulses (o), which of course arise from clock intervals containing an input data pulse, trigger a single shot (38) to produce pulses which last for about one clock interval and which lower the time constant of the " data gate " (32) while they last. Thus the time constant is at the lower value during (only) each clock interval following a clock interval having a data pulse.