Patent GB-1049185-A (GB)
Title: Improvements in or relating to a data processing system
IPC: H04L12/54
Filed: 1963-11-25
Abstract: 1,049,185. Electric digital data-storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 25, 1963 [Dec. 7, 1962], No. 46380/63. Heading G4C. A data processing system includes a plurality of series-connected delay elements each preceded by a gate to route a record, i.e. a group of data either through or past the respective delay element. Stacking system.-A stacking system allows records arriving at random intervals to be stored without intervening gaps in a circulating memory. In Fig. 3 (not shown), a record source 110 provides a record in some or all of a regularly-continuing sequence of record intervals (each say 1 m.sec. long). Each record is delayed an integral number of record intervals in a chain of delay elements D1, D2, D3, D4 having delays of 1, 2, 4, 8 record intervals respectively before being read into a circulating memory. Each record is preceded by a marker pulse which goes to an inverter 124. A sector pulse source 123 (which may be an oscillator synchronized with the circulating memory or a sequence of pulses recorded in the memory) supplies one pulse per record interval to an AND-gate 122. Thus a binary counter 121 counts down one every time a record interval starts without a record concurrently arriving from source 110. Counter stages control AND- gates, e.g. 125, 126, to route the record through or around each delay element D1, D2, D3, D4, so that when the records emerge from the delay chain into the circulating memory no record intervals are empty. The circulating memory may be a magnetic drum, disc or endless tape. Fig. 5 (not shown) shows a modification in which the counter 121 is replaced by a counter 135 comprising a closed loop in which a binary control word circulates once per record interval (Dc being a one-record-interval delay). The control word is reduced by one every time an empty record interval starts (as before) by means of a flip-flop TB which is set to one at the beginning of each record interval if a record is not received, and controls an exclusive-OR gate 136. Flip-flop TB is reset to zero by any bit of the control word (other than the first) which is a one, after this has been delayed one bit interval at D. When a record is received, the control word is also routed in front of it along the delay chain (by-passing each delay), successive bits setting to one or leaving at zero successive flip-flops T1, T2 . . ., AND-gate 153 giving access to the flip-flops for this purpose being successively enabled by a bit ring 133. A modification to Fig. 5 is mentioned in which each incoming record is preceded by a binary representation of its number (i.e. the first record is number one, the second number two &c.) which is compared in a subtraction unit with a count representing the position of the circulating memory. At the beginning of each record interval, this is done in turn for the records currently approaching the gates preceding each delay of the chain. The gates are controlled in accordance with the results of the comparisons. Feeding system.-A. feeding system is a delay chain which, by provision for recirculation within each delay, provides a buffer store enabling successive records in a circulating store to be obtained at irregular intervals. Fig. 9 (not shown) shows two delays D1, D2 of a chain of four D1, D2, D3, D4 having delay times of 1, 2, 4, 8 record intervals respectively. Delay D4 is nearest the circulating memory. Initially 1, 2, 4 and 8 records from the circulating memory are stored in the delay elements D1, D2, D3 and D4, respectively, in which they recirculate indefinitely until the first record is demanded from the chain. A binary counter comprising flip-flops G1, G2 ... counts pulses (from AND- gate 223) one of which arrives each time a record interval starts in which a record is not demanded from the chain. The flip-flops G1, G2 ... control AND-gates 224... 227 ... to route records through or past each delay element D1, D2.... A record emerging from a delay element is passed to the next stage or recirculated depending on the state of a flip-flop H1, H2 .... During the first bit interval of each record interval a pulse Cs is present at OR-gates 233, 233<1> . . . and if the state of the appropriate flip-flop Gi is one, this pulse is routed into the delay ahead of the record. This pulse is lost on recirculation but if Gi is one a new pulse will be provided via OR-gate 233, 233<1> .... Thus each record in a delay is preceded by a bit representing the value of Gi when it (last) entered the delay element. On emergence of the record from the delay, this bit is compared with the current value of Gi in an exclusive-OR gate 234, 235... to control the corresponding flip-flop Hi. A modification is mentioned in which each record is preceded by a binary representation of its number (plus an extra control bit) and at the beginning of each record interval the representations at the inputs to the various stages are sampled in turn to control routing of records. Queuing system.-A queuing system consists of a stacking system followed by a feeding system, the two having one stage in common and cross-connections between corresponding stages in the two to enable the intervening delays to be avoided when they are all empty (Fig. 13, not shown). A modified queuing system, formed from the Fig. 5 stacking system and the related feeding system and using a single set of control logic shared between the two component systems, is mentioned and would not require the cross-connections for the stated purpose. Multiplexed queuing system.-Figs. 14-16 (not shown) show a queuing system arranged for time-division-multiplex operation, four pairs of input and output channels being successively connected to the queuing system the delays of which are four times as long as previously. Flip-flops Gi, Hi as in Fig. 9 are provided for the feeding system part and flip-flops corresponding to the stages of the counter 121 of Fig. 3 (but controlled individually) for the stacking system part are provided. Flip-flops Hi are controlled as in Fig. 9 but the other flipflops are controlled by respective bits of a control word circulating in a loop comprising a one and a three record interval delay in series. Successive quarters of the control word relate to successive channels and only the quarter in the one record interval delay (which is tapped) is effective. The control bits corresponding to the stages of counter 121 in Fig. 3 are the inverses of the contents of the counter stages so that the same logic circuitry, incorporated in the loop, may be used for modifying all parts of the control word (i.e. now all counting is up). A high-speed channel may be obtained by combining two or more of the above channels together, in the sense that records arriving in the high-speed channel are fed to the " combined " channels in turn. It is also mentioned that provision may be made for overloaded channels to borrow space from other channels or to be connected in series with whole (spare) other channels, utilizing interposed delays for proper phasing. Message exchange systems.-Figs. 17, 18 (not shown), show a telephone exchange system utilizing a solenoid-operated switching matrix for routing a message arriving on one of a number of incoming lines to one of a number of outgoing lines with one of three priorities. Each row of the switching matrix is fed by one incoming line via a queuing system. Each column of the matrix relates to a particular priority for a particular outgoing line and feeds that outgoing line via a queuing system and priority logic. The message is stored in the queuing system present in its incoming line until the appropriate column of the matrix is free when the message is transferred to the queuing system in that column. The message is transferred to the outgoing line when the queuing systems relating to higher priorities for that outgoing line are empty and previous messages in the same queuing system have gone. Fig. 19 (not shown) shows a message exchange system using time-division multiplexing, comprising a 256-channel queuing system, successive record intervals in a 256-interval cycle being used by successive channels for receiving and delivering messages (records). Messages on 64 incoming lines are time-division-multiplexed on to a single line and fed into the first 64 channels during the first 64 intervals. During the same intervals messages are taken from the same channels, examined for destination and priority and each passed via a tapped delay line back to the queuing system to be stored in one of the last 192 channels depending on the destination and priority (one channel for each priority for each destination). During the remaining intervals of the cycle, outputs from these latter channels are obtained and then demultiplexed on to 64 outgoing lines. It is arranged that only one channel relating to a given outgoing line delivers a message at a time, this channel being the highest priority non- empty channel of the three relating to that outgoing line. Control of routing into the tapped delay line may occur through the intermediary of a control word inserted in front of the message. It is mentioned that messages longer than one record interval may be dealt with (and transferred from the queuing system in one piece) provided the message is preceded by a control word specifying its length or both preceded and followed by marker words. The single multi-tap delay line of Fig. 19 (not shown) may be replaced by a shorter tapped delay into which the messages from channels 1-64 are fed several times in succession, being stored in an extra delay loop in between (Fig. 20, not shown), or the length of the tapped delay may be further quartered by replacing the extra loop by four quarter-length loops (Fig. 21, not shown). A magnetic core memory may alternatively be used for the transfers from channels 1-64 to channels 65-256. Delay elements.-Spiral recording tracks on three syn