Patent GB-1338633-A (GB)
Title: Digital frequency generator
Inventor: JACOB J-B
IPC: H03L5/00
Filed: 1971-05-28
Abstract: 1338633 Selective signalling SOC LANNIONNAISE D'ELECTRONIQUE and COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 28 May 1971 [28 May 1970 15 June 1970] 18141/71 Heading G4H [Also in Divisions H3-H5] A frequency generator comprises a digitallycontrolled oscillator and a digital stabilization network connected to control the output level of the oscillator. Fig. 1 shows the generator. Apart from clock pulses at H, defining sampling periods T, all the signals shown are m-bit digital numbers, the output at Y from a digital oscillator 1 during each sampling period representing the amplitude at that time of a notional sinusoid of frequency determined by B 1 . Subtractor 2 obtains the difference of modulus Y and Y M  (the average amplitude of the required sinusoid), the result D feeding a digital filter 3, the filter output SF being thresholded at 4 to give a control input B 2  for oscillator 1 which equals 1 for SF between + <SP>1</SP>/ 100  Y M  and -<SP>1</SP>/ 100  Y M , equals <SP>101</SP>/ 100  for SF less than -<SP>1</SP>/ 100  Y M , and equals 99/100 for SF greater than <SP>1</SP>/ 100 Y M , and acts to stabilize the amplitudes represented by the numbers produced at Y. Fig. 6 shows the digital filter 3, controlled by inputs K 1 , K 2  to be low-pass with a resonance at zero frequency. The symbol L denotes log to base 2 modified so that log 0 is finite. K 1 , K 2  are stored in log form at 44, 47. The filter output SF is converted to log form at 31 and stored at 45, 46 to give delays of one and two sampling periods T respectively, these stored values LSF 1 , LSF 2  being added to LK 1 , LK 2  at 25, 34, converted back to linear form at 28, 37 with change of sign, and added at 30, 38 to each other and the filter input D, giving the filter output SF = D-K 1 .SF 1 -K 2 .SF 2 . Thus multiplication is done by addition of logs. 26, 35, 32 are correction memories and 27, 36, 33 are correction adders (purpose not described). The digitial oscillator 1 may use the same calculation circuitry (below the dashed line in Fig. 6) as the filter 3, in a different portion of each sampling period, fed from stores holding LB 1 , LY 1 , LY 2 , LB 2  instead of stores holding LK 1 , LSF 1 , LSK 2 , LK 2  respectively, the input corresponding to D being zero, to produce an output Y = -B 1 Y 1 -B 2 Y 1 . Here Y 1 , Y 2  are the output Y delayed by one and two sampling periods respectively. The output Y, before being used to derive Y 1 , Y 2  and give the generator output Y shown in Fig. 1, is passed through an automatic starter circuit which simply substitutes Y M  when both Y 1 , Y 2  are zero (i.e. initially). In Fig. 7, the digital oscillator 1, with its calculation circuitry 5, and the stabilization feedback via digital filter 3 and thresholder 4, is used to produce pairs of frequencies for telephone dialling, actuation of a selected one of ten keys on a keyboard 53 producing a corresponding pair of frequencies by supplying to calculation circuitry 5 the following quantities in turn during each sampling period: B 1  for the first selected frequency, LK 1  for the stabilization calculation for this, B 1  for the second selected frequency, LK 1  for the stabilization calculation for the latter. The values B 1  come from a matrix memory 55. In each sampling period, the digital outputs Y for the two frequencies are stored at 49, 48 respectively, and added at 50, the sum being stored at 51 and converted to analogue form at 52.