Patent GB-838681-A (GB)
Title: Improvements in or relating to digital transmission systems
IPC: H03M13/17
Filed: 1958-08-08
Abstract: 838,681. Electric data transmission systems. WESTERN ELECTRIC CO. Inc. Aug. 8, 1958 [Aug. 15, 1957; May 1, 1958], No. 25500/58. Class 40 (1). The accuracy of transmission of digital data over a noisy transmission line 30, Fig. 1, is checked by progressively stepping the data in serial form through a shift register 24, a check digit calculating circuit 26 being connected to spaced digit positions and a switching device 28 for interleaving a check digit between each pair of data digits at a point in the train spaced from the digits which are checked by that check digit. Since errors usually occur in " bursts " the transmission of the check digit at one time and the corresponding data at another time, reduces the chance that both will be affected by the same burst of errors in the line. The shift register has additional stages between each of the stages shown so that when shift signals are applied there are intervals in which the check digits can be inserted by switch 28 synchronized with the shift signals. In the form shown in Fig. 1 the check digit, " 0 " or " 1 " derived from stages 1 and 4 is inserted in front of the 7th digit. At the receiver the switch 32 synchronized with switch 28 sorts the data digits into shift register 34 and the check digits into register 36. When the digits which were in positions 1 and 4 of register 24 arrive in positions 1 and 4 of register 34 the check digit was then calculated is in position 7 of register 36. A circuit 38 derives a check digit from the bits in positions 1 and 4 of register 34 and compares it with the previously calculated check digit in position 7. If no errors in transmission have occurred they should be the same, but if they differ there is an output signal. When the data digits have moved a further three places to positions 4 and 7, the previously derived check digit is in position 10 of register 36. A second circuit 40 calculates a check digit from positions 4 and 7 and compared it with the contents of position 10. A signal is produced on disagreement. If circuits 38 and 40 both produce a signal it indicates almost certainly that the common digit in position 4 is erroneous. And gate 42 accordingly responds and causes an inverter switch 44 to become effective to reverse the digit in position 4 as it passes to position 5. By this means an erroneous digit is corrected before being transmitted to the utilization circuit 46. The circuits deriving check digits produce a binary " 0 " if both inputs (e.g. positions 1 and 4 of register 24) are the same, and a " 1 " if they are different. If the circuit 40 gives an error signal and circuit 38 does not, an error in the check digit in position 10 is indicated since if the error were in position 4 of data register 34 circuit 38 would give an error signal too. The digit in position 7 has already been corrected so the error cannot be here. If the data is to be transmitted further the check digit in position 10 can also be corrected. The circuit of Fig. 1 will usually correct bursts of six errors or less but for longer bursts it produces an alarm signal as shown in Fig. 4. A signal from check circuit 38 causes a start circuit 50 to start counter 52. A " burst classification " circuit 54 compares output signals from the check circuits 38 and 40 during successive time periods with outputs representing correctable bursts which can be handled by the correction circuits. Signals from the check circuits are tentatively classified as data digit errors or check digit errors so that by examining the sequence of operation of the two check circuits error sequences other than correctable ones can be recognized and an alarm circuit 56 energized. The counter 52 may take the form of a stepping switch and the other components may be provided by relay circuits. Reduced redundancy.-In the form of Fig. 7 the number of added check digits is reduced, only one being added for every three data digits. Three shift registers 66, 68 and 70 are provided with data from line 72 by a switching circuit 74 and input buffer store 76, one third of the digits being routed to each shift register in turn. The check circuit 78 derives check digits from positions 1, 3 and 5 of register 66, 7 and 11 of register 68 and 13 and 15 of register 70. The three registers and circuit 78 are coupled to a buffer circuit 80 and applied by a switching circuit 82 to the transmission line. The receiver, Fig. 8, has a switching circuit 84 distributing the signals to registers 86, 88, 90 and 92 respectively, three check digit circuits R, S and T being provided, each connected to stages of all four registers. Error correction takes place between positions 5 and 6 of register 86, positions 11 and 12 of register 88, positions 17 and 18 of register 90 and positions 23 and 24 of register 92. The check circuits R, S, T compare the check digits in positions 19, 21 and 23 with check digits derived from positions 1, 3 and 5; 3, 5 and 7 and 5, 7 and 9 of register 86. If each gives an error signal the digit in position 5 must be wrong and gate 98 accordingly causes this digit to be inverted. In register 88 the digit in position 11 is included in the groups checked by circuits R and T but not S and the correction circuit 102, 104 for this digit is energized by error signals from circuits R and T and a noerror signal from circuit S. Similarly the digit in position 17 of register 90 is corrected if circuit R produces a no-error signal while circuits S and T produce an error signal. Since an error in the digit position 23 of check digit register 92 will give an error signal from circuit T only this digit may be corrected by a similar circuit if such a signal is combined with a no-error signal from circuits R and S. Instead of three separate check circuits R, S, T a single circuit can be used operating with a short shift register through which the check signals are shifted in time with the shift of data in the main registers. The form shown in Fig. 12 has a shift register 134 through which the data digits are passed and a four-stage register 136 for the check digits. Circuit 138 derives check digits from positions 1, 4 and 7 of register 136 and from position 13 of register 136. These are interleaved with the data digits as before and applied to lines 142 being separated by switch 144 at the receiver into registers 146 and 148. Three check circuits R, Sand T are connected to stages of the receiver registers corresponding to the connections to circuit 138. All three circuits R, S, T are coupled to position 7 of register 146 and an error signal from all of them causes this digit to be changed. An error signal from circuits R and T and a " no-error " signal from circuit S produces an output from gate 168 to energize an alarm 162. The inverse signals cause gate 166 also to produce a signal for the alarm. Other combinations require no action. This circuit corrects all error bursts of six digits and some of more than six are connected. All error bursts of up to thirteen digits are detected. The. registers may be constituted by chains of relays or in high-speed systems delay lines could be used. Specification 697,744 is referred to.