Patent GB-1347832-A (GB)
Title: Dividing device for normalizing and dividing decimal numbers
IPC: G06F7/52
Filed: 1972-01-27
Abstract: 1347832 Decimal dividing circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 27 Jan 1972 [30 Jan 1971] 3856/72 Heading G4A A divider for dividing decimal numbers according to the method of division without restoration of the remainder includes dividend, divisor, and quotient registers, the highest ordered divisor digit being 0. Division takes place in sequences of additions and subtractions, the remainder resulting from each operation being stored in the dividend register. Prior to the start of division the circuitry determines whether the divisor digit of the highest order but one is less than 5. If it is, both the divisor and dividend are normalized by being multiplied one or more times by a certain factor. When the highest ordered but one divisor digit is #5 the normalization is complete. During the division if the two highest ordered digits of a remainder are <05 or #95 the remainder is shifted into the next higher ordered state and a quotient digit is placed in the lowest order of the quotient register. The normalization reduces the number of division steps that would otherwise be needed. In the example shown in the left hand part of Fig. 2 the dividend is 455 and the divisor 305, these numbers being placed, in binary decimal form, in the appropriate locations in the divisor and dividend registers. Since the divisor digit (3) of highest order but one is less than 5 normalization takes place, by multiplying by 2 in this example. Only one multiplication is necessary here. Division starts with the subtraction of the normalized divisor from the normalized dividend, resulting in a remainder 03000, which is placed in the dividend register. A counter Z is incremented or decremented at each subtraction or addition. Since the remainder is <05 the remainder is shifted one place left, the Z count 1 is set in the quotient register QTR, and the counter is reset to 0. Subtractions continue. After the fifth of this set of subtractions the remainder is negative and is >95. The Z count is decremented by one and the result passed to the quotient register. The remainder is shifted left and the Z count is reset to 0. As the remainder is negative, addition now takes place. In this example, after only one addition the remainder becomes positive resulting in the Z count 9 being passed to QTR, the remainder 01100 being shifted left, and subtraction taking place. Because the result of the first subtraction is <05 the left shift occurs again, Z count 1 is placed in QTR, and subtraction continues. Division continues in like manner until a desired degree of accuracy in the quotient is attained. The number of steps in the division may be reduced by causing a further left shift if the content of the dividend register after a left shift is still <0À5 or #95. In the example shown in Fig. 2 when the quotient 000014 has been developed the remainder is 95000. Prior to a second left shift, as shown at the right hand side of Fig. 2 the Z count is decremented to 9. When the left shift takes place the Z count is passed to the quotient register, the Z counter reset to 0, and the remainder 50000 held in the dividend register. Additions now take place as before. When the remainder reaches 00200 (i.e. <05) two left shifts take place as shown at the bottom of the right hand column, followed by subtraction of the divisor. In a further arrangement, Figs. 3 and 4 (not shown), instead of performing a second left shift as described above, a shift of two places to the left takes place. In this arrangement there is no Z counter, and the divisor and dividend registers include an additional high order stage, the dividend stage being set initially to 0 and divisor stage being set permanently to 9. Addition and subtraction take place as though the values in the additional stages were part of the divisor and dividend. When the remainder is <05 or #95 a single place left shift of the dividend register takes place, the value in the additional stage being passed to the quotient register. When the remainder is <005 or #995 a two place left shift occurs, with the values of the additional stage and of the highest-ordered stage of the remainder passing to the quotient register.