Patent GB-806782-A (GB)
Title: Electrical signal storage systems
Inventor: NEWMAN EDWARD ARTHUR
IPC: G11B5/008
Filed: 1954-03-30
Abstract: 806,782. Electric digital-data-storage apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. June 23, 1955 [March 30, 1954], No. 9337/54. Class 106 (1). In a device for extracting blocks of data from a serial store (e.g. magnetic tape), each block of data having an index number or address, the addresses of the blocks of data which are required to be extracted-i.e. the wanted addresses-are stored in a cyclical access store and each is compared with the address of each block of data one block-period before the block becomes available for reading out of the store, the block only being read out if it is one of the wanted blocks. When the period of the cyclical wanted address store is greater than one block-periodi.e. when all the wanted addresses cannot be compared with the address of the next block to become available in one block-period-then one or more preliminary sorts of the wanted addresses are made into one or more subsidiary stores until a subsidiary store holds no more addresses than that number that can be compared with the address of a block in one blockperiod. In a first embodiment, Fig. 1, where the period of the wanted address store is less than one block-period, and where each data block comprises a multiplicity of digits stored in eight parallel tracks TR1-TR8 on a magnetic tape main store A, the address, assumed to comprise six digits, of each data block is read serially by a head HN positioned one block period in front of data read heads HR and is staticized in triggers S1-S6 under control of a clock pulse CPA, which occurs at the beginning of each data block. Each of the wanted addresses, stored in parallel on six tracks on a circulating magnetic tape B, is compared with the address staticised on triggers S1-S6 by " not-equivalent " devices E1-E6, each of which only produces an output upon the simultaneous receipt of two different inputs, and as a result if the staticised address is one of the wanted addresses a trigger T2 is put on thus permitting, by causing a trigger T3 to be set on at the appropriate time, the read-out of the data block when it reaches the reading heads HR. The pulse from gate G1, signifying a coincidence, is used to set a trigger T5 on, via a trigger T4 (both re-set by clock pulses CPB from the store B) which causes the wanted address that coincides with the staticized address to be erased from the tape B, and a new wanted address, from a mechanical input device, to be put in its place. The trigger T5 is also set on by a trigger T6 when a vacant position in the store B is read. A trigger T1 inhibits the outputs of the not equivalent devices E1-E6 while an address read from the main store is being staticized. In a second embodiment, Fig. 7, where the wanted address store B has a capacity of n<SP>3</SP> addresses, n being the number of addresses that can be read out of the store B in one block-period, three address reading heads HN1-HN3, positioned the indicated number of data blocks apart, operate in conjunction with two pairs of intermediate stores C1, C2, and D1, D2, to control the read-out of wanted data blocks. The head HN1 and its two associated staticizors SB1 and SB2 are so arranged that once every n<SP>2</SP> data blocks the address read by the head is entered into staticizor SB1 and the same number plus (n<SP>2</SP>+ 1) is entered into staticizor SB2. These two numbers remain staticized for n<SP>2</SP> data block periods during which time (a) the store B makes a complete cycle; (b) under control of a comparer CC1 those numbers lying between the two numbers staticized in staticizors SB1 and SB2, are transferred from the store B to one of the stores D1, D2 (D2 as shown), each of which can only hold n2 addresses. While this is happening, the head HN2 and its associated staticizors SD1, SD2 is operating similarly in conjunction of the other of the stores D1 and D2 (D1 as shown), with the exception that they operate every n data blocks as opposed to every n<SP>2</SP> data blocks for head HN1. The result is that to one of stores C1 and C2 are transferred all those addresses from store B which relate to data blocks which will become available in the next n block-periods, and thus since the stores C1 and C2 can each be completely read in one block period, one of these stores can play the part of store B, shown in Fig. 1, and control the extraction of data blocks as in that Figure. The stores D1 and D2, and C1 and C2 function alternately, while one is being filled the other is being emptied. A third embodiment (Fig. 3, not shown) is described with a similar amount of detail to that in Fig. 1, showing the construction of an arrangement, similar in principal to that of Fig. 7, but using only two heads and one pair of intermediate stores. The apparatus described could be used for writing data into a main store as opposed to extracting it. The intermediate stores could be sections of tracks or a magnetic drum having feed-back loops. Specification 717,114 is referred to.