Patent GB-1031202-A (GB)
Title: Universal code translator
IPC: G06F9/30
Filed: 1964-01-24
Abstract: 1,031,202. Matrix stores; electronic counters. SPERRY RAND CORPORATION. Jan. 24, 1964 [Feb. 6, 1963], No. 3213/64. Headings G4A and G4C. In code conversion apparatus, the equivalents of input data characters to be recorded are stored in an erasable memory. Conversion to any one of a plurality of different codes may be effected by storing the equivalents in each of the plurality of codes, of the totality of possible input characters which may be required to be recoded. The arrangement described is for converting 6-bit characters and comprises a 64 x 64 6-plane co-ordinate magnetic core matrix memory 10, Fig. 1b (not shown) in which the 64 X positions in a given row (Y line) can each store a 6-bit character in a particular code corresponding to that Y line. A code conversion operation can effect the conversion automatically of a plurality of characters, the characters to be converted being initially stored in the memory, converted, the converted characters replacing the corresponding original characters (" translate " operation). Alternatively, the characters to be converted can be supplied from an input source 66 the converted characters being stored (" translate and load " operation). Translate operation.-A 23-bit instruction word is entered into an instruction register 26 comprising a 5-stage operation section 26a, a 12-stage memory address section 26b containing the address of the first of a series of characters to be converted, and a 6-stage " count " section 26c into which is entered the number of characters in the series to be converted this number being reduced by one each time a character is converted. The first four bits in the operation section 26a are supplied to conventional matrix encoders 23, 82 which provide the X and Y address-portions of a " locator " word in the memory, this " locator " word designating a row (Y line) in the memory containing the desired code equivalents, and being read out to a temporary storage register (D register) 30. The memory address from section 26b is then transferred to memory address registers 14, 18 to read out the first character to be converted for temporary storage in a register 42 (A register). The contents of the registers 30, 42 are then transferred to the Y and X address registers 14, 18 respectively to read out the recoded character for temporary storage at 42. The memory address from section 26b is again transferred to the address registers 14, 18 and the converted character written from register 42 via write-in circuits 56 for storage at the location from which the character to be converted came. Countdown gates 25, 27 are now effective to reduce the address section 26b and the " count " section 26c by unity, so that the next character can be converted, the process continuing until the count in section 26c reaches zero as detected by a comparator 76 which emits a signal to terminate the operation. Translate and load operation.-This operation is generally similar to the translate operation except that the characters to be converted are obtained from an input source 66 instead of from the memory 10, the conversion and subsequent storage at an address determined by the memory address section 26b being as in the translate operation. Electronic counter, Fig. 2 (not shown).-The count section 26c of the instruction register 26 constitutes a binary counter shown in detail in Fig. 2 and comprising six bi-stable flip-flops C1 to C6, whose true and complementary outputs L1 to L6, L1 to #L6 are connected as shown to AND gates such as 200, 206 which are supplied with the input pulses to be counted on a line 72, the arrangement being such that each input pulse 72 reduces by unity the count as registered in binary form in flip-flops C1 to C6, the supply of input pulses being terminated when the counter reaches zero.