Patent GB-1352787-A (GB)
Title: Arrangement for quantizing signals
IPC: H04N11/04
Filed: 1971-04-19
Abstract: 1352787 A/D converters PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 19 April 1971 [2 April 1970] 25774/71 Heading G4H A delta modulation systemquantizes the most significant of a series of amplitude variations. In Fig. 1, the luminance signal UL of a colour TV video signal is applied to a delay line 12 with taps spaced at intervals of one sampling period and feeding the inputs of difference amplifiers- 18, 19, 20, 21 as shown, each difference amplifier delivering its upper input minus its lower input. The outputs are stored each sampling period on capacitors 34, 35, 36, 37 feeding inputs of difference amplifiers 39, 41, 43, 45, 47; 86 as shown, via absolute-value units of the type at 48, 49, 50 where 48, 50 are diodes and 49 an inverter. The output of difference amplifier 43 sets or resets a bi-stable 33 to control switches 31, 32 so that 31 is closed and 32 open if the output of 43 is positive and vice versa if negative. These switches 31, 32 select the output of one of difference amplifiers 20, 21 to feed a digitizer 52 if a switch 67 is closed. The analogue signal corresponding to the digitizer output is supplied via terminal 71 and integrated (summed) at 75, the sum being applied at 22 to the difference amplifiers 20, 21 as shown. The chrominance signal UC of the TV video signal is applied to a difference amplifier 80, the output from which feeds a digitizer 90 if a switch 87 is closed. The analogue: signal corresponding to the digitizer output is supplied via terminal 92 and integrated (summed) at 96 to form the lower input to the difference amplifier 80. Each sampling period, the difference amplifier 80 output is stored at 84 and its absolute value supplied to the lower input of the difference amplifier 86 mentioned in connection with the luminance signal. Regarding- the remaining inputs to the difference amplifiers 39, 41, 43, 45, 47, ND15 and ND40 are the 15% and 40% decision levels used in luminance digitizer 52 which uses decision levels of 5%, 15%, 40% and representative levels of 2%, 8%, 24%, 60%. The chrominance digitizer 90 uses decision levels of 9%, 30% and representative levels of 2%, 15%, 50%. If any of the difference amplifiers 39, 41, 86 has a positive output, a bi-stable 58 produces an S = 1 signal. Otherwise S = 0. Switches 67, 87 are closed to cause digitization of luminance and chrominance variation signals respectively when S is 1 and 0 respectively, except that closing of both switches is inhibited as necessary under control of S and outputs D2, D4, D<SP>1</SP>6, D<SP>1</SP>8 of luminance digitizer 52 since some digitized values are sent as 2 or 3 digits rather than one digit (see below) and one digit is sent per sampling period. Inverter 56, AND gate 57 and OR gate 55, if they produce a 1 output with the connections shown, set to 0 the outputs D2, D3, D4, D<SP>1</SP>6, D<SP>1</SP>7, D<SP>1</SP>8 of the luminance digitizer 52. The outputs of the digitizers 52, 90 are coded into a code word using possible digits A, B, C, D for quadriphase transmission, each code word ending with A or B. Fig. 4 shows the digitizer (quantizing circuit) outputs for the various representative levels and the corresponding code words. During the period of the line sync. pulse, a repeating sequence of 3As and 3Bs is transmitted instead, for synchronization of demodulation at the receiver. A voltage divider may be connected in one of the inputs of the difference amplifier 86 to introduce a weighting coefficient into the comparison of the absolute values of the variations of the luminance and chrominance signals to decide which shall be transmitted. The leakage resistors 78, 99 shown, of the integrators, can be replaced by reset-to-zero switches closed in response to each line sync pulse.