Patent GB-916992-A (GB)
Title: Improvements in or relating to telecommunication systems
Inventor: WRIGHT ESMOND PHILIP GOODWIN
IPC: H04Q11/04
Filed: 1959-06-12
Abstract: 916,992. Automatic exchange systems. STANDARD TELEPHONES & CABLES Ltd. June 10, 1960 [June 12, 1959], No. 20217/59. Class 40 (4) An exchange has groups of lines served by separate time division multiplex highways each having its own high-speed slave register, the contents of which are scanned at the frequency of the multiplex system, the slave registers being controlled by a slow-speed master register scanned at a frequency which is a sub-multiple of the frequency of the multiplex system and with a capacity equal to that of all the slave registers combined. A time-division-multiplex control system for a time-division-multiplex or space-multiplex exchange is shown in Fig. 1. High-speed slave registers SM with access selectors SAS control transmission gates STGC having access to one of a number of highways over a line-finder switch LAS. A slow-speed master register MM having space to duplicate the information in all the slave registers SM, and having means to process information according to supervisory data obtained from the transmission gates STGC, periodically feeds the high-speed slave registers to keep them up-todate. If there are 21 highways served by as many high-speed registers SM and each highway has 25 channels, then with the high-speed registers scanned at four times the speed of the slow-speed master register MM the master register may be associated with all the channels of the high-speed registers in the sequence SM1, channel 1; SM2, channel 5; SM3, channel 9; and so on. The registers are ferrite core matrices, the rows of which are read serially and define channel time positions. The registers may alternatively be sonic delay lines not needing access selectors. Fig. 3 shows the manner in which a row of the slow-speed register MM is interrogated and processed is conjunction with an associated row of a highspeed slave register which is read out in the first half of a channel time position and is written back in the second half. Each row of MM is given four channel periods in the first of which the row is read out to control circuit ML. In the second period the information in ML is gated to the control circuit SL of the high-speed register SM associated with MM in this time channel and overrides the information otherwise written back into the register SM. It is possible, however, that if the addresses in the registers are written in an error-checking code with error-checking circuits provided, an erroneous code from the slow-speed register MM can be inhibited and the code received from SM by SL can be accepted. For the remaining 524 channel positions before this channel is associated with the register MM once more, the high-speed register SM is autonomous in controlling the transmission gate STGC. Supervisory signals are received by the control circuit ML of register MM over the gates STGC during the third channel time of the interrogation period of a row of MM and after a processing interval the row is brought up to date by a writing function of ML in the fourth channel time. As shown in Fig. 1, a delay circuit DL is employed with gates such as G2, G4, to gather supervisory signals from the transmission gates STGC and to preserve a correct phase relationship between the time when a channel is controlled by SL and the time when processing pertinent to that channel takes place in the register MM. Gates such as G1, G3 govern the writing of information from MM into the registers SM. Fig. 2 shows the provision of a substitute control circuit SLX which is switched in with a substitute high-speed slave register if one of the regular slave registers is found to be faulty. This entails reading out all the rows of MM pertinent to the faulty store and writing them into the substitute store. These rows may be read out in an uninterrupted sequence with a consequent break in the sequence in which the regular stores are interrogated. Alternatively, a spare period may be permanently provided in the slow-speed register cycle whereby the substitute register may be written up whenever this is necessary. Specifications 765,681 and 822,297 are referred to.