Patent EA-001823-B1 (EA)
Title: Method for self-synchronization of configurable elements of programmable component
Inventor: VORBACH MARTIN
IPC: G06F15/78
Filed: 1998-02-07
Abstract: 1. Method of synchronization of the sequence control system of data processing in configurable elements as well as reconfiguration thereof in modules with a two- or multi-dimensional programmable cell structure (DFP, FPGA, DPGA, RAW machines), where a configurable bus system connects the elements to one another, as well as the sequence control system of data processing in conventional processor-based microprocessors, digital signal processors and microcontrollers by conditional lumps. where a bus system connects the processors to one another, characterized in that synchronization signals are generated by the processing configurable elements during processing, by comparisons of the data, signs of counts, carry-overs of arithmetic operations, error states, and the like (0202) and are sent to additional elements (0201, 0203) over the bus system, with the receiving elements using the information for synchronization of data processing and controlling the sequence of data processing (Figures 1-3). 2. Method according to Claim 1, characterized in that in synchronization by a trigger, a configurable element or a processor can be prompted to execute a single operation STEP trigger, (Figure 2). 3. Method according to Claim 1, characterized in that in synchronization by a trigger, a configurable element or a processor can be prompted to execute a plurality of operations (GO trigger, Figure 2). 4. Method according to Claim 1, characterized in that in synchronization by a trigger, the execution of a configurable element or a processor can be stopped (STOP trigger) Figure 2). 5. Method according to Claim 1, characterized in that in synchronization by a trigger, a configurable element can be released for reconfiguration (Figure 6). 6. Method according to Claims 1 through 5, characterized in that the configurable element or a processor indicates its instantaneous status in a status register (0402). 7. Method according to Claims 1 through 6, characterized in that the synchronization signals are transferred to the receiver of the data, to the transmitter of the data or to an independent configurable element or processor (Figures 1-3). 8. Method according to Claims 1 through 7, characterized in that the transfer of the synchronization signals can be blocked. 9. Method according to Claims 1 through 8, characterized in that different synchronization signals are optionally transmitted (comparison, error states, etc.), where the type of synchronization signal is freely selectable in the generating unit, and the effect of the synchronization signals is freely selectable in the receiving unit (Figure 5). 10. Method according to Claims 1 through 9, characterized in that one synchronization signal can be transmitted to multiple receivers (0501). 11. Method according to Claims 1 through 10, characterized in that an acknowledge line is allocated to a synchronization signal (Figure 6: TRIGACK). 12. Method according to Claims 1 through 11, characterized in that a synchronization vector is composed of one or a plurality of synchronization signals (Figure 6: TRIGV). 13. Method according to Claims 1 through 12, characterized in that a configuration register is selected from a plurality of configuration registers by a synchronization vector, or a command register is selected from a plurality of command registers (Figure 7b). 14. Method according to Claims 1 through 13, characterized in that the process of selection of a register is synchronized with the data processing by synchronization signals so that no clock cycle is lost (Figure 6). 15. Method according to Claims 1 through 14, characterized in that the value of the generated synchronization signal is stored in a register allocated to one operation and selected from a plurality of registers, so that another allocated operation can then access it selectively and selects one possible and valid command, and/or one possible and valid configuration, from a plurality of commands/configurations on the basis of this information. 16. Method of synchronization of the sequence control system of data processing in configurable elements as well as reconfiguration thereof in modules with a two- or multi-dimensional programmable cell structure (DFP, FPGA, DPGA, RAW machines), where a configurable bus system connects the elements to one another, as well as the sequence control system of data processing in conventional processor-based microprocessors digital signal processors and microcontrollers by conditional jumps, where a bus system connects the processors to one another, characterized in that configuration words are generated within a configurable element or processor on the basis of corresponding commands and are transferred over the data bus together with the address of the register to be addressed to another configurable element or processor which writes the transferred configuration words into the addressed register (pages 1-2). 17. Method according to Claim 16 characterized in that the configurable element or processor indicates its instantaneous status in a status register (0402). 18. Method according to Claims 16 through 17 characterized in that the information regarding the registers to be controlled is coded in commands and transferred over the data bus (bottom of page 2). 19. Method according to Claims 16 through 18, characterized in that the value of the generated synchronization signal is stored in a register allocated to one operation and selected from a plurality of registers, so that another allocated operation can then access it selectively and selects one possible and valid command, and/or one possible and valid configuration, from a plurality of commands/configurations on the basis of this information. 20. Method of synchronization of the sequence control system of data processing in configurable elements as well as reconfiguration thereof in modules with a two- or multi-dimensional programmable cell structure (DFP, FPGA, DPGA, RAW machines), where a configurable bus system connects the elements to one another, as well as the sequence control system of data processing in conventional processor-based microprocessors, digital signal processors and microcontrollers, by conditional jumps, where a bus system connects the processors to one another, characterized in that a valid configuration of the configurable elements is selected from a plurality of configurations or a valid command is selected from a plurality of possible commands of a processor on the basis of synchronization signals during the running time (Figure 7b). 21. Method according to Claim 20, characterized in than the configurable elements or processor indicates its instantaneous status in a status register (0402). 22. Method according to Claims 20 through 21 characterized in that the synchronization signals are transferred to the receiver of the data to the transmitter of the data or to an independent configurable element or processor (Figures 1-3). 23. Method according to Claims 20 through 22, characterized in that the transfer of synchronization signals can be blocked. 24. Method according to Claims 20 through 23, characterized in that different synchronization signals are optionally transmitted (comparison, error states. etc.), where the type of synchronization signal is freely selectable in the generating unit, and the effect of the synchronization signals is freely selectable in the receiving unit (Figure 5). 25. Method according to Claims 20 through 24, characterized in that one synchronization signal can be transmitted to multiple receivers (0501). 26. Method according to Claims 20 through 25, characterized in that an acknowledge line is allocated to one synchronization signal (Figure 6, TRIGACK). 27. Method according to Claims 20 through 26, characterized in that a synchronization vector is composed of one or a plurality of synchronization signals (Figure 6, TRIGV). 28. Method according to Claims 20 through 27, characterized in that the process of selection of a register is synchronized with the data processing by synchronization signals so that no clock cycle is lost (Figure 6). 29. Method according to Claims 20 through 28, characterized in that the value of the generated synchronization signal is stored in a register allocated to one operation and selected from a plurality of registers, so that another allocated operation can then access it selectively and selects one possible and valid command, and/or one possible and valid configuration, from a plurality of commands/configurations on the basis of this information.