baber/WOPTO huggingface dataset:
Patent JP-H02121337-A (JP)
Title: Structure and manufacture of mos transistor
Inventor: SETODA MASAZUMI
IPC: H01L29/78
Filed: 1988-10-31
Abstract: PURPOSE:To make possible the high-speed operation of a MOS transistor by forming a channel into a short one by a method wherein a gate part is arranged on a recessed part between bird's beak parts, which are respectively formed between source and gate parts and between a drain part and the gate part and consist of a silicon oxide film, and the surface of its lower part is made almost flush with the surfaces of the lower parts of the source and drain parts. CONSTITUTION:An Si substrate 21 is oxidized to form thick SiO2 oxide films W(6) and bird's beak parts X are respectively formed under the end parts of nitride oxide films V(t). Simultaneously, parts V and V doped in the above process are activated and are turned into P<+> layers 8. Thick oxide films W1, on which there is a position for a gate 25, are removed, an Si layer is again exposed on a gate 25 formation part and a hole Z for gate use is formed. An oxide film J is formed on the substrate 21, from which a resist Y and the films V(t) are removed. The film J on the bottom part in the hole Z is turned into a gate oxide film 24. Moreover, a poly silicon film K is formed in the hole Z to form the gate 25. The unnecessary film J is removed. As<+> ions are implanted in the substrate 21 to heat-treat. An impurity is doped to thin SiO2 parts W and 8 source 22 and a drain 23 are formed.
Patent JP-H04150535-A (JP)
Title: Synchronization detector
Inventor: WATANABE HIDEKAZU
IPC: H04L7/00
Filed: 1990-10-13
Abstract: PURPOSE:To attain low power consumption and in addition, miniaturization and lightening in weight by providing a serial/parallel conversion circuit, a first synchronous processing circuit, a latch circuit, and a second synchronous processing circuit. CONSTITUTION:Synchronization detecting processing from parallel data D2 is executed by the first synchronous processing circuit 11, and a timing signal C5 is generated on the basis of this processed result. Then, input data D1 made to be the parallel data D2 is latched by the latch circuit 2, and the synchronization detecting processing from latch data D2L is executed again by the second synchronous processing circuit 13, and simultaneously, the right or the wrong of detected synchronous pattern data is decided. Accordingly, high-speed perfofmance is required for the first synchronous processing circuit 11, but since a circuit scale can be small, the power consumption is lowered. Besides, since the second synchronous processing circuit 13 executes deciding processing, etc., its circuit scale becomes comparatively large, but since it need only handling of the latched data, it can be constituted of comparatively low-speed elements. Thus, the low power consumption, the miniaturization and the lightening in weight are attained.
Patent JP-H02121468-A (JP)
Title: Facsimile equipment
Inventor: SUZUKI YASUHIRO
IPC: H04N1/00
Filed: 1988-10-31
Abstract: PURPOSE:To inform the fact that an original is not reached to a destination to a sender accurately by printing out error information to a copy of the original having a reception fault. CONSTITUTION:A compression circuit 7 storing a data corresponding to one original to be sent while revising the transmission of one original and a frame buffer 8 are provided to the equipment. If one transmission is not normally finished, a decode circuit 10 outputs an error data to an error information storage section 11 and the error information storage section 11 outputs an error information data. A synthesis circuit 9 expands a compressed original data, synthesizes it with the error information data to generate a print data, which is outputted to a print section 12. When a signal representing the fault of the received data arrives, a copy of the content being the result of synthesis between the error information corresponding to the signal and the storage content is discharged and transmission fault is informed accurately.
Patent JP-H02120982-A (JP)
Title: Data base control device
Inventor: DOI TSUGUNORI
IPC: G06F17/30
Filed: 1988-10-31
Abstract: PURPOSE:To easily develop an application program by unitary storing code data, image data and text data as fields in a logical record. CONSTITUTION:Data storage means 1 to 3 prepared in accordance with respective attributes of codes, texts and images store data in data storage media 4 to 6 similarly prepared in each attribute, data retrieving means 7 to 9 retrieve the stored data as a logical record of each attribute and data reading means 10 to 12 read out the data as a logical record of each attribute. Thereby, the code data, text data and image data can be unitary stored as fields in the logical record and correspondence to respective attributes based upon an application program can be omitted. Consequently, an application program can be easily developed.
Patent JP-2001095630-A (JP)
Title: Lifting implement to be built in furniture such as desk
Inventor: NANAMI KIYUUSHIRO
IPC: A47B37/00
Filed: 1999-09-28
Abstract: PROBLEM TO BE SOLVED: To provide a lifting implement for display which has a structure applicable to any desk or counter regardless of the type or size thereof even if the types or sizes of desks or counters are different. SOLUTION: The lifting implement includes left and right upright column members 1, 2 which are parallel to each other, a lifting beam member 6 which is vertically slidably bridged between the members 1, 2 to support an object D to be lifted, and constant torque coil spring mechanisms 9, 10 provided respectively on the members 1, 2 to impart a winding force of constant torque, as a lifting force for the member 6, to the member 6. The lifting implement is disposed below a top board T of a desk or the like.
Patent JP-S61157692-A (JP)
Title: Laminate type plated steel sheet
Inventor: NAKAMORI TOSHIO
IPC: C25D5/10
Filed: 1984-12-28
Abstract: PURPOSE:To allow a laminate type plated steel sheet to show superior performance by coating with paint after conventional chemical conversion treatment by forming a coating not made of an intermetallic compound as the lower layer and a coating of an intermetallic compound as the upper layer. CONSTITUTION:The surface of a steel sheet is coated with one or more among 5-100mg/m<2> Ni or Cu, 10-2,000mg/m<2> Mn and 10-2,000mg/m<2> Cr to form a lower layer not made of an intermetallic compound. The coated surface is further coated with an intermetallic compound by plating by 2-80g/m<2> to form an upper layer. A laminate type plated steel sheet is obtd.
Patent JP-H01119613-A (JP)
Title: Method for treating continuous desiliconization in response to iron tapping condition
Inventor: YOSHIDA MASAAKI
IPC: C21C1/04
Filed: 1987-10-30
Abstract: PURPOSE:To efficiently execute continuous desiliconizing treatment for molten iron with simple constitution by arranging lances at each of an intermediate trough, inclining trough and molten iron receiving hole of torpedo car at downstream side of a skimmer and independently changing charging and blowing rate of desiliconizing agent from each lance in accordance with iron tapping condition. CONSTITUTION:At the time of desiliconizing-treating the molten iron tapping from a blast furnace at interval from the iron trough to the torpedo car 6, each of the lance L1, L2, L3 is arranged above the intermediate trough 4, inclining trough 5 and molten iron receiving hole 6a of the torpedo car 6 at the downstream side of the skimmer 3. The charging and blowing rates of the desiliconizing agent into molten iron from these lances L1, L2, L3 are independently and suitably changed in accordance with the iron tapping condition and in order to prevent lowering of reaction efficiency, the desiliconizing agents from the lances L2, L3 above the inclining trough 5 and molten iron receiving hole 6a of the torpedo car 6 are blown into the position, where is within 400mm of diameter as centering the molten iron dropping point. By this method, the damage of the trough material is reduced and the desiliconizing treatment is efficiently executed.
Patent JP-H07131521-A (JP)
Title: Digital communication system
Inventor: TAKAHASHI HIDEAKI
IPC: H04M3/00
Filed: 1993-11-04
Abstract: PURPOSE:To transfer data with no change of the transfer form by demultiplexing two B channels of an ISDN subscriber line interface into four speech channels of 32Kpbs and then by multiplexing and demultiplexing the data. CONSTITUTION:The data on the ADPCM voices of 32Kpbs or the data on the elements other than the voices which are sent from a transmitter PS1 are received by a device A. The device A turns the received data into the data B'1-B'4 via the registers T11-T13. A multiplexer MX1 used for the transfer speed data of 32Kpbs multiplexes the data B'1-B'4 into the data of 64Kpbs for a channel B1 and also multiplexes the data B'1 and B'2 of a pair B1. In the same way, a multiplexer MX2 multiplexes the data B'3 and B'4 of a pair B2 for a channel B2. Then data B1 and B2 are sent to an ISDN network via an S interface S1. A device B (switchboard X1) demultiplexes the received data B1 and B2 into the data B'1-B'4 of 32Kbps by the data demultiplexers SX1 and SX2 and connects these data with switching to a subscriber line via the registers R21-R24.
Patent JP-2001100896-A (JP)
Title: Key input circuit, device and method for controlling power supply
Inventor: TSUGANE SUGURU
IPC: G06F3/023
Filed: 1999-09-28
Abstract: PROBLEM TO BE SOLVED: To provide a key input circuit, a device and a method for controlling power supply, with which a hardware quantity can be suppressed and a software processing sequence for detecting keying can be simplified. SOLUTION: A power supply control key SW11 is provided on a key switch 102, formed by locating plural key contacts SW11, SW12, SW21, SW22, etc., at the crossings of a key matrix and a key scan circuit 101 for detecting the pressing/releasing state of plural key contacts on the key switch 102 is provided, independently of a power supply control key state detecting part for detecting the opening/closing state of the contact SW11 of a power supply control key, and when a power source is turned on, pressing of the power supply control key SW11 is detected by the power supply control key state detecting part, but when operation is finished or power source is turned off, depressing of that key is detected by the key scan circuit 101, so that supply/stop of power can be controlled.
Patent JP-S62134295-A (JP)
Inventor: HARUTA YOICHI
IPC: B42D15/10
Filed: 1985-12-06
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H11110240-A (JP)
Title: Cyclic code check arithmetic circuit
Inventor: MIZOGUCHI TADAO
IPC: G06F11/10
Filed: 1997-10-08
Abstract: PROBLEM TO BE SOLVED: To prevent increase of the number of hardware component which are necessary for execution of a CRC (cyclic redundancy check) arithmetic operation and accordingly to prevent increase of the scale of an arithmetic circuit and its power consumption by switching the corresponding CRC arithmetic operation in response to a selected generator polynomial to recognize the arithmetic operation. SOLUTION: One of plural generator polynomials stored in a generator polynomial store part 104 is selected at a processing switching part 105. A CRC arithmetic execution part 101 recognizes the CRC arithmetic operation in response to the generator polynomial selected at the part 105 via an arithmetic switching part 107. Thus, the part 101 can execute the CRC arithmetic operations corresponding to plural types of generator polynomials, based on only the notification given from the part 107. Therefore, it's not required to increase the number of hardware component necessary for execution of the CRC arithmetic operations in response to the number of types of generator polynomials. As a result, the CRC arithmetic operations can be executed in response to plural types of generator polynomials without increasing the scale of an arithmetic circuit and its power consumption.
Patent JP-H10125746-A (JP)
Title: Semiconductor device for evaluation and method testing semiconductor device
Inventor: NAGATA SHINICHIRO
IPC: H01L21/66
Filed: 1996-10-18
Abstract: PROBLEM TO BE SOLVED: To estimate the Al slide life of a semiconductor device, using a general-purposed evaluating semiconductor device for testing the temp. cycle, etc., of the semiconductor device. SOLUTION: A passivation film-made test electrode 3 is provided on a part of a semiconductor chip 1, and an evaluating semiconductor device sealed with a transparent resin 2 is formed and thrown in a temp. cycle test to obtain the length data of extending cracks in the test electrode through the clear resin 2. The resin fatigue parameters are obtd. from the obtd. crack growth data to derive Al slide life estimating equations of a process from the Al slide life obtd. from a semiconductor device, in the same process as that of a semiconductor device under test and the parameters to thereby estimate the Al slide life of the semiconductor device under test according to the equations.
Patent JP-S61156833-A (JP)
Title: Manufacture of semiconductor device
Inventor: BANDO JUNJI
IPC: H01L21/3205
Filed: 1984-12-28
Abstract: PURPOSE:To prevent disconnections by reducing the step of the second wiring by a method wherein an interlayer insulation film is left thin between an interlayer insulation film that supports the wiring section of the second wiring and the first wiring. CONSTITUTION:An interlayer insulation film 4 is deposited so as to cover the first wiring 2 equipped with an insulator 1a on a semiconductor substrate 1. Next, a resist film 5 is deposited thereon, and a recess 6 corresponding to the through-hole section is formed. The aperture width 7 of this recess 6 is larger than the line width 3 of this wiring 2. Then, the resist film 5a at the through- hole section and an interlayer insulation film 4 under this resist film are etched until the surface of the wiring 2 is exposed. An interlayer insulation film 4a is partly left in this etching through-hole 8 between the wall 8b and the wiring 2. The second wiring 11 is provided on the wiring 2 via through-hole 8. Because of being backed with the interlayer insulation film 4a, this wiring 11 makes no possibility of disconnection.
Patent JP-H10118185-A (JP)
Title: Relaxation therapy system by sounds and images and said system by sounds, images and scents
Inventor: ABE SHINICHIRO
IPC: G06Q50/22
Filed: 1996-10-18
Abstract: PROBLEM TO BE SOLVED: To provide a relaxation system by optimum sounds and images or by optimum sounds, images and scents corresponding to the conditions of each person by diagnosing symptoms/states by individuals. SOLUTION: When a control program for relaxation therapy is executed while using terminal equipment 102 and diagnostic items are transferred through a communication network 103 to the side of a host device 101, a diagnostic program is executed on the side of the host device 101, diagnosis is performed based on the diagnostic items, the combination of optimum sounds and images suitable for relaxation corresponding to the diagnosed result is selected, and the relevant sounds and images are transferred through the communication network 103 to the terminal equipment 102. Afterwards, the terminal equipment 102 outputs these sounds and images through a speaker and a display device, and the relaxation therapy by optimum sounds and images is provided for system users.
Patent JP-H0980327-A (JP)
Title: Mirror with convex lens
Inventor: NIHEI ISAO
IPC: G02B25/00
Filed: 1995-09-20
Abstract: PROBLEM TO BE SOLVED: To equip the mirror with the functions of a concave mirror, a plane mirror, and a convex lens and make the mirror small-sized and lightweight for easy portage by equipping the mirror with functions which put the convex lens over the front surface of the plane mirror and reset the state. SOLUTION: The plane mirror 1 and convex lens 2 are fixed to a hinge 3 respectively and can be opened and closed individually on the hinge 3 as a fulcrum. When an image of an observer 4 is reflected in the plane mirror 1 through the convex lens 2 put on the front surface of the plane mirror 1, the near point of accommodation of the observer 4 moves close to the plane mirror 1 through the effect of the convex lens 2. Further, the image of the observer 4 reflected in the plane mirror 1 is observed as an enlarged and clear image. Further, when the plane mirror 1 and convex lens 2 are used while separated, an image of life size of the observer 4 can be reflected by using the plane mirror 1 and an enlarged image can be observed by using the convex lens 2.
Patent JP-S61145125-A (JP)
Inventor: REIMONDO PII ZORUTON
IPC: C12P21/08
Filed: 1985-12-10
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-2000105578-A (JP)
Title: Liquid crystal driving device
Inventor: KAWAMOTO MITSUO
IPC: G09G3/36
Filed: 1998-09-30
Abstract: PROBLEM TO BE SOLVED: To provide a liquid crystal driving device which is strong for external obstruction such as noise and of high reliability. SOLUTION: The address decoder 121 of a liquid crystal controller inputs an address signal ADRS, and outputs a control signal from an address Ax to a parameter setting resister 124 through a NOT-circuit 122 and an OR-circuit 123. The OR-circuit 123 inputs a chip selector signal-CS and a light signal-WR. The parameter setting resister 124 inputs a data signal DATA, and outputs the output to a parameter resister 125. The output of a resister 126 inputting an incorporated signal GET from the OR-circuit 123 is output to resisters 127, 128, a clock signal CLK is input to the resisters 127, 128, and a fetch prohibiting signal NG from the reister 128 is sent to the resister 125.  When data is written in the parameter setting resister 124 assigned to the address Ax only by one time, unless the liquid crystal controller 12 is reset, data can not be written into the parameter setting resister 124.
Patent JP-H03136995-A (JP)
Title: Swing arm structure of front-wheel suspension for motorcycle
Inventor: KURAWAKI ICHIROU
IPC: B62K25/24
Filed: 1989-10-24
Abstract: PURPOSE:To take the brake angle sufficiently in the condition to secure a specific steering angle to a front wheel by making the section at the front end of a swing arm in a laterally long form, and making the lateral width size of the section at the middle part in the longitudinal direction smaller than the front end, while making the longitudinal width size in a longitudinally long shape larger than that of the front end. CONSTITUTION:By making the section of the front end of a swing arm 33 in a laterally long form, and making the longitudinal width size d1 of the front end somewhat smaller but making the lateral width size w1 larger, the strength of the part is maintained. The middle part in the longitudinal direction of the swing arm 33 is projected to the outer side, but the lateral width size w2 at the same part is made smaller than the width size w1 to prevent the expansion of the width size of the car body. Since the longitudinal width size d2 at the middle part in the longitudinal direction is larger than the longitudinal width size d1 of the front end, and its section is in a longitudinally long shape, the middle part in the longitudinal direction can maintain a sufficient strength even in comparison with the front end.
Patent JP-H02123654-A (JP)
Title: Ion beam irradiation method and target disc
Inventor: MORI HARUHISA
IPC: H01J37/20
Filed: 1988-11-01
Abstract: PURPOSE:To eliminate an irradiation angle error in ion irradiation by curving a semiconductor wafer to a shape along the internal surface of circular cone formed with the locus of the motion of a wafer placement part and irradiating an ion beam while the wafer is being turned about an axis of rotation. CONSTITUTION:The first straight line B intersecting an ion beam I is used as an axis of rotation, and the internal surface 3 of a circular cone made with the locus of the second straight line C crossing the axis of rotation is used as a wafer placement part. In addition, a semiconductor wafer 1 is curved to a shape along the internal surface 3 of the circular cone and subjected to ion beam irradiation while being turned about the axis of rotation. In other words, the semiconductor wafer 1 is placed as curved like a heavy line (a-o-b) and moves along a broken line (a'-o'-b'), even when a target dis turns. As a result, it is possible to avoid an ion implantation error on the entire surface of the semiconductor wafer 1.
Patent JP-S62136943-A (JP)
Title: Method of coupling data communication
Inventor: ITO HIROSHI
Filed: 1985-12-11
Abstract: PURPOSE:To reduce the man-hour of program generation and to use each equipment in common by constituting the equipment so that plural controllers are used nearly as they are when the plural controllers having a data transmission/ reception function via a transmission line are used while being connected by a common bus. CONSTITUTION:CPUs 11, 21, 31 and memories 12, 22, 32 constituting MCU1, MMU2 and DCU3 are connected by a bus 4 comprising plural wires and a CPU 51 constituting an SRC 5 and an intervention memory 52 are also connected to the bus 4. Plural data collecting panels DGP 71-7n are connected to the bus 4 via an interface 6, the DCU 3 applies control and operation in response to a detection data from each section via the DGP 71-7n, the control data is sent to the DGP71-7n to control various control object equipments. The MCU 1 applies overall discrimination by the data transmission/reception with the MMU2 and gives a command to the DCU 3 by the data transmission/ reception and the DCU 3 executes the control operation according to it.
Patent JP-H08139807-A (JP)
Title: Information transmission system
Inventor: ISHIBASHI MANAMI
IPC: H04L69/40
Filed: 1994-11-10
Abstract: PURPOSE: To provide a system in which the number of personnels in charge to update system configuration information stored in each monitor is reduced with respect to the large scale system in which many transmitters each having a user terminal equipment are interconnected by multiplex transmission lines in the network and the plural monitors monitor the state of the system. CONSTITUTION: The system includes plural transmitters 12 to each of which an information communication user terminal equipment 10 is connected, a multiplex transmission line 14 connecting each transmitter 12 to the network, and a monitor 16 connecting to the plural transmitters 12 to monitor the state of the system, and each transmitter 12 has a means 18 tying the use terminal equipments 10 making communication of information via a user area allocated on the transmission line 14 and a means 20 tying the monitors monitoring information communication for state monitoring via a control area allocated on the transmission line 14.
Patent JP-H01118993-A (JP)
Title: Video tape carrier
Inventor: KOO MASAFUMI
IPC: G07F11/00
Filed: 1987-10-30
Abstract: PURPOSE: To simplify a mechanism and to make a device low in price by detecting both the loading and unloading completion of a video cassette through one sensor. CONSTITUTION: A video tape handler 51 is moved to a slot commanded from a CPU, and a video tape in the slot is held by moving the video tape handler 51 in Z-axis direction after stopping it at this position. When a photosensor 65 is turned on, the execution of clamping is judged, the video tape is loaded inside by driving a conveyer belt 61 in such a state, and when the photosensor 65 is turned off, the completion of storage is judged. Thus, since one sensor can be used for detecting the holding of the video tape and detecting the loading completion of the video tape, the device is made simple in constitution, small in size and low in price.