Patent SG-11201809911W-A (SG)
Title: Method for fabricating a strained semiconductor-on-insulator substrate
Inventor: SCHWARZENBACH WALTER
IPC: H01L21/762
Filed: 2017-05-17
Abstract: INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property :::` , Organization 03 1111111111111111111111111111111111111111111111111111111111111111111111111111111 International Bureau (10) International Publication Number (43) International Publication Date .....•\"\" WO 2017/198686 Al 23 November 2017 (23.11.2017) WI PO I PCT (51) International Patent Classification: LE TOUVET (FR). DAVAL, Nicolas; Fontcouvert, 38570 HO1L 21/762 (2006.01) GONCELIN (FR). (21) International Application Number: (74) Agent: REGIMBEAU; 139 Rue Vendome, 69577 LYON PCT/EP2017/061792 CEDEX 06 (FR). (22) International Filing Date: (81) Designated States (unless otherwise indicated, for every 17 May 2017 (17.05.2017) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, (25) Filing Language: English CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, (26) Publication Language: English DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, (30) Priority Data: KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, 1654368 17 May 2016 (17.05.2016) FR MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, (71) Applicant: SOITEC [FR/FR]; Parc Technologique des PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, Fontaines Chemin des Franques, 38190 BERNIN (FR). SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (72) Inventors: SCHWARZENBACH, Walter; 19, Chemin du Mollard, 38330 SAINT NAZAIRE LES EYMES (FR). (84) Designated States (unless otherwise indicated, for every CHABANNE, Guillaume; 34 Rue des Gaillardes, 38660 kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (54) Title: METHOD FOR FABRICATING A STRAINED SEMICONDUCTOR-ON-INSULATOR SUBSTRATE = T sS01 T = ' Ai 1 13 = 11 an 23 20 = = 21 = = FIGURE 3G = = = = = (57) : The invention relates to a method for fabricating a strained semiconductor-on-insulator substrate, comprising: (a) the provision of a donor substrate (1) comprising a monocrystalline semiconductor layer (13); (b) the provision of a receiving substrate (2) comprising a surface layer (20) of a strained monocrystalline semiconductor material; (c) the bonding of the donor substrate (1) to — the receiving substrate (2), a dielectric layer (11, 22) being at the interface; (d) the transfer of the monocrystalline semiconductor layer Il (13) from the donor substrate (1) to the receiving substrate (2); (e) the cutting of a portion from a stack formed from the transferred Q l monocrystalline semiconductor layer (13), from the dielectric layer (11, 22) and from the strained semiconductor material layer (20), ,t: said cutting operation resulting in the relaxation of the strain in the strained semiconductor material, and in the application of at least a GO part of said strain to the transferred monocrystalline semiconductor layer. Step (b) additionally comprises the formation, on the strained of semiconductor material layer (20) of the receiving substrate (2), of a dielectric bonding layer (22) or of a bonding layer consisting of ON the same relaxed, or at least partially relaxed, monocrystalline material (23) as the monocrystalline semiconductor layer (13) of the Il donor substrate (1), and in that in step (c) said bonding layer (22, 23) is at the bonding interface between the donor substrate and the --.... t -- - receiving substrate. 1-1 0 ei C [Continued on next page] WO 2017/198686 Al MIDEDIMOMOIDEIROIDEMOMOHHEIHE11101111111111111111111 UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3))