Patent GB-1323771-A (GB)
Title: Digital computing apparatus
IPC: G06F7/57
Filed: 1970-07-04
Abstract: 1323771 Arithmetic unit DETREX CHEMICAL INDUSTRIES Inc 4 July 1970 32517/70 Heading G4A A binary arithmetic unit performs multiplication, division, squaring, rooting, addition, subtraction, and code conversion and consists of a slant matrix array of individual arithmetic units, e.g. as described in U.S.A. Specification 3,482,085.  Theory.-A number abcdef when squared is given by: aa + 2ab + 2ac + 2ad + 2ae + 2af + bb + 2bc+ ... &c. Each term in the above expression is followed by a particular number of zeros as follows: The rows of the above table are arranged so that each row contains a common term, e.g. in row two b, in row three c &c. Thus if, e.g. the term b is zero then all terms containing b (i.e. the whole of row two plus other terms) are zero (see below). When dealing with binary numbers the factors of two in the table can be accommodated by shifting the relevant terms one place to the left, e.g. 2ab goes to column 10. The resulting array allows the square of any number to be determined simply by substituting and adding the rows. Conversely square rooting may be performed by sequentially subtracting each of the rows in turn initially assuming all terms to be 1, from the number to be rooted. If any subtraction produces a negative result then all the terms in that row must be zero and all other terms containing the common term of the row, i.e. row 1, a; row 2, b; &c. (see above), must also be zero. Thus as the subtraction proceeds the array of terms is modified and tends towards the array corresponding to the square root. Parallel squaring and rooting hardware.-The matrix illustrated in Fig. 1 consists of arithmetic units, Fig. 2a, as described in U.S.A. Specification 3,482,085. The units add or subtract or perform a by-pass operation, the latter passing the input P unchanged to the output T but generating the carry or borrow that would have been generated had an addition or subtraction been performed. To perform a square root the number to be rooted is applied from register 110 to the P inputs of the units in the first row. The patterns of trial subtractions (given by the array discussed in "Theory" above) are then applied to the E inputs of the appropriate units 12, the patterns being generated initially assuming a = b = c &c. = 1 (see matrix generation below). The minuend digits are applied via normally open NAND gates 20-26 and AND gates 112-118. To start the operation a A (i.e. not add = subtract) signal is applied to all units 12. If the subtraction in the first row produces a negative remainder a borrow signal G from unit Au 1 , 1  is fed via device 19 to a K generator 30. The resulting K signal passes via OR gate 50 to the K inputs of the units in the first row which thus perform a by-pass operation. The K signal also sets a 0 in the most significant bit position, a, of an answer register 60 and, via gate 66, generates a K<SP>1</SP> signal which inhibits gate 20 to block the 1 signals applied to the E inputs of a number of units 12 and thereby begins the modification of the array (see "Theory" above) since all terms in the array containing a must be zero. The process then repeats for the second and subsequent rows of the matrix. The matrix may also be used for squaring operations by placing the number to be squared in registers 100 and 111. Appropriate units 12 then have their inputs energized in accordance with the array discussed in "Theory" above as expressed for the particular number being squared. This is achieved by gates 91, 92 &c. which selectively pass 1 signals from the "square" command line S 11  to the K inputs of appropriate units 12 thereby to produce the array pertinent to the number being squared. The matrix then adds vertically to generate the square. Generation of array for square rooting.-It is required to generate an array for the trial subtractions based initially on the assumption that a = b = c &c. = 1 and subject to modification whenever a subtraction produces a negative remainder. The device illustrated in Fig. 6, consists of several shift register stages 201, 202 &c. and a gating network. A pulse sets register stage 202 to 1 and thus produces the first trial subtractor (aa, see "Theory"). If the subtraction produces a positive result a K signal does not appear on line 223 and a 1 signal appears on line 240. This latter signal is applied to AND gate 251 via inhibit gates 241-243 which are open by virtue of their inputs from higher stages of the register being 0. AND 251 conducts, its other input being the 1 in stage 202 and the signal passes, via open inhibit gate 271, to set stage 201 and, via OR 281, stage 203. The 1 signal on line 290 resets stage 202 and the register contents are shifted one place to the right by a signal on line 220. Thus the register contains the next trial subtractor. If however a K signal is generated inhibit gates 271, 272 are closed and stage 201 is not set. The register thus, after the remaining operations discussed above, contains 001 which is the new trial subtractor. The process repeats for each successive subtractor. Division.-The matrix is used for division by using trial divisors as subtrahends. The bits of a dividend from register 110 are applied via line 13 to the P inputs of the unit 12 in the first row while the bits of the divisor in register 111 are applied via line 15, ANDs 120, 121, &c., and inhibit gates 20, 21, &c. to the E inputs of oblique lines of units 12 with the highest order bit to the left. The matrix is then set to subtract and the operation is similar to that for rooting, the K signals causing a by-pass operation to be performed on the corresponding subtrahend and a zero to be set in the corresponding bit of the quotient. During the operation gates 66, 74 &c. are blocked to prevent any K<SP>1</SP> signals being generated. Any remainder appears in register 90. Multiplication.-The multiplicand bits in register 111 are applied to the E inputs of oblique lines of units 12 as in division, the bits of the multiplier from register 100 being applied to control the inhibit gates 91, 92 &c. which selectively pass a 1 signal from the "multiply" command line. The resulting K<SP>1</SP> signals apply the appropriate array to the units 12 and the matrix adds vertically to produce a product in register 90. Addition/Subtraction.-An augend is applied to the P inputs of the first row of units 12 and an addend to the corresponding E inputs. The add command to the first row causes the addition to be performed. Subtraction is similar, the minuend being applied to the P inputs and the subtrahend to the corresponding E inputs. Code conversion.-Conversions from decimal to binary via BCD and vice versa may be performed. Decimal to binary conversions are made using a decimal keyboard, a diode matrix, and the matrix operating as an adder. The converse conversion is made by applying the binary number to the P inputs of the first row of units 12 and applying to the E terminals of the rows of units 12 the binary equivalents of the decimal partial sums of the largest number the matrix can accommodate expressed in BCD or some other intermediate code, i.e. if the largest number is 9999 the first row would receive 8000, the next 4000, the next 2000, the next 1000, the next 800 and so on. Trial subtractions are then performed with any K signals indicative of a negative result being used to modify the E inputs in a manner similar to that used in division (see above). The result is read into a conventional 8.4.2.1 to decimal converter, the readout being read as 1.2.4.8. Other features.-The matrix may be used in one or more cycles to produce combination results, e.g. A+B<SP>2</SP> is produced in one cycle, and (A+B) - C is produced in two. Reference is directed to Specification 1,323,772.