Patent DE-3665234-D1 (DE)
Title: Arrangement for increasing or decreasing a binary operand with a predeterminated value
Inventor: HUSS ROLF-RUDIGER DR
IPC: G06F7/505
Filed: 1986-01-28
Granted: 1989-09-28
Abstract: 1. Circuit arrangement for optionally incrementing or decrementing a predetermined binary operand (A) by a selectable value (for example "8") corresponding to a predetermined position (for example i = 3) of the operand, especially for data processing systems, characterized - by a first selection switch (for example MUX0 to MUX7) for each of the bit positions (for example i = 0 to i = 7), which is in each case supplied with the mutually inverse operand position signals (for example A0 and A0 ) of the associated bit position (i = 0) as input signals and the output of which supplies the input signal (for example A0 = 0) selected in each case as result signal (S0 ), - by an OR gate (OR0 or OR7 or... or OR7) connected in series with for example the respective control input of the first selection switch (MUX0 to MUX7) which is in each case supplied with the inverted operand position signals with an incrementation and in each case with the non-inverted operand position signals with a decrimentation (for example A0 to A6 and A0 to A6 , respectively) of all least significant bit positions in each case and via which the respective first selection switch (MUX0 or MUX1 or... MUX7) can be switched to switching-through the non-inverted operand signal (A0 or A1 or A7 ) supplied in each case, - by additional second selection switches (MUXUM0 to MUXUM7) per bit position, if necessary with the exception of the highest bit position with signal inputs for the in each case mutually inverse operand position signals (for example A0 and A0 ) and a control input for a first control signal (1DC), which determines the direction of change and which uniformly enables either the non-inverted or the inverted operand position signal of the respectively associated operand bit position as control signal for all OR gates (OR1 to OR7) of the first selection switches (for example MUX1 to MUX7) associated with the subsequent higher bit positions, in which arrangement the second selection switches (for example MUXUM0 to MUXUM2) exhibit for all least significant bit positions (for example i = 0 to i = 2) preceding the bit position (for example i = 3) corresponding to the maximum change value (for example "8") an additional control input and two additional signal inputs to which a signal (for example "0") is applied which prevents the switch-over of the first selection switches, to which is switched over by a second control signal (for example st2) which is supplied to the second control input and which is derived from the change value, and - by a logic circuit (for example U10, OR10), which can be set by the respective change value (for example "8"), for generating individual second control signals (for example st0, st1 and st2) for in each case all least significant bit positions preceding the respective change bit position, in which arrangement these second control signals in each case act simultaneously on the OR gate (for example OR0 or OR1 or OR2) of the selection switch (MUX0 or MUX1 or MUX2) associated with the in each case associated bit position.