Patent GB-1264260-A (GB)
Title: Improvements in monolithic integrated circuit memories
Inventor: CHANG JOSEPH J
IPC: H01L27/07
Filed: 1970-11-04
Abstract: 1,264,260. Integrated semi-conductor circuits. INTERNATIONAL BUSINESS MACHINES CORP. 4 Nov., 1970 [13 Nov., 1969], No. 52369/70. Heading H1K. A monolithic integrated circuit non-destructive memory comprises an array of bi-level operational pairs of transistors each with grounded base and collector-base cross connection. Read-in is by-switching the transistors of a pair from non-conducting-conducting to conducting-non-conducting conditions respectively, and read-out by applying P.D.'s across the collector-emitter circuit and to the emitter,. and then sensing current in the conducting transistor Fig. 1, Fig. 4 (not shown); the diodes and resistors R1<SP>1</SP>, R2<SP>1</SP>, R3<SP>1</SP> being connected in series with each transistor and with address input Y 0 . A single chip memory cell (Figs. 2, 3) comprises transistors 10, 12 surrounded by a diffused isolation region 20, and an epitaxial region 28 of the same conductivity type as the buried cathode 24 of diodes 13, which operates to provide resistances in series with diode cathodes and input region 30 in delta network R 1 , R 2 , R 3 . This is reducible in known manner to a Y equivalent for resistors R 1 <SP>1</SP>, R 2 <SP>1</SP>, and R 3 <SP>1</SP> as functions of the values R1, R2, R3, which are controllable by doping the epitaxial region 28 and by the size and position of diffused control region 26. Since region 28 has differing conductivity type from collector region 38 of the transistors, the latter forms a diode in the region 24 across interface 40, and also with region 28 across the collector interface, whereby diodes 13 exist at each input and a further diode (not shown) is provided between the collectors isolating the adjacent transistors of the memory cell; avoiding the necessity for individual isolation rings. The buried island cathode 24 removes virtual collector-substrate capacitance to the cathode of diode 13, so as to reduce transient switching error. Structurally (Fig. 3) a silicon body 22 of P-conductivity is formed with holes for cathodes of diodes 13, indicated by buried island region 24 of N-type conductivity. A further hole is simultaneously formed between the isolation region and each transistor as a controlled diffusion region 26 of N-type-conductivity; the buried island and control region being formed by diffusion. Thereafter an epitaxial region 28 doped. N-conductivity is grown over the substrate, operating as a resistance path connected to cathode 24 of diodes 13 formed between island 40 and collectors 38 of the transistors; each cell having two transistors formed over two buried island regions 24. Isolation ring 20 is then diffused about the cell, and the transistors are formed by triple diffusion of a P-type collector region, a N-type base region, and a P + -type emitter region. N-type input region 30 is equidistantly diffused relative to both transistors, and ohmic contacts are formed on the semi-conductor regions; contact 31 being Y 0  input, contact 32 being inter-transistor collectorbase connection, contact 34 being dual emitter connection for X line and ground Y 1 , and contact 36 being the common N base connection. An underpass P + region (not shown) may provide the collector-base connection, and negative potential (not shown) may be imposed on the P + region 20. Either PNP or NPN transistors may be employed, and the use of an epitaxial layer as resistance between active elements and to provide inter-element isolation is applicable to any integrated circuit.