Patent GB-1390385-A (GB)
Title: Variable length arithmetic unit
IPC: G06F7/50
Filed: 1972-06-14
Abstract: 1390385 Variable word length processes BURROUGHS CORP 14 June 1972 [28 June 1971] 27842/72 Heading G4A A digital processor for transferring on a data bus a varying number of bits in parallel comprises a variable length arithmetic and logic unit including first and second registers 14, 16 (Fig. 1), storing operands X, Y coupled to a parallel binary adder 141, a store 22 for storing data representing the number of bits to be transferred and a circuit 122 controlled by the store to gate the number of bits to be transferred from the adder to the data bus. As described, the processor is controlled by micro-operators entered successively into register 30 to control a source control circuit 108. The circuit 108 controls the adder 14 so that either addition or subtraction of the two operands is performed. It also controls a switch 110 so that various functions, e.g. X+Y (from OR gate 112), X, Y (from registers 14, 16), X, Y (from inverters 116, 118), and X#Y and binary and binary coded sums and differences (from adder 114), are gated to the data bus via the masking circuit 122 controlled either by the source control 108 or by the length of the data specified by the micro-operator and stored in section CPL of register 22. Arithmetic unit (Fig. 2, not shown).-For adding or subtracting two 24 bit numbers the unit comprises six four bit binary adders and nine look ahead carry logic units, the latter being arranged in pyramid fashion. Each adder receives four sets of signals of the form Xm, Y m  from registers 14, 16 and C m-1  from the carry logic circuits (the lowest order carry C 0  being stored from the previous operation in section CYF of register CP). The adders also receive the signal from source control 108 representing addition or subtraction and generate signals S n  =X n #Y n #C n-1  and, for addition, G n =X n .Y n , P n  = X n .Y n  + X n .Y n  and for subtraction, G n  = X n .Y n , P n  = X n .Y n  + X n .Y n . The carry logic circuit receives the signals P n  and G n  to generate the carry signal for application to the adder circuits. The completion of the carry signal with the highest adder bits, e.g. the carry C 3  is effected in the next higher level carry logic circuit. Depending on the word length specified by section CPL of register 22, the carry signal from the highest order bit position is entered into section CYS when addition is being carried out. For subtraction, a comparator 158 detects whether X is less than Y or X = Y and CYS = 1 to register if necessary a "borrow" signal on lead CYD. A logic circuit 160 is included so that when four bit binary coded decimal code is used a carry is provided for the fourth bit position when the addition results in a sum greater than 10 or, if CYF = 1 in a sum of 9. Logic functions X.Y and X#Y are derived from the generate and propagate outputs G, P of the adder. Binary to binary coded decimal converter (Fig. 5, not shown).-A converter circuit adds 6 to the four bit binary digit S 0 , S 1 , S 2 , S 3  when the sum is between 10 and 15 and a binary coded decimal system is in use. This is effected using a four bit adder, the inputs of which receive the resultant carry signal C 3  and S 1 , C 3  and S 1 , S 2 , C 3  and the generated carry G 1  from the first stage and S 3 , G 1  and the generated carry G 1  from the third stage. The outputs are taken from the second, third and fourth stages together with the signal S 0 .