Patent GB-1301959-A (GB)
IPC: H01L21/00
Filed: 1971-04-19
Abstract: 1301959 Semi-conductors MITSUBISHA DENKI KK 19 April 1971 [19 March 1970] 24737/71 Heading H1K A semi-conductor PNPN switching device comprises (Fig. 1) an e.g. silicon monocrystal N-type wafer 10 establishing a central N layer 16 bounded by a P-type layer 18 and a P-type layer 20 formed by in-diffusion of impurity from end surfaces 12, 14. An outer N-type layer 22 is superimposed on layer 20 by in-alloying an impurity metal from surface 14; the resistivity of layer 20 being lower than that of layer 16 and the resistivities of layers 18, 22 being lower than that of both. Anode and cathode terminals A, K are connected ohmically to layers 18, 22 and a gate terminal G is ohmically connected to layer 20. In a NPNP device the conductivity types are inverse. The varying resistivity across the device is obtained by a nonuniform form concentration of diffused heavy metal, e.g. gold, within the silicon (Fig. 1b, not shown), there being a critically lower concentration in layer 16 adjacent the junction of layers 16, 18 than in the layer adjacent the junction 16, 20, and an equal or higher concentration in layer 20 adjacent junction 20, 22 than in layer 16 adjacent junction 16, 20, the forward ON voltage drop is mathematically shown to be reduced for a given turn-off time, or the latter is reduced for the same value of the former. In a modification (Fig. 2) a circular disc wafer 10 of monoerystalline N-type silicon has parallel surfaces 12a, 14a and gallium is in-diffused to form P-type layers 18, 20, and surfaces 12a, 14a are covered with a phosphorus doping layer by removing the silicon oxide film formed during prior diffusion and heating in phosphorus oxychloride pentoxide. The formed silicon oxide layer is removed and a gold layer is deposited on surface 14a by vacuum evaporation. The wafer is then heated in inert atmosphere to in-diffuse the gold, after which residual gold and phosphorus are removed from surface 14a and gold from surface 12a; a nonuniform gold concentration within the wafer being produced (Fig. 3, not shown) to be a maximum at junction J 2  and decreasing to a minimum at junction J 1 , by interaction of the phosphorus layer. A molybdenum plate is applied to surface 12a over an aluminium foil, and a gold-boron foil 28 is applied centrally to surface 14a while a peripheral gold antimony foil is also applied thereto; the foils and plate being pressure-heat alloyed to the surfaces so that the contact with surface 12a is ohmic, and the gold-boron foil diffuses P-type impurity into layer 20 for ohmic contact, and the gold antimony foil diffuses N- type impurities to form annular layer 22 in the surface 14a and ohmically contacts the same. The wafer is then chemically etched to expose junctions J 1 , J 2  and the periphery is protected with silicon varnish or rubber, and the wafer is enclosed in a shell (not shown). N-type layer 22 may be introduced prior to the phosphorus doping and gold diffusing. Forward voltage drop/current characteristics and leakage current characteristics are compared with those of conventional thyristors (Figs. 4, 5, not shown) for forward and reverse voltages. Iron or copper may be used as the diffused heavy metal.