Patent GB-1193726-A (GB)
Title: Pulse Transmission System
IPC: H04B1/64
Filed: 1968-09-03
Abstract: 1,193,726. Pulse code modulation systems. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 3 Sept., 1968 [2 Sept., 1967; 11 July, 1968], No. 41858/68. Heading G4H. In a pulse code modulation transmission system the size of the coding unit in the analogue/digital converter of the transmitter and the digital/analogue converter of the receiver is determined by the frequency of occurrence of the most significant bit in the transmitted code group. In the embodiment of Figs. 3, 4, a level generator 23 determines the level of a speech signal, the output from which is combined with the speech signal and fed to a. sampler 4. The analogue output voltage from sampler 4 is fed to an analogue/digital converter 7 where it is sequentially compared with voltage reference signals, the reference signal being subtracted from the input signal and a pulse transmitted whenever the analogue signal exceeds the reference signal. The most significant bit (or the two most significant bits) of the transmitted signal is fed to integrating network 26 to increase the coding unit of the analogue/digital converter. At the receiver the most significant bit (or bits) is fed to an integrating network 35 to vary the coding unit of digital/analogue converter 11 where the pulses of the transmitted code groups are combined in accordance with their weights. In the embodiments of Figs. 6 and 7 (not shown) the incoming speech signal is fed to a full-wave rectifier (52), a polarity bit being derived from a limiter (54) and pulse modulator (55), this bit being combined with the code group in a combination device (56). At the receiver the digital/analogue converter (11) delivers a signal representing the code group together with its inverse to a two-way switch (61) controlled by the polarity bit. In the embodiment of Figs. 8 and 9 (not shown) the voltage from sampler (4) is compared with a sawtooth signal, a gate (160) being enabled to pass clock pulses to a counter (163) until the two signals are equal when the count is transferred to a shift register (169) which is sequentially read out. The two most significant bits of the counter control, via AND gates (178, 181), OR gate (182) and integrating network (26), an amplitude modulator (175) to vary the slope of the sawtooth reference signal. At the receiver the two most significant bits similarly controls amplitude modulator (176 )to vary the amplitude of the pulses fed to a Shannon-type digital/analogue converter (11). In the embodiment of Figs. 10, 11 (not shown) the incoming speech signal is sampled and the resultant amplitude signal fed to a capacitor (65). A reference signal is fed to a second capacitor (86) and the voltage across the capacitors compared by comparator (89) a pulse being transmitted on conductor (9) whenever the voltage across the second capacitor exceeds the voltage across the first capacitor. These pulses are also fed via an amplitude modulator (92) to a switch (76) which distributes the pulses sequentially to the branches of a ladder network (64) so that the charge on the first capacitor (65) is reduced by an amount proportional to the weight of the transmitting pulse. The most significant bit controls the amplitude modulator (92). via an integrating network (26). At the receiver the most significant bit controls via a gate (34) an integrating network (35) and an amplitude modulator (118) the amplitude of the pulses which are distributed by a switch (111) to the associated branches of a ladder network (98) to increase the charge on a capacitor (97). At the end of each code group the voltage across the capacitor (97) represents the binary coded signal. Time multiplex transmission of ten speech channels may be obtained by sequentially connecting the incoming signals to an analogue/ digital converter (128, Fig. 12, not shown) an integrating device (134, 234) being included for each channel and synchronously connected to the analogue/digital converter. At the receiver (Fig. 13, not shown) the most significant bit of each code group is connected to its associated integrator (151, 251) to control the digital/ analogue converter (142) the output from which is sequentially connected to each of the output channels.