Patent GB-1278631-A (GB)
Title: Improvements relating to measuring and testing electrical circuits
IPC: H01L21/822
Filed: 1969-06-09
Abstract: 1278631 Testing logic circuits TERADYNE Inc 9 June 1969 [14 June 1968] 29011/69 Heading G1U Apparatus for testing a logic circuit 1, Fig. 1, having m inputs and n outputs includes a generator 9 which provides a sequence of sets of m binary signals, and a switching supply circuit 15 which, in response to each set of m signals from generator 9, applies to each input of the circuit 1 the appropriate one of two reference voltage sources respectively representing logic 0 and 1. The output of generator 9 is also applied to the m inputs of a standard circuit 13, and the n outputs of the two circuits 1 and 13 are continuously compared in in a comparator 17 which, on detecting a discrepancy, halts the sequencing of generator 9 and operates an alarm and a sorter. Throughout the test the total current drawn by the circuit 1 from its supply and the input impedance presented by each of its m inputs to a logic 1 signal is continuously monitored. The apparatus is constructed in three structurally separable parts, the first part comprising those components which are independant of the type of circuit to be tested, the second those components peculiar to a family of logic circuits, e.g. those which determine logic 0 and 1 levels, and the third those components peculiar to the particular type of logic circuit to be tested, e. g. standard circuit 13. Input Signal Generator, Fig.1. In the absence of a fault signal from comparator 17, control unit 3 supplies clock pulses to step on an m-bit binary counter in generator 9, the counter being such that only one bit changes at each clock pulse. The sequence comprising all possible combinations of the m-bits is repeated continuously, the sequence repetition time being less than the time taken to connect circuit 1 to the testing apparatus and then disconnect it again. Lamps in a display 11 indicate the state of the counter at any time. The binary signals constituting the counter output are passed to a lockout circuit, which suppresses certain digits if the particular circuit to be tested has fewer inputs than there are counter digits, and suppresses any combinations of digits which that particular circuit will not in use receive. Generating Reference Voltages; Testing Supply Current, Fig. 8. Various reference and supply voltages are derived from a single reference Vr by respective adjustable-gain amplifiers 51-59, 60. Amplifier 60 provides the supply voltage V cc  required by the circuit under test, and is energized via a resistor R15 so that the voltage dropped across this resistor is a measure of the total current drawn by the circuit under test. Excessive voltage drop, indicating that the circuit under test is faulty, is detected by a level detector 61. Amplifiers 51, 53, 55 respectively provide references V1H for testing the input impedance of circuit 1, V1L constituting the binary 0 input signal for circuit 1, and V0L constituting a binary 0 output signal with which 0 outputs from circuit 1 are compared. Amplifier 57 provides a reference VOH constituting the binary 1 output signal with which 1 outputs from circuit under test are compared, the level of V0H being made dependant on the circuit supply voltate V cc . Input Switching Circuit; Testing Input Impedance, Fig.9. Each of the m binary output signals from generator 9, Fig. 1 is applied to a respective terminal such as I1 of a switching/ detector circuit ID1. When the signal at I1 is 0 the reference level V1L is applied to the corresponding input terminal I1t of the circuit under test via transistor Q. 1. When the signal at I1 is 1 transistor Q1 is cut off and binary 1 is supplied to terminal I1t from supply V s . At the same time Q2 conducts to apply level V1H to one input of a differential amplifier 67, which compares this level with the voltage at the junction of resistors R16-R17. If the input impedance presented at terminal I1t is too low the latter voltage will be less than V1H, changing the polarity of the output of 67, which is detected as being a fault condition. Output Comparator, Fig. 10. Each of the n outputs, such as c, of the circuit 1 under test is connected through a resistor (R23) and diode (CR6) to a resistor - Zener diode network R22-Z1 which presents the correct load impedance. Each of the n outputs is also connected to an input terminal, as D<SP>1</SP>, of a differential amplifier (81). The signal B1 from the corresponding output of the standard circuit 13, Fig. 1 controls switches Q5, Q6 so as to apply the other input of the differential amplifier 81 either the reference level V0H if the signal D1 should be 1, or the level V0L if it should be 0. The output of amplifier 81 is passed to a limiteramplifier 83 which supplies either a 0 or 1 signal to gate X0R according to the polarity of its input. Gate X0R is an exclusive OR gate which receives signal B1 as its other input and thus provides an output only when there is a discrepency between signals B1 and D1, or when signal D1 is correct but of unsuitable magnitude -e.g. is a binary 1 output but has too low a voltage. An output on any one of the gates X0R lights a fault lamp in display 11, Fig. 1 and passes a fault signal to control unit 3.