baber/WOPTO huggingface dataset:
Patent JP-H07325391-A (JP)
Title: Resin composition reactive for visible light and sheetlike optical recording material using the same
Inventor: HOSODA YUKIO
IPC: G03F7/028
Filed: 1994-05-31
Abstract: PURPOSE:To provide a resin compsn. reactive for visible light which rapidly reacts with irradiation of visible semiconductor laser beam, and to provide a sheet type optical recording material in which an excellent image is formed. CONSTITUTION:This resin compsn. reactive for visible light contains (a) p- vinylphenol polymer having >=4000 weight average mol.wt., (b) cation reactive compd., (c) 2,4,6-tris(trichloromethyl)-1,3,5-triazine, (d) squarylium salt sensitizing dye having the max. absorption wavelength between 600nm and 700nm, and (e) aromatic compd. expressed by formula. In formula, R1, R2 are substd. or unsubstd. satd. or unsatd. hydrocarbon groups, and R3 is a substd. or unsubstd. aliphatic group or a substd. or unsubstd. aromatic group. The resin compsn. is used to form a photosensitive recording layer of a sheetlike optical recording material.
Patent JP-S5344919-A (JP)
Title: The construction of flat bottom cylindrical tank
Inventor: HASEGAWA TSUTOMU
IPC: F17C3/00
Filed: 1976-10-05
Abstract: PURPOSE:A construction method of flat bottom cylindrical tank that is so designed that the examination of bottom plate is easy and the bottom plate quality and workabiility is enhernced by effecting the bottom plate construction and roofing material construction is relation to each other.
Patent JP-S5643751-A (JP)
Title: Manufacture of semiconductor device
Inventor: IMAOKA KAZUNORI
IPC: H01L27/10
Filed: 1979-09-17
Abstract: PURPOSE:To hold the degree of insulation between polycrystalline silicon layers and improve the accuracy of positioning by a method wherein an oxide layer is formed on the polycrystalline silicon layer and a silicon nitride layer on the oxide layer, and an oxide film with sufficient thickness is made up to the flank of the silicon layer. CONSTITUTION:The field oxide film 14 and a capacitor oxide film 18 are coated with the first polycrystalline silicon layer 17, an oxide film 19 is formed on the layer 17 by means of high temperature treatment, and the upper surface is further coated with a silicon nitride film 13. The nitride film 13 is etched according to a pattern, and only a power source line electrode layer and a capacitor electrode region are left. Each film and the polycrystalline silicon layer 17 are sufficiently etched so as to over-etch the layer 17. A side etched part is treated at a high temperature, and an oxide film with sufficient thickness is made up. The nitride film 13 functioning as a mask is removed, all oxide films in a gate region are removed, a gate oxide film 20 is formed, and the second polycrystalline silicon layer 15 is wired on the upper surface. Thus, the accuracy of a memory-cell can be improved.
Patent JP-S62278313-A (JP)
Title: Manufacture of dynamic pressure group bearing
Inventor: TSUKADA KIYOTAKA
IPC: F16C33/24
Filed: 1986-05-26
Abstract: PURPOSE:To accurately form a grooved pattern, by forming a member, in which a groove for generating a dynamic pressure must be formed, by ceramics and improving durability and reliability while printing the spiral pattern on a bearing surface on which the groove is formed. CONSTITUTION:A groove for generating a dynamic pressure is provided in either a bearing or a journal opposed to each other, further a relative motion is performed in a condition that fluid is interposed in a fine gap between both the bearing and journal. When the dynamic pressure group bearing is manufactured as in the above, either the bearing or the journal is prepared by ceramics, further paint, mainly composed of resin or rubber, is printed on mutually opposed surfaces of a ceramics made member. And a groove is formed by hardening the paint further applying a shot blast process to a part printing no paint, thereafter the paint is removed. Here the printing is performed by using a screen 13 which forms a spiral pattern 16 by a screen part 14 and a no-hole part 15.
Patent JP-2000027093-A (JP)
Title: Recording paper, its production, water-based coating composition, its coating method and coated product therefrom
Inventor: SAITO YOICHI
IPC: B41M5/50
Filed: 1999-04-27
Abstract: PROBLEM TO BE SOLVED: To obtain recording paper that has a good void layer with high uniformity and evenness, even when the supporter is coated with a dried thick layer, by preparing a coating composition of specific properties from fine particles, a hydrophilic binder and a viscosity thickener. SOLUTION: A hydrophilic binder, for example, a poly(vinyl alcohol) binder, is combined with an inorganic fine particles, for example, fine particles of silica synthesized via the vapor phase process, at a weight ratio of 3-10, in addition, with a viscosity thickener, for example, boric acid or (its salt) whereby the objective coating composition is prepared that has a viscosity of 10-100 cp. at 40 deg.C and a viscosity at 15 deg.C that is substantially more than 20-fold higher that at 40 deg.C and is substantially free from gelatin with a pH of 3.5-6.0. The substrate is coated with the resultant composition with a viscosity of 10-100 cp, then cooled down so that the temperature becomes lower than 20 deg.C at the coating face to increase the viscosity of the coated layer more than 20-fold. Then, the coated layer is blown with the wind higher than 20 deg.C whereby the objective recording paper having the void layer with 30-60 μm thickness on the dry basis is obtained.
Patent JP-S5869040-A (JP)
Inventor: MIRUTON KAAZU
IPC: B32B7/08
Filed: 1982-07-08
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6010376-A (JP)
Title: Processing method of channel device
Inventor: KAMIO KUNIYOSHI
IPC: G06F13/12
Filed: 1983-06-29
Abstract: PURPOSE:To simplify the processing of a channel device by allowing a control section to cancel data reference when a control command is given and an address having a required number of bytes or over is designated. CONSTITUTION:When an address deciding section 1 decides that an inputted address has >=16MB, it is informed to a flag processing section 4. A flag processing section 4 sets a flag being a control command to an idle bit of a channel control word. A flag detecting section 5 detects the presence of the flag, and when the flag exists, a byte count processing section 6 is activated so as to bring a byte count forcibly to ''1''. Thus, a channel device gives an interruption to the processor by the next count. When the flag detecting section 5 detects the absence of flag, an error generating section 3 is operated. On the other hand, when the address deciding section 1 decides that the inputted address is <=16 MB, a data reference processing section is activated and the data reference is attained.
Patent JP-H07262805-A (JP)
Title: Head-lamp-capsule assembly for hid vehicle
Inventor: CHIYAARUZU EMU KUUSHIEIN
IPC: F21V15/00
Filed: 1993-04-23
Abstract: PURPOSE: To withstand operation temperatures and to allow accurate positioning by mounting a wedge holding a rear end part of an arc discharge tube to a base part through an RF ring and a retainer coupling with the wedge in an inclined face. CONSTITUTION: In this arc discharge headlamp capsule 10, a front end part of an arc discharge lamp 16 of a double-end arc tube 12 is provided with a front lead wire 18, while a rear end part 22 thereof is provided with a rear lead wire 20. The rear end part 22 is held inside a cylindrical inner wall 28 of a wedge 24. The wedge 24 is mounted on an inner wall 68 of a base part 66 through an RF ring 64 and a retainer 38 joining with the wedge 24 by a conical wall. The front lead wire 18 is connected to a first coupling body 70 through a front coupling rod 54 inserted through an insulation sleeve 60 and a passage 46 of the retainer 38. The rear lead wire 20 is connected to a second coupling body 72. The coupling bodies 70, 72 are respectively supported by the base part 66, while the base part 66 is formed with a distortion escape part 76 between the coupling bodies 70, 72.
Patent JP-S599084-A (JP)
Title: Thermal multi-color printer
Inventor: KUBO TAKESHI
IPC: B41J35/16
Filed: 1982-07-09
Abstract: PURPOSE:To permit the hard color copying of color pictures, color data, etc., by providing a combination of a transfer mechanism, a transfer ribbon drive mechanism, a positioning mechanism, and a paper drive mechanism in each position of a ribbon in such a way as to enable them to exhibit their respective specific actions. CONSTITUTION:When a printing command is supplied, whether a transfer ribbon 3 is present in a given position is detected by a mark sensor 13. When the transfer ribbon 3 is present in a given position, a thermal head 12 is moved in the direction of A, and the transfer ribbon 3 is pressed through a paper 7 by a platen roller 5. Whereupon, yellow ink coated on the transfer ribbon 3 is orderly transferred to the paper 7 and Y-picture is formed. When the paper 7 is set back to the start position, whether the transfer ribbon 3 is present in a given position is again detected by the mark sensor 13, and a magenta-color picture (M-picture) is printed on the Y-picture. Thereafter, in the same way, a cyanine- color picture (C-picture) is printed in overlapping manner on a composite picture of Y-picture and M-picture to complete a color printing.
Patent JP-S5823113-A (JP)
Inventor: KOUMURA YUKIO
IPC: H01B13/26
Filed: 1981-07-31
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S60262730-A (JP)
Title: Work loading device for rack cage for transportation of works
Inventor: NAKAMURA TOSHIMITSU
IPC: B65G1/07
Filed: 1984-06-11
Abstract: PURPOSE:To automate work loading operation by installing a work transporting rack cage, which is equipped with racks consisting of rods whose tips can swing oscillatively, on a table lifter, and by allowing a work carry-in means to come in and out of the rack cage. CONSTITUTION:This work transporting rack cage 7 is so constructed that a plurality of racks 9 are placed in vertical arrangement in a rectangular framing 11. Each rack 9 is composed of a plurality of rods 8 laid parallelly, wherein the base end of each rod 8 is fixed to a horizontal member 12 mounted at the framing 11, while the foremost end is left free. The rack cage 7 is installed on a table lifter 6 through a transversing conveyor 13. A work carry-in means 10, for ex. carry-in conveyor 10a, is so arranged as capable of moving inside and outside the rack cage 7 as well as positioning between rods 8 when situated inside the rack cage 7. According to this construction, works 1 can be placed automatically on the racks 9 through co-operation of the table lifter 6 and carry-in conveyor 10a.
Patent JP-H04322135-A (JP)
Title: Uniterruptible power supply
Inventor: KITA AKIRA
IPC: H02J7/34
Filed: 1991-04-22
Abstract: PURPOSE:To enhance reliability and performance of an uninterruptible power supply employing enclosed lead battery. CONSTITUTION:The uninterruptible power supply comprises an enclosed lead battery 6 connected through a first switch 5-1 with the joint of a rectifier 2 and an inverter 3 and a charger 9 for feeding the enclosed lead battery 6 with power from a commercial power supply 1 through a second switch 5-2. The second switch 5-2 is normally turned OFF and a control signal generator 7 monitors the open circuit voltage of the enclosed lead battery 6. When the open circuit voltage drops below a predetermined level, the second switch 5-2 is turned OFF to charge the enclosed lead battery 6 and after detection of closed circuit voltage, the second switch 5-2 is turned OFF. Consequently, early deterioration of the enclosed lead battery 6 due to sustained charging operation can be prevented resulting in enhancement of the reliability and performance of uninterruptible power supply.
Patent JP-H02300078-A (JP)
Title: Monitoring device for elevator
Inventor: NAGATA YASUHIRO
IPC: B66B5/02
Filed: 1989-05-12
Abstract: PURPOSE:To arrange so that a superviser may take the minimum necessary counter measures at the time of abnormality occurrence, by connecting a communication controller to a monitoring center and a superviser chamber, and analyzing a trouble data by means of the communication controller, and sending out to an indicator at the superviser chamber a message which is a combination of this analyzed data and a previously memorized memory information. CONSTITUTION:When a trouble occurrence is inspected at an elevator controller 1, a data is made out at a trouble data making out portion 2, and transmitted to a communication controller 11. And the seriousness of the trouble data is decided at an analyzing portion 14, and when it is decided that the trouble is serious, a monitoring center 4 is immediately notified of abnormality, and a serious trouble opposition message is made out of the trouble data and the data of a message data memorizing portion 15 by means of a composition means 16. When it is decided that the trouble is light, a light trouble opposition message is likewise made out at the composition means 16, and an output is made from a transmitting portion 17 to a superviser chamber 20, and an indication is made at an indicating portion 23. Accordingly, a superviser can take measures opposing the light trouble.
Patent JP-H0415991-A (JP)
Title: Manufacture of ceramic wiring substrate
Inventor: BABA YASUYUKI
IPC: H05K3/46
Filed: 1990-05-09
Abstract: PURPOSE:To eliminate a land and form a dense circuit substrate by forming via holes through a film arranged on the front of a green sheet, peeling off the film from the green sheet after filling via conductor in the via holes from the film side and baking the green sheet. CONSTITUTION:Since a green sheet 1 is provided with via holes 2 through a film 4 arranged on the green sheet and via conductor 5 is filled from the film side, even when a land is formed on the film, a landless green sheet whose via holes are filled with conductor is obtained when the film is peeled off from the green sheet afterward. Namely, the landless and dense multilayer substrate is obtained by peeling off the plastic film 4 from the green sheet 1, bonding the green sheet, which is wired under the laminating condition of 200kg/cm<2> at 80 deg.C, by thermocompression, removing a binder at approximately 500 deg.C and baking at 900 deg.C.
Patent JP-S5963452-A (JP)
Inventor: MARUKAMU BITSUKUNERU MATSUKINE
IPC: F24H3/06
Filed: 1983-06-30
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S6012288-A (JP)
Title: Chip dresser
Inventor: YOKOTA HIROMASA
IPC: B23K11/30
Filed: 1983-07-01
Abstract: PURPOSE:To shape chips with good accuracy by providing a chip guide which bears dressing force in place of a gun support and restrains and positions the chips and cutter in specified positions. CONSTITUTION:A chip dresser provided with a chip guide 40 is positioned with respect to a cutter 11 as chips C intrude respectively into bushings 46 when the chips are pressurized. If there is variance in the accuracy of stopping the chips C, the chips C are guided and corrected into the radial parts 47 in the bushings 46. Then the cutter 11 makes revolving operation to dress the chips. The dressing force in this stage is born by the guide 40 around the bushings 46 and is not acted at all to a welding gun and the support side thereof.
Patent JP-H02296214-A (JP)
Title: Liquid crystal device
Inventor: HANIYU YUKIO
IPC: G02F1/1337
Filed: 1989-05-11
Abstract: PURPOSE:To display a high-contrast image and to prevent the occurrence of an afterimage by arranging a pair of substrates each having a film of polyimide consisting of specified structural units and holding a ferroelectric liq. crystal between the substrates. CONSTITUTION:Insulating films 13a, 13b and orientation controlling films 14a, 14b of polyimide represented by formula I are laminated on substrates 11a, 11b coated with transparent electrodes 12a, 12b, respectively, and a ferroelectric liq. crystal 15 is held between substrates 11a, 11b. In the formula I, each of land m is 0 or an integer of 1-3. A high-grade display having high display contrast is obtd. and an offensive afterimage phenomenon is not caused.
Patent JP-S60263472-A (JP)
Title: Semiconductor device
Inventor: KINOSHITA HARUHISA
IPC: H01L29/205
Filed: 1984-06-11
Abstract: PURPOSE:To enhance mutual conductance and simplify the manufacturing process by a method wherein a first and third semiconductor layers are built by means of modulation doping and FETs equipped with channels of first and second conductivity types have second semiconductor layers containing little impurities for the creation of quantum wells. CONSTITUTION:Application of a negative bias voltage to the second gate electrode 13 of a P-channel FET T2 in Fig. A causes energy levels to shift upward in an undoped GaAs layer 6, undoped Al0.3Ga0.7As layer 7, and P<+> Al0.3Ga0.7 As layer 8, producing two-dimensional gas 9 of holes in the GaAs layer 6 along its surface interfacing with the undoped Al0.3Ga0.7As layer 7. The two-dimensional gas 9 of holes is accumulated in a quantum well built in the GaAs layer 6, is distributed along the portion of the GaAs layer 6 interfacing with the undoped Al0.3Ga0.7As layer 7, and forms a P channel. No flow into the second gate electrode 13 takes place of the two-dimensional gas 9 of holes. Similarly, application of a positive bias voltage to the first gate electrode 17 of an N-channel FET T1 in Fig. B results in an N channel composed of two-dimensional gas 19 of electrons distributed in a quantum well built in the GaAs layer 6 along its surface interfacing with a layer 5.
Patent JP-H04275301-A (JP)
Title: Lowering of molecular weight of cellulose acetate, lactone-modified cellulose acetate and production thereof
Inventor: ENDO TOSHIRO
IPC: C09D101/12
Filed: 1991-02-28
Abstract: PURPOSE:To produce a plasticizer having sufficient affinity to cellulose acetate by lowering the mol.wt. of cellulose acetate and subsequently modifying the product with g-caprolactone. CONSTITUTION:10-50 pts.wt. of cellulose acetate having an acetyl-substitution degree of 1.7-2.9 and a number-average polymerization degree of >=50 is subjected to a heating treatment in the presence of 50-90 pts.wt. of epsilon- caprolactone, and the remaining hydroxyl groups are subjected to a ring-opening addition polymerization with the epsilon-caprolactone, thereby permitting to lower the mol.wt. of the cellulose acetate and to produce a plasticizer having sufficient affinity to cellulose acetate.
Patent JP-2000312148-A (JP)
Title: Phase-locked loop circuit
Inventor: KIKUCHI MASARU
IPC: H03L7/081
Filed: 1999-04-27
Abstract: PROBLEM TO BE SOLVED: To cancel dispersion due to a frequency dividing ratio and manufacture by constituting a delay circuit in a closed loop. SOLUTION: A programmable delay circuit 306 is constituted in a closed loop. In such a constitution, an inner signal 312 outputted from a VCO circuit 304 is outputted by adjusting the delay of '+' with respect to an outer input reference clock signal 310 by a programmable delay circuit 305. The inner signal 312 is sent to the programmable delay circuit 306 as a closed loop signal. The programmable delay circuit 306 sends an output signal obtained by adjusting the delay of '-' with respect to the outer input reference clock signal 310 to the clock inputs of a frequency divider 307 and an FF circuit 308. In a divider 307, the inputted signal is frequency divided into N and is sent to the data input of the FF circuit 308. In the FF circuit 308, data is sampled by a signal which is in front of the input in the frequency divider 307, so that delays in the frequency divider 307 are canceled and the precision of delay quantity adjustment is improved.
Patent JP-S5910662-A (JP)
Inventor: FUNAKI GANTAN
IPC: E04D3/35
Filed: 1982-07-12
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S5643838-A (JP)
Title: Busy incoming system
Inventor: KAMISAKA KIYUUICHI
IPC: H04M3/42
Filed: 1979-09-18
Abstract: PURPOSE:To improve the efficiency of utilization of a radio circuit by holding a radio circuit used for a current call even after the end of the call when incoming arrives at a mobile subscriber who is busy and by using it for the incoming arriving during the call. CONSTITUTION:When incoming arrives at mobile subscriber 1 who is busy from telephone set 5, connection controller 6 finds that it is busy and controls switching network 3 to connect incoming guide talkie unit 7 to the channel in switching network 3 that telephone set 2 and subscriber 1 use for the telephone call, thereby informing subscriber 1 of the incoming. Further, stand-by guide talkie unit 8 instructs telephone set 5 to wait because subscriber 1 is busy at that time. Then subscriber 1 also holds itself in the off-hook state. On discriminating the end of the call between subscriber 1 and telephone set 2, connection controller 6 holds the used radio circuit and then connects telephone set 5, connected to unit 8, to the held circuit.
Patent JP-S6011375-A (JP)
Title: Led array light source
Inventor: SHIMADA KAZUYUKI
IPC: G03B27/32
Filed: 1983-06-30
Abstract: PURPOSE:To make it possible to secure linearity, in an LED rray light source for an electrophotographic system, by arranging blocks so as to successively shift the same at every distance over which a photosensitive element moves during an ON/OFF control transfer time between the blocks. CONSTITUTION:When a distance, over which a photosensitive element moves for am ON/OFF control transfer time between blocks B1, B2,... of an LED array, is set to DELTAl, the blocks are arranged stepwise at every distance DELTAl in a sub- scanning direction. In this driving control system, the blocks are divided into two groups in a main scanning direction to attain speed acceleration but, for example, blocks B11, B12 are simultaneously subjected to ON/OFF control and handled as one block B1 though spaced apart to each other while blocks B12, B22,...B1N, B2N are arranged so as to be successively shifted by DELTAl. By this method, in spite of time sharing, the formation of a stepwise latent image is eliminated to make it possible to secure linearity.
Patent JP-S6012587-A (JP)
Inventor: AKIBA KEIJI
IPC: G10L21/013
Filed: 1983-07-01
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-S61278957-A (JP)
Title: I/o transfer data trap system
Inventor: MANO HIROCHIKA
IPC: G06F13/12
Filed: 1985-06-04
Abstract: PURPOSE:To collect access request source source information by checking whether or not the trap definition area of a main memory device is accessed at the time of analyzing a channel command word CCW. CONSTITUTION:When data is transferred to an I/O device 4, a channel device 3 executes the CCW analysis, and a control part 9 checks whether the trap definition is present or not with the aid of trap difinition presence or absence information on contents in a register 5. When the trap definition is present, it is checked to be an access to the trap indication area or not with the aid of the main memory address of a CCW memory 8, the number of transfer words, the trap definition area top addresses of the contents of registers 6 and 7 and a trap definition final address. When it is the access to the trap definition area, a trap detecting flag 10 is set, and a trap interruption is applied to a central processing unit 1. Thus the central processing unit 1 can collect the address of the I/O device issuing an access request and trap information on CCW, etc.