Patent GB-1237517-A (GB)
Title: Muting arrangement for a communication system
Inventor: WATKINSON STEPHEN WILLIAM
IPC: H03G3/34
Filed: 1970-02-05
Abstract: 1,237,517. Muting; limiters; F.M. receivers. PYE Ltd. 5 Feb., 1970, No. 5515/70. Heading H3R and H3T. The invention comprises an arrangement for muting a communication channel in the absence of a desired signal, in which at least part of the content of the communication channel or of an auxiliary channel is applied to a counting circuit whose output is a function of the repetition rate of the components of the channel content or part thereof, the output being employed to control the state of a mute gate provided in the communication channel in such a manner that the gate is closed when components above a given frequency and amplitude appear in the channel content. The arrangement relies on the mean frequency of noise pulses, which are counted by the counter, decreasing as the signal carrier level rises. The invention also comprises a mute gate in which a signal path passes through the source-drain path of a field effect transistor, the gate electrode of which has a bias applied thereto to normally hold the sourcedrain path low resistance and the signal path open, a diode connected to the gate electrode being rendered conducting in the absence of a signal to change the bias to the gate electrode rendering the source-drain path high resistance and closing the signal path. An embodiment comprises a radio receiver for both A.M. and F.M. signals, in a communication system in which the main transmitter is reinforced by auxiliary transmitters used to extend the area covered, transmitting on frequencies offset by a small amount from that of the main station. The receiver comprises R.F., first mixer, first local oscillator, first I.F. filter and amplifier, second mixer and second local oscillator stages 3, Fig. 3, the second I.F. signal being branched into lines 5, 6. Branch 5 is connected to an A.M. I.F. amplifier 7 followed by A.M. detector and A.G.C. stage 9, an A.G.C. output being fed back on line 12 and an audio output being fed to a first input of a muting gate 11. Branch 6 is connected to a limiting F.M. I.F. amplifier 13 followed by discriminator 15, the audio output of which is fed via a de-emphasis circuit 16 to a second input of gate 11. The output from discriminator 15 is also fed to a muting circuit comprising high-pass filter 19 and level control, a noise amplifier and limiter 20 whose upper frequency limit is restricted, a noise detector 21 comprising a counter, emitter-follower and lowpass filter 22, Schmitt trigger circuit 23 and an inverter 24. The output from inverter 24 is passed on line 25 to the control input of gate 11. Selection of the desired audio signal is by means of a switch 27; a further switch 30 earths the input to inverter 24 and disables the muting circuit. In Fig. 4, which shows the muting circuit, high-pass filter 19 comprises capacitor C1 and inductor L, and is arranged to cut off at a frequency higher than the second harmonic of the maximum difference frequency between the transmitters. Noise amplifier and limiter 20 comprises transistors T1, T2 and the bandwidth is restricted to 300 kcs. by capacitor C3; resistors R3-R6 are so chosen that limiting occurs. The pulse counter 21 comprises diodes Dl, D2, the emitter follower 22, transistor T3, and the Schmitt trigger circuit 23, transistors T4, T5. The inverter 24 comprises transistor T6, which is biased by means of diode D3 so as to provide a sharp turn-over action. The gate 11 comprises a pair of field-effect transistors T7, T8, each with its source-drain path in series with one of the audio signal lines 10, 17; their outputs are combined on resistor R24 for application to an audio amplifier comprising transistor T9. The gates of field-effect transistors T7, T8 are biased via resistors R27, R28, R29, switch 27 selecting the transistor which is biased conductive: when muting occurs transistor T6 is biased conductive and the drop in collector potential is communicated to the gates of the field-effect transistors T7, T8 via diodes D4, D5, rendering them both non-conductive.