Patent GB-1340382-A (GB)
Title: Data processing systems
IPC: G06F13/12
Filed: 1971-05-11
Abstract: 1340382 Data processing apparatus INTERNATIONAL BUSINESS MACHINES CORP 11 May 1971 [15 June 1970] 1419/71 Heading G4A Access to a relatively slow speed main memory from one of a number of channels is controlled by a channel priority selector and a timer for inhibiting acceptance of channel requests by the priority selector for one main memory cycle after a priority grant has been made. Each channel request on lines 120 is gated to priority logic 134 provided the channel busy trigger 128 is not set, and the trigger 140 of the highest priority requesting channel is set to send a response over 144 and set the corresponding channel request in process trigger 142 which then blocks any further requests from the same channel for 3 memory cycles to reduce memory interference caused by one channel locking out all the others. Logic 134 also turns on trigger 128 to block further requests from all channels at gates 132 and starts a response counter 150 to time out one memory cycle after which triggers 128, 140 are reset and a timer 154, Fig. 3B, is started. Under certain conditions a long access delay to storage may be encountered by a channel, and this situation is detected by potential drum overrun detector which inhibits the central processing element for a number of machine cycles to reduce the busy memory interference encountered by the channel. Store/fetch requests.-The selected channel responds to the signal on control line 144 to place an address on an address bus which is common to all channels, and the first output 156 of timer 154 gates this address to a channel storage address register CSAR, Fig. 2A (not shown), from which it is passed on to the core and buffer storage address buses. Meanwhile, the output of response counter 150, by resetting triggers 128, 140, has allowed any new request from a different channel to be accepted by priority logic 134, and response line 144 has passed the first request on to encoder 160, pushdown sink stack buffer 162 and decoder 168 from which it is subsequently gated out to set the appropriate advance to channel trigger 174. Following this, for a fetch operation, gate 186 and latch 188 gate the data on a storage bus out SBO to a register CSBO which places the data on a common data bus returned to the channels. For a store operation, output 192 of timer 192 gates data supplied by the selected channel over a common data bus into a core storage data bus register CSDB. Finally, the gate 194, Fig. 3A, enabled by the set trigger 174 resets the set trigger 142 to allow a new request from the first channel to be accepted. Channel fetches are only made from main storage, the requested address being held in CSAR until the requested storage module is free. Channel stores are also only made in main storage, the address is also placed on BSAB and data directories associated with the buffer store are interrogated to see if the address is in buffer storage. If so the relevant block is made invalid in the directory and cannot be fetched again from buffer storage without another transfer from main storage (see below). CPE fetch operation.-A fetch request from CPE is placed on the buffer storage address bus BSAB, and if the required data is not in the buffer store, the fetch request is placed in one of a number of transfer address registers (TAR) which control a block transfer operation. The addresses of words in a block are placed on the core storage address bus CSAB in successive machine cycles, and the words read out being transferred to the buffer store and to the requesting source.