baber/WOPTO huggingface dataset:
Patent TW-448190-B (TW)
Title: The water-absorbing agent and processes therefor
Inventor: WADA KATSUYUKI
IPC: C08L83/00
Filed: 1997-10-06
Granted: 2001-08-01
Abstract: The invention provides a water-absorbing agent, which has high absorption capacity and excellent absorption efficiency under increased pressure and can display excellent water absorption properties when used for sanitary materials even if the resin concentration of a water-absorbent resin is high. The water-absorbing agent has an absorption capacity of 30 (g/g) or more and the below-defined absorption efficiency of 0.7 or more under increased pressure. This agent can be obtained by heating in the presence of a surface-crosslinking agent a water-absorbent resin having an absorption capacity of 40 (g/g) or more and an amount of an eluting component of 1 wt % or less relative to the water-absorbent resin, or by: polymerizing a water-absorbent resin in the presence of a chain transfer agent; treating the polymerized resin with a hydrophilic solution; and heating the treated resin in the presence of a surface-crosslinking agent. Absorption efficiency under increased pressure = absorption capacity of upper swollen gel layer of water absorbing agent under increased pressure/absorption capacity of lower swollen gel layer of water absorbing agent under increased pressure.
Patent TW-359893-B (TW)
Title: Low-impedance CMOS output stage and method
Inventor: WU MICHAEL A
IPC: H03K5/12
Filed: 1997-10-29
Granted: 1999-06-01
Abstract: A CMOS output circuit including a differential error amplifier (3) is operated to provide a stable quiescent bias current in an output MOSFET by causing a first current equal to a threshold voltage of a P-channel reference MOSFET (M1) divided by the resistance of a reference resistor (R1) to flow through an N-channel current mirror control MOSFET (M4). A first N-channel current mirror output MOSFET (M6) having a gate coupled to the gate of the N-channel current mirror control MOSFET (M4) and a drain coupled to a drain of the P-channel reference MOSFET (M1) causes a second current proportional to the first current to flow through the P-channel reference MOSFET (M1). The first current is controlled in response to feedback from the P-channel reference MOSFET (M1). A bias current in an error amplifier (3) is controlled in response to the N-channel current mirror control MOSFET (M4). The bias current in the error amplifier and the resistances of first (R2) and second (R3) resistive load devices of the error amplifier are scaled to produce a drive voltage which applies a gate-to-source quiescent bias voltage to a P-channel pull-up MOSFET (M11) which is substantially equal to and tracks with the gate-to-source voltage of the reference MOSFET (M1).
Patent TW-356565-B (TW)
Title: Method and device for removing a semiconductor wafer from a flat substrate
Inventor: PIETSCH GEORG
IPC: B24B7/17
Filed: 1997-11-17
Granted: 1999-04-21
Abstract: A kind of method for removing a semiconductor wafer from a flat substrate (especially the polishing cloth of the double polishing machine), its characteristics is a liquid is pressed through the substrate against the semiconductor wafer placed on the substrate, the semiconductor water being lifted from the substrate by the liquid and then being picked up by a pick-up device.
Patent TW-364977-B (TW)
Title: System-on-chip layer compilation
Inventor: LUK WING K
IPC: G06F17/50
Filed: 1997-11-21
Granted: 1999-07-21
Abstract: A layout compiler compiles from hardware description language (HDL) and schematic description of a design, which consists of dynamic random access memory (DRAM) components and logic components, to the layout of an integrated logic and DRAM system on a single integrated chip. The layout compiler creates the physical structure (floor-plan) of integrated logic/DRAM chips and generates on-chip interconnections between the DRAM components and logic components. By integrating logic and DRAM memory onto the same chip, the performance gap which is the difference between the logic processor's data processing rate and the DRAM memory's data access rate can be minimized. Further, the bandwidth between the logic processor and the DRAM memory can be increased significantly. The layout methods eliminate the off-chip drivers and heavy capacitive loads presented in the off-chip interconnections. Low power dissipation is a direct result of integrated logic/DRAM chip in high frequency operations. This method enables the optimization of the on-chip metal interconnections between the logic components and the DRAM components in a way to achieve higher system bandwidth and system performance, lower power dissipation and packaging cost.
Patent TW-396440-B (TW)
Title: Method and system for controlling manufacturing steps in the manufacture of monocrystalline semiconductor silicon wafers
Inventor: TOYAMA KOHEI
IPC: H01L21/02
Filed: 1998-03-10
Granted: 2000-07-01
Abstract: There is disclosed a method and system of controlling manufacturing steps in the manufacture of monocrystalline semiconductor silicon wafers. In a main manufacturing process in which wafers obtained by slicing an ingot undergo the manufacturing steps of lapping, chamfering, etching, mirror-polishing, cleaning, inspection, and shipment, a stocker for temporarily storing wafers is disclosed to perform lot control based on a lot measured in wafer units. The method and system improve productivity and quality.
Patent TW-367260-B (TW)
Title: A toy construction system
Inventor: KROG RICCO REINHOLDT
IPC: A63H33/10
Filed: 1998-03-18
Granted: 1999-08-21
Abstract: The present invention relates to a toy construction system comprising building elements of a first type that has a pair of opposed walls that define a space between said opposed walls, wherein those sides of the walls that face towards the space are provided with protruding ribs, and building elements of a second type that have a coupling head which may, by a snap-effect with protruding ribs, be received and releasably secured in the space between the walls on a building element of the first type, wherein said system further comprises building elements of a third type with coupling studs, wherein building elements of the first type or the second type have a cavity for releasably receiving and securing coupling studs on building elements of the third type.
Patent TW-370687-B (TW)
Title: Manufacturing method for forming an opening with deep ultra-violet photoresist
Inventor: LIAO KUAN-YANG
IPC: G03F7/40
Filed: 1998-04-21
Granted: 1999-09-21
Abstract: The present invention provides a manufacturing method for forming an opening with deep ultra-violet photoresist (DUV PR), which includes forming an insulation layer on a substrate having element structures; then forming a DUV PR layer having a first opening on the insulation layer; and forming a capping layer on the DUV PR layer, defining the insulation layer with the first opening and forming a second opening on the insulation layer, wherein the capping layer is used as a protection layer of the DUV PR layer; and removing the DUV PR layer and the capping layer to expose the insulation layer so as to complete a required opening.
Patent TW-360821-B (TW)
Title: Heat sink with foamed metal heat dissipation
Inventor: Zhao zhong-xing
IPC: H05K7/20
Filed: 1998-05-14
Granted: 1999-06-11
Abstract: The invention relates to a heat sink designed according to the porous media heat transfer theory, which can greatly increase the heat dissipation surface area without compromising the convective heat transfer coefficient thereof, under a condition where the surface of heat dissipation maintains a sufficient temperature difference. The use of porous channels enable a turbulent longitudinal diffusion effect while avoiding the problem of the formation of a heat boundary layer in a conventional fin technology. The heat dissipation capability of the invented heat sink with foamed metal heat dissipation can reach 5 W/cm<SP>2</SP>; while the equivalent convective heat transfer coefficient reaches 0.5 W/cm<SP>2</SP> DEG C.
Patent TW-378168-B (TW)
Title: Oscillating mass-based tool with dual stiffness spring
Inventor: COOPER TIMOTHY R
IPC: B25B21/00
Filed: 1998-05-28
Granted: 2000-01-01
Abstract: Disclosed is a low reaction oscillating mass-based torquing tool wherein an oscillating mass is excited into near resonant oscillation by reversing pulses resulting in increased energy stored in oscillation about a dual stiffness spring which develops a higher torque output with the stiffer spring action in the tightening direction and hence tightens the fastener.
Patent TW-419743-B (TW)
Title: RF plasma etch reactor with internal inductive coil antenna and electrically conductive chamber walls
Inventor: YE YAN
IPC: H01J37/32
Filed: 1998-06-24
Granted: 2001-01-21
Abstract: An RF plasma etch reactor having an etch chamber with electrically conductive walls and a protective layer forming the portion of the walls facing the interior of the chamber. The protective layer prevents sputtering of material from the chamber walls by a plasma formed within the chamber. The etch reactor also has an inductive coil antenna disposed within the etch chamber which is used to generate the plasma by inductive coupling. Like the chamber walls, the inductive coil antenna is constructed to prevent sputtering of the material making up the antenna by the plasma. The coil antenna can take on any configuration (e.g., location, shape, orientation) that is necessary to achieve a desired power deposition pattern within the chamber. Examples of potential coil antenna configurations for achieving the desired power deposition pattern include constructing the coil antenna with a unitary or a segmented structure. The segmented structure involves the use of at least two coil segments wherein each segment is electrically isolated from the other segments and connected to a separate RF power signal. The unitary coil antenna or each of the coil segments can have a planar shape, a cylindrical shape, a truncated conical shape, a dome shape, or any combination thereof. The conductive walls are electrically grounded to serve as an electrical ground (i.e., anode) for a workpiece-supporting pedestal which is connected to a source of RF power to create a bias voltage at the surface of the workpiece.
Patent TW-464829-B (TW)
Title: Ballistic effect data selection method, intended to be implemented in electronic devices, in particular in electronic timepieces
Inventor: GUANTER JEAN-CHARLES
IPC: G04G21/00
Filed: 1998-07-08
Granted: 2001-11-21
Abstract: The present invention concerns a method for selecting at least one item of data from a set of data regrouped in accordance with a predetermined order. This method is able to be implemented in an electronic device including means for displaying the selected item of data, input means for supplying, via the action of a user of the device, a direction and successive pulses, means for controlling the display means in a non-instantaneous manner, and a processing unit for the set of data. This method is characterised in that it includes a first step which consists in counting the number of pulses provided, via the action of the user, during the period of time in which said display means is being activated to reach said selected item of data, in order to determine the acceleration provided by said user to said input means during this period of time.
Patent TW-546151-B (TW)
Title: Aqueous liquid pharmaceutical composition containing as main component benzopyran derivative
Inventor: YASUEDA SHINICHI
IPC: A61K47/32
Filed: 1998-07-10
Granted: 2003-08-11
Abstract: In order to promote solubilization or suspension of 4-oxo-8-[4-(4-phenylbutoxy)benzoylamino]-2-(tetrazol-5-yl)-4H-1-benzopyran or its hydrate (pranlukast) in water, at least one component selected from surfactants, water-soluble cellulose derivatives and water-soluble vinyl polymers is formulated together with pranlukast. Thus, it is possible to provide an aqueous liquid pharmaceutical composition containing higher concentration of pranlukast and having good properties.
Patent TW-394925-B (TW)
Title: A vocoder-based voice recognizer
Inventor: HERSHKOVITS YEHUDAH
IPC: G10L15/30
Filed: 1998-07-13
Granted: 2000-06-21
Abstract: A vocoder based voice recognizer recognizes a spoken word using linear prediction coding (LPC) based vocoder data without completely reconstructing the voice data. The recognizer generates at least one energy estimate per frame of the vocoder data and searches for word boundaries in the vocoder data using the associated energy estimates. If a word is found, the LPC word parameters are extracted from the vocoder data associated with the word and recognition features are calculated from the extracted LPC word parameters. Finally, the recognition features are matched with previously stored recognition features of other words, thereby recognizing the spoken word.
Patent TW-402747-B (TW)
Title: Method and apparatus for minimizing dopant outdiffusion in gate structures
Inventor: LOH STEPHEN K
IPC: H01L27/088
Filed: 1998-08-18
Granted: 2000-08-21
Abstract: Methods and apparatus for to methods and apparatus for fabricating gate structures, which include barrier layers, within an integrated circuit are disclosed. According to one aspect of the present invention, a method for minimizing dopant outdiffusion within an integrated circuit involves forming a gate oxide 208 layer over a substrate 206, and forming a layered silicon structure 210 over the gate oxide layer. A silicide layer 214 is formed atop the layered silicon structure. In one embodiment, forming a layered silicon structure includes depositing a first doped silicon layer over the gate oxide layer, forming a first oxide layer over the first silicon layer, nitridizing the first oxide layer, and etching the nitridized first oxide layer to expose nitride at a grain boundaries of the first silicon layer. A second silicon layer may then be deposited over the nitride exposed at the grain boundaries of the first silicon layer. In such an embodiment, nitridizing the first oxide layer causes nitrogen to be diffused into at least a portion of the first doped silicon layer.
Patent TW-441109-B (TW)
Title: Low voltage flash memory cell and method of making
Inventor: WANG LIN-SUNG
IPC: H01L27/115
Filed: 1998-11-02
Granted: 2001-06-16
Abstract: A low voltage flash memory cell formed in a semiconductor substrate. The memory cell comprises: two adjacent trenches formed in the substrate; a thick oxide layer over the substrate and in the two trenches, the thick oxide layer also having a thin tunnel oxide portion over the substrate between the two trenches; a floating gate formed over the thick oxide layer and substantially conforming to the shape of the two adjacent trenches; an interpoly dielectric formed over the floating gate; and a control gate formed over the interpoly dielectric.
Patent TW-428051-B (TW)
Title: Electric feeding method and apparatus for a continuous plating apparatus
Inventor: OHBA KAZUO
IPC: C25D21/00
Filed: 1998-12-01
Granted: 2001-04-01
Abstract: To avoid the formation of an extra amount of plate sticking on electric supply rollers, there is provided a continuous plating apparatus in which a planar article to be plated is clamped on both sides by electric supply rollers (19, 20, 21 and 22) and the article to be plated is moved horizontally in a plating bath by the rotation of the electric supply rollers (19, 20, 21 and 22) to plate both surfaces of the article to be plated, characterized in that the electric supply rollers (19, 20, 21 and 22) are divided into segments in the circumferential direction by electric insulators (19b, 20b, 21b and 22b) and only the segments of the electric supply rollers (19, 20, 21 and 22) in contact with the article to be plated are charged.
Patent TW-521996-B (TW)
Title: Process for making granular L-lysine feed supplement
Inventor: STEVENS JOSEPH MICHAEL
IPC: A23K1/16
Filed: 1999-01-11
Granted: 2003-03-01
Abstract: A process produces an L-Lysine feed supplement with a final L-Lysine purity in the range theoretically between about 35% and 80%, measured as a percent of freebase per kg, and more preferably between about 50% and 80% L-Lysine. The process comprises adding a material containing L-Lysine to an L-Lysine fermentation broth or a fraction of an L-Lysine fermentation broth. The added material being an amount which brings a final L-Lysine feed supplement with an L-Lysine purity into a range theoretically between about 35% and 80%, measured as a percent of freebase per kg, and more preferably between about 50% and 80% L-Lysine. The fraction of L-Lysine fermentation broth is obtained by any suitable separating means such as ultrafiltration or centrifugation. The process also comprises a drying step that may involve any suitable drying means such as a spray granulator, spray dryer, tray dryer, drum dryer, rotary dryer, and tunnel dryer.
Patent TW-397918-B (TW)
Title: Electronic apparatus comprising fingerprint sensing devices
Inventor: HARKIN GERARD FRANCIS
IPC: G07C9/00
Filed: 1998-12-14
Granted: 2000-07-11
Abstract: An electronic apparatus comprising a fingerprint sensing device (10) having an array of sensing elements (12) carried on a transparent substrate (35) for sensing capacitively the ridge pattern of a fingerprint placed over the array, in which the transparency of the device is utilised to provide additional capabilities. Thus, an optical sensing device (60) may be disposed beneath the device (10) to sense optically through the device a further biometric characteristic, or the presence, of the finger overlying the sensing element array. Substantial transparency can be afforded to the device by forming the sense electrodes (30) of the array from transparent conductive material. In products like mobile telephones, notebook computers, PDAs, smart cards or like portable electronic products of small size such as fingerprint sensing device can then advantageously be arranged overlying a display device with the display output being visible through the device.
Patent TW-498187-B (TW)
Title: Method and apparatus for limiting processor clock frequency
Inventor: WILSON JAMES A
IPC: G06F1/08
Filed: 1998-12-15
Granted: 2002-08-11
Abstract: A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.
Patent TW-533356-B (TW)
Title: ROM data output circuit
Inventor: YUSA TERUKAZU
IPC: G06F13/28
Filed: 1998-12-19
Granted: 2003-05-21
Abstract: In the present invention, a ROM data verification circuit is proposed to solve the problem of having testing-time increase for data inside the ROM due to the amount of data reading each time from ROM being too small. According to the present invention, a DMAC 2 directly reads out data written in the ROM 1 when a CPU 3 abandons the authority of using an address bus 5 and a data bus 6. Additionally, the read data is divided into a plurality of divided data such that each divided data is outputted to plural output ports 4 based on the application of the address generated by DMAC2.
Patent TW-495852-B (TW)
Title: Forming method of MOSFET with recessed self-aligned metal silicide contact and extended source/drain junction
Inventor: WU SHIE-LIN
IPC: H01L21/28
Filed: 1999-03-18
Granted: 2002-07-21
Abstract: A manufacturing method of MOSFET is disclosed in the present invention and can contain the following steps. At first, isolation region is formed on the substrate and the gate insulation layer is formed. The first conducting layer is formed on the gate insulation layer, and the first dielectric layer is formed. Part of the first dielectric layer, the first conducting layer, and the gate insulation layer is removed in order to define a gate structure. Then, the first thermal oxide layer is formed on the substrate and the sidewall of the first conducting layer. The first spacer is formed on the sidewall of the gate structure. After that, the first thermal oxide layer that is not covered by the first spacer is removed; and the second thermal oxide layer is formed on the exposed region of the substrate. The first dielectric layer and the first spacer are removed. Ion implantation is performed inside the first thermal oxide layer on the substrate surface. The second spacer is then formed on the sidewall of the gate structure. The second thermal oxide layer is stripped; and the first metal layer is formed on the substrate. Ion implantations for the source/drain/gate, respectively, are conducted. After that, thermal process is conducted in order to make the first metal layer located on the recess region and on the first conductor layer react to form a metal silicide layer. In addition, ions in the first thermal oxide layer are driven to substrate so as to form the extended source/drain junction. The part of the first metal layer that is not reacted is removed.
Patent TW-480292-B (TW)
Title: Palladium surface coatings suitable for wirebonding and process for forming palladium surface coatings
Inventor: ABYS JOSEPH ANTHONY
IPC: C25D3/52
Filed: 1999-05-06
Granted: 2002-03-21
Abstract: A surface finish which provides improved wirebonding performance for integrated circuit packages is disclosed. The surface finish which is formed on a substrate includes a palladium layer and one or more material layers. The one or more material layers are interposed between the substrate and the palladium layer. The palladium layer has a hardness that is less than about 500 (KHN50) while at least one material layer has a hardness that is less than about 250 (KHN50).
Patent TW-552334-B (TW)
Title: Manufacturing process for leather-like sheet
Inventor: ADACHI HIDEAKI
IPC: D06N3/14
Filed: 1999-06-17
Granted: 2003-09-11
Abstract: In a process for making a leather-like sheet by impregnating a fibrous substrate with a polyurethane emulsion, heat gellable polyurethane emulsion having a specific modulus of elasticity is employed as the polyurethane emulsion, and either of following methods (1) and (2) is also employed: (1) before impregnation of the polyurethane emulsion, the fibrous substrates are pretreated with a surfactant having a function of inhibiting adhesion between fibers and polyurethane, (2) in addition to the above modulus of elasticity, the polyurethane emulsion has a specific alpha dispersion temperature, the fibrous substrates are composed of microfine fiber-forming fibers, and after coagulation of polyurethane emulsion, the fibers are converted to microfine fibers. The leather-like sheets obtained according to this invention exhibits natural leather-like softness and hand touchness as well as excellent physical properties such as bending fatigue resistance.
Patent TW-476057-B (TW)
Title: Driving device and driving method of liquid crystal display device
Inventor: NAKAMURA TOSHIHIRO
IPC: G09G3/36
Filed: 1999-07-05
Granted: 2002-02-11
Abstract: A driving device of a liquid crystal display device includes a liquid crystal panel which is provided with a group of segment electrodes and a group of common electrodes and a group of common electrodes disposed to intersect with the group of segment electrodes and a liquid crystal sandwiched therebetween. The driving device includes a controller which controls a changing period for changing an output level of a segment driving signal which drives the group of segment electrodes in a single scanning period, within a voltage level which is the same polarity with respect to a common driving output which drives the group of common electrodes. The driving device corrects a driving voltage error generated by a change in display data and alternating signal by controlling the changing period. As a result, the driving device improves the display quality of the liquid crystal panel.