Patent SG-11201407952S-A (SG)
Title: Wafer level integrated circuit contactor and method of construction
Inventor: EDWARDS JATHAN
IPC: G01R1/067
Filed: 2013-06-19
Abstract: (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 27 December 2013 (27.12.2013) WIPOIPCT (10) International Publication Number WO 2013/192322 A2 (51) International Patent Classification: G01R 1/073 (2006.01) G01R 3/00 (2006.01) (21) International Application Number: PCT/US2013/046604 (22) International Filing Date: 19 June 2013 (19.06.2013) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 61/662,124 20 June 2012 (20.06.2012) US 61/760,928 5 February 2013 (05.02.2013) US (71) Applicant (for all designated States except US): JOHN- STECH INTERNATIONAL CORPORATION [US/US]; 1210 New Brighton Boulevard, Minneapolis, MN 55413 (US). (72) Inventors; and (71) Applicants (for US only): EDWARDS, Jathan [US/US]; 4210 Neal Ave. S„ Afton, MN 55001 (US). MARKS, Charles [US/US]; 614 Taylor St. Ne, Minneapolis, MN 55413 (US). HALVORSON, Brian [US/US]; 121 King Street West, St. Paul, MN 55107 (US). (74) Agents: LASKY, Michael, B. et al.; Altera Law Group, LLC, 120 South 6th Street, Suite 1700, Minneapolis, MN 55402 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, [Continued on next page] (54) Title: WAFER LEVEL INTEGRATED CIRCUIT CONTACTOR AND METHOD OF CONSTRUCTION •If! (57) Abstract: A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are con­ figured to slide relatively to each other and are held in elec­ trically biased contact by an elastomer (80). The elastomer is precompressed from its natural rest state between top a (22) plate and bottom a (70). Pre compression improves the resili­ ent response of the pins. The pin crows (40) are maintained relatively coplanar by the engagement of at least one flang (44a-b) against an up-stop surface 90 of plate 20, thereby in­ suring coplanarity of the crowns. The pin guide (12) is main­ tained in alignment with the retainer 14 by establishing a re­ gistration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner. WO 2013/192322 A2 I lllll llllllll II llllll III lllll lllll lllll III III III lllll lllll lllll lllll llll llll lllllll llll llll TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, Published: EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). — without international search report and to be republished upon receipt of that report (Rule 48.2(g))