baber/WOPTO huggingface dataset:
Patent JP-H10143498-A (JP)
Title: Page dividing communication repeater having link applying function
Inventor: UNNO MIKIHIRO
IPC: G06F17/21
Filed: 1996-11-08
Abstract: PROBLEM TO BE SOLVED: To provide a communication repeater having page dividing function with which the load of communication can be reduced in an organization having a repeating server. SOLUTION: When an extended URL adding a designated page number or a fragment to a URL is inputted from a browser, this is converted to a URL by a URL converting means 12 and outputted to the repeating server, and this designated page number of fragment is stored in a browser input information storage means 14 together with the URL. Then, text data.inputted from the repeating server corresponding to this URL are divided for the unit of a page corresponding to this designated page number or fragment by a page dividing means 16 and outputted to the browser while applying link for moving from one page to any arbitrary page through a page moving link applying means 18.
Patent JP-H03156634-A (JP)
Title: Logic output circuit for flexible disk device
Inventor: KOITABASHI YOSHIO
IPC: G11B19/02
Filed: 1989-11-15
Abstract: PURPOSE:To reduce the cost and to simplify the change of the circuit constitution by providing a NAND gate which inputs two logic inputs and a transistor which takes the logic output out of a collector. CONSTITUTION:A NAND gate 1 is provided to input a logic input A and a logic input B together with a power terminal 2, a resistance 3 connected to the terminal 2, and a transistor 4. The emitter of the transistor 4 is connected to the output of the gate 1, and the base of the transistor 4 is connected to a logic input C and the resistance 3. Then a logic output D is taken out of the collector of the transistor 4. Thus a logic output circuit is easily obtained just with addition of a resistance and a transistor even when the change of the circuit constitution is needed and another logic input is required. As a result, the change of the circuit constitution is simplified and at the same time the cost of the circuit is reduced.
Patent JP-H03156973-A (JP)
Title: Manufacture of semiconductor switching device
Inventor: HACHIMAN AKIHIRO
IPC: H01L21/22
Filed: 1989-11-15
Abstract: PURPOSE:To improve lifetime uniformity, prevent degradation of the device at high-current operation, and reduce reverse current by specifying a range from the wafer surface for the maximum concentration of doped precious metal in semiconductor and a range for a dose of doping. CONSTITUTION:A p-type base layer 12, a p-type emitter layer 14, and an n-type emitter 11 are formed on a wafer by diffusion of acceptor and donor. The wafer is placed in an ion implantation device to introduce Au ions to the p-type emitter. The maximum concentration Rp of Au ions should be within a 0.05-0.1mum range from the wafer surface. The dose should be within a range of 5X10<10> to 5X10<12>.d.cm<-2>, where d is the wafer thickness in mum. With Rp in the specified range, it is possible to prevent impurity diffusion to the outside and the occurrence of crystal defects due to annealing. In addition, with the dose in the specified range, the lifetime killer concentration after annealing is controlled within an appropriate range. It is thus possible to improve lifetime uniformity, prevent degradation of the device at high-current operation, and reduce reverse current.
Patent JP-H05134018-A (JP)
Title: Fault simulation method
Inventor: AMANO YOSHINOBU
IPC: G01R31/3183
Filed: 1991-11-13
Abstract: PURPOSE:To enable a highly reliable test to be performed by reducing a test time and then eliminating scattering of a confirmation result and omission of execution. CONSTITUTION:A fault simulation test mode is set to a fault simulation test mode register 4 manually and a fault simulation start register 6 receives a set data. A microprogram group storage part 10 for fault simulation stores a microporgram group for fault simulation for performing fault simulation. A microporgram address generation circuit part 8 for fault simulation generates a start address based on a data of the simulation test mode and a microporgram storage register 12 reads the microporgram for fault simulation out of the microprogram group storage part 10 for fault simulation for storage. A data generation circuit part 14 for fault simulation generates a data for fault simulation while it is controlled by the microprogram for fault simulation which is stored. A fault simulation storage part 22 performs fault simulation of the register based on the data for fault simulation and then stores the fault simulation result.
Patent JP-H08152799-A (JP)
Title: Fixing heat roller
Inventor: MARUYAMA TAKAHIRO
IPC: H05B3/00
Filed: 1994-11-30
Abstract: PURPOSE: To produce a fixing heat roller in good yield by providing a heating resistor layer of the mixture of glass and conductive material on an insulating layer consisting of an org. resin and specifying the ratio of the centerline average roughness to the maximum depth of the surface. CONSTITUTION: A heating resistor layer 4 is provided on the outer peripheral surface of a metallic pipe 2 of aluminum, etc., having 0.5-1mm wall thickness through an insulating layer 3 consisting of an org. resin such as polyimide, a releasable layer 5 is formed on the outermost surface, and an annular electrode 6 is fixed to both ends of the resistor layer 4 to constitute the roller. The resistor layer 4 consists of the mixture of crystallized glass having <=500 deg.C softening point and a metallic material such as Ag or a conductive material of the oxide such as Re2 O3 , and the thickness is controlled to 5-100μm. Further, the centerline average roughness Ra and maximum depth Rmax* on the layer 4 surface are limited to conform to Ra/Rmax*<0.5.  Consequently, the gas generated in the pore is liberated from the pore in the layer 4, and the adhesion of the releasable layer is enhanced.
Patent JP-H07127884-A (JP)
Title: Cooling/heating device utilizing radiant heat
Inventor: HAGIWARA OKINARI
IPC: F24F5/00
Filed: 1993-11-02
Abstract: PURPOSE:To use a panel body generating radiant heat and mount the panel body on a ceiling-plane without utilizing an indoor wall face. CONSTITUTION:A plurality of radiant panels 2, 2, each having therein a water conduct path, are disposed in a state of a substantially V-shaped sectional shape to form a radiant panel main body 1 while forming a gap extending in the longitudinal direction of the lower end of the radiant panel main body, and a gutter 3 is mounted to the radiant panel main body 1 so as to cover the gap from below. The radiant panel main body 1 is mounted on a ceiling- plane 11, and the gutter 3 is formed in a slant state in its longitudinal direction. Further, a water circulation mechanism 5 is connectively provided to the radiant panel main body 1 so that cold water or hot water can be freely fed and returned through the water conduct paths of the radiant panels 2, 2, and cooling or heating is performed by radiant heat of each radiant panel 2.
Patent JP-H04170246-A (JP)
Title: Sound volume control circuit for on-vehicle telephone set
Inventor: YAMADA TAKAO
IPC: H04B7/26
Filed: 1990-11-02
Abstract: PURPOSE:To attain talking with a clear voice signal without howling by setting a gain of a transmission reception system for each country even when an inter- line coupling between the transmission system and the reception system differs from each country in the case of talking in the hand-free mode. CONSTITUTION:A transmission system (reception system) of a hand-free cradle 3A is provided respectively with an amplifier circuit 33A(35A) whose amplification factor is set by an external amplification factor control signal and the cradle 3A is provided with a control circuit 45 receiving a country name signal entered from a handset 5, generating the amplification factor control signal setting an amplification factor in response to the country name and giving the signal to the amplifier circuits 33A,35A. That is, since the coupling between the lines of the transmission system and the reception system differs from each country, the amplification factor of the amplifier circuits 33A,35A is set so as to be optimum to a line level of each country even when the talking line level is different. Thus, the talking with a clear sound signal without howling is attained.
Patent JP-H01143742-A (JP)
Title: Mold for continuous casting
Inventor: OKIMOTO KAZUO
IPC: B22D11/055
Filed: 1987-11-27
Abstract: PURPOSE:To uniformize the solidified shell and to prevent the development of breakout by parallel arranging plural water cooling zone to longitudinal direction of a mold wall and setting cooling rate at the part of the mold wall corresponding to the each cooling zone, respectively. CONSTITUTION:The mold body having cylindrical mold wall 11 is formed and the water cooling zones 21, 22 are arranged at upper and lower parts with plural water boxes 20 at outer side of the mold wall 11. In the water cooling zones 21, 22, cooling water passages 23, 24 are arranged, and the zone 21 is set at above the meniscus part of molten metal and the zone 22 is set below the meniscus part. The water cooling zone 21 sets at slowly cooling condition to prevent rapid cooling and uneven thickness of the solidified shell. In the water cooling zone 22, the cooling condition to be possible to relatively rapid- cool is set to develop the solidified shell and prevent raising of molten metal temp. As the suitable water cooling condition is set at each water cooling zone and the mold wall 11 is cooled, the solidified shell is uniformized and the breakout caused by longitudinal crack is prevented.
Patent JP-H07152726-A (JP)
Title: Modified cholesky decomposition calculating device
Inventor: YOROZU JUNICHI
IPC: G06F17/16
Filed: 1993-11-29
Abstract: PURPOSE:To improve the calculation speed of a modified cholesky decomposition calculating device by blocking processing based upon optimum block size. CONSTITUTION:This execution example is constituted of an input device 1 such as a keyboard, a data processor 2 to be driven by program control, a storage device 3 for storing data and an output device 4 such as a display. The data processor 2 is provided with a block size determining means 21 and a modified cholesky decomposition calculating means 22. The storage device 3 is provided with a block size determining data storing part 31 and a matrix storing part 32. The storing part 31 previously stores data indicating which block size enables the execution of modified cholesky decomposition at the fastest speed corresponding to the order N of several matrixes. The storing part 31 stores a matrix A to be decomposed immediately after the start of operation but updates the stored contents in accordance with the operation of the processor 2.
Patent JP-H03157927-A (JP)
Title: Drying process of semiconductor wafer
Inventor: WASHITANI AKIHIRO
IPC: H01L21/304
Filed: 1989-11-15
Abstract: PURPOSE:To avoid the wafer pollution for increasing the yield by a method wherein pure water in liquid soluble oxygen concentration not exceeding a specific value is sprayed over the pattern formation surface of a cleaned up semiconductor wafer and then heated and dried up in an inert gas atmosphere. CONSTITUTION:A cleaned up semiconductor wafer 32 is held on a holder 30 in a sealed up vessel 21. Next, an inert gas feeding valve 44 is opened to feed inert gas so that the pressure in the vessel 2 may be increased a little higher than the atmospheric air pressure. Later, a pure water feeding valve 41 is opened to spray super pure water of a dissolved oxygen concentration not exceeding 0.6ppm over a pattern formation surface of the wafer 32 from a spray nozzle 36 so that the super pure water may be substituted for the water content adhered to the wafer 32 in the cleaning process. Next, the valve 41 is closed and an exhausting valve 42 is opened to drain off the super pure water in the vessel 21 and then the valves 42, 44 are closed and a vacuumizing valve 43 is opened to depressurize the vessel 21. Finally, the wafer 32 is heated by an infrared ray lamps 35 to vaporize the water content on the pattern formation surface. Through these procedures, the wafer pollution can be avoided and the yield increased.
Patent JP-H01138808-A (JP)
Title: Voltage comparator circuit
Inventor: TSUJI KAZUHIRO
IPC: H03K5/08
Filed: 1987-11-26
Abstract: PURPOSE:To attain the voltage comparison between a holding signal and a reference signal is excellent way by bringing an output of a 1st capacitor to a low impedance state and holding an input signal from a 2nd switch circuit with high accuracy. CONSTITUTION:With switch circuits SW2, SW3 and SW4 turned on, since the output terminal of the capacitor C1 is in a low impedance because a constant voltage source 3 is connected thereto, even if an input signal Vin2 sampled by the circuit SW2 is a high frequency signal, it is held in the capacitor C1 with high accuracy. A potential difference between a potential at other terminal of the capacitor C1 and that at an operating point of an inverted amplifier circuit 2 is charged in the capacitor C2. Then the switch circuits SW2, SW3 and SW4 are turned off and the input signal Vin1 being a reference of voltage comparison is sampled, then the circuit SW1 is turned on and a potential being the sum of the signals Vin1 and Vin2 to the potential at the operating point of the circuit 2 appears at the input terminal of the circuit 2. Thus, a potential being the amplification of the potential difference between the signals Vin1 and Vin2 is obtained at the output terminal of the circuit 2 and then excellent voltage comparison is applied.
Patent JP-H01138567-A (JP)
Title: Recopying preventive transfer paper and its manufacture
Inventor: KOMATA HIROTSUGU
IPC: G03G21/00
Filed: 1987-11-26
Abstract: PURPOSE:To form a sharp copy image and to prevent the image from being copied again by insulating metal vapor-deposited layers which is laminated on one surface an insulating base material so as to make the one surface into a specular surface in a specific direction at specific intervals. CONSTITUTION:This paper consists of the film or sheet type insulating base material 10 and metal vapor-deposited layers 20 laminated on one surface of the base material 10 so as to make the one surface into the specular surface. The base material 10 is rectangular in plane vision and uses a transparent film such as a polyester film and a polypropylene film. The metal vapor- deposited layers 20 are separated and insulated at specific intervals in parallel to the respective sides, and the insulation intervals are of specific length. This length is set shorter than the arrangement interval between a transfer device which uses the corona charger of an electrophotographic copying machine and a separating device which uses an AC corona charger. Consequently, the sharp copy image can be formed and prevented from being copied again.
Patent JP-S62156554-A (JP)
Title: Concentration measuring instrument
Inventor: KATAYAMA HIDEO
IPC: G01N27/416
Filed: 1985-12-27
Abstract: PURPOSE:To improve the accuracy of measurement by providing an enzyme electrode in which the enzyme of the immobilized enzyme membrane in the position corresponding to the 1st cathode is deactivated and peak detecting means which detects the peak value of the signal from a differentiating means. CONSTITUTION:The enzyme in the immobilized enzyme membrane 9 existing in the position corresponding to the 1st platinum cathode 4 is deactivated by means such as, for example, heating or irradiation of laser light or UV rays and the enzyme reaction does not arise in the deactivated enzyme part 10 of the immobilized enzyme membrane 9. The output currents from a reference electrode and measuring electrode are respectively inputted to the differentiating means 15 by which the currents are converted to the first or second differential value thereof. The min. value thereof is determined by a peak detecting means 16. The resultant min. differential value is recorded in a recorder 17 and is compared with the calibration curve preliminarily formed from the difference between both, by which the concn. of the material to be detected in the sample liquid is calculated.
Patent JP-H11135017-A (JP)
Title: Plasma display panel
Inventor: KAWAMURA HIROYUKI
IPC: H01J11/42
Filed: 1997-10-30
Abstract: PROBLEM TO BE SOLVED: To provide a plasma display panel manufacturing method capable of forming a phosphor layer at a low cost and with good precision in the plasma display panel. SOLUTION: Barrier ribs 21 are provided on one of an electrode and dielectric glass layer-provided front glass substrate for a front glass cover plate or an electrode and phosphor layer-provided back face glass substrate 20 for a back plate, the respective electrode faces are faced mutually with a predetermined gap and are selected, and a dischargeable gas medium is sealed inside so as to form a plasma display panel. In the case of the formation of the phosphor layer in the barrier ribs 21, one of a phosphor ink sealing means provided at one part of the barrier ribs 21 or a shutoff means for phosphor ink discharged from an ink nozzle is disposed, and after the phosphor ink is applied into the barrier ribs as discharging the same from the ink nozzle, the phosphor layer is burnt.
Patent JP-H01137839-A (JP)
Title: Transmission line error supervising circuit
Inventor: SAITO SHIGEAKI
IPC: H04J3/14
Filed: 1987-11-25
Abstract: PURPOSE:To locate a fault in all of low-order PCM signals by providing plural error detection circuits receiving respectively all the low-order PCM signals, an OR circuit adding the outputs, a frequency division circuit frequency-dividing the output of the OR circuit depending on the number of signals without out of synchronization, a selection circuit and a calculation circuit. CONSTITUTION:An error is detected by error detection circuits 11, 12 from each low-order PCM signal and given to an OR circuit 4 with gate circuits 31, 32 opened when no out of synchronization is detected by out of synchronization detecting circuits 21, 22. The erroneous circuits are added by the OR circuit 4, the value subject to frequency division by the number of systems without out of synchronization is counted by a counter circuit 8 via a selection circuit 7 to output number of errors by one system of the signal. Since error is supervised by using only one signal among plural low-order signals to be multiplexed, if an error takes place onto other signal due to a fault, the repeater is located.
Patent JP-H01140098-A (JP)
Title: Glassification device for radioactive waste liquid
Inventor: TORADA SHINICHIROU
IPC: G21F9/36
Filed: 1987-11-26
Abstract: PURPOSE:To take out it if necessary while treating high level radioactive waste liquid into glass solid to store by providing a glass melting furnace, a cullet producing means, a storing vessel, a cullet conveying means and a taking-out pipe. CONSTITUTION:In a glass melting furnace 1 high level radioactive waste liquid and glass raw material supplied from the upper part of a furnace body are heated by electrodes 9 and melted glass 2 is taken out from the lower part of the furnace body. A cullet producing means 3 is composed of a cooling water vessel 10 and a screw conveyor 11, and glass solid cullet 4 which is produced by descending and cooling melting glass in the vessel 10 is taken out by the conveyor 11 from the vessel 10. A cullet conveying means 7 is composed of a hopper 14, a conveying pipe 16 and the like, and the cullet 4 is conveyed from the hopper 14 to a tank 15, and fed in each storing vessel 5 through a supply and taking-out pipe 18. An end of a taking-out pipe 8 is connected to a vacuum aspirator and the cullet 4 in the vessel 5 can be taken out through the pipe 18, the tank 15 and the taking-out pipe 8 with air sucked from a valve 21.
Patent JP-H08154680-A (JP)
Title: Method for predicting bone density
Inventor: EGUCHI HIROSHI
IPC: C12Q1/68
Filed: 1994-12-01
Abstract: PURPOSE: To predict the bone density and its future change by cleaving a specific site in a genomic DNA of a vitamin D receptor with a restriction enzyme ApaI or BsmI, determining the combination of the genotype in the cleaved site and connecting the combination with the bone density. CONSTITUTION: A site in an intron part between exon 8 and exon 9 of a genomic DNA of a vitamin D receptor is cleaved with a restriction enzyme ApaI or BsmI to combine genetic polymorphism AA, Aa or aa determined by the combination of a genotype A uncleavable with the ApaI and a genotype (a) cleavable with the ApaI with a genetic polymorphism BB, Bb or bb determined by the combination of a genotype B uncleavable with the BsmI and a genotype (b) cleavable with the BsmI. The resultant combination of the genotypes is connected with the level of the bone density to thereby predict the bone density or its future change. Thereby, the bone density can be prevented from reducing in the future by taking care of meals, nutrients and living habits to avoid the suffering from osteopathy such as osteoporosis.
Patent JP-H10143367-A (JP)
Title: Processor, and method for speculative command executing
Inventor: SHIGA REIKO
IPC: G06F9/38
Filed: 1996-11-11
Abstract: PROBLEM TO BE SOLVED: To enable speculative execution of following commands including plural move-to-count commands and branch-on-count commands by holding the data of the plural move-to-count commands in plural data holding circuits respectively. SOLUTION: A branch processing unit 4 selects a data line 130 as an input of a logic circuit A10 by a control line 107 and stores it in a shadow count register A11. Simultaneously, the branch processing unit 4 stores the data of the data line 130 in a data holding circuit A13 using a control line 112. A fixed decimal point operating unit 5 reports the completion of command and which data holding circuit of A13 or B23 is used to a command completion unit 40 via a control line 141. The command completion unit 40 completes the command to a count register 42 for holding a count value corresponding to a nonspeculative execution command by transferring the content of the data holding circuit A13 to a count register 42 via a data line 142 by a count register updating circuit 41.
Patent JP-H01140588-A (JP)
Title: High frequency heating device
Inventor: TAKANO AKIHISA
IPC: H05B6/66
Filed: 1987-11-26
Abstract: PURPOSE:To simplify the structure of a control part by supplying power to a relay coil from both of power supplied from the secondary side of a low voltage transformer through a diode and the output of a rectifier part. CONSTITUTION:The secondary side of a low voltage transformer 7 is connected with a relay coil 6 through a relay drive diode 10, and the connected point of the output of a rectifier part 8 with a smoothing capacitor is connected with the coil 6 through a resistance 11. At the time when the output voltage of the diode 10 becomes zero, a drive transistor 14 gets on, and if voltage is supplied to the coil 6, the voltage from the diode 10 is not supplied, while voltage is supplied through the resistance instead, though a relay contact cannot be put on. If a high voltage is supplied through the diode 10 by power phase, the relay contact is closed. Because energy to close the relay contact is supplied from the diode 10, it is necessarily closed at a synchronous timing to the power phase. Need of computation of charging phase at a control part 13 is thus eliminated.