Patent UA-103537-U (UA)
Title: Shaper periodic sequence of three pulse code series with programmable time parameters
Inventor: KOROBKOV MIKOLA GRIGOROVICH
IPC: H03K3/78
Filed: 2015-05-22
Abstract: Shaper periodic sequence of three pulse code series with programmable time parameters, comprising: two reversible binary counters, each of which has an input supply pulse synchronization input adjustment on mode summation / subtraction, entry permit regime counting, entry permit simultaneous parallel downloads and inputs supply data entry asynchronous installation in zero state, the output overflow; inverter; the first and second elements OR; chain consisting of series connected resistor and capacitor; synchronous D-flip-flop with asynchronous input settings in the zero state, the first and second elements double-thread And while the common point of series connected resistor and capacitor connected to the information input of D-flip-flop, with one input of the first and second double-thread item I; double-thread output of the first element is connected to the input of asynchronous installation D-flip-flop in the zero state; a second input of the second element is connected to the output of the first OR element, one of the inputs is connected to the output of D-flip-flop; the output of the first counter overflows, which forms the generator output connected to the input mode permits counting of the second counter, a second input of the first element OR, the first input of the second element OR and inverter input, the output of which is connected to the input mode permits counting of the first counter; second counter overflow output connected to the input mode permits loading a second counter and a second input of the second OR element; inputs parallel data loading first counter inputs form programming on a given generator pulse duration; inputs parallel data loading form a second counter inputs shaper programming on a given length of the pause between pulses; the output of the second element is connected to the input of asynchronous installation of meters in zero condition; clock inputs of the first and second counters are interconnected, creating shaper input - input supply continuous periodic sequence of pulses output from the external oscillator; clock input of D-trigger input supply creates impulses run; the second input of the first element and provides input supply pulses stop forming pulse output, where introduced: the cyclical device (three meter) made two JK-flip-flops, the first of which has two inputs J, one of which is direct, the other inverted, at 'and by united, one inverted input K and asynchronous input settings in the zero state, the second JK-flip-flop has two inputs K, each of which is straight, the other inverted, united in and one inverted J input and asynchronous input settings from zero state; while inverted output of the first JK-flip-flop is connected to the direct input of the second JK-K flip-flop; inverted output of the second JK-flip-flop is connected to the direct input J of the first JK-flip-flop; first, second, third, fourth, fifth and sixth drivers Z-state (high impedance) output, each with inverse input exit permit; outputs of the same name first, second and third drivers combined with appropriate inputs parallel data loading the first counter, and the data inputs form the inputs of the first driver on the same programming shaper duration of the first pulse in the code series at the output of the shaper, inputs data inputs form the second driver programming shaper a specified duration of the second pulse in the code series at the output of the shaper, inputs data inputs form a third driver programming on a given generator pulse duration of the third series of the code in the output of the shaper; same name exits fourth, fifth and sixth drivers combined with the corresponding inputs of the second parallel data download counter, while the fourth driver inputs form the inputs to a given programming shaper duration of the first series of breaks in the code generator to output, inputs data form the fifth driver programming generator inputs on a given length of the second series of breaks in the code generator to output, inputs data form the sixth driver inputs shaper programming on a given length of the pause between series of pulses; first, second and third double-thread NAND element, with the inputs of the first NAND element is connected to an inverted output of the first and second JK-triggers inputs of the second NAND element is connected to direct the first and second JK-flip-flops , the inputs of the third NAND element is connected to an inverted output of the first JK-trigger and direct the second JK-flip-flop; the output of the first NAND element is connected to the inverse inputs permit release of the first and fourth drivers; the output of the second NAND element is connected to the inverse inputs permit the release of the second and fifth drivers; the output of the third NAND element is connected to the inverse inputs permit the release of the third and sixth drivers; inverted inputs JK-flipflops connected to the output of the second OR element; direct access to the second JK-flip-flop is connected to a third input of the first OR element; JK-clock inputs of flip-flops is connected to the input shaper; asynchronous inputs settings in the zero state JK-flipflops connected to the output of the second element I.