Patent GB-819579-A (GB)
Title: Improvements in or relating to electronic calculating apparatus
Inventor: TRUSSELL ALEC
IPC: G06F7/552
Filed: 1955-12-28
Abstract: 819,579. Digital-electric-calculating apparatus. INTERNATIONAL COMPUTERS & TABULATORS Ltd., [formerly BRITISH TABULATING MACHINE CO. Ltd.]. Dec. 13, 1956 [Dec. 28, 1955], No. 37107/55. Class 106 (1). The machine according to this invention is for determining square roots and uses the method of subtracting successive odd integers, i.e. 1, 3, 5, 7, 9 and so on. This method depends on the fact that these odd integers are the differences between successive squares 0, 1, 4, 9, 16, 25, &c., so that by repeatedly subtracting the odd integers in effect a test is made to determine which is the highest square that can be subtracted to leave a positive remainder, the number of subtractive steps giving the square root. Thus to determine the square root of 40 subtraction of odd integers gives in successive steps 39, 36, 31, 24, 15, 4. Since there are six steps the nearest square root is six leaving a remainder of four. In the normal method of working out square roots the digits of the number are paired off from the decimal point and a first quotient digit is chosen by trial and error such that it is the largest digit of which the square can be subtracted from the first pair of digits to leave a positive remainder. The next pair of digits is then brought down to form a new remainder and the first quotient digit is. doubled and moved one place to the left. A second quotient digit is then chosen such that when the sum of the shifted first digit and the second digit is multiplied by the second digit the smallest possible positive remainder is obtained. Further quotient digits are obtained by repeating this step. In this machine to avoid the necessity of choosing digits successive odd integers are subtracted until the remainder becomes negative, the last subtraction is cancelled by re-adding the number subtracted and the process repeated for each pair of digits. The answer is provided by the number of subtractive steps made in each stage. Thus in finding the square root of 53824 the digits are paired off as described above and successive odd integers are subtracted from the first pair (05) 5 - 1 = 4, 4 - 3 = 1. Since two subtractions have been made leaving a positive remainder the first digit is 2, this is doubled and moved to the left the odd integers being added to it in turn to form numbers 41, 43, 45, &c., which are subtracted from the next remainder which is 138 thus 138 - 41 = 97 ; 97 - 43 = 54 ; 54 - 45 = 9. Three subtractions give the next digit of the answer as three. The first two digits 23 are doubled and odd integers added to it as before to give 461, 463, &c., which numbers are subtracted in turn from the next remainder which is 924. Thus 924 - 461 = 463; 463 - 463 = 0, giving a last digit of two. The answer is therefore 232. In the machine according to the invention a result digit related to a pair of dividend (the number to be square-rooted) digits, is calculated in each of a plurality of major cycles, each major cycle including at least one subtractive cycle and the machine includes a two-input subtractor, detecting means operative when the subtractor produces a negative remainder, a counter counting subtraction cycles, means operable to apply to one input of the subtractor on each subtraction cycle unity plus twice the value registered in the counter plus twice the result digit or digits obtained in previous major cycles, shifted one place to the left, and means adapted upon operation of the detecting means to reset the counter to zero and initiate the next major cycle. The arithmetic unit shown in Fig. 1 comprises three ten-stage shifting register stores 1, 2, 3 each store being capable of holding a ten-digit binary coded decimal number, an adder 29 and a complementer 42, which is used for subtraction and various gates which control routing of the numbers within the circuit. Similar arithmetic units are described in Specifications 767,692 and 780,431. The number of which the square root is required is entered in store 2 through gate 21 with the lowest valued digit at the right-hand or exit end. The number is then shifted eight places to the right so that the digits originally in the two positions adjacent the left-hand end are located in the two right-hand positions. The other digits circulate through gate 23, round the loop provided and back into the store. The machine then carries out a major cycle which includes one or more subtraction operations in the first of which the two digits at the exit end of store 2 are fed out to form an initial remainder from which is subtracted the value registered in a quotient counter plus one. The result is entered into remainder store 3 and subsequent subtractions as before are made from this remainder. In the circuit of Fig. 1 this is achieved by opening gates 34 of store 2 for the first two of a series of shift pulses applied to the store via gate 28. Gates 23 are shut for these two shift pulses but open when gates 34 close. The first two digits therefore pass out on line 30 to the adder 29 and subsequent digits are circulated back into the store again through gates 23. Gates 49 are opened at the same time as gates 23 and shift pulses are applied via gates 52 and 59 so that the third and subsequent digits of store 3 are applied to the adder 29 via line 30. The quotient counter which forms part of the control unit counts the number of subtraction operations and provides a read-out value equal to twice that number. This is applied, with the added digit, to the line 31. The doubled number of subtractions is read into the result store 1 at the end of each major cycle. In subsequent cycles since it is displaced one stage to the left it is simultaneously applied to line 31 with the quotient counter read-out and the supplementary digit. For this purpose the gates 41 and 15 are opened so that shift pulses through gate 12 not only shift the value on to line 31 but recirculate it and cause it to be re-entered in the store. Line 31 passes through the complementing circuit 42 to the adder 29, the circuit 42 being made operative by a signal from the control unit on line A10 so that digits entering on line 31 are subtracted from those on line 30. The result is fed by line 32 to the remainder store 3. Line 599 connected to the highest stages of the 1 and 8 registers detects the presence of a nine in this denomination which would indicate a negative remainder. When this is detected further subtractions are prevented and the last number subtracted is added back by repeating the last operation with complementer ineffective to get the last positive remainder. During the add-back shift pulses applied to store 3 are effectively reduced by two so that the remainder is shifted two places upwards in significance and the last two digits of the negative remainder remain in the two right-hand stages of the store and are later lost. Two of the shift pulses applied to register 2 are suppressed so that the number therein is effectively shifted two places to the left to bring the next highest pair of digits into the two stages adjacent the exit end of the store. Twice the value registered by the quotient counter is then entered into the result store 1 via line 650 and the counter is reset to zero. In the next major cycle a new remainder is made by passing the old contents out on to line 30 followed by the next two digits of the original number from store 2. This remainder passes through the adder 29 and a value is subtracted from it which is the value in the result store (equal to twice the previous quotient count) plus twice the current quotients count plus one. The current quotient counter advances by one for each subtraction made so that twice the number registered plus one gives successive odd integers 1, 3, 5, 7, &c. Subtractions continue until the remainder in store 3 becomes negative, the last subtraction then being cancelled, twice the quotient count is added into the result store to give the next digit of the answer, the quotient counter is returned to zero and a new major cycle is begun. In this the new remainder is again formed by adding the next highest pair of digits to the old remainder and the new value to be subtracted is formed by adding to the value in the result store, shifted one place to the left, twice the quotient count and unity. Subtractions again continue until the remainder becomes zero. The process is repeated until the desired number of decimal places is obtained, a major cycle counter being provided which may be plugged to stop the process when sufficiently accurate answer is obtained. The value registered in store 1 is twice the result since twice the quotient count has been entered into it at each major cycle. To obtain the true square root this number is passed through a halving circuit 66. This could be avoided by using separate registers for the actual result digit read from the quotient counter and the doubled value required to form the odd number for subtraction. The various gates are opened and closed by a control circuit which distributes D.C. potentials to open the gates and pulse trains which are used to shift the numbers in the registers. Counters.-The quotient counter is a biquinary counter with four trigger stages valued 1, 2, 4 and 5. The input is through a gate which is controlled by the unset side of stage 4 and which is therefore open when the counter registers zero. An input pulse is therefore allowed to pass to stage 1 and sets it, the counter then registering units. Stages 1 and 2 and stages 2 and 4 are interconnected by gates so that these three stages operate in the normal binary manner each stage being set by the resetting of the stage before. After four pulses stage 4 is set which closes the input gate to prevent the next pulse from reaching stage 1 but opens another gate allowing it to set stage 5 and reset stage 4. The doubled read out is effected by connecting the stages 1, 2 and 4 to gates contro