Patent GB-1314267-A (GB)
Title: Semiconductor wafers and pllets
IPC: H01L21/78
Filed: 1970-05-04
Abstract: 1314267 Semi-conductor devices GENERAL ELECTRIC CO 4 May 1970 [5 May 1969] 21373/70 Heading H1K Plural semi-conductive assemblies formed in a single crystal wafer of, e.g. silicon (Fig. 3) comprise element 51 with spaced parallel major surfaces 52, 54 separated by N-type central zone 56; a first P-type zone 58 being interposed between zone 56 and major surface 52 to form junction, having central parallel portion 60a and peripheral portion 60b angularly extending toward the second major surface 54. A second P-type zone 62 separates the central zone from the second major surface and a third N<SP>+</SP> zone is interposed between the second major surface and a portion of the second zone to form junctions 66, 68. Grooves 70 inwardly spaced from the element edge extend inwardly from the second major surface to intersect the edges of junctions 60b, 66. A dielectric glass passivant 72 is inserted in the grooves to cover the exposed junction edges. An ohmic contact layer 74 is imposed on the first major surface, and similar layers 76, 78 are applied to the third and a portion of the second zone at the second major surface; the uncontacted portion of the surface being oxide coated at 80. In preparation the major surfaces may be, e.g. oxide masked and selectively etched along first and second sets of parallel intersecting corridors aligned on both major surfaces (Fig. 2, not shown) and P-type diffusant penetrates the wafer along the corridors to form edges 58b of the zone 58, after which the mask is removed and both major surfaces diffused to form central portion 58b of zone 58 and zone 62. Masking is reapplied, and removed for diffusion of zone 64 into the second major surface. Gallium arsenide may be used as diffusant. Masking is selectively removed from the second major surface to define the locations of the grooves which intersect in parallel sets (Fig. 4, not shown); plural exposed areas defining grooves being spaced apart by unexposed intersecting sheets. Exposure to etchant forms grooves 70 intersecting the edges of junctions 60b, 66. Passivant glass layers are inserted electrophoretically in the grooves, the masking is removed to permit deposition of contacts 74, 76, 78 and the individual assemblies are separated by sawing or scribing along the sheets separating the glass layers. The assembly is mounted on a sheet metal heat sink provided with a mounting tab and terminal lead and attached to the contact layer 74; other terminal leads being connected by fly wires to layers 76, 78, and the assembly and the mounting portion of the heat sink are encapsulated with silicone, phenol, or epoxy resin (Fig. 5, not shown). The heat sinks and terminals may initially be formed plurally on a single metal plate subdivided after mounting and connection and thereafter encapsulated. Layer 78 may be omitted for an avalanche thyristor. In a modification, (Fig. 6, not shown) a crystal has a central N or P type zone bounded by first and second N or P type zones of opposite conductivities setting up rectifying junctions with the central zone; bounded by a surrounding groove intersecting the portions and incorporating an overlying passivant layer with ohmic contact layers on the major surfaces overlying the first and second zones. A further modification (Fig. 7, not shown) similar to Fig. 3 has a differing shape of groove and boundary of zone 58. A gate controlled thyristor or triac (Figs. 8, 9) comprises a semi-conductor assembly 300 having spaced first and gate layers 302, 304 laterally spaced of like conductivity type forming portions with a second layer 306 of opposed conductivity type. A central layer 308 and emitter layer 312 are of types to layers 302, 304 and fourth layer 310 is of like type to layer 306 to provide a PNPN or NPNP sequence except for a 3 layer sequence at 306A. Contact layer 314 overlies area 316 of one major surface while contact layer 318 overlies the other major surface and a gate contact layer (not shown) overlies area 322 of gate layer 304 and area 324 of layer 306. A peripherally sloped edge intersects junctions 366, 360; the latter having central portion 360a and sloping peripheral portion 360b; a passivant layer 322 overlying the sloped edge and the junction intersections. Other passivants than glass may be employed.