Patent GB-1094870-A (GB)
Title: Radio navigation receiver
Inventor: FRANK ROBERT LEE
IPC: G01S1/24
Filed: 1966-09-16
Abstract: 1,094,870. Radio navigation. SPERRY RAND CORPORATION. Sept. 16, 1966, No. 41392/66. Heading H4D. The Specification describes a Loran C receiver in which means are provided to select in each received pulse the carrier cycle null most nearly coterminous with a prescribed point on the leading edge of the pulse. The position of said null in master and slave pulses is used as a basis for time difference measurements. Fig. 1, shows the section of the receiver receiving the master pulse signals. The received pulse, Figs. 2E, 2F, are fed directly or inverted, to an envelope deriver 4 wherein part of the pulse is delayed ¢ carrier cycle or 5Á sec and added to the original pulse. This produces waveforms as shown in Figs. 2A-2D wherein the position of the envelope null and phase reversal 9 is fixed with respect to the original envelope of the pulse, but the position of the carrier within the envelope may vary from pulse to pulse due to propogation anomolies etc. It is thus necessary to select corresponding carrier nulls 22 in consecutive received pulses and it is assumed that said nulls will be those nearest to said point corresponding to derived envelope null 9. Pulses at the loran p.r.p. are produced by a master divider chain 11 dividing down the output of a 100 Kc. oscillator 10, the time (phase) position of the pulses being altered by adding or subtracting pulses at the input of the divider chain. The pulses are fed to contact 17 of switch 19 and to contact 18 of said switch via two 2.5Á sec delays 15, 16. Alternative gating pulses are thus produced positioned - 2.5Á sec and + 2.5Á sec with respect to pulses extracted on line 21 from the output of delay 15. These gating pulses are ideally situated either side of point 9. Assuming that all switches are in the shown positions, that the received pulse is as shown at Fig. 2F and the derived output of 4 is as shown at Fig. 2B, a + 2.5Á sec gating pulse is applied to the master envelope sampling gate 20 and gates through point 23. The thus gated amplitude is converted to an equivalent digital value in converter 24 and said value is fed to accumulator 25 where it subtracts from the count therein. This continues for consecutive pulses until the accumulator count passes through zero and tends negative. This produces an output on line 40 which causes switch driver 35 to switch over switches 19 and 33. A - 2.5Á sec gating pulse is now applied to gate 20 and the cycle peak to the left of point 9 is now gated. Due to the switch over of switch 33 an add/subtract instruction signal on line 27 to the accumulator, is changed to " add ", such that the output of converter 28 is now added to the now negative count in accumulator 25. The count thus passes through zero again causing another switch change. This repeated passage of the count through zero indicates that the gating pulses are correctly aligned either side of point 9. The pulse on line 21, midway between the two gating pulses is fed to master cycle sampling gate 5 to which the received master pulse is fed. If the pulse is as in Fig. 2F, then the null cycle point 22 is exactly gated and converter gives no output and the pulse on line 21 is stable and is used for determining the time difference between the master and slave pulses. If however point 22 is not gated then converter 41 will produce an output which causes the count in accumulator 42 to eventually overflow the capacity whence a signal is fed to logic means 14 which in turn causes divider chain 11 to shift the pulses on line 12 by 5% of a cycle. This fine phase shifting of the gating pulses is continued until accumulator 42 no longer overflows and the pulse on line 21 is aligned with point 22. If the gating pulses of switch 19 are not either side of point 9, e.g. as with the derived waveform of Fig. 2D, then the output of converter 24 will be applied to accumulator 25 in such a sense that the accumulator will overflow. An overflow signal will be fed on line 126 to logic means 13 which causes the gating pulses to advance half a cycle and the count in accumulator 25 to reverse in sign. A signal is also fed to switch driver 38, causing the switching of switch 39. The reversal of sign in accumulator 25 causes the switch over of switches 19 and 33. Thus, if the previous gating pulse had been the - 2.5Á sec, it is now the + 2.5Á sec and if the output of converter 24 had been applied to give a negative overflow in accumulator 25, it is now subtracted from a positive count in accumulator 25-the serial switching of inverters 2 and 32 cancelling each other out. The result is that the gating pulses now straddle the point 9 and the count in accumulator 25 hunts zero. The section of the receiver receiving the slave pulses (Fig. 4, not shown) is similar to that described. It is required that the slave carrier null selected shall be that corresponding to that selected in the master pulse and not necessarily that nearest point 9. If the interval between point 9 and null 22 is called the envelope error, e.g. zero in Figs. 2B and 2E and quarter cycle in Figs. 2C and 2E, then the slave carrier null selected is such that the difference between the master and slave envelope errors is less than plus or minus half a cycle. The pulse on line 21 may be used to start a pulse counter receiving clockpulses and the corresponding pulse at the gating input of the slave cycle sampling gate, Fig. 4, may be used to stop said counter, the count reached indicating the time difference between the received master and slave pulses.