Patent GB-789660-A (GB)
Title: Improvements in or relating to electrical information storage systems
IPC: H04N5/257
Filed: 1956-10-05
Abstract: 789,660. Statistical apparatus. WESTERN ELECTRIC CO., Inc. Oct. 5, 1956 [Oct. 18, 1955], No. 30433/56. Class 106 (1). [Also in Groups XXXV and XL (b)] Information recorded photographically on a number of slides 25, 26, 28, 29, Fig. 1, is sensed at corresponding positions on each side by projecting light from the screen of a cathode-ray tube 15 through lenses 23 on to the slides and thence through lenses 36 to photo-sensitive elements 31 to derive signals which are passed via gates 32, 33, 34, 35 to an output register 40. The slides.-These may be ordinary photographic glass slides having patterns of opaque and non-opaque areas formed thereon by exposure to a cathode-ray beam in accordance with information it is desired to store. An example of a binary word of the kind stored is shown at 41, Fig. 3c, considerably enlarged from actual size. The word has sixteen binary bits each being an opaque area or a transparent area. The starting address point is 42, the beam being directed to this point when it is necessary to read out the word. Since the four slides 25, 26, 28, 29 all have information stored on them the capacity of the store is four times what could be obtained with one slide. The output gates 32, 33, 34, 35 may be arranged so that signals from one element 31 are passed to the output register while the signals from the other elements are blocked. By this means although all slides are scanned simultaneously information from one slide only is read out at any one time. Parallel read out may also be used whereby a portion of each word is stored on each of the slides and signals from each arrive simultaneously at the gates which act to delay them so that they pass consecutively to the register 40. Checking apparatus is provided for checking that the information in the register 40 is derived from the desired address position and for cancelling it if not. Address selection and beam positioning.-The horizontal and vertical address co-ordinates of the desired data word on one of the slides are entered into registers (e.g. 18) at 7 and 8, Fig. 1, respectively. Fig. 1 shows circuitry for the horizontal deflection control only, the vertical deflection control being substantially identical. In addition to the data bearing slides there are others, of which slides 24 and 27 are vertical and horizontal address positioning slides. Slide 24 has horizontal opaque bands and slide 27 has vertical bands. When a scanning beam is properly positioned on an address position of the storage slides it will also be at the intersection of an opaque band and a non-opaque band on each of the positioning slides as shown in Fig. 3A which depicts the positioning slides as superimposed, the address points being 42 (Fig. 3C), 43, 45. When the light beam impinges on a proper address position it will be half obscured by a band on each of the positioning slides. The other halves of the beams pass through to give signals in the photo elements 31 which are transmitted to differential amplifiers 37 in the horizontal and vertical address control circuits. These amplifiers compare the signals produced with a reference voltage called a " grey reference " and amplify the difference. If there is no difference no " initial position error " signal is transmitted. If the input signal is less than the grey reference because most of one of the beams is on the black band of the corresponding positioning slide, a voltage will appear at the output of the amplifier 37 and likewise if the input signal is greater than the grey reference, a voltage of opposite polarity appears. The initial position error signals from amplifier 37 are fed to an error integrator 47 through an inverter and gate circuit 81. The error integrator comprises two networks of trigger signals there being two triggers in each which will conduct upon receipt of a critical magnitude signal of negative polarity and two triggers which will conduct upon receipt of a critical magnitude signal of positive polarity. The circuits in each error network are oppositely arranged so that an input signal of one polarity will be inverted by one but will retain its original polarity in passing through the other error integrator circuit. The output signals are passed to the summing amplifiers 20, 21 in the respective deflection control circuits for addition to the input address signals. In this way the beam is driven towards the intersection between the opaque and transparent bands on the positioning slides. When accurate positioning is attained the scanning circuit 46, Fig. 1, is actuated via lead 93 by the clock pulse generator and gate control circuit 48 to move the beam across the information slides to read the information into the output register 40. The scanning circuit may comprise a chain of binary counter units producing a voltage increasing in steps and applied to the deflector plates through summing amplifiers 20, 21. If the initial positioning error is greater than the width of a band on one of the positioning slides, the means described will be ineffective to correct it but will merely select the nearest address position and a seventh slide 30 is provided to make a check for this possibility and initiate the necessary corrections. This slide bears, at each address location a binary word defining that address location in both co-ordinates as shown at 49 in Fig. 3D. This address word is normally read out as the same address position is scanned on the other slides and impulses from the photosensitive element 31 are fed to a steering circuit 91 which consists of gates controlled by the clock-pulse generator in such a manner that the information on slide 30 as to the horizontal and vertical addresses is fed through the corresponding horizontal and vertical address -control circuits for comparison with the input address information in both co-ordinates. The comparator used may comprise a number of circuit arrangements of flip-flops and gates to subtract the address check word read on slide 30 with the input address word. In practice only the four least significant of the address digits are used for making the check, the address digits from the two sources being entered into two shifting registers 55, 56 the incoming address digits from the-slide 30 being subtracted one by one from the input address digits by serial subtractor 57 and the difference re-entered in the shifting register 56 which therefore contains a value representing the address error. This error is added to the content of register 55 and the result is passed through an analogue converter 58 to the summing amplifiers 20 (21) to originate a second trial positioning of the beam. A signal from the register 56 in the horizontal or vertical address control circuits is passed over lines 61, 62 to the clock pulse generator and gate control 48 so that when any value is contained in the register (indicating an error) the information in the output register 40 is cancelled (by being displaced) and a second positioning and reading cycle is initiated. After repeated recycling a " trouble " indication may be given and the storage circuit released for the next address. If no value is present in register 56 the value in the output register is allowed to proceed to the processing device. Parallel read out.-When the information is to be read out from all slides simultaneously the check slide 30 can be used as an additional storage slide and the binary words, including the address check word can be distributed over the five slides 25, 26, 28, 29 and 30. The binary digits representing the address word would be gated sequentially into the check registers for use as before and the data words would be gated sequentially to the output register.