Patent GB-1454932-A (GB)
Title: Pulse-code transmission system
IPC: H03M3/02
Filed: 1974-08-30
Abstract: 1454932 Pulse code modulation system PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 30 Aug 1974 [3 Sept 1973] 38031/74 Heading H3H In a delta modulation system in which the input analogue signal is sampled and the difference between it and a prediction signal is fed to a non-uniform quantising circuit with adjustable dynamic range whose output signal is both transmitted to the receiver by PCM and added to the prediction signal to form the input to the predictor, the dynamic range of the quantising circuit is controlled by dynamic control means fed by the predictor input and having a storage and an averaging network which produces a control signal corresponding to the average of the absolute values of the predictor input signal over a limited number of sampling periods. The receivers incorporate a similar dynamic control means which operates in a reciprocal manner to the transmitter control signal. Analogue embodiment (Fig. 1).-The band pass filtered analogue signal x(t) is sampled at 3. The difference between the sampled signal and a prediction signal #(nT) is formed at 11 and fed to non-uniform quantising and compression circuit 5 which has a dynamic range controlled by variable amplifier 20. The output signal e cq (nT) is coded at 7 and transmitted via adder 31. The output signal is also suspended at 10, has its dynamic range controlled by variable amplifier 21 and is added at 9 to the prediction, signal #(nT). The resulting signal forms the input X q (nT) to the predictor 8 which delays the signal by one sampling interval. The predictor input signal is also fed via full wave rectifier 26 to storage elements 22-25 which contain the signals of four successive sampling periods. These are summed and averaged in network 19 and supplied to evaluation circuit 27, which categorises the input signal into one of four ranges and sets the gains of amplifiers 20 and 21 to one of four valves (preferably 8, 4, 2 and 1), the connections being such that the gain of 20 is a maximum when that of 21 is a minimum. The receiver comprises a similar dynamic control circuit and synchronises its clock pulses with the transmitted signal. Digital embodiment (Fig. 4).-Circuit 38 determines the magnitude (le(nT)) and polarity sgn{e(nT)} of the difference signal. The polarity signal is applied directly to parallel to series converter 39 while the magnitude signal passed to counting coding circuit 40 (described under) which generates a non PCM word non linearly related to the difference input and changes the dynamic range under control of signals from 27. The dynamic control circuit 17 divides each input by 4 at 44 by a two place binary shift and stores 4 successive values at 22-25. The stored values are added in adder 41-43 and the result is converted at 27 to a 2 bit binary control signal for the dynamic range of circuit 40. Counting coding circuit 40 (Fig. 6).-Clock pulses from source 52 (at 128 times the sampling frequency) are fed via gate 53 to counters 71 and 54. Counter 54 has 11 stages 55-65 (plus three extra stages 74-76 for dynamic range control) and the clock input may be fed to any of stages 55-61 by control device 77 which responds to the count in counter 71. The output of counter 71 is the PCM word, and that of counter 55 is fed to adder 9 and to D/A converter 66, the analogue output of which is compared with the difference signal at 67 and closes gate 53 at equality. The circuit initially supplies clock pulses to the lowest input (55) of counter 54 and at predetermined counts in counter 71, the input position is stepped to higher stages producing a non linear relationship between the count in 71 (which is the PCM word) and the analogue signal from 66 corresponding to the count in 54. The dynamic range change in steps of two is achieved by moving the clock pulse inputs one or more stages up or down the counter for all settings of control device 77. Error prevention.-To prevent incorrect resurrection of the signal at the receiver due to a transmission fault and an incorrect prediction signal, circuit 28 which is a shift register with module 2 feedback and comparator produces an output at regular intervals. This sets the contacts of all stores 22-25 to a maximum and the contents of predictor 8 to zero. This results in the transmission of the input sample as the next transmitted signal and this will restore the correct level in the receiver predictor circuits.