Patent GB-1305841-A (GB)
IPC: G06F17/18
Filed: 1971-04-19
Abstract: 1305841 Histogram processor INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [17 July 1970] 26257/71 Heading G4A and G4H [Also in Division H4] From the counts in counters 26A-26J (Fig. 2) representing a histogram indicative of different characteristics of an input signal, VIDEO, logic circuitry 27 detects the presence within the histogram of a characteristic which has a lower frequency of occurrence in both its adjacent characteristics, i.e. a DIP characteristic. As described in a first frame scan of a field (1, Fig. 1A, not shown) by a camera (3), the DIP characteristic is found, this information being used in a second frame scan to determine the co-ordinates of the centroid of a target (T) in the field. The amplitude of the video signal generated as the camera (mounted for example on board a space craft) scans the image of the field is compared in operational amplifiers 23 which reference levels E1-E10 the outputs of the amplifiers being fed to logic circuitry 24, 25 which is such that at any time a signal is present on one of ten leads L1V-L10V representing the instantaneous value of the input. The lines are simultaneously periodically scanned as the camera scans the image to feed pulses to the associated counters 26A-26J. When a first counter overflows (either during the frame scan of the camera or during trace back when the counters are simultaneously pulsed by a clock source) the output of an associated logic circuit (35, Fig. 4, not shown) goes to its low state to set an associated bi-stable, e.g. for counter 26E bi-stable (45) which results in all lower bi-stables (40-44) being set. (The higher stages of the counters are locked when they overflow to maintain the overflow pulse.) Any subsequent overflow pulses from lower order counters 26A-26D have no effect of the bi-stables 41-44 and any overflow pulse from a higher order counter 26F-26J results only in its associated bi-stable being set, lower order ones being inhibited by the output from the lowest bi-stable (40). If for example counters 26C, 26D, 26F overflow subsequently to counter 26E during the frame scan bi-stables (41-46) are set and the output of the sixth logic circuit (35) is at a zero level at the end of the scan when the counters are incremented by count up pulses (C U ). If the overflow pulses are such that one or more counters, e.g. 26G, 26H are positioned between two counters, e.g. 26F, 26I which have overflowed one of eight NAND gates (51-58) e.g. NAND gate (57) switches to a zero level to set one of eight associated bi-stables (60-67), e.g. bi-stable (56) to enable a further NAND gate (68) and supply a signal (DD) indicating the presence of a DIP characteristic to a lamp (70, Fig. 5, not shown). If counter 26G then overflows a further bi-stable (47, Fig. 4, not shown) is set but when the last counter 26H overflows its associated bi-stable is not set since the input (L9C) to its associated gate (36) is at zero. Consequently the output (DAL8) from the bi-stable remains at zero and a lamp associated with this level is illuminated together with all higher level lamps. In the frame period following the detection of a DIP characteristic in counter 26H the centroid of the target is found by computing the co-ordinates where X and Y are the x and y addresses of the scanning beam when the target area is sensed (this area being recognized by the video signal being at or above a level associated with the DIP characteristic) and where #A is an elemental unit of the target area. The computation is affected by, each time a signal #A exists, adding the x and y addresses represented by a nine bit parallel binary coded signal to the contents of accumulators 92, 95 (Fig. 6) in parallel adders 91, 94 and storing the results in the accumulators 92, 95, accumulators 93, 96 operating as carry stages to form the sum #X#A and #Y#A. The signal #A generated whenever the video signal has the required level are also accumulated in a counter 102 to form the divisor ##A, the co-ordinates X C  and Y C  being subsequently formed in a serial divider 105 and stored in binary coded decimal form in registers 107, 108 the contents of which may be displayed. The signals #A controlling the computation are derived from logic circuitry (27B, Fig. 5, not shown) in which with a DIP characteristic detected at level 8, i.e. in counter 26H in the subsequent frame period signals (L2VD-L7VD) are held at an UP level whereas signals (L8VD-L9VD) switch levels in response to the signals L8V-L10V (Fig. 2). To prevent errors, the signal #A is not generated until the brightness level of three successive samples is at or above the required level. Each of the parallel adders (Fig. 7a, not shown) comprises, for each stage, a three input circuit (111) receiving one bit of the address signal one bit of the signal from its associated accumulator (92, 95) and a carry bit from the previous stage, carry signals from the highest stage being fed to the auxiliary register (93, 96) which comprises sixteen serially connected bi-stable stages. The divisor (Fig. 9, not shown) which comprises a ten stage shift register (128) operates by repeated subtraction of the divisor from the dividend, the co-ordinates X C  and Y C  being computed serially.