Patent GB-1297866-A (GB)
IPC: G04G3/00
Filed: 1970-07-17
Abstract: 1297866 Electronic timepieces SOC SUISSE POUR L'INDUSTRIE HORLOGERE SA 17 July 1970 [18 July 1969] 34904/70 Heading G3T [Also in Division H3] An electronic timepiece comprises a quartz oscillator O (Fig. 1) the output Vo of which is applied to a generator G which transforms Vo into a 2-phase signal Vox-Voy of same frequency (or to a multiple or sub multiple of the oscillator f), a frequency divider DM having a plurality of dividing stages the supply to which is alternately controlled by one and then the other of the phases X and Y and which serves to lower the frequency of the 2 phase signal (2À4 Mc/s) to a value of 1 c/s (signal Vc). The signal Vc controls a time indicator IT including an electro-machanical converter CE and a gear train s.m.h. driving seconds, minutes and hour hands respectively. Integrated circuit techniques are preferably employed. FREQUENCY DIVIDING The quartz oscillator O output is fed to a cascade amplifier comprising gate-insulated field effect MOS transistors TG1, TG2, the oscillator output controlling TG1 whereas TG2 is controlled by a voltage divider R 1  R 2 . Thereby sinusoidal voltages Vox and Voy in anti-phase are produced at opposite ends of a transformer T at the oscillator frequency. The transformer T may form a tuned circuit with Ca Cb and the overall capacitance of the divider circuit so that energy is periodically stored and recovered and power consumption minimized. The divider comprises stages I, II, III etc. Each stage starting from the second is supplied from source P via a pair of field-effect transistors Tan, Tbn, (eg. Ta 2  Tb 2  in stage II), the gate of the first Tan being controlled by the periodic signal from the preceding dividing stage (eg. Ta 2  is controlled by signal at point a 1 ) and the gate of second Tbn is controlled by the X or Y phase voltage - in alternation from one stage to the next. Each stage comprises two amplifiers e.g. stage II which has amplifiers T 24  C 23  and T 21  C 21 . Transistor T 24  is controlled by the voltage across its self capacitance Cp 2  which is charged via C 24  from between Ta 3  and Tb 3  and is discharged via T 22  and T 23 . Transistor 23 is controlled by the Y phase voltage Voy Corresponding transistors T 33 , T 43 -Tn 3  are controlled by either Vox or Voy in alternation from one stage to the next. OPERATION OF DIVIDER Considering stage II. When the first pulse of a signal Va 1  from stage I reaches point a 1  and the gate of Ta 2  the overall capacitance of stage II discharges through Ta 2  so that the potential Vb 1  at point b 1  becomes zero. Since Tb 2  is controlled by Vox it conducts so that the overall capacitance of stage II is recharged while T 24  is still blocked. This causes a potential Va 2  at point a 2  and gate of Ta 3  so that Ta 3  conducts, whereas Tb 3  is blocked since it is controlled by the Y phase, and the capacitance of stage II is discharged through Ta 3  producing signal Vb 2  at point b 2 . During the subsequent half period of Voy the transistor Ta 3  is blocked and the capacitance of dividing stage III is thus recharged. Because the capacitance of II became discharged when the first pulse Va 1  reached Ta 2 , the potential at point d 2  is zero and T 23  is blocked. Thus at the instant the capacitance of III begins to be recharged the input capacitance Cp 2  of T 24  also becomes recharged via C 24  despite the fact that T 23  turns OFF and ON at the frequency of Voy. When T 24  conducts, the input capacitances of Ta 3  and T 21  become discharged so that they turn off thereby forming the first pulse of signal Va 2 . The input capacitance Cp 2  of T 24  acts as a memory for stage II as it is always charged when Ta 2  receives a pulse signal Va 1  from stage I. Since Cp 2  is charged T 24  conducts and point a 2  remains at zero potential so that the second pulse Va 1  is suppressed. Thus T 21  remains blocked so that T 22  conducts. T 23  is blocked due to its control by Voy. When eventually T 23  conducts Cp 2  of T 24  discharges through T 23  and T 22 . Stage II is now at the same state as when the first pulse Va 1  arrived so that the third pulse Va 1  will cause a pulse Va 2  to form, but not the fourth pulse, and so on. In like manner each stage divides the frequency input from the preceding stage by two. The divider may be constructed by integrated circuit techniques since it uses MOS transistors and MOS capacitors.