Patent GB-1378199-A (GB)
Title: Memory register
IPC: G06F5/08
Filed: 1972-06-21
Abstract: 1378199 Shift register storage systems CASIO COMPUTER CO Ltd 21 June 1972 [26 July 1971] 29078/72 Heading G4C Characters are written in to or read out from a shift register store, which stores a series of characters, under the control of a circuit that detects the presence or absence of characters in each of at least two character positions in the store. The store may comprise registers 1, 2, 3, Fig. 1, the output of register 1 being connected to the input of register 3. Read in: Assume that a series of characters is already in the store and that a character has just been written in to register 2 from input 13, store 3 being empty. The presence of the character in register 2 causes a 1 output to be passed from register 2 to gate 6, this output being inverted at 7 to inhibit gate 8. Similarly the absence of a character in register 3 causes a 0 output to be passed to inverter 9 to enable gate 6. If a write-in instruction is present at input 13 gate 6 triggers unit 10 which delivers a pulse of one character period duration. This pulse enables gate 12 so that the next character of the series is written in to register 2 from input 13, the character previously in register 2 being shifted to register 1. If the character to be read in was the first of a series, all registers being empty, it is read in to register 2 under the control of start signal generator 14. Read out can occur when register 2 is empty and register 3 full. Gate 6 is then inhibited but gate 8 gives an output triggering unit 15 and enabling gate 17 so that the character in register 3 is read out to 18. The character is deleted from the stored series since gate 4 is inhibited by the output of unit 15. A second embodiment, Fig. 2 (not shown), is generally similar to that described above. It includes a fourth register (115) which receives characters from register 1 and feeds them to register 3. During read out, when register 3 contains the last character of the series the fourth register (115) will be empty. This absence of a character is used to reset the start signal generator 14 to be ready for a succeeding writing phase. In a third embodiment, Fig. 8, the first character of a series is read in via gate 4 under the control of start signal generator 14. When this character reaches register 3 unit 21 is triggered. After one character period this delivers a character period pulse a which triggers unit 22, which delivers a delayed but similar pulse b. During pulse a the first character is shifted to register 1. At the end of pulse a, and in the presence of pulse b, gate 24 is enabled so causing the second character to be written in to register 1 immediately following the first character. Similarly the third character is read in immediately after the first and second have been shifted from register 3. Because of the one character delay between the setting and resetting of units 21, 22 the output of 21 indicates the presence or absence of a character in register 3 whereas the output of 22 indicates the presence or absence of a character in the preceding character period, i.e. in effect in stage 1 of register 1. Read out occurs in an analogous manner: when the first charcter is in register 3 pulse a is present and pulse b absent, so that gate 17 is enabled via gate 26 and the character is read out. In a further embodiment, Fig. 9 (not shown), read out is non-destructive, and in a final embodiment, Fig. 10 (not shown), means is provided to ensure that the store can be filled only to one character less than its maximum capacity so that the series is always preceded by a blank character position.