Patent GB-1445714-A (GB)
Title: Array processors
IPC: G06F15/80
Filed: 1973-04-13
Abstract: 1445714 Data processing systems INTERNATIONAL COMPUTERS Ltd 11 April 1974 [13 April 1973 20 June 1973 (2)] 17809/73 29272/73 and 29273/73 Heading G4A Each high level instruction supplied by a general purpose computer 10, Fig. 1, is interpreted by a control unit 11 into a sequence of micro instructions retrieved from a read/write store for execution by an array of processing elements 12 each of which includes a bitaddressable memory and an arithmetic unit operating on a single bit at a time. Parts of each micro instruction held in a register 26 are applied to all the processing elements 12 and to row units 13 associated with the rows of the processing element array. A particular row and/or column of elements 12 may be selected by an address in a register 24, a row decoder 33 setting an activity register A in a selected row unit 13 to enable a gate 59 for the associated row of elements 12. The columns may also have column units similar to the row units 13. The array of processing elements 12 is preferably fabricated by integrated circuit techniques and has a switching arrangement to effect changes in geometry of the array by varying the number of "layers" and correspondingly varying the number of elements 12 in each layer. The edge elements in each layer may be selectively interconnected to form loops or chains in the row and/or column direction. In a multi-layer structure, part of a micro instruction held in register 26 is used to select the row units 13 on a desired layer. Each processing element 12 includes a store 70, Fig. 2, which is bit-addressed by lines on the micro instruction register 26 and an index register 47 of the associated row unit 13. Other micro instruction bits are used to (112) select the sum or carry output of an adder 83 as input to the store 70; (110-112) select a carry register C, operand register P or Q, activity register A1 or A2 or a modifier register B (determining which half of store 70 is used) to receive an input data bit; (113) to select the K output of adder 83 as input to the carry register C; and (129-131) to select a fixed input 121, an output 122-127 of the store 70 of a neighbouring processing element, or the output 128 of the store 70 of the same processing element as an input source. By selecting input 121 as a fixed zero, a bit can he entered from an I/O shift register 52 of the corresponding row unit, via an exclusive OR gate 115. By selecting input 121 as a fixed 1, input data bits from the I/O shift register can be inverted. The processing element array oan either be used to perform identical operations on a large number of operands in parallel, e.g. in meteorological forecasting, i.e. as a peripheral processor for a main computer 10, or as an extension of the far storage for the main computer. In the latter mode, two or more words may be stored at the same bit address of the stores 17 of a column of processing elements 12, and in this mode, 1-bit register 63 in the row units may be used as the I/O register of the storage array. The micro program may be stored in the array, and in main store mode, parallel arithmetic is possible by providing appropriate carry inputs to the adders. The control unit 11 may include a random access memory which stores a micro program loop retrieved from the stores 70 of the processing array, the loop being executed a specified number of times and, if required, parts of micro instructions being incremented at each successive execution of the loop. Execution of the micro program can be interrupted, on completion of the micro instruction, by the main computer 10 supplying a column and bit address to gain access to the processing array in main store mode.