Patent GB-1202863-A (GB)
Title: Improvements in and relating to automatically balancing a.c. bridge
Inventor: WOLFENDALE PETER CALEB FREDERI
IPC: G01R17/06
Filed: 1966-08-18
Abstract: 1,202,863. Electric sampling and integration. NATIONAL RESEARCH DEVELOPMENT CORP. 16 Aug., 1967 [18 Aug., 1966; 21 June, 1967], Nos. 37057/66 and 28716/67.. Heading G4G. [Also in Division G1] An automatically balanced A.C. bridge (Fig. 1), determining ratio of resistive inductive or capacitative elements connected in a double ratio bridge by four leads to points 4, 5, 6, 7 and 8, 9, 10, 11; respectively, is energized from source 19 over points 4, 11 and comprises auto transformer potential dividers 15, 18 between points 6, 9, and 5, 10; ganged taps 16, 17 being connected to transformer 20 whose unbalance output is amplified at 21, noise filtered at 22, and applied to phase detectors 23, 26 synchronously switchable from 19 directly and over quadrature shift to respond to an in phase component to drive tap changer 30 and to a quadrature component to drive a null balancing motor 28 (or 31) adjusting INDUCTOMETER 32 or differential capacitor 12, 13. At balance the ratio of the impedance elements is denoted by the tap ratio of 15, 18. A detector circuit (Fig. 2) coupled over transformer 33 to the output of amplifier 21 comprises balanced grounded field effect transistor switches 36, 37 alternately operated by waveform 132 (Fig. 3b), and charges capacitors 41, 42 over resistance 40 when grounded FET switches 43, 44 are closed by waveforms 135, 139 (Fig. 3b) to integrate the input over a time period with capacitor 41 responding to the in phase and capacitor 42 responding to the quadrature components; switches 36, 37 being synchronized with 43, 44. A further grounded FET switch 45 shunting 41, 43, 42, 44 is driven by waveform 230 (Fig. 5d) to close intermediately of the conduction periods of 43, 44 which represent a fraction of a cycle of the carrier. The resultant pulsating integrator signal is amplified at 54, filtered, and chopped by FET switch 57 synchronous with switch 45, so that an amplified direct signal appears at 56. Pulses 241 and 242 (Fig. 4) represent the increasing integrated signals on capacitors 41 and 42; the charges accumulating until switches 36, 37 remain open for a time interval (pulses 243). The voltage at point 56 is then sampled in response to in-phase and quadrature components, respectively. With switches 36, 37 open the charges on 41, 42 are static, and waveforms 225, 228 (Fig. 5d) operate normally closed FET switches 63, 64 in turn to allow signals to pass to the respective negative and positive inputs of biased differential amplifier 71 When signals applied on opening of 63 and closure of 64 or vice versa are sufficiently negative or positive, the presence or absence of error signal outside the biased range is indicated by positive or negative amplifier output. After sampling, switch 45 is closed to discharge capacitors 41, 42 to prepare the next cycle, whereby the signal is integrated for a period and the integrator is then discharged. The charging period of capacitors 41, 42 is variable to provide a variable B.P.F. effect. Also, amplifier 62 is fed from point 56 in series with field effect transistor switch 59 driven in synchronism with switch 44 to charge capacitor 61 to a level responsive to the quadrature component to drive the null rebalance servomotor 28 or 31. Amplifier 71 feeds a logic circuit (Fig. 2) wherein NAND gates 73, 74 are fed strobe pulses 226, 229 (Fig. 5d) to sample the output. for positive or negative error signal presence; their outputs symmetrically driving further logic circuits wherein (a) NAND gates 77, 79 in bi-stable connection receive a clearing signal 230 (Fig. 5d) at point 100 and energize inverter 81 to operate a digital register of which 91 is a bidirectional counter. If counter 91 is set to a 9 count, gate 96 passes a signal to inverter 92, gate 83 is inhibited from output, and the output of 96 passes to 92. A similar sequence is followed in successive counters. If counter 91 is not set at 9, 83 sets NAND gates 85, 86 in bi-stable, and a reset/count pulse (Fig. 5d) is applied to 87, which restores unset condition and pulses counter 91 to increase one unit. A pulse input from 89 determines direction of count. Similar operations in chain 74, 78, 80, 82, 97 &c. respond to a negative signal. Relays driven by the counters operate inductive voltage dividers 16, 17. Carrier and switching signals are generated (Fig. 3a) from A.C. source 110 driving square wave generating bi-stable 111, which energizes plural other bi-stables 113, 115, 117, 119, 121, 123 through gates 112, 114, 116, 118, 120, 122 to generate respective waveforms 133, 138, 137, 136, 135, 134 while bi-stable 124 generates waveform 132. Bi-stable 113 is set from 111 over gate 112, the rest transition of 111 sets 115 over gate 114, and 115 inhibits 112 from pulsing 113, while enabling 116 to switch 117 on the next transition of 111, which in turn disables 114 to inhibit 115. Gate 120 is then enabled, and the sequence continues until 123 is set. Gate 122 remains enabled, and on the next transition of 111, 123 changes state and enables 120 in reverse sequence until 113 reverses and the forward cycle recommences. Bi-stable 124 halves waveform 136 to generate a phase displaced waveform similar to 133 to drive switches 36, 37 (Fig. 2) while waveform 139 is produced by inversion of 137. Sine wave synthesizer (Fig. 5a) receives waveforms 134 to 138 (Fig. 3b) on FET switches 160 to 164, which operate to vary the attenuation of the voltage source 150, 151 applied to filter 165, and amplifier 168 with feedback notch filter 168A. FET switches 156, 157 are driven reciprocally from waveform 133 to alternate the polarities of the signals varied by switches 160 to 164, and the filtered output derived from variable gain amplifier 166 over meter 171 represents a sine wave synchronous with the waveforms of Fig. 3b. An integrator timing generator (Fig. 5c) is energized from generator 210 whose frequency is subdivided by bi-stable counter chain 211 to 216. A further bi-stable 223 driven from any output 217 to 222 of the divider chain, and on each operation is reset one period of generator 210 later. From the outputs are derived waveform 224 of period 231 representing one generator cycle, waveform 225 operating switch 63 in synchronism with switch 43 for sampling capacitor 41, waveform 226 operating switch 75, waveform 227 operating switch 59 to sample quadrature error in synchronism with switch 44. Waveform 228 synchronized with switch 43 samples negative error signal and waveform 229 operates NAND gate 74 (Fig. 2). Waveform 230 (the remainder of period 231) operates switch 45 alternately to discharge capacitors 41, 42. On termination of pulse 231 of duration set by switch 223A, the following period 232 commences a succeeding cycle. The inductive potential divider bridge arms (Fig. 6a) comprise cascaded identical auto transformers 180, 183, 185, 186, 184 each having 11 taps switchable by pairs of traversing wipers operable by equivalent selective ganged switching (Fig. 6b, not shown). A further identical potential divider chain 190, 191, 192, 193, 185 operates simultaneously. The 10 1 ratio transformers 197, 198 and 199, 200 respectively interconnected as shown with taps 187, 188, 189 and 194, 195, 196 respectively provide the two least significant figures of the 7 decade divider chain. The inputs of transformers 180, 190 are connected (Fig. 1) to the impedances to be measured, and are capacitance tuned to the operating frequency. Relays or semi-conductive elements switch the balancing elements. A modified detector circuit (Fig. 7) receives alternating signals of varying phase and amplitude over transformer 300 to FET switches 301, 302 responsive to signal 334. Similar switches 303-312 are provided and the circuit functions similarly to that of Fig. 2 and corresponding switches 303-312 are provided. Capacitors 317, 318 integrate the inphase signal, and switches 303, 304 operate so that either is charged while the other is discharging. In sequence switch 303 opens; 304, 308, 309 close; capacitor 318 discharges over 308 and capacitor 317 charges from 300 over switches 301, 302, 305 for the integration period until 303 closes. Input is disconnected for a sampling interval in which the bridge is switched, and the cycle is repeated with capacitor 318 charging and 317 discharging. Switch 309 of capacitor 319 is synchronous with the quadrature signal component. Waveforms phase and frequency locked to a source are generated (Fig. 8) by squaring the output at frequency of generator 350 and to triangular waveform at 352, which is fullwave rectified at 353 to triangular wave of frequency 2f which is fullwave rectified at 355 to a triangular waveform at frequency 4f &c, which is differentiated to a squarewave during sequential divide by two stages 559 to 363. A further divide by two element 370 is switchable at 371 to any output 364 to 368 of the dividers to change over for every impulse thereat, so that elements 359 to 368 are reset to zero over reset line 369 on the next impulse from 371. The generated waveforms are illustrated in Fig. 9 (not shown). Waveform 380 is adjustable to establish integrating period P, followed by an intervening sampling period S, and P is a multiple of 1/F at repetition frequency 1/(P + S). For bridge unbalance, the servoloop repetitively adjusts the bridge arms by single steps if the error is above threshold, or alternatively the error signal may be amplified, repetitively sampled and the resultant analog signal digitally converted to adjust the bridge switching as a function of the error magnitude; and accelerate rebalance. The threshold amplifier and logic are replaced by A/D converter and the digital signal added to the held count so that each servo response is a function of the magnitude of the sampled error, which error is integrated repetitively over short periods for initial balancing and long periods for subsequent balancing. The bridge may measu