Patent GB-1457879-A (GB)
Title: Multi-chip calculator system
IPC: G06F15/78
Filed: 1973-12-14
Abstract: 1457879 Calculators TEXAS INSTRUMENTS Inc 14 Dec 1973 [13 Sept 1973] 58041/73 Heading G4A An electronic calculator includes at least two semi-conductor integrated circuits each having timing generators, a condition signal generator being connected to the timing generator on one of the integrated circuits to generate a signal which is sent to a synchronizing circuit provided on the other semi-conductor integrated circuit, the output of the synchronizing circuit being fed to the timing generator on that circuit. As described the two semi-conductor integrated circuits are an arithmetic chip (10, Fig. 2, not shown), in detail in Figs 3a, 3b, and a scanning read-only memory chip (12), shown in detail in Fig. 4. Other units, e.g. a keyboard, display, printer chip and additional storage chip may be connected to the calculator. In the scanning read-only memory chip, the address held in register 23 is fed via gating 22 and decoder 21 to read-only memory 20 to read in parallel an instruction to instruction register 26. The memory is a 13 Î 1024 matrix store (Figs. 9a, 9b, not shown) which is pre-charged through its decode address circuitry and has only one ground per pair of instruction bits. A 13 bit output word is serialized in buffer 27 and transmitted to (1) the arithmetic unit chip, (2) a branch comparator 33, (the twelfth bit indicating when a branch occurs) and (3) an adder 32 where a positive or negative number is added if a branch is required before it is fed to a holding register 24 connected to the address register 23. Normally the address is merely incremented by one in circuit 25 under the control of a signal EXT from the arithmetic chip so that a sub-routine stored in the memory is read out in sequence. A constant register address 34 is also responsive to the command word EXT from the arithmetic chip to address constant read-only memory 35 holding 16 constants when a recall constant command is decoded in decoder 28 connected to the instruction register 26. The constant read-only memory includes for each cell a single transistor having its gate either coupled or decoupled from its associated row line (Fig. 9c, not shown). An instruction word comprises a 3 bit selector gate field I 0 -I 2 , a 4 bit register field I 4 -I 7 , a 1 bit subtract field I 3  a 4 bit mask field I 8 -I 11  and a 1 bit branch field I 12 . An S counter 38 and D scan generator 39 synchronized to a command IDLE from the arithmetic chip generate S and D timing signals therebeing 16 S signals for each D signal. The arithmetic chip includes five 16 digit A-E registers 50a-50e (Fig. 3a), two 1 bit A and B flag registers 53a, 53b, a keyboard register 54 and a sub-routine register 55, the contents of register B or preferably register A being fed to an external display unit provided by a gas discharge tube, liquid crystals, light emitting diodes or preferably a 7 segment display unit. D timing signals are provided by a Detiming generator 67 (Fig. 3b) which counts down from 15 to zero. An incoming instruction word from the memory chip is initially decoded in mask decode 83 which generates masks representing e.g. decimal point location of a mantissa to allow part only of a data word to be manipulated. It is then fed to D/S flag mask comparator 68, flag decode matrix 72 (controlling the flag registers 53a, 53b) and decode matrices 53, 74 (controlling selector gates to couple registers to the arithmetic unit and to recirculate data amongst the registers). The arithmetic unit is of the bit parallel, serial digit type including a precharged binary adder with carry propagation and BCG correction control, utilizing bidirectional IGSET switches Fig. 8a, 8b, not shown. The adder uses exclusive or circuitry to derive a sum S equal to C(AB+AB)+C (AB+ AB) and a carry propagate function K + AB + C (AB+AB). The contents of the adder are fed to register 65. The keyboard register functions mainly to address a specific location in the read only memory, the location being held in sub routine register 55. Information may be fed to the arithmetic unit using an external keyboard unit 11 which is connected via lines K and an encoder 75 to an encoder 77 which supplies to control 79 for keyboard register 54 a 3 bit K co-ordinate signal and a 4 bit digit time signal (which together identify the operated key). A single key depression actuates the encoder 75 for sufficient cycles to complete the routine called for, the encoder 75 having the same entry reimposed on it at the occurrence of the respective D time in each instruction cycle. A comparator 78 recognizes the actuation of a predetermined K line to operate a condition circuit 80. The code matrix 72 controls either latch 81 to provide information as to whether the calculator is idle or not, the IDLE signal being transmitted to the S and D generators of the memory chip for synchronizing purposes. Synchronizing.-Each idle signal from the arithmetic chip changes state from a logic 1 to a logic 0 at a predetermined S time, e.g. S 0 , the counter 38 (Fig. 4) being zero at this time. It may also be programmed to change state at a predetermined D time D 14 so that the D scan generator 39 is synchronized.