Patent GB-1374042-A (GB)
Title: Charge coupled memory system
IPC: G11C11/35
Filed: 1972-01-05
Abstract: 1374042 Charge coupled devices RCA CORPORATION 5 Jan 1972 [14 Jan 1971] 386/72 Heading H1K A charge coupled storage device comprises two closely spaced plates separated from a common semi-conductor layer by a thin insulating layer to define two capacitors, and having means for supplying charge carriers to a region of the semi-conductor layer adjacent to the first plate and a line electrically coupled to a region of the semi-conductor layer adjacent to the first plate. Potentials are selectively applied to the first and second plates and to the line to transfer charge carriers applied to the device to the second capacitor and to transfer charge carriers stored in the second capacitor to the line which is connected to means for sensing the resultant current. As shown, each unit cell of a word-organized matrix memory comprises a storage plate 14 and a control plate 16 constituted by parts of conductive storage and control word lines which are separated from an N type Si substrate 10 by thin portions of an insulating layer 12 the remainder of which is much thicker. A plurality of bit lines B1, B2, B3 are provided by diffused regions which have portions. 20 extending to positions just below the control plates 16 of the associated memory cells. Writing-in.-The cells comprising one word are addressed by applying negative pulses to the control and storage lines. If the bit line associated with a cell is held at 0V minority carriers (holes) are injected into the potential wells formed beneath the control and storage plates to indicate a "1" state. If the bit line is held at - 20V during the addressing pulses any charge residing in the storage capacitor is drained away to the bit line and the absence of stored charge indicates a "0" state. The stored charge is retained by holding the control and storage lines at 0V and - 10V respectively, variation of bit line potential having no effect. Reading-out.-The cells are addressed by applying a negative pulse to the control line and a positive pulse to the storage line, and the bit lines are simultaneously taken to a negative potential. This results in any stored charge being transferred to the bit line, a current flow being sensed by amplifiers 26 for a stored "1" and no current flow being sensed for a stored "0". If desired the information may be rewritten into the cells. The charge carriers may be stored for about 10 seconds and to achieve longer storage times the memory must be periodically refreshed by reading-out and rewriting the bits into the cells. Information may also be stored by utilizing radiation (light or heat) to generate charge carriers in the substrate close to the control plates which may be formed as transparent conductors. Alternatively the lower face of the substrate may be illuminated with the information. The information may be provided by a holographic image produced from a hologram memory by a laser beam, Fig. 6 (not shown). Construction.-An N type Si substrate is masked and B is diffused-in to form the P+ type bit lines. A thick oxide layer is thermally grown over the surface, windows are etched at the storage and control plate sites, a thin layer of SiO 2  is applied at these areas. A layer of Al is vacuum evaporated over the surface and is etched to form the control and storage word lines. A P type substrate with N+ type bit lines may be used in which case the stored charges are electrons. The devices may be produced in a thin Si layer on a sapphire substrate. The control and storage plates at the cell locations may extend closer to one another than do the remaining portions of the associated lines, Fig. 7 (not shown).