Patent GB-1241983-A (GB)
Title: Electronic computer
IPC: G06F7/50
Filed: 1968-08-09
Abstract: 1,241,983. Electronic calculators. SHARP K.K. 9 Aug., 1968 [15 Aug., 1967], No. 38283/68. Heading G4A. [Also in Division H3] In an electronic serial mode calculator having at least one register formed of magnetic memory elements arranged in a matrix for storing binary coded digital information, synchronized read and write control means are provided. As described, signals for serial reading and writing of digits are generated in continuous alternating sequence. As shown (Fig. 1), an electronic calculator comprises an input keyboard 8, two registers 1 and 2 comprising a matrix of magnetic cores (Fig. 4, not shown, see Division H3) for storing two 16-digit binary coded decimal numbers, an adder/subtractor 7, two singledigit buffer registers 3 and 4, a further buffer register 5 associated with an indicator comprising a plurality of number tubes (Fig. 7, not shown), a micro-programme sequencing arrangement 9-11 including a diode matrix and a timing signal generator 13 comprising flip-flop counter circuits for generating signals defining bit and digit periods and digit read and write periods in continuous alternating sequence. Register 6 is for dealing with decimal point, no details of which are given. For addition, the two numbers are initially located in registers 1 and 2. During the first read period of the process the lowest order digits COX1 and COY1 of the two operands are fed serially to the binary full adder 7 and the output temporarily stored in buffer register 3. During the ensuing write period the correction factor of + 6 is added (if necessary) by recycling of the contents of register 3 through the adder 7 and the result directly written into the register 1 (see return paths in Fig. 5, not shown). The process is repeated for all digits. The subtraction operation is performed in a similar manner. Left shift is achieved by reading the lowest order digit of a number in register 1 or 2 into the register 3, recycling the digit in register 3 during the ensuing write period, passing the digit to register 4 during the next read period during which the next to lowest order digit is read into register 3, writing the old lowest order digit during the ensuing write period into the next to lowest order position in the register and repeating the process for all digits. Right shift is achieved in a similar manner by reversing the order of the digit defining output pulses from the timing signal generator 13. The contents of the register, are indicated on glow discharge number tubes. The contents of register 1 are read digit-by-digit into register 3 and immediately rewritten. At the same time the contents of register 3 are passed to the register 5 associated with a diode decoding network associated with the tubes (Fig. 7, not shown). The timing signal generator digit signals are reversed so that read-out takes place from the high order end of the register 1 and a flip-flop connected to the register 5 can detect when the first significant digit occurs to effect zero suppression. The timing generator counting circuits (Fig. 3, not shown) comprise four cascade connected flip-flops and four further flip-flops connected to form a so-called Eicosal counter (Fig. 3(7), not shown), the decoded outputs of which may be reversed in order by application of a control signal.