Patent GB-914805-A (GB)
Title: Improvements in magnetic core logical circuits
IPC: H03K19/16
Filed: 1958-05-28
Abstract: 914,805. Circuits employing bi-stable magnetic cores. TAUB, D. M., and PUGMIRE, J. M. May 27, 1959 [May, 28, 1958], No. 17033/58. Class 40 (9). BUT NOT and AND gates are constructed from three bi-stable cores, one of which at least is linked by a common output winding, halfwrite input signals being applied to windings on each of two of the cores in coincidence with half-write gating pulses applied to windings linked with both of the two cores which also have windings by means of which the two cores are reset subsequent to the receipt of input signals, and a read-out winding linked with at least the third core energization of which resets the cores to a datum state. The BUT NOT gate of Fig. 1 shows windings 6 and 7 to which half-write inputs are applied in coincidence with half-write pulses IA and IB, Fig. 1B, applied to windings which act on the cores 1, 2 and 3 in the sense of the arrows 8 and 12, and 9 and 13, respectively. A core turned over in the direction of a downward arrow is in a 0 state while the upward arrows indicate a drive to the 1 state. The cores 1, 2, 3 are initially in the states 0, 1, 1, respectively. A set input to winding 6 in coincidence with the IA pulse switches core 1 to a 1 state and the current induced in the output circuit switches core 3 to a 0 state. An inhibit input to winding 7 in coincidence with the IB pulse switches core 2 to a 0 state and resets core 3 to a 1 state over the output circuit. A winding linked with cores 1 and 2 and acting in the direction of arrows 10 is then energized by waveform 1SR, Fig. 1B to switch cores 1 and 2 to a 0 state so slowly as to produce no significant signal in the output circuit. A read-out pulse 2A or 2B, depending on whether the output of the circuit is to be applied to a following stage as a set or an inhibit input, is then applied to core 3 over a winding acting in the direction of arrow 14 to drive core 3 to a 1 state and core 3 is switched only in the event that a set input occurs alone. The application of an inhibit pulse without a preceding set pulse would appear, in coincidence with an IB pulse, to switch core 2 but it is to be noted that the load circuit is low impedance in this event and provides a short circuit loop to stop switching. After read-out a waveform 2SR is applied to a winding on core 2 to set it to a 1 state as shown by arrow 11, the core being switched slowly. A table indicating the core states for each possible combination of inputs is shown in Fig. 1A. The waveforms 1SR and 2SR may be combined to drive a single winding linked with cores 1 and 2 as shown by the arrows 14 and 15 of Fig. 2 where the read-out pulse 2A or 2B is applied to a winding linked with cores 2 and 3 as shown by the arrow 16. The table of Fig. 2A indicates how the read-out pulse produces an output only when the set input is applied alone. The arrangement of Fig. 3, not shown, provides a modification of the half-write gating windings energized by waveforms IA and IB to permit the inhibit pulses to be applied first in coincidence with the pulses IA and the set pulses to be applied second in coincidence with the pulses IB. The AND gate shown in Fig. 4 has half-write gating waveform IA acting in the direction of arrows 17, 18 and 21, on all three cores, while half-write gating waveform IB acts in the direction of arrows 19, 20; pulses IA and IB gating the half-write inputs 6 and 7, respectively. The combined waveforms 1SR, 2SR are applied to a winding acting on cores 1 and 2 as indicated by arrows 14 and 15 and a read-out pulse 2A or 2B acts over a winding with the sense of arrow 16 linking cores 2 and 3. The table of Fig. 4A shows how read-out generates an output only when both inputs are present.