baber/WOPTO huggingface dataset:
Patent TW-515162-B (TW)
Title: Transmission of data packets over CDMA type cellular telephone
Inventor: PHILLIPS MARC
IPC: H04W76/02
Filed: 2000-10-03
Granted: 2002-12-21
Abstract: A system and method for enabling the use of popular serial networking application software (24) to transmit PPP packet data via a CDMA type subscriber device (30) to a network such as the internet (22). One or more reserved phone numbers is stored in memory (54) within the subscriber device. The networking application (24) is provided a telephone number to be dialed in order to make a connection to the internet. The telephone number provided to the networking application is compared to the stored reserved telephone numbers. If there is a match, the subscriber device (30) transmits a CONNECT signal back to the networking application and initiates a packet data call. If there is no match, the subscriber device (30) initiates an asynchronous data call.
Patent TW-432790-B (TW)
Title: Circuits and methods for controlling timing and slope compensation in switching regulators
Inventor: HOBURETTO STEPHEN W
IPC: H02M3/158
Filed: 1999-09-10
Granted: 2001-05-01
Abstract: Circuits and methods for controlling timing and slope compensation in switching regulators are provided. These circuit and methods include a timing control circuit that controls the timing of the switching of one or more switching regulator output stages so that the switching occurs at evenly spaced time intervals, and a slope compensation circuit that produces a slope compensation signal having a waveform that need not match the waveform of any oscillator signal, nor that need have the same period as the oscillator signal. Timing control is performed by dividing a master clock signal using a T flip-flop and a ""rolling clock"" (or ""Johnson counter"") to produce 2N clock phase signals. Slope compensation is provided by generating a slope compensation signal using decoding logic, a digital-to-analog converter (DAC), and an integrator.
Patent TW-453107-B (TW)
Title: Circuit and method for fast adjustments of gain value and DC level
Inventor: SHR JEN-SHIANG
IPC: H04N1/40
Filed: 1999-09-13
Granted: 2001-09-01
Abstract: The present invention provides a kind of circuit and method for fast adjustments of gain value and DC level, in which the circuit and method are applied on the calibration circuit of scanner. Because the gain value is not affected by the adjustment of DC value, while the DC value is affected by the adjustment of gain value, therefore, the gain value is first adjusted. After that, the gain value is then used to adjust the DC value such that it is capable of even faster obtaining the optimum input value for the analog to digital (A/D) conversion circuit through one time adjustment of gain value and DC value.
Patent TW-441224-B (TW)
Title: Color electroluminescent display device
Inventor: YOKOYAMA RYOICHI
IPC: H01L27/32
Filed: 1999-10-26
Granted: 2001-06-16
Abstract: The purpose of the present invention is to provide a color electroluminescent display device with less manufacturing steps. The device of the present invention is to form anodes 7 and light emissive layers 15 for respective pixels, while a hole-transport layer 14, an electron-transport layer 16, and a cathode 17 are formed to extend over a plurality of pixels. Accordingly, a process of etching-back the hole-transport layer 14 and the electron-transport layer 16 is eliminated. Also, since partitions 68 as conventionally provided are not formed, the process of formation can also be eliminated. The anode 7 and the cathode 17 are separated by the hole-transport layer 14 and the electron-transport layer 16, and are therefore not subject to shorting, even though no partition 68 is employed. Furthermore, since the light emissive layer 15 is larger than the anode, a leakage current generated at the ends of the anode and field concentration can be prevented.
Patent TW-451132-B (TW)
Title: System and method for cache processing
Inventor: MIYAZAKI MITSUHIRO
IPC: G06F12/122
Filed: 1999-12-08
Granted: 2001-08-21
Abstract: In a cache system, a non-full-set associative cache table such as a direct mapping cache table is coupled with a full-set associative cache table. Tag comparison for cache hit judgment is executed simultaneously in the two cache tables. The number of cache hits to each cache line of the full-set associative cache table is counted by an access counter, and an access count value concerning the cache hit count is stored in an access count area of each cache line. When a cache hit occurred to a cache line of the full-set associative cache table, the access count value of the cache line is increased by 1. When a miss hit occurred to both cache tables, the access count values of all the cache lines of the full-set associative cache table are decreased by 1 at once. If miss hits occurred to both cache tables when the DM cache table has an invalid cache line corresponding to the index of input address data, data fetched from main memory due to the miss hits is written into the invalid cache line corresponding to the index. If the miss hits occurred when the direct mapping cache table has no invalid cache line corresponding to the index and the full-set associative cache table is full of valid cache lines, data stored in the miss hit cache line of the direct mapping cache table is transferred to one of cache lines of the full-set associative cache table having the smallest access count value, and data fetched from the main memory is written into the miss hit cache line of the direct mapping cache table. By such data management/transfer, the cache hit rate and data access speed are increased to maximum levels.
Patent TW-512610-B (TW)
Title: Node of telecommunications network and connection admission control method therefor
Inventor: ANDERSEN IB
IPC: H04L12/54
Filed: 1999-12-18
Granted: 2002-12-01
Abstract: A connection admission control (CAC) technique for a telecommunications node approximates probability of loss using a log moment generating function and its two partial derivatives of workload on a queue over a time interval. The approximation uses four state variables, which depend on the log moment generating function and its two partial derivatives. The four state variables are: (1) linear term in approximation to log loss ratio at a working point; (2) the argument of logarithmic term in approximation to log loss ratio at the working point; (3) a buffer limit used at the working point; and (4) a multiplier of imaginary traffic used at the working point. Advantageously, these state variables vary linearly with the traffic, so a new connection can simply add its contributions to them. The connection admission control (CAC) uses the state variables to produce the following three parameters: (1) an approximation q=z-log(c) to the logarithm of the probability of loss; (2) a buffer size limit B; and (3) a multiple m of imaginary traffic from a design mix. The traffic on all connections is admissable if four conditions are satisfied. The present invention applies, e.g., to a single queue and server, and can be generalized to multiple queues and servers.
Patent TW-525051-B (TW)
Title: A method and apparatus to power up an integrated device from a low power state
Inventor: NOOKALA NARASIMHA
IPC: G06F1/32
Filed: 2000-04-25
Granted: 2003-03-21
Abstract: An apparatus to power up an integrated device from a low power state wherein the clock circuit for generating the internal clocks has been disabled is provided. A small set of programmable registers is reserved inside the CPU interface unit (CIF) of an integrated device (e.g., a display/graphics controller) which can be accessed by the CPU even during a low power state mode (e.g., software controlled sleep mode D3 in the preferred embodiment). The programmable registers store programmed bits that are used in indicating to the power management unit (PMU) the desired power state and whether the clock circuits are to be enabled or disabled. The programmable registers also store multiplication and division factors to be used by the clock circuits in determining their clock rate. Using this information, the integrated device can go through a predetermined power sequence to transition from the low power state to the normal state which includes powering up the clock circuits (e.g., PLLs and oscillator).
Patent TW-452820-B (TW)
Title: System and method for cleaning contaminated surfaces in an ion implanter
Inventor: BERNSTEIN JAMES DAVID
IPC: H01L21/265
Filed: 2000-04-26
Granted: 2001-09-01
Abstract: A method and system is provided for cleaning a contaminated surface of a vacuum chamber, comprising means for (i) generating an ion beam (44) having a reactive species (e.g., fluorine) component; (ii) directing the ion beam toward a contaminated surface (100); (iii) neutralizing the ion beam (44) by introducing, into the chamber proximate the contaminated surface, a neutralizing gas (70) (e.g., xenon) such that the ion beam (44) collides with molecules of the neutralizing gas, and, as a result of charge exchange reactions between the ion beam and the neutralizing gas molecules, creates a beam of energetic reactive neutral atoms of the reactive species; (iv) cleaning the surface (100) by allowing the beam of energetic reactive neutral atoms of the reactive species to react with contaminants to create reaction products; and (v) removing from the chamber any volatile reaction products that result. Alternatively, the method and system include means for (I) generating an energetic non-reactive (e.g., xenon) ion beam (44); (ii) directing the non-reactive ion beam toward a contaminated surface (100); (iii) introducing a cleaning gas (70) proximate the contaminated surface, comprised at least partially of a reactive species (e.g., fluorine) component; (iv) dissociating the cleaning gas using the ion beam (44) to create a supply of energetic reactive neutral atoms of the reactive species; (v) cleaning the surface (100) by allowing the energetic reactive neutral atoms of the reactive species to react with contaminants to create reaction products; and (vi) removing from the chamber any volatile reaction products that result.
Patent TW-464470-B (TW)
Title: Culture soil for cultivating seedings
Inventor: YOSHIOKA MASATOSHI
IPC: A01G22/22
Filed: 2000-05-17
Granted: 2001-11-21
Abstract: A culture soil for cultivating seedlings is formed by agitation mixing and heat forming of chaff and kernel-husk fibers. The kernel-husk fibers are made from kernels and husks. The husks have a lower softening temperature than the kernels. The culture soil for cultivating seedlings includes 1.7x10<SP>-1</SP> to 2.0x10<SP>-1</SP> g/cm<SP>3</SP> of the chaff and 2.0x10<SP>-3</SP> to 8.2x10<SP>-3</SP> g/cm<SP>3</SP> of the kernel-husk fibers. The culture soil for cultivating seedlings preferably includes 2.0x10<SP>-4</SP>- 4.0x10<SP>-4</SP> g/cm<SP>3</SP> of a fertilizer that includes at least nitrogen. Thus, a cheap and mass-produceable culture soil for cultivating seedlings is produced. Moreover, the culture soil for cultivating seedlings is easy to handle because it does not break or crumble.
Patent TW-445652-B (TW)
Title: Thin film transistor process to increase the transmittance
Inventor: HUANG TING-HUEI
IPC: H01L29/786
Filed: 2000-05-16
Granted: 2001-07-11
Abstract: A thin film transistor process to increase the transmittance is revealed, which comprises an interlayer process, then etch the device formed by this interlayer process to remove the silicon nitride layer unblocked by the source or drain, so that the transmittance of the portion unblocked by the silicon nitride layer is larger than that of the blocked portion by silicon nitride layer. And said interlayer process can have three ways: first, bake the TFT panel and form contact and then form the source and the drain conductive pattern. Second, etch the TFT panel to form contact and form the source and the drain conductive pattern and then bake. Third, etch the TFT panel to form contact and sputter metal layer and then bake, then etch the metal layer to form the source and the drain conductive pattern. Said TFT panel comprises polysilicon gate, gate channel and silicon nitride insulating layer.
Patent TW-422764-B (TW)
Title: Novel structure for universal socket wrench
Inventor: TSAI JEN-CHANG
IPC: B25B13/46
Filed: 2000-05-16
Granted: 2001-02-21
Abstract: Disclosed is a novel structure for a universal socket wrench, comprising a main socket base, a spring retainer, a torsion spring, a small C-clip, a large C-clip, a sheath, and a mobile plate. The main socket base is provided with an annular groove at an upper end of an inner groove, and a post projecting from a bottom side for pivoting to the socket, a plurality of roller posts and spring plates of an equal number, where the roller posts are clamped and urged against an interior of an urging face, while the top ends of the spring plates are provided with projections for engaging the sheath. The sheath is formed with a plurality of spaced slots by angular posts distributed at a lower end thereof, while each of the spaced slots is provided at an upper edge thereof with an insertion hole for engaging the spring plate, and an annular groove around a top section thereof. The mobile plate is retained within the sheath by means of a central aperture and includes recessed portions at inner opposing locations. The spring retainer includes short posts for engaging the torsion spring. An inner rotating base is provided at a surface thereof with a plurality of accurate edges of a number equal to that of the spaced slots, an annular groove at an appropriate location, and symmetrically arranged stop blocks, where a manipulating handle is pivoted to projecting ears at a top end thereof. The sheath engages the inner rotating base by means of the central aperture and engages the top end of the sheath by means of a downwardly recessed portion. By such an assembly, the sheath, roller posts, and spring plates can prevent successive movement between the inner rotating base and the main socket base, so as to allow the main socket base to rotate along the driving force of the inner rotating base; further, tension of the springs urges the mobile plate to rotate in an appropriate manner and to allow positioning effect so as to obtain high torque, enhance stability, safety in operation, and effective operation.
Patent TW-475258-B (TW)
Title: Semiconductor device and its manufacturing method
Inventor: YOSHIHARA IKUO
IPC: H01L23/485
Filed: 2000-10-13
Granted: 2002-02-01
Abstract: In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.
Patent TW-568946-B (TW)
Title: Grouting consolidation material
Inventor: SHIMADA SHUNSUKE
IPC: E02D3/12
Filed: 2000-11-21
Granted: 2004-01-01
Abstract: A grouting consolidation material has high strength and excellent durability in spite of a low silica concentration and exhibits a long gelling time and enables seepage into a wide range as the grout for preventing the liquefaction of ground. A grouting consolidation material is obtained by mixing water glass with colloidal silica at a specified ratio or further mixing the resulting mixture with a specific amount of active silicic acid to form a stabilized alkaline silica solution as the base which is non-self curable in itself or further subjecting the resulting alkaline silica solution to dealkalization treatment to form a dealkalized silica solution as the base, and further adding an acidic reactant, another reactant, cement, slag and the like to the base.
Patent TW-594072-B (TW)
Title: Lighting apparatus
Inventor: TANAKA AKIRA
IPC: G02B6/00
Filed: 2000-11-24
Granted: 2004-06-21
Abstract: A lighting apparatus for causing the light from a light source to enter the incident surface of a light guide plate and to project the light toward an object of illumination from the exit surface of the light guide plate extending in the direction perpendicular to the incident surface. The light source is made by placing a light-emitting diode on or near the light source rod extending in the longitudinal direction parallel to the incident surface of the light guide plate. The light source rod and the light guide plate are integrally made by forming a slot in a common plate.
Patent TW-480760-B (TW)
Title: Magnetically coupled autonomous battery equalization circuit
Inventor: PETERSON WILLIAM ANDERS
IPC: H02J7/02
Filed: 2000-12-19
Granted: 2002-03-21
Abstract: A battery equalization circuit for equalizing charge between at least first and second series-connected batteries, where each battery has a positive end and a negative end, with the positive end of the second battery coupled to the negative end of the first battery at a common node, and using: a switching circuit connectable to the positive end of the first battery at a positive node and the negative end of the second battery at a negative node; a transformer having first and second magnetically coupled windings, each with a first end defining a polarity of the winding and a second opposing end; and a transformer reset circuit coupled from the windings of the transformer to the positive and negative nodes. The switching circuit acts to simultaneously couple the first and second windings in parallel with the first and second batteries, respectively, in the same polarity such that a charge is transferred between the first and second batteries as a function of a charge imbalance therebetween. The transformer reset circuit couples one of the first and second windings in parallel with one of the first and second batteries in an opposite polarity to direct reset current from the transformer to that battery to decrease the charge imbalance therebetween.
Patent TW-589580-B (TW)
Title: Device and method for performing high-speed low overhead context switch
Inventor: SUKONIK VITALY
IPC: G06F9/46
Filed: 2000-12-14
Granted: 2004-06-01
Abstract: A device (10) and a method for performing high speed low overhead context switch, and especially in processors that handle multilevel nested tasks. The device (10) handles forward requests (81) and backward requests (82). The device (10) is coupled to a CPU (50) and has a plurality of register files (20, 30) and a direct memory access mechanism that allows the processor to respond to the forward request (81) by starting to handle a higher priority task using a first register file (20) while transferring the halted task context to a context save area within a memory module (60). The processor responds to the backward request (82) by using the context that is stored in a first register file (20), while transferring to a second register file (30) a lower priority task context.
Patent TW-546448-B (TW)
Title: Gland packing
Inventor: FUJIWARA MASARU
IPC: F16J15/22
Filed: 2000-12-26
Granted: 2003-08-11
Abstract: The present invention provides a gland packing in which impairment of the sealing performance due to cracks that unwillingly occur in an end portion in the width direction of an expanded graphite tape of a braiding yarn in the gland packing can be suppressed. The solution of the present invention is that in gland packings 1, 2, braiding yarns include braiding yarns 10A in each of which an expanded graphite tape 30 is bent so as to contract in the width direction, and both end portions 31 in the width direction of the bent expanded graphite tape 30 are folded back, or braiding yarns 20A in each of which at least an outer end portion 31' in the width direction of a twisted expanded graphite tape 30 is folded back.
Patent TW-I232849-B (TW)
Title: Exchanged zeolites X, in particular exchanged with lithium, their process of preparation and their use as adsorbents of nitrogen in the separation of the gases of the air
Inventor: MASINI JEAN-JACQUES
IPC: C01B39/02
Filed: 2001-01-04
Granted: 2005-05-21
Abstract: The present invention relates to zeolites X which have been exchanged with lithium and di- and/or trivalent cations. According to the invention there is provided an X type zeolite having an Si/Al atomic ratio of less than 1.5, the exchangeable cations of which comprise, referred to as equivalents, from approximately 50 to approximately 95% of lithium ions, from approximately 4 to approximately 50% of trivalent aluminium, scandium, gallium, iron (III), chromium (III), indium, yttrium, lanthanide or rare earth metal ions, or a mixture thereof, and/or of divalent calcium, strontium, zinc, copper, chromium (II), iron (II), manganese, nickel or cobalt ions, or a mixture thereof, and 0 to approximately 15% of sodium, potassium, ammonium or hydronium ions, or a mixture thereof, which is capable of being obtained by a process comprising (a) suspending the zeolite in water, (b) exchanging the exchangeable cations of the suspended zeolite with one or more di- and/or trivalent ions by simultaneously and/or successively contacting in a mixer, the suspension with one or more solutions comprising compounds of the di- and/or trivalent ions, and (c) exchanging the exchangeable cations of the zeolite resulting from stage (b) with lithium. The zeolites according to the present invention have improved thermal stability and crystallinity with respect to zeolites of the prior art with the same degree of exchange of lithium and of di- and/or trivalent cations. They are particularly effective as adsorbents of the nitrogen present in various gas mixtures and are well suited to the noncryogenic separation of the gases of the air.
Patent TW-480363-B (TW)
Title: System and method for displaying 3d imagery using a dual projector 3d stereoscopic projection system
Inventor: DIVELBISS ADAM W
IPC: G02B30/25
Filed: 2001-02-02
Granted: 2002-03-21
Abstract: An exemplary embodiment is a system and method for displaying three-dimensional imagery. The system includes an image source a first projector having light emission, a second projector having a light emission and a twisted nematic liquid crystal rotator disposed in the light emission of the first projector. The first projector and second projector are connected to the image source.
Patent TW-477871-B (TW)
Title: Vacuum bearing structure and a method of supporting a movable member
Inventor: RYDING GEOFFREY
IPC: F16C29/02
Filed: 2001-06-04
Granted: 2002-03-01
Abstract: A vacuum bearing structure comprises a combination of a planar gas bearing with a differentially-pumped vacuum seal. The bearing surface and the vacuum seal surfaces are formed of a porous material divided into a first outer region through which bearing gas can percolate to provide support and an inner second region providing the vacuum seal. An exhaust groove separates the two regions so that bearing gas can flow to atmosphere. The resulting structure can operate at a lower fly height to reduce loading on the differentially-pumped vacuum seal. The structure is particularly useful for motion feedthroughs into vacuum processes such as ion implantation.
Patent TW-555780-B (TW)
Title: Manufacturing method of reducing cyclic oligomer content in polyester
Inventor: JEN ZO-CHUN
IPC: C08G63/78
Filed: 2001-03-19
Granted: 2003-10-01
Abstract: This invention relates to a manufacturing method, in a production process of polyethylene terephthalate (PET), of effectively inhibiting the generation quantity of cyclic oligomer in ester pellets and further capable of reducing cyclic oligomers generated in back stage melting process by adding a substance of the following structure.