Patent GB-1071692-A (GB)
Title: Digital signal processing system
IPC: G06F7/02
Filed: 1964-06-24
Abstract: 1,071,692. Digital data stores. SOCIETE NOUVELLE D'ELECTRONIQUE ET DE LA RADIO-INDUSTRIE. June 24, 1964 [July 1, 1963], No. 26108/64. Heading G4C. [Also in Division H4] In a system for processing a train of signals, the signals are quantized with respect to time whereby each signal contains a plurality of digits in respective digital positions, the sequential digits of each quantized signal are serially recorded in a matrix (which may be a single row) of two-state memory elements, and the reading out from the matrix is so timed relative to the recording operation that each digit is read out substantially simultaneously with the recording of a digit having a position in the incoming signal that is earlier than the same digit in the previous recorded signal by a predetermined amount, whereby a digit read out from the matrix is passed to an output device at the same time as the same or another digit in the next signal is applied directly to the output device. The invention is particularly described as applied to echo or responder signals received by a pulse radar, for eliminating spurious or noise signals. General.-Digitized pulse radar receiver output signals are recorded in a memory (3, Fig. 1) having one or more ferrite matrices (N) and having recording-address (5) and read-address (6) circuits controlled by clock pulses synchronized by the radar trigger pulse (E 2 ). Considering the case of a single matrix the over-all initial binary state of its register elements represents the content of the digitized radar signal in the preceding pulse repetition period. (p.r.p.); as the radar signal is currently received each digit is recorded in a successive register stage in place of the extant digit and concurrently the read-address circuit causes serial read-out of the recorded signal as a binary voltage via a " logic decision " circuit (9) to an AND gate (1) fed also with the radar video signal. In accordance with the invention means are provided whereby each of the digits read out from the matrix is derived from a register stage displaced by a prescribed number of positions, e.g. selected to correspond to the inevitable time lag involved in recording. For use in a secondary radar system in which a plurality of different kinds of coded interrogation signals are transmitted to evoke automatic response signals from an airborne transpondere.g. codes which respectively call for information relating to aircraft altitude and speedcorresponding numbers of matrices are utilized, the content of a first one being transferred to a second concurrently with recording of incoming signals on the first and &c. For example if the incoming signal pattern is I 0 , J 0 , K 0 , I 1 , J 1 , K 1 , I 2 , J 2 , K 2  . . . , the I, J and K signals representing respective first, second and third parameters, during reception of signal I 1  at the apparatus input the content of the third matrix corresponds to signal I 0  and the signals I 0 , I 1  are compared bit-by-bit in the AND gate. For response signals of common significance, e.g. in a " de-fruiting process, three consecutive response signals can be compared utilizing two matrices; the contents of both matrices are read out simultaneously, with the desired amount of lead relative to recording, and applied to a coincidence gate the output from which is fed to the AND gate for comparison with the incoming signal. Detailed arrangements. Figs. 2, 2a.-A radar system provides a train I 0 , I 1 , I 2  . . . of similarly-coded response signals each consisting of eight code positions, each position containing a binary information digit, and two successive signals are compared. A keying pulse KP triggers clock circuit 7. Memory 3 is a single register of ferrite cores 3 1  . . . 3 8  as two-state elements. Recording wire 4 is threaded in series through all cores and is connected to digitizer 2. The recording-address system includes a binary counter 50 followed by a binary matrix network 59, the stages of the counter receiving shift pulses from clock circuit 7. Thus line 591 is energized for pulse position 1 of the I signal, line 592 for pulse position 2 and so on. Recording gates 51 . . . 58 each comprise a two-input AND gate. The read-out address system is similar, 60. . . 69, but each read gate has its output connected to a wire displaced two core positions ahead. To avoid the loss of the first two bits of the signal the output of an AND gate 27 is fed to a bistable circuit 37 the output from which supplies one input of an AND gate 47 having as its other input the initial clock pulse C 1  and a similar combination 28, 38, 48 is connected to record-gate 58 and to receive the second clock pulse C 2 . The outputs from AND gates 47, 48 are combined with the output of read wire 10 by an OR gate 90. In a further embodiment three successive response signals are compared utilizing three ferrite registers (Fig. 3). In another embodiment, for use with interleaved pulse trains In, J n , K M , three registers are provided for the I, J, K signals respectively (Figs. 4, 4a). In an alternative arrangement of recording and addressing, each register core (3 1  ... 3 8 , Fig. 5) is associated with a corresponding single record-and-read address wire (101 . . . 108), each wire being connected to the the outputs of respective gates (111 ... 118 and 121 ... 128) and to the inputs of further respective gates (131 . . . 138, 141 . . . 148). One set of gates (111 . . . 118) has first inputs connected to a positive polarity source and second inputs connected to related recording lines (591 . . . 598). In operation energization of a recording line ""enables " corresponding gates to pass a unidirectional current to earth via a record-and-read address wire ; when a reading line (e.g. 697) is energized a pair of gates are " enabled "'to effect reading of a recorded bit into the read wire (10).