Patent GB-1360470-A (GB)
Title: Computer input-output chaining system
IPC: G06F13/12
Filed: 1971-12-03
Abstract: 1360470 Data transfer systems RCA CORPORATION 3 Dec 1971 [11 March 1971] 56201/71 Heading G4A Blocks of data words are stored in corresponding blocks of memory locations, which blocks of locations may be located anywhere within the memory, a dedicated counter initially stores the address of a first location in a list of addresses which is used to sequentially address a plurality of data address counters each of which initially stores the memory location address of the first data word of a corresponding block and is used to sequentially address the words of that block. After a data channel between the memory and an I/O device via an I/O controller has been established by a processor, transfer of a plurality of blocks of data words can thus take place in a predetermined order without further recourse to the processor (called chaining). Output transfer (1).-A chaining output command from the processor over bus 5 to CU in the I/O controller causes FF-I to be set and FF-V to be reset. (2) CU sends a data channel request to the processor which grants the request to establish the channel. (3) A wired-in address WA is sent over address bus AB to the processor to address the dedicated counter DC, Fig. 1b, corresponding to the I/O controller. All counters shown are in fact memory word locations. Counter DC comprises a pair of counters LAC, BC which are addressed sequentially. The addressed counter LAC contains the address of the first word in a list LA and this word which represents the address of a pair of counters PC for block A, is transferred over data bus DB to an address register AR in the I/O controller. LAC is then incremented and BC decremented from their initial values determined by the program. FF-II is then set and FF-III reset. (4) Steps (2), (3) are repeated, but now, since FF-II is set, the address in AR is used to address the counter PC for block A, this counter comprising the sequentially addressed counters DAC, WC. Counter DAC contains the address of the first data word in block A and this word is addressed and transferred over DB, through gate K to the I/O device which returns a data accepted signal. DAC is incremented and WC decremented for each word transferred until WC reaches zero and produces an overflow signal to set FF-III followed by reset of FF-II in the I/O controller. (5) Steps (2) and (3) are repeated to again transfer the wired-in address WA to address LAC which this time addresses the second word in list LA to obtain the address of counter PC for block B and transfer it to address register AR. (6) Step (4) is repeated to transfer block B to the I/O device. A further repetition of steps (2)-(4) causes transfer of block C, but during this operation BC overflows to set FF-IV to terminate the operation when the last data word of block C has been accepted by the I/O device. An earlier termination may be caused if any data word in blocks A-C contains an end of text control character EXT. In addition, less than a complete block may be accessed by including a U.S. control character in the last data word to be transferred from that block, monitor M responding to this character to initiate addressing of the next block or termination of the operation. Operation with more than one I/O controller.- A separate counter DC, PC and list LA is dedicated to each controller, this enabling all controllers to share common data block locations in memory, e.g. one controller may receive blocks A, B and D while another receives blocks A, D and C in that order. Input transfer.-A data channel request is sent to the processor from the I/O controller in response to a data ready signal from the I/O device. FF-V is set to close output gate K and enable input gate Y. Transfer proceeds in a similar manner to the output operation (in the reverse direction), but provision is made to interrupt the processor if the available space in memory is exhausted whereby the processor can allocate more space before the transfer is continued. Normal transfer without chaining.-In this mode the I/O controller is only able to sequentially address the locations of one data block, each new block requiring a fresh initialization procedure to be performed.