Patent GB-819031-A (GB)
Title: Improvements in or relating to electronic pulse delay apparatus
Inventor: WILLIAMS NIGEL ARTHUR FREDERIC
IPC: H03K5/156
Filed: 1955-08-25
Abstract: 819,031. Pulse circuits. INTERNATIONAL COMPUTORS & TABULATORS Ltd., [formerly BRITISH TABULATING MACHINE CO. Ltd.]. July 13, 1956 [Aug. 25, 1955], No. 24460/55. Class 40 (6). In a pulse delaying and shaping circuit clock pulses are applied via a gate to a pulse generator which generates a pulse having a leading edge coincident with the trailing edge of the applied pulse, the pulse then being lengthened by a given amount by a delay device. Fig. 1 shows a pulse delaying and shaping circuit to which a distorted input pulse, Fig. 2A, and a source of clock pulses, Fig. 2B, are applied via an AND gate comprising rectifiers 1, 2 to the grid of a normally conductive tube 5. During the coincidence of positive pulses from the two sources during the time period t to 0, Fig. 2, the AND gate passes an output pulse, Fig. 2C, to the grid of tube 5 to. cause it to conduct so that the heavy damped " ringing " circuit 7, 8 which has a period of 2t produces an output wave, Fig. 2D, having a positive pulse of duration t. The first negative pulse generated is eliminated by diode 11 so that the positive pulse occurring during the time period 0 to + t, Fig. 2, has a leading edge coinciding with the trailing edge of the timing pulse, Fig. 2C. This pulse is applied to an opencircuited delay line 13, 19 so that a positive pulse, Fig. 2F, is generated having a duration 2t. This pulse is clipped and limited by the rectifier 22 and the cathode follower stage 17 to produce an output pulse at its cathode, Fig. 2G. Fig. 3 shows a modification arranged for distributing a succession of pulses sequentially to a plurality of output points. Each circuit 26 1 ... 26x has an input gate 27 1 , 27 2  . . . 27x equivalent to the AND gate of Fig. 1 and an output line 2 8 1  ... 28 x . The output of each circuit 26 except the last one is also connected to the input of an OR gate 29 the output of which is connected through an inverter 30 to control the input gate 27 1 . Timing pulses are applied in common over line 31 to all the gates 27, gate 27 1 , is held open by inverter 30 in the absence of an output from OR gate 29, the remaining gates are closed. The first clock pulse thus passes gate 27 1  to produce an output on line 28 1  which is delayed with respect to the input clock pulse by one clock pulse period, this operates OR gate 29 to produce an output which through inverter 30 closes gate 27 1  to the second clock pulse. The delayed output also opens gate 27 2  to this pulse so that the cycle is repeated until the xth pulse passes through gate 27x to give an output on line 28x, the (x + 1) clock pulse being applied through gate 27 1  to the first circuit. Fig. 4 shows an arrangement in which the clock pulses are applied to control a circuit which produces trains of pulses at intervals spaced by multiples of the duration of one such train, thus when controlling a computer such an arrangement may produce a word length block of pulses one every y word times. In Fig. 4 block 26 denotes a circuit as described with reference to Fig.. 1. The input gate 27 1  is controlled by an OR gate 32 1  which in turn receives the outputs of two further gates 33 1  and 34 1 , gate 33 1  is controlled by clock pulses via inverter 35 from input line 36 and the output of its associated circuit 26. Gate 34 1  is controlled by the master clock pulse on line 36 and also via inverter 30 by the output of OR gate 29 which receives the outputs of all circuits 26 except the last one 26y. The gate 27 receives clock pulses from line 31 and when the first clock pulse is applied to gates 33 1  and 34 1  the latter applies an output to OR gate 32 1  which opens gate 27 1  and passes the clock pulse to circuit 26. The output of 26 passes through gate 33 1  and OR gate 32 1  thus allowing the next clock pulse through gate 27 1 , the cycle repeating until the next clock pulse appears on line 36. The gate 26 also acts as described in connection with Fig. 3 to open gate 34 2  and via OR gate 29 and inverter 30 to close gate 34 1 , The output pulse from the last clock pulse to enter the first stage via gate 34 1  cannot pass gate 33 1  so that the cycle is broken and due to the output of OR gate 29 further clock pulses are ineffective on this stage until the last or y stage has delivered its block of output pulses, thus on output 28 1 , for example, the stage is generating a group of pulses once every y master clock pulses.