Patent GB-1162422-A (GB)
Title: Editing Display System
Inventor: VOSBURY MICHAEL KENNETH
IPC: G06F17/24
Filed: 1966-10-26
Abstract: 1,162,422. Cathode-ray tube displays. SANDERS ASSOCIATES Inc. 26 Oct., 1966, No. 48050/66. Heading H4T. In a cathode-ray tube display system digital signals defining characters to be displayed and the locations at which they are to be displayed are stored at accessible addresses in a digital memory the contents of which may be modified in response to externally supplied commands and the output signals from which are utilized to control the display. The signals are derived from a computer and from a keyboard which also provides command signals utilized for editing purposes. This involves the insertion, deletion and alteration of characters as viewed on the display and the edited data may be " sent-back " to the computer as new data. To facilitate editing a visible marker is produced on the display at the character positions at which editing is to be effected. When characters are inserted or deleted the spacing between the digital signals in the memory, and the spacing between the displayed characters is altered accordingly. Fig. 1 shows the general arrangement of an embodiment of the invention. As shown, digital character signals and character position signals derived from a computer 19 and from a keyboard 17 are fed to an IN-OUT register 32 and in accordance with the mode of operation, which is controlled by a unit 33, are then fed (1) to a Holding register 30 and thence to an instruction register 34 or (2) to the computer 19 for storage and then retransmission to registers 32, 30 and 34 or (3) from register 30 to register 32 and thence to computer 19. When the signals reach register 34 the instruction signals (i.e. command signals) from the keyboard or from the computer included therein are detected by decoder 38 and caused to be supplied from 34 to an Operations register 40 from which they are supplied to the decoder to produce output signals fed to a logic unit 42 controlling the required functions. These include functions similar to those performable on a typewriter such as " carriage returns," i.e. shift to the beginning of the next line, tab, forward space &c. When the signals in register 34 are to be loaded into the memory, they are transferred to a buffer register 36 and thence to a recirculating memory 12 comprising a magnetostrictive delay line 18 and registers 20, 22, 24 and 26. As the signals pass through register 20 they are continuously scanned by Display Controller 41 which supplies the character representative signals via register 43 to produce the actual characters on the CRT 28 at positions determined by the location signals supplied from controller 41 to line and space counters 44, 46, respectively. The whole operation is controlled by a clock pulse distributer 48 which, in a cycle of twenty-seven microseconds provided twenty-seven successive output pulses, each of one microsecond duration on separate lines and a train of pulses of one - quarter - microsecond duration occurring once every microsecond, the timing functions being provided by coincidence of each of the former pulses with one of the latter pulses. Each character is assigned nine bits each of one microsecond length but because the display unit 29 requires more than nine microseconds to generate a character the latter are stored in memory 12 (which has a capacity of about 1000 characters) with a spacing of eighteen microseconds which is employed to store other characters to be displayed later. The address in memory 12 of each character passing though register 20 is indicated by a register 126 which comprises a counter having a capacity equal to the number of character addresses in the memory and the contents of which are increased by " one " at the beginning of each cycle of the clock pulse distributer. At maximum count register 126 resets to zero and commences counting again. The main purpose of this register is to designate " first " and " last " addresses in memory 12 so that during certain editing operations in which the controller 16 continues to the last address in the memory a signal from register 126 prevents the operation from continuing through the first address which follows the last address in memory 12. The marker generator 27 is similar to register 126, the count being increased by " one " for each clock cycle and reset to zero at the end of a complete cycle of the memory if not previously reset by one external signal. This occurs under the control of controller 16 when the position of the marker is to be changed, the actual signal produced in generator 27, when so reset, being supplied to the display via the controller 41. The complete operation of the arrangement is described in detail with reference to block circuit diagrams and decision tables are given for the various functions performed.