Patent GB-1015176-A (GB)
Title: Parity checking system
IPC: G06F11/10
Filed: 1963-04-29
Abstract: 1,015,176. Computing check symbols. SPERRY RAND CORPORATION. April 29, 1963 [May 9, 1962], No. 16661/63. Heading G4A. In an arrangement for generating a parity bit for a N-digit binary number, (1) the number is shifted one place to the left, the result being added without carries to the original number to produce a first result; (2) the first result is added without carries to the first result shifted right two places to produce a second result; (3) the first result is added without carries to the second result shifted right two places to produce a third result; (4) selected digits of the third result are applied to a translator circuit to provide an output which is the required parity of the original N-digit number. The arrangement described employ the same basic circuits as the multiplication apparatus described in Specification 1,015,175, the present Specification describing suitable control circuits for effecting parity generation. The circuit shown, Figs. 1A-1C, is effective under the control of a control circuit, Figs. 2A, 2C (not shown), to form the " logical product " P of two 36-bit binary numbers M, N, i.e. the 36-bit number each digit of which is " 1 " if and only if both corresponding digits of M and N are " 1," the circuit then calculating a parity bit for the number P. As described in Specification 1,015,175, the arithmetic operations are carried out by means of subtractive logic in " half-subtractor " circuits called A* B* halfsubtractor, Fig. 1B, and AB halfsubtractor, Fig. 1C, one of the operands being supplied to each circuit in complement form so that the output is effectively to produce " sum " and " carry " digits, although these are called " difference " and " borrow " digits because of the subtractive nature of the logic. The " half-subtractor " circuits are effectively full subtractors having for each binary order three inputs, but are distinguished from conventional full subtractors in that the carry input is obtained from a previous operation. Operation-(1) Formation of " logical product."-The first 36-bit operand M is entered in an " X " register, Fig. 1B, and transferred via an " X* " register, Fig. 1B, the A* B* halfsubtractor and an " A* " register, Fig. 1A, to a " borrow-pyramid and main adder," Fig. 1A. The second operand N is then entered into the X register and applied via an " XS " register, Fig. 1C, to an " A " register, Fig. 1C. The first operand M is now applied from the main adder to the A register to reset to " 0 " any stage of the A register corresponding to a " 0 " output of the main register. The A register now stores the " logical product " P of M and N, for which it is required to compute a parity bit. (2) Computation of parity bit.-The value P is transmitted to the X register and so is stored in the A and X registers at the commencement of the computation. A B* (borrow) register, Fig. 1A, is filled with all ones and the contents of the X register is transferred with a one-bit left shift to the X* register. The A* B* halfsubtractor now receives as inputs (1) the complemented value P left-shifted by one place from the X* register, (2) the value P directly from the A register, (3) zeros from a B (borrow) register, Fig. 1C, and produces a first result which is complemented in the main adder and borrow pyramid, the result being stored in the A register and then transferred to the X register. The contents of the A* register is now applied right-shifted two places, together with the contents of the X register to the AB halfsubtractor, Fig. 1C, where a further addition takes place to produce a second result which is entered right shifted by two places into the A register. The first result in the X register is now added in the A* B* half-subtractor to the shifted second result in the A register to produce a third result. The output from stages 01, 07, 13, 19, 25 and 31 of the A* register is now applied to a translator 224, Fig. 1A, which generates a parity bit therefrom, which bit represents the required parity of the logical product P.