Patent GB-1108805-A (GB)
Title: Improvements in or relating to electronic data processing systems
IPC: G06F12/14
Filed: 1965-03-29
Abstract: 1,108,805. Electric digital calculators. INTERNATIONAL BUSINESS MACHINES CORPORATION. 29 March, 1965 [6 April, 1964], No.13161/65. Heading G4A. In an electronic data processor, a central processing unit (CPU) is connected to input/ output (I/O) devices through control units, each of which stores an address identifying each of the I/O devices connected thereto, the CPU initiating data transfer between itself and an I/O device by specifying the address of the I/O device, and each control unit having means for compairing the specified address with each address stored in it, data transfer between the CPU and any of the other control units being prevented on equality being detected by one of the comparison in a given control unit. A set of lines is provided from the CPU to all the control units in common, comprising a 9-line " bus out " (8 data, plus parity) from the CPU to the control units, a similar " bus in " in the opposite direction and other in and out lines as mentioned below. Operation is described with respect to a card reader-punch I/O device but tape readerpunches and printers are also mentioned. A character to be punched, received on " bus out " at a control unit is parity-checked and stored in a buffer register from which it is passed via a data register and an 8-bit-to- Hollerith translator to the punch drivers. Punch echo signals are checked for validity (i.e. legal character) and passed via a Hollerith-to-8- bit translator for comparison in a " bit match " circuit with the character in the data register. The results of the parity check, validity check and bit match are stored in sense latches (see below). A character read from a card is passed via the Hollerith-to-8-bit translator and the data register to the buffer register from which it may be passed to " bus in." Other sense latches are provided to indicate overrun and an invalid command (from the CPU). A sense command from the CPU causes the contents of the sense latches to be placed on " bus in." Other commands are read, write and test I/O, the last sending to the CPU the contents of status latches in the control unit. The status latches specify (or not) end received, end, unit free, invalid command, data error, exceptional condition. The control units are called repetitively in turn by a pulse on a " select out " line from the CPU which, on reaching a given control unit enables a given I/O device connected to the latter to be selected by the presence of the device's address on " bus out " or to seize the channel to the CPU for its own purposes, the pulse on " select out " being passed to the next control unit in line if and only if neither of these events happens. The I/O devices may operate in " interleave mode " wherein a device, having sent or received one character on the channel, allows subsequent I/O devices to obtain control, or in " burst mode " wherein control of the channel is retained until a block of characters has been sent or received. Selection of an I/O device by the CPU results in its address being placed on " bus in " by its control unit for comparison in the CPU with the required address, as a check. The contents of the status latches are also sent in. Transmission of address, command or status information on " bus in " or " bus out " is is accompanied by the application of a pulse to a corresponding tag line, e.g. " address in." During operation, the control unit and CPU signal each other alternately on these tag lines and other lines to cause the correct sequence of operation. Lines are also provided to send clock pulses from the CPU to the I/O devices.