baber/WOPTO huggingface dataset:
Patent TW-513349-B (TW)
Title: Liquid discharge head, manufacturing method thereof, and microelectromechanical device
Inventor: OZAKI TERUO
IPC: B41J2/16
Filed: 2000-06-03
Granted: 2002-12-11
Abstract: There is provided a liquid discharge head comprising a substrate, a ceiling plate connected to the substrate, a liquid flow path formed between the substrate and the ceiling plate, and a cantilever-like movable member having a fixed end fixed to the substrate and a free end extending into the liquid flow path, wherein the movable member is formed of a lower protective layer, a heat generating resistive layer, a lower electrode layer, an insulating layer, an upper electrode layer, and an upper protective layer stacked from the side of the substrate in the mentioned order, and wherein application of a voltage to a heat generating portion of the heat generating resistive layer causes bubbling of a liquid in the liquid flow path between the movable member and the substrate to discharge the liquid.
Patent TW-440658-B (TW)
Title: Friction clutch and automatic transmission of automobile using the same and non-stage transmission of automobile, and power distribution device of automobile and power transmission device of motorcycle
Inventor: MIMURA KENJI
IPC: F16D7/00
Filed: 2000-06-20
Granted: 2001-06-16
Abstract: The present invention relates to a friction clutch in which the wear in the sliding state can be reduced and an automatic transmission of an automobile using the friction clutch and a non-stage transmission of an automobile, and a power distribution device of an automobile and a power transmission device of a motorcycle. That is, according to the present invention, an a configuration of making a pair of clutch members opposite to each other in a radial direction with a plurality of rollers held between them, an angle of a turning axis of each roller relative to the rotation axis of a clutch member is made more than 10 DEG and less than 20 DEG, and in the meantime, the angle of the turning axis of each roller relative to the plane including the rotation axis of the clutch member is made more than 25 DEG and less than 90 DEG, so that a stable frictional force may be generated at al times. In this case, when a load in an axial direction is added to the clutch member, each roller generates sliding friction while turning, and therefore, a wear is extremely smaller than that of a structure of bringing the respective fellow clutch plates into surface contact with each other like a multiple disk clutch.
Patent TW-498239-B (TW)
Title: Price determining method for on-line collective transaction
Inventor: GAU SHIN-FU
Filed: 2000-06-27
Granted: 2002-08-11
Abstract: The invention provides a price determining method for on-line collective transaction, allowing a buyer to go through a web site to conduct on-line transaction in which the web site stores the merchandise-related data and the merchandise-related data contains different pricing classes of the merchandise and the corresponding supply volume range. The lower the pricing class is, the higher the corresponding supply volume is. Buyer can target at the current deal price classes to directly place purchase order or targets at the prices lower than the current deal price classes to wait. The method includes the following procedures: showing the transaction data of a merchandise for buyer's reference; receiving the buyer's purchase order or offer concerning a certain price class; and re-determine the new deal price class.
Patent TW-466396-B (TW)
Title: Liquid crystal display and an information processing apparatus having the same
Inventor: KANG JUNG-TAE
IPC: G02F1/13
Filed: 2000-07-21
Granted: 2001-12-01
Abstract: A liquid crystal display capable of being minimized, in which a backlight assembly has a light source portion for generating light, a liquid crystal display panel receives the light from the backlight assembly to display images. A mold frame for sequentially accepting the backlight assembly and liquid crystal display panel is formed to be gradually thinner as further advancing from a first side of accepting to place the light source portion toward a second side opposing to the first side. Also, a chassis coupled to be opposite to the mold frame for closely fixing the backlight assembly and liquid crystal display panel to the mold frame is formed to be gradually thinner as further advancing from the first side of accepting to place the light source portion toward the second side opposing to the first side. Thus, the liquid crystal display can be slimmed.
Patent TW-493302-B (TW)
Title: Using shielding planes to design connectors for both common mode and differential mode
Inventor: LIN GWUN-JIN
IPC: H01R9/11
Filed: 2000-07-25
Granted: 2002-07-01
Abstract: Shielding planes are used in this invention around the outer peripheral of connector to reduce and block the electromagnetic radiation, and it also used as the main ground for design the impedance. This connector is designed to have around 50 ohms for common mode and around 100 ohms for differential mode, so it is very useful for circuits have low voltage differential signal with high frequency transmitted rate and common mode signal together.
Patent TW-526310-B (TW)
Title: Intake control device for engine
Inventor: YAMADA HAJIME
IPC: F02M35/104
Filed: 2000-07-28
Granted: 2003-04-01
Abstract: The object of the motorcycle in accordance with the present invention is to maintain the output performance of an engine at a low speed and meanwhile, effectively reducing intake resistance at high speed rotation range so as to enhance the output performance at high speeds. The technique solution of the present invention is that a small cross sectional area passage 33a and a large cross sectional passage 33b are juxtaposing and arranged in an air filter 17 of an air intake system In mounted to an engine E and comprising an intake control valve 35 for opening/closing the large cross sectional passage 33b. The intake control valve 35 is connected to an actuator 71. The actuator 71 closes the intake control valve 35 when the engine E is in a low speed rotation range and opens the intake control valve when in a high speed rotation range.
Patent TW-473718-B (TW)
Title: Semiconductor memory device
Inventor: HIKIYAMA YOSHIYUKI
IPC: G11C29/50
Filed: 2000-08-16
Granted: 2002-01-21
Abstract: During a burn-in test, a test mode signal TMRS is set to the H level, and word lines WLO to WL3 can be activated by composite gates according to row address signals RA0 to RA3, respectively. Therefore, a potential difference and a high electric field are provided even between word lines WL0, WL2 during the burn-in test. Thus, the defect elimination rate during the burn-in test can be improved.
Patent TW-457561-B (TW)
Title: Film deposition apparatus and method
Inventor: SHINRIKI HIROSHI
IPC: H01L21/316
Filed: 2000-08-30
Granted: 2001-10-01
Abstract: A film deposition apparatus (2) forms a PZT film at a high deposition rate under a low temperature by using a single showerhead (50) throughout the deposition process. Process gases including a raw material gas and an oxidant gas are introduced into a process chamber (4) in which a wafer (W) is accommodated. The process chamber (4) is maintained at a predetermined vacuum during the film depositing process. A gas injection surface (57) of the shower head (50) from which the process gases are injected is divided into an inner zone (84) covering a center portion of the wafer (W) and an outer zone (86) surrounding the inner zone (84). The raw material gas is separately injected from the inner zone (84) and the outer zone (86), and the oxidant gas is separately injected from the inner zone (84) and the outer zone (86).
Patent TW-I225045-B (TW)
Title: Novel aminodicarboxylic acid derivatives having pharmaceutical properties
Inventor: ALONSO-ALIJA CRISTINA
IPC: A61K31/195
Filed: 2000-09-11
Granted: 2004-12-11
Abstract: The present invention relates to the use of compounds of the formula (I) and their salts and stereoisomers, and to the preparation of medicaments for the treatment of cardiovascular disorders.
Patent TW-I289140-B (TW)
Title: Process to prepare aryltriazolinones and novel intermediates thereto
Inventor: GOUDAR JAIDEV S
IPC: C07C257/22
Filed: 2000-10-05
Granted: 2007-11-01
Abstract: A process is described for preparing 1-aryltriazolinones of formula I useful in the production of commercial herbicides: by (i) carbonylating an amidrazone of formula (A) with one or more carbonylating agent, or by (ii) condensing a hydrazonoyl derivative of formula (A) with one or more ring-forming agent, wherein formula (A) is, where W, X, Y, Z, and R1 are fully described herein. Preferred are those where W is halogen or -NHR where R is hydrogen or haloalkyl; X and Y are independently selected from hydrogen, chloro, or fluoro; Z is hydrogen, bromo, iodo, nitro, amino, or methylsulfonylamino; and R1 is methyl. Certain compounds of formula (A) are novel compositions of matter. The process as described herein has utility in providing compounds of formula I in unexpectedly high yield and purity.
Patent TW-501212-B (TW)
Title: Failure analysis method of metal delayer
Inventor: JOU YE-NING
IPC: H01L21/66
Filed: 2000-11-14
Granted: 2002-09-01
Abstract: This invention provides a failure analysis method of metal delayer to open the sealing of via using FIB to remove the second metal layer of the dielectric layer region of an integrated circuit for multi-layer metal interconnect integrated circuit (comprising a first metal layer, a dielectric layer, a second dielectric layer, some barrier layers and a via hole). Then, at the opened via hole, an oxide material is used to fill half and above of the via hole region through the application of FIB. An etching solution consisting of hydrochloric acid and hydrogen peroxide with a ratio of 1:1 and an etching solution of sulfuric acid and hydrogen peroxide with a ratio of 1:1 are employed individually to remove the second metal layer and the barrier layers. Finally, the dielectric layer is removed until the first metal layer is exposed. The inventive method can prepare a test sample without damaging the metal awaiting test during metal delayer, and prevent influencing failure analysis results.
Patent TW-479037-B (TW)
Title: Battery arrangement structure of motorcycle
Inventor: KIKUNO JUNJI
IPC: F02B61/02
Filed: 2000-11-14
Granted: 2002-03-11
Abstract: A lower cover 64 of the seat of a motorcycle is formed into a tapered shape in plan view by arranging a small battery 63 smaller than a luggage box 61 in front of the luggage box 61 and by surrounding the battery 63 and the luggage box 61 in this order with the seat lower cover 64. To increase the freedom of design by tapering the width of the seat 62 situated above the seat lower cover 64 in accordance with the need, for example, in other words, by tapering the seat lower cover 64 in plan view.
Patent TW-487990-B (TW)
Title: Method and apparatus for reducing fixed charges in a semiconductor device
Inventor: HUANG JUDY
IPC: C23C16/42
Filed: 2000-11-21
Granted: 2002-05-21
Abstract: A method and apparatus for reducing trapped charges in a semiconductor device having a first layer and a second layer, said method comprising the steps of providing said first layer, flowing a deposition, a dilution and a conversion gas upon said first layer thereby forming a transition layer, phasing out said flow of conversion gas and forming said second layer upon said transition layer. The deposition gas, dilution gas and conversion gas are preferably trimethylsilane, helium and N2O respectively. The method is performed via chemical vapor deposition or plasma enhanced chemical vapor deposition. The apparatus has a first insulating layer, a transition layer disposed upon said first layer and a second insulating layer disposed upon said transition layer. The transition layer improves the adhesion between said first insulating layer and said second insulating layer. A reduction in the amount of electrical charges (i.e., ions, electrons or the like) trapped between layers of deposited material improves the integrity and quality of devices formed from such layers.
Patent TW-I269538-B (TW)
Title: An RF front-end with a multistage stepdown filtering architecture
Inventor: ZARGARI MASOUD
IPC: H03D7/16
Filed: 2001-02-06
Granted: 2006-12-21
Abstract: A radio-frequency (RF) front-end is described. In one embodiment, the RF front-end comprises a low noise amplifier (LNA), a first mixer and an I/Q quadrature mixer. The LNA amplifies a received signal at a carrier frequency, the LNA having inductive loads. The first mixer is coupled to the low noise amplifier and mixes an amplified received signal with a first local oscillator (LO) signal to down convert the amplified received signal to an intermediate frequency (IF). The first mixer has inductive loads. The first frequency is related to the carrier frequency such that an image channel associated with the carrier and the LO frequency is outside the bandwidth of the inductive loads of the LNA. The I/Q quadrature mixer stage has a second mixer and a third mixer coupled to the first mixer. The I/Q quadrature mixer converts the amplified received signal at the IF to I and Q signals using a second LO signal related to the first LO signal.
Patent TW-471136-B (TW)
Title: Manufacturing method for MOS transistor of embedded memory
Inventor: CHIEN SUN-CHIEH
IPC: H01L21/8229
Filed: 2001-01-19
Granted: 2002-01-01
Abstract: The present invention provides a manufacturing method for MOS transistor of embedded memory, which includes the following steps: sequentially forming a first dielectric layer and an undoped polysilicon layer on the surface of the semiconductor chip with a memory area region and a periphery circuit region defined; then, doping the undoped polysilicon layer on the memory array region and forming a passivation layer on the surface of the semiconductor chip; conducting a first photolithography and etching process (PEP) to etch the passivation layer and the doped polysilicon layer on the memory array region for forming a plurality of gates; forming the lightly doped drain (LDD) around each of the gates; forming a silicon nitride layer and a second dielectric layer on the surface of the semiconductor chip; removing the second dielectric layer, the silicon nitride layer and the passivation layer on the periphery circuit region; finally, conducting a second PEP to etch the undoped polysilicon layer on the periphery circuit region for forming a plurality of gates; then, forming the LDD, the spacer, and the source/drain (S/D) of each of the MOS transistors in the periphery circuit region.
Patent TW-I290252-B (TW)
Title: Liquid crystal display device
Inventor: KUBO MASUMI
IPC: G02F1/1343
Filed: 2001-02-23
Granted: 2007-11-21
Abstract: The present invention provides a liquid crystal display device having a high display quality. The liquid crystal display device displays an image by applying a voltage by a first electrode and a second electrode across a liquid crystal layer which takes a vertical alignment in the absence of an applied voltage. The first electrode includes a lower conductive layer, a dielectric layer covering at least a portion of the lower conductive layer, and an upper conductive layer provided on one side of the dielectric layer which is closer to the liquid crystal layer. The upper conductive layer includes a first opening, and the lower conductive layer is-provided so as to oppose at least a portion of the first opening via the dielectric layer.
Patent TW-533418-B (TW)
Title: Integrated memory and method to function-test of memory-cells of an integrated memory
Inventor: DAEHN WILFRIED
IPC: G01R31/28
Filed: 2001-04-03
Granted: 2003-05-21
Abstract: An integrated memory is described, which has addressable memory-cells (MC) composed into groups of column-lines (C) and row-lines (R). The address (CADR, RADR) of the memory-cells includes a first-part (CADR1, RADR1), through which the respective groups of the column-lines (C) and row-lines (R) are addressable. The memory-cells (MC) in the cross-region (K) of the two groups (C, R) are sequentially tested on the accuracy by means of a method for function-testing. Then the memory-cells (MC) of the next group (C, R) are tested. In the consistence of the compared 1st address-parts (CADR1 RADR1) of the defect memory-cells, the address of at least one defect memory-cell is continuously processed for evaluation, the addresses of other defect memory-cells are not processed. Thus a great compact of the addresses of the defect memory-cells can be attained.
Patent TW-510024-B (TW)
Title: Process for reduction of orientation-dependent oxidation in trench structures and semiconductor memory device produced thereby
Inventor: GRUENING ULRIKE
IPC: H01L27/108
Filed: 2001-04-27
Granted: 2002-11-11
Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar. The isolation collar oxide layer is disposed over an isolation collar nitride interface layer between the isolation collar oxide layer and the trench sidewall, the gate oxide layer is disposed over a gate nitride interface layer between the gate oxide layer and the trench sidewall, or both.
Patent TW-554031-B (TW)
Title: A high efficiency fluorescent material
Inventor: KOBUSCH MANFRED
IPC: C09K11/62
Filed: 2001-06-08
Granted: 2003-09-21
Abstract: The sulfogallate (Thiogallate) is selected preferably in sulfur-bearing metallic (Thiometallate) fluorescent material, and the corresponding chemical formula is (AS). W(B2S3), wherein A is at least one bivalent positive ion in Mg, Ca, Sr families, B is at least one trivalent positive ion in Al, Ga, Y families, and the factor W is in the range of 0.8 <= W <= 0.98 or 1.02 <= W <= 1.2.
Patent TW-I237631-B (TW)
Title: Improved process for the purification and recovery of acetonitrile
Inventor: GODBOLE SAMJAY P
IPC: C07C253/34
Filed: 2001-07-12
Granted: 2005-08-11
Abstract: A method for the purification of crude acetonitrile comprising distilling the crude acetonitrile in a first fractional distillation column at below atmospheric pressure, withdrawing a first side draw fraction comprising acetonitrile, distilling the first side draw fraction in a second fractional distillation column at super atmospheric pressure, and withdrawing from the second distillation a second side draw fraction comprising purified acetonitrile.
Patent TW-594891-B (TW)
Title: The adhesive-attached tape for semiconductor substrate and using them for the copper-affixed laminates
Inventor: OGURA MIKIHIRO
IPC: H01L23/31
Filed: 2001-08-22
Granted: 2004-06-21
Abstract: The adhesive-attached tape of the present invention for semiconductor substrate characterizes in consisting with the insulated film layer having the following characteristics (1) and (2) and the laminate having more than one semihardened adhesive layer. (1) The coefficient of linear expansion in width direction (TD) of film at 50 to 200 DEG C is 17 to 30 ppm/DEG C. (2) The coefficient of tensile elasticity is 6-12 Gpa. By means of the structure, the present invention industrially provides with the adhesive-attached tape suitably for preparing semiconductor apparatus and using them for the copper-affixed laminates, the substrate for semiconductor connection and the semiconductor apparatus, as well as can raise the dependability of the high density packaging semiconductor apparatus.
Patent TW-538121-B (TW)
Title: Solution method for preparing ITO powders
Inventor: LU SHIN-CHUNG
IPC: C09K3/16
Filed: 2001-09-19
Granted: 2003-06-21
Abstract: A solution method for preparing indium-tin oxide (ITO) powders is provided. Different metal compounds are dissolved in water and proper additives respectively to form two solution bodies. Mixing the two solution bodies to form a mixing solution body and then adding some proper additives into the mixing solution bodies to form metal hydroxyl compounds with determined composition. After water washing and filtration, proper additives are added into the solution to peptize the solution. During the peptization process, hydrolysis and condensation reactions occurs between different metal hydroxyl compounds. Solvent of the solution is then removed to form high quality nanometer grade ITO powders.
Patent TW-506077-B (TW)
Title: Control system and its application method
Inventor: CHEN GUO-TZUO
IPC: H01L21/78
Filed: 2001-10-12
Granted: 2002-10-11
Abstract: A control system and its application method are disclosed in the present invention. The invention is utilized in the scribe line of the wafer to control device operation in the scribe line of the control system and its application. Through the use of the control system provided by the invention in the scribe line of the wafer, it is capable of decreasing the number of pads in the scribe line and using a stack type to form the devices in the scribe line. Therefore, much more devices can be placed in the scribe line for testing wafers to increase wafer level testing accuracy such that it is possible to pre-evaluate burn-in time, increase product yield, reduce the production cost and increase the throughput.
Patent TW-530481-B (TW)
Title: Anti-abrasion flat flexible cable structure
Inventor: SHENG KUNG-CHO
IPC: H05K1/00
Filed: 2001-10-19
Granted: 2003-05-01
Abstract: The present invention relates to an anti-abrasion flat flexible cable (FFC) structure applied in a flatbed scanner, which is connected between a circuit board and a carriage and can extend or bend under the scanning flatbed with the movement of the carriage. The FFC structure comprises: a flexible conductor portion with one end electrically connected to the circuit board and the other end electrically connected to the carriage to transmit electrical signal inbetween; a flexible insulator portion wrapped outside the conductor portion to protect the conductor portion; and a flexible spacer adhered to the insulator portion and located between the insulator portion and the scanning flatbed when the insulator portion bends, so as to separate the insulator portion and the scanning flatbed to prevent abrasion damage.
Patent TW-530408-B (TW)
Title: Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof
Inventor: YAMAMOTO MAKOTO
IPC: H01L27/082
Filed: 2001-10-30
Granted: 2003-05-01
Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first isolation region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and on the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first isolation region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region between the first emitter region and the first collector region is distributed such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.