Patent GB-1334000-A (GB)
Title: Multiplex signalling
IPC: H04L5/04
Filed: 1971-10-22
Abstract: 1334000 Multiplex signalling INTERNATIONAL BUSINESS MACHINES CORP 22 Oct 1971 [4 Nov 1970] 49170/71 Headings H4L and H4R When a single channel 1 (Fig. 2, not shown) carries different and simultaneous pulse code patterns of equal time duration from sources D1 to D7 which are amplitude multiplexed to give a single multiamplitude pulse sequence having the same time duration, and this sequence is demultiplexed at receivers CH1, CH2  which recognize their respective code patterns, it is arranged that the different attenuations and delays arising from distribution of the sources D1 to D7 along the channel 1 are compensated by suitable modifications of the timing and amplitude of the source transmissions. The receivers may employ matched filters, and it is stated that the multi-amplitude sequence may be amplitude-limited to give a ternary form signal without loss of correlation at the receivers. The presence of a given pattern in the signal represents " 1 ", and its absence " 0 ". The pulse code transmission from each source is in the form of a seven-bit transorthogonal code unique to that source so that the receiver can identify the source by recognizing its code. Seven sources D1 to D7, each as in Fig. 3, transmit in the same direction over channel 1, to which they are connected by directional couplers 3, to three channel units CH1, CH2, CH3, Figs. 4, 5, which send calling signals over a second channel 2 back to the source units. One channel unit CH3, Fig. 5, generates a synchronizing sequence and sends it in the opposite direction over channel 1 to the other channel units, each as in Fig. 4, and to the sources D1-D7. Each source unit, Fig. 3, contains basic data processing circuits 14 whose output is encoded at 8 and supplied then to a diplexer 6, the received synchronizing signals being conveyed by the diplexer from the coupler 3 to the synch code, decode, and timing circuits 9, 10 which ensure the required in-phase addition of the different code patterns. The latter control the above circuits 8, 14 and also control a demultiplexing circuit and decoder 12 which receives the calling signals from the channel units through another coupler 4 from the second channel 2. In the channel units CH1, CH2, Fig. 4, the arrangement is similar except that the demultiplexer 23 receives its input (from sources D1 to D7) from channel 1 instead of channel 2, and the multiplex-encode circuit 27 feeds the call signals into channel 2. The channel unit CH3 has a similar arrangement to CH1 and CH2 but its synch encode and timing circuits 34, 35 are different (Fig. 11, not shown) and it feeds the synchronizing signal into channel 1. The diplexer is a transistor two-way amplifier (Fig. 7, not shown) including means (256) for adjusting the magnitudes of the different code transmissions to equalize their contributions to the multi-amplitude pulse signal. The multiplex encoders 8, 27, 38 employ a shift register (FSR1, Fig. 8, not shown) having three stages with the outputs of the second and third fed to a mod-2 adder (104) whose output is gated (at 105) to the first stage input. The register is stepped by clock pulses until the three outputs match those of a reference register (RB1) whereupon a comparator (C) responds to reset the circuits. The pulses thereby generated by stage 3 constitute the output (transorthogonally coded) signal which can be changed at will by changing the state of the reference register (RB1). In normal operation this is fixed, but it is possible to allocate more codes if necessary to those source units carrying heavier traffic. The demultiplexer decoders 12, 23, 32 (Fig. 9, not shown) use correlation techniques to detect the presence in a received composite multi-amplitude pulse sequence (at 150) of the various possible transmitted codes, which are supplied in succession to reference terminals (170, 171). Threshold circuits (151, 152) give respective outputs when the multi-amplitude signal is above and below a reference level, and these outputs are compared with the simultaneous bit occurring in the reference code (at 170, 171). Bit matches cause a counter (162) to count up, and mismatches cause it to count down, the resultant count being positive to indicate the presence in the received signal of the reference code, and negative or zero to indicate absence thereof. Latches (186, 185) are operated by AND and OR gates to indicate code match and mismatch respectively, and an " alert " latch 184 warns of possible faults if a preceding count was zero and a new signal is known to have been received (as indicated by setting of a further latch 179). The synch encode, decode and timing circuits 9, 10, 24, 25 of D1-D7, and CH1, CH2 also employ correlation techniques (Fig. 10, not shown); and the synch encode and timing circuits 34, 35 of CH3 employ (Fig. 11, not shown) a main oscillator (254) and a three-stage shift register again connected to a mod 2 adder (250). Instead of a 7-bit code, a 6-bit code may be used in which case the second channel 2 is dispensed with (Fig. 12, not shown); and an arrangement using a 15-bit code is disclosed in connection with Figs. 14, 15, 16 (not shown).