baber/WOPTO huggingface dataset:
Patent TW-I290810-B (TW)
Title: Plasma treatment device
Inventor: SASAKI KAZUO
IPC: H05H1/26
Filed: 2002-09-05
Granted: 2007-12-01
Abstract: To provide a plasma treatment device in which a foreign material can be prevented from being stuck on a dielectric provided between a high frequency antenna and plasma by plasma treatment. A plasma etching device 100 is provided with a high frequency antenna 112, a high frequency power source 160 connected to the high frequency antenna, a susceptor 106 for installing an object to be treated, a dielectric cover 174 provided between the high frequency antenna and the susceptor, a conductor 170 provided between the high frequency antenna and the dielectric, a ground circuit 180 connected to the conductor, an inductance variable inductor 302 provided within the ground circuit and a capacitance variable capacitor 304. By adjusting the inductance or capacitance thereof, the sticking speed of the foreign material to the dielectric cover becomes approximately equal with the sputtering speed of the dielectric cover 174 such that the sticking of the foreign material can be prevented.
Patent TW-593944-B (TW)
Title: Refrigeration system and method
Inventor: TSAI JAU-JR
IPC: F25B1/00
Filed: 2002-10-21
Granted: 2004-06-21
Abstract: The present invention relates to a refrigeration system and method, wherein the system comprises a low temperature brine tank and a warm water tank. A three-way valve is used to connect the brine pipe and piping of the warm water tank. A pump is employed to send the hot water for defrosting to the coil of an evaporator to achieve the function of complete defrosting. The system may be subdivided into several sets to achieve the individual defrosting effect for each compartment of a freezing chamber, to make the device save more power cost and the refrigeration system not necessary to stop operating.
Patent TW-I226516-B (TW)
Title: Process for producing metal microstructure
Inventor: YORITA JUN
IPC: H01L21/48
Filed: 2002-10-25
Granted: 2005-01-11
Abstract: The present invention provides a process for producing metal micro structure by using resin molding (13), which can setup in a mild condition with low damage for the resin molding (13) and a process for producing large exactness metal microstructure (1) by uniform galvanizing. The process for producing metal microstructure according to the present invention comprises: light-sensibility polymer (12) which the chemical component varied by electrical ray, ultraviolet or visible light, a step for forming resin molding layer (2) by fixing the empty pore region (13) with penetrating thickness direction on the electric conductivity substrate (11), a step for exposing the resin molding layer (2) with electrical ray, ultraviolet or visible light, a step for excluding the light-sensibility polymer (12c) after sensitization on the empty pore region of the resin molding (13), and a step for burying the metal (14) by galvanization on the empty pore region of the resin layer (2).
Patent TW-565933-B (TW)
Title: Method of forming ohmic electrode
Inventor: FUDETA MAYUKO
IPC: H01L21/28
Filed: 2002-10-25
Granted: 2003-12-11
Abstract: There is provided a method of forming an ohmic electrode, including the steps of: forming a hafnium layer on a surface of an n type nitride-based compound semiconductor layer to have a thickness of 1 to 15 nm; forming an aluminum layer on the hafnium layer; and annealing the hafnium layer and the aluminum layer to form a layer formed of hafnium and aluminum mixed together.
Patent TW-I226311-B (TW)
Title: Hydrogen peroxide containing water discharge treatment device
Inventor: UESUGI KAZUYA
IPC: B01J19/24
Filed: 2002-12-19
Granted: 2005-01-11
Abstract: The hydrogen peroxide containing water discharge treatment device disclosed in this invention is to allow the hydrogen peroxide containing discharge water flowing upwards in a reaction tower (2). Moreover, catalyst is in the reaction tower (2), which is divided in a top and bottom manner, into a two-layered arrangement of a bottom catalyst layer (8) and a top catalyst layer (14). In addition, there is an exhaust pipe (20) installed onto the reaction tower (2) so that the oxygen generated in the bottom catalyst layer can be discharged out of the reaction tower without contact the top catalyst layer. Therefore, contact efficiency of catalyst and hydrogen peroxide can be increased, the size of the device can be reduced, space can be saved and equipment cost can be reduced.
Patent TW-I234418-B (TW)
Title: RF plasma processing method and RF plasma processing apparatus
Inventor: TSUCHIYA NOBUAKI
IPC: C23C16/505
Filed: 2003-02-07
Granted: 2005-06-11
Abstract: This application discloses the technique of the RF plasma processing using two RF waves of different frequencies, where plasma is generate and retained sufficiently and stably. The first frequency is for generating plasma by igniting a discharge, and the second frequency is for generating self-biasing voltage at a substrate to be processed. The wave of the second frequency is applied with a time-lag after applying the RF wave of the first frequency. This application also discloses the impedance matching technique in the RF plasma processing, where impedance to be provided is optimized both for igniting the discharge and for stabilizing the plasma.
Patent TW-I221613-B (TW)
Title: High speed flat cell structure with discharge path and two-input/two-output reading path
Inventor: TANG CHUEN-AN
IPC: G11C11/21
Filed: 2003-03-14
Granted: 2004-10-01
Abstract: The present invention provides a high speed flat cell structure, which has a discharge path and, when reading the flat cell, achieves the effect of selecting a transistor cell via two paths and outputting the transistor cell via two paths by controlling the reading path to read the cell. The present invention further reduces the resistor and capacitor effects when an external circuit reads data, thereby achieving the purpose of reducing noise, decreasing power consumption, increasing frequency response and reducing temperature.
Patent TW-I227468-B (TW)
Title: Recording method, and storage medium driving apparatus
Inventor: HATTORI MASATO
IPC: G11B27/32
Filed: 2003-03-21
Granted: 2005-02-01
Abstract: A recording method is responsive to a user-initiated single instruction, that includes the steps of copying content data from a storage medium loaded in a first apparatus to a data storage device of a second apparatus; and setting a predetermined check-out count from a predetermined count to the predetermined count minus one, the predetermined check-out count including control information corresponding to a predetermined number of times the content data is allowed to be copied to the data storage device. A storage medium driving apparatus implements the recording method described above.
Patent TW-591286-B (TW)
Title: Liquid crystal display and support thereof
Inventor: YEN CHING-HUI
IPC: G02F1/133
Filed: 2003-03-27
Granted: 2004-06-11
Abstract: A liquid crystal display comprises a support, a display unit and a pre-force mechanism. The support has at least one pivot and at least two sections joined by the pivot. The display unit is connected to the support, thereby applying a gravity torque to the pivot of the support in a first direction. The pro-force mechanism is connected to the pivot and applies a pre-torque to the pivot in a second direction opposite the first direction.
Patent TW-592958-B (TW)
Title: Surface protective film for adhesive resin and process for producing the same
Inventor: SUMITA KATSUHIKO
IPC: C09J7/40
Filed: 2003-05-29
Granted: 2004-06-21
Abstract: A surface protective film which can be easily peeled off from an adhesive resin layer it protects, is free of any component which may have an adverse effect on adhesion of the adhesive resin layer to an object to which it is bonded, and has no adverse effect on thickness uniformity or surface flatness of the adhesive resin layer, and a process for producing the same. More specifically, a surface protective film for protecting an adhesive resin layer, comprising a base film (A) coated, at least on one side, with a cellulose-based resin layer (B) having an SP value of 21.0 to 29.0 (MPa)<1/2>, determined by the Fedors method, and process for producing the same.
Patent TW-I245254-B (TW)
Title: Method for increasing response speed and contrast ratio of liquid crystal display device
Inventor: LIU HONG-DA
IPC: G09G3/20
Filed: 2003-06-27
Granted: 2005-12-11
Abstract: The present invention is provides a method for increasing the response speed and contrast ratio of a liquid crystal display (LCD) device. The method is applied to generate the required gray-scale display condition by dividing the switching time in a scan cycle and applying one or more voltages. The applied voltage includes a voltage larger than or close to the saturation voltage, so as to speed up the liquid crystal response speed and, therefore, increase the response speed of the gray-scale display condition. By adjusting relation between the divided switching times, the LCD contrast ratio can also be increased.
Patent TW-I222376-B (TW)
Title: Connection structure for a weight member of a golf club head
Inventor: CHEN CHAN-TUNG
IPC: A63B53/04
Filed: 2003-08-11
Granted: 2004-10-21
Abstract: A connection structure for a weight member of a golf club head comprises a golf club head and a weight member. The golf club head is formed with a recession for receiving the weight member which has at least one hole for fill up a solder. The weight member is inserted into the recession of the golf club head prior to brazing. When brazing, the solder in the hole of the weight member can be melt and then flow out of the hole to permeated into a gap defined between the weight member and the recession of the golf club head so as to increases entire binding strength therebetween.
Patent TW-I238472-B (TW)
Title: Method of passivating semiconductor device
Inventor: TSAI YAW-MING
IPC: H01L21/322
Filed: 2003-10-27
Granted: 2005-08-21
Abstract: This invention is related to a method of passivating a semiconductor device. The method includes the steps of performing a high pressure annealing treatment on the semiconductor device and performing a plasma treatment on the semiconductor device in order to dissipate charges accumulated in the semiconductor device after the high pressure annealing treatment is performed. The process gas used in the plasma treatment may be N2, H2, H2O, N2O, O2, NH3 or a mixture.
Patent TW-I241587-B (TW)
Title: Nonvolatile variable resistor, memory device, and scaling method of nonvolatile variable resistor
Inventor: TAJIRI MASAYUKI
IPC: G11C13/00
Filed: 2003-11-05
Granted: 2005-10-11
Abstract: Provided are a nonvolatile variable resistor with a structure capable of suppressing an increase in resistance in a case where scaling is applied to reduce a projected area on a plane, a memory device using the nonvolatile variable resistor, and a scaling method of a nonvolatile variable resistor. A first electrode and a second electrode formed on a substrate face each other in a direction of a surface of the substrate. The first electrode is used as an inner electrode, a nonvolatile variable resistance body is formed on an outer surface of the first electrode and the second electrode is formed as an outer electrode on an outer surface of the nonvolatile variable resistance body.
Patent TW-I229477-B (TW)
Title: Connector
Inventor: CHEN HSIANG-FENG
IPC: H01R13/52
Filed: 2003-11-12
Granted: 2005-03-11
Abstract: A connector includes a body, a terminal chamber formed in the body for receiving a terminal therein, and plural elastic petals formed around in the terminal chamber. The terminal is made integral, having an insulating tubular member made of Teflon formed at an inner end portion, a large flange and a small flange formed in the intermediate portion to tightly combine with the elastic petals of the body.
Patent TW-I233545-B (TW)
Title: Mechanism for processor power state aware distribution of lowest priority interrupts
Inventor: HORIGAN JOHN
IPC: G06F1/32
Filed: 2003-12-09
Granted: 2005-06-01
Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.
Patent TW-I236154-B (TW)
Title: Semiconductor device and method for manufacturing the same
Inventor: MAKITA NAOKI
IPC: H01L21/20
Filed: 2003-12-15
Granted: 2005-07-11
Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.
Patent TW-I263787-B (TW)
Title: A universal power measurement SoC and measuring method
Inventor: LIN SYH-SHOEI
IPC: G06F19/00
Filed: 2003-12-25
Granted: 2006-10-11
Abstract: A universal power measurement SoC includes an analog signal conditioning circuit, analog-to-digital converter circuit, memory and micro control unit. The analog signal conditioning circuit receives physical signals from a signal sensor and adjusts the polarities and amplitudes of the signals to produce suitable analog signals and gain status. The analog-to-digital converter circuit converts the adjusted analog signals into digital signals. The memory stores the pre-setup parameters of the power measurement. The micro control unit, according to users' choices, processes the converted digital signals with the gain status to produce the output signals of the power measurement. The SoC can reduce the number of the needed devices, cost, and the production adjusting period for promoting the system functions, increase the stability, accuracy, and the flexibility of application, and simplify the procedure of adjusting and production.
Patent TW-I240958-B (TW)
Title: Organic electroluminescence device and method for manufacturing the same
Inventor: TAKANOSU KEIJI
IPC: H05B33/00
Filed: 2004-01-07
Granted: 2005-10-01
Abstract: At least one of an organic emitting layer, an electron injection layer and an electron transfer layer for pixels of an organic electroluminescence panel is formed from a deposition material by deposition via mask holes of a mul-tilayer metal mask. The mul-tilayer metal mask has a first metal layer on the side of a transparent substrate for forming the organic electroluminescence panel, and a second metal layer on the side of a supply source of the deposition material, wherein the metal layers are different in material. The second metal layer is made of a thick plate of magnetic material. The area of each first mask hole of the first metal layer is made equal to or smaller than that of each second mask hole of the second metal layer. Such a configuration can provide a metal mask for forming organic electroluminescence devices with high reliability, high mechanical strength and high performance. Thus, a high-definition and high-quality organic electroluminescence display panel can be realized.
Patent TW-I247565-B (TW)
Title: Pad structure for improving stray capacitance
Inventor: LEE SHENG-YUAN
IPC: H05K1/02
Filed: 2004-02-17
Granted: 2006-01-11
Abstract: The present invention relates to a pad structure for improving stray capacitance mainly employed to eliminate improper interplanar electrical coupling of circuit board for enhancing the response of routing trace, wherein etch technique is used to etch the position of the grounding plane relative to the surface components on the routing plane so as to reduce the stray capacitance coupled between the mounting pad where surface components reside and the grounding plane. Since the coupling capacitance is reduced, the stray capacitance effect of circuit board generated at high frequency can be eliminated to increase the overall circuit quality of circuit board.
Patent TW-I256561-B (TW)
Title: Automatic installation method and system of test environment setup for information platform
Inventor: LIN TING-CHIEN
IPC: G06F15/82
Filed: 2004-02-27
Granted: 2006-06-11
Abstract: Automatic installation method and system of test environment setup for information platform are applied to an information platform that is controlled by a specific operation system and is used to execute a specific test procedure on the information platform. An automatic test environment installation function is provided so that the test procedure can be smoothly executed under the test environment of the specific operation system. The advantage of this information platform automatic test environment installation method and system is that the same test procedure can be executed on information platforms running different operation system. The manual setup by testing personnel for different operation systems is not necessary, so the whole test procedure is executed more rapidly and efficiently.
Patent TW-I241010-B (TW)
Title: Electrostatic discharge clamping circuit for interface circuit of the mixed voltage source
Inventor: HSU KUO-CHUN
IPC: H03K5/08
Filed: 2004-03-12
Granted: 2005-10-01
Abstract: There present invention discloses an electrostatic discharge clamping circuit for interface circuit of the mixed voltage source, which comprises the detection unit and the protection unit of electrostatic discharge using devices of different tolerance voltage. Under normal situation, the detection unit would not trigger the protection unit of electrostatic discharge, and no electric leakage and reliability problem of the gate would occur. When electrostatic discharge is generated in between the power cords, the detection unit will trigger the protection unit of electrostatic discharge and the protection unit of electrostatic discharge can fast drain out the huge current generated by the electrostatic discharge.
Patent TW-I230048-B (TW)
Title: Bed frame ready for sleeping
Inventor: HARASHIMA TOORU
IPC: A47C27/00
Filed: 2004-03-25
Granted: 2005-04-01
Abstract: This invention relates to a bed frame ready for sleeping, comprising a mattress provided on a bed for a sleeper to sleep thereon. The bed frame ready for sleeping comprises a frame base body, a cushion pad, and a mattress. The frame base body consists of a frame and a bearing member. The frame is a surrounding frame having frame parts provided on circumference thereof. The bearing member has many through holes, can cover the space inside the surrounding frame, and is retained in the surrounding frame to support the weight of the sleeper. The cushion pad is provided on the bearing member and has many through holes whose areas are smaller than those of the bearing member. The mattress can be born by the cushion pad.
Patent TW-I237761-B (TW)
Title: Method for updating a firmware code stored in a non-volatile memory and related device
Inventor: TU LI-CHUN
IPC: G06F9/44
Filed: 2004-04-09
Granted: 2005-08-11
Abstract: A method for updating a firmware code stored in a non-volatile memory and a related device. The non-volatile memory is installed in an electronic device. The method includes providing an updating control unit having a command set, providing the updating control unit with a trigger signal to enable at least one command of the command set, and utilizing the updating control unit to read/write the non-volatile memory according to the enabled command to update the firmware code. Wherein each command of the command set is a memory read/write command. The method further includes updating at least one command of the command set in real time.
Patent TW-I241904-B (TW)
Title: Paper taking device for lithographic toilet paper
Inventor: TSAI RUEI-AN
IPC: A47K10/44
Filed: 2004-04-16
Granted: 2005-10-21
Abstract: Provided is a paper taking device for depositing lithographic toilet paper which comprises: a paper packing box and a paper taking mechanism. The paper packing box mentioned above has a base wall, a surrounding wall having a paper exiting opening and a space for depositing lithographic toilet paper. And the paper taking mechanism comprises: a pushing grip capable of sliding on the base wall along a predetermined direction and a rubbing jack which connects with the pushing grip and is located in the deposition space. The rubbing jack mentioned above leans against one piece of a pile of toilet paper. By means of the binding friction between the rubbing jack and the toilet paper, the lithographic toilet paper can be taken out from the deposition space by a way of pressing and pushing.
Patent TW-I237865-B (TW)
Title: Test key for monitoring gate conductor to deep trench misalignment
Inventor: LIN YU-CHANG
IPC: H01L21/66
Filed: 2004-06-04
Granted: 2005-08-11
Abstract: A test key layout for monitoring gate conductor-to-deep trench capacitor (GC-DT) misalignment. The test key layout includes a substrate in which a number of deep trench capacitors are embedded in an interlacing matrix form. A plurality of GC lines is defined on the substrate and passing over the deep trench capacitors. A first bit line contact pattern, which is surrounded by several first assistant bit line contact patterns, is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern, which is surrounded by several second assistant bit line contact patterns, is disposed on the left side of a second deep trench capacitor. The test key layout has a mirror symmetric line such that the first assistant bit line contact patterns and the second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A plurality of rows of bit lines including a signal-in bit line connected to the first bit line contact pattern and a signal-out bit line connected to the second bit line contact pattern. The rest rows of the bit lines are dummy bit lines and are floating during operations.
Patent TW-I245397-B (TW)
Title: Leadframe with a chip pad for double side stacking and method for manufacturing the same
Inventor: HUANG YAO-TING
IPC: H01L23/495
Filed: 2004-06-29
Granted: 2005-12-11
Abstract: A leadframe with a chip pad for double side stacking includes a chip pad and a plurality of leads. A dielectric adhesive layer is formed on the lower surface of the chip pad and sticks to a wiring layer, the wiring layer has a connecting pad. At least a through hole passes through the chip pad, the dielectric adhesive layer and the wiring layer. An electrically-conductive material is formed inside the through hole so that the connecting pad of the wiring layer is electrically connected to the chip pad. When an electric device is mounted on the lower surface of the chip pad, a plurality of bonding wires having one ends on the upper surface of the chip pads can electrically the electric device to the leads for achieving two side stacking of the chip pad.