baber/WOPTO huggingface dataset:
Patent JP-S6488606-A (JP)
Title: Supervisory control system in digital instrumentation system
Inventor: KAMEYAMA KEIICHI
IPC: G05B23/02
Filed: 1987-09-30
Abstract: PURPOSE:To attain the control of high degree from a host computer by separating supervisory control from the conventional control status of cascade, automatic and manual status and handling it as an independent control mode. CONSTITUTION:For a multi-loop controller 3, a setting value SV and an operating output value MV are set from an exclusive-use operator's console 1 and a host computer 2. When the control mode (supervisory control) is turned on, namely, when a switch to control the control mode is in an S side, for the setting value SV, the set from the exclusive-use operator's console and the set from another control loop are prohibited and the set from the host computer can be executed. The host computer supervises the cascade status and the automatic status and sets the setting value to be obtained from a control loop C1 or a production plan, etc. On the other hand, the operating output value MV is separated from a PID control output at the manual status and directly controlled from the computer. Thus, the control, which is equal with the control to be executed by an operator, can be automatically executed from the host computer 2.
Patent JP-S60136877-A (JP)
Title: Picture input device
Inventor: KUSHIBIKI MASASHI
IPC: G09G5/00
Filed: 1983-12-26
Abstract: PURPOSE:To enable to input a titled for retrieval easily by specifying the voluntary area of the picture which is displayed on a display, by character-recoginizing picture information inside a storage device which corresponds to the area, and by outputting the information as the character code. CONSTITUTION:In the inner part, each unit is connected to a bus 12, and a microprocessor 25 controls the whole system according to the procedure which is shown by a control memory 26. The output of an image scanner 6 is received by a scanner adaptor 13 through a connector 14, and is transmitted to a bit map memory 15. The contents of the memory 15 is displayed on a display 8 through a connector 17 by a display adaptor 16. In addition, the adaptor 16 displays the contents of a character memory 18 on the display 8. When the letter string, which coincides with the titled contents, is observed in an original at the time of titled inputting, letter coding can be executed by a character recognition circuit 20.
Patent JP-S6488963-A (JP)
Title: Address data deciding circuit
Inventor: OKUYAMA TAKEHIKO
IPC: G11B20/10
Filed: 1987-09-30
Abstract: PURPOSE:To promptly read address data even with a linear velocity constant system by deciding whether a white level signal coincides with a prescribed address pattern or not after a horizontal synchronizing signal is detected. CONSTITUTION:A slicing circuit 11 slices a video signal to pass through an LPF 3 near a white level and extracts only the address data and the white level part of the video signal. Thereafter, a synchronization separating part 12 extracts only the horizontal synchronizing signal out of the video signal and sends it to a pattern deciding circuit 13. This circuit 13 decides whether a signal after a prescribed period passes from the fall of the horizontal synchronizing signal is 1000 or 1111 for each H, outputs an OK signal to a circuit 6 composed of a bi-phase demodulating part and a shift register when these signals are input, and outputs an NG signal when the signals different from these signals are outputted. Thereafter, the circuit 13 sends a data signal to a microcomputer 7 only when it outputs the OK signal, and a prompt processing can be executed even with the linear velocity constant system.
Patent JP-H0674556-A (JP)
Title: Control device for heater control relay for bath water purifying device
Inventor: ANDO TAKUMI
IPC: A47K3/00
Filed: 1992-08-20
Abstract: PURPOSE:To prevent relay contacts from turning into an oscillating state wherein turns-on and off are repeated in a short cycle by so constituting that a relay does not turn on until a timer value reaches a setting value once after a detected value of hot water reaches a setting value and the relay has turned off. CONSTITUTION:A bath water purifying device is designed to circulate and purify bath water in a bath tub by way of a circulation passage which includes a filter device or a heat insulation heater by driving a circulation pump 8. In this case, a memory device 2 stores a setting temperature of hot water set by a user by means of a hot water temperature setting instrument. A hot water temperature detection device 3 detects the temperature of hot water in a bath tub. Furthermore, a comparator 4 is used to compare a detected value of hot water with a setting value. On the other hand, the output of the comparator 4 is input into a reset terminal of a timer 5. Each output of the comparator 4 and the timer 5 is input into a determinant apparatus 6 while a power source 9 of a heater 7 is on/off-controlled with a relay 8. The relay 8 is designed to switch on the heater when a detected value of hot water drops by a fixed value than a setting value and the timer 5 exceeds the setting value.
Patent JP-H08108272-A (JP)
Title: Narrow gap butt welding method of fixed tube
Inventor: SUGITANI YUJI
IPC: B23K9/095
Filed: 1994-10-07
Abstract: PURPOSE: To prevent generation of in complete fusion by executing high speed rotating arc welding in first layer welding and build-up layer welding by specifying the rotating speed and rotating diameter of arc and executing welding in final layer welding by weaving a welding torch. CONSTITUTION: Fixed tubes 1, 2 are subjected to narrow gap butt welding by gas metal arc welding. In first layer welding, a copper backing CB is abutted to the rear face of narrow gap 3. The high speed rotating arc welding of 20-100Hz arc rotating speed and 1-4mm arc rotating diameter is used. While the welding condition, for each welding position and each root gap, is selected from the optimum welding condition set in the range of 100-300A welding current and 15-80cm/min welding speed, peripheral downward welding is executed. In build-up layer welding, the arc welding diameter D is changed to 2-6mm, welding is executed in the range of 150-400A welding current and 20-120mm/min welding speed. In final layer welding, welding is executed in the range of 60-180A welding current and 7.5-30cm/min welding speed.
Patent JP-H03107714-A (JP)
Title: Scaling system for graphic data display
Inventor: SAITO KENJI
IPC: G01D3/02
Filed: 1989-09-20
Abstract: PURPOSE:To know the fine variation of observation and measurement data containing error data by removing data corresponding to external set conditions from specific-width data which are rearranged according to a rule. CONSTITUTION:An increasing order sorting processing part 8 rearrange data, read out of a storage device 1 by a data read part 2 to every specific width, in the increasing order. A data extraction part 5 discards M pieces of data from the data, which are rearranged by the processing part 8 in the increasing order, each from the larger side and smaller side. Consequently, error data is removed and an arithmetic processing part 6 and a display position indication part 7 perform graphic processing so that the variation range of data to be scaled almost matches the full scale of a display device 3. Therefore, when a graphic display is made, normal data are not compressed with error data and normal fine variation can be displayed.
Patent JP-S62105830-A (JP)
Title: Bill drawing-out mechanism
Inventor: ORIHARA SUSUMU
IPC: B65H3/04
Filed: 1985-10-31
Abstract: PURPOSE:To correct inclination of bills and feed them one by one by drawing out the bills sandwiched between a rotating belt and a press plate by means of a drawing-out roller having a frictional region and a slide region rotating in a predetermined direction and a roller rotating in the opposite direction to said drawing-out roller. CONSTITUTION:Bills 1 dumped into a bill dumping port are sandwiched between a press plate 4 and a belt 7 rotating in the direction of arrow H. The belt 7 is rotated by a drawing-out roller 5 having friction and slide regions 5a, 5b and rotating in the direction E. The drawing-out roller 5 formes a bill 1 discharging path 3 together with a curved portion 12a extending from the bottom 12. Rollers 14, 15 rotatably driven by rollers 6, 5 along the discharging path 3 in the opposite direction to the roller 5 are provided. While the slide region 5b of drawing-out roller 5 contacts the bill 1, it slips without feeding the bill 1 to correct the inclination of an end of the bill 1. Thus, the bills 1 are arranged properly and sent out one by one in the direction G so that jam and miss judgement of a judging section can be prevented.
Patent JP-S61124234-A (JP)
Inventor: KONISHI HIROO
IPC: H02J3/36
Filed: 1984-11-21
Abstract: (57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。
Patent JP-H03105640-A (JP)
Title: Memory clear control system
Inventor: SHINJO NAOKI
IPC: G06F12/02
Filed: 1989-09-20
Abstract: PURPOSE:To clear plural discontinuous clear areas at a high speed by setting a clear necessary/unnecessary flag of an area which necessitates clear to ON, and cleaning successively each clear area, based on an ON state of this flag. CONSTITUTION:A clear necessary/unnecessary flag 3 shows whether clear of each area A - N of a memory 9 is necessary or not. When a clear mode flag 2 and a prescribed clear necessary/unnecessary flag 3 are set to ON by an SVP (service processor) 1, a memory controller 4 is actuated, and an absolute address range of each clear area set by referring to constituting information of a constituting information storage part 5 is obtained. Subsequently, by comparing the outputs of this address range and an address counter 6, and writing fixed data to a coincidence absolute address, clear of this absolute address part is executed successively. In such a way, this system is constituted so that a single setting operation in the SVP whose operation speed is low is enough. Accordingly, plural discontinuous memory areas can be cleared at a high speed.
Patent JP-2001064381-A (JP)
Title: Production of polytetramethylene ether glycol diacetic ester
Inventor: NAKANO HIDEHIKO
IPC: C08G65/20
Filed: 1999-08-31
Abstract: PROBLEM TO BE SOLVED: To provide a process which can efficiently separate and recover unreacted raw materials from the polymerization reaction solution without causing a deterioration in the quality of the formed polymer and can educe the amount of an inert gas not yet used to be newly introduced into the system to a great extent in the process for producing polytetramethylene ether glycol diacetic ester by ring opening polymerization of tetrahydrofuran in the presence of a solid acid catalyst or acetic anhydride. SOLUTION: In the process for producing polytetramethylene ether glycol diacetic ester by ring opening polymerization of tetrahydrofuran in the presence of a solid acid catalyst or acetic anhydride, the polymerization reaction solution is treated via an evaporator and gas-liquid contact equipment which countercurrently contacts the polymerization reaction solution with an inert gas to separate and recover unreacted raw materials of tetrafydrofuran and acetic anhydride in the polymerization reaction solution and, at the same time, the inert gas after removal of low-boiling distillates is circulated for use as at least part of the inert gas.
Patent JP-H1158210-A (JP)
Title: Ingot cutting method with wire saw
Inventor: KOBAYASHI TATSUNOBU
IPC: H01L21/301
Filed: 1997-08-25
Abstract: PROBLEM TO BE SOLVED: To shorten the cutting time of an ingot, reduce the unevenness of the thickness of a wafer, increase the yield of the wafer per ingot and also reduce the warp of the wafer. SOLUTION: A feed amount per cycle of the go and return of a wire row 11 is made comparatively larger at the cutting start end and cutting final end of the ingot I and comparatively smaller at the cutting central part of the ingot I. As this result, total idle time of the cutting start end and final end with a short contact length to the ingot I an be shortened and the ingot cutting time is shortened. At the same time, the ingot can be cut smoothly with causing the run-out of lubrication of an abrasive liquid at the cutting central part with a long contact length. The unevenness of the thickness of the wafer W just after cutting can be reduced and the yield of the wafer production can be increased. The warp of the wafer W can be reduced and the break of the wafer W and wire disconnection at the lapping time can be prevented, too.
Patent JP-S6490308-A (JP)
Title: Synthetic resin core material
Inventor: IWATA MASANORI
IPC: E21F16/02
Filed: 1987-09-29
Abstract: PURPOSE:To obtain a drain material having a uniform strength by a method in which corrugated synthetic resin ribs are alternately crossed with each other and the tops and bottoms of the ribs are each connected to make up a three- dimensional integrated face drain material. CONSTITUTION:The core 1 of a face drain material is made of many corrugated synthetic resin ribs 2. The ribs 2 are lapped, one over another, in an orthogonally crossing manner, the tops (a) of the ribs 2 are connected, and the bottoms (b) of the ribs 2 are connected to make up an integral face drain material of a three-dimensional form. The core 1 can have a uniform strength as a whole.
Patent JP-H0694765-A (JP)
Title: Discriminating device for polarity of electrolytic capacitor
Inventor: OCHIAI ICHIRO
IPC: G01R31/00
Filed: 1992-09-14
Abstract: PURPOSE:To prevent a malfunction of a polarity deciding inspection due to an inclination of an electrolytic capacitor in the case of inspecting to decide a polarity of the capacitor. CONSTITUTION:A polarity discriminator for an electrolytic capacitor has pinboards 4, 6 approachable to and separable from a printed board 5 mounted with the capacitor 1 and disposed on both side surfaces of the board 5, and a probe pin 2 provided on the board 4 in contact with the upper surface of the capacitor 1. A probe pin 3 in contact with a lead terminal soldered part 9 of the capacitor to the board 5 is provided at the lower pinboard 6. Means for vertically correcting the capacitor 1 inclined before the polarity inspection of the capacitor 1 to position the capacitor 1 to the pin 2 provided on the pinboard 4 is provided.
Patent JP-H07223943-A (JP)
Title: Medicinal composition for maintaining and/or reestablishing aggregation speed approximating normal platelet aggregation speed
Inventor: MARUTO DOUORUNU
IPC: A61K31/22
Filed: 1994-09-14
Abstract: PURPOSE: To obtain a pharmaceutical composition containing a cysteine derivative and/or a cystine derivative, and capable of maintaining and/or reestablishing blood platelet aggregation at close to the normal value. CONSTITUTION: This pharmaceutical composition contains a cysteine (e.g. acetylcysteine), a cystine derivative (e.g. dansylcystine), and/or their salts as an active ingredient in an amount of 30-4000mg, preferably 100-1000 mg. The composition is further suitably compounded with a vitamin B6 vehicle, an emulsifier, a perfume, a preservative, etc., and subsequently prepared into tablets, pills, powders, granules, syrups, suppositories, injections, etc. The daily dose of the composition is 0.1-5 g. It is especially preferable that the composition is used together with a therapeutic method using a medicine causing or probably causing thrombocytopenia or thrombocytopathia as a side effect.
Patent JP-S60137623-A (JP)
Title: Manufacture of resin mold for injection molding product excellent in luster
Inventor: ABE YASUYUKI
IPC: B29C45/26
Filed: 1983-12-27
Abstract: PURPOSE:To obtain the mold made of epoxy resin for injection molding, which enables the product excellent in luster to be obtained by causing epoxy resin fluidized under reduced pressure after the epoxy resin containing a specified diluent and curing agent has been cast, etc. in the mold made of methacryl. CONSTITUTION:The epoxy resin containing the low viscous and reactive diluent with at least one epoxy radical in one molecule and amine group curing agent, is used. Bath diluent and curing agent have vapour pressure equal to or lower than 1mm.Hg at 30 deg.C and the thermal deformation temperature equal to or higher than 60 deg.C after curing. This resin is cast into the master form model made of methacryl resin, or the master form model is gel-coated with the epoxy resin, and then said resin is cured after it has been caused to fluidize under reduced pressure.
Patent JP-H0694877-A (JP)
Title: Reactor core of fast reactor
Inventor: KAWASHIMA MASATOSHI
IPC: G21C7/28
Filed: 1992-09-14
Abstract: PURPOSE:To simplify the upper side of a reactor core, and to make the density coefficient of a cooling material 'negative'. CONSTITUTION:The area of a reflector 12 for control the reactivity is provided at the area neighboring the outer side of a reactor core fuel 11, and a reflector 13 for controlling the reactivity moving vertically neighboring the inner side of the reactor core fuel 11 is provided. An outer side neutron absorber area 15 is provided at the outer side of the outer side reactor 12, while an inner side neutron absorber area 14 is provided at the inner side of the inner side reactor 13.
Patent JP-H1083162-A (JP)
Title: Display device
Inventor: KONOUE AKIHIKO
IPC: G09G3/296
Filed: 1991-02-26
Abstract: PROBLEM TO BE SOLVED: To suppress disturbance in gradation even for an animation and a high luminance image by constituting plural kinds of all sub-fields with different display periods in a field with plural sub-fields with respectively nearly equal display periods. SOLUTION: All sub-fields b0-b7 are displayed twice for a field. To a first electrode, 16 scan pulses 501 corresponding to two all sub-fields are applied for one field. The number of pulses 601 applied to a third electrode are proportionated to the display period of the sub-fields b0-b7, and when these time interval ratios are made 1:2:4:8...:128, 256 gradation are realized according to their combination. When the absolute value of the number of pulses of the third electrode is decided so that the period from the first (display period start point of time) of the sub-field b0 to the end (display period end point of time) of the sub-field b6 becomes smaller than 3.3msec, a critical fusion period becomes 20(=3.3+16.7 (one field period)) msec.
Patent JP-S6486784-A (JP)
Title: Color television camera
Inventor: MIYAWAKI SEIGO
IPC: H04N9/04
Filed: 1987-09-29
Abstract: PURPOSE:To reproduce an accurate chrominance signal even when color light with high luminance level is photographed by generating a color difference signal by mixing the color difference signal passing through a gain control circuit and the color difference signal not passing through the gain control circuit in a color television camera of additive complementary color system using a solid-state image pickup device. CONSTITUTION:The output signal of an image pickup circuit 1 is inputted to an AGC circuit 3 and an amplifier 9 via a sampling circuit 2. When a scene where an object with partial high luminance exists in a dark place as a whole is photographed, thc gain of the AGC circuit 3 is increased since a whole level is low, and output is saturated at a part with high luminance, and a modulation wave component that is a color difference component disappears, and no color difference signal is obtained. However, by reducing the gain of the amplifier 9 to an extent not to saturate the signal, the color difference signal can be obtained from a color difference signal processing circuit 11. Adversely, at the dark place, the level of the color difference signal outputted from the color difference signal processing circuit 11 is reduced remarkably since the gain of the amplifier 9 is low, however, no saturation of the signal at thc AGC circuit 3 is generated, and the color difference signal with high gain can be obtained, thereby, the color difference signal with high level is outputted from a color difference signal processing circuit 8.
Patent JP-2000077720-A (JP)
Title: Optical semiconductor device
Inventor: KUNII HIDEO
IPC: H01L33/56
Filed: 1998-08-31
Abstract: PROBLEM TO BE SOLVED: To form the external shape of a light-emitting element and a photodetector as thin as possible, and to enable a miniaturization of the elements also in a module or a set with these elements incorporated therein. SOLUTION: An optical semiconductor device is provided with semiconductor chips 23 and 24 as its light-emitting element and photodetector, and a resin sealed body 25 for sealing these chips consists of a material transparent to light. Moreover, grooves 27 are respectively formed in the region, where the light is emitted from the light-emitting element, and the region, where the light is incident in the photodetector, and reflective surfaces 26 are respectively constituted on these grooves 27. As a result, it becomes possible that the light is emitted and incident from the light-emitting element and in the photodetector via the side surface E of the sealed body 25. Moreover, as each slant surface 30 is provided on the upper parts of the reflective surfaces, the intensity of the light is strong.
Patent JP-H0969774-A (JP)
Title: Signal processor and isdn terminal equipment
Inventor: FUJII TAKANORI
IPC: H04L12/02
Filed: 1995-08-31
Abstract: PROBLEM TO BE SOLVED: To effectively eliminate the noise component superposed on an analog signal by setting a sound CODEC to the noise elimination mode in the case of a large noise generated in the sound CODEC. SOLUTION: When the generation noise of the sound CODEC is large, the sound CODEC is set to the noise elimination mode. In this case, a control part makes switches 21, 24, 27, 28, and 32 select a normally closed contact 21bm a normally opened contact 24a, a normally closed contact 27b, a normally closed contact 28b, and a normally opened contact 32a respectively by control signal S1 to S5. Consequently, a transmission analog signal X is applied to an A/D converter 22 through the switch 21 and is converted into a digital signal D1 and is applied to an input terminal A of a computing element 23. A signal D2 (the noise component caused by the operation of the A/D converter 22) outputted from an A/D converter 25 is applied to an input terminal B of the computing element 23.  Consequently, an output signal D3 of the computing element 23 is the signal component obtained by eliminating the signal D2 from the signal D1.
Patent JP-H0583251-A (JP)
Title: Data transmission system
Inventor: KIMURA KAZUHIRO
IPC: H04L12/18
Filed: 1991-09-25
Abstract: PURPOSE:To reduce the number of times of transmission and transmission time when multiple address communication is implemented from one node to other node among plural nodes. CONSTITUTION:When a node 1-1 is a sender of multiple address communication, a shortest transfer path 8 to a node 1-5 in the longest path is set and multiple address communication data are sent to the node 1-5 through nodes 1-2, 1-3, 1-4 via a link 2. The nodes 1-2, 1-3, 1-4, 1-5 return an incoming call reply and the node 1-1 confirms that the non-reception is in existence in nodes 1-6, 1-7 based on the supervision of the incoming call reply, a shortest transfer path 9 is set to the node 1-6 in the longest path and the multiple address communication data are sent through the node 1-3. In this case, since the node 1-3 has already received the multiple address communication data, no incoming call reply is implemented.