baber/WOPTO huggingface dataset:
Patent TW-555944-B (TW)
Title: Refractory plate for a slide gate valve and slide gate valve
Inventor: ROTHFUSS HANS
IPC: B22D11/10
Filed: 2000-12-04
Granted: 2003-10-01
Abstract: The invention relates to a refractory plate (1) for a slide gate valve, having a pouring hole (3), circumscribed by a circle C of center (4), at least a portion of the edges (15, 16, 17, 18) of the plate (1) are angularly oriented so as to focus the clamping forces optimally in the throttling area and around the pouring hole.
Patent TW-518372-B (TW)
Title: A brightening and passivating liquid composition and a process of brightening and passivating a metallic surface
Inventor: GIORDANI PAOLO BRUNO
IPC: C23C22/10
Filed: 2000-12-22
Granted: 2003-01-21
Abstract: A chromium- and nitrogen-free brightening and passivating treatment for metal surfaces, particularly iron and steel, comprises: at least one acid; at least one substance containing a peroxy moiety; and at least one organic substance selected from the group consisting of: molecules that contain both at least one ether moiety and at least one hydroxyl moiety; molecules that contain at least two ether moieties; and molecules that contain in each molecule both at least one ether moiety and one nitrogen atom that is covalently bonded to at least three carbon atoms. Preferably part of the acid contains phosphorus, which has been found to act synergistically with the organic substance to stabilize peroxy compounds against decomposition, particularly in the presence of metal ions.
Patent TW-541236-B (TW)
Title: Punching apparatus and the punching unit thereof
Inventor: ISHII TORU
IPC: B21D37/12
Filed: 2001-01-08
Granted: 2003-07-11
Abstract: A punching apparatus is provided which can of punch a non-circular holes at a predetermined position of a work piece. In the punching apparatus for punching a hole by means of a punch integrated into any one of the moving part of a press working machine or the supporting part of the press working machine, and a die integrated with the other one of the moving part and the supporting part; each of the punch and the die has plurality of planes to be fitted with datum planes of a fitting jig. The punching unit for the punching apparatus comprises a punch, a die, and a fitting jig for positioning the punch and the die with respect to each other, wherein each of the punch and the die has plurality of faces for fitting and the fitting jig has datum planes to be fitted with the planes for fitting of the punch and the die.
Patent TW-487613-B (TW)
Title: Hand-held pneumatic rotary drive device
Inventor: IZUMISAWA OSAMU
IPC: B25F5/00
Filed: 2001-03-05
Granted: 2002-05-21
Abstract: A hand-held pneumatic rotary drive tool having an adjustable exhaust. The tool has an elongate housing containing a pneumatic motor. The housing has an inlet passage for pressurized air at the rearward end of the housing and air delivery passaging for flow of pressurized air to the motor. A rotary connector on the housing at the inlet passage permits connection to an air hose. The housing also has an air exhaust passage for exhausting air from the motor. An air deflector for exhausting air exiting the exhaust passage is rotatable around the connector for deflecting exhaust air laterally outward in a selected direction away from a user holding the tool.
Patent TW-I236578-B (TW)
Title: Chemically amplified positive resist composition
Inventor: NAKANISHI JUNJI
IPC: G03F7/004
Filed: 2001-01-29
Granted: 2005-07-21
Abstract: A chemically amplified positive resist composition capable of giving a resist film excellent in adhesion to a substrate; excellent in various resist performance characteristics such as dry etching resistance, sensitivity and resolution; and comprising a resin (X) which, per se, is insoluble or slightly soluble in alkali but becomes soluble in alkali due to an action of acid, and has a polymeric unit (a) derived from 3-hydroxy-1-adamantyl(meth)acrylate and a polymeric unit (b) derived from beta-(meth)acryloyloxy-gamma-butyrolactone wherein the lactone ring may optionally be substituted by alkyl; and an acid generating agent (Y).
Patent TW-523648-B (TW)
Title: Cascode circuits in dual-VT BiCMOS and DTMOS technologies
Inventor: SINGH SURINDER P
IPC: G05F3/26
Filed: 2001-02-27
Granted: 2003-03-11
Abstract: The various embodiments utilize cascode circuits in dual-threshold-voltage (dual-VT), BiCMOS and DTMOS technologies. The circuit topologies include cascode-connected transistors in the output branch of a current mirror and as a cascode amplifier. Such configurations are capable of both high output impedance and high output swing. The cascode circuits of the various embodiments are operable without separate gate-bias voltages for the cascode-connected transistors. The current mirrors can be used in circuits requiring a regulated current or other current mirroring applications. The current mirrors can further be used as active loads, such as an active load for an amplifier.
Patent TW-471954-B (TW)
Title: Electric cleaner
Inventor: URATANI HIROYUKI
IPC: A47L5/36
Filed: 2001-02-27
Granted: 2002-01-11
Abstract: An electric cleaner provided with a main body comprised of a cleaner housing (20) equipped with wheels (27) for mobility on a floor surface. Both side surfaces of the main body extend outwardly beyond rim portions (35) of the respective wheels (27) that stay in contact with the floor surface, and a center of gravity G (40) of the main body is placed in such a position that the main body rolls toward a direction where the wheels (27) stand on the floor surface so as to return itself into an original posture when the main body tilts in a way that one of the side surfaces lies in contact to the floor.
Patent TW-490812-B (TW)
Title: Manufacturing method for mask ROM
Inventor: SHIUE JENG-CHENG
IPC: H01L27/112
Filed: 2001-05-28
Granted: 2002-06-11
Abstract: A manufacturing method for mask ROM includes the following steps: first, forming buried bit lines on a substrate; forming gate dielectric layer and word lines on the substrate, wherein the word lines is vertical to the buried bit lines; and, the portion of the substrate located between a pair of buried bit lines and below one word line is used as a memory unit; then, covering a first dielectric layer on the substrate and forming several coding windows in the first dielectric layer, which are located above part of the memory units; next, implanting an ion in the memory unit below the coding window, and forming a second dielectric layer on the substrate to fill up all the coding windows.
Patent TW-I221385-B (TW)
Title: CCD type scanner powered by a serial bus
Inventor: CHUNG CHING-FU
IPC: H04N1/00
Filed: 2001-05-31
Granted: 2004-09-21
Abstract: A scanner has a scanning module for generating image data by way of scanning a document, a motor for driving the scanning module, and a control circuit electrically connected to the scanning module and the motor for controlling operations of the scanner. The scanning module has a light source for illuminating the document and a charge coupled device (CCD) for detecting reflex light from the document so as to generate the image data. The scanner is just only powered by a serial bus.
Patent TW-530319-B (TW)
Title: Method and apparatus for using scatterometry to perform feedback and feed-forward control
Inventor: MILLER MICHAEL L
IPC: H01L21/02
Filed: 2001-06-08
Granted: 2003-05-01
Abstract: The present invention provides for a method and an apparatus for using scatterometry to perform feedback and feed-forward control. A processing run of semiconductor devices is performed. Metrology data from the processed semiconductor devices is acquired. Error data is acquired by analyzing the acquired metrology data. A determination is made whether the error data merits modification to the processing of semiconductor devices. A feedback modification of the processing of semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices. A feed-forward modification of the processing of the semiconductor devices is performed in response to the determination that the error data merits modification to the processing of semiconductor devices.
Patent TW-I262338-B (TW)
Title: Cholesteric liquid crystal polarizing device, reflective liquid crystal display and method for fabricating the same
Inventor: JIANG YINGQUI
IPC: G02F1/1368
Filed: 2001-06-22
Granted: 2006-09-21
Abstract: A reflective liquid crystal display (LCD) including a cholesteric liquid crystal polarizing device and a liquid crystal cell superimposed with one another. In various embodiments, the reflective LCD may be a normally white mode or normally black mode device. In another variation, the liquid crystal cell may include a 90óX twisted nematic liquid crystal.
Patent TW-517370-B (TW)
Title: Solder bump structure and flip chip package process
Inventor: LI SHIN-HUEI
IPC: H01L23/52
Filed: 2001-06-26
Granted: 2003-01-11
Abstract: A kind of solder bump structure and flip chip package process are disclosed in the present invention. The invented solder bump is composed of materials having two different melting points. After the reflow process, the solder bump has a cylinder shape. By using the invented solder bump structure and flip chip package process, it is capable of eliminating the effect of high melting point on the substrate of flip-chip product caused by high lead solder. In addition, it is capable of generating larger height of bump and larger filling separation without causing obvious dent after the reflow process, and avoiding the risk of bridging between two adjacent bumps generated during the reflow process.
Patent TW-516254-B (TW)
Title: Flat-plate antenna and electric apparatus with the same
Inventor: IKEGAYA MORIHIKO
IPC: H01Q13/10
Filed: 2001-06-26
Granted: 2003-01-01
Abstract: Provided are a low-cost and high-performance antenna that can be placed in a small space inside a portable terminal or an electric appliance or housed in a wall or the like, and an electric apparatus having the same. A slit 2 having a width c and a length d is formed in a conductive flat plate having a width a and a length b. A radiating element portion 3 shaped like a monopole antenna and a ground portion 4 having a width g are formed with the slit 2 between them. The width a of the conductive flat plate 1 (the length of the radiating element portion 3) is substantially a multiple of a quarter of a wavelength attained at the operating frequency of the antenna by an odd-numbered value.
Patent TW-536879-B (TW)
Title: Method and apparatus for puncturing code symbols in a communications system
Inventor: RAZOUMOV LEONID
IPC: H04L1/00
Filed: 2001-07-06
Granted: 2003-06-11
Abstract: Techniques for puncturing symbols in a communications system. S symbols are received for a frame having a capacity of N symbols, with S being greater than N. P symbols need to be punctured so that remaining symbols fit into the frame. A number of puncture distances, D1 through DN, are computed based on S and P. A particular number of symbol punctures is determined for each computed puncture distance. P1 through PN symbol punctures are then performed at the distances of D1 through DN, respectively. For a more even distribution of the symbol punctures, each of the distances D1 through DN can be selected to be greater than or equal to a minimum puncture distance Dmin defined as Dmin=[S/P], where [] denotes a floor operator. The symbol punctures at each computed distance can be performed together or distributed with symbol punctures at other distances. In the alternative, an accumulator is configured to wrap around after it has been incremented to a value of S, each increment being of size P. A symbol index is incremented by one each time the accumulator is incremented by P, until the symbol index exceeds the value S. The process is advantageously begun with a puncture. Each time the accumulator wraps around, another puncture is performed.
Patent TW-533403-B (TW)
Title: Recognition system using lexical trees
Inventor: RIGAZIO LUCA
IPC: G10L15/193
Filed: 2001-07-31
Granted: 2003-05-21
Abstract: The dynamic programming technique employs a lexical tree that is encoded in computer memory as a flat representation in which the nodes of each generation occupy contiguous memory locations. The traversal algorithm employs a set of traversal rules whereby nodes of a given generation are processed before the parent nodes of that generation. The deepest child generation is processed first and traversal among nodes of each generation proceeds in the same topological direction.
Patent TW-514855-B (TW)
Title: Plasma display panel display device and drive method
Inventor: MASUDA SHINJI
IPC: G09G3/296
Filed: 2001-08-15
Granted: 2002-12-21
Abstract: To provide a PDP display device and a drive method which use a set-up pulse having a portion that drops in voltage at a rate of 2V/μsec or more, whereby the occurrence of discharge errors in a sustain period can be suppressed even when wall charges are not sufficiently erased in an erase period and excess wall charges remain on some or all electrodes in a set-up period. To this end, the drop portion of the set-up pulse applied to a scan electrode group is set after a pulse applied to a sustain electrode reaches a voltage which does not cause a discharge between the sustain and scan electrodes. As a result, the occurrence of discharge errors in the sustain period is suppressed, without prolonging the set-up period.
Patent TW-515938-B (TW)
Title: Large server system
Inventor: CHANG BEN
IPC: G06F1/16
Filed: 2001-08-17
Granted: 2003-01-01
Abstract: The present invention is a large server system for cost reduction and optimum heat radiation effect. The large server system is divided into four separated areas, including main board installation area, hard disc installation area, interface card installation area, and power supply installation area. With two sets of heat radiators installed separately on two sides of the main board installation area and a fan of power supply installed in the power supply installation area, a circulatory air flow is formed to improve heat radiation effect. Also, the mechanism cost is reduced when no additional case is required on the internal server.
Patent TW-501235-B (TW)
Title: A method to form a low parasitic capacitance pseudo-SOI CMOS device
Inventor: QUEK ELGIN
IPC: H01L21/8228
Filed: 2001-08-31
Granted: 2002-09-01
Abstract: A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated S/D extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.
Patent TW-498168-B (TW)
Title: Method and apparatus for tracking devices using tags
Inventor: ANDERSON ARTHUR E III
IPC: H04B1/59
Filed: 2001-09-06
Granted: 2002-08-11
Abstract: An apparatus (10, 240, 300) includes a signpost (11, 241-250, 322, 6l2, 623, 626-628, 652, 66l, 682, 686, 703) which transmits relatively low frequency signpost signals that contain a signpost code and are fundamentally magnetic, a beacon tag (12, 271-275, 301-316, 395-397, 616-618, 641-643, 653, 656-657, 662-664, 679, 708, 711) which receives the signpost signals and transmits radio frequency signals containing the signpost code (42, 93), and a reader (13, 26l, 319, 521-530) which receives the radio frequency signals. One of the signpost and tag is mounted on a moveable item to be tracked, and the other is mounted on a similar item or is stationary. A sensor (32) can be provided to detect the presence of an item and cause the signpost to change its transmitted signpost code. The tag can vary the duration, transmission rate, and/or transmission power of its beacon signals. A control system (14, 500) responsive to the reader can cause she signpost to vary its signpost signal in a manner which causes the tag to shift between normal and low power modes, or which causes the tag to vary as least one operational characteristic, such as transmission rate, transmission power, a transmitted password, or various transmitted codes.
Patent TW-I246505-B (TW)
Title: Corrosion-resistive ceramic materials, method of producing the same, and members for semiconductor manufacturing
Inventor: KOBAYASHI HIROMICHI
IPC: C04B35/593
Filed: 2001-10-31
Granted: 2006-01-01
Abstract: The objective of the invention is to provide a corrosion resistant ceramic material suitable for use such as a product for manufacturing a semiconductor which is to be exposed to corrosive material, having high corrosion resistance, reduced in generation of particles caused by exposure to corrosive material, and hardly chipping or cracking at the time of grinding. The corrosion resistant ceramic material of ceramic containing silicon atoms contains each metallic element in the rate of less than 10 wt.ppm except metallic elements constituting a sintering aid, and silicon atoms.
Patent TW-526450-B (TW)
Title: Cryptographic processor
Inventor: ELBE ASTRID
IPC: G06F7/72
Filed: 2001-11-29
Granted: 2003-04-01
Abstract: A cryptographic processor for performing operations for cryptographic applications and comprises a plurality of coprocessors (104a, 104b, 104c), each coprocessor having a control unit and an arithmetic unit, a central processing unit (102) for controlling the said plurality of coprocessors (104a, 104b, 104c) and a bus (101) for connecting each coprocessor (104a, 104b, 104c) to the central processing unit (102). The central processing unit (102), the plurality of coprocessors (104a, 104b, 104c) and the bus (101) are integrated on one single chip (100). The chip further comprises a common power supply terminal (122) for feeding said plurality of coprocessors (104a, 104b, 104c). By way of parallel connection of various coprocessors, there is obtained on the one hand an increase in throughput and on the other hand an improvement in security of the cryptographic processor with respect to attacks that are based on the evaluation of power profiles of the cryptographic processor, since power profiles of at least two coprocessors are superimposed. Furthermore, the cryptographic processor, by utilization of different coprocessors, may also be implemented as a multifunctional cryptographic processor so as to be suitable for a multiplicity of different cryptographic algorithms.
Patent TW-540103-B (TW)
Title: Semiconductor device and its manufacturing method
Inventor: NISSA MITSUO
IPC: H01L27/108
Filed: 2001-11-30
Granted: 2003-07-01
Abstract: A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).
Patent TW-494205-B (TW)
Title: Non-destructive method for repairing leakage of pipeline
Inventor: CHEN JIAN-RUNG
IPC: F16L55/16
Filed: 2001-11-30
Granted: 2002-07-11
Abstract: The present invention relates to a non-destructive method for repairing leakage of a pipeline, which comprises an air compressor, a filling material, a repairing full-open ball valve set, a pressure stabilizer, a pressure reduction device, a device for increasing wind speed and wind flow, a three-way high/low pressure switch, and one or more pressure gages. An assembly of the above components can detect the place of leakage for a pipeline. Then, a test liquid is injected to a covered or wrapped pipeline, and a pressurized washing is conducted. After the washing, a repairing material is injected and a pressure is applied on the leakage place to repair the pipeline without damaging the structure of the main body and the pipeline.
Patent TW-I239218-B (TW)
Title: Method and apparatus for flexible call recovery in a wireless communication system
Inventor: CHEN TAO
IPC: H04W36/08
Filed: 2001-12-05
Granted: 2005-09-01
Abstract: A method and apparatus provides for call recovery in a wireless communication system (10). When the communication link between a mobile station (38) and a base station (32) is in trouble, the mobile station and the infrastructure prearrange potential call recovery operations. A trigger often initiates a call recovery operation, wherein the trigger indicates when a parameter or metric passes a threshold. These thresholds may be dynamic, adapting to conditions of the system (10) and environment, and the thresholds may be adjusted based on a history or statistical record of operation of the system (10).
Patent TW-576020-B (TW)
Title: Pulsed D-Flip-Flop using differential cascode switch
Inventor: GANESAN ANAND
IPC: H03K3/037
Filed: 2002-01-28
Granted: 2004-02-11
Abstract: A differential cascode structure is configured to propagate a data state to a static latch at each active edge of a clock. A clock generator enables the communication of the data state and its inverse to the latch for a predetermined time interval. In a first embodiment, each cascode structure includes three gates in series, the gates being controlled by the clock signal, a delayed inversion of the clock signal, and the data state or its inverse. In an alternative embodiment, each cascode structure includes two gates in series, the gates being controlled by the clock signal and the delayed inversion of the clock signal. In this alternative embodiment, each of these cascode structures is driven directly by the data signal or its inverse. The static latch obviates the need to precharge nodes within the device, thereby minimizing the power consumed by the device. The latch preferably comprises cross-coupled inverters, which, being driven by the differential cascode structure, enhance the switching speed.