Patent GB-1526583-A (GB)
Title: Data processing apparatus
IPC: G06F7/00
Filed: 1976-03-31
Abstract: 1526583 I/O controllers INTERNATIONAL BUSINESS MACHINES CORP 31 March 1976 [14 May 1975] 12966/76 Heading G4A A micro-processor for establishing communication between control and I/O modules over a serial data path comprises a 1-bit ALU 20 having an output accumulator register 22 which is also connected to the data path 10 to receive incoming data bits, a plurality of source data inputs including data and request lines from the I/O modules and a serial output from a memory 24, a serial input bus 36 connected to the ALU, and an instruction memory 26 and decoder 48 for controlling the operations performed by the ALU and for selectively switching, 40, the source data lines to the input bus 36. The decoder 48 may also selectively switch, 42, a serial output bus 38 to a plurality of destination lines including data and select lines to the I/O modules and the input bus 36. The micro-processor is used to transfer information between lines 10 and 12 and the I/O devices and to receive, store and pass on data from receive line 10 to send line 12 unaltered or inverted, i.e. is a loop adapter. Output operation.-Incoming bits on line 10 are sampled by the REC SYNC signal from loop sync. control 14 which restarts the microprocessor when each incoming bit has been stored in the accumulator 22 and a pre-send latch 16. The micro-processor proceeds to execute a programme in memory 26 as sequenced by an instruction counter 28 which may be a feedback shift register instead of a binary counter. Data and a device address are loaded serially into shift register 44, 34 and when completely assembled, transfer is initiated by setting a DOR FULL latch in a group of latches 50 associated with the destination lines. On completion of the transfer the addressed I/O device responds with a REQ RESP signal to cause resetting of the DOR FULL latch. The microprocessor monitors the state of this latch and when reset is detected the programme is resumed to load incoming bits from line 10 into memory 24. Input operation.-I/O devices requiring service raise a REQ line which is tested by the micro-processor when ready to service an input request. On detecting a request, the microprocessor sets a wait for read latch and goes into the wait state while a counter 32 polls the devices by sending successive device addresses over lines SEL 1-SEL 4 via a shift-register 34. When addressed, a requesting device returns a REQ RESP signal to reset the wait for read latch and the micro-processor resumes its program to load data supplied by the I/O device into memory 24. The device address remains in shift register 34 and is used subsequently by the micro-processor to assemble an "attention" command for transmission over the loop 10, 12 to the control module. As with an output operation and pass mode, operation of the micro-processor is synchronized with the loop 10, 12 by the sync. control 14 which gates data from the pre-send latch 16 to the send latch 18 at the appropriate time in a bit period. Time slots in a loop cycle or frame may be allocated to different loop adapter microprocessors which have wired in address inputs BASE SLOT 1-8. Any adapter can bid for use of a shared time slot by sending an "attention" command (service request) on the loop 10, 12. Other adapters not attached to the device whose address is included in the command are forced into the pass mode, if necessary by command from' the control module.