| { |
| "version": 2, |
| "generated_at": "2026-04-14T17:53:42.618598+00:00", |
| "entries": { |
| "Weiyet_RTLStructLib/list__list/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/operator_typo": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/lfsr__lfsr/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/mean__mean/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "OrsuVenkataKrishnaiah1235_RTL-Coding/srff__srff/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__ch06/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__immediate_generator/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__branch/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__ch02/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__ch06/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/case_swap": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__sipo_rx/inverted_condition": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "chili-chips-ba_wireguard-fpga/sdr__sdr.ORIG/signal_typo": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "dpretet_async_fifo/async_fifo__wptr_full/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/operator_typo": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__piso_tx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "WilliamZhang20_ECE298A-TPU/tb__tpu/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/uart__tx/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/concat_swap": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Data_Memory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/edgedet_mealy__edgedet_mealy/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_wr/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqdet__seqdet/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__vram/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/memory_tb__memory_tb/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqdet_ol__seqdet_ol/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__axi_crossbar_wr/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__mux41_tx/case_swap": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_cntrl/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "srpoyrek_RISC-V/register_bank__register_bank/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/p_mul__p_addsub/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__eurorack_pmod/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__programcounter/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__sys_dev/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__inst_rom/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/reg_alu__lib/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/counter__counter/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_rd/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__sipo_rx/missing_enable": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "Mr-Bossman_KISC-V/soc_top__intctrl/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "saivittalb_simd-processor-verification/CPUtop__SIMDadd/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__MUX4to1_32bit/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/case_swap": { |
| "status": "sim_failed" |
| }, |
| "Weiyet_RTLStructLib/fifo__fifo/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/case_swap": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__alu/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_3/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/systolic_array_tb__PE/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/signal_typo": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_tx/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/alu__alu/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__core/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_Wrapper/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__add_normalizer/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/Core__pc/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/state_transition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__csr_unit/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/state_transition": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/case_swap": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__leds/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__pc_reg/missing_reset": { |
| "status": "compile_error" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/signal_typo": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/memory__memory/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__ch05/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__sram/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__uart_dev/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_reset": { |
| "status": "compile_error" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/signal_typo": { |
| "status": "compile_error" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__axi_register_rd/inverted_condition": { |
| "status": "timeout" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__mul_normalizer/concat_swap": { |
| "status": "llm_failed" |
| }, |
| "alexforencich_verilog-axi/axi_dp_ram__axi_ram_rd_if/inverted_condition": { |
| "status": "timeout" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/signal_typo": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit_tb/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__mproc_mem/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/uart_tx__uart_tx/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/knightrider__knight-rider/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__list/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/state_transition": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__datapath/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__transmitter/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo_raw_rd/inverted_condition": { |
| "status": "timeout" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__decoder/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__uart_rx/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/missing_enable": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__mac_pcs/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/case_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch05__xd/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__xd/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_dp_ram__axi_dp_ram/inverted_condition": { |
| "status": "timeout" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/operator_typo": { |
| "status": "compile_error" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_2/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__regfile/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/TicketMachine__TicketMachine/case_swap": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch01__ch01/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__adder/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__memory/delayed_signal": { |
| "status": "llm_failed" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__FemtoRV32/concat_swap": { |
| "status": "llm_failed" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch04__tram/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_wr/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/Core__pc/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/piso__piso/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/modmcountr__modmcountr/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__lfsr/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/alu__lib/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/operator_typo": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/control_unit__main_control/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__sram/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__alu_control/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "thejefflarson_little-cpu/littlecpu__accessor/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__memory/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/lifo__lifo/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__pooler/signal_typo": { |
| "status": "compile_error" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__lib/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_tx/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Control_Unit/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__sync_r2w/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_interconnect_wrap_4x4__axi_interconnect/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/missing_enable": { |
| "status": "llm_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex_mem/missing_reset": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__tx/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__debouncer/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/fa4__lib/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_dp_ram__axi_ram_wr_if/inverted_condition": { |
| "status": "timeout" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/operator_typo": { |
| "status": "compile_error" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_csr/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__datapath/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__mcu/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/off_by_one_counter": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__regfile/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__pc/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/sevensegment__displaydriver/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__bus/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "Weiyet_RTLStructLib/list__sorter/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__ALU/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Instruction_Memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch06__uart_dev/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mem_wb/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "scarv_xcrypto/p_mul__p_shfrot/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__open_mips_top/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Main_Decoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/state_transition": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/signal_typo": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/breathingled__breathing-led/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/signal_typo": { |
| "status": "compile_error" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/pc__lib/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__decoder/delayed_signal": { |
| "status": "llm_failed" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__axi_register_wr/inverted_condition": { |
| "status": "timeout" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/stack_control__stack_control/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/uart__uart/blocking_nonblocking": { |
| "status": "llm_failed" |
| }, |
| "snbk001_100DaysofRTL/jkff__jkff/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/edgedet_moore__edgedet_moore/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "qossayrida_PipelineProcessorDesign/ALU__ALU/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/twin_reg_8bit__twin_reg_8bit/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__registers/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__ch06/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_2x2/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/dualedge_det__dualedge_det/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__receiver/unconnected_port": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/case_swap": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__alu_control/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__top/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__mdu/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__CNU_7/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/piso__piso/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/state_transition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__pc/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch04__font_glyph/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__ch05/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__csr_unit/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__vram/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__uart/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__priority_encoder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__uart/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/transpose__delayline/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__priority_encoder/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/CNU_6__CNU_6/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "ayushc13_32-bit-RISC-processor-using-HDL-Verilog/mips32__mips32/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__eurorack_pmod/signal_typo": { |
| "status": "compile_error" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/sevensegment__bcdcoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__instr_memory/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__fifomem/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ayushc13_32-bit-RISC-processor-using-HDL-Verilog/mips32__mips32/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/missing_enable": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch04__textmode/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__intctrl/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_rx/operator_typo": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/concat_swap": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__int_fp_add/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/uart__rx/state_transition": { |
| "status": "timeout" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_core/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/Core__memory/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__registers/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__programcounter/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/adder_str__adder_str/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_long/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/mux4_str__mux4_str/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__csr_unit/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Hazard_Unit/operator_typo": { |
| "status": "compile_error" |
| }, |
| "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/state_transition": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_top/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__alignment/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "thejefflarson_little-cpu/littlecpu__regfile/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/singleport_ram__singleport_ram/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__uart/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/p_mul__p_shfrot/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mini_sopc/signal_typo": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch04__ch04/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__programcounter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/missing_reset": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__registers/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__CNU_7/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/reg_alu__lib/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_tx/missing_enable": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mem_wb/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/pedge__pedge/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__csr_unit/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/memory_tb__memory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__ch02/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/uart__uart/inverted_condition": { |
| "status": "timeout" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/case_swap": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__MUX2to1_32bit/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__branch/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo_dec/concat_swap": { |
| "status": "timeout" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/off_by_one_counter": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/wrong_bitwidth": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "srpoyrek_RISC-V/data_memory__data_memory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "mciepluc_cocotb-coverage/fifo_mem__fifo/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__I_Mem/concat_swap": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__paritygen_tx/missing_enable": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/off_by_one_counter": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/fifo__fifo/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "saivittalb_simd-processor-verification/CPUtop__SIMDshifter/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/missing_enable": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__inst_rom/missing_enable": { |
| "status": "compile_error" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "dpretet_async_fifo/async_fifo__fifomem/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/transpose__delayline/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_2/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/barrel_shifter_8bit__8bit-Barrel_Shifter/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/state_transition": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_adapter__axi_adapter_rd/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__ch04/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BTB/missing_reset": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/signal_typo": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__control_unit/state_transition": { |
| "status": "sim_failed" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Mux3_1/case_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/case_swap": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/tff__tff/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__leds/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/piso__piso/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU_Control/case_swap": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__receiver/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__cpu/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "Crimsonninja_senior_design_puf/post_mux_counter__post_mux_counter/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/sipo__sipo/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/lfsr__lfsr/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__canv_disp_agu/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Fraunhofer-IMS_airisc_core_complex/airi5c_uart__airi5c_uart/case_swap": { |
| "status": "llm_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/state_transition": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__uart_dev/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__receiver/missing_reset": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__receiver/operator_typo": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "fcayci_sv-digital-design/memory__memory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__mux/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "alexforencich_verilog-axi/axi_ram__axi_ram/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_aludec/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__arbiter/inverted_condition": { |
| "status": "timeout" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__priority_encoder/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/Core__alu_control/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/signal_typo": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/EXEStage__EXEStage/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Crimsonninja_senior_design_puf/post_mux_counter__post_mux_counter/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_pc/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__pc_reg/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__open_mips_top/signal_typo": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__tx/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__sysram/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__uart_rx/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__csr_unit/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch02__canv_disp_agu/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/ALU__ALU/case_swap": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/mean__mean/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/missing_reset": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/signal_typo": { |
| "status": "compile_error" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/state_transition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_tx/inverted_condition": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_rf/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/stack_control__stack_control/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch04__textmode/state_transition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/burst_read_master__burst_read_master/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__max_reg/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__leds/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__transmitter/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "projf_isle/ch05__FemtoRV32/state_transition": { |
| "status": "llm_failed" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "srpoyrek_RISC-V/register_bank__register_bank/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__int_fp_add/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/sevensegment__displaydriver/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/missing_enable": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "defano_digital-design/sevensegment__sevensegment/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__pc/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/missing_reset": { |
| "status": "compile_error" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/VNU_6__VNU_6/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__intctrl/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/width_bit_cutoff": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex_mem/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/missing_reset": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "defano_digital-design/sevensegment__sevensegment/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__core/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__IF_ID/missing_enable": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__qmult/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "qossayrida_PipelineProcessorDesign/InstructionMemory__InstructionMemory/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch01__display/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Inst_Memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/case_swap": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__list/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__mul16x16/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_tx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "defano_digital-design/sevensegment__displaydriver/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__fifo_sync/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/state_transition": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/Compare__Compare/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__axi_crossbar_rd/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/uart__uart/wrong_bitwidth": { |
| "status": "llm_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/alu_8bit__8bit-ALU/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Reg_File_Model/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Decode_Cyle/signal_typo": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_Wrapper/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ultraembedded_biriscv/riscv_core__biriscv_alu/case_swap": { |
| "status": "timeout" |
| }, |
| "snbk001_100DaysofRTL/lfsr__lfsr/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Data_Memory/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/modmcountr__modmcountr/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/Compare__Compare/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/piso__piso/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__alu/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_imm/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/transpose__delayline/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__pc/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__variable_shift_reg/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/sevensegment__sevensegment/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/signal_typo": { |
| "status": "compile_error" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/off_by_one_counter": { |
| "status": "sim_failed" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__branch/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch02__clut/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__adder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/dualedge_det__dualedge_det/missing_reset": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/signal_typo": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/knightrider__knight-rider/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Crimsonninja_senior_design_puf/post_mux_counter__post_mux_counter/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram_byte/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__top/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__alu/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "alexforencich_verilog-axi/axil_adapter__axil_adapter_rd/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__APB/missing_else_latch": { |
| "status": "timeout" |
| }, |
| "projf_isle/ch06__uart_dev/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__sipo_rx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__intctrl/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__mux/width_bit_cutoff": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__int_fp_mul/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/sevensegment__displaydriver/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__int_fp_add/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__mul16x16/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axil_adapter__axil_adapter_wr/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/state_transition": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_nol__seqdetmoore_nol/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__qmult/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick/state_transition": { |
| "status": "sim_ok" |
| }, |
| "thejefflarson_little-cpu/littlecpu__executor/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/missing_reset": { |
| "status": "compile_error" |
| }, |
| "OrsuVenkataKrishnaiah1235_RTL-Coding/Graytobinary__Graytobinary/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/operator_typo": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch05__FemtoRV32/inverted_condition": { |
| "status": "llm_failed" |
| }, |
| "projf_isle/ch06__ch06/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__mcu/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__sram/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__pc/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "alexforencich_verilog-axi/axi_fifo__axi_fifo_wr/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "mciepluc_cocotb-coverage/fifo_mem__fifo/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__int_fp_add/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__instantiation/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "chili-chips-ba_wireguard-fpga/sdr__sdr.ORIG/inverted_condition": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "JN513_Risco-5/Core__leds/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "srpoyrek_RISC-V/data_memory__data_memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__transmitter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/memory__memory/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__uart/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/list__sorter/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__alu_control/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/uart_tx__uart_tx/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch05__ch05/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/state_transition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__clut/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Extention_Unit/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/signal_typo": { |
| "status": "compile_error" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU_Decoder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__textmode/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__control_unit/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__sorter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__programcounter/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/konamiacceptor__debouncer/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__alu_control/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__PC/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__if_id/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/lifo__lifo/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_muldivrem/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_2/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__csr_unit/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "dpretet_async_fifo/async_fifo__rptr_empty/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/width_bit_cutoff": { |
| "status": "sim_failed" |
| }, |
| "0thbit_CRC_parallel/crc__CRC/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/InstructionMemory__InstructionMemory/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Wrapper/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__APB/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_adapter__axi_adapter_wr/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch02__clut/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_ol__seqdetmoore_ol/missing_reset": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/signal_typo": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__tx/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/pc__lib/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__pc_reg/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Mux/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/missing_enable": { |
| "status": "compile_error" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo_raw_wr/inverted_condition": { |
| "status": "timeout" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/wrong_bitwidth": { |
| "status": "timeout" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/CNU_6__CNU_6/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/case_swap": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC_Adderr/missing_enable": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_top__router_top/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/updowncntr__updowncntr/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__gfx_dev/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_mul/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_register/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mem_wb/missing_reset": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__mdu/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/case_swap": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/signal_typo": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/state_transition": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/missing_reset": { |
| "status": "compile_error" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__pc/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_wr/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/konamiacceptor__debouncer/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/missing_reset": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/missing_enable": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/list__list/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BHT/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/signal_typo": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "srpoyrek_RISC-V/data_memory__data_memory/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/TicketMachine__TicketMachine/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__piso_tx/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__add_normalizer/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_reset": { |
| "status": "compile_error" |
| }, |
| "thejefflarson_little-cpu/littlecpu__decoder/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/pipo__pipo/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/systolic_array_top__systolic_array_top/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "qossayrida_PipelineProcessorDesign/InstructionMemory__InstructionMemory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Reg_File_Model/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "dpretet_async_fifo/async_fifo__async_fifo/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_3/missing_reset": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/top__sysmgr/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "wicker_SystemVerilog-FSM/LandingGearController__LandingGear/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex_mem/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "OrsuVenkataKrishnaiah1235_RTL-Coding/srff__srff/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_crossbar_wrap_4x4__priority_encoder/concat_swap": { |
| "status": "timeout" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/missing_enable": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id_ex/missing_reset": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__uart/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/burst_read_master__burst_read_master/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__EX_MEM/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/vca__vca/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__sys_dev/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Wrapper/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_reset": { |
| "status": "compile_error" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/lfsr__lfsr/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/state_transition": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_Wrapper/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU_Decoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__PC_clk/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__sync_w2r/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__rptr_empty/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/case_swap": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/tb__tpu/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/width_bit_cutoff": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__wptr_full/operator_typo": { |
| "status": "timeout" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__uart_rx/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/sevensegment__sevensegment/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__alu/case_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/operator_typo": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__uart/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/uart_tx__uart_tx/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__font_glyph/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_dma__axi_dma_rd/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_rx/state_transition": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/twin_reg_8bit__twin_reg_8bit/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__branch/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/list__list/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/state_transition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Forwarding_Unit/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__mux/delayed_signal": { |
| "status": "llm_failed" |
| }, |
| "Weiyet_RTLStructLib/fifo__fifo/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__BPU/case_swap": { |
| "status": "compile_error" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__int_fp_mul/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__alu/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/counter8bit__counter8bit/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/signal_typo": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/top__top/missing_reset": { |
| "status": "compile_error" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Pipeline_Top/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/sevensegment__sevensegment/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mux/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__int_fp_mul/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "dpretet_async_fifo/async_fifo__rptr_empty/missing_reset": { |
| "status": "timeout" |
| }, |
| "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__sc_bus/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/encoder4x2__encoder4x2/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "dpretet_async_fifo/async_fifo__sync_r2w/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__VNU_3/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__fifo_sync/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__cpu/signal_typo": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_long/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__sys_dev/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__uart_dev/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "ayushc13_32-bit-RISC-processor-using-HDL-Verilog/mips32__mips32/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_aludec/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/signal_typo": { |
| "status": "compile_error" |
| }, |
| "mciepluc_cocotb-coverage/fifo_mem__fifo/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__regfile/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Crimsonninja_senior_design_puf/shift_register__shift_register/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/case_swap": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_rx/missing_reset": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/case_swap": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__top/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_ol__seqdetmoore_ol/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/memory__memory/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Decode_Cyle/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/Compare__Compare/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/breathingled__breathing-led/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/memory_tb__memory/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch06__gfx_dev/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_top__router_top/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__accelerator/signal_typo": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/missing_reset": { |
| "status": "timeout" |
| }, |
| "cocotb_cocotb-bus/burst_read_master__burst_read_master/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__alu/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__core/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__intctrl/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_mul/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_cdma__axi_cdma/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/list__list/state_transition": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/TicketMachine__TicketMachine/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/cal__cal/state_transition": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_decode_mem1/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "ultraembedded_biriscv/riscv_core__biriscv_csr_regfile/case_swap": { |
| "status": "timeout" |
| }, |
| "projf_isle/ch06__lfsr/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/state_transition": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mini_sopc/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/list__sorter/state_transition": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__textmode/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/pc_control__pc_control/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/array_buses__array_buses/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__sync_w2r/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/off_by_one_counter": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/signal_typo": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__EX_MEM/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch06__uart_rx/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__qmult/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/uart__rx/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__piso_tx/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/dualedge_det__dualedge_det/state_transition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__core/delayed_signal": { |
| "status": "llm_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/case_swap": { |
| "status": "compile_error" |
| }, |
| "thejefflarson_little-cpu/littlecpu__decoder/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/vca__vca/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_rx/missing_enable": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/state_transition": { |
| "status": "sim_failed" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__mcu/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__mcu/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "CharanK-glitch_RV32I/ALU__ALU/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/case_swap": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__transmitter/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__sram/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/sevensegment__displaydriver/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__debouncer/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__immediate_generator/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/dual_edge_ff__dual_edge_ff/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__adder/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__pc/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_rx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ID_EX/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__fifo_sync/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "thejefflarson_little-cpu/littlecpu__executor/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__immediate_generator/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "chili-chips-ba_wireguard-fpga/sdr__sdr.ORIG/wrong_bitwidth": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mem/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo/inverted_condition": { |
| "status": "timeout" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_wr/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "OrsuVenkataKrishnaiah1235_RTL-Coding/srff__srff/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__mem/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/signal_typo": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Master/state_transition": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/InstructionMemory__InstructionMemory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/systolic_array_tb__PE/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/operator_typo": { |
| "status": "compile_error" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/concat_swap": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/state_transition": { |
| "status": "sim_failed" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__LDU/case_swap": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_tx/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__PC/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "semify-eda_go.debug/wfg_stim_sine__wfg_stim_sine/concat_swap": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__core/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__paritychecker_rx/missing_else_latch": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/knightrider__knight-rider/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/uart__tx/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Control_Unit_Top/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_slave/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__rptr_empty/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_cdma__axi_cdma/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__instr_memory/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "saivittalb_simd-processor-verification/CPUtop__CPUtop/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/uart_tx__uart_tx/state_transition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/off_by_one_counter": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch06__sys_dev/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/case_swap": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/missing_reset": { |
| "status": "timeout" |
| }, |
| "JN513_Risco-5/Core__core/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__top/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__mac/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "dpretet_async_fifo/async_fifo__wptr_full/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fsm__router_fsm/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__instr_memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/missing_enable": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/case_swap": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Fetch_Cycle/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/off_by_one_counter": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/konamiacceptor__konamiacceptor/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/memory_tb__memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__mac/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "projf_isle/ch04__ch04/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/operator_typo": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_tx/state_transition": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__code_defs_pkg/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/mean__mean/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__branch/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "mciepluc_cocotb-coverage/fifo_mem__fifo/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_decode/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/tb__tb/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch05__ch05/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/state_transition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__vram/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ALU/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_fifo__axi_fifo_rd/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/signal_typo": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch01__display/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch05__FemtoRV32/wrong_bitwidth": { |
| "status": "llm_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "aditeyabaral_DDCO-Lab-UE18CS207/mproc_mem__lib/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/missing_reset": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/breathingled__breathing-led/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__sysram/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__fifomem/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__registers/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/missing_reset": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_rd/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/concat_swap": { |
| "status": "compile_error" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RISCV_CPU/width_bit_cutoff": { |
| "status": "waveform_identical" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/off_by_one_counter": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__memory/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__PC/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "OrsuVenkataKrishnaiah1235_RTL-Coding/srff__srff/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/mean__mean/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "JN513_Risco-5/Core__core/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_wr/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Data_Mem/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Vaibhav-Gunthe_Verilog-Projects/D_ff_synchronous_reset__d_ff_synchronous_reset/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__axi_interconnect/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__mac/signal_typo": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__pooler/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/missing_enable": { |
| "status": "compile_error" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__core/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick/missing_reset": { |
| "status": "compile_error" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__bus/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__inst_rom/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "CharanK-glitch_RV32I/ALU__ALU/case_swap": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__konamicoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__I_Mem/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_top/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__lock_state/signal_typo": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__tx/state_transition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_tx/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regfile/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "Crimsonninja_senior_design_puf/up_counter__up_counter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/uart__uart/missing_reset": { |
| "status": "timeout" |
| }, |
| "snbk001_100DaysofRTL/tff__jkff/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__ch05/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_muldivrem/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/signal_typo": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch04__textmode/off_by_one_counter": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/state_transition": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/case_swap": { |
| "status": "llm_failed" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__mul2x2/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/konamiacceptor__konamicoder/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__ch02/case_swap": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__delayline/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Hazard_unit/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__decoder/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__RISC_V_Wrapper/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane_2ppc__mipi_csi_rx_raw_depacker_8b2lane_2ppc/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/signal_typo": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__control_unit/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/uart__uart/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/signal_typo": { |
| "status": "compile_error" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/uart_tx__uart_tx/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "Crimsonninja_senior_design_puf/post_mux_counter__post_mux_counter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/pc_control__pc_control/case_swap": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/seqdet__seqdet/state_transition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_reset": { |
| "status": "compile_error" |
| }, |
| "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__tram/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/updowncntr__updowncntr/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ultraembedded_biriscv/riscv_core__biriscv_regfile/case_swap": { |
| "status": "timeout" |
| }, |
| "projf_isle/ch05__FemtoRV32/missing_enable": { |
| "status": "llm_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__ch05/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/AXI4Lite_translator__axi/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_FazyRV/fazyrv_top__fazyrv_cntrl/missing_else_latch": { |
| "status": "timeout" |
| }, |
| "Weiyet_RTLStructLib/lifo__lifo/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "Crimsonninja_senior_design_puf/mux_16to1__mux_16to1/case_swap": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/width_bit_cutoff": { |
| "status": "sim_failed" |
| }, |
| "Crimsonninja_senior_design_puf/shift_register__shift_register/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__sys_dev/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/knightrider__knight-rider/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/burst_read_master__burst_read_master/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/signal_typo": { |
| "status": "compile_error" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__pc/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_rd/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_clgen/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/edgedet_moore__edgedet_moore/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_indec/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/off_by_one_counter": { |
| "status": "compile_error" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch02__canv_disp_agu/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__MEM_WB/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/uart__rx/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/top__top/signal_typo": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__mac/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "yaseensalah_Digital-Design-of-FIR-Filter/fir_filter__fir_filter/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__eurorack_pmod/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch05__FemtoRV32/missing_reset": { |
| "status": "llm_failed" |
| }, |
| "JN513_Risco-5/Core__alu/delayed_signal": { |
| "status": "llm_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/operator_typo": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/mean__mean/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__gearbox_seq/missing_reset": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/seqdet_ol__seqdet_ol/missing_reset": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/counter8bit__counter8bit/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_rx/wrong_bitwidth": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__uart_dev/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "defano_digital-design/sevensegment__displaydriver/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_CO/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__if_id/missing_reset": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__receiver/signal_typo": { |
| "status": "compile_error" |
| }, |
| "snbk001_100DaysofRTL/pipo__pipo/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/missing_reset": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/endian_swapper_sv__endian_swapper/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__sram/blocking_nonblocking": { |
| "status": "timeout" |
| }, |
| "JN513_Risco-5/Core__registers/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/instantiation__RAM/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "srpoyrek_RISC-V/data_memory__data_memory/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/uart__rx/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_ol__seqdetmoore_ol/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo_raw/inverted_condition": { |
| "status": "timeout" |
| }, |
| "projf_isle/ch06__uart_rx/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__datapath/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__cpu/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_vfifo__axi_vfifo_raw_rd/concat_swap": { |
| "status": "llm_failed" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Memory_Cycle/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__leds/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__adder/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_sync__router_sync/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Decode_Cyle/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch05__ch05/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Register_File/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__list/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/doubly_linked_list__doubly_linked_list/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__if_id/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Decode_Cyle/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "WilliamZhang20_ECE298A-TPU/control_unit_tb__control_unit/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__D_Mem/concat_swap": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Main_Decoder/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__priority_encoder/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "Crimsonninja_senior_design_puf/up_counter__up_counter/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/avalon_streaming__avalon_streaming/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_rx/inverted_condition": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__scrambler/signal_typo": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Extention_Unit/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/operator_typo": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/missing_enable": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__leds/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__d_ledbar/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_moore/signal_typo": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__ALU/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/VNU_6__VNU_6/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter_combined/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch06__fifo_sync/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "shahsaumya00_Floating-Point-Adder/adder__adder_pipeline/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/signal_typo": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/Extender__Extender/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/case_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/case_swap": { |
| "status": "compile_error" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Data_Mem/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__programcounter/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation/RISC_V_Wrapper__Control_Unit/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__adder/missing_else_latch": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_fifo__router_fifo/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__memory/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/transpose__transpose/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__SPI_SLAVE/signal_typo": { |
| "status": "compile_error" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__cla_nbit/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Writeback_Cycle/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/ClkDivider__clk_divider/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__sysmgr/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_add__add_normalizer/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__input_mux/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_top/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__gfx_dev/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__regfile/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch04__font_glyph/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/width_bit_cutoff": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/fifo__fifo/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Pipeline_Top/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch06__gfx_dev/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_divrem/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__pc_reg/missing_enable": { |
| "status": "compile_error" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_pmul/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/missing_enable": { |
| "status": "compile_error" |
| }, |
| "mciepluc_cocotb-coverage/fifo_mem__fifo/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/sevensegment__sevensegment/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__ALU/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Mux/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__comparator2/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/transpose__delayline/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Hazard_unit/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b4lane__mipi_csi_rx_raw_depacker_8b4lane/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "thejefflarson_little-cpu/littlecpu__accessor/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__csr_unit/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__mac_manual/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/list__sorter/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__MUX4to1_32bit/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_dma__axi_dma_rd/inverted_condition": { |
| "status": "timeout" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/pmod_i2c_master__pmod_i2c_master/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/adder_str__full_adder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "ayushc13_32-bit-RISC-processor-using-HDL-Verilog/mips32__mips32/case_swap": { |
| "status": "sim_ok" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__RF/operator_typo": { |
| "status": "compile_error" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__bitchecker_rx/wrong_bitwidth": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "dpretet_async_fifo/async_fifo__sync_w2r/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/missing_else_latch": { |
| "status": "compile_error" |
| }, |
| "JN513_Risco-5/Core__csr_unit/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "biren15_Design-and-Implementation-of-a-Cruise-Control-System/cruisecontrol__cruisecontrol/off_by_one_counter": { |
| "status": "waveform_identical" |
| }, |
| "alexforencich_verilog-axi/axi_dma__axi_dma_wr/inverted_condition": { |
| "status": "llm_failed" |
| }, |
| "snbk001_100DaysofRTL/muxcond__muxcond/case_swap": { |
| "status": "sim_ok" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Execute_Cycle/signal_typo": { |
| "status": "sim_ok" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "dpretet_async_fifo/async_fifo__wptr_full/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id_ex/blocking_nonblocking": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ID_EX/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id_ex/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__wishbone_master/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "snbk001_100DaysofRTL/seqdet_ol__seqdet_ol/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__csr_unit/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/delayed_signal": { |
| "status": "compile_error" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Data_Memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__tanh_lut/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__tx_gearbox/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_Router-1-x-3-/router_reg__router_reg/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__decoder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Weiyet_RTLStructLib/lifo__lifo/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "projf_isle/ch04__textmode/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__rx_mac/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_alu/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/singly_linked_list__singly_linked_list/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_regbank/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__regfile/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_AMPA_APB4_Protocol/APB_Wrapper__APB_Slave/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_tb/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/state_transition": { |
| "status": "sim_failed" |
| }, |
| "defano_digital-design/uart__rx/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_dma__axi_dma_wr/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "dpretet_async_fifo/async_fifo__sync_r2w/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__memory/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_tick__fsm_tick_en/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM/SPI__SPI/missing_enable": { |
| "status": "waveform_identical" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__ImmGen/concat_swap": { |
| "status": "compile_error" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_rd/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/top__arbiter/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__tanh_lut/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "Fraunhofer-IMS_airisc_core_complex/airi5c_spi__airi5c_spi/case_swap": { |
| "status": "llm_failed" |
| }, |
| "projf_isle/ch01__display/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__timer/missing_else_latch": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/list__list/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__rv32i_lsu/signal_typo": { |
| "status": "compile_error" |
| }, |
| "semify-eda_go.debug/ste_shift_reg__ste_shift_reg/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/CNU_6__CNU_6/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "apfaudio_eurorack-pmod/top__pmod_i2c_master/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "mciepluc_cocotb-coverage/pkt_switch__pkt_switch/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "apfaudio_eurorack-pmod/top__debug_uart/unconnected_port": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder_tb/unconnected_port": { |
| "status": "sim_failed" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__control_unit/inverted_condition": { |
| "status": "waveform_identical" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__convolver/unconnected_port": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__max_reg/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "thedatabusdotio_fpga-ml-accelerator/acclerator__control_logic2/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_rx/missing_reset": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "defano_digital-design/konamiacceptor__debouncer/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "roo16kie_MAC_Verilog/mac__mac/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__mdu/blocking_nonblocking": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/systolic_array_tb__systolic_array_2x2/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "fcayci_sv-digital-design/fsm_pattern_moore__fsm_pattern_mealy/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_tx/missing_reset": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "JN513_Risco-5/Core__mdu/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "cocotb_cocotb-bus/top__axi_register_rd/wrong_bitwidth": { |
| "status": "sim_failed" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__counter_rx/blocking_nonblocking": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "snbk001_100DaysofRTL/seqmultiplier__seqmultiplier/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/hash_table__hash_table/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "accomdemy_accomdemy_rv32i/cpu__dm_control/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__PC/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Sign_Extend/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__memory/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_slave/wrong_bitwidth": { |
| "status": "waveform_identical" |
| }, |
| "cocotb_cocotb-bus/burst_read_master__burst_read_master/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "cocotb_cocotb-bus/top__axi_ram/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "Weiyet_RTLStructLib/fifo__fifo/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__fsm_rx/missing_else_latch": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "apfaudio_eurorack-pmod/vca__vca/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__datapath/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "Weiyet_RTLStructLib/list__adder/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "Mr-Bossman_KISC-V/soc_top__apb_align/delayed_signal": { |
| "status": "waveform_identical" |
| }, |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/alu__alu/case_swap": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__pc_reg/operator_typo": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/fsm_counter__fsm_counter/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/Extender__Extender/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/rx_gearbox__rx_gearbox/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__registers/operator_typo": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_nol__seqdetmoore_nol/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_axil_adapter__axi_axil_adapter_rd/inverted_condition": { |
| "status": "sim_failed" |
| }, |
| "nimanaqavi_Verilog-MathFunctions/part_Ln_TOP__Ln_DP/case_swap": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/TicketMachine__TicketMachine/state_transition": { |
| "status": "waveform_identical" |
| }, |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core/Pipeline_top__Decode_Cyle/blocking_nonblocking": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/VNU_6__VNU_6/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "snbk001_100DaysofRTL/seqdetmoore_nol__seqdetmoore_nol/missing_reset": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/systolic_array_top__pe/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch05__FemtoRV32/case_swap": { |
| "status": "llm_failed" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/delayed_signal": { |
| "status": "sim_ok" |
| }, |
| "qossayrida_PipelineProcessorDesign/IFStage__IFStage/case_swap": { |
| "status": "sim_ok" |
| }, |
| "wicker_SystemVerilog-FSM/TicketMachine__TicketMachine/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/operator_typo": { |
| "status": "waveform_identical" |
| }, |
| "projf_isle/ch06__gfx_dev/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__pcs/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "biren15_Design-and-Verification-of-LDPC-Decoder/LDPC_decoder_TOP__CNU_7/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "chili-chips-ba_wireguard-fpga/led_test__led_test/operator_typo": { |
| "status": "sim_ok", |
| "examples_count": 0 |
| }, |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3/mipi_csi_rx_raw_depacker_8b2lane__mipi_csi_rx_raw_depacker_8b2lane/width_bit_cutoff": { |
| "status": "waveform_identical" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__mcu/unconnected_port": { |
| "status": "waveform_identical" |
| }, |
| "JN513_Risco-5/Core__memory/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac__tx_mac/operator_typo": { |
| "status": "llm_failed" |
| }, |
| "erihsu_INT_FP_MAC/int_fp_mul__int_fp_mul/missing_reset": { |
| "status": "sim_failed" |
| }, |
| "ultraembedded_biriscv/riscv_core__biriscv_lsu/case_swap": { |
| "status": "timeout" |
| }, |
| "arhamhashmi01_Axi4-lite/axi4_lite_top__axi4_lite_master/missing_reset": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__id/case_swap": { |
| "status": "compile_error" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__regfile/missing_enable": { |
| "status": "compile_error" |
| }, |
| "sumukhathrey_Verilog_ASIC_Design/RegisterFile__RegisterFile/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "defano_digital-design/konamiacceptor__displaydriver/missing_reset": { |
| "status": "sim_ok" |
| }, |
| "meiniKi_RV32I_SC_Logisim/mcu__ram/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__ex/signal_typo": { |
| "status": "compile_error" |
| }, |
| "Weiyet_RTLStructLib/table_top__table/inverted_condition": { |
| "status": "compile_error" |
| }, |
| "fcayci_sv-digital-design/memory__memory/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/xc_malu__xc_malu_pmul/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__mac_pcs/signal_typo": { |
| "status": "compile_error" |
| }, |
| "WilliamZhang20_ECE298A-TPU/mmu_feeder_tb__mmu_feeder/operator_typo": { |
| "status": "sim_ok" |
| }, |
| "zhangxin6_iverilog_testbench/display_pal__display_pal/off_by_one_counter": { |
| "status": "sim_ok" |
| }, |
| "alexforencich_verilog-axi/axi_dp_ram__axi_ram_wr_rd_if/inverted_condition": { |
| "status": "timeout" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__Control/operator_typo": { |
| "status": "compile_error" |
| }, |
| "apfaudio_eurorack-pmod/ak4619__ak4619/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "JN513_Risco-5/Core__control_unit/missing_enable": { |
| "status": "sim_failed" |
| }, |
| "snbk001_100DaysofRTL/seqdet__seqdet/missing_reset": { |
| "status": "compile_error" |
| }, |
| "akira2963753_Pipelined-RV32-SoC/RISCV_CPU__CSR/missing_enable": { |
| "status": "compile_error" |
| }, |
| "defano_digital-design/knightrider__knight-rider/wrong_bitwidth": { |
| "status": "sim_ok" |
| }, |
| "mnmhdanas_UART-protocol/UARTtb__piso_tx/missing_enable": { |
| "status": "sim_ok" |
| }, |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory/SPI_Wrapper__RAM/inverted_condition": { |
| "status": "sim_ok" |
| }, |
| "scarv_xcrypto/p_mul__p_mul/concat_swap": { |
| "status": "sim_ok" |
| }, |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules/spi_top__spi_shift_reg/concat_swap": { |
| "status": "waveform_identical" |
| }, |
| "zhangxin6_iverilog_testbench/hdlcrev__hdlcrev/signal_typo": { |
| "status": "compile_error" |
| }, |
| "projf_isle/ch06__sys_dev/case_swap": { |
| "status": "waveform_identical" |
| }, |
| "lucky-wfw_IC_System_Design/mini_sopc__inst_rom/wrong_bitwidth": { |
| "status": "compile_error" |
| }, |
| "ttchisholm_10g-low-latency-ethernet/mac_pcs__encoder/inverted_condition": { |
| "status": "sim_ok" |
| } |
| }, |
| "bug_types_attempted": { |
| "nimanaqavi_Verilog-MathFunctions": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "saivittalb_simd-processor-verification": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable" |
| ], |
| "0thbit_CRC_parallel": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "akira2963753_Pipelined-RV32-SoC": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "aignacio_cocotbext-ahb": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "biren15_Design-and-Verification-of-LDPC-Decoder": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "hurisson_pyuvm_primer": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "OrsuVenkataKrishnaiah1235_RTL-Coding": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "JN513_Risco-5": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "WilliamZhang20_ECE298A-TPU": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "meiniKi_RV32I_SC_Logisim": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "scarv_xcrypto": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "apfaudio_eurorack-pmod": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "qossayrida_PipelineProcessorDesign": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "mnmhdanas_UART-protocol": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "MohamedHussein27_SPI_Slave_With_Single_Port_Memory": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Vaibhav-Gunthe_Verilog-Projects": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "semify-eda_go.debug": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Fraunhofer-IMS_airisc_core_complex": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "circuitvalley_USB_C_Industrial_Camera_FPGA_USB3": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "ayushc13_32-bit-RISC-processor-using-HDL-Verilog": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff" |
| ], |
| "srpoyrek_RISC-V": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "aditeyabaral_DDCO-Lab-UE18CS207": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "roo16kie_MAC_Verilog": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "thedatabusdotio_fpga-ml-accelerator": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "selimsandal_OneShotNPU": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "snbk001_100DaysofRTL": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "dpretet_async_fifo": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Mr-Bossman_KISC-V": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Crimsonninja_senior_design_puf": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "phoeniX-Digital-Design_phoeniX": [ |
| "blocking_nonblocking" |
| ], |
| "zhangxin6_iverilog_testbench": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "sumukhathrey_Verilog_ASIC_Design": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "mciepluc_cocotb-coverage": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "chili-chips-ba_wireguard-fpga": [ |
| "blocking_nonblocking", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_reset", |
| "operator_typo", |
| "signal_typo", |
| "unconnected_port", |
| "wrong_bitwidth" |
| ], |
| "cocotb_cocotb-bus": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "MohamedHussein27_AMPA_APB4_Protocol": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "CharanK-glitch_RV32I": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "alexforencich_verilog-axi": [ |
| "case_swap", |
| "concat_swap" |
| ], |
| "Abdelrahman1810_SPI_Slave_with_Single_Port_RAM": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "yaseensalah_Digital-Design-of-FIR-Filter": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "accomdemy_accomdemy_rv32i": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "meiniKi_FazyRV": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "defano_digital-design": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "MohamedHussein27_RISC-V-Single-Cycle-Implementation": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "shahsaumya00_Floating-Point-Adder": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "projf_isle": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "erihsu_INT_FP_MAC": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "thejefflarson_little-cpu": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Weiyet_RTLStructLib": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "mnmhdanas_Router-1-x-3-": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "biren15_Design-and-Implementation-of-a-Cruise-Control-System": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo" |
| ], |
| "Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "arhamhashmi01_Axi4-lite": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "ttchisholm_10g-low-latency-ethernet": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "lucky-wfw_IC_System_Design": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "wicker_SystemVerilog-FSM": [ |
| "case_swap", |
| "concat_swap", |
| "inverted_condition", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ], |
| "fcayci_sv-digital-design": [ |
| "blocking_nonblocking", |
| "case_swap", |
| "concat_swap", |
| "delayed_signal", |
| "inverted_condition", |
| "missing_else_latch", |
| "missing_enable", |
| "missing_reset", |
| "off_by_one_counter", |
| "operator_typo", |
| "signal_typo", |
| "state_transition", |
| "unconnected_port", |
| "width_bit_cutoff", |
| "wrong_bitwidth" |
| ] |
| } |
| } |
