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/* Define _STRING_ARCH_unaligned. Generic version.
Copyright (C) 2016-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<https://www.gnu.org/licenses/>. */
/* Define to 1 if architecture can access unaligned multi-byte
variables. */
#define _STRING_ARCH_unaligned 0
| {
"language": "Assembly"
} |
;; A large WAST blob which contains the implementations of all the intrinsics
;; that we inject as part of this module. This blob was generated from a Rust
;; program [1] which uses the Rust compiler-builtins project. It's not
;; necessarily perfect but gets the job done! The idea here is that we inject
;; these pretty early so they can continue to be optimized by further passes
;; (aka inlining and whatnot)
;;
;; LOCAL MODS done by hand afterwards:
;; * Remove hardcoded address 1024 which was used for temporary data; instead
;; add $wasm-intrinsics-temp-i64 global for that.
;; * Fix function type of __wasm_ctz_i64, which was wrong somehow,
;; i32, i32 => i32 instead of i64 => i64
;; * Remove unnecessary memory import.
;;
;; [1]: https://gist.github.com/alexcrichton/e7ea67bcdd17ce4b6254e66f77165690
(module
(type $0 (func (param i64 i64) (result i64)))
(type $1 (func (param f32) (result f32)))
(type $2 (func (param f64) (result f64)))
(type $3 (func (param i32) (result i32)))
(type $4 (func (param i32 i32) (result i32)))
(type $5 (func (param i64) (result i64)))
(export "__wasm_i64_sdiv" (func $__wasm_i64_sdiv))
(export "__wasm_i64_udiv" (func $__wasm_i64_udiv))
(export "__wasm_i64_srem" (func $__wasm_i64_srem))
(export "__wasm_i64_urem" (func $__wasm_i64_urem))
(export "__wasm_i64_mul" (func $__wasm_i64_mul))
(export "__wasm_trunc_f32" (func $__wasm_trunc_f32))
(export "__wasm_trunc_f64" (func $__wasm_trunc_f64))
(export "__wasm_ctz_i32" (func $__wasm_ctz_i32))
(export "__wasm_ctz_i64" (func $__wasm_ctz_i64))
(export "__wasm_rotl_i32" (func $__wasm_rotl_i32))
(export "__wasm_rotr_i32" (func $__wasm_rotr_i32))
(export "__wasm_rotl_i64" (func $__wasm_rotl_i64))
(export "__wasm_rotr_i64" (func $__wasm_rotr_i64))
(export "__wasm_nearest_f32" (func $__wasm_nearest_f32))
(export "__wasm_nearest_f64" (func $__wasm_nearest_f64))
(export "__wasm_popcnt_i32" (func $__wasm_popcnt_i32))
(export "__wasm_popcnt_i64" (func $__wasm_popcnt_i64))
(global $__wasm-intrinsics-temp-i64 (mut i64) (i64.const 0))
;; lowering of the i32.popcnt instruction, counts the number of bits set in the
;; input and returns the result
(func $__wasm_popcnt_i32 (param $var$0 i32) (result i32)
(local $var$1 i32)
(block $label$1 (result i32)
(loop $label$2
(drop
(br_if $label$1
(local.get $var$1)
(i32.eqz
(local.get $var$0)
)
)
)
(local.set $var$0
(i32.and
(local.get $var$0)
(i32.sub
(local.get $var$0)
(i32.const 1)
)
)
)
(local.set $var$1
(i32.add
(local.get $var$1)
(i32.const 1)
)
)
(br $label$2)
)
)
)
;; lowering of the i64.popcnt instruction, counts the number of bits set in the
;; input and returns the result
(func $__wasm_popcnt_i64 (param $var$0 i64) (result i64)
(local $var$1 i64)
(block $label$1 (result i64)
(loop $label$2
(drop
(br_if $label$1
(local.get $var$1)
(i64.eqz
(local.get $var$0)
)
)
)
(local.set $var$0
(i64.and
(local.get $var$0)
(i64.sub
(local.get $var$0)
(i64.const 1)
)
)
)
(local.set $var$1
(i64.add
(local.get $var$1)
(i64.const 1)
)
)
(br $label$2)
)
)
)
;; lowering of the i64.div_s instruction, return $var0 / $var$1
(func $__wasm_i64_sdiv (; 0 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(call $_ZN17compiler_builtins3int4sdiv3Div3div17he78fc483e41d7ec7E
(local.get $var$0)
(local.get $var$1)
)
)
;; lowering of the i64.div_u instruction, return $var0 / $var$1
(func $__wasm_i64_udiv (; 1 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(call $_ZN17compiler_builtins3int4udiv10divmod_u6417h6026910b5ed08e40E
(local.get $var$0)
(local.get $var$1)
)
)
;; lowering of the i64.rem_s instruction, return $var0 % $var$1
(func $__wasm_i64_srem (; 2 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(call $_ZN17compiler_builtins3int4sdiv3Mod4mod_17h2cbb7bbf36e41d68E
(local.get $var$0)
(local.get $var$1)
)
)
;; lowering of the i64.rem_u instruction, return $var0 % $var$1
(func $__wasm_i64_urem (; 3 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(drop
(call $_ZN17compiler_builtins3int4udiv10divmod_u6417h6026910b5ed08e40E
(local.get $var$0)
(local.get $var$1)
)
)
(global.get $__wasm-intrinsics-temp-i64)
)
;; lowering of the i64.mul instruction, return $var0 * $var$1
(func $__wasm_i64_mul (; 4 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(call $_ZN17compiler_builtins3int3mul3Mul3mul17h070e9a1c69faec5bE
(local.get $var$0)
(local.get $var$1)
)
)
;; lowering of the f32.trunc instruction, rounds to the nearest integer,
;; towards zero
(func $__wasm_trunc_f32 (; 5 ;) (type $1) (param $var$0 f32) (result f32)
(select
(f32.ceil
(local.get $var$0)
)
(f32.floor
(local.get $var$0)
)
(f32.lt
(local.get $var$0)
(f32.const 0)
)
)
)
;; lowering of the f64.trunc instruction, rounds to the nearest integer,
;; towards zero
(func $__wasm_trunc_f64 (; 6 ;) (type $2) (param $var$0 f64) (result f64)
(select
(f64.ceil
(local.get $var$0)
)
(f64.floor
(local.get $var$0)
)
(f64.lt
(local.get $var$0)
(f64.const 0)
)
)
)
;; lowering of the i32.ctz instruction, counting the number of zeros in $var$0
(func $__wasm_ctz_i32 (; 7 ;) (type $3) (param $var$0 i32) (result i32)
(if
(local.get $var$0)
(return
(i32.sub
(i32.const 31)
(i32.clz
(i32.xor
(i32.add
(local.get $var$0)
(i32.const -1)
)
(local.get $var$0)
)
)
)
)
)
(i32.const 32)
)
;; lowering of the i64.ctz instruction, counting the number of zeros in $var$0
(func $__wasm_ctz_i64 (; 8 ;) (type $5) (param $var$0 i64) (result i64)
(if
(i32.eqz
(i64.eqz
(local.get $var$0)
)
)
(return
(i64.sub
(i64.const 63)
(i64.clz
(i64.xor
(i64.add
(local.get $var$0)
(i64.const -1)
)
(local.get $var$0)
)
)
)
)
)
(i64.const 64)
)
;; lowering of the i32.rotl instruction, rotating the first argument, with
;; wraparound, by the second argument
(func $__wasm_rotl_i32 (; 8 ;) (type $4) (param $var$0 i32) (param $var$1 i32) (result i32)
(local $var$2 i32)
(i32.or
(i32.shl
(i32.and
(i32.shr_u
(i32.const -1)
(local.tee $var$2
(i32.and
(local.get $var$1)
(i32.const 31)
)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i32.shr_u
(i32.and
(i32.shl
(i32.const -1)
(local.tee $var$1
(i32.and
(i32.sub
(i32.const 0)
(local.get $var$1)
)
(i32.const 31)
)
)
)
(local.get $var$0)
)
(local.get $var$1)
)
)
)
;; lowering of the i32.rotr instruction, rotating the first argument, with
;; wraparound, by the second argument
(func $__wasm_rotr_i32 (; 9 ;) (type $4) (param $var$0 i32) (param $var$1 i32) (result i32)
(local $var$2 i32)
(i32.or
(i32.shr_u
(i32.and
(i32.shl
(i32.const -1)
(local.tee $var$2
(i32.and
(local.get $var$1)
(i32.const 31)
)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i32.shl
(i32.and
(i32.shr_u
(i32.const -1)
(local.tee $var$1
(i32.and
(i32.sub
(i32.const 0)
(local.get $var$1)
)
(i32.const 31)
)
)
)
(local.get $var$0)
)
(local.get $var$1)
)
)
)
;; lowering of the i64.rotl instruction, rotating the first argument, with
;; wraparound, by the second argument
(func $__wasm_rotl_i64 (; 10 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i64)
(i64.or
(i64.shl
(i64.and
(i64.shr_u
(i64.const -1)
(local.tee $var$2
(i64.and
(local.get $var$1)
(i64.const 63)
)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i64.shr_u
(i64.and
(i64.shl
(i64.const -1)
(local.tee $var$1
(i64.and
(i64.sub
(i64.const 0)
(local.get $var$1)
)
(i64.const 63)
)
)
)
(local.get $var$0)
)
(local.get $var$1)
)
)
)
;; lowering of the i64.rotr instruction, rotating the first argument, with
;; wraparound, by the second argument
(func $__wasm_rotr_i64 (; 11 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i64)
(i64.or
(i64.shr_u
(i64.and
(i64.shl
(i64.const -1)
(local.tee $var$2
(i64.and
(local.get $var$1)
(i64.const 63)
)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i64.shl
(i64.and
(i64.shr_u
(i64.const -1)
(local.tee $var$1
(i64.and
(i64.sub
(i64.const 0)
(local.get $var$1)
)
(i64.const 63)
)
)
)
(local.get $var$0)
)
(local.get $var$1)
)
)
)
;; lowering of the f32.nearest instruction, rounding the input to the nearest
;; integer while breaking ties by rounding to even
(func $__wasm_nearest_f32 (; 12 ;) (type $1) (param $var$0 f32) (result f32)
(local $var$1 f32)
(local $var$2 f32)
(if
(i32.eqz
(f32.lt
(local.tee $var$2
(f32.sub
(local.get $var$0)
(local.tee $var$1
(f32.floor
(local.get $var$0)
)
)
)
)
(f32.const 0.5)
)
)
(block
(local.set $var$0
(f32.ceil
(local.get $var$0)
)
)
(if
(f32.gt
(local.get $var$2)
(f32.const 0.5)
)
(return
(local.get $var$0)
)
)
(local.set $var$1
(select
(local.get $var$1)
(local.get $var$0)
(f32.eq
(f32.sub
(local.tee $var$2
(f32.mul
(local.get $var$1)
(f32.const 0.5)
)
)
(f32.floor
(local.get $var$2)
)
)
(f32.const 0)
)
)
)
)
)
(local.get $var$1)
)
;; lowering of the f64.nearest instruction, rounding the input to the nearest
;; integer while breaking ties by rounding to even
(func $__wasm_nearest_f64 (; 13 ;) (type $2) (param $var$0 f64) (result f64)
(local $var$1 f64)
(local $var$2 f64)
(if
(i32.eqz
(f64.lt
(local.tee $var$2
(f64.sub
(local.get $var$0)
(local.tee $var$1
(f64.floor
(local.get $var$0)
)
)
)
)
(f64.const 0.5)
)
)
(block
(local.set $var$0
(f64.ceil
(local.get $var$0)
)
)
(if
(f64.gt
(local.get $var$2)
(f64.const 0.5)
)
(return
(local.get $var$0)
)
)
(local.set $var$1
(select
(local.get $var$1)
(local.get $var$0)
(f64.eq
(f64.sub
(local.tee $var$2
(f64.mul
(local.get $var$1)
(f64.const 0.5)
)
)
(f64.floor
(local.get $var$2)
)
)
(f64.const 0)
)
)
)
)
)
(local.get $var$1)
)
(func $_ZN17compiler_builtins3int4udiv10divmod_u6417h6026910b5ed08e40E (; 14 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i32)
(local $var$3 i32)
(local $var$4 i32)
(local $var$5 i64)
(local $var$6 i64)
(local $var$7 i64)
(local $var$8 i64)
(block $label$1
(block $label$2
(block $label$3
(block $label$4
(block $label$5
(block $label$6
(block $label$7
(block $label$8
(block $label$9
(block $label$10
(block $label$11
(if
(local.tee $var$2
(i32.wrap_i64
(i64.shr_u
(local.get $var$0)
(i64.const 32)
)
)
)
(block
(br_if $label$11
(i32.eqz
(local.tee $var$3
(i32.wrap_i64
(local.get $var$1)
)
)
)
)
(br_if $label$9
(i32.eqz
(local.tee $var$4
(i32.wrap_i64
(i64.shr_u
(local.get $var$1)
(i64.const 32)
)
)
)
)
)
(br_if $label$8
(i32.le_u
(local.tee $var$2
(i32.sub
(i32.clz
(local.get $var$4)
)
(i32.clz
(local.get $var$2)
)
)
)
(i32.const 31)
)
)
(br $label$2)
)
)
(br_if $label$2
(i64.ge_u
(local.get $var$1)
(i64.const 4294967296)
)
)
(global.set $__wasm-intrinsics-temp-i64
(i64.extend_i32_u
(i32.sub
(local.tee $var$2
(i32.wrap_i64
(local.get $var$0)
)
)
(i32.mul
(local.tee $var$2
(i32.div_u
(local.get $var$2)
(local.tee $var$3
(i32.wrap_i64
(local.get $var$1)
)
)
)
)
(local.get $var$3)
)
)
)
)
(return
(i64.extend_i32_u
(local.get $var$2)
)
)
)
(local.set $var$3
(i32.wrap_i64
(i64.shr_u
(local.get $var$1)
(i64.const 32)
)
)
)
(br_if $label$7
(i32.eqz
(i32.wrap_i64
(local.get $var$0)
)
)
)
(br_if $label$6
(i32.eqz
(local.get $var$3)
)
)
(br_if $label$6
(i32.and
(local.tee $var$4
(i32.add
(local.get $var$3)
(i32.const -1)
)
)
(local.get $var$3)
)
)
(global.set $__wasm-intrinsics-temp-i64
(i64.or
(i64.shl
(i64.extend_i32_u
(i32.and
(local.get $var$4)
(local.get $var$2)
)
)
(i64.const 32)
)
(i64.and
(local.get $var$0)
(i64.const 4294967295)
)
)
)
(return
(i64.extend_i32_u
(i32.shr_u
(local.get $var$2)
(i32.and
(i32.ctz
(local.get $var$3)
)
(i32.const 31)
)
)
)
)
)
(unreachable)
)
(br_if $label$5
(i32.eqz
(i32.and
(local.tee $var$4
(i32.add
(local.get $var$3)
(i32.const -1)
)
)
(local.get $var$3)
)
)
)
(local.set $var$3
(i32.sub
(i32.const 0)
(local.tee $var$2
(i32.sub
(i32.add
(i32.clz
(local.get $var$3)
)
(i32.const 33)
)
(i32.clz
(local.get $var$2)
)
)
)
)
)
(br $label$3)
)
(local.set $var$3
(i32.sub
(i32.const 63)
(local.get $var$2)
)
)
(local.set $var$2
(i32.add
(local.get $var$2)
(i32.const 1)
)
)
(br $label$3)
)
(global.set $__wasm-intrinsics-temp-i64
(i64.shl
(i64.extend_i32_u
(i32.sub
(local.get $var$2)
(i32.mul
(local.tee $var$4
(i32.div_u
(local.get $var$2)
(local.get $var$3)
)
)
(local.get $var$3)
)
)
)
(i64.const 32)
)
)
(return
(i64.extend_i32_u
(local.get $var$4)
)
)
)
(br_if $label$4
(i32.lt_u
(local.tee $var$2
(i32.sub
(i32.clz
(local.get $var$3)
)
(i32.clz
(local.get $var$2)
)
)
)
(i32.const 31)
)
)
(br $label$2)
)
(global.set $__wasm-intrinsics-temp-i64
(i64.extend_i32_u
(i32.and
(local.get $var$4)
(i32.wrap_i64
(local.get $var$0)
)
)
)
)
(br_if $label$1
(i32.eq
(local.get $var$3)
(i32.const 1)
)
)
(return
(i64.shr_u
(local.get $var$0)
(i64.extend_i32_u
(i32.ctz
(local.get $var$3)
)
)
)
)
)
(local.set $var$3
(i32.sub
(i32.const 63)
(local.get $var$2)
)
)
(local.set $var$2
(i32.add
(local.get $var$2)
(i32.const 1)
)
)
)
(local.set $var$5
(i64.shr_u
(local.get $var$0)
(i64.extend_i32_u
(i32.and
(local.get $var$2)
(i32.const 63)
)
)
)
)
(local.set $var$0
(i64.shl
(local.get $var$0)
(i64.extend_i32_u
(i32.and
(local.get $var$3)
(i32.const 63)
)
)
)
)
(block $label$13
(if
(local.get $var$2)
(block
(local.set $var$8
(i64.add
(local.get $var$1)
(i64.const -1)
)
)
(loop $label$15
(local.set $var$5
(i64.sub
(local.tee $var$5
(i64.or
(i64.shl
(local.get $var$5)
(i64.const 1)
)
(i64.shr_u
(local.get $var$0)
(i64.const 63)
)
)
)
(i64.and
(local.tee $var$6
(i64.shr_s
(i64.sub
(local.get $var$8)
(local.get $var$5)
)
(i64.const 63)
)
)
(local.get $var$1)
)
)
)
(local.set $var$0
(i64.or
(i64.shl
(local.get $var$0)
(i64.const 1)
)
(local.get $var$7)
)
)
(local.set $var$7
(local.tee $var$6
(i64.and
(local.get $var$6)
(i64.const 1)
)
)
)
(br_if $label$15
(local.tee $var$2
(i32.add
(local.get $var$2)
(i32.const -1)
)
)
)
)
(br $label$13)
)
)
)
(global.set $__wasm-intrinsics-temp-i64
(local.get $var$5)
)
(return
(i64.or
(i64.shl
(local.get $var$0)
(i64.const 1)
)
(local.get $var$6)
)
)
)
(global.set $__wasm-intrinsics-temp-i64
(local.get $var$0)
)
(local.set $var$0
(i64.const 0)
)
)
(local.get $var$0)
)
(func $_ZN17compiler_builtins3int3mul3Mul3mul17h070e9a1c69faec5bE (; 15 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i32)
(local $var$3 i32)
(local $var$4 i32)
(local $var$5 i32)
(local $var$6 i32)
(i64.or
(i64.shl
(i64.extend_i32_u
(i32.add
(i32.add
(i32.add
(i32.add
(i32.mul
(local.tee $var$4
(i32.shr_u
(local.tee $var$2
(i32.wrap_i64
(local.get $var$1)
)
)
(i32.const 16)
)
)
(local.tee $var$5
(i32.shr_u
(local.tee $var$3
(i32.wrap_i64
(local.get $var$0)
)
)
(i32.const 16)
)
)
)
(i32.mul
(local.get $var$2)
(i32.wrap_i64
(i64.shr_u
(local.get $var$0)
(i64.const 32)
)
)
)
)
(i32.mul
(i32.wrap_i64
(i64.shr_u
(local.get $var$1)
(i64.const 32)
)
)
(local.get $var$3)
)
)
(i32.shr_u
(local.tee $var$2
(i32.add
(i32.shr_u
(local.tee $var$6
(i32.mul
(local.tee $var$2
(i32.and
(local.get $var$2)
(i32.const 65535)
)
)
(local.tee $var$3
(i32.and
(local.get $var$3)
(i32.const 65535)
)
)
)
)
(i32.const 16)
)
(i32.mul
(local.get $var$2)
(local.get $var$5)
)
)
)
(i32.const 16)
)
)
(i32.shr_u
(local.tee $var$2
(i32.add
(i32.and
(local.get $var$2)
(i32.const 65535)
)
(i32.mul
(local.get $var$4)
(local.get $var$3)
)
)
)
(i32.const 16)
)
)
)
(i64.const 32)
)
(i64.extend_i32_u
(i32.or
(i32.shl
(local.get $var$2)
(i32.const 16)
)
(i32.and
(local.get $var$6)
(i32.const 65535)
)
)
)
)
)
(func $_ZN17compiler_builtins3int4sdiv3Div3div17he78fc483e41d7ec7E (; 16 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i64)
(i64.sub
(i64.xor
(i64.div_u
(i64.sub
(i64.xor
(local.tee $var$2
(i64.shr_s
(local.get $var$0)
(i64.const 63)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i64.sub
(i64.xor
(local.tee $var$2
(i64.shr_s
(local.get $var$1)
(i64.const 63)
)
)
(local.get $var$1)
)
(local.get $var$2)
)
)
(local.tee $var$0
(i64.shr_s
(i64.xor
(local.get $var$1)
(local.get $var$0)
)
(i64.const 63)
)
)
)
(local.get $var$0)
)
)
(func $_ZN17compiler_builtins3int4sdiv3Mod4mod_17h2cbb7bbf36e41d68E (; 17 ;) (type $0) (param $var$0 i64) (param $var$1 i64) (result i64)
(local $var$2 i64)
(i64.sub
(i64.xor
(i64.rem_u
(i64.sub
(i64.xor
(local.tee $var$2
(i64.shr_s
(local.get $var$0)
(i64.const 63)
)
)
(local.get $var$0)
)
(local.get $var$2)
)
(i64.sub
(i64.xor
(local.tee $var$0
(i64.shr_s
(local.get $var$1)
(i64.const 63)
)
)
(local.get $var$1)
)
(local.get $var$0)
)
)
(local.get $var$2)
)
(local.get $var$2)
)
)
;; custom section "linking", size 3
)
| {
"language": "Assembly"
} |
; RUN: opt < %s -simplifycfg -disable-output
define i1 @foo() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
%X = invoke i1 @foo( )
to label %N unwind label %F ; <i1> [#uses=1]
F: ; preds = %0
%val = landingpad { i8*, i32 }
catch i8* null
ret i1 false
N: ; preds = %0
br i1 %X, label %A, label %B
A: ; preds = %N
ret i1 true
B: ; preds = %N
ret i1 true
}
declare i32 @__gxx_personality_v0(...)
| {
"language": "Assembly"
} |
; RUN: opt -loop-vectorize -S -mattr=avx512f < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; This test checks that "gather" operation is choosen since it's cost is better
; than interleaving pattern.
;
;unsigned long A[SIZE];
;unsigned long B[SIZE];
;
;void foo() {
; for (int i=0; i<N; i+=8) {
; B[i] = A[i] + 5;
; }
;}
@A = global [10240 x i64] zeroinitializer, align 16
@B = global [10240 x i64] zeroinitializer, align 16
; CHECK_LABEL: strided_load_i64
; CHECK: masked.gather
define void @strided_load_i64() {
br label %1
; <label>:1: ; preds = %0, %1
%indvars.iv = phi i64 [ 0, %0 ], [ %indvars.iv.next, %1 ]
%2 = getelementptr inbounds [10240 x i64], [10240 x i64]* @A, i64 0, i64 %indvars.iv
%3 = load i64, i64* %2, align 16
%4 = add i64 %3, 5
%5 = getelementptr inbounds [10240 x i64], [10240 x i64]* @B, i64 0, i64 %indvars.iv
store i64 %4, i64* %5, align 16
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 8
%6 = icmp slt i64 %indvars.iv.next, 1024
br i1 %6, label %1, label %7
; <label>:7: ; preds = %1
ret void
}
| {
"language": "Assembly"
} |
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#ifdef CONFIG_MX6DL_LPDDR2
/* IOMUX SETTINGS */
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
DATA 4 0x020E04bc 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
DATA 4 0x020E04c0 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
DATA 4 0x020E04c4 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
DATA 4 0x020E04c8 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
DATA 4 0x020E04cc 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
DATA 4 0x020E04d0 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
DATA 4 0x020E04d4 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
DATA 4 0x020E04d8 0x00003028
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
DATA 4 0x020E0470 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
DATA 4 0x020E0474 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
DATA 4 0x020E0478 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
DATA 4 0x020E047c 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
DATA 4 0x020E0480 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
DATA 4 0x020E0484 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
DATA 4 0x020E0488 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
DATA 4 0x020E048c 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
DATA 4 0x020E0464 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
DATA 4 0x020E0490 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
DATA 4 0x020E04ac 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
DATA 4 0x020E04b0 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
DATA 4 0x020E0494 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
DATA 4 0x020E04a4 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
DATA 4 0x020E04a8 0x00000038
/*
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
* DSE can be configured using Group Control Register:
* IOMUXC_SW_PAD_CTL_GRP_CTLDS
*/
DATA 4 0x020E04a0 0x00000000
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
DATA 4 0x020E04b4 0x00000038
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
DATA 4 0x020E04b8 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
DATA 4 0x020E0764 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
DATA 4 0x020E0770 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
DATA 4 0x020E0778 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
DATA 4 0x020E077c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
DATA 4 0x020E0780 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
DATA 4 0x020E0784 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
DATA 4 0x020E078c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
DATA 4 0x020E0748 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
DATA 4 0x020E074c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
DATA 4 0x020E076c 0x00000038
/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
DATA 4 0x020E0750 0x00020000
/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
DATA 4 0x020E0754 0x00000000
/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
DATA 4 0x020E0760 0x00020000
/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
DATA 4 0x020E0774 0x00080000
/*
* DDR Controller Registers
*
* Manufacturer: Mocron
* Device Part Number: MT42L64M64D2KH-18
* Clock Freq.: 528MHz
* MMDC channels: Both MMDC0, MMDC1
*Density per CS in Gb: 256M
* Chip Selects used: 2
* Number of Banks: 8
* Row address: 14
* Column address: 9
* Data bus width 32
*/
/* MMDC_P0_BASE_ADDR = 0x021b0000 */
/* MMDC_P1_BASE_ADDR = 0x021b4000 */
/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b001c 0x00008000
/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b401c 0x00008000
/*LPDDR2 ZQ params */
DATA 4 0x021b085c 0x1b5f01ff
DATA 4 0x021b485c 0x1b5f01ff
/* Calibration setup. */
/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
DATA 4 0x021b0800 0xa1390003
/*ca bus abs delay */
DATA 4 0x021b0890 0x00400000
/*ca bus abs delay */
DATA 4 0x021b4890 0x00400000
/* values of 20,40,50,60,7f tried. no difference seen */
/* DDR_PHY_P1_MPWRCADL */
DATA 4 0x021b48bc 0x00055555
/*frc_msr.*/
DATA 4 0x021b08b8 0x00000800
/*frc_msr.*/
DATA 4 0x021b48b8 0x00000800
/* DDR_PHY_P0_MPREDQBY0DL3 */
DATA 4 0x021b081c 0x33333333
/* DDR_PHY_P0_MPREDQBY1DL3 */
DATA 4 0x021b0820 0x33333333
/* DDR_PHY_P0_MPREDQBY2DL3 */
DATA 4 0x021b0824 0x33333333
/* DDR_PHY_P0_MPREDQBY3DL3 */
DATA 4 0x021b0828 0x33333333
/* DDR_PHY_P1_MPREDQBY0DL3 */
DATA 4 0x021b481c 0x33333333
/* DDR_PHY_P1_MPREDQBY1DL3 */
DATA 4 0x021b4820 0x33333333
/* DDR_PHY_P1_MPREDQBY2DL3 */
DATA 4 0x021b4824 0x33333333
/* DDR_PHY_P1_MPREDQBY3DL3 */
DATA 4 0x021b4828 0x33333333
/*
* Read and write data delay, per byte.
* For optimized DDR operation it is recommended to run mmdc_calibration
* on your board, and replace 4 delay register assigns with resulted values
* Note:
* a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
* should be skipped, or the write/read calibration comming after that
* will stall
* b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
*/
DATA 4 0x021b0848 0x4b4b524f
DATA 4 0x021b4848 0x494f4c44
DATA 4 0x021b0850 0x3c3d303c
DATA 4 0x021b4850 0x3c343d38
/*dqs gating dis */
DATA 4 0x021b083c 0x20000000
DATA 4 0x021b0840 0x0
DATA 4 0x021b483c 0x20000000
DATA 4 0x021b4840 0x0
/*clk delay */
DATA 4 0x021b0858 0xa00
/*clk delay */
DATA 4 0x021b4858 0xa00
/*frc_msr */
DATA 4 0x021b08b8 0x00000800
/*frc_msr */
DATA 4 0x021b48b8 0x00000800
/* Calibration setup end */
/* Channel0 - startng address 0x80000000 */
/* MMDC0_MDCFG0 */
DATA 4 0x021b000c 0x34386145
/* MMDC0_MDPDC */
DATA 4 0x021b0004 0x00020036
/* MMDC0_MDCFG1 */
DATA 4 0x021b0010 0x00100c83
/* MMDC0_MDCFG2 */
DATA 4 0x021b0014 0x000000Dc
/* MMDC0_MDMISC */
DATA 4 0x021b0018 0x0000174C
/* MMDC0_MDRWD;*/
DATA 4 0x021b002c 0x0f9f26d2
/* MMDC0_MDOR */
DATA 4 0x021b0030 0x009f0e10
/* MMDC0_MDCFG3LP */
DATA 4 0x021b0038 0x00190778
/* MMDC0_MDOTC */
DATA 4 0x021b0008 0x00000000
/* CS0_END */
DATA 4 0x021b0040 0x0000005f
/* ROC */
DATA 4 0x021b0404 0x0000000f
/* MMDC0_MDCTL */
DATA 4 0x021b0000 0xc3010000
/* Channel1 - starting address 0x10000000 */
/* MMDC1_MDCFG0 */
DATA 4 0x021b400c 0x34386145
/* MMDC1_MDPDC */
DATA 4 0x021b4004 0x00020036
/* MMDC1_MDCFG1 */
DATA 4 0x021b4010 0x00100c83
/* MMDC1_MDCFG2 */
DATA 4 0x021b4014 0x000000Dc
/* MMDC1_MDMISC */
DATA 4 0x021b4018 0x0000174C
/* MMDC1_MDRWD;*/
DATA 4 0x021b402c 0x0f9f26d2
/* MMDC1_MDOR */
DATA 4 0x021b4030 0x009f0e10
/* MMDC1_MDCFG3LP */
DATA 4 0x021b4038 0x00190778
/* MMDC1_MDOTC */
DATA 4 0x021b4008 0x00000000
/* CS0_END */
DATA 4 0x021b4040 0x0000003f
/* MMDC1_MDCTL */
DATA 4 0x021b4000 0xc3010000
/* Channel0 : Configure DDR device:*/
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
DATA 4 0x021b001c 0x003f8030
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
DATA 4 0x021b001c 0xff0a8030
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
DATA 4 0x021b001c 0xa2018030
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
DATA 4 0x021b001c 0x06028030
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
DATA 4 0x021b001c 0x01038030
/* Channel1 : Configure DDR device:*/
/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
DATA 4 0x021b401c 0x003f8030
/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
DATA 4 0x021b401c 0xff0a8030
/* MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=a2 */
DATA 4 0x021b401c 0xa2018030
/* MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=6. tcl=8, tcwl=4 */
DATA 4 0x021b401c 0x06028030
/* MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=2.drive=240/6 */
DATA 4 0x021b401c 0x01038030
/* MMDC0_MDREF */
DATA 4 0x021b0020 0x00005800
/* MMDC1_MDREF */
DATA 4 0x021b4020 0x00005800
/* DDR_PHY_P0_MPODTCTRL */
DATA 4 0x021b0818 0x0
/* DDR_PHY_P1_MPODTCTRL */
DATA 4 0x021b4818 0x0
/*
* calibration values based on calibration compare of 0x00ffff00:
* Note, these calibration values are based on Freescale's board
* May need to run calibration on target board to fine tune these
*/
/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
DATA 4 0x021b0800 0xa1310003
/* DDR_PHY_P0_MPMUR0, frc_msr */
DATA 4 0x021b08b8 0x00000800
/* DDR_PHY_P1_MPMUR0, frc_msr */
DATA 4 0x021b48b8 0x00000800
/*
* MMDC0_MDSCR, clear this register
* (especially the configuration bit as initialization is complete)
*/
DATA 4 0x021b001c 0x00000000
/*
* MMDC0_MDSCR, clear this register
* (especially the configuration bit as initialization is complete)
*/
DATA 4 0x021b401c 0x00000000
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
DATA 4 0x020e0010 0xF00000CF
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#else /* CONFIG_MX6DL_LPDDR2 */
DATA 4 0x020e0798 0x000c0000
DATA 4 0x020e0758 0x00000000
DATA 4 0x020e0588 0x00000030
DATA 4 0x020e0594 0x00000030
DATA 4 0x020e056c 0x00000030
DATA 4 0x020e0578 0x00000030
DATA 4 0x020e074c 0x00000030
DATA 4 0x020e057c 0x00000030
DATA 4 0x020e0590 0x00003000
DATA 4 0x020e0598 0x00003000
DATA 4 0x020e058c 0x00000000
DATA 4 0x020e059c 0x00003030
DATA 4 0x020e05a0 0x00003030
DATA 4 0x020e078c 0x00000030
DATA 4 0x020e0750 0x00020000
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
DATA 4 0x020e051c 0x00000030
DATA 4 0x020e0518 0x00000030
DATA 4 0x020e050c 0x00000030
DATA 4 0x020e05b8 0x00000030
DATA 4 0x020e05c0 0x00000030
DATA 4 0x020e0774 0x00020000
DATA 4 0x020e0784 0x00000030
DATA 4 0x020e0788 0x00000030
DATA 4 0x020e0794 0x00000030
DATA 4 0x020e079c 0x00000030
DATA 4 0x020e07a0 0x00000030
DATA 4 0x020e07a4 0x00000030
DATA 4 0x020e07a8 0x00000030
DATA 4 0x020e0748 0x00000030
DATA 4 0x020e05ac 0x00000030
DATA 4 0x020e05b4 0x00000030
DATA 4 0x020e0528 0x00000030
DATA 4 0x020e0520 0x00000030
DATA 4 0x020e0514 0x00000030
DATA 4 0x020e0510 0x00000030
DATA 4 0x020e05bc 0x00000030
DATA 4 0x020e05c4 0x00000030
DATA 4 0x021b0800 0xa1390003
DATA 4 0x021b4800 0xa1390003
DATA 4 0x021b080c 0x001F001F
DATA 4 0x021b0810 0x001F001F
DATA 4 0x021b480c 0x00370037
DATA 4 0x021b4810 0x00370037
DATA 4 0x021b083c 0x422f0220
DATA 4 0x021b0840 0x021f0219
DATA 4 0x021b483C 0x422f0220
DATA 4 0x021b4840 0x022d022f
DATA 4 0x021b0848 0x47494b49
DATA 4 0x021b4848 0x48484c47
DATA 4 0x021b0850 0x39382b2f
DATA 4 0x021b4850 0x2f35312c
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
DATA 4 0x021b481c 0x33333333
DATA 4 0x021b4820 0x33333333
DATA 4 0x021b4824 0x33333333
DATA 4 0x021b4828 0x33333333
DATA 4 0x021b08b8 0x00000800
DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b0004 0x0002002d
DATA 4 0x021b0008 0x00333030
DATA 4 0x021b000c 0x40445323
DATA 4 0x021b0010 0xb66e8c63
DATA 4 0x021b0014 0x01ff00db
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x00440e21
#ifdef CONFIG_DDR_32BIT
DATA 4 0x021b0040 0x00000017
DATA 4 0x021b0000 0xc3190000
#else
DATA 4 0x021b0040 0x00000027
DATA 4 0x021b0000 0xc31a0000
#endif
DATA 4 0x021b001c 0x04008032
DATA 4 0x021b001c 0x0400803a
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x0000803b
DATA 4 0x021b001c 0x00428031
DATA 4 0x021b001c 0x00428039
DATA 4 0x021b001c 0x07208030
DATA 4 0x021b001c 0x07208038
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00000007
DATA 4 0x021b4818 0x00000007
DATA 4 0x021b0004 0x0002556d
DATA 4 0x021b4004 0x00011006
DATA 4 0x021b001c 0x00000000
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
DATA 4 0x020e0010 0xF00000CF
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
#endif /* CONFIG_MX6DL_LPDDR2 */
| {
"language": "Assembly"
} |
fact: load -5
ptop
ret
main: loadr r0, 1
loadr r1, 5
call fact, 1
halt 0
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basicaa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512BW
define <8 x i32> @add_sub_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: @add_sub_v8i32(
; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = sub <8 x i32> [[A]], [[B]]
; CHECK-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%b0 = extractelement <8 x i32> %b, i32 0
%b1 = extractelement <8 x i32> %b, i32 1
%b2 = extractelement <8 x i32> %b, i32 2
%b3 = extractelement <8 x i32> %b, i32 3
%b4 = extractelement <8 x i32> %b, i32 4
%b5 = extractelement <8 x i32> %b, i32 5
%b6 = extractelement <8 x i32> %b, i32 6
%b7 = extractelement <8 x i32> %b, i32 7
%ab0 = add i32 %a0, %b0
%ab1 = add i32 %a1, %b1
%ab2 = add i32 %a2, %b2
%ab3 = add i32 %a3, %b3
%ab4 = sub i32 %a4, %b4
%ab5 = sub i32 %a5, %b5
%ab6 = sub i32 %a6, %b6
%ab7 = sub i32 %a7, %b7
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <4 x i32> @add_and_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @add_and_v4i32(
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[A]], [[B]]
; CHECK-NEXT: [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x i32> [[R3]]
;
%a0 = extractelement <4 x i32> %a, i32 0
%a1 = extractelement <4 x i32> %a, i32 1
%a2 = extractelement <4 x i32> %a, i32 2
%a3 = extractelement <4 x i32> %a, i32 3
%b0 = extractelement <4 x i32> %b, i32 0
%b1 = extractelement <4 x i32> %b, i32 1
%b2 = extractelement <4 x i32> %b, i32 2
%b3 = extractelement <4 x i32> %b, i32 3
%ab0 = add i32 %a0, %b0
%ab1 = add i32 %a1, %b1
%ab2 = and i32 %a2, %b2
%ab3 = and i32 %a3, %b3
%r0 = insertelement <4 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <4 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <4 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <4 x i32> %r2, i32 %ab3, i32 3
ret <4 x i32> %r3
}
define <4 x i32> @add_mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
; SSE-LABEL: @add_mul_v4i32(
; SSE-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
; SSE-NEXT: [[TMP2:%.*]] = add <4 x i32> [[A]], [[B]]
; SSE-NEXT: [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
; SSE-NEXT: ret <4 x i32> [[R3]]
;
; SLM-LABEL: @add_mul_v4i32(
; SLM-NEXT: [[A0:%.*]] = extractelement <4 x i32> [[A:%.*]], i32 0
; SLM-NEXT: [[A1:%.*]] = extractelement <4 x i32> [[A]], i32 1
; SLM-NEXT: [[A2:%.*]] = extractelement <4 x i32> [[A]], i32 2
; SLM-NEXT: [[A3:%.*]] = extractelement <4 x i32> [[A]], i32 3
; SLM-NEXT: [[B0:%.*]] = extractelement <4 x i32> [[B:%.*]], i32 0
; SLM-NEXT: [[B1:%.*]] = extractelement <4 x i32> [[B]], i32 1
; SLM-NEXT: [[B2:%.*]] = extractelement <4 x i32> [[B]], i32 2
; SLM-NEXT: [[B3:%.*]] = extractelement <4 x i32> [[B]], i32 3
; SLM-NEXT: [[AB0:%.*]] = mul i32 [[A0]], [[B0]]
; SLM-NEXT: [[AB1:%.*]] = add i32 [[A1]], [[B1]]
; SLM-NEXT: [[AB2:%.*]] = add i32 [[A2]], [[B2]]
; SLM-NEXT: [[AB3:%.*]] = mul i32 [[A3]], [[B3]]
; SLM-NEXT: [[R0:%.*]] = insertelement <4 x i32> undef, i32 [[AB0]], i32 0
; SLM-NEXT: [[R1:%.*]] = insertelement <4 x i32> [[R0]], i32 [[AB1]], i32 1
; SLM-NEXT: [[R2:%.*]] = insertelement <4 x i32> [[R1]], i32 [[AB2]], i32 2
; SLM-NEXT: [[R3:%.*]] = insertelement <4 x i32> [[R2]], i32 [[AB3]], i32 3
; SLM-NEXT: ret <4 x i32> [[R3]]
;
; AVX-LABEL: @add_mul_v4i32(
; AVX-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
; AVX-NEXT: [[TMP2:%.*]] = add <4 x i32> [[A]], [[B]]
; AVX-NEXT: [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
; AVX-NEXT: ret <4 x i32> [[R3]]
;
; AVX512-LABEL: @add_mul_v4i32(
; AVX512-NEXT: [[TMP1:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
; AVX512-NEXT: [[TMP2:%.*]] = add <4 x i32> [[A]], [[B]]
; AVX512-NEXT: [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
; AVX512-NEXT: ret <4 x i32> [[R3]]
;
%a0 = extractelement <4 x i32> %a, i32 0
%a1 = extractelement <4 x i32> %a, i32 1
%a2 = extractelement <4 x i32> %a, i32 2
%a3 = extractelement <4 x i32> %a, i32 3
%b0 = extractelement <4 x i32> %b, i32 0
%b1 = extractelement <4 x i32> %b, i32 1
%b2 = extractelement <4 x i32> %b, i32 2
%b3 = extractelement <4 x i32> %b, i32 3
%ab0 = mul i32 %a0, %b0
%ab1 = add i32 %a1, %b1
%ab2 = add i32 %a2, %b2
%ab3 = mul i32 %a3, %b3
%r0 = insertelement <4 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <4 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <4 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <4 x i32> %r2, i32 %ab3, i32 3
ret <4 x i32> %r3
}
define <8 x i32> @ashr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: @ashr_shl_v8i32(
; SSE-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
; SSE-NEXT: [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
; SSE-NEXT: [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
; SSE-NEXT: [[B2:%.*]] = extractelement <8 x i32> [[B]], i32 2
; SSE-NEXT: [[B3:%.*]] = extractelement <8 x i32> [[B]], i32 3
; SSE-NEXT: [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
; SSE-NEXT: [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
; SSE-NEXT: [[AB2:%.*]] = ashr i32 [[A2]], [[B2]]
; SSE-NEXT: [[AB3:%.*]] = ashr i32 [[A3]], [[B3]]
; SSE-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[A]], [[B]]
; SSE-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
; SSE-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[R3]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; SSE-NEXT: ret <8 x i32> [[R7]]
;
; SLM-LABEL: @ashr_shl_v8i32(
; SLM-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
; SLM-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
; SLM-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; SLM-NEXT: ret <8 x i32> [[R7]]
;
; AVX-LABEL: @ashr_shl_v8i32(
; AVX-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
; AVX-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
; AVX-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; AVX-NEXT: ret <8 x i32> [[R7]]
;
; AVX512-LABEL: @ashr_shl_v8i32(
; AVX512-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
; AVX512-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
; AVX512-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; AVX512-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%b0 = extractelement <8 x i32> %b, i32 0
%b1 = extractelement <8 x i32> %b, i32 1
%b2 = extractelement <8 x i32> %b, i32 2
%b3 = extractelement <8 x i32> %b, i32 3
%b4 = extractelement <8 x i32> %b, i32 4
%b5 = extractelement <8 x i32> %b, i32 5
%b6 = extractelement <8 x i32> %b, i32 6
%b7 = extractelement <8 x i32> %b, i32 7
%ab0 = ashr i32 %a0, %b0
%ab1 = ashr i32 %a1, %b1
%ab2 = ashr i32 %a2, %b2
%ab3 = ashr i32 %a3, %b3
%ab4 = shl i32 %a4, %b4
%ab5 = shl i32 %a5, %b5
%ab6 = shl i32 %a6, %b6
%ab7 = shl i32 %a7, %b7
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <8 x i32> @ashr_shl_v8i32_const(<8 x i32> %a) {
; SSE-LABEL: @ashr_shl_v8i32_const(
; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; SSE-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], <i32 2, i32 2, i32 2, i32 2>
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; SSE-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 3, i32 3, i32 3, i32 3>
; SSE-NEXT: [[R7:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; SSE-NEXT: ret <8 x i32> [[R7]]
;
; SLM-LABEL: @ashr_shl_v8i32_const(
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; SLM-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], <i32 2, i32 2, i32 2, i32 2>
; SLM-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; SLM-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 3, i32 3, i32 3, i32 3>
; SLM-NEXT: [[R7:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; SLM-NEXT: ret <8 x i32> [[R7]]
;
; AVX1-LABEL: @ashr_shl_v8i32_const(
; AVX1-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX1-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], <i32 2, i32 2, i32 2, i32 2>
; AVX1-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
; AVX1-NEXT: [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 3, i32 3, i32 3, i32 3>
; AVX1-NEXT: [[R7:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; AVX1-NEXT: ret <8 x i32> [[R7]]
;
; AVX2-LABEL: @ashr_shl_v8i32_const(
; AVX2-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
; AVX2-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
; AVX2-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; AVX2-NEXT: ret <8 x i32> [[R7]]
;
; AVX512-LABEL: @ashr_shl_v8i32_const(
; AVX512-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
; AVX512-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
; AVX512-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; AVX512-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%ab0 = ashr i32 %a0, 2
%ab1 = ashr i32 %a1, 2
%ab2 = ashr i32 %a2, 2
%ab3 = ashr i32 %a3, 2
%ab4 = shl i32 %a4, 3
%ab5 = shl i32 %a5, 3
%ab6 = shl i32 %a6, 3
%ab7 = shl i32 %a7, 3
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <8 x i32> @ashr_lshr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: @ashr_lshr_shl_v8i32(
; SSE-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
; SSE-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
; SSE-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
; SSE-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
; SSE-NEXT: [[A4:%.*]] = extractelement <8 x i32> [[A]], i32 4
; SSE-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; SSE-NEXT: [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
; SSE-NEXT: [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
; SSE-NEXT: [[B2:%.*]] = extractelement <8 x i32> [[B]], i32 2
; SSE-NEXT: [[B3:%.*]] = extractelement <8 x i32> [[B]], i32 3
; SSE-NEXT: [[B4:%.*]] = extractelement <8 x i32> [[B]], i32 4
; SSE-NEXT: [[B5:%.*]] = extractelement <8 x i32> [[B]], i32 5
; SSE-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B]], i32 6
; SSE-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
; SSE-NEXT: [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
; SSE-NEXT: [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
; SSE-NEXT: [[AB2:%.*]] = lshr i32 [[A2]], [[B2]]
; SSE-NEXT: [[AB3:%.*]] = lshr i32 [[A3]], [[B3]]
; SSE-NEXT: [[AB4:%.*]] = lshr i32 [[A4]], [[B4]]
; SSE-NEXT: [[AB5:%.*]] = lshr i32 [[A5]], [[B5]]
; SSE-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
; SSE-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
; SSE-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
; SSE-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
; SSE-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; SSE-NEXT: ret <8 x i32> [[R7]]
;
; SLM-LABEL: @ashr_lshr_shl_v8i32(
; SLM-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
; SLM-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
; SLM-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
; SLM-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; SLM-NEXT: [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
; SLM-NEXT: [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
; SLM-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B]], i32 6
; SLM-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
; SLM-NEXT: [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
; SLM-NEXT: [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
; SLM-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[A]], [[B]]
; SLM-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
; SLM-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
; SLM-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
; SLM-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
; SLM-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP2]], i32 2
; SLM-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
; SLM-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP3]], i32 3
; SLM-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
; SLM-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP4]], i32 4
; SLM-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
; SLM-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP5]], i32 5
; SLM-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; SLM-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; SLM-NEXT: ret <8 x i32> [[R7]]
;
; AVX1-LABEL: @ashr_lshr_shl_v8i32(
; AVX1-NEXT: [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
; AVX1-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
; AVX1-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
; AVX1-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; AVX1-NEXT: [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
; AVX1-NEXT: [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
; AVX1-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B]], i32 6
; AVX1-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
; AVX1-NEXT: [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
; AVX1-NEXT: [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
; AVX1-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[A]], [[B]]
; AVX1-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
; AVX1-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
; AVX1-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[AB0]], i32 0
; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
; AVX1-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
; AVX1-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP2]], i32 2
; AVX1-NEXT: [[TMP3:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
; AVX1-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP3]], i32 3
; AVX1-NEXT: [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
; AVX1-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP4]], i32 4
; AVX1-NEXT: [[TMP5:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
; AVX1-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP5]], i32 5
; AVX1-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; AVX1-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; AVX1-NEXT: ret <8 x i32> [[R7]]
;
; AVX2-LABEL: @ashr_lshr_shl_v8i32(
; AVX2-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
; AVX2-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; AVX2-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
; AVX2-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX2-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
; AVX2-NEXT: [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
; AVX2-NEXT: [[TMP5:%.*]] = lshr <8 x i32> [[A]], [[B]]
; AVX2-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
; AVX2-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
; AVX2-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
; AVX2-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[TMP6]], i32 0
; AVX2-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
; AVX2-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[TMP7]], i32 1
; AVX2-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
; AVX2-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP8]], i32 2
; AVX2-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
; AVX2-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP9]], i32 3
; AVX2-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i32 4
; AVX2-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP10]], i32 4
; AVX2-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP5]], i32 5
; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP11]], i32 5
; AVX2-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; AVX2-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; AVX2-NEXT: ret <8 x i32> [[R7]]
;
; AVX512-LABEL: @ashr_lshr_shl_v8i32(
; AVX512-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
; AVX512-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; AVX512-NEXT: [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
; AVX512-NEXT: [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX512-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP5:%.*]] = lshr <8 x i32> [[A]], [[B]]
; AVX512-NEXT: [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
; AVX512-NEXT: [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
; AVX512-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
; AVX512-NEXT: [[R0:%.*]] = insertelement <8 x i32> undef, i32 [[TMP6]], i32 0
; AVX512-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
; AVX512-NEXT: [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[TMP7]], i32 1
; AVX512-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
; AVX512-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP8]], i32 2
; AVX512-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
; AVX512-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP9]], i32 3
; AVX512-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i32 4
; AVX512-NEXT: [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP10]], i32 4
; AVX512-NEXT: [[TMP11:%.*]] = extractelement <8 x i32> [[TMP5]], i32 5
; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP11]], i32 5
; AVX512-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; AVX512-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; AVX512-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%b0 = extractelement <8 x i32> %b, i32 0
%b1 = extractelement <8 x i32> %b, i32 1
%b2 = extractelement <8 x i32> %b, i32 2
%b3 = extractelement <8 x i32> %b, i32 3
%b4 = extractelement <8 x i32> %b, i32 4
%b5 = extractelement <8 x i32> %b, i32 5
%b6 = extractelement <8 x i32> %b, i32 6
%b7 = extractelement <8 x i32> %b, i32 7
%ab0 = ashr i32 %a0, %b0
%ab1 = ashr i32 %a1, %b1
%ab2 = lshr i32 %a2, %b2
%ab3 = lshr i32 %a3, %b3
%ab4 = lshr i32 %a4, %b4
%ab5 = lshr i32 %a5, %b5
%ab6 = shl i32 %a6, %b6
%ab7 = shl i32 %a7, %b7
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <8 x i32> @add_v8i32_undefs(<8 x i32> %a) {
; CHECK-LABEL: @add_v8i32_undefs(
; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> [[A:%.*]], <i32 undef, i32 4, i32 8, i32 16, i32 undef, i32 4, i32 8, i32 16>
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%ab0 = add i32 %a0, undef
%ab1 = add i32 %a1, 4
%ab2 = add i32 %a2, 8
%ab3 = add i32 %a3, 16
%ab4 = add i32 %a4, undef
%ab5 = add i32 %a5, 4
%ab6 = add i32 %a6, 8
%ab7 = add i32 %a7, 16
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
; CHECK-LABEL: @sdiv_v8i32_undefs(
; CHECK-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 1
; CHECK-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
; CHECK-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
; CHECK-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
; CHECK-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
; CHECK-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
; CHECK-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; CHECK-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8
; CHECK-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16
; CHECK-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; CHECK-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; CHECK-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
; CHECK-NEXT: [[R1:%.*]] = insertelement <8 x i32> undef, i32 [[AB1]], i32 1
; CHECK-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
; CHECK-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i32 5
; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
; CHECK-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%ab0 = sdiv i32 %a0, undef
%ab1 = sdiv i32 %a1, 4
%ab2 = sdiv i32 %a2, 8
%ab3 = sdiv i32 %a3, 16
%ab4 = sdiv i32 %a4, undef
%ab5 = sdiv i32 %a5, 4
%ab6 = sdiv i32 %a6, 8
%ab7 = sdiv i32 %a7, 16
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
; CHECK-LABEL: @add_sub_v8i32_splat(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i32> undef, i32 [[B:%.*]], i32 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
; CHECK-NEXT: [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
; CHECK-NEXT: [[R7:%.*]] = shufflevector <8 x i32> [[TMP3]], <8 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <8 x i32> [[R7]]
;
%a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5
%a6 = extractelement <8 x i32> %a, i32 6
%a7 = extractelement <8 x i32> %a, i32 7
%ab0 = add i32 %a0, %b
%ab1 = add i32 %b, %a1
%ab2 = add i32 %a2, %b
%ab3 = add i32 %b, %a3
%ab4 = sub i32 %b, %a4
%ab5 = sub i32 %b, %a5
%ab6 = sub i32 %b, %a6
%ab7 = sub i32 %b, %a7
%r0 = insertelement <8 x i32> undef, i32 %ab0, i32 0
%r1 = insertelement <8 x i32> %r0, i32 %ab1, i32 1
%r2 = insertelement <8 x i32> %r1, i32 %ab2, i32 2
%r3 = insertelement <8 x i32> %r2, i32 %ab3, i32 3
%r4 = insertelement <8 x i32> %r3, i32 %ab4, i32 4
%r5 = insertelement <8 x i32> %r4, i32 %ab5, i32 5
%r6 = insertelement <8 x i32> %r5, i32 %ab6, i32 6
%r7 = insertelement <8 x i32> %r6, i32 %ab7, i32 7
ret <8 x i32> %r7
}
| {
"language": "Assembly"
} |
// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -S -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: @test_builtin_clz(
// CHECK: tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
void test_builtin_clz(global int* out, int a)
{
*out = __builtin_clz(a);
}
// CHECK-LABEL: @test_builtin_clzl(
// CHECK: tail call i64 @llvm.ctlz.i64(i64 %a, i1 true)
void test_builtin_clzl(global long* out, long a)
{
*out = __builtin_clzl(a);
}
// CHECK: tail call i8 addrspace(5)* @llvm.frameaddress.p5i8(i32 0)
void test_builtin_frame_address(int *out) {
*out = __builtin_frame_address(0);
}
| {
"language": "Assembly"
} |
GPR0 0000000000000000
GPR1 0000000000000040
GPR2 0000000000000000
GPR3 0000000000000000
GPR4 FFE0007FFFFFFFBE
GPR5 0000000000000000
GPR6 FFFFFFFFFFFFFFF8
GPR7 FFFFFFFFFFFFFFFF
GPR8 0000000000000000
GPR9 0000000000000020
GPR10 0000000000000000
GPR11 0000000000000008
GPR12 0000000000000000
GPR13 0000000000000000
GPR14 0000000000000000
GPR15 7FFFFFFFFFFFFFFF
GPR16 007FFFFFFF038026
GPR17 0000000000000000
GPR18 0000000000000000
GPR19 0000000000000000
GPR20 0000000000000000
GPR21 0000000000000000
GPR22 0000000000000000
GPR23 0000000000000000
GPR24 FFFFFFFFFFFFFFFF
GPR25 0000000000000000
GPR26 0000000000000000
GPR27 00000000C0080000
GPR28 00000000000163FE
GPR29 0000000000000000
GPR30 0000000000000000
GPR31
CR 0000000030905B04
LR 0000000000000000
CTR FFFFFFFFFFFFFFFF
XER 0000000080000000
| {
"language": "Assembly"
} |
/*
BLIS
An object-based framework for developing high-performance BLAS-like
libraries.
Copyright (C) 2014, The University of Texas at Austin
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name(s) of the copyright holder(s) nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "blis.h"
//
// Define function pointer query interfaces.
//
#undef GENFRONT
#define GENFRONT( opname ) \
\
GENARRAY_FPA( PASTECH2(opname,BLIS_TAPI_EX_SUF,_vft), \
PASTECH(opname,BLIS_TAPI_EX_SUF) ); \
\
PASTECH2(opname,BLIS_TAPI_EX_SUF,_vft) \
PASTEMAC2(opname,BLIS_TAPI_EX_SUF,_qfp)( num_t dt ) \
{ \
return PASTECH2(opname,BLIS_TAPI_EX_SUF,_fpa)[ dt ]; \
}
GENFRONT( asumv )
GENFRONT( mkherm )
GENFRONT( mksymm )
GENFRONT( mktrim )
GENFRONT( norm1v )
GENFRONT( normfv )
GENFRONT( normiv )
GENFRONT( norm1m )
GENFRONT( normfm )
GENFRONT( normim )
GENFRONT( randv )
GENFRONT( randnv )
GENFRONT( randm )
GENFRONT( randnm )
GENFRONT( sumsqv )
#undef GENFRONT
#define GENFRONT( opname ) \
\
/*
GENARRAY_FPA( void_fp, opname ); \
*/ \
\
GENARRAY_FPA( PASTECH(opname,_vft), \
PASTECH0(opname) ); \
\
PASTECH(opname,_vft) \
PASTEMAC(opname,_qfp)( num_t dt ) \
{ \
return PASTECH(opname,_fpa)[ dt ]; \
}
GENFRONT( fprintv )
GENFRONT( fprintm )
//GENFRONT( printv )
//GENFRONT( printm )
| {
"language": "Assembly"
} |
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
/**************************************************************************/
/**************************************************************************/
SYSTEM_CLOCK = 6000000
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
/* Setup the stack and heap areas. */
STACK_SIZE = 0x00000400
HEAP_SIZE = 0x00000000
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M33/AC6 */
/* 6.0.2 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 06-30-2020 Scott Larson Initial Version 6.0.1 */
/* 08-14-2020 Scott Larson Modified comment(s), clean up */
/* whitespace, resulting */
/* in version 6.0.2 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)
// {
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global _tx_initialize_low_level
.thumb_func
.type _tx_initialize_low_level, function
_tx_initialize_low_level:
/* Disable interrupts during ThreadX initialization. */
CPSID i
/* Set base of available memory to end of non-initialised RAM area. */
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address
ADD r1, r1, #4 //
STR r1, [r0] // Setup first unused memory pointer
/* Setup Vector Table Offset Register. */
MOV r0, #0xE000E000 // Build address of NVIC registers
LDR r1, =__Vectors // Pickup address of vector table
STR r1, [r0, #0xD08] // Set vector table address
/* Enable the cycle count register. */
LDR r0, =0xE0001000 // Build address of DWT register
LDR r1, [r0] // Pickup the current value
ORR r1, r1, #1 // Set the CYCCNTENA bit
STR r1, [r0] // Enable the cycle count register
/* Set system stack pointer from vector value. */
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
LDR r1, =__Vectors // Pickup address of vector table
LDR r1, [r1] // Pickup reset stack pointer
STR r1, [r0] // Save system stack pointer
/* Configure SysTick. */
MOV r0, #0xE000E000 // Build address of NVIC registers
LDR r1, =SYSTICK_CYCLES
STR r1, [r0, #0x14] // Setup SysTick Reload Value
MOV r1, #0x7 // Build SysTick Control Enable Value
STR r1, [r0, #0x10] // Setup SysTick Control
/* Configure handler priorities. */
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
// Note: SVC must be lowest priority, which is 0xFF
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
// Note: PnSV must be lowest priority, which is 0xFF
/* Return to caller. */
BX lr
// }
/* Define shells for each of the unused vectors. */
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_BadHandler
.thumb_func
.type __tx_BadHandler, function
__tx_BadHandler:
B __tx_BadHandler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_IntHandler
.thumb_func
.type __tx_IntHandler, function
__tx_IntHandler:
// VOID InterruptHandler (VOID)
// {
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
/* Do interrupt handler work here */
/* .... */
POP {r0,lr}
BX LR
// }
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global SysTick_Handler
.thumb_func
.type SysTick_Handler, function
SysTick_Handler:
// VOID TimerInterruptHandler (VOID)
// {
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
BL _tx_timer_interrupt
POP {r0,lr}
BX LR
// }
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global HardFault_Handler
.thumb_func
.type HardFault_Handler, function
HardFault_Handler:
B HardFault_Handler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global UsageFault_Handler
.thumb_func
.type UsageFault_Handler, function
UsageFault_Handler:
CPSID i // Disable interrupts
// Check for stack limit fault
LDR r0, =0xE000ED28 // CFSR address
LDR r1,[r0] // Pick up CFSR
TST r1, #0x00100000 // Check for Stack Overflow
_unhandled_usage_loop:
BEQ _unhandled_usage_loop // If not stack overflow then loop
// Handle stack overflow
STR r1, [r0] // Clear CFSR flag(s)
#ifdef __ARM_PCS_VFP
LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address
LDR r1, [r0] // Load FPCCR
BIC r1, r1, #1 // Clear the lazy preservation active bit
STR r1, [r0] // Store the value
#endif
LDR r0, =_tx_thread_current_ptr // Build current thread pointer address
LDR r0,[r0] // Pick up current thread pointer
PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment)
BL _tx_thread_stack_error_handler // Call ThreadX/user handler
POP {r0,lr} // Restore LR and dummy reg
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
// Call the thread exit function to indicate the thread is no longer executing.
PUSH {r0, lr} // Save LR (and r0 just for alignment)
BL _tx_execution_thread_exit // Call the thread exit function
POP {r0, lr} // Recover LR
#endif
MOV r1, #0 // Build NULL value
LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer
STR r1, [r0] // Clear current thread pointer
// Return from UsageFault_Handler exception
LDR r0, =0xE000ED04 // Load ICSR
LDR r1, =0x10000000 // Set PENDSVSET bit
STR r1, [r0] // Store ICSR
DSB // Wait for memory access to complete
CPSIE i // Enable interrupts
BX lr // Return from exception
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_NMIHandler
.thumb_func
.type __tx_NMIHandler, function
__tx_NMIHandler:
B __tx_NMIHandler
.section .text
.balign 4
.syntax unified
.eabi_attribute Tag_ABI_align_preserved, 1
.global __tx_DBGHandler
.thumb_func
.type __tx_DBGHandler, function
__tx_DBGHandler:
B __tx_DBGHandler
.end
| {
"language": "Assembly"
} |
.386p
NAME kbhit
EXTRN "C", __cbyte :BYTE
DGROUP GROUP CONST,CONST2,_DATA,_BSS
_TEXT SEGMENT BYTE PUBLIC USE32 'CODE'
ASSUME CS:_TEXT ,DS:DGROUP,SS:DGROUP
PUBLIC "C",kbhit_
kbhit_ proc near
cmp dword ptr __cbyte,00000000H
jz L1
mov eax,00000001H
ret
L1: mov ax,ds:[41ah]
cmp ax,ds:[41ch]
jnz L2
xor eax,eax
ret
L2: mov ah,0bH
int 21H
cbw
cwde
ret
kbhit_ endp
_TEXT ENDS
CONST SEGMENT DWORD PUBLIC USE32 'DATA'
CONST ENDS
CONST2 SEGMENT DWORD PUBLIC USE32 'DATA'
CONST2 ENDS
_DATA SEGMENT DWORD PUBLIC USE32 'DATA'
_DATA ENDS
_BSS SEGMENT DWORD PUBLIC USE32 'BSS'
_BSS ENDS
END
| {
"language": "Assembly"
} |
#!/usr/bin/env perl
#
# ====================================================================
# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
# project. Rights for redistribution and usage in source and binary
# forms are granted according to the OpenSSL license.
# ====================================================================
#
# Version 1.1
#
# The major reason for undertaken effort was to mitigate the hazard of
# cache-timing attack. This is [currently and initially!] addressed in
# two ways. 1. S-boxes are compressed from 5KB to 2KB+256B size each.
# 2. References to them are scheduled for L2 cache latency, meaning
# that the tables don't have to reside in L1 cache. Once again, this
# is an initial draft and one should expect more countermeasures to
# be implemented...
#
# Version 1.1 prefetches T[ed]4 in order to mitigate attack on last
# round.
#
# Even though performance was not the primary goal [on the contrary,
# extra shifts "induced" by compressed S-box and longer loop epilogue
# "induced" by scheduling for L2 have negative effect on performance],
# the code turned out to run in ~23 cycles per processed byte en-/
# decrypted with 128-bit key. This is pretty good result for code
# with mentioned qualities and UltraSPARC core. Compared to Sun C
# generated code my encrypt procedure runs just few percents faster,
# while decrypt one - whole 50% faster [yes, Sun C failed to generate
# optimal decrypt procedure]. Compared to GNU C generated code both
# procedures are more than 60% faster:-)
$bits=32;
for (@ARGV) { $bits=64 if (/\-m64/ || /\-xarch\=v9/); }
if ($bits==64) { $bias=2047; $frame=192; }
else { $bias=0; $frame=112; }
$locals=16;
$acc0="%l0";
$acc1="%o0";
$acc2="%o1";
$acc3="%o2";
$acc4="%l1";
$acc5="%o3";
$acc6="%o4";
$acc7="%o5";
$acc8="%l2";
$acc9="%o7";
$acc10="%g1";
$acc11="%g2";
$acc12="%l3";
$acc13="%g3";
$acc14="%g4";
$acc15="%g5";
$t0="%l4";
$t1="%l5";
$t2="%l6";
$t3="%l7";
$s0="%i0";
$s1="%i1";
$s2="%i2";
$s3="%i3";
$tbl="%i4";
$key="%i5";
$rounds="%i7"; # aliases with return address, which is off-loaded to stack
sub _data_word()
{ my $i;
while(defined($i=shift)) { $code.=sprintf"\t.long\t0x%08x,0x%08x\n",$i,$i; }
}
$code.=<<___ if ($bits==64);
.register %g2,#scratch
.register %g3,#scratch
___
$code.=<<___;
.section ".text",#alloc,#execinstr
.align 256
AES_Te:
___
&_data_word(
0xc66363a5, 0xf87c7c84, 0xee777799, 0xf67b7b8d,
0xfff2f20d, 0xd66b6bbd, 0xde6f6fb1, 0x91c5c554,
0x60303050, 0x02010103, 0xce6767a9, 0x562b2b7d,
0xe7fefe19, 0xb5d7d762, 0x4dababe6, 0xec76769a,
0x8fcaca45, 0x1f82829d, 0x89c9c940, 0xfa7d7d87,
0xeffafa15, 0xb25959eb, 0x8e4747c9, 0xfbf0f00b,
0x41adadec, 0xb3d4d467, 0x5fa2a2fd, 0x45afafea,
0x239c9cbf, 0x53a4a4f7, 0xe4727296, 0x9bc0c05b,
0x75b7b7c2, 0xe1fdfd1c, 0x3d9393ae, 0x4c26266a,
0x6c36365a, 0x7e3f3f41, 0xf5f7f702, 0x83cccc4f,
0x6834345c, 0x51a5a5f4, 0xd1e5e534, 0xf9f1f108,
0xe2717193, 0xabd8d873, 0x62313153, 0x2a15153f,
0x0804040c, 0x95c7c752, 0x46232365, 0x9dc3c35e,
0x30181828, 0x379696a1, 0x0a05050f, 0x2f9a9ab5,
0x0e070709, 0x24121236, 0x1b80809b, 0xdfe2e23d,
0xcdebeb26, 0x4e272769, 0x7fb2b2cd, 0xea75759f,
0x1209091b, 0x1d83839e, 0x582c2c74, 0x341a1a2e,
0x361b1b2d, 0xdc6e6eb2, 0xb45a5aee, 0x5ba0a0fb,
0xa45252f6, 0x763b3b4d, 0xb7d6d661, 0x7db3b3ce,
0x5229297b, 0xdde3e33e, 0x5e2f2f71, 0x13848497,
0xa65353f5, 0xb9d1d168, 0x00000000, 0xc1eded2c,
0x40202060, 0xe3fcfc1f, 0x79b1b1c8, 0xb65b5bed,
0xd46a6abe, 0x8dcbcb46, 0x67bebed9, 0x7239394b,
0x944a4ade, 0x984c4cd4, 0xb05858e8, 0x85cfcf4a,
0xbbd0d06b, 0xc5efef2a, 0x4faaaae5, 0xedfbfb16,
0x864343c5, 0x9a4d4dd7, 0x66333355, 0x11858594,
0x8a4545cf, 0xe9f9f910, 0x04020206, 0xfe7f7f81,
0xa05050f0, 0x783c3c44, 0x259f9fba, 0x4ba8a8e3,
0xa25151f3, 0x5da3a3fe, 0x804040c0, 0x058f8f8a,
0x3f9292ad, 0x219d9dbc, 0x70383848, 0xf1f5f504,
0x63bcbcdf, 0x77b6b6c1, 0xafdada75, 0x42212163,
0x20101030, 0xe5ffff1a, 0xfdf3f30e, 0xbfd2d26d,
0x81cdcd4c, 0x180c0c14, 0x26131335, 0xc3ecec2f,
0xbe5f5fe1, 0x359797a2, 0x884444cc, 0x2e171739,
0x93c4c457, 0x55a7a7f2, 0xfc7e7e82, 0x7a3d3d47,
0xc86464ac, 0xba5d5de7, 0x3219192b, 0xe6737395,
0xc06060a0, 0x19818198, 0x9e4f4fd1, 0xa3dcdc7f,
0x44222266, 0x542a2a7e, 0x3b9090ab, 0x0b888883,
0x8c4646ca, 0xc7eeee29, 0x6bb8b8d3, 0x2814143c,
0xa7dede79, 0xbc5e5ee2, 0x160b0b1d, 0xaddbdb76,
0xdbe0e03b, 0x64323256, 0x743a3a4e, 0x140a0a1e,
0x924949db, 0x0c06060a, 0x4824246c, 0xb85c5ce4,
0x9fc2c25d, 0xbdd3d36e, 0x43acacef, 0xc46262a6,
0x399191a8, 0x319595a4, 0xd3e4e437, 0xf279798b,
0xd5e7e732, 0x8bc8c843, 0x6e373759, 0xda6d6db7,
0x018d8d8c, 0xb1d5d564, 0x9c4e4ed2, 0x49a9a9e0,
0xd86c6cb4, 0xac5656fa, 0xf3f4f407, 0xcfeaea25,
0xca6565af, 0xf47a7a8e, 0x47aeaee9, 0x10080818,
0x6fbabad5, 0xf0787888, 0x4a25256f, 0x5c2e2e72,
0x381c1c24, 0x57a6a6f1, 0x73b4b4c7, 0x97c6c651,
0xcbe8e823, 0xa1dddd7c, 0xe874749c, 0x3e1f1f21,
0x964b4bdd, 0x61bdbddc, 0x0d8b8b86, 0x0f8a8a85,
0xe0707090, 0x7c3e3e42, 0x71b5b5c4, 0xcc6666aa,
0x904848d8, 0x06030305, 0xf7f6f601, 0x1c0e0e12,
0xc26161a3, 0x6a35355f, 0xae5757f9, 0x69b9b9d0,
0x17868691, 0x99c1c158, 0x3a1d1d27, 0x279e9eb9,
0xd9e1e138, 0xebf8f813, 0x2b9898b3, 0x22111133,
0xd26969bb, 0xa9d9d970, 0x078e8e89, 0x339494a7,
0x2d9b9bb6, 0x3c1e1e22, 0x15878792, 0xc9e9e920,
0x87cece49, 0xaa5555ff, 0x50282878, 0xa5dfdf7a,
0x038c8c8f, 0x59a1a1f8, 0x09898980, 0x1a0d0d17,
0x65bfbfda, 0xd7e6e631, 0x844242c6, 0xd06868b8,
0x824141c3, 0x299999b0, 0x5a2d2d77, 0x1e0f0f11,
0x7bb0b0cb, 0xa85454fc, 0x6dbbbbd6, 0x2c16163a);
$code.=<<___;
.byte 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5
.byte 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76
.byte 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0
.byte 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0
.byte 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc
.byte 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15
.byte 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a
.byte 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75
.byte 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0
.byte 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84
.byte 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b
.byte 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf
.byte 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85
.byte 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8
.byte 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5
.byte 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2
.byte 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17
.byte 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73
.byte 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88
.byte 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb
.byte 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c
.byte 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79
.byte 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9
.byte 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08
.byte 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6
.byte 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a
.byte 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e
.byte 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e
.byte 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94
.byte 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf
.byte 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68
.byte 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
.type AES_Te,#object
.size AES_Te,(.-AES_Te)
.align 64
.skip 16
_sparcv9_AES_encrypt:
save %sp,-$frame-$locals,%sp
stx %i7,[%sp+$bias+$frame+0] ! off-load return address
ld [$key+240],$rounds
ld [$key+0],$t0
ld [$key+4],$t1 !
ld [$key+8],$t2
srl $rounds,1,$rounds
xor $t0,$s0,$s0
ld [$key+12],$t3
srl $s0,21,$acc0
xor $t1,$s1,$s1
ld [$key+16],$t0
srl $s1,13,$acc1 !
xor $t2,$s2,$s2
ld [$key+20],$t1
xor $t3,$s3,$s3
ld [$key+24],$t2
and $acc0,2040,$acc0
ld [$key+28],$t3
nop
.Lenc_loop:
srl $s2,5,$acc2 !
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $s3,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
srl $s1,21,$acc4
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2 !
srl $s2,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $s3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4
fmovs %f0,%f0
sll $s0,3,$acc7 !
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $s2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
srl $s3,13,$acc9
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7 !
srl $s0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $s1,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9
fmovs %f0,%f0
srl $s3,21,$acc12 !
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $s0,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
srl $s1,5,$acc14
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12 !
sll $s2,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
and $acc15,2040,$acc15
add $key,32,$key
ldx [$tbl+$acc14],$acc14
fmovs %f0,%f0
subcc $rounds,1,$rounds !
ldx [$tbl+$acc15],$acc15
bz,a,pn %icc,.Lenc_last
add $tbl,2048,$rounds
srlx $acc1,8,$acc1
xor $acc0,$t0,$t0
ld [$key+0],$s0
fmovs %f0,%f0
srlx $acc2,16,$acc2 !
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3 !
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
fmovs %f0,%f0
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10 !
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15 !
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,21,$acc0
xor $acc14,$t3,$t3
srl $t1,13,$acc1
xor $acc15,$t3,$t3
and $acc0,2040,$acc0 !
srl $t2,5,$acc2
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $t3,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
fmovs %f0,%f0
srl $t1,21,$acc4 !
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2
srl $t2,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $t3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4 !
sll $t0,3,$acc7
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $t2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
fmovs %f0,%f0
srl $t3,13,$acc9 !
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7
srl $t0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $t1,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9 !
srl $t3,21,$acc12
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $t0,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
fmovs %f0,%f0
srl $t1,5,$acc14 !
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12
sll $t2,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
srlx $acc1,8,$acc1
and $acc15,2040,$acc15
ldx [$tbl+$acc14],$acc14 !
srlx $acc2,16,$acc2
xor $acc0,$s0,$s0
ldx [$tbl+$acc15],$acc15
srlx $acc3,24,$acc3
xor $acc1,$s0,$s0
ld [$key+16],$t0
fmovs %f0,%f0
srlx $acc5,8,$acc5 !
xor $acc2,$s0,$s0
ld [$key+20],$t1
srlx $acc6,16,$acc6
xor $acc3,$s0,$s0
ld [$key+24],$t2
srlx $acc7,24,$acc7
xor $acc4,$s1,$s1
ld [$key+28],$t3 !
srlx $acc9,8,$acc9
xor $acc5,$s1,$s1
ldx [$tbl+2048+0],%g0 ! prefetch te4
srlx $acc10,16,$acc10
xor $acc6,$s1,$s1
ldx [$tbl+2048+32],%g0 ! prefetch te4
srlx $acc11,24,$acc11
xor $acc7,$s1,$s1
ldx [$tbl+2048+64],%g0 ! prefetch te4
srlx $acc13,8,$acc13
xor $acc8,$s2,$s2
ldx [$tbl+2048+96],%g0 ! prefetch te4
srlx $acc14,16,$acc14 !
xor $acc9,$s2,$s2
ldx [$tbl+2048+128],%g0 ! prefetch te4
srlx $acc15,24,$acc15
xor $acc10,$s2,$s2
ldx [$tbl+2048+160],%g0 ! prefetch te4
srl $s0,21,$acc0
xor $acc11,$s2,$s2
ldx [$tbl+2048+192],%g0 ! prefetch te4
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
ldx [$tbl+2048+224],%g0 ! prefetch te4
srl $s1,13,$acc1 !
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ba .Lenc_loop
and $acc0,2040,$acc0
.align 32
.Lenc_last:
srlx $acc1,8,$acc1 !
xor $acc0,$t0,$t0
ld [$key+0],$s0
srlx $acc2,16,$acc2
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2 !
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9 !
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14 !
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,24,$acc0
xor $acc14,$t3,$t3
srl $t1,16,$acc1 !
xor $acc15,$t3,$t3
srl $t2,8,$acc2
and $acc1,255,$acc1
ldub [$rounds+$acc0],$acc0
srl $t1,24,$acc4
and $acc2,255,$acc2
ldub [$rounds+$acc1],$acc1
srl $t2,16,$acc5 !
and $t3,255,$acc3
ldub [$rounds+$acc2],$acc2
ldub [$rounds+$acc3],$acc3
srl $t3,8,$acc6
and $acc5,255,$acc5
ldub [$rounds+$acc4],$acc4
fmovs %f0,%f0
srl $t2,24,$acc8 !
and $acc6,255,$acc6
ldub [$rounds+$acc5],$acc5
srl $t3,16,$acc9
and $t0,255,$acc7
ldub [$rounds+$acc6],$acc6
ldub [$rounds+$acc7],$acc7
fmovs %f0,%f0
srl $t0,8,$acc10 !
and $acc9,255,$acc9
ldub [$rounds+$acc8],$acc8
srl $t3,24,$acc12
and $acc10,255,$acc10
ldub [$rounds+$acc9],$acc9
srl $t0,16,$acc13
and $t1,255,$acc11
ldub [$rounds+$acc10],$acc10 !
srl $t1,8,$acc14
and $acc13,255,$acc13
ldub [$rounds+$acc11],$acc11
ldub [$rounds+$acc12],$acc12
and $acc14,255,$acc14
ldub [$rounds+$acc13],$acc13
and $t2,255,$acc15
ldub [$rounds+$acc14],$acc14 !
sll $acc0,24,$acc0
xor $acc3,$s0,$s0
ldub [$rounds+$acc15],$acc15
sll $acc1,16,$acc1
xor $acc0,$s0,$s0
ldx [%sp+$bias+$frame+0],%i7 ! restore return address
fmovs %f0,%f0
sll $acc2,8,$acc2 !
xor $acc1,$s0,$s0
sll $acc4,24,$acc4
xor $acc2,$s0,$s0
sll $acc5,16,$acc5
xor $acc7,$s1,$s1
sll $acc6,8,$acc6
xor $acc4,$s1,$s1
sll $acc8,24,$acc8 !
xor $acc5,$s1,$s1
sll $acc9,16,$acc9
xor $acc11,$s2,$s2
sll $acc10,8,$acc10
xor $acc6,$s1,$s1
sll $acc12,24,$acc12
xor $acc8,$s2,$s2
sll $acc13,16,$acc13 !
xor $acc9,$s2,$s2
sll $acc14,8,$acc14
xor $acc10,$s2,$s2
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ret
restore
.type _sparcv9_AES_encrypt,#function
.size _sparcv9_AES_encrypt,(.-_sparcv9_AES_encrypt)
.align 32
.globl AES_encrypt
AES_encrypt:
or %o0,%o1,%g1
andcc %g1,3,%g0
bnz,pn %xcc,.Lunaligned_enc
save %sp,-$frame,%sp
ld [%i0+0],%o0
ld [%i0+4],%o1
ld [%i0+8],%o2
ld [%i0+12],%o3
1: call .+8
add %o7,AES_Te-1b,%o4
call _sparcv9_AES_encrypt
mov %i2,%o5
st %o0,[%i1+0]
st %o1,[%i1+4]
st %o2,[%i1+8]
st %o3,[%i1+12]
ret
restore
.align 32
.Lunaligned_enc:
ldub [%i0+0],%l0
ldub [%i0+1],%l1
ldub [%i0+2],%l2
sll %l0,24,%l0
ldub [%i0+3],%l3
sll %l1,16,%l1
ldub [%i0+4],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+5],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+6],%l6
sll %l5,16,%l5
or %l0,%l2,%o0
ldub [%i0+7],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
ldub [%i0+8],%l0
or %l7,%l6,%l6
ldub [%i0+9],%l1
or %l4,%l6,%o1
ldub [%i0+10],%l2
sll %l0,24,%l0
ldub [%i0+11],%l3
sll %l1,16,%l1
ldub [%i0+12],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+13],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+14],%l6
sll %l5,16,%l5
or %l0,%l2,%o2
ldub [%i0+15],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
or %l7,%l6,%l6
or %l4,%l6,%o3
1: call .+8
add %o7,AES_Te-1b,%o4
call _sparcv9_AES_encrypt
mov %i2,%o5
srl %o0,24,%l0
srl %o0,16,%l1
stb %l0,[%i1+0]
srl %o0,8,%l2
stb %l1,[%i1+1]
stb %l2,[%i1+2]
srl %o1,24,%l4
stb %o0,[%i1+3]
srl %o1,16,%l5
stb %l4,[%i1+4]
srl %o1,8,%l6
stb %l5,[%i1+5]
stb %l6,[%i1+6]
srl %o2,24,%l0
stb %o1,[%i1+7]
srl %o2,16,%l1
stb %l0,[%i1+8]
srl %o2,8,%l2
stb %l1,[%i1+9]
stb %l2,[%i1+10]
srl %o3,24,%l4
stb %o2,[%i1+11]
srl %o3,16,%l5
stb %l4,[%i1+12]
srl %o3,8,%l6
stb %l5,[%i1+13]
stb %l6,[%i1+14]
stb %o3,[%i1+15]
ret
restore
.type AES_encrypt,#function
.size AES_encrypt,(.-AES_encrypt)
___
$code.=<<___;
.align 256
AES_Td:
___
&_data_word(
0x51f4a750, 0x7e416553, 0x1a17a4c3, 0x3a275e96,
0x3bab6bcb, 0x1f9d45f1, 0xacfa58ab, 0x4be30393,
0x2030fa55, 0xad766df6, 0x88cc7691, 0xf5024c25,
0x4fe5d7fc, 0xc52acbd7, 0x26354480, 0xb562a38f,
0xdeb15a49, 0x25ba1b67, 0x45ea0e98, 0x5dfec0e1,
0xc32f7502, 0x814cf012, 0x8d4697a3, 0x6bd3f9c6,
0x038f5fe7, 0x15929c95, 0xbf6d7aeb, 0x955259da,
0xd4be832d, 0x587421d3, 0x49e06929, 0x8ec9c844,
0x75c2896a, 0xf48e7978, 0x99583e6b, 0x27b971dd,
0xbee14fb6, 0xf088ad17, 0xc920ac66, 0x7dce3ab4,
0x63df4a18, 0xe51a3182, 0x97513360, 0x62537f45,
0xb16477e0, 0xbb6bae84, 0xfe81a01c, 0xf9082b94,
0x70486858, 0x8f45fd19, 0x94de6c87, 0x527bf8b7,
0xab73d323, 0x724b02e2, 0xe31f8f57, 0x6655ab2a,
0xb2eb2807, 0x2fb5c203, 0x86c57b9a, 0xd33708a5,
0x302887f2, 0x23bfa5b2, 0x02036aba, 0xed16825c,
0x8acf1c2b, 0xa779b492, 0xf307f2f0, 0x4e69e2a1,
0x65daf4cd, 0x0605bed5, 0xd134621f, 0xc4a6fe8a,
0x342e539d, 0xa2f355a0, 0x058ae132, 0xa4f6eb75,
0x0b83ec39, 0x4060efaa, 0x5e719f06, 0xbd6e1051,
0x3e218af9, 0x96dd063d, 0xdd3e05ae, 0x4de6bd46,
0x91548db5, 0x71c45d05, 0x0406d46f, 0x605015ff,
0x1998fb24, 0xd6bde997, 0x894043cc, 0x67d99e77,
0xb0e842bd, 0x07898b88, 0xe7195b38, 0x79c8eedb,
0xa17c0a47, 0x7c420fe9, 0xf8841ec9, 0x00000000,
0x09808683, 0x322bed48, 0x1e1170ac, 0x6c5a724e,
0xfd0efffb, 0x0f853856, 0x3daed51e, 0x362d3927,
0x0a0fd964, 0x685ca621, 0x9b5b54d1, 0x24362e3a,
0x0c0a67b1, 0x9357e70f, 0xb4ee96d2, 0x1b9b919e,
0x80c0c54f, 0x61dc20a2, 0x5a774b69, 0x1c121a16,
0xe293ba0a, 0xc0a02ae5, 0x3c22e043, 0x121b171d,
0x0e090d0b, 0xf28bc7ad, 0x2db6a8b9, 0x141ea9c8,
0x57f11985, 0xaf75074c, 0xee99ddbb, 0xa37f60fd,
0xf701269f, 0x5c72f5bc, 0x44663bc5, 0x5bfb7e34,
0x8b432976, 0xcb23c6dc, 0xb6edfc68, 0xb8e4f163,
0xd731dcca, 0x42638510, 0x13972240, 0x84c61120,
0x854a247d, 0xd2bb3df8, 0xaef93211, 0xc729a16d,
0x1d9e2f4b, 0xdcb230f3, 0x0d8652ec, 0x77c1e3d0,
0x2bb3166c, 0xa970b999, 0x119448fa, 0x47e96422,
0xa8fc8cc4, 0xa0f03f1a, 0x567d2cd8, 0x223390ef,
0x87494ec7, 0xd938d1c1, 0x8ccaa2fe, 0x98d40b36,
0xa6f581cf, 0xa57ade28, 0xdab78e26, 0x3fadbfa4,
0x2c3a9de4, 0x5078920d, 0x6a5fcc9b, 0x547e4662,
0xf68d13c2, 0x90d8b8e8, 0x2e39f75e, 0x82c3aff5,
0x9f5d80be, 0x69d0937c, 0x6fd52da9, 0xcf2512b3,
0xc8ac993b, 0x10187da7, 0xe89c636e, 0xdb3bbb7b,
0xcd267809, 0x6e5918f4, 0xec9ab701, 0x834f9aa8,
0xe6956e65, 0xaaffe67e, 0x21bccf08, 0xef15e8e6,
0xbae79bd9, 0x4a6f36ce, 0xea9f09d4, 0x29b07cd6,
0x31a4b2af, 0x2a3f2331, 0xc6a59430, 0x35a266c0,
0x744ebc37, 0xfc82caa6, 0xe090d0b0, 0x33a7d815,
0xf104984a, 0x41ecdaf7, 0x7fcd500e, 0x1791f62f,
0x764dd68d, 0x43efb04d, 0xccaa4d54, 0xe49604df,
0x9ed1b5e3, 0x4c6a881b, 0xc12c1fb8, 0x4665517f,
0x9d5eea04, 0x018c355d, 0xfa877473, 0xfb0b412e,
0xb3671d5a, 0x92dbd252, 0xe9105633, 0x6dd64713,
0x9ad7618c, 0x37a10c7a, 0x59f8148e, 0xeb133c89,
0xcea927ee, 0xb761c935, 0xe11ce5ed, 0x7a47b13c,
0x9cd2df59, 0x55f2733f, 0x1814ce79, 0x73c737bf,
0x53f7cdea, 0x5ffdaa5b, 0xdf3d6f14, 0x7844db86,
0xcaaff381, 0xb968c43e, 0x3824342c, 0xc2a3405f,
0x161dc372, 0xbce2250c, 0x283c498b, 0xff0d9541,
0x39a80171, 0x080cb3de, 0xd8b4e49c, 0x6456c190,
0x7bcb8461, 0xd532b670, 0x486c5c74, 0xd0b85742);
$code.=<<___;
.byte 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38
.byte 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb
.byte 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87
.byte 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb
.byte 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d
.byte 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e
.byte 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2
.byte 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25
.byte 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16
.byte 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92
.byte 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda
.byte 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84
.byte 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a
.byte 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06
.byte 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02
.byte 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b
.byte 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea
.byte 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73
.byte 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85
.byte 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e
.byte 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89
.byte 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b
.byte 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20
.byte 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4
.byte 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31
.byte 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f
.byte 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d
.byte 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef
.byte 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0
.byte 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61
.byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26
.byte 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d
.type AES_Td,#object
.size AES_Td,(.-AES_Td)
.align 64
.skip 16
_sparcv9_AES_decrypt:
save %sp,-$frame-$locals,%sp
stx %i7,[%sp+$bias+$frame+0] ! off-load return address
ld [$key+240],$rounds
ld [$key+0],$t0
ld [$key+4],$t1 !
ld [$key+8],$t2
ld [$key+12],$t3
srl $rounds,1,$rounds
xor $t0,$s0,$s0
ld [$key+16],$t0
xor $t1,$s1,$s1
ld [$key+20],$t1
srl $s0,21,$acc0 !
xor $t2,$s2,$s2
ld [$key+24],$t2
xor $t3,$s3,$s3
and $acc0,2040,$acc0
ld [$key+28],$t3
srl $s3,13,$acc1
nop
.Ldec_loop:
srl $s2,5,$acc2 !
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $s1,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
srl $s1,21,$acc4
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2 !
srl $s0,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $s3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4
fmovs %f0,%f0
sll $s2,3,$acc7 !
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $s2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
srl $s1,13,$acc9
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7 !
srl $s0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $s3,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9
fmovs %f0,%f0
srl $s3,21,$acc12 !
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $s2,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
srl $s1,5,$acc14
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12 !
sll $s0,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
and $acc15,2040,$acc15
add $key,32,$key
ldx [$tbl+$acc14],$acc14
fmovs %f0,%f0
subcc $rounds,1,$rounds !
ldx [$tbl+$acc15],$acc15
bz,a,pn %icc,.Ldec_last
add $tbl,2048,$rounds
srlx $acc1,8,$acc1
xor $acc0,$t0,$t0
ld [$key+0],$s0
fmovs %f0,%f0
srlx $acc2,16,$acc2 !
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3 !
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
fmovs %f0,%f0
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10 !
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15 !
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,21,$acc0
xor $acc14,$t3,$t3
xor $acc15,$t3,$t3
srl $t3,13,$acc1
and $acc0,2040,$acc0 !
srl $t2,5,$acc2
and $acc1,2040,$acc1
ldx [$tbl+$acc0],$acc0
sll $t1,3,$acc3
and $acc2,2040,$acc2
ldx [$tbl+$acc1],$acc1
fmovs %f0,%f0
srl $t1,21,$acc4 !
and $acc3,2040,$acc3
ldx [$tbl+$acc2],$acc2
srl $t0,13,$acc5
and $acc4,2040,$acc4
ldx [$tbl+$acc3],$acc3
srl $t3,5,$acc6
and $acc5,2040,$acc5
ldx [$tbl+$acc4],$acc4 !
sll $t2,3,$acc7
and $acc6,2040,$acc6
ldx [$tbl+$acc5],$acc5
srl $t2,21,$acc8
and $acc7,2040,$acc7
ldx [$tbl+$acc6],$acc6
fmovs %f0,%f0
srl $t1,13,$acc9 !
and $acc8,2040,$acc8
ldx [$tbl+$acc7],$acc7
srl $t0,5,$acc10
and $acc9,2040,$acc9
ldx [$tbl+$acc8],$acc8
sll $t3,3,$acc11
and $acc10,2040,$acc10
ldx [$tbl+$acc9],$acc9 !
srl $t3,21,$acc12
and $acc11,2040,$acc11
ldx [$tbl+$acc10],$acc10
srl $t2,13,$acc13
and $acc12,2040,$acc12
ldx [$tbl+$acc11],$acc11
fmovs %f0,%f0
srl $t1,5,$acc14 !
and $acc13,2040,$acc13
ldx [$tbl+$acc12],$acc12
sll $t0,3,$acc15
and $acc14,2040,$acc14
ldx [$tbl+$acc13],$acc13
srlx $acc1,8,$acc1
and $acc15,2040,$acc15
ldx [$tbl+$acc14],$acc14 !
srlx $acc2,16,$acc2
xor $acc0,$s0,$s0
ldx [$tbl+$acc15],$acc15
srlx $acc3,24,$acc3
xor $acc1,$s0,$s0
ld [$key+16],$t0
fmovs %f0,%f0
srlx $acc5,8,$acc5 !
xor $acc2,$s0,$s0
ld [$key+20],$t1
srlx $acc6,16,$acc6
xor $acc3,$s0,$s0
ld [$key+24],$t2
srlx $acc7,24,$acc7
xor $acc4,$s1,$s1
ld [$key+28],$t3 !
srlx $acc9,8,$acc9
xor $acc5,$s1,$s1
ldx [$tbl+2048+0],%g0 ! prefetch td4
srlx $acc10,16,$acc10
xor $acc6,$s1,$s1
ldx [$tbl+2048+32],%g0 ! prefetch td4
srlx $acc11,24,$acc11
xor $acc7,$s1,$s1
ldx [$tbl+2048+64],%g0 ! prefetch td4
srlx $acc13,8,$acc13
xor $acc8,$s2,$s2
ldx [$tbl+2048+96],%g0 ! prefetch td4
srlx $acc14,16,$acc14 !
xor $acc9,$s2,$s2
ldx [$tbl+2048+128],%g0 ! prefetch td4
srlx $acc15,24,$acc15
xor $acc10,$s2,$s2
ldx [$tbl+2048+160],%g0 ! prefetch td4
srl $s0,21,$acc0
xor $acc11,$s2,$s2
ldx [$tbl+2048+192],%g0 ! prefetch td4
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
ldx [$tbl+2048+224],%g0 ! prefetch td4
and $acc0,2040,$acc0 !
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ba .Ldec_loop
srl $s3,13,$acc1
.align 32
.Ldec_last:
srlx $acc1,8,$acc1 !
xor $acc0,$t0,$t0
ld [$key+0],$s0
srlx $acc2,16,$acc2
xor $acc1,$t0,$t0
ld [$key+4],$s1
srlx $acc3,24,$acc3
xor $acc2,$t0,$t0
ld [$key+8],$s2 !
srlx $acc5,8,$acc5
xor $acc3,$t0,$t0
ld [$key+12],$s3
srlx $acc6,16,$acc6
xor $acc4,$t1,$t1
srlx $acc7,24,$acc7
xor $acc5,$t1,$t1
srlx $acc9,8,$acc9 !
xor $acc6,$t1,$t1
srlx $acc10,16,$acc10
xor $acc7,$t1,$t1
srlx $acc11,24,$acc11
xor $acc8,$t2,$t2
srlx $acc13,8,$acc13
xor $acc9,$t2,$t2
srlx $acc14,16,$acc14 !
xor $acc10,$t2,$t2
srlx $acc15,24,$acc15
xor $acc11,$t2,$t2
xor $acc12,$acc14,$acc14
xor $acc13,$t3,$t3
srl $t0,24,$acc0
xor $acc14,$t3,$t3
xor $acc15,$t3,$t3 !
srl $t3,16,$acc1
srl $t2,8,$acc2
and $acc1,255,$acc1
ldub [$rounds+$acc0],$acc0
srl $t1,24,$acc4
and $acc2,255,$acc2
ldub [$rounds+$acc1],$acc1
srl $t0,16,$acc5 !
and $t1,255,$acc3
ldub [$rounds+$acc2],$acc2
ldub [$rounds+$acc3],$acc3
srl $t3,8,$acc6
and $acc5,255,$acc5
ldub [$rounds+$acc4],$acc4
fmovs %f0,%f0
srl $t2,24,$acc8 !
and $acc6,255,$acc6
ldub [$rounds+$acc5],$acc5
srl $t1,16,$acc9
and $t2,255,$acc7
ldub [$rounds+$acc6],$acc6
ldub [$rounds+$acc7],$acc7
fmovs %f0,%f0
srl $t0,8,$acc10 !
and $acc9,255,$acc9
ldub [$rounds+$acc8],$acc8
srl $t3,24,$acc12
and $acc10,255,$acc10
ldub [$rounds+$acc9],$acc9
srl $t2,16,$acc13
and $t3,255,$acc11
ldub [$rounds+$acc10],$acc10 !
srl $t1,8,$acc14
and $acc13,255,$acc13
ldub [$rounds+$acc11],$acc11
ldub [$rounds+$acc12],$acc12
and $acc14,255,$acc14
ldub [$rounds+$acc13],$acc13
and $t0,255,$acc15
ldub [$rounds+$acc14],$acc14 !
sll $acc0,24,$acc0
xor $acc3,$s0,$s0
ldub [$rounds+$acc15],$acc15
sll $acc1,16,$acc1
xor $acc0,$s0,$s0
ldx [%sp+$bias+$frame+0],%i7 ! restore return address
fmovs %f0,%f0
sll $acc2,8,$acc2 !
xor $acc1,$s0,$s0
sll $acc4,24,$acc4
xor $acc2,$s0,$s0
sll $acc5,16,$acc5
xor $acc7,$s1,$s1
sll $acc6,8,$acc6
xor $acc4,$s1,$s1
sll $acc8,24,$acc8 !
xor $acc5,$s1,$s1
sll $acc9,16,$acc9
xor $acc11,$s2,$s2
sll $acc10,8,$acc10
xor $acc6,$s1,$s1
sll $acc12,24,$acc12
xor $acc8,$s2,$s2
sll $acc13,16,$acc13 !
xor $acc9,$s2,$s2
sll $acc14,8,$acc14
xor $acc10,$s2,$s2
xor $acc12,$acc14,$acc14
xor $acc13,$s3,$s3
xor $acc14,$s3,$s3
xor $acc15,$s3,$s3
ret
restore
.type _sparcv9_AES_decrypt,#function
.size _sparcv9_AES_decrypt,(.-_sparcv9_AES_decrypt)
.align 32
.globl AES_decrypt
AES_decrypt:
or %o0,%o1,%g1
andcc %g1,3,%g0
bnz,pn %xcc,.Lunaligned_dec
save %sp,-$frame,%sp
ld [%i0+0],%o0
ld [%i0+4],%o1
ld [%i0+8],%o2
ld [%i0+12],%o3
1: call .+8
add %o7,AES_Td-1b,%o4
call _sparcv9_AES_decrypt
mov %i2,%o5
st %o0,[%i1+0]
st %o1,[%i1+4]
st %o2,[%i1+8]
st %o3,[%i1+12]
ret
restore
.align 32
.Lunaligned_dec:
ldub [%i0+0],%l0
ldub [%i0+1],%l1
ldub [%i0+2],%l2
sll %l0,24,%l0
ldub [%i0+3],%l3
sll %l1,16,%l1
ldub [%i0+4],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+5],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+6],%l6
sll %l5,16,%l5
or %l0,%l2,%o0
ldub [%i0+7],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
ldub [%i0+8],%l0
or %l7,%l6,%l6
ldub [%i0+9],%l1
or %l4,%l6,%o1
ldub [%i0+10],%l2
sll %l0,24,%l0
ldub [%i0+11],%l3
sll %l1,16,%l1
ldub [%i0+12],%l4
sll %l2,8,%l2
or %l1,%l0,%l0
ldub [%i0+13],%l5
sll %l4,24,%l4
or %l3,%l2,%l2
ldub [%i0+14],%l6
sll %l5,16,%l5
or %l0,%l2,%o2
ldub [%i0+15],%l7
sll %l6,8,%l6
or %l5,%l4,%l4
or %l7,%l6,%l6
or %l4,%l6,%o3
1: call .+8
add %o7,AES_Td-1b,%o4
call _sparcv9_AES_decrypt
mov %i2,%o5
srl %o0,24,%l0
srl %o0,16,%l1
stb %l0,[%i1+0]
srl %o0,8,%l2
stb %l1,[%i1+1]
stb %l2,[%i1+2]
srl %o1,24,%l4
stb %o0,[%i1+3]
srl %o1,16,%l5
stb %l4,[%i1+4]
srl %o1,8,%l6
stb %l5,[%i1+5]
stb %l6,[%i1+6]
srl %o2,24,%l0
stb %o1,[%i1+7]
srl %o2,16,%l1
stb %l0,[%i1+8]
srl %o2,8,%l2
stb %l1,[%i1+9]
stb %l2,[%i1+10]
srl %o3,24,%l4
stb %o2,[%i1+11]
srl %o3,16,%l5
stb %l4,[%i1+12]
srl %o3,8,%l6
stb %l5,[%i1+13]
stb %l6,[%i1+14]
stb %o3,[%i1+15]
ret
restore
.type AES_decrypt,#function
.size AES_decrypt,(.-AES_decrypt)
___
# fmovs instructions substituting for FP nops were originally added
# to meet specific instruction alignment requirements to maximize ILP.
# As UltraSPARC T1, a.k.a. Niagara, has shared FPU, FP nops can have
# undesired effect, so just omit them and sacrifice some portion of
# percent in performance...
$code =~ s/fmovs.*$//gm;
print $code;
close STDOUT; # ensure flush
| {
"language": "Assembly"
} |
// /** @file
// SMM Core SMM Services Table Library.
//
// SMM Core SMM Services Table Library.
//
// Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// **/
#string STR_MODULE_ABSTRACT #language en-US "SMM Core SMM Services Table Library"
#string STR_MODULE_DESCRIPTION #language en-US "SMM Core SMM Services Table Library."
| {
"language": "Assembly"
} |
/* AArch64 assembler/disassembler support.
Copyright (C) 2009-2016 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef OPCODE_AARCH64_H
#define OPCODE_AARCH64_H
#include "bfd.h"
#include "bfd_stdint.h"
#include <assert.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/* The offset for pc-relative addressing is currently defined to be 0. */
#define AARCH64_PCREL_OFFSET 0
typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD)
#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD \
| AARCH64_FEATURE_CRC \
| AARCH64_FEATURE_V8_1 \
| AARCH64_FEATURE_LSE \
| AARCH64_FEATURE_PAN \
| AARCH64_FEATURE_LOR \
| AARCH64_FEATURE_RDMA)
#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_V8_2 \
| AARCH64_FEATURE_F16 \
| AARCH64_FEATURE_RAS \
| AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD \
| AARCH64_FEATURE_CRC \
| AARCH64_FEATURE_V8_1 \
| AARCH64_FEATURE_LSE \
| AARCH64_FEATURE_PAN \
| AARCH64_FEATURE_LOR \
| AARCH64_FEATURE_RDMA)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
/* CPU-specific features. */
typedef unsigned long aarch64_feature_set;
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU) & (FEAT)) != 0)
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) | (F2); \
} \
while (0)
#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) &~ (F2); \
} \
while (0)
#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
(((OPC) & (FEAT)) != 0)
enum aarch64_operand_class
{
AARCH64_OPND_CLASS_NIL,
AARCH64_OPND_CLASS_INT_REG,
AARCH64_OPND_CLASS_MODIFIED_REG,
AARCH64_OPND_CLASS_FP_REG,
AARCH64_OPND_CLASS_SIMD_REG,
AARCH64_OPND_CLASS_SIMD_ELEMENT,
AARCH64_OPND_CLASS_SISD_REG,
AARCH64_OPND_CLASS_SIMD_REGLIST,
AARCH64_OPND_CLASS_CP_REG,
AARCH64_OPND_CLASS_ADDRESS,
AARCH64_OPND_CLASS_IMMEDIATE,
AARCH64_OPND_CLASS_SYSTEM,
AARCH64_OPND_CLASS_COND,
};
/* Operand code that helps both parsing and coding.
Keep AARCH64_OPERANDS synced. */
enum aarch64_opnd
{
AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
AARCH64_OPND_Rd, /* Integer register as destination. */
AARCH64_OPND_Rn, /* Integer register as source. */
AARCH64_OPND_Rm, /* Integer register as source. */
AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
AARCH64_OPND_PAIRREG, /* Paired register operand. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
AARCH64_OPND_Fd, /* Floating-point Fd. */
AARCH64_OPND_Fn, /* Floating-point Fn. */
AARCH64_OPND_Fm, /* Floating-point Fm. */
AARCH64_OPND_Fa, /* Floating-point Fa. */
AARCH64_OPND_Ft, /* Floating-point Ft. */
AARCH64_OPND_Ft2, /* Floating-point Ft2. */
AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
structure to all lanes. */
AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
(no encoding). */
AARCH64_OPND_IMM0, /* Immediate for #0. */
AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
AARCH64_OPND_IMM, /* Immediate. */
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
each condition flag. */
AARCH64_OPND_LIMM, /* Logical Immediate. */
AARCH64_OPND_AIMM, /* Arithmetic immediate. */
AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
AARCH64_OPND_COND, /* Standard condition as the last operand. */
AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
negative or unaligned and there is
no writeback allowed. This operand code
is only used to support the programmer-
friendly feature of using LDR/STR as the
the mnemonic name for LDUR/STUR instructions
wherever there is no ambiguity. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
AARCH64_OPND_SYSREG, /* System register operand. */
AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
operand type or limits values available to an operand type.
N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
enum aarch64_opnd_qualifier
{
/* Indicating no further qualification on an operand. */
AARCH64_OPND_QLF_NIL,
/* Qualifying an operand which is a general purpose (integer) register;
indicating the operand data size or a specific register. */
AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
AARCH64_OPND_QLF_WSP, /* WSP. */
AARCH64_OPND_QLF_SP, /* SP. */
/* Qualifying an operand which is a floating-point register, a SIMD
vector element or a SIMD vector element list; indicating operand data
size or the size of each SIMD vector element in the case of a SIMD
vector element list.
These qualifiers are also used to qualify an address operand to
indicate the size of data element a load/store instruction is
accessing.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_S_B,
AARCH64_OPND_QLF_S_H,
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
register list; indicating register shape.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_16B,
AARCH64_OPND_QLF_V_2H,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_8H,
AARCH64_OPND_QLF_V_2S,
AARCH64_OPND_QLF_V_4S,
AARCH64_OPND_QLF_V_1D,
AARCH64_OPND_QLF_V_2D,
AARCH64_OPND_QLF_V_1Q,
/* Constraint on value. */
AARCH64_OPND_QLF_imm_0_7,
AARCH64_OPND_QLF_imm_0_15,
AARCH64_OPND_QLF_imm_0_31,
AARCH64_OPND_QLF_imm_0_63,
AARCH64_OPND_QLF_imm_1_32,
AARCH64_OPND_QLF_imm_1_64,
/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
or shift-ones. */
AARCH64_OPND_QLF_LSL,
AARCH64_OPND_QLF_MSL,
/* Special qualifier helping retrieve qualifier information during the
decoding time (currently not in use). */
AARCH64_OPND_QLF_RETRIEVE,
};
/* Instruction class. */
enum aarch64_insn_class
{
addsub_carry,
addsub_ext,
addsub_imm,
addsub_shift,
asimdall,
asimddiff,
asimdelem,
asimdext,
asimdimm,
asimdins,
asimdmisc,
asimdperm,
asimdsame,
asimdshf,
asimdtbl,
asisddiff,
asisdelem,
asisdlse,
asisdlsep,
asisdlso,
asisdlsop,
asisdmisc,
asisdone,
asisdpair,
asisdsame,
asisdshf,
bitfield,
branch_imm,
branch_reg,
compbranch,
condbranch,
condcmp_imm,
condcmp_reg,
condsel,
cryptoaes,
cryptosha2,
cryptosha3,
dp_1src,
dp_2src,
dp_3src,
exception,
extract,
float2fix,
float2int,
floatccmp,
floatcmp,
floatdp1,
floatdp2,
floatdp3,
floatimm,
floatsel,
ldst_immpost,
ldst_immpre,
ldst_imm9, /* immpost or immpre */
ldst_pos,
ldst_regoff,
ldst_unpriv,
ldst_unscaled,
ldstexcl,
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
loadlit,
log_imm,
log_shift,
lse_atomic,
movewide,
pcreladdr,
ic_system,
testbranch,
};
/* Opcode enumerators. */
enum aarch64_op
{
OP_NIL,
OP_STRB_POS,
OP_LDRB_POS,
OP_LDRSB_POS,
OP_STRH_POS,
OP_LDRH_POS,
OP_LDRSH_POS,
OP_STR_POS,
OP_LDR_POS,
OP_STRF_POS,
OP_LDRF_POS,
OP_LDRSW_POS,
OP_PRFM_POS,
OP_STURB,
OP_LDURB,
OP_LDURSB,
OP_STURH,
OP_LDURH,
OP_LDURSH,
OP_STUR,
OP_LDUR,
OP_STURV,
OP_LDURV,
OP_LDURSW,
OP_PRFUM,
OP_LDR_LIT,
OP_LDRV_LIT,
OP_LDRSW_LIT,
OP_PRFM_LIT,
OP_ADD,
OP_B,
OP_BL,
OP_MOVN,
OP_MOVZ,
OP_MOVK,
OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
OP_MOV_V, /* MOV alias for moving vector register. */
OP_ASR_IMM,
OP_LSR_IMM,
OP_LSL_IMM,
OP_BIC,
OP_UBFX,
OP_BFXIL,
OP_SBFX,
OP_SBFIZ,
OP_BFI,
OP_BFC, /* ARMv8.2. */
OP_UBFIZ,
OP_UXTB,
OP_UXTH,
OP_UXTW,
OP_CINC,
OP_CINV,
OP_CNEG,
OP_CSET,
OP_CSETM,
OP_FCVT,
OP_FCVTN,
OP_FCVTN2,
OP_FCVTL,
OP_FCVTL2,
OP_FCVTXN_S, /* Scalar version. */
OP_ROR_IMM,
OP_SXTL,
OP_SXTL2,
OP_UXTL,
OP_UXTL2,
OP_TOTAL_NUM, /* Pseudo. */
};
/* Maximum number of operands an instruction can have. */
#define AARCH64_MAX_OPND_NUM 6
/* Maximum number of qualifier sequences an instruction can have. */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size. */
typedef unsigned char aarch64_opnd_qualifier_t;
/* Operand qualifier sequence typedef. */
typedef aarch64_opnd_qualifier_t \
aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
/* FIXME: improve the efficiency. */
static inline bfd_boolean
empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
{
int i;
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
return FALSE;
return TRUE;
}
/* This structure holds information for a particular opcode. */
struct aarch64_opcode
{
/* The name of the mnemonic. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
aarch64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
aarch64_insn mask;
/* Instruction class. */
enum aarch64_insn_class iclass;
/* Enumerator identifier. */
enum aarch64_op op;
/* Which architecture variant provides this instruction. */
const aarch64_feature_set *avariant;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
/* A list of operand qualifier code sequence. Each operand qualifier
code qualifies the corresponding operand code. Each operand
qualifier sequence specifies a valid opcode variant and related
constraint on operands. */
aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
/* Flags providing information about this instruction */
uint32_t flags;
/* If non-NULL, a function to verify that a given instruction is valid. */
bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
};
typedef struct aarch64_opcode aarch64_opcode;
/* Table describing all the AArch64 opcodes. */
extern aarch64_opcode aarch64_opcode_table[];
/* Opcode flags. */
#define F_ALIAS (1 << 0)
#define F_HAS_ALIAS (1 << 1)
/* Disassembly preference priority 1-3 (the larger the higher). If nothing
is specified, it is the priority 0 by default, i.e. the lowest priority. */
#define F_P1 (1 << 2)
#define F_P2 (2 << 2)
#define F_P3 (3 << 2)
/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
#define F_COND (1 << 4)
/* Instruction has the field of 'sf'. */
#define F_SF (1 << 5)
/* Instruction has the field of 'size:Q'. */
#define F_SIZEQ (1 << 6)
/* Floating-point instruction has the field of 'type'. */
#define F_FPTYPE (1 << 7)
/* AdvSIMD scalar instruction has the field of 'size'. */
#define F_SSIZE (1 << 8)
/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
#define F_T (1 << 9)
/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
#define F_GPRSIZE_IN_Q (1 << 10)
/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
#define F_LDS_SIZE (1 << 11)
/* Optional operand; assume maximum of 1 operand can be optional. */
#define F_OPD0_OPT (1 << 12)
#define F_OPD1_OPT (2 << 12)
#define F_OPD2_OPT (3 << 12)
#define F_OPD3_OPT (4 << 12)
#define F_OPD4_OPT (5 << 12)
/* Default value for the optional operand when omitted from the assembly. */
#define F_DEFAULT(X) (((X) & 0x1f) << 15)
/* Instruction that is an alias of another instruction needs to be
encoded/decoded by converting it to/from the real form, followed by
the encoding/decoding according to the rules of the real opcode.
This compares to the direct coding using the alias's information.
N.B. this flag requires F_ALIAS to be used together. */
#define F_CONV (1 << 20)
/* Use together with F_ALIAS to indicate an alias opcode is a programmer
friendly pseudo instruction available only in the assembly code (thus will
not show up in the disassembly). */
#define F_PSEUDO (1 << 21)
/* Instruction has miscellaneous encoding/decoding rules. */
#define F_MISC (1 << 22)
/* Instruction has the field of 'N'; used in conjunction with F_SF. */
#define F_N (1 << 23)
/* Opcode dependent field. */
#define F_OD(X) (((X) & 0x7) << 24)
/* Instruction has the field of 'sz'. */
#define F_LSE_SZ (1 << 27)
/* Next bit is 28. */
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
}
static inline bfd_boolean
opcode_has_alias (const aarch64_opcode *opcode)
{
return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
}
/* Priority for disassembling preference. */
static inline int
opcode_priority (const aarch64_opcode *opcode)
{
return (opcode->flags >> 2) & 0x3;
}
static inline bfd_boolean
pseudo_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
}
static inline bfd_boolean
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
return (((opcode->flags >> 12) & 0x7) == idx + 1)
? TRUE : FALSE;
}
static inline aarch64_insn
get_optional_operand_default_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 15) & 0x1f;
}
static inline unsigned int
get_opcode_dependent_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 24) & 0x7;
}
static inline bfd_boolean
opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
: FALSE;
}
struct aarch64_name_value_pair
{
const char * name;
aarch64_insn value;
};
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options [];
typedef struct
{
const char * name;
aarch64_insn value;
uint32_t flags;
} aarch64_sys_reg;
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
typedef struct
{
const char *name;
uint32_t value;
uint32_t flags ;
} aarch64_sys_ins_reg;
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_ins_reg *);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
/* Shift/extending operator kinds.
N.B. order is important; keep aarch64_operand_modifiers synced. */
enum aarch64_modifier_kind
{
AARCH64_MOD_NONE,
AARCH64_MOD_MSL,
AARCH64_MOD_ROR,
AARCH64_MOD_ASR,
AARCH64_MOD_LSR,
AARCH64_MOD_LSL,
AARCH64_MOD_UXTB,
AARCH64_MOD_UXTH,
AARCH64_MOD_UXTW,
AARCH64_MOD_UXTX,
AARCH64_MOD_SXTB,
AARCH64_MOD_SXTH,
AARCH64_MOD_SXTW,
AARCH64_MOD_SXTX,
};
bfd_boolean
aarch64_extend_operator_p (enum aarch64_modifier_kind);
enum aarch64_modifier_kind
aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
/* Condition. */
typedef struct
{
/* A list of names with the first one as the disassembly preference;
terminated by NULL if fewer than 3. */
const char *names[3];
aarch64_insn value;
} aarch64_cond;
extern const aarch64_cond aarch64_conds[16];
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
/* Structure representing an operand. */
struct aarch64_opnd_info
{
enum aarch64_opnd type;
aarch64_opnd_qualifier_t qualifier;
int idx;
union
{
struct
{
unsigned regno;
} reg;
struct
{
unsigned int regno;
int64_t index;
} reglane;
/* e.g. LVn. */
struct
{
unsigned first_regno : 5;
unsigned num_regs : 3;
/* 1 if it is a list of reg element. */
unsigned has_index : 1;
/* Lane index; valid only when has_index is 1. */
int64_t index;
} reglist;
/* e.g. immediate or pc relative address offset. */
struct
{
int64_t value;
unsigned is_fp : 1;
} imm;
/* e.g. address in STR (register offset). */
struct
{
unsigned base_regno;
struct
{
union
{
int imm;
unsigned regno;
};
unsigned is_reg;
} offset;
unsigned pcrel : 1; /* PC-relative. */
unsigned writeback : 1;
unsigned preind : 1; /* Pre-indexed. */
unsigned postind : 1; /* Post-indexed. */
} addr;
const aarch64_cond *cond;
/* The encoding of the system register. */
aarch64_insn sysreg;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
const struct aarch64_name_value_pair *barrier;
const struct aarch64_name_value_pair *hint_option;
const struct aarch64_name_value_pair *prfop;
};
/* Operand shifter; in use when the operand is a register offset address,
add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
struct
{
enum aarch64_modifier_kind kind;
int amount;
unsigned operator_present: 1; /* Only valid during encoding. */
/* Value of the 'S' field in ld/st reg offset; used only in decoding. */
unsigned amount_present: 1;
} shifter;
unsigned skip:1; /* Operand is not completed if there is a fixup needed
to be done on it. In some (but not all) of these
cases, we need to tell libopcodes to skip the
constraint checking and the encoding for this
operand, so that the libopcodes can pick up the
right opcode before the operand is fixed-up. This
flag should only be used during the
assembling/encoding. */
unsigned present:1; /* Whether this operand is present in the assembly
line; not used during the disassembly. */
};
typedef struct aarch64_opnd_info aarch64_opnd_info;
/* Structure representing an instruction.
It is used during both the assembling and disassembling. The assembler
fills an aarch64_inst after a successful parsing and then passes it to the
encoding routine to do the encoding. During the disassembling, the
disassembler calls the decoding routine to decode a binary instruction; on a
successful return, such a structure will be filled with information of the
instruction; then the disassembler uses the information to print out the
instruction. */
struct aarch64_inst
{
/* The value of the binary instruction. */
aarch64_insn value;
/* Corresponding opcode entry. */
const aarch64_opcode *opcode;
/* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
const aarch64_cond *cond;
/* Operands information. */
aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
};
typedef struct aarch64_inst aarch64_inst;
/* Diagnosis related declaration and interface. */
/* Operand error kind enumerators.
AARCH64_OPDE_RECOVERABLE
Less severe error found during the parsing, very possibly because that
GAS has picked up a wrong instruction template for the parsing.
AARCH64_OPDE_SYNTAX_ERROR
General syntax error; it can be either a user error, or simply because
that GAS is trying a wrong instruction template.
AARCH64_OPDE_FATAL_SYNTAX_ERROR
Definitely a user syntax error.
AARCH64_OPDE_INVALID_VARIANT
No syntax error, but the operands are not a valid combination, e.g.
FMOV D0,S0
AARCH64_OPDE_OUT_OF_RANGE
Error about some immediate value out of a valid range.
AARCH64_OPDE_UNALIGNED
Error about some immediate value not properly aligned (i.e. not being a
multiple times of a certain value).
AARCH64_OPDE_REG_LIST
Error about the register list operand having unexpected number of
registers.
AARCH64_OPDE_OTHER_ERROR
Error of the highest severity and used for any severe issue that does not
fall into any of the above categories.
The enumerators are only interesting to GAS. They are declared here (in
libopcodes) because that some errors are detected (and then notified to GAS)
by libopcodes (rather than by GAS solely).
The first three errors are only deteced by GAS while the
AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
only libopcodes has the information about the valid variants of each
instruction.
The enumerators have an increasing severity. This is helpful when there are
multiple instruction templates available for a given mnemonic name (e.g.
FMOV); this mechanism will help choose the most suitable template from which
the generated diagnostics can most closely describe the issues, if any. */
enum aarch64_operand_error_kind
{
AARCH64_OPDE_NIL,
AARCH64_OPDE_RECOVERABLE,
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
AARCH64_OPDE_REG_LIST,
AARCH64_OPDE_OTHER_ERROR
};
/* N.B. GAS assumes that this structure work well with shallow copy. */
struct aarch64_operand_error
{
enum aarch64_operand_error_kind kind;
int index;
const char *error;
int data[3]; /* Some data for extra information. */
};
typedef struct aarch64_operand_error aarch64_operand_error;
/* Encoding entrypoint. */
extern int
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
aarch64_insn *, aarch64_opnd_qualifier_t *,
aarch64_operand_error *);
extern const aarch64_opcode *
aarch64_replace_opcode (struct aarch64_inst *,
const aarch64_opcode *);
/* Given the opcode enumerator OP, return the pointer to the corresponding
opcode entry. */
extern const aarch64_opcode *
aarch64_get_opcode (enum aarch64_op);
/* Generate the string representation of an operand. */
extern void
aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
const aarch64_opnd_info *, int, int *, bfd_vma *);
/* Miscellaneous interface. */
extern int
aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
extern aarch64_opnd_qualifier_t
aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
const aarch64_opnd_qualifier_t, int);
extern int
aarch64_num_of_operands (const aarch64_opcode *);
extern int
aarch64_stack_pointer_p (const aarch64_opnd_info *);
extern int
aarch64_zero_register_p (const aarch64_opnd_info *);
extern int
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
extern unsigned char
aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
extern enum aarch64_operand_class
aarch64_get_operand_class (enum aarch64_opnd);
extern const char *
aarch64_get_operand_name (enum aarch64_opnd);
extern const char *
aarch64_get_operand_desc (enum aarch64_opnd);
#ifdef DEBUG_AARCH64
extern int debug_dump;
extern void
aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
#define DEBUG_TRACE(M, ...) \
{ \
if (debug_dump) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#define DEBUG_TRACE_IF(C, M, ...) \
{ \
if (debug_dump && (C)) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#else /* !DEBUG_AARCH64 */
#define DEBUG_TRACE(M, ...) ;
#define DEBUG_TRACE_IF(C, M, ...) ;
#endif /* DEBUG_AARCH64 */
#ifdef __cplusplus
}
#endif
#endif /* OPCODE_AARCH64_H */
| {
"language": "Assembly"
} |
// Copyright 2013 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
define i1 @test1(i8 %A) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: ret i1 true
;
%B = sitofp i8 %A to double
%C = fcmp ult double %B, 128.0
ret i1 %C
}
define i1 @test2(i8 %A) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: ret i1 true
;
%B = sitofp i8 %A to double
%C = fcmp ugt double %B, -128.1
ret i1 %C
}
define i1 @test3(i8 %A) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: ret i1 true
;
%B = sitofp i8 %A to double
%C = fcmp ule double %B, 127.0
ret i1 %C
}
define i1 @test4(i8 %A) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[A:%.*]], 127
; CHECK-NEXT: ret i1 [[C]]
;
%B = sitofp i8 %A to double
%C = fcmp ult double %B, 127.0
ret i1 %C
}
define i32 @test5(i32 %A) {
; CHECK-LABEL: @test5(
; CHECK-NEXT: ret i32 [[A:%.*]]
;
%B = sitofp i32 %A to double
%C = fptosi double %B to i32
%D = uitofp i32 %C to double
%E = fptoui double %D to i32
ret i32 %E
}
define i32 @test6(i32 %A) {
; CHECK-LABEL: @test6(
; CHECK-NEXT: [[ADDCONV:%.*]] = and i32 [[A:%.*]], 39
; CHECK-NEXT: ret i32 [[ADDCONV]]
;
%B = and i32 %A, 7
%C = and i32 %A, 32
%D = sitofp i32 %B to double
%E = sitofp i32 %C to double
%F = fadd double %D, %E
%G = fptosi double %F to i32
ret i32 %G
}
define i32 @test7(i32 %A) {
; CHECK-LABEL: @test7(
; CHECK-NEXT: ret i32 [[A:%.*]]
;
%B = sitofp i32 %A to double
%C = fptoui double %B to i32
ret i32 %C
}
define i32 @test8(i32 %A) {
; CHECK-LABEL: @test8(
; CHECK-NEXT: ret i32 [[A:%.*]]
;
%B = uitofp i32 %A to double
%C = fptosi double %B to i32
ret i32 %C
}
define i32 @test9(i8 %A) {
; CHECK-LABEL: @test9(
; CHECK-NEXT: [[C:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = sitofp i8 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
define i32 @test10(i8 %A) {
; CHECK-LABEL: @test10(
; CHECK-NEXT: [[C:%.*]] = sext i8 [[A:%.*]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = sitofp i8 %A to float
%C = fptosi float %B to i32
ret i32 %C
}
; If the input value is outside of the range of the output cast, it's
; undefined behavior, so we can assume it fits.
define i8 @test11(i32 %A) {
; CHECK-LABEL: @test11(
; CHECK-NEXT: [[C:%.*]] = trunc i32 [[A:%.*]] to i8
; CHECK-NEXT: ret i8 [[C]]
;
%B = sitofp i32 %A to float
%C = fptosi float %B to i8
ret i8 %C
}
; If the input value is negative, it'll be outside the range of the
; output cast, and thus undefined behavior.
define i32 @test12(i8 %A) {
; CHECK-LABEL: @test12(
; CHECK-NEXT: [[C:%.*]] = zext i8 [[A:%.*]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = sitofp i8 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
; This can't fold because the 25-bit input doesn't fit in the mantissa.
define i32 @test13(i25 %A) {
; CHECK-LABEL: @test13(
; CHECK-NEXT: [[B:%.*]] = uitofp i25 [[A:%.*]] to float
; CHECK-NEXT: [[C:%.*]] = fptoui float [[B]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = uitofp i25 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
; But this one can.
define i32 @test14(i24 %A) {
; CHECK-LABEL: @test14(
; CHECK-NEXT: [[C:%.*]] = zext i24 [[A:%.*]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = uitofp i24 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
; And this one can too.
define i24 @test15(i32 %A) {
; CHECK-LABEL: @test15(
; CHECK-NEXT: [[C:%.*]] = trunc i32 [[A:%.*]] to i24
; CHECK-NEXT: ret i24 [[C]]
;
%B = uitofp i32 %A to float
%C = fptoui float %B to i24
ret i24 %C
}
; This can fold because the 25-bit input is signed and we discard the sign bit.
define i32 @test16(i25 %A) {
; CHECK-LABEL: @test16(
; CHECK-NEXT: [[C:%.*]] = zext i25 [[A:%.*]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = sitofp i25 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
; This can't fold because the 26-bit input won't fit the mantissa
; even after discarding the signed bit.
define i32 @test17(i26 %A) {
; CHECK-LABEL: @test17(
; CHECK-NEXT: [[B:%.*]] = sitofp i26 [[A:%.*]] to float
; CHECK-NEXT: [[C:%.*]] = fptoui float [[B]] to i32
; CHECK-NEXT: ret i32 [[C]]
;
%B = sitofp i26 %A to float
%C = fptoui float %B to i32
ret i32 %C
}
; This can fold because the 54-bit output is signed and we discard the sign bit.
define i54 @test18(i64 %A) {
; CHECK-LABEL: @test18(
; CHECK-NEXT: [[C:%.*]] = trunc i64 [[A:%.*]] to i54
; CHECK-NEXT: ret i54 [[C]]
;
%B = sitofp i64 %A to double
%C = fptosi double %B to i54
ret i54 %C
}
; This can't fold because the 55-bit output won't fit the mantissa
; even after discarding the sign bit.
define i55 @test19(i64 %A) {
; CHECK-LABEL: @test19(
; CHECK-NEXT: [[B:%.*]] = sitofp i64 [[A:%.*]] to double
; CHECK-NEXT: [[C:%.*]] = fptosi double [[B]] to i55
; CHECK-NEXT: ret i55 [[C]]
;
%B = sitofp i64 %A to double
%C = fptosi double %B to i55
ret i55 %C
}
| {
"language": "Assembly"
} |
/*
***************************************************************************
* Ralink Tech Inc.
* 4F, No. 2 Technology 5th Rd.
* Science-based Industrial Park
* Hsin-chu, Taiwan, R.O.C.
*
* (c) Copyright 2002-2009, Ralink Technology, Inc.
*
* All rights reserved. Ralink's source code is an unpublished work and the
* use of a copyright notice does not imply otherwise. This source code
* contains confidential trade secret material of Ralink Tech. Any attemp
* or participation in deciphering, decoding, reverse engineering or in any
* way altering the source code is stricitly prohibited, unless the prior
* written consent of Ralink Technology, Inc. is obtained.
***************************************************************************
Module Name:
misc.h
Abstract:
Handling Misc Problem
Revision History:
Who When What
-------- ---------- ----------------------------------------------
Sean Wang 2009-08-12 Create
John Li 2009-12-23 Modified
*/
| {
"language": "Assembly"
} |
dnl AMD64 mpn_gcd_22. Assumes useless bsf, useless shrd, no tzcnt, no shlx.
dnl We actually use tzcnt here, when table cannot count bits, as tzcnt always
dnl works for our use, and helps a lot for certain CPUs.
dnl Copyright 2019 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/bit
C AMD K8,K9 8.9
C AMD K10 8.8
C AMD bd1 9.7
C AMD bd2 7.8
C AMD bd3 ?
C AMD bd4 7.4
C AMD bt1 9.2
C AMD bt2 9.1
C AMD zn1 7.5
C AMD zn2 7.5
C Intel P4 ?
C Intel CNR 10.5
C Intel PNR 10.5
C Intel NHM 9.7
C Intel WSM 9.7
C Intel SBR 10.7
C Intel IBR ?
C Intel HWL 9.5
C Intel BWL 8.7
C Intel SKL 8.6
C Intel atom 18.9
C Intel SLM 14.0
C Intel GLM 9.8
C Intel GLM+ 8.8
C VIA nano ?
C ctz_table[n] is the number of trailing zeros on n, or MAXSHIFT if n==0.
deflit(MAXSHIFT, 8)
deflit(MASK, eval((m4_lshift(1,MAXSHIFT))-1))
DEF_OBJECT(ctz_table,64)
.byte MAXSHIFT
forloop(i,1,MASK,
` .byte m4_count_trailing_zeros(i)
')
END_OBJECT(ctz_table)
define(`u1', `%rdi')
define(`u0', `%rsi')
define(`v1', `%rdx')
define(`v0_param', `%rcx')
define(`v0', `%rax')
define(`cnt', `%rcx')
define(`s0', `%r8')
define(`s1', `%r9')
define(`t0', `%rcx')
define(`t1', `%r11')
dnl ABI_SUPPORT(DOS64) C returns mp_double_limb_t in memory
ABI_SUPPORT(STD64)
ASM_START()
TEXT
ALIGN(64)
PROLOGUE(mpn_gcd_22)
FUNC_ENTRY(4)
mov v0_param, v0
LEA( ctz_table, %r10)
ALIGN(16)
L(top): mov v0, t0
sub u0, t0
jz L(lowz) C jump when low limb result = 0
mov v1, t1
sbb u1, t1
mov u0, s0
mov u1, s1
sub v0, u0
sbb v1, u1
L(bck): cmovc t0, u0 C u = |u - v|
cmovc t1, u1 C u = |u - v|
cmovc s0, v0 C v = min(u,v)
cmovc s1, v1 C v = min(u,v)
and $MASK, R32(t0)
movzbl (%r10,t0), R32(cnt)
jz L(count_better)
C Rightshift (u1,,u0) into (u1,,u0)
L(shr): shr R8(cnt), u0
mov u1, t1
shr R8(cnt), u1
neg cnt
shl R8(cnt), t1
or t1, u0
test v1, v1
jnz L(top)
test u1, u1
jnz L(top)
L(gcd_11):
mov v0, %rdi
C mov u0, %rsi
TCALL( mpn_gcd_11)
L(count_better):
rep;bsf u0, cnt C tzcnt!
jmp L(shr)
L(lowz):C We come here when v0 - u0 = 0
C 1. If v1 - u1 = 0, then gcd is u = v.
C 2. Else compute gcd_21({v1,v0}, |u1-v1|)
mov v1, t0
sub u1, t0
je L(end)
xor t1, t1
mov u0, s0
mov u1, s1
mov u1, u0
xor u1, u1
sub v1, u0
jmp L(bck)
L(end): C mov v0, %rax
C mov v1, %rdx
FUNC_EXIT()
ret
EPILOGUE()
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple i386-unknown-unknown -emit-pth -o %t %S/pth.h
// RUN: %clang_cc1 -triple i386-unknown-unknown -include-pth %t -fsyntax-only %s 2>&1 | FileCheck %s
#error This is the only diagnostic
// CHECK: This is the only diagnostic
// CHECK: 1 error generated. | {
"language": "Assembly"
} |
Route19_Script:
call EnableAutoTextBoxDrawing
ld hl, Route19TrainerHeader0
ld de, Route19_ScriptPointers
ld a, [wRoute19CurScript]
call ExecuteCurMapScriptInTable
ld [wRoute19CurScript], a
ret
Route19_ScriptPointers:
dw CheckFightingMapTrainers
dw DisplayEnemyTrainerTextAndStartBattle
dw EndTrainerBattle
Route19_TextPointers:
dw Route19Text1
dw Route19Text2
dw Route19Text3
dw Route19Text4
dw Route19Text5
dw Route19Text6
dw Route19Text7
dw Route19Text8
dw Route19Text9
dw Route19Text10
dw Route19Text11
Route19TrainerHeader0:
trainer EVENT_BEAT_ROUTE_19_TRAINER_0, 4, Route19BattleText1, Route19EndBattleText1, Route19AfterBattleText1
Route19TrainerHeader1:
trainer EVENT_BEAT_ROUTE_19_TRAINER_1, 3, Route19BattleText2, Route19EndBattleText2, Route19AfterBattleText2
Route19TrainerHeader2:
trainer EVENT_BEAT_ROUTE_19_TRAINER_2, 3, Route19BattleText3, Route19EndBattleText3, Route19AfterBattleText3
Route19TrainerHeader3:
trainer EVENT_BEAT_ROUTE_19_TRAINER_3, 4, Route19BattleText4, Route19EndBattleText4, Route19AfterBattleText4
Route19TrainerHeader4:
trainer EVENT_BEAT_ROUTE_19_TRAINER_4, 4, Route19BattleText5, Route19EndBattleText5, Route19AfterBattleText5
Route19TrainerHeader5:
trainer EVENT_BEAT_ROUTE_19_TRAINER_5, 4, Route19BattleText6, Route19EndBattleText6, Route19AfterBattleText6
Route19TrainerHeader6:
trainer EVENT_BEAT_ROUTE_19_TRAINER_6, 3, Route19BattleText7, Route19EndBattleText7, Route19AfterBattleText7
Route19TrainerHeader7:
trainer EVENT_BEAT_ROUTE_19_TRAINER_7, 1, 4, Route19BattleText8, Route19EndBattleText8, Route19AfterBattleText8
Route19TrainerHeader8:
trainer EVENT_BEAT_ROUTE_19_TRAINER_8, 1, 4, Route19BattleText9, Route19EndBattleText9, Route19AfterBattleText9
Route19TrainerHeader9:
trainer EVENT_BEAT_ROUTE_19_TRAINER_9, 1, 4, Route19BattleText10, Route19EndBattleText10, Route19AfterBattleText10
db -1 ; end
Route19Text1:
text_asm
ld hl, Route19TrainerHeader0
call TalkToTrainer
jp TextScriptEnd
Route19Text2:
text_asm
ld hl, Route19TrainerHeader1
call TalkToTrainer
jp TextScriptEnd
Route19Text3:
text_asm
ld hl, Route19TrainerHeader2
call TalkToTrainer
jp TextScriptEnd
Route19Text4:
text_asm
ld hl, Route19TrainerHeader3
call TalkToTrainer
jp TextScriptEnd
Route19Text5:
text_asm
ld hl, Route19TrainerHeader4
call TalkToTrainer
jp TextScriptEnd
Route19Text6:
text_asm
ld hl, Route19TrainerHeader5
call TalkToTrainer
jp TextScriptEnd
Route19Text7:
text_asm
ld hl, Route19TrainerHeader6
call TalkToTrainer
jp TextScriptEnd
Route19Text8:
text_asm
ld hl, Route19TrainerHeader7
call TalkToTrainer
jp TextScriptEnd
Route19Text9:
text_asm
ld hl, Route19TrainerHeader8
call TalkToTrainer
jp TextScriptEnd
Route19Text10:
text_asm
ld hl, Route19TrainerHeader9
call TalkToTrainer
jp TextScriptEnd
Route19BattleText1:
text_far _Route19BattleText1
text_end
Route19EndBattleText1:
text_far _Route19EndBattleText1
text_end
Route19AfterBattleText1:
text_far _Route19AfterBattleText1
text_end
Route19BattleText2:
text_far _Route19BattleText2
text_end
Route19EndBattleText2:
text_far _Route19EndBattleText2
text_end
Route19AfterBattleText2:
text_far _Route19AfterBattleText2
text_end
Route19BattleText3:
text_far _Route19BattleText3
text_end
Route19EndBattleText3:
text_far _Route19EndBattleText3
text_end
Route19AfterBattleText3:
text_far _Route19AfterBattleText3
text_end
Route19BattleText4:
text_far _Route19BattleText4
text_end
Route19EndBattleText4:
text_far _Route19EndBattleText4
text_end
Route19AfterBattleText4:
text_far _Route19AfterBattleText4
text_end
Route19BattleText5:
text_far _Route19BattleText5
text_end
Route19EndBattleText5:
text_far _Route19EndBattleText5
text_end
Route19AfterBattleText5:
text_far _Route19AfterBattleText5
text_end
Route19BattleText6:
text_far _Route19BattleText6
text_end
Route19EndBattleText6:
text_far _Route19EndBattleText6
text_end
Route19AfterBattleText6:
text_far _Route19AfterBattleText6
text_end
Route19BattleText7:
text_far _Route19BattleText7
text_end
Route19EndBattleText7:
text_far _Route19EndBattleText7
text_end
Route19AfterBattleText7:
text_far _Route19AfterBattleText7
text_end
Route19BattleText8:
text_far _Route19BattleText8
text_end
Route19EndBattleText8:
text_far _Route19EndBattleText8
text_end
Route19AfterBattleText8:
text_far _Route19AfterBattleText8
text_end
Route19BattleText9:
text_far _Route19BattleText9
text_end
Route19EndBattleText9:
text_far _Route19EndBattleText9
text_end
Route19AfterBattleText9:
text_far _Route19AfterBattleText9
text_end
Route19BattleText10:
text_far _Route19BattleText10
text_end
Route19EndBattleText10:
text_far _Route19EndBattleText10
text_end
Route19AfterBattleText10:
text_far _Route19AfterBattleText10
text_end
Route19Text11:
text_far _Route19Text11
text_end
| {
"language": "Assembly"
} |
/*
* Copyright 2014 Martin Peres <martin.peres@free.fr>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the folloing conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
/******************************************************************************
* arith data segment
*****************************************************************************/
#ifdef INCLUDE_PROC
#endif
#ifdef INCLUDE_DATA
#endif
/******************************************************************************
* arith code segment
*****************************************************************************/
#ifdef INCLUDE_CODE
// does a 32x32 -> 64 multiplication
//
// A * B = A_lo * B_lo
// + ( A_hi * B_lo ) << 16
// + ( A_lo * B_hi ) << 16
// + ( A_hi * B_hi ) << 32
//
// $r15 - current
// $r14 - A
// $r13 - B
// $r12 - mul_lo (return)
// $r11 - mul_hi (return)
// $r0 - zero
mulu32_32_64:
push $r1 // A_hi
push $r2 // B_hi
push $r3 // tmp0
push $r4 // tmp1
shr b32 $r1 $r14 16
shr b32 $r2 $r13 16
clear b32 $r12
clear b32 $r11
// A_lo * B_lo
mulu $r12 $r14 $r13
// ( A_hi * B_lo ) << 16
mulu $r3 $r1 $r13 // tmp0 = A_hi * B_lo
mov b32 $r4 $r3
and $r3 0xffff // tmp0 = tmp0_lo
shl b32 $r3 16
shr b32 $r4 16 // tmp1 = tmp0_hi
add b32 $r12 $r3
adc b32 $r11 $r4
// ( A_lo * B_hi ) << 16
mulu $r3 $r14 $r2 // tmp0 = A_lo * B_hi
mov b32 $r4 $r3
and $r3 0xffff // tmp0 = tmp0_lo
shl b32 $r3 16
shr b32 $r4 16 // tmp1 = tmp0_hi
add b32 $r12 $r3
adc b32 $r11 $r4
// ( A_hi * B_hi ) << 32
mulu $r3 $r1 $r2 // tmp0 = A_hi * B_hi
add b32 $r11 $r3
pop $r4
pop $r3
pop $r2
pop $r1
ret
#endif
| {
"language": "Assembly"
} |
#include <asm/reg.h>
#include <asm/ppc_asm.h>
#include <asm/processor.h>
.text
_GLOBAL(mpc52xx_deep_sleep)
mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
/* enable interrupts */
mfmsr r7
ori r7, r7, 0x8000 /* EE */
mtmsr r7
sync; isync;
li r10, 0 /* flag that irq handler sets */
/* enable tmr7 (or any other) interrupt */
lwz r8, 0x14(r6) /* intr->main_mask */
ori r8, r8, 0x1
xori r8, r8, 0x1
stw r8, 0x14(r6)
sync
/* emulate tmr7 interrupt */
li r8, 0x1
stw r8, 0x40(r6) /* intr->main_emulate */
sync
/* wait for it to happen */
1:
cmpi cr0, r10, 1
bne cr0, 1b
/* lock icache */
mfspr r10, SPRN_HID0
ori r10, r10, 0x2000
sync; isync;
mtspr SPRN_HID0, r10
sync; isync;
mflr r9 /* save LR */
/* jump to sram */
mtlr r3
blrl
mtlr r9 /* restore LR */
/* unlock icache */
mfspr r10, SPRN_HID0
ori r10, r10, 0x2000
xori r10, r10, 0x2000
sync; isync;
mtspr SPRN_HID0, r10
sync; isync;
/* return to C code */
blr
_GLOBAL(mpc52xx_ds_sram)
mpc52xx_ds_sram:
/* put SDRAM into self-refresh */
lwz r8, 0x4(r4) /* sdram->ctrl */
oris r8, r8, 0x8000 /* mode_en */
stw r8, 0x4(r4)
sync
ori r8, r8, 0x0002 /* soft_pre */
stw r8, 0x4(r4)
sync
xori r8, r8, 0x0002
xoris r8, r8, 0x8000 /* !mode_en */
stw r8, 0x4(r4)
sync
oris r8, r8, 0x5000
xoris r8, r8, 0x4000 /* ref_en !cke */
stw r8, 0x4(r4)
sync
/* disable SDRAM clock */
lwz r8, 0x14(r5) /* cdm->clkenable */
ori r8, r8, 0x0008
xori r8, r8, 0x0008
stw r8, 0x14(r5)
sync
/* put mpc5200 to sleep */
mfmsr r10
oris r10, r10, 0x0004 /* POW = 1 */
sync; isync;
mtmsr r10
sync; isync;
/* enable clock */
lwz r8, 0x14(r5)
ori r8, r8, 0x0008
stw r8, 0x14(r5)
sync
/* get ram out of self-refresh */
lwz r8, 0x4(r4)
oris r8, r8, 0x5000 /* cke ref_en */
stw r8, 0x4(r4)
sync
blr
_GLOBAL(mpc52xx_ds_sram_size)
mpc52xx_ds_sram_size:
.long $-mpc52xx_ds_sram
/* ### interrupt handler for wakeup from deep-sleep ### */
_GLOBAL(mpc52xx_ds_cached)
mpc52xx_ds_cached:
mtspr SPRN_SPRG0, r7
mtspr SPRN_SPRG1, r8
/* disable emulated interrupt */
mfspr r7, 311 /* MBAR */
addi r7, r7, 0x540 /* intr->main_emul */
li r8, 0
stw r8, 0(r7)
sync
dcbf 0, r7
/* acknowledge wakeup, so CCS releases power pown */
mfspr r7, 311 /* MBAR */
addi r7, r7, 0x524 /* intr->enc_status */
lwz r8, 0(r7)
ori r8, r8, 0x0400
stw r8, 0(r7)
sync
dcbf 0, r7
/* flag - we handled the interrupt */
li r10, 1
mfspr r8, SPRN_SPRG1
mfspr r7, SPRN_SPRG0
rfi
_GLOBAL(mpc52xx_ds_cached_size)
mpc52xx_ds_cached_size:
.long $-mpc52xx_ds_cached
| {
"language": "Assembly"
} |
/*
* LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* Some parts of this code was based on the OpenWrt specific lzma-loader
* for the BCM47xx and ADM5120 based boards:
* Copyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)
* Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <asm/asm.h>
#include <asm/regdef.h>
#include "cp0regdef.h"
#include "cacheops.h"
#include "config.h"
#define KSEG0 0x80000000
.macro ehb
sll zero, 3
.endm
.text
LEAF(startup)
.set noreorder
.set mips32
mtc0 zero, CP0_WATCHLO # clear watch registers
mtc0 zero, CP0_WATCHHI
mtc0 zero, CP0_CAUSE # clear before writing status register
mfc0 t0, CP0_STATUS
li t1, 0x1000001f
or t0, t1
xori t0, 0x1f
mtc0 t0, CP0_STATUS
ehb
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE
ehb
la t0, __reloc_label # get linked address of label
bal __reloc_label # branch and link to label to
nop # get actual address
__reloc_label:
subu t0, ra, t0 # get reloc_delta
beqz t0, __reloc_done # if delta is 0 we are in the right place
nop
/* Copy our code to the right place */
la t1, _code_start # get linked address of _code_start
la t2, _code_end # get linked address of _code_end
addu t0, t0, t1 # calculate actual address of _code_start
__reloc_copy:
lw t3, 0(t0)
sw t3, 0(t1)
add t1, 4
blt t1, t2, __reloc_copy
add t0, 4
/* flush cache */
la t0, _code_start
la t1, _code_end
li t2, ~(CONFIG_CACHELINE_SIZE - 1)
and t0, t2
and t1, t2
li t2, CONFIG_CACHELINE_SIZE
b __flush_check
nop
__flush_line:
cache Hit_Writeback_Inv_D, 0(t0)
cache Hit_Invalidate_I, 0(t0)
add t0, t2
__flush_check:
bne t0, t1, __flush_line
nop
sync
__reloc_done:
/* clear bss */
la t0, _bss_start
la t1, _bss_end
b __bss_check
nop
__bss_fill:
sw zero, 0(t0)
addi t0, 4
__bss_check:
bne t0, t1, __bss_fill
nop
/* Setup new "C" stack */
la sp, _stack
/* jump to the decompressor routine */
la t0, loader_main
jr t0
nop
.set reorder
END(startup)
| {
"language": "Assembly"
} |
// SNES SPC700 Axel-F Song Demo (SPC Code) by krom (Peter Lemon):
arch snes.smp
output "Axel-F.spc", create
macro seek(variable offset) { // Set SPC700 Memory Map
origin (offset - SPCRAM)
base offset
}
macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation
tya // A = Y (Pattern Offset Index)
tax // X = A (Pattern Offset Index)
ldy #{CHANNEL}*2 // Y = CHANNEL * 2
lda (PATTERNOFS),y // A = Pattern List (LSB)
sta.b PATTERN // Store A To Zero Page RAM
iny // Y++
lda (PATTERNOFS),y // A = Pattern List (MSB)
sta.b PATTERN+1 // Store A To Zero Page RAM
txa // A = X (Pattern Offset Index)
tay // Y = A (Pattern Offset Index)
lda (PATTERN),y // A = Pattern Byte
cmp #REST // Compare A To REST Byte ($FE)
beq {#}KEYOFF // IF (A == REST) GOTO Key Off
cmp #SUST // Compare A To SUST Byte ($FD)
beq {#}KEYEND // IF (A == SUST) GOTO Key End
bra {#}KEYON // ELSE GOTO Key On
{#}KEYOFF: // Key Off
WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags
bra {#}KEYEND // GOTO Key End
{#}KEYON: // Key On
tax // X = A (Sample Pitch Table Offset)
str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB)
lda.w {PITCHTABLE},x // A = Voice Pitch (LSB)
sta.b REG_DSPDATA // DSP Register Data = A
str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB)
inx // X++ (Increment Sample Pitch Table Offset)
lda.w {PITCHTABLE},x // A = Voice Pitch (MSB)
sta.b REG_DSPDATA // DSP Register Data = A
WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags
WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags
{#}KEYEND: // Key End
}
include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros
// Constants
constant MaxQuant(128) // Maximum Quantization ms
constant PatternSize(64) // Pattern Size (1..256)
constant ChannelCount(6) // (1 For Each Sample)
// Setup Zero Page RAM
constant PATTERN($00) // Pattern Zero Page RAM Address
constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address
seek(SPCRAM); Start:
SPC_INIT() // Run SPC700 Initialisation Routine
WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset
WDSP(DSP_KOFF,$00) // Reset Key Off Flags
WDSP(DSP_MVOLL,63) // Master Volume Left
WDSP(DSP_MVOLR,63) // Master Volume Right
SPCRAMClear($C000,$40) // Clear Echo Buffer RAM
WDSP(DSP_ESA,$C0) // Echo Source Address
WDSP(DSP_EDL,8) // Echo Delay
WDSP(DSP_EON,%00001011) // Echo On Flags
WDSP(DSP_FLG,0) // Enable Echo Buffer Writes
WDSP(DSP_EFB,100) // Echo Feedback
WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0
WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1
WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2
WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3
WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4
WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5
WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6
WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7
WDSP(DSP_EVOLL,25) // Echo Volume Left
WDSP(DSP_EVOLR,25) // Echo Volume Right
WDSP(DSP_V0VOLL,50) // Voice 0: Volume Left
WDSP(DSP_V0VOLR,50) // Voice 0: Volume Right
WDSP(DSP_V0SRCN,0) // Voice 0: SawTooth
WDSP(DSP_V0ADSR1,$FA) // Voice 0: ADSR1
WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2
WDSP(DSP_V0GAIN,127) // Voice 0: Gain
WDSP(DSP_V1VOLL,50) // Voice 1: Volume Left
WDSP(DSP_V1VOLR,50) // Voice 1: Volume Right
WDSP(DSP_V1SRCN,0) // Voice 1: SawTooth
WDSP(DSP_V1ADSR1,$FA) // Voice 1: ADSR1
WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2
WDSP(DSP_V1GAIN,127) // Voice 1: Gain
WDSP(DSP_V2VOLL,127) // Voice 2: Volume Left
WDSP(DSP_V2VOLR,127) // Voice 2: Volume Right
WDSP(DSP_V2SRCN,1) // Voice 2: SynthBass
WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1
WDSP(DSP_V2ADSR2,$F0) // Voice 2: ADSR2
WDSP(DSP_V2GAIN,127) // Voice 2: Gain
WDSP(DSP_V3VOLL,80) // Voice 3: Volume Left
WDSP(DSP_V3VOLR,80) // Voice 3: Volume Right
WDSP(DSP_V3SRCN,2) // Voice 3: Clap
WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1
WDSP(DSP_V3ADSR2,$F0) // Voice 3: ADSR2
WDSP(DSP_V3GAIN,127) // Voice 3: Gain
WDSP(DSP_V4VOLL,127) // Voice 4: Volume Left
WDSP(DSP_V4VOLR,127) // Voice 4: Volume Right
WDSP(DSP_V4SRCN,3) // Voice 4: KickDrum
WDSP(DSP_V4ADSR1,$FF) // Voice 4: ADSR1
WDSP(DSP_V4ADSR2,$F0) // Voice 4: ADSR2
WDSP(DSP_V4GAIN,127) // Voice 4: Gain
WDSP(DSP_V5VOLL,127) // Voice 5: Volume Left
WDSP(DSP_V5VOLR,127) // Voice 5: Volume Right
WDSP(DSP_V5SRCN,4) // Voice 5: Snare
WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1
WDSP(DSP_V5ADSR2,$F0) // Voice 5: ADSR2
WDSP(DSP_V5GAIN,127) // Voice 5: Gain
StartSong: // Each Bar = 2048ms, Each Beat = 512ms, 3/4 Beat = 384ms, 1/2 Beat = 256ms, 1/4 Beat 128ms
lda #PATTERNLIST // A = Pattern List (LSB)
ldy #PATTERNLIST>>8 // Y = Pattern List (MSB)
stw PATTERNOFS // Store YA To Zero Page RAM
ldy #0 // Y = 0 (Pattern Offset Index)
LoopSong:
ChannelPattern(0, 0, SawToothPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table
ChannelPattern(1, 1, SawToothDetunePitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table
ChannelPattern(2, 2, SynthBassPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table
ChannelPattern(3, 3, ClapPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table
ChannelPattern(4, 4, KickDrumPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table
ChannelPattern(5, 5, SnarePitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table
// Wait For MilliSecond Amount (8kHz Timer)
lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms
str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms)
str REG_CONTROL=#$01
WaitMS:
bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer
dec // A--
bne WaitMS // IF (A != 0) Loop Timer Wait
iny // Increment Pattern Index Offset
cpy #PatternSize // Compare Y To Pattern Size
beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment
jmp PatternEnd // ELSE Pattern End
PatternIncrement: // Channel 1..6 Pattern Increment
ldy #0 // Y = 0
lda #ChannelCount * 2 // YA = Channel Count * 2
adw PATTERNOFS // YA += Pattern Offset
stw PATTERNOFS // Pattern Offset = YA
// Compare Pattern List Change Address
lda #PATTERNLISTCHANGE // A = Pattern List Change (LSB)
ldy #PATTERNLISTCHANGE>>8 // Y = Pattern List Change (MSB)
cpw PATTERNOFS // Compare YA To Zero Page RAM
bne PatternCmpEnd // IF (Pattern Offset != Pattern List Change Offset) Pattern Compare End, ELSE Set Pattern Change Offset
WDSP(DSP_KOFF,%00000011) // DSP Register Data = Key Off Flags
// Set Staccato Saw Tooth (Channel 1)
WDSP(DSP_V0VOLL,100) // Voice 0: Volume Left
WDSP(DSP_V0VOLR,100) // Voice 0: Volume Right
WDSP(DSP_V0ADSR1,$FE) // Voice 0: ADSR1
WDSP(DSP_V0ADSR2,$2F) // Voice 0: ADSR2
// Set Staccato Saw Tooth Detune (Channel 2)
WDSP(DSP_V1VOLL,100) // Voice 1: Volume Left
WDSP(DSP_V1VOLR,100) // Voice 1: Volume Right
WDSP(DSP_V1ADSR1,$FE) // Voice 1: ADSR1
WDSP(DSP_V1ADSR2,$2F) // Voice 1: ADSR2
PatternCmpEnd: // Compare Pattern List End Address
lda #PATTERNLISTEND // A = Pattern List End (LSB)
ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB)
cpw PATTERNOFS // Compare YA To Zero Page RAM
bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset
// Set Pattern Loop Offset
lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB)
ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB)
stw PATTERNOFS // Store YA To Zero Page RAM
WDSP(DSP_KOFF,%00000011) // DSP Register Data = Key Off Flags
// Set Saw Tooth (Channel 1)
WDSP(DSP_V0VOLL,50) // Voice 0: Volume Left
WDSP(DSP_V0VOLR,50) // Voice 0: Volume Right
WDSP(DSP_V0ADSR1,$FA) // Voice 0: ADSR1
WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2
// Set Saw Tooth Detune (Channel 2)
WDSP(DSP_V1VOLL,50) // Voice 1: Volume Left
WDSP(DSP_V1VOLR,50) // Voice 1: Volume Right
WDSP(DSP_V1ADSR1,$FA) // Voice 1: ADSR1
WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2
PatternIncEnd:
ldy #0 // Y = 0 (Pattern Index Offset)
PatternEnd:
jmp LoopSong // GOTO Loop Song
SawToothPitchTable:
WritePitchTable($8868) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words)
SawToothDetunePitchTable:
WritePitchTable($8748) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words)
SynthBassPitchTable:
WritePitchTable($8868) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words)
ClapPitchTable:
dw $9468 // Write Sample Pitch Table
KickDrumPitchTable:
dw $8868 // Write Sample Pitch Table
SnarePitchTable:
dw $9668 // Write Sample Pitch Table
PATTERN00: // Pattern 00: Rest (Channel 1..8)
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 1
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 2
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 3
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 4
PATTERN01: // Pattern 01: Saw Tooth / Saw Tooth Detune (Channel 1 & 2)
db F5, SUST, SUST, SUST, G5s, SUST, SUST, F5, SUST, F5, A5s, SUST, F5, SUST, D5s, SUST // 1
db F5, SUST, SUST, SUST, C6, SUST, SUST, F5, SUST, F5, C6s, SUST, C6, SUST, G5s, SUST // 2
db F5, SUST, C6, SUST, F6, SUST, F5, D5s, SUST, D5s, C5, SUST, G5, SUST, F5, SUST // 3
db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 4
PATTERN02: // Pattern 02: Bass (Channel 3)
db F3, SUST, SUST, SUST, F4, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 9
db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, C3, C4, SUST, D4s, SUST, F4, SUST // 10
db C3s, SUST, SUST, SUST, C4s, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 11
db F3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, F4, C4, SUST, A3s, SUST, G3s, SUST // 12
PATTERN03: // Pattern 03: Bass (Channel 3)
db F3, SUST, SUST, SUST, F4, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 21
db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, C3, C4, SUST, D4s, SUST, F4, SUST // 22
db C3s, SUST, SUST, SUST, C4s, SUST, SUST, D3s, SUST, SUST, SUST, SUST, D4s, SUST, SUST, SUST // 23
db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, F4, C4, SUST, A3s, SUST, G3s, SUST // 24
PATTERN04: // Pattern 04: Clap (Channel 4)
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 9
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 10
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 11
db REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 12
PATTERN05: // Pattern 05: Clap (Channel 4)
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 13
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, SUST, HIT, SUST, HIT, SUST // 14
db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 15
db REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 16
PATTERN06: // Pattern 06: Kick Drum (Channel 5)
db HIT, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, HIT, HIT, SUST, SUST, SUST, SUST, SUST // 13
db HIT, SUST, SUST, SUST, HIT, SUST, SUST, SUST, SUST, HIT, HIT, SUST, SUST, SUST, SUST, SUST // 14
db HIT, SUST, SUST, SUST, HIT, SUST, SUST, HIT, SUST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 15
db HIT, SUST, SUST, SUST, HIT, SUST, SUST, SUST, SUST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 16
PATTERN07: // Pattern 07: Snare (Channel 6)
db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 17
db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 18
db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 19
db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 20
PATTERN08: // Pattern 08: Staccato Saw Tooth (Channel 1)
db REST, REST, F5, SUST, SUST, SUST, F5, G5, SUST, G5, SUST, G5, F5, SUST, F5, SUST // 21
db SUST, SUST, F5, SUST, F5, SUST, F5, G5, SUST, G5, F5, SUST, F5, SUST, SUST, SUST // 22
db SUST, SUST, C5s, SUST, C5s, SUST, C5s, SUST, C5s, D5s, SUST, D5s, SUST, D5s, SUST, D5s // 23
db D5s, SUST, F5, SUST, F5, SUST, F5, SUST, D5s, F5, SUST, F5, SUST, SUST, SUST, SUST // 24
PATTERN09: // Pattern 09: Staccato Saw Tooth Detune (Channel 2)
db REST, REST, C6, SUST, SUST, SUST, C6, D6s, SUST, D6s, SUST, D6s, D6, SUST, D6, SUST // 21
db SUST, SUST, C6, SUST, C6, SUST, C6, D6s, SUST, D6s, D6, SUST, C6, SUST, SUST, SUST // 22
db SUST, SUST, G5s, SUST, G5s, SUST, G5s, SUST, G5s, A5s, SUST, A5s, SUST, A5s, SUST, A5s // 23
db A5s, SUST, C6, SUST, C6, SUST, C6, SUST, A5s, C6, SUST, C6, SUST, SUST, SUST, SUST // 24
PATTERNLIST:
dw PATTERN01,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List
dw PATTERN01,PATTERN01,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List
dw PATTERN00,PATTERN00,PATTERN02,PATTERN04,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List
dw PATTERN00,PATTERN00,PATTERN02,PATTERN05,PATTERN06,PATTERN00 // Channel 1..6 Pattern Address List
PATTERNLISTLOOP:
dw PATTERN01,PATTERN01,PATTERN02,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List
dw PATTERN01,PATTERN01,PATTERN02,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List
PATTERNLISTCHANGE:
dw PATTERN08,PATTERN09,PATTERN03,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List
dw PATTERN08,PATTERN09,PATTERN03,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List
PATTERNLISTEND:
seek($2A00); sampleDIR:
dw SawTooth, SawTooth + 2691 // 0
dw SynthBass, 0 // 1
dw Clap, 0 // 2
dw KickDrum, 0 // 3
dw Snare, 0 // 4
seek($2B00) // Sample Data
insert SawTooth, "BRR/MSAWTOOF(Loop=2691,AD=$FA,SR=$F0,Echo)(C9Pitch=$8868).brr"
insert SynthBass, "BRR/SYNBSS3(AD=$FF,SR=$F0)(C9Pitch=$8868).brr"
insert Clap, "BRR/CLAPTRAP(AD=$FF,SR=$F0)(C9Pitch=$8868).brr"
insert KickDrum, "BRR/KICK5(AD=$FF,SR=$F0)(C9Pitch=$8868).brr"
insert Snare, "BRR/SNAREA13(AD=$FF,SR=$F0)(C9Pitch=$8868).brr" | {
"language": "Assembly"
} |
byte mbr_buf[] = {
0xEB, 0x03, 0x54, 0x53, 0x4C, 0xB8, 0xC0, 0x07,
0x8E, 0xD8, 0xFA, 0x33, 0xC0, 0x8E, 0xD0, 0xBC,
0x00, 0x7C, 0xFB, 0xB8, 0xE0, 0x07, 0x8E, 0xC0,
0xBE, 0x67, 0x01, 0x81, 0x3E, 0xFE, 0x01, 0x55,
0xAA, 0x75, 0x31, 0xB9, 0x00, 0x01, 0x33, 0xF6,
0x8B, 0xFE, 0xFC, 0xF3, 0xA5, 0x8C, 0xC0, 0x8E,
0xD8, 0xE9, 0x00, 0x02, 0xBE, 0xEE, 0x01, 0xB9,
0x04, 0x00, 0x33, 0xDB, 0xF6, 0x04, 0x80, 0x74,
0x03, 0x8B, 0xC1, 0x43, 0x83, 0xEE, 0x10, 0xE2,
0xF3, 0x48, 0x83, 0xFB, 0x01, 0x7F, 0x63, 0x74,
0x05, 0xBE, 0x25, 0x01, 0xEB, 0x4C, 0x50, 0xE8,
0x8F, 0x00, 0xB8, 0xC0, 0x07, 0x8E, 0xC0, 0x33,
0xDB, 0xB8, 0x01, 0x02, 0x8A, 0x14, 0x80, 0xE2,
0x81, 0x8A, 0x74, 0x01, 0x8A, 0x4C, 0x02, 0x8A,
0x6C, 0x03, 0xCD, 0x13, 0x73, 0x05, 0xBE, 0x7F,
0x01, 0xEB, 0x27, 0x26, 0x81, 0x3E, 0xFE, 0x01,
0x55, 0xAA, 0x74, 0x05, 0xBE, 0x67, 0x01, 0xEB,
0x19, 0xCD, 0x12, 0xB1, 0x06, 0xD3, 0xE0, 0x48,
0x8E, 0xC0, 0x58, 0x26, 0xA2, 0x0F, 0x00, 0x81,
0xC6, 0x00, 0x7E, 0x33, 0xC0, 0x8E, 0xD8, 0xE9,
0x5E, 0xFD, 0xE8, 0x50, 0x00, 0xE8, 0x64, 0x00,
0xEB, 0xFE, 0xBE, 0x38, 0x01, 0xE8, 0x5C, 0x00,
0xEB, 0x05, 0xE8, 0x40, 0x00, 0x8B, 0xD0, 0xB4,
0x01, 0xCD, 0x16, 0x74, 0x06, 0x32, 0xE4, 0xCD,
0x16, 0xEB, 0xF4, 0xBE, 0x55, 0x01, 0xE8, 0x43,
0x00, 0x32, 0xE4, 0xCD, 0x16, 0xA2, 0x1F, 0x01,
0xBE, 0x1F, 0x01, 0xE8, 0x36, 0x00, 0x3C, 0x34,
0x77, 0xD0, 0x2C, 0x31, 0x72, 0xCC, 0xE8, 0x08,
0x00, 0xF6, 0x04, 0x80, 0x74, 0xC4, 0xE9, 0x6D,
0xFF, 0x50, 0xBE, 0xBE, 0x01, 0xB4, 0x10, 0xF6,
0xE4, 0x03, 0xF0, 0x58, 0xC3, 0x50, 0x53, 0x32,
0xFF, 0xB4, 0x0F, 0xCD, 0x10, 0x24, 0x07, 0x3C,
0x07, 0x74, 0x02, 0xB0, 0x03, 0x32, 0xE4, 0xCD,
0x10, 0x5B, 0x58, 0xC3, 0x50, 0x53, 0xBB, 0x0F,
0x00, 0xB4, 0x0E, 0xAC, 0x84, 0xC0, 0x74, 0x04,
0xCD, 0x10, 0xEB, 0xF2, 0x5B, 0x58, 0xC3, 0x00,
0x0D, 0x0A, 0x0D, 0x0A, 0x00, 0x4E, 0x6F, 0x20,
0x4D, 0x4F, 0x53, 0x20, 0x70, 0x61, 0x72, 0x74,
0x69, 0x74, 0x69, 0x6F, 0x6E, 0x73, 0x07, 0x00,
0x20, 0x4E, 0x6F, 0x74, 0x20, 0x61, 0x20, 0x42,
0x6F, 0x6F, 0x74, 0x61, 0x62, 0x6C, 0x65, 0x20,
0x50, 0x61, 0x72, 0x74, 0x69, 0x74, 0x69, 0x6F,
0x6E, 0x21, 0x3F, 0x0D, 0x0A, 0x42, 0x6F, 0x6F,
0x74, 0x20, 0x50, 0x61, 0x72, 0x74, 0x69, 0x74,
0x69, 0x6F, 0x6E, 0x3F, 0x20, 0x07, 0x00, 0x49,
0x6E, 0x76, 0x61, 0x6C, 0x69, 0x64, 0x20, 0x62,
0x6F, 0x6F, 0x74, 0x20, 0x73, 0x69, 0x67, 0x6E,
0x61, 0x74, 0x75, 0x72, 0x65, 0x07, 0x00, 0x43,
0x61, 0x6E, 0x6E, 0x6F, 0x74, 0x20, 0x6C, 0x6F,
0x61, 0x64, 0x20, 0x4D, 0x4F, 0x53, 0x07, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xAA
};
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -std=c99 -E %s -o - | FileCheck --check-prefix=CHECK-PED-NONE %s
// RUN: %clang_cc1 -std=c99 -pedantic-errors -E %s -o - | FileCheck --check-prefix=CHECK-PED-ERR %s
// CHECK-PED-NONE: no_dummy_extension
#if !__has_extension(dummy_extension)
int no_dummy_extension();
#endif
// Arbitrary feature to test that has_extension is a superset of has_feature
// CHECK-PED-NONE: attribute_overloadable
#if __has_extension(attribute_overloadable)
int attribute_overloadable();
#endif
// CHECK-PED-NONE: has_c_static_assert
// CHECK-PED-ERR: no_c_static_assert
#if __has_extension(c_static_assert)
int has_c_static_assert();
#else
int no_c_static_assert();
#endif
// CHECK-PED-NONE: has_c_generic_selections
// CHECK-PED-ERR: no_c_generic_selections
#if __has_extension(c_generic_selections)
int has_c_generic_selections();
#else
int no_c_generic_selections();
#endif
// CHECK-PED-NONE: has_c_alignas
// CHECK-PED-ERR: no_c_alignas
#if __has_extension(c_alignas)
int has_c_alignas();
#else
int no_c_alignas();
#endif
// CHECK-PED-NONE: has_c_alignof
// CHECK-PED-ERR: no_c_alignof
#if __has_extension(c_alignof)
int has_c_alignof();
#else
int no_c_alignof();
#endif
// Arbitrary feature to test that the extension name can be surrounded with
// double underscores.
// CHECK-PED-NONE: has_double_underscores
#if __has_extension(__c_alignas__)
int has_double_underscores();
#endif
| {
"language": "Assembly"
} |
//
// (c) Yuri Kiryanov, openh323@kiryanov.com
// for Openh323, www.Openh323.org
//
// Windows CE Port
// Extra header file
//
#include <stdlibx.h>
| {
"language": "Assembly"
} |
// Copyright 2005-2015 Intel Corporation. All Rights Reserved.
//
// This file is part of Threading Building Blocks. Threading Building Blocks is free software;
// you can redistribute it and/or modify it under the terms of the GNU General Public License
// version 2 as published by the Free Software Foundation. Threading Building Blocks is
// distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
// implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details. You should have received a copy of
// the GNU General Public License along with Threading Building Blocks; if not, write to the
// Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
//
// As a special exception, you may use this file as part of a free software library without
// restriction. Specifically, if other files instantiate templates or use macros or inline
// functions from this file, or you compile this file and link it with other files to produce
// an executable, this file does not by itself cause the resulting executable to be covered
// by the GNU General Public License. This exception does not however invalidate any other
// reasons why the executable file might be covered by the GNU General Public License.
.section .text
.align 16
// unsigned long __TBB_machine_lg( unsigned long x );
// r32 = x
.proc __TBB_machine_lg#
.global __TBB_machine_lg#
__TBB_machine_lg:
shr r16=r32,1 // .x
;;
shr r17=r32,2 // ..x
or r32=r32,r16 // xx
;;
shr r16=r32,3 // ...xx
or r32=r32,r17 // xxx
;;
shr r17=r32,5 // .....xxx
or r32=r32,r16 // xxxxx
;;
shr r16=r32,8 // ........xxxxx
or r32=r32,r17 // xxxxxxxx
;;
shr r17=r32,13
or r32=r32,r16 // 13x
;;
shr r16=r32,21
or r32=r32,r17 // 21x
;;
shr r17=r32,34
or r32=r32,r16 // 34x
;;
shr r16=r32,55
or r32=r32,r17 // 55x
;;
or r32=r32,r16 // 64x
;;
popcnt r8=r32
;;
add r8=-1,r8
br.ret.sptk.many b0
.endp __TBB_machine_lg#
| {
"language": "Assembly"
} |
;
; Extended memory driver for the C256K memory expansion
; Marco van den Heuvel, 2010-01-27
;
.include "zeropage.inc"
.include "em-kernel.inc"
.include "em-error.inc"
.macpack generic
.macpack module
; ------------------------------------------------------------------------
; Header. Includes jump table
module_header _c64_c256k_emd
; Driver signature
.byte $65, $6d, $64 ; "emd"
.byte EMD_API_VERSION ; EM API version number
; Library reference
.addr $0000
; Jump table
.addr INSTALL
.addr UNINSTALL
.addr PAGECOUNT
.addr MAP
.addr USE
.addr COMMIT
.addr COPYFROM
.addr COPYTO
; ------------------------------------------------------------------------
; Constants
BASE = $4000
PAGES = 3 * 256
TARGETLOC = $200 ; Target location for copy/check code
PIA = $DFC0
; ------------------------------------------------------------------------
; Data.
.data
; This function is used to copy code from and to the extended memory
.proc copy
template:
.org ::TARGETLOC ; Assemble for target location
entry:
stx PIA
stashop = $91 ; 'sta' opcode
operation := * ; Location and opcode is patched at runtime
address := *+1
lda ($00),y
ldx #$dc
stx PIA
rts
.reloc
.endproc
; This function is used to check for the existence of the extended memory
.proc check
template:
.org ::TARGETLOC
entry:
ldy #$00 ; Assume hardware not present
lda #$fc
sta PIA
lda $01
tax
and #$f8
sta $01
lda $4000
cmp $c000
bne done ; Jump if not found
inc $c000
cmp $4000
beq done ; Jump if not found
; Hardware is present
iny
done: stx $01
ldx #$dc
stx PIA
rts
.reloc
.endproc
.bss
curpage: .res 2 ; Current page number
curbank: .res 1 ; Current bank
window: .res 256 ; Memory "window"
; Since the functions above are copied to $200, the current contents of this
; memory area must be saved into backup storage. Allocate enough space.
backup: .res .max (.sizeof (copy), .sizeof (check))
.code
; ------------------------------------------------------------------------
; INSTALL routine. Is called after the driver is loaded into memory. If
; possible, check if the hardware is present and determine the amount of
; memory available.
; Must return an EM_ERR_xx code in a/x.
;
INSTALL:
lda PIA+1 ; Select Peripheral Registers
ora #4
sta PIA+1
tax
lda PIA+3
ora #4
sta PIA+3
tay
lda #$DC ; Set the default memory bank data
sta PIA
lda #$FE
sta PIA+2
txa ; Select Data Direction Registers
and #$FB
sta PIA+1
tya
and #$FB
sta PIA+3
lda #$FF ; Set the ports to output
sta PIA
sta PIA+2
txa
and #$C7
ora #$30 ; Set CA1 and
sta PIA+1 ; select Peripheral Registers
sty PIA+3
jsr backup_and_setup_check_routine
jsr check::entry
cli
ldx #.sizeof (check) - 1
jsr restore_data
cpy #$01
beq @present
lda #<EM_ERR_NO_DEVICE
ldx #>EM_ERR_NO_DEVICE
rts
@present:
lda #<EM_ERR_OK
ldx #>EM_ERR_OK
; rts ; Run into UNINSTALL instead
; ------------------------------------------------------------------------
; UNINSTALL routine. Is called before the driver is removed from memory.
; Can do cleanup or whatever. Must not return anything.
;
UNINSTALL:
rts
; ------------------------------------------------------------------------
; PAGECOUNT: Return the total number of available pages in a/x.
;
PAGECOUNT:
lda #<PAGES
ldx #>PAGES
rts
; ------------------------------------------------------------------------
; MAP: Map the page in a/x into memory and return a pointer to the page in
; a/x. The contents of the currently mapped page (if any) may be discarded
; by the driver.
;
MAP:
sei
sta curpage ; Remember the new page
stx curpage+1
jsr adjust_page_and_bank
stx curbank
clc
adc #>BASE
sta ptr1+1
ldy #0
sty ptr1
jsr backup_and_setup_copy_routine
ldx #<ptr1
stx copy::address
@L1:
ldx curbank
jsr copy::entry
ldx ptr1
sta window,x
inc ptr1
bne @L1
; Return the memory window
jsr restore_copy_routine
lda #<window
ldx #>window ; Return the window address
cli
rts
; ------------------------------------------------------------------------
; USE: Tell the driver that the window is now associated with a given page.
USE: sta curpage ; Remember the page
stx curpage+1
lda #<window
ldx #>window ; Return the window
rts
; ------------------------------------------------------------------------
; COMMIT: Commit changes in the memory window to extended storage.
COMMIT:
sei
lda curpage ; Get the current page
ldx curpage+1
jsr adjust_page_and_bank
stx curbank
clc
adc #>BASE
sta ptr1+1
ldy #0
sty ptr1
jsr backup_and_setup_copy_routine
ldx #<ptr1
stx copy::address
ldx #<copy::stashop
stx copy::operation
@L1:
ldx ptr1
lda window,x
ldx curbank
jsr copy::entry
inc ptr1
bne @L1
; Return the memory window
jsr restore_copy_routine
done:
cli
rts
; ------------------------------------------------------------------------
; COPYFROM: Copy from extended into linear memory. A pointer to a structure
; describing the request is passed in a/x.
; The function must not return anything.
;
COPYFROM:
sei
jsr setup
jsr backup_and_setup_copy_routine
; Setup is:
;
; - ptr1 contains the struct pointer
; - ptr2 contains the linear memory buffer
; - ptr3 contains -(count-1)
; - ptr4 contains the page memory buffer plus offset
; - tmp1 contains zero (to be used for linear memory buffer offset)
; - tmp2 contains the bank value
lda #<ptr4
sta copy::address
jmp @L3
@L1:
ldx tmp2
ldy #0
jsr copy::entry
ldy tmp1
sta (ptr2),y
inc tmp1
bne @L2
inc ptr2+1
@L2:
inc ptr4
beq @L4
; Bump count and repeat
@L3:
inc ptr3
bne @L1
inc ptr3+1
bne @L1
jsr restore_copy_routine
cli
rts
; Bump page register
@L4:
inc ptr4+1
lda ptr4+1
cmp #$80
bne @L3
lda #>BASE
sta ptr4+1
lda tmp2
clc
adc #$10
sta tmp2
jmp @L3
; ------------------------------------------------------------------------
; COPYTO: Copy from linear into extended memory. A pointer to a structure
; describing the request is passed in a/x.
; The function must not return anything.
;
COPYTO:
sei
jsr setup
jsr backup_and_setup_copy_routine
; Setup is:
;
; - ptr1 contains the struct pointer
; - ptr2 contains the linear memory buffer
; - ptr3 contains -(count-1)
; - ptr4 contains the page memory buffer plus offset
; - tmp1 contains zero (to be used for linear memory buffer offset)
; - tmp2 contains the bank value
lda #<ptr4
sta copy::address
lda #<copy::stashop
sta copy::operation
jmp @L3
@L1:
ldy tmp1
lda (ptr2),y
ldx tmp2
ldy #0
jsr copy::entry
inc tmp1
bne @L2
inc ptr2+1
@L2:
inc ptr4
beq @L4
; Bump count and repeat
@L3:
inc ptr3
bne @L1
inc ptr3+1
bne @L1
jsr restore_copy_routine
cli
rts
; Bump page register
@L4:
inc ptr4+1
lda ptr4+1
cmp #$80
bne @L3
lda #>BASE
sta ptr4+1
lda tmp2
clc
adc #$10
sta tmp2
jmp @L3
; ------------------------------------------------------------------------
; Helper function for COPYFROM and COPYTO: Store the pointer to the request
; structure and prepare data for the copy
setup:
sta ptr1
stx ptr1+1 ; Save passed pointer
; Get the page number from the struct and adjust it so that it may be used
; with the hardware. That is: ptr4 has the page address and page offset
; tmp2 will hold the bank value
ldy #EM_COPY::PAGE+1
lda (ptr1),y
tax
ldy #EM_COPY::PAGE
lda (ptr1),y
jsr adjust_page_and_bank
clc
adc #>BASE
sta ptr4+1
stx tmp2
; Get the buffer pointer into ptr2
ldy #EM_COPY::BUF
lda (ptr1),y
sta ptr2
iny
lda (ptr1),y
sta ptr2+1
; Get the count, calculate -(count-1) and store it into ptr3
ldy #EM_COPY::COUNT
lda (ptr1),y
eor #$FF
sta ptr3
iny
lda (ptr1),y
eor #$FF
sta ptr3+1
; Get the page offset into ptr4 and clear tmp1
ldy #EM_COPY::OFFS
lda (ptr1),y
sta ptr4
lda #0
sta tmp1
; Done
rts
; Helper routines for copying to and from the +256k ram
backup_and_setup_copy_routine:
ldx #.sizeof (copy) - 1
@L1:
lda copy::entry,x
sta backup,x
lda copy::template,x
sta copy::entry,x
dex
bpl @L1
rts
backup_and_setup_check_routine:
ldx #.sizeof (check) - 1
@L1:
lda check::entry,x
sta backup,x
lda check::template,x
sta check::entry,x
dex
bpl @L1
rts
restore_copy_routine:
ldx #.sizeof (copy) - 1
restore_data:
lda backup,x
sta TARGETLOC,x
dex
bpl restore_data
rts
; Helper routine to correct for the bank and page
adjust_page_and_bank:
sta tmp4
lda #$0C
sta tmp3
lda tmp4
and #$c0
lsr
lsr
ora tmp3
sta tmp3
txa
asl
asl
asl
asl
asl
asl
ora tmp3
tax
lda tmp4
and #$3f
rts
| {
"language": "Assembly"
} |
config BR2_PACKAGE_AT_SPI2_CORE
bool "at-spi2-core"
depends on BR2_PACKAGE_XORG7 # xlib-libxtst
depends on BR2_TOOLCHAIN_HAS_THREADS # dbus, glib2
depends on BR2_USE_MMU # glib2
depends on BR2_USE_WCHAR # glib2
select BR2_PACKAGE_DBUS
select BR2_PACKAGE_LIBGLIB2
select BR2_PACKAGE_XLIB_LIBXTST
help
The At-Spi2 Core package is a part of the GNOME
Accessibility Project. It provides a Service Provider
Interface for the Assistive Technologies available on the
GNOME platform and a library against which applications
can be linked.
https://wiki.gnome.org/Accessibility
comment "at-spi2-core needs a toolchain w/ wchar, threads"
depends on BR2_USE_MMU
depends on !BR2_USE_WCHAR || !BR2_TOOLCHAIN_HAS_THREADS
comment "at-spi2-core depends on X.org"
depends on BR2_USE_MMU
depends on !BR2_PACKAGE_XORG7
| {
"language": "Assembly"
} |
glabel func_80A438B4
/* 00B84 80A438B4 AFA40000 */ sw $a0, 0x0000($sp)
/* 00B88 80A438B8 3C048016 */ lui $a0, %hi(gSaveContext)
/* 00B8C 80A438BC 3C038012 */ lui $v1, %hi(gBitFlags)
/* 00B90 80A438C0 24637120 */ addiu $v1, %lo(gBitFlags)
/* 00B94 80A438C4 2484E660 */ addiu $a0, %lo(gSaveContext)
/* 00B98 80A438C8 8C8200A4 */ lw $v0, 0x00A4($a0) ## 8015E704
/* 00B9C 80A438CC 8C6E0004 */ lw $t6, 0x0004($v1) ## 80127124
/* 00BA0 80A438D0 AFA50004 */ sw $a1, 0x0004($sp)
/* 00BA4 80A438D4 01C27824 */ and $t7, $t6, $v0
/* 00BA8 80A438D8 51E00007 */ beql $t7, $zero, .L80A438F8
/* 00BAC 80A438DC 8C79004C */ lw $t9, 0x004C($v1) ## 8012716C
/* 00BB0 80A438E0 8C980004 */ lw $t8, 0x0004($a0) ## 8015E664
/* 00BB4 80A438E4 57000004 */ bnel $t8, $zero, .L80A438F8
/* 00BB8 80A438E8 8C79004C */ lw $t9, 0x004C($v1) ## 8012716C
/* 00BBC 80A438EC 03E00008 */ jr $ra
/* 00BC0 80A438F0 24023043 */ addiu $v0, $zero, 0x3043 ## $v0 = 00003043
.L80A438F4:
/* 00BC4 80A438F4 8C79004C */ lw $t9, 0x004C($v1) ## 8012716C
.L80A438F8:
/* 00BC8 80A438F8 03224024 */ and $t0, $t9, $v0
/* 00BCC 80A438FC 51000004 */ beql $t0, $zero, .L80A43910
/* 00BD0 80A43900 94890ED8 */ lhu $t1, 0x0ED8($a0) ## 8015F538
/* 00BD4 80A43904 03E00008 */ jr $ra
/* 00BD8 80A43908 24023027 */ addiu $v0, $zero, 0x3027 ## $v0 = 00003027
.L80A4390C:
/* 00BDC 80A4390C 94890ED8 */ lhu $t1, 0x0ED8($a0) ## 8015F538
.L80A43910:
/* 00BE0 80A43910 312A0008 */ andi $t2, $t1, 0x0008 ## $t2 = 00000000
/* 00BE4 80A43914 51400004 */ beql $t2, $zero, .L80A43928
/* 00BE8 80A43918 948B0F14 */ lhu $t3, 0x0F14($a0) ## 8015F574
/* 00BEC 80A4391C 10000009 */ beq $zero, $zero, .L80A43944
/* 00BF0 80A43920 24033021 */ addiu $v1, $zero, 0x3021 ## $v1 = 00003021
/* 00BF4 80A43924 948B0F14 */ lhu $t3, 0x0F14($a0) ## 8015F574
.L80A43928:
/* 00BF8 80A43928 24023008 */ addiu $v0, $zero, 0x3008 ## $v0 = 00003008
/* 00BFC 80A4392C 316C0001 */ andi $t4, $t3, 0x0001 ## $t4 = 00000000
/* 00C00 80A43930 11800003 */ beq $t4, $zero, .L80A43940
/* 00C04 80A43934 00000000 */ nop
/* 00C08 80A43938 10000001 */ beq $zero, $zero, .L80A43940
/* 00C0C 80A4393C 2402302A */ addiu $v0, $zero, 0x302A ## $v0 = 0000302A
.L80A43940:
/* 00C10 80A43940 00401825 */ or $v1, $v0, $zero ## $v1 = 0000302A
.L80A43944:
/* 00C14 80A43944 3062FFFF */ andi $v0, $v1, 0xFFFF ## $v0 = 0000302A
/* 00C18 80A43948 03E00008 */ jr $ra
/* 00C1C 80A4394C 00000000 */ nop
| {
"language": "Assembly"
} |
.rdata
glabel D_80154230
.asciz "\x1b[33m"
.balign 4
glabel D_80154238
.asciz "？？？？？？？？？？？？？？？？ z_message.c ？？？？？？？？？？？？？？？？？？\n"
.balign 4
glabel D_80154290
.asciz "\x1b[m"
.balign 4
glabel D_80154294
.asciz "../z_message_PAL.c"
.balign 4
glabel D_801542A8
.asciz "../z_message_PAL.c"
.balign 4
glabel D_801542BC
.asciz "../z_message_PAL.c"
.balign 4
glabel D_801542D0
.asciz "../z_message_PAL.c"
.balign 4
glabel D_801542E4
# Text Box Type＝%d
.asciz "吹き出し種類＝%d\n"
.balign 4
glabel D_801542F8
.asciz "../z_message_PAL.c"
.balign 4
.text
glabel func_8010B0C0
/* B82260 8010B0C0 27BDFFB8 */ addiu $sp, $sp, -0x48
/* B82264 8010B0C4 3C0F0001 */ lui $t7, 1
/* B82268 8010B0C8 AFBF0024 */ sw $ra, 0x24($sp)
/* B8226C 8010B0CC AFB00020 */ sw $s0, 0x20($sp)
/* B82270 8010B0D0 AFA40048 */ sw $a0, 0x48($sp)
/* B82274 8010B0D4 AFA5004C */ sw $a1, 0x4c($sp)
/* B82278 8010B0D8 01E47821 */ addu $t7, $t7, $a0
/* B8227C 8010B0DC 91EF03DC */ lbu $t7, 0x3dc($t7)
/* B82280 8010B0E0 3C108016 */ lui $s0, %hi(gGameInfo) # $s0, 0x8016
/* B82284 8010B0E4 30A7FFFF */ andi $a3, $a1, 0xffff
/* B82288 8010B0E8 15E00005 */ bnez $t7, .L8010B100
/* B8228C 8010B0EC 2610FA90 */ addiu $s0, %lo(gGameInfo) # addiu $s0, $s0, -0x570
/* B82290 8010B0F0 3C058016 */ lui $a1, %hi(gSaveContext) # $a1, 0x8016
/* B82294 8010B0F4 24A5E660 */ addiu $a1, %lo(gSaveContext) # addiu $a1, $a1, -0x19a0
/* B82298 8010B0F8 94B813EA */ lhu $t8, 0x13ea($a1)
/* B8229C 8010B0FC A4B813EE */ sh $t8, 0x13ee($a1)
.L8010B100:
/* B822A0 8010B100 8E030000 */ lw $v1, ($s0)
/* B822A4 8010B104 3C058016 */ lui $a1, %hi(gSaveContext) # $a1, 0x8016
/* B822A8 8010B108 24010010 */ li $at, 16
/* B822AC 8010B10C 847904B2 */ lh $t9, 0x4b2($v1)
/* B822B0 8010B110 24A5E660 */ addiu $a1, %lo(gSaveContext) # addiu $a1, $a1, -0x19a0
/* B822B4 8010B114 24040005 */ li $a0, 5
/* B822B8 8010B118 17210007 */ bne $t9, $at, .L8010B138
/* B822BC 8010B11C 00000000 */ nop
/* B822C0 8010B120 0C020978 */ jal Interface_ChangeAlpha
/* B822C4 8010B124 A7A7004E */ sh $a3, 0x4e($sp)
/* B822C8 8010B128 3C058016 */ lui $a1, %hi(gSaveContext) # $a1, 0x8016
/* B822CC 8010B12C 24A5E660 */ addiu $a1, %lo(gSaveContext) # addiu $a1, $a1, -0x19a0
/* B822D0 8010B130 97A7004E */ lhu $a3, 0x4e($sp)
/* B822D4 8010B134 8E030000 */ lw $v1, ($s0)
.L8010B138:
/* B822D8 8010B138 3C088015 */ lui $t0, %hi(D_8014B308) # $t0, 0x8015
/* B822DC 8010B13C 2508B308 */ addiu $t0, %lo(D_8014B308) # addiu $t0, $t0, -0x4cf8
/* B822E0 8010B140 A5000000 */ sh $zero, ($t0)
/* B822E4 8010B144 850A0000 */ lh $t2, ($t0)
/* B822E8 8010B148 3C048015 */ lui $a0, %hi(D_8014B300) # $a0, 0x8015
/* B822EC 8010B14C 3C068015 */ lui $a2, %hi(D_8014B2F4) # $a2, 0x8015
/* B822F0 8010B150 24C6B2F4 */ addiu $a2, %lo(D_8014B2F4) # addiu $a2, $a2, -0x4d0c
/* B822F4 8010B154 2484B300 */ addiu $a0, %lo(D_8014B300) # addiu $a0, $a0, -0x4d00
/* B822F8 8010B158 3C018015 */ lui $at, %hi(D_8014B318) # $at, 0x8015
/* B822FC 8010B15C A08A0000 */ sb $t2, ($a0)
/* B82300 8010B160 A0CA0000 */ sb $t2, ($a2)
/* B82304 8010B164 314B00FF */ andi $t3, $t2, 0xff
/* B82308 8010B168 A42BB318 */ sh $t3, %lo(D_8014B318)($at)
/* B8230C 8010B16C 28E10500 */ slti $at, $a3, 0x500
/* B82310 8010B170 14200011 */ bnez $at, .L8010B1B8
/* B82314 8010B174 00E01025 */ move $v0, $a3
/* B82318 8010B178 28410600 */ slti $at, $v0, 0x600
/* B8231C 8010B17C 1020000E */ beqz $at, .L8010B1B8
/* B82320 8010B180 240C0001 */ li $t4, 1
/* B82324 8010B184 A50C0000 */ sh $t4, ($t0)
/* B82328 8010B188 240D0055 */ li $t5, 85
/* B8232C 8010B18C A46D0B06 */ sh $t5, 0xb06($v1)
/* B82330 8010B190 8E0F0000 */ lw $t7, ($s0)
/* B82334 8010B194 240E0006 */ li $t6, 6
/* B82338 8010B198 24180014 */ li $t8, 20
/* B8233C 8010B19C A5EE0B04 */ sh $t6, 0xb04($t7)
/* B82340 8010B1A0 8E190000 */ lw $t9, ($s0)
/* B82344 8010B1A4 24090030 */ li $t1, 48
/* B82348 8010B1A8 A7380B00 */ sh $t8, 0xb00($t9)
/* B8234C 8010B1AC 8E0A0000 */ lw $t2, ($s0)
/* B82350 8010B1B0 10000009 */ b .L8010B1D8
/* B82354 8010B1B4 A5490496 */ sh $t1, 0x496($t2)
.L8010B1B8:
/* B82358 8010B1B8 240B004B */ li $t3, 75
/* B8235C 8010B1BC A46B0B06 */ sh $t3, 0xb06($v1)
/* B82360 8010B1C0 8E0D0000 */ lw $t5, ($s0)
/* B82364 8010B1C4 240C000C */ li $t4, 12
/* B82368 8010B1C8 240E0041 */ li $t6, 65
/* B8236C 8010B1CC A5AC0B04 */ sh $t4, 0xb04($t5)
/* B82370 8010B1D0 8E0F0000 */ lw $t7, ($s0)
/* B82374 8010B1D4 A5EE0B00 */ sh $t6, 0xb00($t7)
.L8010B1D8:
/* B82378 8010B1D8 240100C2 */ li $at, 194
/* B8237C 8010B1DC 10410004 */ beq $v0, $at, .L8010B1F0
/* B82380 8010B1E0 3C03F000 */ lui $v1, 0xf000
/* B82384 8010B1E4 240100FA */ li $at, 250
/* B82388 8010B1E8 1441000E */ bne $v0, $at, .L8010B224
/* B8238C 8010B1EC 8FB00048 */ lw $s0, 0x48($sp)
.L8010B1F0:
/* B82390 8010B1F0 8CB800A4 */ lw $t8, 0xa4($a1)
/* B82394 8010B1F4 8FB00048 */ lw $s0, 0x48($sp)
/* B82398 8010B1F8 34018000 */ li $at, 32768
/* B8239C 8010B1FC 0303C824 */ and $t9, $t8, $v1
/* B823A0 8010B200 03234824 */ and $t1, $t9, $v1
/* B823A4 8010B204 00095702 */ srl $t2, $t1, 0x1c
/* B823A8 8010B208 004A3821 */ addu $a3, $v0, $t2
/* B823AC 8010B20C 261020D8 */ addiu $s0, $s0, 0x20d8
/* B823B0 8010B210 02015821 */ addu $t3, $s0, $at
/* B823B4 8010B214 30E7FFFF */ andi $a3, $a3, 0xffff
/* B823B8 8010B218 00E01025 */ move $v0, $a3
/* B823BC 8010B21C 1000001D */ b .L8010B294
/* B823C0 8010B220 AFAB002C */ sw $t3, 0x2c($sp)
.L8010B224:
/* B823C4 8010B224 261020D8 */ addiu $s0, $s0, 0x20d8
/* B823C8 8010B228 34018000 */ li $at, 32768
/* B823CC 8010B22C 02016021 */ addu $t4, $s0, $at
/* B823D0 8010B230 AFAC002C */ sw $t4, 0x2c($sp)
/* B823D4 8010B234 958362F8 */ lhu $v1, 0x62f8($t4)
/* B823D8 8010B238 2401000C */ li $at, 12
/* B823DC 8010B23C 3C0E8012 */ lui $t6, %hi(gBitFlags+8) # $t6, 0x8012
/* B823E0 8010B240 1461000B */ bne $v1, $at, .L8010B270
/* B823E4 8010B244 3C0F8012 */ lui $t7, %hi(gEquipShifts) # $t7, 0x8012
/* B823E8 8010B248 8DCE7128 */ lw $t6, %lo(gBitFlags+8)($t6)
/* B823EC 8010B24C 91EF71F0 */ lbu $t7, %lo(gEquipShifts)($t7)
/* B823F0 8010B250 94B9009C */ lhu $t9, 0x9c($a1)
/* B823F4 8010B254 01EEC004 */ sllv $t8, $t6, $t7
/* B823F8 8010B258 03194824 */ and $t1, $t8, $t9
/* B823FC 8010B25C 51200005 */ beql $t1, $zero, .L8010B274
/* B82400 8010B260 240100B4 */ li $at, 180
/* B82404 8010B264 2407000B */ li $a3, 11
/* B82408 8010B268 1000000A */ b .L8010B294
/* B8240C 8010B26C 2402000B */ li $v0, 11
.L8010B270:
/* B82410 8010B270 240100B4 */ li $at, 180
.L8010B274:
/* B82414 8010B274 54610008 */ bnel $v1, $at, .L8010B298
/* B82418 8010B278 24014077 */ li $at, 16503
/* B8241C 8010B27C 94AA0EE6 */ lhu $t2, 0xee6($a1)
/* B82420 8010B280 314B0040 */ andi $t3, $t2, 0x40
/* B82424 8010B284 51600004 */ beql $t3, $zero, .L8010B298
/* B82428 8010B288 24014077 */ li $at, 16503
/* B8242C 8010B28C 240700B5 */ li $a3, 181
/* B82430 8010B290 240200B5 */ li $v0, 181
.L8010B294:
/* B82434 8010B294 24014077 */ li $at, 16503
.L8010B298:
/* B82438 8010B298 1041000A */ beq $v0, $at, .L8010B2C4
/* B8243C 8010B29C 24040001 */ li $a0, 1
/* B82440 8010B2A0 2401407A */ li $at, 16506
/* B82444 8010B2A4 10410007 */ beq $v0, $at, .L8010B2C4
/* B82448 8010B2A8 24012061 */ li $at, 8289
/* B8244C 8010B2AC 10410005 */ beq $v0, $at, .L8010B2C4
/* B82450 8010B2B0 24015035 */ li $at, 20533
/* B82454 8010B2B4 10410003 */ beq $v0, $at, .L8010B2C4
/* B82458 8010B2B8 240140AC */ li $at, 16556
/* B8245C 8010B2BC 5441000B */ bnel $v0, $at, .L8010B2EC
/* B82460 8010B2C0 26017FFF */ addiu $at, $s0, 0x7fff
.L8010B2C4:
/* B82464 8010B2C4 AFA20030 */ sw $v0, 0x30($sp)
/* B82468 8010B2C8 0C020978 */ jal Interface_ChangeAlpha
/* B8246C 8010B2CC A7A7004E */ sh $a3, 0x4e($sp)
/* B82470 8010B2D0 3C058016 */ lui $a1, %hi(gSaveContext) # $a1, 0x8016
/* B82474 8010B2D4 3C088015 */ lui $t0, %hi(D_8014B308) # $t0, 0x8015
/* B82478 8010B2D8 2508B308 */ addiu $t0, %lo(D_8014B308) # addiu $t0, $t0, -0x4cf8
/* B8247C 8010B2DC 24A5E660 */ addiu $a1, %lo(gSaveContext) # addiu $a1, $a1, -0x19a0
/* B82480 8010B2E0 8FA20030 */ lw $v0, 0x30($sp)
/* B82484 8010B2E4 97A7004E */ lhu $a3, 0x4e($sp)
/* B82488 8010B2E8 26017FFF */ addiu $at, $s0, 0x7fff
.L8010B2EC:
/* B8248C 8010B2EC A42762F9 */ sh $a3, 0x62f9($at)
/* B82490 8010B2F0 24012030 */ li $at, 8240
/* B82494 8010B2F4 14410013 */ bne $v0, $at, .L8010B344
/* B82498 8010B2F8 3C048015 */ lui $a0, %hi(D_80154230) # $a0, 0x8015
/* B8249C 8010B2FC 24844230 */ addiu $a0, %lo(D_80154230) # addiu $a0, $a0, 0x4230
/* B824A0 8010B300 0C00084C */ jal osSyncPrintf
/* B824A4 8010B304 A7A7004E */ sh $a3, 0x4e($sp)
/* B824A8 8010B308 3C048015 */ lui $a0, %hi(D_80154238) # $a0, 0x8015
/* B824AC 8010B30C 0C00084C */ jal osSyncPrintf
/* B824B0 8010B310 24844238 */ addiu $a0, %lo(D_80154238) # addiu $a0, $a0, 0x4238
/* B824B4 8010B314 3C048015 */ lui $a0, %hi(D_80154290) # $a0, 0x8015
/* B824B8 8010B318 0C00084C */ jal osSyncPrintf
/* B824BC 8010B31C 24844290 */ addiu $a0, %lo(D_80154290) # addiu $a0, $a0, 0x4290
/* B824C0 8010B320 3C058016 */ lui $a1, %hi(gSaveContext) # $a1, 0x8016
/* B824C4 8010B324 24A5E660 */ addiu $a1, %lo(gSaveContext) # addiu $a1, $a1, -0x19a0
/* B824C8 8010B328 3C088015 */ lui $t0, %hi(D_8014B308) # $t0, 0x8015
/* B824CC 8010B32C 97A7004E */ lhu $a3, 0x4e($sp)
/* B824D0 8010B330 2508B308 */ addiu $t0, %lo(D_8014B308) # addiu $t0, $t0, -0x4cf8
/* B824D4 8010B334 A4A01400 */ sh $zero, 0x1400($a1)
/* B824D8 8010B338 A4A013FE */ sh $zero, 0x13fe($a1)
/* B824DC 8010B33C A4A013FC */ sh $zero, 0x13fc($a1)
/* B824E0 8010B340 A4A013FA */ sh $zero, 0x13fa($a1)
.L8010B344:
/* B824E4 8010B344 850C0000 */ lh $t4, ($t0)
/* B824E8 8010B348 8FA40048 */ lw $a0, 0x48($sp)
/* B824EC 8010B34C 51800018 */ beql $t4, $zero, .L8010B3B0
/* B824F0 8010B350 90A21409 */ lbu $v0, 0x1409($a1)
/* B824F4 8010B354 0C041D8A */ jal func_80107628
/* B824F8 8010B358 30E5FFFF */ andi $a1, $a3, 0xffff
/* B824FC 8010B35C 8FA20048 */ lw $v0, 0x48($sp)
/* B82500 8010B360 26017FFF */ addiu $at, $s0, 0x7fff
/* B82504 8010B364 3C0F0097 */ lui $t7, %hi(_staff_message_data_staticSegmentRomStart) # $t7, 0x97
/* B82508 8010B368 8C4D2204 */ lw $t5, 0x2204($v0)
/* B8250C 8010B36C 25EF3000 */ addiu $t7, %lo(_staff_message_data_staticSegmentRomStart) # addiu $t7, $t7, 0x3000
/* B82510 8010B370 3C078015 */ lui $a3, %hi(D_80154294) # $a3, 0x8015
/* B82514 8010B374 AC2D6301 */ sw $t5, 0x6301($at)
/* B82518 8010B378 8C4E2200 */ lw $t6, 0x2200($v0)
/* B8251C 8010B37C 3401DC88 */ li $at, 56456
/* B82520 8010B380 241807A2 */ li $t8, 1954
/* B82524 8010B384 24422200 */ addiu $v0, $v0, 0x2200
/* B82528 8010B388 8C460004 */ lw $a2, 4($v0)
/* B8252C 8010B38C AFA20030 */ sw $v0, 0x30($sp)
/* B82530 8010B390 AFB80010 */ sw $t8, 0x10($sp)
/* B82534 8010B394 00412021 */ addu $a0, $v0, $at
/* B82538 8010B398 24E74294 */ addiu $a3, %lo(D_80154294) # addiu $a3, $a3, 0x4294
/* B8253C 8010B39C 0C0006A8 */ jal DmaMgr_SendRequest1
/* B82540 8010B3A0 01CF2821 */ addu $a1, $t6, $t7
/* B82544 8010B3A4 1000004A */ b .L8010B4D0
/* B82548 8010B3A8 8FA20030 */ lw $v0, 0x30($sp)
/* B8254C 8010B3AC 90A21409 */ lbu $v0, 0x1409($a1)
.L8010B3B0:
/* B82550 8010B3B0 8FA40048 */ lw $a0, 0x48($sp)
/* B82554 8010B3B4 24010001 */ li $at, 1
/* B82558 8010B3B8 14400017 */ bnez $v0, .L8010B418
/* B8255C 8010B3BC 00000000 */ nop
/* B82560 8010B3C0 0C041D12 */ jal func_80107448
/* B82564 8010B3C4 30E5FFFF */ andi $a1, $a3, 0xffff
/* B82568 8010B3C8 8FA20048 */ lw $v0, 0x48($sp)
/* B8256C 8010B3CC 26017FFF */ addiu $at, $s0, 0x7fff
/* B82570 8010B3D0 3C0A008C */ lui $t2, %hi(_nes_message_data_staticSegmentRomStart) # $t2, 0x8c
/* B82574 8010B3D4 8C592204 */ lw $t9, 0x2204($v0)
/* B82578 8010B3D8 254A6000 */ addiu $t2, %lo(_nes_message_data_staticSegmentRomStart) # addiu $t2, $t2, 0x6000
/* B8257C 8010B3DC 3C078015 */ lui $a3, %hi(D_801542A8) # $a3, 0x8015
/* B82580 8010B3E0 AC396301 */ sw $t9, 0x6301($at)
/* B82584 8010B3E4 8C492200 */ lw $t1, 0x2200($v0)
/* B82588 8010B3E8 3401DC88 */ li $at, 56456
/* B8258C 8010B3EC 240B07AE */ li $t3, 1966
/* B82590 8010B3F0 24422200 */ addiu $v0, $v0, 0x2200
/* B82594 8010B3F4 8C460004 */ lw $a2, 4($v0)
/* B82598 8010B3F8 AFA20030 */ sw $v0, 0x30($sp)
/* B8259C 8010B3FC AFAB0010 */ sw $t3, 0x10($sp)
/* B825A0 8010B400 00412021 */ addu $a0, $v0, $at
/* B825A4 8010B404 24E742A8 */ addiu $a3, %lo(D_801542A8) # addiu $a3, $a3, 0x42a8
/* B825A8 8010B408 0C0006A8 */ jal DmaMgr_SendRequest1
/* B825AC 8010B40C 012A2821 */ addu $a1, $t1, $t2
/* B825B0 8010B410 1000002F */ b .L8010B4D0
/* B825B4 8010B414 8FA20030 */ lw $v0, 0x30($sp)
.L8010B418:
/* B825B8 8010B418 14410018 */ bne $v0, $at, .L8010B47C
/* B825BC 8010B41C 8FA40048 */ lw $a0, 0x48($sp)
/* B825C0 8010B420 8FA40048 */ lw $a0, 0x48($sp)
/* B825C4 8010B424 0C041D12 */ jal func_80107448
/* B825C8 8010B428 30E5FFFF */ andi $a1, $a3, 0xffff
/* B825CC 8010B42C 8FA20048 */ lw $v0, 0x48($sp)
/* B825D0 8010B430 26017FFF */ addiu $at, $s0, 0x7fff
/* B825D4 8010B434 3C0E0090 */ lui $t6, %hi(_ger_message_data_staticSegmentRomStart) # $t6, 0x90
/* B825D8 8010B438 8C4C2204 */ lw $t4, 0x2204($v0)
/* B825DC 8010B43C 25CEF000 */ addiu $t6, %lo(_ger_message_data_staticSegmentRomStart) # addiu $t6, $t6, -0x1000
/* B825E0 8010B440 3C078015 */ lui $a3, %hi(D_801542BC) # $a3, 0x8015
/* B825E4 8010B444 AC2C6301 */ sw $t4, 0x6301($at)
/* B825E8 8010B448 8C4D2200 */ lw $t5, 0x2200($v0)
/* B825EC 8010B44C 3401DC88 */ li $at, 56456
/* B825F0 8010B450 240F07BA */ li $t7, 1978
/* B825F4 8010B454 24422200 */ addiu $v0, $v0, 0x2200
/* B825F8 8010B458 8C460004 */ lw $a2, 4($v0)
/* B825FC 8010B45C AFA20030 */ sw $v0, 0x30($sp)
/* B82600 8010B460 AFAF0010 */ sw $t7, 0x10($sp)
/* B82604 8010B464 00412021 */ addu $a0, $v0, $at
/* B82608 8010B468 24E742BC */ addiu $a3, %lo(D_801542BC) # addiu $a3, $a3, 0x42bc
/* B8260C 8010B46C 0C0006A8 */ jal DmaMgr_SendRequest1
/* B82610 8010B470 01AE2821 */ addu $a1, $t5, $t6
/* B82614 8010B474 10000016 */ b .L8010B4D0
/* B82618 8010B478 8FA20030 */ lw $v0, 0x30($sp)
.L8010B47C:
/* B8261C 8010B47C 0C041D12 */ jal func_80107448
/* B82620 8010B480 30E5FFFF */ andi $a1, $a3, 0xffff
/* B82624 8010B484 8FA20048 */ lw $v0, 0x48($sp)
/* B82628 8010B488 26017FFF */ addiu $at, $s0, 0x7fff
/* B8262C 8010B48C 3C090094 */ lui $t1, %hi(_fra_message_data_staticSegmentRomStart) # $t1, 0x94
/* B82630 8010B490 8C582204 */ lw $t8, 0x2204($v0)
/* B82634 8010B494 2529B000 */ addiu $t1, %lo(_fra_message_data_staticSegmentRomStart) # addiu $t1, $t1, -0x5000
/* B82638 8010B498 3C078015 */ lui $a3, %hi(D_801542D0) # $a3, 0x8015
/* B8263C 8010B49C AC386301 */ sw $t8, 0x6301($at)
/* B82640 8010B4A0 8C592200 */ lw $t9, 0x2200($v0)
/* B82644 8010B4A4 3401DC88 */ li $at, 56456
/* B82648 8010B4A8 240A07C6 */ li $t2, 1990
/* B8264C 8010B4AC 24422200 */ addiu $v0, $v0, 0x2200
/* B82650 8010B4B0 8C460004 */ lw $a2, 4($v0)
/* B82654 8010B4B4 AFA20030 */ sw $v0, 0x30($sp)
/* B82658 8010B4B8 AFAA0010 */ sw $t2, 0x10($sp)
/* B8265C 8010B4BC 00412021 */ addu $a0, $v0, $at
/* B82660 8010B4C0 24E742D0 */ addiu $a3, %lo(D_801542D0) # addiu $a3, $a3, 0x42d0
/* B82664 8010B4C4 0C0006A8 */ jal DmaMgr_SendRequest1
/* B82668 8010B4C8 03292821 */ addu $a1, $t9, $t1
/* B8266C 8010B4CC 8FA20030 */ lw $v0, 0x30($sp)
.L8010B4D0:
/* B82670 8010B4D0 904B0008 */ lbu $t3, 8($v0)
/* B82674 8010B4D4 26017FFF */ addiu $at, $s0, 0x7fff
/* B82678 8010B4D8 3C048015 */ lui $a0, %hi(D_801542E4) # $a0, 0x8015
/* B8267C 8010B4DC A02B62FD */ sb $t3, 0x62fd($at)
/* B82680 8010B4E0 8FAC002C */ lw $t4, 0x2c($sp)
/* B82684 8010B4E4 248442E4 */ addiu $a0, %lo(D_801542E4) # addiu $a0, $a0, 0x42e4
/* B82688 8010B4E8 918D62FC */ lbu $t5, 0x62fc($t4)
/* B8268C 8010B4EC 000D7103 */ sra $t6, $t5, 4
/* B82690 8010B4F0 A02E62FE */ sb $t6, 0x62fe($at)
/* B82694 8010B4F4 8FAF002C */ lw $t7, 0x2c($sp)
/* B82698 8010B4F8 91F862FC */ lbu $t8, 0x62fc($t7)
/* B8269C 8010B4FC 3319000F */ andi $t9, $t8, 0xf
/* B826A0 8010B500 A03962FF */ sb $t9, 0x62ff($at)
/* B826A4 8010B504 8FA9002C */ lw $t1, 0x2c($sp)
/* B826A8 8010B508 912562FD */ lbu $a1, 0x62fd($t1)
/* B826AC 8010B50C 0C00084C */ jal osSyncPrintf
/* B826B0 8010B510 A7A5003E */ sh $a1, 0x3e($sp)
/* B826B4 8010B514 87A3003E */ lh $v1, 0x3e($sp)
/* B826B8 8010B518 8FAA002C */ lw $t2, 0x2c($sp)
/* B826BC 8010B51C 3C0C8015 */ lui $t4, %hi(D_80153C50) # $t4, 0x8015
/* B826C0 8010B520 28610004 */ slti $at, $v1, 4
/* B826C4 8010B524 10200046 */ beqz $at, .L8010B640
/* B826C8 8010B528 00035840 */ sll $t3, $v1, 1
/* B826CC 8010B52C 258C3C50 */ addiu $t4, %lo(D_80153C50) # addiu $t4, $t4, 0x3c50
/* B826D0 8010B530 016C1021 */ addu $v0, $t3, $t4
/* B826D4 8010B534 844D0000 */ lh $t5, ($v0)
/* B826D8 8010B538 3C0F008C */ lui $t7, %hi(_message_staticSegmentRomStart) # $t7, 0x8c
/* B826DC 8010B53C 25EFA000 */ addiu $t7, %lo(_message_staticSegmentRomStart) # addiu $t7, $t7, -0x6000
/* B826E0 8010B540 8D4462B0 */ lw $a0, 0x62b0($t2)
/* B826E4 8010B544 3C078015 */ lui $a3, %hi(D_801542F8) # $a3, 0x8015
/* B826E8 8010B548 241807D6 */ li $t8, 2006
/* B826EC 8010B54C 000D7300 */ sll $t6, $t5, 0xc
/* B826F0 8010B550 01CF2821 */ addu $a1, $t6, $t7
/* B826F4 8010B554 AFB80010 */ sw $t8, 0x10($sp)
/* B826F8 8010B558 24E742F8 */ addiu $a3, %lo(D_801542F8) # addiu $a3, $a3, 0x42f8
/* B826FC 8010B55C AFA20030 */ sw $v0, 0x30($sp)
/* B82700 8010B560 0C0006A8 */ jal DmaMgr_SendRequest1
/* B82704 8010B564 24061000 */ li $a2, 4096
/* B82708 8010B568 8FA20030 */ lw $v0, 0x30($sp)
/* B8270C 8010B56C 3C198015 */ lui $t9, %hi(D_80153C50) # $t9, 0x8015
/* B82710 8010B570 27393C50 */ addiu $t9, %lo(D_80153C50) # addiu $t9, $t9, 0x3c50
/* B82714 8010B574 14590006 */ bne $v0, $t9, .L8010B590
/* B82718 8010B578 3C098015 */ lui $t1, %hi(D_80153C52) # $t1, 0x8015
/* B8271C 8010B57C 26017FFF */ addiu $at, $s0, 0x7fff
/* B82720 8010B580 A42063FF */ sh $zero, 0x63ff($at)
/* B82724 8010B584 A4206401 */ sh $zero, 0x6401($at)
/* B82728 8010B588 1000001A */ b .L8010B5F4
/* B8272C 8010B58C A4206403 */ sh $zero, 0x6403($at)
.L8010B590:
/* B82730 8010B590 25293C52 */ addiu $t1, %lo(D_80153C52) # addiu $t1, $t1, 0x3c52
/* B82734 8010B594 14490009 */ bne $v0, $t1, .L8010B5BC
/* B82738 8010B598 3C0D8015 */ lui $t5, %hi(D_80153C54) # $t5, 0x8015
/* B8273C 8010B59C 26017FFF */ addiu $at, $s0, 0x7fff
/* B82740 8010B5A0 240A0046 */ li $t2, 70
/* B82744 8010B5A4 240B0032 */ li $t3, 50
/* B82748 8010B5A8 240C001E */ li $t4, 30
/* B8274C 8010B5AC A42A63FF */ sh $t2, 0x63ff($at)
/* B82750 8010B5B0 A42B6401 */ sh $t3, 0x6401($at)
/* B82754 8010B5B4 1000000F */ b .L8010B5F4
/* B82758 8010B5B8 A42C6403 */ sh $t4, 0x6403($at)
.L8010B5BC:
/* B8275C 8010B5BC 25AD3C54 */ addiu $t5, %lo(D_80153C54) # addiu $t5, $t5, 0x3c54
/* B82760 8010B5C0 144D0008 */ bne $v0, $t5, .L8010B5E4
/* B82764 8010B5C4 241800FF */ li $t8, 255
/* B82768 8010B5C8 26017FFF */ addiu $at, $s0, 0x7fff
/* B8276C 8010B5CC 240E000A */ li $t6, 10
/* B82770 8010B5D0 240F0032 */ li $t7, 50
/* B82774 8010B5D4 A42063FF */ sh $zero, 0x63ff($at)
/* B82778 8010B5D8 A42E6401 */ sh $t6, 0x6401($at)
/* B8277C 8010B5DC 10000005 */ b .L8010B5F4
/* B82780 8010B5E0 A42F6403 */ sh $t7, 0x6403($at)
.L8010B5E4:
/* B82784 8010B5E4 26017FFF */ addiu $at, $s0, 0x7fff
/* B82788 8010B5E8 A43863FF */ sh $t8, 0x63ff($at)
/* B8278C 8010B5EC A4206401 */ sh $zero, 0x6401($at)
/* B82790 8010B5F0 A4206403 */ sh $zero, 0x6403($at)
.L8010B5F4:
/* B82794 8010B5F4 3C198015 */ lui $t9, %hi(D_80153C52) # $t9, 0x8015
/* B82798 8010B5F8 27393C52 */ addiu $t9, %lo(D_80153C52) # addiu $t9, $t9, 0x3c52
/* B8279C 8010B5FC 14590005 */ bne $v0, $t9, .L8010B614
/* B827A0 8010B600 3C0A8015 */ lui $t2, %hi(D_80153C56) # $t2, 0x8015
/* B827A4 8010B604 240900E6 */ li $t1, 230
/* B827A8 8010B608 26017FFF */ addiu $at, $s0, 0x7fff
/* B827AC 8010B60C 1000000A */ b .L8010B638
/* B827B0 8010B610 A4296405 */ sh $t1, 0x6405($at)
.L8010B614:
/* B827B4 8010B614 254A3C56 */ addiu $t2, %lo(D_80153C56) # addiu $t2, $t2, 0x3c56
/* B827B8 8010B618 144A0005 */ bne $v0, $t2, .L8010B630
/* B827BC 8010B61C 240C00AA */ li $t4, 170
/* B827C0 8010B620 240B00B4 */ li $t3, 180
/* B827C4 8010B624 26017FFF */ addiu $at, $s0, 0x7fff
/* B827C8 8010B628 10000003 */ b .L8010B638
/* B827CC 8010B62C A42B6405 */ sh $t3, 0x6405($at)
.L8010B630:
/* B827D0 8010B630 26017FFF */ addiu $at, $s0, 0x7fff
/* B827D4 8010B634 A42C6405 */ sh $t4, 0x6405($at)
.L8010B638:
/* B827D8 8010B638 26017FFF */ addiu $at, $s0, 0x7fff
/* B827DC 8010B63C A4206407 */ sh $zero, 0x6407($at)
.L8010B640:
/* B827E0 8010B640 26017FFF */ addiu $at, $s0, 0x7fff
/* B827E4 8010B644 A02063E5 */ sb $zero, 0x63e5($at)
/* B827E8 8010B648 8FAD002C */ lw $t5, 0x2c($sp)
/* B827EC 8010B64C 91A263E4 */ lbu $v0, 0x63e4($t5)
/* B827F0 8010B650 A42063D3 */ sh $zero, 0x63d3($at)
/* B827F4 8010B654 A42263D7 */ sh $v0, 0x63d7($at)
/* B827F8 8010B658 A02263E7 */ sb $v0, 0x63e7($at)
/* B827FC 8010B65C 8FAE002C */ lw $t6, 0x2c($sp)
/* B82800 8010B660 95C263D2 */ lhu $v0, 0x63d2($t6)
/* B82804 8010B664 A42263D1 */ sh $v0, 0x63d1($at)
/* B82808 8010B668 A42263CF */ sh $v0, 0x63cf($at)
/* B8280C 8010B66C 8FBF0024 */ lw $ra, 0x24($sp)
/* B82810 8010B670 8FB00020 */ lw $s0, 0x20($sp)
/* B82814 8010B674 27BD0048 */ addiu $sp, $sp, 0x48
/* B82818 8010B678 03E00008 */ jr $ra
/* B8281C 8010B67C 00000000 */ nop
| {
"language": "Assembly"
} |
#
# RT-Mutex test
#
# Op: C(ommand)/T(est)/W(ait)
# | opcode
# | | threadid: 0-7
# | | | opcode argument
# | | | |
# C: lock: 0: 0
#
# Commands
#
# opcode opcode argument
# schedother nice value
# schedfifo priority
# lock lock nr (0-7)
# locknowait lock nr (0-7)
# lockint lock nr (0-7)
# lockintnowait lock nr (0-7)
# lockcont lock nr (0-7)
# unlock lock nr (0-7)
# lockbkl lock nr (0-7)
# unlockbkl lock nr (0-7)
# signal 0
# reset 0
# resetevent 0
#
# Tests / Wait
#
# opcode opcode argument
#
# prioeq priority
# priolt priority
# priogt priority
# nprioeq normal priority
# npriolt normal priority
# npriogt normal priority
# locked lock nr (0-7)
# blocked lock nr (0-7)
# blockedwake lock nr (0-7)
# unlocked lock nr (0-7)
# lockedbkl dont care
# blockedbkl dont care
# unlockedbkl dont care
# opcodeeq command opcode or number
# opcodelt number
# opcodegt number
# eventeq number
# eventgt number
# eventlt number
#
# 2 threads 1 lock
#
C: resetevent: 0: 0
W: opcodeeq: 0: 0
# Set schedulers
C: schedfifo: 0: 80
C: schedfifo: 1: 80
# T0 lock L0
C: locknowait: 0: 0
C: locknowait: 1: 0
W: locked: 0: 0
W: blocked: 1: 0
T: prioeq: 0: 80
# T0 unlock L0
C: unlock: 0: 0
W: locked: 1: 0
# Verify T0
W: unlocked: 0: 0
T: prioeq: 0: 80
# Unlock
C: unlock: 1: 0
W: unlocked: 1: 0
# T1,T0 lock L0
C: locknowait: 1: 0
C: locknowait: 0: 0
W: locked: 1: 0
W: blocked: 0: 0
T: prioeq: 1: 80
# T1 unlock L0
C: unlock: 1: 0
W: locked: 0: 0
# Verify T1
W: unlocked: 1: 0
T: prioeq: 1: 80
# Unlock and exit
C: unlock: 0: 0
W: unlocked: 0: 0
| {
"language": "Assembly"
} |
;;; TOOL: run-interp
(module
(func $f (param i32) (result i32)
block $default
block $2
block $1
block $0
get_local 0
br_table $0 $1 $2 $default
end
;; 0
i32.const 0
return
end
;; 1
i32.const 1
return
end
end
;; 2, fallthrough
;; default
i32.const 2
return)
(func (export "test0") (result i32)
i32.const 0
call $f)
(func (export "test1") (result i32)
i32.const 1
call $f)
(func (export "test2") (result i32)
i32.const 2
call $f)
(func (export "test3") (result i32)
i32.const 3
call $f))
(;; STDOUT ;;;
test0() => i32:0
test1() => i32:1
test2() => i32:2
test3() => i32:2
;;; STDOUT ;;)
| {
"language": "Assembly"
} |
-- DISTRIBUTE_RESULT |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- ASSIGN |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- HYBRID_HASH_JOIN [$$30][$$20] |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- DATASOURCE_SCAN |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- EMPTY_TUPLE_SOURCE |PARTITIONED|
-- HASH_PARTITION_EXCHANGE [$$20] |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- STREAM_SELECT |PARTITIONED|
-- ASSIGN |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- BTREE_SEARCH |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- STABLE_SORT [$$35(ASC)] |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- LENGTH_PARTITIONED_INVERTED_INDEX_SEARCH |PARTITIONED|
-- BROADCAST_EXCHANGE |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- ASSIGN |PARTITIONED|
-- STREAM_PROJECT |PARTITIONED|
-- ASSIGN |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- DATASOURCE_SCAN |PARTITIONED|
-- ONE_TO_ONE_EXCHANGE |PARTITIONED|
-- EMPTY_TUPLE_SOURCE |PARTITIONED|
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-feature +altivec -ffreestanding -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-feature +altivec -ffreestanding -emit-llvm -fno-lax-vector-conversions -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -target-feature +altivec -ffreestanding -emit-llvm -x c++ -o - %s | FileCheck %s
#include <altivec.h>
// Verify that simply including <altivec.h> does not generate any code
// (i.e. all inline routines in the header are marked "static")
// CHECK: target triple = "powerpc64-
// CHECK-NEXT: {{^$}}
// CHECK-NEXT: {{llvm\..*}}
| {
"language": "Assembly"
} |
; https://bugs.llvm.org/show_bug.cgi?id=4374
; TEST-ARGS: -disable-undef-input
define float @src(float %a, float %b) nounwind {
entry:
%tmp3 = fsub float %a, %b ; <float> [#uses=1]
%tmp4 = fsub float -0.000000e+00, %tmp3 ; <float> [#uses=1]
ret float %tmp4
}
define float @tgt(float %a, float %b) nounwind {
entry:
%tmp3 = fsub float %b, %a ; <float> [#uses=1]
ret float %tmp3
}
; ERROR: Value mismatch
| {
"language": "Assembly"
} |
/* Copyright (C) 1997-2016 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#ifndef _SYS_PCI_H
#define _SYS_PCI_H 1
/* We use the constants from the kernel. */
#include <linux/pci.h>
#endif /* sys/pci.h */
| {
"language": "Assembly"
} |
COMMENT @----------------------------------------------------------------------
Copyright (c) GeoWorks 1989 -- All Rights Reserved
PROJECT: PC GEOS
MODULE: Kernel/Object
FILE: objectReloc.asm
ROUTINES:
Name Description
---- -----------
INT ObjRelocate Relocate an object
INT ObjUnRelocate Un-relocate an object
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 2/89 Initial version
DESCRIPTION:
This file contains routines to load a GEODE and execute it.
$Id: objectReloc.asm,v 1.1 97/04/05 01:14:31 newdeal Exp $
------------------------------------------------------------------------------@
ObjectLoad segment resource
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocateObjBlock
DESCRIPTION: Relocate all objects in an object block
CALLED BY: INTERNAL
FullObjLock
PASS:
ds - segment of block to relocate
cx - VMRelocType:
VMRT_UNRELOCATE_BEFORE_WRITE
VMRT_RELOCATE_AFTER_READ
VMRT_RELOCATE_AFTER_WRITE
VMRT_LOADED_FROM_RESOURCE
RETURN:
carry - set if error (non-ec only)
DESTROYED:
ax, bx, cx, dx, si, di, bp
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
RelocateObjBlock proc near
mov dx, cx ;dx = type
push es
; set the LMEM bit for the handle *now* so EC code won't die. doesn't
; seem to be any advantage to doing this at the end as it was before...
mov bx,ds:[LMBH_handle]
LoadVarSeg es
BitSet es:[bx].HM_flags, HF_LMEM
if MOVABLE_CORE_BLOCKS
call LockOwnersCoreBlockAndLibraries
endif
segmov es,ds
push ds:[OLMBH_inUseCount] ;save count
mov ds:[OLMBH_inUseCount],offset RelocateLow
; relocate the object block output
call RelocOutput
; for (each chunk in block) {
mov si,ds:LMBH_offset ;si points at handle
mov cx,ds:LMBH_nHandles ;cx is a counter
mov bp,ds:[si] ;ds:bp = flags for block
;ds = es
;ds:si - current position in handle table
;ds:bp - current position in flags table
;cx - count
relloop:
mov di,es:[si]
inc di
jz next
dec di
jz next
; if (OCF_IS_OBJECT) {
; ObjRelocate(chunk)
mov al, es:[bp]
test al, mask OCF_IS_OBJECT
jz next
call RelocOrUnRelocObj
jc error
next:
add si,2
inc bp
loop relloop
segmov ds,es
pop ds:[OLMBH_inUseCount] ;recover count
BitSet ds:[LMBH_flags],LMF_RELOCATED
pop es
EC < call ECLMemValidateHeapFar >
clc
NEC<done: >
if MOVABLE_CORE_BLOCKS
mov bx, ds:[LMBH_handle]
call UnlockOwnersCoreBlockAndLibraries
endif
ret
error:
NEC < segmov ds,es ; return segment in ds >
NEC < pop es:[OLMBH_inUseCount] ; recover count >
NEC < pop es ; and ES >
NEC < jmp done ; Exit w/carry set >
EC < ERROR CANNOT_RELOCATE >
RelocateObjBlock endp
COMMENT @----------------------------------------------------------------------
FUNCTION: UnRelocateObjBlock
DESCRIPTION: UnRelocate all objects in an object block
CALLED BY: INTERNAL
DetachObjBlock
PASS:
ds - segment of block to relocate
cx - VMRelocType:
VMRT_UNRELOCATE_BEFORE_WRITE
VMRT_RELOCATE_AFTER_READ
VMRT_RELOCATE_AFTER_WRITE
VMRT_LOADED_FROM_RESOURCE
RETURN:
carry - set if error (non-ec only)
DESTROYED:
ax, bx, cx, dx, si, di, bp
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
UnRelocateObjBlock proc far
mov dx, cx ;dx = type
push es
segmov es,ds
if MOVABLE_CORE_BLOCKS
mov bx, ds:[LMBH_handle]
call LockOwnersCoreBlockAndLibraries
endif
BitClr ds:[LMBH_flags],LMF_RELOCATED
push ds:[OLMBH_inUseCount] ;save count
mov ds:[OLMBH_inUseCount],offset UnRelocateLow
; for (each chunk in block) {
mov si,ds:LMBH_offset ;si points at handle
mov cx,ds:LMBH_nHandles ;cx is a counter
mov bp,ds:[si] ;ds:bp = flags for block
;ds:si - current position in handle table
;ds:bp - current position in flags table
;cx - count
Uloop:
mov di,es:[si] ;ES:DI <- addr of chunk
inc di ;If DI was -1, block is empty
jz Unext ; so go to next.
dec di ;If DI was 0, block is freed,
jz Unext ; so go to next.
; if (OCF_IS_OBJECT) {
; ObjRelocate(chunk)
mov al, es:[bp]
test al, mask OCF_IS_OBJECT
jz Unext
call RelocOrUnRelocObj
jc error
Unext:
add si,2 ;Go to the next chunk
inc bp ;go to next flag
loop Uloop ;branch
segmov ds,es
; relocate the object block output (after doing the objects)
call RelocOutput
pop ds:[OLMBH_inUseCount] ;recover count
clc ;no erro
pop es
NEC <done: >
mov bx, ds:[LMBH_handle]
call UnlockOwnersCoreBlockAndLibraries
ret
error:
NEC < segmov ds,es ;return segment in ds >
NEC < pop ds:[OLMBH_inUseCount] ;recover inUseCount >
NEC < pop es ; and ES >
NEC < jmp done >
EC < ERROR CANNOT_UNRELOCATE >
UnRelocateObjBlock endp
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocOutput
DESCRIPTION: Relocate the output field of an object block
CALLED BY: INTERNAL
PASS:
ds - object block
es:[OLMBH_inUseCount] - routine to call (Reloc or UnReloc)
RETURN:
none
DESTROYED:
ax,bx,cx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 6/30/92 Initial version
------------------------------------------------------------------------------@
RelocOutput proc near
uses dx
.enter
movdw cxdx, ds:[OLMBH_output]
mov bx, ds:[LMBH_handle]
mov al, RELOC_HANDLE
call es:[OLMBH_inUseCount]
movdw ds:[OLMBH_output], cxdx
.leave
ret
RelocOutput endp
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocOrUnRelocObj
DESCRIPTION: Relocate an object
CALLED BY: INTERNAL
PASS:
es:[OLMBH_inUseCount] - routine to call (Reloc or UnReloc)
*es:si - object
al - ObjChunkFlags
dx - VMRelocType:
VMRT_UNRELOCATE_BEFORE_WRITE
VMRT_RELOCATE_AFTER_READ
VMRT_RELOCATE_AFTER_WRITE
RETURN:
none
DESTROYED:
ax, bx, di, ds
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
RelocOrUnRelocObj proc near uses cx, dx, si, bp, es
; "object" is used by RelocOrUnRelocClass()
.warn -unref_local
object local lptr \
push si
.warn @unref_local
relocType local VMRelocType \
push dx
objflags local word \
push ax
classoff local nptr
vdStart local word
vdEnd local word
ForceRef vdEnd
ForceRef relocType
ForceRef objflags
ForceRef classoff
.enter
EC < cmp es:[OLMBH_inUseCount], offset RelocateLow >
EC < je checkAfter >
EC < segxchg ds, es >
EC < call ECCheckLMemObject >
EC < segxchg ds, es >
EC <checkAfter: >
mov bx,es:[si] ;es:bx = object
call RelocOrUnRelocAndLoadClass ;ds:si = class
NEC < LONG jc done >
EC < cmp es:[OLMBH_inUseCount], offset RelocateLow >
EC < jne alreadyChecked >
EC < segxchg ds, es >
EC < push si >
EC < mov si, object >
EC < call ECCheckLMemObject >
EC < pop si >
EC < segxchg ds, es >
EC <alreadyChecked: >
; figure start and end of vardata for any relocations there may be
; in there while we've got the bottom class handy..
mov di, ds:[si].Class_masterOffset
tst di ; any master parts?
jz addInstanceSize ; no -- vardata comes after instance
; data for bottom class
mov ax, es:[bx][di] ; ax <- value in master offset
inc di ; assume no data for final master part
inc di ; so vardata starts after base struct
; (which assumes that master parts are
; built from the bottom up...)
tst ax ; correct?
jz haveStart ; yes, so di is start of vardata
mov_tr di, ax ; no. use start of last master part
; as thing to which to add size of
; last master part to get start of
; var data
addInstanceSize:
add di, ds:[si].Class_instanceSize
haveStart:
add di, bx
mov ss:[vdStart], di
; loop to do all classes - ds:si = class
call RelocOrUnRelocClass
NEC <done: >
.leave
ret
RelocOrUnRelocObj endp
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocOrUnRelocClass
DESCRIPTION: Relocate or unrelocate at the class level
CALLED BY: INTERNAL
PASS:
ds:si - class
es - block containing object
ss:bp - inherited variables
RETURN:
carry - set if error
DESTROYED:
ax, bx, cx, dx, si, di, ds
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 8/24/92 Initial version
------------------------------------------------------------------------------@
RelocOrUnRelocClass proc far
.enter inherit RelocOrUnRelocObj
EC < tst ds:[si].Class_superClass.segment ; MetaClass? >
EC < jz classOK ; yes => must have no relocation table, so ok >
EC < test ds:[si].Class_flags, mask CLASSF_NEVER_SAVED >
EC < ERROR_NZ CLASS_AT_DS_SI_MARKED_NEVER_SAVED_SO_WHY_AM_I_RELOCATING_OR_UNRELOCATING_IT_BUB? >
EC <classOK: >
test ds:[si].Class_flags, mask CLASSF_HAS_RELOC
LONG jz noCustomRelocation
; send method to object to relocate itsself (for this class's part)
; this message will call Reloc
push bp
mov dx, relocType
segxchg ds, es ;es=class, ds = obj
mov di, si ;es:di = class
mov si, object ;*ds:si = object
; compute bx and di to pass
mov bp, di ;es:bp = class
mov ax,MSG_META_RELOCATE ;pass method in di. PCFOM
; will shift to ax for us.
cmp ds:[OLMBH_inUseCount],offset RelocateLow
jz 99$
mov ax,MSG_META_UNRELOCATE
99$:
mov ss:[TPD_dataAX], ax ;data to pass in AX
mov bx, ds:[si]
mov ss:[TPD_dataBX], bx ;data to pass in BX (base o'
; object
mov di, es:[bp].Class_masterOffset
tst di
jz 100$
add bx, ds:[bx][di] ;bx = di to send
100$:
mov di, bx
;
; Now point to the relocation handler's address, which is
; immediately after the method table (or the CMethodDef table that
; follows the method table for a C class).
;
mov bx, es:[bp].Class_methodCount ;calculate methodCount*6
mov cx, bx ; save *1
shl bx ;*2
add bx, cx ; bx = *3
mov cx, bx ; save for C class
shl bx ; *6
add bx, bp
test es:[bp].Class_flags, mask CLASSF_C_HANDLERS
pop bp ;bp = frame pointer
jnz callCHandler
mov ax, ({fptr.far}es:Class_methodTable[bx]).offset
mov bx, ({fptr.far}es:Class_methodTable[bx]).segment
call ProcCallFixedOrMovable
done:
EC < ERROR_C ERROR_RETURNED_BY_RELOCATION_HANDLER >
ret
callCHandler:
; C handler -- (pself, oself, message, VMRelocationType, frame)
inc cx ; round up to nearest word,
andnf cx, not 1 ; since that's what compilers
; like to do.
add bx, cx ; skip the CMethodDef table
push ds, di ; pass pself
push ds:[LMBH_handle], si ; pass oself
push ss:[TPD_dataAX] ; pass message
push dx ; pass reloc type
push bp ; pass inherited locals
segmov ds, es ; always a Good Thing to pass dgroup
; to a C routine (this assumes
; all C classes live in dgroup,
; of course, but we make that
; assumption elsewhere, too...)
mov ax, ({fptr.far}ds:Class_methodTable[bx]).offset
mov bx, ({fptr.far}ds:Class_methodTable[bx]).segment
call ProcCallFixedOrMovable
tst ax ;zero return (clears carry)?
jz done ;yes -- boogie
stc ;no -- indicate error by setting
; carry
EC < jmp done ;catch error in EC... >
NEC < ret ;return it in NEC... >
noCustomRelocation:
;
; If no custom relocation, than just obey the relocation table for
; the class, letting ObjRelocOrUnRelocSuper call us back for the
; super class.
;
.leave
mov di, object ;*es:di = object
segxchg ds, es
xchg si, di ;*ds:si = object, es:di = class
FALL_THRU ObjRelocOrUnRelocSuper
RelocOrUnRelocClass endp
COMMENT @----------------------------------------------------------------------
FUNCTION: ObjRelocOrUnRelocSuper
DESCRIPTION: Relocate an object's superclass
CALLED BY: INTERNAL
PASS:
*ds:si - object
bp - inherited variables
es:di - class
RETURN:
carry - set if error
DESTROYED:
ax, cx, dx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 8/24/92 Initial version
------------------------------------------------------------------------------@
ObjRelocOrUnRelocSuper proc far uses bx, si, di, ds, es
.enter inherit RelocOrUnRelocObj
segxchg ds, es
xchg si, di ;ds:si = class, *es:di = obj
mov classoff, si
; do instance data relocations
push ds:[si].Class_vdRelocTable
mov cx, ds:[si].Class_relocTable ;ds:si = reloc table
jcxz staticDataDone ;no relocations -- done
mov bx, es:[di] ;es:bx = object
mov di, ds:[si].Class_masterOffset ;compute instance offset
tst di
jz noMaster
mov si, es:[bx][di]
tst si
jz staticDataDone
add bx, si ;es:bx = instance
noMaster:
mov si, cx ;ds:si = table
; loop to do relocations -- ds:si = table, es:bx = object
relloop:
lodsb ;al = type
CheckHack <RELOC_END_OF_LIST eq 0>
tst al
jz staticDataDone
EC < cmp al,RELOC_LAST_LEGAL >
EC < ERROR_A BAD_RELOCATION_TYPE >
push bx
mov_tr cx, ax ;save type
lodsw
mov di, bx
add di, ax ;es:di = target
mov ax, cx ;ax = type
mov cx, es:[di] ;dx:cx = data at target
cmp al,RELOC_ENTRY_POINT ;RELOC_ENTRY_POINT does dword
je relEP ;branch to read/write dword
mov bx, es:[LMBH_handle] ;bx = object handle
call es:[OLMBH_inUseCount]
pop bx
LONG jc popSIDone ; Bail if error returned from
; lower level handler (*after*
; fixing stack!) -- Doug 5/17/93
mov_tr ax, cx ;store adjusted data
stosw
jmp relloop
relEP:
mov dx, es:[di][2]
mov bx, es:[LMBH_handle] ;bx = object handle
call es:[OLMBH_inUseCount]
pop bx
LONG jc popSIDone ; Bail if error returned from
; lower level handler (*after*
; fixing stack!) -- Doug 5/17/93
mov_tr ax, cx ;store adjusted data
stosw
mov_tr ax, dx
stosw
jmp relloop
; done with normal instance data relocations -- now do vardata
; instance relocations
staticDataDone:
pop si ;ds:si = table
tst si
jz toVardataDone
test objflags, mask OCF_VARDATA_RELOC
jnz doVardata
toVardataDone:
jmp vardataDone
doVardata:
; recompute the end of the vardata area
mov bx, object
mov bx, es:[bx]
ChunkSizePtr es, bx, ax
add ax, bx
mov ss:[vdEnd], ax
varrelloop:
lodsw ;al = type and tag
CheckHack <RELOC_END_OF_LIST eq 0>
test ax, mask VORT_RELOC_TYPE
jz vardataDoneLeap
mov_tr cx, ax ;cx = tag and type
lodsw ;ax = offset
xchg ax, cx ;ax = tag and type, cx = offset
mov bx, ss:[vdStart]
push si
mov si, ss:[vdEnd]
varrelFindLoop:
cmp bx, si ; hit end of vardata?
jae novardata ; yes
mov dx, es:[bx].VDE_dataType
mov di, dx ; see if all bits except
xor di, ax ; VarDataFlags are the same
and di, not mask VarDataFlags ; in both ax & dx, while
; preserving VDF_EXTRA_DATA
; in DX...
jz varrelFoundIt ; yes
inc bx ; assume no extra data
inc bx
test dx, mask VDF_EXTRA_DATA
jz varrelFindLoop
CheckHack <offset VDE_entrySize eq 2>
add bx, es:[bx]
dec bx
dec bx
jmp varrelFindLoop
varrelFoundIt:
EC < test es:[bx].VDE_dataType, mask VDF_EXTRA_DATA >
EC < ERROR_Z ILLEGAL_VARDATA_RELOCATION_OFFSET >
EC < push ax >
EC < mov ax, es:[bx].VDE_entrySize >
EC < sub ax, size VarDataEntry >
EC < cmp cx, ax >
EC < pop ax >
EC < ERROR_AE ILLEGAL_VARDATA_RELOCATION_OFFSET >
lea di, es:[bx].VDE_extraData ; es:di <- start of extra data
add di, cx ; point to proper place in same
and al, mask VORT_RELOC_TYPE
EC < cmp al,RELOC_LAST_LEGAL >
EC < ERROR_A BAD_RELOCATION_TYPE >
mov cx, es:[di] ;cx = data
cmp al,RELOC_ENTRY_POINT ;RELOC_ENTRY_POINT does dword
je varrelEP ;branch to read/write dword
mov bx, es:[LMBH_handle]
call es:[OLMBH_inUseCount]
jc popSIDone ; Bail if error returned from
; lower level handler (*after*
; fixing stack!) -- Doug 5/17/93
mov_tr ax, cx ;store adjusted data
stosw
novardata:
pop si
jmp varrelloop
vardataDoneLeap:
jmp vardataDone
varrelEP:
mov dx, es:[di][2]
mov bx, es:[LMBH_handle]
call es:[OLMBH_inUseCount]
jc popSIDone ; Bail if error returned from
; lower level handler (*after*
; fixing stack!) -- Doug 5/17/93
mov_tr ax, cx ;store adjusted data
stosw
mov_tr ax, dx
stosw
pop si
jmp varrelloop
; done with this class - move to next class
popSIDone:
pop si
jmp short done
vardataDone:
mov si, classoff
mov cx,ds:[si].Class_superClass.segment
jcxz done
cmp cx,VARIANT_CLASS ;variant class ?
jz variant
mov si, ds:[si].Class_superClass.offset
mov ds, cx
toSuper:
call RelocOrUnRelocClass
done:
.leave
ret
;---------------------
; superclass is a variant -- get class from instance data
variant:
mov bx, ds:[si].Class_masterOffset
mov si, object
mov si, es:[si]
add si, es:[si][bx]
; When unrelocating a class, the offset may be zero, but
; the segment cannot be zero (with one exception).
; However, when relocating,
; the entry point number of the class, which is stored in
; the segment can be zero, but the ObjRelocationID will not
; be zero (with one exception). So we must OR the segment
; and offset and if the result is non-zero, then continue
; with the reloc or unreloc. In the two exceptions I mentioned
; above, unrelocating a class with a zero segment and relocating
; a class with an ObjRelocationID of 0 (ORS_NULL), the desired
; result is zero in both segment and offset which is already
; the case.
mov cx,es:[si].MB_class.segment
or cx,es:[si].MB_class.offset
jz done ;if data null then done (carry clear)
mov bx, si
call RelocOrUnRelocAndLoadClass ; ds:si = class
EC < jmp toSuper >
NEC < jnc toSuper >
NEC < jmp done >
ObjRelocOrUnRelocSuper endp
COMMENT @%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
OBJRELOCORUNRELOCSUPER
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
SYNOPSIS: C stub for ObjRelocOrUnRelocSuper
CALLED BY: Boolean _pascal ObjRelocOrUnRelocSuper(
optr oself
ClassStruct *class,
word frame)
PASS:
RETURN:
DESTROYED:
SIDE EFFECTS:
PSEUDO CODE/STRATEGY:
REVISION HISTORY:
Name Date Description
---- ---- -----------
ardeb 9/30/92 Initial version
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%@
SetGeosConvention
OBJRELOCORUNRELOCSUPER proc far oself:optr,
thisclass:fptr.ClassStruct,
frame:word
uses ds, si, di, bp, es
.enter
movdw bxsi, ss:[oself]
les di, ss:[thisclass]
mov bp, ss:[frame] ; we have no local variables, so Esp
; doesn't need us to preserve the
; bp it set up for us; it can recover
; without it.
call MemDerefDS
call ObjRelocOrUnRelocSuper
mov ax, 0
jnc done
dec ax
done:
.leave
ret
OBJRELOCORUNRELOCSUPER endp
SetDefaultConvention
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocOrUnRelocAndLoadClass
DESCRIPTION: Relocate or unrelocate class pointer
CALLED BY: RelocOrUnRelocObj
PASS:
es:bx - instance
es:[OLMBH_inUseCount] - routine to call (Reloc or UnReloc)
RETURN:
class pointer relocated or unrelocated
ds:si = class pointer
carry set if error relocating/unrelocating class pointer
DESTROYED:
ax, cx, dx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
RelocOrUnRelocAndLoadClass proc near
mov cx,es:[bx].MB_class.offset ;low word in cx
mov dx,es:[bx].MB_class.segment ;high word in dx
mov al,RELOC_ENTRY_POINT
push bx
mov bx,es:[LMBH_handle]
EC < call ECCheckMemHandleFar >
cmp es:[OLMBH_inUseCount], offset UnRelocateLow
jne callReloc
mov ds, dx ; Get the class pointer now
mov si, cx
callReloc:
pushf
call es:[OLMBH_inUseCount]
NEC < jc error >
popf
clc
je havePointer
mov ds, dx
mov si, cx
havePointer:
pop bx
if ERROR_CHECK
je valid ;Branch if unrelocating, not relocating
HMA < cmp dx, HMA_SEGMENT >
HMA < je valid >
cmp dh, high MAX_SEGMENT
ERROR_AE CLASS_MUST_BE_IN_FIXED_RESOURCE
valid:
endif
mov es:[bx].MB_class.offset,cx
mov es:[bx].MB_class.segment,dx
ret
NEC <error: >
NEC < popf >
NEC < stc >
NEC < jmp havePointer >
RelocOrUnRelocAndLoadClass endp
COMMENT @----------------------------------------------------------------------
FUNCTION: ObjDoRelocation
DESCRIPTION: Relocate a given word or double word
CALLED BY: GLOBAL
PASS:
al - relocation type (RelocationTypes)
RELOC_HANDLE - resource ID to handle
RELOC_SEGMENT - resource ID to segment
RELOC_ENTRY_POINT - resource ID/entry # to dword
bx - handle of block containing relocation
cx - low word of relocation data
dx - high word of relocation data (only used if RELOC_ENTRY_POINT)
RETURN:
cx - low word, relocated
dx - high word, relocated (if not RELOC_ENTRY_POINT then destroyed)
carry set on error
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
ObjDoRelocation proc far
if MOVABLE_CORE_BLOCKS
call LockOwnersCoreBlockAndLibraries
endif
push ax, bx
call RelocateLow
pop ax, bx
if MOVABLE_CORE_BLOCKS
call UnlockOwnersCoreBlockAndLibraries
endif
ret
ObjDoRelocation endp
COMMENT @----------------------------------------------------------------------
FUNCTION: ObjDoUnRelocation
DESCRIPTION: UnRelocate a given word or double word
CALLED BY: GLOBAL
PASS:
al - relocation type (RelocationTypes)
RELOC_HANDLE - resource ID to handle
RELOC_SEGMENT - resource ID to segment
RELOC_ENTRY_POINT - resource ID/entry # to dword
bx - handle of block containing relocation
cx - low word of relocation data
dx - high word of relocation data (only used if RELOC_ENTRY_POINT)
RETURN:
cx - low word, unrelocated
dx - high word, unrelocated (if not RELOC_ENTRY_POINT then unchanged)
carry set on error
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
ObjDoUnRelocation proc far
if MOVABLE_CORE_BLOCKS
call LockOwnersCoreBlockAndLibraries
endif
push ax, bx
call UnRelocateLow
pop ax, bx
if MOVABLE_CORE_BLOCKS
call UnlockOwnersCoreBlockAndLibraries
endif
ret
ObjDoUnRelocation endp
COMMENT @----------------------------------------------------------------------
FUNCTION: RelocateLow
DESCRIPTION: Relocate a given word or double word
CALLED BY: ObjDoRelocation, RelocateObjBlock (via vector)
PASS:
al - relocation type (RelocationTypes)
RELOC_HANDLE - resource ID to handle
RELOC_SEGMENT - resource ID to segment
RELOC_ENTRY_POINT - resource ID/entry # to dword
bx - handle of block containing relocation
cx - low word of relocation data
dx - high word of relocation data (only used if RELOC_ENTRY_POINT)
owner's core block and imported libraries locked
RETURN:
cx - low word, relocated
dx - high word, relocated (if not RELOC_ENTRY_POINT then destroyed)
DESTROYED:
ax, bx
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
RelocateLow proc near
mov ah,ch
andnf cx,not mask RID_SOURCE
andnf ah,mask RID_SOURCE shr 8 ;ah = relocation source
jnz notNull ;source = 0 -> null relocation
; Null relocation
cmp al,RELOC_ENTRY_POINT ;if entry point must clear dx
jnz ret1
clr dx
ret1:
xor cx, cx ;clear cx, carry bit
ret
notNull:
cmp ah,ORS_CURRENT_BLOCK shl (offset RID_SOURCE-8)
jnz notSelf
; relocation to current block
cmp al,RELOC_HANDLE
EC < ERROR_NZ CANNOT_RELOC_CURRENT_BLOCK_TO_OTHER_THAN_HANDLE >
NEC < jne error >
mov cx,bx ;return handle
ret
notSelf:
EC < cmp ah,ORS_KERNEL shl (offset RID_SOURCE-8) >
EC < ERROR_Z KERNEL_RELOCATION_TYPE_IS_OBSOLETE >
push ds
LoadVarSeg ds
cmp ah,ORS_OWNING_GEODE shl (offset RID_SOURCE-8)
jnz notOwningGeode
; relocation to owning geode
call MemOwnerFar
mov ds,ds:[bx].HM_addr ;ds = owning geode
cmp cx,ds:[GH_resCount]
EC < ERROR_AE CANNOT_RELOC_OWNING_GEODE_TO_BAD_RESOURCE_ID >
NEC < jae errorPopDS >
shl cx,1 ;*2 for index into table
mov bx,cx
add bx,ds:[GH_resHandleOff]
mov cx,ds:[bx] ;cx = handle
cmp al,RELOC_HANDLE
jz done
LoadVarSeg ds ;must get segment address
mov bx,cx
mov cx,ds:[bx].HM_addr
cmp al,RELOC_SEGMENT
jz done
clc
xchg cx,dx
done:
pop ds
ret
NEC <errorUnlockLibPopDS: >
if not ERROR_CHECK and DELAY_LIBRARY_CORE_BLOCK_LOCK
jcxz errorPopDS ; => owning geode, so no unlock needed
mov bx, ds:[GH_geodeHandle]
LoadVarSeg ds, ax
FastUnLock ds, bx, ax
endif
NEC <errorPopDS: >
NEC < pop ds >
NEC <error: >
NEC < stc >
NEC < ret >
;--------------------
notOwningGeode:
; ah = RID_SOURCE field of CX
; bx = handle in which relocation is located
; al = ObjRelocationType
; cx = RID_INDEX
; dx = additional info
;
cmp ah,ORS_LIBRARY shl (offset RID_SOURCE-8)
LONG jnz notLibrary
; relocation to a library. Find the thing's core block
call MemOwnerFar
mov ds, ds:[bx].HM_addr ;ds = owning geode
mov bx, ds:[GH_libOffset] ;assume explicit table
cmp cx, ds:[GH_libCount] ; in range?
jb getLibraryHandle ; yes
mov bx, ds:[GH_extraLibOffset] ; use implicit table
sub cx, ds:[GH_libCount] ; and adjust index accordingly
EC < cmp cx, ds:[GH_extraLibCount] >
EC < ERROR_AE OBJ_RELOCATION_TO_INVALID_LIBRARY_NUMBER >
getLibraryHandle:
shl cx, 1 ;multiply by 2 to get offset
add bx, cx
mov bx, ds:[bx] ;bx = library handle
LoadVarSeg ds, cx
ife DELAY_LIBRARY_CORE_BLOCK_LOCK
mov ds, ds:[bx].HM_addr ;ds=library's core block
else
FastLock1 ds, bx, cx, RLL1, RLL2
mov ds, cx
endif
libraryCommon:
;
; Fetch entry point from either a library or the owning geode.
; ds = core block (to be unlocked if library)
; dx = entry point #
; cx = 0 if owning geode, non-zero (ds) if library
;
; ERROR-CHECK PARAMETERS:
; - we do not support handle or segment object relocations
; to entry points.
; - entry point number must be within bounds of the table
;
CheckHack <RELOC_HANDLE lt RELOC_SEGMENT and \
RELOC_ENTRY_POINT gt RELOC_SEGMENT>
cmp al, RELOC_SEGMENT
EC < ERROR_BE CANNOT_RELOC_LIBRARY_ENTRY_TO_HANDLE_OR_SEGMENT >
NEC< jbe error >
cmp dx, ds:[GH_exportEntryCount]
EC < ERROR_AE OBJ_RELOCATION_TO_INVALID_LIBRARY_ROUTINE_NUMBER >
NEC< jae errorUnlockLibPopDS >
shl dx,1 ; index far-pointer table
shl dx,1
mov bx, ds:[GH_exportLibTabOff]
add bx, dx
if DELAY_LIBRARY_CORE_BLOCK_LOCK
tst cx ; library?
endif
mov cx, ds:[bx].offset
mov dx, ds:[bx].segment
if DELAY_LIBRARY_CORE_BLOCK_LOCK
jz libraryCommonDone ; => owning geode entry point
; so no unlock needed
push bx
mov bx, ds:[LMBH_handle]
LoadVarSeg ds, ax
FastUnLock ds, bx, ax
pop bx
libraryCommonDone:
endif
pop ds
; cx = new offset, dx = new segment
clc
;ret2:
ret
;--------------------
notLibrary:
; if a relocation to entry point in the owning geode
; then use the same code as for an arbitrary library except use the
; core block that we already have
;
; ah = RID_SOURCE field of CX
; bx = handle in which relocation is located
; al = ObjRelocationType
; cx = RID_INDEX
; dx = additional info
;
cmp ah,ORS_OWNING_GEODE_ENTRY_POINT shl (offset RID_SOURCE-8)
jnz notOwningGeodeEntryPoint
; relocation to entry point in the owning geode
call MemOwnerFar
mov ds,ds:[bx].HM_addr ;ds = owning geode
if DELAY_LIBRARY_CORE_BLOCK_LOCK
clr cx ; signal owning geode
endif
jmp libraryCommon
if DELAY_LIBRARY_CORE_BLOCK_LOCK
FastLock2 ds, bx, cx, RLL1, RLL2
endif
;--------------------
notOwningGeodeEntryPoint:
;
; ah = RID_SOURCE field of CX
; bx = handle in which relocation is located
; al = ObjRelocationType
; cx = RID_INDEX
; dx = additional info
;
cmp ah,ORS_VM_HANDLE shl (offset RID_SOURCE-8)
jnz notStateVM
; relocation to VM handle of saved block
cmp al,RELOC_HANDLE
EC < ERROR_NZ CANNOT_RELOC_VM_HANDLE_TO_OTHER_THAN_HANDLE >
EC < push bx >
NEC< LONG jne errorPopDS >
call MemOwnerFar
mov ds,ds:[bx].HM_addr ;ds = owning geode
mov bx,ds:[PH_savedBlockPtr]
LoadVarSeg ds
savedLoop:
tst bx
jz hackMaster1
cmp cx,ds:[bx].HSB_vmID
jz dupFound
mov bx,ds:[bx].HSB_next
jmp savedLoop
dupFound:
mov cx,ds:[bx].HSB_handle
EC < pop bx >
dupNotFoundButWeDontCare:
pop ds
ret
hackMaster1:
;
; Deal with a relocation to a resource block in a data file. We
; often get these when saving out data files containing objects that
; are still on-screen. When the file is opened from a fresh instance
; of the application, we can't find the proper memory handle again,
; but that's ok because the pointer will get overwritten in a minute
; anyway. If the file is re-opened from the same instance of the app
; that saved it, we won't get here anyway b/c the saved block list
; will contain the block being sought. Rather than choke in this
; perfectly reasonable situation, we just relocate to 0 if we can't
; find the memory handle when the relocation is in a VM block..
; This is not a kludge. Really.
;
EC < pop bx ;make sure the block's a VM >
EC < mov ds, ds:[bx].HM_addr ; block in a data file >
EC < test ds:[LMBH_flags], mask LMF_IS_VM >
EC < ERROR_Z BAD_RELOCATION_CANNOT_FIND_VM_HANDLE >
clr cx ;set word to 0 (clears carry)
jmp dupNotFoundButWeDontCare
;--------------------
notStateVM:
;
; ah = RID_SOURCE field of CX
; bx = handle in which relocation is located
; al = ObjRelocationType
; cx = RID_INDEX
; dx = additional info
;
cmp ah,ORS_NON_STATE_VM shl (offset RID_SOURCE-8)
jnz notNonStateVM
; relocation to VM file stored in the block header
cmp al,RELOC_HANDLE
EC < ERROR_NZ CANNOT_RELOC_VM_HANDLE_TO_OTHER_THAN_HANDLE >
NEC< LONG jne errorPopDS >
mov_tr ax, cx ;ax = index
call VMObjIndexToMemHandle ;returns ax = mem handle
moveAndExit:
mov_tr cx, ax
clc
pop ds
ret
;--------------------
notNonStateVM:
;
; ah = RID_SOURCE field of CX
; bx = handle in which relocation is located
; al = ObjRelocationType
; cx = RID_INDEX
; dx = additional info
;
cmp ah, ORS_UNKNOWN_BLOCK shl (offset RID_SOURCE-8)
EC < ERROR_NZ BAD_RELOCATION_TYPE >
NEC< LONG jne errorPopDS >
mov_tr ax, cx
mov cl, 4
shl ax, cl
jmp moveAndExit
RelocateLow endp
COMMENT @----------------------------------------------------------------------
FUNCTION: UnRelocateLow
DESCRIPTION: UnRelocate a given word or double word
CALLED BY: ObjDoUnRelocation, UnRelocateObjBlock (via vector)
PASS:
al - relocation type (RelocationTypes)
RELOC_HANDLE - handle to resource ID
RELOC_SEGMENT - segment to resource ID
RELOC_ENTRY_POINT - dword to resource ID/entry #
bx - handle of block containing relocation
cx - low word of relocation data
dx - high word of relocation data (only used if RELOC_ENTRY_POINT)
owner's core block and imported libraries locked
RETURN:
carry - set if error
cx - low word, unrelocated
dx - high word, unrelocated (if not RELOC_ENTRY_POINT then unchanged)
DESTROYED:
ax
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 3/89 Initial version
------------------------------------------------------------------------------@
UnRelocateLow proc near
; check for value 0
tst cx
jnz notZero
cmp al,RELOC_ENTRY_POINT ; need we check DX too? (only double-
; word relocation)
jnz 10$ ; no -- just use ORS_NULL
tst dx
jnz notZero
10$:
; Please don't get any ideas about "optimizing" this by realizing
; that a plain "or" will clear the carry -- esp has the right to delete
; the "ornf" altgeher since the only affect is to change the carry, &
; hence this actually saves byes over an "or". Aside from that, I've
; already spent some 3 hours tracking down a problem here, & would
; appreciate not have to do it gain. In summary, keep your mitts off!
; Thank you. -- Doug 5/1793
;
or cx,ORS_NULL shl offset RID_SOURCE ; (clears carry)
ret
notZero:
push ax, di, bp, ds, es, si
cbw ; clear ah (1-byte inst)
mov_tr bp,ax ;bp hold type (1-byte inst)
; Convert whatever type is given into a handle (since this is
; easy to deal with).
cmp bp,RELOC_HANDLE
jz gotHandle
; convert segment to handle -- since all the block types that we
; relocate have the handle at the beginning (except the kernel)
cmp bp,RELOC_ENTRY_POINT ;entry point has segment in dx
jnz segmentInCX
xchg cx,dx ;cx = seg, dx = off
segmentInCX:
mov si, cx ;si <- seg for export table
; comparison
HMA < cmp cx, HMA_SEGMENT ;check hi-mem segment >
HMA < je fixed >
cmp ch, high MAX_SEGMENT ;movable?
jb fixed ;no -- deal with segment
; "segment" is handle shifted right four bits. shift it back again...
mov_tr ax, cx
mov cl, 4 ;shift left four times to multiply by
shl ax, cl ;16 to get number of bytes
mov cx, ax
jmp gotHandle
fixed:
call MemSegmentToHandle ;returns cx = handle
EC < ERROR_NC ILLEGAL_SEGMENT_VALUE >
NEC < jnc errorPop >
; cx contains the handle of the relocation -- convert to type
; check for ORS_CURRENT_BLOCK
gotHandle:
; cx = handle of target
; dx = offset, if far pointer
; bx = handle of block in which relocation sits
; bp = ObjRelocationType
;
cmp bx,cx
jnz notCurrentBlock
cmp bp,RELOC_ENTRY_POINT
EC < ERROR_Z CANNOT_UNRELOCATE_CURRENT_BLOCK_TO_ENTRY_POINT >
NEC < je errorPop >
mov cx,ORS_CURRENT_BLOCK shl offset RID_SOURCE
popAndReturn:
clc
NEC <popAndReturnNoCLC: >
pop ax, di, bp, ds, es, si
ret
NEC <errorPop: >
NEC < stc >
NEC < jmp popAndReturnNoCLC >
; check for resource
;--------------------
notCurrentBlock:
; cx = handle of target
; dx = offset, if far pointer
; bx = handle of block in which relocation sits
; bp = ObjRelocationType
;
LoadVarSeg ds
push cx ;save reloc handle
xchg bx, cx ;bx = handle to reloc,
; cx = handle holding reloc
call HandleToID
xchg bx, cx ;bx = data block, cx = ID
mov es, ax ;es <- core block of target's
; owner
LONG jc notResource
; figure whose export table we should look at by seeing who owns the
; block that holds the entry point itself.
mov di, bx
call MemOwnerFar
xchg bx, di ;bx = block, di = owner
cmp di, es:[GH_geodeHandle] ;target owned by same geode
; as owns the data block?
je isOwningGeode
; to deal with the target being a shared resource handle while the
; object block is an unshared block owned by the second instance of
; an app, we need to compare the file handles for the two geodes
; to see if they refer to the same geode (XXX: THIS WON'T WORK IF THE
; TWO GEODES AREN'T KEEP_FILE_OPEN; for practical purposes, however,
; all geodes that might require unrelocating will have discardable
; resources...)
mov ax, es:[GH_geoHandle] ; fetch file handle for target's
; owner
FXIP < tst ax >
FXIP < jz UnotOwningGeode >
push ds
if MOVABLE_CORE_BLOCKS
EC < tst ds:[di].HM_lockCount >
EC < ERROR_Z OWNER_CORE_BLOCK_NOT_LOCKED >
endif
mov ds, ds:[di].HM_addr ; locked by caller
cmp ax, ds:[GH_geoHandle]
pop ds
jne UnotOwningGeode ;nope. must be a library
isOwningGeode:
cmp bp,RELOC_ENTRY_POINT
pop di ;discard handle
jz ownerEntryPoint
; if not entry point, CX already contains the resource ID, which
; must be all that's needed.
ornf cx,ORS_OWNING_GEODE shl offset RID_SOURCE
push bx
mov bx, es:[GH_geodeHandle]
call MemUnlock
;;ES will be popped in a moment, so no need for this....
;;EC < call NullES >
pop bx ;it's already locked by caller
jmp popAndReturn
; entry point in the owning geode, search library table
ownerEntryPoint:
mov cx,ORS_OWNING_GEODE_ENTRY_POINT shl offset RID_SOURCE
LoadVarSeg ds
jmp findLibraryEntry
; The item is a resource, but is not one of ours or one of our
; libraries. HELP!
NEC <noMatchPanic: >
if DELAY_LIBRARY_CORE_BLOCK_LOCK
NEC < xchg ax, bx ; bx <- library core >
NEC < call MemUnlock >
NEC < mov_tr bx, ax >
endif
NEC < pop cx ; handle... >
NEC < jmp errorPop >
; handle is a resource from a different owner (es = owner core block)
; check for ORS_LIBRARY
; on stack: ax, cx, ds, es
; di = owner of data block in which relocation itself resides.
UnotOwningGeode:
mov ax,es:[GH_geodeHandle] ;ax = handle to match
mov es,ds:[di].HM_addr ;es = core block of client
mov di,es:[GH_libOffset] ;es:di = library table
mov cx,es:[GH_libCount]
repne scasw
jne checkExtraLibs
sub cx, es:[GH_libCount]
not cx
foundLibrary:
; cx = library # (either explicitly imported or implicitly...)
inc sp ; discard saved data block
inc sp ; handle
mov_tr di, ax
mov es, ds:[di].HM_addr ;es <- target owner's core
; block (needed in libDone)
ornf cx,ORS_LIBRARY shl offset RID_SOURCE
cmp bp,RELOC_ENTRY_POINT
jnz libDone ;if not entry point, all we
; can need is the library #
;else we need to find the entry
; point # as well.
; search for entry point
; es = segment of target owner's core block
; ds = dgroup
findLibraryEntry:
push cx
xchg ax,si ;ax = segment of entry point
mov di,es:[GH_exportLibTabOff] ;es:di = exported lib table
mov cx,es:[GH_exportEntryCount]
shl cx
; cx = #entry points * 2
; es:di = entry point list
; ax = segment to match, dx = offset to match
findEntryLoopNoMatchCheckCX:
jcxz notFound ;if no entry points then not
;found
findEntryLoopNoMatch:
clr si ; clear "partial match" flag
findEntryLoop:
xchg ax, dx
scasw
loopne findEntryLoopNoMatch
jne notFound ;if words not equal, then
; we fell through the loopne
; because cx=0 => not found
not si ;set "partial match" flag
test cx, 1 ;if cx odd then we're in the
jnz findEntryLoop ; middle of our double word
; compare, loop to finish it
tst si ;since we're here the second
jnz findEntryLoopNoMatchCheckCX ; word matched, if the first
; word matched then a match
; else continue looping
; match found -- find the entry point #
; es:di points at entry after the match
; cx = (# of entries *2) - (match's entry # * 2)
xchg ax, cx ; 1b
shr ax ; 2b
sub ax, es:[GH_exportEntryCount] ; 4b
not ax ; 2b
xchg dx, ax ; 1b -- dx = entry #
pop cx ; 1b
libDone:
push bx
mov bx, es:[GH_geodeHandle]
call MemUnlock ; (ES popped in a moment, so no NullES)
pop bx
jmp popAndReturn
checkExtraLibs:
mov cx, es:[GH_extraLibCount]
mov di, es:[GH_extraLibOffset]
repne scasw
EC < ERROR_NZ CANNOT_UNRELOCATE_UNKNOWN_RESOURCE_HANDLE >
NEC < LONG jnz noMatchPanic >
sub cx, es:[GH_extraLibCount]
not cx
add cx, es:[GH_libCount] ; offset by # explicitly-imported libs
jmp foundLibrary
notFound:
EC < ERROR CANNOT_UNRELOCATE >
NEC < pop cx >
NEC < jmp errorPop >
; not a resource, check for a duplicated block (ds = idata)
notResource:
pop cx ;recover data handle
call MemOwnerFar ;bx = owner
mov es,ds:[bx].HM_addr ;es = core block of owner
mov di,es:[PH_savedBlockPtr]
UsavedLoop:
tst di ;at end of list ?
jz notDuplicate
cmp cx,ds:[di].HSB_handle
jz UdupFound
mov di,ds:[di].HSB_next
jmp UsavedLoop
UdupFound:
cmp bp,RELOC_ENTRY_POINT
EC < ERROR_Z CANNOT_UNRELOCATE_VM_HANDLE_TO_ENTRY_POINT >
NEC < LONG je errorPop >
mov cx,ds:[di].HSB_vmID
ornf cx,ORS_VM_HANDLE shl offset RID_SOURCE
jmp popAndReturn
; last ditch effort -- it must be a VM memory handle
notDuplicate:
mov bx, cx ;bx = handle to relocate
push bx
mov bx, ds:[bx].HM_owner
cmp ds:[bx].HG_type, SIG_VM
pop bx
jnz unknownBlock
call VMObjMemHandleToIndex
ornf ax, ORS_NON_STATE_VM shl offset RID_SOURCE
movePopAndReturn:
mov cx, ax
jmp popAndReturn
; we have no idea what this block is -- just preserve the handle so
; that at least we work in VM cases
unknownBlock:
mov ax, cx
mov cl, 4
shr ax, cl
ornf ax, ORS_UNKNOWN_BLOCK shl offset RID_SOURCE
jmp movePopAndReturn
UnRelocateLow endp
;------------------------------------------------------
ObjectLoad ends
ObjectFile segment resource
COMMENT @----------------------------------------------------------------------
FUNCTION: ObjRelocateEntryPoint
DESCRIPTION: Relocate an entry point from a structure that identifies
the geode from which the object comes
CALLED BY: INTERNAL
PASS:
On the stack, pushed in this order:
dword - pointer to EntryPointRelocation structure
RETURN:
dx:ax - entry point, or 0 if geode not available
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 8/ 3/92 Initial version
------------------------------------------------------------------------------@
OBJRELOCATEENTRYPOINT proc far relocPtr:fptr
uses bx, cx, di, es
.enter
; find the geode in the system
les di, relocPtr ;name
mov ax, GEODE_NAME_SIZE ;# chars to match
clr cx
clr dx
call GeodeFind
jnc notFound
; lock the core block for the current geode to make sure that this
; is an imported library (or the geode itsself)
mov cx, bx ;cx = geode to relocate to
mov bx, ss:TPD_processHandle
cmp bx, cx
jz geodeOK
; lock the core block to search the library table
call MemLock
mov es, ax ;es = current process
mov_tr ax, cx
mov cx, es:[GH_libCount]
mov di, es:[GH_libOffset]
repne scasw
jz foundLib
mov cx, es:[GH_extraLibCount]
mov di, es:[GH_extraLibOffset]
repne scasw
jz foundLib
call MemUnlock
notFound:
clrdw dxax
jmp done
foundLib:
; the library is found
call MemUnlock
EC < call NullES >
mov_tr cx, ax ;cx = library
geodeOK:
; cx = library, lock its core block and get the entry point
mov bx, cx
les di, relocPtr
mov ax, es:[di].EPR_entryNumber
call ProcGetLibraryEntry ;bxax = entry point
mov dx, bx ;dxax = entry point
done:
.leave
ret @ArgSize
OBJRELOCATEENTRYPOINT endp
COMMENT @----------------------------------------------------------------------
FUNCTION: ObjUnRelocateEntryPoint
DESCRIPTION: Unrelocate an entry point to a structure that identifies
the geode from which the object comes
CALLED BY: INTERNAL
PASS:
On the stack, pushed in this order:
dword - pointer to EntryPointRelocation structure (to fill in)
dword - entry point
RETURN:
none
DESTROYED:
none
REGISTER/STACK USAGE:
PSEUDO CODE/STRATEGY:
KNOWN BUGS/SIDE EFFECTS/CAVEATS/IDEAS:
REVISION HISTORY:
Name Date Description
---- ---- -----------
Tony 8/ 3/92 Initial version
------------------------------------------------------------------------------@
OBJUNRELOCATEENTRYPOINT proc far entryPoint:fptr, relocPtr:fptr
uses ax, bx, cx, dx, di, ds, es
.enter
; call the general routine to help us
mov bx, ss:[TPD_processHandle]
movdw dxcx, entryPoint
mov al, RELOC_ENTRY_POINT
call ObjDoUnRelocation
EC < ERROR_C ILLEGAL_SEGMENT_VALUE >
mov ax, cx
and ax, mask RID_SOURCE
cmp ax, ORS_OWNING_GEODE_ENTRY_POINT shl offset RID_SOURCE
jz gotGeode
; get library handle
push bx
and cx, mask RID_INDEX
call MemLock ;lock core block
mov ds, ax
mov bx, ds:[GH_libOffset]
cmp cx, ds:[GH_libCount]
jb getLibraryHandle
mov bx, ds:[GH_extraLibOffset]
sub cx, ds:[GH_libCount]
EC < cmp cx, ds:[GH_extraLibCount] >
EC < ERROR_AE OBJ_RELOCATION_TO_INVALID_LIBRARY_NUMBER >
getLibraryHandle:
shl cx ;multiply by 2 to get offset
add bx, cx
mov ax, ds:[bx] ;ax = library handle
pop bx
call MemUnlock
EC < call NullDS >
mov_tr bx, ax
gotGeode:
; bx = geode handle, dx = entry point number
les di, relocPtr
mov es:[di].EPR_entryNumber, dx
mov ax, GGIT_PERM_NAME_ONLY
call GeodeGetInfo
.leave
ret @ArgSize
OBJUNRELOCATEENTRYPOINT endp
ObjectFile ends
| {
"language": "Assembly"
} |
/*
Copyright (c) 2017, Lawrence Livermore National Security, LLC.
Produced at the Lawrence Livermore National Laboratory
Written by Chunhua Liao, Pei-Hung Lin, Joshua Asplund,
Markus Schordan, and Ian Karlin
(email: liao6@llnl.gov, lin32@llnl.gov, asplund1@llnl.gov,
schordan1@llnl.gov, karlin1@llnl.gov)
LLNL-CODE-732144
All rights reserved.
This file is part of DataRaceBench. For details, see
https://github.com/LLNL/dataracebench. Please also see the LICENSE file
for our additional BSD notice.
Redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the disclaimer below.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the disclaimer (as noted below)
in the documentation and/or other materials provided with the
distribution.
* Neither the name of the LLNS/LLNL nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LAWRENCE LIVERMORE NATIONAL
SECURITY, LLC, THE U.S. DEPARTMENT OF ENERGY OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
The loop in this example cannot be parallelized.
This pattern has two pair of dependencies:
1. loop carried output dependence
x = .. :
2. loop carried true dependence due to:
.. = x;
x = ..;
Data race pairs: we allow two pairs to preserve the original code pattern.
1. x@73:12 vs. x@74:5
2. x@74:5 vs. x@74:5
*/
#include <stdio.h>
int a[100];
int main()
{
int len=100;
int i,x=10;
#pragma omp parallel for
for (i=0;i<len;i++)
{
a[i] = x;
x=i;
}
printf("x=%d",x);
return 0;
}
| {
"language": "Assembly"
} |
From 357954613bdbab0c1f3986589ff30cc4855a2efd Mon Sep 17 00:00:00 2001
From: root <root@cent.localnet>
Date: Sun, 6 Dec 2009 18:26:43 +0000
Subject: [PATCH 03/14] kexec fix
---
arch/x86/kernel/relocate_kernel_32.S | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
--- a/arch/x86/kernel/relocate_kernel_32.S
+++ b/arch/x86/kernel/relocate_kernel_32.S
@@ -54,8 +54,10 @@ relocate_kernel:
movl %eax, CR0(%edi)
movl %cr3, %eax
movl %eax, CR3(%edi)
+#ifndef CONFIG_X86_RDC321X
movl %cr4, %eax
movl %eax, CR4(%edi)
+#endif
/* read the arguments and say goodbye to the stack */
movl 20+4(%esp), %ebx /* page_list */
@@ -124,7 +126,9 @@ identity_mapped:
* Setting everything to zero seems safe.
*/
xorl %eax, %eax
+#ifndef CONFIG_X86_RDC321X
movl %eax, %cr4
+#endif
jmp 1f
1:
@@ -195,8 +199,10 @@ identity_mapped:
ret
virtual_mapped:
+#ifndef CONFIG_X86_RDC321X
movl CR4(%edi), %eax
movl %eax, %cr4
+#endif
movl CR3(%edi), %eax
movl %eax, %cr3
movl CR0(%edi), %eax
| {
"language": "Assembly"
} |
# RISC-V Compliance Test SLTIU-01
#
# Copyright (c) 2019, Imperas Software Ltd.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of the Imperas Software Ltd. nor the
# names of its contributors may be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Specification: RV32I Base Integer Instruction Set, Version 2.1
# Description: Testing instruction 'SLTIU'.
#include "riscv_test_macros.h"
#include "compliance_test.h"
#include "compliance_io.h"
RV_COMPLIANCE_RV32M
RV_COMPLIANCE_CODE_BEGIN
RVTEST_IO_INIT
RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 1\n")
# address for test results
la x5, test_1_res
TEST_IMM_OP(sltiu, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0
TEST_IMM_OP(sltiu, x1, x30, 0x1, 0x1, -0x7ff, x5, 4, x6) # Testcase 1
TEST_IMM_OP(sltiu, x2, x29, 0x1, 0x0, -0x1, x5, 8, x6) # Testcase 2
TEST_IMM_OP(sltiu, x3, x28, 0x1, 0x7ff, -0x800, x5, 12, x6) # Testcase 3
TEST_IMM_OP(sltiu, x4, x27, 0x1, 0x0, 0x800, x5, 16, x6) # Testcase 4
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 2\n")
# address for test results
la x1, test_2_res
TEST_IMM_OP(sltiu, x5, x26, 0x1, 0x800, 0x800, x1, 0, x2) # Testcase 5
TEST_IMM_OP(sltiu, x6, x25, 0x1, 0x7654321, 0x800, x1, 4, x2) # Testcase 6
TEST_IMM_OP(sltiu, x7, x24, 0x0, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7
TEST_IMM_OP(sltiu, x8, x23, 0x1, 0x1, 0x800, x1, 12, x2) # Testcase 8
TEST_IMM_OP(sltiu, x9, x22, 0x0, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 3\n")
# address for test results
la x1, test_3_res
TEST_IMM_OP(sltiu, x10, x21, 0x1, 0x1234, 0x800, x1, 0, x7) # Testcase 10
TEST_IMM_OP(sltiu, x11, x20, 0x0, 0x80000000, 0x0, x1, 4, x7) # Testcase 11
TEST_IMM_OP(sltiu, x12, x19, 0x0, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12
TEST_IMM_OP(sltiu, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13
TEST_IMM_OP(sltiu, x14, x17, 0x0, -0x7ff, 0x1, x1, 16, x7) # Testcase 14
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 4\n")
# address for test results
la x2, test_4_res
TEST_IMM_OP(sltiu, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15
TEST_IMM_OP(sltiu, x16, x15, 0x0, -0x1, 0x0, x2, 4, x3) # Testcase 16
TEST_IMM_OP(sltiu, x17, x14, 0x1, 0x1, -0x7ff, x2, 8, x3) # Testcase 17
TEST_IMM_OP(sltiu, x18, x13, 0x1, 0x0, -0x1, x2, 12, x3) # Testcase 18
TEST_IMM_OP(sltiu, x19, x12, 0x1, 0x7ff, -0x800, x2, 16, x3) # Testcase 19
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 5\n")
# address for test results
la x1, test_5_res
TEST_IMM_OP(sltiu, x20, x11, 0x1, 0x0, 0x800, x1, 0, x2) # Testcase 20
TEST_IMM_OP(sltiu, x21, x10, 0x1, 0x800, 0x800, x1, 4, x2) # Testcase 21
TEST_IMM_OP(sltiu, x22, x9, 0x1, 0x7654321, 0x800, x1, 8, x2) # Testcase 22
TEST_IMM_OP(sltiu, x23, x8, 0x0, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23
TEST_IMM_OP(sltiu, x24, x7, 0x1, 0x1, 0x800, x1, 16, x2) # Testcase 24
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 6\n")
# address for test results
la x1, test_6_res
TEST_IMM_OP(sltiu, x25, x6, 0x0, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25
TEST_IMM_OP(sltiu, x26, x5, 0x1, 0x1234, 0x800, x1, 4, x7) # Testcase 26
TEST_IMM_OP(sltiu, x27, x4, 0x0, 0x80000000, 0x0, x1, 8, x7) # Testcase 27
TEST_IMM_OP(sltiu, x28, x3, 0x0, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28
TEST_IMM_OP(sltiu, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "# Test number 7\n")
# address for test results
la x2, test_7_res
TEST_IMM_OP(sltiu, x30, x1, 0x0, -0x7ff, 0x1, x2, 0, x3) # Testcase 30
TEST_IMM_OP(sltiu, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31
# ---------------------------------------------------------------------------------------------
RVTEST_IO_WRITE_STR(x31, "Test End\n")
# ---------------------------------------------------------------------------------------------
RV_COMPLIANCE_HALT
RV_COMPLIANCE_CODE_END
# Input data section.
.data
# Output data section.
RV_COMPLIANCE_DATA_BEGIN
test_1_res:
.fill 5, 4, -1
test_2_res:
.fill 5, 4, -1
test_3_res:
.fill 5, 4, -1
test_4_res:
.fill 5, 4, -1
test_5_res:
.fill 5, 4, -1
test_6_res:
.fill 5, 4, -1
test_7_res:
.fill 5, 4, -1
RV_COMPLIANCE_DATA_END
| {
"language": "Assembly"
} |
# Feed this file to script/make-artificial.go
make deflate
blockDynamicHuffman (final) {
huffman CodeLength {
# 15 codes of length 4.
0 0000
1 0001
etcetera
13 1101
14 1110
# 4 codes of length 6.
15 111100
16 111101
17 111110
18 111111
}
# script/print-deflate-huff-table-size.go prints:
# primLen 9: 852 entries = 512 prim + 340 seco
# @1 @2 @3 @4 @5 @6 @7 @8 @9 @10 @11 @12 @13 @14 @15
# 1 1 1 0 0 0 0 0 0; 1 229 49 1 1 2
huffman Literal/Length {
0 0
1 10
2 110
3 1110000000
# 229 codes of length 11.
4 11100000010
5 11100000011
etcetera
231 11111100101
232 11111100110
# 49 codes of length 12.
233 111111001110
234 111111001111
etcetera
256 111111100101
257 111111100110
etcetera
280 111111111101
281 111111111110
# 1+1+2 = 4 codes of length 13+.
282 1111111111110
283 11111111111110
284 111111111111110
285 111111111111111
}
# script/print-deflate-huff-table-size.go prints:
# primLen 9: 592 entries = 512 prim + 80 seco
# @1 @2 @3 @4 @5 @6 @7 @8 @9 @10 @11 @12 @13 @14 @15
# 1 1 1 1 1 1 1 0 0; 1 9 9 1 1 2
huffman Distance {
0 0
1 10
2 110
3 1110
4 11110
5 111110
6 1111110
7 1111111000
# 9 codes of length 11.
8 11111110010
9 11111110011
etcetera
15 11111111001
16 11111111010
# 9 codes of length 12.
17 111111110110
18 111111110111
etcetera
24 111111111101
25 111111111110
# 1+1+2 = 4 codes of length 13+.
26 1111111111110
27 11111111111110
28 111111111111110
29 111111111111111
}
literal "ban"
len 3 dist 2
endOfBlock
}
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
#include "funcdata.h"
//
// System calls for AMD64, Linux
//
// func Syscall(trap int64, a1, a2, a3 uintptr) (r1, r2, err uintptr);
// Trap # in AX, args in DI SI DX R10 R8 R9, return in AX DX
// Note that this differs from "standard" ABI convention, which
// would pass 4th arg in CX, not R10.
TEXT ·Syscall(SB),NOSPLIT,$0-56
CALL runtime·entersyscall(SB)
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
CMPQ AX, $0xfffffffffffff001
JLS ok
MOVQ $-1, r1+32(FP)
MOVQ $0, r2+40(FP)
NEGQ AX
MOVQ AX, err+48(FP)
CALL runtime·exitsyscall(SB)
RET
ok:
MOVQ AX, r1+32(FP)
MOVQ DX, r2+40(FP)
MOVQ $0, err+48(FP)
CALL runtime·exitsyscall(SB)
RET
// func Syscall6(trap, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2, err uintptr)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
CALL runtime·entersyscall(SB)
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ a4+32(FP), R10
MOVQ a5+40(FP), R8
MOVQ a6+48(FP), R9
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
CMPQ AX, $0xfffffffffffff001
JLS ok6
MOVQ $-1, r1+56(FP)
MOVQ $0, r2+64(FP)
NEGQ AX
MOVQ AX, err+72(FP)
CALL runtime·exitsyscall(SB)
RET
ok6:
MOVQ AX, r1+56(FP)
MOVQ DX, r2+64(FP)
MOVQ $0, err+72(FP)
CALL runtime·exitsyscall(SB)
RET
// func RawSyscall(trap, a1, a2, a3 uintptr) (r1, r2, err uintptr)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
CMPQ AX, $0xfffffffffffff001
JLS ok1
MOVQ $-1, r1+32(FP)
MOVQ $0, r2+40(FP)
NEGQ AX
MOVQ AX, err+48(FP)
RET
ok1:
MOVQ AX, r1+32(FP)
MOVQ DX, r2+40(FP)
MOVQ $0, err+48(FP)
RET
// func RawSyscall6(trap, a1, a2, a3, a4, a5, a6 uintptr) (r1, r2, err uintptr)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ a4+32(FP), R10
MOVQ a5+40(FP), R8
MOVQ a6+48(FP), R9
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
CMPQ AX, $0xfffffffffffff001
JLS ok2
MOVQ $-1, r1+56(FP)
MOVQ $0, r2+64(FP)
NEGQ AX
MOVQ AX, err+72(FP)
RET
ok2:
MOVQ AX, r1+56(FP)
MOVQ DX, r2+64(FP)
MOVQ $0, err+72(FP)
RET
// func rawVforkSyscall(trap, a1 uintptr) (r1, err uintptr)
TEXT ·rawVforkSyscall(SB),NOSPLIT,$0-32
MOVQ a1+8(FP), DI
MOVQ $0, SI
MOVQ $0, DX
MOVQ $0, R10
MOVQ $0, R8
MOVQ $0, R9
MOVQ trap+0(FP), AX // syscall entry
POPQ R12 // preserve return address
SYSCALL
PUSHQ R12
CMPQ AX, $0xfffffffffffff001
JLS ok2
MOVQ $-1, r1+16(FP)
NEGQ AX
MOVQ AX, err+24(FP)
RET
ok2:
MOVQ AX, r1+16(FP)
MOVQ $0, err+24(FP)
RET
// func rawSyscallNoError(trap, a1, a2, a3 uintptr) (r1, r2 uintptr)
TEXT ·rawSyscallNoError(SB),NOSPLIT,$0-48
MOVQ a1+8(FP), DI
MOVQ a2+16(FP), SI
MOVQ a3+24(FP), DX
MOVQ trap+0(FP), AX // syscall entry
SYSCALL
MOVQ AX, r1+32(FP)
MOVQ DX, r2+40(FP)
RET
// func gettimeofday(tv *Timeval) (err uintptr)
TEXT ·gettimeofday(SB),NOSPLIT,$0-16
MOVQ tv+0(FP), DI
MOVQ $0, SI
MOVQ runtime·vdsoGettimeofdaySym(SB), AX
CALL AX
CMPQ AX, $0xfffffffffffff001
JLS ok7
NEGQ AX
MOVQ AX, err+8(FP)
RET
ok7:
MOVQ $0, err+8(FP)
RET
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//
// System calls for amd64, Windows are implemented in runtime/syscall_windows.goc
//
TEXT ·getprocaddress(SB), 7, $0-32
JMP syscall·getprocaddress(SB)
TEXT ·loadlibrary(SB), 7, $0-8
JMP syscall·loadlibrary(SB)
| {
"language": "Assembly"
} |
# ROFLCOPTER
$the_cow = <<EOC;
$thoughts
$thoughts
ROFL:LOL:ROFL:ROFL
_^___
L __/ [] \\
LOL===__ \\
L \________]
I I
--------/
EOC
| {
"language": "Assembly"
} |
// Copyright 2009 the Sputnik authors. All rights reserved.
// This code is governed by the BSD license found in the LICENSE file.
/**
* CARRIAGE RETURN (U+000D) within strings is not allowed
*
* @path ch07/7.3/S7.3_A2.2_T2.js
* @description Insert real CARRIAGE RETURN into string
* @negative
*/
//CHECK#1
"
str
ing
";
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
*
* This file is part of Libav.
*
* Libav is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* Libav is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with Libav; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "libavutil/arm/asm.S"
.macro ldcol.8 rd, rs, rt, n=8, hi=0
.if \n == 8 || \hi == 0
vld1.8 {\rd[0]}, [\rs], \rt
vld1.8 {\rd[1]}, [\rs], \rt
vld1.8 {\rd[2]}, [\rs], \rt
vld1.8 {\rd[3]}, [\rs], \rt
.endif
.if \n == 8 || \hi == 1
vld1.8 {\rd[4]}, [\rs], \rt
vld1.8 {\rd[5]}, [\rs], \rt
vld1.8 {\rd[6]}, [\rs], \rt
vld1.8 {\rd[7]}, [\rs], \rt
.endif
.endm
.macro add16x8 dq, dl, dh, rl, rh
vaddl.u8 \dq, \rl, \rh
vadd.u16 \dl, \dl, \dh
vpadd.u16 \dl, \dl, \dl
vpadd.u16 \dl, \dl, \dl
.endm
function ff_pred16x16_128_dc_neon, export=1
vmov.i8 q0, #128
b .L_pred16x16_dc_end
endfunc
function ff_pred16x16_top_dc_neon, export=1
sub r2, r0, r1
vld1.8 {q0}, [r2,:128]
add16x8 q0, d0, d1, d0, d1
vrshrn.u16 d0, q0, #4
vdup.8 q0, d0[0]
b .L_pred16x16_dc_end
endfunc
function ff_pred16x16_left_dc_neon, export=1
sub r2, r0, #1
ldcol.8 d0, r2, r1
ldcol.8 d1, r2, r1
add16x8 q0, d0, d1, d0, d1
vrshrn.u16 d0, q0, #4
vdup.8 q0, d0[0]
b .L_pred16x16_dc_end
endfunc
function ff_pred16x16_dc_neon, export=1
sub r2, r0, r1
vld1.8 {q0}, [r2,:128]
sub r2, r0, #1
ldcol.8 d2, r2, r1
ldcol.8 d3, r2, r1
vaddl.u8 q0, d0, d1
vaddl.u8 q1, d2, d3
vadd.u16 q0, q0, q1
vadd.u16 d0, d0, d1
vpadd.u16 d0, d0, d0
vpadd.u16 d0, d0, d0
vrshrn.u16 d0, q0, #5
vdup.8 q0, d0[0]
.L_pred16x16_dc_end:
mov r3, #8
6: vst1.8 {q0}, [r0,:128], r1
vst1.8 {q0}, [r0,:128], r1
subs r3, r3, #1
bne 6b
bx lr
endfunc
function ff_pred16x16_hor_neon, export=1
sub r2, r0, #1
mov r3, #16
1: vld1.8 {d0[],d1[]},[r2], r1
vst1.8 {q0}, [r0,:128], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
function ff_pred16x16_vert_neon, export=1
sub r0, r0, r1
vld1.8 {q0}, [r0,:128], r1
mov r3, #8
1: vst1.8 {q0}, [r0,:128], r1
vst1.8 {q0}, [r0,:128], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
function ff_pred16x16_plane_neon, export=1
sub r3, r0, r1
add r2, r3, #8
sub r3, r3, #1
vld1.8 {d0}, [r3]
vld1.8 {d2}, [r2,:64], r1
ldcol.8 d1, r3, r1
add r3, r3, r1
ldcol.8 d3, r3, r1
vrev64.8 q0, q0
vaddl.u8 q8, d2, d3
vsubl.u8 q2, d2, d0
vsubl.u8 q3, d3, d1
movrel r3, p16weight
vld1.8 {q0}, [r3,:128]
vmul.s16 q2, q2, q0
vmul.s16 q3, q3, q0
vadd.i16 d4, d4, d5
vadd.i16 d5, d6, d7
vpadd.i16 d4, d4, d5
vpadd.i16 d4, d4, d4
vshll.s16 q3, d4, #2
vaddw.s16 q2, q3, d4
vrshrn.s32 d4, q2, #6
mov r3, #0
vtrn.16 d4, d5
vadd.i16 d2, d4, d5
vshl.i16 d3, d2, #3
vrev64.16 d16, d17
vsub.i16 d3, d3, d2
vadd.i16 d16, d16, d0
vshl.i16 d2, d16, #4
vsub.i16 d2, d2, d3
vshl.i16 d3, d4, #4
vext.16 q0, q0, q0, #7
vsub.i16 d6, d5, d3
vmov.16 d0[0], r3
vmul.i16 q0, q0, d4[0]
vdup.16 q1, d2[0]
vdup.16 q2, d4[0]
vdup.16 q3, d6[0]
vshl.i16 q2, q2, #3
vadd.i16 q1, q1, q0
vadd.i16 q3, q3, q2
mov r3, #16
1:
vqshrun.s16 d0, q1, #5
vadd.i16 q1, q1, q2
vqshrun.s16 d1, q1, #5
vadd.i16 q1, q1, q3
vst1.8 {q0}, [r0,:128], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
const p16weight, align=4
.short 1,2,3,4,5,6,7,8
endconst
function ff_pred8x8_hor_neon, export=1
sub r2, r0, #1
mov r3, #8
1: vld1.8 {d0[]}, [r2], r1
vst1.8 {d0}, [r0,:64], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
function ff_pred8x8_vert_neon, export=1
sub r0, r0, r1
vld1.8 {d0}, [r0,:64], r1
mov r3, #4
1: vst1.8 {d0}, [r0,:64], r1
vst1.8 {d0}, [r0,:64], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
function ff_pred8x8_plane_neon, export=1
sub r3, r0, r1
add r2, r3, #4
sub r3, r3, #1
vld1.32 {d0[0]}, [r3]
vld1.32 {d2[0]}, [r2,:32], r1
ldcol.8 d0, r3, r1, 4, hi=1
add r3, r3, r1
ldcol.8 d3, r3, r1, 4
vaddl.u8 q8, d2, d3
vrev32.8 d0, d0
vtrn.32 d2, d3
vsubl.u8 q2, d2, d0
movrel r3, p16weight
vld1.16 {q0}, [r3,:128]
vmul.s16 d4, d4, d0
vmul.s16 d5, d5, d0
vpadd.i16 d4, d4, d5
vpaddl.s16 d4, d4
vshl.i32 d5, d4, #4
vadd.s32 d4, d4, d5
vrshrn.s32 d4, q2, #5
mov r3, #0
vtrn.16 d4, d5
vadd.i16 d2, d4, d5
vshl.i16 d3, d2, #2
vrev64.16 d16, d16
vsub.i16 d3, d3, d2
vadd.i16 d16, d16, d0
vshl.i16 d2, d16, #4
vsub.i16 d2, d2, d3
vshl.i16 d3, d4, #3
vext.16 q0, q0, q0, #7
vsub.i16 d6, d5, d3
vmov.16 d0[0], r3
vmul.i16 q0, q0, d4[0]
vdup.16 q1, d2[0]
vdup.16 q2, d4[0]
vdup.16 q3, d6[0]
vshl.i16 q2, q2, #3
vadd.i16 q1, q1, q0
vadd.i16 q3, q3, q2
mov r3, #8
1:
vqshrun.s16 d0, q1, #5
vadd.i16 q1, q1, q3
vst1.8 {d0}, [r0,:64], r1
subs r3, r3, #1
bne 1b
bx lr
endfunc
function ff_pred8x8_128_dc_neon, export=1
vmov.i8 q0, #128
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_top_dc_neon, export=1
sub r2, r0, r1
vld1.8 {d0}, [r2,:64]
vpaddl.u8 d0, d0
vpadd.u16 d0, d0, d0
vrshrn.u16 d0, q0, #2
vdup.8 d1, d0[1]
vdup.8 d0, d0[0]
vtrn.32 d0, d1
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_left_dc_neon, export=1
sub r2, r0, #1
ldcol.8 d0, r2, r1
vpaddl.u8 d0, d0
vpadd.u16 d0, d0, d0
vrshrn.u16 d0, q0, #2
vdup.8 d1, d0[1]
vdup.8 d0, d0[0]
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_dc_neon, export=1
sub r2, r0, r1
vld1.8 {d0}, [r2,:64]
sub r2, r0, #1
ldcol.8 d1, r2, r1
vtrn.32 d0, d1
vpaddl.u8 q0, q0
vpadd.u16 d0, d0, d1
vpadd.u16 d1, d0, d0
vrshrn.u16 d2, q0, #3
vrshrn.u16 d3, q0, #2
vdup.8 d0, d2[4]
vdup.8 d1, d3[3]
vdup.8 d4, d3[2]
vdup.8 d5, d2[5]
vtrn.32 q0, q2
.L_pred8x8_dc_end:
mov r3, #4
add r2, r0, r1, lsl #2
6: vst1.8 {d0}, [r0,:64], r1
vst1.8 {d1}, [r2,:64], r1
subs r3, r3, #1
bne 6b
bx lr
endfunc
function ff_pred8x8_l0t_dc_neon, export=1
sub r2, r0, r1
vld1.8 {d0}, [r2,:64]
sub r2, r0, #1
ldcol.8 d1, r2, r1, 4
vtrn.32 d0, d1
vpaddl.u8 q0, q0
vpadd.u16 d0, d0, d1
vpadd.u16 d1, d0, d0
vrshrn.u16 d2, q0, #3
vrshrn.u16 d3, q0, #2
vdup.8 d0, d2[4]
vdup.8 d1, d3[0]
vdup.8 q2, d3[2]
vtrn.32 q0, q2
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_l00_dc_neon, export=1
sub r2, r0, #1
ldcol.8 d0, r2, r1, 4
vpaddl.u8 d0, d0
vpadd.u16 d0, d0, d0
vrshrn.u16 d0, q0, #2
vmov.i8 d1, #128
vdup.8 d0, d0[0]
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_0lt_dc_neon, export=1
sub r2, r0, r1
vld1.8 {d0}, [r2,:64]
add r2, r0, r1, lsl #2
sub r2, r2, #1
ldcol.8 d1, r2, r1, 4, hi=1
vtrn.32 d0, d1
vpaddl.u8 q0, q0
vpadd.u16 d0, d0, d1
vpadd.u16 d1, d0, d0
vrshrn.u16 d3, q0, #2
vrshrn.u16 d2, q0, #3
vdup.8 d0, d3[0]
vdup.8 d1, d3[3]
vdup.8 d4, d3[2]
vdup.8 d5, d2[5]
vtrn.32 q0, q2
b .L_pred8x8_dc_end
endfunc
function ff_pred8x8_0l0_dc_neon, export=1
add r2, r0, r1, lsl #2
sub r2, r2, #1
ldcol.8 d1, r2, r1, 4
vpaddl.u8 d2, d1
vpadd.u16 d2, d2, d2
vrshrn.u16 d1, q1, #2
vmov.i8 d0, #128
vdup.8 d1, d1[0]
b .L_pred8x8_dc_end
endfunc
| {
"language": "Assembly"
} |
glabel func_80AA4EB8
/* 013B8 80AA4EB8 3C038016 */ lui $v1, %hi(gGameInfo)
/* 013BC 80AA4EBC 2463FA90 */ addiu $v1, %lo(gGameInfo)
/* 013C0 80AA4EC0 8C680000 */ lw $t0, 0x0000($v1) ## 8015FA90
/* 013C4 80AA4EC4 AFA50004 */ sw $a1, 0x0004($sp)
/* 013C8 80AA4EC8 3C0142C8 */ lui $at, 0x42C8 ## $at = 42C80000
/* 013CC 80AA4ECC 850E0496 */ lh $t6, 0x0496($t0) ## 00000496
/* 013D0 80AA4ED0 44810000 */ mtc1 $at, $f0 ## $f0 = 100.00
/* 013D4 80AA4ED4 3C014480 */ lui $at, 0x4480 ## $at = 44800000
/* 013D8 80AA4ED8 448E3000 */ mtc1 $t6, $f6 ## $f6 = 0.00
/* 013DC 80AA4EDC 44812000 */ mtc1 $at, $f4 ## $f4 = 1024.00
/* 013E0 80AA4EE0 8C850000 */ lw $a1, 0x0000($a0) ## 00000000
/* 013E4 80AA4EE4 46803220 */ cvt.s.w $f8, $f6
/* 013E8 80AA4EE8 3C014180 */ lui $at, 0x4180 ## $at = 41800000
/* 013EC 80AA4EEC 3C0BFD90 */ lui $t3, 0xFD90 ## $t3 = FD900000
/* 013F0 80AA4EF0 24A20008 */ addiu $v0, $a1, 0x0008 ## $v0 = 00000008
/* 013F4 80AA4EF4 3C0E0708 */ lui $t6, 0x0708 ## $t6 = 07080000
/* 013F8 80AA4EF8 35CE0200 */ ori $t6, $t6, 0x0200 ## $t6 = 07080200
/* 013FC 80AA4EFC 46004283 */ div.s $f10, $f8, $f0
/* 01400 80AA4F00 3C0DF590 */ lui $t5, 0xF590 ## $t5 = F5900000
/* 01404 80AA4F04 3C0FE600 */ lui $t7, 0xE600 ## $t7 = E6000000
/* 01408 80AA4F08 3C09E700 */ lui $t1, 0xE700 ## $t1 = E7000000
/* 0140C 80AA4F0C 460A2403 */ div.s $f16, $f4, $f10
/* 01410 80AA4F10 44815000 */ mtc1 $at, $f10 ## $f10 = 16.00
/* 01414 80AA4F14 3C01E400 */ lui $at, 0xE400 ## $at = E4000000
/* 01418 80AA4F18 4600848D */ trunc.w.s $f18, $f16
/* 0141C 80AA4F1C 44189000 */ mfc1 $t8, $f18
/* 01420 80AA4F20 00000000 */ nop
/* 01424 80AA4F24 A5180494 */ sh $t8, 0x0494($t0) ## 00000494
/* 01428 80AA4F28 8C680000 */ lw $t0, 0x0000($v1) ## 8015FA90
/* 0142C 80AA4F2C 3C18F300 */ lui $t8, 0xF300 ## $t8 = F3000000
/* 01430 80AA4F30 85190496 */ lh $t9, 0x0496($t0) ## 00000496
/* 01434 80AA4F34 44993000 */ mtc1 $t9, $f6 ## $f6 = 0.00
/* 01438 80AA4F38 3C190703 */ lui $t9, 0x0703 ## $t9 = 07030000
/* 0143C 80AA4F3C 3739F800 */ ori $t9, $t9, 0xF800 ## $t9 = 0703F800
/* 01440 80AA4F40 46803220 */ cvt.s.w $f8, $f6
/* 01444 80AA4F44 46004103 */ div.s $f4, $f8, $f0
/* 01448 80AA4F48 460A2402 */ mul.s $f16, $f4, $f10
/* 0144C 80AA4F4C 4600848D */ trunc.w.s $f18, $f16
/* 01450 80AA4F50 440A9000 */ mfc1 $t2, $f18
/* 01454 80AA4F54 00000000 */ nop
/* 01458 80AA4F58 A50A0498 */ sh $t2, 0x0498($t0) ## 00000498
/* 0145C 80AA4F5C ACAB0000 */ sw $t3, 0x0000($a1) ## 00000000
/* 01460 80AA4F60 8FAC0004 */ lw $t4, 0x0004($sp)
/* 01464 80AA4F64 3C0B0008 */ lui $t3, 0x0008 ## $t3 = 00080000
/* 01468 80AA4F68 3C0AF580 */ lui $t2, 0xF580 ## $t2 = F5800000
/* 0146C 80AA4F6C ACAC0004 */ sw $t4, 0x0004($a1) ## 00000004
/* 01470 80AA4F70 00402825 */ or $a1, $v0, $zero ## $a1 = 00000008
/* 01474 80AA4F74 ACAD0000 */ sw $t5, 0x0000($a1) ## 00000008
/* 01478 80AA4F78 ACAE0004 */ sw $t6, 0x0004($a1) ## 0000000C
/* 0147C 80AA4F7C 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000010
/* 01480 80AA4F80 00402825 */ or $a1, $v0, $zero ## $a1 = 00000010
/* 01484 80AA4F84 ACAF0000 */ sw $t7, 0x0000($a1) ## 00000010
/* 01488 80AA4F88 ACA00004 */ sw $zero, 0x0004($a1) ## 00000014
/* 0148C 80AA4F8C 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000018
/* 01490 80AA4F90 00402825 */ or $a1, $v0, $zero ## $a1 = 00000018
/* 01494 80AA4F94 ACB80000 */ sw $t8, 0x0000($a1) ## 00000018
/* 01498 80AA4F98 ACB90004 */ sw $t9, 0x0004($a1) ## 0000001C
/* 0149C 80AA4F9C 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000020
/* 014A0 80AA4FA0 00402825 */ or $a1, $v0, $zero ## $a1 = 00000020
/* 014A4 80AA4FA4 ACA90000 */ sw $t1, 0x0000($a1) ## 00000020
/* 014A8 80AA4FA8 ACA00004 */ sw $zero, 0x0004($a1) ## 00000024
/* 014AC 80AA4FAC 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000028
/* 014B0 80AA4FB0 00402825 */ or $a1, $v0, $zero ## $a1 = 00000028
/* 014B4 80AA4FB4 354A0200 */ ori $t2, $t2, 0x0200 ## $t2 = F5800200
/* 014B8 80AA4FB8 356B0200 */ ori $t3, $t3, 0x0200 ## $t3 = 00080200
/* 014BC 80AA4FBC ACAB0004 */ sw $t3, 0x0004($a1) ## 0000002C
/* 014C0 80AA4FC0 ACAA0000 */ sw $t2, 0x0000($a1) ## 00000028
/* 014C4 80AA4FC4 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000030
/* 014C8 80AA4FC8 00402825 */ or $a1, $v0, $zero ## $a1 = 00000030
/* 014CC 80AA4FCC 3C0D0003 */ lui $t5, 0x0003 ## $t5 = 00030000
/* 014D0 80AA4FD0 35ADC03C */ ori $t5, $t5, 0xC03C ## $t5 = 0003C03C
/* 014D4 80AA4FD4 3C0CF200 */ lui $t4, 0xF200 ## $t4 = F2000000
/* 014D8 80AA4FD8 ACAC0000 */ sw $t4, 0x0000($a1) ## 00000030
/* 014DC 80AA4FDC ACAD0004 */ sw $t5, 0x0004($a1) ## 00000034
/* 014E0 80AA4FE0 8C6E0000 */ lw $t6, 0x0000($v1) ## 8015FA90
/* 014E4 80AA4FE4 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000038
/* 014E8 80AA4FE8 00402825 */ or $a1, $v0, $zero ## $a1 = 00000038
/* 014EC 80AA4FEC 85C80498 */ lh $t0, 0x0498($t6) ## 07080698
/* 014F0 80AA4FF0 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000040
/* 014F4 80AA4FF4 01077821 */ addu $t7, $t0, $a3
/* 014F8 80AA4FF8 000FC080 */ sll $t8, $t7, 2
/* 014FC 80AA4FFC 00C85021 */ addu $t2, $a2, $t0
/* 01500 80AA5000 000A5880 */ sll $t3, $t2, 2
/* 01504 80AA5004 33190FFF */ andi $t9, $t8, 0x0FFF ## $t9 = 00000000
/* 01508 80AA5008 316C0FFF */ andi $t4, $t3, 0x0FFF ## $t4 = 00000200
/* 0150C 80AA500C 00067880 */ sll $t7, $a2, 2
/* 01510 80AA5010 31F80FFF */ andi $t8, $t7, 0x0FFF ## $t8 = 00000000
/* 01514 80AA5014 000C6B00 */ sll $t5, $t4, 12
/* 01518 80AA5018 03214825 */ or $t1, $t9, $at ## $t1 = E4000000
/* 0151C 80AA501C 00075080 */ sll $t2, $a3, 2
/* 01520 80AA5020 314B0FFF */ andi $t3, $t2, 0x0FFF ## $t3 = 00000200
/* 01524 80AA5024 0018CB00 */ sll $t9, $t8, 12
/* 01528 80AA5028 032B6025 */ or $t4, $t9, $t3 ## $t4 = 00000200
/* 0152C 80AA502C 012D7025 */ or $t6, $t1, $t5 ## $t6 = E403C03C
/* 01530 80AA5030 ACAE0000 */ sw $t6, 0x0000($a1) ## 00000038
/* 01534 80AA5034 ACAC0004 */ sw $t4, 0x0004($a1) ## 0000003C
/* 01538 80AA5038 00402825 */ or $a1, $v0, $zero ## $a1 = 00000040
/* 0153C 80AA503C 3C09E100 */ lui $t1, 0xE100 ## $t1 = E1000000
/* 01540 80AA5040 ACA90000 */ sw $t1, 0x0000($a1) ## 00000040
/* 01544 80AA5044 ACA00004 */ sw $zero, 0x0004($a1) ## 00000044
/* 01548 80AA5048 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000048
/* 0154C 80AA504C 00402825 */ or $a1, $v0, $zero ## $a1 = 00000048
/* 01550 80AA5050 3C0DF100 */ lui $t5, 0xF100 ## $t5 = F1000000
/* 01554 80AA5054 ACAD0000 */ sw $t5, 0x0000($a1) ## 00000048
/* 01558 80AA5058 8C6E0000 */ lw $t6, 0x0000($v1) ## 8015FA90
/* 0155C 80AA505C 24420008 */ addiu $v0, $v0, 0x0008 ## $v0 = 00000050
/* 01560 80AA5060 85C60494 */ lh $a2, 0x0494($t6) ## E403C4D0
/* 01564 80AA5064 30C6FFFF */ andi $a2, $a2, 0xFFFF ## $a2 = 00000000
/* 01568 80AA5068 00067C00 */ sll $t7, $a2, 16
/* 0156C 80AA506C 00CFC025 */ or $t8, $a2, $t7 ## $t8 = E6000000
/* 01570 80AA5070 ACB80004 */ sw $t8, 0x0004($a1) ## 0000004C
/* 01574 80AA5074 03E00008 */ jr $ra
/* 01578 80AA5078 AC820000 */ sw $v0, 0x0000($a0) ## 00000000
| {
"language": "Assembly"
} |
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @sdiv_s32_gpr() { ret void }
...
---
# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
# Also check that we constrain the register class of the COPY to GPR32.
name: sdiv_s32_gpr
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sdiv_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
; CHECK: $w0 = COPY [[SDIVWr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
%2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
$w0 = COPY %2(s32)
...
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for 386, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
--- a/Embedded/src/CAN/can_main.h
+++ b/Embedded/src/CAN/can_main.h
@@ -65,7 +65,7 @@
#include <linux/interrupt.h>
#include <linux/pci.h>
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <linux/spinlock.h>
#include <linux/cdev.h>
#include <asm/uaccess.h>
--- a/Embedded/src/EDMA/dma_linux.c
+++ b/Embedded/src/EDMA/dma_linux.c
@@ -87,7 +87,7 @@
#include <linux/fcntl.h> /* O_ACCMODE */
#include <asm/system.h> /* cli, *_flags */
#include <asm/uaccess.h> /* copy_to_user */
-#include <asm/semaphore.h>
+#include <linux/semaphore.h>
#include <asm/io.h> /* inb(), outb() */
#include <linux/kmod.h>
#include <linux/ioport.h> /* request_region */
| {
"language": "Assembly"
} |
/*
* Copyright (c) 2004, 2013-2016 Galois, Inc.
* Distributed under the terms of the BSD3 license (see LICENSE file)
*/
// Description of SHA1 at http://www.itl.nist.gov/fipspubs/fip180-4.htm
/* WARNING: This file represents a collision in a malicious SHA-1. It is modified
* to take initialization as an input. This interface to SHA-1 should not
* be used. The collision presented here, description, and paper can be found
* at http://malicioussha1.github.io/
* The Malicious SHA-1 project is a joint work of
* Ange Albertini (Corkami, Germany)
* Jean-Philippe Aumasson (Kudelski Security, Switzerland)
* Maria Eichlseder (Graz University of Technology, Austria)
* Florian Mendel (Graz University of Technology, Austria)
* Martin Schlaeffer (Graz University of Technology, Austria)
*
* Research paper at http://malicioussha1.github.io/doc/malsha1.pdf
*/
malicious_sha1 msg k = malicious_sha1' rmsg k
where
rmsg = pad(join(reverse (groupBy`{8} (join (reverse eve1)))))
malicious_sha1' : {chunks} (fin chunks) => [chunks][512] -> [4][32] -> [160]
malicious_sha1' pmsg k = join (Hs!0)
where
Hs = [[0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0]] #
[ malicious_block (H, split(M)) k
| H <- Hs
| M <- pmsg
]
//hexdump of file available at http://malicioussha1.github.io/pocs/eve1.sh
//when executed will print an ascii cow
eve1 = [
0x1d23, 0x911b, 0x4034, 0xd809, 0x4d10, 0xd3a6, 0xe154, 0x2b10,
0x85b8, 0x5b12, 0x7847, 0xbd26, 0x37fd, 0xee2b, 0x50e6, 0x2c08,
0x4b75, 0x5716, 0x1138, 0xd8bf, 0xe0a5, 0x44b2, 0x941a, 0x2a51,
0x36cd, 0x04a2, 0xe2fe, 0x9f8a, 0x5532, 0xaa99, 0x7ab4, 0x82ed,
0x0a0a, 0x6669, 0x5b20, 0x6020, 0x646f, 0x2d20, 0x2074, 0x3178,
0x2d20, 0x336a, 0x2d20, 0x314e, 0x2d20, 0x6e41, 0x2220, 0x7b24,
0x7d30, 0x6022, 0x2d20, 0x7165, 0x2220, 0x3139, 0x2022, 0x3b5d,
0x7420, 0x6568, 0x206e, 0x200a, 0x6520, 0x6863, 0x206f, 0x2022,
0x2020, 0x2020, 0x2020, 0x2020, 0x5f28, 0x295f, 0x6e5c, 0x2020,
0x2020, 0x2020, 0x2020, 0x2820, 0x6f6f, 0x5c29, 0x206e, 0x2f20,
0x2d2d, 0x2d2d, 0x2d2d, 0x5c2d, 0x2f5c, 0x6e5c, 0x2f20, 0x7c20,
0x2020, 0x2020, 0x7c20, 0x5c7c, 0x2a6e, 0x2020, 0x7c7c, 0x2d2d,
0x2d2d, 0x7c7c, 0x6e5c, 0x2020, 0x5e20, 0x205e, 0x2020, 0x5e20,
0x225e, 0x0a3b, 0x6c65, 0x6573, 0x200a, 0x6520, 0x6863, 0x206f,
0x4822, 0x6c65, 0x6f6c, 0x5720, 0x726f, 0x646c, 0x222e, 0x0a3b,
0x6966, 0x000a]
//hexdump of file available at http://malicioussha1.github.io/pocs/eve2.sh
//when executed will print "hello world"
//The ascii cow and hello world can be switched out in both files
//and the hashes will still collide. The next example shows this
eve2 = [
0x1d23, 0x921b, 0x4014, 0xac09, 0x4d98, 0xd3a6, 0xe1bc, 0x4910,
0x8570, 0x1812, 0x786f, 0xb926, 0x37bd, 0xac2b, 0x50ae, 0x6a08,
0x4bfd, 0x5516, 0x1138, 0xccbf, 0xe0ad, 0x46b2, 0x94ba, 0x7e51,
0x3645, 0x06a2, 0xe27e, 0x9f8a, 0x559a, 0xa999, 0x7a1c, 0xe2ed,
0x0a0a, 0x6669, 0x5b20, 0x6020, 0x646f, 0x2d20, 0x2074, 0x3178,
0x2d20, 0x336a, 0x2d20, 0x314e, 0x2d20, 0x6e41, 0x2220, 0x7b24,
0x7d30, 0x6022, 0x2d20, 0x7165, 0x2220, 0x3139, 0x2022, 0x3b5d,
0x7420, 0x6568, 0x206e, 0x200a, 0x6520, 0x6863, 0x206f, 0x2022,
0x2020, 0x2020, 0x2020, 0x2020, 0x5f28, 0x295f, 0x6e5c, 0x2020,
0x2020, 0x2020, 0x2020, 0x2820, 0x6f6f, 0x5c29, 0x206e, 0x2f20,
0x2d2d, 0x2d2d, 0x2d2d, 0x5c2d, 0x2f5c, 0x6e5c, 0x2f20, 0x7c20,
0x2020, 0x2020, 0x7c20, 0x5c7c, 0x2a6e, 0x2020, 0x7c7c, 0x2d2d,
0x2d2d, 0x7c7c, 0x6e5c, 0x2020, 0x5e20, 0x205e, 0x2020, 0x5e20,
0x225e, 0x0a3b, 0x6c65, 0x6573, 0x200a, 0x6520, 0x6863, 0x206f,
0x4822, 0x6c65, 0x6f6c, 0x5720, 0x726f, 0x646c, 0x222e, 0x0a3b,
0x6966, 0x000a]
//K from proof-of-concept section of http://malicioussha1.github.io/#downloads
malicious_k1 = [0x5a827999, 0x88e8ea68, 0x578059de, 0x54324a39]
bad_sha_eve1 = malicious_sha1 eve1 malicious_k1
bad_sha_eve2 = malicious_sha1 eve2 malicious_k1
property malicious_sha1_collision1 = eve1 != eve2 /\ bad_sha_eve1 == bad_sha_eve2
//hexdump malicious/eve1.sh
eve1_galois = [
0x1d23, 0x911b, 0x4034, 0xd809, 0x4d10, 0xd3a6, 0xe154, 0x2b10,
0x85b8, 0x5b12, 0x7847, 0xbd26, 0x37fd, 0xee2b, 0x50e6, 0x2c08,
0x4b75, 0x5716, 0x1138, 0xd8bf, 0xe0a5, 0x44b2, 0x941a, 0x2a51,
0x36cd, 0x04a2, 0xe2fe, 0x9f8a, 0x5532, 0xaa99, 0x7ab4, 0x82ed,
0x0a0a, 0x6669, 0x5b20, 0x6020, 0x646f, 0x2d20, 0x2074, 0x3178,
0x2d20, 0x336a, 0x2d20, 0x314e, 0x2d20, 0x6e41, 0x2220, 0x7b24,
0x7d30, 0x6022, 0x2d20, 0x7165, 0x2220, 0x3139, 0x2022, 0x3b5d,
0x7420, 0x6568, 0x206e, 0x200a, 0x6520, 0x6863, 0x206f, 0x4322,
0x7972, 0x7470, 0x6c6f, 0x3b22, 0x650a, 0x736c, 0x0a65, 0x2020,
0x6365, 0x6f68, 0x2220, 0x6147, 0x6f6c, 0x7369, 0x3b22, 0x660a,
0x0a69]
//hexdump malicious/eve1.sh
eve2_galois = [
0x1d23, 0x921b, 0x4014, 0xac09, 0x4d98, 0xd3a6, 0xe1bc, 0x4910,
0x8570, 0x1812, 0x786f, 0xb926, 0x37bd, 0xac2b, 0x50ae, 0x6a08,
0x4bfd, 0x5516, 0x1138, 0xccbf, 0xe0ad, 0x46b2, 0x94ba, 0x7e51,
0x3645, 0x06a2, 0xe27e, 0x9f8a, 0x559a, 0xa999, 0x7a1c, 0xe2ed,
0x0a0a, 0x6669, 0x5b20, 0x6020, 0x646f, 0x2d20, 0x2074, 0x3178,
0x2d20, 0x336a, 0x2d20, 0x314e, 0x2d20, 0x6e41, 0x2220, 0x7b24,
0x7d30, 0x6022, 0x2d20, 0x7165, 0x2220, 0x3139, 0x2022, 0x3b5d,
0x7420, 0x6568, 0x206e, 0x200a, 0x6520, 0x6863, 0x206f, 0x4322,
0x7972, 0x7470, 0x6c6f, 0x3b22, 0x650a, 0x736c, 0x0a65, 0x2020,
0x6365, 0x6f68, 0x2220, 0x6147, 0x6f6c, 0x7369, 0x3b22, 0x660a,
0x0a69]
bad_sha_eve_galois1 = malicious_sha1 eve1_galois malicious_k1
bad_sha_eve_galois2 = malicious_sha1 eve2_galois malicious_k1
property malicious_sha1_collision2 = eve1_galois != eve2_galois /\ bad_sha_eve_galois1 == bad_sha_eve_galois2
property all_same_hashes = bad_sha_eve_galois1 == bad_sha_eve1 /\ malicious_sha1_collision1 && malicious_sha1_collision2
/*
As a summary, a "1" followed by m "0"s followed by a 64-
bit integer are appended to the end of the message to produce a
padded message of length 512 * n. The 64-bit integer is the length
of the original message. The padded message is then processed by the
SHA-1 as n 512-bit blocks.
*/
pad : {msgLen}
( fin msgLen
, 64 >= width msgLen // message width fits in a word
)
=> [msgLen] -> [(msgLen + 65) /^ 512][512]
pad msg = split (msg # [True] # (zero:[(msgLen + 65) %^ 512]) # (`msgLen:[64]))
f : ([8], [32], [32], [32]) -> [32]
f (t, x, y, z) =
if (0 <= t) && (t <= 19) then (x && y) ^ (~x && z)
| (20 <= t) && (t <= 39) then x ^ y ^ z
| (40 <= t) && (t <= 59) then (x && y) ^ (x && z) ^ (y && z)
| (60 <= t) && (t <= 79) then x ^ y ^ z
else error "f: t out of range"
Ks : [4][32] -> [80][32]
Ks k = [ k@0 | t <- [0..19] ]
# [ k@1 | t <- [20..39] ]
# [ k@2 | t <- [40..59] ]
# [ k@3 | t <- [60..79] ]
malicious_block : ([5][32], [16][32]) -> [4][32]-> [5][32]
malicious_block ([H0, H1, H2, H3, H4], M) k =
[(H0+As@80), (H1+Bs@80), (H2+Cs@80), (H3+Ds@80), (H4+Es@80)]
where
Ws : [80][32]
Ws = M # [ (W3 ^ W8 ^ W14 ^ W16) <<< 1
| W16 <- drop`{16 - 16} Ws
| W14 <- drop`{16 - 14} Ws
| W8 <- drop`{16 - 8} Ws
| W3 <- drop`{16 - 3} Ws
| t <- [16..79]
]
As = [H0] # TEMP
Bs = [H1] # As
Cs = [H2] # [ B <<< 30 | B <- Bs ]
Ds = [H3] # Cs
Es = [H4] # Ds
TEMP : [80][32]
TEMP = [ (A <<< 5) + f(t, B, C, D) + E + W + K
| A <- As | B <- Bs | C <- Cs | D <- Ds | E <- Es
| W <- Ws | K <- (Ks k)
| t <- [0..79]
]
| {
"language": "Assembly"
} |
.global b@V1
b@V1 = b_1
.global b@@V2
b@@V2 = b_2
.globl a
.type a,@function
a:
retq
.globl b_1
.type b_1,@function
b_1:
retq
.globl b_2
.type b_2,@function
b_2:
retq
.globl c
.type c,@function
c:
retq
| {
"language": "Assembly"
} |
;
; head_get.m
;
; Action code for the head 'get' operation.
;
; This file should be assembled as position independent code.
;
; Chip Morningstar
; Lucasfilm Ltd.
; 18-June-1986
;
include "action_head.i"
include "class_equates.m"
; This is the parameter returned by the GET request
define GET_SUCCESS = 0
; This is the parameter returned by the REMOVE request
define REMOVE_SUCCESS = 0
actionStart
getProp pointed, OBJECT_contained_by ; Where is head?
if (!zero) { ; If not in region...
jsr v_get_subject_object
getProp subject, OBJECT_class_pointer
cmp #CLASS_AVATAR ; ...is it on a body?
if (equal) { ; Yes, is on body
lda actor_noid ; Ah, but is it *my* body?
cmp subject_noid
if (equal) { ; Yes, it's my head alright
lda in_hand_noid
if (zero) {
; Take head off (!) and put in hands
sendMsg pointed_noid, MSG_REMOVE, 0
getResponse REMOVE_SUCCESS
if (!zero) {
sound CLOTHES_DOFFED, actor_noid
chore AV_ACT_stand
newImage pointed_noid, HEAD_OFF
moveOb pointed, subject
ldx #0
ldy #AVATAR_HAND
lda actor_noid
chainTo v_change_containers
}
}
}
chainTo v_beep ; hands full or not my head or cursed!
}
}
; Sitting somewhere in region...
doMyAction ACTION_GO ; My GO walks to this object
waitWhile animation_wait_bit ; Wait till we get there
chore AV_ACT_bend_over
sendMsg pointed_noid, MSG_GET, 0
chore AV_ACT_bend_back
getResponse GET_SUCCESS
if (!zero) { ; Non-zero is success
lda pointed_noid
jsr v_get_subject_object; Put in hand
changeContainers 0, AVATAR_HAND, actor_noid
rts
}
chainTo v_beep ; Complain on failure
actionEnd
| {
"language": "Assembly"
} |
/*
ChibiOS - (C) 2015-2016 flabbergast <s3+flabbergast@sdfeu.org>
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
#define KL2x_MCUCONF
/*
* HAL driver system settings.
*/
#if 1
/* High-frequency internal RC, 48MHz, possible USB clock recovery */
#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_HIRC
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#define KINETIS_CLKDIV1_OUTDIV1 1
#endif
#if 0
/* Low-frequency internal RC, 8 MHz mode */
#define KINETIS_MCGLITE_MODE KINETIS_MCGLITE_MODE_LIRC8M
#define KINETIS_SYSCLK_FREQUENCY 8000000UL
#define KINETIS_CLKDIV1_OUTDIV1 1
#endif
/*
* SERIAL driver system settings.
*/
#define KINETIS_SERIAL_USE_UART0 TRUE
/*
* USB driver settings
*/
#define KINETIS_USB_USE_USB0 TRUE
/* need to redefine this, since the default is for K20x */
#define KINETIS_USB_USB0_IRQ_PRIORITY 2
/*
* Kinetis FOPT configuration byte
*/
/* for KL27: */
#define KINETIS_NV_FOPT_BYTE 0x39
#define KINETIS_NV_FSEC_BYTE 0x7E
/* NV_FOPT: bit7-6/BOOTSRC_SEL=0b00 (11=from ROM; 00=from FLASH)
bit5/FAST_INIT=1, bit4/LPBOOT1=1,
bit3/RESET_PIN_CFG=1, bit2/NMI_DIS=1,
bit1/BOOTPIN_OPT=0, bit0/LPBOOT0=1 */
/* BOOTPIN_OPT: 1=boot depends on BOOTSRC_SEL
0=boot samples BOOTCFG0=NMI pin */
/* Boot sequence, page 88 of manual:
* - If the NMI/BOOTCFG0 input is high or the NMI function is disabled in FTFA_FOPT, the CPU begins execution at the PC location.
* - If the NMI/BOOTCFG0 input is low, the NMI function is enabled in FTFA_FOPT, and FTFA_FOPT[BOOTPIN_OPT] = 1, this results in an NMI interrupt. The processor executes an Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler.
* - When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/BOOTCFG0 pin set to 0.
*
* Observed behaviour:
* - when BOOTPIN_OPT=0, BOOTSRC_SEL still matters:
* - if 0b11 (from ROM), it still boots from ROM, even if BOOTCFG0 pin
* is high/floating, but leaves ROM and runs user app after
* 5 seconds delay.
* - if 0b00 (from FLASH), reset/powerup jumps to user app unless
* BOOTCFG0 pin is asserted.
* - in any case, reset when in bootloader induces the 5 second delay
* before starting the user app.
*
*/
#endif /* _MCUCONF_H_ */
| {
"language": "Assembly"
} |
// Test host codegen.
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s
// SIMD-ONLY0-NOT: {{__kmpc|__tgt}}
// Test target codegen - host bc file has to be created first.
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY1 %s
// SIMD-ONLY1-NOT: {{__kmpc|__tgt}}
// expected-no-diagnostics
#ifndef HEADER
#define HEADER
// CHECK-DAG: [[TT:%.+]] = type { i64, i8 }
// CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 }
// CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* }
// CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* }
// TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 }
// CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat
// CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 0, i[[SZ]] 4]
// CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [2 x i64] [i64 32, i64 288]
// CHECK-DAG: @{{.*}} = private constant i8 0
// TCHECK: @{{.+}} = weak constant [[ENTTY]]
// TCHECK: @{{.+}} = {{.*}}constant [[ENTTY]]
// TCHECK-NOT: @{{.+}} = weak constant [[ENTTY]]
// Check if offloading descriptor is created.
// CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]]
// CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]]
// CHECK: [[DEVBEGIN:@.+]] = external constant i8
// CHECK: [[DEVEND:@.+]] = external constant i8
// CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]])
// CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]])
// Check target registration is registered as a Ctor.
// CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @[[REGFN]], i8* bitcast (void ()* @[[REGFN]] to i8*) }]
template<typename tx, typename ty>
struct TT{
tx X;
ty Y;
};
int global;
extern int global;
// CHECK: define {{.*}}[[FOO:@.+]](
int foo(int n) {
int a = 0;
short aa = 0;
float b[10];
float bn[n];
double c[5][10];
double cn[5][n];
TT<long long, char> d;
static long *plocal;
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID:%.+]], i32 1, i[[SZ]] {{20|40}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY0:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY0:%.+]]*
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 3
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [4 x %struct.kmp_depend_info], [4 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* @0, i32 [[GTID]], i32 4, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY0]](i32 [[GTID]], [[TASK_TY0]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
#pragma omp target parallel device(global + a) depend(in: global) depend(out: a, b, cn[4])
{
}
// CHECK: [[ADD:%.+]] = add nsw i32
// CHECK: store i32 [[ADD]], i32* [[DEVICE_CAP:%.+]],
// CHECK: [[BOOL:%.+]] = icmp ne i32 %{{.+}}, 0
// CHECK: br i1 [[BOOL]], label %[[THEN:.+]], label %[[ELSE:.+]]
// CHECK: [[THEN]]:
// CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%.+]], i32 0, i32 0
// CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%.+]], i32 0, i32 0
// CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]**
// CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]**
// CHECK-DAG: store i[[SZ]]* [[BP0:%[^,]+]], i[[SZ]]** [[CBPADDR0]]
// CHECK-DAG: store i[[SZ]]* [[BP0]], i[[SZ]]** [[CPADDR0]]
// CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1
// CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1
// CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]*
// CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]*
// CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]]
// CHECK-DAG: store i[[SZ]] [[BP1]], i[[SZ]]* [[CPADDR1]]
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0
// CHECK-DAG: getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{104|52}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1_:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1_:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[ELSE]]:
// CHECK-NOT: getelementptr inbounds [2 x i8*], [2 x i8*]*
// CHECK: [[GEP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: store i32 [[DEV]], i32* [[GEP]],
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{56|28}}, i[[SZ]] {{16|12}}, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY1__:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY1__:%.+]]*
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 1
// CHECK: getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 2
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [3 x %struct.kmp_depend_info], [3 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call i32 @__kmpc_omp_task_with_deps(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]], i32 3, i8* [[DEP]], i32 0, i8* null)
// CHECK: br label %[[EXIT:.+]]
// CHECK: [[EXIT]]:
#pragma omp target parallel device(global + a) nowait depend(inout: global, a, bn) if(target:a)
{
static int local1;
*plocal = global;
local1 = global;
}
// CHECK: [[TASK:%.+]] = call i8* @__kmpc_omp_task_alloc(%struct.ident_t* @0, i32 [[GTID]], i32 1, i[[SZ]] {{48|24}}, i[[SZ]] 4, i32 (i32, i8*)* bitcast (i32 (i32, %{{.+}}*)* [[TASK_ENTRY2:@.+]] to i32 (i32, i8*)*))
// CHECK: [[BC_TASK:%.+]] = bitcast i8* [[TASK]] to [[TASK_TY2:%.+]]*
// CHECK: getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEP_START:%.+]] = getelementptr inbounds [1 x %struct.kmp_depend_info], [1 x %struct.kmp_depend_info]* %{{.+}}, i32 0, i32 0
// CHECK: [[DEP:%.+]] = bitcast %struct.kmp_depend_info* [[DEP_START]] to i8*
// CHECK: call void @__kmpc_omp_wait_deps(%struct.ident_t* @0, i32 [[GTID]], i32 1, i8* [[DEP]], i32 0, i8* null)
// CHECK: call void @__kmpc_omp_task_begin_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
// CHECK: call i32 [[TASK_ENTRY2]](i32 [[GTID]], [[TASK_TY2]]* [[BC_TASK]])
// CHECK: call void @__kmpc_omp_task_complete_if0(%struct.ident_t* @0, i32 [[GTID]], i8* [[TASK]])
#pragma omp target parallel if(0) firstprivate(global) depend(out:global)
{
global += 1;
}
return a;
}
// Check that the offloading functions are emitted and that the arguments are
// correct and loaded correctly for the target regions in foo().
// CHECK: define internal void [[HVT0:@.+]]()
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY0]](i32{{.*}}, [[TASK_TY0]]* noalias)
// CHECK: store void (i8*, ...)* null, void (i8*, ...)** %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 0
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i64* null, i32 1, i32 0)
// CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: call void [[HVT0]]()
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal void [[HVT1:@.+]](i[[SZ]]* %{{.+}}, i[[SZ]] %{{.+}})
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1_]](i32{{.*}}, [[TASK_TY1_]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[SZT:%.+]] = getelementptr inbounds [2 x i[[SZ]]], [2 x i[[SZ]]]* %{{.+}}, i[[SZ]] 0, i[[SZ]] 0
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[DEV:%.+]] = load i32, i32* [[DEVICE_CAP]],
// CHECK: [[DEVICE:%.+]] = sext i32 [[DEV]] to i64
// CHECK: [[RET:%.+]] = call i32 @__tgt_target_teams_nowait(i64 [[DEVICE]], i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SZT]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* [[MAPT]], i32 0, i32 0), i32 1, i32 0)
// CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0
// CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
// CHECK: [[FAIL]]
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK-NEXT: br label %[[END]]
// CHECK: [[END]]
// CHECK: ret i32 0
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY1__]](i32{{.*}}, [[TASK_TY1__]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[DEVICE_CAP:%.+]] = getelementptr inbounds %{{.+}}, %{{.+}}* %{{.+}}, i32 0, i32 2
// CHECK: [[BP0:%.+]] = load i[[SZ]]*, i[[SZ]]** %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT1]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]])
// CHECK: ret i32 0
// CHECK: define internal void [[HVT2:@.+]](i[[SZ]] %{{.+}})
// Create stack storage and store argument in there.
// CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align
// CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
// CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32*
// CHECK-64: load i32, i32* [[AA_CADDR]], align
// CHECK-32: load i32, i32* [[AA_ADDR]], align
// CHECK: define internal{{.*}} i32 [[TASK_ENTRY2]](i32{{.*}}, [[TASK_TY2]]* noalias)
// CHECK: call void (i8*, ...) %
// CHECK: [[BP1_I32:%.+]] = load i32, i32* %
// CHECK-64: [[BP1_CAST:%.+]] = bitcast i[[SZ]]* [[BP1_PTR:%.+]] to i32*
// CHECK-64: store i32 [[BP1_I32]], i32* [[BP1_CAST]],
// CHECK-32: store i32 [[BP1_I32]], i32* [[BP1_PTR:%.+]],
// CHECK: [[BP1:%.+]] = load i[[SZ]], i[[SZ]]* [[BP1_PTR]],
// CHECK: call void [[HVT2]](i[[SZ]] [[BP1]])
// CHECK: ret i32 0
#endif
| {
"language": "Assembly"
} |
.size 8000
.text@48
jp lstatint
.text@100
jp lbegin
.data@143
c0
.text@150
lbegin:
ld a, 00
ldff(ff), a
ld a, 30
ldff(00), a
ld a, 01
ldff(4d), a
stop, 00
ld b, 97
call lwaitly_b
ld a, 99
ldff(45), a
ld a, 40
ldff(41), a
ld a, 00
ld(8000), a
ld a, 01
ld(c000), a
ld a, c0
ldff(51), a
xor a, a
ldff(52), a
ldff(54), a
ld a, 80
ldff(53), a
xor a, a
ldff(0f), a
ld a, 02
ldff(ff), a
ei
ld hl, 8000
ld a, 05
ldff(43), a
halt
.text@1000
lstatint:
ld b, 03
ld a, 00
ldff(55), a
.text@1147
ldff a, (41)
and a, b
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
pop af
ld(9800), a
ld bc, 7a00
ld hl, 8000
ld d, a0
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
| {
"language": "Assembly"
} |
/*
Simple DirectMedia Layer
Copyright (C) 1997-2018 Sam Lantinga <slouken@libsdl.org>
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
*/
/**
* \file SDL_pixels.h
*
* Header for the enumerated pixel format definitions.
*/
#ifndef SDL_pixels_h_
#define SDL_pixels_h_
#include "SDL_stdinc.h"
#include "SDL_endian.h"
#include "begin_code.h"
/* Set up for C function definitions, even when using C++ */
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name Transparency definitions
*
* These define alpha as the opacity of a surface.
*/
/* @{ */
#define SDL_ALPHA_OPAQUE 255
#define SDL_ALPHA_TRANSPARENT 0
/* @} */
/** Pixel type. */
enum
{
SDL_PIXELTYPE_UNKNOWN,
SDL_PIXELTYPE_INDEX1,
SDL_PIXELTYPE_INDEX4,
SDL_PIXELTYPE_INDEX8,
SDL_PIXELTYPE_PACKED8,
SDL_PIXELTYPE_PACKED16,
SDL_PIXELTYPE_PACKED32,
SDL_PIXELTYPE_ARRAYU8,
SDL_PIXELTYPE_ARRAYU16,
SDL_PIXELTYPE_ARRAYU32,
SDL_PIXELTYPE_ARRAYF16,
SDL_PIXELTYPE_ARRAYF32
};
/** Bitmap pixel order, high bit -> low bit. */
enum
{
SDL_BITMAPORDER_NONE,
SDL_BITMAPORDER_4321,
SDL_BITMAPORDER_1234
};
/** Packed component order, high bit -> low bit. */
enum
{
SDL_PACKEDORDER_NONE,
SDL_PACKEDORDER_XRGB,
SDL_PACKEDORDER_RGBX,
SDL_PACKEDORDER_ARGB,
SDL_PACKEDORDER_RGBA,
SDL_PACKEDORDER_XBGR,
SDL_PACKEDORDER_BGRX,
SDL_PACKEDORDER_ABGR,
SDL_PACKEDORDER_BGRA
};
/** Array component order, low byte -> high byte. */
/* !!! FIXME: in 2.1, make these not overlap differently with
!!! FIXME: SDL_PACKEDORDER_*, so we can simplify SDL_ISPIXELFORMAT_ALPHA */
enum
{
SDL_ARRAYORDER_NONE,
SDL_ARRAYORDER_RGB,
SDL_ARRAYORDER_RGBA,
SDL_ARRAYORDER_ARGB,
SDL_ARRAYORDER_BGR,
SDL_ARRAYORDER_BGRA,
SDL_ARRAYORDER_ABGR
};
/** Packed component layout. */
enum
{
SDL_PACKEDLAYOUT_NONE,
SDL_PACKEDLAYOUT_332,
SDL_PACKEDLAYOUT_4444,
SDL_PACKEDLAYOUT_1555,
SDL_PACKEDLAYOUT_5551,
SDL_PACKEDLAYOUT_565,
SDL_PACKEDLAYOUT_8888,
SDL_PACKEDLAYOUT_2101010,
SDL_PACKEDLAYOUT_1010102
};
#define SDL_DEFINE_PIXELFOURCC(A, B, C, D) SDL_FOURCC(A, B, C, D)
#define SDL_DEFINE_PIXELFORMAT(type, order, layout, bits, bytes) \
((1 << 28) | ((type) << 24) | ((order) << 20) | ((layout) << 16) | \
((bits) << 8) | ((bytes) << 0))
#define SDL_PIXELFLAG(X) (((X) >> 28) & 0x0F)
#define SDL_PIXELTYPE(X) (((X) >> 24) & 0x0F)
#define SDL_PIXELORDER(X) (((X) >> 20) & 0x0F)
#define SDL_PIXELLAYOUT(X) (((X) >> 16) & 0x0F)
#define SDL_BITSPERPIXEL(X) (((X) >> 8) & 0xFF)
#define SDL_BYTESPERPIXEL(X) \
(SDL_ISPIXELFORMAT_FOURCC(X) ? \
((((X) == SDL_PIXELFORMAT_YUY2) || \
((X) == SDL_PIXELFORMAT_UYVY) || \
((X) == SDL_PIXELFORMAT_YVYU)) ? 2 : 1) : (((X) >> 0) & 0xFF))
#define SDL_ISPIXELFORMAT_INDEXED(format) \
(!SDL_ISPIXELFORMAT_FOURCC(format) && \
((SDL_PIXELTYPE(format) == SDL_PIXELTYPE_INDEX1) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_INDEX4) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_INDEX8)))
#define SDL_ISPIXELFORMAT_PACKED(format) \
(!SDL_ISPIXELFORMAT_FOURCC(format) && \
((SDL_PIXELTYPE(format) == SDL_PIXELTYPE_PACKED8) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_PACKED16) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_PACKED32)))
#define SDL_ISPIXELFORMAT_ARRAY(format) \
(!SDL_ISPIXELFORMAT_FOURCC(format) && \
((SDL_PIXELTYPE(format) == SDL_PIXELTYPE_ARRAYU8) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_ARRAYU16) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_ARRAYU32) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_ARRAYF16) || \
(SDL_PIXELTYPE(format) == SDL_PIXELTYPE_ARRAYF32)))
#define SDL_ISPIXELFORMAT_ALPHA(format) \
((SDL_ISPIXELFORMAT_PACKED(format) && \
((SDL_PIXELORDER(format) == SDL_PACKEDORDER_ARGB) || \
(SDL_PIXELORDER(format) == SDL_PACKEDORDER_RGBA) || \
(SDL_PIXELORDER(format) == SDL_PACKEDORDER_ABGR) || \
(SDL_PIXELORDER(format) == SDL_PACKEDORDER_BGRA))) || \
(SDL_ISPIXELFORMAT_ARRAY(format) && \
((SDL_PIXELORDER(format) == SDL_ARRAYORDER_ARGB) || \
(SDL_PIXELORDER(format) == SDL_ARRAYORDER_RGBA) || \
(SDL_PIXELORDER(format) == SDL_ARRAYORDER_ABGR) || \
(SDL_PIXELORDER(format) == SDL_ARRAYORDER_BGRA))))
/* The flag is set to 1 because 0x1? is not in the printable ASCII range */
#define SDL_ISPIXELFORMAT_FOURCC(format) \
((format) && (SDL_PIXELFLAG(format) != 1))
/* Note: If you modify this list, update SDL_GetPixelFormatName() */
enum
{
SDL_PIXELFORMAT_UNKNOWN,
SDL_PIXELFORMAT_INDEX1LSB =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_INDEX1, SDL_BITMAPORDER_4321, 0,
1, 0),
SDL_PIXELFORMAT_INDEX1MSB =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_INDEX1, SDL_BITMAPORDER_1234, 0,
1, 0),
SDL_PIXELFORMAT_INDEX4LSB =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_INDEX4, SDL_BITMAPORDER_4321, 0,
4, 0),
SDL_PIXELFORMAT_INDEX4MSB =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_INDEX4, SDL_BITMAPORDER_1234, 0,
4, 0),
SDL_PIXELFORMAT_INDEX8 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_INDEX8, 0, 0, 8, 1),
SDL_PIXELFORMAT_RGB332 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED8, SDL_PACKEDORDER_XRGB,
SDL_PACKEDLAYOUT_332, 8, 1),
SDL_PIXELFORMAT_RGB444 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_XRGB,
SDL_PACKEDLAYOUT_4444, 12, 2),
SDL_PIXELFORMAT_RGB555 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_XRGB,
SDL_PACKEDLAYOUT_1555, 15, 2),
SDL_PIXELFORMAT_BGR555 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_XBGR,
SDL_PACKEDLAYOUT_1555, 15, 2),
SDL_PIXELFORMAT_ARGB4444 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_ARGB,
SDL_PACKEDLAYOUT_4444, 16, 2),
SDL_PIXELFORMAT_RGBA4444 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_RGBA,
SDL_PACKEDLAYOUT_4444, 16, 2),
SDL_PIXELFORMAT_ABGR4444 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_ABGR,
SDL_PACKEDLAYOUT_4444, 16, 2),
SDL_PIXELFORMAT_BGRA4444 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_BGRA,
SDL_PACKEDLAYOUT_4444, 16, 2),
SDL_PIXELFORMAT_ARGB1555 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_ARGB,
SDL_PACKEDLAYOUT_1555, 16, 2),
SDL_PIXELFORMAT_RGBA5551 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_RGBA,
SDL_PACKEDLAYOUT_5551, 16, 2),
SDL_PIXELFORMAT_ABGR1555 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_ABGR,
SDL_PACKEDLAYOUT_1555, 16, 2),
SDL_PIXELFORMAT_BGRA5551 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_BGRA,
SDL_PACKEDLAYOUT_5551, 16, 2),
SDL_PIXELFORMAT_RGB565 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_XRGB,
SDL_PACKEDLAYOUT_565, 16, 2),
SDL_PIXELFORMAT_BGR565 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED16, SDL_PACKEDORDER_XBGR,
SDL_PACKEDLAYOUT_565, 16, 2),
SDL_PIXELFORMAT_RGB24 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_ARRAYU8, SDL_ARRAYORDER_RGB, 0,
24, 3),
SDL_PIXELFORMAT_BGR24 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_ARRAYU8, SDL_ARRAYORDER_BGR, 0,
24, 3),
SDL_PIXELFORMAT_RGB888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_XRGB,
SDL_PACKEDLAYOUT_8888, 24, 4),
SDL_PIXELFORMAT_RGBX8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_RGBX,
SDL_PACKEDLAYOUT_8888, 24, 4),
SDL_PIXELFORMAT_BGR888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_XBGR,
SDL_PACKEDLAYOUT_8888, 24, 4),
SDL_PIXELFORMAT_BGRX8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_BGRX,
SDL_PACKEDLAYOUT_8888, 24, 4),
SDL_PIXELFORMAT_ARGB8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_ARGB,
SDL_PACKEDLAYOUT_8888, 32, 4),
SDL_PIXELFORMAT_RGBA8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_RGBA,
SDL_PACKEDLAYOUT_8888, 32, 4),
SDL_PIXELFORMAT_ABGR8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_ABGR,
SDL_PACKEDLAYOUT_8888, 32, 4),
SDL_PIXELFORMAT_BGRA8888 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_BGRA,
SDL_PACKEDLAYOUT_8888, 32, 4),
SDL_PIXELFORMAT_ARGB2101010 =
SDL_DEFINE_PIXELFORMAT(SDL_PIXELTYPE_PACKED32, SDL_PACKEDORDER_ARGB,
SDL_PACKEDLAYOUT_2101010, 32, 4),
/* Aliases for RGBA byte arrays of color data, for the current platform */
#if SDL_BYTEORDER == SDL_BIG_ENDIAN
SDL_PIXELFORMAT_RGBA32 = SDL_PIXELFORMAT_RGBA8888,
SDL_PIXELFORMAT_ARGB32 = SDL_PIXELFORMAT_ARGB8888,
SDL_PIXELFORMAT_BGRA32 = SDL_PIXELFORMAT_BGRA8888,
SDL_PIXELFORMAT_ABGR32 = SDL_PIXELFORMAT_ABGR8888,
#else
SDL_PIXELFORMAT_RGBA32 = SDL_PIXELFORMAT_ABGR8888,
SDL_PIXELFORMAT_ARGB32 = SDL_PIXELFORMAT_BGRA8888,
SDL_PIXELFORMAT_BGRA32 = SDL_PIXELFORMAT_ARGB8888,
SDL_PIXELFORMAT_ABGR32 = SDL_PIXELFORMAT_RGBA8888,
#endif
SDL_PIXELFORMAT_YV12 = /**< Planar mode: Y + V + U (3 planes) */
SDL_DEFINE_PIXELFOURCC('Y', 'V', '1', '2'),
SDL_PIXELFORMAT_IYUV = /**< Planar mode: Y + U + V (3 planes) */
SDL_DEFINE_PIXELFOURCC('I', 'Y', 'U', 'V'),
SDL_PIXELFORMAT_YUY2 = /**< Packed mode: Y0+U0+Y1+V0 (1 plane) */
SDL_DEFINE_PIXELFOURCC('Y', 'U', 'Y', '2'),
SDL_PIXELFORMAT_UYVY = /**< Packed mode: U0+Y0+V0+Y1 (1 plane) */
SDL_DEFINE_PIXELFOURCC('U', 'Y', 'V', 'Y'),
SDL_PIXELFORMAT_YVYU = /**< Packed mode: Y0+V0+Y1+U0 (1 plane) */
SDL_DEFINE_PIXELFOURCC('Y', 'V', 'Y', 'U'),
SDL_PIXELFORMAT_NV12 = /**< Planar mode: Y + U/V interleaved (2 planes) */
SDL_DEFINE_PIXELFOURCC('N', 'V', '1', '2'),
SDL_PIXELFORMAT_NV21 = /**< Planar mode: Y + V/U interleaved (2 planes) */
SDL_DEFINE_PIXELFOURCC('N', 'V', '2', '1'),
SDL_PIXELFORMAT_EXTERNAL_OES = /**< Android video texture format */
SDL_DEFINE_PIXELFOURCC('O', 'E', 'S', ' ')
};
typedef struct SDL_Color
{
Uint8 r;
Uint8 g;
Uint8 b;
Uint8 a;
} SDL_Color;
#define SDL_Colour SDL_Color
typedef struct SDL_Palette
{
int ncolors;
SDL_Color *colors;
Uint32 version;
int refcount;
} SDL_Palette;
/**
* \note Everything in the pixel format structure is read-only.
*/
typedef struct SDL_PixelFormat
{
Uint32 format;
SDL_Palette *palette;
Uint8 BitsPerPixel;
Uint8 BytesPerPixel;
Uint8 padding[2];
Uint32 Rmask;
Uint32 Gmask;
Uint32 Bmask;
Uint32 Amask;
Uint8 Rloss;
Uint8 Gloss;
Uint8 Bloss;
Uint8 Aloss;
Uint8 Rshift;
Uint8 Gshift;
Uint8 Bshift;
Uint8 Ashift;
int refcount;
struct SDL_PixelFormat *next;
} SDL_PixelFormat;
/**
* \brief Get the human readable name of a pixel format
*/
extern DECLSPEC const char* SDLCALL SDL_GetPixelFormatName(Uint32 format);
/**
* \brief Convert one of the enumerated pixel formats to a bpp and RGBA masks.
*
* \return SDL_TRUE, or SDL_FALSE if the conversion wasn't possible.
*
* \sa SDL_MasksToPixelFormatEnum()
*/
extern DECLSPEC SDL_bool SDLCALL SDL_PixelFormatEnumToMasks(Uint32 format,
int *bpp,
Uint32 * Rmask,
Uint32 * Gmask,
Uint32 * Bmask,
Uint32 * Amask);
/**
* \brief Convert a bpp and RGBA masks to an enumerated pixel format.
*
* \return The pixel format, or ::SDL_PIXELFORMAT_UNKNOWN if the conversion
* wasn't possible.
*
* \sa SDL_PixelFormatEnumToMasks()
*/
extern DECLSPEC Uint32 SDLCALL SDL_MasksToPixelFormatEnum(int bpp,
Uint32 Rmask,
Uint32 Gmask,
Uint32 Bmask,
Uint32 Amask);
/**
* \brief Create an SDL_PixelFormat structure from a pixel format enum.
*/
extern DECLSPEC SDL_PixelFormat * SDLCALL SDL_AllocFormat(Uint32 pixel_format);
/**
* \brief Free an SDL_PixelFormat structure.
*/
extern DECLSPEC void SDLCALL SDL_FreeFormat(SDL_PixelFormat *format);
/**
* \brief Create a palette structure with the specified number of color
* entries.
*
* \return A new palette, or NULL if there wasn't enough memory.
*
* \note The palette entries are initialized to white.
*
* \sa SDL_FreePalette()
*/
extern DECLSPEC SDL_Palette *SDLCALL SDL_AllocPalette(int ncolors);
/**
* \brief Set the palette for a pixel format structure.
*/
extern DECLSPEC int SDLCALL SDL_SetPixelFormatPalette(SDL_PixelFormat * format,
SDL_Palette *palette);
/**
* \brief Set a range of colors in a palette.
*
* \param palette The palette to modify.
* \param colors An array of colors to copy into the palette.
* \param firstcolor The index of the first palette entry to modify.
* \param ncolors The number of entries to modify.
*
* \return 0 on success, or -1 if not all of the colors could be set.
*/
extern DECLSPEC int SDLCALL SDL_SetPaletteColors(SDL_Palette * palette,
const SDL_Color * colors,
int firstcolor, int ncolors);
/**
* \brief Free a palette created with SDL_AllocPalette().
*
* \sa SDL_AllocPalette()
*/
extern DECLSPEC void SDLCALL SDL_FreePalette(SDL_Palette * palette);
/**
* \brief Maps an RGB triple to an opaque pixel value for a given pixel format.
*
* \sa SDL_MapRGBA
*/
extern DECLSPEC Uint32 SDLCALL SDL_MapRGB(const SDL_PixelFormat * format,
Uint8 r, Uint8 g, Uint8 b);
/**
* \brief Maps an RGBA quadruple to a pixel value for a given pixel format.
*
* \sa SDL_MapRGB
*/
extern DECLSPEC Uint32 SDLCALL SDL_MapRGBA(const SDL_PixelFormat * format,
Uint8 r, Uint8 g, Uint8 b,
Uint8 a);
/**
* \brief Get the RGB components from a pixel of the specified format.
*
* \sa SDL_GetRGBA
*/
extern DECLSPEC void SDLCALL SDL_GetRGB(Uint32 pixel,
const SDL_PixelFormat * format,
Uint8 * r, Uint8 * g, Uint8 * b);
/**
* \brief Get the RGBA components from a pixel of the specified format.
*
* \sa SDL_GetRGB
*/
extern DECLSPEC void SDLCALL SDL_GetRGBA(Uint32 pixel,
const SDL_PixelFormat * format,
Uint8 * r, Uint8 * g, Uint8 * b,
Uint8 * a);
/**
* \brief Calculate a 256 entry gamma ramp for a gamma value.
*/
extern DECLSPEC void SDLCALL SDL_CalculateGammaRamp(float gamma, Uint16 * ramp);
/* Ends C function definitions when using C++ */
#ifdef __cplusplus
}
#endif
#include "close_code.h"
#endif /* SDL_pixels_h_ */
/* vi: set ts=4 sw=4 expandtab: */
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file startup_stm32f412zx.s
* @author MCD Application Team
* @brief STM32F412Zx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word 0 /* Reserved */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */
.word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word RNG_IRQHandler /* RNG */
.word FPU_IRQHandler /* FPU */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word QUADSPI_IRQHandler /* QuadSPI */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */
.word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak FMPI2C1_EV_IRQHandler
.thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
.weak FMPI2C1_ER_IRQHandler
.thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
--- dnsspoof.c.orig Fri Oct 15 13:51:17 2004
+++ dnsspoof.c Fri Oct 15 13:51:24 2004
@@ -5,10 +5,9 @@
#include <string.h>
#include <netinet/in.h>
#include <arpa/inet.h>
+#include <sys/socket.h>
#include <netinet/if_ether.h>
-#include <netinet/ether.h>
#include <net/ethernet.h>
-#include <sys/socket.h>
#include <libnet.h>
#include "dnsspoof.h"
| {
"language": "Assembly"
} |
# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass simple-register-coalescing -o - %s | FileCheck %s
# Check there is no partial redundent copy left in the loop after register coalescing.
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
@b = common local_unnamed_addr global i8* null, align 8
@a = common local_unnamed_addr global i32 0, align 4
define i32 @foo() local_unnamed_addr {
entry:
%t0 = load i8*, i8** @b, align 8
%t1 = load i8, i8* %t0, align 1
%cmp4 = icmp eq i8 %t1, 0
%t2 = load i32, i32* @a, align 4
br i1 %cmp4, label %while.end, label %while.body.preheader
while.body.preheader: ; preds = %entry
br label %while.body
while.body: ; preds = %while.body, %while.body.preheader
%t3 = phi i32 [ %add3, %while.body ], [ %t2, %while.body.preheader ]
%t4 = phi i8 [ %t5, %while.body ], [ %t1, %while.body.preheader ]
%conv = sext i8 %t4 to i32
%add = mul i32 %t3, 33
%add3 = add nsw i32 %add, %conv
store i32 %add3, i32* @a, align 4
%t5 = load i8, i8* %t0, align 1
%cmp = icmp eq i8 %t5, 0
br i1 %cmp, label %while.end, label %while.body
while.end: ; preds = %while.body, %entry
%.lcssa = phi i32 [ %t2, %entry ], [ %add3, %while.body ]
ret i32 %.lcssa
}
...
---
# Check A = B and B = A copies will not exist in the loop at the same time.
# CHECK: name: foo
# CHECK: [[L1:bb.3]].{{[a-zA-Z0-9.]+}}:
# CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
# CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
# CHECK: JNE_1 %[[L1]]
name: foo
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr8 }
- { id: 2, class: gr32 }
- { id: 3, class: gr32 }
- { id: 4, class: gr8 }
- { id: 5, class: gr32 }
- { id: 6, class: gr8 }
- { id: 7, class: gr32 }
- { id: 8, class: gr32 }
- { id: 9, class: gr32 }
- { id: 10, class: gr32 }
- { id: 11, class: gr32 }
- { id: 12, class: gr8 }
- { id: 13, class: gr32 }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
%0 = MOV64rm $rip, 1, $noreg, @b, $noreg :: (dereferenceable load 8 from @b)
%12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def $eflags
%11 = MOV32rm $rip, 1, $noreg, @a, $noreg :: (dereferenceable load 4 from @a)
JNE_1 %bb.1, implicit killed $eflags
bb.4:
%10 = COPY %11
JMP_1 %bb.3
bb.1.while.body.preheader:
bb.2.while.body:
%8 = MOVSX32rr8 %12
%10 = COPY %11
%10 = SHL32ri %10, 5, implicit-def dead $eflags
%10 = ADD32rr %10, %11, implicit-def dead $eflags
%10 = ADD32rr %10, %8, implicit-def dead $eflags
MOV32mr $rip, 1, $noreg, @a, $noreg, %10 :: (store 4 into @a)
%12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def $eflags
%11 = COPY %10
JNE_1 %bb.2, implicit killed $eflags
JMP_1 %bb.3
bb.3.while.end:
$eax = COPY %10
RET 0, killed $eax
...
| {
"language": "Assembly"
} |
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Configure the clock system and the external SRAM
;* mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMPER_IRQHandler
SECTION .text:CODE:REORDER(1)
TAMPER_IRQHandler
B TAMPER_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTCAlarm_IRQHandler
SECTION .text:CODE:REORDER(1)
RTCAlarm_IRQHandler
B RTCAlarm_IRQHandler
PUBWEAK CEC_IRQHandler
SECTION .text:CODE:REORDER(1)
CEC_IRQHandler
B CEC_IRQHandler
PUBWEAK TIM12_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM12_IRQHandler
B TIM12_IRQHandler
PUBWEAK TIM13_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM13_IRQHandler
B TIM13_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel4_5_IRQHandler
B DMA2_Channel4_5_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
END
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
// Copyright ©2016 The Gonum Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !noasm,!appengine,!safe
#include "textflag.h"
// MOVDDUP X2, X3
#define MOVDDUP_X2_X3 BYTE $0xF2; BYTE $0x0F; BYTE $0x12; BYTE $0xDA
// MOVDDUP X4, X5
#define MOVDDUP_X4_X5 BYTE $0xF2; BYTE $0x0F; BYTE $0x12; BYTE $0xEC
// MOVDDUP X6, X7
#define MOVDDUP_X6_X7 BYTE $0xF2; BYTE $0x0F; BYTE $0x12; BYTE $0xFE
// MOVDDUP X8, X9
#define MOVDDUP_X8_X9 BYTE $0xF2; BYTE $0x45; BYTE $0x0F; BYTE $0x12; BYTE $0xC8
// ADDSUBPD X2, X3
#define ADDSUBPD_X2_X3 BYTE $0x66; BYTE $0x0F; BYTE $0xD0; BYTE $0xDA
// ADDSUBPD X4, X5
#define ADDSUBPD_X4_X5 BYTE $0x66; BYTE $0x0F; BYTE $0xD0; BYTE $0xEC
// ADDSUBPD X6, X7
#define ADDSUBPD_X6_X7 BYTE $0x66; BYTE $0x0F; BYTE $0xD0; BYTE $0xFE
// ADDSUBPD X8, X9
#define ADDSUBPD_X8_X9 BYTE $0x66; BYTE $0x45; BYTE $0x0F; BYTE $0xD0; BYTE $0xC8
// func AxpyIncTo(dst []complex128, incDst, idst uintptr, alpha complex128, x, y []complex128, n, incX, incY, ix, iy uintptr)
TEXT ·AxpyIncTo(SB), NOSPLIT, $0
MOVQ dst_base+0(FP), DI // DI = &dst
MOVQ x_base+56(FP), SI // SI = &x
MOVQ y_base+80(FP), DX // DX = &y
MOVQ n+104(FP), CX // CX = n
CMPQ CX, $0 // if n==0 { return }
JE axpyi_end
MOVQ ix+128(FP), R8 // R8 = ix // Load the first index
SHLQ $4, R8 // R8 *= sizeof(complex128)
MOVQ iy+136(FP), R9 // R9 = iy
SHLQ $4, R9 // R9 *= sizeof(complex128)
MOVQ idst+32(FP), R10 // R10 = idst
SHLQ $4, R10 // R10 *= sizeof(complex128)
LEAQ (SI)(R8*1), SI // SI = &(x[ix])
LEAQ (DX)(R9*1), DX // DX = &(y[iy])
LEAQ (DI)(R10*1), DI // DI = &(dst[idst])
MOVQ incX+112(FP), R8 // R8 = incX
SHLQ $4, R8 // R8 *= sizeof(complex128)
MOVQ incY+120(FP), R9 // R9 = incY
SHLQ $4, R9 // R9 *= sizeof(complex128)
MOVQ incDst+24(FP), R10 // R10 = incDst
SHLQ $4, R10 // R10 *= sizeof(complex128)
MOVUPS alpha+40(FP), X0 // X0 = { imag(a), real(a) }
MOVAPS X0, X1
SHUFPD $0x1, X1, X1 // X1 = { real(a), imag(a) }
MOVAPS X0, X10 // Copy X0 and X1 for pipelining
MOVAPS X1, X11
MOVQ CX, BX
ANDQ $3, CX // CX = n % 4
SHRQ $2, BX // BX = floor( n / 4 )
JZ axpyi_tail // if BX == 0 { goto axpyi_tail }
axpyi_loop: // do {
MOVUPS (SI), X2 // X_i = { imag(x[i]), real(x[i]) }
MOVUPS (SI)(R8*1), X4
LEAQ (SI)(R8*2), SI // SI = &(SI[incX*2])
MOVUPS (SI), X6
MOVUPS (SI)(R8*1), X8
// X_(i+1) = { real(x[i], real(x[i]) }
MOVDDUP_X2_X3
MOVDDUP_X4_X5
MOVDDUP_X6_X7
MOVDDUP_X8_X9
// X_i = { imag(x[i]), imag(x[i]) }
SHUFPD $0x3, X2, X2
SHUFPD $0x3, X4, X4
SHUFPD $0x3, X6, X6
SHUFPD $0x3, X8, X8
// X_i = { real(a) * imag(x[i]), imag(a) * imag(x[i]) }
// X_(i+1) = { imag(a) * real(x[i]), real(a) * real(x[i]) }
MULPD X1, X2
MULPD X0, X3
MULPD X11, X4
MULPD X10, X5
MULPD X1, X6
MULPD X0, X7
MULPD X11, X8
MULPD X10, X9
// X_(i+1) = {
// imag(result[i]): imag(a)*real(x[i]) + real(a)*imag(x[i]),
// real(result[i]): real(a)*real(x[i]) - imag(a)*imag(x[i])
// }
ADDSUBPD_X2_X3
ADDSUBPD_X4_X5
ADDSUBPD_X6_X7
ADDSUBPD_X8_X9
// X_(i+1) = { imag(result[i]) + imag(y[i]), real(result[i]) + real(y[i]) }
ADDPD (DX), X3
ADDPD (DX)(R9*1), X5
LEAQ (DX)(R9*2), DX // DX = &(DX[incY*2])
ADDPD (DX), X7
ADDPD (DX)(R9*1), X9
MOVUPS X3, (DI) // dst[i] = X_(i+1)
MOVUPS X5, (DI)(R10*1)
LEAQ (DI)(R10*2), DI
MOVUPS X7, (DI)
MOVUPS X9, (DI)(R10*1)
LEAQ (SI)(R8*2), SI // SI = &(SI[incX*2])
LEAQ (DX)(R9*2), DX // DX = &(DX[incY*2])
LEAQ (DI)(R10*2), DI // DI = &(DI[incDst*2])
DECQ BX
JNZ axpyi_loop // } while --BX > 0
CMPQ CX, $0 // if CX == 0 { return }
JE axpyi_end
axpyi_tail: // do {
MOVUPS (SI), X2 // X_i = { imag(x[i]), real(x[i]) }
MOVDDUP_X2_X3 // X_(i+1) = { real(x[i], real(x[i]) }
SHUFPD $0x3, X2, X2 // X_i = { imag(x[i]), imag(x[i]) }
MULPD X1, X2 // X_i = { real(a) * imag(x[i]), imag(a) * imag(x[i]) }
MULPD X0, X3 // X_(i+1) = { imag(a) * real(x[i]), real(a) * real(x[i]) }
// X_(i+1) = {
// imag(result[i]): imag(a)*real(x[i]) + real(a)*imag(x[i]),
// real(result[i]): real(a)*real(x[i]) - imag(a)*imag(x[i])
// }
ADDSUBPD_X2_X3
// X_(i+1) = { imag(result[i]) + imag(y[i]), real(result[i]) + real(y[i]) }
ADDPD (DX), X3
MOVUPS X3, (DI) // y[i] X_(i+1)
ADDQ R8, SI // SI += incX
ADDQ R9, DX // DX += incY
ADDQ R10, DI // DI += incDst
LOOP axpyi_tail // } while --CX > 0
axpyi_end:
RET
| {
"language": "Assembly"
} |
; RUN: opt < %s -S -ipsccp | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @fn2() {
entry:
br label %if.end
for.cond1: ; preds = %if.end, %for.end
br i1 undef, label %if.end, label %if.end
if.end: ; preds = %lbl, %for.cond1
%e.2 = phi i32* [ undef, %entry ], [ null, %for.cond1 ], [ null, %for.cond1 ]
%0 = load i32, i32* %e.2, align 4
%call = call i32 @fn1(i32 %0)
br label %for.cond1
}
define internal i32 @fn1(i32 %p1) {
entry:
%tobool = icmp ne i32 %p1, 0
%cond = select i1 %tobool, i32 %p1, i32 %p1
ret i32 %cond
}
define void @fn_no_null_opt() #0 {
entry:
br label %if.end
for.cond1: ; preds = %if.end, %for.end
br i1 undef, label %if.end, label %if.end
if.end: ; preds = %lbl, %for.cond1
%e.2 = phi i32* [ undef, %entry ], [ null, %for.cond1 ], [ null, %for.cond1 ]
%0 = load i32, i32* %e.2, align 4
%call = call i32 @fn0(i32 %0)
br label %for.cond1
}
define internal i32 @fn0(i32 %p1) {
entry:
%tobool = icmp ne i32 %p1, 0
%cond = select i1 %tobool, i32 %p1, i32 %p1
ret i32 %cond
}
attributes #0 = { "null-pointer-is-valid"="true" }
; CHECK-LABEL: define void @fn2(
; CHECK: call i32 @fn1(i32 undef)
; CHECK-LABEL: define internal i32 @fn1(
; CHECK:%[[COND:.*]] = select i1 undef, i32 undef, i32 undef
; CHECK: ret i32 %[[COND]]
; CHECK-LABEL: define void @fn_no_null_opt(
; CHECK: call i32 @fn0(i32 %0)
; CHECK-LABEL: define internal i32 @fn0(
; CHECK:%[[TOBOOL:.*]] = icmp ne i32 %p1, 0
; CHECK:%[[COND:.*]] = select i1 %[[TOBOOL]], i32 %p1, i32 %p1
; CHECK: ret i32 %[[COND]]
| {
"language": "Assembly"
} |
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -instruction-tables < %s | FileCheck %s
vcvtph2ps %xmm0, %xmm2
vcvtph2ps (%rax), %xmm2
vcvtph2ps %xmm0, %ymm2
vcvtph2ps (%rax), %ymm2
vcvtps2ph $0, %xmm0, %xmm2
vcvtps2ph $0, %xmm0, (%rax)
vcvtps2ph $0, %ymm0, %xmm2
vcvtps2ph $0, %ymm0, (%rax)
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 5 1.00 vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: 2 9 0.50 * vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 2 10 0.50 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 2 5 1.00 vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: 4 6 1.00 * vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: 2 7 1.00 vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: 4 8 1.00 * vcvtps2ph $0, %ymm0, (%rax)
# CHECK: Resources:
# CHECK-NEXT: [0] - SKXDivider
# CHECK-NEXT: [1] - SKXFPDivider
# CHECK-NEXT: [2] - SKXPort0
# CHECK-NEXT: [3] - SKXPort1
# CHECK-NEXT: [4] - SKXPort2
# CHECK-NEXT: [5] - SKXPort3
# CHECK-NEXT: [6] - SKXPort4
# CHECK-NEXT: [7] - SKXPort5
# CHECK-NEXT: [8] - SKXPort6
# CHECK-NEXT: [9] - SKXPort7
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 4.00 4.00 1.67 1.67 2.00 6.00 - 0.67
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - 0.50 0.50 - - - 1.00 - - vcvtph2ps %xmm0, %xmm2
# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: - - 0.50 0.50 - - - 1.00 - - vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: - - 0.50 0.50 0.50 0.50 - - - - vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: - - 0.50 0.50 - - - 1.00 - - vcvtps2ph $0, %xmm0, %xmm2
# CHECK-NEXT: - - 0.50 0.50 0.33 0.33 1.00 1.00 - 0.33 vcvtps2ph $0, %xmm0, (%rax)
# CHECK-NEXT: - - 0.50 0.50 - - - 1.00 - - vcvtps2ph $0, %ymm0, %xmm2
# CHECK-NEXT: - - 0.50 0.50 0.33 0.33 1.00 1.00 - 0.33 vcvtps2ph $0, %ymm0, (%rax)
| {
"language": "Assembly"
} |
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8.753158E+00 4.565649E+01
8.753036E+00 4.565646E+01
8.752854E+00 4.565641E+01
8.752722E+00 4.565637E+01
8.752528E+00 4.565632E+01
8.752435E+00 4.565629E+01
8.752429E+00 4.565629E+01
8.752284E+00 4.565642E+01
8.752234E+00 4.565640E+01
8.752102E+00 4.565635E+01
8.751933E+00 4.565628E+01
8.751784E+00 4.565622E+01
8.751648E+00 4.565616E+01
8.751530E+00 4.565610E+01
8.751406E+00 4.565604E+01
8.751274E+00 4.565596E+01
8.751154E+00 4.565590E+01
8.751040E+00 4.565583E+01
8.750894E+00 4.565574E+01
8.750750E+00 4.565565E+01
8.750624E+00 4.565558E+01
8.750494E+00 4.565551E+01
8.750438E+00 4.565548E+01
8.750341E+00 4.565541E+01
8.750211E+00 4.565533E+01
8.750128E+00 4.565527E+01
8.750014E+00 4.565521E+01
8.749938E+00 4.565516E+01
8.749872E+00 4.565512E+01
8.749814E+00 4.565509E+01
8.749830E+00 4.565492E+01
8.749668E+00 4.565488E+01
8.749529E+00 4.565512E+01
8.749461E+00 4.565523E+01
8.749412E+00 4.565533E+01
8.749363E+00 4.565545E+01
8.749318E+00 4.565555E+01
8.749312E+00 4.565556E+01
8.749271E+00 4.565561E+01
8.749166E+00 4.565558E+01
8.748962E+00 4.565553E+01
8.748775E+00 4.565548E+01
8.748622E+00 4.565544E+01
8.748396E+00 4.565539E+01
8.748350E+00 4.565538E+01
8.748265E+00 4.565535E+01
8.748140E+00 4.565533E+01
8.747975E+00 4.565529E+01
8.747789E+00 4.565528E+01
8.747587E+00 4.565526E+01
8.747396E+00 4.565523E+01
8.747258E+00 4.565519E+01
8.747128E+00 4.565515E+01
8.746970E+00 4.565508E+01
8.746845E+00 4.565503E+01
8.746682E+00 4.565496E+01
8.746578E+00 4.565493E+01
8.746525E+00 4.565491E+01
8.746453E+00 4.565490E+01
8.746433E+00 4.565492E+01
8.746335E+00 4.565501E+01
8.746257E+00 4.565511E+01
8.746185E+00 4.565520E+01
8.746133E+00 4.565525E+01
8.745999E+00 4.565520E+01
8.745747E+00 4.565511E+01
8.745560E+00 4.565503E+01
8.745387E+00 4.565496E+01
8.745232E+00 4.565490E+01
8.745047E+00 4.565484E+01
8.744929E+00 4.565481E+01
8.744847E+00 4.565479E+01
8.744797E+00 4.565478E+01
8.744448E+00 4.565506E+01
8.743167E+00 4.565453E+01
8.742003E+00 4.565405E+01
8.741822E+00 4.565398E+01
8.741573E+00 4.565388E+01
8.741441E+00 4.565382E+01
8.741332E+00 4.565377E+01
8.741130E+00 4.565369E+01
8.740925E+00 4.565363E+01
8.739562E+00 4.565321E+01
8.740171E+00 4.565224E+01
8.740782E+00 4.565121E+01
8.741393E+00 4.565015E+01
8.739830E+00 4.564974E+01
8.737947E+00 4.564924E+01
8.736112E+00 4.564880E+01
8.734520E+00 4.564838E+01
8.733602E+00 4.564815E+01
8.733262E+00 4.564806E+01
8.731623E+00 4.564756E+01
8.729759E+00 4.564691E+01
8.729274E+00 4.564675E+01
8.728801E+00 4.564805E+01
8.728591E+00 4.564805E+01
8.727950E+00 4.565043E+01
8.727471E+00 4.565231E+01
8.727295E+00 4.565364E+01
8.726876E+00 4.565471E+01
8.726112E+00 4.565733E+01
8.725995E+00 4.565793E+01
8.727074E+00 4.565818E+01
8.727041E+00 4.565823E+01
8.726961E+00 4.565835E+01
8.726896E+00 4.565845E+01
8.726792E+00 4.565865E+01
8.726714E+00 4.565879E+01
8.726661E+00 4.565893E+01
8.726612E+00 4.565906E+01
8.726593E+00 4.565913E+01
8.726553E+00 4.565923E+01
8.726506E+00 4.565939E+01
8.726459E+00 4.565954E+01
8.726409E+00 4.565967E+01
8.726357E+00 4.565980E+01
8.726298E+00 4.565992E+01
8.726254E+00 4.566005E+01
8.726176E+00 4.566027E+01
8.726114E+00 4.566045E+01
8.726075E+00 4.566056E+01
8.726007E+00 4.566076E+01
8.725992E+00 4.566083E+01
8.725987E+00 4.566086E+01
8.725941E+00 4.566105E+01
8.725901E+00 4.566118E+01
8.725849E+00 4.566131E+01
8.725803E+00 4.566140E+01
8.725717E+00 4.566158E+01
8.725644E+00 4.566172E+01
8.725562E+00 4.566188E+01
8.725502E+00 4.566203E+01
8.725422E+00 4.566221E+01
8.725365E+00 4.566237E+01
8.725339E+00 4.566247E+01
8.725297E+00 4.566264E+01
8.725259E+00 4.566280E+01
8.725228E+00 4.566294E+01
8.725218E+00 4.566303E+01
8.725222E+00 4.566305E+01
8.725211E+00 4.566311E+01
8.725186E+00 4.566323E+01
8.725161E+00 4.566340E+01
8.725150E+00 4.566352E+01
8.725129E+00 4.566371E+01
8.725093E+00 4.566390E+01
8.725078E+00 4.566403E+01
8.725063E+00 4.566415E+01
8.725032E+00 4.566432E+01
8.724996E+00 4.566449E+01
8.724967E+00 4.566464E+01
8.724957E+00 4.566474E+01
8.724963E+00 4.566482E+01
8.724975E+00 4.566483E+01
8.725032E+00 4.566490E+01
8.725062E+00 4.566493E+01
8.725136E+00 4.566499E+01
8.725248E+00 4.566509E+01
8.725340E+00 4.566517E+01
8.725435E+00 4.566524E+01
8.725654E+00 4.566544E+01
8.726413E+00 4.566610E+01
8.726558E+00 4.566614E+01
8.726510E+00 4.566664E+01
8.726467E+00 4.566683E+01
8.726409E+00 4.566715E+01
8.726409E+00 4.566726E+01
8.726447E+00 4.566730E+01
8.726516E+00 4.566732E+01
8.726628E+00 4.566736E+01
8.726750E+00 4.566738E+01
8.726921E+00 4.566738E+01
8.727050E+00 4.566739E+01
8.727305E+00 4.566741E+01
8.727520E+00 4.566742E+01
8.727786E+00 4.566744E+01
8.727998E+00 4.566745E+01
8.728181E+00 4.566747E+01
8.728185E+00 4.566752E+01
8.728185E+00 4.566760E+01
8.728186E+00 4.566770E+01
8.728181E+00 4.566775E+01
8.728168E+00 4.566784E+01
8.728119E+00 4.566805E+01
8.728063E+00 4.566825E+01
8.728019E+00 4.566839E+01
8.727965E+00 4.566853E+01
8.727922E+00 4.566866E+01
8.727889E+00 4.566885E+01
8.727892E+00 4.566888E+01
8.727909E+00 4.566890E+01
8.727928E+00 4.566891E+01
8.727980E+00 4.566893E+01
8.728018E+00 4.566895E+01
8.728105E+00 4.566898E+01
8.728204E+00 4.566902E+01
8.728220E+00 4.566903E+01
8.728374E+00 4.566911E+01
8.728652E+00 4.566927E+01
8.728802E+00 4.566935E+01
8.728959E+00 4.566946E+01
8.729082E+00 4.566954E+01
8.729206E+00 4.566962E+01
8.729322E+00 4.566969E+01
8.729399E+00 4.566974E+01
8.729556E+00 4.566983E+01
8.729690E+00 4.566995E+01
8.729784E+00 4.567005E+01
8.729816E+00 4.567010E+01
8.729818E+00 4.567014E+01
8.729801E+00 4.567019E+01
8.729780E+00 4.567023E+01
8.729759E+00 4.567028E+01
8.729751E+00 4.567030E+01
8.729728E+00 4.567035E+01
8.729712E+00 4.567041E+01
8.729702E+00 4.567044E+01
8.729697E+00 4.567048E+01
8.729694E+00 4.567053E+01
8.729692E+00 4.567058E+01
8.729692E+00 4.567062E+01
8.729701E+00 4.567067E+01
8.729712E+00 4.567073E+01
8.729733E+00 4.567081E+01
8.729754E+00 4.567093E+01
8.729791E+00 4.567109E+01
8.729809E+00 4.567121E+01
8.729833E+00 4.567138E+01
8.729835E+00 4.567154E+01
8.729820E+00 4.567171E+01
8.729803E+00 4.567188E+01
8.729799E+00 4.567203E+01
8.729793E+00 4.567218E+01
8.729783E+00 4.567236E+01
8.729771E+00 4.567256E+01
8.729739E+00 4.567278E+01
8.729703E+00 4.567299E+01
8.729668E+00 4.567313E+01
8.729637E+00 4.567326E+01
8.729590E+00 4.567340E+01
8.729587E+00 4.567341E+01
8.729506E+00 4.567355E+01
8.729432E+00 4.567365E+01
8.729361E+00 4.567375E+01
8.729278E+00 4.567386E+01
8.729201E+00 4.567395E+01
8.729128E+00 4.567406E+01
8.729066E+00 4.567417E+01
8.729034E+00 4.567427E+01
8.729012E+00 4.567439E+01
8.729010E+00 4.567452E+01
8.729003E+00 4.567463E+01
8.728995E+00 4.567474E+01
8.728985E+00 4.567481E+01
8.728920E+00 4.567516E+01
8.729449E+00 4.567536E+01
8.729198E+00 4.567577E+01
END
END
| {
"language": "Assembly"
} |
RUN: llvm-opt-report -r %p %p/Inputs/unrl.yaml | FileCheck -strict-whitespace %s
; CHECK: < {{.*[/\]}}unrl.c
; CHECK-NEXT: 1 | void bar();
; CHECK-NEXT: 2 |
; CHECK-NEXT: 3 | void foo() {
; CHECK-NEXT: 4 U5 | for (int i = 0; i < 5; ++i)
; CHECK-NEXT: 5 | bar();
; CHECK-NEXT: 6 |
; CHECK-NEXT: 7 U11 | for (int i = 0; i < 11; ++i)
; CHECK-NEXT: 8 | bar();
; CHECK-NEXT: 9 | }
; CHECK-NEXT: 10 |
| {
"language": "Assembly"
} |
//===--- inheriting_ctor.cc - test input file for iwyu --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
#include "inheriting_ctor-d1.h"
// IWYU: Derived is defined in .*-i1.h
void func() { Derived d(1); }
/**** IWYU_SUMMARY
tests/cxx/inheriting_ctor.cc should add these lines:
#include "inheriting_ctor-i1.h"
tests/cxx/inheriting_ctor.cc should remove these lines:
- #include "inheriting_ctor-d1.h" // lines XX-XX
The full include-list for tests/cxx/inheriting_ctor.cc:
#include "inheriting_ctor-i1.h" // for Derived
***** IWYU_SUMMARY */
| {
"language": "Assembly"
} |
use std
use crypto
const main = {
hasheq(crypto.sha384("")[:], \
"38b060a751ac96384cd9327eb1b1e36a21fdb71114be07434c0cc7bf63f6e1da274edebfe76f65fbd51ad2f14898b95b")
hasheq(crypto.sha384("h")[:], \
"a4eb0778c79fce94c02126543cba398d645b2fd4c6ff6a02eecc026bbe0cc0dd666279722b7615bc15b4c9126b941c04")
/* 64 byte block */
hasheq(crypto.sha384("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa")[:], \
"2e404b9339da795776e510d96930b3be2904c500395b8cb7413334b82d4dec413b4b8113045a05bbbcff846f027423f6")
/* tail spanning */
hasheq(crypto.sha384("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaabbbbb")[:], \
"f8f4b55a0fb1ac8506d2e5195c714a1ad16c3bf61ad8b2d544344b105a49a77ff3b8eb61e8f970a71864e9dad87042b1")
hasheq(crypto.sha512("")[:], \
"cf83e1357eefb8bdf1542850d66d8007d620e4050b5715dc83f4a921d36ce9ce47d0d13c5d85f2b0ff8318d2877eec2f63b931bd47417a81a538327af927da3e")
hasheq(crypto.sha512("h")[:], \
"2241bc8fc70705b42efead371fd4982c5ba69917e5b4b895810002644f0386da9c3131793458c2bf47608480d64a07278133c99912e0ba2daf23098f3520eb97")
/* 64 byte block */
hasheq(crypto.sha512("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa")[:], \
"01d35c10c6c38c2dcf48f7eebb3235fb5ad74a65ec4cd016e2354c637a8fb49b695ef3c1d6f7ae4cd74d78cc9c9bcac9d4f23a73019998a7f73038a5c9b2dbde")
/* tail spanning */
hasheq(crypto.sha512("aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaabbbbb")[:], \
"d5c989d2e41299b6bfd57562b4b09cd2efa56f13c8fa109e0ce5ddbd6bfb5b34f8563608d6162104bef750023732581f22704d5df43feecbb05742be1d7c34fa")
}
const hasheq = {got, expected
var sb, str
sb = std.mksb()
for x : got
std.sbfmt(sb, "{p=0,w=2,x}", x)
;;
str = std.sbfin(sb)
if (!std.eq(str, expected))
std.fatal("mismatched hashes:\n\tgot:\t{}\n\texpected:\t{}\n", str, expected)
;;
std.slfree(str)
}
| {
"language": "Assembly"
} |
STARTUP(crt0.o)
OUTPUT_ARCH(m68k)
/* Uncomment this if you want srecords. This is needed for a.out
* if you plan to use GDB.
OUTPUT_FORMAT(srec)
*/
SEARCH_DIR(.)
GROUP(-lmvme162 -lc -lgcc)
__DYNAMIC = 0;
/*
* Setup the memory map of the Motorola MVME135 Board
* stack grows down from high memory.
*
* The memory map look like this:
* +--------------------+ <- low memory
* | .text |
* | _etext |
* | ctor list | the ctor and dtor lists are for
* | dtor list | C++ support
* +--------------------+
* | .data | initialized data goes here
* | _edata |
* +--------------------+
* | .bss |
* | __bss_start | start of bss, cleared by crt0
* | _end | start of heap, used by sbrk()
* +--------------------+
* . .
* . .
* . .
* | __stack | top of stack
* +--------------------+
*/
MEMORY
{
monitor : ORIGIN = 0x0000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x10000, LENGTH = 16M
}
/*
* allocate the stack to be at the top of memory, since the stack
* grows down
*/
PROVIDE (__stack = 16M - 8);
/*
* Initalize some symbols to be zero so we can reference them in the
* crt0 without core dumping. These functions are all optional, but
* we do this so we can have our crt0 always use them if they exist.
* This is so BSPs work better when using the crt0 installed with gcc.
* We have to initalize them twice, so we cover a.out (which prepends
* an underscore) and coff object file formats.
*/
PROVIDE (hardware_init_hook = 0);
PROVIDE (_hardware_init_hook = 0);
PROVIDE (software_init_hook = 0);
PROVIDE (_software_init_hook = 0);
/*
* stick everything in ram (of course)
*/
SECTIONS
{
.text :
{
*(.text .text.*)
. = ALIGN(0x4);
__CTOR_LIST__ = .;
___CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
___DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
*(.rodata .rodata.*)
*(.gcc_except_table)
. = ALIGN(0x2);
__INIT_SECTION__ = . ;
LONG (0x4e560000) /* linkw %fp,#0 */
*(.init)
SHORT (0x4e5e) /* unlk %fp */
SHORT (0x4e75) /* rts */
__FINI_SECTION__ = . ;
LONG (0x4e560000) /* linkw %fp,#0 */
*(.fini)
SHORT (0x4e5e) /* unlk %fp */
SHORT (0x4e75) /* rts */
_etext = .;
*(.lit)
} > ram
.data :
{
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.*)
_edata = .;
} > ram
.bss :
{
. = ALIGN(0x4);
__bss_start = . ;
*(.shbss)
*(.bss .bss.*)
*(COMMON)
_end = ALIGN (0x8);
__end = _end;
} > ram
.stab 0 (NOLOAD) :
{
*(.stab)
}
.stabstr 0 (NOLOAD) :
{
*(.stabstr)
}
}
| {
"language": "Assembly"
} |
; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
; test vector shifts converted to proper SSE2 vector shifts when the shift
; amounts are the same.
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
; CHECK-LABEL: shift1a:
; CHECK: psrlq
%lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %lshr, <2 x i64>* %dst
ret void
}
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
; CHECK-LABEL: shift1b:
; CHECK: movd
; CHECK: psrlq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
%lshr = lshr <2 x i64> %val, %1
store <2 x i64> %lshr, <2 x i64>* %dst
ret void
}
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
; CHECK-LABEL: shift2a:
; CHECK: psrld
%lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
store <4 x i32> %lshr, <4 x i32>* %dst
ret void
}
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
; CHECK-LABEL: shift2b:
; CHECK: movd
; CHECK: psrld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
%3 = insertelement <4 x i32> %2, i32 %amt, i32 3
%lshr = lshr <4 x i32> %val, %3
store <4 x i32> %lshr, <4 x i32>* %dst
ret void
}
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
; CHECK-LABEL: shift3a:
; CHECK: psrlw
%lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %lshr, <8 x i16>* %dst
ret void
}
; properly zero extend the shift amount
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: movd
; CHECK: psrlw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %1, i16 %amt, i32 2
%3 = insertelement <8 x i16> %2, i16 %amt, i32 3
%4 = insertelement <8 x i16> %3, i16 %amt, i32 4
%5 = insertelement <8 x i16> %4, i16 %amt, i32 5
%6 = insertelement <8 x i16> %5, i16 %amt, i32 6
%7 = insertelement <8 x i16> %6, i16 %amt, i32 7
%lshr = lshr <8 x i16> %val, %7
store <8 x i16> %lshr, <8 x i16>* %dst
ret void
}
| {
"language": "Assembly"
} |
/*/*********************************************************\
* File: MySceneContext.h *
*
* Copyright (C) 2002-2013 The PixelLight Team (http://www.pixellight.org/)
*
* This file is part of PixelLight.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\*********************************************************/
#ifndef __PLSAMPLE_82_QTINPUTHANDLING_MYSCENECONTEXT_H__
#define __PLSAMPLE_82_QTINPUTHANDLING_MYSCENECONTEXT_H__
#pragma once
//[-------------------------------------------------------]
//[ Includes ]
//[-------------------------------------------------------]
#include <PLFrontendQt/QPLSceneContext.h>
//[-------------------------------------------------------]
//[ Classes ]
//[-------------------------------------------------------]
/**
* @brief
* Scene context
*/
class MySceneContext : public PLFrontendQt::QPLSceneContext {
//[-------------------------------------------------------]
//[ Public functions ]
//[-------------------------------------------------------]
public:
/**
* @brief
* Constructor
*/
MySceneContext();
/**
* @brief
* Destructor
*/
virtual ~MySceneContext();
//[-------------------------------------------------------]
//[ Protected virtual PLFrontendQt::QPLSceneContext functions ]
//[-------------------------------------------------------]
protected:
virtual void OnCreateScene(PLScene::SceneContainer &cContainer) override;
};
#endif // __PLSAMPLE_82_QTINPUTHANDLING_MYSCENECONTEXT_H__
| {
"language": "Assembly"
} |
// go run mkasm_darwin.go amd64
// Code generated by the command above; DO NOT EDIT.
// +build go1.13
#include "textflag.h"
TEXT ·libc_fdopendir_trampoline(SB),NOSPLIT,$0-0
JMP libc_fdopendir(SB)
TEXT ·libc_closedir_trampoline(SB),NOSPLIT,$0-0
JMP libc_closedir(SB)
TEXT ·libc_readdir_r_trampoline(SB),NOSPLIT,$0-0
JMP libc_readdir_r(SB)
| {
"language": "Assembly"
} |
; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN64
@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00"
@sel = external global i8*
@sel3 = external global i8*
@sel4 = external global i8*
@sel5 = external global i8*
@sel6 = external global i8*
@sel7 = external global i8*
; X64: @foo
; X64: jmp
; WIN64: @foo
; WIN64: callq
define void @foo(i64 %arg) nounwind optsize ssp noredzone {
entry:
%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
ret void
}
declare i32 @printf(i8*, ...) optsize noredzone
; X64: @bar
; X64: jmp
; WIN64: @bar
; WIN64: jmp
define void @bar(i64 %arg) nounwind optsize ssp noredzone {
entry:
tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone
ret void
}
declare void @bar2(i8*, i64) optsize noredzone
; X64: @foo2
; X64: jmp
; WIN64: @foo2
; WIN64: callq
define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone {
entry:
%tmp1 = load i8** @sel, align 8
%call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone
ret i8* %call
}
declare i8* @x2(i8*, i8*, ...) optsize noredzone
; X64: @foo6
; X64: jmp
; WIN64: @foo6
; WIN64: callq
define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
entry:
%tmp2 = load i8** @sel3, align 8
%tmp3 = load i8** @sel4, align 8
%tmp4 = load i8** @sel5, align 8
%tmp5 = load i8** @sel6, align 8
%call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone
ret i8* %call
}
declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone
; X64: @foo7
; X64: callq
; WIN64: @foo7
; WIN64: callq
define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
entry:
%tmp2 = load i8** @sel3, align 8
%tmp3 = load i8** @sel4, align 8
%tmp4 = load i8** @sel5, align 8
%tmp5 = load i8** @sel6, align 8
%tmp6 = load i8** @sel7, align 8
%call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone
ret i8* %call
}
declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone
; X64: @foo8
; X64: callq
; WIN64: @foo8
; WIN64: callq
define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone {
entry:
%tmp2 = load i8** @sel3, align 8
%tmp3 = load i8** @sel4, align 8
%tmp4 = load i8** @sel5, align 8
%tmp5 = load i8** @sel6, align 8
%call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone
ret i8* %call
}
| {
"language": "Assembly"
} |
/* mpn_add_n -- add (or subtract) bignums.
Copyright (C) 2013-2018 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<http://www.gnu.org/licenses/>. */
#include <sysdep.h>
#include <arm-features.h>
.syntax unified
.text
#ifdef USE_AS_SUB_N
# define INITC cmp r0, r0
# define OPC sbcs
# define RETC sbc r0, r0, r0; neg r0, r0
# define FUNC __mpn_sub_n
#else
# define INITC cmn r0, #0
# define OPC adcs
# define RETC mov r0, #0; adc r0, r0, r0
# define FUNC __mpn_add_n
#endif
/* mp_limb_t mpn_add_n(res_ptr, src1_ptr, src2_ptr, size) */
ENTRY (FUNC)
push { r4, r5, r6, r7, r8, r10, lr }
cfi_adjust_cfa_offset (28)
cfi_rel_offset (r4, 0)
cfi_rel_offset (r5, 4)
cfi_rel_offset (r6, 8)
cfi_rel_offset (r7, 12)
cfi_rel_offset (r8, 16)
cfi_rel_offset (r10, 20)
cfi_rel_offset (lr, 24)
INITC /* initialize carry flag */
tst r3, #1 /* count & 1 == 1? */
add lr, r1, r3, lsl #2 /* compute end src1 */
beq 1f
ldr r4, [r1], #4 /* do one to make count even */
ldr r5, [r2], #4
OPC r4, r4, r5
teq r1, lr /* end of count? (preserve carry) */
str r4, [r0], #4
beq 9f
1:
tst r3, #2 /* count & 2 == 2? */
beq 2f
ldm r1!, { r4, r5 } /* do two to make count 0 mod 4 */
ldm r2!, { r6, r7 }
OPC r4, r4, r6
OPC r5, r5, r7
teq r1, lr /* end of count? */
stm r0!, { r4, r5 }
beq 9f
2:
ldm r1!, { r3, r5, r7, r10 } /* do four each loop */
ldm r2!, { r4, r6, r8, ip }
OPC r3, r3, r4
OPC r5, r5, r6
OPC r7, r7, r8
OPC r10, r10, ip
teq r1, lr
stm r0!, { r3, r5, r7, r10 }
bne 2b
9:
RETC /* copy carry out */
#ifndef ARM_ALWAYS_BX
pop { r4, r5, r6, r7, r8, r10, pc }
#else
pop { r4, r5, r6, r7, r8, r10, lr }
bx lr
#endif
END (FUNC)
| {
"language": "Assembly"
} |
/*
* linux/arch/arm/mm/proc-v7.S
*
* Copyright (C) 2001 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This is the "shell" of the ARMv7 processor support.
*/
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include "proc-macros.S"
#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
#include "proc-v7-2level.S"
#endif
ENTRY(cpu_v7_proc_init)
mov pc, lr
ENDPROC(cpu_v7_proc_init)
ENTRY(cpu_v7_proc_fin)
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x0006 @ .............ca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
mov pc, lr
ENDPROC(cpu_v7_proc_fin)
/*
* cpu_v7_reset(loc)
*
* Perform a soft reset of the system. Put the CPU into the
* same state as it would be if it had been reset, and branch
* to what would be the reset vector.
*
* - loc - location to jump to for soft reset
*
* This code must be executed using a flat identity mapping with
* caches disabled.
*/
.align 5
.pushsection .idmap.text, "ax"
ENTRY(cpu_v7_reset)
mrc p15, 0, r1, c1, c0, 0 @ ctrl register
bic r1, r1, #0x1 @ ...............m
THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
mcr p15, 0, r1, c1, c0, 0 @ disable MMU
isb
bx r0
ENDPROC(cpu_v7_reset)
.popsection
/*
* cpu_v7_do_idle()
*
* Idle the processor (eg, wait for interrupt).
*
* IRQs are already disabled.
*/
ENTRY(cpu_v7_do_idle)
dsb @ WFI may enter a low-power mode
wfi
mov pc, lr
ENDPROC(cpu_v7_do_idle)
ENTRY(cpu_v7_dcache_clean_area)
ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
ALT_UP_B(1f)
mov pc, lr
1: dcache_line_size r2, r3
2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
add r0, r0, r2
subs r1, r1, r2
bhi 2b
dsb
mov pc, lr
ENDPROC(cpu_v7_dcache_clean_area)
string cpu_v7_name, "ARMv7 Processor"
.align
/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl cpu_v7_suspend_size
.equ cpu_v7_suspend_size, 4 * 8
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
stmfd sp!, {r4 - r10, lr}
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
stmia r0!, {r4 - r5}
#ifdef CONFIG_MMU
mrc p15, 0, r6, c3, c0, 0 @ Domain ID
mrc p15, 0, r7, c2, c0, 1 @ TTB 1
mrc p15, 0, r11, c2, c0, 2 @ TTB control register
#endif
mrc p15, 0, r8, c1, c0, 0 @ Control register
mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
stmia r0, {r6 - r11}
ldmfd sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)
ENTRY(cpu_v7_do_resume)
mov ip, #0
mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
ldmia r0!, {r4 - r5}
mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
ldmia r0, {r6 - r11}
#ifdef CONFIG_MMU
mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
mcr p15, 0, r6, c3, c0, 0 @ Domain ID
#ifndef CONFIG_ARM_LPAE
ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
#endif
mcr p15, 0, r1, c2, c0, 0 @ TTB 0
mcr p15, 0, r7, c2, c0, 1 @ TTB 1
mcr p15, 0, r11, c2, c0, 2 @ TTB control register
ldr r4, =PRRR @ PRRR
ldr r5, =NMRR @ NMRR
mcr p15, 0, r4, c10, c2, 0 @ write PRRR
mcr p15, 0, r5, c10, c2, 1 @ write NMRR
#endif /* CONFIG_MMU */
mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
teq r4, r9 @ Is it already set?
mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
isb
dsb
mov r0, r8 @ control register
b cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif
#ifdef CONFIG_CPU_PJ4B
globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
globl_equ cpu_pj4b_reset, cpu_v7_reset
#ifdef CONFIG_PJ4B_ERRATA_4742
ENTRY(cpu_pj4b_do_idle)
dsb @ WFI may enter a low-power mode
wfi
dsb @barrier
mov pc, lr
ENDPROC(cpu_pj4b_do_idle)
#else
globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
#endif
globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
#endif
/*
* __v7_setup
*
* Initialise TLB, Caches, and MMU state ready to switch the MMU
* on. Return in r0 the new CP15 C1 control register setting.
*
* This should be able to cover all ARMv7 cores.
*
* It is assumed that:
* - cache type register is implemented
*/
__v7_ca5mp_setup:
__v7_ca9mp_setup:
__v7_cr7mp_setup:
mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
b 1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
mov r10, #0
1:
#ifdef CONFIG_SMP
ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
orreq r0, r0, r10 @ Enable CPU-specific SMP bits
mcreq p15, 0, r0, c1, c0, 1
#endif
b __v7_setup
__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B
/* Auxiliary Debug Modes Control 1 Register */
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
/* Auxiliary Debug Modes Control 2 Register */
#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
/* Auxiliary Functional Modes Control Register 0 */
#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
/* Auxiliary Debug Modes Control 0 Register */
#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
/* Auxiliary Debug Modes Control 1 Register */
mrc p15, 1, r0, c15, c1, 1
orr r0, r0, #PJ4B_CLEAN_LINE
orr r0, r0, #PJ4B_BCK_OFF_STREX
orr r0, r0, #PJ4B_INTER_PARITY
bic r0, r0, #PJ4B_STATIC_BP
mcr p15, 1, r0, c15, c1, 1
/* Auxiliary Debug Modes Control 2 Register */
mrc p15, 1, r0, c15, c1, 2
bic r0, r0, #PJ4B_FAST_LDR
orr r0, r0, #PJ4B_AUX_DBG_CTRL2
mcr p15, 1, r0, c15, c1, 2
/* Auxiliary Functional Modes Control Register 0 */
mrc p15, 1, r0, c15, c2, 0
#ifdef CONFIG_SMP
orr r0, r0, #PJ4B_SMP_CFB
#endif
orr r0, r0, #PJ4B_L1_PAR_CHK
orr r0, r0, #PJ4B_BROADCAST_CACHE
mcr p15, 1, r0, c15, c2, 0
/* Auxiliary Debug Modes Control 0 Register */
mrc p15, 1, r0, c15, c1, 0
orr r0, r0, #PJ4B_WFI_WFE
mcr p15, 1, r0, c15, c1, 0
#endif /* CONFIG_CPU_PJ4B */
__v7_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
bl v7_flush_dcache_louis
ldmia r12, {r0-r5, r7, r9, r11, lr}
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
and r10, r0, #0xff000000 @ ARM?
teq r10, #0x41000000
bne 3f
and r5, r0, #0x00f00000 @ variant
and r6, r0, #0x0000000f @ revision
orr r6, r6, r5, lsr #20-4 @ combine variant and revision
ubfx r0, r0, #4, #12 @ primary part number
/* Cortex-A8 Errata */
ldr r10, =0x00000c08 @ Cortex-A8 primary part number
teq r0, r10
bne 2f
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
teq r5, #0x00100000 @ only present in r1p*
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
orreq r10, r10, #(1 << 6) @ set IBE to 1
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
teq r6, #0x20 @ only present in r2p0
mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
orreq r10, r10, #(1 << 5) @ set L1NEON to 1
orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
teq r6, #0x20 @ only present in r2p0
mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
tsteq r10, #1 << 22
orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
#endif
b 3f
/* Cortex-A9 Errata */
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r10
bne 3f
#ifdef CONFIG_ARM_ERRATA_742230
cmp r6, #0x22 @ only present up to r2p2
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
orrle r10, r10, #1 << 4 @ set bit #4
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
teq r6, #0x20 @ present in r2p0
teqne r6, #0x21 @ present in r2p1
teqne r6, #0x22 @ present in r2p2
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
orreq r10, r10, #1 << 12 @ set bit #12
orreq r10, r10, #1 << 22 @ set bit #22
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
teq r5, #0x00200000 @ only present in r2p*
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
orreq r10, r10, #1 << 6 @ set bit #6
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
ALT_UP_B(1f)
mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
orrlt r10, r10, #1 << 11 @ set bit #11
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
1:
#endif
3: mov r10, #0
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
dsb
#ifdef CONFIG_MMU
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
ldr r5, =PRRR @ PRRR
ldr r6, =NMRR @ NMRR
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
#endif
#ifndef CONFIG_ARM_THUMBEE
mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
and r0, r0, #(0xf << 12) @ ThumbEE enabled field
teq r0, #(1 << 12) @ check if ThumbEE is present
bne 1f
mov r5, #0
mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
mrc p14, 6, r0, c0, c0, 0 @ load TEECR
orr r0, r0, #1 @ set the 1st bit in order to
mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
1:
#endif
adr r5, v7_crval
ldmia r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
orr r6, r6, #1 << 25 @ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
orr r5, r5, #(1 << 10) @ set SW bit in "clear"
bic r6, r6, #(1 << 10) @ clear it in "mmuset"
#endif
mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, r0, r5 @ clear bits them
orr r0, r0, r6 @ set them
THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
mov pc, lr @ return to head.S:__ret
ENDPROC(__v7_setup)
.align 2
__v7_setup_stack:
.space 4 * 11 @ 11 registers
__INITDATA
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#ifdef CONFIG_CPU_PJ4B
define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#endif
.section ".rodata"
string cpu_arch_name, "armv7"
string cpu_elf_name, "v7"
.align
.section ".proc.info.init", #alloc, #execinstr
/*
* Standard v7 proc info content
*/
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
W(b) \initfunc
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
HWCAP_EDSP | HWCAP_TLS | \hwcaps
.long cpu_v7_name
.long \proc_fns
.long v7wbi_tlb_fns
.long v6_user_fns
.long v7_cache_fns
.endm
#ifndef CONFIG_ARM_LPAE
/*
* ARM Ltd. Cortex A5 processor.
*/
.type __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
.long 0x410fc050
.long 0xff0ffff0
__v7_proc __v7_ca5mp_setup
.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
/*
* ARM Ltd. Cortex A9 processor.
*/
.type __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
.long 0x410fc090
.long 0xff0ffff0
__v7_proc __v7_ca9mp_setup
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
#endif /* CONFIG_ARM_LPAE */
/*
* Marvell PJ4B processor.
*/
#ifdef CONFIG_CPU_PJ4B
.type __v7_pj4b_proc_info, #object
__v7_pj4b_proc_info:
.long 0x560f5800
.long 0xff0fff00
__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
#endif
/*
* ARM Ltd. Cortex R7 processor.
*/
.type __v7_cr7mp_proc_info, #object
__v7_cr7mp_proc_info:
.long 0x410fc170
.long 0xff0ffff0
__v7_proc __v7_cr7mp_setup
.size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
/*
* ARM Ltd. Cortex A7 processor.
*/
.type __v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
.long 0x410fc070
.long 0xff0ffff0
__v7_proc __v7_ca7mp_setup
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
/*
* ARM Ltd. Cortex A15 processor.
*/
.type __v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
.long 0x410fc0f0
.long 0xff0ffff0
__v7_proc __v7_ca15mp_setup
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
/*
* Qualcomm Inc. Krait processors.
*/
.type __krait_proc_info, #object
__krait_proc_info:
.long 0x510f0400 @ Required ID value
.long 0xff0ffc00 @ Mask for ID
/*
* Some Krait processors don't indicate support for SDIV and UDIV
* instructions in the ARM instruction set, even though they actually
* do support them.
*/
__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
.size __krait_proc_info, . - __krait_proc_info
/*
* Match any ARMv7 processor core.
*/
.type __v7_proc_info, #object
__v7_proc_info:
.long 0x000f0000 @ Required ID value
.long 0x000f0000 @ Mask for ID
__v7_proc __v7_setup
.size __v7_proc_info, . - __v7_proc_info
| {
"language": "Assembly"
} |
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build arm64
// +build !gccgo
#include "textflag.h"
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
B syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
BL runtime·entersyscall(SB)
MOVD a1+8(FP), R0
MOVD a2+16(FP), R1
MOVD a3+24(FP), R2
MOVD $0, R3
MOVD $0, R4
MOVD $0, R5
MOVD trap+0(FP), R8 // syscall entry
SVC
MOVD R0, r1+32(FP) // r1
MOVD R1, r2+40(FP) // r2
BL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
B syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOVD a1+8(FP), R0
MOVD a2+16(FP), R1
MOVD a3+24(FP), R2
MOVD $0, R3
MOVD $0, R4
MOVD $0, R5
MOVD trap+0(FP), R8 // syscall entry
SVC
MOVD R0, r1+32(FP)
MOVD R1, r2+40(FP)
RET
| {
"language": "Assembly"
} |
# Create a GOT reference for every function under test.
.abicalls
.option pic2
.include "compressed-plt-1.s"
.macro test_one, name, types
lw $2,%got(\name)($gp)
.endm
.if micromips
.set micromips
.endif
.section .text.d, "ax", @progbits
.globl testgot
.ent testgot
.set noreorder
testgot:
test_all
.end testgot
| {
"language": "Assembly"
} |
StartChar: Zcaron
Encoding: 381 381 217
GlifName: Z_caron
Width: 1024
VWidth: 0
Flags: W
HStem: 0 120<293 1024> 1288 120<148 839>
LayerCount: 5
Back
Fore
SplineSet
148 1288 m 1
148 1408 l 1
1004 1408 l 1
1004 1318 l 1
293 130 l 1
293 120 l 1
1024 120 l 1
1024 0 l 1
128 0 l 1
128 92 l 1
839 1278 l 1
839 1288 l 1
148 1288 l 1
497 1539 m 1
200 1795 l 1
358 1795 l 1
576 1631 l 1
794 1795 l 1
952 1795 l 1
655 1539 l 1
497 1539 l 1
EndSplineSet
Validated: 1
Layer: 2
Layer: 3
Layer: 4
Substitution2: "'ss14' Style Set 14 lookup 14 subtable" Zcaron.sq
EndChar
| {
"language": "Assembly"
} |
/* -*- Mode: java; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
*
* ***** BEGIN LICENSE BLOCK *****
* Version: MPL 1.1/GPL 2.0/LGPL 2.1
*
* The contents of this file are subject to the Mozilla Public License Version
* 1.1 (the "License"); you may not use this file except in compliance with
* the License. You may obtain a copy of the License at
* http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS" basis,
* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
* for the specific language governing rights and limitations under the
* License.
*
* The Original Code is Rhino code, released
* May 6, 1999.
*
* The Initial Developer of the Original Code is
* Netscape Communications Corporation.
* Portions created by the Initial Developer are Copyright (C) 1997-2000
* the Initial Developer. All Rights Reserved.
*
* Contributor(s):
* Igor Bukanov
* Ethan Hugg
* Milen Nankov
*
* Alternatively, the contents of this file may be used under the terms of
* either the GNU General Public License Version 2 or later (the "GPL"), or
* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
* in which case the provisions of the GPL or the LGPL are applicable instead
* of those above. If you wish to allow use of your version of this file only
* under the terms of either the GPL or the LGPL, and not to allow others to
* use your version of this file under the terms of the MPL, indicate your
* decision by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL or the LGPL. If you do not delete
* the provisions above, a recipient may use your version of this file under
* the terms of any one of the MPL, the GPL or the LGPL.
*
* ***** END LICENSE BLOCK ***** */
START("10.5.1 - ToAttributeName applied to the String type");
var actual = 'Test not implemented';
var expect = 'PASS';
TEST(1, expect, actual);
END();
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file startup_stm32f407xx.s
* @author MCD Application Team
* @brief STM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FSMC_IRQHandler /* FSMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* CRYP crypto */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak HASH_RNG_IRQHandler
.thumb_set HASH_RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
| {
"language": "Assembly"
} |
.text
.globl bar
.type bar, @function
bar:
leaq __FUNCTION__.2215(%rip), %rdi
jmp *puts@GOTPCREL(%rip)
.size bar, .-bar
.globl plt
.type plt, @function
plt:
leaq __FUNCTION__.2219(%rip), %rdi
subq $8, %rsp
call *puts@GOTPCREL(%rip)
leaq __FUNCTION__.2219(%rip), %rdi
addq $8, %rsp
jmp *puts@GOTPCREL(%rip)
.size plt, .-plt
.section .rodata
.type __FUNCTION__.2219, @object
.size __FUNCTION__.2219, 4
__FUNCTION__.2219:
.string "plt"
.type __FUNCTION__.2215, @object
.size __FUNCTION__.2215, 4
__FUNCTION__.2215:
.string "bar"
| {
"language": "Assembly"
} |
config TEGRA_MC
bool "NVIDIA Tegra Memory Controller support"
default y
depends on ARCH_TEGRA
help
This driver supports the Memory Controller (MC) hardware found on
NVIDIA Tegra SoCs.
config TEGRA124_EMC
bool "NVIDIA Tegra124 External Memory Controller driver"
default y
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
help
This driver is for the External Memory Controller (EMC) found on
Tegra124 chips. The EMC controls the external DRAM on the board.
This driver is required to change memory timings / clock rate for
external memory.
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -S -emit-llvm -triple %itanium_abi_triple -o - %s -finstrument-functions -disable-llvm-passes | FileCheck %s
int test1(int x) {
// CHECK: @_Z5test1i(i32 {{.*}}%x) #[[ATTR1:[0-9]+]]
// CHECK: ret
return x;
}
int test2(int) __attribute__((no_instrument_function));
int test2(int x) {
// CHECK: @_Z5test2i(i32 {{.*}}%x) #[[ATTR2:[0-9]+]]
// CHECK: ret
return x;
}
// CHECK: attributes #[[ATTR1]] =
// CHECK-SAME: "instrument-function-entry"="__cyg_profile_func_enter"
// CHECK-SAME: "instrument-function-exit"="__cyg_profile_func_exit"
// CHECK: attributes #[[ATTR2]] =
// CHECK-NOT: "instrument-function-entry"
// This test case previously crashed code generation. It exists solely
// to test -finstrument-function does not crash codegen for this trivial
// case.
namespace rdar9445102 {
class Rdar9445102 {
public:
Rdar9445102();
};
}
static rdar9445102::Rdar9445102 s_rdar9445102Initializer;
| {
"language": "Assembly"
} |
/* mpf_init_set_d -- Initialize a float and assign it from a double.
Copyright 1993-1995, 2000, 2001, 2004 Free Software Foundation, Inc.
This file is part of the GNU MP Library.
The GNU MP Library is free software; you can redistribute it and/or modify
it under the terms of either:
* the GNU Lesser General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your
option) any later version.
or
* the GNU General Public License as published by the Free Software
Foundation; either version 2 of the License, or (at your option) any
later version.
or both in parallel, as here.
The GNU MP Library is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received copies of the GNU General Public License and the
GNU Lesser General Public License along with the GNU MP Library. If not,
see https://www.gnu.org/licenses/. */
#include "gmp-impl.h"
void
mpf_init_set_d (mpf_ptr r, double val)
{
mp_size_t prec = __gmp_default_fp_limb_precision;
r->_mp_prec = prec;
r->_mp_d = __GMP_ALLOCATE_FUNC_LIMBS (prec + 1);
mpf_set_d (r, val);
}
| {
"language": "Assembly"
} |
dnl AMD64 mpn_add_n, mpn_sub_n optimised for bobcat.
dnl Copyright 2003-2005, 2007, 2008, 2010-2013 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb
C AMD K8,K9 1.77
C AMD K10 1.76\1.82
C AMD bd1 1.67\2.12
C AMD bd2 1.62\1.82
C AMD bd3
C AMD bd4 1.55\2.2
C AMD zen
C AMD bt1 2.54
C AMD bt2 2
C Intel P4 11
C Intel PNR 4.76
C Intel NHM 5.27
C Intel SBR 2
C Intel IBR 1.94
C Intel HWL 1.63
C Intel BWL 1.51
C Intel SKL 1.51
C Intel atom 3.56
C Intel SLM 4
C VIA nano
C The loop of this code is the result of running a code generation and
C optimization tool suite written by David Harvey and Torbjorn Granlund.
C INPUT PARAMETERS
define(`rp', `%rdi') C rcx
define(`up', `%rsi') C rdx
define(`vp', `%rdx') C r8
define(`n', `%rcx') C r9
define(`cy', `%r8') C rsp+40 (mpn_add_nc and mpn_sub_nc)
ifdef(`OPERATION_add_n', `
define(ADCSBB, adc)
define(func, mpn_add_n)
define(func_nc, mpn_add_nc)')
ifdef(`OPERATION_sub_n', `
define(ADCSBB, sbb)
define(func, mpn_sub_n)
define(func_nc, mpn_sub_nc)')
MULFUNC_PROLOGUE(mpn_add_n mpn_add_nc mpn_sub_n mpn_sub_nc)
ABI_SUPPORT(DOS64)
ABI_SUPPORT(STD64)
ASM_START()
TEXT
ALIGN(16)
PROLOGUE(func)
FUNC_ENTRY(4)
xor %r8, %r8
L(ent): test $1, R8(n)
jnz L(bx1)
L(bx0): test $2, R8(n)
jnz L(b10)
L(b00): shr $2, n
neg %r8
mov $3, R32(%rax)
mov (up), %r10
mov 8(up), %r11
jmp L(lo0)
L(b10): shr $2, n
neg %r8
mov $1, R32(%rax)
mov (up), %r8
mov 8(up), %r9
jrcxz L(cj2)
jmp L(top)
L(bx1): test $2, R8(n)
jnz L(b11)
L(b01): shr $2, n
neg %r8
mov $0, R32(%rax)
mov (up), %r9
jrcxz L(cj1)
mov 8(up), %r10
jmp L(lo1)
ALIGN(8)
L(b11): inc n
shr $2, n
neg %r8
mov $2, R32(%rax)
mov (up), %r11
jmp L(lo3)
ALIGN(4)
L(top): mov 8(up,%rax,8), %r10
ADCSBB -8(vp,%rax,8), %r8
mov %r8, -8(rp,%rax,8)
L(lo1): mov 16(up,%rax,8), %r11
ADCSBB (vp,%rax,8), %r9
lea 4(%rax), %rax
mov %r9, -32(rp,%rax,8)
L(lo0): ADCSBB -24(vp,%rax,8), %r10
mov %r10, -24(rp,%rax,8)
L(lo3): ADCSBB -16(vp,%rax,8), %r11
dec n
mov -8(up,%rax,8), %r8
mov %r11, -16(rp,%rax,8)
L(lo2): mov (up,%rax,8), %r9
jnz L(top)
L(cj2): ADCSBB -8(vp,%rax,8), %r8
mov %r8, -8(rp,%rax,8)
L(cj1): ADCSBB (vp,%rax,8), %r9
mov %r9, (rp,%rax,8)
mov $0, R32(%rax)
adc $0, R32(%rax)
FUNC_EXIT()
ret
EPILOGUE()
ALIGN(16)
PROLOGUE(func_nc)
FUNC_ENTRY(4)
IFDOS(` mov 56(%rsp), %r8 ')
jmp L(ent)
EPILOGUE()
| {
"language": "Assembly"
} |
#
# Samsung Pin control drivers
#
config PINCTRL_SAMSUNG
bool
select PINMUX
select PINCONF
config PINCTRL_EXYNOS
bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
select PINCTRL_SAMSUNG
config PINCTRL_EXYNOS5440
bool "Samsung EXYNOS5440 SoC pinctrl driver"
depends on SOC_EXYNOS5440
select PINMUX
select PINCONF
config PINCTRL_S3C24XX
bool "Samsung S3C24XX SoC pinctrl driver"
depends on ARCH_S3C24XX
select PINCTRL_SAMSUNG
config PINCTRL_S3C64XX
bool "Samsung S3C64XX SoC pinctrl driver"
depends on ARCH_S3C64XX
select PINCTRL_SAMSUNG
| {
"language": "Assembly"
} |
#include "z_en_anubice.h"
#define ROOM 0x00
#define FLAGS 0x00000015
void EnAnubice_Init(EnAnubice* this, GlobalContext* globalCtx);
void EnAnubice_Destroy(EnAnubice* this, GlobalContext* globalCtx);
void EnAnubice_Update(EnAnubice* this, GlobalContext* globalCtx);
void EnAnubice_Draw(EnAnubice* this, GlobalContext* globalCtx);
/*
const ActorInit En_Anubice_InitVars =
{
ACTOR_EN_ANUBICE,
ACTORTYPE_ENEMY,
ROOM,
FLAGS,
OBJECT_ANUBICE,
sizeof(EnAnubice),
(ActorFunc)EnAnubice_Init,
(ActorFunc)EnAnubice_Destroy,
(ActorFunc)EnAnubice_Update,
(ActorFunc)EnAnubice_Draw,
};
*/
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B1120.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B11C0.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/EnAnubice_Init.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/EnAnubice_Destroy.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B142C.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B1524.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B15CC.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B16AC.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B17FC.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B1884.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B1984.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B1A54.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/EnAnubice_Update.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B2104.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/func_809B2150.s")
#pragma GLOBAL_ASM("asm/non_matchings/overlays/actors/ovl_En_Anubice/EnAnubice_Draw.s")
| {
"language": "Assembly"
} |
(*
Result: OK
$Log: flex_rec.sml,v $
Revision 1.1 1994/05/27 17:17:07 jont
new file
Copyright 2013 Ravenbrook Limited <http://www.ravenbrook.com/>.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*)
val y = (0,0,0,0,0,0,0,0,0,0)
val x = #10 y
| {
"language": "Assembly"
} |
LIBRARY "gemaes","gemvdi"
REM $option k20
REM $option g,y+,v+,u+,#,[,]
DEFINT a-z
DIM SHARED junk
REM DECLARE FUNCTION Dialog
REM $include sharewar.bh
REM $include gemaes.bh
DIM SHARED tree&
DEF FNObjectAddr&(object)=tree&+object*ob_sizeof
DEF FNGetob_spec&(object)=PEEKL(FNObjectAddr&(object)+ob_spec)
SUB Exclob_state(object,flag_mask)
STATIC t&
t&=FNObjectAddr&(object)+ob_state
POKEW t&,PEEKW(t&) AND (NOT flag_mask)
END SUB
SUB SelectTreeAddr(t&)
tree&=t&
END SUB
SUB SelectTree(treeno)
STATIC formaddr&
junk=FNrsrc_gaddr(type_tree,treeno,formaddr&)
SelectTreeAddr formaddr&
END SUB
SUB form_show (dial)
STATIC junk,tree&,x,y,w,h,but,type_tree,treeno,tree&
junk=FNrsrc_gaddr(0,dial,tree&)
form_center tree&,x,y,w,h
form_dial FMD_START,0,0,0,0,x,y,w,h
junk=FNobjc_draw(tree&,0,10,x,y,w,h)
END SUB
SUB form_show_part (dial, object)
STATIC junk,tree&,x,y,w,h,but,type_tree,treeno,tree&
STATIC x2,y2,w2,h2
junk=FNrsrc_gaddr(0,dial,tree&)
form_center tree&,x,y,w,h
SelectTree dial
form_dial FMD_START,0,0,0,0,x,y,w,h
junk=FNobjc_draw(tree&,object,0,x,y,w,h)
END SUB
'Returns the value of the ob_x field in the given object of the current tree
DEF FNGetob_x (object)
FNGetob_x=PEEKW(FNObjectAddr&(object)+ob_x)
END DEF
'Returns the value of the ob_y field in the given object of the current tree
DEF FNGetob_y (object)
FNGetob_y=PEEKW(FNObjectAddr&(object)+ob_y)
END DEF
'Returns the value of the ob_width field in the given object of the current tree
DEF FNGetob_width (object)
FNGetob_width=PEEKW(FNObjectAddr&(object)+ob_width)
END DEF
'Returns the value of the ob_height field in the given object of the current tree
DEF FNGetob_height (object)
FNGetob_height=PEEKW(FNObjectAddr&(object)+ob_height)
END DEF
'Sets the value of the ob_width field in the given object of the current tree
SUB Setob_width (object, value)
POKEW FNObjectAddr&(object)+ob_width,value
END SUB
SUB InitResourceFile(name$)
STATIC junk
SHARED resource_loaded
IF FNrsrc_load(name$)=0 THEN
junk=FNform_alert(1,"[3][ Couldn't find SHAREWAR.RSC! ][ Quit ]")
SYSTEM
END IF
resource_loaded=-1
END SUB
SUB StartProgram (resourcefile$)
WINDOW ON
InitResourceFile resourcefile$
END SUB
SUB StopProgram
STATIC junk
junk=FNrsrc_free
STOP -1
END SUB
SUB GetSetObjects
SHARED wwidth,swidth,spart
SelectTree sharedial
wwidth=FNgetob_width (whiteback)
setob_width slidebar, 0
swidth=0
spart=wwidth/100
END SUB
SUB do_timer
SHARED swidth,wwidth,spart
SHARED finished
swidth=swidth+spart
IF swidth>wwidth THEN
finished=-1
ELSE
setob_width slidebar,swidth
' form_show_part sharedial, whiteback
form_show_part sharedial, slidebar
END IF
END SUB
DIM mess(16)
StartProgram "SHAREWAR.RSC"
GetSetObjects
form_show (sharedial)
DO
e=FNevnt_multi(MU_TIMER,0,0,0,0,0,0,0,0,0,0,0,0,0,_
VARPTR(mess(0)),100,0,0,0,0,k,0)
IF e AND MU_TIMER THEN CALL do_timer
IF finished=-1 THEN CALL StopProgram
LOOP | {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
start AppIconAreaSCMonikerResource, data;
chunk RenameFileSCBitmap = data {
Bitmap <48,30,0,BMF_4BIT or mask BMT_MASK>
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x18, 0x00, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdb, 0xbd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xbb, 0xb8, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x1c, 0x0f, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdb, 0xb8, 0xdd,
0xdd, 0xdd, 0xcc, 0xcc, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x1c, 0x1f, 0x80, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdb, 0xb8, 0xdd,
0xdd, 0xdc, 0xcc, 0xc8, 0x8d, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x07, 0x1c, 0x7f, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdc, 0xcc, 0xdd, 0xdb, 0xb8, 0xdd,
0xdc, 0xcc, 0xc8, 0x88, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x0f, 0xdf, 0xff, 0x80, 0x00, 0x00
db 0xdd, 0xdd, 0xbb, 0xcc, 0xcc, 0xdb, 0xbb, 0xbb,
0xcc, 0xcc, 0x88, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x1f, 0xff, 0xff, 0xc0, 0x00, 0x00
db 0xdd, 0xdb, 0xb8, 0xbb, 0xcc, 0xcc, 0xb8, 0x8c,
0xcc, 0x88, 0x8b, 0xb8, 0x8b, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x1f, 0xff, 0xef, 0x60, 0x00, 0x00
db 0xdd, 0xdb, 0xb8, 0xbb, 0x88, 0xcc, 0xcc, 0xcc,
0xcb, 0x8d, 0xbb, 0x88, 0xdb, 0x8d, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x0f, 0x9f, 0xee, 0x20, 0x00, 0x00
db 0xdd, 0xdd, 0x8b, 0xbb, 0x8d, 0xdb, 0xcc, 0xcc,
0xcb, 0x8d, 0xbb, 0x8d, 0xdd, 0x8d, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x1b, 0x9f, 0xee, 0x00, 0x00, 0x00
db 0xdd, 0xdb, 0xbd, 0xbb, 0x8d, 0xdc, 0xcc, 0xcc,
0xcc, 0xcd, 0xbb, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x3f, 0xbf, 0xfe, 0x00, 0x00, 0x00
db 0xdd, 0xbb, 0x88, 0xbb, 0x8d, 0xcc, 0xc8, 0x8c,
0xcc, 0xcc, 0xcb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x1d, 0xff, 0xff, 0xc0, 0x00, 0x00
db 0xdd, 0xdb, 0xbb, 0xdb, 0xcc, 0xc8, 0xbb, 0xbb,
0x8c, 0xcc, 0xcc, 0xcb, 0xbb, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x0f, 0xf7, 0xbf, 0xe1, 0x80, 0x00
db 0xdd, 0xdd, 0x88, 0x8c, 0xcc, 0x88, 0xd8, 0x88,
0x8d, 0x8c, 0xcc, 0xcc, 0xc8, 0x8d, 0xdd, 0xde,
0xed, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x03, 0xe0, 0x0f, 0xc7, 0xc0, 0x00
db 0xdd, 0xdd, 0xdd, 0xcc, 0x88, 0x8d, 0xdd, 0xdd,
0xdd, 0xdd, 0x8c, 0xcc, 0xc8, 0xdd, 0xde, 0xee,
0xe8, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x01, 0x80, 0x03, 0xc3, 0xc0, 0x00
db 0xdd, 0xdd, 0xdd, 0xd8, 0x8d, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0x8c, 0xc8, 0xdd, 0xdd, 0x8e,
0xe8, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x00, 0x00, 0xc1, 0xc0, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0x88, 0xdd, 0xdd, 0xde,
0xe8, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x00, 0x00, 0x01, 0xc0, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xe8, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x00, 0x3c, 0x1d, 0xc3, 0xc0
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xee, 0xee, 0xdd, 0xdd, 0xde, 0xee, 0xde,
0xe8, 0xdd, 0xdd, 0xee, 0xee, 0xdd, 0xdd, 0xdd
db 0x00, 0x00, 0xfe, 0x3f, 0xc7, 0xe0
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xee, 0x78, 0x8e, 0xed, 0xdd, 0xee, 0x88, 0xee,
0xe8, 0xdd, 0xde, 0x78, 0x88, 0xed, 0xdd, 0xdd
db 0x00, 0x00, 0xe7, 0x39, 0xc6, 0x30
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xe8, 0x8d, 0xde, 0xe8, 0xdd, 0xe8, 0x8d, 0xde,
0xe8, 0xdd, 0xde, 0x8d, 0xdd, 0xee, 0xdd, 0xdd
db 0x00, 0x01, 0xc3, 0x71, 0xcf, 0xf8
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xe8, 0xdd, 0xdd, 0x88, 0xde, 0xe8, 0xdd, 0xde,
0xe8, 0xdd, 0xee, 0xee, 0xee, 0xee, 0x8d, 0xdd
db 0x00, 0x01, 0xc0, 0x71, 0xcf, 0xf8
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xe8, 0xdd, 0xdd, 0xdd, 0xde, 0xe8, 0xdd, 0xde,
0xe8, 0xdd, 0xee, 0x88, 0x88, 0x88, 0x8d, 0xdd
db 0x00, 0x01, 0xc0, 0x71, 0xce, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xe8, 0xdd, 0xdd, 0xdd, 0xde, 0xe8, 0xdd, 0xde,
0xe8, 0xdd, 0xee, 0x8d, 0xdd, 0xdd, 0xdd, 0xdd
db 0x00, 0x01, 0xc1, 0x71, 0xce, 0x08
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xee, 0xdd, 0xdd, 0xde, 0xde, 0xe8, 0xdd, 0xde,
0xe8, 0xdd, 0xee, 0x8d, 0xdd, 0xdd, 0xed, 0xdd
db 0x00, 0x01, 0xe3, 0xf1, 0xce, 0x1c
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xde,
0xee, 0x8d, 0xdd, 0xe7, 0x8e, 0xe8, 0xdd, 0xde,
0xe8, 0xdd, 0xee, 0xed, 0xdd, 0xde, 0x78, 0xdd
db 0x00, 0x00, 0xff, 0x33, 0xc7, 0x38
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xee, 0xee, 0xee, 0x78, 0xdd, 0xee, 0xdd, 0xee,
0xee, 0xdd, 0xde, 0xe8, 0xdd, 0xee, 0x8d, 0xdd
db 0x00, 0x00, 0x7e, 0x1f, 0xe3, 0xf8
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xde, 0xee, 0xe8, 0x8d, 0xdd, 0xde, 0xee, 0x7e,
0xe8, 0x8d, 0xdd, 0xee, 0xee, 0x78, 0x8d, 0xdd
db 0x00, 0x00, 0x3c, 0x0e, 0xc1, 0xe0
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0x88, 0x88, 0xdd, 0xdd, 0xdd, 0x88, 0x8d,
0x88, 0xdd, 0xdd, 0xd8, 0x88, 0x8d, 0xdd, 0xdd
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
db 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd
}
end AppIconAreaSCMonikerResource;
start AppIconAreaSMMonikerResource, data;
chunk RenameFileSMBitmap = data {
Bitmap <48,30,0,BMF_MONO>
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
db 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00
db 0x00, 0x1c, 0x00, 0x00, 0x00, 0x00
db 0x00, 0x0c, 0x07, 0x80, 0x00, 0x00
db 0x00, 0x0c, 0x0f, 0x00, 0x00, 0x00
db 0x03, 0x8c, 0x3c, 0x00, 0x00, 0x00
db 0x07, 0xef, 0xf9, 0xc0, 0x00, 0x00
db 0x0d, 0xfc, 0xe3, 0x20, 0x00, 0x00
db 0x0d, 0x9f, 0xe6, 0x20, 0x00, 0x00
db 0x03, 0x8f, 0xe6, 0x00, 0x00, 0x00
db 0x0d, 0x8f, 0xf6, 0x00, 0x00, 0x00
db 0x19, 0x9c, 0xff, 0x00, 0x00, 0x00
db 0x0e, 0xf7, 0xbf, 0xe0, 0x00, 0x00
db 0x00, 0xe0, 0x0f, 0xc0, 0xc0, 0x00
db 0x01, 0x80, 0x03, 0xc3, 0xc0, 0x00
db 0x00, 0x00, 0x00, 0xc0, 0xc0, 0x00
db 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00
db 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00
db 0x00, 0x00, 0x1e, 0x0e, 0xc1, 0xe0
db 0x00, 0x00, 0x63, 0x19, 0xc2, 0x10
db 0x00, 0x00, 0x43, 0x10, 0xc2, 0x18
db 0x00, 0x00, 0xc0, 0x30, 0xc7, 0xf8
db 0x00, 0x00, 0xc0, 0x30, 0xc6, 0x00
db 0x00, 0x00, 0xc0, 0x30, 0xc6, 0x00
db 0x00, 0x00, 0xe0, 0xb0, 0xc6, 0x04
db 0x00, 0x00, 0xe1, 0x30, 0xc7, 0x08
db 0x00, 0x00, 0x7e, 0x19, 0xe3, 0x18
db 0x00, 0x00, 0x3c, 0x0e, 0xc1, 0xe0
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
end AppIconAreaSMMonikerResource;
start AppIconAreaSCGAMonikerResource, data;
chunk RenameFileSCGABitmap = data {
Bitmap <48,14,0,BMF_MONO>
db 0x07, 0x00, 0x00, 0x00, 0x00, 0x00
db 0x00, 0xf0, 0x00, 0x00, 0x01, 0xe0
db 0x00, 0x3f, 0xbf, 0x8f, 0xfe, 0x00
db 0x00, 0x73, 0xf9, 0xfe, 0xe0, 0x00
db 0x00, 0x7f, 0xff, 0x9c, 0x00, 0x00
db 0x01, 0xff, 0xb9, 0xfc, 0xe0, 0x00
db 0x3e, 0x73, 0xbf, 0x8f, 0xc0, 0x00
db 0x00, 0x00, 0x00, 0x00, 0x38, 0x00
db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
db 0x00, 0x00, 0x03, 0xf3, 0xf9, 0xfc
db 0x00, 0x00, 0x07, 0x3b, 0x9d, 0xc0
db 0x00, 0x00, 0x07, 0x03, 0x9d, 0xf0
db 0x00, 0x00, 0x07, 0x3b, 0x9d, 0xc0
db 0x00, 0x00, 0x03, 0xf3, 0xf9, 0xfc
}
end AppIconAreaSCGAMonikerResource;
| {
"language": "Assembly"
} |
OUTPUT_ARCH(mips)
SECTIONS {
.text : {
_code_start = .;
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.data.lzma)
}
. = ALIGN(32);
.data : {
*(.data)
*(.data.*)
. = . + 524288; /* workaround for buggy bootloaders */
}
. = ALIGN(32);
_code_end = .;
_bss_start = .;
.bss : {
*(.bss)
*(.bss.*)
}
. = ALIGN(32);
_bss_end = .;
. = . + 8192;
_stack = .;
workspace = .;
}
| {
"language": "Assembly"
} |
;
; trap_put.m
; code for generic go-to-object-and-drop-something operation.
;
;
; This file should be assembled as position independent code.
;
; Originally coded by Randy Farmer
; Prettified by Chip Morningstar
; Lucasfilm Ltd.
; 30-April-1986
;
include "action_head.i"
actionStart
lda in_hand_noid
if (zero) {chainTo v_beep } ; Hand must NOT be empty
cmp pointed_noid
if (equal) {chainTo v_beep}
getProp pointed, TRAP_type ; 0, 1 ,2 or ???
cmp #2 ; ground ONLY
if (!equal) {chainto v_beep}
containerAbort
doMyAction ACTION_GO ; My GO walks to this object
waitWhile animation_wait_bit ; Wait till we get there
jsr v_face_cursor
chore AV_ACT_bend_over
lda #THE_REGION_NOID ; Drop in the region
rjsr v_putInto
chore AV_ACT_bend_back
rts
actionEnd
| {
"language": "Assembly"
} |
.size 8000
.text@48
jp lstatint
.text@100
jp lbegin
.data@143
c0
.text@150
lbegin:
ld a, 00
ldff(ff), a
ld a, 30
ldff(00), a
ld a, 01
ldff(4d), a
stop, 00
ld a, ff
ldff(45), a
ld b, 42
call lwaitly_b
ld a, 40
ldff(41), a
ld a, 02
ldff(ff), a
xor a, a
ldff(0f), a
ei
ld a, b
inc a
inc a
ldff(45), a
ld c, 0f
.text@1000
lstatint:
ld a, 48
ldff(41), a
ldff(45), a
xor a, a
.text@10d3
ldff(c), a
ld a, 44
ldff(45), a
nop
nop
ldff a, (c)
jp lprint_a
.text@7000
lprint_a:
push af
ld b, 91
call lwaitly_b
xor a, a
ldff(40), a
ld bc, 7a00
ld hl, 8000
ld d, 00
lprint_copytiles:
ld a, (bc)
inc bc
ld(hl++), a
dec d
jrnz lprint_copytiles
pop af
ld b, a
srl a
srl a
srl a
srl a
ld(9800), a
ld a, b
and a, 0f
ld(9801), a
ld a, c0
ldff(47), a
ld a, 80
ldff(68), a
ld a, ff
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
ldff(69), a
xor a, a
ldff(69), a
ldff(69), a
ldff(43), a
ld a, 91
ldff(40), a
lprint_limbo:
jr lprint_limbo
.text@7400
lwaitly_b:
ld c, 44
lwaitly_b_loop:
ldff a, (c)
cmp a, b
jrnz lwaitly_b_loop
ret
.data@7a00
00 00 7f 7f 41 41 41 41
41 41 41 41 41 41 7f 7f
00 00 08 08 08 08 08 08
08 08 08 08 08 08 08 08
00 00 7f 7f 01 01 01 01
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 01 01 01 01
3f 3f 01 01 01 01 7f 7f
00 00 41 41 41 41 41 41
7f 7f 01 01 01 01 01 01
00 00 7f 7f 40 40 40 40
7e 7e 01 01 01 01 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 41 41 41 41 7f 7f
00 00 7f 7f 01 01 02 02
04 04 08 08 10 10 10 10
00 00 3e 3e 41 41 41 41
3e 3e 41 41 41 41 3e 3e
00 00 7f 7f 41 41 41 41
7f 7f 01 01 01 01 7f 7f
00 00 08 08 22 22 41 41
7f 7f 41 41 41 41 41 41
00 00 7e 7e 41 41 41 41
7e 7e 41 41 41 41 7e 7e
00 00 3e 3e 41 41 40 40
40 40 40 40 41 41 3e 3e
00 00 7e 7e 41 41 41 41
41 41 41 41 41 41 7e 7e
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 7f 7f
00 00 7f 7f 40 40 40 40
7f 7f 40 40 40 40 40 40
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBCDIO
bool "libcdio"
depends on BR2_USE_MMU # fork()
select BR2_PACKAGE_LIBICONV if !BR2_ENABLE_LOCALE
help
The GNU Compact Disc Input and Control library.
http://www.gnu.org/software/libcdio/
| {
"language": "Assembly"
} |
/*
*****************************************************************************
**
** File : LinkerScript.ld
**
** Abstract : Linker script for STM32F446ZETx Device with
** 512KByte FLASH, 128KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
** (c)Copyright Ac6.
** You may use this file as-is or modify it according to the needs of your
** project. Distribution of this file (unmodified or modified) is not
** permitted. Ac6 permit registered System Workbench for MCU users the
** rights to distribute the assembled, compiled & linked contents of this
** file as part of an application binary file, provided that it is built
** using the System Workbench for MCU toolchain.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20020000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200;; /* required amount of heap */
_Min_Stack_Size = 0x400;; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}
| {
"language": "Assembly"
} |
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# CRYSTAL-12.288MHZ"
#
DEF CRYSTAL-12.288MHZ" Y 0 40 N N 1 L N
F0 "Y" 0 80 45 H V L BNN
F1 "CRYSTAL-12.288MHZ\"" 0 -80 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 30 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-09653" 160 215 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-12MHZ"
#
DEF CRYSTAL-12MHZ" Y 0 40 N N 1 L N
F0 "Y" 0 80 45 H V L BNN
F1 "CRYSTAL-12MHZ\"" 0 -80 45 H V L BNN
F2 "Clocks:CRYSTAL-SMD-3.2X2.5MM" 30 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-13518" 160 215 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-16MHZPTH-HC49US
#
DEF CRYSTAL-16MHZPTH-HC49US Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-16MHZPTH-HC49US" 0 -150 45 H V L BNN
F2 "HC49US" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-08181" 0 250 60 H V C CNN
$FPLIST
*HC49US*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-16MHZSMD-5X3.2
#
DEF CRYSTAL-16MHZSMD-5X3.2 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-16MHZSMD-5X3.2" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-08218" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-24MHZ"
#
DEF CRYSTAL-24MHZ" Y 0 40 N N 1 L N
F0 "Y" 0 80 45 H V L BNN
F1 "CRYSTAL-24MHZ\"" 0 -80 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 30 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-08298" 160 215 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-26MHZSMD-3.2X2.5
#
DEF CRYSTAL-26MHZSMD-3.2X2.5 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-26MHZSMD-3.2X2.5" 0 -300 45 H V L BNN
F2 "CRYSTAL-SMD-3.2X2.5MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-12454" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-3.2X2.5MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -110 0 -62 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 3 2 0 -200 100 U 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
X 3 4 0 -200 100 U 40 40 1 1 P N
ENDDRAW
ENDDEF
#
# CRYSTAL-32.768KHZPTH-2X6
#
DEF CRYSTAL-32.768KHZPTH-2X6 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32.768KHZPTH-2X6" 0 -150 45 H V L BNN
F2 "CRYSTAL-PTH-2X6-CYL" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-10112" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-PTH-2X6-CYL*
*CRYSTAL-PTH-2X6-CYL-KIT*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-32.768KHZPTH-2X6-KIT
#
DEF CRYSTAL-32.768KHZPTH-2X6-KIT Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32.768KHZPTH-2X6-KIT" 0 -150 45 H V L BNN
F2 "CRYSTAL-PTH-2X6-CYL-KIT" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-10112" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-PTH-2X6-CYL-KIT*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-32.768KHZSMD-2X6
#
DEF CRYSTAL-32.768KHZSMD-2X6 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32.768KHZSMD-2X6" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-2X6-CYL" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-07894" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-2X6-CYL*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 X1 -100 0 0 R 40 40 1 1 P
X 2 X2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-32.768KHZSMD-3.2X1.5
#
DEF CRYSTAL-32.768KHZSMD-3.2X1.5 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32.768KHZSMD-3.2X1.5" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-3.2X1.5MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-13062" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-3.2X1.5MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 P$1 -100 0 0 R 40 40 1 1 P
X 2 P$2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-32.768KHZSMD-MC146
#
DEF CRYSTAL-32.768KHZSMD-MC146 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32.768KHZSMD-MC146" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-MC-146" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-09342" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-MC-146*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 2 P$1 100 0 0 L 40 40 1 1 P
X 1 P$2 -100 0 0 R 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-32MHZ-SMD-2.0X1.6MM
#
DEF CRYSTAL-32MHZ-SMD-2.0X1.6MM Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-32MHZ-SMD-2.0X1.6MM" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-2.0X1.6MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-13459" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-2.0X1.6MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-8MHZSMD-5X3.2
#
DEF CRYSTAL-8MHZSMD-5X3.2 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-8MHZSMD-5X3.2" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-09431" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-8MHZSMD-HC49UP
#
DEF CRYSTAL-8MHZSMD-HC49UP Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-8MHZSMD-HC49UP" 0 -150 45 H V L BNN
F2 "HC49UP" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-11706" 0 250 60 H V C CNN
$FPLIST
*HC49UP*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTAL-GROUNDEDSMD-3.2X2.5
#
DEF CRYSTAL-GROUNDEDSMD-3.2X2.5 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-GROUNDEDSMD-3.2X2.5" 0 -300 45 H V L BNN
F2 "CRYSTAL-SMD-3.2X2.5MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-3.2X2.5MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -110 0 -62 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 3 2 0 -200 100 U 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
X 3 4 0 -200 100 U 40 40 1 1 P N
ENDDRAW
ENDDEF
#
# CRYSTAL-GROUNDEDSMD-5X3.2
#
DEF CRYSTAL-GROUNDEDSMD-5X3.2 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTAL-GROUNDEDSMD-5X3.2" 0 -300 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -110 0 -62 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 2 1 100 0 0 L 40 40 1 1 P
X 3 2 0 -200 100 U 40 40 1 1 P
X 1 3 -100 0 0 R 40 40 1 1 P
X 3 4 0 -200 100 U 40 40 1 1 P N
ENDDRAW
ENDDEF
#
# CRYSTALPTH-2X6
#
DEF CRYSTALPTH-2X6 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALPTH-2X6" 0 -150 45 H V L BNN
F2 "CRYSTAL-PTH-2X6-CYL" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-PTH-2X6-CYL*
*CRYSTAL-PTH-2X6-CYL-KIT*
*CRYSTAL-PTH-3X8-CYL*
*HC49US*
*HC49U*
*HC49UP*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALPTH-2X6-KIT
#
DEF CRYSTALPTH-2X6-KIT Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALPTH-2X6-KIT" 0 -150 45 H V L BNN
F2 "CRYSTAL-PTH-2X6-CYL-KIT" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-PTH-2X6-CYL-KIT*
*CRYSTAL-PTH-3X8-CYL*
*HC49US*
*HC49U*
*HC49UP*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALPTH-3X8
#
DEF CRYSTALPTH-3X8 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALPTH-3X8" 0 -150 45 H V L BNN
F2 "CRYSTAL-PTH-3X8-CYL" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-PTH-3X8-CYL*
*HC49US*
*HC49U*
*HC49UP*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALPTH-HC49US
#
DEF CRYSTALPTH-HC49US Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALPTH-HC49US" 0 -150 45 H V L BNN
F2 "HC49US" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*HC49US*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALPTH-HC49UV
#
DEF CRYSTALPTH-HC49UV Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALPTH-HC49UV" 0 -150 45 H V L BNN
F2 "HC49U" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*HC49U*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-2X6
#
DEF CRYSTALSMD-2X6 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-2X6" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-2X6-CYL" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-2X6-CYL*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 X1 -100 0 0 R 40 40 1 1 P
X 2 X2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-3.2X1.5
#
DEF CRYSTALSMD-3.2X1.5 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-3.2X1.5" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-3.2X1.5MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-3.2X1.5MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 P$1 -100 0 0 R 40 40 1 1 P
X 2 P$2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-3.2X2.5
#
DEF CRYSTALSMD-3.2X2.5 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-3.2X2.5" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-3.2X2.5MM" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-3.2X2.5MM*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-5X3.2-2PAD
#
DEF CRYSTALSMD-5X3.2-2PAD Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-5X3.2-2PAD" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-2PAD" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-2PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 P$1 -100 0 0 R 40 40 1 1 P
X 2 P$2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-5X3.2-4PAD
#
DEF CRYSTALSMD-5X3.2-4PAD Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-5X3.2-4PAD" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-5X3.2-4PAD" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-5X3.2-4PAD*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 3 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-HC49UP
#
DEF CRYSTALSMD-HC49UP Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-HC49UP" 0 -150 45 H V L BNN
F2 "HC49UP" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*HC49UP*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -100 0 0 R 40 40 1 1 P
X 2 2 100 0 0 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CRYSTALSMD-MC146
#
DEF CRYSTALSMD-MC146 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "CRYSTALSMD-MC146" 0 -150 45 H V L BNN
F2 "CRYSTAL-SMD-MC-146" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*CRYSTAL-SMD-MC-146*
$ENDFPLIST
DRAW
T 0 -72 -31 27 0 1 0 1 Normal 0 C C
T 0 73 -31 27 0 1 0 2 Normal 0 C C
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -40 70 -40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 -70 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 2 P$1 100 0 0 L 40 40 1 1 P
X 1 P$2 -100 0 0 R 40 40 1 1 P
ENDDRAW
ENDDEF
#
# DS1077U
#
DEF DS1077U U 0 40 Y Y 1 L N
F0 "U" -400 450 45 H V L BNN
F1 "DS1077U" -400 -500 45 H V L BNN
F2 "SO08-TIGHT" 0 450 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "IC-09075" 0 500 60 H V C CNN
$FPLIST
*SO08-TIGHT*
$ENDFPLIST
DRAW
P 5 1 1 0 -400 400 -400 -400 400 -400 400 400 -400 400 f
X OUT1 1 -500 300 100 R 40 40 1 1 B
X OUT0 2 -500 100 100 R 40 40 1 1 B
X VCC 3 -500 -100 100 R 40 40 1 1 B
X GND 4 -500 -300 100 R 40 40 1 1 B
X CTRL0 5 500 -300 100 L 40 40 1 1 B
X CTRL1 6 500 -100 100 L 40 40 1 1 B
X SDA 7 500 100 100 L 40 40 1 1 B
X SCL 8 500 300 100 L 40 40 1 1 B
ENDDRAW
ENDDEF
#
# DS1307Z
#
DEF DS1307Z U 0 40 Y Y 1 L N
F0 "U" -300 250 45 H V L BNN
F1 "DS1307Z" -300 -400 45 H V L BNN
F2 "SO08-TIGHT" 0 350 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "IC-08138" 0 400 60 H V C CNN
$FPLIST
*SO08-TIGHT*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 200 400 200 400 -300 -300 -300 -300 200 f
X X1 1 -400 100 100 R 40 40 1 1 B
X X2 2 -400 0 100 R 40 40 1 1 B
X VBATT 3 -400 -100 100 R 40 40 1 1 B
X GND 4 -400 -200 100 R 40 40 1 1 B
X SDA 5 500 -200 100 L 40 40 1 1 B
X SCL 6 500 -100 100 L 40 40 1 1 B
X SQW 7 500 0 100 L 40 40 1 1 B
X VCC 8 500 100 100 L 40 40 1 1 B
ENDDRAW
ENDDEF
#
# DS3231M
#
DEF DS3231M RTC 0 40 Y Y 1 L N
F0 "RTC" -300 350 45 H V L BNN
F1 "DS3231M" -300 -300 45 H V L BNN
F2 "SO08" 0 450 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "IC-11985" 0 500 60 H V C CNN
$FPLIST
*SO08*
$ENDFPLIST
DRAW
P 5 1 1 0 300 -200 -300 -200 -300 300 300 300 300 -200 f
X 32KHZ 1 -500 200 200 R 40 40 1 1 O
X VCC 2 -500 100 200 R 40 40 1 1 W
X SQW 3 -500 0 200 R 40 40 1 1 O
X RST 4 -500 -100 200 R 40 40 1 1 B
X GND 5 500 -100 200 L 40 40 1 1 W
X VBAT 6 500 0 200 L 40 40 1 1 W
X SDA 7 500 100 200 L 40 40 1 1 B
X SCL 8 500 200 200 L 40 40 1 1 B
ENDDRAW
ENDDEF
#
# DS3234
#
DEF DS3234 U 0 40 Y Y 1 L N
F0 "U" -400 650 45 H V L BNN
F1 "DS3234" -400 -800 45 H V L BNN
F2 "SO20-0.3" 0 700 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "IC-10016" 0 750 60 H V C CNN
$FPLIST
*SO20-0.3*
$ENDFPLIST
DRAW
P 5 1 1 0 -400 600 -400 -700 500 -700 500 600 -400 600 f
X CS 1 -500 -100 100 R 40 40 1 1 B
X GND 2 600 300 100 L 40 40 1 1 B
X 32KHZ 3 -500 -600 100 R 40 40 1 1 B
X VCC 4 -500 500 100 R 40 40 1 1 B
X INT/SQW 5 -500 -300 100 R 40 40 1 1 B
X RST 6 -500 -500 100 R 40 40 1 1 B
X GND 7 600 200 100 L 40 40 1 1 B
X GND 8 600 100 100 L 40 40 1 1 B
X GND 9 600 0 100 L 40 40 1 1 B
X GND 10 600 -100 100 L 40 40 1 1 B
X SCLK 20 -500 200 100 R 40 40 1 1 B
X GND 11 600 -200 100 L 40 40 1 1 B
X GND 12 600 -300 100 L 40 40 1 1 B
X GND 13 600 -400 100 L 40 40 1 1 B
X GND 14 600 -500 100 L 40 40 1 1 B
X GND 15 600 -600 100 L 40 40 1 1 B
X VBAT 16 600 500 100 L 40 40 1 1 B
X DIN 17 -500 0 100 R 40 40 1 1 B
X SCLK 18 -500 300 100 R 40 40 1 1 B
X DOUT 19 -500 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# OSCILLATOR-16MHZSMD-7X5-4PAD
#
DEF OSCILLATOR-16MHZSMD-7X5-4PAD Y 0 40 Y N 1 L N
F0 "Y" -300 250 45 H V L BNN
F1 "OSCILLATOR-16MHZSMD-7X5-4PAD" -300 -300 45 H V L BNN
F2 "OSCILLATOR-SMD-7X5-4PAD" 0 350 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-11225" 0 400 60 H V C CNN
$FPLIST
*OSCILLATOR-SMD-7X5-4PAD*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 -200 -300 200 300 200 300 -200 -300 -200 f
X EN 1 -400 -100 100 R 40 40 1 1 B
X GND 2 400 -100 100 L 40 40 1 1 B
X OUT 3 400 100 100 L 40 40 1 1 B
X VCC 4 -400 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# OSCILLATOR-33MHZ
#
DEF OSCILLATOR-33MHZ Y 0 40 Y N 1 L N
F0 "Y" -300 250 45 H V L BNN
F1 "OSCILLATOR-33MHZ" -300 -300 45 H V L BNN
F2 "OSCILLATOR-SMD-5X3.2" 0 350 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-11986" 0 400 60 H V C CNN
$FPLIST
*OSCILLATOR-SMD-5X3.2*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 -200 -300 200 300 200 300 -200 -300 -200 f
X EN 1 -400 -100 100 R 40 40 1 1 B
X GND 2 400 -100 100 L 40 40 1 1 B
X OUT 3 400 100 100 L 40 40 1 1 B
X VCC 4 -400 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# OSCILLATORSMD-5X3
#
DEF OSCILLATORSMD-5X3 Y 0 40 Y N 1 L N
F0 "Y" -300 250 45 H V L BNN
F1 "OSCILLATORSMD-5X3" -300 -300 45 H V L BNN
F2 "OSCILLATOR-SMD-5X3.2" 0 300 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 350 60 H V C CNN
$FPLIST
*OSCILLATOR-SMD-5X3.2*
*OSCILLATOR-SMD-7X5-4PAD*
*OSCILLATOR-SMD-7.5X5.2-6PIN*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 -200 -300 200 300 200 300 -200 -300 -200 f
X EN 1 -400 -100 100 R 40 40 1 1 B
X GND 2 400 -100 100 L 40 40 1 1 B
X OUT 3 400 100 100 L 40 40 1 1 B
X VCC 4 -400 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# OSCILLATORSMD-7X5-4PAD
#
DEF OSCILLATORSMD-7X5-4PAD Y 0 40 Y N 1 L N
F0 "Y" -300 250 45 H V L BNN
F1 "OSCILLATORSMD-7X5-4PAD" -300 -300 45 H V L BNN
F2 "OSCILLATOR-SMD-7X5-4PAD" 0 350 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 400 60 H V C CNN
$FPLIST
*OSCILLATOR-SMD-7X5-4PAD*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 -200 -300 200 300 200 300 -200 -300 -200 f
X EN 1 -400 -100 100 R 40 40 1 1 B
X GND 2 400 -100 100 L 40 40 1 1 B
X OUT 3 400 100 100 L 40 40 1 1 B
X VCC 4 -400 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# OSCILLATORSMD-7X5-6PAD
#
DEF OSCILLATORSMD-7X5-6PAD Y 0 40 Y N 1 L N
F0 "Y" -300 250 45 H V L BNN
F1 "OSCILLATORSMD-7X5-6PAD" -300 -300 45 H V L BNN
F2 "OSCILLATOR-SMD-7.5X5.2-6PIN" 0 350 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 400 60 H V C CNN
$FPLIST
*OSCILLATOR-SMD-7.5X5.2-6PIN*
$ENDFPLIST
DRAW
P 5 1 1 0 -300 -200 -300 200 300 200 300 -200 -300 -200 f
X EN 1 -400 -100 100 R 40 40 1 1 B
X GND 2 400 -100 100 L 40 40 1 1 B
X OUT 3 400 100 100 L 40 40 1 1 B
X VCC 4 -400 100 100 R 40 40 1 1 B
ENDDRAW
ENDDEF
#
# RESONATOR-16MHZSMD_3.2X1.3
#
DEF RESONATOR-16MHZSMD_3.2X1.3 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATOR-16MHZSMD_3.2X1.3" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-3.2X1.3" 0 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-08900" 0 200 60 H V C CNN
$FPLIST
*RESONATOR-SMD-3.2X1.3*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATOR-4MHZSMD-4.5X2
#
DEF RESONATOR-4MHZSMD-4.5X2 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATOR-4MHZSMD-4.5X2" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-4.5X2.0" 0 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-12492" 0 200 60 H V C CNN
$FPLIST
*RESONATOR-SMD-4.5X2.0*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATOR-8MHZSMD_3.2X1.3
#
DEF RESONATOR-8MHZSMD_3.2X1.3 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATOR-8MHZSMD_3.2X1.3" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-3.2X1.3" 0 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XTAL-08895" 0 200 60 H V C CNN
$FPLIST
*RESONATOR-SMD-3.2X1.3*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATORPTH-7.6X3.8
#
DEF RESONATORPTH-7.6X3.8 Y 0 40 N N 1 L N
F0 "Y" 0 100 45 H V L BNN
F1 "RESONATORPTH-7.6X3.8" 0 -400 45 H V L BNN
F2 "RESONATOR-PTH-7.6X3.8" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*RESONATOR-PTH-7.6X3.8*
*RESONATOR-SMD-3.2X1.3*
*RESONATOR-SMD-4.5X2.0*
*RESONATOR-SMD-7.4X3.4*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATORSMD-3.2X1.3
#
DEF RESONATORSMD-3.2X1.3 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATORSMD-3.2X1.3" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-3.2X1.3" 0 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 200 60 H V C CNN
$FPLIST
*RESONATOR-SMD-3.2X1.3*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATORSMD-4.5X2.0
#
DEF RESONATORSMD-4.5X2.0 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATORSMD-4.5X2.0" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-4.5X2.0" 0 200 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 250 60 H V C CNN
$FPLIST
*RESONATOR-SMD-4.5X2.0*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# RESONATORSMD-7.4X3.4
#
DEF RESONATORSMD-7.4X3.4 Y 0 40 N N 1 L N
F0 "Y" -150 50 45 H V L BNN
F1 "RESONATORSMD-7.4X3.4" 50 -300 45 H V L BNN
F2 "RESONATOR-SMD-7.4X3.4" 0 150 20 H I C CNN
F3 "" 0 0 50 H I C CNN
F4 "XXX-00000" 0 200 60 H V C CNN
$FPLIST
*RESONATOR-SMD-7.4X3.4*
$ENDFPLIST
DRAW
P 2 1 0 0 -100 -120 -130 -120 N
P 2 1 0 0 -100 -120 -100 -200 N
P 2 1 0 0 -100 -80 -130 -80 N
P 2 1 0 0 -100 -80 -100 0 N
P 2 1 0 0 -100 0 -40 0 N
P 2 1 0 0 -70 -120 -100 -120 N
P 2 1 0 0 -70 -80 -100 -80 N
P 2 1 0 0 -40 0 -40 -70 N
P 2 1 0 0 -40 70 -40 0 N
P 2 1 0 0 0 -200 -100 -200 N
P 2 1 0 0 0 -200 0 -300 N
P 2 1 0 0 40 0 40 -70 N
P 2 1 0 0 40 0 100 0 N
P 2 1 0 0 40 70 40 0 N
P 2 1 0 0 100 -200 0 -200 N
P 2 1 0 0 100 -120 70 -120 N
P 2 1 0 0 100 -120 100 -200 N
P 2 1 0 0 100 -80 70 -80 N
P 2 1 0 0 100 0 100 -80 N
P 2 1 0 0 130 -120 100 -120 N
P 2 1 0 0 130 -80 100 -80 N
P 5 1 1 0 -15 60 -15 -60 15 -60 15 60 -15 60 f
X 1 1 -150 0 100 R 40 40 1 1 P
X 2 2 0 -300 0 U 40 40 1 1 P
X 3 3 150 0 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
#End Library
| {
"language": "Assembly"
} |