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/* -----------------------------------------------------------------------------------------------------------
Software License for The Fraunhofer FDK AAC Codec Library for Android
© Copyright 1995 - 2013 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
All rights reserved.
1. INTRODUCTION
The Fraunhofer FDK AAC Codec Library for Android ("FDK AAC Codec") is software that implements
the MPEG Advanced Audio Coding ("AAC") encoding and decoding scheme for digital audio.
This FDK AAC Codec software is intended to be used on a wide variety of Android devices.
AAC's HE-AAC and HE-AAC v2 versions are regarded as today's most efficient general perceptual
audio codecs. AAC-ELD is considered the best-performing full-bandwidth communications codec by
independent studies and is widely deployed. AAC has been standardized by ISO and IEC as part
of the MPEG specifications.
Patent licenses for necessary patent claims for the FDK AAC Codec (including those of Fraunhofer)
may be obtained through Via Licensing (www.vialicensing.com) or through the respective patent owners
individually for the purpose of encoding or decoding bit streams in products that are compliant with
the ISO/IEC MPEG audio standards. Please note that most manufacturers of Android devices already license
these patent claims through Via Licensing or directly from the patent owners, and therefore FDK AAC Codec
software may already be covered under those patent licenses when it is used for those licensed purposes only.
Commercially-licensed AAC software libraries, including floating-point versions with enhanced sound quality,
are also available from Fraunhofer. Users are encouraged to check the Fraunhofer website for additional
applications information and documentation.
2. COPYRIGHT LICENSE
Redistribution and use in source and binary forms, with or without modification, are permitted without
payment of copyright license fees provided that you satisfy the following conditions:
You must retain the complete text of this software license in redistributions of the FDK AAC Codec or
your modifications thereto in source code form.
You must retain the complete text of this software license in the documentation and/or other materials
provided with redistributions of the FDK AAC Codec or your modifications thereto in binary form.
You must make available free of charge copies of the complete source code of the FDK AAC Codec and your
modifications thereto to recipients of copies in binary form.
The name of Fraunhofer may not be used to endorse or promote products derived from this library without
prior written permission.
You may not charge copyright license fees for anyone to use, copy or distribute the FDK AAC Codec
software or your modifications thereto.
Your modified versions of the FDK AAC Codec must carry prominent notices stating that you changed the software
and the date of any change. For modified versions of the FDK AAC Codec, the term
"Fraunhofer FDK AAC Codec Library for Android" must be replaced by the term
"Third-Party Modified Version of the Fraunhofer FDK AAC Codec Library for Android."
3. NO PATENT LICENSE
NO EXPRESS OR IMPLIED LICENSES TO ANY PATENT CLAIMS, including without limitation the patents of Fraunhofer,
ARE GRANTED BY THIS SOFTWARE LICENSE. Fraunhofer provides no warranty of patent non-infringement with
respect to this software.
You may use this FDK AAC Codec software or modifications thereto only for purposes that are authorized
by appropriate patent licenses.
4. DISCLAIMER
This FDK AAC Codec software is provided by Fraunhofer on behalf of the copyright holders and contributors
"AS IS" and WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, including but not limited to the implied warranties
of merchantability and fitness for a particular purpose. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE for any direct, indirect, incidental, special, exemplary, or consequential damages,
including but not limited to procurement of substitute goods or services; loss of use, data, or profits,
or business interruption, however caused and on any theory of liability, whether in contract, strict
liability, or tort (including negligence), arising in any way out of the use of this software, even if
advised of the possibility of such damage.
5. CONTACT INFORMATION
Fraunhofer Institute for Integrated Circuits IIS
Attention: Audio and Multimedia Departments - FDK AAC LL
Am Wolfsmantel 33
91058 Erlangen, Germany
www.iis.fraunhofer.de/amm
amm-info@iis.fraunhofer.de
----------------------------------------------------------------------------------------------------------- */
/******************************** Fraunhofer IIS ***************************
Author(s): Arthur Tritthart
Description: (ARM optimised) SBR domain coding
******************************************************************************/
#ifndef INCLUSION_GUARD_CALC_ENV_ARM
#define INCLUSION_GUARD_CALC_ENV_ARM
/*!
\brief Compute maximal value of a complex array (re/im) of a given width
Negative values are temporarily logically or'ed with 0xFFFFFFFF
instead of negating the value, if the sign bit is set.
\param maxVal Preset maximal value
\param reTmp real input signal
\param imTmp imaginary input signal
\return new maximal value
*/
#ifdef FUNCTION_FDK_get_maxval
__asm FIXP_DBL FDK_get_maxval (FIXP_DBL maxVal, FIXP_DBL *reTmp, FIXP_DBL *imTmp, int width )
{
/* Register map:
r0 maxVal
r1 reTmp
r2 imTmp
r3 width
r4 real
r5 imag
*/
PUSH {r4-r5}
MOVS r3, r3, ASR #1
ADC r3, r3, #0
BCS FDK_get_maxval_loop_2nd_part
BEQ FDK_get_maxval_loop_end
FDK_get_maxval_loop
LDR r4, [r1], #4
LDR r5, [r2], #4
EOR r4, r4, r4, ASR #31
EOR r5, r5, r5, ASR #31
ORR r0, r0, r4
ORR r0, r0, r5
FDK_get_maxval_loop_2nd_part
LDR r4, [r1], #4
LDR r5, [r2], #4
EOR r4, r4, r4, ASR #31
EOR r5, r5, r5, ASR #31
ORR r0, r0, r4
ORR r0, r0, r5
SUBS r3, r3, #1
BNE FDK_get_maxval_loop
FDK_get_maxval_loop_end
POP {r4-r5}
BX lr
}
#endif /* FUNCTION_FDK_get_maxval */
#endif /* INCLUSION_GUARD_CALC_ENV_ARM */
| {
"language": "Assembly"
} |
@
@ Copyright 2011-16 ARM Limited and Contributors.
@ All rights reserved.
@
@ Redistribution and use in source and binary forms, with or without
@ modification, are permitted provided that the following conditions are met:
@ * Redistributions of source code must retain the above copyright
@ notice, this list of conditions and the following disclaimer.
@ * Redistributions in binary form must reproduce the above copyright
@ notice, this list of conditions and the following disclaimer in the
@ documentation and/or other materials provided with the distribution.
@ * Neither the name of ARM Limited nor the
@ names of its contributors may be used to endorse or promote products
@ derived from this software without specific prior written permission.
@
@ THIS SOFTWARE IS PROVIDED BY ARM LIMITED AND CONTRIBUTORS "AS IS" AND
@ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
@ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@ DISCLAIMED. IN NO EVENT SHALL ARM LIMITED AND CONTRIBUTORS BE LIABLE FOR ANY
@ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
@ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
@ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
@ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
@
@
@ NE10 Library : math/NE10_normalize.neon.s
@
.text
.syntax unified
.include "NE10header.s"
.balign 4
.global ne10_normalize_vec2f_neon
.thumb
.thumb_func
ne10_normalize_vec2f_neon:
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@
@ arm_result_t ne10_normalize_vec2f(arm_vec2f_t * dst,
@ arm_vec2f_t * src,
@ unsigned int count);
@
@ r0: *dst & the current dst entry's address
@ r1: *src & current src entry's address
@ r2: int count & the number of items in the input array that can be
@ processed in chunks of 4 vectors
@ r3: the number of items that are left to be processed at the end of
@ the input array
@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
and r3, r2, #3 @ r3 = count % 4;
sub r2, r2, r3 @ count = count - r3; This is what's left to be processed after this loop
cbz r2, .L_check_vec2
@ load values for the first iteration
vld2.32 {q0-q1}, [r1]!
subs r2, r2, #4
@ calculate sum of square of the components
vmul.f32 q2, q0, q0
vmla.f32 q2, q1, q1
ble .L_mainloopend_vec2
.L_mainloop_vec2:
@ load the next set of values
vmov.f32 q10, q0
vmov.f32 q11, q1
vld2.32 {q0-q1}, [r1]!
subs r2, r2, #4
@ get reciprocal SQRT of the last vector while loading a new vector
vrsqrte.f32 q3, q2
vmul.f32 q4, q2, q3
vrsqrts.f32 q4, q4, q3
vmul.f32 q4, q3, q4
@ normalize the components
vmul.f32 q3, q10, q4 @ q3 = q0(8) * q4
vmul.f32 q4, q11, q4 @ q4 = q1(9) * q4
vst2.32 {d6,d7,d8,d9}, [r0]!
@ calculate sum of square of the components
vmul.f32 q2, q0, q0
vmla.f32 q2, q1, q1
bgt .L_mainloop_vec2 @ loop if r2 is > r3, if we have at least another 4 vectors (8 floats) to process
.L_mainloopend_vec2:
@ the last iteration for this call
@ get reciprocal SQRT of the last vector
vrsqrte.f32 q3, q2
vmul.f32 q4, q2, q3
vrsqrts.f32 q4, q4, q3
vmul.f32 q4, q3, q4
@ normalize the components
vmul.f32 q3, q0, q4 @ q3 = q0 * q4
vmul.f32 q4, q1, q4 @ q4 = q1 * q4
vst2.32 {d6,d7,d8,d9}, [r0]!
.L_check_vec2:
@ check if anything left to process at the end of the input array
cmp r3, #0
ble .L_return_vec2
.L_secondloop_vec2:
@ process the last few items left in the input array
vld1.f32 d0, [r1]! @ Fill in d0 = { V.x, V.y };
subs r3, r3, #1
@ calculate sum of square of the components
vmul.f32 d1, d0, d0 @ d1= { V.x^2, V.y^2 };
vpadd.f32 d3, d1, d1 @ d3= { V.x^2 + (V.y^2), V.y^2 + (V.x^2) };
@ get reciprocal SQRT of the last vector
vrsqrte.f32 d2, d3
vmul.f32 d1, d3, d2
vrsqrts.f32 d1, d1, d2
vmul.f32 d1, d2, d1
@ normalize the components
vmul.f32 d0, d0, d1
vst1.32 {d0}, [r0]!
bgt .L_secondloop_vec2
.L_return_vec2:
@ return
mov r0, #0
bx lr
.align 2
.global ne10_normalize_vec3f_neon
.thumb
.thumb_func
ne10_normalize_vec3f_neon:
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@
@ arm_result_t ne10_normalize_vec3f(arm_vec3t_t * dst,
@ arm_vec3f_t * src,
@ unsigned int count);
@
@ r0: *dst & the current dst entry's address
@ r1: *src & current src entry's address
@ r2: int count & the number of items in the input array that can be
@ processed in chunks of 4 vectors
@ r3: the number of items that are left to be processed at the end of
@ the input array
@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
and r3, r2, #3 @ r3 = count % 4;
sub r2, r2, r3 @ count = count - r3; This is what's left to be processed after this loop
cmp r2, #0
beq .L_check_vec3
@ load values for the first iteration
vld3.32 {d0, d2, d4}, [r1]!
vld3.32 {d1, d3, d5}, [r1]!
subs r2, r2, #4
@ calculate sum of square of the components
vmul.f32 q3, q0, q0
vmla.f32 q3, q1, q1
vmla.f32 q3, q2, q2
ble .L_mainloopend_vec3
.L_mainloop_vec3:
@ load the next set of values
vmov.f32 q10, q0
vmov.f32 q11, q1
vmov.f32 q12, q2
vld3.32 {d0,d2,d4}, [r1]!
vld3.32 {d1,d3,d5}, [r1]!
subs r2, r2, #4
@ get reciprocal SQRT of the last vector while loading a new vector
vrsqrte.f32 q5, q3
vmul.f32 q4, q3, q5
vrsqrts.f32 q4, q4, q5
vmul.f32 q4, q5, q4
@ normalize the components
vmul.f32 q5, q10, q4
vmul.f32 q6, q11, q4
vmul.f32 q7, q12, q4
vst3.32 {d10, d12, d14}, [r0]!
vst3.32 {d11, d13, d15}, [r0]!
@ calculate sum of square of the components
vmul.f32 q3, q0, q0
vmla.f32 q3, q1, q1
vmla.f32 q3, q2, q2
bgt .L_mainloop_vec3 @ loop if r2 is > r3, if we have at least another 4 vectors (12 floats) to process
.L_mainloopend_vec3:
@ the last iteration for this call
@ get reciprocal SQRT of the last vector
vrsqrte.f32 q5, q3
vmul.f32 q4, q3, q5
vrsqrts.f32 q4, q4, q5
vmul.f32 q4, q5, q4
@ normalize the components
vmul.f32 q5, q0, q4
vmul.f32 q6, q1, q4
vmul.f32 q7, q2, q4
vst3.32 {d10, d12, d14}, [r0]!
vst3.32 {d11, d13, d15}, [r0]!
.L_check_vec3:
@ check if anything left to process at the end of the input array
cmp r3, #0
ble .L_return_vec3
.L_secondloop_vec3:
@ process the last few items left in the input array
vld3.f32 {d0[0], d2[0], d4[0]}, [r1]! @ The values are loaded like so:
@ q0 = { V.x, -, -, - };
@ q1 = { V.y, -, -, - };
@ q2 = { V.z, -, -, - };
subs r3, r3, #1
@ calculate sum of square of the components
vmul.f32 q3, q0, q0 @ V.x^2
vmla.f32 q3, q1, q1 @ V.x^2 + V.y^2
vmla.f32 q3, q2, q2 @ V.x^2 + V.y^2 + V.z^2
@ get reciprocal SQRT of the last vector
vrsqrte.f32 q5, q3
vmul.f32 q4, q3, q5
vrsqrts.f32 q4, q4, q5
vmul.f32 q4, q5, q4
@ normalize the components
vmul.f32 q0, q0, q4
vmul.f32 q1, q1, q4
vmul.f32 q2, q2, q4
vst3.32 {d0[0], d2[0], d4[0]}, [r0]!
bgt .L_secondloop_vec3
.L_return_vec3:
@ return
mov r0, #0
bx lr
.align 2
.global ne10_normalize_vec4f_neon
.thumb
.thumb_func
ne10_normalize_vec4f_neon:
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
@
@ arm_result_t ne10_normalize_vec4f(arm_vec4f_t * dst,
@ arm_vec4f_t * src,
@ unsigned int count);
@
@ r0: *dst & the current dst entry's address
@ r1: *src & current src entry's address
@ r2: int count & the number of items in the input array that can be
@ processed in chunks of 4 vectors
@ r3: the number of items that are left to be processed at the end of
@ the input array
@
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
and r3, r2, #3 @ r3 = count % 4;
sub r2, r2, r3 @ count = count - r3; This is what's left to be processed after this loop
cmp r2, #0
beq .L_check_vec4
@ load values for the first iteration
vld4.32 {d0, d2, d4, d6}, [r1]!
vld4.32 {d1, d3, d5, d7}, [r1]!
subs r2, r2, #4
@ calculate sum of square of the components
vmul.f32 q5, q0, q0
vmla.f32 q5, q1, q1
vmla.f32 q5, q2, q2
vmla.f32 q5, q3, q3
ble .L_mainloopend_vec4
.L_mainloop_vec4:
@ load the next set of values
vmov q10, q0
vmov q11, q1
vmov q12, q2
vmov q13, q3
vld4.32 {d0, d2, d4, d6}, [r1]!
vld4.32 {d1, d3, d5, d7}, [r1]!
subs r2, r2, #4
@ get reciprocal SQRT of the last vector while loading a new vector
vrsqrte.f32 q6, q5
vmul.f32 q4, q5, q6
vrsqrts.f32 q4, q4, q6
vmul.f32 q4, q6, q4
@ normalize the components
vmul.f32 q10, q10, q4
vmul.f32 q11, q11, q4
vmul.f32 q12, q12, q4
vmul.f32 q13, q13, q4
vst4.32 {d20, d22, d24, d26}, [r0]!
vst4.32 {d21, d23, d25, d27}, [r0]!
@ calculate sum of square of the components
vmul.f32 q5, q0, q0
vmla.f32 q5, q1, q1
vmla.f32 q5, q2, q2
vmla.f32 q5, q3, q3
bgt .L_mainloop_vec4 @ loop if r2 is > r3, if we have at least another 4 vectors (12 floats) to process
.L_mainloopend_vec4:
@ the last iteration for this call
@ get reciprocal SQRT of the last vector
vrsqrte.f32 q6, q5
vmul.f32 q4, q5, q6
vrsqrts.f32 q4, q4, q6
vmul.f32 q4, q6, q4
@ normalize the components
vmul.f32 q0, q0, q4
vmul.f32 q1, q1, q4
vmul.f32 q2, q2, q4
vmul.f32 q3, q3, q4
vst4.32 {d0, d2, d4, d6}, [r0]!
vst4.32 {d1, d3, d5, d7}, [r0]!
.L_check_vec4:
@ check if anything left to process at the end of the input array
cmp r3, #0
ble .L_return_vec4
.L_secondloop_vec4:
@ process the last few items left in the input array
vld4.f32 {d0[0], d2[0], d4[0], d6[0]}, [r1]! @ The values are loaded like so:
@ q0 = { V.x, -, -, - };
@ q1 = { V.y, -, -, - };
@ q2 = { V.z, -, -, - };
subs r3, r3, #1
@ calculate sum of square of the components
vmul.f32 q4, q0, q0 @ V.x^2
vmla.f32 q4, q1, q1 @ V.x^2 + V.y^2
vmla.f32 q4, q2, q2 @ V.x^2 + V.y^2 + V.z^2
vmla.f32 q4, q3, q3 @ V.x^2 + V.y^2 + V.z^2 + V.w^2
@ get reciprocal SQRT of the last vector
vrsqrte.f32 q5, q4
vmul.f32 q6, q4, q5
vrsqrts.f32 q6, q6, q5
vmul.f32 q6, q5, q6
@ normalize the components
vmul.f32 q0, q0, q6
vmul.f32 q1, q1, q6
vmul.f32 q2, q2, q6
vmul.f32 q3, q3, q6
vst4.32 {d0[0], d2[0], d4[0], d6[0]}, [r0]! @ The values are loaded like so:
bgt .L_secondloop_vec4
.L_return_vec4:
@ return
mov r0, #0
bx lr
| {
"language": "Assembly"
} |
# SPDX-License-Identifier: GPL-2.0
config DRM_DW_HDMI
tristate
select DRM_KMS_HELPER
select CEC_CORE if CEC_NOTIFIER
config DRM_DW_HDMI_AHB_AUDIO
tristate "Synopsys Designware AHB Audio interface"
depends on DRM_DW_HDMI && SND
select SND_PCM
select SND_PCM_ELD
select SND_PCM_IEC958
help
Support the AHB Audio interface which is part of the Synopsys
Designware HDMI block. This is used in conjunction with
the i.MX6 HDMI driver.
config DRM_DW_HDMI_I2S_AUDIO
tristate "Synopsys Designware I2S Audio interface"
depends on SND_SOC
depends on DRM_DW_HDMI
select SND_SOC_HDMI_CODEC
help
Support the I2S Audio interface which is part of the Synopsys
Designware HDMI block.
config DRM_DW_HDMI_CEC
tristate "Synopsis Designware CEC interface"
depends on DRM_DW_HDMI
select CEC_CORE
select CEC_NOTIFIER
help
Support the CE interface which is part of the Synopsys
Designware HDMI block.
| {
"language": "Assembly"
} |
/* 32 and 64-bit millicode, original author Hewlett-Packard
adapted for gcc by Paul Bame <bame@debian.org>
and Alan Modra <alan@linuxcare.com.au>.
Copyright (C) 2001-2019 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
.previous
#endif
#ifdef pa64
.level 2.0w
#endif
/* Hardware General Registers. */
r0: .reg %r0
r1: .reg %r1
r2: .reg %r2
r3: .reg %r3
r4: .reg %r4
r5: .reg %r5
r6: .reg %r6
r7: .reg %r7
r8: .reg %r8
r9: .reg %r9
r10: .reg %r10
r11: .reg %r11
r12: .reg %r12
r13: .reg %r13
r14: .reg %r14
r15: .reg %r15
r16: .reg %r16
r17: .reg %r17
r18: .reg %r18
r19: .reg %r19
r20: .reg %r20
r21: .reg %r21
r22: .reg %r22
r23: .reg %r23
r24: .reg %r24
r25: .reg %r25
r26: .reg %r26
r27: .reg %r27
r28: .reg %r28
r29: .reg %r29
r30: .reg %r30
r31: .reg %r31
/* Hardware Space Registers. */
sr0: .reg %sr0
sr1: .reg %sr1
sr2: .reg %sr2
sr3: .reg %sr3
sr4: .reg %sr4
sr5: .reg %sr5
sr6: .reg %sr6
sr7: .reg %sr7
/* Hardware Floating Point Registers. */
fr0: .reg %fr0
fr1: .reg %fr1
fr2: .reg %fr2
fr3: .reg %fr3
fr4: .reg %fr4
fr5: .reg %fr5
fr6: .reg %fr6
fr7: .reg %fr7
fr8: .reg %fr8
fr9: .reg %fr9
fr10: .reg %fr10
fr11: .reg %fr11
fr12: .reg %fr12
fr13: .reg %fr13
fr14: .reg %fr14
fr15: .reg %fr15
/* Hardware Control Registers. */
cr11: .reg %cr11
sar: .reg %cr11 /* Shift Amount Register */
/* Software Architecture General Registers. */
rp: .reg r2 /* return pointer */
#ifdef pa64
mrp: .reg r2 /* millicode return pointer */
#else
mrp: .reg r31 /* millicode return pointer */
#endif
ret0: .reg r28 /* return value */
ret1: .reg r29 /* return value (high part of double) */
sp: .reg r30 /* stack pointer */
dp: .reg r27 /* data pointer */
arg0: .reg r26 /* argument */
arg1: .reg r25 /* argument or high part of double argument */
arg2: .reg r24 /* argument */
arg3: .reg r23 /* argument or high part of double argument */
/* Software Architecture Space Registers. */
/* sr0 ; return link from BLE */
sret: .reg sr1 /* return value */
sarg: .reg sr1 /* argument */
/* sr4 ; PC SPACE tracker */
/* sr5 ; process private data */
/* Frame Offsets (millicode convention!) Used when calling other
millicode routines. Stack unwinding is dependent upon these
definitions. */
r31_slot: .equ -20 /* "current RP" slot */
sr0_slot: .equ -16 /* "static link" slot */
#if defined(pa64)
mrp_slot: .equ -16 /* "current RP" slot */
psp_slot: .equ -8 /* "previous SP" slot */
#else
mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
#endif
#define DEFINE(name,value)name: .EQU value
#define RDEFINE(name,value)name: .REG value
#ifdef milliext
#define MILLI_BE(lbl) BE lbl(sr7,r0)
#define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
#define MILLI_BLE(lbl) BLE lbl(sr7,r0)
#define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
#define MILLIRETN BE,n 0(sr0,mrp)
#define MILLIRET BE 0(sr0,mrp)
#define MILLI_RETN BE,n 0(sr0,mrp)
#define MILLI_RET BE 0(sr0,mrp)
#else
#define MILLI_BE(lbl) B lbl
#define MILLI_BEN(lbl) B,n lbl
#define MILLI_BLE(lbl) BL lbl,mrp
#define MILLI_BLEN(lbl) BL,n lbl,mrp
#define MILLIRETN BV,n 0(mrp)
#define MILLIRET BV 0(mrp)
#define MILLI_RETN BV,n 0(mrp)
#define MILLI_RET BV 0(mrp)
#endif
#ifdef __STDC__
#define CAT(a,b) a##b
#else
#define CAT(a,b) a/**/b
#endif
#ifdef ELF
#define SUBSPA_MILLI .section .text
#define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
#define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
#define ATTR_MILLI
#define SUBSPA_DATA .section .data
#define ATTR_DATA
#define GLOBAL $global$
#define GSYM(sym) !sym:
#define LSYM(sym) !CAT(.L,sym:)
#define LREF(sym) CAT(.L,sym)
#else
#ifdef coff
/* This used to be .milli but since link32 places different named
sections in different segments millicode ends up a long ways away
from .text (1meg?). This way they will be a lot closer.
The SUBSPA_MILLI_* specify locality sets for certain millicode
modules in order to ensure that modules that call one another are
placed close together. Without locality sets this is unlikely to
happen because of the Dynamite linker library search algorithm. We
want these modules close together so that short calls always reach
(we don't want to require long calls or use long call stubs). */
#define SUBSPA_MILLI .subspa .text
#define SUBSPA_MILLI_DIV .subspa .text$dv,align=16
#define SUBSPA_MILLI_MUL .subspa .text$mu,align=16
#define ATTR_MILLI .attr code,read,execute
#define SUBSPA_DATA .subspa .data
#define ATTR_DATA .attr init_data,read,write
#define GLOBAL _gp
#else
#define SUBSPA_MILLI .subspa $MILLICODE$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=8
#define SUBSPA_MILLI_DIV SUBSPA_MILLI
#define SUBSPA_MILLI_MUL SUBSPA_MILLI
#define ATTR_MILLI
#define SUBSPA_DATA .subspa $BSS$,quad=1,align=8,access=0x1f,sort=80,zero
#define ATTR_DATA
#define GLOBAL $global$
#endif
#define SPACE_DATA .space $PRIVATE$,spnum=1,sort=16
#define GSYM(sym) !sym
#define LSYM(sym) !CAT(L$,sym)
#define LREF(sym) CAT(L$,sym)
#endif
#ifdef L_dyncall
SUBSPA_MILLI
ATTR_DATA
GSYM($$dyncall)
.export $$dyncall,millicode
.proc
.callinfo millicode
.entry
bb,>=,n %r22,30,LREF(1) ; branch if not plabel address
depi 0,31,2,%r22 ; clear the two least significant bits
ldw 4(%r22),%r19 ; load new LTP value
ldw 0(%r22),%r22 ; load address of target
LSYM(1)
#ifdef LINUX
bv %r0(%r22) ; branch to the real target
#else
ldsid (%sr0,%r22),%r1 ; get the "space ident" selected by r22
mtsp %r1,%sr0 ; move that space identifier into sr0
be 0(%sr0,%r22) ; branch to the real target
#endif
stw %r2,-24(%r30) ; save return address into frame marker
.exit
.procend
#endif
#ifdef L_divI
/* ROUTINES: $$divI, $$divoI
Single precision divide for signed binary integers.
The quotient is truncated towards zero.
The sign of the quotient is the XOR of the signs of the dividend and
divisor.
Divide by zero is trapped.
Divide of -2**31 by -1 is trapped for $$divoI but not for $$divI.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions:
. divisor is zero (traps with ADDIT,= 0,25,0)
. dividend==-2**31 and divisor==-1 and routine is $$divoI
. (traps with ADDO 26,25,0)
. Changes memory at the following places:
. NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Branchs to other millicode routines using BE
. $$div_# for # being 2,3,4,5,6,7,8,9,10,12,14,15
.
. For selected divisors, calls a divide by constant routine written by
. Karl Pettis. Eligible divisors are 1..15 excluding 11 and 13.
.
. The only overflow case is -2**31 divided by -1.
. Both routines return -2**31 but only $$divoI traps. */
RDEFINE(temp,r1)
RDEFINE(retreg,ret1) /* r29 */
RDEFINE(temp1,arg0)
SUBSPA_MILLI_DIV
ATTR_MILLI
.import $$divI_2,millicode
.import $$divI_3,millicode
.import $$divI_4,millicode
.import $$divI_5,millicode
.import $$divI_6,millicode
.import $$divI_7,millicode
.import $$divI_8,millicode
.import $$divI_9,millicode
.import $$divI_10,millicode
.import $$divI_12,millicode
.import $$divI_14,millicode
.import $$divI_15,millicode
.export $$divI,millicode
.export $$divoI,millicode
.proc
.callinfo millicode
.entry
GSYM($$divoI)
comib,=,n -1,arg1,LREF(negative1) /* when divisor == -1 */
GSYM($$divI)
ldo -1(arg1),temp /* is there at most one bit set ? */
and,<> arg1,temp,r0 /* if not, don't use power of 2 divide */
addi,> 0,arg1,r0 /* if divisor > 0, use power of 2 divide */
b,n LREF(neg_denom)
LSYM(pow2)
addi,>= 0,arg0,retreg /* if numerator is negative, add the */
add arg0,temp,retreg /* (denominaotr -1) to correct for shifts */
extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
extrs retreg,15,16,retreg /* retreg = retreg >> 16 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
ldi 0xcc,temp1 /* setup 0xcc in temp1 */
extru,= arg1,23,8,temp /* test denominator with 0xff00 */
extrs retreg,23,24,retreg /* retreg = retreg >> 8 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
ldi 0xaa,temp /* setup 0xaa in temp */
extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
extrs retreg,27,28,retreg /* retreg = retreg >> 4 */
and,= arg1,temp1,r0 /* test denominator with 0xcc */
extrs retreg,29,30,retreg /* retreg = retreg >> 2 */
and,= arg1,temp,r0 /* test denominator with 0xaa */
extrs retreg,30,31,retreg /* retreg = retreg >> 1 */
MILLIRETN
LSYM(neg_denom)
addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power of 2 */
b,n LREF(regular_seq)
sub r0,arg1,temp /* make denominator positive */
comb,=,n arg1,temp,LREF(regular_seq) /* test against 0x80000000 and 0 */
ldo -1(temp),retreg /* is there at most one bit set ? */
and,= temp,retreg,r0 /* if so, the denominator is power of 2 */
b,n LREF(regular_seq)
sub r0,arg0,retreg /* negate numerator */
comb,=,n arg0,retreg,LREF(regular_seq) /* test against 0x80000000 */
copy retreg,arg0 /* set up arg0, arg1 and temp */
copy temp,arg1 /* before branching to pow2 */
b LREF(pow2)
ldo -1(arg1),temp
LSYM(regular_seq)
comib,>>=,n 15,arg1,LREF(small_divisor)
add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
LSYM(normal)
subi 0,retreg,retreg /* make it positive */
sub 0,arg1,temp /* clear carry, */
/* negate the divisor */
ds 0,temp,0 /* set V-bit to the comple- */
/* ment of the divisor sign */
add retreg,retreg,retreg /* shift msb bit into carry */
ds r0,arg1,temp /* 1st divide step, if no carry */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 32nd divide step, */
addc retreg,retreg,retreg /* shift last retreg bit into retreg */
xor,>= arg0,arg1,0 /* get correct sign of quotient */
sub 0,retreg,retreg /* based on operand signs */
MILLIRETN
nop
LSYM(small_divisor)
#if defined(pa64)
/* Clear the upper 32 bits of the arg1 register. We are working with */
/* small divisors (and 32-bit integers) We must not be mislead */
/* by "1" bits left in the upper 32 bits. */
depd %r0,31,32,%r25
#endif
blr,n arg1,r0
nop
/* table for divisor == 0,1, ... ,15 */
addit,= 0,arg1,r0 /* trap if divisor == 0 */
nop
MILLIRET /* divisor == 1 */
copy arg0,retreg
MILLI_BEN($$divI_2) /* divisor == 2 */
nop
MILLI_BEN($$divI_3) /* divisor == 3 */
nop
MILLI_BEN($$divI_4) /* divisor == 4 */
nop
MILLI_BEN($$divI_5) /* divisor == 5 */
nop
MILLI_BEN($$divI_6) /* divisor == 6 */
nop
MILLI_BEN($$divI_7) /* divisor == 7 */
nop
MILLI_BEN($$divI_8) /* divisor == 8 */
nop
MILLI_BEN($$divI_9) /* divisor == 9 */
nop
MILLI_BEN($$divI_10) /* divisor == 10 */
nop
b LREF(normal) /* divisor == 11 */
add,>= 0,arg0,retreg
MILLI_BEN($$divI_12) /* divisor == 12 */
nop
b LREF(normal) /* divisor == 13 */
add,>= 0,arg0,retreg
MILLI_BEN($$divI_14) /* divisor == 14 */
nop
MILLI_BEN($$divI_15) /* divisor == 15 */
nop
LSYM(negative1)
sub 0,arg0,retreg /* result is negation of dividend */
MILLIRET
addo arg0,arg1,r0 /* trap iff dividend==0x80000000 && divisor==-1 */
.exit
.procend
.end
#endif
#ifdef L_divU
/* ROUTINE: $$divU
.
. Single precision divide for unsigned integers.
.
. Quotient is truncated towards zero.
. Traps on divide by zero.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions:
. divisor is zero
. Changes memory at the following places:
. NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Branchs to other millicode routines using BE:
. $$divU_# for 3,5,6,7,9,10,12,14,15
.
. For selected small divisors calls the special divide by constant
. routines written by Karl Pettis. These are: 3,5,6,7,9,10,12,14,15. */
RDEFINE(temp,r1)
RDEFINE(retreg,ret1) /* r29 */
RDEFINE(temp1,arg0)
SUBSPA_MILLI_DIV
ATTR_MILLI
.export $$divU,millicode
.import $$divU_3,millicode
.import $$divU_5,millicode
.import $$divU_6,millicode
.import $$divU_7,millicode
.import $$divU_9,millicode
.import $$divU_10,millicode
.import $$divU_12,millicode
.import $$divU_14,millicode
.import $$divU_15,millicode
.proc
.callinfo millicode
.entry
GSYM($$divU)
/* The subtract is not nullified since it does no harm and can be used
by the two cases that branch back to "normal". */
ldo -1(arg1),temp /* is there at most one bit set ? */
and,= arg1,temp,r0 /* if so, denominator is power of 2 */
b LREF(regular_seq)
addit,= 0,arg1,0 /* trap for zero dvr */
copy arg0,retreg
extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
extru retreg,15,16,retreg /* retreg = retreg >> 16 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
ldi 0xcc,temp1 /* setup 0xcc in temp1 */
extru,= arg1,23,8,temp /* test denominator with 0xff00 */
extru retreg,23,24,retreg /* retreg = retreg >> 8 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
ldi 0xaa,temp /* setup 0xaa in temp */
extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
extru retreg,27,28,retreg /* retreg = retreg >> 4 */
and,= arg1,temp1,r0 /* test denominator with 0xcc */
extru retreg,29,30,retreg /* retreg = retreg >> 2 */
and,= arg1,temp,r0 /* test denominator with 0xaa */
extru retreg,30,31,retreg /* retreg = retreg >> 1 */
MILLIRETN
nop
LSYM(regular_seq)
comib,>= 15,arg1,LREF(special_divisor)
subi 0,arg1,temp /* clear carry, negate the divisor */
ds r0,temp,r0 /* set V-bit to 1 */
LSYM(normal)
add arg0,arg0,retreg /* shift msb bit into carry */
ds r0,arg1,temp /* 1st divide step, if no carry */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 32nd divide step, */
MILLIRET
addc retreg,retreg,retreg /* shift last retreg bit into retreg */
/* Handle the cases where divisor is a small constant or has high bit on. */
LSYM(special_divisor)
/* blr arg1,r0 */
/* comib,>,n 0,arg1,LREF(big_divisor) ; nullify previous instruction */
/* Pratap 8/13/90. The 815 Stirling chip set has a bug that prevents us from
generating such a blr, comib sequence. A problem in nullification. So I
rewrote this code. */
#if defined(pa64)
/* Clear the upper 32 bits of the arg1 register. We are working with
small divisors (and 32-bit unsigned integers) We must not be mislead
by "1" bits left in the upper 32 bits. */
depd %r0,31,32,%r25
#endif
comib,> 0,arg1,LREF(big_divisor)
nop
blr arg1,r0
nop
LSYM(zero_divisor) /* this label is here to provide external visibility */
addit,= 0,arg1,0 /* trap for zero dvr */
nop
MILLIRET /* divisor == 1 */
copy arg0,retreg
MILLIRET /* divisor == 2 */
extru arg0,30,31,retreg
MILLI_BEN($$divU_3) /* divisor == 3 */
nop
MILLIRET /* divisor == 4 */
extru arg0,29,30,retreg
MILLI_BEN($$divU_5) /* divisor == 5 */
nop
MILLI_BEN($$divU_6) /* divisor == 6 */
nop
MILLI_BEN($$divU_7) /* divisor == 7 */
nop
MILLIRET /* divisor == 8 */
extru arg0,28,29,retreg
MILLI_BEN($$divU_9) /* divisor == 9 */
nop
MILLI_BEN($$divU_10) /* divisor == 10 */
nop
b LREF(normal) /* divisor == 11 */
ds r0,temp,r0 /* set V-bit to 1 */
MILLI_BEN($$divU_12) /* divisor == 12 */
nop
b LREF(normal) /* divisor == 13 */
ds r0,temp,r0 /* set V-bit to 1 */
MILLI_BEN($$divU_14) /* divisor == 14 */
nop
MILLI_BEN($$divU_15) /* divisor == 15 */
nop
/* Handle the case where the high bit is on in the divisor.
Compute: if( dividend>=divisor) quotient=1; else quotient=0;
Note: dividend>==divisor iff dividend-divisor does not borrow
and not borrow iff carry. */
LSYM(big_divisor)
sub arg0,arg1,r0
MILLIRET
addc r0,r0,retreg
.exit
.procend
.end
#endif
#ifdef L_remI
/* ROUTINE: $$remI
DESCRIPTION:
. $$remI returns the remainder of the division of two signed 32-bit
. integers. The sign of the remainder is the same as the sign of
. the dividend.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = destroyed
. arg1 = destroyed
. ret1 = remainder
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: DIVIDE BY ZERO
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable
. Does not create a stack frame
. Is usable for internal or external microcode
DISCUSSION:
. Calls other millicode routines via mrp: NONE
. Calls other millicode routines: NONE */
RDEFINE(tmp,r1)
RDEFINE(retreg,ret1)
SUBSPA_MILLI
ATTR_MILLI
.proc
.callinfo millicode
.entry
GSYM($$remI)
GSYM($$remoI)
.export $$remI,MILLICODE
.export $$remoI,MILLICODE
ldo -1(arg1),tmp /* is there at most one bit set ? */
and,<> arg1,tmp,r0 /* if not, don't use power of 2 */
addi,> 0,arg1,r0 /* if denominator > 0, use power */
/* of 2 */
b,n LREF(neg_denom)
LSYM(pow2)
comb,>,n 0,arg0,LREF(neg_num) /* is numerator < 0 ? */
and arg0,tmp,retreg /* get the result */
MILLIRETN
LSYM(neg_num)
subi 0,arg0,arg0 /* negate numerator */
and arg0,tmp,retreg /* get the result */
subi 0,retreg,retreg /* negate result */
MILLIRETN
LSYM(neg_denom)
addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power */
/* of 2 */
b,n LREF(regular_seq)
sub r0,arg1,tmp /* make denominator positive */
comb,=,n arg1,tmp,LREF(regular_seq) /* test against 0x80000000 and 0 */
ldo -1(tmp),retreg /* is there at most one bit set ? */
and,= tmp,retreg,r0 /* if not, go to regular_seq */
b,n LREF(regular_seq)
comb,>,n 0,arg0,LREF(neg_num_2) /* if arg0 < 0, negate it */
and arg0,retreg,retreg
MILLIRETN
LSYM(neg_num_2)
subi 0,arg0,tmp /* test against 0x80000000 */
and tmp,retreg,retreg
subi 0,retreg,retreg
MILLIRETN
LSYM(regular_seq)
addit,= 0,arg1,0 /* trap if div by zero */
add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
sub 0,retreg,retreg /* make it positive */
sub 0,arg1, tmp /* clear carry, */
/* negate the divisor */
ds 0, tmp,0 /* set V-bit to the comple- */
/* ment of the divisor sign */
or 0,0, tmp /* clear tmp */
add retreg,retreg,retreg /* shift msb bit into carry */
ds tmp,arg1, tmp /* 1st divide step, if no carry */
/* out, msb of quotient = 0 */
addc retreg,retreg,retreg /* shift retreg with/into carry */
LSYM(t1)
ds tmp,arg1, tmp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 32nd divide step, */
addc retreg,retreg,retreg /* shift last bit into retreg */
movb,>=,n tmp,retreg,LREF(finish) /* branch if pos. tmp */
add,< arg1,0,0 /* if arg1 > 0, add arg1 */
add,tr tmp,arg1,retreg /* for correcting remainder tmp */
sub tmp,arg1,retreg /* else add absolute value arg1 */
LSYM(finish)
add,>= arg0,0,0 /* set sign of remainder */
sub 0,retreg,retreg /* to sign of dividend */
MILLIRET
nop
.exit
.procend
#ifdef milliext
.origin 0x00000200
#endif
.end
#endif
#ifdef L_remU
/* ROUTINE: $$remU
. Single precision divide for remainder with unsigned binary integers.
.
. The remainder must be dividend-(dividend/divisor)*divisor.
. Divide by zero is trapped.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = remainder
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: DIVIDE BY ZERO
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Calls other millicode routines using mrp: NONE
. Calls other millicode routines: NONE */
RDEFINE(temp,r1)
RDEFINE(rmndr,ret1) /* r29 */
SUBSPA_MILLI
ATTR_MILLI
.export $$remU,millicode
.proc
.callinfo millicode
.entry
GSYM($$remU)
ldo -1(arg1),temp /* is there at most one bit set ? */
and,= arg1,temp,r0 /* if not, don't use power of 2 */
b LREF(regular_seq)
addit,= 0,arg1,r0 /* trap on div by zero */
and arg0,temp,rmndr /* get the result for power of 2 */
MILLIRETN
LSYM(regular_seq)
comib,>=,n 0,arg1,LREF(special_case)
subi 0,arg1,rmndr /* clear carry, negate the divisor */
ds r0,rmndr,r0 /* set V-bit to 1 */
add arg0,arg0,temp /* shift msb bit into carry */
ds r0,arg1,rmndr /* 1st divide step, if no carry */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 2nd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 3rd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 4th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 5th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 6th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 7th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 8th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 9th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 10th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 11th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 12th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 13th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 14th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 15th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 16th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 17th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 18th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 19th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 20th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 21st divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 22nd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 23rd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 24th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 25th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 26th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 27th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 28th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 29th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 30th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 31st divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 32nd divide step, */
comiclr,<= 0,rmndr,r0
add rmndr,arg1,rmndr /* correction */
MILLIRETN
nop
/* Putting >= on the last DS and deleting COMICLR does not work! */
LSYM(special_case)
sub,>>= arg0,arg1,rmndr
copy arg0,rmndr
MILLIRETN
nop
.exit
.procend
.end
#endif
#ifdef L_div_const
/* ROUTINE: $$divI_2
. $$divI_3 $$divU_3
. $$divI_4
. $$divI_5 $$divU_5
. $$divI_6 $$divU_6
. $$divI_7 $$divU_7
. $$divI_8
. $$divI_9 $$divU_9
. $$divI_10 $$divU_10
.
. $$divI_12 $$divU_12
.
. $$divI_14 $$divU_14
. $$divI_15 $$divU_15
. $$divI_16
. $$divI_17 $$divU_17
.
. Divide by selected constants for single precision binary integers.
INPUT REGISTERS:
. arg0 == dividend
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: NONE
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Calls other millicode routines using mrp: NONE
. Calls other millicode routines: NONE */
/* TRUNCATED DIVISION BY SMALL INTEGERS
We are interested in q(x) = floor(x/y), where x >= 0 and y > 0
(with y fixed).
Let a = floor(z/y), for some choice of z. Note that z will be
chosen so that division by z is cheap.
Let r be the remainder(z/y). In other words, r = z - ay.
Now, our method is to choose a value for b such that
q'(x) = floor((ax+b)/z)
is equal to q(x) over as large a range of x as possible. If the
two are equal over a sufficiently large range, and if it is easy to
form the product (ax), and it is easy to divide by z, then we can
perform the division much faster than the general division algorithm.
So, we want the following to be true:
. For x in the following range:
.
. ky <= x < (k+1)y
.
. implies that
.
. k <= (ax+b)/z < (k+1)
We want to determine b such that this is true for all k in the
range {0..K} for some maximum K.
Since (ax+b) is an increasing function of x, we can take each
bound separately to determine the "best" value for b.
(ax+b)/z < (k+1) implies
(a((k+1)y-1)+b < (k+1)z implies
b < a + (k+1)(z-ay) implies
b < a + (k+1)r
This needs to be true for all k in the range {0..K}. In
particular, it is true for k = 0 and this leads to a maximum
acceptable value for b.
b < a+r or b <= a+r-1
Taking the other bound, we have
k <= (ax+b)/z implies
k <= (aky+b)/z implies
k(z-ay) <= b implies
kr <= b
Clearly, the largest range for k will be achieved by maximizing b,
when r is not zero. When r is zero, then the simplest choice for b
is 0. When r is not 0, set
. b = a+r-1
Now, by construction, q'(x) = floor((ax+b)/z) = q(x) = floor(x/y)
for all x in the range:
. 0 <= x < (K+1)y
We need to determine what K is. Of our two bounds,
. b < a+(k+1)r is satisfied for all k >= 0, by construction.
The other bound is
. kr <= b
This is always true if r = 0. If r is not 0 (the usual case), then
K = floor((a+r-1)/r), is the maximum value for k.
Therefore, the formula q'(x) = floor((ax+b)/z) yields the correct
answer for q(x) = floor(x/y) when x is in the range
(0,(K+1)y-1) K = floor((a+r-1)/r)
To be most useful, we want (K+1)y-1 = (max x) >= 2**32-1 so that
the formula for q'(x) yields the correct value of q(x) for all x
representable by a single word in HPPA.
We are also constrained in that computing the product (ax), adding
b, and dividing by z must all be done quickly, otherwise we will be
better off going through the general algorithm using the DS
instruction, which uses approximately 70 cycles.
For each y, there is a choice of z which satisfies the constraints
for (K+1)y >= 2**32. We may not, however, be able to satisfy the
timing constraints for arbitrary y. It seems that z being equal to
a power of 2 or a power of 2 minus 1 is as good as we can do, since
it minimizes the time to do division by z. We want the choice of z
to also result in a value for (a) that minimizes the computation of
the product (ax). This is best achieved if (a) has a regular bit
pattern (so the multiplication can be done with shifts and adds).
The value of (a) also needs to be less than 2**32 so the product is
always guaranteed to fit in 2 words.
In actual practice, the following should be done:
1) For negative x, you should take the absolute value and remember
. the fact so that the result can be negated. This obviously does
. not apply in the unsigned case.
2) For even y, you should factor out the power of 2 that divides y
. and divide x by it. You can then proceed by dividing by the
. odd factor of y.
Here is a table of some odd values of y, and corresponding choices
for z which are "good".
y z r a (hex) max x (hex)
3 2**32 1 55555555 100000001
5 2**32 1 33333333 100000003
7 2**24-1 0 249249 (infinite)
9 2**24-1 0 1c71c7 (infinite)
11 2**20-1 0 1745d (infinite)
13 2**24-1 0 13b13b (infinite)
15 2**32 1 11111111 10000000d
17 2**32 1 f0f0f0f 10000000f
If r is 1, then b = a+r-1 = a. This simplifies the computation
of (ax+b), since you can compute (x+1)(a) instead. If r is 0,
then b = 0 is ok to use which simplifies (ax+b).
The bit patterns for 55555555, 33333333, and 11111111 are obviously
very regular. The bit patterns for the other values of a above are:
y (hex) (binary)
7 249249 001001001001001001001001 << regular >>
9 1c71c7 000111000111000111000111 << regular >>
11 1745d 000000010111010001011101 << irregular >>
13 13b13b 000100111011000100111011 << irregular >>
The bit patterns for (a) corresponding to (y) of 11 and 13 may be
too irregular to warrant using this method.
When z is a power of 2 minus 1, then the division by z is slightly
more complicated, involving an iterative solution.
The code presented here solves division by 1 through 17, except for
11 and 13. There are algorithms for both signed and unsigned
quantities given.
TIMINGS (cycles)
divisor positive negative unsigned
. 1 2 2 2
. 2 4 4 2
. 3 19 21 19
. 4 4 4 2
. 5 18 22 19
. 6 19 22 19
. 8 4 4 2
. 10 18 19 17
. 12 18 20 18
. 15 16 18 16
. 16 4 4 2
. 17 16 18 16
Now, the algorithm for 7, 9, and 14 is an iterative one. That is,
a loop body is executed until the tentative quotient is 0. The
number of times the loop body is executed varies depending on the
dividend, but is never more than two times. If the dividend is
less than the divisor, then the loop body is not executed at all.
Each iteration adds 4 cycles to the timings.
divisor positive negative unsigned
. 7 19+4n 20+4n 20+4n n = number of iterations
. 9 21+4n 22+4n 21+4n
. 14 21+4n 22+4n 20+4n
To give an idea of how the number of iterations varies, here is a
table of dividend versus number of iterations when dividing by 7.
smallest largest required
dividend dividend iterations
. 0 6 0
. 7 0x6ffffff 1
0x1000006 0xffffffff 2
There is some overlap in the range of numbers requiring 1 and 2
iterations. */
RDEFINE(t2,r1)
RDEFINE(x2,arg0) /* r26 */
RDEFINE(t1,arg1) /* r25 */
RDEFINE(x1,ret1) /* r29 */
SUBSPA_MILLI_DIV
ATTR_MILLI
.proc
.callinfo millicode
.entry
/* NONE of these routines require a stack frame
ALL of these routines are unwindable from millicode */
GSYM($$divide_by_constant)
.export $$divide_by_constant,millicode
/* Provides a "nice" label for the code covered by the unwind descriptor
for things like gprof. */
/* DIVISION BY 2 (shift by 1) */
GSYM($$divI_2)
.export $$divI_2,millicode
comclr,>= arg0,0,0
addi 1,arg0,arg0
MILLIRET
extrs arg0,30,31,ret1
/* DIVISION BY 4 (shift by 2) */
GSYM($$divI_4)
.export $$divI_4,millicode
comclr,>= arg0,0,0
addi 3,arg0,arg0
MILLIRET
extrs arg0,29,30,ret1
/* DIVISION BY 8 (shift by 3) */
GSYM($$divI_8)
.export $$divI_8,millicode
comclr,>= arg0,0,0
addi 7,arg0,arg0
MILLIRET
extrs arg0,28,29,ret1
/* DIVISION BY 16 (shift by 4) */
GSYM($$divI_16)
.export $$divI_16,millicode
comclr,>= arg0,0,0
addi 15,arg0,arg0
MILLIRET
extrs arg0,27,28,ret1
/****************************************************************************
*
* DIVISION BY DIVISORS OF FFFFFFFF, and powers of 2 times these
*
* includes 3,5,15,17 and also 6,10,12
*
****************************************************************************/
/* DIVISION BY 3 (use z = 2**32; a = 55555555) */
GSYM($$divI_3)
.export $$divI_3,millicode
comb,<,N x2,0,LREF(neg3)
addi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,0,x1
LSYM(neg3)
subi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(neg)
addc x1,0,x1
GSYM($$divU_3)
.export $$divU_3,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,30,t1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,t1,x1
/* DIVISION BY 5 (use z = 2**32; a = 33333333) */
GSYM($$divI_5)
.export $$divI_5,millicode
comb,<,N x2,0,LREF(neg5)
addi 3,x2,t1 /* this cannot overflow */
sh1add x2,t1,x2 /* multiply by 3 to get started */
b LREF(pos)
addc 0,0,x1
LSYM(neg5)
sub 0,x2,x2 /* negate x2 */
addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,31,x1 /* get top bit (can be 1) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
b LREF(neg)
addc x1,0,x1
GSYM($$divU_5)
.export $$divU_5,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,31,t1 /* multiply by 3 to get started */
sh1add x2,x2,x2
b LREF(pos)
addc t1,x1,x1
/* DIVISION BY 6 (shift to divide by 2 then divide by 3) */
GSYM($$divI_6)
.export $$divI_6,millicode
comb,<,N x2,0,LREF(neg6)
extru x2,30,31,x2 /* divide by 2 */
addi 5,x2,t1 /* compute 5*(x2+1) = 5*x2+5 */
sh2add x2,t1,x2 /* multiply by 5 to get started */
b LREF(pos)
addc 0,0,x1
LSYM(neg6)
subi 2,x2,x2 /* negate, divide by 2, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,30,31,x2
shd 0,x2,30,x1
sh2add x2,x2,x2 /* multiply by 5 to get started */
b LREF(neg)
addc x1,0,x1
GSYM($$divU_6)
.export $$divU_6,millicode
extru x2,30,31,x2 /* divide by 2 */
addi 1,x2,x2 /* cannot carry */
shd 0,x2,30,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,0,x1
/* DIVISION BY 10 (shift to divide by 2 then divide by 5) */
GSYM($$divU_10)
.export $$divU_10,millicode
extru x2,30,31,x2 /* divide by 2 */
addi 3,x2,t1 /* compute 3*(x2+1) = (3*x2)+3 */
sh1add x2,t1,x2 /* multiply by 3 to get started */
addc 0,0,x1
LSYM(pos)
shd x1,x2,28,t1 /* multiply by 0x11 */
shd x2,0,28,t2
add x2,t2,x2
addc x1,t1,x1
LSYM(pos_for_17)
shd x1,x2,24,t1 /* multiply by 0x101 */
shd x2,0,24,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,16,t1 /* multiply by 0x10001 */
shd x2,0,16,t2
add x2,t2,x2
MILLIRET
addc x1,t1,x1
GSYM($$divI_10)
.export $$divI_10,millicode
comb,< x2,0,LREF(neg10)
copy 0,x1
extru x2,30,31,x2 /* divide by 2 */
addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
LSYM(neg10)
subi 2,x2,x2 /* negate, divide by 2, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,30,31,x2
sh1add x2,x2,x2 /* multiply by 3 to get started */
LSYM(neg)
shd x1,x2,28,t1 /* multiply by 0x11 */
shd x2,0,28,t2
add x2,t2,x2
addc x1,t1,x1
LSYM(neg_for_17)
shd x1,x2,24,t1 /* multiply by 0x101 */
shd x2,0,24,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,16,t1 /* multiply by 0x10001 */
shd x2,0,16,t2
add x2,t2,x2
addc x1,t1,x1
MILLIRET
sub 0,x1,x1
/* DIVISION BY 12 (shift to divide by 4 then divide by 3) */
GSYM($$divI_12)
.export $$divI_12,millicode
comb,< x2,0,LREF(neg12)
copy 0,x1
extru x2,29,30,x2 /* divide by 4 */
addib,tr 1,x2,LREF(pos) /* compute 5*(x2+1) = 5*x2+5 */
sh2add x2,x2,x2 /* multiply by 5 to get started */
LSYM(neg12)
subi 4,x2,x2 /* negate, divide by 4, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,29,30,x2
b LREF(neg)
sh2add x2,x2,x2 /* multiply by 5 to get started */
GSYM($$divU_12)
.export $$divU_12,millicode
extru x2,29,30,x2 /* divide by 4 */
addi 5,x2,t1 /* cannot carry */
sh2add x2,t1,x2 /* multiply by 5 to get started */
b LREF(pos)
addc 0,0,x1
/* DIVISION BY 15 (use z = 2**32; a = 11111111) */
GSYM($$divI_15)
.export $$divI_15,millicode
comb,< x2,0,LREF(neg15)
copy 0,x1
addib,tr 1,x2,LREF(pos)+4
shd x1,x2,28,t1
LSYM(neg15)
b LREF(neg)
subi 1,x2,x2
GSYM($$divU_15)
.export $$divU_15,millicode
addi 1,x2,x2 /* this CAN overflow */
b LREF(pos)
addc 0,0,x1
/* DIVISION BY 17 (use z = 2**32; a = f0f0f0f) */
GSYM($$divI_17)
.export $$divI_17,millicode
comb,<,n x2,0,LREF(neg17)
addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
b LREF(pos_for_17)
subb t1,0,x1
LSYM(neg17)
subi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
b LREF(neg_for_17)
subb t1,0,x1
GSYM($$divU_17)
.export $$divU_17,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,28,t1 /* multiply by 0xf to get started */
LSYM(u17)
shd x2,0,28,t2
sub t2,x2,x2
b LREF(pos_for_17)
subb t1,x1,x1
/* DIVISION BY DIVISORS OF FFFFFF, and powers of 2 times these
includes 7,9 and also 14
z = 2**24-1
r = z mod x = 0
so choose b = 0
Also, in order to divide by z = 2**24-1, we approximate by dividing
by (z+1) = 2**24 (which is easy), and then correcting.
(ax) = (z+1)q' + r
. = zq' + (q'+r)
So to compute (ax)/z, compute q' = (ax)/(z+1) and r = (ax) mod (z+1)
Then the true remainder of (ax)/z is (q'+r). Repeat the process
with this new remainder, adding the tentative quotients together,
until a tentative quotient is 0 (and then we are done). There is
one last correction to be done. It is possible that (q'+r) = z.
If so, then (q'+r)/(z+1) = 0 and it looks like we are done. But,
in fact, we need to add 1 more to the quotient. Now, it turns
out that this happens if and only if the original value x is
an exact multiple of y. So, to avoid a three instruction test at
the end, instead use 1 instruction to add 1 to x at the beginning. */
/* DIVISION BY 7 (use z = 2**24-1; a = 249249) */
GSYM($$divI_7)
.export $$divI_7,millicode
comb,<,n x2,0,LREF(neg7)
LSYM(7)
addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,x1
sh3add x2,x2,x2
addc x1,0,x1
LSYM(pos7)
shd x1,x2,26,t1
shd x2,0,26,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,20,t1
shd x2,0,20,t2
add x2,t2,x2
addc x1,t1,t1
/* computed <t1,x2>. Now divide it by (2**24 - 1) */
copy 0,x1
shd,= t1,x2,24,t1 /* tentative quotient */
LSYM(1)
addb,tr t1,x1,LREF(2) /* add to previous quotient */
extru x2,31,24,x2 /* new remainder (unadjusted) */
MILLIRETN
LSYM(2)
addb,tr t1,x2,LREF(1) /* adjust remainder */
extru,= x2,7,8,t1 /* new quotient */
LSYM(neg7)
subi 1,x2,x2 /* negate x2 and add 1 */
LSYM(8)
shd 0,x2,29,x1
sh3add x2,x2,x2
addc x1,0,x1
LSYM(neg7_shift)
shd x1,x2,26,t1
shd x2,0,26,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,20,t1
shd x2,0,20,t2
add x2,t2,x2
addc x1,t1,t1
/* computed <t1,x2>. Now divide it by (2**24 - 1) */
copy 0,x1
shd,= t1,x2,24,t1 /* tentative quotient */
LSYM(3)
addb,tr t1,x1,LREF(4) /* add to previous quotient */
extru x2,31,24,x2 /* new remainder (unadjusted) */
MILLIRET
sub 0,x1,x1 /* negate result */
LSYM(4)
addb,tr t1,x2,LREF(3) /* adjust remainder */
extru,= x2,7,8,t1 /* new quotient */
GSYM($$divU_7)
.export $$divU_7,millicode
addi 1,x2,x2 /* can carry */
addc 0,0,x1
shd x1,x2,29,t1
sh3add x2,x2,x2
b LREF(pos7)
addc t1,x1,x1
/* DIVISION BY 9 (use z = 2**24-1; a = 1c71c7) */
GSYM($$divI_9)
.export $$divI_9,millicode
comb,<,n x2,0,LREF(neg9)
addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(pos7)
subb t1,0,x1
LSYM(neg9)
subi 1,x2,x2 /* negate and add 1 */
shd 0,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(neg7_shift)
subb t1,0,x1
GSYM($$divU_9)
.export $$divU_9,millicode
addi 1,x2,x2 /* can carry */
addc 0,0,x1
shd x1,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(pos7)
subb t1,x1,x1
/* DIVISION BY 14 (shift to divide by 2 then divide by 7) */
GSYM($$divI_14)
.export $$divI_14,millicode
comb,<,n x2,0,LREF(neg14)
GSYM($$divU_14)
.export $$divU_14,millicode
b LREF(7) /* go to 7 case */
extru x2,30,31,x2 /* divide by 2 */
LSYM(neg14)
subi 2,x2,x2 /* negate (and add 2) */
b LREF(8)
extru x2,30,31,x2 /* divide by 2 */
.exit
.procend
.end
#endif
#ifdef L_mulI
/* VERSION "@(#)$$mulI $ Revision: 12.4 $ $ Date: 94/03/17 17:18:51 $" */
/******************************************************************************
This routine is used on PA2.0 processors when gcc -mno-fpregs is used
ROUTINE: $$mulI
DESCRIPTION:
$$mulI multiplies two single word integers, giving a single
word result.
INPUT REGISTERS:
arg0 = Operand 1
arg1 = Operand 2
r31 == return pc
sr0 == return space when called externally
OUTPUT REGISTERS:
arg0 = undefined
arg1 = undefined
ret1 = result
OTHER REGISTERS AFFECTED:
r1 = undefined
SIDE EFFECTS:
Causes a trap under the following conditions: NONE
Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
Unwindable
Does not create a stack frame
Is usable for internal or external microcode
DISCUSSION:
Calls other millicode routines via mrp: NONE
Calls other millicode routines: NONE
***************************************************************************/
#define a0 %arg0
#define a1 %arg1
#define t0 %r1
#define r %ret1
#define a0__128a0 zdep a0,24,25,a0
#define a0__256a0 zdep a0,23,24,a0
#define a1_ne_0_b_l0 comb,<> a1,0,LREF(l0)
#define a1_ne_0_b_l1 comb,<> a1,0,LREF(l1)
#define a1_ne_0_b_l2 comb,<> a1,0,LREF(l2)
#define b_n_ret_t0 b,n LREF(ret_t0)
#define b_e_shift b LREF(e_shift)
#define b_e_t0ma0 b LREF(e_t0ma0)
#define b_e_t0 b LREF(e_t0)
#define b_e_t0a0 b LREF(e_t0a0)
#define b_e_t02a0 b LREF(e_t02a0)
#define b_e_t04a0 b LREF(e_t04a0)
#define b_e_2t0 b LREF(e_2t0)
#define b_e_2t0a0 b LREF(e_2t0a0)
#define b_e_2t04a0 b LREF(e2t04a0)
#define b_e_3t0 b LREF(e_3t0)
#define b_e_4t0 b LREF(e_4t0)
#define b_e_4t0a0 b LREF(e_4t0a0)
#define b_e_4t08a0 b LREF(e4t08a0)
#define b_e_5t0 b LREF(e_5t0)
#define b_e_8t0 b LREF(e_8t0)
#define b_e_8t0a0 b LREF(e_8t0a0)
#define r__r_a0 add r,a0,r
#define r__r_2a0 sh1add a0,r,r
#define r__r_4a0 sh2add a0,r,r
#define r__r_8a0 sh3add a0,r,r
#define r__r_t0 add r,t0,r
#define r__r_2t0 sh1add t0,r,r
#define r__r_4t0 sh2add t0,r,r
#define r__r_8t0 sh3add t0,r,r
#define t0__3a0 sh1add a0,a0,t0
#define t0__4a0 sh2add a0,0,t0
#define t0__5a0 sh2add a0,a0,t0
#define t0__8a0 sh3add a0,0,t0
#define t0__9a0 sh3add a0,a0,t0
#define t0__16a0 zdep a0,27,28,t0
#define t0__32a0 zdep a0,26,27,t0
#define t0__64a0 zdep a0,25,26,t0
#define t0__128a0 zdep a0,24,25,t0
#define t0__t0ma0 sub t0,a0,t0
#define t0__t0_a0 add t0,a0,t0
#define t0__t0_2a0 sh1add a0,t0,t0
#define t0__t0_4a0 sh2add a0,t0,t0
#define t0__t0_8a0 sh3add a0,t0,t0
#define t0__2t0_a0 sh1add t0,a0,t0
#define t0__3t0 sh1add t0,t0,t0
#define t0__4t0 sh2add t0,0,t0
#define t0__4t0_a0 sh2add t0,a0,t0
#define t0__5t0 sh2add t0,t0,t0
#define t0__8t0 sh3add t0,0,t0
#define t0__8t0_a0 sh3add t0,a0,t0
#define t0__9t0 sh3add t0,t0,t0
#define t0__16t0 zdep t0,27,28,t0
#define t0__32t0 zdep t0,26,27,t0
#define t0__256a0 zdep a0,23,24,t0
SUBSPA_MILLI
ATTR_MILLI
.align 16
.proc
.callinfo millicode
.export $$mulI,millicode
GSYM($$mulI)
combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */
copy 0,r /* zero out the result */
xor a0,a1,a0 /* swap a0 & a1 using the */
xor a0,a1,a1 /* old xor trick */
xor a0,a1,a0
LSYM(l4)
combt,<= 0,a0,LREF(l3) /* if a0>=0 then proceed like unsigned */
zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
sub,> 0,a1,t0 /* otherwise negate both and */
combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
sub 0,a0,a1
movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
LSYM(l0) r__r_t0 /* add in this partial product */
LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
extru a1,23,24,a1 /* a1 >>= 8 ****************** */
/*16 insts before this. */
/* a0 <<= 8 ************************** */
LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
LSYM(x2) a1_ne_0_b_l1 ! r__r_2a0 ! MILLIRETN ! nop
LSYM(x3) a1_ne_0_b_l0 ! t0__3a0 ! MILLIRET ! r__r_t0
LSYM(x4) a1_ne_0_b_l1 ! r__r_4a0 ! MILLIRETN ! nop
LSYM(x5) a1_ne_0_b_l0 ! t0__5a0 ! MILLIRET ! r__r_t0
LSYM(x6) t0__3a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x7) t0__3a0 ! a1_ne_0_b_l0 ! r__r_4a0 ! b_n_ret_t0
LSYM(x8) a1_ne_0_b_l1 ! r__r_8a0 ! MILLIRETN ! nop
LSYM(x9) a1_ne_0_b_l0 ! t0__9a0 ! MILLIRET ! r__r_t0
LSYM(x10) t0__5a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x11) t0__3a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
LSYM(x12) t0__3a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x13) t0__5a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
LSYM(x14) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x15) t0__5a0 ! a1_ne_0_b_l0 ! t0__3t0 ! b_n_ret_t0
LSYM(x16) t0__16a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x17) t0__9a0 ! a1_ne_0_b_l0 ! t0__t0_8a0 ! b_n_ret_t0
LSYM(x18) t0__9a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x19) t0__9a0 ! a1_ne_0_b_l0 ! t0__2t0_a0 ! b_n_ret_t0
LSYM(x20) t0__5a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x21) t0__5a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x22) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x23) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x24) t0__3a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x25) t0__5a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
LSYM(x26) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x27) t0__3a0 ! a1_ne_0_b_l0 ! t0__9t0 ! b_n_ret_t0
LSYM(x28) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x29) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x30) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
LSYM(x31) t0__32a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x32) t0__32a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x33) t0__8a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x34) t0__16a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x35) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__t0_8a0
LSYM(x36) t0__9a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x37) t0__9a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x38) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x39) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x40) t0__5a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x41) t0__5a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
LSYM(x42) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x43) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x44) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x45) t0__9a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
LSYM(x46) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_a0
LSYM(x47) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_2a0
LSYM(x48) t0__3a0 ! a1_ne_0_b_l0 ! t0__16t0 ! b_n_ret_t0
LSYM(x49) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_4a0
LSYM(x50) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
LSYM(x51) t0__9a0 ! t0__t0_8a0 ! b_e_t0 ! t0__3t0
LSYM(x52) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x53) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x54) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
LSYM(x55) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x56) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x57) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x58) t0__3a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x59) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__3t0
LSYM(x60) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x61) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x62) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x63) t0__64a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x64) t0__64a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x65) t0__8a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
LSYM(x66) t0__32a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x67) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x68) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x69) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x70) t0__64a0 ! t0__t0_4a0 ! b_e_t0 ! t0__t0_2a0
LSYM(x71) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__t0ma0
LSYM(x72) t0__9a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x73) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_t0
LSYM(x74) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x75) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x76) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x77) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x78) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x79) t0__16a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
LSYM(x80) t0__16a0 ! t0__5t0 ! b_e_shift ! r__r_t0
LSYM(x81) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_t0
LSYM(x82) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x83) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x84) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x85) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x86) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x87) t0__9a0 ! t0__9t0 ! b_e_t02a0 ! t0__t0_4a0
LSYM(x88) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x89) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x90) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
LSYM(x91) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x92) t0__5a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x93) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__3t0
LSYM(x94) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__t0_2a0
LSYM(x95) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x96) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x97) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x98) t0__32a0 ! t0__3t0 ! b_e_t0 ! t0__t0_2a0
LSYM(x99) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x100) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
LSYM(x101) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x102) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
LSYM(x103) t0__5a0 ! t0__5t0 ! b_e_t02a0 ! t0__4t0_a0
LSYM(x104) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x105) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x106) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x107) t0__9a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__8t0_a0
LSYM(x108) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x109) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x110) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x111) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x112) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__16t0
LSYM(x113) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__3t0
LSYM(x114) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x115) t0__9a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x116) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x117) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x118) t0__3a0 ! t0__4t0_a0 ! b_e_t0a0 ! t0__9t0
LSYM(x119) t0__3a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__9t0
LSYM(x120) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x121) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x122) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x123) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x124) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
LSYM(x125) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
LSYM(x126) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x127) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x128) t0__128a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x129) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0_a0 ! b_n_ret_t0
LSYM(x130) t0__64a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x131) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x132) t0__8a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x133) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x134) t0__8a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
LSYM(x136) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x137) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x138) t0__8a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x139) t0__8a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__4t0_a0
LSYM(x140) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__5t0
LSYM(x141) t0__8a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x142) t0__9a0 ! t0__8t0 ! b_e_2t0 ! t0__t0ma0
LSYM(x143) t0__16a0 ! t0__9t0 ! b_e_t0 ! t0__t0ma0
LSYM(x144) t0__9a0 ! t0__8t0 ! b_e_shift ! r__r_2t0
LSYM(x145) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x146) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x147) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x148) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x149) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x150) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x151) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x152) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x153) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x154) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x155) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__5t0
LSYM(x156) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x157) t0__32a0 ! t0__t0ma0 ! b_e_t02a0 ! t0__5t0
LSYM(x158) t0__16a0 ! t0__5t0 ! b_e_2t0 ! t0__t0ma0
LSYM(x159) t0__32a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
LSYM(x160) t0__5a0 ! t0__4t0 ! b_e_shift ! r__r_8t0
LSYM(x161) t0__8a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x162) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_2t0
LSYM(x163) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x164) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x165) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x166) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x167) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x168) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x169) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x170) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__5t0
LSYM(x171) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x172) t0__5a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x173) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__9t0
LSYM(x174) t0__32a0 ! t0__t0_2a0 ! b_e_t04a0 ! t0__5t0
LSYM(x175) t0__8a0 ! t0__2t0_a0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x176) t0__5a0 ! t0__4t0_a0 ! b_e_8t0 ! t0__t0_a0
LSYM(x177) t0__5a0 ! t0__4t0_a0 ! b_e_8t0a0 ! t0__t0_a0
LSYM(x178) t0__5a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__8t0_a0
LSYM(x179) t0__5a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__8t0_a0
LSYM(x180) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
LSYM(x181) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x182) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x183) t0__9a0 ! t0__5t0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x184) t0__5a0 ! t0__9t0 ! b_e_4t0 ! t0__t0_a0
LSYM(x185) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x186) t0__32a0 ! t0__t0ma0 ! b_e_2t0 ! t0__3t0
LSYM(x187) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__5t0
LSYM(x188) t0__9a0 ! t0__5t0 ! b_e_4t0 ! t0__t0_2a0
LSYM(x189) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x190) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__5t0
LSYM(x191) t0__64a0 ! t0__3t0 ! b_e_t0 ! t0__t0ma0
LSYM(x192) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x193) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x194) t0__8a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x195) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x196) t0__8a0 ! t0__3t0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x197) t0__8a0 ! t0__3t0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x198) t0__64a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
LSYM(x199) t0__8a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x200) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_8t0
LSYM(x201) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x202) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x203) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__4t0_a0
LSYM(x204) t0__8a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
LSYM(x205) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x206) t0__64a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__3t0
LSYM(x207) t0__8a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
LSYM(x208) t0__5a0 ! t0__5t0 ! b_e_8t0 ! t0__t0_a0
LSYM(x209) t0__5a0 ! t0__5t0 ! b_e_8t0a0 ! t0__t0_a0
LSYM(x210) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__5t0
LSYM(x211) t0__5a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__5t0
LSYM(x212) t0__3a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x213) t0__3a0 ! t0__4t0_a0 ! b_e_4t0a0 ! t0__4t0_a0
LSYM(x214) t0__9a0 ! t0__t0_4a0 ! b_e_2t04a0 ! t0__8t0_a0
LSYM(x215) t0__5a0 ! t0__4t0_a0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x216) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x217) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x218) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x219) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x220) t0__3a0 ! t0__9t0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x221) t0__3a0 ! t0__9t0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x222) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x223) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x224) t0__9a0 ! t0__3t0 ! b_e_8t0 ! t0__t0_a0
LSYM(x225) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
LSYM(x226) t0__3a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__32t0
LSYM(x227) t0__9a0 ! t0__5t0 ! b_e_t02a0 ! t0__5t0
LSYM(x228) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
LSYM(x229) t0__9a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__3t0
LSYM(x230) t0__9a0 ! t0__5t0 ! b_e_5t0 ! t0__t0_a0
LSYM(x231) t0__9a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
LSYM(x232) t0__3a0 ! t0__2t0_a0 ! b_e_8t0 ! t0__4t0_a0
LSYM(x233) t0__3a0 ! t0__2t0_a0 ! b_e_8t0a0 ! t0__4t0_a0
LSYM(x234) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__9t0
LSYM(x235) t0__3a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__9t0
LSYM(x236) t0__9a0 ! t0__2t0_a0 ! b_e_4t08a0 ! t0__3t0
LSYM(x237) t0__16a0 ! t0__5t0 ! b_e_3t0 ! t0__t0ma0
LSYM(x238) t0__3a0 ! t0__4t0_a0 ! b_e_2t04a0 ! t0__9t0
LSYM(x239) t0__16a0 ! t0__5t0 ! b_e_t0ma0 ! t0__3t0
LSYM(x240) t0__9a0 ! t0__t0_a0 ! b_e_8t0 ! t0__3t0
LSYM(x241) t0__9a0 ! t0__t0_a0 ! b_e_8t0a0 ! t0__3t0
LSYM(x242) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__8t0_a0
LSYM(x243) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__3t0
LSYM(x244) t0__5a0 ! t0__3t0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x245) t0__8a0 ! t0__3t0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x246) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x247) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x248) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_8t0
LSYM(x249) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__8t0_a0
LSYM(x250) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__5t0
LSYM(x251) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__5t0
LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
/*1040 insts before this. */
LSYM(ret_t0) MILLIRET
LSYM(e_t0) r__r_t0
LSYM(e_shift) a1_ne_0_b_l2
a0__256a0 /* a0 <<= 8 *********** */
MILLIRETN
LSYM(e_t0ma0) a1_ne_0_b_l0
t0__t0ma0
MILLIRET
r__r_t0
LSYM(e_t0a0) a1_ne_0_b_l0
t0__t0_a0
MILLIRET
r__r_t0
LSYM(e_t02a0) a1_ne_0_b_l0
t0__t0_2a0
MILLIRET
r__r_t0
LSYM(e_t04a0) a1_ne_0_b_l0
t0__t0_4a0
MILLIRET
r__r_t0
LSYM(e_2t0) a1_ne_0_b_l1
r__r_2t0
MILLIRETN
LSYM(e_2t0a0) a1_ne_0_b_l0
t0__2t0_a0
MILLIRET
r__r_t0
LSYM(e2t04a0) t0__t0_2a0
a1_ne_0_b_l1
r__r_2t0
MILLIRETN
LSYM(e_3t0) a1_ne_0_b_l0
t0__3t0
MILLIRET
r__r_t0
LSYM(e_4t0) a1_ne_0_b_l1
r__r_4t0
MILLIRETN
LSYM(e_4t0a0) a1_ne_0_b_l0
t0__4t0_a0
MILLIRET
r__r_t0
LSYM(e4t08a0) t0__t0_2a0
a1_ne_0_b_l1
r__r_4t0
MILLIRETN
LSYM(e_5t0) a1_ne_0_b_l0
t0__5t0
MILLIRET
r__r_t0
LSYM(e_8t0) a1_ne_0_b_l1
r__r_8t0
MILLIRETN
LSYM(e_8t0a0) a1_ne_0_b_l0
t0__8t0_a0
MILLIRET
r__r_t0
.procend
.end
#endif
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
// RUN: -emit-llvm -o - -O1 %s | \
// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
//
// Check that we generate TBAA metadata for struct copies correctly.
struct A {
short s;
int i;
char c;
int j;
};
typedef A __attribute__((may_alias)) AA;
void copy(A *a1, A *a2) {
// CHECK-LABEL: _Z4copyP1AS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS:!.*]]
// CHECK-NEW-SAME: !tbaa [[TAG_A:![0-9]*]]
*a1 = *a2;
}
struct B {
char c;
A a;
int i;
};
void copy2(B *b1, B *b2) {
// CHECK-LABEL: _Z5copy2P1BS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 24, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS2:!.*]]
// CHECK-NEW-SAME: !tbaa [[TAG_B:![0-9]*]]
*b1 = *b2;
}
struct S {
_Complex char cc;
_Complex int ci;
};
union U {
_Complex int ci;
S s;
};
void copy3(U *u1, U *u2) {
// CHECK-LABEL: _Z5copy3P1US0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 12, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS3:!.*]]
// CHECK-NEW-SAME: !tbaa [[TAG_U:![0-9]*]]
*u1 = *u2;
}
// Make sure that zero-length bitfield works.
struct C {
char a;
int : 0; // Shall not be ignored; see r185018.
char b;
char c;
} __attribute__((ms_struct));
void copy4(C *c1, C *c2) {
// CHECK-LABEL: _Z5copy4P1CS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 3, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS4:!.*]]
// CHECK-NEW-SAME: !tbaa [[TAG_C:![0-9]*]]
*c1 = *c2;
}
struct D {
char a;
int : 0;
char b;
char c;
};
void copy5(D *d1, D *d2) {
// CHECK-LABEL: _Z5copy5P1DS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 6, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS5:!.*]]
// CHECK-NEW-SAME: !tbaa [[TAG_D:![0-9]*]]
*d1 = *d2;
}
void copy6(AA *a1, A *a2) {
// CHECK-LABEL: _Z5copy6P1AS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS]]
// CHECK-NEW-SAME: !tbaa [[TAG_char:![0-9]*]]
*a1 = *a2;
}
void copy7(A *a1, AA *a2) {
// CHECK-LABEL: _Z5copy7P1AS0_
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
// CHECK-OLD-SAME: !tbaa.struct [[TS]]
// CHECK-NEW-SAME: !tbaa [[TAG_char]]
*a1 = *a2;
}
// CHECK-OLD: [[TS]] = !{i64 0, i64 2, !{{.*}}, i64 4, i64 4, !{{.*}}, i64 8, i64 1, !{{.*}}, i64 12, i64 4, !{{.*}}}
// CHECK-OLD: [[CHAR:!.*]] = !{!"omnipotent char", !{{.*}}}
// CHECK-OLD: [[TAG_INT:!.*]] = !{[[INT:!.*]], [[INT]], i64 0}
// CHECK-OLD: [[INT]] = !{!"int", [[CHAR]]
// CHECK-OLD: [[TAG_CHAR:!.*]] = !{[[CHAR]], [[CHAR]], i64 0}
// (offset, size) = (0,1) char; (4,2) short; (8,4) int; (12,1) char; (16,4) int; (20,4) int
// CHECK-OLD: [[TS2]] = !{i64 0, i64 1, !{{.*}}, i64 4, i64 2, !{{.*}}, i64 8, i64 4, !{{.*}}, i64 12, i64 1, !{{.*}}, i64 16, i64 4, {{.*}}, i64 20, i64 4, {{.*}}}
// (offset, size) = (0,8) char; (0,2) char; (4,8) char
// CHECK-OLD: [[TS3]] = !{i64 0, i64 8, !{{.*}}, i64 0, i64 2, !{{.*}}, i64 4, i64 8, !{{.*}}}
// CHECK-OLD: [[TS4]] = !{i64 0, i64 1, [[TAG_CHAR]], i64 1, i64 4, [[TAG_INT]], i64 1, i64 1, [[TAG_CHAR]], i64 2, i64 1, [[TAG_CHAR]]}
// CHECK-OLD: [[TS5]] = !{i64 0, i64 1, [[TAG_CHAR]], i64 4, i64 4, [[TAG_INT]], i64 4, i64 1, [[TAG_CHAR]], i64 5, i64 1, [[TAG_CHAR]]}
// CHECK-NEW-DAG: [[TYPE_char:!.*]] = !{{{.*}}, i64 1, !"omnipotent char"}
// CHECK-NEW-DAG: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 0}
// CHECK-NEW-DAG: [[TYPE_short:!.*]] = !{[[TYPE_char]], i64 2, !"short"}
// CHECK-NEW-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
// CHECK-NEW-DAG: [[TYPE_A:!.*]] = !{[[TYPE_char]], i64 16, !"_ZTS1A", [[TYPE_short]], i64 0, i64 2, [[TYPE_int]], i64 4, i64 4, [[TYPE_char]], i64 8, i64 1, [[TYPE_int]], i64 12, i64 4}
// CHECK-NEW-DAG: [[TAG_A]] = !{[[TYPE_A]], [[TYPE_A]], i64 0, i64 16}
// CHECK-NEW-DAG: [[TYPE_B:!.*]] = !{[[TYPE_char]], i64 24, !"_ZTS1B", [[TYPE_char]], i64 0, i64 1, [[TYPE_A]], i64 4, i64 16, [[TYPE_int]], i64 20, i64 4}
// CHECK-NEW-DAG: [[TAG_B]] = !{[[TYPE_B]], [[TYPE_B]], i64 0, i64 24}
// CHECK-NEW-DAG: [[TAG_U]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 12}
// CHECK-NEW-DAG: [[TYPE_C:!.*]] = !{[[TYPE_char]], i64 3, !"_ZTS1C", [[TYPE_char]], i64 0, i64 1, [[TYPE_int]], i64 1, i64 4, [[TYPE_char]], i64 1, i64 1, [[TYPE_char]], i64 2, i64 1}
// CHECK-NEW-DAG: [[TAG_C]] = !{[[TYPE_C]], [[TYPE_C]], i64 0, i64 3}
// CHECK-NEW-DAG: [[TYPE_D:!.*]] = !{[[TYPE_char]], i64 6, !"_ZTS1D", [[TYPE_char]], i64 0, i64 1, [[TYPE_int]], i64 4, i64 4, [[TYPE_char]], i64 4, i64 1, [[TYPE_char]], i64 5, i64 1}
// CHECK-NEW-DAG: [[TAG_D]] = !{[[TYPE_D]], [[TYPE_D]], i64 0, i64 6}
| {
"language": "Assembly"
} |
W
512
// 0.450000
0x3999999A
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.286465
0x24AADE89
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.095450
0x0C37B31D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.057224
0x07531C7F
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.040825
0x0539BF94
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.031701
0x040ECB11
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.025885
0x03503464
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.021850
0x02CBF773
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.018882
0x026ABCF4
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.016607
0x0220297F
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.014804
0x01E5159B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.013339
0x01B5137C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.012123
0x018D3FAD
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.011097
0x016BA358
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.010219
0x014EDC9A
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.009458
0x0135EB2E
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.008791
0x012010ED
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.008201
0x010CBDC3
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.007675
0x00FB8288
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.007203
0x00EC0818
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.006776
0x00DE092B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.006387
0x00D14DF9
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.006032
0x00C5A91A
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.005705
0x00BAF531
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.005404
0x00B1133B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.005124
0x00A7E942
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.004864
0x009F615F
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.004621
0x009768F4
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.004393
0x008FF017
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.004178
0x0088E914
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003976
0x00824810
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003785
0x007C02BA
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003603
0x0076100E
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003430
0x0070681E
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003266
0x006B03EC
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.003109
0x0065DD47
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002958
0x0060EEA9
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002814
0x005C3326
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002675
0x0057A653
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002541
0x00534438
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002412
0x004F093C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002287
0x004AF221
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002166
0x0046FBF2
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.002049
0x004323FC
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001935
0x003F67C8
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001824
0x003BC513
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001716
0x003839C7
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001610
0x0034C3F7
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001507
0x003161D9
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001406
0x002E11C6
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001307
0x002AD230
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001209
0x0027A1A4
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001114
0x00247EC5
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.001020
0x0021684A
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000927
0x001E5CFC
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000835
0x001B5BB4
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000744
0x00186356
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000655
0x001572D5
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000566
0x0012892D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000477
0x000FA563
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000390
0x000CC683
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000303
0x0009EBA1
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000216
0x000713D5
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000129
0x00043E3A
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// 0.000043
0x000169EE
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000043
0xFFFE9612
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000129
0xFFFBC1C6
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000216
0xFFF8EC2B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000303
0xFFF6145F
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000390
0xFFF3397D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000477
0xFFF05A9D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000566
0xFFED76D3
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000655
0xFFEA8D2B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000744
0xFFE79CAA
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000835
0xFFE4A44C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.000927
0xFFE1A304
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001020
0xFFDE97B6
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001114
0xFFDB813B
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001209
0xFFD85E5C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001307
0xFFD52DD0
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001406
0xFFD1EE3A
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001507
0xFFCE9E27
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001610
0xFFCB3C09
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001716
0xFFC7C639
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001824
0xFFC43AED
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.001935
0xFFC09838
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002049
0xFFBCDC04
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002166
0xFFB9040E
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002287
0xFFB50DDF
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002412
0xFFB0F6C4
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002541
0xFFACBBC8
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002675
0xFFA859AD
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002814
0xFFA3CCDA
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.002958
0xFF9F1157
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003109
0xFF9A22B9
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003266
0xFF94FC14
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003430
0xFF8F97E2
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003603
0xFF89EFF2
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003785
0xFF83FD46
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.003976
0xFF7DB7F0
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.004178
0xFF7716EC
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.004393
0xFF700FE9
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.004621
0xFF68970C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.004864
0xFF609EA1
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.005124
0xFF5816BE
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.005404
0xFF4EECC5
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.005705
0xFF450ACF
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.006032
0xFF3A56E6
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.006387
0xFF2EB207
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.006776
0xFF21F6D5
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.007203
0xFF13F7E8
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.007675
0xFF047D78
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.008201
0xFEF3423D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.008791
0xFEDFEF13
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.009458
0xFECA14D2
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.010219
0xFEB12366
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.011097
0xFE945CA8
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.012123
0xFE72C053
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.013339
0xFE4AEC84
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.014804
0xFE1AEA65
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.016607
0xFDDFD681
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.018882
0xFD95430C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.021850
0xFD34088D
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.025885
0xFCAFCB9C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.031701
0xFBF134EF
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.040825
0xFAC6406C
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.057224
0xF8ACE381
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.095450
0xF3C84CE3
// 0.000000
0x00000000
// 0.000000
0x00000000
// -0.003516
0xFF8CCCCD
// -0.286465
0xDB552177
| {
"language": "Assembly"
} |
/** @file
AsmReadGdtr function
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "BaseLibInternals.h"
/**
Reads the current Global Descriptor Table Register(GDTR) descriptor.
Reads and returns the current GDTR descriptor and returns it in Gdtr. This
function is only available on IA-32 and x64.
@param Gdtr The pointer to a GDTR descriptor.
**/
VOID
EFIAPI
InternalX86ReadGdtr (
OUT IA32_DESCRIPTOR *Gdtr
)
{
_asm {
mov eax, Gdtr
sgdt fword ptr [eax]
}
}
| {
"language": "Assembly"
} |
// Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
#include "const_amd64.h"
// func square(out, in *[5]uint64)
TEXT ·square(SB),7,$0-16
MOVQ out+0(FP), DI
MOVQ in+8(FP), SI
MOVQ 0(SI),AX
MULQ 0(SI)
MOVQ AX,CX
MOVQ DX,R8
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 8(SI)
MOVQ AX,R9
MOVQ DX,R10
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 16(SI)
MOVQ AX,R11
MOVQ DX,R12
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 24(SI)
MOVQ AX,R13
MOVQ DX,R14
MOVQ 0(SI),AX
SHLQ $1,AX
MULQ 32(SI)
MOVQ AX,R15
MOVQ DX,BX
MOVQ 8(SI),AX
MULQ 8(SI)
ADDQ AX,R11
ADCQ DX,R12
MOVQ 8(SI),AX
SHLQ $1,AX
MULQ 16(SI)
ADDQ AX,R13
ADCQ DX,R14
MOVQ 8(SI),AX
SHLQ $1,AX
MULQ 24(SI)
ADDQ AX,R15
ADCQ DX,BX
MOVQ 8(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,CX
ADCQ DX,R8
MOVQ 16(SI),AX
MULQ 16(SI)
ADDQ AX,R15
ADCQ DX,BX
MOVQ 16(SI),DX
IMUL3Q $38,DX,AX
MULQ 24(SI)
ADDQ AX,CX
ADCQ DX,R8
MOVQ 16(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,R9
ADCQ DX,R10
MOVQ 24(SI),DX
IMUL3Q $19,DX,AX
MULQ 24(SI)
ADDQ AX,R9
ADCQ DX,R10
MOVQ 24(SI),DX
IMUL3Q $38,DX,AX
MULQ 32(SI)
ADDQ AX,R11
ADCQ DX,R12
MOVQ 32(SI),DX
IMUL3Q $19,DX,AX
MULQ 32(SI)
ADDQ AX,R13
ADCQ DX,R14
MOVQ $REDMASK51,SI
SHLQ $13,R8:CX
ANDQ SI,CX
SHLQ $13,R10:R9
ANDQ SI,R9
ADDQ R8,R9
SHLQ $13,R12:R11
ANDQ SI,R11
ADDQ R10,R11
SHLQ $13,R14:R13
ANDQ SI,R13
ADDQ R12,R13
SHLQ $13,BX:R15
ANDQ SI,R15
ADDQ R14,R15
IMUL3Q $19,BX,DX
ADDQ DX,CX
MOVQ CX,DX
SHRQ $51,DX
ADDQ R9,DX
ANDQ SI,CX
MOVQ DX,R8
SHRQ $51,DX
ADDQ R11,DX
ANDQ SI,R8
MOVQ DX,R9
SHRQ $51,DX
ADDQ R13,DX
ANDQ SI,R9
MOVQ DX,AX
SHRQ $51,DX
ADDQ R15,DX
ANDQ SI,AX
MOVQ DX,R10
SHRQ $51,DX
IMUL3Q $19,DX,DX
ADDQ DX,CX
ANDQ SI,R10
MOVQ CX,0(DI)
MOVQ R8,8(DI)
MOVQ R9,16(DI)
MOVQ AX,24(DI)
MOVQ R10,32(DI)
RET
| {
"language": "Assembly"
} |
/*************************************************************************/
/* */
/* Cepstral, LLC */
/* Copyright (c) 2001 */
/* All Rights Reserved. */
/* */
/* Permission is hereby granted, free of charge, to use and distribute */
/* this software and its documentation without restriction, including */
/* without limitation the rights to use, copy, modify, merge, publish, */
/* distribute, sublicense, and/or sell copies of this work, and to */
/* permit persons to whom this work is furnished to do so, subject to */
/* the following conditions: */
/* 1. The code must retain the above copyright notice, this list of */
/* conditions and the following disclaimer. */
/* 2. Any modifications must be clearly marked as such. */
/* 3. Original authors' names are not deleted. */
/* 4. The authors' names are not used to endorse or promote products */
/* derived from this software without specific prior written */
/* permission. */
/* */
/* CEPSTRAL, LLC AND THE CONTRIBUTORS TO THIS WORK DISCLAIM ALL */
/* WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED */
/* WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL */
/* CEPSTRAL, LLC NOR THE CONTRIBUTORS BE LIABLE FOR ANY SPECIAL, */
/* INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER */
/* RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION */
/* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR */
/* IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
/* */
/*************************************************************************/
/* Author: David Huggins-Daines (dhd@cepstral.com) */
/* Date: December 2001 */
/*************************************************************************/
/* */
/* FliteCMUKalDiphone.h: instantiation of Flite SAPI for cmu_us_kal */
/* */
/*************************************************************************/
#ifndef __FLITECMUKALDIPHONEOBJ_H_
#define __FLITECMUKALDIPHONEOBJ_H_
#include "resource.h"
#include "FliteTTSEngineObj.h"
#include "flite_sapi_usenglish.h"
extern "C" {
#include "voxdefs.h"
cst_voice *REGISTER_VOX(const char *voxdir);
void UNREGISTER_VOX(cst_voice *vox);
};
class ATL_NO_VTABLE CFliteCMUKalDiphoneObj :
public CComCoClass<CFliteCMUKalDiphoneObj, &CLSID_FliteCMUKalDiphoneObj>,
public CFliteTTSEngineObj
{
public:
DECLARE_REGISTRY_RESOURCEID(IDR_FLITECMUKALDIPHONEOBJ)
BEGIN_COM_MAP(CFliteCMUKalDiphoneObj)
COM_INTERFACE_ENTRY(ISpTTSEngine)
COM_INTERFACE_ENTRY(ISpObjectWithToken)
END_COM_MAP()
public:
CFliteCMUKalDiphoneObj() {
regfunc = REGISTER_VOX;
unregfunc = UNREGISTER_VOX;
phonemefunc = flite_sapi_usenglish_phoneme;
visemefunc = flite_sapi_usenglish_viseme;
featurefunc = flite_sapi_usenglish_feature;
pronouncefunc = flite_sapi_usenglish_pronounce;
}
~CFliteCMUKalDiphoneObj() {}
};
#endif //__FLITECMUKALDIPHONEOBJ_H_
| {
"language": "Assembly"
} |
;borders - can be found in asm.asm at the tmp work area (size 8K = 1024 rows)
ALIGN 4
polysides dw 0
polyxy dw 16 dup(0,0);
poly PROC NEAR
mov ax,cs
mov ds,ax
mov ax,cs:starvram
mov es,ax
jmp polyf
poly ENDP
;*** POLYF / POLYFT
ALIGN 4
borders dw 4096 dup(0)
feax dd 0
fedx dd 0
fleftaddl dd 0 ;+0
fleftaddh dw 0 ;+4
fleftrown dw 0 ;+6
fleftzb dd 0 ;+8
fleftze dd 0 ;+12
flefttx0 dw 0 ;+16
fleftty0 dw 0 ;+18
flefttxa dw 0 ;+20
flefttya dw 0 ;+22
fleftcnt dw 0 ;+24
fleftcnta dw 0 ;+26
fleftd3a dw 0 ;+28
frightaddl dd 0 ;+0
frightaddh dw 0 ;+4
frightrown dw 0 ;+6
frightzb dd 0 ;+8
frightze dd 0 ;+12
frighttx0 dw 0 ;+16
frightty0 dw 0 ;+18
frighttxa dw 0 ;+20
frighttya dw 0 ;+22
frightcnt dw 0 ;+24
frightcnta dw 0 ;+26
frightd3a dw 0 ;+28
finfolen dw 0
finfo0 dw 0
finfo1 dw 0
fwmaxy1 dw 0
wminx dw 0
wmaxx dw 319
wminy dw 0+100h
wmaxy dw 399+100h
finfo dw 32 dup(0,0,0,0,0,0,0,0)
;x,y,zlo,zhi,tx,ty,0,0
polyf PROC NEAR ;ONLY CONVEX POLYGONS - FAST?
;input: polysides/polyxy
;requirements:
;es=vram
;cpolysides>=4 (not checked)
;color=set
;**COPY/SEEK UPPERMOST**
mov ax,cs
mov gs,ax
mov ds,ax
mov cx,ds:polysides
mov ax,cx
shl ax,4 ;*16
mov ds:finfolen,ax
add ax,OFFSET finfo
mov ds:finfo1,ax
mov ax,gs:wmaxy
inc ax
mov ds:fwmaxy1,ax
mov edx,077770000h
xor bx,bx
mov si,OFFSET polyxy
mov di,OFFSET finfo
mov ds:finfo0,di
pfn1: mov eax,dword ptr ds:[si]
cmp eax,edx
jg pfn2
mov edx,eax
mov bx,di
pfn2: mov dword ptr ds:[di],eax
add si,4
add di,16
loop pfn1
;[bx]=uppermost
;**SETUP REGS**
mov ds:fleftrown,-32767
mov ds:frightrown,-32767
mov si,bx
mov di,bx
mov bp,ds:[si+2]
mov bx,OFFSET borders
mov ax,bp
cmp ax,gs:wminy
jge pfn35
mov ax,gs:wminy
pfn35: mov gs:[bx],ax
add bx,2
mov cx,16 ;max tmp count to avoid hanging on illegal polygons
;eax=left
;bx=pointer to borders[]
;cx=count
;edx=right
;si=left
;di=right
;bp=y
pfn63: push cx
push bx
cmp bp,ds:fleftrown
jl pfn42
push edx
push di
mov di,si
sub di,16
cmp di,ds:finfo0
jae pfn41
add di,ds:finfolen
pfn41: mov bx,OFFSET fleftaddl
call polyfcalc
add cx,bp
mov ds:fleftrown,cx
movzx eax,word ptr ds:[si+0]
mov ebx,ds:fleftaddl
mov dx,ds:fleftaddh
sar dx,1
rcr ebx,1
xor bx,bx
sub eax,ebx
sbb ax,dx
mov si,di
pop di
pop edx
pfn42:
cmp bp,ds:frightrown
jl pfn52
push eax
push si
mov si,di
add di,16
cmp di,ds:finfo1
jb pfn51
sub di,ds:finfolen
pfn51: mov bx,OFFSET frightaddl
call polyfcalc
add cx,bp
mov ds:frightrown,cx
movzx edx,word ptr ds:[si+0]
mov ebx,ds:frightaddl
mov ax,ds:frightaddh
sar ax,1
rcr ebx,1
xor bx,bx
sub edx,ebx
sbb dx,ax
pop si
pop eax
pfn52: mov bx,ds:fleftrown
mov cx,ds:frightrown
cmp cx,bx
jl pfn61
mov cx,bx
pfn61: sub cx,bp
pop bx
cmp cx,0
jg pfn71
pfn6: pop cx
cmp bp,ds:fwmaxy1
jg pfn64
cmp si,di
je pfn64
dec cx
jz pfn64
jmp pfn63
pfn64: mov word ptr gs:[bx],-32767
mov si,OFFSET borders
call polyn_disp
ret
pfn65: ;above screen
;entering screen, cut.
add bp,cx
push bp
push cx
cmp bp,gs:wminy
jl pfn66
sub bp,cx
mov cx,gs:wminy
sub cx,bp
pfn66: ;
movsx ecx,cx
ror eax,16
mov ds:feax,eax
ror edx,16
mov ds:fedx,edx
;
mov ax,ds:fleftaddh
shl eax,16
mov ax,word ptr ds:fleftaddl[2]
imul ecx
add ds:feax,eax
;
mov ax,ds:frightaddh
shl eax,16
mov ax,word ptr ds:frightaddl[2]
imul ecx
add ds:fedx,eax
;
mov eax,ds:feax
ror eax,16
mov edx,ds:fedx
ror edx,16
mov bp,cx
pop cx
sub cx,bp
pop bp
cmp cx,0
jne pfn6b
jmp pfn6
pfn6b: mov bp,gs:wminy
pfn71: ;process segment
cmp bp,gs:wminy
jl pfn65 ;above screen still
add bp,cx
;clip max to maxy
cmp bp,ds:fwmaxy1
jle pfn72
sub bp,cx
mov cx,ds:fwmaxy1
sub cx,bp
mov bp,ds:fwmaxy1
pfn72: cmp cx,0
jle pfn6
push si
push di
push bp
ror ebx,16
neg cx
mov bx,cx
ror ebx,16
mov esi,ds:fleftaddl
mov edi,ds:frightaddl
mov bp,ds:fleftaddh
mov cx,ds:frightaddh
pfn7: add eax,esi
adc ax,bp
add edx,edi
adc dx,cx
mov gs:[bx],ax
mov gs:[bx+2],dx
add ebx,10004h
jnc pfn7
pop bp
pop di
pop si
jmp pfn6
polyfcalc: ;**** subroutine ****
;calc slope for line [SI]->[DI] to [BX], returns CX=len
mov cx,ds:[di+2]
sub cx,bp ;ds:[si+2]
jle pfc1
mov ax,ds:[di+0]
sub ax,ds:[si+0]
jl pfc2
xor dx,dx
div cx
mov ds:[bx+4],ax
xor ax,ax
div cx
mov ds:[bx+2],ax
;dec cx
ret
pfc1: xor cx,cx
ret
pfc2: neg ax
xor dx,dx
div cx
push ax
xor ax,ax
div cx
pop dx
neg ax
adc dx,0
neg dx
mov ds:[bx+4],dx
mov ds:[bx+2],ax
;dec cx
ret
polyf ENDP
polyn_disp PROC NEAR
;calc/load regs
mov si,OFFSET borders
mov bx,ds:[si]
add si,2
plnd3: ;draw hlines
push cx
push bx
mov ax,ds:[si]
cmp ax,-32767
je polyn_dispx
mov dx,ds:[si+2]
call hline1 ;must not change DS:SI!
pop bx
pop cx
inc bx
add si,8
jmp plnd3
polyn_dispx:
pop bx
pop cx
mov dx,3ceh
mov ax,0ff08h
out dx,ax
ret
polyn_disp ENDP
ALIGN 4
leftside db 11111111b,01111111b,00111111b,00011111b,00001111b,00000111b,00000011b,00000001b
rightside db 10000000b,11000000b,11100000b,11110000b,11111000b,11111100b,11111110b,11111111b
ALIGN 4
hline1 PROC NEAR
;DS:SI must be preserved!
;(ax,bx)-(dx,bx)
sub bx,256
cmp bx,199
ja hlixx
cmp ax,dx
jl hli1
xchg ax,dx
hli1: inc dx
dec dx
cmp dx,ax
jg hli21
hlixx: ret
hli21: cmp ax,0
jnl hli2
cmp dx,0
jl hli0
xor ax,ax
hli2: cmp dx,cs:wmaxx
jng hliok
cmp ax,cs:wmaxx
jg hli0
mov dx,cs:wmaxx
hliok: mov di,ax
sar di,3
mov cx,dx
sar cx,3
sub cx,di
shl bx,1
add di,ds:rows[bx]
mov bp,7
and bp,ax
mov bl,ds:leftside[bp]
mov bp,7
and bp,dx
mov bh,ds:rightside[bp]
cmp cx,0
je hli30
mov dx,3ceh
mov al,8
mov ah,bl
out dx,ax
mov ah,es:[di]
mov byte ptr es:[di],255
inc di
dec cx
jcxz hli33
mov ah,0ffh
out dx,ax
mov ax,0ffffh
test di,1
jz hli32
mov es:[di],al
inc di
dec cx
hli32: shr cx,1
rep stosw
adc cx,cx
rep stosb
hli33: mov dx,3ceh
mov al,8
mov ah,bh
out dx,ax
mov ah,es:[di]
mov byte ptr es:[di],255
hli0: ret
hli30: ;end and beg in same byte
mov dx,3ceh
mov al,8
mov ah,bh
and ah,bl
out dx,ax
mov al,es:[di]
mov byte ptr es:[di],255
ret
hline1 ENDP
| {
"language": "Assembly"
} |
glabel func_8096ACFC
/* 0122C 8096ACFC 27BDFFD8 */ addiu $sp, $sp, 0xFFD8 ## $sp = FFFFFFD8
/* 01230 8096AD00 AFBF0024 */ sw $ra, 0x0024($sp)
/* 01234 8096AD04 AFA40028 */ sw $a0, 0x0028($sp)
/* 01238 8096AD08 90AE1D6C */ lbu $t6, 0x1D6C($a1) ## 00001D6C
/* 0123C 8096AD0C 51C0001D */ beql $t6, $zero, .L8096AD84
/* 01240 8096AD10 8FBF0024 */ lw $ra, 0x0024($sp)
/* 01244 8096AD14 8CA21D94 */ lw $v0, 0x1D94($a1) ## 00001D94
/* 01248 8096AD18 5040001A */ beql $v0, $zero, .L8096AD84
/* 0124C 8096AD1C 8FBF0024 */ lw $ra, 0x0024($sp)
/* 01250 8096AD20 944F0000 */ lhu $t7, 0x0000($v0) ## 00000000
/* 01254 8096AD24 24010004 */ addiu $at, $zero, 0x0004 ## $at = 00000004
/* 01258 8096AD28 3C040600 */ lui $a0, 0x0600 ## $a0 = 06000000
/* 0125C 8096AD2C 51E10015 */ beql $t7, $at, .L8096AD84
/* 01260 8096AD30 8FBF0024 */ lw $ra, 0x0024($sp)
/* 01264 8096AD34 0C028800 */ jal SkelAnime_GetFrameCount
/* 01268 8096AD38 24841D70 */ addiu $a0, $a0, 0x1D70 ## $a0 = 06001D70
/* 0126C 8096AD3C 44822000 */ mtc1 $v0, $f4 ## $f4 = 0.00
/* 01270 8096AD40 44800000 */ mtc1 $zero, $f0 ## $f0 = 0.00
/* 01274 8096AD44 8FA40028 */ lw $a0, 0x0028($sp)
/* 01278 8096AD48 468021A0 */ cvt.s.w $f6, $f4
/* 0127C 8096AD4C 3C050600 */ lui $a1, 0x0600 ## $a1 = 06000000
/* 01280 8096AD50 24180002 */ addiu $t8, $zero, 0x0002 ## $t8 = 00000002
/* 01284 8096AD54 44070000 */ mfc1 $a3, $f0
/* 01288 8096AD58 AFB80014 */ sw $t8, 0x0014($sp)
/* 0128C 8096AD5C 24A51D70 */ addiu $a1, $a1, 0x1D70 ## $a1 = 06001D70
/* 01290 8096AD60 E7A60010 */ swc1 $f6, 0x0010($sp)
/* 01294 8096AD64 3C063F80 */ lui $a2, 0x3F80 ## $a2 = 3F800000
/* 01298 8096AD68 2484014C */ addiu $a0, $a0, 0x014C ## $a0 = 0000014C
/* 0129C 8096AD6C 0C029468 */ jal SkelAnime_ChangeAnimation
/* 012A0 8096AD70 E7A00018 */ swc1 $f0, 0x0018($sp)
/* 012A4 8096AD74 8FA80028 */ lw $t0, 0x0028($sp)
/* 012A8 8096AD78 2419000F */ addiu $t9, $zero, 0x000F ## $t9 = 0000000F
/* 012AC 8096AD7C AD190198 */ sw $t9, 0x0198($t0) ## 00000198
/* 012B0 8096AD80 8FBF0024 */ lw $ra, 0x0024($sp)
.L8096AD84:
/* 012B4 8096AD84 27BD0028 */ addiu $sp, $sp, 0x0028 ## $sp = 00000000
/* 012B8 8096AD88 03E00008 */ jr $ra
/* 012BC 8096AD8C 00000000 */ nop
| {
"language": "Assembly"
} |
// TR1 cstdarg -*- C++ -*-
// Copyright (C) 2006-2013 Free Software Foundation, Inc.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the
// Free Software Foundation; either version 3, or (at your option)
// any later version.
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// Under Section 7 of GPL version 3, you are granted additional
// permissions described in the GCC Runtime Library Exception, version
// 3.1, as published by the Free Software Foundation.
// You should have received a copy of the GNU General Public License and
// a copy of the GCC Runtime Library Exception along with this program;
// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
// <http://www.gnu.org/licenses/>.
/** @file tr1/cstdarg
* This is a TR1 C++ Library header.
*/
#ifndef _GLIBCXX_TR1_CSTDARG
#define _GLIBCXX_TR1_CSTDARG 1
#include <cstdarg>
#endif // _GLIBCXX_TR1_CSTDARG
| {
"language": "Assembly"
} |
StartChar: v.LATmedi
Encoding: 66003 -1 1561
Width: 527
VWidth: 0
Flags: HMW
LayerCount: 3
Fore
SplineSet
432 415 m 1
434 415 l 2
443 415 451 405 446 397 c 0
442 390 438 342 438 326 c 2
438 114 l 2
438 73 440 45 456 45 c 0
466 45 492 46 502 48 c 0
507 49 517 47 517 35 c 0
517 24 508 21 503 21 c 0
451 14 415 -1 386 -13 c 0
382 -15 368 -19 362 -19 c 0
358 -19 359 -18 359 -15 c 0
359 -2 364 34 364 51 c 2
364 57 l 1
312 6 261 -14 199 -14 c 0
134 -14 85 27 85 105 c 2
85 308 l 2
85 337 72 353 42 365 c 0
39 366 29 370 29 380 c 0
29 393 39 396 44 397 c 0
98 399 108 405 147 414 c 1
157 415 162 410 161 400 c 0
157 369 155 353 155 323 c 2
155 128 l 2
155 80 196 37 239 37 c 0
273 37 298 38 323 57 c 0
338 68 368 91 368 132 c 2
368 315 l 2
368 356 323 364 303 365 c 0
298 365 280 368 280 382 c 0
280 394 299 397 303 397 c 0
404 402 396 405 432 415 c 1
EndSplineSet
Validated: 1
EndChar
| {
"language": "Assembly"
} |
// RUN: clspv -constant-args-ubo -inline-entry-points -cluster-pod-kernel-args %s -o %t.spv -pod-ubo
// RUN: clspv-reflection %t.spv -o %t2.map
// RUN: FileCheck -check-prefix=MAP %s < %t2.map
// RUN: spirv-val --target-env vulkan1.0 %t.spv
typedef struct {
int x __attribute__((aligned(16)));
} data_type;
__constant data_type c_var[2] = {{0}, {1}};
__kernel void foo(__global data_type *data, __constant data_type *c_arg,
int n) {
data[n].x = c_arg[n].x + c_var[n].x;
}
// Just checking that the argument names are recorded correctly when clustering pod args.
// MAP: kernel,foo,arg,data,argOrdinal,0,descriptorSet,0,binding,0,offset,0,argKind,buffer
// MAP-NEXT: kernel,foo,arg,c_arg,argOrdinal,1,descriptorSet,0,binding,1,offset,0,argKind,buffer_ubo
// MAP-NEXT: kernel,foo,arg,n,argOrdinal,2,descriptorSet,0,binding,2,offset,0,argKind,pod_ubo
| {
"language": "Assembly"
} |
dnl x86-64 mpn_popcount.
dnl Copyright 2007, 2011 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
MULFUNC_PROLOGUE(mpn_popcount)
include_mpn(`x86/pentium4/sse2/popcount.asm')
| {
"language": "Assembly"
} |
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
; RUN: verify-uselistorder %s
; Basic smoke test for half type.
; CHECK: define half @halftest
define half @halftest(half %A0) {
; CHECK: ret half %A0
ret half %A0
}
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBSHAIRPLAY
bool "libshairplay"
depends on BR2_INET_IPV6
depends on BR2_TOOLCHAIN_HAS_THREADS
depends on BR2_USE_MMU # avahi
depends on !BR2_PREFER_STATIC_LIB # avahi
select BR2_PACKAGE_AVAHI
select BR2_PACKAGE_AVAHI_DAEMON
select BR2_PACKAGE_AVAHI_LIBDNSSD_COMPATIBILITY # runtime
help
libshairplay is a client library that emulates an airplay
server.
https://github.com/juhovh/shairplay
comment "libshairplay needs a toolchain w/ IPv6, threads, dynamic library"
depends on BR2_USE_MMU
depends on !BR2_INET_IPV6 || !BR2_TOOLCHAIN_HAS_THREADS || BR2_PREFER_STATIC_LIB
| {
"language": "Assembly"
} |
// This file is UTF8 encoded
// Spelling to phoneme rules for Azerbaijani
// Stress rule: Right-most vowel, but stop before the vowel which is
// marked as unstressed [%].
.L02 ı a o u // back vowels
.L03 i e ö ü
.group a
a a
ai (K aI
-) a (_ a
.group b
b b
.group c
c dZ
.group ç
ç tS
.group d
d d
-) dan (_ d%an
-) dən (_ d%&n
-) dək (_ d%&k
.group e
e e
.group ə
ə &
@) ə (_ %&
-) ə (_ %&
.group f
f f
.group g
g J
.group ğ
ğ Q
A) ğ :
a) ğa :
o) ğo :
u) ğu :
ö) ğö :
ü) ğü :
i) ğ j
e) ğ j
.group h
h h
.group x
x x
.group ı
ı @
.group i
i i
@) iya (_ =i;a
.group j
j Z
.group k
k c
k (K C
.group q
q g
q (_ x
.group l
l l
l (L02 L
L02) l (K L
.group m
m m
.group n
n n
.group o
o o
.group ö
ö W
.group p
p p
.group r
r R
A) r (A *
ğ) r (A *
C) r (_ @-r
.group s
s s
.group ş
ş S
.group t
t t
L03) t (L03 ts
.group u
u u
.group ü
ü y
.group v
v v
.group w
w w
.group y
y j
.group z
z z
.group
ä &
| {
"language": "Assembly"
} |
SUMMARY="X.Org X11 library"
DESCRIPTION="The X.Org project provides an open source implementation of the \
X Window System. \
The development work is being done in conjunction with the freedesktop.org \
community. \
The X.Org Foundation is the educational non-profit corporation whose \
Board serves this effort, and whose Members lead this work."
HOMEPAGE="https://www.x.org/"
# TODO: sort & merge
COPYRIGHT="2003-2006,2008 Jamey Sharp, Josh Triplett
2009 Red Hat, Inc.
1990-1992,1999,2000,2004,2009,2010 Oracle and/or its affiliates.
1984-1994, 1998 The Open Group
1985, 1986, 1987, 1988, 1989, 1990, 1991, 1994, 1996 X Consortium
2000 The XFree86 Project, Inc.
1985, 1986, 1987, 1988, 1989, 1990, 1991, 1993 Digital Equipment Corporation
1990, 1991 by Tektronix, Inc.
1999-2000 Free Software Foundation, Inc.
1990, 1991 Tektronix, Inc.
1990, 1991, 1992, 1993, 1994, 1995 FUJITSU LIMITED
1992 by Oki Technosystems Laboratory, Inc.
1992 by Fuji Xerox Co., Ltd.
1995 David E. Wexelblat
1990, 1991 by OMRON Corporation
1993 Digital Equipment Corporation, Maynard, Massachusetts,
1994 Sony Corporation
1991 the Open Software Foundation
1993, 1994 Sony Corporation
1993, 1995 Silicon Graphics Computer Systems, Inc.
1992, 1993 by FUJITSU LIMITED
1993 Fujitsu Open Systems Solutions, Inc.
1994 Sony Corporation
1987, 1988, 1990, 1993 by Digital Equipment Corporation, Maynard, Massachusetts,
1993 SunSoft, Inc.
1999-2000 by Bruno Haible
1991 the Open Software Foundation
1993 the TOSHIBA Corp
1988 Wyse Technology, Inc., San Jose, Ca.
1991 the Open Software Foundation
1993, 1994 the Sony Corporation
1992, 1993 FUJITSU LIMITED
1993 Fujitsu Open Systems Solutions, Inc.
1993, 1994 Sony Corporation
1986, 1998 The Open Group
2000 The XFree86 Project, Inc.
1990, 1991 OMRON Corporation, NTT Software Corporation, and Nippon Telegraph and Telephone Corporation
1991 the Open Software Foundation
1993 the FUJITSU LIMITED
1988 Wyse Technology, Inc., San Jose, Ca,
1987 Digital Equipment Corporation, Maynard, Massachusetts
1991, 1992 Fuji Xerox Co., Ltd.
1992, 1993, 1994 FUJITSU LIMITED
2006 Josh Triplett
1996 Sebastien Marineau and Holger Veit
1990, 1991 OMRON Corporation, NTT Software Corporation, and Nippon Telegraph and Telephone Corporation
1991 the Open Software Foundation
1993 the TOSHIBA Corp.
1993, 1994 Sony Corporation
1993, 1994 the FUJITSU LIMITED
2000 Bruno Haible
2003 Keith Packard
2007-2009 Troy D. Hanson
1992, 1993 TOSHIBA Corp.
1993 IBM Corporation
1990, 1991 OMRON Corporation, NTT Software Corporation, and Nippon Telegraph and Telephone Corporation
"
# TODO: check all the licenses in the COPYING file in the next century.
LICENSE="MIT"
REVISION="1"
SOURCE_URI="https://www.x.org/releases/individual/lib/libX11-$portVersion.tar.bz2"
CHECKSUM_SHA256="9cc7e8d000d6193fa5af580d50d689380b8287052270f5bb26a5fb6b58b2bed1"
SOURCE_DIR="libX11-$portVersion"
# TODO: fix the remaining xmlto conversions
PATCHES="libx11-$portVersion.patchset"
ARCHITECTURES="x86_gcc2 x86 x86_64"
SECONDARY_ARCHITECTURES="x86_gcc2 x86"
# TODO: patch to detect libnetwork
PROVIDES="
libx11$secondaryArchSuffix = $portVersion
lib:libX11$secondaryArchSuffix = 6.3.0 compat >= 6
lib:libX11_xcb$secondaryArchSuffix = 1.0.0 compat >= 1
"
REQUIRES="
haiku$secondaryArchSuffix
lib:libXcb$secondaryArchSuffix
"
PROVIDES_devel="
libx11${secondaryArchSuffix}_devel = $portVersion
devel:libX11$secondaryArchSuffix = 6.3.0 compat >= 6
devel:libX11_xcb$secondaryArchSuffix = 1.0.0 compat >= 1
"
REQUIRES_devel="
libx11$secondaryArchSuffix == $portVersion base
devel:kbproto
devel:libXcb$secondaryArchSuffix
devel:xproto
"
BUILD_REQUIRES="
haiku${secondaryArchSuffix}_devel
docbook_xml_dtd
docbook_xsl_stylesheets
devel:libXcb$secondaryArchSuffix
devel:util_macros
devel:xorg_sgml_doctools
devel:xtrans
"
BUILD_PREREQUIRES="
cmd:autoconf
cmd:gcc$secondaryArchSuffix
cmd:libtoolize$secondaryArchSuffix
cmd:make
cmd:pkg_config$secondaryArchSuffix
cmd:xmlto
cmd:xsltproc
"
defineDebugInfoPackage libx11$secondaryArchSuffix \
"$libDir"/libX11.so.6.3.0 \
"$libDir"/libX11-xcb.so.1.0.0
BUILD()
{
export CPPFLAGS="-D_BSD_SOURCE"
export LDFLAGS="-lnetwork"
autoreconf -vfi
# --disable-selective-werror else makekeys does not even reach main()
runConfigure --omit-dirs docDir ./configure \
--docdir=$developDocDir \
--disable-selective-werror \
--enable-static=no \
--enable-unix-transport \
--enable-loadable-i18n \
--enable-xlocaledir
make $jobArgs
}
INSTALL()
{
make install-strip
rm -f $libDir/lib*.la
rm -f $libDir/X11/locale/common/*.la
prepareInstalledDevelLibs \
libX11 \
libX11-xcb
fixPkgconfig
if [ -n "$secondaryArchSuffix" ]; then
rm -rf $manDir
maybe_manDir_man3=
else
maybe_manDir_man3=$manDir/man3
fi
packageEntries devel \
$developDir \
$maybe_manDir_man3
}
TEST()
{
make check
}
| {
"language": "Assembly"
} |
glabel func_80B3C7D4
/* 005F4 80B3C7D4 8C820260 */ lw $v0, 0x0260($a0) ## 00000260
/* 005F8 80B3C7D8 2401000B */ addiu $at, $zero, 0x000B ## $at = 0000000B
/* 005FC 80B3C7DC 10A20006 */ beq $a1, $v0, .L80B3C7F8
/* 00600 80B3C7E0 00000000 */ nop
/* 00604 80B3C7E4 54410004 */ bnel $v0, $at, .L80B3C7F8
/* 00608 80B3C7E8 AC870260 */ sw $a3, 0x0260($a0) ## 00000260
/* 0060C 80B3C7EC 03E00008 */ jr $ra
/* 00610 80B3C7F0 AC860260 */ sw $a2, 0x0260($a0) ## 00000260
.L80B3C7F4:
/* 00614 80B3C7F4 AC870260 */ sw $a3, 0x0260($a0) ## 00000260
.L80B3C7F8:
/* 00618 80B3C7F8 03E00008 */ jr $ra
/* 0061C 80B3C7FC 00000000 */ nop
| {
"language": "Assembly"
} |
// Copyright 2017 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
struct bfu {
unsigned int a:11;
unsigned int f:9;
unsigned int :2;
unsigned int z:3;
};
struct bfu bfuu_init(unsigned int a)
{
struct bfu bf = { .f = a, };
return bf;
}
struct bfu bfus_init(int a)
{
struct bfu bf = { .f = a, };
return bf;
}
unsigned int bfu_get0(void)
{
struct bfu bf = { };
return bf.f;
}
struct bfs {
signed int a:11;
signed int f:9;
signed int :2;
signed int z:3;
};
struct bfs bfsu_init(unsigned int a)
{
struct bfs bf = { .f = a, };
return bf;
}
struct bfs bfss_init(int a)
{
struct bfs bf = { .f = a, };
return bf;
}
int bfs_get0(void)
{
struct bfs bf = { };
return bf.f;
}
/*
* check-name: bitfield implicit init zero
* check-command: test-linearize -Wno-decl $file
*
* check-output-start
bfuu_init:
.L0:
<entry-point>
and.32 %r4 <- %arg1, $511
shl.32 %r5 <- %r4, $11
ret.32 %r5
bfus_init:
.L2:
<entry-point>
and.32 %r13 <- %arg1, $511
shl.32 %r14 <- %r13, $11
ret.32 %r14
bfu_get0:
.L4:
<entry-point>
ret.32 $0
bfsu_init:
.L6:
<entry-point>
and.32 %r27 <- %arg1, $511
shl.32 %r28 <- %r27, $11
ret.32 %r28
bfss_init:
.L8:
<entry-point>
and.32 %r36 <- %arg1, $511
shl.32 %r37 <- %r36, $11
ret.32 %r37
bfs_get0:
.L10:
<entry-point>
ret.32 $0
* check-output-end
*/
| {
"language": "Assembly"
} |
.\" Title: mailodf
.\" Author: S\(/oren Roug
.\" Generator: DocBook XSL Stylesheets v1.74.0 <http://docbook.sf.net/>
.\" Date: 03/15/2009
.\" Manual: User commands
.\" Source: odfpy
.\" Language: English
.\"
.TH "MAILODF" "1" "03/15/2009" "odfpy" "User commands"
.\" -----------------------------------------------------------------
.\" * (re)Define some macros
.\" -----------------------------------------------------------------
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" toupper - uppercase a string (locale-aware)
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de toupper
.tr aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpPqQrRsStTuUvVwWxXyYzZ
\\$*
.tr aabbccddeeffgghhiijjkkllmmnnooppqqrrssttuuvvwwxxyyzz
..
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" SH-xref - format a cross-reference to an SH section
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de SH-xref
.ie n \{\
.\}
.toupper \\$*
.el \{\
\\$*
.\}
..
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" SH - level-one heading that works better for non-TTY output
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de1 SH
.\" put an extra blank line of space above the head in non-TTY output
.if t \{\
.sp 1
.\}
.sp \\n[PD]u
.nr an-level 1
.set-an-margin
.nr an-prevailing-indent \\n[IN]
.fi
.in \\n[an-margin]u
.ti 0
.HTML-TAG ".NH \\n[an-level]"
.it 1 an-trap
.nr an-no-space-flag 1
.nr an-break-flag 1
\." make the size of the head bigger
.ps +3
.ft B
.ne (2v + 1u)
.ie n \{\
.\" if n (TTY output), use uppercase
.toupper \\$*
.\}
.el \{\
.nr an-break-flag 0
.\" if not n (not TTY), use normal case (not uppercase)
\\$1
.in \\n[an-margin]u
.ti 0
.\" if not n (not TTY), put a border/line under subheading
.sp -.6
\l'\n(.lu'
.\}
..
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" SS - level-two heading that works better for non-TTY output
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de1 SS
.sp \\n[PD]u
.nr an-level 1
.set-an-margin
.nr an-prevailing-indent \\n[IN]
.fi
.in \\n[IN]u
.ti \\n[SN]u
.it 1 an-trap
.nr an-no-space-flag 1
.nr an-break-flag 1
.ps \\n[PS-SS]u
\." make the size of the head bigger
.ps +2
.ft B
.ne (2v + 1u)
.if \\n[.$] \&\\$*
..
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" BB/BE - put background/screen (filled box) around block of text
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de BB
.if t \{\
.sp -.5
.br
.in +2n
.ll -2n
.gcolor red
.di BX
.\}
..
.de EB
.if t \{\
.if "\\$2"adjust-for-leading-newline" \{\
.sp -1
.\}
.br
.di
.in
.ll
.gcolor
.nr BW \\n(.lu-\\n(.i
.nr BH \\n(dn+.5v
.ne \\n(BHu+.5v
.ie "\\$2"adjust-for-leading-newline" \{\
\M[\\$1]\h'1n'\v'+.5v'\D'P \\n(BWu 0 0 \\n(BHu -\\n(BWu 0 0 -\\n(BHu'\M[]
.\}
.el \{\
\M[\\$1]\h'1n'\v'-.5v'\D'P \\n(BWu 0 0 \\n(BHu -\\n(BWu 0 0 -\\n(BHu'\M[]
.\}
.in 0
.sp -.5v
.nf
.BX
.in
.sp .5v
.fi
.\}
..
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.\" BM/EM - put colored marker in margin next to block of text
.\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.de BM
.if t \{\
.br
.ll -2n
.gcolor red
.di BX
.\}
..
.de EM
.if t \{\
.br
.di
.ll
.gcolor
.nr BH \\n(dn
.ne \\n(BHu
\M[\\$1]\D'P -.75n 0 0 \\n(BHu -(\\n[.i]u - \\n(INu - .75n) 0 0 -\\n(BHu'\M[]
.in 0
.nf
.BX
.in
.fi
.\}
..
.\" -----------------------------------------------------------------
.\" * set default formatting
.\" -----------------------------------------------------------------
.\" disable hyphenation
.nh
.\" disable justification (adjust text to left margin only)
.ad l
.\" -----------------------------------------------------------------
.\" * MAIN CONTENT STARTS HERE *
.\" -----------------------------------------------------------------
.SH "Name"
mailodf \- Email ODF file as HTML archive
.SH "Synopsis"
.fam C
.HP \w'\fBmailodf\fR\ 'u
\fBmailodf\fR [\-f\ \fIfrom\fR] [\-s\ \fIsubject\fR] \fIinputfile\fR \fIrecipients\fR...
.fam
.SH "Description"
.PP
mailodf is a program that will create a MIME\-encapsulated web archive and then sends it as an email\&. Most email programs that understand HTML understands this format\&.
.PP
\(lqInputfile\(rq
is assumed to be an OpenDocument file of text, spreadsheet or presentation type\&.
.SH "References"
.RS 4
HTTRACK (http://www\&.httrack\&.com/) can create such archives with the \-%M option\&.
.RE
.RS 4
http://en\&.wikipedia\&.org/wiki/MHTML
.RE
.RS 4
http://www\&.dsv\&.su\&.se/~jpalme/ietf/mhtml\&.html
.RE
.RS 4
http://users\&.otenet\&.gr/~geosp/kmhtconvert/
.RE
.RS 4
http://www\&.faqs\&.org/rfcs/rfc2557\&.html
.RE
.SH "Example"
.sp
.if n \{\
.RS 4
.\}
.fam C
.ps -1
.nf
.if t \{\
.sp -1
.\}
.BB lightgray adjust-for-leading-newline
.sp -1
mailodf \-f lars\&.oppermann@sun\&.com \-s "F\&.Y\&.I" odf\-file
.EB lightgray adjust-for-leading-newline
.if t \{\
.sp 1
.\}
.fi
.fam
.ps +1
.if n \{\
.RE
.\}
.SH "See Also"
.PP
odf2mht
.SH "Author"
.PP
\fBS\(/oren Roug\fR
.RS 4
Original author
.RE
| {
"language": "Assembly"
} |
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// g_DepthBuffer texture float 2dMS4 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target 0 x 0 TARGET float x
//
ps_4_0
dcl_resource_texture2dms(4) (float,float,float,float) t0
dcl_input_ps linear v1.xy
dcl_output o0.x
dcl_temps 3
resinfo_uint r0.xyzw, l(0), t0.xyzw
utof r0.xy, r0.xyxx
mul r0.xy, r0.xyxx, v1.xyxx
ftoi r0.xy, r0.xyxx
mov r0.zw, l(0,0,0,0)
ldms r1.xyzw, r0.xyww, t0.xyzw, l(0)
ldms r2.xyzw, r0.xyww, t0.xyzw, l(1)
min r1.x, r1.x, r2.x
ldms r2.xyzw, r0.xyww, t0.xyzw, l(2)
ldms r0.xyzw, r0.xyzw, t0.xyzw, l(3)
min r0.y, r1.x, r2.x
min o0.x, r0.x, r0.y
ret
// Approximately 13 instruction slots used
| {
"language": "Assembly"
} |
.file "wp-mmx.s"
.text
.globl whirlpool_block_mmx
.type whirlpool_block_mmx,@function
.align 16
whirlpool_block_mmx:
.L_whirlpool_block_mmx_begin:
pushl %ebp
pushl %ebx
pushl %esi
pushl %edi
movl 20(%esp),%esi
movl 24(%esp),%edi
movl 28(%esp),%ebp
movl %esp,%eax
subl $148,%esp
andl $-64,%esp
leal 128(%esp),%ebx
movl %esi,(%ebx)
movl %edi,4(%ebx)
movl %ebp,8(%ebx)
movl %eax,16(%ebx)
call .L000pic_point
.L000pic_point:
popl %ebp
leal .L001table-.L000pic_point(%ebp),%ebp
xorl %ecx,%ecx
xorl %edx,%edx
movq (%esi),%mm0
movq 8(%esi),%mm1
movq 16(%esi),%mm2
movq 24(%esi),%mm3
movq 32(%esi),%mm4
movq 40(%esi),%mm5
movq 48(%esi),%mm6
movq 56(%esi),%mm7
.L002outerloop:
movq %mm0,(%esp)
movq %mm1,8(%esp)
movq %mm2,16(%esp)
movq %mm3,24(%esp)
movq %mm4,32(%esp)
movq %mm5,40(%esp)
movq %mm6,48(%esp)
movq %mm7,56(%esp)
pxor (%edi),%mm0
pxor 8(%edi),%mm1
pxor 16(%edi),%mm2
pxor 24(%edi),%mm3
pxor 32(%edi),%mm4
pxor 40(%edi),%mm5
pxor 48(%edi),%mm6
pxor 56(%edi),%mm7
movq %mm0,64(%esp)
movq %mm1,72(%esp)
movq %mm2,80(%esp)
movq %mm3,88(%esp)
movq %mm4,96(%esp)
movq %mm5,104(%esp)
movq %mm6,112(%esp)
movq %mm7,120(%esp)
xorl %esi,%esi
movl %esi,12(%ebx)
.align 16
.L003round:
movq 4096(%ebp,%esi,8),%mm0
movl (%esp),%eax
movl 4(%esp),%ebx
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm0
movq 7(%ebp,%edi,8),%mm1
movb %al,%cl
movb %ah,%dl
movl 8(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
movq 6(%ebp,%esi,8),%mm2
movq 5(%ebp,%edi,8),%mm3
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
movq 4(%ebp,%esi,8),%mm4
movq 3(%ebp,%edi,8),%mm5
movb %bl,%cl
movb %bh,%dl
movl 12(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
movq 2(%ebp,%esi,8),%mm6
movq 1(%ebp,%edi,8),%mm7
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm1
pxor 7(%ebp,%edi,8),%mm2
movb %al,%cl
movb %ah,%dl
movl 16(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm3
pxor 5(%ebp,%edi,8),%mm4
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm5
pxor 3(%ebp,%edi,8),%mm6
movb %bl,%cl
movb %bh,%dl
movl 20(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm7
pxor 1(%ebp,%edi,8),%mm0
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm2
pxor 7(%ebp,%edi,8),%mm3
movb %al,%cl
movb %ah,%dl
movl 24(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm4
pxor 5(%ebp,%edi,8),%mm5
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm6
pxor 3(%ebp,%edi,8),%mm7
movb %bl,%cl
movb %bh,%dl
movl 28(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm0
pxor 1(%ebp,%edi,8),%mm1
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm3
pxor 7(%ebp,%edi,8),%mm4
movb %al,%cl
movb %ah,%dl
movl 32(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm5
pxor 5(%ebp,%edi,8),%mm6
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm7
pxor 3(%ebp,%edi,8),%mm0
movb %bl,%cl
movb %bh,%dl
movl 36(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm1
pxor 1(%ebp,%edi,8),%mm2
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm4
pxor 7(%ebp,%edi,8),%mm5
movb %al,%cl
movb %ah,%dl
movl 40(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm6
pxor 5(%ebp,%edi,8),%mm7
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm0
pxor 3(%ebp,%edi,8),%mm1
movb %bl,%cl
movb %bh,%dl
movl 44(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm2
pxor 1(%ebp,%edi,8),%mm3
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm5
pxor 7(%ebp,%edi,8),%mm6
movb %al,%cl
movb %ah,%dl
movl 48(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm7
pxor 5(%ebp,%edi,8),%mm0
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm1
pxor 3(%ebp,%edi,8),%mm2
movb %bl,%cl
movb %bh,%dl
movl 52(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm3
pxor 1(%ebp,%edi,8),%mm4
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm6
pxor 7(%ebp,%edi,8),%mm7
movb %al,%cl
movb %ah,%dl
movl 56(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm0
pxor 5(%ebp,%edi,8),%mm1
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm2
pxor 3(%ebp,%edi,8),%mm3
movb %bl,%cl
movb %bh,%dl
movl 60(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm4
pxor 1(%ebp,%edi,8),%mm5
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm7
pxor 7(%ebp,%edi,8),%mm0
movb %al,%cl
movb %ah,%dl
movl 64(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm1
pxor 5(%ebp,%edi,8),%mm2
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm3
pxor 3(%ebp,%edi,8),%mm4
movb %bl,%cl
movb %bh,%dl
movl 68(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm5
pxor 1(%ebp,%edi,8),%mm6
movq %mm0,(%esp)
movq %mm1,8(%esp)
movq %mm2,16(%esp)
movq %mm3,24(%esp)
movq %mm4,32(%esp)
movq %mm5,40(%esp)
movq %mm6,48(%esp)
movq %mm7,56(%esp)
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm0
pxor 7(%ebp,%edi,8),%mm1
movb %al,%cl
movb %ah,%dl
movl 72(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm2
pxor 5(%ebp,%edi,8),%mm3
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm4
pxor 3(%ebp,%edi,8),%mm5
movb %bl,%cl
movb %bh,%dl
movl 76(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm6
pxor 1(%ebp,%edi,8),%mm7
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm1
pxor 7(%ebp,%edi,8),%mm2
movb %al,%cl
movb %ah,%dl
movl 80(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm3
pxor 5(%ebp,%edi,8),%mm4
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm5
pxor 3(%ebp,%edi,8),%mm6
movb %bl,%cl
movb %bh,%dl
movl 84(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm7
pxor 1(%ebp,%edi,8),%mm0
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm2
pxor 7(%ebp,%edi,8),%mm3
movb %al,%cl
movb %ah,%dl
movl 88(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm4
pxor 5(%ebp,%edi,8),%mm5
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm6
pxor 3(%ebp,%edi,8),%mm7
movb %bl,%cl
movb %bh,%dl
movl 92(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm0
pxor 1(%ebp,%edi,8),%mm1
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm3
pxor 7(%ebp,%edi,8),%mm4
movb %al,%cl
movb %ah,%dl
movl 96(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm5
pxor 5(%ebp,%edi,8),%mm6
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm7
pxor 3(%ebp,%edi,8),%mm0
movb %bl,%cl
movb %bh,%dl
movl 100(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm1
pxor 1(%ebp,%edi,8),%mm2
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm4
pxor 7(%ebp,%edi,8),%mm5
movb %al,%cl
movb %ah,%dl
movl 104(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm6
pxor 5(%ebp,%edi,8),%mm7
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm0
pxor 3(%ebp,%edi,8),%mm1
movb %bl,%cl
movb %bh,%dl
movl 108(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm2
pxor 1(%ebp,%edi,8),%mm3
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm5
pxor 7(%ebp,%edi,8),%mm6
movb %al,%cl
movb %ah,%dl
movl 112(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm7
pxor 5(%ebp,%edi,8),%mm0
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm1
pxor 3(%ebp,%edi,8),%mm2
movb %bl,%cl
movb %bh,%dl
movl 116(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm3
pxor 1(%ebp,%edi,8),%mm4
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm6
pxor 7(%ebp,%edi,8),%mm7
movb %al,%cl
movb %ah,%dl
movl 120(%esp),%eax
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm0
pxor 5(%ebp,%edi,8),%mm1
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm2
pxor 3(%ebp,%edi,8),%mm3
movb %bl,%cl
movb %bh,%dl
movl 124(%esp),%ebx
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm4
pxor 1(%ebp,%edi,8),%mm5
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%eax
pxor (%ebp,%esi,8),%mm7
pxor 7(%ebp,%edi,8),%mm0
movb %al,%cl
movb %ah,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 6(%ebp,%esi,8),%mm1
pxor 5(%ebp,%edi,8),%mm2
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
shrl $16,%ebx
pxor 4(%ebp,%esi,8),%mm3
pxor 3(%ebp,%edi,8),%mm4
movb %bl,%cl
movb %bh,%dl
leal (%ecx,%ecx,1),%esi
leal (%edx,%edx,1),%edi
pxor 2(%ebp,%esi,8),%mm5
pxor 1(%ebp,%edi,8),%mm6
leal 128(%esp),%ebx
movl 12(%ebx),%esi
addl $1,%esi
cmpl $10,%esi
je .L004roundsdone
movl %esi,12(%ebx)
movq %mm0,64(%esp)
movq %mm1,72(%esp)
movq %mm2,80(%esp)
movq %mm3,88(%esp)
movq %mm4,96(%esp)
movq %mm5,104(%esp)
movq %mm6,112(%esp)
movq %mm7,120(%esp)
jmp .L003round
.align 16
.L004roundsdone:
movl (%ebx),%esi
movl 4(%ebx),%edi
movl 8(%ebx),%eax
pxor (%edi),%mm0
pxor 8(%edi),%mm1
pxor 16(%edi),%mm2
pxor 24(%edi),%mm3
pxor 32(%edi),%mm4
pxor 40(%edi),%mm5
pxor 48(%edi),%mm6
pxor 56(%edi),%mm7
pxor (%esi),%mm0
pxor 8(%esi),%mm1
pxor 16(%esi),%mm2
pxor 24(%esi),%mm3
pxor 32(%esi),%mm4
pxor 40(%esi),%mm5
pxor 48(%esi),%mm6
pxor 56(%esi),%mm7
movq %mm0,(%esi)
movq %mm1,8(%esi)
movq %mm2,16(%esi)
movq %mm3,24(%esi)
movq %mm4,32(%esi)
movq %mm5,40(%esi)
movq %mm6,48(%esi)
movq %mm7,56(%esi)
leal 64(%edi),%edi
subl $1,%eax
jz .L005alldone
movl %edi,4(%ebx)
movl %eax,8(%ebx)
jmp .L002outerloop
.L005alldone:
emms
movl 16(%ebx),%esp
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
.align 64
.L001table:
.byte 24,24,96,24,192,120,48,216
.byte 24,24,96,24,192,120,48,216
.byte 35,35,140,35,5,175,70,38
.byte 35,35,140,35,5,175,70,38
.byte 198,198,63,198,126,249,145,184
.byte 198,198,63,198,126,249,145,184
.byte 232,232,135,232,19,111,205,251
.byte 232,232,135,232,19,111,205,251
.byte 135,135,38,135,76,161,19,203
.byte 135,135,38,135,76,161,19,203
.byte 184,184,218,184,169,98,109,17
.byte 184,184,218,184,169,98,109,17
.byte 1,1,4,1,8,5,2,9
.byte 1,1,4,1,8,5,2,9
.byte 79,79,33,79,66,110,158,13
.byte 79,79,33,79,66,110,158,13
.byte 54,54,216,54,173,238,108,155
.byte 54,54,216,54,173,238,108,155
.byte 166,166,162,166,89,4,81,255
.byte 166,166,162,166,89,4,81,255
.byte 210,210,111,210,222,189,185,12
.byte 210,210,111,210,222,189,185,12
.byte 245,245,243,245,251,6,247,14
.byte 245,245,243,245,251,6,247,14
.byte 121,121,249,121,239,128,242,150
.byte 121,121,249,121,239,128,242,150
.byte 111,111,161,111,95,206,222,48
.byte 111,111,161,111,95,206,222,48
.byte 145,145,126,145,252,239,63,109
.byte 145,145,126,145,252,239,63,109
.byte 82,82,85,82,170,7,164,248
.byte 82,82,85,82,170,7,164,248
.byte 96,96,157,96,39,253,192,71
.byte 96,96,157,96,39,253,192,71
.byte 188,188,202,188,137,118,101,53
.byte 188,188,202,188,137,118,101,53
.byte 155,155,86,155,172,205,43,55
.byte 155,155,86,155,172,205,43,55
.byte 142,142,2,142,4,140,1,138
.byte 142,142,2,142,4,140,1,138
.byte 163,163,182,163,113,21,91,210
.byte 163,163,182,163,113,21,91,210
.byte 12,12,48,12,96,60,24,108
.byte 12,12,48,12,96,60,24,108
.byte 123,123,241,123,255,138,246,132
.byte 123,123,241,123,255,138,246,132
.byte 53,53,212,53,181,225,106,128
.byte 53,53,212,53,181,225,106,128
.byte 29,29,116,29,232,105,58,245
.byte 29,29,116,29,232,105,58,245
.byte 224,224,167,224,83,71,221,179
.byte 224,224,167,224,83,71,221,179
.byte 215,215,123,215,246,172,179,33
.byte 215,215,123,215,246,172,179,33
.byte 194,194,47,194,94,237,153,156
.byte 194,194,47,194,94,237,153,156
.byte 46,46,184,46,109,150,92,67
.byte 46,46,184,46,109,150,92,67
.byte 75,75,49,75,98,122,150,41
.byte 75,75,49,75,98,122,150,41
.byte 254,254,223,254,163,33,225,93
.byte 254,254,223,254,163,33,225,93
.byte 87,87,65,87,130,22,174,213
.byte 87,87,65,87,130,22,174,213
.byte 21,21,84,21,168,65,42,189
.byte 21,21,84,21,168,65,42,189
.byte 119,119,193,119,159,182,238,232
.byte 119,119,193,119,159,182,238,232
.byte 55,55,220,55,165,235,110,146
.byte 55,55,220,55,165,235,110,146
.byte 229,229,179,229,123,86,215,158
.byte 229,229,179,229,123,86,215,158
.byte 159,159,70,159,140,217,35,19
.byte 159,159,70,159,140,217,35,19
.byte 240,240,231,240,211,23,253,35
.byte 240,240,231,240,211,23,253,35
.byte 74,74,53,74,106,127,148,32
.byte 74,74,53,74,106,127,148,32
.byte 218,218,79,218,158,149,169,68
.byte 218,218,79,218,158,149,169,68
.byte 88,88,125,88,250,37,176,162
.byte 88,88,125,88,250,37,176,162
.byte 201,201,3,201,6,202,143,207
.byte 201,201,3,201,6,202,143,207
.byte 41,41,164,41,85,141,82,124
.byte 41,41,164,41,85,141,82,124
.byte 10,10,40,10,80,34,20,90
.byte 10,10,40,10,80,34,20,90
.byte 177,177,254,177,225,79,127,80
.byte 177,177,254,177,225,79,127,80
.byte 160,160,186,160,105,26,93,201
.byte 160,160,186,160,105,26,93,201
.byte 107,107,177,107,127,218,214,20
.byte 107,107,177,107,127,218,214,20
.byte 133,133,46,133,92,171,23,217
.byte 133,133,46,133,92,171,23,217
.byte 189,189,206,189,129,115,103,60
.byte 189,189,206,189,129,115,103,60
.byte 93,93,105,93,210,52,186,143
.byte 93,93,105,93,210,52,186,143
.byte 16,16,64,16,128,80,32,144
.byte 16,16,64,16,128,80,32,144
.byte 244,244,247,244,243,3,245,7
.byte 244,244,247,244,243,3,245,7
.byte 203,203,11,203,22,192,139,221
.byte 203,203,11,203,22,192,139,221
.byte 62,62,248,62,237,198,124,211
.byte 62,62,248,62,237,198,124,211
.byte 5,5,20,5,40,17,10,45
.byte 5,5,20,5,40,17,10,45
.byte 103,103,129,103,31,230,206,120
.byte 103,103,129,103,31,230,206,120
.byte 228,228,183,228,115,83,213,151
.byte 228,228,183,228,115,83,213,151
.byte 39,39,156,39,37,187,78,2
.byte 39,39,156,39,37,187,78,2
.byte 65,65,25,65,50,88,130,115
.byte 65,65,25,65,50,88,130,115
.byte 139,139,22,139,44,157,11,167
.byte 139,139,22,139,44,157,11,167
.byte 167,167,166,167,81,1,83,246
.byte 167,167,166,167,81,1,83,246
.byte 125,125,233,125,207,148,250,178
.byte 125,125,233,125,207,148,250,178
.byte 149,149,110,149,220,251,55,73
.byte 149,149,110,149,220,251,55,73
.byte 216,216,71,216,142,159,173,86
.byte 216,216,71,216,142,159,173,86
.byte 251,251,203,251,139,48,235,112
.byte 251,251,203,251,139,48,235,112
.byte 238,238,159,238,35,113,193,205
.byte 238,238,159,238,35,113,193,205
.byte 124,124,237,124,199,145,248,187
.byte 124,124,237,124,199,145,248,187
.byte 102,102,133,102,23,227,204,113
.byte 102,102,133,102,23,227,204,113
.byte 221,221,83,221,166,142,167,123
.byte 221,221,83,221,166,142,167,123
.byte 23,23,92,23,184,75,46,175
.byte 23,23,92,23,184,75,46,175
.byte 71,71,1,71,2,70,142,69
.byte 71,71,1,71,2,70,142,69
.byte 158,158,66,158,132,220,33,26
.byte 158,158,66,158,132,220,33,26
.byte 202,202,15,202,30,197,137,212
.byte 202,202,15,202,30,197,137,212
.byte 45,45,180,45,117,153,90,88
.byte 45,45,180,45,117,153,90,88
.byte 191,191,198,191,145,121,99,46
.byte 191,191,198,191,145,121,99,46
.byte 7,7,28,7,56,27,14,63
.byte 7,7,28,7,56,27,14,63
.byte 173,173,142,173,1,35,71,172
.byte 173,173,142,173,1,35,71,172
.byte 90,90,117,90,234,47,180,176
.byte 90,90,117,90,234,47,180,176
.byte 131,131,54,131,108,181,27,239
.byte 131,131,54,131,108,181,27,239
.byte 51,51,204,51,133,255,102,182
.byte 51,51,204,51,133,255,102,182
.byte 99,99,145,99,63,242,198,92
.byte 99,99,145,99,63,242,198,92
.byte 2,2,8,2,16,10,4,18
.byte 2,2,8,2,16,10,4,18
.byte 170,170,146,170,57,56,73,147
.byte 170,170,146,170,57,56,73,147
.byte 113,113,217,113,175,168,226,222
.byte 113,113,217,113,175,168,226,222
.byte 200,200,7,200,14,207,141,198
.byte 200,200,7,200,14,207,141,198
.byte 25,25,100,25,200,125,50,209
.byte 25,25,100,25,200,125,50,209
.byte 73,73,57,73,114,112,146,59
.byte 73,73,57,73,114,112,146,59
.byte 217,217,67,217,134,154,175,95
.byte 217,217,67,217,134,154,175,95
.byte 242,242,239,242,195,29,249,49
.byte 242,242,239,242,195,29,249,49
.byte 227,227,171,227,75,72,219,168
.byte 227,227,171,227,75,72,219,168
.byte 91,91,113,91,226,42,182,185
.byte 91,91,113,91,226,42,182,185
.byte 136,136,26,136,52,146,13,188
.byte 136,136,26,136,52,146,13,188
.byte 154,154,82,154,164,200,41,62
.byte 154,154,82,154,164,200,41,62
.byte 38,38,152,38,45,190,76,11
.byte 38,38,152,38,45,190,76,11
.byte 50,50,200,50,141,250,100,191
.byte 50,50,200,50,141,250,100,191
.byte 176,176,250,176,233,74,125,89
.byte 176,176,250,176,233,74,125,89
.byte 233,233,131,233,27,106,207,242
.byte 233,233,131,233,27,106,207,242
.byte 15,15,60,15,120,51,30,119
.byte 15,15,60,15,120,51,30,119
.byte 213,213,115,213,230,166,183,51
.byte 213,213,115,213,230,166,183,51
.byte 128,128,58,128,116,186,29,244
.byte 128,128,58,128,116,186,29,244
.byte 190,190,194,190,153,124,97,39
.byte 190,190,194,190,153,124,97,39
.byte 205,205,19,205,38,222,135,235
.byte 205,205,19,205,38,222,135,235
.byte 52,52,208,52,189,228,104,137
.byte 52,52,208,52,189,228,104,137
.byte 72,72,61,72,122,117,144,50
.byte 72,72,61,72,122,117,144,50
.byte 255,255,219,255,171,36,227,84
.byte 255,255,219,255,171,36,227,84
.byte 122,122,245,122,247,143,244,141
.byte 122,122,245,122,247,143,244,141
.byte 144,144,122,144,244,234,61,100
.byte 144,144,122,144,244,234,61,100
.byte 95,95,97,95,194,62,190,157
.byte 95,95,97,95,194,62,190,157
.byte 32,32,128,32,29,160,64,61
.byte 32,32,128,32,29,160,64,61
.byte 104,104,189,104,103,213,208,15
.byte 104,104,189,104,103,213,208,15
.byte 26,26,104,26,208,114,52,202
.byte 26,26,104,26,208,114,52,202
.byte 174,174,130,174,25,44,65,183
.byte 174,174,130,174,25,44,65,183
.byte 180,180,234,180,201,94,117,125
.byte 180,180,234,180,201,94,117,125
.byte 84,84,77,84,154,25,168,206
.byte 84,84,77,84,154,25,168,206
.byte 147,147,118,147,236,229,59,127
.byte 147,147,118,147,236,229,59,127
.byte 34,34,136,34,13,170,68,47
.byte 34,34,136,34,13,170,68,47
.byte 100,100,141,100,7,233,200,99
.byte 100,100,141,100,7,233,200,99
.byte 241,241,227,241,219,18,255,42
.byte 241,241,227,241,219,18,255,42
.byte 115,115,209,115,191,162,230,204
.byte 115,115,209,115,191,162,230,204
.byte 18,18,72,18,144,90,36,130
.byte 18,18,72,18,144,90,36,130
.byte 64,64,29,64,58,93,128,122
.byte 64,64,29,64,58,93,128,122
.byte 8,8,32,8,64,40,16,72
.byte 8,8,32,8,64,40,16,72
.byte 195,195,43,195,86,232,155,149
.byte 195,195,43,195,86,232,155,149
.byte 236,236,151,236,51,123,197,223
.byte 236,236,151,236,51,123,197,223
.byte 219,219,75,219,150,144,171,77
.byte 219,219,75,219,150,144,171,77
.byte 161,161,190,161,97,31,95,192
.byte 161,161,190,161,97,31,95,192
.byte 141,141,14,141,28,131,7,145
.byte 141,141,14,141,28,131,7,145
.byte 61,61,244,61,245,201,122,200
.byte 61,61,244,61,245,201,122,200
.byte 151,151,102,151,204,241,51,91
.byte 151,151,102,151,204,241,51,91
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.byte 207,207,27,207,54,212,131,249
.byte 207,207,27,207,54,212,131,249
.byte 43,43,172,43,69,135,86,110
.byte 43,43,172,43,69,135,86,110
.byte 118,118,197,118,151,179,236,225
.byte 118,118,197,118,151,179,236,225
.byte 130,130,50,130,100,176,25,230
.byte 130,130,50,130,100,176,25,230
.byte 214,214,127,214,254,169,177,40
.byte 214,214,127,214,254,169,177,40
.byte 27,27,108,27,216,119,54,195
.byte 27,27,108,27,216,119,54,195
.byte 181,181,238,181,193,91,119,116
.byte 181,181,238,181,193,91,119,116
.byte 175,175,134,175,17,41,67,190
.byte 175,175,134,175,17,41,67,190
.byte 106,106,181,106,119,223,212,29
.byte 106,106,181,106,119,223,212,29
.byte 80,80,93,80,186,13,160,234
.byte 80,80,93,80,186,13,160,234
.byte 69,69,9,69,18,76,138,87
.byte 69,69,9,69,18,76,138,87
.byte 243,243,235,243,203,24,251,56
.byte 243,243,235,243,203,24,251,56
.byte 48,48,192,48,157,240,96,173
.byte 48,48,192,48,157,240,96,173
.byte 239,239,155,239,43,116,195,196
.byte 239,239,155,239,43,116,195,196
.byte 63,63,252,63,229,195,126,218
.byte 63,63,252,63,229,195,126,218
.byte 85,85,73,85,146,28,170,199
.byte 85,85,73,85,146,28,170,199
.byte 162,162,178,162,121,16,89,219
.byte 162,162,178,162,121,16,89,219
.byte 234,234,143,234,3,101,201,233
.byte 234,234,143,234,3,101,201,233
.byte 101,101,137,101,15,236,202,106
.byte 101,101,137,101,15,236,202,106
.byte 186,186,210,186,185,104,105,3
.byte 186,186,210,186,185,104,105,3
.byte 47,47,188,47,101,147,94,74
.byte 47,47,188,47,101,147,94,74
.byte 192,192,39,192,78,231,157,142
.byte 192,192,39,192,78,231,157,142
.byte 222,222,95,222,190,129,161,96
.byte 222,222,95,222,190,129,161,96
.byte 28,28,112,28,224,108,56,252
.byte 28,28,112,28,224,108,56,252
.byte 253,253,211,253,187,46,231,70
.byte 253,253,211,253,187,46,231,70
.byte 77,77,41,77,82,100,154,31
.byte 77,77,41,77,82,100,154,31
.byte 146,146,114,146,228,224,57,118
.byte 146,146,114,146,228,224,57,118
.byte 117,117,201,117,143,188,234,250
.byte 117,117,201,117,143,188,234,250
.byte 6,6,24,6,48,30,12,54
.byte 6,6,24,6,48,30,12,54
.byte 138,138,18,138,36,152,9,174
.byte 138,138,18,138,36,152,9,174
.byte 178,178,242,178,249,64,121,75
.byte 178,178,242,178,249,64,121,75
.byte 230,230,191,230,99,89,209,133
.byte 230,230,191,230,99,89,209,133
.byte 14,14,56,14,112,54,28,126
.byte 14,14,56,14,112,54,28,126
.byte 31,31,124,31,248,99,62,231
.byte 31,31,124,31,248,99,62,231
.byte 98,98,149,98,55,247,196,85
.byte 98,98,149,98,55,247,196,85
.byte 212,212,119,212,238,163,181,58
.byte 212,212,119,212,238,163,181,58
.byte 168,168,154,168,41,50,77,129
.byte 168,168,154,168,41,50,77,129
.byte 150,150,98,150,196,244,49,82
.byte 150,150,98,150,196,244,49,82
.byte 249,249,195,249,155,58,239,98
.byte 249,249,195,249,155,58,239,98
.byte 197,197,51,197,102,246,151,163
.byte 197,197,51,197,102,246,151,163
.byte 37,37,148,37,53,177,74,16
.byte 37,37,148,37,53,177,74,16
.byte 89,89,121,89,242,32,178,171
.byte 89,89,121,89,242,32,178,171
.byte 132,132,42,132,84,174,21,208
.byte 132,132,42,132,84,174,21,208
.byte 114,114,213,114,183,167,228,197
.byte 114,114,213,114,183,167,228,197
.byte 57,57,228,57,213,221,114,236
.byte 57,57,228,57,213,221,114,236
.byte 76,76,45,76,90,97,152,22
.byte 76,76,45,76,90,97,152,22
.byte 94,94,101,94,202,59,188,148
.byte 94,94,101,94,202,59,188,148
.byte 120,120,253,120,231,133,240,159
.byte 120,120,253,120,231,133,240,159
.byte 56,56,224,56,221,216,112,229
.byte 56,56,224,56,221,216,112,229
.byte 140,140,10,140,20,134,5,152
.byte 140,140,10,140,20,134,5,152
.byte 209,209,99,209,198,178,191,23
.byte 209,209,99,209,198,178,191,23
.byte 165,165,174,165,65,11,87,228
.byte 165,165,174,165,65,11,87,228
.byte 226,226,175,226,67,77,217,161
.byte 226,226,175,226,67,77,217,161
.byte 97,97,153,97,47,248,194,78
.byte 97,97,153,97,47,248,194,78
.byte 179,179,246,179,241,69,123,66
.byte 179,179,246,179,241,69,123,66
.byte 33,33,132,33,21,165,66,52
.byte 33,33,132,33,21,165,66,52
.byte 156,156,74,156,148,214,37,8
.byte 156,156,74,156,148,214,37,8
.byte 30,30,120,30,240,102,60,238
.byte 30,30,120,30,240,102,60,238
.byte 67,67,17,67,34,82,134,97
.byte 67,67,17,67,34,82,134,97
.byte 199,199,59,199,118,252,147,177
.byte 199,199,59,199,118,252,147,177
.byte 252,252,215,252,179,43,229,79
.byte 252,252,215,252,179,43,229,79
.byte 4,4,16,4,32,20,8,36
.byte 4,4,16,4,32,20,8,36
.byte 81,81,89,81,178,8,162,227
.byte 81,81,89,81,178,8,162,227
.byte 153,153,94,153,188,199,47,37
.byte 153,153,94,153,188,199,47,37
.byte 109,109,169,109,79,196,218,34
.byte 109,109,169,109,79,196,218,34
.byte 13,13,52,13,104,57,26,101
.byte 13,13,52,13,104,57,26,101
.byte 250,250,207,250,131,53,233,121
.byte 250,250,207,250,131,53,233,121
.byte 223,223,91,223,182,132,163,105
.byte 223,223,91,223,182,132,163,105
.byte 126,126,229,126,215,155,252,169
.byte 126,126,229,126,215,155,252,169
.byte 36,36,144,36,61,180,72,25
.byte 36,36,144,36,61,180,72,25
.byte 59,59,236,59,197,215,118,254
.byte 59,59,236,59,197,215,118,254
.byte 171,171,150,171,49,61,75,154
.byte 171,171,150,171,49,61,75,154
.byte 206,206,31,206,62,209,129,240
.byte 206,206,31,206,62,209,129,240
.byte 17,17,68,17,136,85,34,153
.byte 17,17,68,17,136,85,34,153
.byte 143,143,6,143,12,137,3,131
.byte 143,143,6,143,12,137,3,131
.byte 78,78,37,78,74,107,156,4
.byte 78,78,37,78,74,107,156,4
.byte 183,183,230,183,209,81,115,102
.byte 183,183,230,183,209,81,115,102
.byte 235,235,139,235,11,96,203,224
.byte 235,235,139,235,11,96,203,224
.byte 60,60,240,60,253,204,120,193
.byte 60,60,240,60,253,204,120,193
.byte 129,129,62,129,124,191,31,253
.byte 129,129,62,129,124,191,31,253
.byte 148,148,106,148,212,254,53,64
.byte 148,148,106,148,212,254,53,64
.byte 247,247,251,247,235,12,243,28
.byte 247,247,251,247,235,12,243,28
.byte 185,185,222,185,161,103,111,24
.byte 185,185,222,185,161,103,111,24
.byte 19,19,76,19,152,95,38,139
.byte 19,19,76,19,152,95,38,139
.byte 44,44,176,44,125,156,88,81
.byte 44,44,176,44,125,156,88,81
.byte 211,211,107,211,214,184,187,5
.byte 211,211,107,211,214,184,187,5
.byte 231,231,187,231,107,92,211,140
.byte 231,231,187,231,107,92,211,140
.byte 110,110,165,110,87,203,220,57
.byte 110,110,165,110,87,203,220,57
.byte 196,196,55,196,110,243,149,170
.byte 196,196,55,196,110,243,149,170
.byte 3,3,12,3,24,15,6,27
.byte 3,3,12,3,24,15,6,27
.byte 86,86,69,86,138,19,172,220
.byte 86,86,69,86,138,19,172,220
.byte 68,68,13,68,26,73,136,94
.byte 68,68,13,68,26,73,136,94
.byte 127,127,225,127,223,158,254,160
.byte 127,127,225,127,223,158,254,160
.byte 169,169,158,169,33,55,79,136
.byte 169,169,158,169,33,55,79,136
.byte 42,42,168,42,77,130,84,103
.byte 42,42,168,42,77,130,84,103
.byte 187,187,214,187,177,109,107,10
.byte 187,187,214,187,177,109,107,10
.byte 193,193,35,193,70,226,159,135
.byte 193,193,35,193,70,226,159,135
.byte 83,83,81,83,162,2,166,241
.byte 83,83,81,83,162,2,166,241
.byte 220,220,87,220,174,139,165,114
.byte 220,220,87,220,174,139,165,114
.byte 11,11,44,11,88,39,22,83
.byte 11,11,44,11,88,39,22,83
.byte 157,157,78,157,156,211,39,1
.byte 157,157,78,157,156,211,39,1
.byte 108,108,173,108,71,193,216,43
.byte 108,108,173,108,71,193,216,43
.byte 49,49,196,49,149,245,98,164
.byte 49,49,196,49,149,245,98,164
.byte 116,116,205,116,135,185,232,243
.byte 116,116,205,116,135,185,232,243
.byte 246,246,255,246,227,9,241,21
.byte 246,246,255,246,227,9,241,21
.byte 70,70,5,70,10,67,140,76
.byte 70,70,5,70,10,67,140,76
.byte 172,172,138,172,9,38,69,165
.byte 172,172,138,172,9,38,69,165
.byte 137,137,30,137,60,151,15,181
.byte 137,137,30,137,60,151,15,181
.byte 20,20,80,20,160,68,40,180
.byte 20,20,80,20,160,68,40,180
.byte 225,225,163,225,91,66,223,186
.byte 225,225,163,225,91,66,223,186
.byte 22,22,88,22,176,78,44,166
.byte 22,22,88,22,176,78,44,166
.byte 58,58,232,58,205,210,116,247
.byte 58,58,232,58,205,210,116,247
.byte 105,105,185,105,111,208,210,6
.byte 105,105,185,105,111,208,210,6
.byte 9,9,36,9,72,45,18,65
.byte 9,9,36,9,72,45,18,65
.byte 112,112,221,112,167,173,224,215
.byte 112,112,221,112,167,173,224,215
.byte 182,182,226,182,217,84,113,111
.byte 182,182,226,182,217,84,113,111
.byte 208,208,103,208,206,183,189,30
.byte 208,208,103,208,206,183,189,30
.byte 237,237,147,237,59,126,199,214
.byte 237,237,147,237,59,126,199,214
.byte 204,204,23,204,46,219,133,226
.byte 204,204,23,204,46,219,133,226
.byte 66,66,21,66,42,87,132,104
.byte 66,66,21,66,42,87,132,104
.byte 152,152,90,152,180,194,45,44
.byte 152,152,90,152,180,194,45,44
.byte 164,164,170,164,73,14,85,237
.byte 164,164,170,164,73,14,85,237
.byte 40,40,160,40,93,136,80,117
.byte 40,40,160,40,93,136,80,117
.byte 92,92,109,92,218,49,184,134
.byte 92,92,109,92,218,49,184,134
.byte 248,248,199,248,147,63,237,107
.byte 248,248,199,248,147,63,237,107
.byte 134,134,34,134,68,164,17,194
.byte 134,134,34,134,68,164,17,194
.byte 24,35,198,232,135,184,1,79
.byte 54,166,210,245,121,111,145,82
.byte 96,188,155,142,163,12,123,53
.byte 29,224,215,194,46,75,254,87
.byte 21,119,55,229,159,240,74,218
.byte 88,201,41,10,177,160,107,133
.byte 189,93,16,244,203,62,5,103
.byte 228,39,65,139,167,125,149,216
.byte 251,238,124,102,221,23,71,158
.byte 202,45,191,7,173,90,131,51
.size whirlpool_block_mmx,.-.L_whirlpool_block_mmx_begin
| {
"language": "Assembly"
} |
# REQUIRES: x86
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t1
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \
# RUN: %p/Inputs/include.s -o %t2
# RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux \
# RUN: %p/Inputs/notinclude.s -o %t3.notinclude
# RUN: echo "SECTIONS {} " > %t.script
# RUN: ld.lld -o %t --script %t.script %t1 %t2 %t3.notinclude
# RUN: llvm-objdump -d %t | FileCheck %s
# CHECK: Disassembly of section .text:
# CHECK-EMPTY:
# CHECK: _start:
# CHECK-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax
# CHECK-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi
# CHECK-NEXT: : cc int3
# CHECK-NEXT: : cc int3
# CHECK: _potato:
# CHECK-NEXT: : 90 nop
# CHECK-NEXT: : 90 nop
# CHECK-NEXT: : cc int3
# CHECK-NEXT: : cc int3
# CHECK: tomato:
# CHECK-NEXT: : b8 01 00 00 00 movl $1, %eax
# RUN: echo "SECTIONS { .patatino : \
# RUN: { KEEP(*(EXCLUDE_FILE(*notinclude) .text)) } }" \
# RUN: > %t.script
# RUN: ld.lld -o %t4 --script %t.script %t1 %t2 %t3.notinclude
# RUN: llvm-objdump -d %t4 | FileCheck %s --check-prefix=EXCLUDE
# EXCLUDE: Disassembly of section .patatino:
# EXCLUDE-EMPTY:
# EXCLUDE: _start:
# EXCLUDE-NEXT: : 48 c7 c0 3c 00 00 00 movq $60, %rax
# EXCLUDE-NEXT: : 48 c7 c7 2a 00 00 00 movq $42, %rdi
# EXCLUDE-NEXT: : cc int3
# EXCLUDE-NEXT: : cc int3
# EXCLUDE: _potato:
# EXCLUDE-NEXT: : 90 nop
# EXCLUDE-NEXT: : 90 nop
# EXCLUDE: Disassembly of section .text:
# EXCLUDE-EMPTY:
# EXCLUDE: tomato:
# EXCLUDE-NEXT: : b8 01 00 00 00 movl $1, %eax
.section .text
.globl _start
_start:
mov $60, %rax
mov $42, %rdi
| {
"language": "Assembly"
} |
BEGIN:VCALENDAR
PRODID:-//Inverse inc.//NONSGML IANA 2019c//EN
VERSION:2.0
BEGIN:VTIMEZONE
TZID:Asia/Sakhalin
LAST-MODIFIED:20191023T183904Z
X-LIC-LOCATION:Asia/Sakhalin
BEGIN:STANDARD
TZNAME:+11
TZOFFSETFROM:+1100
TZOFFSETTO:+1100
DTSTART:19700101T000000
END:STANDARD
END:VTIMEZONE
END:VCALENDAR
| {
"language": "Assembly"
} |
#! /usr/bin/env perl
# Copyright 2016-2020 The OpenSSL Project Authors. All Rights Reserved.
#
# Licensed under the OpenSSL license (the "License"). You may not use
# this file except in compliance with the License. You can obtain a copy
# in the file LICENSE in the source distribution or at
# https://www.openssl.org/source/license.html
#
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see http://www.openssl.org/~appro/cryptogams/.
# ====================================================================
#
# This module implements Poly1305 hash for s390x.
#
# June 2015
#
# ~6.6/2.3 cpb on z10/z196+, >2x improvement over compiler-generated
# code. For older compiler improvement coefficient is >3x, because
# then base 2^64 and base 2^32 implementations are compared.
#
# On side note, z13 enables vector base 2^26 implementation...
$flavour = shift;
if ($flavour =~ /3[12]/) {
$SIZE_T=4;
$g="";
} else {
$SIZE_T=8;
$g="g";
}
while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {}
open STDOUT,">$output";
$sp="%r15";
my ($ctx,$inp,$len,$padbit) = map("%r$_",(2..5));
$code.=<<___;
.text
.globl poly1305_init
.type poly1305_init,\@function
.align 16
poly1305_init:
lghi %r0,0
lghi %r1,-1
stg %r0,0($ctx) # zero hash value
stg %r0,8($ctx)
stg %r0,16($ctx)
cl${g}r $inp,%r0
je .Lno_key
lrvg %r4,0($inp) # load little-endian key
lrvg %r5,8($inp)
nihl %r1,0xffc0 # 0xffffffc0ffffffff
srlg %r0,%r1,4 # 0x0ffffffc0fffffff
srlg %r1,%r1,4
nill %r1,0xfffc # 0x0ffffffc0ffffffc
ngr %r4,%r0
ngr %r5,%r1
stg %r4,32($ctx)
stg %r5,40($ctx)
.Lno_key:
lghi %r2,0
br %r14
.size poly1305_init,.-poly1305_init
___
{
my ($d0hi,$d0lo,$d1hi,$d1lo,$t0,$h0,$t1,$h1,$h2) = map("%r$_",(6..14));
my ($r0,$r1,$s1) = map("%r$_",(0..2));
$code.=<<___;
.globl poly1305_blocks
.type poly1305_blocks,\@function
.align 16
poly1305_blocks:
srl${g} $len,4 # fixed-up in 64-bit build
lghi %r0,0
cl${g}r $len,%r0
je .Lno_data
stm${g} %r6,%r14,`6*$SIZE_T`($sp)
llgfr $padbit,$padbit # clear upper half, much needed with
# non-64-bit ABI
lg $r0,32($ctx) # load key
lg $r1,40($ctx)
lg $h0,0($ctx) # load hash value
lg $h1,8($ctx)
lg $h2,16($ctx)
st$g $ctx,`2*$SIZE_T`($sp) # off-load $ctx
srlg $s1,$r1,2
algr $s1,$r1 # s1 = r1 + r1>>2
j .Loop
.align 16
.Loop:
lrvg $d0lo,0($inp) # load little-endian input
lrvg $d1lo,8($inp)
la $inp,16($inp)
algr $d0lo,$h0 # accumulate input
alcgr $d1lo,$h1
lgr $h0,$d0lo
mlgr $d0hi,$r0 # h0*r0 -> $d0hi:$d0lo
lgr $h1,$d1lo
mlgr $d1hi,$s1 # h1*5*r1 -> $d1hi:$d1lo
mlgr $t0,$r1 # h0*r1 -> $t0:$h0
mlgr $t1,$r0 # h1*r0 -> $t1:$h1
alcgr $h2,$padbit
algr $d0lo,$d1lo
lgr $d1lo,$h2
alcgr $d0hi,$d1hi
lghi $d1hi,0
algr $h1,$h0
alcgr $t1,$t0
msgr $d1lo,$s1 # h2*s1
msgr $h2,$r0 # h2*r0
algr $h1,$d1lo
alcgr $t1,$d1hi # $d1hi is zero
algr $h1,$d0hi
alcgr $h2,$t1
lghi $h0,-4 # final reduction step
ngr $h0,$h2
srlg $t0,$h2,2
algr $h0,$t0
lghi $t1,3
ngr $h2,$t1
algr $h0,$d0lo
alcgr $h1,$d1hi # $d1hi is still zero
alcgr $h2,$d1hi # $d1hi is still zero
brct$g $len,.Loop
l$g $ctx,`2*$SIZE_T`($sp) # restore $ctx
stg $h0,0($ctx) # store hash value
stg $h1,8($ctx)
stg $h2,16($ctx)
lm${g} %r6,%r14,`6*$SIZE_T`($sp)
.Lno_data:
br %r14
.size poly1305_blocks,.-poly1305_blocks
___
}
{
my ($mac,$nonce)=($inp,$len);
my ($h0,$h1,$h2,$d0,$d1)=map("%r$_",(5..9));
$code.=<<___;
.globl poly1305_emit
.type poly1305_emit,\@function
.align 16
poly1305_emit:
stm${g} %r6,%r9,`6*$SIZE_T`($sp)
lg $h0,0($ctx)
lg $h1,8($ctx)
lg $h2,16($ctx)
lghi %r0,5
lghi %r1,0
lgr $d0,$h0
lgr $d1,$h1
algr $h0,%r0 # compare to modulus
alcgr $h1,%r1
alcgr $h2,%r1
srlg $h2,$h2,2 # did it borrow/carry?
slgr %r1,$h2 # 0-$h2>>2
lg $h2,0($nonce) # load nonce
lghi %r0,-1
lg $ctx,8($nonce)
xgr %r0,%r1 # ~%r1
ngr $h0,%r1
ngr $d0,%r0
ngr $h1,%r1
ngr $d1,%r0
ogr $h0,$d0
rllg $d0,$h2,32 # flip nonce words
ogr $h1,$d1
rllg $d1,$ctx,32
algr $h0,$d0 # accumulate nonce
alcgr $h1,$d1
strvg $h0,0($mac) # write little-endian result
strvg $h1,8($mac)
lm${g} %r6,%r9,`6*$SIZE_T`($sp)
br %r14
.size poly1305_emit,.-poly1305_emit
.string "Poly1305 for s390x, CRYPTOGAMS by <appro\@openssl.org>"
___
}
$code =~ s/\`([^\`]*)\`/eval $1/gem;
$code =~ s/\b(srlg\s+)(%r[0-9]+\s*,)\s*([0-9]+)/$1$2$2$3/gm;
print $code;
close STDOUT or die "error closing STDOUT: $!";
| {
"language": "Assembly"
} |
.sect .text; .sect .rom; .sect .data; .sect .bss
.sect .text
.define _chown
_chown:
jmp __chown
| {
"language": "Assembly"
} |
; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
foo:
;-----------------------------------------------------------------------------
; Indexed loads
;-----------------------------------------------------------------------------
ldr w5, [x4, #20]
ldr x4, [x3]
ldr x2, [sp, #32]
ldr b5, [sp, #1]
ldr h6, [sp, #2]
ldr s7, [sp, #4]
ldr d8, [sp, #8]
ldr q9, [sp, #16]
ldrb w4, [x3]
ldrb w5, [x4, #20]
ldrb w2, [x3, _foo@pageoff]
ldrb w3, [x2, "+[Test method].var"@PAGEOFF]
ldrsb w9, [x3]
ldrsb x2, [sp, #128]
ldrh w2, [sp, #32]
ldrsh w3, [sp, #32]
ldrsh x5, [x9, #24]
ldrsw x9, [sp, #512]
prfm #5, [sp, #32]
prfm #31, [sp, #32]
prfm pldl1keep, [x2]
prfm pldl1strm, [x2]
prfm pldl2keep, [x2]
prfm pldl2strm, [x2]
prfm pldl3keep, [x2]
prfm pldl3strm, [x2]
prfm pstl1keep, [x2]
prfm pstl1strm, [x2]
prfm pstl2keep, [x2]
prfm pstl2strm, [x2]
prfm pstl3keep, [x2]
prfm pstl3strm, [x2]
prfm pstl3strm, [x4, x5, lsl #3]
; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9]
; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d]
; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d]
; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd]
; CHECK: ldr d8, [sp, #8] ; encoding: [0xe8,0x07,0x40,0xfd]
; CHECK: ldr q9, [sp, #16] ; encoding: [0xe9,0x07,0xc0,0x3d]
; CHECK: ldrb w4, [x3] ; encoding: [0x64,0x00,0x40,0x39]
; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
; CHECK: ldrb w2, [x3, _foo@PAGEOFF] ; encoding: [0x62,0bAAAAAA00,0b01AAAAAA,0x39]
; CHECK: ldrb w3, [x2, "+[Test method].var"@PAGEOFF] ; encoding: [0x43,0bAAAAAA00,0b01AAAAAA,0x39]
; CHECK: ldrsb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x39]
; CHECK: ldrsb x2, [sp, #128] ; encoding: [0xe2,0x03,0x82,0x39]
; CHECK: ldrh w2, [sp, #32] ; encoding: [0xe2,0x43,0x40,0x79]
; CHECK: ldrsh w3, [sp, #32] ; encoding: [0xe3,0x43,0xc0,0x79]
; CHECK: ldrsh x5, [x9, #24] ; encoding: [0x25,0x31,0x80,0x79]
; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9]
; CHECK: prfm pldl3strm, [sp, #32] ; encoding: [0xe5,0x13,0x80,0xf9]
; CHECK: prfm #31, [sp, #32] ; encoding: [0xff,0x13,0x80,0xf9]
; CHECK: prfm pldl1keep, [x2] ; encoding: [0x40,0x00,0x80,0xf9]
; CHECK: prfm pldl1strm, [x2] ; encoding: [0x41,0x00,0x80,0xf9]
; CHECK: prfm pldl2keep, [x2] ; encoding: [0x42,0x00,0x80,0xf9]
; CHECK: prfm pldl2strm, [x2] ; encoding: [0x43,0x00,0x80,0xf9]
; CHECK: prfm pldl3keep, [x2] ; encoding: [0x44,0x00,0x80,0xf9]
; CHECK: prfm pldl3strm, [x2] ; encoding: [0x45,0x00,0x80,0xf9]
; CHECK: prfm pstl1keep, [x2] ; encoding: [0x50,0x00,0x80,0xf9]
; CHECK: prfm pstl1strm, [x2] ; encoding: [0x51,0x00,0x80,0xf9]
; CHECK: prfm pstl2keep, [x2] ; encoding: [0x52,0x00,0x80,0xf9]
; CHECK: prfm pstl2strm, [x2] ; encoding: [0x53,0x00,0x80,0xf9]
; CHECK: prfm pstl3keep, [x2] ; encoding: [0x54,0x00,0x80,0xf9]
; CHECK: prfm pstl3strm, [x2] ; encoding: [0x55,0x00,0x80,0xf9]
; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
;-----------------------------------------------------------------------------
; Indexed stores
;-----------------------------------------------------------------------------
str x4, [x3]
str x2, [sp, #32]
str w5, [x4, #20]
str b5, [sp, #1]
str h6, [sp, #2]
str s7, [sp, #4]
str d8, [sp, #8]
str q9, [sp, #16]
strb w4, [x3]
strb w5, [x4, #20]
strh w2, [sp, #32]
; CHECK: str x4, [x3] ; encoding: [0x64,0x00,0x00,0xf9]
; CHECK: str x2, [sp, #32] ; encoding: [0xe2,0x13,0x00,0xf9]
; CHECK: str w5, [x4, #20] ; encoding: [0x85,0x14,0x00,0xb9]
; CHECK: str b5, [sp, #1] ; encoding: [0xe5,0x07,0x00,0x3d]
; CHECK: str h6, [sp, #2] ; encoding: [0xe6,0x07,0x00,0x7d]
; CHECK: str s7, [sp, #4] ; encoding: [0xe7,0x07,0x00,0xbd]
; CHECK: str d8, [sp, #8] ; encoding: [0xe8,0x07,0x00,0xfd]
; CHECK: str q9, [sp, #16] ; encoding: [0xe9,0x07,0x80,0x3d]
; CHECK: strb w4, [x3] ; encoding: [0x64,0x00,0x00,0x39]
; CHECK: strb w5, [x4, #20] ; encoding: [0x85,0x50,0x00,0x39]
; CHECK: strh w2, [sp, #32] ; encoding: [0xe2,0x43,0x00,0x79]
;-----------------------------------------------------------------------------
; Unscaled immediate loads and stores
;-----------------------------------------------------------------------------
ldur w2, [x3]
ldur w2, [sp, #24]
ldur x2, [x3]
ldur x2, [sp, #24]
ldur b5, [sp, #1]
ldur h6, [sp, #2]
ldur s7, [sp, #4]
ldur d8, [sp, #8]
ldur q9, [sp, #16]
ldursb w9, [x3]
ldursb x2, [sp, #128]
ldursh w3, [sp, #32]
ldursh x5, [x9, #24]
ldursw x9, [sp, #-128]
; CHECK: ldur w2, [x3] ; encoding: [0x62,0x00,0x40,0xb8]
; CHECK: ldur w2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xb8]
; CHECK: ldur x2, [x3] ; encoding: [0x62,0x00,0x40,0xf8]
; CHECK: ldur x2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xf8]
; CHECK: ldur b5, [sp, #1] ; encoding: [0xe5,0x13,0x40,0x3c]
; CHECK: ldur h6, [sp, #2] ; encoding: [0xe6,0x23,0x40,0x7c]
; CHECK: ldur s7, [sp, #4] ; encoding: [0xe7,0x43,0x40,0xbc]
; CHECK: ldur d8, [sp, #8] ; encoding: [0xe8,0x83,0x40,0xfc]
; CHECK: ldur q9, [sp, #16] ; encoding: [0xe9,0x03,0xc1,0x3c]
; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38]
; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38]
; CHECK: ldursh w3, [sp, #32] ; encoding: [0xe3,0x03,0xc2,0x78]
; CHECK: ldursh x5, [x9, #24] ; encoding: [0x25,0x81,0x81,0x78]
; CHECK: ldursw x9, [sp, #-128] ; encoding: [0xe9,0x03,0x98,0xb8]
stur w4, [x3]
stur w2, [sp, #32]
stur x4, [x3]
stur x2, [sp, #32]
stur w5, [x4, #20]
stur b5, [sp, #1]
stur h6, [sp, #2]
stur s7, [sp, #4]
stur d8, [sp, #8]
stur q9, [sp, #16]
sturb w4, [x3]
sturb w5, [x4, #20]
sturh w2, [sp, #32]
prfum #5, [sp, #32]
; CHECK: stur w4, [x3] ; encoding: [0x64,0x00,0x00,0xb8]
; CHECK: stur w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xb8]
; CHECK: stur x4, [x3] ; encoding: [0x64,0x00,0x00,0xf8]
; CHECK: stur x2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xf8]
; CHECK: stur w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0xb8]
; CHECK: stur b5, [sp, #1] ; encoding: [0xe5,0x13,0x00,0x3c]
; CHECK: stur h6, [sp, #2] ; encoding: [0xe6,0x23,0x00,0x7c]
; CHECK: stur s7, [sp, #4] ; encoding: [0xe7,0x43,0x00,0xbc]
; CHECK: stur d8, [sp, #8] ; encoding: [0xe8,0x83,0x00,0xfc]
; CHECK: stur q9, [sp, #16] ; encoding: [0xe9,0x03,0x81,0x3c]
; CHECK: sturb w4, [x3] ; encoding: [0x64,0x00,0x00,0x38]
; CHECK: sturb w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0x38]
; CHECK: sturh w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0x78]
; CHECK: prfum pldl3strm, [sp, #32] ; encoding: [0xe5,0x03,0x82,0xf8]
;-----------------------------------------------------------------------------
; Unprivileged loads and stores
;-----------------------------------------------------------------------------
ldtr w3, [x4, #16]
ldtr x3, [x4, #16]
ldtrb w3, [x4, #16]
ldtrsb w9, [x3]
ldtrsb x2, [sp, #128]
ldtrh w3, [x4, #16]
ldtrsh w3, [sp, #32]
ldtrsh x5, [x9, #24]
ldtrsw x9, [sp, #-128]
; CHECK: ldtr w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xb8]
; CHECK: ldtr x3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xf8]
; CHECK: ldtrb w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x38]
; CHECK: ldtrsb w9, [x3] ; encoding: [0x69,0x08,0xc0,0x38]
; CHECK: ldtrsb x2, [sp, #128] ; encoding: [0xe2,0x0b,0x88,0x38]
; CHECK: ldtrh w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x78]
; CHECK: ldtrsh w3, [sp, #32] ; encoding: [0xe3,0x0b,0xc2,0x78]
; CHECK: ldtrsh x5, [x9, #24] ; encoding: [0x25,0x89,0x81,0x78]
; CHECK: ldtrsw x9, [sp, #-128] ; encoding: [0xe9,0x0b,0x98,0xb8]
sttr w5, [x4, #20]
sttr x4, [x3]
sttr x2, [sp, #32]
sttrb w4, [x3]
sttrb w5, [x4, #20]
sttrh w2, [sp, #32]
; CHECK: sttr w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0xb8]
; CHECK: sttr x4, [x3] ; encoding: [0x64,0x08,0x00,0xf8]
; CHECK: sttr x2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0xf8]
; CHECK: sttrb w4, [x3] ; encoding: [0x64,0x08,0x00,0x38]
; CHECK: sttrb w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0x38]
; CHECK: sttrh w2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0x78]
;-----------------------------------------------------------------------------
; Pre-indexed loads and stores
;-----------------------------------------------------------------------------
ldr x29, [x7, #8]!
ldr x30, [x7, #8]!
ldr b5, [x0, #1]!
ldr h6, [x0, #2]!
ldr s7, [x0, #4]!
ldr d8, [x0, #8]!
ldr q9, [x0, #16]!
str x30, [x7, #-8]!
str x29, [x7, #-8]!
str b5, [x0, #-1]!
str h6, [x0, #-2]!
str s7, [x0, #-4]!
str d8, [x0, #-8]!
str q9, [x0, #-16]!
; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc]
; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc]
; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
; CHECK: str d8, [x0, #-8]! ; encoding: [0x08,0x8c,0x1f,0xfc]
; CHECK: str q9, [x0, #-16]! ; encoding: [0x09,0x0c,0x9f,0x3c]
;-----------------------------------------------------------------------------
; post-indexed loads and stores
;-----------------------------------------------------------------------------
str x30, [x7], #-8
str x29, [x7], #-8
str b5, [x0], #-1
str h6, [x0], #-2
str s7, [x0], #-4
str d8, [x0], #-8
str q9, [x0], #-16
ldr x29, [x7], #8
ldr x30, [x7], #8
ldr b5, [x0], #1
ldr h6, [x0], #2
ldr s7, [x0], #4
ldr d8, [x0], #8
ldr q9, [x0], #16
; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc]
; CHECK: ldr d8, [x0], #8 ; encoding: [0x08,0x84,0x40,0xfc]
; CHECK: ldr q9, [x0], #16 ; encoding: [0x09,0x04,0xc1,0x3c]
;-----------------------------------------------------------------------------
; Load/Store pair (indexed, offset)
;-----------------------------------------------------------------------------
ldp w3, w2, [x15, #16]
ldp x4, x9, [sp, #-16]
ldpsw x2, x3, [x14, #16]
ldpsw x2, x3, [sp, #-16]
ldp s10, s1, [x2, #64]
ldp d10, d1, [x2]
ldp q2, q3, [x0, #32]
; CHECK: ldp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x29]
; CHECK: ldp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa9]
; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69]
; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69]
; CHECK: ldp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2d]
; CHECK: ldp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6d]
; CHECK: ldp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x41,0xad]
stp w3, w2, [x15, #16]
stp x4, x9, [sp, #-16]
stp s10, s1, [x2, #64]
stp d10, d1, [x2]
stp q2, q3, [x0, #32]
; CHECK: stp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x29]
; CHECK: stp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa9]
; CHECK: stp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2d]
; CHECK: stp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6d]
; CHECK: stp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x01,0xad]
;-----------------------------------------------------------------------------
; Load/Store pair (pre-indexed)
;-----------------------------------------------------------------------------
ldp w3, w2, [x15, #16]!
ldp x4, x9, [sp, #-16]!
ldpsw x2, x3, [x14, #16]!
ldpsw x2, x3, [sp, #-16]!
ldp s10, s1, [x2, #64]!
ldp d10, d1, [x2, #16]!
; CHECK: ldp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0xc2,0x29]
; CHECK: ldp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xff,0xa9]
; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69]
; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69]
; CHECK: ldp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0xc8,0x2d]
; CHECK: ldp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0xc1,0x6d]
stp w3, w2, [x15, #16]!
stp x4, x9, [sp, #-16]!
stp s10, s1, [x2, #64]!
stp d10, d1, [x2, #16]!
; CHECK: stp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0x82,0x29]
; CHECK: stp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xbf,0xa9]
; CHECK: stp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0x88,0x2d]
; CHECK: stp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0x81,0x6d]
;-----------------------------------------------------------------------------
; Load/Store pair (post-indexed)
;-----------------------------------------------------------------------------
ldp w3, w2, [x15], #16
ldp x4, x9, [sp], #-16
ldpsw x2, x3, [x14], #16
ldpsw x2, x3, [sp], #-16
ldp s10, s1, [x2], #64
ldp d10, d1, [x2], #16
; CHECK: ldp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0xc2,0x28]
; CHECK: ldp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xff,0xa8]
; CHECK: ldpsw x2, x3, [x14], #16 ; encoding: [0xc2,0x0d,0xc2,0x68]
; CHECK: ldpsw x2, x3, [sp], #-16 ; encoding: [0xe2,0x0f,0xfe,0x68]
; CHECK: ldp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0xc8,0x2c]
; CHECK: ldp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0xc1,0x6c]
stp w3, w2, [x15], #16
stp x4, x9, [sp], #-16
stp s10, s1, [x2], #64
stp d10, d1, [x2], #16
; CHECK: stp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0x82,0x28]
; CHECK: stp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xbf,0xa8]
; CHECK: stp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0x88,0x2c]
; CHECK: stp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0x81,0x6c]
;-----------------------------------------------------------------------------
; Load/Store pair (no-allocate)
;-----------------------------------------------------------------------------
ldnp w3, w2, [x15, #16]
ldnp x4, x9, [sp, #-16]
ldnp s10, s1, [x2, #64]
ldnp d10, d1, [x2]
; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28]
; CHECK: ldnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa8]
; CHECK: ldnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2c]
; CHECK: ldnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6c]
stnp w3, w2, [x15, #16]
stnp x4, x9, [sp, #-16]
stnp s10, s1, [x2, #64]
stnp d10, d1, [x2]
; CHECK: stnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x28]
; CHECK: stnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa8]
; CHECK: stnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2c]
; CHECK: stnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6c]
;-----------------------------------------------------------------------------
; Load/Store register offset
;-----------------------------------------------------------------------------
ldr w0, [x0, x0]
ldr w0, [x0, x0, lsl #2]
ldr x0, [x0, x0]
ldr x0, [x0, x0, lsl #3]
ldr x0, [x0, x0, sxtx]
; CHECK: ldr w0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xb8]
; CHECK: ldr w0, [x0, x0, lsl #2] ; encoding: [0x00,0x78,0x60,0xb8]
; CHECK: ldr x0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xf8]
; CHECK: ldr x0, [x0, x0, lsl #3] ; encoding: [0x00,0x78,0x60,0xf8]
; CHECK: ldr x0, [x0, x0, sxtx] ; encoding: [0x00,0xe8,0x60,0xf8]
ldr b1, [x1, x2]
ldr b1, [x1, x2, lsl #0]
ldr h1, [x1, x2]
ldr h1, [x1, x2, lsl #1]
ldr s1, [x1, x2]
ldr s1, [x1, x2, lsl #2]
ldr d1, [x1, x2]
ldr d1, [x1, x2, lsl #3]
ldr q1, [x1, x2]
ldr q1, [x1, x2, lsl #4]
; CHECK: ldr b1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x3c]
; CHECK: ldr b1, [x1, x2, lsl #0] ; encoding: [0x21,0x78,0x62,0x3c]
; CHECK: ldr h1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x7c]
; CHECK: ldr h1, [x1, x2, lsl #1] ; encoding: [0x21,0x78,0x62,0x7c]
; CHECK: ldr s1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xbc]
; CHECK: ldr s1, [x1, x2, lsl #2] ; encoding: [0x21,0x78,0x62,0xbc]
; CHECK: ldr d1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xfc]
; CHECK: ldr d1, [x1, x2, lsl #3] ; encoding: [0x21,0x78,0x62,0xfc]
; CHECK: ldr q1, [x1, x2] ; encoding: [0x21,0x68,0xe2,0x3c]
; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c]
str d1, [sp, x3]
str d1, [sp, w3, uxtw #3]
str q1, [sp, x3]
str q1, [sp, w3, uxtw #4]
; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc]
; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc]
; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c]
; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c]
;-----------------------------------------------------------------------------
; Load literal
;-----------------------------------------------------------------------------
ldr w5, foo
ldr x4, foo
ldrsw x9, foo
prfm #5, foo
; CHECK: ldr w5, foo ; encoding: [0bAAA00101,A,A,0x18]
; CHECK: ldr x4, foo ; encoding: [0bAAA00100,A,A,0x58]
; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98]
; CHECK: prfm pldl3strm, foo ; encoding: [0bAAA00101,A,A,0xd8]
;-----------------------------------------------------------------------------
; Load/Store exclusive
;-----------------------------------------------------------------------------
ldxr w6, [x1]
ldxr x6, [x1]
ldxrb w6, [x1]
ldxrh w6, [x1]
ldxp w7, w3, [x9]
ldxp x7, x3, [x9]
; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08]
; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48]
; CHECK: ldxp w7, w3, [x9] ; encoding: [0x27,0x0d,0x7f,0x88]
; CHECK: ldxp x7, x3, [x9] ; encoding: [0x27,0x0d,0x7f,0xc8]
stxr w1, x4, [x3]
stxr w1, w4, [x3]
stxrb w1, w4, [x3]
stxrh w1, w4, [x3]
stxp w1, x2, x6, [x1]
stxp w1, w2, w6, [x1]
; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
; CHECK: stxrb w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x08]
; CHECK: stxrh w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x48]
; CHECK: stxp w1, x2, x6, [x1] ; encoding: [0x22,0x18,0x21,0xc8]
; CHECK: stxp w1, w2, w6, [x1] ; encoding: [0x22,0x18,0x21,0x88]
;-----------------------------------------------------------------------------
; Load-acquire/Store-release non-exclusive
;-----------------------------------------------------------------------------
ldar w4, [sp]
ldar x4, [sp, #0]
ldarb w4, [sp]
ldarh w4, [sp]
; CHECK: ldar w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x88]
; CHECK: ldar x4, [sp] ; encoding: [0xe4,0xff,0xdf,0xc8]
; CHECK: ldarb w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x08]
; CHECK: ldarh w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x48]
stlr w3, [x6]
stlr x3, [x6]
stlrb w3, [x6]
stlrh w3, [x6]
; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88]
; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8]
; CHECK: stlrb w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x08]
; CHECK: stlrh w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x48]
;-----------------------------------------------------------------------------
; Load-acquire/Store-release exclusive
;-----------------------------------------------------------------------------
ldaxr w2, [x4]
ldaxr x2, [x4]
ldaxrb w2, [x4, #0]
ldaxrh w2, [x4]
ldaxp w2, w6, [x1]
ldaxp x2, x6, [x1]
; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
; CHECK: ldaxrb w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x08]
; CHECK: ldaxrh w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x48]
; CHECK: ldaxp w2, w6, [x1] ; encoding: [0x22,0x98,0x7f,0x88]
; CHECK: ldaxp x2, x6, [x1] ; encoding: [0x22,0x98,0x7f,0xc8]
stlxr w8, x7, [x1]
stlxr w8, w7, [x1]
stlxrb w8, w7, [x1]
stlxrh w8, w7, [x1]
stlxp w1, x2, x6, [x1]
stlxp w1, w2, w6, [x1]
; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
; CHECK: stlxrb w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x08]
; CHECK: stlxrh w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x48]
; CHECK: stlxp w1, x2, x6, [x1] ; encoding: [0x22,0x98,0x21,0xc8]
; CHECK: stlxp w1, w2, w6, [x1] ; encoding: [0x22,0x98,0x21,0x88]
;-----------------------------------------------------------------------------
; LDUR/STUR aliases for negative and unaligned LDR/STR instructions.
;
; According to the ARM ISA documentation:
; "A programmer-friendly assembler should also generate these instructions
; in response to the standard LDR/STR mnemonics when the immediate offset is
; unambiguous, i.e. negative or unaligned."
;-----------------------------------------------------------------------------
ldr x11, [x29, #-8]
ldr x11, [x29, #7]
ldr w0, [x0, #2]
ldr w0, [x0, #-256]
ldr b2, [x1, #-2]
ldr h3, [x2, #3]
ldr h3, [x3, #-4]
ldr s3, [x4, #3]
ldr s3, [x5, #-4]
ldr d4, [x6, #4]
ldr d4, [x7, #-8]
ldr q5, [x8, #8]
ldr q5, [x9, #-16]
; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8]
; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
; CHECK: ldur h3, [x2, #3] ; encoding: [0x43,0x30,0x40,0x7c]
; CHECK: ldur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x5f,0x7c]
; CHECK: ldur s3, [x4, #3] ; encoding: [0x83,0x30,0x40,0xbc]
; CHECK: ldur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x5f,0xbc]
; CHECK: ldur d4, [x6, #4] ; encoding: [0xc4,0x40,0x40,0xfc]
; CHECK: ldur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x5f,0xfc]
; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
str x11, [x29, #-8]
str x11, [x29, #7]
str w0, [x0, #2]
str w0, [x0, #-256]
str b2, [x1, #-2]
str h3, [x2, #3]
str h3, [x3, #-4]
str s3, [x4, #3]
str s3, [x5, #-4]
str d4, [x6, #4]
str d4, [x7, #-8]
str q5, [x8, #8]
str q5, [x9, #-16]
; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8]
; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
; CHECK: stur h3, [x2, #3] ; encoding: [0x43,0x30,0x00,0x7c]
; CHECK: stur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x1f,0x7c]
; CHECK: stur s3, [x4, #3] ; encoding: [0x83,0x30,0x00,0xbc]
; CHECK: stur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x1f,0xbc]
; CHECK: stur d4, [x6, #4] ; encoding: [0xc4,0x40,0x00,0xfc]
; CHECK: stur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x1f,0xfc]
; CHECK: stur q5, [x8, #8] ; encoding: [0x05,0x81,0x80,0x3c]
; CHECK: stur q5, [x9, #-16] ; encoding: [0x25,0x01,0x9f,0x3c]
ldrb w3, [x1, #-1]
ldrh w4, [x2, #1]
ldrh w5, [x3, #-1]
ldrsb w6, [x4, #-1]
ldrsb x7, [x5, #-1]
ldrsh w8, [x6, #1]
ldrsh w9, [x7, #-1]
ldrsh x1, [x8, #1]
ldrsh x2, [x9, #-1]
ldrsw x3, [x10, #10]
ldrsw x4, [x11, #-1]
; CHECK: ldurb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x5f,0x38]
; CHECK: ldurh w4, [x2, #1] ; encoding: [0x44,0x10,0x40,0x78]
; CHECK: ldurh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x5f,0x78]
; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38]
; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38]
; CHECK: ldursh w8, [x6, #1] ; encoding: [0xc8,0x10,0xc0,0x78]
; CHECK: ldursh w9, [x7, #-1] ; encoding: [0xe9,0xf0,0xdf,0x78]
; CHECK: ldursh x1, [x8, #1] ; encoding: [0x01,0x11,0x80,0x78]
; CHECK: ldursh x2, [x9, #-1] ; encoding: [0x22,0xf1,0x9f,0x78]
; CHECK: ldursw x3, [x10, #10] ; encoding: [0x43,0xa1,0x80,0xb8]
; CHECK: ldursw x4, [x11, #-1] ; encoding: [0x64,0xf1,0x9f,0xb8]
strb w3, [x1, #-1]
strh w4, [x2, #1]
strh w5, [x3, #-1]
; CHECK: sturb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x1f,0x38]
; CHECK: sturh w4, [x2, #1] ; encoding: [0x44,0x10,0x00,0x78]
; CHECK: sturh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x1f,0x78]
| {
"language": "Assembly"
} |
/*
Copyright (c) 2017, Lawrence Livermore National Security, LLC.
Produced at the Lawrence Livermore National Laboratory
Written by Chunhua Liao, Pei-Hung Lin, Joshua Asplund,
Markus Schordan, and Ian Karlin
(email: liao6@llnl.gov, lin32@llnl.gov, asplund1@llnl.gov,
schordan1@llnl.gov, karlin1@llnl.gov)
LLNL-CODE-732144
All rights reserved.
This file is part of DataRaceBench. For details, see
https://github.com/LLNL/dataracebench. Please also see the LICENSE file
for our additional BSD notice.
Redistribution and use in source and binary forms, with
or without modification, are permitted provided that the following
conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the disclaimer below.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the disclaimer (as noted below)
in the documentation and/or other materials provided with the
distribution.
* Neither the name of the LLNS/LLNL nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LAWRENCE LIVERMORE NATIONAL
SECURITY, LLC, THE U.S. DEPARTMENT OF ENERGY OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Data race on outLen due to ++ operation.
Adding private (outLen) can avoid race condition. But it is wrong semantically.
Data races on outLen also cause output[outLen++] to have data races.
Data race pairs (we allow two pairs to preserve the original code pattern):
1. outLen@72 vs. outLen@72
2. output[]@72 vs. output[]@72
*/
#include <stdlib.h>
#include <stdio.h>
int input[1000];
int output[1000];
int main()
{
int i ;
int inLen=1000 ;
int outLen = 0;
for (i=0; i<inLen; ++i)
input[i]= i;
#pragma omp parallel for
for (i=0; i<inLen; ++i)
{
output[outLen++] = input[i] ;
}
printf("output[500]=%d\n",output[500]);
return 0;
}
| {
"language": "Assembly"
} |
/*
* Syscalls for uClibc
*
* Copyright (C) 2000-2006 Erik Andersen <andersen@uclibc.org>
*
* Licensed under the LGPL v2.1, see the file COPYING.LIB in this tarball.
*/
/* Extracted from ../common/syscalls.c by Erik Andersen <andersen@codepoet.org>
* Adapted to FR-V by Alexandre Oliva <aoliva@redhat.com>
*/
#include <sys/syscall.h>
#include <unistd.h>
#include <sys/stat.h>
_syscall2(int, stat, const char *, file_name, struct stat *, buf)
libc_hidden_def(stat)
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -E -std=c++11 -o - %s | FileCheck %s
#define id(x) x
id("s")_x // CHECK: "s" _x
id(L"s")_x // CHECK: L"s" _x
id(u8"s")_x // CHECK: u8"s" _x
id(u"s")_x // CHECK: u"s" _x
id(U"s")_x // CHECK: U"s" _x
id('s')_x // CHECK: 's' _x
id(L's')_x // CHECK: L's' _x
id(u's')_x // CHECK: u's' _x
id(U's')_x // CHECK: U's' _x
id("s"_x)_y // CHECK: "s"_x _y
id(1.0_)f // CHECK: 1.0_ f
id(1.0)_f // CHECK: 1.0 _f
id(0xface+)b_count // CHECK: 0xface+ b_count
id("s")1 // CHECK: "s"1
id("s"_x)1 // CHECK: "s"_x 1
id(1)_2_x // CHECK: 1 _2_x
| {
"language": "Assembly"
} |
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
| {
"language": "Assembly"
} |
#
! $Source$
! $State$
! $Revision$
! Declare segments (the order is important).
.sect .text
.sect .rom
.sect .data
.sect .bss
.sect .text
! ****** WARNING! ******
!
! The PC boot sector requires a magic number at the end to signify that the
! disk is bootable. Unfortunately, the ACK assembler is a bit simple and we
! can't tell it to put the 0xAA55 at a particular address without writing our
! own custom binary generator. As a result, we need to manually insert just
! the right amount of padding in order to make this work.
!
! If you ever need to change the boot code, this needs adjusting. I recommend
! a hex editor.
PADDING = 0xB3
! Some definitions.
BOOT_SEGMENT = 0x07C0 ! Where we've been loaded
#define PRINT(N) push ax; push bx; movb ah, 0x0E; movb al, N; mov bx, 0x0007; int 0x10; pop bx; pop ax
begtext:
! This code makes up the PC boot sector, and is the first thing on the
! floppy disk. The PC will load this sector to 0x07C0:0000 and jump to it
! with dl set to our drive, but it won't necessarily do it in a sane way
! (some BIOSes jump to 0x0000:7C00 instead). So, we need to fix that.
jmpf BOOT_SEGMENT : start2
start2:
! Set up the segment descriptors. We're running in tiny mode, so it's just
! a matter of copying the contents of cs (already been set up by the jmpf)
! into the other registers.
mov ax, cs
mov ds, ax
mov ss, ax
! Defer setting es until after probing the drive.
! Initialise the stack, which will start at the top of our segment and work
! down.
mov sp, 0 ! the first push will wrap round to 0xFFFF
! Some more startup housekeeping.
sti
cld
! We're now set up for actual code. Write out our banner. Remember that
! at this point dl contains our drive number, which we want to keep.
mov si, banner_msg
call write_string
! Probe the drive to figure out its geometry.
! This might clobber es.
push dx
mov ax, 0x0800 ! service number
int 0x13
mov ax, cs ! restore es
mov es, ax
pop ax
jc cant_boot
! At this point:
! al: current drive
! cl: maximum sector number (bottom six bits)
! dh: maximum head number
! We don't care about the rest.
andb cl, 0x3F
! We now need to go through a loop loading each sector in turn.
! During this loop, the registers will be set up as follows:
! al: current cylinder
! ah: maximum head
! bx: address
! cl: current sector (one based)
! ch: maximum sector (one based)
! dl: current drive
! dh: current head
! Why, yes, they are painstakingly shoehorned in to get all the data
! into registers.
movb dl, al
movb ch, cl
movb ah, dh
movb al, 0 ! start on cylinder 0
mov bx, 0x0200 ! don't overwrite boot sector
movb cl, 2 ! start on sector 2 (skip boot sector)
movb dh, 0 ! start on head 0
1:
call read_sector
! Next memory area.
add bx, 0x0200
cmp bx, enddata
ja finished
! Next sector.
incb cl
cmpb cl, ch
jle 1b
movb cl, 1 ! back to sector 1 again
! Next head.
incb dh
cmpb dh, ah
jle 1b
movb dh, 0 ! back to head 1 again
! Next cylinder.
incb al
jmp 1b
cant_boot:
mov si, bootfail_msg
call write_string
jmp EXIT
! Reads a sector into memory. The parameters are:
! al: cylinder
! bx: address
! cl: sector
! dl: drive
! dh: head
! If an error occurs, it'll automatically try again. And again.
! And again...
read_sector:
push ax
push bx
push cx
push dx
#if 0
push dx
xorb dh, dh
movb dl, cl
call write_hex4
pop dx
PRINT(0x20)
push dx
movb dl, dh
xorb dh, dh
call write_hex4
pop dx
PRINT(0x20)
push dx
movb dl, al
xorb dh, dh
call write_hex4
pop dx
#endif
1:
movb ch, al
mov ax, 0x0201 ! service 2, read one sector
int 0x13
jc 2f
mov ax, 0x0E2E ! write out a .
mov bx, 0x0007 ! page 0, white
int 0x10
pop dx
pop cx
pop bx
pop ax
ret
! If a read fail occurs, the spec (such as it is) states that we need
! to reset the fd controller and try again.
2:
push ax
push bx
mov ax, 0x0E21 ! write out a !
mov bx, 0x0007 ! page 0, white
int 0x10
mov ax, 0x0000
int 0x13
pop bx
pop ax
jmp 1b
! Waits for a keystroke (and then discards it).
pause:
push ax
xorb ah, ah
int 0x16
pop ax
ret
! This utility writes the string pointed to by ds:si out to the console.
write_string:
push ax
push bx
1:
lodsb
andb al, al
jz 2f
movb ah, 0xE ! service
mov bx, 0x0007 ! page 0, white
int 0x10
jmp 1b
2:
pop bx
pop ax
ret
! Writes out the contents of dx as hex.
write_hex4:
push ax
push cx
mov cx, 4 ! 4 hex digits
1:
rol dx, 1 ! rotate so that highest 4 bits are at the bottom
rol dx, 1
rol dx, 1
rol dx, 1
mov ax, 0xE0F ! ah = request, al = mask for nybble
andb al, dl
addb al, 0x90 ! convert al to ascii hex (four instructions)
daa
adcb al, 0x40
daa
int 0x10
loop 1b
pop cx
pop ax
ret
! Everything loaded successfully!
!
! We now need to do some setup and start the program itself.
finished:
mov si, running_msg
call write_string
! Wipe the bss. (I'm a little suprised that __m_a_i_n doesn't do this.)
mov di, begbss
mov cx, endbss
sub cx, di
mov ax, 0
rep stosb
! Push standard parameters onto the stack and go.
mov ax, envp
push ax
mov ax, argv
push ax
mov ax, 1
push ax
call __m_a_i_n
! fall through into the exit routine.
! Halts, waits for a keypress, and reboots. This also becomes the
! application termination routine.
.define __exit
.extern __exit
.define EXIT
.extern EXIT
__exit:
EXIT:
mov si, halted_msg
call write_string
1:
jmp 1b
xor ax, ax
int 0x16 ! get key
int 0x19 ! reboot
! Some text messages.
banner_msg: .asciz 'ACKBOOT\n\r'
nl_msg = banner_msg + 7 ! cheap trick
bootfail_msg: .asciz 'Unable to boot!\n\r'
loading_msg: .asciz '\n\rLoading...\n\r'
halted_msg: .asciz '\n\rHalted.\n\r'
running_msg: .asciz '\n\rRunning.\n\r'
! The argv and env arrays.
argv: .data2 exename, 0
envp: .data2 0
exename: .asciz 'pc86.img'
! ...and we need this to fool the PC into booting our boot sector.
.space PADDING
.data2 0xAA55
! Define symbols at the beginning of our various segments, so that we can find
! them. (Except .text, which has already been done.)
.define begtext, begdata, begbss
.sect .data; begdata:
.sect .rom; begrom:
.sect .bss; begbss:
! Some magic data. All EM systems need these.
.define .trppc, .ignmask, _errno
.comm .trppc, 4
.comm .ignmask, 4
.comm _errno, 4
| {
"language": "Assembly"
} |
////////////////////////////////////////////////////////////////////////////////
///////////////////InstallShield Media Library Report Summary///////////////////
////////////////////////////////////////////////////////////////////////////////
Media Name : CD-ROM
Report Filename : D:\My Installations\Executor-Win32 Demo\Media\CD-ROM\Report Files\4-06-1998 2.53.17PM.rpt
Date : 04/06/1998
Time : 2:53PM
Number of Components: 5
Number of File Groups: 5
Number of Files: 129
Total Size of Files: 11,147,702 (bytes)
==========
COMPONENTS
==========
Executor Component
CD Enable
CD vxd
NT CD Enable
NT CD sys files
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////Report Details/////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
================================================================================
COMPONENT: "Executor Component"
================================================================================
SUMMARY:
Total Files: 125 (files for this component only)
Source Bytes: 11,100,982 (files for this component only)
**** File Group: "Executor Files" ****
<Directory>: I:\execwin32.demo
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
executor.lnk 11/11/1997 19:01:14 308
extemp.hfv 06/10/1997 18:43:12 2,097,152
hfv16dll.dll 11/06/1997 20:28:18 1,792
hfv32.dll 11/06/1997 20:26:00 26,624
makehfv.exe 08/11/1996 22:12:46 110,108
printdef.ini 10/01/1997 22:32:20 99
printers.ini 12/30/1997 11:40:40 2,021
readme.txt 11/24/1997 18:41:22 1,404
tips.txt 01/08/1998 17:02:18 2,584
executor.exe 04/06/1998 14:45:36 1,996,288
SDL-dx5.dll 04/04/1998 17:51:24 105,629
SDL-dib.dll 04/04/1998 17:51:24 83,403
exsystem.hfv 12/01/1997 21:41:46 6,291,456
stdout.txt 04/06/1998 13:57:20 0
stderr.txt 04/06/1998 13:57:18 0
-------------------------- ---------- -------- ----------- -------------
Count=15 10,718,868
<Directory>: I:\execwin32.demo\configur
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
32362e32.ecf 10/21/1997 16:21:34 330
3842494d.ecf 10/21/1997 16:21:34 436
3f3f3f3f.ecf 10/21/1997 16:21:34 366
41443344.ecf 10/21/1997 16:21:34 344
414f7163.ecf 10/21/1997 16:21:34 357
41525435.ecf 10/21/1997 16:21:34 455
41527c46.ecf 10/21/1997 16:21:34 328
4154726e.ecf 10/21/1997 16:21:34 343
4164426b.ecf 10/21/1997 16:21:34 326
41706569.ecf 10/21/1997 16:21:34 339
42454132.ecf 10/21/1997 16:21:34 344
424f4c4f.ecf 10/21/1997 16:21:34 310
426163d5.ecf 10/21/1997 16:21:34 365
42646c6d.ecf 10/21/1997 16:21:34 372
426e4871.ecf 10/21/1997 16:21:34 324
43475246.ecf 10/21/1997 16:21:34 348
43504354.ecf 10/21/1997 16:21:34 316
4352534c.ecf 10/21/1997 16:21:34 359
4354494d.ecf 10/21/1997 16:21:34 370
43555341.ecf 10/21/1997 16:21:34 357
43574c44.ecf 10/21/1997 16:21:34 361
43595153.ecf 10/21/1997 16:21:34 126
43764d4d.ecf 10/21/1997 16:21:34 312
4444534b.ecf 10/21/1997 16:21:34 357
44454c49.ecf 10/21/1997 16:21:34 349
44494132.ecf 10/21/1997 16:21:34 227
444f4c4c.ecf 10/21/1997 16:21:34 350
44576174.ecf 10/21/1997 16:21:34 348
44616e47.ecf 10/21/1997 16:21:34 126
454a3035.ecf 10/21/1997 16:21:34 312
45535041.ecf 10/21/1997 16:21:34 332
455544c6.ecf 10/21/1997 16:21:34 280
46424420.ecf 10/21/1997 16:21:34 334
466c6974.ecf 10/21/1997 16:21:34 338
46756e47.ecf 10/21/1997 16:21:34 331
47436f6e.ecf 10/21/1997 16:21:34 430
474f474f.ecf 10/21/1997 16:21:34 340
47534361.ecf 10/21/1997 16:21:34 334
47756e53.ecf 10/21/1997 16:21:34 126
483444c6.ecf 10/21/1997 16:21:34 362
48525630.ecf 10/21/1997 16:21:34 374
48525631.ecf 10/21/1997 16:21:34 375
48734c61.ecf 10/21/1997 16:21:34 337
496d6167.ecf 10/21/1997 16:21:34 343
4a4b5445.ecf 10/21/1997 16:21:34 126
4a524735.ecf 10/21/1997 16:21:34 343
4a70616b.ecf 10/21/1997 16:21:34 323
4b705353.ecf 10/21/1997 16:21:34 328
4c415a48.ecf 10/21/1997 16:21:34 273
4c505243.ecf 10/21/1997 16:21:34 324
4d427264.ecf 10/21/1997 16:21:34 364
4d4b444e.ecf 10/21/1997 16:21:34 165
4d4d4343.ecf 10/21/1997 16:21:34 347
4d4d5042.ecf 10/21/1997 16:21:34 363
4d504e54.ecf 10/21/1997 16:21:34 265
4d535744.ecf 10/21/1997 16:21:34 331
4d61656c.ecf 10/21/1997 16:21:34 337
4d687a75.ecf 10/21/1997 16:21:34 351
4d6f6c54.ecf 10/21/1997 16:21:34 321
50217268.ecf 10/21/1997 16:21:34 276
50474150.ecf 10/21/1997 16:21:34 336
504c5073.ecf 10/21/1997 16:21:34 272
504e4331.ecf 10/21/1997 16:21:34 157
50505456.ecf 10/21/1997 16:21:34 333
50566d74.ecf 10/21/1997 16:21:34 126
50674c67.ecf 10/21/1997 16:21:34 364
506fc450.ecf 10/21/1997 16:21:34 432
50736f64.ecf 10/21/1997 16:21:34 392
51444c58.ecf 10/21/1997 16:21:34 331
522a6368.ecf 10/21/1997 16:21:34 371
52415a5a.ecf 10/21/1997 16:21:34 334
5249534b.ecf 10/21/1997 16:21:34 336
524a4253.ecf 10/21/1997 16:21:34 175
524c4d5a.ecf 10/21/1997 16:21:34 417
52565253.ecf 10/21/1997 16:21:34 126
526a3031.ecf 10/21/1997 16:21:34 324
53414e54.ecf 10/21/1997 16:21:34 329
53495421.ecf 10/21/1997 16:21:34 374
53495478.ecf 10/21/1997 16:21:34 329
534d4c53.ecf 10/21/1997 16:21:34 326
53635246.ecf 10/21/1997 16:21:34 373
5368537a.ecf 10/21/1997 16:21:34 126
53704a4b.ecf 10/21/1997 16:21:34 337
53706563.ecf 10/21/1997 16:21:34 324
5370696e.ecf 10/21/1997 16:21:34 320
54424235.ecf 10/21/1997 16:21:34 338
54424236.ecf 10/21/1997 16:21:34 335
544b4e4f.ecf 10/21/1997 16:21:34 166
54745264.ecf 10/21/1997 16:21:36 165
54775231.ecf 10/21/1997 16:21:36 321
55505550.ecf 10/21/1997 16:21:36 329
556c7433.ecf 10/21/1997 16:21:36 364
57435345.ecf 10/21/1997 16:21:36 320
574f4c46.ecf 10/21/1997 16:21:36 363
57504332.ecf 10/21/1997 16:21:36 323
5843454c.ecf 10/21/1997 16:21:36 323
58505233.ecf 10/21/1997 16:21:36 362
63417244.ecf 10/21/1997 16:21:36 345
674f4c46.ecf 10/21/1997 16:21:36 353
6c6f6733.ecf 10/21/1997 16:21:36 329
6f7a6d35.ecf 10/21/1997 16:21:36 346
72647020.ecf 10/21/1997 16:21:36 324
72706db5.ecf 10/21/1997 16:21:36 360
73506433.ecf 10/21/1997 16:21:36 322
a78ea8a0.ecf 10/21/1997 16:21:36 328
a7bfc2a2.ecf 10/21/1997 16:21:36 320
ac7e5ea0.ecf 10/21/1997 16:21:36 126
f5536b69.ecf 10/21/1997 16:21:36 350
-------------------------- ---------- -------- ----------- -------------
Count=108 34,306
<Directory>: I:\execwin32.demo\splash
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
splash.1bp 08/11/1996 23:12:46 38,488
splash.8bp 09/30/1997 09:52:14 309,320
-------------------------- ---------- -------- ----------- -------------
Count=2 347,808
================================================================================
COMPONENT: "CD Enable"
================================================================================
SUMMARY:
Total Files: 1 (files for this component only)
Source Bytes: 11,126,582 (files for this component only)
**** File Group: "CD Enable" ****
<Directory>: I:\execwin32.demo
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
cdenable.exe 11/11/1997 03:13:12 25,600
-------------------------- ---------- -------- ----------- -------------
Count=1 25,600
================================================================================
COMPONENT: "CD Enable\CD vxd"
================================================================================
SUMMARY:
Total Files: 1 (files for this component only)
Source Bytes: 11,136,470 (files for this component only)
**** File Group: "CD vxd" ****
<Directory>: I:\execwin32.demo
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
cdenable.vxd 03/13/1998 00:51:16 9,888
-------------------------- ---------- -------- ----------- -------------
Count=1 9,888
================================================================================
COMPONENT: "NT CD Enable"
================================================================================
SUMMARY:
Total Files: 1 (files for this component only)
Source Bytes: 11,141,590 (files for this component only)
**** File Group: "cdenableNT exe" ****
<Directory>: I:\execwin32.demo
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
cdenablent.exe 11/22/1997 17:34:00 5,120
-------------------------- ---------- -------- ----------- -------------
Count=1 5,120
================================================================================
COMPONENT: "NT CD Enable\NT CD sys files"
================================================================================
SUMMARY:
Total Files: 1 (files for this component only)
Source Bytes: 11,147,702 (files for this component only)
**** File Group: "cdenableNT sys" ****
<Directory>: I:\execwin32.demo
Filename Date Time Size Version
-------------------------- ---------- -------- ----------- -------------
cdenable.sys 11/18/1997 05:05:52 6,112
-------------------------- ---------- -------- ----------- -------------
Count=1 6,112
| {
"language": "Assembly"
} |
/*
*****************************************************************************
**
** File : LinkerScript.ld
**
** Abstract : Linker script for STM32F401VCTx Device with
** 256KByte FLASH, 64KByte RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
** (c)Copyright Ac6.
** You may use this file as-is or modify it according to the needs of your
** project. Distribution of this file (unmodified or modified) is not
** permitted. Ac6 permit registered System Workbench for MCU users the
** rights to distribute the assembled, compiled & linked contents of this
** file as part of an application binary file, provided that it is built
** using the System Workbench for MCU toolchain.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20010000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200;; /* required amount of heap */
_Min_Stack_Size = 0x400;; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
/*
* This file is part of the OregonCore Project. See AUTHORS file for Copyright information
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <https://www.gnu.org/licenses/>.
*/
#include "ScriptPCH.h"
| {
"language": "Assembly"
} |
/* -*- Mode: C++; tab-width: 4; indent-tabs-mode: nil; c-basic-offset: 4 -*- */
/*
* This file is part of the LibreOffice project.
*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at http://mozilla.org/MPL/2.0/.
*
* This file incorporates work covered by the following license notice:
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed
* with this work for additional information regarding copyright
* ownership. The ASF licenses this file to you under the Apache
* License, Version 2.0 (the "License"); you may not use this file
* except in compliance with the License. You may obtain a copy of
* the License at http://www.apache.org/licenses/LICENSE-2.0 .
*/
#ifndef __com_sun_star_sheet_SubTotalFieldsEnumeration_idl__
#define __com_sun_star_sheet_SubTotalFieldsEnumeration_idl__
#include <com/sun/star/container/XEnumeration.idl>
module com { module sun { module star { module sheet {
/** represents an enumeration of sub total fields.
@see com::sun::star::sheet::SubTotalField
*/
published service SubTotalFieldsEnumeration
{
/** provides methods to access the sub total fields in the enumeration.
@see com::sun::star::sheet::SubTotalField
*/
interface com::sun::star::container::XEnumeration;
};
}; }; }; };
#endif
/* vim:set shiftwidth=4 softtabstop=4 expandtab: */
| {
"language": "Assembly"
} |
[bits 32]
[CPU intelnop]
; Copyright (c) 2010, Intel Corporation
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; * Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; * Neither the name of Intel Corporation nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
; BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
align 16
global _do_rdtsc
_do_rdtsc:
rdtsc
ret
| {
"language": "Assembly"
} |
//============
// N64 Header
//============
// PI_BSB_DOM1
db $80 // Initial PI_BSB_DOM1_LAT_REG Value
db $37 // Initial PI_BSB_DOM1_PGS_REG Value
db $12 // Initial PI_BSB_DOM1_PWD_REG Value
db $40 // Initial PI_BSB_DOM1_PGS_REG Value
// CLOCK RATE
dw $000F // Initial Clock Rate
// VECTOR
dw Start // Boot Address Offset
dw $1444 // Release Offset
// COMPLEMENT CHECK & CHECKSUM
db "CRC1" // CRC1: COMPLEMENT CHECK
db "CRC2" // CRC2: CHECKSUM
dd 0 // UNUSED
// PROGRAM TITLE (27 Byte ASCII String, Use Spaces For Unused Bytes)
db "CPU TEST CPU LW "
// "123456789012345678901234567"
// DEVELOPER ID CODE
db $00 // "N" = Nintendo
// CARTRIDGE ID CODE
db $00
db 0 // UNUSED
// COUNTRY CODE
db $00 // "D" = Germany, "E" = USA, "J" = Japan, "P" = Europe, "U" = Australia
db 0 // UNUSED | {
"language": "Assembly"
} |
.include "macro.inc"
# assembler directives
.set noat # allow manual use of $at
.set noreorder # don't insert nops after branches
.set gp=64 # allow use of 64-bit general purposee registers
.section .text
.align 4
glabel func_800B34E0
/* B2A680 800B34E0 90820000 */ lbu $v0, ($a0)
/* B2A684 800B34E4 24010001 */ li $at, 1
/* B2A688 800B34E8 10400011 */ beqz $v0, .L800B3530
/* B2A68C 800B34EC 00000000 */ nop
/* B2A690 800B34F0 10410005 */ beq $v0, $at, .L800B3508
/* B2A694 800B34F4 24010002 */ li $at, 2
/* B2A698 800B34F8 5041000D */ beql $v0, $at, .L800B3530
/* B2A69C 800B34FC A0800007 */ sb $zero, 7($a0)
/* B2A6A0 800B3500 1000000B */ b .L800B3530
/* B2A6A4 800B3504 00000000 */ nop
.L800B3508:
/* B2A6A8 800B3508 908E0002 */ lbu $t6, 2($a0)
/* B2A6AC 800B350C A4800008 */ sh $zero, 8($a0)
/* B2A6B0 800B3510 240F00FF */ li $t7, 255
/* B2A6B4 800B3514 11C00003 */ beqz $t6, .L800B3524
/* B2A6B8 800B3518 00000000 */ nop
/* B2A6BC 800B351C 10000004 */ b .L800B3530
/* B2A6C0 800B3520 A08F0007 */ sb $t7, 7($a0)
.L800B3524:
/* B2A6C4 800B3524 10000002 */ b .L800B3530
/* B2A6C8 800B3528 A0800007 */ sb $zero, 7($a0)
/* B2A6CC 800B352C A0800007 */ sb $zero, 7($a0)
.L800B3530:
/* B2A6D0 800B3530 03E00008 */ jr $ra
/* B2A6D4 800B3534 A0800001 */ sb $zero, 1($a0)
glabel func_800B3538
/* B2A6D8 800B3538 27BDFFE8 */ addiu $sp, $sp, -0x18
/* B2A6DC 800B353C AFBF0014 */ sw $ra, 0x14($sp)
/* B2A6E0 800B3540 AFA40018 */ sw $a0, 0x18($sp)
/* B2A6E4 800B3544 0C001114 */ jal bzero
/* B2A6E8 800B3548 2405000C */ li $a1, 12
/* B2A6EC 800B354C 8FBF0014 */ lw $ra, 0x14($sp)
/* B2A6F0 800B3550 8FA20018 */ lw $v0, 0x18($sp)
/* B2A6F4 800B3554 27BD0018 */ addiu $sp, $sp, 0x18
/* B2A6F8 800B3558 03E00008 */ jr $ra
/* B2A6FC 800B355C 00000000 */ nop
glabel func_800B3560
/* B2A700 800B3560 03E00008 */ jr $ra
/* B2A704 800B3564 AFA40000 */ sw $a0, ($sp)
glabel func_800B3568
/* B2A708 800B3568 27BDFFD0 */ addiu $sp, $sp, -0x30
/* B2A70C 800B356C AFBF0014 */ sw $ra, 0x14($sp)
/* B2A710 800B3570 90820000 */ lbu $v0, ($a0)
/* B2A714 800B3574 00803825 */ move $a3, $a0
/* B2A718 800B3578 24010001 */ li $at, 1
/* B2A71C 800B357C 50400063 */ beql $v0, $zero, .L800B370C
/* B2A720 800B3580 8FBF0014 */ lw $ra, 0x14($sp)
/* B2A724 800B3584 10410005 */ beq $v0, $at, .L800B359C
/* B2A728 800B3588 24010002 */ li $at, 2
/* B2A72C 800B358C 50410037 */ beql $v0, $at, .L800B366C
/* B2A730 800B3590 90ED0007 */ lbu $t5, 7($a3)
/* B2A734 800B3594 1000005D */ b .L800B370C
/* B2A738 800B3598 8FBF0014 */ lw $ra, 0x14($sp)
.L800B359C:
/* B2A73C 800B359C 94EE0008 */ lhu $t6, 8($a3)
/* B2A740 800B35A0 3C028016 */ lui $v0, %hi(gSaveContext+0x1418) # $v0, 0x8016
/* B2A744 800B35A4 3C048014 */ lui $a0, %hi(D_801430C0) # $a0, 0x8014
/* B2A748 800B35A8 01C57821 */ addu $t7, $t6, $a1
/* B2A74C 800B35AC A4EF0008 */ sh $t7, 8($a3)
/* B2A750 800B35B0 9042FA78 */ lbu $v0, %lo(gSaveContext+0x1418)($v0)
/* B2A754 800B35B4 31F8FFFF */ andi $t8, $t7, 0xffff
/* B2A758 800B35B8 24190001 */ li $t9, 1
/* B2A75C 800B35BC 0302082A */ slt $at, $t8, $v0
/* B2A760 800B35C0 14200005 */ bnez $at, .L800B35D8
/* B2A764 800B35C4 248430C0 */ addiu $a0, %lo(D_801430C0) # addiu $a0, $a0, 0x30c0
/* B2A768 800B35C8 A4E20008 */ sh $v0, 8($a3)
/* B2A76C 800B35CC 3C028016 */ lui $v0, %hi(gSaveContext+0x1418) # $v0, 0x8016
/* B2A770 800B35D0 A0F90001 */ sb $t9, 1($a3)
/* B2A774 800B35D4 9042FA78 */ lbu $v0, %lo(gSaveContext+0x1418)($v0)
.L800B35D8:
/* B2A778 800B35D8 54400007 */ bnezl $v0, .L800B35F8
/* B2A77C 800B35DC 94E80008 */ lhu $t0, 8($a3)
/* B2A780 800B35E0 0C00084C */ jal osSyncPrintf
/* B2A784 800B35E4 AFA70030 */ sw $a3, 0x30($sp)
/* B2A788 800B35E8 3C028016 */ lui $v0, %hi(gSaveContext+0x1418) # $v0, 0x8016
/* B2A78C 800B35EC 9042FA78 */ lbu $v0, %lo(gSaveContext+0x1418)($v0)
/* B2A790 800B35F0 8FA70030 */ lw $a3, 0x30($sp)
/* B2A794 800B35F4 94E80008 */ lhu $t0, 8($a3)
.L800B35F8:
/* B2A798 800B35F8 3C01437F */ li $at, 0x437F0000 # 0.000000
/* B2A79C 800B35FC 44812000 */ mtc1 $at, $f4
/* B2A7A0 800B3600 44883000 */ mtc1 $t0, $f6
/* B2A7A4 800B3604 44829000 */ mtc1 $v0, $f18
/* B2A7A8 800B3608 05010005 */ bgez $t0, .L800B3620
/* B2A7AC 800B360C 46803220 */ cvt.s.w $f8, $f6
/* B2A7B0 800B3610 3C014F80 */ li $at, 0x4F800000 # 0.000000
/* B2A7B4 800B3614 44815000 */ mtc1 $at, $f10
/* B2A7B8 800B3618 00000000 */ nop
/* B2A7BC 800B361C 460A4200 */ add.s $f8, $f8, $f10
.L800B3620:
/* B2A7C0 800B3620 46082402 */ mul.s $f16, $f4, $f8
/* B2A7C4 800B3624 3C014F80 */ li $at, 0x4F800000 # 0.000000
/* B2A7C8 800B3628 240B00FF */ li $t3, 255
/* B2A7CC 800B362C 04410004 */ bgez $v0, .L800B3640
/* B2A7D0 800B3630 468091A0 */ cvt.s.w $f6, $f18
/* B2A7D4 800B3634 44815000 */ mtc1 $at, $f10
/* B2A7D8 800B3638 00000000 */ nop
/* B2A7DC 800B363C 460A3180 */ add.s $f6, $f6, $f10
.L800B3640:
/* B2A7E0 800B3640 46068103 */ div.s $f4, $f16, $f6
/* B2A7E4 800B3644 90EA0002 */ lbu $t2, 2($a3)
/* B2A7E8 800B3648 4600220D */ trunc.w.s $f8, $f4
/* B2A7EC 800B364C 44034000 */ mfc1 $v1, $f8
/* B2A7F0 800B3650 11400003 */ beqz $t2, .L800B3660
/* B2A7F4 800B3654 01636023 */ subu $t4, $t3, $v1
/* B2A7F8 800B3658 1000002B */ b .L800B3708
/* B2A7FC 800B365C A0EC0007 */ sb $t4, 7($a3)
.L800B3660:
/* B2A800 800B3660 10000029 */ b .L800B3708
/* B2A804 800B3664 A0E30007 */ sb $v1, 7($a3)
/* B2A808 800B3668 90ED0007 */ lbu $t5, 7($a3)
.L800B366C:
/* B2A80C 800B366C 3C028016 */ lui $v0, %hi(gGameInfo) # $v0, 0x8016
/* B2A810 800B3670 8C42FA90 */ lw $v0, %lo(gGameInfo)($v0)
/* B2A814 800B3674 A7AD002A */ sh $t5, 0x2a($sp)
/* B2A818 800B3678 84430D38 */ lh $v1, 0xd38($v0)
/* B2A81C 800B367C 50600021 */ beql $v1, $zero, .L800B3704
/* B2A820 800B3680 87A9002A */ lh $t1, 0x2a($sp)
/* B2A824 800B3684 0461000D */ bgez $v1, .L800B36BC
/* B2A828 800B3688 24440D38 */ addiu $a0, $v0, 0xd38
/* B2A82C 800B368C 27A4002A */ addiu $a0, $sp, 0x2a
/* B2A830 800B3690 240500FF */ li $a1, 255
/* B2A834 800B3694 240600FF */ li $a2, 255
/* B2A838 800B3698 0C01DE5F */ jal Math_ApproxS
/* B2A83C 800B369C AFA70030 */ sw $a3, 0x30($sp)
/* B2A840 800B36A0 10400017 */ beqz $v0, .L800B3700
/* B2A844 800B36A4 8FA70030 */ lw $a3, 0x30($sp)
/* B2A848 800B36A8 3C0F8016 */ lui $t7, %hi(gGameInfo) # $t7, 0x8016
/* B2A84C 800B36AC 8DEFFA90 */ lw $t7, %lo(gGameInfo)($t7)
/* B2A850 800B36B0 240E0096 */ li $t6, 150
/* B2A854 800B36B4 10000012 */ b .L800B3700
/* B2A858 800B36B8 A5EE0D38 */ sh $t6, 0xd38($t7)
.L800B36BC:
/* B2A85C 800B36BC 24050014 */ li $a1, 20
/* B2A860 800B36C0 2406003C */ li $a2, 60
/* B2A864 800B36C4 0C01DE5F */ jal Math_ApproxS
/* B2A868 800B36C8 AFA70030 */ sw $a3, 0x30($sp)
/* B2A86C 800B36CC 3C188016 */ lui $t8, %hi(gGameInfo) # $t8, 0x8016
/* B2A870 800B36D0 8F18FA90 */ lw $t8, %lo(gGameInfo)($t8)
/* B2A874 800B36D4 27A4002A */ addiu $a0, $sp, 0x2a
/* B2A878 800B36D8 00002825 */ move $a1, $zero
/* B2A87C 800B36DC 0C01DE5F */ jal Math_ApproxS
/* B2A880 800B36E0 87060D38 */ lh $a2, 0xd38($t8)
/* B2A884 800B36E4 10400006 */ beqz $v0, .L800B3700
/* B2A888 800B36E8 8FA70030 */ lw $a3, 0x30($sp)
/* B2A88C 800B36EC 3C198016 */ lui $t9, %hi(gGameInfo) # $t9, 0x8016
/* B2A890 800B36F0 8F39FA90 */ lw $t9, %lo(gGameInfo)($t9)
/* B2A894 800B36F4 24080001 */ li $t0, 1
/* B2A898 800B36F8 A7200D38 */ sh $zero, 0xd38($t9)
/* B2A89C 800B36FC A0E80001 */ sb $t0, 1($a3)
.L800B3700:
/* B2A8A0 800B3700 87A9002A */ lh $t1, 0x2a($sp)
.L800B3704:
/* B2A8A4 800B3704 A0E90007 */ sb $t1, 7($a3)
.L800B3708:
/* B2A8A8 800B3708 8FBF0014 */ lw $ra, 0x14($sp)
.L800B370C:
/* B2A8AC 800B370C 27BD0030 */ addiu $sp, $sp, 0x30
/* B2A8B0 800B3710 03E00008 */ jr $ra
/* B2A8B4 800B3714 00000000 */ nop
glabel func_800B3718
/* B2A8B8 800B3718 908E0007 */ lbu $t6, 7($a0)
/* B2A8BC 800B371C 3C188013 */ lui $t8, %hi(D_8012CEA0) # $t8, 0x8013
/* B2A8C0 800B3720 2718CEA0 */ addiu $t8, %lo(D_8012CEA0) # addiu $t8, $t8, -0x3160
/* B2A8C4 800B3724 19C0002B */ blez $t6, .L800B37D4
/* B2A8C8 800B3728 3C0FDE00 */ lui $t7, 0xde00
/* B2A8CC 800B372C 8CA20000 */ lw $v0, ($a1)
/* B2A8D0 800B3730 3C19FA00 */ lui $t9, 0xfa00
/* B2A8D4 800B3734 3C01F600 */ lui $at, 0xf600
/* B2A8D8 800B3738 24460008 */ addiu $a2, $v0, 8
/* B2A8DC 800B373C AC4F0000 */ sw $t7, ($v0)
/* B2A8E0 800B3740 AC580004 */ sw $t8, 4($v0)
/* B2A8E4 800B3744 ACD90000 */ sw $t9, ($a2)
/* B2A8E8 800B3748 24820004 */ addiu $v0, $a0, 4
/* B2A8EC 800B374C 90490000 */ lbu $t1, ($v0)
/* B2A8F0 800B3750 904C0001 */ lbu $t4, 1($v0)
/* B2A8F4 800B3754 90580002 */ lbu $t8, 2($v0)
/* B2A8F8 800B3758 904B0003 */ lbu $t3, 3($v0)
/* B2A8FC 800B375C 00095600 */ sll $t2, $t1, 0x18
/* B2A900 800B3760 000C6C00 */ sll $t5, $t4, 0x10
/* B2A904 800B3764 014D7025 */ or $t6, $t2, $t5
/* B2A908 800B3768 0018CA00 */ sll $t9, $t8, 8
/* B2A90C 800B376C 01D94025 */ or $t0, $t6, $t9
/* B2A910 800B3770 010B6025 */ or $t4, $t0, $t3
/* B2A914 800B3774 ACCC0004 */ sw $t4, 4($a2)
/* B2A918 800B3778 3C0A8013 */ lui $t2, %hi(gScreenWidth) # $t2, 0x8013
/* B2A91C 800B377C 8D4AD270 */ lw $t2, %lo(gScreenWidth)($t2)
/* B2A920 800B3780 3C198013 */ lui $t9, %hi(gScreenHeight) # $t9, 0x8013
/* B2A924 800B3784 8F39D274 */ lw $t9, %lo(gScreenHeight)($t9)
/* B2A928 800B3788 254DFFFF */ addiu $t5, $t2, -1
/* B2A92C 800B378C 24C30008 */ addiu $v1, $a2, 8
/* B2A930 800B3790 31AF03FF */ andi $t7, $t5, 0x3ff
/* B2A934 800B3794 2729FFFF */ addiu $t1, $t9, -1
/* B2A938 800B3798 312803FF */ andi $t0, $t1, 0x3ff
/* B2A93C 800B379C 000FC380 */ sll $t8, $t7, 0xe
/* B2A940 800B37A0 00601025 */ move $v0, $v1
/* B2A944 800B37A4 03017025 */ or $t6, $t8, $at
/* B2A948 800B37A8 00085880 */ sll $t3, $t0, 2
/* B2A94C 800B37AC 01CB6025 */ or $t4, $t6, $t3
/* B2A950 800B37B0 AC4C0000 */ sw $t4, ($v0)
/* B2A954 800B37B4 AC400004 */ sw $zero, 4($v0)
/* B2A958 800B37B8 24630008 */ addiu $v1, $v1, 8
/* B2A95C 800B37BC 00601025 */ move $v0, $v1
/* B2A960 800B37C0 3C0AE700 */ lui $t2, 0xe700
/* B2A964 800B37C4 AC4A0000 */ sw $t2, ($v0)
/* B2A968 800B37C8 AC400004 */ sw $zero, 4($v0)
/* B2A96C 800B37CC 24630008 */ addiu $v1, $v1, 8
/* B2A970 800B37D0 ACA30000 */ sw $v1, ($a1)
.L800B37D4:
/* B2A974 800B37D4 03E00008 */ jr $ra
/* B2A978 800B37D8 00000000 */ nop
glabel func_800B37DC
/* B2A97C 800B37DC 03E00008 */ jr $ra
/* B2A980 800B37E0 90820001 */ lbu $v0, 1($a0)
glabel func_800B37E4
/* B2A984 800B37E4 03E00008 */ jr $ra
/* B2A988 800B37E8 AC850004 */ sw $a1, 4($a0)
glabel func_800B37EC
/* B2A98C 800B37EC 24010001 */ li $at, 1
/* B2A990 800B37F0 14A10004 */ bne $a1, $at, .L800B3804
/* B2A994 800B37F4 24020001 */ li $v0, 1
/* B2A998 800B37F8 A0820000 */ sb $v0, ($a0)
/* B2A99C 800B37FC 03E00008 */ jr $ra
/* B2A9A0 800B3800 A0820002 */ sb $v0, 2($a0)
.L800B3804:
/* B2A9A4 800B3804 24010002 */ li $at, 2
/* B2A9A8 800B3808 14A10004 */ bne $a1, $at, .L800B381C
/* B2A9AC 800B380C 24020001 */ li $v0, 1
/* B2A9B0 800B3810 A0820000 */ sb $v0, ($a0)
/* B2A9B4 800B3814 03E00008 */ jr $ra
/* B2A9B8 800B3818 A0800002 */ sb $zero, 2($a0)
.L800B381C:
/* B2A9BC 800B381C 24010003 */ li $at, 3
/* B2A9C0 800B3820 14A10003 */ bne $a1, $at, .L800B3830
/* B2A9C4 800B3824 240E0002 */ li $t6, 2
/* B2A9C8 800B3828 03E00008 */ jr $ra
/* B2A9CC 800B382C A08E0000 */ sb $t6, ($a0)
.L800B3830:
/* B2A9D0 800B3830 A0800000 */ sb $zero, ($a0)
/* B2A9D4 800B3834 03E00008 */ jr $ra
/* B2A9D8 800B3838 00000000 */ nop
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple x86_64-unknown-linux -fvisibility hidden -fsanitize=cfi-nvcall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple x86_64-unknown-linux -fvisibility hidden -fsanitize=cfi-nvcall,cfi-cast-strict -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-STRICT %s
struct A {
virtual void f();
};
struct B : A {
int i;
void g();
};
struct C : A {
void g();
};
// CHECK-LABEL: @bg
// CHECK-STRICT-LABEL: @bg
extern "C" void bg(B *b) {
// CHECK: call i1 @llvm.type.test(i8* {{%[^ ]*}}, metadata !"_ZTS1B")
// CHECK-STRICT: call i1 @llvm.type.test(i8* {{%[^ ]*}}, metadata !"_ZTS1B")
b->g();
}
// CHECK-LABEL: @cg
// CHECK-STRICT-LABEL: @cg
extern "C" void cg(C *c) {
// http://clang.llvm.org/docs/ControlFlowIntegrity.html#strictness
// In this case C's layout is the same as its base class, so we allow
// c to be of type A in non-strict mode.
// CHECK: call i1 @llvm.type.test(i8* {{%[^ ]*}}, metadata !"_ZTS1A")
// CHECK-STRICT: call i1 @llvm.type.test(i8* {{%[^ ]*}}, metadata !"_ZTS1C")
c->g();
}
| {
"language": "Assembly"
} |
# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t
# RUN: llvm-dwarfdump -debug-names %t | FileCheck %s
# CHECK: LocalTU[0]: 0x0000000d
# CHECK-NEXT: LocalTU[1]: 0x00000028
# CHECK: ForeignTU[0]: 0x0011223344556677
# CHECK-NEXT: ForeignTU[1]: 0x1122334455667788
.section .debug_abbrev,"",@progbits
.byte 1 # Abbreviation Code
.byte 17 # DW_TAG_compile_unit
.byte 0 # DW_CHILDREN_no
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 2 # Abbreviation Code
.byte 19 # DW_TAG_structure_type
.byte 0 # DW_CHILDREN_no
.byte 3 # DW_AT_name
.byte 8 # DW_FORM_string
.byte 0 # EOM(1)
.byte 0 # EOM(2)
.byte 0
.section .debug_names,"",@progbits
.long .Lnames_end0-.Lnames_start0 # Header: unit length
.Lnames_start0:
.short 5 # Header: version
.short 0 # Header: padding
.long 1 # Header: compilation unit count
.long 2 # Header: local type unit count
.long 2 # Header: foreign type unit count
.long 0 # Header: bucket count
.long 2 # Header: name count
.long .Lnames_abbrev_end0-.Lnames_abbrev_start0 # Header: abbreviation table size
.long 0 # Header: augmentation string size
.long .Lcu_begin0 # Compilation unit 0
.long .Ltu_begin0 # Local TU 0
.long .Ltu_begin1 # Local TU 1
.quad 0x0011223344556677 # Foreign TU 0
.quad 0x1122334455667788 # Foreign TU 1
.long .Lstring0 # String in Bucket 0: A
.long .Lstring1 # String in Bucket 1: B
.long .Lnames0-.Lnames_entries0 # Offset in Bucket 0
.long .Lnames1-.Lnames_entries0 # Offset in Bucket 1
.Lnames_abbrev_start0:
.byte 1 # Abbrev code
.byte 19 # DW_TAG_structure_type
.byte 3 # DW_IDX_die_offset
.byte 19 # DW_FORM_ref4
.byte 0 # End of abbrev
.byte 0 # End of abbrev
.byte 0 # End of abbrev list
.Lnames_abbrev_end0:
.Lnames_entries0:
.Lnames0:
.byte 1 # Abbreviation code
.long .Ltu_die0-.Lcu_begin0 # DW_IDX_die_offset
.long 0 # End of list: A
.Lnames1:
.byte 1 # Abbreviation code
.long .Ltu_die1-.Lcu_begin0 # DW_IDX_die_offset
.long 0 # End of list: B
.p2align 2
.Lnames_end0:
.section .debug_info,"",@progbits
.Lcu_begin0:
.long .Lcu_end0-.Lcu_begin0-4 # Length of Unit
.short 5 # DWARF version number
.byte 1 # DW_UT_compile
.byte 8 # Address Size (in bytes)
.long .debug_abbrev # Offset Into Abbrev. Section
.byte 1 # Abbrev [1] DW_TAG_compile_unit
.Lcu_end0:
.Ltu_begin0:
.long .Ltu_end0-.Ltu_begin0-4 # Length of Unit
.short 5 # DWARF version number
.byte 2 # DW_UT_type
.byte 8 # Address Size (in bytes)
.long .debug_abbrev # Offset Into Abbrev. Section
.quad 0x0011223344556677 # Type Signature
.long .Ltu_die0-.Ltu_begin0 # Type Offset
.Ltu_die0:
.byte 2 # Abbrev [2] DW_TAG_structure_type
.asciz "A"
.Ltu_end0:
.Ltu_begin1:
.long .Ltu_end1-.Ltu_begin1-4 # Length of Unit
.short 5 # DWARF version number
.byte 2 # DW_UT_type
.byte 8 # Address Size (in bytes)
.long .debug_abbrev # Offset Into Abbrev. Section
.quad 0x1122334455667788 # Type Signature
.long .Ltu_die1-.Ltu_begin1 # Type Offset
.Ltu_die1:
.byte 2 # Abbrev [1] 0xc:0x48 DW_TAG_structure_type
.asciz "B"
.Ltu_end1:
.section .debug_str,"MS",@progbits,1
.Lstring0:
.asciz "A"
.Lstring1:
.asciz "B"
| {
"language": "Assembly"
} |
;Software License Agreement (BSD License)
;
;Copyright (c) 1997-2008, David Lindauer, (LADSoft).
;All rights reserved.
;
;Redistribution and use of this software in source and binary forms, with or without modification, are
;permitted provided that the following conditions are met:
;
;* Redistributions of source code must retain the above
; copyright notice, this list of conditions and the
; following disclaimer.
;
;* Redistributions in binary form must reproduce the above
; copyright notice, this list of conditions and the
; following disclaimer in the documentation and/or other
; materials provided with the distribution.
;
;* Neither the name of LADSoft nor the names of its
; contributors may be used to endorse or promote products
; derived from this software without specific prior
; written permission of LADSoft.
;
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
;WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
;PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
;ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
;TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
;ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
XDEF _exit
XREF __rexit
section code
_exit:
move.l (4,A7),d0
move.l (__rexit,pc),(a7)
rts | {
"language": "Assembly"
} |
/*
* Copyright (C) 2006 KPIT Cummins
* Copyright (C) 2009 Conny Marco Menebröcker
* All rights reserved.
*
* Redistribution and use in source and binary forms is permitted
* provided that the above copyright notice and following paragraph are
* duplicated in all such forms.
*
* This file is distributed WITHOUT ANY WARRANTY; without even the implied
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
.section .text
.global setjmp
_setjmp:
#ifdef __xc16xL__
rets
#else
ret
#endif
| {
"language": "Assembly"
} |
/* Definitions for Xtensa instructions, types, and protos. */
/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 2003-2004 Tensilica Inc.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
/* NOTE: This file exists only for backward compatibility with T1050
and earlier Xtensa releases. It includes only a subset of the
available header files. */
#ifndef _XTENSA_BASE_HEADER
#define _XTENSA_BASE_HEADER
#ifdef __XTENSA__
#include <xtensa/tie/xt_core.h>
#include <xtensa/tie/xt_misc.h>
#endif /* __XTENSA__ */
#endif /* !_XTENSA_BASE_HEADER */
| {
"language": "Assembly"
} |
#include "harness.h"
TEST_CASE(arc_arc_roundtrip) {
CHECK_LOAD("arc_arc.slvs");
CHECK_RENDER("arc_arc.png");
CHECK_SAVE("arc_arc.slvs");
}
TEST_CASE(arc_arc_migrate_from_v20) {
CHECK_LOAD("arc_arc_v20.slvs");
CHECK_SAVE("arc_arc.slvs");
}
TEST_CASE(arc_arc_migrate_from_v22) {
CHECK_LOAD("arc_arc_v22.slvs");
CHECK_SAVE("arc_arc.slvs");
}
TEST_CASE(arc_cubic_roundtrip) {
CHECK_LOAD("arc_cubic.slvs");
CHECK_RENDER("arc_cubic.png");
CHECK_SAVE("arc_cubic.slvs");
}
TEST_CASE(arc_cubic_migrate_from_v20) {
CHECK_LOAD("arc_cubic_v20.slvs");
CHECK_SAVE("arc_cubic.slvs");
}
TEST_CASE(arc_cubic_migrate_from_v22) {
CHECK_LOAD("arc_cubic_v22.slvs");
CHECK_SAVE("arc_cubic.slvs");
}
| {
"language": "Assembly"
} |
/* syslimits.h stands for the system's own limits.h file.
If we can use it ok unmodified, then we install this text.
If fixincludes fixes it, then the fixed version is installed
instead of this text. */
#define _GCC_NEXT_LIMITS_H /* tell gcc's limits.h to recurse */
#include_next <limits.h>
#undef _GCC_NEXT_LIMITS_H
| {
"language": "Assembly"
} |
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f446xx.s
;* Author : MCD Application Team
;* Version : V2.4.0
;* Date : 14-August-2015
;* Description : STM32F446x devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FMC_IRQHandler ; FMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI4_IRQHandler ; SPI4
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SAI1_IRQHandler ; SAI1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SAI2_IRQHandler ; SAI2
DCD QUADSPI_IRQHandler ; QuadSPI
DCD CEC_IRQHandler ; CEC
DCD SPDIF_RX_IRQHandler ; SPDIF RX
DCD I2C4_Event_IRQHandler ; I2C 4 Event
DCD I2C4_Error_IRQHandler ; I2C 4 Error
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT SAI1_IRQHandler [WEAK]
EXPORT SAI2_IRQHandler [WEAK]
EXPORT QUADSPI_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT SPDIF_RX_IRQHandler [WEAK]
EXPORT I2C4_Event_IRQHandler [WEAK]
EXPORT I2C4_Error_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
SAI1_IRQHandler
SAI2_IRQHandler
QUADSPI_IRQHandler
CEC_IRQHandler
SPDIF_RX_IRQHandler
I2C4_Event_IRQHandler
I2C4_Error_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
| {
"language": "Assembly"
} |
; RUN: llc %s -mtriple=arm64-apple-darwin -o - | FileCheck %s
; CHECK-LABEL: ; -- Begin function foo
; CHECK: foo:
define hidden i32 @foo() {
entry:
ret i32 30
}
; CHECK: ; -- End function
; CHECK-LABEL: ; -- Begin function bar
; CHECK: bar:
define i32 @bar() {
entry:
ret i32 30
}
; CHECK: ; -- End function
| {
"language": "Assembly"
} |
/* SoX Resampler Library Copyright (c) 2007-16 robs@users.sourceforge.net
* Licence for this file: LGPL v2.1 See LICENCE for details. */
#define RATE_CB _soxr_rate64_cb
#define CORE_STR "cr64"
#define CORE_TYPE CORE_DBL
#include "cr-core.c"
| {
"language": "Assembly"
} |
#include <complex.h>
#include <math_ldbl_opt.h>
#undef weak_alias
#define weak_alias(n,a)
#include <math/s_ctanl.c>
long_double_symbol (libm, __ctanl, ctanl);
| {
"language": "Assembly"
} |
//
// StaticLibraryTarget.xcconfig
//
// These are static library target settings for libgtest.a. It
// is set in the "Based On:" dropdown in the "Target" info dialog.
// This file is based on the Xcode Configuration files in:
// http://code.google.com/p/google-toolbox-for-mac/
//
// Static libs can be included in bundles so make them position independent
GCC_DYNAMIC_NO_PIC = NO
// Static libs should not have their internal globals or external symbols
// stripped.
STRIP_STYLE = debugging
// Let the user install by specifying the $DSTROOT with xcodebuild
SKIP_INSTALL = NO
| {
"language": "Assembly"
} |
From 433ffb21119a0f39e882dd3fea4742e64aadcc40 Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Sat, 11 Aug 2018 09:56:40 -0700
Subject: [PATCH] eject: Include sys/sysmacros.h for major/minor
Fixes
arm-bec-linux-gnueabi/gcc/arm-bec-linux-gnueabi/8.2.0/ld: eject.o: in function `GetMajorMinor':
/usr/src/debug/eject/2.1.5-r1/eject-2.1.5/../../../../../../../workspace/sources/eject/eject.c:866: undefined reference to `major'
Upstream-Status: Pending
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
eject.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/eject.c b/eject.c
index 47e09fe..b171218 100644
--- a/eject.c
+++ b/eject.c
@@ -54,6 +54,7 @@
#include <sys/wait.h>
#include <sys/mtio.h>
#include <sys/mount.h>
+#include <sys/sysmacros.h>
#if defined(__linux__)
#include <linux/version.h>
| {
"language": "Assembly"
} |
// Code generated by mkduff.go; DO NOT EDIT.
// Run go generate from src/runtime to update.
// See mkduff.go for comments.
#include "textflag.h"
TEXT runtime·duffzero(SB), NOSPLIT, $0-0
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
MOVW.P R0, 4(R1)
RET
TEXT runtime·duffcopy(SB), NOSPLIT, $0-0
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
MOVW.P 4(R1), R0
MOVW.P R0, 4(R2)
RET
| {
"language": "Assembly"
} |
/*********************************************************************/
/* */
/* Optimized BLAS libraries */
/* By Kazushige Goto <kgoto@tacc.utexas.edu> */
/* */
/* Copyright (c) The University of Texas, 2009. All rights reserved. */
/* UNIVERSITY EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES CONCERNING */
/* THIS SOFTWARE AND DOCUMENTATION, INCLUDING ANY WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, */
/* NON-INFRINGEMENT AND WARRANTIES OF PERFORMANCE, AND ANY WARRANTY */
/* THAT MIGHT OTHERWISE ARISE FROM COURSE OF DEALING OR USAGE OF */
/* TRADE. NO WARRANTY IS EITHER EXPRESS OR IMPLIED WITH RESPECT TO */
/* THE USE OF THE SOFTWARE OR DOCUMENTATION. */
/* Under no circumstances shall University be liable for incidental, */
/* special, indirect, direct or consequential damages or loss of */
/* profits, interruption of business, or related expenses which may */
/* arise from use of Software or Documentation, including but not */
/* limited to those resulting from defects in Software and/or */
/* Documentation, or loss or inaccuracy of data of any kind. */
/*********************************************************************/
#define ASSEMBLER
#include "common.h"
#define STACK 16
#define ARGS 0
#define STACK_M 4 + STACK + ARGS(%esi)
#define STACK_N 8 + STACK + ARGS(%esi)
#define STACK_K 12 + STACK + ARGS(%esi)
#define STACK_ALPHA_R 16 + STACK + ARGS(%esi)
#define STACK_ALPHA_I 24 + STACK + ARGS(%esi)
#define STACK_A 32 + STACK + ARGS(%esi)
#define STACK_B 36 + STACK + ARGS(%esi)
#define STACK_C 40 + STACK + ARGS(%esi)
#define STACK_LDC 44 + STACK + ARGS(%esi)
#define STACK_OFFT 48 + STACK + ARGS(%esi)
#define POSINV 0(%esp)
#define K 16(%esp)
#define N 20(%esp)
#define M 24(%esp)
#define A 28(%esp)
#define C 32(%esp)
#define J 36(%esp)
#define OLD_STACK 40(%esp)
#define OFFSET 44(%esp)
#define KK 48(%esp)
#define KKK 52(%esp)
#define AORIG 56(%esp)
#define BORIG 60(%esp)
#define BUFFER 128(%esp)
#define STACK_ALIGN 4096
#define STACK_OFFSET 1024
#if defined(OPTERON) || defined(BARCELONA)
#define PREFETCH prefetch
#else
#define PREFETCH prefetcht0
#endif
#define PREFETCHSIZE (8 * 10 + 4)
#define AA %edx
#define BB %ecx
#define LDC %ebp
#define B %edi
#define CO1 %esi
#ifndef CONJ
#define NN
#else
#if defined(LN) || defined(LT)
#define CN
#else
#define NC
#endif
#endif
#define KERNEL1(address) \
mulpd %xmm0, %xmm2; \
addpd %xmm2, %xmm4; \
PREFETCH (PREFETCHSIZE + 0) * SIZE + (address) * 1 * SIZE(AA); \
movapd 2 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm0, %xmm2; \
addpd %xmm2, %xmm5; \
movapd 4 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm0, %xmm2; \
mulpd 6 * SIZE + (address) * 4 * SIZE(BB), %xmm0; \
addpd %xmm2, %xmm6; \
movapd 16 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
addpd %xmm0, %xmm7; \
movapd 2 * SIZE + (address) * 1 * SIZE(AA), %xmm0
#define KERNEL2(address) \
mulpd %xmm0, %xmm3; \
addpd %xmm3, %xmm4; \
movapd 10 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm0, %xmm3; \
addpd %xmm3, %xmm5; \
movapd 12 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm0, %xmm3; \
mulpd 14 * SIZE + (address) * 4 * SIZE(BB), %xmm0; \
addpd %xmm3, %xmm6; \
movapd 24 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
addpd %xmm0, %xmm7; \
movapd 4 * SIZE + (address) * 1 * SIZE(AA), %xmm0
#define KERNEL3(address) \
mulpd %xmm0, %xmm2; \
addpd %xmm2, %xmm4; \
movapd 18 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm0, %xmm2; \
addpd %xmm2, %xmm5; \
movapd 20 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm0, %xmm2; \
mulpd 22 * SIZE + (address) * 4 * SIZE(BB), %xmm0; \
addpd %xmm2, %xmm6; \
movapd 32 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
addpd %xmm0, %xmm7; \
movapd 6 * SIZE + (address) * 1 * SIZE(AA), %xmm0
#define KERNEL4(address) \
mulpd %xmm0, %xmm3; \
addpd %xmm3, %xmm4; \
movapd 26 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm0, %xmm3; \
addpd %xmm3, %xmm5; \
movapd 28 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm0, %xmm3; \
mulpd 30 * SIZE + (address) * 4 * SIZE(BB), %xmm0; \
addpd %xmm3, %xmm6; \
movapd 40 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
addpd %xmm0, %xmm7; \
movapd 16 * SIZE + (address) * 1 * SIZE(AA), %xmm0
#define KERNEL5(address) \
PREFETCH (PREFETCHSIZE + 8) * SIZE + (address) * 1 * SIZE(AA); \
mulpd %xmm1, %xmm2; \
addpd %xmm2, %xmm4; \
movapd 34 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm1, %xmm2; \
addpd %xmm2, %xmm5; \
movapd 36 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm1, %xmm2; \
mulpd 38 * SIZE + (address) * 4 * SIZE(BB), %xmm1; \
addpd %xmm2, %xmm6; \
movapd 48 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
addpd %xmm1, %xmm7; \
movapd 10 * SIZE + (address) * 1 * SIZE(AA), %xmm1
#define KERNEL6(address) \
mulpd %xmm1, %xmm3; \
addpd %xmm3, %xmm4; \
movapd 42 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm1, %xmm3; \
addpd %xmm3, %xmm5; \
movapd 44 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm1, %xmm3; \
mulpd 46 * SIZE + (address) * 4 * SIZE(BB), %xmm1; \
addpd %xmm3, %xmm6; \
movapd 56 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
addpd %xmm1, %xmm7; \
movapd 12 * SIZE + (address) * 1 * SIZE(AA), %xmm1
#define KERNEL7(address) \
mulpd %xmm1, %xmm2; \
addpd %xmm2, %xmm4; \
movapd 50 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm1, %xmm2; \
addpd %xmm2, %xmm5; \
movapd 52 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
mulpd %xmm1, %xmm2; \
mulpd 54 * SIZE + (address) * 4 * SIZE(BB), %xmm1; \
addpd %xmm2, %xmm6; \
movapd 64 * SIZE + (address) * 4 * SIZE(BB), %xmm2; \
addpd %xmm1, %xmm7; \
movapd 14 * SIZE + (address) * 1 * SIZE(AA), %xmm1
#define KERNEL8(address) \
mulpd %xmm1, %xmm3; \
addpd %xmm3, %xmm4; \
movapd 58 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm1, %xmm3; \
addpd %xmm3, %xmm5; \
movapd 60 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
mulpd %xmm1, %xmm3; \
mulpd 62 * SIZE + (address) * 4 * SIZE(BB), %xmm1; \
addpd %xmm3, %xmm6; \
movapd 72 * SIZE + (address) * 4 * SIZE(BB), %xmm3; \
addpd %xmm1, %xmm7; \
movapd 24 * SIZE + (address) * 1 * SIZE(AA), %xmm1
PROLOGUE
pushl %ebp
pushl %edi
pushl %esi
pushl %ebx
PROFCODE
movl %esp, %esi # save old stack
subl $128 + LOCAL_BUFFER_SIZE + STACK_OFFSET, %esp
andl $-STACK_ALIGN, %esp # align stack
addl $STACK_OFFSET, %esp
STACK_TOUCHING
movl STACK_M, %ebx
movl STACK_N, %eax
movl STACK_K, %ecx
movl STACK_A, %edx
movl %ebx, M
movl %eax, N
movl %ecx, K
movl %edx, A
movl %esi, OLD_STACK
movl STACK_B, B
movl STACK_C, %ebx
movss STACK_OFFT, %xmm4
pcmpeqb %xmm7, %xmm7
psllq $63, %xmm7 # Generate mask
pxor %xmm2, %xmm2
movlpd %xmm2, 0 + POSINV
movlpd %xmm7, 8 + POSINV
movl %ebx, C
movl STACK_LDC, LDC
movss %xmm4, OFFSET
movss %xmm4, KK
sall $ZBASE_SHIFT, LDC
#ifdef LN
movl M, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, C
imull K, %eax
addl %eax, A
#endif
#ifdef RT
movl N, %eax
sall $ZBASE_SHIFT, %eax
imull K, %eax
addl %eax, B
movl N, %eax
imull LDC, %eax
addl %eax, C
#endif
#ifdef RN
negl KK
#endif
#ifdef RT
movl N, %eax
subl OFFSET, %eax
movl %eax, KK
#endif
movl N, %eax
andl $1, %eax
jle .L100
ALIGN_4
.L101:
#ifdef LN
movl OFFSET, %eax
addl M, %eax
movl %eax, KK
#endif
leal BUFFER, BB
#ifdef RT
movl K, %eax
sall $ZBASE_SHIFT, %eax
subl %eax, B
#endif
#if defined(LN) || defined(RT)
movl KK, %eax
movl B, BORIG
sall $ZBASE_SHIFT, %eax
addl %eax, B
leal (BB, %eax, 2), BB
#endif
#if defined(LT)
movl OFFSET, %eax
movl %eax, KK
#endif
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
sarl $2, %eax
jle .L103
ALIGN_4
.L102:
prefetchnta 56 * SIZE(B)
movlpd 0 * SIZE(B), %xmm0
movlpd 1 * SIZE(B), %xmm1
movlpd 2 * SIZE(B), %xmm2
movlpd 3 * SIZE(B), %xmm3
movlpd 4 * SIZE(B), %xmm4
movlpd 5 * SIZE(B), %xmm5
movlpd 6 * SIZE(B), %xmm6
movlpd 7 * SIZE(B), %xmm7
movlpd %xmm0, 0 * SIZE(BB)
movlpd %xmm0, 1 * SIZE(BB)
movlpd %xmm1, 2 * SIZE(BB)
movlpd %xmm1, 3 * SIZE(BB)
movlpd %xmm2, 4 * SIZE(BB)
movlpd %xmm2, 5 * SIZE(BB)
movlpd %xmm3, 6 * SIZE(BB)
movlpd %xmm3, 7 * SIZE(BB)
movlpd %xmm4, 8 * SIZE(BB)
movlpd %xmm4, 9 * SIZE(BB)
movlpd %xmm5, 10 * SIZE(BB)
movlpd %xmm5, 11 * SIZE(BB)
movlpd %xmm6, 12 * SIZE(BB)
movlpd %xmm6, 13 * SIZE(BB)
movlpd %xmm7, 14 * SIZE(BB)
movlpd %xmm7, 15 * SIZE(BB)
addl $ 8 * SIZE, B
subl $-16 * SIZE, BB
decl %eax
jne .L102
ALIGN_4
.L103:
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
andl $3, %eax
BRANCH
jle .L105
ALIGN_4
.L104:
movlpd 0 * SIZE(B), %xmm0
movlpd 1 * SIZE(B), %xmm1
movlpd %xmm0, 0 * SIZE(BB)
movlpd %xmm0, 1 * SIZE(BB)
movlpd %xmm1, 2 * SIZE(BB)
movlpd %xmm1, 3 * SIZE(BB)
addl $2 * SIZE, B
addl $4 * SIZE, BB
decl %eax
jne .L104
ALIGN_4
.L105:
#if defined(LT) || defined(RN)
movl A, %eax
movl %eax, AA
#else
movl A, %eax
movl %eax, AORIG
#endif
#ifdef RT
subl LDC, C
#endif
movl C, CO1
#ifndef RT
addl LDC, C
#endif
movl M, %ebx
testl %ebx, %ebx
jle .L199
ALIGN_4
.L110:
#ifdef LN
movl K, %eax
sall $ZBASE_SHIFT, %eax
subl %eax, AORIG
#endif
#if defined(LN) || defined(RT)
movl AORIG, %eax
movl %eax, AA
movl KK, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, AA
#endif
leal BUFFER, BB
#if defined(LN) || defined(RT)
movl KK, %eax
sall $ZBASE_SHIFT, %eax
leal (BB, %eax, 2), BB
#endif
pxor %xmm4, %xmm4
pxor %xmm5, %xmm5
pxor %xmm6, %xmm6
pxor %xmm7, %xmm7
movapd 0 * SIZE(AA), %xmm0
movapd 8 * SIZE(AA), %xmm1
movapd 0 * SIZE(BB), %xmm2
movapd 8 * SIZE(BB), %xmm3
#ifdef LN
prefetchw -2 * SIZE(CO1)
#else
prefetchw 2 * SIZE(CO1)
#endif
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
sarl $3, %eax
je .L112
ALIGN_4
.L111:
PREFETCH (PREFETCHSIZE + 0) * SIZE(AA)
mulpd %xmm0, %xmm2
mulpd 2 * SIZE(BB), %xmm0
addpd %xmm2, %xmm4
movapd 4 * SIZE(BB), %xmm2
addpd %xmm0, %xmm5
movapd 2 * SIZE(AA), %xmm0
mulpd %xmm0, %xmm2
mulpd 6 * SIZE(BB), %xmm0
addpd %xmm2, %xmm6
movapd 16 * SIZE(BB), %xmm2
addpd %xmm0, %xmm7
movapd 4 * SIZE(AA), %xmm0
mulpd %xmm0, %xmm3
mulpd 10 * SIZE(BB), %xmm0
addpd %xmm3, %xmm4
movapd 12 * SIZE(BB), %xmm3
addpd %xmm0, %xmm5
movapd 6 * SIZE(AA), %xmm0
mulpd %xmm0, %xmm3
mulpd 14 * SIZE(BB), %xmm0
addpd %xmm3, %xmm6
movapd 24 * SIZE(BB), %xmm3
addpd %xmm0, %xmm7
movapd 16 * SIZE(AA), %xmm0
mulpd %xmm1, %xmm2
mulpd 18 * SIZE(BB), %xmm1
addpd %xmm2, %xmm4
movapd 20 * SIZE(BB), %xmm2
addpd %xmm1, %xmm5
movapd 10 * SIZE(AA), %xmm1
mulpd %xmm1, %xmm2
mulpd 22 * SIZE(BB), %xmm1
addpd %xmm2, %xmm6
movapd 32 * SIZE(BB), %xmm2
addpd %xmm1, %xmm7
movapd 12 * SIZE(AA), %xmm1
mulpd %xmm1, %xmm3
mulpd 26 * SIZE(BB), %xmm1
addpd %xmm3, %xmm4
movapd 28 * SIZE(BB), %xmm3
addpd %xmm1, %xmm5
movapd 14 * SIZE(AA), %xmm1
mulpd %xmm1, %xmm3
mulpd 30 * SIZE(BB), %xmm1
addpd %xmm3, %xmm6
movapd 40 * SIZE(BB), %xmm3
addpd %xmm1, %xmm7
movapd 24 * SIZE(AA), %xmm1
addl $16 * SIZE, AA
addl $32 * SIZE, BB
decl %eax
jne .L111
ALIGN_4
.L112:
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
andl $7, %eax # if (k & 1)
BRANCH
je .L114
ALIGN_4
.L113:
mulpd %xmm0, %xmm2
mulpd 2 * SIZE(BB), %xmm0
addpd %xmm2, %xmm4
movapd 4 * SIZE(BB), %xmm2
addpd %xmm0, %xmm5
movapd 2 * SIZE(AA), %xmm0
addl $2 * SIZE, AA
addl $4 * SIZE, BB
decl %eax
jg .L113
ALIGN_4
.L114:
#if defined(LN) || defined(RT)
movl KK, %eax
#ifdef LN
subl $1, %eax
#else
subl $1, %eax
#endif
movl AORIG, AA
movl BORIG, B
leal BUFFER, BB
sall $ZBASE_SHIFT, %eax
addl %eax, AA
addl %eax, B
leal (BB, %eax, 2), BB
#endif
movapd POSINV, %xmm1
addpd %xmm6, %xmm4
addpd %xmm7, %xmm5
SHUFPD_1 %xmm5, %xmm5
#if defined(NN) || defined(NT) || defined(TN) || defined(TT) || \
defined(NR) || defined(NC) || defined(TR) || defined(TC)
xorpd %xmm1, %xmm5
#else
xorpd %xmm1, %xmm4
#endif
#if defined(NN) || defined(NT) || defined(TN) || defined(TT) || \
defined(RR) || defined(RC) || defined(CR) || defined(CC)
subpd %xmm5, %xmm4
#else
addpd %xmm5, %xmm4
#endif
#if defined(LN) || defined(LT)
movapd 0 * SIZE(B), %xmm5
subpd %xmm4, %xmm5
#else
movapd 0 * SIZE(AA), %xmm5
subpd %xmm4, %xmm5
#endif
#ifndef CONJ
SHUFPD_1 %xmm1, %xmm1
#endif
#if defined(LN) || defined(LT)
movlpd 0 * SIZE(AA), %xmm2
movhpd 0 * SIZE(AA), %xmm2
movlpd 1 * SIZE(AA), %xmm3
movhpd 1 * SIZE(AA), %xmm3
pshufd $0x4e, %xmm5, %xmm4
xorpd %xmm1, %xmm4
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
addpd %xmm4, %xmm5
#endif
#ifdef RN
movlpd 0 * SIZE(B), %xmm2
movhpd 0 * SIZE(B), %xmm2
movlpd 1 * SIZE(B), %xmm3
movhpd 1 * SIZE(B), %xmm3
pshufd $0x4e, %xmm5, %xmm4
xorpd %xmm1, %xmm4
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
addpd %xmm4, %xmm5
#endif
#ifdef RT
movlpd 0 * SIZE(B), %xmm2
movhpd 0 * SIZE(B), %xmm2
movlpd 1 * SIZE(B), %xmm3
movhpd 1 * SIZE(B), %xmm3
pshufd $0x4e, %xmm5, %xmm4
xorpd %xmm1, %xmm4
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
addpd %xmm4, %xmm5
#endif
#ifdef LN
subl $2 * SIZE, CO1
#endif
movlpd %xmm5, 0 * SIZE(CO1)
movhpd %xmm5, 1 * SIZE(CO1)
#if defined(LN) || defined(LT)
movapd %xmm5, 0 * SIZE(B)
movlpd %xmm5, 0 * SIZE(BB)
movlpd %xmm5, 1 * SIZE(BB)
movhpd %xmm5, 2 * SIZE(BB)
movhpd %xmm5, 3 * SIZE(BB)
#else
movapd %xmm5, 0 * SIZE(AA)
#endif
#ifndef LN
addl $2 * SIZE, CO1
#endif
#if defined(LT) || defined(RN)
movl K, %eax
subl KK, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, AA
#ifdef LT
addl $2 * SIZE, B
#endif
#endif
#ifdef LN
subl $1, KK
movl BORIG, B
#endif
#ifdef LT
addl $1, KK
#endif
#ifdef RT
movl K, %eax
movl BORIG, B
sall $ZBASE_SHIFT, %eax
addl %eax, AORIG
#endif
decl %ebx # i --
jg .L110
ALIGN_4
.L199:
#ifdef LN
movl K, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, B
#endif
#if defined(LT) || defined(RN)
movl K, %eax
subl KK, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, B
#endif
#ifdef RN
addl $1, KK
#endif
#ifdef RT
subl $1, KK
#endif
ALIGN_4
.L100:
movl N, %eax
sarl $1, %eax
movl %eax, J # j = n
jle .L500
ALIGN_4
.L01:
#ifdef LN
movl OFFSET, %eax
addl M, %eax
movl %eax, KK
#endif
leal BUFFER, BB
#ifdef RT
movl K, %eax
sall $1 + ZBASE_SHIFT, %eax
subl %eax, B
#endif
#if defined(LN) || defined(RT)
movl KK, %eax
movl B, BORIG
sall $1 + ZBASE_SHIFT, %eax
addl %eax, B
leal (BB, %eax, 2), BB
#endif
#if defined(LT)
movl OFFSET, %eax
movl %eax, KK
#endif
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
sarl $1, %eax
jle .L03
ALIGN_4
.L02:
prefetchnta 56 * SIZE(B)
movlpd 0 * SIZE(B), %xmm0
movlpd 1 * SIZE(B), %xmm1
movlpd 2 * SIZE(B), %xmm2
movlpd 3 * SIZE(B), %xmm3
movlpd 4 * SIZE(B), %xmm4
movlpd 5 * SIZE(B), %xmm5
movlpd 6 * SIZE(B), %xmm6
movlpd 7 * SIZE(B), %xmm7
movlpd %xmm0, 0 * SIZE(BB)
movlpd %xmm0, 1 * SIZE(BB)
movlpd %xmm1, 2 * SIZE(BB)
movlpd %xmm1, 3 * SIZE(BB)
movlpd %xmm2, 4 * SIZE(BB)
movlpd %xmm2, 5 * SIZE(BB)
movlpd %xmm3, 6 * SIZE(BB)
movlpd %xmm3, 7 * SIZE(BB)
movlpd %xmm4, 8 * SIZE(BB)
movlpd %xmm4, 9 * SIZE(BB)
movlpd %xmm5, 10 * SIZE(BB)
movlpd %xmm5, 11 * SIZE(BB)
movlpd %xmm6, 12 * SIZE(BB)
movlpd %xmm6, 13 * SIZE(BB)
movlpd %xmm7, 14 * SIZE(BB)
movlpd %xmm7, 15 * SIZE(BB)
addl $ 8 * SIZE, B
subl $-16 * SIZE, BB
decl %eax
jne .L02
ALIGN_4
.L03:
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
andl $1, %eax
BRANCH
jle .L05
movlpd 0 * SIZE(B), %xmm0
movlpd 1 * SIZE(B), %xmm1
movlpd 2 * SIZE(B), %xmm2
movlpd 3 * SIZE(B), %xmm3
movlpd %xmm0, 0 * SIZE(BB)
movlpd %xmm0, 1 * SIZE(BB)
movlpd %xmm1, 2 * SIZE(BB)
movlpd %xmm1, 3 * SIZE(BB)
movlpd %xmm2, 4 * SIZE(BB)
movlpd %xmm2, 5 * SIZE(BB)
movlpd %xmm3, 6 * SIZE(BB)
movlpd %xmm3, 7 * SIZE(BB)
addl $4 * SIZE, B
ALIGN_4
.L05:
#if defined(LT) || defined(RN)
movl A, %eax
movl %eax, AA
#else
movl A, %eax
movl %eax, AORIG
#endif
#ifdef RT
leal (, LDC, 2), %eax
subl %eax, C
#endif
movl C, CO1
#ifndef RT
leal (, LDC, 2), %eax
addl %eax, C
#endif
movl M, %ebx
testl %ebx, %ebx
jle .L100
ALIGN_4
.L10:
#ifdef LN
movl K, %eax
sall $ZBASE_SHIFT, %eax
subl %eax, AORIG
#endif
#if defined(LN) || defined(RT)
movl AORIG, %eax
movl %eax, AA
movl KK, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, AA
#endif
leal BUFFER, BB
#if defined(LN) || defined(RT)
movl KK, %eax
sall $1 + ZBASE_SHIFT, %eax
leal (BB, %eax, 2), BB
#endif
movapd 0 * SIZE(AA), %xmm0
pxor %xmm4, %xmm4
movapd 8 * SIZE(AA), %xmm1
pxor %xmm5, %xmm5
movapd 0 * SIZE(BB), %xmm2
pxor %xmm6, %xmm6
movapd 8 * SIZE(BB), %xmm3
pxor %xmm7, %xmm7
#ifdef LN
prefetchw -2 * SIZE(CO1)
prefetchw -2 * SIZE(CO1, LDC)
#else
prefetchw 2 * SIZE(CO1)
prefetchw 2 * SIZE(CO1, LDC)
#endif
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
#if 1
andl $-8, %eax
sall $4, %eax
je .L15
.L1X:
KERNEL1(16 * 0)
KERNEL2(16 * 0)
KERNEL3(16 * 0)
KERNEL4(16 * 0)
KERNEL5(16 * 0)
KERNEL6(16 * 0)
KERNEL7(16 * 0)
KERNEL8(16 * 0)
cmpl $128 * 1, %eax
jle .L12
KERNEL1(16 * 1)
KERNEL2(16 * 1)
KERNEL3(16 * 1)
KERNEL4(16 * 1)
KERNEL5(16 * 1)
KERNEL6(16 * 1)
KERNEL7(16 * 1)
KERNEL8(16 * 1)
cmpl $128 * 2, %eax
jle .L12
KERNEL1(16 * 2)
KERNEL2(16 * 2)
KERNEL3(16 * 2)
KERNEL4(16 * 2)
KERNEL5(16 * 2)
KERNEL6(16 * 2)
KERNEL7(16 * 2)
KERNEL8(16 * 2)
cmpl $128 * 3, %eax
jle .L12
KERNEL1(16 * 3)
KERNEL2(16 * 3)
KERNEL3(16 * 3)
KERNEL4(16 * 3)
KERNEL5(16 * 3)
KERNEL6(16 * 3)
KERNEL7(16 * 3)
KERNEL8(16 * 3)
cmpl $128 * 4, %eax
jle .L12
KERNEL1(16 * 4)
KERNEL2(16 * 4)
KERNEL3(16 * 4)
KERNEL4(16 * 4)
KERNEL5(16 * 4)
KERNEL6(16 * 4)
KERNEL7(16 * 4)
KERNEL8(16 * 4)
cmpl $128 * 5, %eax
jle .L12
KERNEL1(16 * 5)
KERNEL2(16 * 5)
KERNEL3(16 * 5)
KERNEL4(16 * 5)
KERNEL5(16 * 5)
KERNEL6(16 * 5)
KERNEL7(16 * 5)
KERNEL8(16 * 5)
cmpl $128 * 6, %eax
jle .L12
KERNEL1(16 * 6)
KERNEL2(16 * 6)
KERNEL3(16 * 6)
KERNEL4(16 * 6)
KERNEL5(16 * 6)
KERNEL6(16 * 6)
KERNEL7(16 * 6)
KERNEL8(16 * 6)
cmpl $128 * 7, %eax
jle .L12
KERNEL1(16 * 7)
KERNEL2(16 * 7)
KERNEL3(16 * 7)
KERNEL4(16 * 7)
KERNEL5(16 * 7)
KERNEL6(16 * 7)
KERNEL7(16 * 7)
KERNEL8(16 * 7)
addl $128 * 4 * SIZE, BB
addl $128 * 1 * SIZE, AA
subl $128 * 8, %eax
jg .L1X
jmp .L15
.L12:
leal (AA, %eax, 1), AA
leal (BB, %eax, 4), BB
ALIGN_4
#else
sarl $3, %eax
je .L15
ALIGN_4
.L12:
KERNEL1(16 * 0)
KERNEL2(16 * 0)
KERNEL3(16 * 0)
KERNEL4(16 * 0)
KERNEL5(16 * 0)
KERNEL6(16 * 0)
KERNEL7(16 * 0)
KERNEL8(16 * 0)
addl $64 * SIZE, BB
addl $16 * SIZE, AA
decl %eax
jne .L11
ALIGN_4
#endif
.L15:
#if defined(LT) || defined(RN)
movl KK, %eax
#else
movl K, %eax
subl KK, %eax
#endif
andl $7, %eax # if (k & 1)
BRANCH
je .L14
ALIGN_4
.L13:
mulpd %xmm0, %xmm2
addpd %xmm2, %xmm4
movapd 2 * SIZE(BB), %xmm2
mulpd %xmm0, %xmm2
addpd %xmm2, %xmm5
movapd 4 * SIZE(BB), %xmm2
mulpd %xmm0, %xmm2
mulpd 6 * SIZE(BB), %xmm0
addpd %xmm2, %xmm6
movapd 8 * SIZE(BB), %xmm2
addpd %xmm0, %xmm7
movapd 2 * SIZE(AA), %xmm0
addl $2 * SIZE, AA
addl $8 * SIZE, BB
decl %eax
jg .L13
ALIGN_4
.L14:
#if defined(LN) || defined(RT)
movl KK, %eax
#ifdef LN
subl $1, %eax
#else
subl $2, %eax
#endif
movl AORIG, AA
movl BORIG, B
leal BUFFER, BB
sall $ZBASE_SHIFT, %eax
addl %eax, AA
leal (B, %eax, 2), B
leal (BB, %eax, 4), BB
#endif
movapd POSINV, %xmm1
SHUFPD_1 %xmm5, %xmm5
SHUFPD_1 %xmm7, %xmm7
#if defined(NN) || defined(NT) || defined(TN) || defined(TT) || \
defined(NR) || defined(NC) || defined(TR) || defined(TC)
xorpd %xmm1, %xmm5
xorpd %xmm1, %xmm7
#else
xorpd %xmm1, %xmm4
xorpd %xmm1, %xmm6
#endif
#if defined(NN) || defined(NT) || defined(TN) || defined(TT) || \
defined(RR) || defined(RC) || defined(CR) || defined(CC)
subpd %xmm5, %xmm4
subpd %xmm7, %xmm6
#else
addpd %xmm5, %xmm4
addpd %xmm7, %xmm6
#endif
#if defined(LN) || defined(LT)
movapd 0 * SIZE(B), %xmm5
movapd 2 * SIZE(B), %xmm7
subpd %xmm4, %xmm5
subpd %xmm6, %xmm7
#else
movapd 0 * SIZE(AA), %xmm5
movapd 2 * SIZE(AA), %xmm7
subpd %xmm4, %xmm5
subpd %xmm6, %xmm7
#endif
#ifndef CONJ
SHUFPD_1 %xmm1, %xmm1
#endif
#if defined(LN) || defined(LT)
movlpd 0 * SIZE(AA), %xmm2
movhpd 0 * SIZE(AA), %xmm2
movlpd 1 * SIZE(AA), %xmm3
movhpd 1 * SIZE(AA), %xmm3
pshufd $0x4e, %xmm5, %xmm4
pshufd $0x4e, %xmm7, %xmm6
xorpd %xmm1, %xmm4
xorpd %xmm1, %xmm6
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
mulpd %xmm2, %xmm7
mulpd %xmm3, %xmm6
addpd %xmm4, %xmm5
addpd %xmm6, %xmm7
#endif
#ifdef RN
movlpd 0 * SIZE(B), %xmm2
movhpd 0 * SIZE(B), %xmm2
movlpd 1 * SIZE(B), %xmm3
movhpd 1 * SIZE(B), %xmm3
pshufd $0x4e, %xmm5, %xmm4
xorpd %xmm1, %xmm4
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
addpd %xmm4, %xmm5
movlpd 2 * SIZE(B), %xmm2
movhpd 2 * SIZE(B), %xmm2
movlpd 3 * SIZE(B), %xmm3
movhpd 3 * SIZE(B), %xmm3
movapd %xmm5, %xmm4
pshufd $0x4e, %xmm5, %xmm6
xorpd %xmm1, %xmm6
mulpd %xmm2, %xmm4
mulpd %xmm3, %xmm6
subpd %xmm4, %xmm7
subpd %xmm6, %xmm7
movlpd 6 * SIZE(B), %xmm2
movhpd 6 * SIZE(B), %xmm2
movlpd 7 * SIZE(B), %xmm3
movhpd 7 * SIZE(B), %xmm3
pshufd $0x4e, %xmm7, %xmm6
xorpd %xmm1, %xmm6
mulpd %xmm2, %xmm7
mulpd %xmm3, %xmm6
addpd %xmm6, %xmm7
#endif
#ifdef RT
movlpd 6 * SIZE(B), %xmm2
movhpd 6 * SIZE(B), %xmm2
movlpd 7 * SIZE(B), %xmm3
movhpd 7 * SIZE(B), %xmm3
pshufd $0x4e, %xmm7, %xmm6
xorpd %xmm1, %xmm6
mulpd %xmm2, %xmm7
mulpd %xmm3, %xmm6
addpd %xmm6, %xmm7
movlpd 4 * SIZE(B), %xmm2
movhpd 4 * SIZE(B), %xmm2
movlpd 5 * SIZE(B), %xmm3
movhpd 5 * SIZE(B), %xmm3
movapd %xmm7, %xmm4
pshufd $0x4e, %xmm7, %xmm6
xorpd %xmm1, %xmm6
mulpd %xmm2, %xmm4
mulpd %xmm3, %xmm6
subpd %xmm4, %xmm5
subpd %xmm6, %xmm5
movlpd 0 * SIZE(B), %xmm2
movhpd 0 * SIZE(B), %xmm2
movlpd 1 * SIZE(B), %xmm3
movhpd 1 * SIZE(B), %xmm3
pshufd $0x4e, %xmm5, %xmm4
xorpd %xmm1, %xmm4
mulpd %xmm2, %xmm5
mulpd %xmm3, %xmm4
addpd %xmm4, %xmm5
#endif
#ifdef LN
subl $2 * SIZE, CO1
#endif
movlpd %xmm5, 0 * SIZE(CO1)
movhpd %xmm5, 1 * SIZE(CO1)
movlpd %xmm7, 0 * SIZE(CO1, LDC)
movhpd %xmm7, 1 * SIZE(CO1, LDC)
#if defined(LN) || defined(LT)
movapd %xmm5, 0 * SIZE(B)
movapd %xmm7, 2 * SIZE(B)
movlpd %xmm5, 0 * SIZE(BB)
movlpd %xmm5, 1 * SIZE(BB)
movhpd %xmm5, 2 * SIZE(BB)
movhpd %xmm5, 3 * SIZE(BB)
movlpd %xmm7, 4 * SIZE(BB)
movlpd %xmm7, 5 * SIZE(BB)
movhpd %xmm7, 6 * SIZE(BB)
movhpd %xmm7, 7 * SIZE(BB)
#else
movapd %xmm5, 0 * SIZE(AA)
movapd %xmm7, 2 * SIZE(AA)
#endif
#ifndef LN
addl $2 * SIZE, CO1
#endif
#if defined(LT) || defined(RN)
movl K, %eax
subl KK, %eax
sall $ZBASE_SHIFT, %eax
addl %eax, AA
#ifdef LT
addl $4 * SIZE, B
#endif
#endif
#ifdef LN
subl $1, KK
movl BORIG, B
#endif
#ifdef LT
addl $1, KK
#endif
#ifdef RT
movl K, %eax
movl BORIG, B
sall $ZBASE_SHIFT, %eax
addl %eax, AORIG
#endif
decl %ebx # i --
jg .L10
ALIGN_4
.L99:
#ifdef LN
movl K, %eax
sall $1 + ZBASE_SHIFT, %eax
addl %eax, B
#endif
#if defined(LT) || defined(RN)
movl K, %eax
subl KK, %eax
sall $1 + ZBASE_SHIFT, %eax
addl %eax, B
#endif
#ifdef RN
addl $2, KK
#endif
#ifdef RT
subl $2, KK
#endif
decl J # j --
jg .L01
ALIGN_4
.L500:
movl OLD_STACK, %esp
popl %ebx
popl %esi
popl %edi
popl %ebp
ret
EPILOGUE
| {
"language": "Assembly"
} |
dnl
dnl at90can128.m4
dnl
dnl Copyright (c) 2012 by Frank Sautter
dnl
dnl This program is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
dnl the Free Software Foundation; either version 3 of the License, or
dnl (at your option) any later version.
dnl
dnl
dnl This program is distributed in the hope that it will be useful,
dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
dnl GNU General Public License for more details.
dnl
dnl You should have received a copy of the GNU General Public License
dnl along with this program; if not, write to the Free Software
dnl Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
dnl
ifdef(`need_spi', `dnl
/* spi defines */
pin(SPI_MOSI, PB2, OUTPUT)
pin(SPI_MISO, PB3)
pin(SPI_SCK, PB1, OUTPUT)
pin(SPI_CS_HARDWARE, PB0, OUTPUT)
')dnl
#define ADC_CHANNELS 8
| {
"language": "Assembly"
} |
.sect .text; .sect .rom; .sect .data; .sect .bss
.define _signal
.sect .text
_signal:
call sig1
mov ax,48
mov dx,ctch
callf 0x7:0x0
jb 4f
ret
sig1:
mov ax,8(sp)
cmp ax,20
jae 1f
mov dx,table(ax*4)
mov (prev),dx
mov dx,12(sp)
mov table(ax*4),dx
ret
1:
pop ax
mov ax,0x16
4:
mov (_errno),ax
mov ax,-1
cdq
ret
ctch:
add sp,4
callf 0xf:0x0
.sect .bss
table:
.space 40
prev:
.space 4
| {
"language": "Assembly"
} |
[FORMAT "WCOFF"]
[INSTRSET "i486p"]
[BITS 32]
[FILE "api019.nas"]
GLOBAL _api_freetimer
[SECTION .text]
_api_freetimer: ; void api_freetimer(int timer);
PUSH EBX
MOV EDX,19
MOV EBX,[ESP+ 8] ; timer
INT 0x40
POP EBX
RET
| {
"language": "Assembly"
} |
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -instruction-tables < %s | FileCheck %s
crc32b %al, %ecx
crc32b (%rax), %ecx
crc32l %eax, %ecx
crc32l (%rax), %ecx
crc32w %ax, %ecx
crc32w (%rax), %ecx
crc32b %al, %rcx
crc32b (%rax), %rcx
crc32q %rax, %rcx
crc32q (%rax), %rcx
pcmpestri $1, %xmm0, %xmm2
pcmpestri $1, (%rax), %xmm2
pcmpestrm $1, %xmm0, %xmm2
pcmpestrm $1, (%rax), %xmm2
pcmpistri $1, %xmm0, %xmm2
pcmpistri $1, (%rax), %xmm2
pcmpistrm $1, %xmm0, %xmm2
pcmpistrm $1, (%rax), %xmm2
pcmpgtq %xmm0, %xmm2
pcmpgtq (%rax), %xmm2
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 crc32b %al, %ecx
# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %ecx
# CHECK-NEXT: 1 3 1.00 crc32l %eax, %ecx
# CHECK-NEXT: 2 8 1.00 * crc32l (%rax), %ecx
# CHECK-NEXT: 1 3 1.00 crc32w %ax, %ecx
# CHECK-NEXT: 2 8 1.00 * crc32w (%rax), %ecx
# CHECK-NEXT: 1 3 1.00 crc32b %al, %rcx
# CHECK-NEXT: 2 8 1.00 * crc32b (%rax), %rcx
# CHECK-NEXT: 1 3 1.00 crc32q %rax, %rcx
# CHECK-NEXT: 2 8 1.00 * crc32q (%rax), %rcx
# CHECK-NEXT: 8 18 4.00 pcmpestri $1, %xmm0, %xmm2
# CHECK-NEXT: 9 24 4.00 * pcmpestri $1, (%rax), %xmm2
# CHECK-NEXT: 9 19 4.00 pcmpestrm $1, %xmm0, %xmm2
# CHECK-NEXT: 10 25 4.00 * pcmpestrm $1, (%rax), %xmm2
# CHECK-NEXT: 3 10 3.00 pcmpistri $1, %xmm0, %xmm2
# CHECK-NEXT: 4 16 3.00 * pcmpistri $1, (%rax), %xmm2
# CHECK-NEXT: 3 10 3.00 pcmpistrm $1, %xmm0, %xmm2
# CHECK-NEXT: 4 16 3.00 * pcmpistrm $1, (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 pcmpgtq %xmm0, %xmm2
# CHECK-NEXT: 2 9 1.00 * pcmpgtq (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - SKLDivider
# CHECK-NEXT: [1] - SKLFPDivider
# CHECK-NEXT: [2] - SKLPort0
# CHECK-NEXT: [3] - SKLPort1
# CHECK-NEXT: [4] - SKLPort2
# CHECK-NEXT: [5] - SKLPort3
# CHECK-NEXT: [6] - SKLPort4
# CHECK-NEXT: [7] - SKLPort5
# CHECK-NEXT: [8] - SKLPort6
# CHECK-NEXT: [9] - SKLPort7
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 29.67 11.67 5.00 5.00 - 15.67 1.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - - 1.00 - - - - - - crc32b %al, %ecx
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - crc32b (%rax), %ecx
# CHECK-NEXT: - - - 1.00 - - - - - - crc32l %eax, %ecx
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - crc32l (%rax), %ecx
# CHECK-NEXT: - - - 1.00 - - - - - - crc32w %ax, %ecx
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - crc32w (%rax), %ecx
# CHECK-NEXT: - - - 1.00 - - - - - - crc32b %al, %rcx
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - crc32b (%rax), %rcx
# CHECK-NEXT: - - - 1.00 - - - - - - crc32q %rax, %rcx
# CHECK-NEXT: - - - 1.00 0.50 0.50 - - - - crc32q (%rax), %rcx
# CHECK-NEXT: - - 4.25 0.25 - - - 3.25 0.25 - pcmpestri $1, %xmm0, %xmm2
# CHECK-NEXT: - - 4.25 0.25 0.50 0.50 - 3.25 0.25 - pcmpestri $1, (%rax), %xmm2
# CHECK-NEXT: - - 4.58 0.58 - - - 3.58 0.25 - pcmpestrm $1, %xmm0, %xmm2
# CHECK-NEXT: - - 4.58 0.58 0.50 0.50 - 3.58 0.25 - pcmpestrm $1, (%rax), %xmm2
# CHECK-NEXT: - - 3.00 - - - - - - - pcmpistri $1, %xmm0, %xmm2
# CHECK-NEXT: - - 3.00 - 0.50 0.50 - - - - pcmpistri $1, (%rax), %xmm2
# CHECK-NEXT: - - 3.00 - - - - - - - pcmpistrm $1, %xmm0, %xmm2
# CHECK-NEXT: - - 3.00 - 0.50 0.50 - - - - pcmpistrm $1, (%rax), %xmm2
# CHECK-NEXT: - - - - - - - 1.00 - - pcmpgtq %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 0.50 - 1.00 - - pcmpgtq (%rax), %xmm2
| {
"language": "Assembly"
} |
SECTION code_crt0_sccz80
PUBLIC l_div_u
; HL = DE / HL, DE = DE % HL
l_div_u:
LD b,h ; store divisor to bc
LD c,l
LD HL,0 ; clear remainder
XOR a ; clear carry
LD a,17 ; load loop counter
PUSH AF
ccduv1: LD a,e ; left shift dividend into carry
RLA
LD e,a
LD a,d
RLA
LD d,a
JP C,ccduv2 ; we have to keep carry -> calling else branch
POP AF ; decrement loop counter
DEC a
JP Z,ccduv5
PUSH AF
XOR a ; clear carry
JP ccduv3
ccduv2: POP AF ; decrement loop counter
DEC a
JP Z,ccduv5
PUSH AF
SCF ; set carry
ccduv3: LD a,l ; left shift carry into remainder
RLA
LD l,a
LD a,h
RLA
LD h,a
LD a,l ; substract divisor from remainder
sub c
LD l,a
LD a,h
SBC b
LD h,a
JP NC,ccduv4 ; if result negative, add back divisor, clear carry
LD a,l ; add back divisor
ADD A,c
LD l,a
LD a,h
ADC A,b
LD h,a
XOR a ; clear carry
JP ccduv1
ccduv4: SCF ; set carry
JP ccduv1
ccduv5: EX DE,HL
ret
| {
"language": "Assembly"
} |
# REQUIRES: lit-max-individual-test-time
# llvm.org/PR33944
# UNSUPPORTED: system-windows
# FIXME: This test is fragile because it relies on time which can
# be affected by system performance. In particular we are currently
# assuming that `short.py` can be successfully executed within 2
# seconds of wallclock time.
# Test per test timeout using external shell
# RUN: not %{lit} \
# RUN: %{inputs}/shtest-timeout/infinite_loop.py \
# RUN: %{inputs}/shtest-timeout/short.py \
# RUN: -j 1 -v --debug --timeout 2 --param external=1 > %t.extsh.out 2> %t.extsh.err
# RUN: FileCheck --check-prefix=CHECK-OUT-COMMON < %t.extsh.out %s
# RUN: FileCheck --check-prefix=CHECK-EXTSH-ERR < %t.extsh.err %s
#
# CHECK-EXTSH-ERR: Using external shell
# Test per test timeout using internal shell
# RUN: not %{lit} \
# RUN: %{inputs}/shtest-timeout/infinite_loop.py \
# RUN: %{inputs}/shtest-timeout/short.py \
# RUN: -j 1 -v --debug --timeout 2 --param external=0 > %t.intsh.out 2> %t.intsh.err
# RUN: FileCheck --check-prefix=CHECK-OUT-COMMON < %t.intsh.out %s
# RUN: FileCheck --check-prefix=CHECK-INTSH-OUT < %t.intsh.out %s
# RUN: FileCheck --check-prefix=CHECK-INTSH-ERR < %t.intsh.err %s
# CHECK-INTSH-OUT: TIMEOUT: per_test_timeout :: infinite_loop.py
# CHECK-INTSH-OUT: command output:
# CHECK-INTSH-OUT: command reached timeout: True
# CHECK-INTSH-ERR: Using internal shell
# Test per test timeout set via a config file rather than on the command line
# RUN: not %{lit} \
# RUN: %{inputs}/shtest-timeout/infinite_loop.py \
# RUN: %{inputs}/shtest-timeout/short.py \
# RUN: -j 1 -v --debug --param external=0 \
# RUN: --param set_timeout=2 > %t.cfgset.out 2> %t.cfgset.err
# RUN: FileCheck --check-prefix=CHECK-OUT-COMMON < %t.cfgset.out %s
# RUN: FileCheck --check-prefix=CHECK-CFGSET-ERR < %t.cfgset.err %s
#
# CHECK-CFGSET-ERR: Using internal shell
# CHECK-OUT-COMMON: TIMEOUT: per_test_timeout :: infinite_loop.py
# CHECK-OUT-COMMON: Timeout: Reached timeout of 2 seconds
# CHECK-OUT-COMMON: Command {{([0-9]+ )?}}Output
# CHECK-OUT-COMMON: PASS: per_test_timeout :: short.py
# CHECK-OUT-COMMON: Expected Passes{{ *}}: 1
# CHECK-OUT-COMMON: Individual Timeouts{{ *}}: 1
# Test per test timeout via a config file and on the command line.
# The value set on the command line should override the config file.
# RUN: not %{lit} \
# RUN: %{inputs}/shtest-timeout/infinite_loop.py \
# RUN: %{inputs}/shtest-timeout/short.py \
# RUN: -j 1 -v --debug --param external=0 \
# RUN: --param set_timeout=1 --timeout=2 > %t.cmdover.out 2> %t.cmdover.err
# RUN: FileCheck --check-prefix=CHECK-CMDLINE-OVERRIDE-OUT < %t.cmdover.out %s
# RUN: FileCheck --check-prefix=CHECK-CMDLINE-OVERRIDE-ERR < %t.cmdover.err %s
# CHECK-CMDLINE-OVERRIDE-ERR: Forcing timeout to be 2 seconds
# CHECK-CMDLINE-OVERRIDE-OUT: TIMEOUT: per_test_timeout :: infinite_loop.py
# CHECK-CMDLINE-OVERRIDE-OUT: Timeout: Reached timeout of 2 seconds
# CHECK-CMDLINE-OVERRIDE-OUT: Command {{([0-9]+ )?}}Output
# CHECK-CMDLINE-OVERRIDE-OUT: PASS: per_test_timeout :: short.py
# CHECK-CMDLINE-OVERRIDE-OUT: Expected Passes{{ *}}: 1
# CHECK-CMDLINE-OVERRIDE-OUT: Individual Timeouts{{ *}}: 1
| {
"language": "Assembly"
} |
/// @file
/// IPF specific Debug Breakpoint Registers accessing functions
///
/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
/// This program and the accompanying materials
/// are licensed and made available under the terms and conditions of the BSD License
/// which accompanies this distribution. The full text of the license may be found at
/// http://opensource.org/licenses/bsd-license.php.
///
/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
///
/// Module Name: AccessDbr.s
///
///
//---------------------------------------------------------------------------------
//++
// AsmReadDbr
//
// This routine is used to Reads the current value of Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
//
// Return Value: The current value of DBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadDbr, @function
.proc AsmReadDbr
.regstk 1, 0, 0, 0
AsmReadDbr::
mov r8 = dbr[in0];;
br.ret.dpnt b0;;
.endp AsmReadDbr
//---------------------------------------------------------------------------------
//++
// AsmWriteDbr
//
// This routine is used to write the current value to Data Breakpoint Register (DBR).
//
// Arguments :
//
// On Entry : The 8-bit DBR index to read.
// The value should be written to DBR
//
// Return Value: The value written to DBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteDbr, @function
.proc AsmWriteDbr
.regstk 2, 0, 0, 0
AsmWriteDbr::
mov dbr[in0] = in1
mov r8 = in1;;
srlz.d;;
br.ret.dpnt b0;;
.endp AsmWriteDbr
//---------------------------------------------------------------------------------
//++
// AsmReadIbr
//
// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
//
// Return Value: The current value of IBR by Index.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmReadIbr, @function
.proc AsmReadIbr
.regstk 1, 0, 0, 0
AsmReadIbr::
mov r8 = ibr[in0];;
br.ret.dpnt b0;;
.endp AsmReadIbr
//---------------------------------------------------------------------------------
//++
// AsmWriteIbr
//
// This routine is used to write the current value to Instruction Breakpoint Register (IBR).
//
// Arguments :
//
// On Entry : The 8-bit IBR index.
// The value should be written to IBR
//
// Return Value: The value written to IBR.
//
//--
//----------------------------------------------------------------------------------
.text
.type AsmWriteIbr, @function
.proc AsmWriteIbr
.regstk 2, 0, 0, 0
AsmWriteIbr::
mov ibr[in0] = in1
mov r8 = in1;;
srlz.i;;
br.ret.dpnt b0;;
.endp AsmWriteIbr
| {
"language": "Assembly"
} |
;------------------------------------------------------------------------------
;*
;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
;* SPDX-License-Identifier: BSD-2-Clause-Patent
;*
;*
;------------------------------------------------------------------------------
SECTION .rodata
;
; Float control word initial value:
; all exceptions masked, double-extended-precision, round-to-nearest
;
mFpuControlWord: DW 0x37F
;
; Multimedia-extensions control word:
; all exceptions masked, round-to-nearest, flush to zero for masked underflow
;
mMmxControlWord: DD 0x1F80
DEFAULT REL
SECTION .text
;
; Initializes floating point units for requirement of UEFI specification.
;
; This function initializes floating-point control word to 0x027F (all exceptions
; masked,double-precision, round-to-nearest) and multimedia-extensions control word
; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
; for masked underflow).
;
global ASM_PFX(InitializeFloatingPointUnits)
ASM_PFX(InitializeFloatingPointUnits):
;
; Initialize floating point units
;
finit
fldcw [mFpuControlWord]
;
; Set OSFXSR bit 9 in CR4
;
mov rax, cr4
or rax, BIT9
mov cr4, rax
ldmxcsr [mMmxControlWord]
ret
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBAIO
bool "libaio"
depends on \
BR2_arm || BR2_armeb || BR2_avr32 || BR2_i386 || \
BR2_m68k || BR2_mips || BR2_mipsel || BR2_powerpc || \
BR2_sparc || BR2_x86_64
help
Library for doing asynchronous I/O
| {
"language": "Assembly"
} |
; RUN: opt < %s -instcombine -S | FileCheck %s
@T1 = external constant i32
@T2 = external constant i32
@T3 = external constant i32
declare i32 @generic_personality(i32, i64, i8*, i8*)
declare i32 @__gxx_personality_v0(i32, i64, i8*, i8*)
declare i32 @__objc_personality_v0(i32, i64, i8*, i8*)
declare i32 @__C_specific_handler(...)
declare void @bar()
define void @foo_generic() personality i32 (i32, i64, i8*, i8*)* @generic_personality {
; CHECK-LABEL: @foo_generic(
invoke void @bar()
to label %cont.a unwind label %lpad.a
cont.a:
invoke void @bar()
to label %cont.b unwind label %lpad.b
cont.b:
invoke void @bar()
to label %cont.c unwind label %lpad.c
cont.c:
invoke void @bar()
to label %cont.d unwind label %lpad.d
cont.d:
invoke void @bar()
to label %cont.e unwind label %lpad.e
cont.e:
invoke void @bar()
to label %cont.f unwind label %lpad.f
cont.f:
invoke void @bar()
to label %cont.g unwind label %lpad.g
cont.g:
invoke void @bar()
to label %cont.h unwind label %lpad.h
cont.h:
invoke void @bar()
to label %cont.i unwind label %lpad.i
cont.i:
ret void
lpad.a:
%a = landingpad { i8*, i32 }
catch i32* @T1
catch i32* @T2
catch i32* @T1
catch i32* @T2
unreachable
; CHECK: %a = landingpad
; CHECK-NEXT: @T1
; CHECK-NEXT: @T2
; CHECK-NEXT: unreachable
lpad.b:
%b = landingpad { i8*, i32 }
filter [0 x i32*] zeroinitializer
catch i32* @T1
unreachable
; CHECK: %b = landingpad
; CHECK-NEXT: filter
; CHECK-NEXT: unreachable
lpad.c:
%c = landingpad { i8*, i32 }
catch i32* @T1
filter [1 x i32*] [i32* @T1]
catch i32* @T2
unreachable
; Caught types should not be removed from filters
; CHECK: %c = landingpad
; CHECK-NEXT: catch i32* @T1
; CHECK-NEXT: filter [1 x i32*] [i32* @T1]
; CHECK-NEXT: catch i32* @T2
; CHECK-NEXT: unreachable
lpad.d:
%d = landingpad { i8*, i32 }
filter [3 x i32*] zeroinitializer
unreachable
; CHECK: %d = landingpad
; CHECK-NEXT: filter [1 x i32*] zeroinitializer
; CHECK-NEXT: unreachable
lpad.e:
%e = landingpad { i8*, i32 }
catch i32* @T1
filter [3 x i32*] [i32* @T1, i32* @T2, i32* @T2]
unreachable
; Caught types should not be removed from filters
; CHECK: %e = landingpad
; CHECK-NEXT: catch i32* @T1
; CHECK-NEXT: filter [2 x i32*] [i32* @T1, i32* @T2]
; CHECK-NEXT: unreachable
lpad.f:
%f = landingpad { i8*, i32 }
filter [2 x i32*] [i32* @T2, i32* @T1]
filter [1 x i32*] [i32* @T1]
unreachable
; CHECK: %f = landingpad
; CHECK-NEXT: filter [1 x i32*] [i32* @T1]
; CHECK-NEXT: unreachable
lpad.g:
%g = landingpad { i8*, i32 }
filter [1 x i32*] [i32* @T1]
catch i32* @T3
filter [2 x i32*] [i32* @T2, i32* @T1]
unreachable
; CHECK: %g = landingpad
; CHECK-NEXT: filter [1 x i32*] [i32* @T1]
; CHECK-NEXT: catch i32* @T3
; CHECK-NEXT: unreachable
lpad.h:
%h = landingpad { i8*, i32 }
filter [2 x i32*] [i32* @T1, i32* null]
filter [1 x i32*] zeroinitializer
unreachable
; CHECK: %h = landingpad
; CHECK-NEXT: filter [1 x i32*] zeroinitializer
; CHECK-NEXT: unreachable
lpad.i:
%i = landingpad { i8*, i32 }
cleanup
filter [0 x i32*] zeroinitializer
unreachable
; CHECK: %i = landingpad
; CHECK-NEXT: filter
; CHECK-NEXT: unreachable
}
define void @foo_cxx() personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0 {
; CHECK-LABEL: @foo_cxx(
invoke void @bar()
to label %cont.a unwind label %lpad.a
cont.a:
invoke void @bar()
to label %cont.b unwind label %lpad.b
cont.b:
invoke void @bar()
to label %cont.c unwind label %lpad.c
cont.c:
invoke void @bar()
to label %cont.d unwind label %lpad.d
cont.d:
ret void
lpad.a:
%a = landingpad { i8*, i32 }
catch i32* null
catch i32* @T1
unreachable
; CHECK: %a = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
lpad.b:
%b = landingpad { i8*, i32 }
filter [1 x i32*] zeroinitializer
unreachable
; CHECK: %b = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.c:
%c = landingpad { i8*, i32 }
filter [2 x i32*] [i32* @T1, i32* null]
unreachable
; CHECK: %c = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.d:
%d = landingpad { i8*, i32 }
cleanup
catch i32* null
unreachable
; CHECK: %d = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
}
define void @foo_objc() personality i32 (i32, i64, i8*, i8*)* @__objc_personality_v0 {
; CHECK-LABEL: @foo_objc(
invoke void @bar()
to label %cont.a unwind label %lpad.a
cont.a:
invoke void @bar()
to label %cont.b unwind label %lpad.b
cont.b:
invoke void @bar()
to label %cont.c unwind label %lpad.c
cont.c:
invoke void @bar()
to label %cont.d unwind label %lpad.d
cont.d:
ret void
lpad.a:
%a = landingpad { i8*, i32 }
catch i32* null
catch i32* @T1
unreachable
; CHECK: %a = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
lpad.b:
%b = landingpad { i8*, i32 }
filter [1 x i32*] zeroinitializer
unreachable
; CHECK: %b = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.c:
%c = landingpad { i8*, i32 }
filter [2 x i32*] [i32* @T1, i32* null]
unreachable
; CHECK: %c = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.d:
%d = landingpad { i8*, i32 }
cleanup
catch i32* null
unreachable
; CHECK: %d = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
}
define void @foo_seh() personality i32 (...)* @__C_specific_handler {
; CHECK-LABEL: @foo_seh(
invoke void @bar()
to label %cont.a unwind label %lpad.a
cont.a:
invoke void @bar()
to label %cont.b unwind label %lpad.b
cont.b:
invoke void @bar()
to label %cont.c unwind label %lpad.c
cont.c:
invoke void @bar()
to label %cont.d unwind label %lpad.d
cont.d:
ret void
lpad.a:
%a = landingpad { i8*, i32 }
catch i32* null
catch i32* @T1
unreachable
; CHECK: %a = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
lpad.b:
%b = landingpad { i8*, i32 }
filter [1 x i32*] zeroinitializer
unreachable
; CHECK: %b = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.c:
%c = landingpad { i8*, i32 }
filter [2 x i32*] [i32* @T1, i32* null]
unreachable
; CHECK: %c = landingpad
; CHECK-NEXT: cleanup
; CHECK-NEXT: unreachable
lpad.d:
%d = landingpad { i8*, i32 }
cleanup
catch i32* null
unreachable
; CHECK: %d = landingpad
; CHECK-NEXT: null
; CHECK-NEXT: unreachable
}
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for 386, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
; $ clang++ -S -emit-llvm -o - -gdwarf-5 -o - -O1 tail2.cc
; volatile int sink;
; void __attribute__((noinline)) bat() { sink++; }
; void __attribute__((noinline)) bar() { sink++; }
; void __attribute__((noinline)) foo() {
; bar(); bat();
; bar(); bat();
; }
; int __attribute__((disable_tail_calls)) main() { foo(); }
; On Windows, we don't handle the relocations needed for AT_return_pc properly
; and fail with "failed to compute relocation: IMAGE_REL_AMD64_ADDR32".
; UNSUPPORTED: cygwin,windows-gnu,windows-msvc
; REQUIRES: object-emission
; RUN: %llc_dwarf -mtriple=x86_64-- < %s -o - | FileCheck %s -check-prefix=ASM
; RUN: %llc_dwarf -debugger-tune=lldb -mtriple=x86_64-- < %s -filetype=obj -o %t.o
; RUN: llvm-dwarfdump %t.o -o - | FileCheck %s -check-prefix=OBJ -implicit-check-not=DW_TAG_call_site
; RUN: llvm-dwarfdump -verify %t.o 2>&1 | FileCheck %s -check-prefix=VERIFY
; RUN: llvm-dwarfdump -statistics %t.o | FileCheck %s -check-prefix=STATS
; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis -o /dev/null
; VERIFY: No errors.
; STATS: "call site DIEs":6
@sink = global i32 0, align 4, !dbg !0
; ASM: DW_TAG_subprogram
; ASM: DW_AT_call_all_calls
; OBJ: [[bat_sp:.*]]: DW_TAG_subprogram
; OBJ: DW_AT_call_all_calls (true)
; OBJ: DW_AT_name ("bat")
define void @_Z3batv() !dbg !13 {
entry:
%0 = load volatile i32, i32* @sink, align 4, !dbg !16, !tbaa !17
%inc = add nsw i32 %0, 1, !dbg !16
store volatile i32 %inc, i32* @sink, align 4, !dbg !16, !tbaa !17
ret void, !dbg !21
}
; ASM: DW_TAG_subprogram
; ASM: DW_AT_call_all_calls
; OBJ: [[bar_sp:.*]]: DW_TAG_subprogram
; OBJ: DW_AT_call_all_calls (true)
; OBJ: DW_AT_name ("bar")
define void @_Z3barv() !dbg !22 {
entry:
%0 = load volatile i32, i32* @sink, align 4, !dbg !23, !tbaa !17
%inc = add nsw i32 %0, 1, !dbg !23
store volatile i32 %inc, i32* @sink, align 4, !dbg !23, !tbaa !17
ret void, !dbg !24
}
; ASM: DW_TAG_subprogram
; ASM: DW_AT_call_all_calls
; OBJ: [[foo_sp:.*]]: DW_TAG_subprogram
; OBJ: DW_AT_call_all_calls (true)
; OBJ: DW_AT_name ("foo")
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_origin ([[bar_sp]])
; OBJ: DW_AT_call_return_pc
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_origin ([[bat_sp]])
; OBJ: DW_AT_call_return_pc
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_origin ([[bar_sp]])
; OBJ: DW_AT_call_return_pc
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_origin ([[bat_sp]])
; OBJ: DW_AT_call_tail_call
define void @_Z3foov() !dbg !25 {
entry:
tail call void @_Z3barv(), !dbg !26
tail call void @_Z3batv(), !dbg !27
tail call void @_Z3barv(), !dbg !26
tail call void @_Z3batv(), !dbg !27
ret void, !dbg !28
}
; ASM: DW_TAG_subprogram
; ASM: DW_AT_call_all_calls
; OBJ: DW_TAG_subprogram
; OBJ: DW_AT_call_all_calls (true)
; OBJ: DW_AT_name ("main")
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_origin ([[foo_sp]])
; OBJ: DW_AT_call_return_pc
; OBJ: DW_TAG_call_site
; OBJ: DW_AT_call_target
; OBJ: DW_AT_call_return_pc
define i32 @main() !dbg !29 {
entry:
call void @_Z3foov(), !dbg !32
%indirect_target = load void ()*, void ()** undef
call void %indirect_target()
call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
ret i32 0, !dbg !33
}
!llvm.dbg.cu = !{!2}
!llvm.module.flags = !{!8, !9, !10, !11}
!llvm.ident = !{!12}
!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression())
!1 = distinct !DIGlobalVariable(name: "sink", scope: !2, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true)
!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "clang version 7.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5)
!3 = !DIFile(filename: "/Users/vsk/src/llvm.org-tailcall/tail2.cc", directory: "/Users/vsk/src/builds/llvm-project-tailcall-RA", checksumkind: CSK_MD5, checksum: "3b61952c21b7f657ddb7c0ad44cf5529")
!4 = !{}
!5 = !{!0}
!6 = !DIDerivedType(tag: DW_TAG_volatile_type, baseType: !7)
!7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!8 = !{i32 2, !"Dwarf Version", i32 5}
!9 = !{i32 2, !"Debug Info Version", i32 3}
!10 = !{i32 1, !"wchar_size", i32 4}
!11 = !{i32 7, !"PIC Level", i32 2}
!12 = !{!"clang version 7.0.0 "}
!13 = distinct !DISubprogram(name: "bat", linkageName: "_Z3batv", scope: !3, file: !3, line: 2, type: !14, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, isOptimized: true, unit: !2, retainedNodes: !4)
!14 = !DISubroutineType(types: !15)
!15 = !{null}
!16 = !DILocation(line: 2, column: 44, scope: !13)
!17 = !{!18, !18, i64 0}
!18 = !{!"int", !19, i64 0}
!19 = !{!"omnipotent char", !20, i64 0}
!20 = !{!"Simple C++ TBAA"}
!21 = !DILocation(line: 2, column: 48, scope: !13)
!22 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !3, file: !3, line: 3, type: !14, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, isOptimized: true, unit: !2, retainedNodes: !4)
!23 = !DILocation(line: 3, column: 44, scope: !22)
!24 = !DILocation(line: 3, column: 48, scope: !22)
!25 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", scope: !3, file: !3, line: 4, type: !14, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, isOptimized: true, unit: !2, retainedNodes: !4)
!26 = !DILocation(line: 5, column: 3, scope: !25)
!27 = !DILocation(line: 6, column: 3, scope: !25)
!28 = !DILocation(line: 7, column: 1, scope: !25)
!29 = distinct !DISubprogram(name: "main", scope: !3, file: !3, line: 8, type: !30, isLocal: false, isDefinition: true, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, isOptimized: true, unit: !2, retainedNodes: !4)
!30 = !DISubroutineType(types: !31)
!31 = !{!7}
!32 = !DILocation(line: 8, column: 50, scope: !29)
!33 = !DILocation(line: 8, column: 57, scope: !29)
| {
"language": "Assembly"
} |
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Immediate out of lower bound [-16, 14].
ld2h {z12.h, z13.h}, p4/z, [x12, #-18, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
// CHECK-NEXT: ld2h {z12.h, z13.h}, p4/z, [x12, #-18, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h {z7.h, z8.h}, p3/z, [x1, #16, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
// CHECK-NEXT: ld2h {z7.h, z8.h}, p3/z, [x1, #16, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Immediate not a multiple of two.
ld2h {z12.h, z13.h}, p4/z, [x12, #-7, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
// CHECK-NEXT: ld2h {z12.h, z13.h}, p4/z, [x12, #-7, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14].
// CHECK-NEXT: ld2h {z7.h, z8.h}, p3/z, [x1, #5, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid scalar + scalar addressing modes
ld2h { z0.h, z1.h }, p0/z, [x0, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, xzr]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.h }, p0/z, [x0, w0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
// CHECK-NEXT: ld2h { z0.h, z1.h }, p0/z, [x0, w0, uxtw]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: ld2h {z2.h, z3.h}, p8/z, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
ld2h { }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: ld2h { }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.h, z2.h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2h { z0.h, z1.h, z2.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z1.s }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
// CHECK-NEXT: ld2h { z0.h, z1.s }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { z0.h, z2.h }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
// CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ld2h { v0.2d, v1.2d }, p0/z, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z21.h, p5/z, z28.h
ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z21, z28
ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
| {
"language": "Assembly"
} |
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-freebsd10.0"
; RUN: llc < %s -march=ppc64 -relocation-model=pic | FileCheck %s
@a = common global i32 0, align 4
define void @test1(i32 %c) nounwind {
entry:
br label %for.body
for.body: ; preds = %for.body, %entry
%i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = load volatile i32* @a, align 4
%add = add nsw i32 %0, %c
store volatile i32 %add, i32* @a, align 4
%inc = add nsw i32 %i.01, 1
%exitcond = icmp eq i32 %inc, 2048
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body
ret void
; CHECK: @test1
; CHECK-NOT: or 3, 3, 3
; CHECK: mtctr
; CHECK-NOT: addi {[0-9]+}
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
define void @test2(i32 %c, i32 %d) nounwind {
entry:
%cmp1 = icmp sgt i32 %d, 0
br i1 %cmp1, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%0 = load volatile i32* @a, align 4
%add = add nsw i32 %0, %c
store volatile i32 %add, i32* @a, align 4
%inc = add nsw i32 %i.02, 1
%exitcond = icmp eq i32 %inc, %d
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
; CHECK: @test2
; CHECK: mtctr
; CHECK-NOT: addi {[0-9]+}
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
define void @test3(i32 %c, i32 %d) nounwind {
entry:
%cmp1 = icmp sgt i32 %d, 0
br i1 %cmp1, label %for.body, label %for.end
for.body: ; preds = %entry, %for.body
%i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
%mul = mul nsw i32 %i.02, %c
%0 = load volatile i32* @a, align 4
%add = add nsw i32 %0, %mul
store volatile i32 %add, i32* @a, align 4
%inc = add nsw i32 %i.02, 1
%exitcond = icmp eq i32 %inc, %d
br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry
ret void
; CHECK: @test3
; CHECK: mtctr
; CHECK-NOT: addi {[0-9]+}
; CHECK-NOT: cmplwi
; CHECK: bdnz
}
@tls_var = external thread_local global i8
define i32 @test4() {
entry:
br label %for.body
for.body: ; preds = %for.body, %entry
%phi = phi i32 [ %dec, %for.body ], [ undef, %entry ]
%load = ptrtoint i8* @tls_var to i32
%dec = add i32 %phi, -1
%cmp = icmp sgt i32 %phi, 1
br i1 %cmp, label %for.body, label %return
return: ; preds = %for.body
ret i32 %load
; CHECK-LABEL: @test4
; CHECK-NOT: mtctr
; CHECK: addi {{[0-9]+}}
; CHECK: cmpwi
; CHECK-NOT: bdnz
; CHECK: bgt
}
| {
"language": "Assembly"
} |
Prism.languages.git = {
/*
* A simple one line comment like in a git status command
* For instance:
* $ git status
* # On branch infinite-scroll
* # Your branch and 'origin/sharedBranches/frontendTeam/infinite-scroll' have diverged,
* # and have 1 and 2 different commits each, respectively.
* nothing to commit (working directory clean)
*/
'comment': /^#.*/m,
/*
* Regexp to match the changed lines in a git diff output. Check the example below.
*/
'deleted': /^[-–].*/m,
'inserted': /^\+.*/m,
/*
* a string (double and simple quote)
*/
'string': /("|')(\\?.)*?\1/m,
/*
* a git command. It starts with a random prompt finishing by a $, then "git" then some other parameters
* For instance:
* $ git add file.txt
*/
'command': {
pattern: /^.*\$ git .*$/m,
inside: {
/*
* A git command can contain a parameter starting by a single or a double dash followed by a string
* For instance:
* $ git diff --cached
* $ git log -p
*/
'parameter': /\s(--|-)\w+/m
}
},
/*
* Coordinates displayed in a git diff command
* For instance:
* $ git diff
* diff --git file.txt file.txt
* index 6214953..1d54a52 100644
* --- file.txt
* +++ file.txt
* @@ -1 +1,2 @@
* -Here's my tetx file
* +Here's my text file
* +And this is the second line
*/
'coord': /^@@.*@@$/m,
/*
* Match a "commit [SHA1]" line in a git log output.
* For instance:
* $ git log
* commit a11a14ef7e26f2ca62d4b35eac455ce636d0dc09
* Author: lgiraudel
* Date: Mon Feb 17 11:18:34 2014 +0100
*
* Add of a new line
*/
'commit_sha1': /^commit \w{40}$/m
};
| {
"language": "Assembly"
} |
// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build riscv64,!gccgo
#include "textflag.h"
//
// System calls for linux/riscv64.
//
// Where available, just jump to package syscall's implementation of
// these functions.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-48
CALL runtime·entersyscall(SB)
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV $0, A3
MOV $0, A4
MOV $0, A5
MOV $0, A6
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP) // r1
MOV A1, r2+40(FP) // r2
CALL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-48
MOV a1+8(FP), A0
MOV a2+16(FP), A1
MOV a3+24(FP), A2
MOV ZERO, A3
MOV ZERO, A4
MOV ZERO, A5
MOV trap+0(FP), A7 // syscall entry
ECALL
MOV A0, r1+32(FP)
MOV A1, r2+40(FP)
RET
| {
"language": "Assembly"
} |
//===-- Implementation of logb function -----------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "src/__support/common.h"
#include "utils/FPUtil/ManipulationFunctions.h"
namespace __llvm_libc {
double LLVM_LIBC_ENTRYPOINT(logb)(double x) { return fputil::logb(x); }
} // namespace __llvm_libc
| {
"language": "Assembly"
} |
ENTRY(Reset_Handler)
_estack = 0x20002000; /* end of $(RAM_LENGTH) RAM */
_Min_Heap_Size = 0; /* required amount of heap */
_Min_Stack_Size = 0x100; /* required amount of stack (256 bytes) */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
}
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array*))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = .;
/* Initialized data sections goes into SRAM, load LMA copy after code */
.data : AT ( _sidata )
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}
| {
"language": "Assembly"
} |
// Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for amd64, Solaris are implemented in runtime/syscall_solaris.go
//
TEXT ·sysvicall6(SB),NOSPLIT,$0-88
JMP syscall·sysvicall6(SB)
TEXT ·rawSysvicall6(SB),NOSPLIT,$0-88
JMP syscall·rawSysvicall6(SB)
| {
"language": "Assembly"
} |
menu "SoC Audio for Freescale CPUs"
comment "Common SoC Audio options for Freescale CPUs:"
config SND_SOC_FSL_ASRC
tristate "Asynchronous Sample Rate Converter (ASRC) module support"
depends on HAS_DMA
select REGMAP_MMIO
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y if you want to add Asynchronous Sample Rate Converter (ASRC)
support for the Freescale CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_SOC_FSL_SAI
tristate "Synchronous Audio Interface (SAI) module support"
select REGMAP_MMIO
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y if you want to add Synchronous Audio Interface (SAI)
support for the Freescale CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_SOC_FSL_SSI
tristate "Synchronous Serial Interface module (SSI) support"
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC)
select REGMAP_MMIO
help
Say Y if you want to add Synchronous Serial Interface (SSI)
support for the Freescale CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_SOC_FSL_SPDIF
tristate "Sony/Philips Digital Interface (S/PDIF) module support"
select REGMAP_MMIO
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC)
select BITREVERSE
help
Say Y if you want to add Sony/Philips Digital Interface (SPDIF)
support for the Freescale CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_SOC_FSL_ESAI
tristate "Enhanced Serial Audio Interface (ESAI) module support"
select REGMAP_MMIO
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
help
Say Y if you want to add Enhanced Synchronous Audio Interface
(ESAI) support for the Freescale CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_SOC_FSL_UTILS
tristate
config SND_SOC_IMX_PCM_DMA
tristate
select SND_SOC_GENERIC_DMAENGINE_PCM
config SND_SOC_IMX_AUDMUX
tristate "Digital Audio Mux module support"
help
Say Y if you want to add Digital Audio Mux (AUDMUX) support
for the ARM i.MX CPUs.
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
config SND_POWERPC_SOC
tristate "SoC Audio for Freescale PowerPC CPUs"
depends on FSL_SOC || PPC_MPC52xx
help
Say Y or M if you want to add support for codecs attached to
the PowerPC CPUs.
config SND_IMX_SOC
tristate "SoC Audio for Freescale i.MX CPUs"
depends on ARCH_MXC || COMPILE_TEST
help
Say Y or M if you want to add support for codecs attached to
the i.MX CPUs.
if SND_POWERPC_SOC
config SND_MPC52xx_DMA
tristate
config SND_SOC_POWERPC_DMA
tristate
comment "SoC Audio support for Freescale PPC boards:"
config SND_SOC_MPC8610_HPCD
tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
# I2C is necessary for the CS4270 driver
depends on MPC8610_HPCD && I2C
select SND_SOC_FSL_SSI
select SND_SOC_FSL_UTILS
select SND_SOC_POWERPC_DMA
select SND_SOC_CS4270
select SND_SOC_CS4270_VD33_ERRATA
default y if MPC8610_HPCD
help
Say Y if you want to enable audio on the Freescale MPC8610 HPCD.
config SND_SOC_P1022_DS
tristate "ALSA SoC support for the Freescale P1022 DS board"
# I2C is necessary for the WM8776 driver
depends on P1022_DS && I2C
select SND_SOC_FSL_SSI
select SND_SOC_FSL_UTILS
select SND_SOC_POWERPC_DMA
select SND_SOC_WM8776
default y if P1022_DS
help
Say Y if you want to enable audio on the Freescale P1022 DS board.
This will also include the Wolfson Microelectronics WM8776 codec
driver.
config SND_SOC_P1022_RDK
tristate "ALSA SoC support for the Freescale / iVeia P1022 RDK board"
# I2C is necessary for the WM8960 driver
depends on P1022_RDK && I2C
select SND_SOC_FSL_SSI
select SND_SOC_FSL_UTILS
select SND_SOC_POWERPC_DMA
select SND_SOC_WM8960
default y if P1022_RDK
help
Say Y if you want to enable audio on the Freescale / iVeia
P1022 RDK board. This will also include the Wolfson
Microelectronics WM8960 codec driver.
config SND_SOC_MPC5200_I2S
tristate "Freescale MPC5200 PSC in I2S mode driver"
depends on PPC_MPC52xx && PPC_BESTCOMM
select SND_MPC52xx_DMA
select PPC_BESTCOMM_GEN_BD
help
Say Y here to support the MPC5200 PSCs in I2S mode.
config SND_SOC_MPC5200_AC97
tristate "Freescale MPC5200 PSC in AC97 mode driver"
depends on PPC_MPC52xx && PPC_BESTCOMM
select SND_SOC_AC97_BUS
select SND_MPC52xx_DMA
select PPC_BESTCOMM_GEN_BD
help
Say Y here to support the MPC5200 PSCs in AC97 mode.
config SND_MPC52xx_SOC_PCM030
tristate "SoC AC97 Audio support for Phytec pcm030 and WM9712"
depends on PPC_MPC5200_SIMPLE
select SND_SOC_MPC5200_AC97
select SND_SOC_WM9712
help
Say Y if you want to add support for sound on the Phytec pcm030
baseboard.
config SND_MPC52xx_SOC_EFIKA
tristate "SoC AC97 Audio support for bbplan Efika and STAC9766"
depends on PPC_EFIKA
select SND_SOC_MPC5200_AC97
select SND_SOC_STAC9766
help
Say Y if you want to add support for sound on the Efika.
endif # SND_POWERPC_SOC
config SND_SOC_IMX_PCM_FIQ
tristate
default y if SND_SOC_IMX_SSI=y && (SND_SOC_FSL_SSI=m || SND_SOC_FSL_SPDIF=m) && (MXC_TZIC || MXC_AVIC)
select FIQ
if SND_IMX_SOC
config SND_SOC_IMX_SSI
tristate
select SND_SOC_FSL_UTILS
comment "SoC Audio support for Freescale i.MX boards:"
config SND_MXC_SOC_WM1133_EV1
tristate "Audio on the i.MX31ADS with WM1133-EV1 fitted"
depends on MACH_MX31ADS_WM1133_EV1
select SND_SOC_WM8350
select SND_SOC_IMX_PCM_FIQ
select SND_SOC_IMX_AUDMUX
select SND_SOC_IMX_SSI
help
Enable support for audio on the i.MX31ADS with the WM1133-EV1
PMIC board with WM8835x fitted.
config SND_SOC_MX27VIS_AIC32X4
tristate "SoC audio support for Visstrim M10 boards"
depends on MACH_IMX27_VISSTRIM_M10 && I2C
select SND_SOC_TLV320AIC32X4
select SND_SOC_IMX_PCM_DMA
select SND_SOC_IMX_AUDMUX
select SND_SOC_IMX_SSI
help
Say Y if you want to add support for SoC audio on Visstrim SM10
board with TLV320AIC32X4 codec.
config SND_SOC_PHYCORE_AC97
tristate "SoC Audio support for Phytec phyCORE (and phyCARD) boards"
depends on MACH_PCM043 || MACH_PCA100
select SND_SOC_AC97_BUS
select SND_SOC_WM9712
select SND_SOC_IMX_PCM_FIQ
select SND_SOC_IMX_AUDMUX
select SND_SOC_IMX_SSI
help
Say Y if you want to add support for SoC audio on Phytec phyCORE
and phyCARD boards in AC97 mode
config SND_SOC_EUKREA_TLV320
tristate "Eukrea TLV320"
depends on ARCH_MXC && !ARM64 && I2C
select SND_SOC_TLV320AIC23_I2C
select SND_SOC_IMX_AUDMUX
select SND_SOC_IMX_SSI
select SND_SOC_FSL_SSI
select SND_SOC_IMX_PCM_DMA
help
Enable I2S based access to the TLV320AIC23B codec attached
to the SSI interface
config SND_SOC_IMX_WM8962
tristate "SoC Audio support for i.MX boards with wm8962"
depends on OF && I2C && INPUT
select SND_SOC_WM8962
select SND_SOC_IMX_PCM_DMA
select SND_SOC_IMX_AUDMUX
select SND_SOC_FSL_SSI
help
Say Y if you want to add support for SoC audio on an i.MX board with
a wm8962 codec.
config SND_SOC_IMX_ES8328
tristate "SoC Audio support for i.MX boards with the ES8328 codec"
depends on OF && (I2C || SPI)
select SND_SOC_ES8328_I2C if I2C
select SND_SOC_ES8328_SPI if SPI_MASTER
select SND_SOC_IMX_PCM_DMA
select SND_SOC_IMX_AUDMUX
select SND_SOC_FSL_SSI
help
Say Y if you want to add support for the ES8328 audio codec connected
via SSI/I2S over either SPI or I2C.
config SND_SOC_IMX_SGTL5000
tristate "SoC Audio support for i.MX boards with sgtl5000"
depends on OF && I2C
select SND_SOC_SGTL5000
select SND_SOC_IMX_PCM_DMA
select SND_SOC_IMX_AUDMUX
select SND_SOC_FSL_SSI
help
Say Y if you want to add support for SoC audio on an i.MX board with
a sgtl5000 codec.
config SND_SOC_IMX_SPDIF
tristate "SoC Audio support for i.MX boards with S/PDIF"
select SND_SOC_IMX_PCM_DMA
select SND_SOC_FSL_SPDIF
help
SoC Audio support for i.MX boards with S/PDIF
Say Y if you want to add support for SoC audio on an i.MX board with
a S/DPDIF.
config SND_SOC_IMX_MC13783
tristate "SoC Audio support for I.MX boards with mc13783"
depends on MFD_MC13XXX && ARM
select SND_SOC_IMX_SSI
select SND_SOC_IMX_AUDMUX
select SND_SOC_MC13783
select SND_SOC_IMX_PCM_DMA
config SND_SOC_FSL_ASOC_CARD
tristate "Generic ASoC Sound Card with ASRC support"
depends on OF && I2C
# enforce SND_SOC_FSL_ASOC_CARD=m if SND_AC97_CODEC=m:
depends on SND_AC97_CODEC || SND_AC97_CODEC=n
select SND_SOC_IMX_AUDMUX
select SND_SOC_IMX_PCM_DMA
select SND_SOC_FSL_ESAI
select SND_SOC_FSL_SAI
select SND_SOC_FSL_SSI
help
ALSA SoC Audio support with ASRC feature for Freescale SoCs that have
ESAI/SAI/SSI and connect with external CODECs such as WM8962, CS42888,
CS4271, CS4272 and SGTL5000.
Say Y if you want to add support for Freescale Generic ASoC Sound Card.
endif # SND_IMX_SOC
endmenu
| {
"language": "Assembly"
} |
.file 1 "jalx-2-main.c"
.section .mdebug.abi32
.previous
.gnu_attribute 4, 1
.abicalls
.option pic0
.text
.align 2
.globl internal_function
.set nomips16
.set micromips
.ent internal_function
.type internal_function, @function
internal_function:
.frame $fp,8,$31 # vars= 0, regs= 1/0, args= 0, gp= 0
.mask 0x40000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
addiu $sp,$sp,-8
sw $fp,4($sp)
move $fp,$sp
move $sp,$fp
lw $fp,4($sp)
jraddiusp 8
.set macro
.set reorder
.end internal_function
.size internal_function, .-internal_function
.rdata
.align 2
$LC0:
.ascii "hello world\012\000"
.text
.align 2
.globl main
.set nomips16
.set micromips
.ent main
.type main, @function
main:
.frame $fp,32,$31 # vars= 0, regs= 2/0, args= 16, gp= 8
.mask 0xc0000000,-4
.fmask 0x00000000,0
.set noreorder
.set nomacro
addiu $sp,$sp,-32
sw $31,28($sp)
sw $fp,24($sp)
move $fp,$sp
sw $4,32($fp)
sw $5,36($fp)
lui $2,%hi($LC0)
addiu $4,$2,%lo($LC0)
jal printf
nop
jal internal_function
nop
jal external_function
nop
move $sp,$fp
lw $31,28($sp)
lw $fp,24($sp)
jraddiusp 32
.set macro
.set reorder
.end main
.size main, .-main
.ident "GCC: (Sourcery G++ Lite 4.4-999999 - Preview) 4.4.1"
| {
"language": "Assembly"
} |
%% 134
<_>1*2 <_>2
<_>2 <_>1*2 <_>2 <3 5>4 <4 6>
<_>2 <5>4 <6!> <_>1 <_>1.*2
<_>1.*4
<_>1. <7 9>2 <6 8> <5 7> <_+ 5> <6>1 <_>2 <6>1
<_>1.*2 <_!>2 <_+>1 <_->2 <_!>1 <_>1.
<_>1.*2 <6!>1. <_>1.*2
<_>1. <5> <3 5>1 <4! 6>2 <_>1.*2
<_>1.*2 <5>1 <6>2 <_>1.*2
<_>1. <6> <_>1.*5
<_>1. <_>1*3
<_>1*2 <_>2.*2
<5>2 <6+>4 <_>2.*3
<_>2.*3 <_>4 <7> <6>
<_>2.*4
<_>2. <_-> <_>2.*2
<_>2. <5>2 <6>4 <5>2 <6>4 <3! 9>2 <8>4
<_>2. <_>4 <6>2 <_>2.*2
<_>2.*4
<_>
<5>2 <6>4 <3! 9>2 <8>4 <_! 7>2 <_->4 <_> <_->2
<_!>2. <_> <_! 7>2. <4 6>4 <4 5> <3>
<_>2.*2 <_!>2. <7>4 <6>2
<_>2. <_>4 <6>2 <5>4 <6>2 <_>2.*2
<_>2.*3 <9>2 <8>4 <7>2.
<_>4 <6>2 <5>4 <6>2 <5>4 <6>2 <_>2.*3
<_>1 <4 6 8>2 <4 7 9> <_>1 <6>2 <6> | {
"language": "Assembly"
} |
config BR2_PACKAGE_ZMQPP
bool "zmqpp"
depends on !BR2_avr32 # compiler needs c++0x support
depends on !BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC201103 # c++0x support
depends on !BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC201009 # c++0x support
depends on BR2_INSTALL_LIBSTDCPP
depends on BR2_INET_IPV6 # zeromq
depends on BR2_LARGEFILE # util-linux
depends on BR2_USE_WCHAR # util-linux
depends on BR2_TOOLCHAIN_HAS_THREADS # zeromq
select BR2_PACKAGE_ZEROMQ
help
C++ binding for zeromq (ZeroMQ, 0MQ, zmq).
This C++ binding is a 'high-level' library that hides most of the
C-style interface core zeromq provides.
http://github.com/benjamg/zmqpp
comment "zmqpp needs a toolchain w/ C++, IPv6, largefile, wchar, threads"
depends on !BR2_avr32
depends on !(BR2_INSTALL_LIBSTDCPP && BR2_INET_IPV6 && BR2_LARGEFILE \
&& BR2_USE_WCHAR && BR2_TOOLCHAIN_HAS_THREADS)
if BR2_PACKAGE_ZMQPP
config BR2_PACKAGE_ZMQPP_CLIENT
bool "zmqpp client"
depends on BR2_TOOLCHAIN_HAS_THREADS # boost
select BR2_PACKAGE_BOOST
select BR2_PACKAGE_BOOST_PROGRAM_OPTIONS
help
Build and install the zmqpp client, a command line tool that can be
used to listen or send to zeromq sockets.
comment "zmqpp client needs a toolchain w/ threads"
depends on !BR2_TOOLCHAIN_HAS_THREADS
endif
| {
"language": "Assembly"
} |
dnl AMD K6 mpn_addmul_1/mpn_submul_1 -- add or subtract mpn multiple.
dnl Copyright 1999-2003, 2005 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb
C P5
C P6 model 0-8,10-12 5.94
C P6 model 9 (Banias) 5.51
C P6 model 13 (Dothan) 5.57
C P4 model 0 (Willamette)
C P4 model 1 (?)
C P4 model 2 (Northwood)
C P4 model 3 (Prescott)
C P4 model 4 (Nocona)
C AMD K6 7.65-8.5 (data dependent)
C AMD K7
C AMD K8
dnl K6: large multipliers small multipliers
dnl UNROLL_COUNT cycles/limb cycles/limb
dnl 4 9.5 7.78
dnl 8 9.0 7.78
dnl 16 8.4 7.65
dnl 32 8.4 8.2
dnl
dnl Maximum possible unrolling with the current code is 32.
dnl
dnl Unrolling to 16 limbs/loop makes the unrolled loop fit exactly in a 256
dnl byte block, which might explain the good speed at that unrolling.
deflit(UNROLL_COUNT, 16)
ifdef(`OPERATION_addmul_1', `
define(M4_inst, addl)
define(M4_function_1, mpn_addmul_1)
define(M4_function_1c, mpn_addmul_1c)
',`ifdef(`OPERATION_submul_1', `
define(M4_inst, subl)
define(M4_function_1, mpn_submul_1)
define(M4_function_1c, mpn_submul_1c)
',`m4_error(`Need OPERATION_addmul_1 or OPERATION_submul_1
')')')
MULFUNC_PROLOGUE(mpn_addmul_1 mpn_addmul_1c mpn_submul_1 mpn_submul_1c)
C mp_limb_t mpn_addmul_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C mp_limb_t mult);
C mp_limb_t mpn_addmul_1c (mp_ptr dst, mp_srcptr src, mp_size_t size,
C mp_limb_t mult, mp_limb_t carry);
C mp_limb_t mpn_submul_1 (mp_ptr dst, mp_srcptr src, mp_size_t size,
C mp_limb_t mult);
C mp_limb_t mpn_submul_1c (mp_ptr dst, mp_srcptr src, mp_size_t size,
C mp_limb_t mult, mp_limb_t carry);
C
C The jadcl0()s in the unrolled loop makes the speed data dependent. Small
C multipliers (most significant few bits clear) result in few carry bits and
C speeds up to 7.65 cycles/limb are attained. Large multipliers (most
C significant few bits set) make the carry bits 50/50 and lead to something
C more like 8.4 c/l. With adcl's both of these would be 9.3 c/l.
C
C It's important that the gains for jadcl0 on small multipliers don't come
C at the cost of slowing down other data. Tests on uniformly distributed
C random data, designed to confound branch prediction, show about a 7%
C speed-up using jadcl0 over adcl (8.93 versus 9.57 cycles/limb, with all
C overheads included).
C
C In the simple loop, jadcl0() measures slower than adcl (11.9-14.7 versus
C 11.0 cycles/limb), and hence isn't used.
C
C In the simple loop, note that running ecx from negative to zero and using
C it as an index in the two movs wouldn't help. It would save one
C instruction (2*addl+loop becoming incl+jnz), but there's nothing unpaired
C that would be collapsed by this.
C
C Attempts at a simpler main loop, with less unrolling, haven't yielded much
C success, generally running over 9 c/l.
C
C
C jadcl0
C ------
C
C jadcl0() being faster than adcl $0 seems to be an artifact of two things,
C firstly the instruction decoding and secondly the fact that there's a
C carry bit for the jadcl0 only on average about 1/4 of the time.
C
C The code in the unrolled loop decodes something like the following.
C
C decode cycles
C mull %ebp 2
C M4_inst %esi, disp(%edi) 1
C adcl %eax, %ecx 2
C movl %edx, %esi \ 1
C jnc 1f /
C incl %esi \ 1
C 1: movl disp(%ebx), %eax /
C ---
C 7
C
C In a back-to-back style test this measures 7 with the jnc not taken, or 8
C with it taken (both when correctly predicted). This is opposite to the
C measurements showing small multipliers running faster than large ones.
C Don't really know why.
C
C It's not clear how much branch misprediction might be costing. The K6
C doco says it will be 1 to 4 cycles, but presumably it's near the low end
C of that range to get the measured results.
C
C
C In the code the two carries are more or less the preceding mul product and
C the calculation is roughly
C
C x*y + u*b+v
C
C where b=2^32 is the size of a limb, x*y is the two carry limbs, and u and
C v are the two limbs it's added to (being the low of the next mul, and a
C limb from the destination).
C
C To get a carry requires x*y+u*b+v >= b^2, which is u*b+v >= b^2-x*y, and
C there are b^2-(b^2-x*y) = x*y many such values, giving a probability of
C x*y/b^2. If x, y, u and v are random and uniformly distributed between 0
C and b-1, then the total probability can be summed over x and y,
C
C 1 b-1 b-1 x*y 1 b*(b-1) b*(b-1)
C --- * sum sum --- = --- * ------- * ------- = 1/4
C b^2 x=0 y=1 b^2 b^4 2 2
C
C Actually it's a very tiny bit less than 1/4 of course. If y is fixed,
C then the probability is 1/2*y/b thus varying linearly between 0 and 1/2.
ifdef(`PIC',`
deflit(UNROLL_THRESHOLD, 9)
',`
deflit(UNROLL_THRESHOLD, 6)
')
defframe(PARAM_CARRY, 20)
defframe(PARAM_MULTIPLIER,16)
defframe(PARAM_SIZE, 12)
defframe(PARAM_SRC, 8)
defframe(PARAM_DST, 4)
TEXT
ALIGN(32)
PROLOGUE(M4_function_1c)
pushl %esi
deflit(`FRAME',4)
movl PARAM_CARRY, %esi
jmp L(start_nc)
EPILOGUE()
PROLOGUE(M4_function_1)
push %esi
deflit(`FRAME',4)
xorl %esi, %esi C initial carry
L(start_nc):
movl PARAM_SIZE, %ecx
pushl %ebx
deflit(`FRAME',8)
movl PARAM_SRC, %ebx
pushl %edi
deflit(`FRAME',12)
cmpl $UNROLL_THRESHOLD, %ecx
movl PARAM_DST, %edi
pushl %ebp
deflit(`FRAME',16)
jae L(unroll)
C simple loop
movl PARAM_MULTIPLIER, %ebp
L(simple):
C eax scratch
C ebx src
C ecx counter
C edx scratch
C esi carry
C edi dst
C ebp multiplier
movl (%ebx), %eax
addl $4, %ebx
mull %ebp
addl $4, %edi
addl %esi, %eax
adcl $0, %edx
M4_inst %eax, -4(%edi)
adcl $0, %edx
movl %edx, %esi
loop L(simple)
popl %ebp
popl %edi
popl %ebx
movl %esi, %eax
popl %esi
ret
C -----------------------------------------------------------------------------
C The unrolled loop uses a "two carry limbs" scheme. At the top of the loop
C the carries are ecx=lo, esi=hi, then they swap for each limb processed.
C For the computed jump an odd size means they start one way around, an even
C size the other.
C
C VAR_JUMP holds the computed jump temporarily because there's not enough
C registers at the point of doing the mul for the initial two carry limbs.
C
C The add/adc for the initial carry in %esi is necessary only for the
C mpn_addmul/submul_1c entry points. Duplicating the startup code to
C eliminate this for the plain mpn_add/submul_1 doesn't seem like a good
C idea.
dnl overlapping with parameters already fetched
define(VAR_COUNTER, `PARAM_SIZE')
define(VAR_JUMP, `PARAM_DST')
L(unroll):
C eax
C ebx src
C ecx size
C edx
C esi initial carry
C edi dst
C ebp
movl %ecx, %edx
decl %ecx
subl $2, %edx
negl %ecx
shrl $UNROLL_LOG2, %edx
andl $UNROLL_MASK, %ecx
movl %edx, VAR_COUNTER
movl %ecx, %edx
shll $4, %edx
negl %ecx
C 15 code bytes per limb
ifdef(`PIC',`
call L(pic_calc)
L(here):
',`
leal L(entry) (%edx,%ecx,1), %edx
')
movl (%ebx), %eax C src low limb
movl PARAM_MULTIPLIER, %ebp
movl %edx, VAR_JUMP
mull %ebp
addl %esi, %eax C initial carry (from _1c)
jadcl0( %edx)
leal 4(%ebx,%ecx,4), %ebx
movl %edx, %esi C high carry
movl VAR_JUMP, %edx
leal (%edi,%ecx,4), %edi
testl $1, %ecx
movl %eax, %ecx C low carry
jz L(noswap)
movl %esi, %ecx C high,low carry other way around
movl %eax, %esi
L(noswap):
jmp *%edx
ifdef(`PIC',`
L(pic_calc):
C See mpn/x86/README about old gas bugs
leal (%edx,%ecx,1), %edx
addl $L(entry)-L(here), %edx
addl (%esp), %edx
ret_internal
')
C -----------------------------------------------------------
ALIGN(32)
L(top):
deflit(`FRAME',16)
C eax scratch
C ebx src
C ecx carry lo
C edx scratch
C esi carry hi
C edi dst
C ebp multiplier
C
C 15 code bytes per limb
leal UNROLL_BYTES(%edi), %edi
L(entry):
forloop(`i', 0, UNROLL_COUNT/2-1, `
deflit(`disp0', eval(2*i*4))
deflit(`disp1', eval(disp0 + 4))
Zdisp( movl, disp0,(%ebx), %eax)
mull %ebp
Zdisp( M4_inst,%ecx, disp0,(%edi))
adcl %eax, %esi
movl %edx, %ecx
jadcl0( %ecx)
movl disp1(%ebx), %eax
mull %ebp
M4_inst %esi, disp1(%edi)
adcl %eax, %ecx
movl %edx, %esi
jadcl0( %esi)
')
decl VAR_COUNTER
leal UNROLL_BYTES(%ebx), %ebx
jns L(top)
popl %ebp
M4_inst %ecx, UNROLL_BYTES(%edi)
popl %edi
movl %esi, %eax
popl %ebx
jadcl0( %eax)
popl %esi
ret
EPILOGUE()
| {
"language": "Assembly"
} |
// RUN: %empty-directory(%t)
// RUN: cp %s %t/main.swift
// RUN: %target-build-swift -whole-module-optimization -module-name PlaygroundSupport -emit-module-path %t/PlaygroundSupport.swiftmodule -parse-as-library -c -o %t/PlaygroundSupport.o %S/Inputs/PCMacroRuntime.swift %S/Inputs/SilentPlaygroundsRuntime.swift
// RUN: %target-build-swift -Xfrontend -pc-macro -o %t/main -I=%t %t/PlaygroundSupport.o %t/main.swift
// RUN: %target-codesign %t/main
// RUN: %target-run %t/main | %FileCheck %s
// RUN: %target-build-swift -Xfrontend -pc-macro -Xfrontend -playground -Xfrontend -debugger-support -o %t/main2 -I=%t %t/PlaygroundSupport.o %t/main.swift
// RUN: %target-run %t/main | %FileCheck %s
// REQUIRES: executable_test
// XFAIL: *
// FIXME: rdar://problem/30234450 PCMacro tests fail on linux in optimized mode
// UNSUPPORTED: OS=linux-gnu
import PlaygroundSupport
#sourceLocation(file: "main.swift", line: 8)
var a = false
if (a) {
5
} else if a {
7
}
// CHECK: [8:1-8:14] pc before
// CHECK-NEXT: [8:1-8:14] pc after
// CHECK-NEXT: [9:1-9:7] pc before
// CHECK-NEXT: [9:1-9:7] pc after
// This doesn't work correctly, it highlights only the if.
// It should highlight the else also.
// CHECK-NEXT: [11:3-11:12] pc before
// CHECK-NEXT: [11:3-11:12] pc after
// CHECK-NEXT: [12:3-12:4] pc before
// CHECK-NEXT: [12:3-12:4] pc after
| {
"language": "Assembly"
} |
/*
Linker script for PYBD with STM32F767
Memory layout for mboot configuration (this here describes the app part):
FLASH_APP .isr_vector
FLASH_APP .text
FLASH_APP .big_const
FLASH_APP .data
RAM .data
RAM .bss
RAM .heap
RAM .stack
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 32K /* sector 0, 32K */
FLASH_APP (rx) : ORIGIN = 0x08008000, LENGTH = 2016K /* sectors 1-11 3x32K 1*128K 7*256K */
FLASH_EXT (rx) : ORIGIN = 0x90000000, LENGTH = 2048K /* external QSPI */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 512K /* DTCM=128k, SRAM1=368K, SRAM2=16K */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* Define the stack. The stack is full descending so begins just above last byte
of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */
_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
_sstack = _estack - 24K;
/* RAM extents for the garbage collector */
_ram_start = ORIGIN(RAM);
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_start = _ebss; /* heap starts just after statically allocated memory */
_heap_end = _sstack;
ENTRY(Reset_Handler)
/* Define output sections */
SECTIONS
{
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector))
. = ALIGN(4);
} >FLASH_APP
.text :
{
. = ALIGN(4);
*(.text*)
*(.rodata*)
. = ALIGN(512);
*(.big_const*)
. = ALIGN(4);
_etext = .;
} >FLASH_APP
_sidata = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data*)
. = ALIGN(4);
_edata = .;
} >RAM AT> FLASH_APP
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >RAM
.heap :
{
. = ALIGN(4);
. = . + _minimum_heap_size;
. = ALIGN(4);
} >RAM
.stack :
{
. = ALIGN(4);
. = . + _minimum_stack_size;
. = ALIGN(4);
} >RAM
}
| {
"language": "Assembly"
} |
// Copyright 2012 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// This code was translated into a form compatible with 6a from the public
// domain sources in SUPERCOP: http://bench.cr.yp.to/supercop.html
// +build amd64,!gccgo,!appengine
#include "const_amd64.h"
// func freeze(inout *[5]uint64)
TEXT ·freeze(SB),7,$0-8
MOVQ inout+0(FP), DI
MOVQ 0(DI),SI
MOVQ 8(DI),DX
MOVQ 16(DI),CX
MOVQ 24(DI),R8
MOVQ 32(DI),R9
MOVQ $REDMASK51,AX
MOVQ AX,R10
SUBQ $18,R10
MOVQ $3,R11
REDUCELOOP:
MOVQ SI,R12
SHRQ $51,R12
ANDQ AX,SI
ADDQ R12,DX
MOVQ DX,R12
SHRQ $51,R12
ANDQ AX,DX
ADDQ R12,CX
MOVQ CX,R12
SHRQ $51,R12
ANDQ AX,CX
ADDQ R12,R8
MOVQ R8,R12
SHRQ $51,R12
ANDQ AX,R8
ADDQ R12,R9
MOVQ R9,R12
SHRQ $51,R12
ANDQ AX,R9
IMUL3Q $19,R12,R12
ADDQ R12,SI
SUBQ $1,R11
JA REDUCELOOP
MOVQ $1,R12
CMPQ R10,SI
CMOVQLT R11,R12
CMPQ AX,DX
CMOVQNE R11,R12
CMPQ AX,CX
CMOVQNE R11,R12
CMPQ AX,R8
CMOVQNE R11,R12
CMPQ AX,R9
CMOVQNE R11,R12
NEGQ R12
ANDQ R12,AX
ANDQ R12,R10
SUBQ R10,SI
SUBQ AX,DX
SUBQ AX,CX
SUBQ AX,R8
SUBQ AX,R9
MOVQ SI,0(DI)
MOVQ DX,8(DI)
MOVQ CX,16(DI)
MOVQ R8,24(DI)
MOVQ R9,32(DI)
RET
| {
"language": "Assembly"
} |
// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM64, NetBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
// REQUIRES: x86
// RUN: llvm-mc %s -o %t.o -filetype=obj -triple=x86_64-pc-linux
// RUN: ld.lld --eh-frame-hdr %t.o -o /dev/null -shared
// We would fail to parse multiple cies in the same file.
.cfi_startproc
.cfi_personality 0x9b, foo
.cfi_endproc
.cfi_startproc
.cfi_endproc
foo:
| {
"language": "Assembly"
} |
/* Special .init and .fini section support for MIPS (n64).
Copyright (C) 1995-2020 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
In addition to the permissions in the GNU Lesser General Public
License, the Free Software Foundation gives you unlimited
permission to link the compiled version of this file with other
programs, and to distribute those programs without any restriction
coming from the use of this file. (The GNU Lesser General Public
License restrictions do apply in other respects; for example, they
cover modification of the file, and distribution when not linked
into another program.)
Note that people who make modified versions of this file are not
obligated to grant this special exception for their modified
versions; it is their choice whether to do so. The GNU Lesser
General Public License gives permission to release a modified
version without this exception; this exception also makes it
possible to release a modified version which carries forward this
exception.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
/* crtn.S puts function epilogues in the .init and .fini sections
corresponding to the prologues in crti.S. */
.set nomips16
.section .init,"ax",@progbits
ld $31,8($sp)
ld $28,0($sp)
.set noreorder
.set nomacro
j $31
daddiu $sp,$sp,16
.set macro
.set reorder
.section .fini,"ax",@progbits
ld $31,8($sp)
ld $28,0($sp)
.set noreorder
.set nomacro
j $31
daddiu $sp,$sp,16
.set macro
.set reorder
| {
"language": "Assembly"
} |
/*++
Copyright (c) 2012 Minoca Corp.
This file is licensed under the terms of the GNU General Public License
version 3. Alternative licensing terms are available. Contact
info@minocacorp.com for details. See the LICENSE file at the root of this
project for complete licensing information.
Module Name:
kdsup.S
Abstract:
This module implements kernel debugger support routines on the x86
architecture.
Author:
Evan Green 21-Sep-2012
Environment:
Kernel mode
--*/
//
// ------------------------------------------------------------------ Includes
//
#include <minoca/kernel/x86.inc>
//
// --------------------------------------------------------------- Definitions
//
//
// ---------------------------------------------------------------------- Code
//
//
// .text specifies that this code belongs in the executable section.
//
// .code32 specifies that this is 32-bit protected mode code.
//
.text
.code32
//
// VOID
// KdpBreak (
// VOID
// )
//
/*++
Routine Description:
This routine causes a break into the debugger.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION(KdpBreak)
int $3 # Debugger break.
ret
END_FUNCTION(KdpBreak)
//
// VOID
// KdpInitializeDebugRegisters (
// VOID
// )
//
/*++
Routine Description:
This routine is called during debugger initialization. It resets all
hardware debug registers.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION(KdpInitializeDebugRegisters)
movl $0, %eax #
movl %eax, %dr7 # Turn all hardware breakpoints off.
movl %eax, %dr0 # Set 0 to the address of all debug
movl %eax, %dr1 # registers.
movl %eax, %dr2 #
movl %eax, %dr3 #
movl %eax, %dr6 # Reset the status register.
ret #
END_FUNCTION(KdpInitializeDebugRegisters)
//
// ULONG
// KdpAtomicCompareExchange32 (
// volatile ULONG *Address,
// ULONG ExchangeValue,
// ULONG CompareValue
// )
//
/*++
Routine Description:
This routine atomically compares memory at the given address with a value
and exchanges it with another value if they are equal.
Arguments:
Address - Supplies the address of the value to compare and potentially
exchange.
ExchangeValue - Supplies the value to write to Address if the comparison
returns equality.
CompareValue - Supplies the value to compare against.
Return Value:
Returns the original value at the given address.
--*/
FUNCTION(KdpAtomicCompareExchange32)
movl 12(%esp), %eax # Move CompareValue into eax.
movl 8(%esp), %ecx # Move ExchangeValue into ecx.
movl 4(%esp), %edx # Move Address into edx.
lock cmpxchgl %ecx, (%edx) # Compare Address to eax, exchange with ecx.
ret # Return. Result is already in eax.
END_FUNCTION(KdpAtomicCompareExchange32)
//
// ULONG
// KdpAtomicAdd32 (
// volatile ULONG *Address,
// ULONG Increment
// )
//
/*++
Routine Description:
This routine atomically adds the given amount to a 32-bit variable.
Arguments:
Address - Supplies the address of the value to atomically add to.
Increment - Supplies the amount to add.
Return Value:
Returns the value before the atomic addition was performed.
--*/
FUNCTION(KdpAtomicAdd32)
movl 4(%esp), %edx # Move Address into edx.
movl 8(%esp), %ecx # Move Increment into ecx.
pushl %ebx # Save ebx.
KdpAtomicAdd32Loop:
movl (%edx), %eax # Get value of Address.
movl %ecx, %ebx # Move Increment to ebx.
add %eax, %ebx # Add *Address + Increment, save to ebx.
lock cmpxchgl %ebx, (%edx) # Compare *Address to original, save in ebx.
jne KdpAtomicAdd32Loop # Try again if the value changed.
popl %ebx # Restore ebx and return.
ret # Original *Address is still in eax.
END_FUNCTION(KdpAtomicAdd32)
//
// VOID
// KdpDisableInterrupts (
// VOID
// )
//
/*++
Routine Description:
This routine disables all interrupts on the current processor.
Arguments:
None.
Return Value:
None.
--*/
FUNCTION(KdpDisableInterrupts)
cli # Clear the interrupt flag.
ret
END_FUNCTION(KdpDisableInterrupts)
| {
"language": "Assembly"
} |
// Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
// uint32 runtime·atomicload(uint32 volatile* addr)
TEXT ·atomicload(SB),NOSPLIT,$-8-12
MOVD ptr+0(FP), R0
LDARW (R0), R0
MOVW R0, ret+8(FP)
RET
// uint64 runtime·atomicload64(uint64 volatile* addr)
TEXT ·atomicload64(SB),NOSPLIT,$-8-16
MOVD ptr+0(FP), R0
LDAR (R0), R0
MOVD R0, ret+8(FP)
RET
// void *runtime·atomicloadp(void *volatile *addr)
TEXT ·atomicloadp(SB),NOSPLIT,$-8-16
MOVD ptr+0(FP), R0
LDAR (R0), R0
MOVD R0, ret+8(FP)
RET
TEXT runtime·atomicstorep1(SB), NOSPLIT, $0-16
B runtime·atomicstore64(SB)
TEXT runtime·atomicstore(SB), NOSPLIT, $0-12
MOVD ptr+0(FP), R0
MOVW val+8(FP), R1
STLRW R1, (R0)
RET
TEXT runtime·atomicstore64(SB), NOSPLIT, $0-16
MOVD ptr+0(FP), R0
MOVD val+8(FP), R1
STLR R1, (R0)
RET
TEXT runtime·xchg(SB), NOSPLIT, $0-20
again:
MOVD ptr+0(FP), R0
MOVW new+8(FP), R1
LDAXRW (R0), R2
STLXRW R1, (R0), R3
CBNZ R3, again
MOVW R2, ret+16(FP)
RET
TEXT runtime·xchg64(SB), NOSPLIT, $0-24
again:
MOVD ptr+0(FP), R0
MOVD new+8(FP), R1
LDAXR (R0), R2
STLXR R1, (R0), R3
CBNZ R3, again
MOVD R2, ret+16(FP)
RET
// bool runtime·cas64(uint64 *ptr, uint64 old, uint64 new)
// Atomically:
// if(*val == *old){
// *val = new;
// return 1;
// } else {
// return 0;
// }
TEXT runtime·cas64(SB), NOSPLIT, $0-25
MOVD ptr+0(FP), R0
MOVD old+8(FP), R1
MOVD new+16(FP), R2
again:
LDAXR (R0), R3
CMP R1, R3
BNE ok
STLXR R2, (R0), R3
CBNZ R3, again
ok:
CSET EQ, R0
MOVB R0, ret+24(FP)
RET
// uint32 xadd(uint32 volatile *ptr, int32 delta)
// Atomically:
// *val += delta;
// return *val;
TEXT runtime·xadd(SB), NOSPLIT, $0-20
again:
MOVD ptr+0(FP), R0
MOVW delta+8(FP), R1
LDAXRW (R0), R2
ADDW R2, R1, R2
STLXRW R2, (R0), R3
CBNZ R3, again
MOVW R2, ret+16(FP)
RET
TEXT runtime·xadd64(SB), NOSPLIT, $0-24
again:
MOVD ptr+0(FP), R0
MOVD delta+8(FP), R1
LDAXR (R0), R2
ADD R2, R1, R2
STLXR R2, (R0), R3
CBNZ R3, again
MOVD R2, ret+16(FP)
RET
TEXT runtime·xchguintptr(SB), NOSPLIT, $0-24
B runtime·xchg64(SB)
TEXT ·publicationBarrier(SB),NOSPLIT,$-8-0
DMB $0xe // DMB ST
RET
| {
"language": "Assembly"
} |
; haribote-os boot asm
; TAB=4
[INSTRSET "i486p"]
VBEMODE EQU 0x105 ; 1024 x 768 x 8bit彩色
; （画面模式一览）
; 0x100 : 640 x 400 x 8bit彩色
; 0x101 : 640 x 480 x 8bit彩色
; 0x103 : 800 x 600 x 8bit彩色
; 0x105 : 1024 x 768 x 8bit彩色
; 0x107 : 1280 x 1024 x 8bit彩色
BOTPAK EQU 0x00280000 ; 加载bootpack
DSKCAC EQU 0x00100000 ; 磁盘缓存的位置
DSKCAC0 EQU 0x00008000 ; 磁盘缓存的位置（实模式）
; BOOT_INFO相关
CYLS EQU 0x0ff0 ; 引导扇区设置
LEDS EQU 0x0ff1
VMODE EQU 0x0ff2 ; 关于颜色的信息
SCRNX EQU 0x0ff4 ; 分辨率X
SCRNY EQU 0x0ff6 ; 分辨率Y
VRAM EQU 0x0ff8 ; 图像缓冲区的起始地址
ORG 0xc200 ; 这个的程序要被装载的内存地址
; 确认VBE是否存在
MOV AX,0x9000
MOV ES,AX
MOV DI,0
MOV AX,0x4f00
INT 0x10
CMP AX,0x004f
JNE scrn320
; 检查VBA版本
MOV AX,[ES:DI+4]
CMP AX,0x0200
JB scrn320 ; if (AX < 0x0200) goto scrn320
; 取得画面模式信息
MOV CX,VBEMODE
MOV AX,0x4f01
INT 0x10
CMP AX,0x004f
JNE scrn320
; 画面模式信息的确认
CMP BYTE [ES:DI+0x19],8
JNE scrn320
CMP BYTE [ES:DI+0x1b],4
JNE scrn320
MOV AX,[ES:DI+0x00]
AND AX,0x0080
JZ scrn320 ; 模式属性的bit是0,所以放弃
; 画面模式的切换
MOV BX,VBEMODE+0x4000
MOV AX,0x4f02
INT 0x10
MOV BYTE [VMODE],8 ; 记下画面模式（参考C语言）
MOV AX,[ES:DI+0x12]
MOV [SCRNX],AX
MOV AX,[ES:DI+0x14]
MOV [SCRNY],AX
MOV EAX,[ES:DI+0x28]
MOV [VRAM],EAX
JMP keystatus
scrn320:
MOV AL,0x13 ; VGA图、320×200×8bit彩色
MOV AH,0x00
INT 0x10
MOV BYTE [VMODE],8 ; 记下画面模式（参考C语言）
MOV WORD [SCRNX],320
MOV WORD [SCRNY],200
MOV DWORD [VRAM],0x000a0000
; 通过BIOS获取指示灯状态
keystatus:
MOV AH,0x02
INT 0x16 ; keyboard BIOS
MOV [LEDS],AL
; PIC关闭一切中断
; 根据AT兼容机的规格，如果要初始化PIC,
; 必须在CLI之前进行，否则有时会挂起。
; 随后进行PIC的初始化
MOV AL,0xff
OUT 0x21,AL
NOP ; 如果连续执行OUT指令, 有些机种无法发正常运行（CPU休息一个时钟）
OUT 0xa1,AL
CLI ; 禁止CPU级别的中断
; 让CPU支持1M以上内存、设置A20GATE
CALL waitkbdout
MOV AL,0xd1
OUT 0x64,AL
CALL waitkbdout
MOV AL,0xdf ; enable A20
OUT 0x60,AL
CALL waitkbdout
; 保护模式转换
[INSTRSET "i486p"] ; 说明使用486指令
LGDT [GDTR0] ; 设置临时GDT
MOV EAX,CR0
AND EAX,0x7fffffff ; 使用bit31（为了禁止分页）
OR EAX,0x00000001 ; bit0到1转换（保护模式过渡）
MOV CR0,EAX
JMP pipelineflush
pipelineflush:
MOV AX,1*8 ; 写读写的段 32bit
MOV DS,AX
MOV ES,AX
MOV FS,AX
MOV GS,AX
MOV SS,AX
; bootpack传递
MOV ESI,bootpack ; 转送源
MOV EDI,BOTPAK ; 转送的目标
MOV ECX,512*1024/4
CALL memcpy
; 磁盘数据最终转送到它本来的位置去
; 首先从引导区开始
MOV ESI,0x7c00 ; 转送源
MOV EDI,DSKCAC ; 转送的目标
MOV ECX,512/4
CALL memcpy
; 剩余的全部
MOV ESI,DSKCAC0+512 ; 转送源
MOV EDI,DSKCAC+512 ; 转送的目标
MOV ECX,0
MOV CL,BYTE [CYLS]
IMUL ECX,512*18*2/4 ; 从柱面数变换为字节数/4(转送数据大小是以双字为单位)
SUB ECX,512/4 ; 减去IPL
CALL memcpy
; 必须由asmhead来完成的工作，至此全部完毕
; 以后就交由bootpack来完成
; bootpack启动
MOV EBX,BOTPAK
MOV ECX,[EBX+16]
ADD ECX,3 ; ECX += 3;
SHR ECX,2 ; ECX /= 4;
JZ skip ; 传输完成（没有要转送的东西时）
MOV ESI,[EBX+20] ; 转送源
ADD ESI,EBX
MOV EDI,[EBX+12] ; 转送目的地
CALL memcpy
skip:
MOV ESP,[EBX+12] ; 栈的初始化
JMP DWORD 2*8:0x0000001b
waitkbdout:
IN AL,0x64
AND AL,0x02
JNZ waitkbdout ; AND结果不为0就跳转到waitkbdout
RET
memcpy:
MOV EAX,[ESI]
ADD ESI,4
MOV [EDI],EAX
ADD EDI,4
SUB ECX,1
JNZ memcpy ; 运算结果不为0就跳转到memcpy
RET
; memcpy地址前缀大小
ALIGNB 16
GDT0:
RESB 8 ; NULL selector
DW 0xffff,0x0000,0x9200,0x00cf ; 可以读写的段（segment）32bit
DW 0xffff,0x0000,0x9a28,0x0047 ; 可以执行的段（segment）32bit(bootpack用)
DW 0
GDTR0:
DW 8*3-1
DD GDT0
ALIGNB 16
bootpack:
| {
"language": "Assembly"
} |
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
foo:
sbis 4, 3
sbis 6, 2
sbis 16, 5
sbis 0, 0
sbis FOO+4, 7
; CHECK: sbis 4, 3 ; encoding: [0x23,0x9b]
; CHECK: sbis 6, 2 ; encoding: [0x32,0x9b]
; CHECK: sbis 16, 5 ; encoding: [0x85,0x9b]
; CHECK: sbis 0, 0 ; encoding: [0x00,0x9b]
; CHECK: sbis FOO+4, 7 ; encoding: [0bAAAAA111,0x9b]
; CHECK: ; fixup A - offset: 0, value: FOO+4, kind: fixup_port5
| {
"language": "Assembly"
} |
; Option definitions for TI C6X.
; Copyright (C) 2010-2019 Free Software Foundation, Inc.
; Contributed by Bernd Schmidt <bernds@codesourcery.com>
; Contributed by CodeSourcery.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3, or (at your option)
; any later version.
;
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
HeaderInclude
config/c6x/c6x-opts.h
SourceInclude
config/c6x/c6x-opts.h
mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN)
Use big-endian byte order.
mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
Use little-endian byte order.
msim
Target RejectNegative
Use simulator runtime.
msdata=
Target RejectNegative Enum(c6x_sdata) Joined Var(c6x_sdata_mode) Init(C6X_SDATA_DEFAULT)
Select method for sdata handling.
Enum
Name(c6x_sdata) Type(enum c6x_sdata)
Valid arguments for the -msdata= option:
EnumValue
Enum(c6x_sdata) String(none) Value(C6X_SDATA_NONE)
EnumValue
Enum(c6x_sdata) String(default) Value(C6X_SDATA_DEFAULT)
EnumValue
Enum(c6x_sdata) String(all) Value(C6X_SDATA_ALL)
mdsbt
Target Mask(DSBT)
Compile for the DSBT shared library ABI.
mlong-calls
Target Report Mask(LONG_CALLS)
Avoid generating pc-relative calls; use indirection.
march=
Target RejectNegative Joined Enum(c6x_isa) Var(c6x_arch_option)
Specify the name of the target architecture.
| {
"language": "Assembly"
} |
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* DWtype __avr32_lsr64(DWtype u, word_type b)
*/
.text
.global __avr32_lsr64
.type __avr32_lsr64,@function
__avr32_lsr64:
cp.w r12, 0
reteq r12
rsub r9, r12, 32
brle 1f
lsl r8, r11, r9
lsr r11, r11, r12
lsr r10, r10, r12
or r10, r8
retal r12
1: neg r9
lsr r10, r11, r9
mov r11, 0
retal r12
| {
"language": "Assembly"
} |
;
; Copyright (c) 2016, Alliance for Open Media. All rights reserved
;
; This source code is subject to the terms of the BSD 2 Clause License and
; the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
; was not distributed with this source code in the LICENSE file, you can
; obtain it at www.aomedia.org/license/software. If the Alliance for Open
; Media Patent License 1.0 was not distributed with this source code in the
; PATENTS file, you can obtain it at www.aomedia.org/license/patent.
;
;
%include "aom_ports/x86_abi_support.asm"
section .text
global sym(aom_reset_mmx_state) PRIVATE
sym(aom_reset_mmx_state):
emms
ret
%if LIBAOM_YASM_WIN64
global sym(aom_winx64_fldcw) PRIVATE
sym(aom_winx64_fldcw):
sub rsp, 8
mov [rsp], rcx ; win x64 specific
fldcw [rsp]
add rsp, 8
ret
global sym(aom_winx64_fstcw) PRIVATE
sym(aom_winx64_fstcw):
sub rsp, 8
fstcw [rsp]
mov rax, [rsp]
add rsp, 8
ret
%endif
| {
"language": "Assembly"
} |
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2013-2017
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
SECTIONS
{
. = 0;
.boot : {
*(.boot.entry)
*(.boot)
}
. = 0x1000;
.cmdline : {
*(.cmdline)
BYTE(0); /* empty string in case no buffer is provided */
}
.text : {
*(.text)
}
. = ALIGN(16);
.rodata : {
*(.rodata)
}
. = ALIGN(16);
.data : {
*(.data)
}
.bss : {
bss_start = .;
*(.bss)
. = ALIGN(8);
}
bss_dwords = SIZEOF(.bss) / 4;
bss_qwords = SIZEOF(.bss) / 8;
. = ALIGN(4096);
. += 0x1000;
stack_top = .;
/DISCARD/ : {
*(.eh_frame*)
}
}
ENTRY(__reset_entry)
| {
"language": "Assembly"
} |
dnl Copyright (c) 1995, 1996, 1997, 1998
dnl The Regents of the University of California. All rights reserved.
dnl
dnl Redistribution and use in source and binary forms, with or without
dnl modification, are permitted provided that: (1) source code distributions
dnl retain the above copyright notice and this paragraph in its entirety, (2)
dnl distributions including binary code include the above copyright notice and
dnl this paragraph in its entirety in the documentation or other materials
dnl provided with the distribution, and (3) all advertising materials mentioning
dnl features or use of this software display the following acknowledgement:
dnl ``This product includes software developed by the University of California,
dnl Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
dnl the University nor the names of its contributors may be used to endorse
dnl or promote products derived from this software without specific prior
dnl written permission.
dnl THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
dnl WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
dnl MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
dnl
dnl LBL autoconf macros
dnl
dnl
dnl Do whatever AC_LBL_C_INIT work is necessary before using AC_PROG_CC.
dnl
dnl It appears that newer versions of autoconf (2.64 and later) will,
dnl if you use AC_TRY_COMPILE in a macro, stick AC_PROG_CC at the
dnl beginning of the macro, even if the macro itself calls AC_PROG_CC.
dnl See the "Prerequisite Macros" and "Expanded Before Required" sections
dnl in the Autoconf documentation.
dnl
dnl This causes a steaming heap of fail in our case, as we were, in
dnl AC_LBL_C_INIT, doing the tests we now do in AC_LBL_C_INIT_BEFORE_CC,
dnl calling AC_PROG_CC, and then doing the tests we now do in
dnl AC_LBL_C_INIT. Now, we run AC_LBL_C_INIT_BEFORE_CC, AC_PROG_CC,
dnl and AC_LBL_C_INIT at the top level.
dnl
AC_DEFUN(AC_LBL_C_INIT_BEFORE_CC,
[
AC_BEFORE([$0], [AC_LBL_C_INIT])
AC_BEFORE([$0], [AC_PROG_CC])
AC_BEFORE([$0], [AC_LBL_FIXINCLUDES])
AC_BEFORE([$0], [AC_LBL_DEVEL])
AC_ARG_WITH(gcc, [ --without-gcc don't use gcc])
$1=""
if test "${srcdir}" != "." ; then
$1="-I\$(srcdir)"
fi
if test "${CFLAGS+set}" = set; then
LBL_CFLAGS="$CFLAGS"
fi
if test -z "$CC" ; then
case "$host_os" in
bsdi*)
AC_CHECK_PROG(SHLICC2, shlicc2, yes, no)
if test $SHLICC2 = yes ; then
CC=shlicc2
export CC
fi
;;
esac
fi
if test -z "$CC" -a "$with_gcc" = no ; then
CC=cc
export CC
fi
])
dnl
dnl Determine which compiler we're using (cc or gcc)
dnl If using gcc, determine the version number
dnl If using cc:
dnl require that it support ansi prototypes
dnl use -O (AC_PROG_CC will use -g -O2 on gcc, so we don't need to
dnl do that ourselves for gcc)
dnl add -g flags, as appropriate
dnl explicitly specify /usr/local/include
dnl
dnl NOTE WELL: with newer versions of autoconf, "gcc" means any compiler
dnl that defines __GNUC__, which means clang, for example, counts as "gcc".
dnl
dnl usage:
dnl
dnl AC_LBL_C_INIT(copt, incls)
dnl
dnl results:
dnl
dnl $1 (copt set)
dnl $2 (incls set)
dnl CC
dnl LDFLAGS
dnl LBL_CFLAGS
dnl
AC_DEFUN(AC_LBL_C_INIT,
[
AC_BEFORE([$0], [AC_LBL_FIXINCLUDES])
AC_BEFORE([$0], [AC_LBL_DEVEL])
AC_BEFORE([$0], [AC_LBL_SHLIBS_INIT])
if test "$GCC" = yes ; then
#
# -Werror forces warnings to be errors.
#
ac_lbl_cc_force_warning_errors=-Werror
#
# Try to have the compiler default to hiding symbols,
# so that only symbols explicitly exported with
# PCAP_API will be visible outside (shared) libraries.
#
AC_LBL_CHECK_COMPILER_OPT($1, -fvisibility=hidden)
else
$2="$$2 -I/usr/local/include"
LDFLAGS="$LDFLAGS -L/usr/local/lib"
case "$host_os" in
darwin*)
#
# This is assumed either to be GCC or clang, both
# of which use -Werror to force warnings to be errors.
#
ac_lbl_cc_force_warning_errors=-Werror
#
# Try to have the compiler default to hiding symbols,
# so that only symbols explicitly exported with
# PCAP_API will be visible outside (shared) libraries.
#
AC_LBL_CHECK_COMPILER_OPT($1, -fvisibility=hidden)
;;
hpux*)
#
# HP C, which is what we presume we're using, doesn't
# exit with a non-zero exit status if we hand it an
# invalid -W flag, can't be forced to do so even with
# +We, and doesn't handle GCC-style -W flags, so we
# don't want to try using GCC-style -W flags.
#
ac_lbl_cc_dont_try_gcc_dashW=yes
;;
irix*)
#
# MIPS C, which is what we presume we're using, doesn't
# necessarily exit with a non-zero exit status if we
# hand it an invalid -W flag, can't be forced to do
# so, and doesn't handle GCC-style -W flags, so we
# don't want to try using GCC-style -W flags.
#
ac_lbl_cc_dont_try_gcc_dashW=yes
#
# It also, apparently, defaults to "char" being
# unsigned, unlike most other C implementations;
# I suppose we could say "signed char" whenever
# we want to guarantee a signed "char", but let's
# just force signed chars.
#
# -xansi is normally the default, but the
# configure script was setting it; perhaps -cckr
# was the default in the Old Days. (Then again,
# that would probably be for backwards compatibility
# in the days when ANSI C was Shiny and New, i.e.
# 1989 and the early '90's, so maybe we can just
# drop support for those compilers.)
#
# -g is equivalent to -g2, which turns off
# optimization; we choose -g3, which generates
# debugging information but doesn't turn off
# optimization (even if the optimization would
# cause inaccuracies in debugging).
#
$1="$$1 -xansi -signed -g3"
;;
osf*)
#
# Presumed to be DEC OSF/1, Digital UNIX, or
# Tru64 UNIX.
#
# The DEC C compiler, which is what we presume we're
# using, doesn't exit with a non-zero exit status if we
# hand it an invalid -W flag, can't be forced to do
# so, and doesn't handle GCC-style -W flags, so we
# don't want to try using GCC-style -W flags.
#
ac_lbl_cc_dont_try_gcc_dashW=yes
#
# -g is equivalent to -g2, which turns off
# optimization; we choose -g3, which generates
# debugging information but doesn't turn off
# optimization (even if the optimization would
# cause inaccuracies in debugging).
#
$1="$$1 -g3"
;;
solaris*)
#
# Assumed to be Sun C, which requires -errwarn to force
# warnings to be treated as errors.
#
ac_lbl_cc_force_warning_errors=-errwarn
#
# Try to have the compiler default to hiding symbols,
# so that only symbols explicitly exported with
# PCAP_API will be visible outside (shared) libraries.
#
AC_LBL_CHECK_COMPILER_OPT($1, -xldscope=hidden)
;;
ultrix*)
AC_MSG_CHECKING(that Ultrix $CC hacks const in prototypes)
AC_CACHE_VAL(ac_cv_lbl_cc_const_proto,
AC_TRY_COMPILE(
[#include <sys/types.h>],
[struct a { int b; };
void c(const struct a *)],
ac_cv_lbl_cc_const_proto=yes,
ac_cv_lbl_cc_const_proto=no))
AC_MSG_RESULT($ac_cv_lbl_cc_const_proto)
if test $ac_cv_lbl_cc_const_proto = no ; then
AC_DEFINE(const,[],
[to handle Ultrix compilers that don't support const in prototypes])
fi
;;
esac
$1="$$1 -O"
fi
])
dnl
dnl Check whether, if you pass an unknown warning option to the
dnl compiler, it fails or just prints a warning message and succeeds.
dnl Set ac_lbl_unknown_warning_option_error to the appropriate flag
dnl to force an error if it would otherwise just print a warning message
dnl and succeed.
dnl
AC_DEFUN(AC_LBL_CHECK_UNKNOWN_WARNING_OPTION_ERROR,
[
AC_MSG_CHECKING([whether the compiler fails when given an unknown warning option])
save_CFLAGS="$CFLAGS"
CFLAGS="$CFLAGS -Wxyzzy-this-will-never-succeed-xyzzy"
AC_TRY_COMPILE(
[],
[return 0],
[
AC_MSG_RESULT([no])
#
# We're assuming this is clang, where
# -Werror=unknown-warning-option is the appropriate
# option to force the compiler to fail.
#
ac_lbl_unknown_warning_option_error="-Werror=unknown-warning-option"
],
[
AC_MSG_RESULT([yes])
])
CFLAGS="$save_CFLAGS"
])
dnl
dnl Check whether the compiler option specified as the second argument
dnl is supported by the compiler and, if so, add it to the macro
dnl specified as the first argument
dnl
dnl If a third argument is supplied, treat it as C code to be compiled
dnl with the flag in question, and the "treat warnings as errors" flag
dnl set, and don't add the flag to the first argument if the compile
dnl fails; this is for warning options cause problems that can't be
dnl worked around. If a third argument is supplied, a fourth argument
dnl should also be supplied; it's a message desribing what the test
dnl program is checking.
dnl
AC_DEFUN(AC_LBL_CHECK_COMPILER_OPT,
[
AC_MSG_CHECKING([whether the compiler supports the $2 option])
save_CFLAGS="$CFLAGS"
if expr "x$2" : "x-W.*" >/dev/null
then
CFLAGS="$CFLAGS $ac_lbl_unknown_warning_option_error $2"
elif expr "x$2" : "x-f.*" >/dev/null
then
CFLAGS="$CFLAGS -Werror $2"
elif expr "x$2" : "x-m.*" >/dev/null
then
CFLAGS="$CFLAGS -Werror $2"
else
CFLAGS="$CFLAGS $2"
fi
AC_TRY_COMPILE(
[],
[return 0],
[
AC_MSG_RESULT([yes])
can_add_to_cflags=yes
#
# The compile supports this; do we have some C code for
# which the warning should *not* appear?
# We test the fourth argument because the third argument
# could contain quotes, breaking the test.
#
if test "x$4" != "x"
then
CFLAGS="$CFLAGS $ac_lbl_cc_force_warning_errors"
AC_MSG_CHECKING(whether $2 $4)
AC_COMPILE_IFELSE(
[AC_LANG_SOURCE($3)],
[
#
# Not a problem.
#
AC_MSG_RESULT(no)
],
[
#
# A problem.
#
AC_MSG_RESULT(yes)
can_add_to_cflags=no
])
fi
CFLAGS="$save_CFLAGS"
if test x"$can_add_to_cflags" = "xyes"
then
$1="$$1 $2"
fi
],
[
AC_MSG_RESULT([no])
CFLAGS="$save_CFLAGS"
])
])
dnl
dnl Check whether the compiler supports an option to generate
dnl Makefile-style dependency lines
dnl
dnl GCC uses -M for this. Non-GCC compilers that support this
dnl use a variety of flags, including but not limited to -M.
dnl
dnl We test whether the flag in question is supported, as older
dnl versions of compilers might not support it.
dnl
dnl We don't try all the possible flags, just in case some flag means
dnl "generate dependencies" on one compiler but means something else
dnl on another compiler.
dnl
dnl Most compilers that support this send the output to the standard
dnl output by default. IBM's XLC, however, supports -M but sends
dnl the output to {sourcefile-basename}.u, and AIX has no /dev/stdout
dnl to work around that, so we don't bother with XLC.
dnl
AC_DEFUN(AC_LBL_CHECK_DEPENDENCY_GENERATION_OPT,
[
AC_MSG_CHECKING([whether the compiler supports generating dependencies])
if test "$GCC" = yes ; then
#
# GCC, or a compiler deemed to be GCC by AC_PROG_CC (even
# though it's not); we assume that, in this case, the flag
# would be -M.
#
ac_lbl_dependency_flag="-M"
else
#
# Not GCC or a compiler deemed to be GCC; what platform is
# this? (We're assuming that if the compiler isn't GCC
# it's the compiler from the vendor of the OS; that won't
# necessarily be true for x86 platforms, where it might be
# the Intel C compiler.)
#
case "$host_os" in
irix*|osf*|darwin*)
#
# MIPS C for IRIX, DEC C, and clang all use -M.
#
ac_lbl_dependency_flag="-M"
;;
solaris*)
#
# Sun C uses -xM.
#
ac_lbl_dependency_flag="-xM"
;;
hpux*)
#
# HP's older C compilers don't support this.
# HP's newer C compilers support this with
# either +M or +Make; the older compilers
# interpret +M as something completely
# different, so we use +Make so we don't
# think it works with the older compilers.
#
ac_lbl_dependency_flag="+Make"
;;
*)
#
# Not one of the above; assume no support for
# generating dependencies.
#
ac_lbl_dependency_flag=""
;;
esac
fi
#
# Is ac_lbl_dependency_flag defined and, if so, does the compiler
# complain about it?
#
# Note: clang doesn't seem to exit with an error status when handed
# an unknown non-warning error, even if you pass it
# -Werror=unknown-warning-option. However, it always supports
# -M, so the fact that this test always succeeds with clang
# isn't an issue.
#
if test ! -z "$ac_lbl_dependency_flag"; then
AC_LANG_CONFTEST(
[AC_LANG_SOURCE([[int main(void) { return 0; }]])])
if AC_RUN_LOG([eval "$CC $ac_lbl_dependency_flag conftest.c >/dev/null 2>&1"]); then
AC_MSG_RESULT([yes, with $ac_lbl_dependency_flag])
DEPENDENCY_CFLAG="$ac_lbl_dependency_flag"
MKDEP='${srcdir}/mkdep'
else
AC_MSG_RESULT([no])
#
# We can't run mkdep, so have "make depend" do
# nothing.
#
MKDEP='${srcdir}/nomkdep'
fi
rm -rf conftest*
else
AC_MSG_RESULT([no])
#
# We can't run mkdep, so have "make depend" do
# nothing.
#
MKDEP='${srcdir}/nomkdep'
fi
AC_SUBST(DEPENDENCY_CFLAG)
AC_SUBST(MKDEP)
])
dnl
dnl Determine what options are needed to build a shared library
dnl
dnl usage:
dnl
dnl AC_LBL_SHLIBS_INIT
dnl
dnl results:
dnl
dnl V_SHLIB_CCOPT (modified to build position-independent code)
dnl V_SHLIB_CMD
dnl V_SHLIB_OPT
dnl V_SONAME_OPT
dnl V_RPATH_OPT
dnl
AC_DEFUN(AC_LBL_SHLIBS_INIT,
[AC_PREREQ(2.50)
if test "$GCC" = yes ; then
#
# On platforms where we build a shared library:
#
# add options to generate position-independent code,
# if necessary (it's the default in AIX and Darwin/macOS);
#
# define option to set the soname of the shared library,
# if the OS supports that;
#
# add options to specify, at link time, a directory to
# add to the run-time search path, if that's necessary.
#
V_SHLIB_CMD="\$(CC)"
V_SHLIB_OPT="-shared"
case "$host_os" in
aix*)
;;
freebsd*|netbsd*|openbsd*|dragonfly*|linux*|osf*|midipix*)
#
# Platforms where the linker is the GNU linker
# or accepts command-line arguments like
# those the GNU linker accepts.
#
# Some instruction sets require -fPIC on some
# operating systems. Check for them. If you
# have a combination that requires it, add it
# here.
#
PIC_OPT=-fpic
case "$host_cpu" in
sparc64*)
case "$host_os" in
freebsd*|openbsd*|linux*)
PIC_OPT=-fPIC
;;
esac
;;
esac
V_SHLIB_CCOPT="$V_SHLIB_CCOPT $PIC_OPT"
V_SONAME_OPT="-Wl,-soname,"
V_RPATH_OPT="-Wl,-rpath,"
;;
hpux*)
V_SHLIB_CCOPT="$V_SHLIB_CCOPT -fpic"
#
# XXX - this assumes GCC is using the HP linker,
# rather than the GNU linker, and that the "+h"
# option is used on all HP-UX platforms, both .sl
# and .so.
#
V_SONAME_OPT="-Wl,+h,"
#
# By default, directories specifed with -L
# are added to the run-time search path, so
# we don't add them in pcap-config.
#
;;
solaris*)
V_SHLIB_CCOPT="$V_SHLIB_CCOPT -fpic"
#
# XXX - this assumes GCC is using the Sun linker,
# rather than the GNU linker.
#
V_SONAME_OPT="-Wl,-h,"
V_RPATH_OPT="-Wl,-R,"
;;
esac
else
#
# Set the appropriate compiler flags and, on platforms
# where we build a shared library:
#
# add options to generate position-independent code,
# if necessary (it's the default in Darwin/macOS);
#
# if we generate ".so" shared libraries, define the
# appropriate options for building the shared library;
#
# add options to specify, at link time, a directory to
# add to the run-time search path, if that's necessary.
#
# Note: spaces after V_SONAME_OPT are significant; on
# some platforms the soname is passed with a GCC-like
# "-Wl,-soname,{soname}" option, with the soname part
# of the option, while on other platforms the C compiler
# driver takes it as a regular option with the soname
# following the option. The same applies to V_RPATH_OPT.
#
case "$host_os" in
aix*)
V_SHLIB_CMD="\$(CC)"
V_SHLIB_OPT="-G -bnoentry -bexpall"
;;
freebsd*|netbsd*|openbsd*|dragonfly*|linux*)
#
# "cc" is GCC.
#
V_SHLIB_CCOPT="$V_SHLIB_CCOPT -fpic"
V_SHLIB_CMD="\$(CC)"
V_SHLIB_OPT="-shared"
V_SONAME_OPT="-Wl,-soname,"
V_RPATH_OPT="-Wl,-rpath,"
;;
hpux*)
V_SHLIB_CCOPT="$V_SHLIB_CCOPT +z"
V_SHLIB_CMD="\$(LD)"
V_SHLIB_OPT="-b"
V_SONAME_OPT="+h "
#
# By default, directories specifed with -L
# are added to the run-time search path, so
# we don't add them in pcap-config.
#
;;
osf*)
#
# Presumed to be DEC OSF/1, Digital UNIX, or
# Tru64 UNIX.
#
V_SHLIB_CMD="\$(CC)"
V_SHLIB_OPT="-shared"
V_SONAME_OPT="-soname "
V_RPATH_OPT="-rpath "
;;
solaris*)
V_SHLIB_CCOPT="$V_SHLIB_CCOPT -Kpic"
V_SHLIB_CMD="\$(CC)"
V_SHLIB_OPT="-G"
V_SONAME_OPT="-h "
V_RPATH_OPT="-R"
;;
esac
fi
])
#
# Try compiling a sample of the type of code that appears in
# gencode.c with "inline", "__inline__", and "__inline".
#
# Autoconf's AC_C_INLINE, at least in autoconf 2.13, isn't good enough,
# as it just tests whether a function returning "int" can be inlined;
# at least some versions of HP's C compiler can inline that, but can't
# inline a function that returns a struct pointer.
#
# Make sure we use the V_CCOPT flags, because some of those might
# disable inlining.
#
AC_DEFUN(AC_LBL_C_INLINE,
[AC_MSG_CHECKING(for inline)
save_CFLAGS="$CFLAGS"
CFLAGS="$V_CCOPT"
AC_CACHE_VAL(ac_cv_lbl_inline, [
ac_cv_lbl_inline=""
ac_lbl_cc_inline=no
for ac_lbl_inline in inline __inline__ __inline
do
AC_TRY_COMPILE(
[#define inline $ac_lbl_inline
static inline struct iltest *foo(void);
struct iltest {
int iltest1;
int iltest2;
};
static inline struct iltest *
foo()
{
static struct iltest xxx;
return &xxx;
}],,ac_lbl_cc_inline=yes,)
if test "$ac_lbl_cc_inline" = yes ; then
break;
fi
done
if test "$ac_lbl_cc_inline" = yes ; then
ac_cv_lbl_inline=$ac_lbl_inline
fi])
CFLAGS="$save_CFLAGS"
if test ! -z "$ac_cv_lbl_inline" ; then
AC_MSG_RESULT($ac_cv_lbl_inline)
else
AC_MSG_RESULT(no)
fi
AC_DEFINE_UNQUOTED(inline, $ac_cv_lbl_inline, [Define as token for inline if inlining supported])])
dnl
dnl If using gcc, make sure we have ANSI ioctl definitions
dnl
dnl usage:
dnl
dnl AC_LBL_FIXINCLUDES
dnl
AC_DEFUN(AC_LBL_FIXINCLUDES,
[if test "$GCC" = yes ; then
AC_MSG_CHECKING(for ANSI ioctl definitions)
AC_CACHE_VAL(ac_cv_lbl_gcc_fixincludes,
AC_TRY_COMPILE(
[/*
* This generates a "duplicate case value" when fixincludes
* has not be run.
*/
# include <sys/types.h>
# include <sys/time.h>
# include <sys/ioctl.h>
# ifdef HAVE_SYS_IOCCOM_H
# include <sys/ioccom.h>
# endif],
[switch (0) {
case _IO('A', 1):;
case _IO('B', 1):;
}],
ac_cv_lbl_gcc_fixincludes=yes,
ac_cv_lbl_gcc_fixincludes=no))
AC_MSG_RESULT($ac_cv_lbl_gcc_fixincludes)
if test $ac_cv_lbl_gcc_fixincludes = no ; then
# Don't cache failure
unset ac_cv_lbl_gcc_fixincludes
AC_MSG_ERROR(see the INSTALL for more info)
fi
fi])
dnl
dnl Checks to see if union wait is used with WEXITSTATUS()
dnl
dnl usage:
dnl
dnl AC_LBL_UNION_WAIT
dnl
dnl results:
dnl
dnl DECLWAITSTATUS (defined)
dnl
AC_DEFUN(AC_LBL_UNION_WAIT,
[AC_MSG_CHECKING(if union wait is used)
AC_CACHE_VAL(ac_cv_lbl_union_wait,
AC_TRY_COMPILE([
# include <sys/types.h>
# include <sys/wait.h>],
[int status;
u_int i = WEXITSTATUS(status);
u_int j = waitpid(0, &status, 0);],
ac_cv_lbl_union_wait=no,
ac_cv_lbl_union_wait=yes))
AC_MSG_RESULT($ac_cv_lbl_union_wait)
if test $ac_cv_lbl_union_wait = yes ; then
AC_DEFINE(DECLWAITSTATUS,union wait,[type for wait])
else
AC_DEFINE(DECLWAITSTATUS,int,[type for wait])
fi])
dnl
dnl Checks to see if -R is used
dnl
dnl usage:
dnl
dnl AC_LBL_HAVE_RUN_PATH
dnl
dnl results:
dnl
dnl ac_cv_lbl_have_run_path (yes or no)
dnl
AC_DEFUN(AC_LBL_HAVE_RUN_PATH,
[AC_MSG_CHECKING(for ${CC-cc} -R)
AC_CACHE_VAL(ac_cv_lbl_have_run_path,
[echo 'main(){}' > conftest.c
${CC-cc} -o conftest conftest.c -R/a1/b2/c3 >conftest.out 2>&1
if test ! -s conftest.out ; then
ac_cv_lbl_have_run_path=yes
else
ac_cv_lbl_have_run_path=no
fi
rm -f -r conftest*])
AC_MSG_RESULT($ac_cv_lbl_have_run_path)
])
dnl
dnl Checks to see if unaligned memory accesses fail
dnl
dnl usage:
dnl
dnl AC_LBL_UNALIGNED_ACCESS
dnl
dnl results:
dnl
dnl LBL_ALIGN (DEFINED)
dnl
AC_DEFUN(AC_LBL_UNALIGNED_ACCESS,
[AC_MSG_CHECKING(if unaligned accesses fail)
AC_CACHE_VAL(ac_cv_lbl_unaligned_fail,
[case "$host_cpu" in
#
# These are CPU types where:
#
# the CPU faults on an unaligned access, but at least some
# OSes that support that CPU catch the fault and simulate
# the unaligned access (e.g., Alpha/{Digital,Tru64} UNIX) -
# the simulation is slow, so we don't want to use it;
#
# the CPU, I infer (from the old
#
# XXX: should also check that they don't do weird things (like on arm)
#
# comment) doesn't fault on unaligned accesses, but doesn't
# do a normal unaligned fetch, either (e.g., presumably, ARM);
#
# for whatever reason, the test program doesn't work
# (this has been claimed to be the case for several of those
# CPUs - I don't know what the problem is; the problem
# was reported as "the test program dumps core" for SuperH,
# but that's what the test program is *supposed* to do -
# it dumps core before it writes anything, so the test
# for an empty output file should find an empty output
# file and conclude that unaligned accesses don't work).
#
# This run-time test won't work if you're cross-compiling, so
# in order to support cross-compiling for a particular CPU,
# we have to wire in the list of CPU types anyway, as far as
# I know, so perhaps we should just have a set of CPUs on
# which we know it doesn't work, a set of CPUs on which we
# know it does work, and have the script just fail on other
# cpu types and update it when such a failure occurs.
#
alpha*|arm*|bfin*|hp*|mips*|sh*|sparc*|ia64|nv1)
ac_cv_lbl_unaligned_fail=yes
;;
*)
cat >conftest.c <<EOF
# include <sys/types.h>
# include <sys/wait.h>
# include <stdio.h>
unsigned char a[[5]] = { 1, 2, 3, 4, 5 };
main() {
unsigned int i;
pid_t pid;
int status;
/* avoid "core dumped" message */
pid = fork();
if (pid < 0)
exit(2);
if (pid > 0) {
/* parent */
pid = waitpid(pid, &status, 0);
if (pid < 0)
exit(3);
exit(!WIFEXITED(status));
}
/* child */
i = *(unsigned int *)&a[[1]];
printf("%d\n", i);
exit(0);
}
EOF
${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS \
conftest.c $LIBS >/dev/null 2>&1
if test ! -x conftest ; then
dnl failed to compile for some reason
ac_cv_lbl_unaligned_fail=yes
else
./conftest >conftest.out
if test ! -s conftest.out ; then
ac_cv_lbl_unaligned_fail=yes
else
ac_cv_lbl_unaligned_fail=no
fi
fi
rm -f -r conftest* core core.conftest
;;
esac])
AC_MSG_RESULT($ac_cv_lbl_unaligned_fail)
if test $ac_cv_lbl_unaligned_fail = yes ; then
AC_DEFINE(LBL_ALIGN,1,[if unaligned access fails])
fi])
dnl
dnl If the file .devel exists:
dnl Add some warning flags if the compiler supports them
dnl If an os prototype include exists, symlink os-proto.h to it
dnl
dnl usage:
dnl
dnl AC_LBL_DEVEL(copt)
dnl
dnl results:
dnl
dnl $1 (copt appended)
dnl HAVE_OS_PROTO_H (defined)
dnl os-proto.h (symlinked)
dnl
AC_DEFUN(AC_LBL_DEVEL,
[rm -f os-proto.h
if test "${LBL_CFLAGS+set}" = set; then
$1="$$1 ${LBL_CFLAGS}"
fi
if test -f .devel ; then
#
# Skip all the warning option stuff on some compilers.
#
if test "$ac_lbl_cc_dont_try_gcc_dashW" != yes; then
AC_LBL_CHECK_UNKNOWN_WARNING_OPTION_ERROR()
AC_LBL_CHECK_COMPILER_OPT($1, -W)
AC_LBL_CHECK_COMPILER_OPT($1, -Wall)
AC_LBL_CHECK_COMPILER_OPT($1, -Wcomma)
AC_LBL_CHECK_COMPILER_OPT($1, -Wdeclaration-after-statement)
AC_LBL_CHECK_COMPILER_OPT($1, -Wdocumentation)
AC_LBL_CHECK_COMPILER_OPT($1, -Wformat-nonliteral)
AC_LBL_CHECK_COMPILER_OPT($1, -Wmissing-noreturn)
AC_LBL_CHECK_COMPILER_OPT($1, -Wmissing-prototypes)
AC_LBL_CHECK_COMPILER_OPT($1, -Wmissing-variable-declarations)
AC_LBL_CHECK_COMPILER_OPT($1, -Wshadow)
AC_LBL_CHECK_COMPILER_OPT($1, -Wsign-compare)
AC_LBL_CHECK_COMPILER_OPT($1, -Wstrict-prototypes)
AC_LBL_CHECK_COMPILER_OPT($1, -Wunused-parameter)
AC_LBL_CHECK_COMPILER_OPT($1, -Wused-but-marked-unused)
# Warns about safeguards added in case the enums are
# extended
# AC_LBL_CHECK_COMPILER_OPT($1, -Wcovered-switch-default)
#
# This can cause problems with ntohs(), ntohl(),
# htons(), and htonl() on some platforms, such
# as OpenBSD 6.3 with Clang 5.0.1. I guess the
# problem is that the macro that ultimately does
# the byte-swapping involves a conditional
# expression that tests whether the value being
# swapped is a compile-time constant or not,
# using __builtin_constant_p(), and, depending
# on whether it is, does a compile-time swap or
# a run-time swap; perhaps the compiler always
# considers one of the two results of the
# conditional expressin is never evaluated,
# because the conditional check is done at
# compile time, and thus always says "that
# expression is never executed".
#
# (Perhaps there should be a way of flagging
# an expression that you *want* evaluated at
# compile time, so that the compiler 1) warns
# if it *can't* be evaluated at compile time
# and 2) *doesn't* warn that the true or false
# branch will never be reached.)
#
AC_LBL_CHECK_COMPILER_OPT($1, -Wunreachable-code,
[
#include <arpa/inet.h>
unsigned short
testme(unsigned short a)
{
return ntohs(a);
}
],
[generates warnings from ntohs()])
fi
AC_LBL_CHECK_DEPENDENCY_GENERATION_OPT()
#
# We used to set -n32 for IRIX 6 when not using GCC (presumed
# to mean that we're using MIPS C or MIPSpro C); it specified
# the "new" faster 32-bit ABI, introduced in IRIX 6.2. I'm
# not sure why that would be something to do *only* with a
# .devel file; why should the ABI for which we produce code
# depend on .devel?
#
os=`echo $host_os | sed -e 's/\([[0-9]][[0-9]]*\)[[^0-9]].*$/\1/'`
name="lbl/os-$os.h"
if test -f $name ; then
ln -s $name os-proto.h
AC_DEFINE(HAVE_OS_PROTO_H, 1,
[if there's an os_proto.h for this platform, to use additional prototypes])
else
AC_MSG_WARN(can't find $name)
fi
fi])
dnl
dnl Improved version of AC_CHECK_LIB
dnl
dnl Thanks to John Hawkinson (jhawk@mit.edu)
dnl
dnl usage:
dnl
dnl AC_LBL_CHECK_LIB(LIBRARY, FUNCTION [, ACTION-IF-FOUND [,
dnl ACTION-IF-NOT-FOUND [, OTHER-LIBRARIES]]])
dnl
dnl results:
dnl
dnl LIBS
dnl
dnl XXX - "AC_LBL_LIBRARY_NET" was redone to use "AC_SEARCH_LIBS"
dnl rather than "AC_LBL_CHECK_LIB", so this isn't used any more.
dnl We keep it around for reference purposes in case it's ever
dnl useful in the future.
dnl
define(AC_LBL_CHECK_LIB,
[AC_MSG_CHECKING([for $2 in -l$1])
dnl Use a cache variable name containing the library, function
dnl name, and extra libraries to link with, because the test really is
dnl for library $1 defining function $2, when linked with potinal
dnl library $5, not just for library $1. Separate tests with the same
dnl $1 and different $2's or $5's may have different results.
ac_lib_var=`echo $1['_']$2['_']$5 | sed 'y%./+- %__p__%'`
AC_CACHE_VAL(ac_cv_lbl_lib_$ac_lib_var,
[ac_save_LIBS="$LIBS"
LIBS="-l$1 $5 $LIBS"
AC_TRY_LINK(dnl
ifelse([$2], [main], , dnl Avoid conflicting decl of main.
[/* Override any gcc2 internal prototype to avoid an error. */
]ifelse(AC_LANG, CPLUSPLUS, [#ifdef __cplusplus
extern "C"
#endif
])dnl
[/* We use char because int might match the return type of a gcc2
builtin and then its argument prototype would still apply. */
char $2();
]),
[$2()],
eval "ac_cv_lbl_lib_$ac_lib_var=yes",
eval "ac_cv_lbl_lib_$ac_lib_var=no")
LIBS="$ac_save_LIBS"
])dnl
if eval "test \"`echo '$ac_cv_lbl_lib_'$ac_lib_var`\" = yes"; then
AC_MSG_RESULT(yes)
ifelse([$3], ,
[changequote(, )dnl
ac_tr_lib=HAVE_LIB`echo $1 | sed -e 's/[^a-zA-Z0-9_]/_/g' \
-e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
changequote([, ])dnl
AC_DEFINE_UNQUOTED($ac_tr_lib)
LIBS="-l$1 $LIBS"
], [$3])
else
AC_MSG_RESULT(no)
ifelse([$4], , , [$4
])dnl
fi
])
dnl
dnl AC_LBL_LIBRARY_NET
dnl
dnl This test is for network applications that need socket functions and
dnl getaddrinfo()/getnameinfo()-ish functions. We now require
dnl getaddrinfo() and getnameinfo(). We also prefer versions of
dnl recvmsg() that conform to the Single UNIX Specification, so that we
dnl can check whether a datagram received with recvmsg() was truncated
dnl when received due to the buffer being too small.
dnl
dnl On most operating systems, they're available in the system library.
dnl
dnl Under Solaris, we need to link with libsocket and libnsl to get
dnl getaddrinfo() and getnameinfo() and, if we have libxnet, we need to
dnl link with libxnet before libsocket to get a version of recvmsg()
dnl that conforms to the Single UNIX Specification.
dnl
dnl We use getaddrinfo() because we want a portable thread-safe way
dnl of getting information for a host name or port; there exist _r
dnl versions of gethostbyname() and getservbyname() on some platforms,
dnl but not on all platforms.
dnl
AC_DEFUN(AC_LBL_LIBRARY_NET, [
#
# Most operating systems have getaddrinfo() in the default searched
# libraries (i.e. libc). Check there first.
#
AC_CHECK_FUNC(getaddrinfo,,
[
#
# Not found in the standard system libraries.
# Try libsocket, which requires libnsl.
#
AC_CHECK_LIB(socket, getaddrinfo,
[
#
# OK, we found it in libsocket.
#
LIBS="-lsocket -lnsl $LIBS"
],
[
#
# We didn't find it.
#
AC_MSG_ERROR([getaddrinfo is required, but wasn't found])
], -lnsl)
#
# OK, do we have recvmsg() in libxnet?
# We also link with libsocket and libnsl.
#
AC_CHECK_LIB(xnet, recvmsg,
[
#
# Yes - link with it as well.
#
LIBS="-lxnet $LIBS"
], , -lsocket -lnsl)
])
# DLPI needs putmsg under HPUX so test for -lstr while we're at it
AC_SEARCH_LIBS(putmsg, str)
])
| {
"language": "Assembly"
} |
// Copyright 2014 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
// uint32 runtime∕internal∕atomic·Load(uint32 volatile* addr)
TEXT ·Load(SB),NOSPLIT,$0-12
MOVD ptr+0(FP), R0
LDARW (R0), R0
MOVW R0, ret+8(FP)
RET
// uint8 runtime∕internal∕atomic·Load8(uint8 volatile* addr)
TEXT ·Load8(SB),NOSPLIT,$0-9
MOVD ptr+0(FP), R0
LDARB (R0), R0
MOVB R0, ret+8(FP)
RET
// uint64 runtime∕internal∕atomic·Load64(uint64 volatile* addr)
TEXT ·Load64(SB),NOSPLIT,$0-16
MOVD ptr+0(FP), R0
LDAR (R0), R0
MOVD R0, ret+8(FP)
RET
// void *runtime∕internal∕atomic·Loadp(void *volatile *addr)
TEXT ·Loadp(SB),NOSPLIT,$0-16
MOVD ptr+0(FP), R0
LDAR (R0), R0
MOVD R0, ret+8(FP)
RET
// uint32 runtime∕internal∕atomic·LoadAcq(uint32 volatile* addr)
TEXT ·LoadAcq(SB),NOSPLIT,$0-12
B ·Load(SB)
TEXT runtime∕internal∕atomic·StorepNoWB(SB), NOSPLIT, $0-16
B runtime∕internal∕atomic·Store64(SB)
TEXT runtime∕internal∕atomic·StoreRel(SB), NOSPLIT, $0-12
B runtime∕internal∕atomic·Store(SB)
TEXT runtime∕internal∕atomic·Store(SB), NOSPLIT, $0-12
MOVD ptr+0(FP), R0
MOVW val+8(FP), R1
STLRW R1, (R0)
RET
TEXT runtime∕internal∕atomic·Store8(SB), NOSPLIT, $0-9
MOVD ptr+0(FP), R0
MOVB val+8(FP), R1
STLRB R1, (R0)
RET
TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-16
MOVD ptr+0(FP), R0
MOVD val+8(FP), R1
STLR R1, (R0)
RET
TEXT runtime∕internal∕atomic·Xchg(SB), NOSPLIT, $0-20
MOVD ptr+0(FP), R0
MOVW new+8(FP), R1
again:
LDAXRW (R0), R2
STLXRW R1, (R0), R3
CBNZ R3, again
MOVW R2, ret+16(FP)
RET
TEXT runtime∕internal∕atomic·Xchg64(SB), NOSPLIT, $0-24
MOVD ptr+0(FP), R0
MOVD new+8(FP), R1
again:
LDAXR (R0), R2
STLXR R1, (R0), R3
CBNZ R3, again
MOVD R2, ret+16(FP)
RET
// bool runtime∕internal∕atomic·Cas64(uint64 *ptr, uint64 old, uint64 new)
// Atomically:
// if(*val == *old){
// *val = new;
// return 1;
// } else {
// return 0;
// }
TEXT runtime∕internal∕atomic·Cas64(SB), NOSPLIT, $0-25
MOVD ptr+0(FP), R0
MOVD old+8(FP), R1
MOVD new+16(FP), R2
again:
LDAXR (R0), R3
CMP R1, R3
BNE ok
STLXR R2, (R0), R3
CBNZ R3, again
ok:
CSET EQ, R0
MOVB R0, ret+24(FP)
RET
// uint32 xadd(uint32 volatile *ptr, int32 delta)
// Atomically:
// *val += delta;
// return *val;
TEXT runtime∕internal∕atomic·Xadd(SB), NOSPLIT, $0-20
MOVD ptr+0(FP), R0
MOVW delta+8(FP), R1
again:
LDAXRW (R0), R2
ADDW R2, R1, R2
STLXRW R2, (R0), R3
CBNZ R3, again
MOVW R2, ret+16(FP)
RET
TEXT runtime∕internal∕atomic·Xadd64(SB), NOSPLIT, $0-24
MOVD ptr+0(FP), R0
MOVD delta+8(FP), R1
again:
LDAXR (R0), R2
ADD R2, R1, R2
STLXR R2, (R0), R3
CBNZ R3, again
MOVD R2, ret+16(FP)
RET
TEXT runtime∕internal∕atomic·Xchguintptr(SB), NOSPLIT, $0-24
B runtime∕internal∕atomic·Xchg64(SB)
TEXT ·And8(SB), NOSPLIT, $0-9
MOVD ptr+0(FP), R0
MOVB val+8(FP), R1
LDAXRB (R0), R2
AND R1, R2
STLXRB R2, (R0), R3
CBNZ R3, -3(PC)
RET
TEXT ·Or8(SB), NOSPLIT, $0-9
MOVD ptr+0(FP), R0
MOVB val+8(FP), R1
LDAXRB (R0), R2
ORR R1, R2
STLXRB R2, (R0), R3
CBNZ R3, -3(PC)
RET
| {
"language": "Assembly"
} |
// go run mkasm_darwin.go arm64
// Code generated by the command above; DO NOT EDIT.
// +build go1.12
#include "textflag.h"
TEXT ·libc_getgroups_trampoline(SB),NOSPLIT,$0-0
JMP libc_getgroups(SB)
TEXT ·libc_setgroups_trampoline(SB),NOSPLIT,$0-0
JMP libc_setgroups(SB)
TEXT ·libc_wait4_trampoline(SB),NOSPLIT,$0-0
JMP libc_wait4(SB)
TEXT ·libc_accept_trampoline(SB),NOSPLIT,$0-0
JMP libc_accept(SB)
TEXT ·libc_bind_trampoline(SB),NOSPLIT,$0-0
JMP libc_bind(SB)
TEXT ·libc_connect_trampoline(SB),NOSPLIT,$0-0
JMP libc_connect(SB)
TEXT ·libc_socket_trampoline(SB),NOSPLIT,$0-0
JMP libc_socket(SB)
TEXT ·libc_getsockopt_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsockopt(SB)
TEXT ·libc_setsockopt_trampoline(SB),NOSPLIT,$0-0
JMP libc_setsockopt(SB)
TEXT ·libc_getpeername_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpeername(SB)
TEXT ·libc_getsockname_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsockname(SB)
TEXT ·libc_shutdown_trampoline(SB),NOSPLIT,$0-0
JMP libc_shutdown(SB)
TEXT ·libc_socketpair_trampoline(SB),NOSPLIT,$0-0
JMP libc_socketpair(SB)
TEXT ·libc_recvfrom_trampoline(SB),NOSPLIT,$0-0
JMP libc_recvfrom(SB)
TEXT ·libc_sendto_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendto(SB)
TEXT ·libc_recvmsg_trampoline(SB),NOSPLIT,$0-0
JMP libc_recvmsg(SB)
TEXT ·libc_sendmsg_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendmsg(SB)
TEXT ·libc_kevent_trampoline(SB),NOSPLIT,$0-0
JMP libc_kevent(SB)
TEXT ·libc___sysctl_trampoline(SB),NOSPLIT,$0-0
JMP libc___sysctl(SB)
TEXT ·libc_utimes_trampoline(SB),NOSPLIT,$0-0
JMP libc_utimes(SB)
TEXT ·libc_futimes_trampoline(SB),NOSPLIT,$0-0
JMP libc_futimes(SB)
TEXT ·libc_fcntl_trampoline(SB),NOSPLIT,$0-0
JMP libc_fcntl(SB)
TEXT ·libc_poll_trampoline(SB),NOSPLIT,$0-0
JMP libc_poll(SB)
TEXT ·libc_madvise_trampoline(SB),NOSPLIT,$0-0
JMP libc_madvise(SB)
TEXT ·libc_mlock_trampoline(SB),NOSPLIT,$0-0
JMP libc_mlock(SB)
TEXT ·libc_mlockall_trampoline(SB),NOSPLIT,$0-0
JMP libc_mlockall(SB)
TEXT ·libc_mprotect_trampoline(SB),NOSPLIT,$0-0
JMP libc_mprotect(SB)
TEXT ·libc_msync_trampoline(SB),NOSPLIT,$0-0
JMP libc_msync(SB)
TEXT ·libc_munlock_trampoline(SB),NOSPLIT,$0-0
JMP libc_munlock(SB)
TEXT ·libc_munlockall_trampoline(SB),NOSPLIT,$0-0
JMP libc_munlockall(SB)
TEXT ·libc_ptrace_trampoline(SB),NOSPLIT,$0-0
JMP libc_ptrace(SB)
TEXT ·libc_getattrlist_trampoline(SB),NOSPLIT,$0-0
JMP libc_getattrlist(SB)
TEXT ·libc_pipe_trampoline(SB),NOSPLIT,$0-0
JMP libc_pipe(SB)
TEXT ·libc_getxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_getxattr(SB)
TEXT ·libc_fgetxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fgetxattr(SB)
TEXT ·libc_setxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_setxattr(SB)
TEXT ·libc_fsetxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fsetxattr(SB)
TEXT ·libc_removexattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_removexattr(SB)
TEXT ·libc_fremovexattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fremovexattr(SB)
TEXT ·libc_listxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_listxattr(SB)
TEXT ·libc_flistxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_flistxattr(SB)
TEXT ·libc_setattrlist_trampoline(SB),NOSPLIT,$0-0
JMP libc_setattrlist(SB)
TEXT ·libc_kill_trampoline(SB),NOSPLIT,$0-0
JMP libc_kill(SB)
TEXT ·libc_ioctl_trampoline(SB),NOSPLIT,$0-0
JMP libc_ioctl(SB)
TEXT ·libc_sendfile_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendfile(SB)
TEXT ·libc_access_trampoline(SB),NOSPLIT,$0-0
JMP libc_access(SB)
TEXT ·libc_adjtime_trampoline(SB),NOSPLIT,$0-0
JMP libc_adjtime(SB)
TEXT ·libc_chdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_chdir(SB)
TEXT ·libc_chflags_trampoline(SB),NOSPLIT,$0-0
JMP libc_chflags(SB)
TEXT ·libc_chmod_trampoline(SB),NOSPLIT,$0-0
JMP libc_chmod(SB)
TEXT ·libc_chown_trampoline(SB),NOSPLIT,$0-0
JMP libc_chown(SB)
TEXT ·libc_chroot_trampoline(SB),NOSPLIT,$0-0
JMP libc_chroot(SB)
TEXT ·libc_close_trampoline(SB),NOSPLIT,$0-0
JMP libc_close(SB)
TEXT ·libc_dup_trampoline(SB),NOSPLIT,$0-0
JMP libc_dup(SB)
TEXT ·libc_dup2_trampoline(SB),NOSPLIT,$0-0
JMP libc_dup2(SB)
TEXT ·libc_exchangedata_trampoline(SB),NOSPLIT,$0-0
JMP libc_exchangedata(SB)
TEXT ·libc_exit_trampoline(SB),NOSPLIT,$0-0
JMP libc_exit(SB)
TEXT ·libc_faccessat_trampoline(SB),NOSPLIT,$0-0
JMP libc_faccessat(SB)
TEXT ·libc_fchdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchdir(SB)
TEXT ·libc_fchflags_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchflags(SB)
TEXT ·libc_fchmod_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchmod(SB)
TEXT ·libc_fchmodat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchmodat(SB)
TEXT ·libc_fchown_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchown(SB)
TEXT ·libc_fchownat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchownat(SB)
TEXT ·libc_flock_trampoline(SB),NOSPLIT,$0-0
JMP libc_flock(SB)
TEXT ·libc_fpathconf_trampoline(SB),NOSPLIT,$0-0
JMP libc_fpathconf(SB)
TEXT ·libc_fsync_trampoline(SB),NOSPLIT,$0-0
JMP libc_fsync(SB)
TEXT ·libc_ftruncate_trampoline(SB),NOSPLIT,$0-0
JMP libc_ftruncate(SB)
TEXT ·libc_getdtablesize_trampoline(SB),NOSPLIT,$0-0
JMP libc_getdtablesize(SB)
TEXT ·libc_getegid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getegid(SB)
TEXT ·libc_geteuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_geteuid(SB)
TEXT ·libc_getgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getgid(SB)
TEXT ·libc_getpgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpgid(SB)
TEXT ·libc_getpgrp_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpgrp(SB)
TEXT ·libc_getpid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpid(SB)
TEXT ·libc_getppid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getppid(SB)
TEXT ·libc_getpriority_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpriority(SB)
TEXT ·libc_getrlimit_trampoline(SB),NOSPLIT,$0-0
JMP libc_getrlimit(SB)
TEXT ·libc_getrusage_trampoline(SB),NOSPLIT,$0-0
JMP libc_getrusage(SB)
TEXT ·libc_getsid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsid(SB)
TEXT ·libc_getuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getuid(SB)
TEXT ·libc_issetugid_trampoline(SB),NOSPLIT,$0-0
JMP libc_issetugid(SB)
TEXT ·libc_kqueue_trampoline(SB),NOSPLIT,$0-0
JMP libc_kqueue(SB)
TEXT ·libc_lchown_trampoline(SB),NOSPLIT,$0-0
JMP libc_lchown(SB)
TEXT ·libc_link_trampoline(SB),NOSPLIT,$0-0
JMP libc_link(SB)
TEXT ·libc_linkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_linkat(SB)
TEXT ·libc_listen_trampoline(SB),NOSPLIT,$0-0
JMP libc_listen(SB)
TEXT ·libc_mkdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkdir(SB)
TEXT ·libc_mkdirat_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkdirat(SB)
TEXT ·libc_mkfifo_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkfifo(SB)
TEXT ·libc_mknod_trampoline(SB),NOSPLIT,$0-0
JMP libc_mknod(SB)
TEXT ·libc_open_trampoline(SB),NOSPLIT,$0-0
JMP libc_open(SB)
TEXT ·libc_openat_trampoline(SB),NOSPLIT,$0-0
JMP libc_openat(SB)
TEXT ·libc_pathconf_trampoline(SB),NOSPLIT,$0-0
JMP libc_pathconf(SB)
TEXT ·libc_pread_trampoline(SB),NOSPLIT,$0-0
JMP libc_pread(SB)
TEXT ·libc_pwrite_trampoline(SB),NOSPLIT,$0-0
JMP libc_pwrite(SB)
TEXT ·libc_read_trampoline(SB),NOSPLIT,$0-0
JMP libc_read(SB)
TEXT ·libc_readlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_readlink(SB)
TEXT ·libc_readlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_readlinkat(SB)
TEXT ·libc_rename_trampoline(SB),NOSPLIT,$0-0
JMP libc_rename(SB)
TEXT ·libc_renameat_trampoline(SB),NOSPLIT,$0-0
JMP libc_renameat(SB)
TEXT ·libc_revoke_trampoline(SB),NOSPLIT,$0-0
JMP libc_revoke(SB)
TEXT ·libc_rmdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_rmdir(SB)
TEXT ·libc_lseek_trampoline(SB),NOSPLIT,$0-0
JMP libc_lseek(SB)
TEXT ·libc_select_trampoline(SB),NOSPLIT,$0-0
JMP libc_select(SB)
TEXT ·libc_setegid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setegid(SB)
TEXT ·libc_seteuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_seteuid(SB)
TEXT ·libc_setgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setgid(SB)
TEXT ·libc_setlogin_trampoline(SB),NOSPLIT,$0-0
JMP libc_setlogin(SB)
TEXT ·libc_setpgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setpgid(SB)
TEXT ·libc_setpriority_trampoline(SB),NOSPLIT,$0-0
JMP libc_setpriority(SB)
TEXT ·libc_setprivexec_trampoline(SB),NOSPLIT,$0-0
JMP libc_setprivexec(SB)
TEXT ·libc_setregid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setregid(SB)
TEXT ·libc_setreuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setreuid(SB)
TEXT ·libc_setrlimit_trampoline(SB),NOSPLIT,$0-0
JMP libc_setrlimit(SB)
TEXT ·libc_setsid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setsid(SB)
TEXT ·libc_settimeofday_trampoline(SB),NOSPLIT,$0-0
JMP libc_settimeofday(SB)
TEXT ·libc_setuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setuid(SB)
TEXT ·libc_symlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_symlink(SB)
TEXT ·libc_symlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_symlinkat(SB)
TEXT ·libc_sync_trampoline(SB),NOSPLIT,$0-0
JMP libc_sync(SB)
TEXT ·libc_truncate_trampoline(SB),NOSPLIT,$0-0
JMP libc_truncate(SB)
TEXT ·libc_umask_trampoline(SB),NOSPLIT,$0-0
JMP libc_umask(SB)
TEXT ·libc_undelete_trampoline(SB),NOSPLIT,$0-0
JMP libc_undelete(SB)
TEXT ·libc_unlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_unlink(SB)
TEXT ·libc_unlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_unlinkat(SB)
TEXT ·libc_unmount_trampoline(SB),NOSPLIT,$0-0
JMP libc_unmount(SB)
TEXT ·libc_write_trampoline(SB),NOSPLIT,$0-0
JMP libc_write(SB)
TEXT ·libc_mmap_trampoline(SB),NOSPLIT,$0-0
JMP libc_mmap(SB)
TEXT ·libc_munmap_trampoline(SB),NOSPLIT,$0-0
JMP libc_munmap(SB)
TEXT ·libc_gettimeofday_trampoline(SB),NOSPLIT,$0-0
JMP libc_gettimeofday(SB)
TEXT ·libc_fstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstat(SB)
TEXT ·libc_fstatat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstatat(SB)
TEXT ·libc_fstatfs_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstatfs(SB)
TEXT ·libc_getfsstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_getfsstat(SB)
TEXT ·libc_lstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_lstat(SB)
TEXT ·libc_stat_trampoline(SB),NOSPLIT,$0-0
JMP libc_stat(SB)
TEXT ·libc_statfs_trampoline(SB),NOSPLIT,$0-0
JMP libc_statfs(SB)
| {
"language": "Assembly"
} |
# /* **************************************************************************
# * *
# * (C) Copyright Paul Mensonides 2002.
# * Distributed under the Boost Software License, Version 1.0. (See
# * accompanying file LICENSE_1_0.txt or copy at
# * http://www.boost.org/LICENSE_1_0.txt)
# * *
# ************************************************************************** */
#
# /* See http://www.boost.org for most recent version. */
#
# ifndef BOOST_PREPROCESSOR_SLOT_DETAIL_DEF_HPP
# define BOOST_PREPROCESSOR_SLOT_DETAIL_DEF_HPP
#
# /* BOOST_PP_SLOT_OFFSET_x */
#
# define BOOST_PP_SLOT_OFFSET_10(x) (x) % 1000000000UL
# define BOOST_PP_SLOT_OFFSET_9(x) BOOST_PP_SLOT_OFFSET_10(x) % 100000000UL
# define BOOST_PP_SLOT_OFFSET_8(x) BOOST_PP_SLOT_OFFSET_9(x) % 10000000UL
# define BOOST_PP_SLOT_OFFSET_7(x) BOOST_PP_SLOT_OFFSET_8(x) % 1000000UL
# define BOOST_PP_SLOT_OFFSET_6(x) BOOST_PP_SLOT_OFFSET_7(x) % 100000UL
# define BOOST_PP_SLOT_OFFSET_5(x) BOOST_PP_SLOT_OFFSET_6(x) % 10000UL
# define BOOST_PP_SLOT_OFFSET_4(x) BOOST_PP_SLOT_OFFSET_5(x) % 1000UL
# define BOOST_PP_SLOT_OFFSET_3(x) BOOST_PP_SLOT_OFFSET_4(x) % 100UL
# define BOOST_PP_SLOT_OFFSET_2(x) BOOST_PP_SLOT_OFFSET_3(x) % 10UL
#
# /* BOOST_PP_SLOT_CC_x */
#
# define BOOST_PP_SLOT_CC_2(a, b) BOOST_PP_SLOT_CC_2_D(a, b)
# define BOOST_PP_SLOT_CC_3(a, b, c) BOOST_PP_SLOT_CC_3_D(a, b, c)
# define BOOST_PP_SLOT_CC_4(a, b, c, d) BOOST_PP_SLOT_CC_4_D(a, b, c, d)
# define BOOST_PP_SLOT_CC_5(a, b, c, d, e) BOOST_PP_SLOT_CC_5_D(a, b, c, d, e)
# define BOOST_PP_SLOT_CC_6(a, b, c, d, e, f) BOOST_PP_SLOT_CC_6_D(a, b, c, d, e, f)
# define BOOST_PP_SLOT_CC_7(a, b, c, d, e, f, g) BOOST_PP_SLOT_CC_7_D(a, b, c, d, e, f, g)
# define BOOST_PP_SLOT_CC_8(a, b, c, d, e, f, g, h) BOOST_PP_SLOT_CC_8_D(a, b, c, d, e, f, g, h)
# define BOOST_PP_SLOT_CC_9(a, b, c, d, e, f, g, h, i) BOOST_PP_SLOT_CC_9_D(a, b, c, d, e, f, g, h, i)
# define BOOST_PP_SLOT_CC_10(a, b, c, d, e, f, g, h, i, j) BOOST_PP_SLOT_CC_10_D(a, b, c, d, e, f, g, h, i, j)
#
# define BOOST_PP_SLOT_CC_2_D(a, b) a ## b
# define BOOST_PP_SLOT_CC_3_D(a, b, c) a ## b ## c
# define BOOST_PP_SLOT_CC_4_D(a, b, c, d) a ## b ## c ## d
# define BOOST_PP_SLOT_CC_5_D(a, b, c, d, e) a ## b ## c ## d ## e
# define BOOST_PP_SLOT_CC_6_D(a, b, c, d, e, f) a ## b ## c ## d ## e ## f
# define BOOST_PP_SLOT_CC_7_D(a, b, c, d, e, f, g) a ## b ## c ## d ## e ## f ## g
# define BOOST_PP_SLOT_CC_8_D(a, b, c, d, e, f, g, h) a ## b ## c ## d ## e ## f ## g ## h
# define BOOST_PP_SLOT_CC_9_D(a, b, c, d, e, f, g, h, i) a ## b ## c ## d ## e ## f ## g ## h ## i
# define BOOST_PP_SLOT_CC_10_D(a, b, c, d, e, f, g, h, i, j) a ## b ## c ## d ## e ## f ## g ## h ## i ## j
#
# endif
| {
"language": "Assembly"
} |