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// go run mkasm_darwin.go arm
// Code generated by the command above; DO NOT EDIT.
// +build go1.12
#include "textflag.h"
TEXT ·libc_getgroups_trampoline(SB),NOSPLIT,$0-0
JMP libc_getgroups(SB)
TEXT ·libc_setgroups_trampoline(SB),NOSPLIT,$0-0
JMP libc_setgroups(SB)
TEXT ·libc_wait4_trampoline(SB),NOSPLIT,$0-0
JMP libc_wait4(SB)
TEXT ·libc_accept_trampoline(SB),NOSPLIT,$0-0
JMP libc_accept(SB)
TEXT ·libc_bind_trampoline(SB),NOSPLIT,$0-0
JMP libc_bind(SB)
TEXT ·libc_connect_trampoline(SB),NOSPLIT,$0-0
JMP libc_connect(SB)
TEXT ·libc_socket_trampoline(SB),NOSPLIT,$0-0
JMP libc_socket(SB)
TEXT ·libc_getsockopt_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsockopt(SB)
TEXT ·libc_setsockopt_trampoline(SB),NOSPLIT,$0-0
JMP libc_setsockopt(SB)
TEXT ·libc_getpeername_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpeername(SB)
TEXT ·libc_getsockname_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsockname(SB)
TEXT ·libc_shutdown_trampoline(SB),NOSPLIT,$0-0
JMP libc_shutdown(SB)
TEXT ·libc_socketpair_trampoline(SB),NOSPLIT,$0-0
JMP libc_socketpair(SB)
TEXT ·libc_recvfrom_trampoline(SB),NOSPLIT,$0-0
JMP libc_recvfrom(SB)
TEXT ·libc_sendto_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendto(SB)
TEXT ·libc_recvmsg_trampoline(SB),NOSPLIT,$0-0
JMP libc_recvmsg(SB)
TEXT ·libc_sendmsg_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendmsg(SB)
TEXT ·libc_kevent_trampoline(SB),NOSPLIT,$0-0
JMP libc_kevent(SB)
TEXT ·libc___sysctl_trampoline(SB),NOSPLIT,$0-0
JMP libc___sysctl(SB)
TEXT ·libc_utimes_trampoline(SB),NOSPLIT,$0-0
JMP libc_utimes(SB)
TEXT ·libc_futimes_trampoline(SB),NOSPLIT,$0-0
JMP libc_futimes(SB)
TEXT ·libc_fcntl_trampoline(SB),NOSPLIT,$0-0
JMP libc_fcntl(SB)
TEXT ·libc_poll_trampoline(SB),NOSPLIT,$0-0
JMP libc_poll(SB)
TEXT ·libc_madvise_trampoline(SB),NOSPLIT,$0-0
JMP libc_madvise(SB)
TEXT ·libc_mlock_trampoline(SB),NOSPLIT,$0-0
JMP libc_mlock(SB)
TEXT ·libc_mlockall_trampoline(SB),NOSPLIT,$0-0
JMP libc_mlockall(SB)
TEXT ·libc_mprotect_trampoline(SB),NOSPLIT,$0-0
JMP libc_mprotect(SB)
TEXT ·libc_msync_trampoline(SB),NOSPLIT,$0-0
JMP libc_msync(SB)
TEXT ·libc_munlock_trampoline(SB),NOSPLIT,$0-0
JMP libc_munlock(SB)
TEXT ·libc_munlockall_trampoline(SB),NOSPLIT,$0-0
JMP libc_munlockall(SB)
TEXT ·libc_ptrace_trampoline(SB),NOSPLIT,$0-0
JMP libc_ptrace(SB)
TEXT ·libc_getattrlist_trampoline(SB),NOSPLIT,$0-0
JMP libc_getattrlist(SB)
TEXT ·libc_pipe_trampoline(SB),NOSPLIT,$0-0
JMP libc_pipe(SB)
TEXT ·libc_getxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_getxattr(SB)
TEXT ·libc_fgetxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fgetxattr(SB)
TEXT ·libc_setxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_setxattr(SB)
TEXT ·libc_fsetxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fsetxattr(SB)
TEXT ·libc_removexattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_removexattr(SB)
TEXT ·libc_fremovexattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_fremovexattr(SB)
TEXT ·libc_listxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_listxattr(SB)
TEXT ·libc_flistxattr_trampoline(SB),NOSPLIT,$0-0
JMP libc_flistxattr(SB)
TEXT ·libc_setattrlist_trampoline(SB),NOSPLIT,$0-0
JMP libc_setattrlist(SB)
TEXT ·libc_kill_trampoline(SB),NOSPLIT,$0-0
JMP libc_kill(SB)
TEXT ·libc_ioctl_trampoline(SB),NOSPLIT,$0-0
JMP libc_ioctl(SB)
TEXT ·libc_sendfile_trampoline(SB),NOSPLIT,$0-0
JMP libc_sendfile(SB)
TEXT ·libc_access_trampoline(SB),NOSPLIT,$0-0
JMP libc_access(SB)
TEXT ·libc_adjtime_trampoline(SB),NOSPLIT,$0-0
JMP libc_adjtime(SB)
TEXT ·libc_chdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_chdir(SB)
TEXT ·libc_chflags_trampoline(SB),NOSPLIT,$0-0
JMP libc_chflags(SB)
TEXT ·libc_chmod_trampoline(SB),NOSPLIT,$0-0
JMP libc_chmod(SB)
TEXT ·libc_chown_trampoline(SB),NOSPLIT,$0-0
JMP libc_chown(SB)
TEXT ·libc_chroot_trampoline(SB),NOSPLIT,$0-0
JMP libc_chroot(SB)
TEXT ·libc_close_trampoline(SB),NOSPLIT,$0-0
JMP libc_close(SB)
TEXT ·libc_dup_trampoline(SB),NOSPLIT,$0-0
JMP libc_dup(SB)
TEXT ·libc_dup2_trampoline(SB),NOSPLIT,$0-0
JMP libc_dup2(SB)
TEXT ·libc_exchangedata_trampoline(SB),NOSPLIT,$0-0
JMP libc_exchangedata(SB)
TEXT ·libc_exit_trampoline(SB),NOSPLIT,$0-0
JMP libc_exit(SB)
TEXT ·libc_faccessat_trampoline(SB),NOSPLIT,$0-0
JMP libc_faccessat(SB)
TEXT ·libc_fchdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchdir(SB)
TEXT ·libc_fchflags_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchflags(SB)
TEXT ·libc_fchmod_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchmod(SB)
TEXT ·libc_fchmodat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchmodat(SB)
TEXT ·libc_fchown_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchown(SB)
TEXT ·libc_fchownat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fchownat(SB)
TEXT ·libc_flock_trampoline(SB),NOSPLIT,$0-0
JMP libc_flock(SB)
TEXT ·libc_fpathconf_trampoline(SB),NOSPLIT,$0-0
JMP libc_fpathconf(SB)
TEXT ·libc_fsync_trampoline(SB),NOSPLIT,$0-0
JMP libc_fsync(SB)
TEXT ·libc_ftruncate_trampoline(SB),NOSPLIT,$0-0
JMP libc_ftruncate(SB)
TEXT ·libc_getdtablesize_trampoline(SB),NOSPLIT,$0-0
JMP libc_getdtablesize(SB)
TEXT ·libc_getegid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getegid(SB)
TEXT ·libc_geteuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_geteuid(SB)
TEXT ·libc_getgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getgid(SB)
TEXT ·libc_getpgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpgid(SB)
TEXT ·libc_getpgrp_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpgrp(SB)
TEXT ·libc_getpid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpid(SB)
TEXT ·libc_getppid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getppid(SB)
TEXT ·libc_getpriority_trampoline(SB),NOSPLIT,$0-0
JMP libc_getpriority(SB)
TEXT ·libc_getrlimit_trampoline(SB),NOSPLIT,$0-0
JMP libc_getrlimit(SB)
TEXT ·libc_getrusage_trampoline(SB),NOSPLIT,$0-0
JMP libc_getrusage(SB)
TEXT ·libc_getsid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getsid(SB)
TEXT ·libc_getuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_getuid(SB)
TEXT ·libc_issetugid_trampoline(SB),NOSPLIT,$0-0
JMP libc_issetugid(SB)
TEXT ·libc_kqueue_trampoline(SB),NOSPLIT,$0-0
JMP libc_kqueue(SB)
TEXT ·libc_lchown_trampoline(SB),NOSPLIT,$0-0
JMP libc_lchown(SB)
TEXT ·libc_link_trampoline(SB),NOSPLIT,$0-0
JMP libc_link(SB)
TEXT ·libc_linkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_linkat(SB)
TEXT ·libc_listen_trampoline(SB),NOSPLIT,$0-0
JMP libc_listen(SB)
TEXT ·libc_mkdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkdir(SB)
TEXT ·libc_mkdirat_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkdirat(SB)
TEXT ·libc_mkfifo_trampoline(SB),NOSPLIT,$0-0
JMP libc_mkfifo(SB)
TEXT ·libc_mknod_trampoline(SB),NOSPLIT,$0-0
JMP libc_mknod(SB)
TEXT ·libc_open_trampoline(SB),NOSPLIT,$0-0
JMP libc_open(SB)
TEXT ·libc_openat_trampoline(SB),NOSPLIT,$0-0
JMP libc_openat(SB)
TEXT ·libc_pathconf_trampoline(SB),NOSPLIT,$0-0
JMP libc_pathconf(SB)
TEXT ·libc_pread_trampoline(SB),NOSPLIT,$0-0
JMP libc_pread(SB)
TEXT ·libc_pwrite_trampoline(SB),NOSPLIT,$0-0
JMP libc_pwrite(SB)
TEXT ·libc_read_trampoline(SB),NOSPLIT,$0-0
JMP libc_read(SB)
TEXT ·libc_readlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_readlink(SB)
TEXT ·libc_readlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_readlinkat(SB)
TEXT ·libc_rename_trampoline(SB),NOSPLIT,$0-0
JMP libc_rename(SB)
TEXT ·libc_renameat_trampoline(SB),NOSPLIT,$0-0
JMP libc_renameat(SB)
TEXT ·libc_revoke_trampoline(SB),NOSPLIT,$0-0
JMP libc_revoke(SB)
TEXT ·libc_rmdir_trampoline(SB),NOSPLIT,$0-0
JMP libc_rmdir(SB)
TEXT ·libc_lseek_trampoline(SB),NOSPLIT,$0-0
JMP libc_lseek(SB)
TEXT ·libc_select_trampoline(SB),NOSPLIT,$0-0
JMP libc_select(SB)
TEXT ·libc_setegid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setegid(SB)
TEXT ·libc_seteuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_seteuid(SB)
TEXT ·libc_setgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setgid(SB)
TEXT ·libc_setlogin_trampoline(SB),NOSPLIT,$0-0
JMP libc_setlogin(SB)
TEXT ·libc_setpgid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setpgid(SB)
TEXT ·libc_setpriority_trampoline(SB),NOSPLIT,$0-0
JMP libc_setpriority(SB)
TEXT ·libc_setprivexec_trampoline(SB),NOSPLIT,$0-0
JMP libc_setprivexec(SB)
TEXT ·libc_setregid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setregid(SB)
TEXT ·libc_setreuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setreuid(SB)
TEXT ·libc_setrlimit_trampoline(SB),NOSPLIT,$0-0
JMP libc_setrlimit(SB)
TEXT ·libc_setsid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setsid(SB)
TEXT ·libc_settimeofday_trampoline(SB),NOSPLIT,$0-0
JMP libc_settimeofday(SB)
TEXT ·libc_setuid_trampoline(SB),NOSPLIT,$0-0
JMP libc_setuid(SB)
TEXT ·libc_symlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_symlink(SB)
TEXT ·libc_symlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_symlinkat(SB)
TEXT ·libc_sync_trampoline(SB),NOSPLIT,$0-0
JMP libc_sync(SB)
TEXT ·libc_truncate_trampoline(SB),NOSPLIT,$0-0
JMP libc_truncate(SB)
TEXT ·libc_umask_trampoline(SB),NOSPLIT,$0-0
JMP libc_umask(SB)
TEXT ·libc_undelete_trampoline(SB),NOSPLIT,$0-0
JMP libc_undelete(SB)
TEXT ·libc_unlink_trampoline(SB),NOSPLIT,$0-0
JMP libc_unlink(SB)
TEXT ·libc_unlinkat_trampoline(SB),NOSPLIT,$0-0
JMP libc_unlinkat(SB)
TEXT ·libc_unmount_trampoline(SB),NOSPLIT,$0-0
JMP libc_unmount(SB)
TEXT ·libc_write_trampoline(SB),NOSPLIT,$0-0
JMP libc_write(SB)
TEXT ·libc_mmap_trampoline(SB),NOSPLIT,$0-0
JMP libc_mmap(SB)
TEXT ·libc_munmap_trampoline(SB),NOSPLIT,$0-0
JMP libc_munmap(SB)
TEXT ·libc_gettimeofday_trampoline(SB),NOSPLIT,$0-0
JMP libc_gettimeofday(SB)
TEXT ·libc_fstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstat(SB)
TEXT ·libc_fstatat_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstatat(SB)
TEXT ·libc_fstatfs_trampoline(SB),NOSPLIT,$0-0
JMP libc_fstatfs(SB)
TEXT ·libc_getfsstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_getfsstat(SB)
TEXT ·libc_lstat_trampoline(SB),NOSPLIT,$0-0
JMP libc_lstat(SB)
TEXT ·libc_stat_trampoline(SB),NOSPLIT,$0-0
JMP libc_stat(SB)
TEXT ·libc_statfs_trampoline(SB),NOSPLIT,$0-0
JMP libc_statfs(SB)
| {
"language": "Assembly"
} |
/** @file
Implementation of BaseGpioCheckConflictLib.
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Library/GpioCheckConflictLib.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Private/Library/GpioPrivateLib.h>
/**
Check Gpio PadMode conflict and report it.
@retval none.
**/
VOID
GpioCheckConflict (
VOID
)
{
EFI_HOB_GUID_TYPE *GpioCheckConflictHob;
GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
UINT32 HobDataSize;
UINT32 GpioCount;
UINT32 GpioIndex;
GPIO_CONFIG GpioActualConfig;
GpioCheckConflictHob = NULL;
GpioCheckConflictHobData = NULL;
DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n"));
//
//Use Guid to find HOB.
//
GpioCheckConflictHob = (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCheckConflictHobGuid);
if (GpioCheckConflictHob == NULL) {
DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n"));
} else {
while (GpioCheckConflictHob != NULL) {
//
// Find the Data area pointer and Data size from the Hob
//
GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DATA (GpioCheckConflictHob);
HobDataSize = GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob);
GpioCount = HobDataSize / sizeof (GPIO_PAD_MODE_INFO);
DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount = %d\n", GpioCount));
//
// Probe Gpio entries in Hob and compare which are conflicted
//
for (GpioIndex = 0; GpioIndex < GpioCount ; GpioIndex++) {
GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &GpioActualConfig);
if (GpioCheckConflictHobData[GpioIndex].GpioPadMode != GpioActualConfig.PadMode) {
DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad)));
}
}
//
// Find next Hob and return the Hob pointer by the specific Hob Guid
//
GpioCheckConflictHob = GET_NEXT_HOB (GpioCheckConflictHob);
GpioCheckConflictHob = GetNextGuidHob (&gGpioCheckConflictHobGuid, GpioCheckConflictHob);
}
DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n"));
}
return;
}
/**
This libaray will create one Hob for each Gpio config table
without PadMode is GpioHardwareDefault
@param[in] GpioDefinition Point to Platform Gpio table
@param[in] GpioTableCount Number of Gpio table entries
@retval none.
**/
VOID
CreateGpioCheckConflictHob (
IN GPIO_INIT_CONFIG *GpioDefinition,
IN UINT16 GpioTableCount
)
{
UINT32 Index;
UINT32 GpioIndex;
GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
UINT16 GpioCount;
GpioCount = 0;
GpioIndex = 0;
DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n"));
for (Index = 0; Index < GpioTableCount ; Index++) {
if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
continue;
} else {
//
// Calculate how big size the Hob Data needs
//
GpioCount++;
}
}
//
// Build a HOB tagged with a GUID for identification and returns
// the start address of GUID HOB data.
//
GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpioCheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO));
//
// Record Non Default Gpio entries to the Hob
//
for (Index = 0; Index < GpioTableCount; Index++) {
if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
continue;
} else {
GpioCheckConflictHobData[GpioIndex].GpioPad = GpioDefinition[Index].GpioPad;
GpioCheckConflictHobData[GpioIndex].GpioPadMode = GpioDefinition[Index].GpioConfig.PadMode;
GpioIndex++;
}
}
DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n"));
return;
}
| {
"language": "Assembly"
} |
/* Copyright (C) 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#ifndef _SYS_REG_H
#define _SYS_REG_H 1
#include <bits/wordsize.h>
#if __WORDSIZE == 64
/* Index into an array of 8 byte longs returned from ptrace for
location of the users' stored general purpose registers. */
# define R15 0
# define R14 1
# define R13 2
# define R12 3
# define RBP 4
# define RBX 5
# define R11 6
# define R10 7
# define R9 8
# define R8 9
# define RAX 10
# define RCX 11
# define RDX 12
# define RSI 13
# define RDI 14
# define ORIG_RAX 15
# define RIP 16
# define CS 17
# define EFLAGS 18
# define RSP 19
# define SS 20
# define FS_BASE 21
# define GS_BASE 22
# define DS 23
# define ES 24
# define FS 25
# define GS 26
#else
/* Index into an array of 4 byte integers returned from ptrace for
* location of the users' stored general purpose registers. */
# define EBX 0
# define ECX 1
# define EDX 2
# define ESI 3
# define EDI 4
# define EBP 5
# define EAX 6
# define DS 7
# define ES 8
# define FS 9
# define GS 10
# define ORIG_EAX 11
# define EIP 12
# define CS 13
# define EFL 14
# define UESP 15
# define SS 16
#endif
#endif
| {
"language": "Assembly"
} |
config BR2_PACKAGE_XENOMAI_COBALT_ARCH_SUPPORTS
bool
default y
depends on BR2_i386 || BR2_x86_64 || (BR2_arm && !BR2_ARM_CPU_ARMV7M) || \
BR2_powerpc
comment "xenomai needs a glibc or uClibc toolchain w/ threads"
depends on BR2_USE_MMU
depends on BR2_TOOLCHAIN_HAS_SYNC_4
depends on !BR2_TOOLCHAIN_HAS_THREADS || BR2_TOOLCHAIN_USES_MUSL
config BR2_PACKAGE_XENOMAI
bool "Xenomai Userspace"
depends on BR2_USE_MMU
depends on BR2_TOOLCHAIN_HAS_SYNC_4
depends on BR2_TOOLCHAIN_HAS_THREADS
# uses <error.h>, __WORDSIZE and bits/local_lim.h
depends on !BR2_TOOLCHAIN_USES_MUSL
help
Real-Time Framework for Linux
http://www.xenomai.org
Xenomai is split in two parts: a kernel part and an
userspace part.
This package contains the userspace part, which consists
mainly in libraries to write userspace real-time programs
that interact with the in-kernel Xenomai real-time core.
For those libraries to work, you need a Xenomai-enabled
kernel. This is possible in two ways:
- if you compile your kernel with Buildroot, you need to go
to Linux Kernel -> Linux Kernel Extensions to enable the
Xenomai extension.
- if you compile your kernel outside of Buildroot, you need
to make sure that it is Xenomai-enabled.
Finally, if you are using a static /dev, make sure to
uncomment the Xenomai entries listed in
target/generic/device_table_dev.txt.
if BR2_PACKAGE_XENOMAI
config BR2_PACKAGE_XENOMAI_VERSION
string "Custom Xenomai version"
help
Manually select Xenomai version. If left empty, the default
version will be used.
Make sure that the selected version has a patch for your
selected Linux kernel. If it does not, download and select
a patch manually with
BR2_LINUX_KERNEL_EXT_XENOMAI_ADEOS_PATCH, in the Linux
Kernel -> Linux Kernel Extensions menu.
choice
prompt "Xenomai core"
default BR2_PACKAGE_XENOMAI_MERCURY
help
Select the Xenomai core: dual kernel (Cobalt)
or native Linux Kernel (Mercury).
config BR2_PACKAGE_XENOMAI_MERCURY
bool "Mercury"
depends on !BR2_LINUX_KERNEL_EXT_XENOMAI
help
Select Mercury core for the Xenomai userspace.
You want to use it if you have the native Linux Kernel.
config BR2_PACKAGE_XENOMAI_COBALT
bool "Cobalt"
depends on BR2_PACKAGE_XENOMAI_COBALT_ARCH_SUPPORTS
help
Select Cobalt core (dual kernel) for the Xenomai
userspace. Use this if you use a Xenomai-patched
Linux kernel.
If you want to use Cobalt core, your kernel must have
the Adeos and Xenomai patches applied to it. You can
add these through the BR2_LINUX_KERNEL_EXT_XENOMAI option
in the Linux Kernel Extensions menu.
endchoice
config BR2_PACKAGE_XENOMAI_ENABLE_SMP
bool "Enable SMP support"
default y
help
This option enables SMP support in Xenomai userspace.
If this option is turned on while no SMP support is enabled
in the kernel, things will still work. However, if SMP is
enabled in the kernel but this option is not turned on,
Xenomai applications will complain with:
feature mismatch: missing="smp/nosmp"
Please refer to this troubleshooting guide for more
information:
http://xenomai.org/troubleshooting-a-dual-kernel-configuration/#feature_mismatch_missing8221smpnosmp8221
config BR2_PACKAGE_XENOMAI_ENABLE_REGISTRY
bool "Enable registry"
depends on !BR2_STATIC_LIBS # libfuse
depends on BR2_TOOLCHAIN_HAS_THREADS # libfuse
depends on BR2_USE_MMU # libfuse
select BR2_PACKAGE_LIBFUSE
help
Xenomai APIs can export their internal state through a
pseudo-filesystem, whose files may be read to obtain
information about the existing real-time objects, such as
tasks, semaphores, message queues and so on.
comment "registry needs a toolchain w/ threads, dynamic library"
depends on BR2_USE_MMU
depends on BR2_STATIC_LIBS || !BR2_TOOLCHAIN_HAS_THREADS
config BR2_PACKAGE_XENOMAI_ENABLE_REGISTRY_PATH
string "Custom registry root path"
depends on BR2_PACKAGE_XENOMAI_ENABLE_REGISTRY
help
Specify the root path of the registry here.
To use the Xenomai default (currently: /var/run/xenomai),
leave this option empty.
config BR2_PACKAGE_XENOMAI_ADDITIONAL_CONF_OPTS
string "Additional configure options"
help
Specify any additional options to pass to the configure
script here. See Xenomai documentation for details.
config BR2_PACKAGE_XENOMAI_TESTSUITE
bool "Install testsuite"
help
This option allows to install the Xenomai test programs.
config BR2_PACKAGE_XENOMAI_RTCAN
bool "RTCan utilities"
help
This option allows to install the Xenomai RT-CAN utilities.
config BR2_PACKAGE_XENOMAI_ANALOGY
bool "Analogy libs and utils"
help
This option allows to install the Xenomai Analogy utilities
and libraries
menu "Skin selection"
config BR2_PACKAGE_XENOMAI_NATIVE_SKIN
bool "Alchemy (native) skin"
default y
help
This option allows to install the Alchemy Xenomai skin,
previously called 'native'
config BR2_PACKAGE_XENOMAI_POSIX_SKIN
bool "POSIX skin"
default y
help
This option allows to install the POSIX Xenomai skin
config BR2_PACKAGE_XENOMAI_PSOS_SKIN
bool "pSOS skin"
help
This option allows to install the pSOS Xenomai skin
config BR2_PACKAGE_XENOMAI_RTAI_SKIN
bool "RTAI skin"
help
This option allows to install the RTAI Xenomai skin
config BR2_PACKAGE_XENOMAI_SMOKEY_SKIN
bool "Smokey skin"
help
This option allows to install the Smokey Xenomai skin
config BR2_PACKAGE_XENOMAI_UITRON_SKIN
bool "uITRON skin"
help
This option allows to install the uITRON Xenomai skin
config BR2_PACKAGE_XENOMAI_VRTX_SKIN
bool "VRTX skin"
help
This option allows to install the VRTX Xenomai skin
config BR2_PACKAGE_XENOMAI_VXWORKS_SKIN
bool "VxWorks skin"
help
This option allows to install the VxWorks Xenomai skin
endmenu
endif
| {
"language": "Assembly"
} |
; REQUIRES: asserts
; RUN: opt < %s -mergefunc -stats -disable-output 2>&1 | not grep "functions merged"
define i32 @foo1(i32 %x) {
entry:
%A = add i32 %x, 1
%B = call i32 @foo1(i32 %A)
br label %loop
loop:
%C = phi i32 [%B, %entry], [%D, %loop]
%D = add i32 %x, 2
%E = icmp ugt i32 %D, 10000
br i1 %E, label %loopexit, label %loop
loopexit:
ret i32 %D
}
define i32 @foo2(i32 %x) {
entry:
%0 = add i32 %x, 1
%1 = call i32 @foo2(i32 %0)
br label %loop
loop:
%2 = phi i32 [%1, %entry], [%3, %loop]
%3 = add i32 %2, 2
%4 = icmp ugt i32 %3, 10000
br i1 %4, label %loopexit, label %loop
loopexit:
ret i32 %3
}
| {
"language": "Assembly"
} |
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -indvars -S | FileCheck %s
; RUN: opt < %s -S -passes='lcssa,loop-simplify,require<targetir>,require<scalar-evolution>,require<domtree>,loop(indvars)' | FileCheck %s
; Provide legal integer types.
target datalayout = "n8:16:32:64"
target triple = "x86_64-apple-darwin"
declare void @use(i64 %x)
; Only one phi now.
; One trunc for the gep.
; One trunc for the dummy() call.
define void @loop_0(i32* %a) {
; CHECK-LABEL: @loop_0(
; CHECK-NEXT: Prologue:
; CHECK-NEXT: br i1 undef, label [[B18_PREHEADER:%.*]], label [[B6:%.*]]
; CHECK: B18.preheader:
; CHECK-NEXT: br label [[B18:%.*]]
; CHECK: B18:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[B18_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[B24:%.*]] ]
; CHECK-NEXT: call void @use(i64 [[INDVARS_IV]])
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDVARS_IV]] to i32
; CHECK-NEXT: [[O:%.*]] = getelementptr i32, i32* [[A:%.*]], i32 [[TMP0]]
; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[O]]
; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[V]], 0
; CHECK-NEXT: br i1 [[T]], label [[EXIT24:%.*]], label [[B24]]
; CHECK: B24:
; CHECK-NEXT: [[T2:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 20
; CHECK-NEXT: br i1 [[T2]], label [[B6_LOOPEXIT:%.*]], label [[B18]]
; CHECK: B6.loopexit:
; CHECK-NEXT: br label [[B6]]
; CHECK: B6:
; CHECK-NEXT: ret void
; CHECK: exit24:
; CHECK-NEXT: [[DOT02_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV]], [[B18]] ]
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[DOT02_LCSSA_WIDE]] to i32
; CHECK-NEXT: call void @dummy(i32 [[TMP1]])
; CHECK-NEXT: unreachable
;
Prologue:
br i1 undef, label %B18, label %B6
B18: ; preds = %B24, %Prologue
%.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ]
%tmp23 = zext i32 %.02 to i64
call void @use(i64 %tmp23)
%tmp33 = add i32 %.02, 1
%o = getelementptr i32, i32* %a, i32 %.02
%v = load i32, i32* %o
%t = icmp eq i32 %v, 0
br i1 %t, label %exit24, label %B24
B24: ; preds = %B18
%t2 = icmp eq i32 %tmp33, 20
br i1 %t2, label %B6, label %B18
B6: ; preds = %Prologue
ret void
exit24: ; preds = %B18
call void @dummy(i32 %.02)
unreachable
}
; Make sure that dead zext is removed and no widening happens.
define void @loop_0_dead(i32* %a) {
; CHECK-LABEL: @loop_0_dead(
; CHECK-NEXT: Prologue:
; CHECK-NEXT: br i1 undef, label [[B18_PREHEADER:%.*]], label [[B6:%.*]]
; CHECK: B18.preheader:
; CHECK-NEXT: br label [[B18:%.*]]
; CHECK: B18:
; CHECK-NEXT: [[DOT02:%.*]] = phi i32 [ [[TMP33:%.*]], [[B24:%.*]] ], [ 0, [[B18_PREHEADER]] ]
; CHECK-NEXT: [[TMP33]] = add nuw i32 [[DOT02]], 1
; CHECK-NEXT: [[O:%.*]] = getelementptr i32, i32* [[A:%.*]], i32 [[DOT02]]
; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[O]]
; CHECK-NEXT: [[T:%.*]] = icmp eq i32 [[V]], 0
; CHECK-NEXT: br i1 [[T]], label [[EXIT24:%.*]], label [[B24]]
; CHECK: B24:
; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[TMP33]], 20
; CHECK-NEXT: br i1 [[T2]], label [[B6_LOOPEXIT:%.*]], label [[B18]]
; CHECK: B6.loopexit:
; CHECK-NEXT: br label [[B6]]
; CHECK: B6:
; CHECK-NEXT: ret void
; CHECK: exit24:
; CHECK-NEXT: [[DOT02_LCSSA:%.*]] = phi i32 [ [[DOT02]], [[B18]] ]
; CHECK-NEXT: call void @dummy(i32 [[DOT02_LCSSA]])
; CHECK-NEXT: unreachable
;
Prologue:
br i1 undef, label %B18, label %B6
B18: ; preds = %B24, %Prologue
%.02 = phi i32 [ 0, %Prologue ], [ %tmp33, %B24 ]
%tmp23 = zext i32 %.02 to i64
%tmp33 = add i32 %.02, 1
%o = getelementptr i32, i32* %a, i32 %.02
%v = load i32, i32* %o
%t = icmp eq i32 %v, 0
br i1 %t, label %exit24, label %B24
B24: ; preds = %B18
%t2 = icmp eq i32 %tmp33, 20
br i1 %t2, label %B6, label %B18
B6: ; preds = %Prologue
ret void
exit24: ; preds = %B18
call void @dummy(i32 %.02)
unreachable
}
define void @loop_1(i32 %lim) {
; CHECK-LABEL: @loop_1(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ENTRY_COND:%.*]] = icmp ne i32 [[LIM:%.*]], 0
; CHECK-NEXT: br i1 [[ENTRY_COND]], label [[LOOP_PREHEADER:%.*]], label [[LEAVE:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[LIM]] to i64
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[INDVARS_IV]], -1
; CHECK-NEXT: call void @dummy.i64(i64 [[TMP1]])
; CHECK-NEXT: [[BE_COND:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT]], [[TMP0]]
; CHECK-NEXT: br i1 [[BE_COND]], label [[LOOP]], label [[LEAVE_LOOPEXIT:%.*]]
; CHECK: leave.loopexit:
; CHECK-NEXT: br label [[LEAVE]]
; CHECK: leave:
; CHECK-NEXT: ret void
;
entry:
%entry.cond = icmp ne i32 %lim, 0
br i1 %entry.cond, label %loop, label %leave
loop:
%iv = phi i32 [ 1, %entry ], [ %iv.inc, %loop ]
%iv.inc = add i32 %iv, 1
%iv.inc.sub = add i32 %iv, -1
%iv.inc.sub.zext = zext i32 %iv.inc.sub to i64
call void @dummy.i64(i64 %iv.inc.sub.zext)
%be.cond = icmp ult i32 %iv.inc, %lim
br i1 %be.cond, label %loop, label %leave
leave:
ret void
}
declare void @dummy(i32)
declare void @dummy.i64(i64)
define void @loop_2(i32 %size, i32 %nsteps, i32 %hsize, i32* %lined, i8 %tmp1) {
; CHECK-LABEL: @loop_2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP215:%.*]] = icmp sgt i32 [[SIZE:%.*]], 1
; CHECK-NEXT: [[BC0:%.*]] = bitcast i32* [[LINED:%.*]] to i8*
; CHECK-NEXT: [[TMP0:%.*]] = sext i32 [[SIZE]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[HSIZE:%.*]] to i64
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[NSTEPS:%.*]] to i64
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV7:%.*]] = phi i64 [ [[INDVARS_IV_NEXT8:%.*]], [[FOR_INC:%.*]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: [[TMP3:%.*]] = mul nsw i64 [[INDVARS_IV7]], [[TMP0]]
; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[TMP3]], [[TMP1]]
; CHECK-NEXT: br i1 [[CMP215]], label [[FOR_BODY2_PREHEADER:%.*]], label [[FOR_INC]]
; CHECK: for.body2.preheader:
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[SIZE]] to i64
; CHECK-NEXT: br label [[FOR_BODY2:%.*]]
; CHECK: for.body2:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 1, [[FOR_BODY2_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY2]] ]
; CHECK-NEXT: [[TMP5:%.*]] = add nsw i64 [[TMP4]], [[INDVARS_IV]]
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, i8* [[BC0]], i64 [[TMP5]]
; CHECK-NEXT: store i8 [[TMP1:%.*]], i8* [[ADD_PTR]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY2]], label [[FOR_BODY3_PREHEADER:%.*]]
; CHECK: for.body3.preheader:
; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP4]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
; CHECK-NEXT: [[WIDE_TRIP_COUNT5:%.*]] = zext i32 [[SIZE]] to i64
; CHECK-NEXT: br label [[FOR_BODY3:%.*]]
; CHECK: for.body3:
; CHECK-NEXT: [[INDVARS_IV2:%.*]] = phi i64 [ 1, [[FOR_BODY3_PREHEADER]] ], [ [[INDVARS_IV_NEXT3:%.*]], [[FOR_BODY3]] ]
; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], [[INDVARS_IV2]]
; CHECK-NEXT: [[ADD_PTR2:%.*]] = getelementptr inbounds i8, i8* [[BC0]], i64 [[TMP8]]
; CHECK-NEXT: store i8 [[TMP1]], i8* [[ADD_PTR2]], align 1
; CHECK-NEXT: [[INDVARS_IV_NEXT3]] = add nuw nsw i64 [[INDVARS_IV2]], 1
; CHECK-NEXT: [[EXITCOND6:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT3]], [[WIDE_TRIP_COUNT5]]
; CHECK-NEXT: br i1 [[EXITCOND6]], label [[FOR_BODY3]], label [[FOR_INC_LOOPEXIT:%.*]]
; CHECK: for.inc.loopexit:
; CHECK-NEXT: br label [[FOR_INC]]
; CHECK: for.inc:
; CHECK-NEXT: [[INDVARS_IV_NEXT8]] = add nuw nsw i64 [[INDVARS_IV7]], 1
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT8]], [[TMP2]]
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]]
; CHECK: for.end.loopexit:
; CHECK-NEXT: ret void
;
entry:
%cmp215 = icmp sgt i32 %size, 1
%bc0 = bitcast i32* %lined to i8*
br label %for.body
for.body:
%j = phi i32 [ 0, %entry ], [ %inc6, %for.inc ]
%mul = mul nsw i32 %j, %size
%add = add nsw i32 %mul, %hsize
br i1 %cmp215, label %for.body2, label %for.inc
; check that the induction variable of the inner loop has been widened after indvars.
for.body2:
%k = phi i32 [ %inc, %for.body2 ], [ 1, %for.body ]
%add4 = add nsw i32 %add, %k
%idx.ext = sext i32 %add4 to i64
%add.ptr = getelementptr inbounds i8, i8* %bc0, i64 %idx.ext
store i8 %tmp1, i8* %add.ptr, align 1
%inc = add nsw i32 %k, 1
%cmp2 = icmp slt i32 %inc, %size
br i1 %cmp2, label %for.body2, label %for.body3
; check that the induction variable of the inner loop has been widened after indvars.
for.body3:
%l = phi i32 [ %inc2, %for.body3 ], [ 1, %for.body2 ]
%add5 = add nuw i32 %add, %l
%idx.ext2 = zext i32 %add5 to i64
%add.ptr2 = getelementptr inbounds i8, i8* %bc0, i64 %idx.ext2
store i8 %tmp1, i8* %add.ptr2, align 1
%inc2 = add nsw i32 %l, 1
%cmp3 = icmp slt i32 %inc2, %size
br i1 %cmp3, label %for.body3, label %for.inc
for.inc:
%inc6 = add nsw i32 %j, 1
%cmp = icmp slt i32 %inc6, %nsteps
br i1 %cmp, label %for.body, label %for.end.loopexit
for.end.loopexit:
ret void
}
| {
"language": "Assembly"
} |
/*
* Unlock an object.
*
* Exceptions that occur when unlocking a monitor need to appear as
* if they happened at the following instruction. See the Dalvik
* instruction spec.
*/
/* monitor-exit vAA */
EXPORT_PC()
GET_OPA(a2) # a2 <- AA
GET_VREG(a0, a2) # a0 <- vAA (object)
move a1, rSELF # a1 <- self
JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self)
bnez v0, MterpException
FETCH_ADVANCE_INST(1) # advance rPC, load rINST
GET_INST_OPCODE(t0) # extract opcode from rINST
GOTO_OPCODE(t0) # jump to next instruction
| {
"language": "Assembly"
} |
/*********************************************************************/
/* Copyright 2009, 2010 The University of Texas at Austin. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or */
/* without modification, are permitted provided that the following */
/* conditions are met: */
/* */
/* 1. Redistributions of source code must retain the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer. */
/* */
/* 2. Redistributions in binary form must reproduce the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer in the documentation and/or other materials */
/* provided with the distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
/* POSSIBILITY OF SUCH DAMAGE. */
/* */
/* The views and conclusions contained in the software and */
/* documentation are those of the authors and should not be */
/* interpreted as representing official policies, either expressed */
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/
#define ASSEMBLER
#include "common.h"
#ifdef XDOUBLE
#define PREFETCH_SIZE ( 8 * 16)
#elif defined(DOUBLE)
#define PREFETCH_SIZE (16 * 16)
#else
#define PREFETCH_SIZE (32 * 16)
#endif
#ifndef CONJ
#define FMA1 FNMA
#define FMA2 FMA
#else
#define FMA1 FMA
#define FMA2 FNMA
#endif
#define SP r12
#ifdef XDOUBLE
#define N r32
#define X1 r14
#define INCX r15
#define Y1 r16
#define INCY r17
#else
#define N r32
#define X1 r37
#define INCX r38
#define Y1 r39
#define INCY r36
#endif
#define PREX1 r2
#define PREY1 r3
#define I r18
#define J r19
#define Y2 r20
#define X2 r21
#define INCX8 r22
#define INCY8 r23
#define YY1 r24
#define YY2 r25
#define YY3 r26
#define YY4 r27
#define INCX2M1 loc0
#define INCY2M1 loc1
#define INCX4M1 loc2
#define INCY4M1 loc3
#define X3 loc4
#define Y3 loc5
#define X4 loc6
#define Y4 loc7
#define PREX2 loc8
#define PREY2 loc9
#define ARLC r29
#define PR r30
#define ALPHA_R f8
#define ALPHA_I f9
PROLOGUE
.prologue
PROFCODE
{ .mmi
adds r14 = 16, SP
adds r15 = 24, SP
adds r16 = 32, SP
}
{ .mmb
adds r17 = 40, SP
cmp.gt p15, p0 = r0, N
(p15) br.ret.sptk.many b0
}
;;
#ifdef XDOUBLE
{ .mmi
ld8 X1 = [r14]
ld8 INCX = [r15]
nop __LINE__
}
{ .mmi
ld8 Y1 = [r16]
ld8 INCY = [r17]
nop __LINE__
}
;;
#else
{ .mmi
ld8 INCY = [r14]
nop __LINE__
nop __LINE__
}
;;
#endif
{ .mmi
.save ar.pfs, r10
alloc r10 = ar.pfs, 8, 16, 0, 0
and J = 7, N
shl INCX = INCX, ZBASE_SHIFT
}
{ .mmi
adds PREX1 = (PREFETCH_SIZE + 2) * SIZE, X1
adds PREY1 = (PREFETCH_SIZE + 2) * SIZE, Y1
shl INCY = INCY, ZBASE_SHIFT
}
;;
{ .mmi
shladd INCX8 = INCX, 3, r0
shladd INCY8 = INCY, 3, r0
.save ar.lc, ARLC
mov ARLC = ar.lc
}
{ .mmi
adds INCX2M1 = -SIZE, INCX
adds INCY2M1 = -SIZE, INCY
shr I = N, 3
}
;;
{ .mmi
add INCX2M1 = INCX2M1, INCX
add INCY2M1 = INCY2M1, INCY
mov PR = pr
}
{ .mmi
add X2 = X1, INCX
add Y2 = Y1, INCY
nop __LINE__
}
;;
{ .mmi
shladd INCX4M1 = INCX, 1, INCX2M1
shladd INCY4M1 = INCY, 1, INCY2M1
mov pr.rot= 0
}
{ .mmi
shladd X3 = INCX, 1, X1
shladd Y3 = INCY, 1, Y1
}
;;
{ .mmi
shladd X4 = INCX, 1, X2
shladd Y4 = INCY, 1, Y2
adds I = -1, I
}
{ .mmi
cmp.eq p16, p0 = r0, r0
and r8 = 127, Y1
and PREX1 = -128, PREX1
}
;;
{ .mmi
mov YY1 = Y1
mov YY2 = Y2
mov ar.ec = 3
}
{ .mmi
mov YY3 = Y3
mov YY4 = Y4
or PREX1 = PREX1, r8
}
;;
{ .mmi
shladd PREX2 = INCX, 2, PREX1
shladd PREY2 = INCY, 2, PREY1
mov ar.lc = I
}
{ .mib
cmp.eq p11 ,p0 = -1, I
tbit.z p0, p13 = N, 2
(p11) br.cond.dpnt .L25
}
;;
.align 32
.L22:
#ifdef XDOUBLE
{ .mmf
(p16) LDFD f80 = [Y1], 1 * SIZE
(p16) LDFD f83 = [Y2], 1 * SIZE
(p18) FMA1 f82 = ALPHA_I, f40, f82
}
{ .mmf
(p16) LDFD f92 = [Y3], 1 * SIZE
(p16) LDFD f95 = [Y4], 1 * SIZE
(p18) FMA1 f85 = ALPHA_I, f43, f85
}
;;
{ .mmf
(p16) LDFD f86 = [Y1], INCY4M1
(p16) LDFD f89 = [Y2], INCY4M1
(p18) FMA1 f94 = ALPHA_I, f52, f94
}
{ .mmf
(p16) LDFD f98 = [Y3], INCY4M1
(p16) LDFD f101 = [Y4], INCY4M1
(p18) FMA1 f97 = ALPHA_I, f55, f97
}
;;
{ .mmf
(p16) LDFD f32 = [X1], 1 * SIZE
(p16) LDFD f35 = [X2], 1 * SIZE
(p18) FMA f88 = ALPHA_I, f34, f88
}
{ .mmf
(p16) LDFD f44 = [X3], 1 * SIZE
(p16) LDFD f47 = [X4], 1 * SIZE
(p18) FMA f91 = ALPHA_I, f37, f91
}
;;
{ .mmf
(p16) LDFD f38 = [X1], INCX4M1
(p16) LDFD f41 = [X2], INCX4M1
(p18) FMA f100 = ALPHA_I, f46, f100
}
{ .mmf
(p16) LDFD f50 = [X3], INCX4M1
(p16) LDFD f53 = [X4], INCX4M1
(p18) FMA f103 = ALPHA_I, f49, f103
}
;;
{ .mmf
(p18) STFD [YY1] = f82, 1 * SIZE
(p18) STFD [YY2] = f85, 1 * SIZE
(p18) FMA f106 = ALPHA_R, f58, f106
}
{ .mmf
(p19) add YY3 = YY3, INCY4M1
(p19) add YY4 = YY4, INCY4M1
(p18) FMA f109 = ALPHA_R, f61, f109
}
;;
{ .mmf
(p18) STFD [YY3] = f94, 1 * SIZE
(p18) STFD [YY4] = f97, 1 * SIZE
(p18) FMA f118 = ALPHA_R, f70, f118
}
{ .mmf
(p16) lfetch.excl.nt1 [PREY1], INCY8
(p16) lfetch.excl.nt1 [PREY2], INCY8
(p18) FMA f121 = ALPHA_R, f73, f121
}
;;
{ .mmf
(p18) STFD [YY1] = f88
(p18) STFD [YY2] = f91
(p18) FMA2 f112 = ALPHA_R, f64, f112
}
{ .mmf
(p18) add YY1 = YY1, INCY4M1
(p18) add YY2 = YY2, INCY4M1
(p18) FMA2 f115 = ALPHA_R, f67, f115
}
;;
{ .mmf
(p18) STFD [YY3] = f100
(p18) STFD [YY4] = f103
(p18) FMA2 f124 = ALPHA_R, f76, f124
}
{ .mmf
(p18) add YY3 = YY3, INCY4M1
(p18) add YY4 = YY4, INCY4M1
(p18) FMA2 f127 = ALPHA_R, f79, f127
}
;;
{ .mmf
(p16) LDFD f104 = [Y1], 1 * SIZE
(p16) LDFD f107 = [Y2], 1 * SIZE
(p18) FMA1 f106 = ALPHA_I, f64, f106
}
{ .mmf
(p16) LDFD f116 = [Y3], 1 * SIZE
(p16) LDFD f119 = [Y4], 1 * SIZE
(p18) FMA1 f109 = ALPHA_I, f67, f109
}
;;
{ .mmf
(p16) LDFD f110 = [Y1], INCY4M1
(p16) LDFD f113 = [Y2], INCY4M1
(p18) FMA1 f118 = ALPHA_I, f76, f118
}
{ .mmf
(p16) LDFD f122 = [Y3], INCY4M1
(p16) LDFD f125 = [Y4], INCY4M1
(p18) FMA1 f121 = ALPHA_I, f79, f121
}
;;
{ .mmf
(p16) LDFD f56 = [X1], 1 * SIZE
(p16) LDFD f59 = [X2], 1 * SIZE
(p18) FMA f112 = ALPHA_I, f58, f112
}
{ .mmf
(p16) LDFD f68 = [X3], 1 * SIZE
(p16) LDFD f71 = [X4], 1 * SIZE
(p18) FMA f115 = ALPHA_I, f61, f115
}
;;
{ .mmf
(p16) LDFD f62 = [X1], INCX4M1
(p16) LDFD f65 = [X2], INCX4M1
(p18) FMA f124 = ALPHA_I, f70, f124
}
{ .mmf
(p16) LDFD f74 = [X3], INCX4M1
(p16) LDFD f77 = [X4], INCX4M1
(p18) FMA f127 = ALPHA_I, f73, f127
}
;;
{ .mmf
(p18) STFD [YY1] = f106, 1 * SIZE
(p18) STFD [YY2] = f109, 1 * SIZE
(p17) FMA f81 = ALPHA_R, f33, f81
}
{ .mmf
nop __LINE__
nop __LINE__
(p17) FMA f84 = ALPHA_R, f36, f84
}
;;
{ .mmf
(p18) STFD [YY3] = f118, 1 * SIZE
(p18) STFD [YY4] = f121, 1 * SIZE
(p17) FMA f93 = ALPHA_R, f45, f93
}
{ .mmf
(p16) lfetch.nt1 [PREX1], INCX8
(p16) lfetch.nt1 [PREX2], INCX8
(p17) FMA f96 = ALPHA_R, f48, f96
}
;;
{ .mmf
(p18) STFD [YY1] = f112
(p18) STFD [YY2] = f115
(p17) FMA2 f87 = ALPHA_R, f39, f87
}
{ .mmf
(p18) add YY1 = YY1, INCY4M1
(p18) add YY2 = YY2, INCY4M1
(p17) FMA2 f90 = ALPHA_R, f42, f90
}
;;
{ .mmf
(p18) STFD [YY3] = f124
(p18) STFD [YY4] = f127
(p17) FMA2 f99 = ALPHA_R, f51, f99
}
{ .mfb
nop __LINE__
(p17) FMA2 f102 = ALPHA_R, f54, f102
br.ctop.sptk.few .L22
}
;;
;;
(p19) add YY3 = YY3, INCY4M1
(p19) add YY4 = YY4, INCY4M1
;;
#else
{ .mmf
(p19) STFD [YY3] = f125
(p19) STFD [YY4] = f32
(p18) FMA2 f100 = ALPHA_R, f52, f100
}
{ .mmf
(p16) lfetch.excl.nt1 [PREY1], INCY8
nop __LINE__
(p18) FMA2 f103 = ALPHA_R, f55, f103
}
;;
{ .mmf
(p16) LDFD f80 = [Y1], 1 * SIZE
(p16) LDFD f83 = [Y2], 1 * SIZE
(p18) FMA1 f82 = ALPHA_I, f40, f82
}
{ .mmf
(p16) LDFD f92 = [Y3], 1 * SIZE
(p16) LDFD f95 = [Y4], 1 * SIZE
(p18) FMA1 f85 = ALPHA_I, f43, f85
}
;;
{ .mmf
(p16) LDFD f86 = [Y1], INCY4M1
(p16) LDFD f89 = [Y2], INCY4M1
(p18) FMA1 f94 = ALPHA_I, f52, f94
}
{ .mmf
(p19) add YY3 = YY3, INCY4M1
(p19) add YY4 = YY4, INCY4M1
(p18) FMA1 f97 = ALPHA_I, f55, f97
}
;;
{ .mmf
(p16) LDFD f98 = [Y3], INCY4M1
(p16) LDFD f101 = [Y4], INCY4M1
(p18) FMA f88 = ALPHA_I, f34, f88
}
{ .mmf
(p19) add YY1 = YY1, INCY4M1
(p19) add YY2 = YY2, INCY4M1
(p18) FMA f91 = ALPHA_I, f37, f91
}
;;
{ .mmf
(p16) LDFD f32 = [X1], 1 * SIZE
(p16) LDFD f35 = [X2], 1 * SIZE
(p18) FMA f100 = ALPHA_I, f46, f100
}
{ .mmf
(p16) LDFD f44 = [X3], 1 * SIZE
(p16) LDFD f47 = [X4], 1 * SIZE
(p18) FMA f103 = ALPHA_I, f49, f103
}
;;
{ .mmf
(p18) STFD [YY1] = f82, 1 * SIZE
(p18) STFD [YY2] = f85, 1 * SIZE
(p18) FMA f106 = ALPHA_R, f58, f106
}
{ .mmf
(p16) LDFD f38 = [X1], INCX4M1
(p16) LDFD f41 = [X2], INCX4M1
(p18) FMA f109 = ALPHA_R, f61, f109
}
;;
{ .mmf
(p18) STFD [YY3] = f94, 1 * SIZE
(p18) STFD [YY4] = f97, 1 * SIZE
(p18) FMA f118 = ALPHA_R, f70, f118
}
{ .mmf
(p16) LDFD f50 = [X3], INCX4M1
(p16) LDFD f53 = [X4], INCX4M1
(p18) FMA f121 = ALPHA_R, f73, f121
}
;;
{ .mmf
(p18) STFD [YY1] = f88
(p18) STFD [YY2] = f91
(p18) FMA2 f112 = ALPHA_R, f64, f112
}
{ .mmf
(p16) lfetch.nt1 [PREX1], INCX8
nop __LINE__
(p18) FMA2 f115 = ALPHA_R, f67, f115
}
;;
{ .mmf
(p18) STFD [YY3] = f100
(p18) STFD [YY4] = f103
(p18) FMA2 f124 = ALPHA_R, f76, f124
}
{ .mmf
(p16) LDFD f104 = [Y1], 1 * SIZE
(p16) LDFD f107 = [Y2], 1 * SIZE
(p18) FMA2 f127 = ALPHA_R, f79, f127
}
;;
{ .mmf
(p16) LDFD f116 = [Y3], 1 * SIZE
(p16) LDFD f119 = [Y4], 1 * SIZE
(p18) FMA1 f106 = ALPHA_I, f64, f106
}
{ .mmf
(p18) add YY1 = YY1, INCY4M1
(p18) add YY2 = YY2, INCY4M1
(p18) FMA1 f109 = ALPHA_I, f67, f109
}
;;
{ .mmf
(p16) LDFD f110 = [Y1], INCY4M1
(p16) LDFD f113 = [Y2], INCY4M1
(p18) FMA1 f118 = ALPHA_I, f76, f118
}
{ .mmf
(p18) add YY3 = YY3, INCY4M1
(p18) add YY4 = YY4, INCY4M1
(p18) FMA1 f121 = ALPHA_I, f79, f121
}
;;
{ .mmf
(p16) LDFD f122 = [Y3], INCY4M1
(p16) LDFD f125 = [Y4], INCY4M1
(p18) FMA f112 = ALPHA_I, f58, f112
}
{ .mmf
nop __LINE__
nop __LINE__
(p18) FMA f115 = ALPHA_I, f61, f115
}
;;
{ .mmf
(p16) LDFD f56 = [X1], 1 * SIZE
(p16) LDFD f59 = [X2], 1 * SIZE
(p18) FMA f124 = ALPHA_I, f70, f124
}
{ .mmf
(p16) LDFD f68 = [X3], 1 * SIZE
(p16) LDFD f71 = [X4], 1 * SIZE
(p18) FMA f127 = ALPHA_I, f73, f127
}
;;
{ .mmf
(p18) STFD [YY1] = f106, 1 * SIZE
(p18) STFD [YY2] = f109, 1 * SIZE
(p17) FMA f81 = ALPHA_R, f33, f81
}
{ .mmf
(p16) LDFD f62 = [X1], INCX4M1
(p16) LDFD f65 = [X2], INCX4M1
(p17) FMA f84 = ALPHA_R, f36, f84
}
;;
{ .mmf
(p18) STFD [YY3] = f118, 1 * SIZE
(p18) STFD [YY4] = f121, 1 * SIZE
(p17) FMA f93 = ALPHA_R, f45, f93
}
{ .mmf
(p16) LDFD f74 = [X3], INCX4M1
(p16) LDFD f77 = [X4], INCX4M1
(p17) FMA f96 = ALPHA_R, f48, f96
}
;;
{ .mmf
(p18) STFD [YY1] = f112
(p18) STFD [YY2] = f115
(p17) FMA2 f87 = ALPHA_R, f39, f87
}
{ .mfb
nop __LINE__
(p17) FMA2 f90 = ALPHA_R, f42, f90
br.ctop.sptk.few .L22
}
;;
{ .mmi
(p19) STFD [YY3] = f125
(p19) STFD [YY4] = f32
(p19) add YY1 = YY1, INCY4M1
}
{ .mmi
(p19) add YY2 = YY2, INCY4M1
(p19) add YY3 = YY3, INCY4M1
(p19) add YY4 = YY4, INCY4M1
}
;;
#endif
.align 32
.L25:
{ .mmi
(p13) LDFD f32 = [X1], 1 * SIZE
(p13) LDFD f34 = [X2], 1 * SIZE
mov ar.lc = ARLC
}
{ .mmi
(p13) LDFD f36 = [X3], 1 * SIZE
(p13) LDFD f38 = [X4], 1 * SIZE
cmp.eq p12, p0 = r0, J
}
;;
{ .mmi
(p13) LDFD f80 = [Y1], 1 * SIZE
(p13) LDFD f82 = [Y2], 1 * SIZE
mov pr = PR, -65474
}
{ .mmb
(p13) LDFD f84 = [Y3], 1 * SIZE
(p13) LDFD f86 = [Y4], 1 * SIZE
(p12) br.ret.sptk.many b0
}
;;
{ .mmi
(p13) LDFD f33 = [X1], INCX4M1
(p13) LDFD f35 = [X2], INCX4M1
tbit.z p0, p14 = N, 1
}
{ .mmi
(p13) LDFD f81 = [Y1], INCY4M1
(p13) LDFD f83 = [Y2], INCY4M1
nop __LINE__
}
;;
{ .mmi
(p13) LDFD f37 = [X3], INCX4M1
(p13) LDFD f39 = [X4], INCX4M1
tbit.z p0, p15 = N, 0
}
{ .mmi
(p13) LDFD f85 = [Y3], INCY4M1
(p13) LDFD f87 = [Y4], INCY4M1
nop __LINE__
}
;;
{ .mmf
(p14) LDFD f40 = [X1], 1 * SIZE
(p14) LDFD f42 = [X2], 1 * SIZE
}
;;
{ .mmf
(p14) LDFD f88 = [Y1], 1 * SIZE
(p14) LDFD f90 = [Y2], 1 * SIZE
}
;;
{ .mmf
(p14) LDFD f41 = [X1], INCX2M1
(p14) LDFD f43 = [X2], INCX2M1
(p13) FMA f80 = ALPHA_R, f32, f80
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f82 = ALPHA_R, f34, f82
}
;;
{ .mmf
(p14) LDFD f89 = [Y1], INCY2M1
(p14) LDFD f91 = [Y2], INCY2M1
(p13) FMA f84 = ALPHA_R, f36, f84
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f86 = ALPHA_R, f38, f86
}
;;
{ .mmf
(p15) LDFD f44 = [X1], 1 * SIZE
(p15) LDFD f92 = [Y1], 1 * SIZE
(p13) FMA2 f81 = ALPHA_R, f33, f81
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA2 f83 = ALPHA_R, f35, f83
}
;;
{ .mmf
(p15) LDFD f45 = [X1]
(p15) LDFD f93 = [Y1]
(p13) FMA2 f85 = ALPHA_R, f37, f85
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA2 f87 = ALPHA_R, f39, f87
}
;;
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA1 f80 = ALPHA_I, f33, f80
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA1 f82 = ALPHA_I, f35, f82
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA1 f84 = ALPHA_I, f37, f84
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA1 f86 = ALPHA_I, f39, f86
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f81 = ALPHA_I, f32, f81
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f83 = ALPHA_I, f34, f83
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f85 = ALPHA_I, f36, f85
}
{ .mmf
nop __LINE__
nop __LINE__
(p13) FMA f87 = ALPHA_I, f38, f87
}
;;
{ .mmf
(p13) STFD [YY1] = f80, 1 * SIZE
(p13) STFD [YY2] = f82, 1 * SIZE
(p14) FMA f88 = ALPHA_R, f40, f88
}
{ .mmf
nop __LINE__
nop __LINE__
(p14) FMA f90 = ALPHA_R, f42, f90
}
;;
{ .mmf
(p13) STFD [YY3] = f84, 1 * SIZE
(p13) STFD [YY4] = f86, 1 * SIZE
(p14) FMA2 f89 = ALPHA_R, f41, f89
}
{ .mmf
nop __LINE__
nop __LINE__
(p14) FMA2 f91 = ALPHA_R, f43, f91
}
;;
{ .mmf
(p13) STFD [YY1] = f81
(p13) STFD [YY2] = f83
(p15) FMA f92 = ALPHA_R, f44, f92
}
{ .mmf
(p13) add YY1 = YY1, INCY4M1
(p13) add YY2 = YY2, INCY4M1
(p15) FMA2 f93 = ALPHA_R, f45, f93
}
;;
{ .mmf
(p13) STFD [YY3] = f85
(p13) STFD [YY4] = f87
(p14) FMA1 f88 = ALPHA_I, f41, f88
}
{ .mmf
(p13) add YY3 = YY3, INCY4M1
(p13) add YY4 = YY4, INCY4M1
(p14) FMA1 f90 = ALPHA_I, f43, f90
}
;;
{ .mmf
nop __LINE__
nop __LINE__
(p14) FMA f89 = ALPHA_I, f40, f89
}
{ .mmf
nop __LINE__
nop __LINE__
(p14) FMA f91 = ALPHA_I, f42, f91
}
{ .mmf
nop __LINE__
nop __LINE__
(p15) FMA1 f92 = ALPHA_I, f45, f92
}
{ .mmf
nop __LINE__
nop __LINE__
(p15) FMA f93 = ALPHA_I, f44, f93
}
;;
{ .mmi
(p14) STFD [YY1] = f88, 1 * SIZE
(p14) STFD [YY2] = f90, 1 * SIZE
nop __LINE__
}
;;
{ .mmi
(p14) STFD [YY1] = f89
(p14) STFD [YY2] = f91
(p14) add YY1 = YY1, INCY2M1
}
;;
{ .mmi
(p15) STFD [YY1] = f92, 1 * SIZE
nop __LINE__
nop __LINE__
}
;;
{ .mmb
(p15) STFD [YY1] = f93
nop __LINE__
br.ret.sptk.many b0
}
;;
EPILOGUE
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple %itanium_abi_triple -emit-llvm %s -o - | FileCheck %s
template <class T> struct A { A(); };
struct B { A<int> x; };
void a() {
B b;
}
// CHECK: call {{.*}} @_ZN1BC1Ev
// CHECK: define linkonce_odr {{.*}} @_ZN1BC1Ev(%struct.B* {{.*}}%this) unnamed_addr
// CHECK: call {{.*}} @_ZN1AIiEC1Ev
| {
"language": "Assembly"
} |
// Copyright 2009 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for AMD64, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-56
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-80
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-104
JMP syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-56
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-80
JMP syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -triple i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s
// PR8864
struct Foo {
friend bool TryFoo(Foo *f2) { return TryFoo(0, f2); }
// CHECK: define{{.*}}Z6TryFooP3Foo
// CHECK-NOT: ret
// CHECK: call{{.*}}Z6TryFooiP3Foo
// CHECK: ret
friend bool TryFoo(int, Foo *f3);
};
bool TryFoo(Foo *f5);
int main(void) {
Foo f;
TryFoo(&f);
}
| {
"language": "Assembly"
} |
// RUN: flatbuffer_translate -mlir-to-tflite-flatbuffer %s -o - | flatbuffer_to_string - | FileCheck %s
func @main(tensor<1x6x6x16xf32>) -> tensor<1x1x1x16xf32> {
^bb0(%arg0: tensor<1x6x6x16xf32>):
// CHECK: {
// CHECK-NEXT: version: 3,
// CHECK-NEXT: operator_codes: [ {
// CHECK-NEXT: builtin_code: AVERAGE_POOL_2D,
// CHECK-NEXT: version: 1
// CHECK-NEXT: } ],
// CHECK-NEXT: subgraphs: [ {
// CHECK-NEXT: tensors: [ {
// CHECK-NEXT: shape: [ 1, 6, 6, 16 ],
// CHECK-NEXT: buffer: 1,
// CHECK-NEXT: name: "arg0",
// CHECK-NEXT: quantization: {
// CHECK-EMPTY:
// CHECK-NEXT: }
// CHECK-NEXT: }, {
// CHECK-NEXT: shape: [ 1, 1, 1, 16 ],
// CHECK-NEXT: buffer: 2,
// CHECK-NEXT: name: "avgpool",
// CHECK-NEXT: quantization: {
// CHECK-EMPTY:
// CHECK-NEXT: }
// CHECK-NEXT: } ],
// CHECK-NEXT: inputs: [ 0 ],
// CHECK-NEXT: outputs: [ 1 ],
// CHECK-NEXT: operators: [ {
// CHECK-NEXT: inputs: [ 0 ],
// CHECK-NEXT: outputs: [ 1 ],
// CHECK-NEXT: builtin_options_type: Pool2DOptions,
// CHECK-NEXT: builtin_options: {
// CHECK-NEXT: padding: VALID,
// CHECK-NEXT: stride_w: 1,
// CHECK-NEXT: stride_h: 3,
// CHECK-NEXT: filter_width: 6,
// CHECK-NEXT: filter_height: 3
// CHECK-NEXT: }
// CHECK-NEXT: } ]
// CHECK-NEXT: name: "main"
// CHECK-NEXT: } ],
// CHECK-NEXT: description: "MLIR Converted.",
// CHECK-NEXT: buffers: [ {
// CHECK-EMPTY:
// CHECK-NEXT: }, {
// CHECK-EMPTY:
// CHECK-NEXT: }, {
// CHECK-EMPTY:
// CHECK-NEXT: }, {
// CHECK-NEXT: data: [ 49, 46, 53, 46, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ]
// CHECK-NEXT: } ],
// CHECK-NEXT: metadata: [ {
// CHECK-NEXT: name: "min_runtime_version",
// CHECK-NEXT: buffer: 3
// CHECK-NEXT: } ]
// CHECK-NEXT: }
%0 = "tfl.average_pool_2d"(%arg0) {filter_height = 3 : i32, filter_width = 6 : i32, fused_activation_function = "NONE", padding = "VALID", stride_h = 3 : i32, stride_w = 1 : i32} : (tensor<1x6x6x16xf32>) -> tensor<1x1x1x16xf32> loc("avgpool")
return %0 : tensor<1x1x1x16xf32>
}
| {
"language": "Assembly"
} |
; RUN: opt < %s -loop-extract -disable-output
; This testcase is failing the loop extractor because not all exit blocks
; are dominated by all of the live-outs.
define i32 @ab(i32 %alpha, i32 %beta) {
entry:
br label %loopentry.1.preheader
loopentry.1.preheader: ; preds = %entry
br label %loopentry.1
loopentry.1: ; preds = %no_exit.1, %loopentry.1.preheader
br i1 false, label %no_exit.1, label %loopexit.0.loopexit1
no_exit.1: ; preds = %loopentry.1
%tmp.53 = load i32, i32* null ; <i32> [#uses=1]
br i1 false, label %shortcirc_next.2, label %loopentry.1
shortcirc_next.2: ; preds = %no_exit.1
%tmp.563 = call i32 @wins( i32 0, i32 %tmp.53, i32 3 ) ; <i32> [#uses=0]
ret i32 0
loopexit.0.loopexit1: ; preds = %loopentry.1
br label %loopexit.0
loopexit.0: ; preds = %loopexit.0.loopexit1
ret i32 0
}
declare i32 @wins(i32, i32, i32)
declare i16 @ab_code()
| {
"language": "Assembly"
} |
; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
; RUN: grep lxvd2x < %t | count 18
; RUN: grep stxvd2x < %t | count 18
; RUN: grep xxpermdi < %t | count 36
@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16
@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@vsll = global <2 x i64> <i64 255, i64 -937>, align 16
@vull = global <2 x i64> <i64 1447, i64 2894>, align 16
@res_vsi = common global <4 x i32> zeroinitializer, align 16
@res_vui = common global <4 x i32> zeroinitializer, align 16
@res_vf = common global <4 x float> zeroinitializer, align 16
@res_vsll = common global <2 x i64> zeroinitializer, align 16
@res_vull = common global <2 x i64> zeroinitializer, align 16
@res_vd = common global <2 x double> zeroinitializer, align 16
define void @test1() {
entry:
; CHECK-LABEL: test1
%__a.addr.i31 = alloca i32, align 4
%__b.addr.i32 = alloca <4 x i32>*, align 8
%__a.addr.i29 = alloca i32, align 4
%__b.addr.i30 = alloca <4 x float>*, align 8
%__a.addr.i27 = alloca i32, align 4
%__b.addr.i28 = alloca <2 x i64>*, align 8
%__a.addr.i25 = alloca i32, align 4
%__b.addr.i26 = alloca <2 x i64>*, align 8
%__a.addr.i23 = alloca i32, align 4
%__b.addr.i24 = alloca <2 x double>*, align 8
%__a.addr.i20 = alloca <4 x i32>, align 16
%__b.addr.i21 = alloca i32, align 4
%__c.addr.i22 = alloca <4 x i32>*, align 8
%__a.addr.i17 = alloca <4 x i32>, align 16
%__b.addr.i18 = alloca i32, align 4
%__c.addr.i19 = alloca <4 x i32>*, align 8
%__a.addr.i14 = alloca <4 x float>, align 16
%__b.addr.i15 = alloca i32, align 4
%__c.addr.i16 = alloca <4 x float>*, align 8
%__a.addr.i11 = alloca <2 x i64>, align 16
%__b.addr.i12 = alloca i32, align 4
%__c.addr.i13 = alloca <2 x i64>*, align 8
%__a.addr.i8 = alloca <2 x i64>, align 16
%__b.addr.i9 = alloca i32, align 4
%__c.addr.i10 = alloca <2 x i64>*, align 8
%__a.addr.i6 = alloca <2 x double>, align 16
%__b.addr.i7 = alloca i32, align 4
%__c.addr.i = alloca <2 x double>*, align 8
%__a.addr.i = alloca i32, align 4
%__b.addr.i = alloca <4 x i32>*, align 8
store i32 0, i32* %__a.addr.i, align 4
store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8
%0 = load i32* %__a.addr.i, align 4
%1 = load <4 x i32>** %__b.addr.i, align 8
%2 = bitcast <4 x i32>* %1 to i8*
%3 = getelementptr i8* %2, i32 %0
%4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
store <4 x i32> %4, <4 x i32>* @res_vsi, align 16
store i32 0, i32* %__a.addr.i31, align 4
store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8
%5 = load i32* %__a.addr.i31, align 4
%6 = load <4 x i32>** %__b.addr.i32, align 8
%7 = bitcast <4 x i32>* %6 to i8*
%8 = getelementptr i8* %7, i32 %5
%9 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %8)
store <4 x i32> %9, <4 x i32>* @res_vui, align 16
store i32 0, i32* %__a.addr.i29, align 4
store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8
%10 = load i32* %__a.addr.i29, align 4
%11 = load <4 x float>** %__b.addr.i30, align 8
%12 = bitcast <4 x float>* %11 to i8*
%13 = getelementptr i8* %12, i32 %10
%14 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %13)
%15 = bitcast <4 x i32> %14 to <4 x float>
store <4 x float> %15, <4 x float>* @res_vf, align 16
store i32 0, i32* %__a.addr.i27, align 4
store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8
%16 = load i32* %__a.addr.i27, align 4
%17 = load <2 x i64>** %__b.addr.i28, align 8
%18 = bitcast <2 x i64>* %17 to i8*
%19 = getelementptr i8* %18, i32 %16
%20 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %19)
%21 = bitcast <2 x double> %20 to <2 x i64>
store <2 x i64> %21, <2 x i64>* @res_vsll, align 16
store i32 0, i32* %__a.addr.i25, align 4
store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8
%22 = load i32* %__a.addr.i25, align 4
%23 = load <2 x i64>** %__b.addr.i26, align 8
%24 = bitcast <2 x i64>* %23 to i8*
%25 = getelementptr i8* %24, i32 %22
%26 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %25)
%27 = bitcast <2 x double> %26 to <2 x i64>
store <2 x i64> %27, <2 x i64>* @res_vull, align 16
store i32 0, i32* %__a.addr.i23, align 4
store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8
%28 = load i32* %__a.addr.i23, align 4
%29 = load <2 x double>** %__b.addr.i24, align 8
%30 = bitcast <2 x double>* %29 to i8*
%31 = getelementptr i8* %30, i32 %28
%32 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %31)
store <2 x double> %32, <2 x double>* @res_vd, align 16
%33 = load <4 x i32>* @vsi, align 16
store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16
store i32 0, i32* %__b.addr.i21, align 4
store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8
%34 = load <4 x i32>* %__a.addr.i20, align 16
%35 = load i32* %__b.addr.i21, align 4
%36 = load <4 x i32>** %__c.addr.i22, align 8
%37 = bitcast <4 x i32>* %36 to i8*
%38 = getelementptr i8* %37, i32 %35
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %34, i8* %38)
%39 = load <4 x i32>* @vui, align 16
store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16
store i32 0, i32* %__b.addr.i18, align 4
store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8
%40 = load <4 x i32>* %__a.addr.i17, align 16
%41 = load i32* %__b.addr.i18, align 4
%42 = load <4 x i32>** %__c.addr.i19, align 8
%43 = bitcast <4 x i32>* %42 to i8*
%44 = getelementptr i8* %43, i32 %41
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %40, i8* %44)
%45 = load <4 x float>* @vf, align 16
store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16
store i32 0, i32* %__b.addr.i15, align 4
store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8
%46 = load <4 x float>* %__a.addr.i14, align 16
%47 = bitcast <4 x float> %46 to <4 x i32>
%48 = load i32* %__b.addr.i15, align 4
%49 = load <4 x float>** %__c.addr.i16, align 8
%50 = bitcast <4 x float>* %49 to i8*
%51 = getelementptr i8* %50, i32 %48
call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %47, i8* %51) #1
%52 = load <2 x i64>* @vsll, align 16
store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16
store i32 0, i32* %__b.addr.i12, align 4
store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8
%53 = load <2 x i64>* %__a.addr.i11, align 16
%54 = bitcast <2 x i64> %53 to <2 x double>
%55 = load i32* %__b.addr.i12, align 4
%56 = load <2 x i64>** %__c.addr.i13, align 8
%57 = bitcast <2 x i64>* %56 to i8*
%58 = getelementptr i8* %57, i32 %55
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %54, i8* %58)
%59 = load <2 x i64>* @vull, align 16
store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16
store i32 0, i32* %__b.addr.i9, align 4
store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8
%60 = load <2 x i64>* %__a.addr.i8, align 16
%61 = bitcast <2 x i64> %60 to <2 x double>
%62 = load i32* %__b.addr.i9, align 4
%63 = load <2 x i64>** %__c.addr.i10, align 8
%64 = bitcast <2 x i64>* %63 to i8*
%65 = getelementptr i8* %64, i32 %62
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %61, i8* %65)
%66 = load <2 x double>* @vd, align 16
store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16
store i32 0, i32* %__b.addr.i7, align 4
store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8
%67 = load <2 x double>* %__a.addr.i6, align 16
%68 = load i32* %__b.addr.i7, align 4
%69 = load <2 x double>** %__c.addr.i, align 8
%70 = bitcast <2 x double>* %69 to i8*
%71 = getelementptr i8* %70, i32 %68
call void @llvm.ppc.vsx.stxvd2x(<2 x double> %67, i8* %71)
ret void
}
declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*)
declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*)
declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*)
declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*)
| {
"language": "Assembly"
} |
//
// MNNNV21ToRGBAUnit.S
// MNN
//
// Created by MNN on 2018/12/28.
// Copyright © 2018, Alibaba Group Holding Limited
//
#ifdef __arm__
#ifndef __aarch64__
#include "MNNAsmGlobal.h"
.text
.align 5
//void MNNNV21ToRGBAUnit(const unsigned char* source, unsigned char* dest, size_t count, const unsigned char* uv);
//Auto: r0:source, r1:dest, r2:count, r3:uv
asm_function MNNNV21ToRGBAUnit
push {r4, lr}
vpush {q4}
mov r4, #73
vmov.i8 d31, #128
mov r12, #25
vmov.i16 d0[0], r4
vmov.i16 d0[1], r12
mov r4, #37
mov r12, #130
vmov.i16 d0[2], r4
vmov.i16 d0[3], r12
vmov.i16 q4, #0
LoopL1:
vld2.8 {d18, d19}, [r3]!
vsubl.u8 q11, d18, d31
vld2.8 {d16, d17}, [r0]!
vsubl.u8 q10, d19, d31
//q1-q3: RGB offset
vmul.s16 q1, q11, d0[0]// + R Offset
vmul.s16 q2, q10, d0[1]
vmul.s16 q3, q10, d0[3]// + B Offset
vmla.s16 q2, q11, d0[2]// - G Offset
vshll.u8 q10, d16, #6
vshll.u8 q11, d17, #6
vadd.s16 q12, q10, q1
vsub.s16 q13, q10, q2
vadd.s16 q14, q10, q3
vmax.s16 q12, q12, q4
vmax.s16 q13, q13, q4
vmax.s16 q14, q14, q4
vqshrn.u16 d16, q12, #6
vqshrn.u16 d17, q13, #6
vqshrn.u16 d18, q14, #6
vadd.s16 q12, q11, q1
vsub.s16 q13, q11, q2
vadd.s16 q14, q11, q3
vmax.s16 q12, q12, q4
vmax.s16 q13, q13, q4
vmax.s16 q14, q14, q4
vqshrn.u16 d20, q12, #6
vqshrn.u16 d21, q13, #6
vqshrn.u16 d22, q14, #6
vzip.8 d16, d20
vmov.i8 d19, #255
vzip.8 d17, d21
vzip.8 d18, d22
vmov.i8 d23, #255
vst4.u8 {d16, d17, d18, d19}, [r1]!
vst4.u8 {d20, d21, d22, d23}, [r1]!
subs r2, r2, #1
bne LoopL1
vpop {q4}
pop {r4, pc}
#endif
#endif
| {
"language": "Assembly"
} |
// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -show-encoding %s | llvm-readobj -s -sd | FileCheck %s --check-prefix=ELF
// For compatibility reasons we treat convert .text sections to .hsatext
// ELF: Section {
// ELF: Name: .text
// ELF: Type: SHT_PROGBITS (0x1)
// ELF: Flags [ (0x6)
// ELF: SHF_ALLOC (0x2)
// ELF: SHF_EXECINSTR (0x4)
// ELF: Size: 260
// ELF: }
.text
// ASM: .text
.hsa_code_object_version 1,0
// ASM: .hsa_code_object_version 1,0
.hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
// ASM: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
.amd_kernel_code_t
.end_amd_kernel_code_t
s_endpgm
| {
"language": "Assembly"
} |
// Copyright ©2017 The Gonum Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
//+build !noasm,!appengine,!safe
#include "textflag.h"
#define SRC SI
#define DST SI
#define LEN CX
#define IDX AX
#define TAIL BX
#define ALPHA X0
#define ALPHA_2 X1
#define MOVDDUP_ALPHA LONG $0x44120FF2; WORD $0x0824 // MOVDDUP 8(SP), X0
// func DscalUnitary(alpha float64, x []complex128)
TEXT ·DscalUnitary(SB), NOSPLIT, $0
MOVQ x_base+8(FP), SRC // SRC = &x
MOVQ x_len+16(FP), LEN // LEN = len(x)
CMPQ LEN, $0 // if LEN == 0 { return }
JE dscal_end
MOVDDUP_ALPHA // ALPHA = alpha
XORQ IDX, IDX // IDX = 0
MOVUPS ALPHA, ALPHA_2 // Copy ALPHA to ALPHA_2 for pipelining
MOVQ LEN, TAIL // TAIL = LEN
SHRQ $2, LEN // LEN = floor( n / 4 )
JZ dscal_tail // if LEN == 0 { goto dscal_tail }
dscal_loop: // do {
MOVUPS (SRC)(IDX*8), X2 // X_i = x[i]
MOVUPS 16(SRC)(IDX*8), X3
MOVUPS 32(SRC)(IDX*8), X4
MOVUPS 48(SRC)(IDX*8), X5
MULPD ALPHA, X2 // X_i *= ALPHA
MULPD ALPHA_2, X3
MULPD ALPHA, X4
MULPD ALPHA_2, X5
MOVUPS X2, (DST)(IDX*8) // x[i] = X_i
MOVUPS X3, 16(DST)(IDX*8)
MOVUPS X4, 32(DST)(IDX*8)
MOVUPS X5, 48(DST)(IDX*8)
ADDQ $8, IDX // IDX += 8
DECQ LEN
JNZ dscal_loop // } while --LEN > 0
dscal_tail:
ANDQ $3, TAIL // TAIL = TAIL % 4
JZ dscal_end // if TAIL == 0 { return }
dscal_tail_loop: // do {
MOVUPS (SRC)(IDX*8), X2 // X_i = x[i]
MULPD ALPHA, X2 // X_i *= ALPHA
MOVUPS X2, (DST)(IDX*8) // x[i] = X_i
ADDQ $2, IDX // IDX += 2
DECQ TAIL
JNZ dscal_tail_loop // } while --TAIL > 0
dscal_end:
RET
| {
"language": "Assembly"
} |
/**
******************************************************************************
* @file startup_stm32f10x_cl.s
* @author MCD Application Team
* @version V3.1.0
* @date 06/19/2009
* @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR
* address.
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
*******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
*
* Andy's modified this slightly to include the branch to SystemInit before
* main because ST were doing the SystemInit() as line 1 in main and we
* don't think you need to bother your code with that burden.
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global SystemInit_ExtMemCtl_Dummy
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word OTG_FS_WKUP_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word ETH_IRQHandler
.word ETH_WKUP_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word OTG_FS_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x Connectivity line Devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
/*
* SysTick_Handler in stm32plus is now marked 'weak' so that compatibility with other
* frameworks is made possible.
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
*/
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak ETH_IRQHandler
.thumb_set ETH_IRQHandler,Default_Handler
.weak ETH_WKUP_IRQHandler
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler ,Default_Handler
| {
"language": "Assembly"
} |
config BR2_PACKAGE_CONNTRACK_TOOLS
bool "conntrack-tools"
depends on BR2_USE_MMU # fork()
depends on BR2_TOOLCHAIN_HAS_NATIVE_RPC || BR2_TOOLCHAIN_HAS_THREADS # libtirpc
depends on !BR2_STATIC_LIBS # dlopen()
select BR2_PACKAGE_LIBNETFILTER_CONNTRACK
select BR2_PACKAGE_LIBNETFILTER_CTHELPER
select BR2_PACKAGE_LIBNETFILTER_CTTIMEOUT
select BR2_PACKAGE_LIBNETFILTER_QUEUE
select BR2_PACKAGE_LIBTIRPC if !BR2_TOOLCHAIN_HAS_NATIVE_RPC
help
The conntrack-tools are a set of tools targeted at
system administrators.
They are conntrack, the userspace command line interface,
and conntrackd, the userspace daemon.
http://www.netfilter.org/projects/conntrack-tools/
comment "conntrack-tools needs a toolchain w/ threads, dynamic library"
depends on BR2_USE_MMU
depends on !(BR2_TOOLCHAIN_HAS_THREADS || BR2_TOOLCHAIN_HAS_NATIVE_RPC) || \
BR2_STATIC_LIBS
| {
"language": "Assembly"
} |
// RUN: %clang -target hexagon -### -mnvs %s 2>&1 \
// RUN: | FileCheck %s -check-prefix CHECK-NVS
// RUN: %clang -target hexagon -### -mno-nvs %s 2>&1 \
// RUN: | FileCheck %s -check-prefix CHECK-NO-NVS
// CHECK-NVS: "-target-feature" "+nvs"
// CHECK-NO-NVS: "-target-feature" "-nvs"
| {
"language": "Assembly"
} |
AT+CPMS=?
+CPMS: ("SM","ME"), ("SM","ME"), ("SM","ME")
OK
| {
"language": "Assembly"
} |
#pragma once
#ifdef __GNUC__
#pragma GCC system_header
#endif
#include "mavlink/v2.0/common/mavlink.h"
| {
"language": "Assembly"
} |
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
| {
"language": "Assembly"
} |
; RUN: opt < %s -partial-inliner -S -skip-partial-inlining-cost-analysis | FileCheck %s
; RUN: opt < %s -passes=partial-inliner -S -skip-partial-inlining-cost-analysis | FileCheck %s
@stat = external global i32, align 4
define i32 @vararg(i32 %count, ...) {
entry:
%vargs = alloca i8*, align 8
%stat1 = load i32, i32* @stat, align 4
%cmp = icmp slt i32 %stat1, 0
br i1 %cmp, label %bb2, label %bb1
bb1: ; preds = %entry
%vg1 = add nsw i32 %stat1, 1
store i32 %vg1, i32* @stat, align 4
%vargs1 = bitcast i8** %vargs to i8*
call void @llvm.va_start(i8* %vargs1)
%va1 = va_arg i8** %vargs, i32
call void @foo(i32 %count, i32 %va1) #2
call void @llvm.va_end(i8* %vargs1)
br label %bb2
bb2: ; preds = %bb1, %entry
%res = phi i32 [ 1, %bb1 ], [ 0, %entry ]
ret i32 %res
}
declare void @foo(i32, i32)
declare void @llvm.va_start(i8*)
declare void @llvm.va_end(i8*)
define i32 @caller1(i32 %arg) {
bb:
%tmp = tail call i32 (i32, ...) @vararg(i32 %arg)
ret i32 %tmp
}
; CHECK-LABEL: @caller1
; CHECK: codeRepl.i:
; CHECK-NEXT: call void (i32, i8**, i32, ...) @vararg.3.bb1(i32 %stat1.i, i8** %vargs.i, i32 %arg)
define i32 @caller2(i32 %arg, float %arg2) {
bb:
%tmp = tail call i32 (i32, ...) @vararg(i32 %arg, i32 10, float %arg2)
ret i32 %tmp
}
; CHECK-LABEL: @caller2
; CHECK: codeRepl.i:
; CHECK-NEXT: call void (i32, i8**, i32, ...) @vararg.3.bb1(i32 %stat1.i, i8** %vargs.i, i32 %arg, i32 10, float %arg2)
; Test case to check that we do not extract a vararg function, if va_end is in
; a block that is not outlined.
define i32 @vararg_not_legal(i32 %count, ...) {
entry:
%vargs = alloca i8*, align 8
%vargs0 = bitcast i8** %vargs to i8*
%stat1 = load i32, i32* @stat, align 4
%cmp = icmp slt i32 %stat1, 0
br i1 %cmp, label %bb2, label %bb1
bb1: ; preds = %entry
%vg1 = add nsw i32 %stat1, 1
store i32 %vg1, i32* @stat, align 4
%vargs1 = bitcast i8** %vargs to i8*
call void @llvm.va_start(i8* %vargs1)
%va1 = va_arg i8** %vargs, i32
call void @foo(i32 %count, i32 %va1)
br label %bb2
bb2: ; preds = %bb1, %entry
%res = phi i32 [ 1, %bb1 ], [ 0, %entry ]
%ptr = phi i8* [ %vargs1, %bb1 ], [ %vargs0, %entry]
call void @llvm.va_end(i8* %ptr)
ret i32 %res
}
; CHECK-LABEL: @caller3
; CHECK: tail call i32 (i32, ...) @vararg_not_legal(i32 %arg, i32 %arg)
define i32 @caller3(i32 %arg) {
bb:
%res = tail call i32 (i32, ...) @vararg_not_legal(i32 %arg, i32 %arg)
ret i32 %res
}
declare i32* @err(i32*)
define signext i32 @vararg2(i32 * %l, ...) {
entry:
br i1 undef, label %cleanup, label %cond.end
cond.end: ; preds = %entry
%call51 = call i32* @err(i32* nonnull %l)
unreachable
cleanup: ; preds = %entry
ret i32 0
}
define i32* @caller_with_signext(i32* %foo) {
entry:
%call1 = tail call signext i32 (i32*, ...) @vararg2(i32* %foo, i32 signext 8)
unreachable
}
; CHECK-LABEL: @caller_with_signext
; CHECK: codeRepl.i:
; CHECK-NEXT: call void (i32*, ...) @vararg2.1.cond.end(i32* %foo, i32 signext 8)
| {
"language": "Assembly"
} |
// Copyright 2017 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
TEXT ·socketcall(SB),NOSPLIT,$0-72
JMP syscall·socketcall(SB)
TEXT ·rawsocketcall(SB),NOSPLIT,$0-72
JMP syscall·rawsocketcall(SB)
| {
"language": "Assembly"
} |
// Copyright 2018 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System calls for ppc64, AIX are implemented in runtime/syscall_aix.go
//
TEXT ·syscall6(SB),NOSPLIT,$0-88
JMP syscall·syscall6(SB)
TEXT ·rawSyscall6(SB),NOSPLIT,$0-88
JMP syscall·rawSyscall6(SB)
| {
"language": "Assembly"
} |
# RUN: clangd -lit-test < %s | FileCheck -strict-whitespace %s
# RUN: clangd -lit-test -pch-storage=memory < %s | FileCheck -strict-whitespace %s
{"jsonrpc":"2.0","id":0,"method":"initialize","params":{"processId":123,"rootPath":"clangd","capabilities":{},"trace":"off"}}
---
{"jsonrpc":"2.0","method":"textDocument/didOpen","params":{"textDocument":{"uri":"test:///main.cpp","languageId":"cpp","version":1,"text":"struct S { int a; };\nint main() {\nS().\n}"}}}
---
{"jsonrpc":"2.0","id":1,"method":"textDocument/completion","params":{"textDocument":{"uri":"test:///main.cpp"},"position":{"line":2,"character":4}}}
# CHECK: "id": 1
# CHECK-NEXT: "jsonrpc": "2.0",
# CHECK-NEXT: "result": {
# CHECK-NEXT: "isIncomplete": false,
# CHECK-NEXT: "items": [
# CHECK-NEXT: {
# CHECK-NEXT: "detail": "int",
# CHECK-NEXT: "filterText": "a",
# CHECK-NEXT: "insertText": "a",
# CHECK-NEXT: "insertTextFormat": 1,
# CHECK-NEXT: "kind": 5,
# CHECK-NEXT: "label": " a",
# CHECK-NEXT: "score": {{[0-9]+.[0-9]+}},
# CHECK-NEXT: "sortText": "{{.*}}a"
# CHECK-NEXT: "textEdit": {
# CHECK-NEXT: "newText": "a",
# CHECK-NEXT: "range": {
# CHECK-NEXT: "end": {
# CHECK-NEXT: "character": 4,
# CHECK-NEXT: "line": 2
# CHECK-NEXT: }
# CHECK-NEXT: "start": {
# CHECK-NEXT: "character": 4,
# CHECK-NEXT: "line": 2
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: ]
---
# Update the source file and check for completions again.
{"jsonrpc":"2.0","method":"textDocument/didChange","params":{"textDocument":{"uri":"test:///main.cpp","version":2},"contentChanges":[{"text":"struct S { int b; };\nint main() {\nS().\n}"}]}}
---
{"jsonrpc":"2.0","id":3,"method":"textDocument/completion","params":{"textDocument":{"uri":"test:///main.cpp"},"position":{"line":2,"character":4}}}
# CHECK: "id": 3,
# CHECK-NEXT: "jsonrpc": "2.0",
# CHECK-NEXT: "result": {
# CHECK-NEXT: "isIncomplete": false,
# CHECK-NEXT: "items": [
# CHECK-NEXT: {
# CHECK-NEXT: "detail": "int",
# CHECK-NEXT: "filterText": "b",
# CHECK-NEXT: "insertText": "b",
# CHECK-NEXT: "insertTextFormat": 1,
# CHECK-NEXT: "kind": 5,
# CHECK-NEXT: "label": " b",
# CHECK-NEXT: "score": {{[0-9]+.[0-9]+}},
# CHECK-NEXT: "sortText": "{{.*}}b"
# CHECK-NEXT: "textEdit": {
# CHECK-NEXT: "newText": "b",
# CHECK-NEXT: "range": {
# CHECK-NEXT: "end": {
# CHECK-NEXT: "character": 4,
# CHECK-NEXT: "line": 2
# CHECK-NEXT: }
# CHECK-NEXT: "start": {
# CHECK-NEXT: "character": 4,
# CHECK-NEXT: "line": 2
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: ]
---
{"jsonrpc":"2.0","id":4,"method":"shutdown"}
---
{"jsonrpc":"2.0","method":"exit"}
| {
"language": "Assembly"
} |
// RUN: %target-sil-opt -module-name Swift -enable-sil-verify-all %s -early-codemotion -retain-sinking | %FileCheck %s
import Builtin
enum Never {}
struct Int {
var value : Builtin.Int64
}
struct Int32 {
var value : Builtin.Int32
}
struct Int64 {
var value : Builtin.Int64
}
struct UInt64 {
var value : Builtin.Int64
}
struct Bool {
var value : Builtin.Int1
}
class fuzz { }
enum Boo {
case one
case two
}
class B { }
class E : B { }
class C {}
enum Either {
case First(Builtin.NativeObject)
case Second(C)
}
enum ThreeCaseEnum {
case A
case B
case C
}
struct S {
var ptr : Builtin.NativeObject
}
enum ThreeCaseAbstractionDifference {
case A(Builtin.Int32)
case B(Builtin.NativeObject)
case C(S)
}
struct foo {
var a: Int
init(a: Int)
init()
}
enum Optional<T> {
case none
case some(T)
}
class Klass {}
sil @user : $@convention(thin) (Builtin.NativeObject) -> ()
sil @user_int : $@convention(thin) (Int) -> ()
sil @optional_user : $@convention(thin) (Optional<Builtin.Int32>) -> ()
sil @blocker : $@convention(thin) () -> ()
sil @get_object : $@convention(thin) () -> Builtin.NativeObject
sil @foo_init : $@convention(thin) (@thin foo.Type) -> foo
// CHECK-LABEL: sil @sink_from_preds
// CHECK: bb1:
// CHECK-NEXT: br bb3
// CHECK: bb2:
// CHECK-NEXT: br bb3
// CHECK: bb3:
// CHECK: strong_retain
// CHECK: return
sil @sink_from_preds : $@convention(thin) (Builtin.Int1, B) -> () {
bb0(%0 : $Builtin.Int1, %1 : $B):
cond_br %0, bb1, bb2
bb1:
strong_retain %1 : $B
br bb3
bb2:
strong_retain %1 : $B
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
// CHECK-LABEL: sil @do_not_sink_local_uses
// CHECK: integer_literal
// CHECK: integer_literal
// CHECK: return
sil @do_not_sink_local_uses : $@convention(thin) (Builtin.Int1) -> Builtin.Int32 {
bb0(%0 : $Builtin.Int1):
cond_br %0, bb1, bb3
bb1:
%1 = integer_literal $Builtin.Int32, 7
br bb2(%1 : $Builtin.Int32)
bb3:
%2 = integer_literal $Builtin.Int32, 8
br bb2(%2 : $Builtin.Int32)
bb2(%3 : $Builtin.Int32):
return %3 : $Builtin.Int32
}
// CHECK-LABEL: sil @deep_sink1
// CHECK: integer_literal
// CHECK: br bb3
// CHECK: integer_literal
// CHECK: br bb3
// CHECK: bb3
// CHECK: strong_retain
// CHECK-NEXT: return
sil @deep_sink1 : $@convention(thin) (Builtin.Int1, B) -> Builtin.Int32 {
bb0(%0 : $Builtin.Int1, %1 : $B):
cond_br %0, bb1, bb2
bb1:
strong_retain %1 : $B
%3 = integer_literal $Builtin.Int32, 9
br bb3(%3 : $Builtin.Int32)
bb2:
strong_retain %1 : $B
%5 = integer_literal $Builtin.Int32, 7
br bb3(%5 : $Builtin.Int32)
bb3(%6 : $Builtin.Int32):
return %6 : $Builtin.Int32
}
// CHECK-LABEL: sil @deep_sink2
// CHECK-NOT: integer_literal
// CHECK: br bb3
// CHECK-NOT: integer_literal
// CHECK: br bb3
// CHECK: bb3
// CHECK: integer_literal
// CHECK: strong_retain
// CHECK-NEXT: return
sil @deep_sink2 : $@convention(thin) (Builtin.Int1, B) -> Builtin.Int32 {
bb0(%0 : $Builtin.Int1, %1 : $B):
cond_br %0, bb1, bb2
bb1:
strong_retain %1 : $B
%3 = integer_literal $Builtin.Int32, 7
br bb3(%3 : $Builtin.Int32)
bb2:
strong_retain %1 : $B
%5 = integer_literal $Builtin.Int32, 7
br bb3(%5 : $Builtin.Int32)
bb3(%6 : $Builtin.Int32):
return %6 : $Builtin.Int32
}
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_switch_enum_1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0({{.*}}):
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: retain_value
// CHECK-NEXT: apply
// CHECK-NEXT: alloc_stack
// CHECK-NEXT: dealloc_stack
// CHECK-NEXT: switch_enum
// CHECK: bb1({{.*}}):
// CHECK: strong_retain
// CHECK: bb2:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value
// CHECK-NOT: strong_retain
// CHECK: bb3:
// CHECK-NOT: retain_value
// CHECK-NOT: strong_retain
sil @sink_ref_count_ops_enum_over_switch_enum_1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%1 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %0 : $Optional<Builtin.NativeObject>
apply %1() : $@convention(thin) () -> ()
%3 = alloc_stack $Builtin.Int32
retain_value %0 : $Optional<Builtin.NativeObject>
dealloc_stack %3 : $*Builtin.Int32
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1(%2 : $Builtin.NativeObject):
apply %1() : $@convention(thin) () -> ()
br bb3
bb2:
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
// This test makes sure that we do move ref counts over instructions that cannot reference it.
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_switch_enum_4 :
// CHECK: bb0({{%[0-9]+}} : $Optional<Builtin.NativeObject>, [[ARG1:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK-NOT: retain_value [[ARG1]]
// CHECK: switch_enum
// CHECK: bb1:
// CHECK: retain_value
// CHECK: bb2:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value [[ARG1]]
// CHECK-NOT: strong_retain
// CHECK: bb3:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value [[ARG1]]
// CHECK-NOT: strong_retain
sil @sink_ref_count_ops_enum_over_switch_enum_4 : $@convention(thin) (Optional<Builtin.NativeObject>, Optional<Builtin.NativeObject>) -> Optional<Builtin.NativeObject> {
bb0(%0 : $Optional<Builtin.NativeObject>, %1 : $Optional<Builtin.NativeObject>):
%2 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %1 : $Optional<Builtin.NativeObject>
%3 = alloc_stack $Optional<Builtin.Int32>
retain_value %0 : $Optional<Builtin.NativeObject>
switch_enum %1 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
apply %2() : $@convention(thin) () -> ()
br bb3
bb2:
br bb3
bb3:
dealloc_stack %3 : $*Optional<Builtin.Int32>
return %1 : $Optional<Builtin.NativeObject>
}
/// This version does not work since we have a release before the terminator
/// even though we have the select_enum before it.
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_switch_enum_5 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
// CHECK: bb0({{.*}}):
// CHECK: bb1:
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: alloc_stack
// CHECK-NEXT: dealloc_stack
// CHECK-NEXT: retain_value
// CHECK-NEXT: release_value
// CHECK-NEXT: switch_enum
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK-NOT: retain_value
// CHECK: bb4:
// CHECK-NOT: retain_value
sil @sink_ref_count_ops_enum_over_switch_enum_5 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
bb0(%0 : $Optional<Builtin.Int32>):
br bb10
bb10:
%1 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %0 : $Optional<Builtin.Int32>
%3 = alloc_stack $Builtin.Int32
dealloc_stack %3 : $*Builtin.Int32
release_value %0 : $Optional<Builtin.Int32>
switch_enum %0 : $Optional<Builtin.Int32>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
br bb3
bb2:
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_select_enum_1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0({{.*}}):
// CHECK-NEXT: integer_literal
// CHECK-NEXT: integer_literal
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: retain_value
// CHECK-NEXT: apply
// CHECK-NEXT: alloc_stack
// CHECK-NEXT: dealloc_stack
// CHECK-NEXT: select_enum
// CHECK-NEXT: cond_br
// CHECK: bb1:
// CHECK: strong_retain
// CHECK: bb2:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value
// CHECK-NOT: strong_retain
// CHECK: bb3:
// CHECK-NOT: retain_value
// CHECK-NOT: strong_retain
sil @sink_ref_count_ops_enum_over_select_enum_1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
%1 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %0 : $Optional<Builtin.NativeObject>
apply %1() : $@convention(thin) () -> ()
%3 = alloc_stack $Builtin.Int32
retain_value %0 : $Optional<Builtin.NativeObject>
dealloc_stack %3 : $*Builtin.Int32
%100 = select_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
cond_br %100, bb1, bb2
bb1:
apply %1() : $@convention(thin) () -> ()
br bb3
bb2:
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_select_enum_2 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
// CHECK: bb0({{.*}}):
// CHECK-NEXT: integer_literal
// CHECK-NEXT: integer_literal
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: cond_br
// CHECK: bb1:
// CHECK: bb2:
// CHECK-NEXT: select_enum
// CHECK-NEXT: cond_br
// CHECK: bb3:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value
// CHECK-LABEL: } // end sil function 'sink_ref_count_ops_enum_over_select_enum_2'
sil @sink_ref_count_ops_enum_over_select_enum_2 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
bb0(%0 : $Optional<Builtin.Int32>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
%1 = function_ref @blocker : $@convention(thin) () -> ()
cond_br undef, bb1, bb2
bb1:
retain_value %0 : $Optional<Builtin.Int32>
%100 = select_enum %0 : $Optional<Builtin.Int32>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
cond_br %100, bb2, bb3
bb2:
br bb4
bb3:
br bb4
bb4:
%2 = tuple()
return %2 : $()
}
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_select_enum_3 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
// CHECK: bb0({{.*}}):
// CHECK-NEXT: integer_literal
// CHECK-NEXT: integer_literal
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: cond_br
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK-NEXT: select_enum
// CHECK-NEXT: cond_br
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value
// CHECK-LABEL: } // end sil function 'sink_ref_count_ops_enum_over_select_enum_3'
sil @sink_ref_count_ops_enum_over_select_enum_3 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
bb0(%0 : $Optional<Builtin.Int32>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
%1 = function_ref @blocker : $@convention(thin) () -> ()
cond_br undef, bb1, bb3
bb1:
retain_value %0 : $Optional<Builtin.Int32>
%100 = select_enum %0 : $Optional<Builtin.Int32>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
cond_br %100, bb2, bb3
bb2:
br bb4
bb3:
br bb4
bb4:
%2 = tuple()
return %2 : $()
}
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_select_enum_4 : $@convention(thin) (Optional<Builtin.NativeObject>, Optional<Builtin.NativeObject>) -> Optional<Builtin.NativeObject> {
// CHECK: bb0({{%[0-9]+}} : $Optional<Builtin.NativeObject>, [[ARG1:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK-NOT: retain_value [[ARG1]]
// CHECK: select_enum
// CHECK: cond_br
// CHECK: bb1:
// CHECK: retain_value
// CHECK: bb2:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value [[ARG1]]
// CHECK: bb3:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: retain_value [[ARG1]]
sil @sink_ref_count_ops_enum_over_select_enum_4 : $@convention(thin) (Optional<Builtin.NativeObject>, Optional<Builtin.NativeObject>) -> Optional<Builtin.NativeObject> {
bb0(%0 : $Optional<Builtin.NativeObject>, %1 : $Optional<Builtin.NativeObject>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
%2 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %1 : $Optional<Builtin.NativeObject>
retain_value %0 : $Optional<Builtin.NativeObject>
%100 = select_enum %1 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
cond_br %100, bb1, bb2
bb1:
apply %2() : $@convention(thin) () -> ()
br bb3
bb2:
br bb3
bb3:
return %1 : $Optional<Builtin.NativeObject>
}
/// This version does not work since we have a release before the terminator
/// even though we have the select_enum before it.
// CHECK-LABEL: sil @sink_ref_count_ops_enum_over_select_enum_5 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
// CHECK: bb0({{.*}}):
// CHECK: bb1:
// CHECK-NEXT: function_ref blocker
// CHECK-NEXT: function_ref @blocker
// CHECK-NEXT: alloc_stack
// CHECK-NEXT: dealloc_stack
// CHECK-NEXT: select_enum
// CHECK-NEXT: retain_value
// CHECK-NEXT: release_value
// CHECK-NEXT: cond_br
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK-NOT: retain_value
// CHECK: bb4:
// CHECK-NOT: retain_value
sil @sink_ref_count_ops_enum_over_select_enum_5 : $@convention(thin) (Optional<Builtin.Int32>) -> () {
bb0(%0 : $Optional<Builtin.Int32>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
br bb10
bb10:
%1 = function_ref @blocker : $@convention(thin) () -> ()
retain_value %0 : $Optional<Builtin.Int32>
%3 = alloc_stack $Builtin.Int32
dealloc_stack %3 : $*Builtin.Int32
%100 = select_enum %0 : $Optional<Builtin.Int32>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
release_value %0 : $Optional<Builtin.Int32>
cond_br %100, bb1, bb2
bb1:
br bb3
bb2:
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
// Sink the struct instruction
// CHECK-LABEL: sil @sink_struct : $@convention(thin) (Optional<Builtin.Int32>) -> Bool {
// CHECK: bb0({{.*}}):
// CHECK: switch_enum
// CHECK: bb1:
// CHECK: integer_literal $Builtin.Int1, -1
// CHECK: br bb3({{.*}} : $Builtin.Int1)
// CHECK: bb2:
// CHECK: integer_literal $Builtin.Int1, 0
// CHECK: br bb3({{.*}} : $Builtin.Int1)
// CHECK: bb3({{.*}} : $Builtin.Int1):
// CHECK: struct $Bool
// CHECK: return
sil @sink_struct : $@convention(thin) (Optional<Builtin.Int32>) -> Bool {
bb0(%0 : $Optional<Builtin.Int32>):
switch_enum %0 : $Optional<Builtin.Int32>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
%6 = integer_literal $Builtin.Int1, -1
%7 = struct $Bool (%6 : $Builtin.Int1)
br bb3(%7 : $Bool)
bb2:
%9 = integer_literal $Builtin.Int1, 0
%10 = struct $Bool (%9 : $Builtin.Int1)
br bb3(%10 : $Bool)
bb3(%12 : $Bool):
return %12 : $Bool
}
// Sink retain down the successors so we can pair up retain with release on the
// fast path.
class Test {
func testing() -> UInt64
}
sil_global @test : $Test
sil_global @x : $UInt64
// CHECK-LABEL: @sink_refcount_to_succs
sil @sink_refcount_to_succs : $@convention(thin) () -> () {
bb0:
%0 = global_addr @test : $*Test
%1 = alloc_ref $Test
store %1 to %0 : $*Test
%7 = global_addr @x : $*UInt64
%8 = integer_literal $Builtin.Int64, 0
%9 = struct $UInt64 (%8 : $Builtin.Int64)
store %9 to %7 : $*UInt64
br bb1
bb1:
// CHECK: bb1:
// CHECK-NOT: strong_retain
%17 = load %0 : $*Test
strong_retain %17 : $Test
%19 = class_method %17 : $Test, #Test.testing : (Test) -> () -> UInt64, $@convention(method) (@guaranteed Test) -> UInt64
%20 = load %7 : $*UInt64
checked_cast_br [exact] %17 : $Test to Test, bb3, bb4
bb2:
// CHECK: bb2:
// CHECK-NOT: strong_retain
%36 = tuple ()
return %36 : $()
bb3(%38 : $Test):
// CHECK: bb3(
// CHECK: strong_retain
// CHECK: strong_release
strong_release %17 : $Test
br bb2
bb4:
// CHECK: bb4:
// CHECK: strong_retain
// CHECK: apply
%65 = apply %19(%17) : $@convention(method) (@guaranteed Test) -> UInt64
br bb2
}
sil @virtual_callee : $@convention(method) (@guaranteed Test) -> UInt64
sil_vtable Test {
#Test.testing: @virtual_callee
}
// CHECK-LABEL: sil @sink_retains_from_preds : $@convention(thin) (Builtin.NativeObject) -> () {
// CHECK: bb1:
// CHECK-NOT: retain_value
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK: strong_retain
sil @sink_retains_from_preds : $@convention(thin) (Builtin.NativeObject) -> () {
bb0(%0 : $Builtin.NativeObject):
cond_br undef, bb1, bb2
bb1:
retain_value %0 : $Builtin.NativeObject
br bb3
bb2:
retain_value %0 : $Builtin.NativeObject
br bb3
bb3:
%1 = tuple()
return %1 : $()
}
// CHECK-LABEL: sil @enum_simplification_test1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0
// CHECK-NEXT: retain_value
// CHECK-NEXT: release_value
sil @enum_simplification_test1 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
retain_value %0 : $Optional<Builtin.NativeObject>
release_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test3 : $@convention(thin) () -> () {
// CHECK: bb0
// CHECK-NEXT: enum
// CHECK-NOT: strong_retain
// CHECK-NOT: strong_release
// CHECK-NEXT: tuple
// CHECK-NEXT: return
sil @enum_simplification_test3 : $@convention(thin) () -> () {
bb0:
%0 = enum $Optional<Builtin.NativeObject>, #Optional.none!enumelt
retain_value %0 : $Optional<Builtin.NativeObject>
release_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test4 : $@convention(thin) () -> () {
// CHECK: bb0
// CHECK-NEXT: get_object
// CHECK-NEXT: function_ref @get_object
// CHECK-NEXT: apply
// CHECK-NEXT: enum
// CHECK: strong_retain
// CHECK: strong_release
sil @enum_simplification_test4 : $@convention(thin) () -> () {
bb0:
%0 = function_ref @get_object : $@convention(thin) () -> Builtin.NativeObject
%1 = apply %0() : $@convention(thin) () -> Builtin.NativeObject
%2 = enum $Optional<Builtin.NativeObject>, #Optional.some!enumelt, %1 : $Builtin.NativeObject
retain_value %2 : $Optional<Builtin.NativeObject>
release_value %2 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test5 : $@convention(thin) () -> () {
// CHECK: bb1:
// CHECK-NOT: strong_retain
// CHECK: bb2:
// CHECK-NOT: strong_retain
// CHECK: bb3:
// CHECK: strong_retain
sil @enum_simplification_test5 : $@convention(thin) () -> () {
bb0:
%0 = function_ref @get_object : $@convention(thin) () -> Builtin.NativeObject
%1 = apply %0() : $@convention(thin) () -> Builtin.NativeObject
%2 = enum $Optional<Builtin.NativeObject>, #Optional.some!enumelt, %1 : $Builtin.NativeObject
%3 = function_ref @blocker : $@convention(thin) () -> ()
cond_br undef, bb1, bb2
bb1:
retain_value %2 : $Optional<Builtin.NativeObject>
apply %3() : $@convention(thin) () -> ()
br bb3
bb2:
retain_value %2 : $Optional<Builtin.NativeObject>
apply %3() : $@convention(thin) () -> ()
br bb3
bb3:
%9999 = tuple()
return %9999 : $()
}
// This test is testing that we can properly simplify unchecked_enum_data if we
// know the tag. We also sink it.
//
// CHECK-LABEL: sil @enum_simplification_test6a : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb1:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: strong_retain
// CHECK-NOT: retain_value
// CHECK: bb2:
// CHECK-NOT: unchecked_enum_data
// CHECK-NOT: strong_retain
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK: retain_value
sil @enum_simplification_test6a : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%1 = unchecked_enum_data %0 : $Optional<Builtin.NativeObject>, #Optional.some!enumelt
cond_br undef, bb1, bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb3:
%9999 = tuple()
return %9999 : $()
}
// Because our enum is not local to this function, we cannot move retain_value
// %0 past blocker.
//
// CHECK-LABEL: sil @enum_simplification_test6b : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb1:
// CHECK: strong_retain
// CHECK: bb2:
// CHECK: strong_retain
// CHECK: bb3:
// CHECK-NOT: retain_value
sil @enum_simplification_test6b : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%1 = unchecked_enum_data %0 : $Optional<Builtin.NativeObject>, #Optional.some!enumelt
%2 = function_ref @blocker : $@convention(thin) () -> ()
cond_br undef, bb1, bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
apply %2() : $@convention(thin) () -> ()
br bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb3:
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test7 : $@convention(thin) () -> () {
// CHECK-NOT: retain
// CHECK-NOT: retain
// CHECK: return
sil @enum_simplification_test7 : $@convention(thin) () -> () {
bb0:
%0 = enum $Optional<Builtin.NativeObject>, #Optional.none!enumelt
cond_br undef, bb1, bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb3:
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test8 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0([[INPUT:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK-NOT: retain_value [[INPUT]]
// CHECK: bb2:
// CHECK-NEXT: [[PAYLOAD:%[0-9]+]] = unchecked_enum_data [[INPUT]]
// CHECK-NOT: strong_retain
// CHECK-NOT: retain_value
// CHECK: bb4:
// CHECK: retain_value [[INPUT]]
sil @enum_simplification_test8 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
cond_br undef, bb1, bb2
bb1:
%1 = unchecked_enum_data %0 : $Optional<Builtin.NativeObject>, #Optional.some!enumelt
cond_br undef, bb2, bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb4
bb3:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb4
bb4:
retain_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test9 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0([[INPUT:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK: bb1:
// CHECK: strong_retain
// CHECK: bb2:
// CHECK-NOT: retain
// CHECK: bb3:
// CHECK: retain_value [[INPUT]]
sil @enum_simplification_test9 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%1 = function_ref @blocker : $@convention(thin) () -> ()
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
apply %1() : $@convention(thin) () -> ()
br bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb3:
retain_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// Note, this is the same as test9, but for enums
// CHECK-LABEL: sil @enum_simplification_test9_enums : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0([[INPUT:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK: bb1:
// CHECK: strong_retain
// CHECK: bb2:
// CHECK-NOT: retain
// CHECK: bb3:
// CHECK: retain_value [[INPUT]]
sil @enum_simplification_test9_enums : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
%t = integer_literal $Builtin.Int1, 1
%f = integer_literal $Builtin.Int1, 0
%2 = function_ref @blocker : $@convention(thin) () -> ()
%1 = select_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: %t, case #Optional.none!enumelt: %f : $Builtin.Int1
cond_br %1, bb1, bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
apply %2() : $@convention(thin) () -> ()
br bb3
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb3:
retain_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
////////////////
// Loop Tests //
////////////////
// CHECK-LABEL: sil @enum_simplification_test10 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0([[INPUT:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK: retain_value [[INPUT]]
// CHECK: retain_value [[INPUT]]
// CHECK: retain_value [[INPUT]]
// CHECK: retain_value [[INPUT]]
sil @enum_simplification_test10 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb3
bb1:
br bb2
// Single BB Loop
bb2:
retain_value %0 : $Optional<Builtin.NativeObject>
cond_br undef, bb2, bb9999
bb3:
br bb4
// Two BB Loop. We can use loop or domination to handle this case. But we don't
// handle it now.
bb4:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb5
bb5:
retain_value %0 : $Optional<Builtin.NativeObject>
cond_br undef, bb4, bb9999
bb9999:
retain_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// Make sure we don't propagate state out of loops.
// CHECK-LABEL: sil @enum_simplification_test11 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0([[INPUT:%[0-9]+]] : $Optional<Builtin.NativeObject>):
// CHECK: retain_value [[INPUT]]
// CHECK: retain_value [[INPUT]]
sil @enum_simplification_test11 : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
br bb3
bb2:
br bb5
bb3:
retain_value %0 : $Optional<Builtin.NativeObject>
cond_br undef, bb3, bb4
bb4:
br bb5
bb5:
retain_value %0 : $Optional<Builtin.NativeObject>
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test14 : $@convention(thin) (Either) -> () {
// CHECK: bb0(
// CHECK-NOT: release
// CHECK: bb1:
// CHECK: release
sil @enum_simplification_test14 : $@convention(thin) (Either) -> () {
bb0(%0 : $Either):
%1 = unchecked_enum_data %0 : $Either, #Either.First!enumelt
cond_br undef, bb1, bb2
bb1:
release_value %0 : $Either
br bb3
bb2:
br bb3
bb3:
%9999 = tuple()
return %9999 : $()
}
// CHECK-LABEL: sil @enum_simplification_test15 : $@convention(thin) (Either, ThreeCaseEnum) -> () {
// CHECK: bb1:
// CHECK: release
// CHECK: bb2:
// CHECK-NOT: release
// CHECK: bb3:
// CHECK-NOT: release
sil @enum_simplification_test15 : $@convention(thin) (Either, ThreeCaseEnum) -> () {
bb0(%0 : $Either, %1 : $ThreeCaseEnum):
%2 = unchecked_enum_data %0 : $Either, #Either.First!enumelt
switch_enum %1 : $ThreeCaseEnum, case #ThreeCaseEnum.A!enumelt: bb1,
case #ThreeCaseEnum.B!enumelt: bb2,
case #ThreeCaseEnum.C!enumelt: bb3
bb1:
release_value %0 : $Either
br bb4
bb2:
br bb4
bb3:
br bb4
bb4:
%9999 = tuple()
return %9999 : $()
}
sil @unknown : $@convention(thin) () -> ()
// CHECK-LABEL: sil @sink_retains_out_of_switch_regions : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb1:
// CHECK-NOT: retain_value
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK: retain_value
sil @sink_retains_out_of_switch_regions : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb2:
br bb3
bb3:
%1 = tuple()
return %1 : $()
}
// CHECK-LABEL: sil @sink_retains_through_multiple_switches : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK-NOT: retain_value
// CHECK: bb9:
// CHECK: retain_value
sil @sink_retains_through_multiple_switches : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
retain_value %0 : $Optional<Builtin.NativeObject>
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
br bb3
bb2:
br bb3
bb3:
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb4, case #Optional.none!enumelt: bb5
bb4:
br bb6
bb5:
br bb6
bb6:
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb7, case #Optional.none!enumelt: bb8
bb7:
br bb9
bb8:
br bb9
bb9:
%1 = tuple()
return %1 : $()
}
// CHECK-LABEL: sil @sink_retains_through_switch_with_body : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK-NOT: retain_value
// CHECK: bb5:
// CHECK: retain_value
sil @sink_retains_through_switch_with_body : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
retain_value %0 : $Optional<Builtin.NativeObject>
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
br bb3
bb2:
br bb4
bb3:
br bb5
bb4:
br bb5
bb5:
%1 = tuple()
return %1 : $()
}
// CHECK-LABEL: sil @sink_retains_through_separated_switches : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK-NOT: retain_value
// CHECK: bb3:
// CHECK: retain_value
// CHECK: bb4:
// CHECK: retain_value
// CHECK: bb5:
// CHECK-NOT: retain_value
sil @sink_retains_through_separated_switches : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
retain_value %0 : $Optional<Builtin.NativeObject>
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
cond_br undef, bb3, bb4
bb2:
br bb5
bb3:
br bb5
bb4:
br bb5
bb5:
%1 = tuple()
return %1 : $()
}
// Make sure that we blot pointers from the enumbbtoenumbbcaselist map after
// merging predecessors. This ensures that the failure to merge unrelating
// values does not stop sinking out of retain, release regions.
// CHECK-LABEL: sil @enumbbtoenumbbcaselist_invalidation_test : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb3:
// CHECK: retain_value
sil @enumbbtoenumbbcaselist_invalidation_test : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
switch_enum %0 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
retain_value %0 : $Optional<Builtin.NativeObject>
br bb3
bb2:
%1 = enum $Optional<Builtin.NativeObject>, #Optional.none!enumelt
br bb3
bb3:
%2 = tuple()
return %2 : $()
}
// We can do the deletion in simplify-cfg.
//
// CHECK-LABEL: sil @delete_instead_of_sinkretainsintounreachable_bb : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
// CHECK: bb0(
// CHECK-NOT: retain_value
// CHECK: bb1:
// CHECK-NEXT: unreachable
// CHECK: bb2:
// CHECK: retain_value
sil @delete_instead_of_sinkretainsintounreachable_bb : $@convention(thin) (Optional<Builtin.NativeObject>) -> () {
bb0(%0 : $Optional<Builtin.NativeObject>):
retain_value %0 : $Optional<Builtin.NativeObject>
cond_br undef, bb1, bb2
bb1:
unreachable
bb2:
%1 = tuple()
return %1 : $()
}
// CHECK-LABEL: sil @sink_retain_over_switch_enum_cast
// CHECK: bb0(
// CHECK-NOT: retain_value
// CHECK: switch_enum
// CHECK: bb1:
// CHECK-NOT: retain_value
// CHECK: br bb3
// CHECK: bb2:
// CHECK-NOT: retain_value
// CHECK: br bb3
// CHECK: bb3:
// CHECK: strong_retain
sil @sink_retain_over_switch_enum_cast : $@convention(thin) (Builtin.NativeObject) -> () {
bb0(%0 : $Builtin.NativeObject):
retain_value %0 : $Builtin.NativeObject
%1 = unchecked_ref_cast %0 : $Builtin.NativeObject to $Optional<Builtin.NativeObject>
switch_enum %1 : $Optional<Builtin.NativeObject>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb2
bb1:
br bb3
bb2:
br bb3
bb3:
%4 = tuple()
return %4 : $()
}
class F {}
class G {}
// CHECK-LABEL: sil @cast_consumption
// CHECK: store
// CHECK-NEXT: strong_retain
// CHECK-NEXT: unconditional_checked_cast_addr
// CHECK-NEXT: strong_release
sil @cast_consumption : $@convention(thin) (@owned F) -> () {
bb0(%0 : $F):
%1 = alloc_stack $F
store %0 to %1 : $*F
strong_retain %0 : $F
unconditional_checked_cast_addr F in %1 : $*F to G in %1 : $*F
strong_release %0 : $F
dealloc_stack %1 : $*F
%2 = tuple ()
return %2 : $()
}
// Make sure that is_unique stops code motion.
// CHECK-LABEL: sil @is_unique_stops_codemotion : $@convention(thin) (@inout Builtin.NativeObject) -> () {
// CHECK: bb0([[IN:%[0-9]+]] : $*Builtin.NativeObject):
// CHECK: [[LD:%[0-9]+]] = load [[IN]] : $*Builtin.NativeObject
// CHECK: strong_retain [[LD]] : $Builtin.NativeObject
// CHECK: is_unique [[IN]] : $*Builtin.NativeObject
sil @is_unique_stops_codemotion : $@convention(thin) (@inout Builtin.NativeObject) -> () {
bb0(%0 : $*Builtin.NativeObject):
%1 = load %0 : $*Builtin.NativeObject
strong_retain %1 : $Builtin.NativeObject
is_unique %0 : $*Builtin.NativeObject
%9999 = tuple()
return %9999 : $()
}
sil @no_return_func : $@convention(thin) () -> Never
// Make sure that we do not move retains over noreturn functions.
// CHECK-LABEL: sil @no_return_stops_codemotion : $@convention(thin) (Builtin.NativeObject) -> () {
// CHECK: apply
// CHECK-NEXT: unreachable
sil @no_return_stops_codemotion : $@convention(thin) (Builtin.NativeObject) -> () {
bb0(%0 : $Builtin.NativeObject):
%1 = alloc_ref $C
strong_retain %1 : $C
%9999 = function_ref @no_return_func : $@convention(thin) () -> Never
apply %9999() : $@convention(thin) () -> Never
unreachable
}
class URefd {
}
class Cont {
unowned var x : URefd
unowned var y : URefd
init()
}
// CHECK-LABEL: sil @sink_unowned_to_ref_through_args
// CHECK: [[LD1:%[0-9]+]] = load
// CHECK-NEXT: br bb3([[LD1]] : $@sil_unowned URefd)
// CHECK: [[LD2:%[0-9]+]] = load
// CHECK-NEXT: br bb3([[LD2]] : $@sil_unowned URefd)
// CHECK: bb3([[ARG:%[0-9]+]] : $@sil_unowned URefd):
// CHECK-NEXT: [[R:%[0-9]+]] = unowned_to_ref [[ARG]]
// CHECK-NEXT: return [[R]]
sil @sink_unowned_to_ref_through_args : $@convention(thin) (Builtin.Int1, Cont) -> URefd {
bb0(%0 : $Builtin.Int1, %1 : $Cont):
cond_br %0, bb1, bb2
bb1:
%x1 = ref_element_addr %1 : $Cont, #Cont.x
%x2 = load %x1 : $*@sil_unowned URefd
%x3 = unowned_to_ref %x2 : $@sil_unowned URefd to $URefd
br bb3(%x3 : $URefd)
bb2:
%y1 = ref_element_addr %1 : $Cont, #Cont.y
%y2 = load %y1 : $*@sil_unowned URefd
%y3 = unowned_to_ref %y2 : $@sil_unowned URefd to $URefd
br bb3(%y3 : $URefd)
bb3(%12 : $URefd):
return %12 : $URefd
}
class X { func ping() {} }
class Y : X { }
// CHECK-LABEL: sil @canonicalize_releases
sil @canonicalize_releases : $@convention(thin) (@owned Optional<X>) -> () {
bb0(%0 : $Optional<X>):
debug_value %0 : $Optional<X>, let, name "x" // id: %1
switch_enum %0 : $Optional<X>, case #Optional.some!enumelt: bb1, case #Optional.none!enumelt: bb3 // id: %2
bb1: // Preds: bb0
%3 = unchecked_enum_data %0 : $Optional<X>, #Optional.some!enumelt // users: %4, %13, %14, %15
checked_cast_br [exact] %3 : $X to X, bb4, bb5 // id: %4
// Make sure we were able to sink the release.
// CHECK: strong_release
// CHECK-NEXT: tuple ()
// CHECK-NEXT: return
bb2: // Preds: bb4 bb5
%5 = tuple () // user: %6
return %5 : $() // id: %6
bb3: // Preds: bb0
%7 = integer_literal $Builtin.Int1, -1 // user: %8
cond_fail %7 : $Builtin.Int1 // id: %8
unreachable // id: %9
// Canonicalize the re
bb4(%10 : $X): // Preds: bb1
strong_release %10 : $X // id: %11
br bb2 // id: %12
bb5: // Preds: bb1
%13 = class_method %3 : $X, #X.ping : (X) -> () -> (), $@convention(method) (@guaranteed X) -> () // user: %14
%14 = apply %13(%3) : $@convention(method) (@guaranteed X) -> ()
strong_release %3 : $X // id: %15
br bb2 // id: %16
}
// The input swift code:
// func foo(x : X) -> Int {
// if let z = x as? Y {
// z.ping()
// z.ping()
// }
// return 0
// }
//CHECK-LABEL: sil @canonicalize_casts
// Make sure we are replacing all uses of %3 with %0.
sil @canonicalize_casts: $@convention(thin) (@owned X) -> Int32 {
bb0(%0 : $X):
debug_value %0 : $X, let, name "x" // id: %1
checked_cast_br %0 : $X to Y, bb1, bb3 // id: %2
bb1(%3 : $Y): // Preds: bb0
debug_value %3 : $Y, let, name "z" // id: %4
%5 = upcast %3 : $Y to $X // users: %6, %7, %21, %23
%6 = class_method %5 : $X, #X.ping : (X) -> () -> (), $@convention(method) (@guaranteed X) -> () // users: %21, %23
checked_cast_br [exact] %5 : $X to Y, bb5, bb6 // id: %7
bb2: // Preds: bb5 bb6
//CHECK: strong_release %0
//CHECK-NEXT: strong_release %0
strong_release %0 : $X // id: %8
strong_release %3 : $Y // id: %9
br bb4 // id: %10
bb3: // Preds: bb0
br bb4 // id: %11
bb4: // Preds: bb2 bb3
%12 = integer_literal $Builtin.Int32, 0 // user: %13
%13 = struct $Int32 (%12 : $Builtin.Int32) // user: %15
strong_release %0 : $X // id: %14
return %13 : $Int32 // id: %15
bb5(%16 : $Y): // Preds: bb1
//CHECK: strong_retain %0
//CHECK-NEXT: strong_retain %0
strong_retain %0 : $X // id: %17
strong_retain %3 : $Y // id: %18
br bb2 // id: %19
bb6: // Preds: bb1
//CHECK: strong_retain %0
//CHECK-NEXT: apply
//CHECK-NEXT: strong_retain %0
//CHECK-NEXT: apply
strong_retain %3 : $Y // id: %20
%21 = apply %6(%5) : $@convention(method) (@guaranteed X) -> ()
strong_retain %0 : $X // id: %22
%23 = apply %6(%5) : $@convention(method) (@guaranteed X) -> ()
br bb2 // id: %24
}
// Make sure we are not crashing on this one:
sil @direct_branch0: $@convention(thin) (@owned X) -> Int {
bb0(%0 : $X):
br bb1(%0 : $X)
bb1(%1 : $X):
strong_release %1 : $X
br bb2(%1 : $X)
bb2(%4 : $X):
strong_release %4 : $X
br bb2(%4 : $X)
}
//CHECK-LABEL: @cond_branch0
sil @cond_branch0: $@convention(thin) (@owned X) -> Int {
bb0(%0 : $X):
cond_br undef, bb1(%0 : $X), bb2(%0 : $X)
bb1(%1 : $X):
//CHECK: strong_release %0
strong_release %1 : $X
br bb2(%1 : $X)
bb2(%4 : $X):
br bb3(%4 : $X)
bb3(%6 : $X):
//CHECK: strong_release %6
strong_release %6 : $X
br bb3(%6 : $X)
}
// CHECK-LABEL: sil @sink_literals_through_arguments
sil @sink_literals_through_arguments : $@convention(thin) (Builtin.Int1) -> Builtin.RawPointer {
bb0(%0 : $Builtin.Int1):
cond_br %0, bb1, bb2
bb1:
%x1 = string_literal utf8 "0"
br bb3(%x1 : $Builtin.RawPointer)
bb2:
%y1 = string_literal utf8 "0"
br bb3(%y1 : $Builtin.RawPointer)
bb3(%z1 : $Builtin.RawPointer):
//CHECK: string_literal utf8 "0"
//CHECK-NEXT: return
return %z1 : $Builtin.RawPointer
}
// CHECK-LABEL: sil hidden @sink_allocation_inst
sil hidden @sink_allocation_inst : $@convention(thin) (Boo, Boo) -> Bool {
bb0(%0 : $Boo, %1 : $Boo):
debug_value %0 : $Boo, let, name "x" // id: %2
debug_value %0 : $Boo // id: %3
debug_value %0 : $Boo, let, name "self" // id: %4
switch_enum %0 : $Boo, case #Boo.one!enumelt: bb1, case #Boo.two!enumelt: bb3 // id: %5
bb1: // Preds: bb0
%6 = alloc_ref $fuzz // users: %7, %8
debug_value %6 : $fuzz, let, name "self" // id: %7
br bb2(%6 : $fuzz) // id: %8
bb3: // Preds: bb0
%15 = alloc_ref $fuzz // users: %16, %17
debug_value %15 : $fuzz, let, name "self" // id: %16
br bb2(%15 : $fuzz) // id: %17
bb2(%9 : $fuzz):
// Make sure we have a single alloc_ref instruction and not two.
// CHECK: alloc_ref
// CHECK-NOT: alloc_ref
// CHECK: return
debug_value %9 : $fuzz, let, name "lhs" // id: %10
%11 = integer_literal $Builtin.Int1, -1 // user: %12
%12 = struct $Bool (%11 : $Builtin.Int1) // user: %14
strong_release %9 : $fuzz // id: %13
return %12 : $Bool // id: %14
}
// Make sure retain instruction is not sunk across copy_addr inst, as copy_addr
// may decrement the refcount of %0 here.
//
// CHECK-LABEL: retain_blocked_by_copyaddr
// CHECK: bb0
// CHECK-NEXT: retain_value
sil hidden @retain_blocked_by_copyaddr : $@convention(thin) <T> (@in T, B) -> @out T {
bb0(%0 : $*T, %1 : $*T, %2 : $B):
retain_value %2 : $B
copy_addr [take] %1 to %0 : $*T // id: %3
%4 = tuple () // user: %5
return %4 : $() // id: %5
}
// Make sure retain instruction is sunk across copy_addr inst, as copy_addr
// dest is initialized.
//
// CHECK-LABEL: retain_not_blocked_by_copyaddrinit
// CHECK: bb0
// CHECK-NEXT: copy_addr
// CHECK-NEXT: tuple
// CHECK-NEXT: strong_retain
sil hidden @retain_not_blocked_by_copyaddrinit : $@convention(thin) <T> (@in T, B) -> @out T {
bb0(%0 : $*T, %1 : $*T, %2 : $B):
retain_value %2 : $B
copy_addr [take] %1 to [initialization] %0 : $*T // id: %3
%4 = tuple () // user: %5
return %4 : $() // id: %5
}
// Make sure retain instruction is sunk across copy_addr inst, as copy_addr
// dest is initialized.
//
// CHECK-LABEL: retain_not_blocked_by_copyaddr_notake_init
// CHECK: bb0
// CHECK-NEXT: copy_addr
// CHECK-NEXT: tuple
// CHECK-NEXT: strong_retain
sil hidden @retain_not_blocked_by_copyaddr_notake_init : $@convention(thin) <T> (@in T, B) -> @out T {
bb0(%0 : $*T, %1 : $*T, %2 : $B):
retain_value %2 : $B
copy_addr %1 to [initialization] %0 : $*T // id: %3
%4 = tuple () // user: %5
return %4 : $() // id: %5
}
// Make sure we do not sink the SILArgument for bb3.
//
// CHECK-LABEL: no_sinkargument_on_clobbered_load
// CHECK: bb3(%20 : $Int):
// CHECK-NOT: load
// CHECK: return
sil hidden @no_sinkargument_on_clobbered_load : $@convention(thin) (Bool) -> () {
// %0 // users: %2, %7
bb0(%0 : $Bool):
%1 = alloc_stack $foo // users: %6, %11, %17, %24
debug_value %0 : $Bool // id: %2
// function_ref foo_init
%3 = function_ref @foo_init : $@convention(thin) (@thin foo.Type) -> foo // user: %5
%4 = metatype $@thin foo.Type // user: %5
%5 = apply %3(%4) : $@convention(thin) (@thin foo.Type) -> foo // user: %6
store %5 to %1 : $*foo // id: %6
%7 = struct_extract %0 : $Bool, #Bool.value // user: %8
cond_br %7, bb1, bb2 // id: %8
bb1: // Preds: bb0
%9 = integer_literal $Builtin.Int64, 11 // user: %10
%10 = struct $Int (%9 : $Builtin.Int64) // user: %13
%11 = struct_element_addr %1 : $*foo, #foo.a // users: %12, %13
%12 = load %11 : $*Int // user: %14
store %10 to %11 : $*Int // id: %13
br bb3(%12 : $Int) // id: %14
bb2: // Preds: bb0
%15 = integer_literal $Builtin.Int64, 12 // user: %16
%16 = struct $Int (%15 : $Builtin.Int64)
%17 = struct_element_addr %1 : $*foo, #foo.a // user: %18
%18 = load %17 : $*Int // user: %19
br bb3(%18 : $Int) // id: %19
// %20 // user: %22
bb3(%20 : $Int): // Preds: bb1 bb2
// function_ref user_int
%21 = function_ref @user_int : $@convention(thin) (Int) -> () // user: %22
%22 = apply %21(%20) : $@convention(thin) (Int) -> ()
%23 = tuple () // user: %25
dealloc_stack %1 : $*foo // id: %24
return %23 : $() // id: %25
}
// Make sure that we properly perform global blotting of values and do not crash
// on this code. This will only fail reliably in ASAN builds of swift in such a
// case.
sil @test_global_blotting : $@convention(thin) () -> () {
bbBegin:
%0a = enum $Optional<Klass>, #Optional.none!enumelt
cond_br undef, bb1, bb2
bb1:
br bb8(%0a : $Optional<Klass>)
bb2:
%0 = enum $Optional<Klass>, #Optional.none!enumelt
cond_br undef, bb7, bb3
bb3:
cond_br undef, bb4, bb5
bb4:
br bb6
bb5:
br bb6
bb6:
br bb9
bb7:
br bb8(%0 : $Optional<Klass>)
bb8(%result : $Optional<Klass>):
release_value %result : $Optional<Klass>
br bb9
bb9:
%9999 = tuple()
return %9999 : $()
}
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBCLC
bool "libclc"
depends on BR2_PACKAGE_LLVM_ARCH_SUPPORTS
depends on BR2_HOST_GCC_AT_LEAST_4_8
help
libclc is an open source, BSD licensed implementation of
the library requirements of the OpenCL C programming language,
as specified by the OpenCL 1.1 Specification.
http://libclc.llvm.org/
| {
"language": "Assembly"
} |
;
; Probably belongs somewhere more general eventually
;
.globl porta, pioc, portc, portb, portcl, ddrc, portd
.globl ddrd,porte, cforc, oc1m, oc1d, tcnth, tcntl
.globl tic1h, tic1l, tic2h, tic2l, tic3h, tic3l
.globl toc1h, toc1l, toc2h, toc2l, toc3h, toc3l
.globl toc4h, toc4l, ti4o5h, ti4o5l, tctl1, tctl2
.globl tmsk1, tflg1, tmsk2, tflg2, pactl, pacnt
.globl spcr, spsr, spdr, baud, sccr1, sccr2
.globl scsr, scdr, adctl, adr1, adr2, adr3, adr4
.globl bprot, eprog, option, coprst, pprog, hprio, init
.equ porta, iobase + 0x00
; reserved 0x01
.equ pioc, iobase + 0x02
.equ portc, iobase + 0x03
.equ portb, iobase + 0x04
.equ portcl, iobase + 0x05
; reserved 0x06
.equ ddrc, iobase + 0x07
.equ portd, iobase + 0x08
.equ ddrd, iobase + 0x09
.equ porte, iobase + 0x0A
.equ cforc, iobase + 0x0B
.equ oc1m, iobase + 0x0C
.equ oc1d, iobase + 0x0D
.equ tcnth, iobase + 0x0E
.equ tcntl, iobase + 0x0F
.equ tic1h, iobase + 0x10
.equ tic1l, iobase + 0x11
.equ tic2h, iobase + 0x12
.equ tic2l, iobase + 0x13
.equ tic3h, iobase + 0x14
.equ tic3l, iobase + 0x15
.equ toc1h, iobase + 0x16
.equ toc1l, iobase + 0x17
.equ toc2h, iobase + 0x18
.equ toc2l, iobase + 0x19
.equ toc3h, iobase + 0x1a
.equ toc3l, iobase + 0x1b
.equ toc4h, iobase + 0x1c
.equ toc4l, iobase + 0x1d
.equ ti4o5h, iobase + 0x1e
.equ ti405l, iobase + 0x1f
.equ tctl1, iobase + 0x20
.equ tctl2, iobase + 0x21
.equ tmsk1, iobase + 0x22
.equ tflg1, iobase + 0x23
.equ tmsk2, iobase + 0x24
.equ tflg2, iobase + 0x25
.equ pactl, iobase + 0x26
.equ pacnt, iobase + 0x27
.equ spcr, iobase + 0x28
.equ spsr, iobase + 0x29
.equ spdr, iobase + 0x2A
.equ baud, iobase + 0x2B
.equ sccr1, iobase + 0x2C
.equ sccr2, iobase + 0x2D
.equ scsr, iobase + 0x2E
.equ scdr, iobase + 0x2F
.equ adctl, iobase + 0x30
.equ adr1, iobase + 0x31
.equ adr2, iobase + 0x32
.equ adr3, iobase + 0x33
.equ adr4, iobase + 0x34
.equ bprot, iobase + 0x35
.equ eprog, iobase + 0x36
; reserved 0x37
; reserved 0x38
.equ option, iobase + 0x39
.equ coprst, iobase + 0x3A
.equ pprog, iobase + 0x3B
.equ hprio, iobase + 0x3C
.equ init, iobase + 0x3D
; reserved 0x3E
.equ config, iobase + 0x3F
| {
"language": "Assembly"
} |
#------------------------------------------------------------------------------
# $File: xo65,v 1.4 2009/09/19 16:28:13 christos Exp $
# xo65 object files
# From: "Ullrich von Bassewitz" <uz@cc65.org>
#
0 string \x55\x7A\x6E\x61 xo65 object,
>4 leshort x version %d,
>6 leshort&0x0001 =0x0001 with debug info
>6 leshort&0x0001 =0x0000 no debug info
# xo65 library files
0 string \x6E\x61\x55\x7A xo65 library,
>4 leshort x version %d
# o65 object files
0 string \x01\x00\x6F\x36\x35 o65
>6 leshort&0x1000 =0x0000 executable,
>6 leshort&0x1000 =0x1000 object,
>5 byte x version %d,
>6 leshort&0x8000 =0x8000 65816,
>6 leshort&0x8000 =0x0000 6502,
>6 leshort&0x2000 =0x2000 32 bit,
>6 leshort&0x2000 =0x0000 16 bit,
>6 leshort&0x4000 =0x4000 page reloc,
>6 leshort&0x4000 =0x0000 byte reloc,
>6 leshort&0x0003 =0x0000 alignment 1
>6 leshort&0x0003 =0x0001 alignment 2
>6 leshort&0x0003 =0x0002 alignment 4
>6 leshort&0x0003 =0x0003 alignment 256
| {
"language": "Assembly"
} |
/* AArch64 assembler/disassembler support.
Copyright (C) 2009-2019 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef OPCODE_AARCH64_H
#define OPCODE_AARCH64_H
#include "bfd.h"
#include "bfd_stdint.h"
#include <assert.h>
#include <stdlib.h>
#ifdef __cplusplus
extern "C" {
#endif
/* The offset for pc-relative addressing is currently defined to be 0. */
#define AARCH64_PCREL_OFFSET 0
typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
/* Flag Manipulation insns. */
#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
/* FRINT[32,64][Z,X] insns. */
#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
/* SB instruction. */
#define AARCH64_FEATURE_SB 0x10000000000ULL
/* Execution and Data Prediction Restriction instructions. */
#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
/* DC CVADP. */
#define AARCH64_FEATURE_CVADP 0x40000000000ULL
/* Random Number instructions. */
#define AARCH64_FEATURE_RNG 0x80000000000ULL
/* BTI instructions. */
#define AARCH64_FEATURE_BTI 0x100000000000ULL
/* SCXTNUM_ELx. */
#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
/* ID_PFR2 instructions. */
#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
/* SSBS mechanism enabled. */
#define AARCH64_FEATURE_SSBS 0x800000000000ULL
/* Memory Tagging Extension. */
#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD)
#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
AARCH64_FEATURE_CRC \
| AARCH64_FEATURE_V8_1 \
| AARCH64_FEATURE_LSE \
| AARCH64_FEATURE_PAN \
| AARCH64_FEATURE_LOR \
| AARCH64_FEATURE_RDMA)
#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
AARCH64_FEATURE_V8_2 \
| AARCH64_FEATURE_RAS)
#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
AARCH64_FEATURE_V8_3 \
| AARCH64_FEATURE_RCPC \
| AARCH64_FEATURE_COMPNUM)
#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
AARCH64_FEATURE_V8_4 \
| AARCH64_FEATURE_DOTPROD \
| AARCH64_FEATURE_F16_FML)
#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
AARCH64_FEATURE_V8_5 \
| AARCH64_FEATURE_FLAGMANIP \
| AARCH64_FEATURE_FRINTTS \
| AARCH64_FEATURE_SB \
| AARCH64_FEATURE_PREDRES \
| AARCH64_FEATURE_CVADP \
| AARCH64_FEATURE_BTI \
| AARCH64_FEATURE_SCXTNUM \
| AARCH64_FEATURE_ID_PFR2 \
| AARCH64_FEATURE_SSBS)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
/* CPU-specific features. */
typedef unsigned long long aarch64_feature_set;
#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
((~(CPU) & (FEAT)) == 0)
#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
(((CPU) & (FEAT)) != 0)
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) | (F2); \
} \
while (0)
#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) &~ (F2); \
} \
while (0)
#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
enum aarch64_operand_class
{
AARCH64_OPND_CLASS_NIL,
AARCH64_OPND_CLASS_INT_REG,
AARCH64_OPND_CLASS_MODIFIED_REG,
AARCH64_OPND_CLASS_FP_REG,
AARCH64_OPND_CLASS_SIMD_REG,
AARCH64_OPND_CLASS_SIMD_ELEMENT,
AARCH64_OPND_CLASS_SISD_REG,
AARCH64_OPND_CLASS_SIMD_REGLIST,
AARCH64_OPND_CLASS_SVE_REG,
AARCH64_OPND_CLASS_PRED_REG,
AARCH64_OPND_CLASS_ADDRESS,
AARCH64_OPND_CLASS_IMMEDIATE,
AARCH64_OPND_CLASS_SYSTEM,
AARCH64_OPND_CLASS_COND,
};
/* Operand code that helps both parsing and coding.
Keep AARCH64_OPERANDS synced. */
enum aarch64_opnd
{
AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
AARCH64_OPND_Rd, /* Integer register as destination. */
AARCH64_OPND_Rn, /* Integer register as source. */
AARCH64_OPND_Rm, /* Integer register as source. */
AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
AARCH64_OPND_PAIRREG, /* Paired register operand. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
AARCH64_OPND_Fd, /* Floating-point Fd. */
AARCH64_OPND_Fn, /* Floating-point Fn. */
AARCH64_OPND_Fm, /* Floating-point Fm. */
AARCH64_OPND_Fa, /* Floating-point Fa. */
AARCH64_OPND_Ft, /* Floating-point Ft. */
AARCH64_OPND_Ft2, /* Floating-point Ft2. */
AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
qualifier is S_H. */
AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
structure to all lanes. */
AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
(no encoding). */
AARCH64_OPND_IMM0, /* Immediate for #0. */
AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
AARCH64_OPND_IMM, /* Immediate. */
AARCH64_OPND_IMM_2, /* Immediate. */
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
each condition flag. */
AARCH64_OPND_LIMM, /* Logical Immediate. */
AARCH64_OPND_AIMM, /* Arithmetic immediate. */
AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
AARCH64_OPND_COND, /* Standard condition as the last operand. */
AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
negative or unaligned and there is
no writeback allowed. This operand code
is only used to support the programmer-
friendly feature of using LDR/STR as the
the mnemonic name for LDUR/STUR instructions
wherever there is no ambiguity. */
AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
16) immediate. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
16) immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
AARCH64_OPND_SYSREG, /* System register operand. */
AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
Bit 14 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
Bit 22 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
Bit 14 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
Bit 22 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
Bit 14 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
Bit 22 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
Bit 14 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
Bit 22 controls S/U choice. */
AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
operand type or limits values available to an operand type.
N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
enum aarch64_opnd_qualifier
{
/* Indicating no further qualification on an operand. */
AARCH64_OPND_QLF_NIL,
/* Qualifying an operand which is a general purpose (integer) register;
indicating the operand data size or a specific register. */
AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
AARCH64_OPND_QLF_WSP, /* WSP. */
AARCH64_OPND_QLF_SP, /* SP. */
/* Qualifying an operand which is a floating-point register, a SIMD
vector element or a SIMD vector element list; indicating operand data
size or the size of each SIMD vector element in the case of a SIMD
vector element list.
These qualifiers are also used to qualify an address operand to
indicate the size of data element a load/store instruction is
accessing.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_S_B,
AARCH64_OPND_QLF_S_H,
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
/* This type qualifier has a special meaning in that it means that 4 x 1 byte
are selected by the instruction. Other than that it has no difference
with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
reasons and is an exception from normal AArch64 disassembly scheme. */
AARCH64_OPND_QLF_S_4B,
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
register list; indicating register shape.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_V_4B,
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_16B,
AARCH64_OPND_QLF_V_2H,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_8H,
AARCH64_OPND_QLF_V_2S,
AARCH64_OPND_QLF_V_4S,
AARCH64_OPND_QLF_V_1D,
AARCH64_OPND_QLF_V_2D,
AARCH64_OPND_QLF_V_1Q,
AARCH64_OPND_QLF_P_Z,
AARCH64_OPND_QLF_P_M,
/* Used in scaled signed immediate that are scaled by a Tag granule
like in stg, st2g, etc. */
AARCH64_OPND_QLF_imm_tag,
/* Constraint on value. */
AARCH64_OPND_QLF_CR, /* CRn, CRm. */
AARCH64_OPND_QLF_imm_0_7,
AARCH64_OPND_QLF_imm_0_15,
AARCH64_OPND_QLF_imm_0_31,
AARCH64_OPND_QLF_imm_0_63,
AARCH64_OPND_QLF_imm_1_32,
AARCH64_OPND_QLF_imm_1_64,
/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
or shift-ones. */
AARCH64_OPND_QLF_LSL,
AARCH64_OPND_QLF_MSL,
/* Special qualifier helping retrieve qualifier information during the
decoding time (currently not in use). */
AARCH64_OPND_QLF_RETRIEVE,
};
/* Instruction class. */
enum aarch64_insn_class
{
addsub_carry,
addsub_ext,
addsub_imm,
addsub_shift,
asimdall,
asimddiff,
asimdelem,
asimdext,
asimdimm,
asimdins,
asimdmisc,
asimdperm,
asimdsame,
asimdshf,
asimdtbl,
asisddiff,
asisdelem,
asisdlse,
asisdlsep,
asisdlso,
asisdlsop,
asisdmisc,
asisdone,
asisdpair,
asisdsame,
asisdshf,
bitfield,
branch_imm,
branch_reg,
compbranch,
condbranch,
condcmp_imm,
condcmp_reg,
condsel,
cryptoaes,
cryptosha2,
cryptosha3,
dp_1src,
dp_2src,
dp_3src,
exception,
extract,
float2fix,
float2int,
floatccmp,
floatcmp,
floatdp1,
floatdp2,
floatdp3,
floatimm,
floatsel,
ldst_immpost,
ldst_immpre,
ldst_imm9, /* immpost or immpre */
ldst_imm10, /* LDRAA/LDRAB */
ldst_pos,
ldst_regoff,
ldst_unpriv,
ldst_unscaled,
ldstexcl,
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
loadlit,
log_imm,
log_shift,
lse_atomic,
movewide,
pcreladdr,
ic_system,
sve_cpy,
sve_index,
sve_limm,
sve_misc,
sve_movprfx,
sve_pred_zm,
sve_shift_pred,
sve_shift_unpred,
sve_size_bhs,
sve_size_bhsd,
sve_size_hsd,
sve_size_sd,
testbranch,
cryptosm3,
cryptosm4,
dotproduct,
};
/* Opcode enumerators. */
enum aarch64_op
{
OP_NIL,
OP_STRB_POS,
OP_LDRB_POS,
OP_LDRSB_POS,
OP_STRH_POS,
OP_LDRH_POS,
OP_LDRSH_POS,
OP_STR_POS,
OP_LDR_POS,
OP_STRF_POS,
OP_LDRF_POS,
OP_LDRSW_POS,
OP_PRFM_POS,
OP_STURB,
OP_LDURB,
OP_LDURSB,
OP_STURH,
OP_LDURH,
OP_LDURSH,
OP_STUR,
OP_LDUR,
OP_STURV,
OP_LDURV,
OP_LDURSW,
OP_PRFUM,
OP_LDR_LIT,
OP_LDRV_LIT,
OP_LDRSW_LIT,
OP_PRFM_LIT,
OP_ADD,
OP_B,
OP_BL,
OP_MOVN,
OP_MOVZ,
OP_MOVK,
OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
OP_MOV_V, /* MOV alias for moving vector register. */
OP_ASR_IMM,
OP_LSR_IMM,
OP_LSL_IMM,
OP_BIC,
OP_UBFX,
OP_BFXIL,
OP_SBFX,
OP_SBFIZ,
OP_BFI,
OP_BFC, /* ARMv8.2. */
OP_UBFIZ,
OP_UXTB,
OP_UXTH,
OP_UXTW,
OP_CINC,
OP_CINV,
OP_CNEG,
OP_CSET,
OP_CSETM,
OP_FCVT,
OP_FCVTN,
OP_FCVTN2,
OP_FCVTL,
OP_FCVTL2,
OP_FCVTXN_S, /* Scalar version. */
OP_ROR_IMM,
OP_SXTL,
OP_SXTL2,
OP_UXTL,
OP_UXTL2,
OP_MOV_P_P,
OP_MOV_Z_P_Z,
OP_MOV_Z_V,
OP_MOV_Z_Z,
OP_MOV_Z_Zi,
OP_MOVM_P_P_P,
OP_MOVS_P_P,
OP_MOVZS_P_P_P,
OP_MOVZ_P_P_P,
OP_NOTS_P_P_P_Z,
OP_NOT_P_P_P_Z,
OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
OP_TOTAL_NUM, /* Pseudo. */
};
/* Error types. */
enum err_type
{
ERR_OK,
ERR_UND,
ERR_UNP,
ERR_NYI,
ERR_VFI,
ERR_NR_ENTRIES
};
/* Maximum number of operands an instruction can have. */
#define AARCH64_MAX_OPND_NUM 6
/* Maximum number of qualifier sequences an instruction can have. */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size. */
typedef unsigned char aarch64_opnd_qualifier_t;
/* Operand qualifier sequence typedef. */
typedef aarch64_opnd_qualifier_t \
aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
/* FIXME: improve the efficiency. */
static inline bfd_boolean
empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
{
int i;
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
return FALSE;
return TRUE;
}
/* Forward declare error reporting type. */
typedef struct aarch64_operand_error aarch64_operand_error;
/* Forward declare instruction sequence type. */
typedef struct aarch64_instr_sequence aarch64_instr_sequence;
/* Forward declare instruction definition. */
typedef struct aarch64_inst aarch64_inst;
/* This structure holds information for a particular opcode. */
struct aarch64_opcode
{
/* The name of the mnemonic. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
aarch64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
aarch64_insn mask;
/* Instruction class. */
enum aarch64_insn_class iclass;
/* Enumerator identifier. */
enum aarch64_op op;
/* Which architecture variant provides this instruction. */
const aarch64_feature_set *avariant;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
/* A list of operand qualifier code sequence. Each operand qualifier
code qualifies the corresponding operand code. Each operand
qualifier sequence specifies a valid opcode variant and related
constraint on operands. */
aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
/* Flags providing information about this instruction */
uint64_t flags;
/* Extra constraints on the instruction that the verifier checks. */
uint32_t constraints;
/* If nonzero, this operand and operand 0 are both registers and
are required to have the same register number. */
unsigned char tied_operand;
/* If non-NULL, a function to verify that a given instruction is valid. */
enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
bfd_vma, bfd_boolean, aarch64_operand_error *,
struct aarch64_instr_sequence *);
};
typedef struct aarch64_opcode aarch64_opcode;
/* Table describing all the AArch64 opcodes. */
extern aarch64_opcode aarch64_opcode_table[];
/* Opcode flags. */
#define F_ALIAS (1 << 0)
#define F_HAS_ALIAS (1 << 1)
/* Disassembly preference priority 1-3 (the larger the higher). If nothing
is specified, it is the priority 0 by default, i.e. the lowest priority. */
#define F_P1 (1 << 2)
#define F_P2 (2 << 2)
#define F_P3 (3 << 2)
/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
#define F_COND (1 << 4)
/* Instruction has the field of 'sf'. */
#define F_SF (1 << 5)
/* Instruction has the field of 'size:Q'. */
#define F_SIZEQ (1 << 6)
/* Floating-point instruction has the field of 'type'. */
#define F_FPTYPE (1 << 7)
/* AdvSIMD scalar instruction has the field of 'size'. */
#define F_SSIZE (1 << 8)
/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
#define F_T (1 << 9)
/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
#define F_GPRSIZE_IN_Q (1 << 10)
/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
#define F_LDS_SIZE (1 << 11)
/* Optional operand; assume maximum of 1 operand can be optional. */
#define F_OPD0_OPT (1 << 12)
#define F_OPD1_OPT (2 << 12)
#define F_OPD2_OPT (3 << 12)
#define F_OPD3_OPT (4 << 12)
#define F_OPD4_OPT (5 << 12)
/* Default value for the optional operand when omitted from the assembly. */
#define F_DEFAULT(X) (((X) & 0x1f) << 15)
/* Instruction that is an alias of another instruction needs to be
encoded/decoded by converting it to/from the real form, followed by
the encoding/decoding according to the rules of the real opcode.
This compares to the direct coding using the alias's information.
N.B. this flag requires F_ALIAS to be used together. */
#define F_CONV (1 << 20)
/* Use together with F_ALIAS to indicate an alias opcode is a programmer
friendly pseudo instruction available only in the assembly code (thus will
not show up in the disassembly). */
#define F_PSEUDO (1 << 21)
/* Instruction has miscellaneous encoding/decoding rules. */
#define F_MISC (1 << 22)
/* Instruction has the field of 'N'; used in conjunction with F_SF. */
#define F_N (1 << 23)
/* Opcode dependent field. */
#define F_OD(X) (((X) & 0x7) << 24)
/* Instruction has the field of 'sz'. */
#define F_LSE_SZ (1 << 27)
/* Require an exact qualifier match, even for NIL qualifiers. */
#define F_STRICT (1ULL << 28)
/* This system instruction is used to read system registers. */
#define F_SYS_READ (1ULL << 29)
/* This system instruction is used to write system registers. */
#define F_SYS_WRITE (1ULL << 30)
/* This instruction has an extra constraint on it that imposes a requirement on
subsequent instructions. */
#define F_SCAN (1ULL << 31)
/* Next bit is 32. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
#define C_SCAN_MOVPRFX (1U << 0)
/* This instruction's operation width is determined by the operand with the
largest element size. */
#define C_MAX_ELEM (1U << 1)
/* Next bit is 2. */
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
}
static inline bfd_boolean
opcode_has_alias (const aarch64_opcode *opcode)
{
return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
}
/* Priority for disassembling preference. */
static inline int
opcode_priority (const aarch64_opcode *opcode)
{
return (opcode->flags >> 2) & 0x3;
}
static inline bfd_boolean
pseudo_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
}
static inline bfd_boolean
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
return (((opcode->flags >> 12) & 0x7) == idx + 1)
? TRUE : FALSE;
}
static inline aarch64_insn
get_optional_operand_default_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 15) & 0x1f;
}
static inline unsigned int
get_opcode_dependent_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 24) & 0x7;
}
static inline bfd_boolean
opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
: FALSE;
}
struct aarch64_name_value_pair
{
const char * name;
aarch64_insn value;
};
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options [];
typedef struct
{
const char * name;
aarch64_insn value;
uint32_t flags;
} aarch64_sys_reg;
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
typedef struct
{
const char *name;
uint32_t value;
uint32_t flags ;
} aarch64_sys_ins_reg;
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_ins_reg *);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
/* Shift/extending operator kinds.
N.B. order is important; keep aarch64_operand_modifiers synced. */
enum aarch64_modifier_kind
{
AARCH64_MOD_NONE,
AARCH64_MOD_MSL,
AARCH64_MOD_ROR,
AARCH64_MOD_ASR,
AARCH64_MOD_LSR,
AARCH64_MOD_LSL,
AARCH64_MOD_UXTB,
AARCH64_MOD_UXTH,
AARCH64_MOD_UXTW,
AARCH64_MOD_UXTX,
AARCH64_MOD_SXTB,
AARCH64_MOD_SXTH,
AARCH64_MOD_SXTW,
AARCH64_MOD_SXTX,
AARCH64_MOD_MUL,
AARCH64_MOD_MUL_VL,
};
bfd_boolean
aarch64_extend_operator_p (enum aarch64_modifier_kind);
enum aarch64_modifier_kind
aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
/* Condition. */
typedef struct
{
/* A list of names with the first one as the disassembly preference;
terminated by NULL if fewer than 3. */
const char *names[4];
aarch64_insn value;
} aarch64_cond;
extern const aarch64_cond aarch64_conds[16];
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
/* Structure representing an operand. */
struct aarch64_opnd_info
{
enum aarch64_opnd type;
aarch64_opnd_qualifier_t qualifier;
int idx;
union
{
struct
{
unsigned regno;
} reg;
struct
{
unsigned int regno;
int64_t index;
} reglane;
/* e.g. LVn. */
struct
{
unsigned first_regno : 5;
unsigned num_regs : 3;
/* 1 if it is a list of reg element. */
unsigned has_index : 1;
/* Lane index; valid only when has_index is 1. */
int64_t index;
} reglist;
/* e.g. immediate or pc relative address offset. */
struct
{
int64_t value;
unsigned is_fp : 1;
} imm;
/* e.g. address in STR (register offset). */
struct
{
unsigned base_regno;
struct
{
union
{
int imm;
unsigned regno;
};
unsigned is_reg;
} offset;
unsigned pcrel : 1; /* PC-relative. */
unsigned writeback : 1;
unsigned preind : 1; /* Pre-indexed. */
unsigned postind : 1; /* Post-indexed. */
} addr;
struct
{
/* The encoding of the system register. */
aarch64_insn value;
/* The system register flags. */
uint32_t flags;
} sysreg;
const aarch64_cond *cond;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
const struct aarch64_name_value_pair *barrier;
const struct aarch64_name_value_pair *hint_option;
const struct aarch64_name_value_pair *prfop;
};
/* Operand shifter; in use when the operand is a register offset address,
add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
struct
{
enum aarch64_modifier_kind kind;
unsigned operator_present: 1; /* Only valid during encoding. */
/* Value of the 'S' field in ld/st reg offset; used only in decoding. */
unsigned amount_present: 1;
int64_t amount;
} shifter;
unsigned skip:1; /* Operand is not completed if there is a fixup needed
to be done on it. In some (but not all) of these
cases, we need to tell libopcodes to skip the
constraint checking and the encoding for this
operand, so that the libopcodes can pick up the
right opcode before the operand is fixed-up. This
flag should only be used during the
assembling/encoding. */
unsigned present:1; /* Whether this operand is present in the assembly
line; not used during the disassembly. */
};
typedef struct aarch64_opnd_info aarch64_opnd_info;
/* Structure representing an instruction.
It is used during both the assembling and disassembling. The assembler
fills an aarch64_inst after a successful parsing and then passes it to the
encoding routine to do the encoding. During the disassembling, the
disassembler calls the decoding routine to decode a binary instruction; on a
successful return, such a structure will be filled with information of the
instruction; then the disassembler uses the information to print out the
instruction. */
struct aarch64_inst
{
/* The value of the binary instruction. */
aarch64_insn value;
/* Corresponding opcode entry. */
const aarch64_opcode *opcode;
/* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
const aarch64_cond *cond;
/* Operands information. */
aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
};
/* Defining the HINT #imm values for the aarch64_hint_options. */
#define HINT_OPD_CSYNC 0x11
#define HINT_OPD_C 0x22
#define HINT_OPD_J 0x24
#define HINT_OPD_JC 0x26
#define HINT_OPD_NULL 0x00
/* Diagnosis related declaration and interface. */
/* Operand error kind enumerators.
AARCH64_OPDE_RECOVERABLE
Less severe error found during the parsing, very possibly because that
GAS has picked up a wrong instruction template for the parsing.
AARCH64_OPDE_SYNTAX_ERROR
General syntax error; it can be either a user error, or simply because
that GAS is trying a wrong instruction template.
AARCH64_OPDE_FATAL_SYNTAX_ERROR
Definitely a user syntax error.
AARCH64_OPDE_INVALID_VARIANT
No syntax error, but the operands are not a valid combination, e.g.
FMOV D0,S0
AARCH64_OPDE_UNTIED_OPERAND
The asm failed to use the same register for a destination operand
and a tied source operand.
AARCH64_OPDE_OUT_OF_RANGE
Error about some immediate value out of a valid range.
AARCH64_OPDE_UNALIGNED
Error about some immediate value not properly aligned (i.e. not being a
multiple times of a certain value).
AARCH64_OPDE_REG_LIST
Error about the register list operand having unexpected number of
registers.
AARCH64_OPDE_OTHER_ERROR
Error of the highest severity and used for any severe issue that does not
fall into any of the above categories.
The enumerators are only interesting to GAS. They are declared here (in
libopcodes) because that some errors are detected (and then notified to GAS)
by libopcodes (rather than by GAS solely).
The first three errors are only deteced by GAS while the
AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
only libopcodes has the information about the valid variants of each
instruction.
The enumerators have an increasing severity. This is helpful when there are
multiple instruction templates available for a given mnemonic name (e.g.
FMOV); this mechanism will help choose the most suitable template from which
the generated diagnostics can most closely describe the issues, if any. */
enum aarch64_operand_error_kind
{
AARCH64_OPDE_NIL,
AARCH64_OPDE_RECOVERABLE,
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
AARCH64_OPDE_UNTIED_OPERAND,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
AARCH64_OPDE_REG_LIST,
AARCH64_OPDE_OTHER_ERROR
};
/* N.B. GAS assumes that this structure work well with shallow copy. */
struct aarch64_operand_error
{
enum aarch64_operand_error_kind kind;
int index;
const char *error;
int data[3]; /* Some data for extra information. */
bfd_boolean non_fatal;
};
/* AArch64 sequence structure used to track instructions with F_SCAN
dependencies for both assembler and disassembler. */
struct aarch64_instr_sequence
{
/* The instruction that caused this sequence to be opened. */
aarch64_inst *instr;
/* The number of instructions the above instruction allows to be kept in the
sequence before an automatic close is done. */
int num_insns;
/* The instructions currently added to the sequence. */
aarch64_inst **current_insns;
/* The number of instructions already in the sequence. */
int next_insn;
};
/* Encoding entrypoint. */
extern int
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
aarch64_insn *, aarch64_opnd_qualifier_t *,
aarch64_operand_error *, aarch64_instr_sequence *);
extern const aarch64_opcode *
aarch64_replace_opcode (struct aarch64_inst *,
const aarch64_opcode *);
/* Given the opcode enumerator OP, return the pointer to the corresponding
opcode entry. */
extern const aarch64_opcode *
aarch64_get_opcode (enum aarch64_op);
/* Generate the string representation of an operand. */
extern void
aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
const aarch64_opnd_info *, int, int *, bfd_vma *,
char **);
/* Miscellaneous interface. */
extern int
aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
extern aarch64_opnd_qualifier_t
aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
const aarch64_opnd_qualifier_t, int);
extern bfd_boolean
aarch64_is_destructive_by_operands (const aarch64_opcode *);
extern int
aarch64_num_of_operands (const aarch64_opcode *);
extern int
aarch64_stack_pointer_p (const aarch64_opnd_info *);
extern int
aarch64_zero_register_p (const aarch64_opnd_info *);
extern enum err_type
aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
aarch64_operand_error *);
extern void
init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
extern unsigned char
aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
extern enum aarch64_operand_class
aarch64_get_operand_class (enum aarch64_opnd);
extern const char *
aarch64_get_operand_name (enum aarch64_opnd);
extern const char *
aarch64_get_operand_desc (enum aarch64_opnd);
extern bfd_boolean
aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
#ifdef DEBUG_AARCH64
extern int debug_dump;
extern void
aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
#define DEBUG_TRACE(M, ...) \
{ \
if (debug_dump) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#define DEBUG_TRACE_IF(C, M, ...) \
{ \
if (debug_dump && (C)) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#else /* !DEBUG_AARCH64 */
#define DEBUG_TRACE(M, ...) ;
#define DEBUG_TRACE_IF(C, M, ...) ;
#endif /* DEBUG_AARCH64 */
extern const char *const aarch64_sve_pattern_array[32];
extern const char *const aarch64_sve_prfop_array[16];
#ifdef __cplusplus
}
#endif
#endif /* OPCODE_AARCH64_H */
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -fsyntax-only -verify %s
// rdar://8914293
// We want be compatible with gcc and warn, not error.
/* expected-warning {{missing terminating}} */ #define FOO "foo
/* expected-warning {{missing terminating}} */ #define KOO 'k
| {
"language": "Assembly"
} |
#class ofEvent
<!--
_visible: True_
_advanced: False_
_istemplated: False_
_extends: of::priv::BaseEvent<of::priv::Function<T, Mutex>, Mutex>_
-->
##InlineDescription
##Description
Class for creating custom events. Also used inside oF for its own events (see ofCoreEvents).
ie: To create a new event:
~~~~{.cpp}
ofEvent<float> onVolumeChange;
~~~~
To notify an event of that type:
~~~~{.cpp}
float value = 10.0f;
ofNotifyEvent(onVolumeChange, value);
~~~~
To add a listener to that event, if the event is for example in an object called mySoundObject, and you want to register ofApp as a listener for that event:
~~~~{.cpp}
ofAddListener(mySoundObject.onVolumeChange, this, &ofApp::onVolumeChange);
~~~~
where ofApp::onVolumeChange is a function with the following signature:
~~~~{.cpp}
void onVolumeChange(float & volume);
~~~~
See the advancedEventsExample to see a complete example of how to work with events in oF.
Be careful when using events, it's a powerful structure but can also lead to really confusing code as there's no direct calls to an object.
It's important to unregister events in the destruction of listeners, if not an object that has already been destroyed can get called and the application will crash.
~~~~{.cpp}
ofRemoveListener(mySoundObject.onVolumeChange, this, &ofApp:onVolumeChange);
~~~~
Events have a private copy constructor to avoid that a copy of an object with an event gets all the registered listeners of the original. To be able to create a copy of an object that contains an event, use a pointer to an event instead of a normal var. This also means that you cannot store events directly in a vector or any other collection, the solution is the same, just use a pointer to an event.
ie:
wrong:
~~~~{.cpp}
vector< ofEvent<int> > events;
~~~~
right:
~~~~{.cpp}
vector< ofEvent<int>* > events;
~~~~
##Methods
###void add(*listener, method, priority)
<!--
_syntax: add(*listener, method, priority)_
_name: add_
_returns: void_
_returns_description: _
_parameters: TObj *listener, TMethod method, int priority_
_access: public_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void add(function, priority)
<!--
_syntax: add(function, priority)_
_name: add_
_returns: void_
_returns_description: _
_parameters: TFunction function, int priority_
_access: public_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*, f, priority)
<!--
_syntax: make_function(*, f, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: function< bool (const void *, T &) > f, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*, f, priority)
<!--
_syntax: make_function(*, f, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: function< void (const void *, T &) > f, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*listener, *, method, priority)
<!--
_syntax: make_function(*listener, *, method, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: TObj *listener, bool (TObj::*)(const void *, T &) method, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*listener, *, method, priority)
<!--
_syntax: make_function(*listener, *, method, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: TObj *listener, void (TObj::*)(const void *, T &) method, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*listener, method, priority)
<!--
_syntax: make_function(*listener, method, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: TObj *listener, bool (TObj::*)(T &) method, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(*listener, method, priority)
<!--
_syntax: make_function(*listener, method, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: TObj *listener, void (TObj::*)(T &) method, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(f, priority)
<!--
_syntax: make_function(f, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: function< bool (T &) > f, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###ofEvent::FunctionPtr make_function(f, priority)
<!--
_syntax: make_function(f, priority)_
_name: make_function_
_returns: ofEvent::FunctionPtr_
_returns_description: _
_parameters: function< void (T &) > f, int priority_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###unique_ptr<FunctionId< TObj, TMethod> > make_function_id(*listener, method)
<!--
_syntax: make_function_id(*listener, method)_
_name: make_function_id_
_returns: unique_ptr<FunctionId< TObj, TMethod> >_
_returns_description: _
_parameters: TObj *listener, TMethod method_
_access: protected_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###unique_ptr< of::priv::BaseFunctionId > make_std_function_id(&f)
<!--
_syntax: make_std_function_id(&f)_
_name: make_std_function_id_
_returns: unique_ptr< of::priv::BaseFunctionId >_
_returns_description: _
_parameters: const F &f_
_access: protected_
_version_started: 0.10.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###unique_ptr< of::priv::AbstractEventToken > newListener(*listener, method, priority)
<!--
_syntax: newListener(*listener, method, priority)_
_name: newListener_
_returns: unique_ptr< of::priv::AbstractEventToken >_
_returns_description: _
_parameters: TObj *listener, TMethod method, int priority_
_access: public_
_version_started: 0.10.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###unique_ptr< of::priv::AbstractEventToken > newListener(function, priority)
<!--
_syntax: newListener(function, priority)_
_name: newListener_
_returns: unique_ptr< of::priv::AbstractEventToken >_
_returns_description: _
_parameters: TFunction function, int priority_
_access: public_
_version_started: 0.10.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###bool notify(¶m)
<!--
_syntax: notify(¶m)_
_name: notify_
_returns: bool_
_returns_description: _
_parameters: T ¶m_
_access: public_
_version_started: 0.10.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###bool notify(*sender, ¶m)
<!--
_syntax: notify(*sender, ¶m)_
_name: notify_
_returns: bool_
_returns_description: _
_parameters: const void *sender, T ¶m_
_access: public_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void remove(*listener, method, priority)
<!--
_syntax: remove(*listener, method, priority)_
_name: remove_
_returns: void_
_returns_description: _
_parameters: TObj *listener, TMethod method, int priority_
_access: public_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
###void remove(function, priority)
<!--
_syntax: remove(function, priority)_
_name: remove_
_returns: void_
_returns_description: _
_parameters: TFunction function, int priority_
_access: public_
_version_started: 0.9.0_
_version_deprecated: _
_summary: _
_constant: False_
_static: False_
_visible: True_
_advanced: False_
-->
_inlined_description: _
_description: _
<!----------------------------------------------------------------------------->
##Variables
| {
"language": "Assembly"
} |
@ RUN: llvm-mc -triple armv7-elf -filetype asm -o - %s | FileCheck %s
@ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s \
@ RUN: | llvm-readobj -arm-attributes - | FileCheck %s --check-prefix=CHECK-OBJ
.eabi_attribute Tag_CPU_arch, 9
@CHECK: .eabi_attribute 6, 9
@CHECK-OBJ: Tag: 6
@CHECK-OBJ-NEXT: Value: 9
@CHECK-OBJ-NEXT: TagName: CPU_arch
@CHECK-OBJ-NEXT: Description: ARM v6K
.eabi_attribute Tag_ABI_align_needed, 9
@CHECK: .eabi_attribute 24, 9
@CHECK-OBJ: Tag: 24
@CHECK-OBJ-NEXT: Value: 9
@CHECK-OBJ-NEXT: TagName: ABI_align_needed
@CHECK-OBJ-NEXT: Description: 8-byte alignment, 512-byte extended alignment
.eabi_attribute Tag_ABI_align_preserved, 9
@CHECK: .eabi_attribute 25, 9
@CHECK-OBJ: Tag: 25
@CHECK-OBJ-NEXT: Value: 9
@CHECK-OBJ-NEXT: TagName: ABI_align_preserved
@CHECK-OBJ-NEXT: Description: 8-byte stack alignment, 512-byte data alignment
| {
"language": "Assembly"
} |
# Boost.Context Library Build Jamfile
# Copyright Oliver Kowalke 2009.
# Distributed under the Boost Software License, Version 1.0.
# (See accompanying file LICENSE_1_0.txt or copy at
# http://www.boost.org/LICENSE_1_0.txt)
import common ;
import feature ;
import indirect ;
import modules ;
import os ;
import toolset ;
import ../../config/checks/config : requires ;
feature.feature segmented-stacks : on : optional propagated composite ;
feature.compose <segmented-stacks>on : <define>BOOST_USE_SEGMENTED_STACKS ;
feature.feature htm : tsx : optional propagated composite ;
feature.compose <htm>tsx : <define>BOOST_USE_TSX ;
feature.feature valgrind : on : optional propagated composite ;
feature.compose <valgrind>on : <define>BOOST_USE_VALGRIND ;
project boost/context
: requirements
<target-os>windows:<define>_WIN32_WINNT=0x0601
<toolset>gcc,<segmented-stacks>on:<cxxflags>-fsplit-stack
<toolset>gcc,<segmented-stacks>on:<cxxflags>-DBOOST_USE_SEGMENTED_STACKS
<toolset>gcc,<segmented-stacks>on:<linkflags>"-static-libgcc"
<toolset>clang,<segmented-stacks>on:<cxxflags>-fsplit-stack
<toolset>clang,<segmented-stacks>on:<cxxflags>-DBOOST_USE_SEGMENTED_STACKS
<toolset>clang,<segmented-stacks>on:<linkflags>"-static-libgcc"
<toolset>intel,<link>shared:<define>BOOST_CONTEXT_EXPORT=EXPORT
<toolset>intel,<link>static:<define>BOOST_CONTEXT_EXPORT=
<toolset>msvc,<link>shared:<define>BOOST_CONTEXT_EXPORT=EXPORT
<toolset>msvc,<link>static:<define>BOOST_CONTEXT_EXPORT=
<toolset>clang-win,<link>shared:<define>BOOST_CONTEXT_EXPORT=EXPORT
<toolset>clang-win,<link>static:<define>BOOST_CONTEXT_EXPORT=
<link>shared:<define>BOOST_CONTEXT_DYN_LINK=1
<define>BOOST_CONTEXT_SOURCE
<threading>multi
: usage-requirements
<link>shared:<define>BOOST_CONTEXT_DYN_LINK=1
<optimization>speed:<define>BOOST_DISABLE_ASSERTS
<variant>release:<define>BOOST_DISABLE_ASSERTS
: source-location ../src
;
local rule default_binary_format ( )
{
local tmp = elf ;
if [ os.name ] = "NT" { tmp = pe ; }
else if [ os.name ] = "CYGWIN" { tmp = pe ; }
else if [ os.name ] = "AIX" { tmp = xcoff ; }
else if [ os.name ] = "MACOSX" { tmp = mach-o ; }
return $(tmp) ;
}
feature.feature binary-format
: elf
mach-o
pe
xcoff
: propagated
;
feature.set-default binary-format : [ default_binary_format ] ;
local rule default_abi ( )
{
local tmp = sysv ;
if [ os.name ] = "NT" { tmp = ms ; }
else if [ os.name ] = "CYGWIN" { tmp = ms ; }
else if [ os.platform ] = "ARM" { tmp = aapcs ; }
else if [ os.platform ] = "MIPS" { tmp = o32 ; }
return $(tmp) ;
}
feature.feature abi
: aapcs
eabi
ms
n32
n64
o32
o64
sysv
x32
: propagated
;
feature.set-default abi : [ default_abi ] ;
feature.feature context-impl
: fcontext
ucontext
winfib
: propagated
composite
;
feature.set-default context-impl : fcontext ;
feature.compose <context-impl>ucontext : <define>BOOST_USE_UCONTEXT ;
feature.compose <context-impl>winfib : <define>BOOST_USE_WINFIB ;
# ARM
# ARM/AAPCS/ELF
alias asm_sources
: asm/make_arm_aapcs_elf_gas.S
asm/jump_arm_aapcs_elf_gas.S
asm/ontop_arm_aapcs_elf_gas.S
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_arm_aapcs_elf_gas.S
asm/jump_arm_aapcs_elf_gas.S
asm/ontop_arm_aapcs_elf_gas.S
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>elf
<toolset>gcc
;
alias asm_sources
: asm/make_arm_aapcs_elf_gas.S
asm/jump_arm_aapcs_elf_gas.S
asm/ontop_arm_aapcs_elf_gas.S
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>elf
<toolset>qcc
;
# ARM/AAPCS/MACH-O
alias asm_sources
: asm/make_arm_aapcs_macho_gas.S
asm/jump_arm_aapcs_macho_gas.S
asm/ontop_arm_aapcs_macho_gas.S
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>mach-o
<toolset>clang
;
alias asm_sources
: asm/make_arm_aapcs_macho_gas.S
asm/jump_arm_aapcs_macho_gas.S
asm/ontop_arm_aapcs_macho_gas.S
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>mach-o
<toolset>darwin
;
# ARM/AAPCS/PE
alias asm_sources
: asm/make_arm_aapcs_pe_armasm.asm
asm/jump_arm_aapcs_pe_armasm.asm
asm/ontop_arm_aapcs_pe_armasm.asm
untested.cpp
: <abi>aapcs
<address-model>32
<architecture>arm
<binary-format>pe
<toolset>msvc
;
# ARM64
# ARM64/AAPCS/ELF
alias asm_sources
: asm/make_arm64_aapcs_elf_gas.S
asm/jump_arm64_aapcs_elf_gas.S
asm/ontop_arm64_aapcs_elf_gas.S
: <abi>aapcs
<address-model>64
<architecture>arm
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_arm64_aapcs_elf_gas.S
asm/jump_arm64_aapcs_elf_gas.S
asm/ontop_arm64_aapcs_elf_gas.S
: <abi>aapcs
<address-model>64
<architecture>arm
<binary-format>elf
<toolset>gcc
;
# ARM64/AAPCS/MACH-O
alias asm_sources
: asm/make_arm64_aapcs_macho_gas.S
asm/jump_arm64_aapcs_macho_gas.S
asm/ontop_arm64_aapcs_macho_gas.S
: <abi>aapcs
<address-model>64
<architecture>arm
<binary-format>mach-o
<toolset>clang
;
alias asm_sources
: asm/make_arm64_aapcs_macho_gas.S
asm/jump_arm64_aapcs_macho_gas.S
asm/ontop_arm64_aapcs_macho_gas.S
: <abi>aapcs
<address-model>64
<architecture>arm
<binary-format>mach-o
<toolset>darwin
;
# MIPS
# MIPS32/O32/ELF
alias asm_sources
: asm/make_mips32_o32_elf_gas.S
asm/jump_mips32_o32_elf_gas.S
asm/ontop_mips32_o32_elf_gas.S
: <abi>o32
<address-model>32
<architecture>mips1
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_mips32_o32_elf_gas.S
asm/jump_mips32_o32_elf_gas.S
asm/ontop_mips32_o32_elf_gas.S
: <abi>o32
<address-model>32
<architecture>mips1
<binary-format>elf
<toolset>gcc
;
# MIPS64/N64/ELF
alias asm_sources
: asm/make_mips64_n64_elf_gas.S
asm/jump_mips64_n64_elf_gas.S
asm/ontop_mips64_n64_elf_gas.S
: <abi>n64
<address-model>64
<architecture>mips1
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_mips64_n64_elf_gas.S
asm/jump_mips64_n64_elf_gas.S
asm/ontop_mips64_n64_elf_gas.S
: <abi>n64
<address-model>64
<architecture>mips1
<binary-format>elf
<toolset>gcc
;
# POWERPC_32
# POWERPC_32/SYSV/ELF
alias asm_sources
: asm/make_ppc32_sysv_elf_gas.S
asm/jump_ppc32_sysv_elf_gas.S
asm/ontop_ppc32_sysv_elf_gas.S
asm/tail_ppc32_sysv_elf_gas.cpp
: <abi>sysv
<address-model>32
<architecture>power
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_ppc32_sysv_elf_gas.S
asm/jump_ppc32_sysv_elf_gas.S
asm/ontop_ppc32_sysv_elf_gas.S
asm/tail_ppc32_sysv_elf_gas.cpp
: <abi>sysv
<address-model>32
<architecture>power
<binary-format>elf
<toolset>gcc
;
alias asm_sources
: asm/make_ppc32_sysv_macho_gas.S
asm/jump_ppc32_sysv_macho_gas.S
asm/ontop_ppc32_sysv_macho_gas.S
: <abi>sysv
<address-model>32
<architecture>power
<binary-format>mach-o
<toolset>darwin
;
#POWERPC_32/SYSV/XCOFF
alias asm_sources
: asm/make_ppc32_sysv_xcoff_gas.S
asm/jump_ppc32_sysv_xcoff_gas.S
asm/ontop_ppc32_sysv_xcoff_gas.S
: <abi>sysv
<address-model>32
<architecture>power
<binary-format>xcoff
<toolset>clang
;
alias asm_sources
: asm/make_ppc32_sysv_xcoff_gas.S
asm/jump_ppc32_sysv_xcoff_gas.S
asm/ontop_ppc32_sysv_xcoff_gas.S
: <abi>sysv
<address-model>32
<architecture>power
<binary-format>xcoff
<toolset>gcc
;
# POWERPC_64
# POWERPC_64/SYSV/ELF
alias asm_sources
: asm/make_ppc64_sysv_elf_gas.S
asm/jump_ppc64_sysv_elf_gas.S
asm/ontop_ppc64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_ppc64_sysv_elf_gas.S
asm/jump_ppc64_sysv_elf_gas.S
asm/ontop_ppc64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>elf
<toolset>gcc
;
# POWERPC_64/SYSV/MACH-O
alias asm_sources
: asm/make_ppc64_sysv_macho_gas.S
asm/jump_ppc64_sysv_macho_gas.S
asm/ontop_ppc64_sysv_macho_gas.S
untested.cpp
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>mach-o
<toolset>clang
;
alias asm_sources
: asm/make_ppc64_sysv_macho_gas.S
asm/jump_ppc64_sysv_macho_gas.S
asm/ontop_ppc64_sysv_macho_gas.S
untested.cpp
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>mach-o
<toolset>darwin
;
# POWERPC_64/SYSV/XCOFF
alias asm_sources
: asm/make_ppc64_sysv_xcoff_gas.S
asm/jump_ppc64_sysv_xcoff_gas.S
asm/ontop_ppc64_sysv_xcoff_gas.S
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>xcoff
<toolset>clang
;
alias asm_sources
: asm/make_ppc64_sysv_xcoff_gas.S
asm/jump_ppc64_sysv_xcoff_gas.S
asm/ontop_ppc64_sysv_xcoff_gas.S
: <abi>sysv
<address-model>64
<architecture>power
<binary-format>xcoff
<toolset>gcc
;
# POWERPC universal
# POWERPC_32_64/SYSV/MACH-O
alias asm_sources
: asm/make_ppc32_ppc64_sysv_macho_gas.S
asm/jump_ppc32_ppc64_sysv_macho_gas.S
asm/ontop_ppc32_ppc64_sysv_macho_gas.S
: <abi>sysv
<address-model>32_64
<architecture>power
<binary-format>mach-o
;
# RISCV64
# RISCV64/SYSV/ELF
alias asm_sources
: asm/make_riscv64_sysv_elf_gas.S
asm/jump_riscv64_sysv_elf_gas.S
asm/ontop_riscv64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>riscv
<binary-format>elf
<toolset>gcc
;
# S390X
# S390X/SYSV/ELF
alias asm_sources
: asm/make_s390x_sysv_elf_gas.S
asm/jump_s390x_sysv_elf_gas.S
asm/ontop_s390x_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>s390x
<binary-format>elf
<toolset>gcc
;
# X86
# X86/SYSV/ELF
alias asm_sources
: asm/make_i386_sysv_elf_gas.S
asm/jump_i386_sysv_elf_gas.S
asm/ontop_i386_sysv_elf_gas.S
: <abi>sysv
<address-model>32
<architecture>x86
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_i386_sysv_elf_gas.S
asm/jump_i386_sysv_elf_gas.S
asm/ontop_i386_sysv_elf_gas.S
: <abi>sysv
<address-model>32
<architecture>x86
<binary-format>elf
<toolset>gcc
;
alias asm_sources
: asm/make_i386_sysv_elf_gas.S
asm/jump_i386_sysv_elf_gas.S
asm/ontop_i386_sysv_elf_gas.S
: <abi>sysv
<address-model>32
<architecture>x86
<binary-format>elf
<toolset>intel
;
# X86/SYSV/MACH-O
alias asm_sources
: asm/make_i386_sysv_macho_gas.S
asm/jump_i386_sysv_macho_gas.S
asm/ontop_i386_sysv_macho_gas.S
: <abi>sysv
<address-model>32
<architecture>x86
<binary-format>mach-o
<toolset>clang
;
alias asm_sources
: asm/make_i386_sysv_macho_gas.S
asm/jump_i386_sysv_macho_gas.S
asm/ontop_i386_sysv_macho_gas.S
: <abi>sysv
<address-model>32
<architecture>x86
<binary-format>mach-o
<toolset>darwin
;
# X86/MS/PE
alias asm_sources
: asm/make_i386_ms_pe_gas.asm
asm/jump_i386_ms_pe_gas.asm
asm/ontop_i386_ms_pe_gas.asm
dummy.cpp
: <abi>ms
<address-model>32
<architecture>x86
<binary-format>pe
<toolset>clang
;
alias asm_sources
: asm/make_i386_ms_pe_masm.asm
asm/jump_i386_ms_pe_masm.asm
asm/ontop_i386_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>32
<architecture>x86
<binary-format>pe
<toolset>clang-win
;
alias asm_sources
: asm/make_i386_ms_pe_gas.asm
asm/jump_i386_ms_pe_gas.asm
asm/ontop_i386_ms_pe_gas.asm
dummy.cpp
: <abi>ms
<address-model>32
<architecture>x86
<binary-format>pe
<toolset>gcc
;
alias asm_sources
: asm/make_i386_ms_pe_masm.asm
asm/jump_i386_ms_pe_masm.asm
asm/ontop_i386_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>32
<architecture>x86
<binary-format>pe
<toolset>intel
;
alias asm_sources
: asm/make_i386_ms_pe_masm.asm
asm/jump_i386_ms_pe_masm.asm
asm/ontop_i386_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>32
<architecture>x86
<binary-format>pe
<toolset>msvc
;
# X86_64
# X86_64/SYSV/ELF
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>gcc
;
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>intel
;
# X86_64/SYSV/MACH-O
alias asm_sources
: asm/make_x86_64_sysv_macho_gas.S
asm/jump_x86_64_sysv_macho_gas.S
asm/ontop_x86_64_sysv_macho_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>mach-o
<toolset>clang
;
alias asm_sources
: asm/make_x86_64_sysv_macho_gas.S
asm/jump_x86_64_sysv_macho_gas.S
asm/ontop_x86_64_sysv_macho_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>mach-o
<toolset>darwin
;
alias asm_sources
: asm/make_x86_64_sysv_macho_gas.S
asm/jump_x86_64_sysv_macho_gas.S
asm/ontop_x86_64_sysv_macho_gas.S
: <abi>sysv
<address-model>64
<architecture>x86
<binary-format>mach-o
<toolset>intel
;
# X86_64/MS/PE
alias asm_sources
: asm/make_x86_64_ms_pe_gas.asm
asm/jump_x86_64_ms_pe_gas.asm
asm/ontop_x86_64_ms_pe_gas.asm
dummy.cpp
: <abi>ms
<address-model>64
<architecture>x86
<binary-format>pe
<toolset>clang
;
alias asm_sources
: asm/make_x86_64_ms_pe_masm.asm
asm/jump_x86_64_ms_pe_masm.asm
asm/ontop_x86_64_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>64
<architecture>x86
<binary-format>pe
<toolset>clang-win
;
alias asm_sources
: asm/make_x86_64_ms_pe_gas.asm
asm/jump_x86_64_ms_pe_gas.asm
asm/ontop_x86_64_ms_pe_gas.asm
dummy.cpp
: <abi>ms
<address-model>64
<architecture>x86
<binary-format>pe
<toolset>gcc
;
alias asm_sources
: asm/make_x86_64_ms_pe_masm.asm
asm/jump_x86_64_ms_pe_masm.asm
asm/ontop_x86_64_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>64
<architecture>x86
<binary-format>pe
<toolset>intel
;
alias asm_sources
: asm/make_x86_64_ms_pe_masm.asm
asm/jump_x86_64_ms_pe_masm.asm
asm/ontop_x86_64_ms_pe_masm.asm
dummy.cpp
: <abi>ms
<address-model>64
<architecture>x86
<binary-format>pe
<toolset>msvc
;
# X86_64/SYSV/X32
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>x32
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>clang
;
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>x32
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>gcc
;
alias asm_sources
: asm/make_x86_64_sysv_elf_gas.S
asm/jump_x86_64_sysv_elf_gas.S
asm/ontop_x86_64_sysv_elf_gas.S
: <abi>x32
<address-model>64
<architecture>x86
<binary-format>elf
<toolset>intel
;
#X86 universal
alias asm_sources
: asm/make_i386_x86_64_sysv_macho_gas.S
asm/jump_i386_x86_64_sysv_macho_gas.S
asm/ontop_i386_x86_64_sysv_macho_gas.S
: <abi>sysv
<address-model>32_64
<architecture>x86
<binary-format>mach-o
;
# COMBINED
alias asm_sources
: asm/make_combined_sysv_macho_gas.S
asm/jump_combined_sysv_macho_gas.S
asm/ontop_combined_sysv_macho_gas.S
: <abi>sysv
<architecture>combined
<binary-format>mach-o
;
explicit asm_sources ;
# fcontext_t
alias impl_sources
: asm_sources
: <context-impl>fcontext
;
# ucontext_t
alias impl_sources
: continuation.cpp
fiber.cpp
: <context-impl>ucontext
[ requires cxx11_auto_declarations
cxx11_constexpr
cxx11_defaulted_functions
cxx11_final
cxx11_hdr_thread
cxx11_hdr_tuple
cxx11_lambdas
cxx11_noexcept
cxx11_nullptr
cxx11_rvalue_references
cxx11_template_aliases
cxx11_thread_local
cxx11_variadic_templates ]
;
# WinFiber
alias impl_sources
: continuation.cpp
fiber.cpp
: <context-impl>winfib
[ requires cxx11_auto_declarations
cxx11_constexpr
cxx11_defaulted_functions
cxx11_final
cxx11_hdr_thread
cxx11_hdr_tuple
cxx11_lambdas
cxx11_noexcept
cxx11_nullptr
cxx11_rvalue_references
cxx11_template_aliases
cxx11_thread_local
cxx11_variadic_templates ]
;
explicit impl_sources ;
obj cxx11_hdr_mutex_check : ../build/cxx11_hdr_mutex.cpp ;
explicit cxx11_hdr_mutex_check ;
local cxx11_mutex = [ check-target-builds
cxx11_hdr_mutex_check "C++11 mutex"
:
: <library>/boost/thread//boost_thread
] ;
alias stack_traits_sources
: windows/stack_traits.cpp
: <target-os>windows
:
: $(cxx11_mutex)
;
alias stack_traits_sources
: posix/stack_traits.cpp
:
:
: $(cxx11_mutex)
;
explicit stack_traits_sources ;
lib boost_context
: impl_sources
stack_traits_sources
;
boost-install boost_context ;
| {
"language": "Assembly"
} |
.segment "CODE"
; ----------------------------------------------------------------------------
; "RUN" COMMAND
; ----------------------------------------------------------------------------
RUN:
bne L27CF
jmp SETPTRS
L27CF:
jsr CLEARC
jmp L27E9
; ----------------------------------------------------------------------------
; "GOSUB" STATEMENT
;
; LEAVES 7 BYTES ON STACK:
; 2 -- RETURN ADDRESS (NEWSTT)
; 2 -- TXTPTR
; 2 -- LINE #
; 1 -- GOSUB TOKEN
; ----------------------------------------------------------------------------
GOSUB:
lda #$03
jsr CHKMEM
lda TXTPTR+1
pha
lda TXTPTR
pha
lda CURLIN+1
pha
lda CURLIN
pha
lda #TOKEN_GOSUB
pha
L27E9:
jsr CHRGOT
jsr GOTO
jmp NEWSTT
; ----------------------------------------------------------------------------
; "GOTO" STATEMENT
; ALSO USED BY "RUN" AND "GOSUB"
; ----------------------------------------------------------------------------
GOTO:
jsr LINGET
jsr REMN
lda CURLIN+1
cmp LINNUM+1
bcs L2809
tya
sec
adc TXTPTR
ldx TXTPTR+1
bcc L280D
inx
bcs L280D
L2809:
lda TXTTAB
ldx TXTTAB+1
L280D:
.ifdef KBD
jsr LF457
bne UNDERR
.else
jsr FL1
bcc UNDERR
.endif
lda LOWTRX
sbc #$01
sta TXTPTR
lda LOWTRX+1
sbc #$00
sta TXTPTR+1
L281E:
rts
; ----------------------------------------------------------------------------
; "POP" AND "RETURN" STATEMENTS
; ----------------------------------------------------------------------------
POP:
bne L281E
lda #$FF
.ifdef CONFIG_2A
sta FORPNT+1 ; bugfix, wrong in AppleSoft II
.else
sta FORPNT
.endif
jsr GTFORPNT
txs
cmp #TOKEN_GOSUB
beq RETURN
ldx #ERR_NOGOSUB
.byte $2C
UNDERR:
ldx #ERR_UNDEFSTAT
jmp ERROR
; ----------------------------------------------------------------------------
SYNERR2:
jmp SYNERR
; ----------------------------------------------------------------------------
RETURN:
pla
pla
sta CURLIN
pla
sta CURLIN+1
pla
sta TXTPTR
pla
sta TXTPTR+1
; ----------------------------------------------------------------------------
; "DATA" STATEMENT
; EXECUTED BY SKIPPING TO NEXT COLON OR EOL
; ----------------------------------------------------------------------------
DATA:
jsr DATAN
; ----------------------------------------------------------------------------
; ADD (Y) TO TXTPTR
; ----------------------------------------------------------------------------
ADDON:
tya
clc
adc TXTPTR
sta TXTPTR
bcc L2852
inc TXTPTR+1
L2852:
rts
; ----------------------------------------------------------------------------
; SCAN AHEAD TO NEXT ":" OR EOL
; ----------------------------------------------------------------------------
DATAN:
ldx #$3A
.byte $2C
REMN:
ldx #$00
stx CHARAC
ldy #$00
sty ENDCHR
L285E:
lda ENDCHR
ldx CHARAC
sta CHARAC
stx ENDCHR
L2866:
lda (TXTPTR),y
beq L2852
cmp ENDCHR
beq L2852
iny
cmp #$22
.ifndef CONFIG_11
beq L285E; old: swap & cont is faster
bne L2866
.else
bne L2866; new: cont is faster
beq L285E
.endif
; ----------------------------------------------------------------------------
; "IF" STATEMENT
; ----------------------------------------------------------------------------
IF:
jsr FRMEVL
jsr CHRGOT
cmp #TOKEN_GOTO
beq L2884
lda #TOKEN_THEN
jsr SYNCHR
L2884:
lda FAC
bne L288D
; ----------------------------------------------------------------------------
; "REM" STATEMENT, OR FALSE "IF" STATEMENT
; ----------------------------------------------------------------------------
REM:
jsr REMN
beq ADDON
L288D:
jsr CHRGOT
bcs L2895
jmp GOTO
L2895:
jmp EXECUTE_STATEMENT
; ----------------------------------------------------------------------------
; "ON" STATEMENT
;
; ON <EXP> GOTO <LIST>
; ON <EXP> GOSUB <LIST>
; ----------------------------------------------------------------------------
ON:
jsr GETBYT
pha
cmp #TOKEN_GOSUB
beq L28A4
L28A0:
cmp #TOKEN_GOTO
bne SYNERR2
L28A4:
dec FAC_LAST
bne L28AC
pla
jmp EXECUTE_STATEMENT1
L28AC:
jsr CHRGET
jsr LINGET
cmp #$2C
beq L28A4
pla
L28B7:
rts
| {
"language": "Assembly"
} |
config BR2_PACKAGE_TEKUI
bool "tekui"
depends on !BR2_STATIC_LIBS
depends on BR2_PACKAGE_HAS_LUAINTERPRETER
depends on BR2_TOOLCHAIN_HAS_THREADS
select BR2_PACKAGE_FREETYPE
select BR2_PACKAGE_LUAFILESYSTEM # runtime only
select BR2_PACKAGE_LUAEXPAT # runtime only
select BR2_PACKAGE_LUASOCKET # runtime only
select BR2_PACKAGE_LUAPOSIX # runtime only
help
TekUI is a small, freestanding and portable graphical user interface
(GUI) toolkit written in Lua and C. It was initially developed for
the X Window System and has been ported to DirectFB, Windows, Nano-X
and a raw framebuffer since
http://tekui.neoscientists.org/
comment "tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library"
depends on !BR2_PACKAGE_HAS_LUAINTERPRETER || !BR2_TOOLCHAIN_HAS_THREADS || \
BR2_STATIC_LIBS
| {
"language": "Assembly"
} |
// RUN: %clang -mmmx -target i386-unknown-unknown -emit-llvm -S %s -o - | FileCheck %s
// <rdar://problem/9091220>
#include <mmintrin.h>
// CHECK: { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
void foo(long long fill) {
__m64 vfill = _mm_cvtsi64_m64(fill);
__m64 v1, v2, v3, v4, v5, v6, v7;
__asm__ __volatile__ (
"\tmovq %7, %0\n"
"\tmovq %7, %1\n"
"\tmovq %7, %2\n"
"\tmovq %7, %3\n"
"\tmovq %7, %4\n"
"\tmovq %7, %5\n"
"\tmovq %7, %6"
: "=&y" (v1), "=&y" (v2), "=&y" (v3),
"=&y" (v4), "=&y" (v5), "=&y" (v6), "=y" (v7)
: "y" (vfill));
}
| {
"language": "Assembly"
} |
# arm testcase for ldmia $rb!,{$rlist}
# mach: unfinished
.include "testutils.inc"
start
.global ldmia
ldmia:
ldmia r0!,{0}
pass
| {
"language": "Assembly"
} |
# @Author: Tom Link (micathom AT gmail com)
# @License: GPL (see http://www.gnu.org/licenses/gpl.txt)
# @Revision: 14
def crc_vim_table
tbl = [0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419,
0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4,
0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07,
0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856,
0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4,
0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3,
0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a,
0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599,
0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190,
0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f,
0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e,
0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed,
0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3,
0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a,
0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5,
0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010,
0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17,
0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6,
0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615,
0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344,
0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a,
0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1,
0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c,
0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef,
0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe,
0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31,
0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c,
0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b,
0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1,
0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278,
0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7,
0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66,
0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605,
0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8,
0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b,
0x2d02ef8d]
tbl.map! do |num|
b = "%b" % num
bits = b.split(//)
bits.map! {|b| b.to_i}
bits.reverse
end
VIM::command("let @t = '#{tbl.inspect}'")
end
| {
"language": "Assembly"
} |
;
; jmemdosa.asm
;
; Copyright (C) 1992, Thomas G. Lane.
; This file is part of the Independent JPEG Group's software.
; For conditions of distribution and use, see the accompanying README file.
;
; This file contains low-level interface routines to support the MS-DOS
; backing store manager (jmemdos.c). Routines are provided to access disk
; files through direct DOS calls, and to access XMS and EMS drivers.
;
; This file should assemble with Microsoft's MASM or any compatible
; assembler (including Borland's Turbo Assembler). If you haven't got
; a compatible assembler, better fall back to jmemansi.c or jmemname.c.
;
; To minimize dependence on the C compiler's register usage conventions,
; we save and restore all 8086 registers, even though most compilers only
; require SI,DI,DS to be preserved. Also, we use only 16-bit-wide return
; values, which everybody returns in AX.
;
; Based on code contributed by Ge' Weijers.
;
JMEMDOSA_TXT segment byte public 'CODE'
assume cs:JMEMDOSA_TXT
public _jdos_open
public _jdos_close
public _jdos_seek
public _jdos_read
public _jdos_write
public _jxms_getdriver
public _jxms_calldriver
public _jems_available
public _jems_calldriver
;
; short far jdos_open (short far * handle, char far * filename)
;
; Create and open a temporary file
;
_jdos_open proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov cx,0 ; normal file attributes
lds dx,dword ptr [bp+10] ; get filename pointer
mov ah,3ch ; create file
int 21h
jc open_err ; if failed, return error code
lds bx,dword ptr [bp+6] ; get handle pointer
mov word ptr [bx],ax ; save the handle
xor ax,ax ; return zero for OK
open_err: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jdos_open endp
;
; short far jdos_close (short handle)
;
; Close the file handle
;
_jdos_close proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov bx,word ptr [bp+6] ; file handle
mov ah,3eh ; close file
int 21h
jc close_err ; if failed, return error code
xor ax,ax ; return zero for OK
close_err: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jdos_close endp
;
; short far jdos_seek (short handle, long offset)
;
; Set file position
;
_jdos_seek proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov bx,word ptr [bp+6] ; file handle
mov dx,word ptr [bp+8] ; LS offset
mov cx,word ptr [bp+10] ; MS offset
mov ax,4200h ; absolute seek
int 21h
jc seek_err ; if failed, return error code
xor ax,ax ; return zero for OK
seek_err: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jdos_seek endp
;
; short far jdos_read (short handle, void far * buffer, unsigned short count)
;
; Read from file
;
_jdos_read proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov bx,word ptr [bp+6] ; file handle
lds dx,dword ptr [bp+8] ; buffer address
mov cx,word ptr [bp+12] ; number of bytes
mov ah,3fh ; read file
int 21h
jc read_err ; if failed, return error code
cmp ax,word ptr [bp+12] ; make sure all bytes were read
je read_ok
mov ax,1 ; else return 1 for not OK
jmp short read_err
read_ok: xor ax,ax ; return zero for OK
read_err: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jdos_read endp
;
; short far jdos_write (short handle, void far * buffer, unsigned short count)
;
; Write to file
;
_jdos_write proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov bx,word ptr [bp+6] ; file handle
lds dx,dword ptr [bp+8] ; buffer address
mov cx,word ptr [bp+12] ; number of bytes
mov ah,40h ; write file
int 21h
jc write_err ; if failed, return error code
cmp ax,word ptr [bp+12] ; make sure all bytes written
je write_ok
mov ax,1 ; else return 1 for not OK
jmp short write_err
write_ok: xor ax,ax ; return zero for OK
write_err: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jdos_write endp
;
; void far jxms_getdriver (XMSDRIVER far *)
;
; Get the address of the XMS driver, or NULL if not available
;
_jxms_getdriver proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov ax,4300h ; call multiplex interrupt with
int 2fh ; a magic cookie, hex 4300
cmp al,80h ; AL should contain hex 80
je xmsavail
xor dx,dx ; no XMS driver available
xor ax,ax ; return a nil pointer
jmp short xmsavail_done
xmsavail: mov ax,4310h ; fetch driver address with
int 2fh ; another magic cookie
mov dx,es ; copy address to dx:ax
mov ax,bx
xmsavail_done: les bx,dword ptr [bp+6] ; get pointer to return value
mov word ptr es:[bx],ax
mov word ptr es:[bx+2],dx
pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jxms_getdriver endp
;
; void far jxms_calldriver (XMSDRIVER, XMScontext far *)
;
; The XMScontext structure contains values for the AX,DX,BX,SI,DS registers.
; These are loaded, the XMS call is performed, and the new values of the
; AX,DX,BX registers are written back to the context structure.
;
_jxms_calldriver proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
les bx,dword ptr [bp+10] ; get XMScontext pointer
mov ax,word ptr es:[bx] ; load registers
mov dx,word ptr es:[bx+2]
mov si,word ptr es:[bx+6]
mov ds,word ptr es:[bx+8]
mov bx,word ptr es:[bx+4]
call dword ptr [bp+6] ; call the driver
mov cx,bx ; save returned BX for a sec
les bx,dword ptr [bp+10] ; get XMScontext pointer
mov word ptr es:[bx],ax ; put back ax,dx,bx
mov word ptr es:[bx+2],dx
mov word ptr es:[bx+4],cx
pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jxms_calldriver endp
;
; short far jems_available (void)
;
; Have we got an EMS driver? (this comes straight from the EMS 4.0 specs)
;
_jems_available proc far
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
mov ax,3567h ; get interrupt vector 67h
int 21h
push cs
pop ds
mov di,000ah ; check offs 10 in returned seg
lea si,ASCII_device_name ; against literal string
mov cx,8
cld
repe cmpsb
jne no_ems
mov ax,1 ; match, it's there
jmp short avail_done
no_ems: xor ax,ax ; it's not there
avail_done: pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
ret
ASCII_device_name db "EMMXXXX0"
_jems_available endp
;
; void far jems_calldriver (EMScontext far *)
;
; The EMScontext structure contains values for the AX,DX,BX,SI,DS registers.
; These are loaded, the EMS trap is performed, and the new values of the
; AX,DX,BX registers are written back to the context structure.
;
_jems_calldriver proc far
push bp ; linkage
mov bp,sp
push si ; save all registers for safety
push di
push bx
push cx
push dx
push es
push ds
les bx,dword ptr [bp+6] ; get EMScontext pointer
mov ax,word ptr es:[bx] ; load registers
mov dx,word ptr es:[bx+2]
mov si,word ptr es:[bx+6]
mov ds,word ptr es:[bx+8]
mov bx,word ptr es:[bx+4]
int 67h ; call the EMS driver
mov cx,bx ; save returned BX for a sec
les bx,dword ptr [bp+6] ; get EMScontext pointer
mov word ptr es:[bx],ax ; put back ax,dx,bx
mov word ptr es:[bx+2],dx
mov word ptr es:[bx+4],cx
pop ds ; restore registers and exit
pop es
pop dx
pop cx
pop bx
pop di
pop si
pop bp
ret
_jems_calldriver endp
JMEMDOSA_TXT ends
end
| {
"language": "Assembly"
} |
// rdar://problem/23727705:
// RUN-DISABLED: %target-swift-frontend -O %s -disable-llvm-optzns -emit-ir -g -o - | %FileCheck %s
import StdlibUnittest
// CHECK: define {{.*}}i1 {{.*}}4main4sort
// CHECK: call void @llvm.dbg.value(metadata i8*{{.*}}, metadata ![[A:.*]], metadata ![[P1:.*]])
// CHECK: call void @llvm.dbg.value(metadata i{{[0-9]+}} {{.*}}, metadata ![[A]], metadata ![[P2:.*]])
// CHECK: call void @llvm.dbg.value(metadata i{{[0-9]+}} {{.*}}, metadata ![[A]], metadata ![[P3:.*]])
// CHECK: call void @llvm.dbg.value(metadata i8*{{.*}}, metadata ![[B:.*]], metadata ![[P1]])
// CHECK: call void @llvm.dbg.value(metadata i{{[0-9]+}} {{.*}}, metadata ![[B]], metadata ![[P2]])
// CHECK: call void @llvm.dbg.value(metadata i{{[0-9]+}} {{.*}}, metadata ![[B]], metadata ![[P3]])
// CHECK-DAG: ![[A]] = !DILocalVariable(name: "a",{{.*}} line: 17
// CHECK-DAG: ![[B]] = !DILocalVariable(name: "b",{{.*}} line: 17
// CHECK-DAG: ![[P1]] = !DIExpression(DW_OP_bit_piece, 0, {{(32|64)}})
// CHECK-DAG: ![[P2]] = !DIExpression(DW_OP_bit_piece, {{(32, 32|64, 64)}})
// CHECK-DAG: ![[P3]] = !DIExpression(DW_OP_bit_piece, {{(64, 32|128, 64)}})
public func sort(_ a: String, b: String) -> Bool {
_blackHole("Sorting..\(a) & \(b)")
return (a < b)
}
public func demo() {
let names = ["Sean", "Barry", "Kate"]
let sortedNames = names.sorted(by: sort)
var sortedNamesAsString : String = String()
for name in sortedNames {
sortedNamesAsString += ("\(name), ")
}
_blackHole(sortedNamesAsString)
}
demo()
// At -O0, we should have a single aggregate argument.
// RUN: %target-swift-frontend %s -emit-ir -g -o - | %FileCheck %s --check-prefix=CHECK-O0
// Verify that a reabstraction thunk does not have a line number.
// CHECK-O0-NOT: DW_OP_bit_piece
// CHECK-O0-NOT: DW_OP_bit_piece
// CHECK-O0: !DILocalVariable(name: "a", arg: 1{{.*}} line: 17,
// CHECK-O0-NOT: DW_OP_bit_piece
// CHECK-O0: !DILocalVariable(name: "b", arg: 2{{.*}} line: 17,
// CHECK-O0-NOT: DW_OP_bit_piece
// CHECK-O0: !DISubprogram(linkageName: "_T0S2SSbs5Error_pIxxxdzo_S2SSbsAA_pIxiidzo_TR",
| {
"language": "Assembly"
} |
/*
Copyright Oliver Kowalke 2009.
Copyright Thomas Sailer 2013.
Distributed under the Boost Software License, Version 1.0.
(See accompanying file LICENSE_1_0.txt or copy at
http://www.boost.org/LICENSE_1_0.txt)
*/
/**************************************************************************************
* *
* ---------------------------------------------------------------------------------- *
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | *
* ---------------------------------------------------------------------------------- *
* | 0x0 | 0x4 | 0x8 | 0xc | 0x10 | 0x14 | 0x18 | 0x1c | *
* ---------------------------------------------------------------------------------- *
* | fbr_strg | fc_dealloc | limit | base | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | *
* ---------------------------------------------------------------------------------- *
* | 0x20 | 0x24 | 0x28 | 0x2c | 0x30 | 0x34 | 0x38 | 0x3c | *
* ---------------------------------------------------------------------------------- *
* | R12 | R13 | R14 | R15 | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | *
* ---------------------------------------------------------------------------------- *
* | 0xe40 | 0x44 | 0x48 | 0x4c | 0x50 | 0x54 | 0x58 | 0x5c | *
* ---------------------------------------------------------------------------------- *
* | RDI | RSI | RBX | RBP | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | *
* ---------------------------------------------------------------------------------- *
* | 0x60 | 0x64 | 0x68 | 0x6c | 0x70 | 0x74 | 0x78 | 0x7c | *
* ---------------------------------------------------------------------------------- *
* | hidden | RIP | EXIT | parameter area | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 32 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | *
* ---------------------------------------------------------------------------------- *
* | 0x80 | 0x84 | 0x88 | 0x8c | 0x90 | 0x94 | 0x98 | 0x9c | *
* ---------------------------------------------------------------------------------- *
* | parameter area | FCTX | *
* ---------------------------------------------------------------------------------- *
* ---------------------------------------------------------------------------------- *
* | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | *
* ---------------------------------------------------------------------------------- *
* | 0xa0 | 0xa4 | 0xa8 | 0xac | 0xb0 | 0xb4 | 0xb8 | 0xbc | *
* ---------------------------------------------------------------------------------- *
* | DATA | | | | *
* ---------------------------------------------------------------------------------- *
* *
* ***********************************************************************************/
.file "jump_x86_64_ms_pe_gas.asm"
.text
.p2align 4,,15
.globl jump_fcontext
.def jump_fcontext; .scl 2; .type 32; .endef
.seh_proc jump_fcontext
jump_fcontext:
.seh_endprologue
pushq %rcx /* save hidden address of transport_t */
pushq %rbp /* save RBP */
pushq %rbx /* save RBX */
pushq %rsi /* save RSI */
pushq %rdi /* save RDI */
pushq %r15 /* save R15 */
pushq %r14 /* save R14 */
pushq %r13 /* save R13 */
pushq %r12 /* save R12 */
/* load NT_TIB */
movq %gs:(0x30), %r10
/* save current stack base */
movq 0x08(%r10), %rax
pushq %rax
/* save current stack limit */
movq 0x10(%r10), %rax
pushq %rax
/* save current deallocation stack */
movq 0x1478(%r10), %rax
pushq %rax
/* save fiber local storage */
movq 0x18(%r10), %rax
pushq %rax
/* preserve RSP (pointing to context-data) in R9 */
movq %rsp, %r9
/* restore RSP (pointing to context-data) from RDX */
movq %rdx, %rsp
/* load NT_TIB */
movq %gs:(0x30), %r10
/* restore fiber local storage */
popq %rax
movq %rax, 0x18(%r10)
/* restore deallocation stack */
popq %rax
movq %rax, 0x1478(%r10)
/* restore stack limit */
popq %rax
movq %rax, 0x10(%r10)
/* restore stack base */
popq %rax
movq %rax, 0x8(%r10)
popq %r12 /* restore R12 */
popq %r13 /* restore R13 */
popq %r14 /* restore R14 */
popq %r15 /* restore R15 */
popq %rdi /* restore RDI */
popq %rsi /* restore RSI */
popq %rbx /* restore RBX */
popq %rbp /* restore RBP */
popq %rax /* restore hidden address of transport_t */
/* restore return-address */
popq %r10
/* transport_t returned in RAX */
/* return parent fcontext_t */
movq %r9, (%rax)
/* return data */
movq %r8, 0x8(%rax)
/* transport_t as 1.arg of context-function */
movq %rax, %rcx
/* indirect jump to context */
jmp *%r10
.seh_endproc
.section .drectve
.ascii " -export:\"jump_fcontext\""
| {
"language": "Assembly"
} |
;/*
; * Copyright (c) 2016-2020 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: ARMv8M Mainline Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
#ifndef DOMAIN_NS
#define DOMAIN_NS 0
#endif
#ifdef __ARMVFP__
FPU_USED EQU 1
#else
FPU_USED EQU 0
#endif
#if (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))
MVE_USED EQU 1
#else
MVE_USED EQU 0
#endif
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SM_OFS EQU 48 ; TCB.stack_mem offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
EXPORT irqRtxLib
irqRtxLib DCB 0 ; Non weak library reference
SECTION .text:CODE:NOROOT(2)
THUMB
SVC_Handler
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
#if (DOMAIN_NS == 1)
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
MRSEQ R0,MSP ; Get MSP if return stack is MSP
MRSNE R0,PSP ; Get PSP if return stack is PSP
LDR R1,[R0,#24] ; Load saved PC from stack
LDRB R1,[R1,#-2] ; Load SVC number
CMP R1,#0
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STM R12,{R0-R1} ; Store function return values
SVC_Context
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
#if ((FPU_USED == 1) || (MVE_USED == 1))
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
TST LR,#0x10 ; Check if extended stack frame
BNE SVC_ContextSwitch
LDR R1,=0xE000EF34 ; FPCCR Address
LDR R0,[R1] ; Load FPCCR
BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
STR R0,[R1] ; Store FPCCR
B SVC_ContextSwitch
#else
CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
#endif
SVC_ContextSave
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN
#endif
SVC_ContextSave1
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
#if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
#endif
SVC_ContextSave2
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
SVC_ContextRestore
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
#endif
SVC_ContextRestore1
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
MSR PSPLIM,R0 ; Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#if (DOMAIN_NS == 1)
TST LR,#0x40 ; Check domain of interrupted thread
BNE SVC_ContextRestore2 ; Branch if secure
#endif
#if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
SVC_ContextRestore2
MSR PSP,R0 ; Set PSP
SVC_Exit
BX LR ; Exit from handler
SVC_User
LDR R2,=osRtxUserSVC ; Load address of SVC table
LDR R3,[R2] ; Load SVC maximum number
CMP R1,R3 ; Check SVC number range
BHI SVC_Exit ; Branch if out of range
PUSH {R0,LR} ; Save SP and EXC_RETURN
LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
LDM R0,{R0-R3} ; Load function parameters from stack
BLX R12 ; Call service function
POP {R12,LR} ; Restore SP and EXC_RETURN
STR R0,[R12] ; Store function return value
BX LR ; Return from handler
PendSV_Handler
EXPORT PendSV_Handler
IMPORT osRtxPendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
B Sys_Context
SysTick_Handler
EXPORT SysTick_Handler
IMPORT osRtxTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
B Sys_Context
Sys_Context
EXPORT Sys_Context
IMPORT osRtxInfo
#if (DOMAIN_NS == 1)
IMPORT TZ_LoadContext_S
IMPORT TZ_StoreContext_S
#endif
LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
Sys_ContextSave
#if (DOMAIN_NS == 1)
LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context
PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN
BL TZ_StoreContext_S ; Store secure context
POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN
Sys_ContextSave1
TST LR,#0x40 ; Check domain of interrupted thread
IT NE
MRSNE R0,PSP ; Get PSP
BNE Sys_ContextSave3 ; Branch if secure
#endif
Sys_ContextSave2
MRS R0,PSP ; Get PSP
STMDB R0!,{R4-R11} ; Save R4..R11
#if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31
#endif
Sys_ContextSave3
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information
Sys_ContextSwitch
STR R2,[R3] ; osRtxInfo.run: curr = next
Sys_ContextRestore
#if (DOMAIN_NS == 1)
LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier
CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context
PUSH {R2,R3} ; Save registers
BL TZ_LoadContext_S ; Load secure context
POP {R2,R3} ; Restore registers
#endif
Sys_ContextRestore1
LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base
LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
MSR PSPLIM,R0 ; Set PSPLIM
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
#if (DOMAIN_NS == 1)
TST LR,#0x40 ; Check domain of interrupted thread
BNE Sys_ContextRestore2 ; Branch if secure
#endif
#if ((FPU_USED == 1) || (MVE_USED == 1))
TST LR,#0x10 ; Check if extended stack frame
IT EQ
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
#endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
Sys_ContextRestore2
MSR PSP,R0 ; Set PSP
Sys_ContextExit
BX LR ; Exit from handler
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBFCGI
bool "libfcgi"
depends on BR2_USE_MMU # fork()
help
FCGI, a fastcgi developer library for C/C++
http://www.fastcgi.com/
| {
"language": "Assembly"
} |
//////////////////// overlay ////////////////////
-cm-core-overlay()
/* --------------------------------------------- */
/** overlay style **/
.cm-toast
.cm-loading
.cm-mask
pointer-events auto
transform translate3d(0, 0, 0)
.cm-toast.hidden
.cm-toast.fade-out
.cm-loading.hidden
.cm-loading.fade-out
.cm-mask.hidden
.cm-mask.fade-out
opacity 0
pointer-events none
.cm-toast.fade-in
.cm-loading.fade-in
.cm-mask.fade-in
transition opacity 0.15s linear
.cm-toast.fade-out
.cm-loading.fade-out
.cm-mask.fade-out
transition opacity 0.20s linear
/* --------------------------------------------- */
/** mask **/
// Why not use `fixed` for mask?
// On iOS, viewport updates async while scrolling, making Mask sluggish.
.cm-mask
absolute left top
z-index 100
size 100% 100%
background black
opacity 0.6
-webkit-tap-highlight-color transparent
/* --------------------------------------------- */
/** loading **/
.cm-loading
&
fixed left -210px top
z-index 200
min-width 100px
max-width 200px
min-height 100px
overflow hidden
background black
border-radius 10px
opacity 0.75
// loading icon
.cm-icon
margin auto
margin-top 25px
&.cm-text .cm-icon
margin-top 18px
// loading text
p
display none
&.cm-text p
display block
margin 5px 20px 10px
color white
text-align center
/* --------------------------------------------- */
/** dialog **/
.cm-dialog
display none
position absolute
z-index 110
| {
"language": "Assembly"
} |
.model flat,c
.code
; _Mat4x4Transpose macro
;
; Description: This macro computes the transpose of a 4x4
; single-precision floating-point matrix.
;
; Input Matrix Output Matrtix
; xmm0 a3 a2 a1 a0 xmm4 d0 c0 b0 a0
; xmm1 b3 b2 b1 b0 xmm5 d1 c1 b1 a1
; xmm2 c3 c2 c1 c0 xmm6 d2 c2 b2 a2
; xmm3 d3 d2 d1 d0 xmm7 d3 c3 b3 a3
;
; Note: The row of a 4x4 matrix is reversed when loaded into an
; XMM register due to x86 little-endian ordering.
;
; Requires: SSE
_Mat4x4Transpose macro
movaps xmm4,xmm0
unpcklps xmm4,xmm1 ;xmm4 = b1 a1 b0 a0
unpckhps xmm0,xmm1 ;xmm0 = b3 a3 b2 a2
movaps xmm5,xmm2
unpcklps xmm5,xmm3 ;xmm5 = d1 c1 d0 c0
unpckhps xmm2,xmm3 ;xmm2 = d3 c3 d2 c2
movaps xmm1,xmm4
movlhps xmm4,xmm5 ;xmm4 = d0 c0 b0 a0
movhlps xmm5,xmm1 ;xmm5 = d1 c1 b1 a1
movaps xmm6,xmm0
movlhps xmm6,xmm2 ;xmm6 = d2 c2 b2 a2
movaps xmm7,xmm2
movhlps xmm7,xmm0 ;xmm7 = d3 c3 b2 a3
endm
; extern "C" void SsePfpMatrix4x4Multiply_(Mat4x4 m_des, Mat4x4 m_src1, Mat4x4 m_src2);
;
; Description: The following function computes the product of two
; 4x4 single-precision floating-point matrices.
;
; Requires: SSE4.1
SsePfpMatrix4x4Multiply_ proc
push ebp
mov ebp,esp
push ebx
; Compute transpose of m_src2 (m_src2_T)
mov ebx,[ebp+16] ;ebx = m_src2
movaps xmm0,[ebx]
movaps xmm1,[ebx+16]
movaps xmm2,[ebx+32]
movaps xmm3,[ebx+48] ;xmm3:xmm0 = m_src2
_Mat4x4Transpose ;xmm7:xmm4 = m_src2_T
; Perform initializations for matrix product
mov edx,[ebp+8] ;edx = m_des
mov ebx,[ebp+12] ;ebx = m_src1
mov ecx,4 ;ecx = number of rows
xor eax,eax ;eax = offset into arrays
; Repeat loop until matrix product is calculated.
align 16
@@: movaps xmm0,[ebx+eax] ;xmm0 = row i of m_src1
; Compute dot product of m_src1 row i and m_src2_T row 0
movaps xmm1,xmm0
dpps xmm1,xmm4,11110001b ;xmm1[31:0] = dot product
insertps xmm3,xmm1,00000000b ;xmm3[31:0] = xmm1[31:0]
; Compute dot product of m_src1 row i and m_src2_T row 1
movaps xmm2,xmm0
dpps xmm2,xmm5,11110001b ;xmm2[31:0] = dot product
insertps xmm3,xmm2,00010000b ;xmm3[63:32] = xmm2[31:0]
; Compute dot product of m_src1 row i and m_src2_T row 2
movaps xmm1,xmm0
dpps xmm1,xmm6,11110001b ;xmm1[31:0] = dot product
insertps xmm3,xmm1,00100000b ;xmm3[95:64] = xmm1[31:0]
; Compute dot product of m_src1 row i and m_src2_T row 3
movaps xmm2,xmm0
dpps xmm2,xmm7,11110001b ;xmm2[31:0] = dot product
insertps xmm3,xmm2,00110000b ;xmm3[127:96] = xmm2[31:0]
; Save m_des.row i and update loop variables
movaps [edx+eax],xmm3 ;save current row result
add eax,16 ;set array offset to next row
dec ecx
jnz @B
pop ebx
pop ebp
ret
SsePfpMatrix4x4Multiply_ endp
; extern void SsePfpMatrix4x4TransformVectors_(Vec4x1* v_des, Mat4x4 m_src, Vec4x1* v_src, int num_vec);
;
; Description: The following function applies a transformation matrix
; to an array 4x1 single-precision floating-point vectors.
;
; Requires: SSE4.1
SsePfpMatrix4x4TransformVectors_ proc
push ebp
mov ebp,esp
push esi
push edi
; Make sure num_vec is valid
mov ecx,[ebp+20] ;ecx = num_vec
test ecx,ecx
jle Done ;jump if num_vec <= 0
; Load m_src into xmm3:xmm0
mov eax,[ebp+12] ;eax = pointer to m_src
movaps xmm0,[eax] ;xmm0 = row 0
movaps xmm1,[eax+16] ;xmm1 = row 1
movaps xmm2,[eax+32] ;xmm2 = row 2
movaps xmm3,[eax+48] ;xmm3 = row 3
; Initialize pointers to v_src and v_des
mov esi,[ebp+16] ;esi = pointer to v_src
mov edi,[ebp+8] ;edi = pointer to v_des
xor eax,eax ;eax = array offset
; Compute v_des[i] = m_src * v_src[i]
align 16
@@: movaps xmm4,[esi+eax] ;xmm4 = vector v_src[i]
; Compute dot product of m_src row 0 and v_src[i]
movaps xmm5,xmm4
dpps xmm5,xmm0,11110001b ;xmm5[31:0] = dot product
insertps xmm7,xmm5,00000000b ;xmm7[31:0] = xmm5[31:0]
; Compute dot product of m_src row 1 and v_src[i]
movaps xmm6,xmm4
dpps xmm6,xmm1,11110001b ;xmm6[31:0] = dot product
insertps xmm7,xmm6,00010000b ;xmm7[63:32] = xmm6[31:0]
; Compute dot product of m_src row 2 and v_src[i]
movaps xmm5,xmm4
dpps xmm5,xmm2,11110001b ;xmm5[31:0] = dot product
insertps xmm7,xmm5,00100000b ;xmm7[95:64] = xmm5[31:0]
; Compute dot product of m_src row 3 and v_src[i]
movaps xmm6,xmm4
dpps xmm6,xmm3,11110001b ;xmm6[31:0] = dot product
insertps xmm7,xmm6,00110000b ;xmm7[127:96] = xmm6[31:0]
; Save v_des[i] and update loop variables
movaps [edi+eax],xmm7 ;save transformed vector
add eax,16
dec ecx
jnz @B
Done: pop edi
pop esi
pop ebp
ret
SsePfpMatrix4x4TransformVectors_ endp
end
| {
"language": "Assembly"
} |
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
int main(int, char**)
{
return 0;
}
| {
"language": "Assembly"
} |
.text
.globl sha512_block_data_order
.type sha512_block_data_order,@function
.align 16
sha512_block_data_order:
.L_sha512_block_data_order_begin:
pushl %ebp
pushl %ebx
pushl %esi
pushl %edi
movl 20(%esp),%esi
movl 24(%esp),%edi
movl 28(%esp),%eax
movl %esp,%ebx
call .L000pic_point
.L000pic_point:
popl %ebp
leal .L001K512-.L000pic_point(%ebp),%ebp
subl $16,%esp
andl $-64,%esp
shll $7,%eax
addl %edi,%eax
movl %esi,(%esp)
movl %edi,4(%esp)
movl %eax,8(%esp)
movl %ebx,12(%esp)
.align 16
.L002loop_x86:
movl (%edi),%eax
movl 4(%edi),%ebx
movl 8(%edi),%ecx
movl 12(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 16(%edi),%eax
movl 20(%edi),%ebx
movl 24(%edi),%ecx
movl 28(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 32(%edi),%eax
movl 36(%edi),%ebx
movl 40(%edi),%ecx
movl 44(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 48(%edi),%eax
movl 52(%edi),%ebx
movl 56(%edi),%ecx
movl 60(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 64(%edi),%eax
movl 68(%edi),%ebx
movl 72(%edi),%ecx
movl 76(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 80(%edi),%eax
movl 84(%edi),%ebx
movl 88(%edi),%ecx
movl 92(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 96(%edi),%eax
movl 100(%edi),%ebx
movl 104(%edi),%ecx
movl 108(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
movl 112(%edi),%eax
movl 116(%edi),%ebx
movl 120(%edi),%ecx
movl 124(%edi),%edx
bswap %eax
bswap %ebx
bswap %ecx
bswap %edx
pushl %eax
pushl %ebx
pushl %ecx
pushl %edx
addl $128,%edi
subl $72,%esp
movl %edi,204(%esp)
leal 8(%esp),%edi
movl $16,%ecx
.long 2784229001
.align 16
.L00300_15_x86:
movl 40(%esp),%ecx
movl 44(%esp),%edx
movl %ecx,%esi
shrl $9,%ecx
movl %edx,%edi
shrl $9,%edx
movl %ecx,%ebx
shll $14,%esi
movl %edx,%eax
shll $14,%edi
xorl %esi,%ebx
shrl $5,%ecx
xorl %edi,%eax
shrl $5,%edx
xorl %ecx,%eax
shll $4,%esi
xorl %edx,%ebx
shll $4,%edi
xorl %esi,%ebx
shrl $4,%ecx
xorl %edi,%eax
shrl $4,%edx
xorl %ecx,%eax
shll $5,%esi
xorl %edx,%ebx
shll $5,%edi
xorl %esi,%eax
xorl %edi,%ebx
movl 48(%esp),%ecx
movl 52(%esp),%edx
movl 56(%esp),%esi
movl 60(%esp),%edi
addl 64(%esp),%eax
adcl 68(%esp),%ebx
xorl %esi,%ecx
xorl %edi,%edx
andl 40(%esp),%ecx
andl 44(%esp),%edx
addl 192(%esp),%eax
adcl 196(%esp),%ebx
xorl %esi,%ecx
xorl %edi,%edx
movl (%ebp),%esi
movl 4(%ebp),%edi
addl %ecx,%eax
adcl %edx,%ebx
movl 32(%esp),%ecx
movl 36(%esp),%edx
addl %esi,%eax
adcl %edi,%ebx
movl %eax,(%esp)
movl %ebx,4(%esp)
addl %ecx,%eax
adcl %edx,%ebx
movl 8(%esp),%ecx
movl 12(%esp),%edx
movl %eax,32(%esp)
movl %ebx,36(%esp)
movl %ecx,%esi
shrl $2,%ecx
movl %edx,%edi
shrl $2,%edx
movl %ecx,%ebx
shll $4,%esi
movl %edx,%eax
shll $4,%edi
xorl %esi,%ebx
shrl $5,%ecx
xorl %edi,%eax
shrl $5,%edx
xorl %ecx,%ebx
shll $21,%esi
xorl %edx,%eax
shll $21,%edi
xorl %esi,%eax
shrl $21,%ecx
xorl %edi,%ebx
shrl $21,%edx
xorl %ecx,%eax
shll $5,%esi
xorl %edx,%ebx
shll $5,%edi
xorl %esi,%eax
xorl %edi,%ebx
movl 8(%esp),%ecx
movl 12(%esp),%edx
movl 16(%esp),%esi
movl 20(%esp),%edi
addl (%esp),%eax
adcl 4(%esp),%ebx
orl %esi,%ecx
orl %edi,%edx
andl 24(%esp),%ecx
andl 28(%esp),%edx
andl 8(%esp),%esi
andl 12(%esp),%edi
orl %esi,%ecx
orl %edi,%edx
addl %ecx,%eax
adcl %edx,%ebx
movl %eax,(%esp)
movl %ebx,4(%esp)
movb (%ebp),%dl
subl $8,%esp
leal 8(%ebp),%ebp
cmpb $148,%dl
jne .L00300_15_x86
.align 16
.L00416_79_x86:
movl 312(%esp),%ecx
movl 316(%esp),%edx
movl %ecx,%esi
shrl $1,%ecx
movl %edx,%edi
shrl $1,%edx
movl %ecx,%eax
shll $24,%esi
movl %edx,%ebx
shll $24,%edi
xorl %esi,%ebx
shrl $6,%ecx
xorl %edi,%eax
shrl $6,%edx
xorl %ecx,%eax
shll $7,%esi
xorl %edx,%ebx
shll $1,%edi
xorl %esi,%ebx
shrl $1,%ecx
xorl %edi,%eax
shrl $1,%edx
xorl %ecx,%eax
shll $6,%edi
xorl %edx,%ebx
xorl %edi,%eax
movl %eax,(%esp)
movl %ebx,4(%esp)
movl 208(%esp),%ecx
movl 212(%esp),%edx
movl %ecx,%esi
shrl $6,%ecx
movl %edx,%edi
shrl $6,%edx
movl %ecx,%eax
shll $3,%esi
movl %edx,%ebx
shll $3,%edi
xorl %esi,%eax
shrl $13,%ecx
xorl %edi,%ebx
shrl $13,%edx
xorl %ecx,%eax
shll $10,%esi
xorl %edx,%ebx
shll $10,%edi
xorl %esi,%ebx
shrl $10,%ecx
xorl %edi,%eax
shrl $10,%edx
xorl %ecx,%ebx
shll $13,%edi
xorl %edx,%eax
xorl %edi,%eax
movl 320(%esp),%ecx
movl 324(%esp),%edx
addl (%esp),%eax
adcl 4(%esp),%ebx
movl 248(%esp),%esi
movl 252(%esp),%edi
addl %ecx,%eax
adcl %edx,%ebx
addl %esi,%eax
adcl %edi,%ebx
movl %eax,192(%esp)
movl %ebx,196(%esp)
movl 40(%esp),%ecx
movl 44(%esp),%edx
movl %ecx,%esi
shrl $9,%ecx
movl %edx,%edi
shrl $9,%edx
movl %ecx,%ebx
shll $14,%esi
movl %edx,%eax
shll $14,%edi
xorl %esi,%ebx
shrl $5,%ecx
xorl %edi,%eax
shrl $5,%edx
xorl %ecx,%eax
shll $4,%esi
xorl %edx,%ebx
shll $4,%edi
xorl %esi,%ebx
shrl $4,%ecx
xorl %edi,%eax
shrl $4,%edx
xorl %ecx,%eax
shll $5,%esi
xorl %edx,%ebx
shll $5,%edi
xorl %esi,%eax
xorl %edi,%ebx
movl 48(%esp),%ecx
movl 52(%esp),%edx
movl 56(%esp),%esi
movl 60(%esp),%edi
addl 64(%esp),%eax
adcl 68(%esp),%ebx
xorl %esi,%ecx
xorl %edi,%edx
andl 40(%esp),%ecx
andl 44(%esp),%edx
addl 192(%esp),%eax
adcl 196(%esp),%ebx
xorl %esi,%ecx
xorl %edi,%edx
movl (%ebp),%esi
movl 4(%ebp),%edi
addl %ecx,%eax
adcl %edx,%ebx
movl 32(%esp),%ecx
movl 36(%esp),%edx
addl %esi,%eax
adcl %edi,%ebx
movl %eax,(%esp)
movl %ebx,4(%esp)
addl %ecx,%eax
adcl %edx,%ebx
movl 8(%esp),%ecx
movl 12(%esp),%edx
movl %eax,32(%esp)
movl %ebx,36(%esp)
movl %ecx,%esi
shrl $2,%ecx
movl %edx,%edi
shrl $2,%edx
movl %ecx,%ebx
shll $4,%esi
movl %edx,%eax
shll $4,%edi
xorl %esi,%ebx
shrl $5,%ecx
xorl %edi,%eax
shrl $5,%edx
xorl %ecx,%ebx
shll $21,%esi
xorl %edx,%eax
shll $21,%edi
xorl %esi,%eax
shrl $21,%ecx
xorl %edi,%ebx
shrl $21,%edx
xorl %ecx,%eax
shll $5,%esi
xorl %edx,%ebx
shll $5,%edi
xorl %esi,%eax
xorl %edi,%ebx
movl 8(%esp),%ecx
movl 12(%esp),%edx
movl 16(%esp),%esi
movl 20(%esp),%edi
addl (%esp),%eax
adcl 4(%esp),%ebx
orl %esi,%ecx
orl %edi,%edx
andl 24(%esp),%ecx
andl 28(%esp),%edx
andl 8(%esp),%esi
andl 12(%esp),%edi
orl %esi,%ecx
orl %edi,%edx
addl %ecx,%eax
adcl %edx,%ebx
movl %eax,(%esp)
movl %ebx,4(%esp)
movb (%ebp),%dl
subl $8,%esp
leal 8(%ebp),%ebp
cmpb $23,%dl
jne .L00416_79_x86
movl 840(%esp),%esi
movl 844(%esp),%edi
movl (%esi),%eax
movl 4(%esi),%ebx
movl 8(%esi),%ecx
movl 12(%esi),%edx
addl 8(%esp),%eax
adcl 12(%esp),%ebx
movl %eax,(%esi)
movl %ebx,4(%esi)
addl 16(%esp),%ecx
adcl 20(%esp),%edx
movl %ecx,8(%esi)
movl %edx,12(%esi)
movl 16(%esi),%eax
movl 20(%esi),%ebx
movl 24(%esi),%ecx
movl 28(%esi),%edx
addl 24(%esp),%eax
adcl 28(%esp),%ebx
movl %eax,16(%esi)
movl %ebx,20(%esi)
addl 32(%esp),%ecx
adcl 36(%esp),%edx
movl %ecx,24(%esi)
movl %edx,28(%esi)
movl 32(%esi),%eax
movl 36(%esi),%ebx
movl 40(%esi),%ecx
movl 44(%esi),%edx
addl 40(%esp),%eax
adcl 44(%esp),%ebx
movl %eax,32(%esi)
movl %ebx,36(%esi)
addl 48(%esp),%ecx
adcl 52(%esp),%edx
movl %ecx,40(%esi)
movl %edx,44(%esi)
movl 48(%esi),%eax
movl 52(%esi),%ebx
movl 56(%esi),%ecx
movl 60(%esi),%edx
addl 56(%esp),%eax
adcl 60(%esp),%ebx
movl %eax,48(%esi)
movl %ebx,52(%esi)
addl 64(%esp),%ecx
adcl 68(%esp),%edx
movl %ecx,56(%esi)
movl %edx,60(%esi)
addl $840,%esp
subl $640,%ebp
cmpl 8(%esp),%edi
jb .L002loop_x86
movl 12(%esp),%esp
popl %edi
popl %esi
popl %ebx
popl %ebp
ret
.align 64
.L001K512:
.long 3609767458,1116352408
.long 602891725,1899447441
.long 3964484399,3049323471
.long 2173295548,3921009573
.long 4081628472,961987163
.long 3053834265,1508970993
.long 2937671579,2453635748
.long 3664609560,2870763221
.long 2734883394,3624381080
.long 1164996542,310598401
.long 1323610764,607225278
.long 3590304994,1426881987
.long 4068182383,1925078388
.long 991336113,2162078206
.long 633803317,2614888103
.long 3479774868,3248222580
.long 2666613458,3835390401
.long 944711139,4022224774
.long 2341262773,264347078
.long 2007800933,604807628
.long 1495990901,770255983
.long 1856431235,1249150122
.long 3175218132,1555081692
.long 2198950837,1996064986
.long 3999719339,2554220882
.long 766784016,2821834349
.long 2566594879,2952996808
.long 3203337956,3210313671
.long 1034457026,3336571891
.long 2466948901,3584528711
.long 3758326383,113926993
.long 168717936,338241895
.long 1188179964,666307205
.long 1546045734,773529912
.long 1522805485,1294757372
.long 2643833823,1396182291
.long 2343527390,1695183700
.long 1014477480,1986661051
.long 1206759142,2177026350
.long 344077627,2456956037
.long 1290863460,2730485921
.long 3158454273,2820302411
.long 3505952657,3259730800
.long 106217008,3345764771
.long 3606008344,3516065817
.long 1432725776,3600352804
.long 1467031594,4094571909
.long 851169720,275423344
.long 3100823752,430227734
.long 1363258195,506948616
.long 3750685593,659060556
.long 3785050280,883997877
.long 3318307427,958139571
.long 3812723403,1322822218
.long 2003034995,1537002063
.long 3602036899,1747873779
.long 1575990012,1955562222
.long 1125592928,2024104815
.long 2716904306,2227730452
.long 442776044,2361852424
.long 593698344,2428436474
.long 3733110249,2756734187
.long 2999351573,3204031479
.long 3815920427,3329325298
.long 3928383900,3391569614
.long 566280711,3515267271
.long 3454069534,3940187606
.long 4000239992,4118630271
.long 1914138554,116418474
.long 2731055270,174292421
.long 3203993006,289380356
.long 320620315,460393269
.long 587496836,685471733
.long 1086792851,852142971
.long 365543100,1017036298
.long 2618297676,1126000580
.long 3409855158,1288033470
.long 4234509866,1501505948
.long 987167468,1607167915
.long 1246189591,1816402316
.long 67438087,66051
.long 202182159,134810123
.size sha512_block_data_order,.-.L_sha512_block_data_order_begin
.byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97
.byte 110,115,102,111,114,109,32,102,111,114,32,120,56,54,44,32
.byte 67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97
.byte 112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103
.byte 62,0
| {
"language": "Assembly"
} |
#include "arm/sysregs.h"
#include "mm.h"
.section ".text.boot"
.globl _start
_start:
mrs x0, mpidr_el1
and x0, x0,#0xFF // Check processor id
cbz x0, master // Hang for all non-primary CPU
b proc_hang
proc_hang:
b proc_hang
master:
ldr x0, =SCTLR_VALUE_MMU_DISABLED
msr sctlr_el1, x0
ldr x0, =HCR_VALUE
msr hcr_el2, x0
ldr x0, =SCR_VALUE
msr scr_el3, x0
ldr x0, =SPSR_VALUE
msr spsr_el3, x0
adr x0, el1_entry
msr elr_el3, x0
eret
el1_entry:
adr x0, bss_begin
adr x1, bss_end
sub x1, x1, x0
bl memzero
mov sp, #(2 * SECTION_SIZE)
bl kernel_main
b proc_hang // should never come here
| {
"language": "Assembly"
} |
; RUN: opt < %s -indvars -S | FileCheck %s
;
; This loop has multiple exits, and the value of %b1 depends on which
; exit is taken. Indvars should correctly compute the exit values.
;
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-pc-linux-gnu"
%struct..0anon = type <{ i8, [3 x i8] }>
define i32 @main() nounwind {
; CHECK-LABEL: @main(
; CHECK: %b.1 = phi i32 [ 2, %bb ], [ 1, %bb2 ]
entry:
br label %bb2
bb2: ; preds = %bb, %entry
%sdata.0 = phi i32 [ 1, %entry ], [ %ins10, %bb ] ; <i32> [#uses=2]
%b.0 = phi i32 [ 0, %entry ], [ %t0, %bb ] ; <i32> [#uses=2]
%tmp6 = trunc i32 %sdata.0 to i8 ; <i8> [#uses=2]
%t2 = and i8 %tmp6, 1 ; <i8> [#uses=1]
%t3 = icmp eq i8 %t2, 0 ; <i1> [#uses=1]
%t4 = xor i8 %tmp6, 1 ; <i8> [#uses=1]
%tmp8 = zext i8 %t4 to i32 ; <i32> [#uses=1]
%mask9 = and i32 %sdata.0, -256 ; <i32> [#uses=1]
%ins10 = or i32 %tmp8, %mask9 ; <i32> [#uses=1]
br i1 %t3, label %bb3, label %bb
bb: ; preds = %bb2
%t0 = add i32 %b.0, 1 ; <i32> [#uses=3]
%t1 = icmp sgt i32 %t0, 100 ; <i1> [#uses=1]
br i1 %t1, label %bb3, label %bb2
bb3: ; preds = %bb, %bb2
%b.1 = phi i32 [ %t0, %bb ], [ %b.0, %bb2 ] ; <i32> [#uses=1]
%t5 = icmp eq i32 %b.1, 1 ; <i1> [#uses=1]
br i1 %t5, label %bb5, label %bb4
bb4: ; preds = %bb3
tail call void @abort() noreturn nounwind
unreachable
bb5: ; preds = %bb3
ret i32 0
}
declare void @abort() noreturn nounwind
| {
"language": "Assembly"
} |
// Modified by Lubos Dolezel for Darling
/*
* Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. The rights granted to you under the License
* may not be used to create, or enable the creation or redistribution of,
* unlawful or unlicensed copies of an Apple operating system, or to
* circumvent, violate, or enable the circumvention or violation of, any
* terms of an Apple operating system software license agreement.
*
* Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
*/
/*
* Mach Operating System
* Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*/
#ifdef PRIVATE
#ifndef _MACH_I386_SYSCALL_SW_H_
#define _MACH_I386_SYSCALL_SW_H_
#include <architecture/i386/asm_help.h>
/*
* Software interrupt codes for 32-bit system call entry:
*/
#define UNIX_INT 0x80
#define MACH_INT 0x81
#define MACHDEP_INT 0x82
#define DIAG_INT 0x83
#if defined(__i386__)
#ifndef KERNEL
/*
* Syscall entry macros for use in libc:
*/
#ifndef DARLING
#define UNIX_SYSCALL_TRAP \
int $(UNIX_INT)
#define MACHDEP_SYSCALL_TRAP \
int $(MACHDEP_INT)
#else // DARLING
#define UNIX_SYSCALL_TRAP \
call __darling_bsd_syscall
#define MACHDEP_SYSCALL_TRAP \
call __darling_machdep_syscall
#endif
/*
* Macro to generate Mach call stubs in libc:
*/
#ifndef DARLING
#define kernel_trap(trap_name,trap_number,number_args) \
LEAF(_##trap_name,0) ;\
movl $##trap_number, %eax ;\
call __sysenter_trap ;\
END(_##trap_name)
#else
#define kernel_trap(trap_name,trap_number,number_args) \
LEAF(_##trap_name,0) ;\
movl $##trap_number, %eax ;\
call __darling_mach_syscall ;\
END(_##trap_name)
#endif /* DARLING */
#endif /* !KERNEL */
#endif /* defined(__i386__) */
#if defined(__x86_64__)
#ifndef KERNEL
#define UNIX_SYSCALL_TRAP \
call __darling_bsd_syscall
#define MACHDEP_SYSCALL_TRAP \
call __darling_machdep_syscall
/*
* Macro to generate Mach call stubs in Libc.
* Existing calls use negative numbers for Mach traps, so
* until we change those and change the 32-bit kernel_trap
* macro above, we negate those numbers here for the 64-bit
* code path.
*/
#ifndef DARLING
#define kernel_trap(trap_name,trap_number,number_args) \
LEAF(_##trap_name,0) ;\
movq %rcx, %r10 ;\
movl $ SYSCALL_CONSTRUCT_MACH(-##trap_number), %eax ;\
syscall ;\
END(_##trap_name)
#else
#define kernel_trap(trap_name,trap_number,number_args) \
LEAF(_##trap_name,0) ;\
movl $##trap_number, %eax ;\
call __darling_mach_syscall;\
END(_##trap_name)
#endif
#endif /* !KERNEL */
#endif /* defined(__x86_64__) */
/*
* Syscall classes for 64-bit system call entry.
* For 64-bit users, the 32-bit syscall number is partitioned
* with the high-order bits representing the class and low-order
* bits being the syscall number within that class.
* The high-order 32-bits of the 64-bit syscall number are unused.
* All system classes enter the kernel via the syscall instruction.
*
* These are not #ifdef'd for x86-64 because they might be used for
* 32-bit someday and so the 64-bit comm page in a 32-bit kernel
* can use them.
*/
#define SYSCALL_CLASS_SHIFT 24
#define SYSCALL_CLASS_MASK (0xFF << SYSCALL_CLASS_SHIFT)
#define SYSCALL_NUMBER_MASK (~SYSCALL_CLASS_MASK)
#define I386_SYSCALL_CLASS_MASK SYSCALL_CLASS_MASK
#define I386_SYSCALL_ARG_BYTES_SHIFT (16)
#define I386_SYSCALL_ARG_DWORDS_SHIFT (I386_SYSCALL_ARG_BYTES_SHIFT + 2)
#define I386_SYSCALL_ARG_BYTES_NUM (64) /* Must be <= sizeof(uu_arg) */
#define I386_SYSCALL_ARG_DWORDS_MASK ((I386_SYSCALL_ARG_BYTES_NUM >> 2) -1)
#define I386_SYSCALL_ARG_BYTES_MASK (((I386_SYSCALL_ARG_BYTES_NUM -1)&~0x3) << I386_SYSCALL_ARG_BYTES_SHIFT)
#define I386_SYSCALL_NUMBER_MASK (0xFFFF)
#define SYSCALL_CLASS_NONE 0 /* Invalid */
#define SYSCALL_CLASS_MACH 1 /* Mach */
#define SYSCALL_CLASS_UNIX 2 /* Unix/BSD */
#define SYSCALL_CLASS_MDEP 3 /* Machine-dependent */
#define SYSCALL_CLASS_DIAG 4 /* Diagnostics */
#define SYSCALL_CLASS_IPC 5 /* Mach IPC */
/* Macros to simpllfy constructing syscall numbers. */
#define SYSCALL_CONSTRUCT_MACH(syscall_number) \
((SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT) | \
(SYSCALL_NUMBER_MASK & (syscall_number)))
#define SYSCALL_CONSTRUCT_UNIX(syscall_number) \
((SYSCALL_CLASS_UNIX << SYSCALL_CLASS_SHIFT) | \
(SYSCALL_NUMBER_MASK & (syscall_number)))
#define SYSCALL_CONSTRUCT_MDEP(syscall_number) \
((SYSCALL_CLASS_MDEP << SYSCALL_CLASS_SHIFT) | \
(SYSCALL_NUMBER_MASK & (syscall_number)))
#define SYSCALL_CONSTRUCT_DIAG(syscall_number) \
((SYSCALL_CLASS_DIAG << SYSCALL_CLASS_SHIFT) | \
(SYSCALL_NUMBER_MASK & (syscall_number)))
#endif /* _MACH_I386_SYSCALL_SW_H_ */
#endif /* PRIVATE */
| {
"language": "Assembly"
} |
// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
#include "textflag.h"
// No need for _rt0_arm64_darwin as darwin/arm64 only
// supports external linking.
TEXT _rt0_arm64_darwin(SB),NOSPLIT,$-8
MOVD $42, R0
MOVD $1, R16 // SYS_exit
SVC $0x80
// When linking with -buildmode=c-archive or -buildmode=c-shared,
// this symbol is called from a global initialization function.
//
// Note that all currently shipping darwin/arm64 platforms require
// cgo and do not support c-shared.
TEXT _rt0_arm64_darwin_lib(SB),NOSPLIT,$168
// Preserve callee-save registers.
MOVD R19, 24(RSP)
MOVD R20, 32(RSP)
MOVD R21, 40(RSP)
MOVD R22, 48(RSP)
MOVD R23, 56(RSP)
MOVD R24, 64(RSP)
MOVD R25, 72(RSP)
MOVD R26, 80(RSP)
MOVD R27, 88(RSP)
FMOVD F8, 96(RSP)
FMOVD F9, 104(RSP)
FMOVD F10, 112(RSP)
FMOVD F11, 120(RSP)
FMOVD F12, 128(RSP)
FMOVD F13, 136(RSP)
FMOVD F14, 144(RSP)
FMOVD F15, 152(RSP)
MOVD R0, _rt0_arm64_darwin_lib_argc<>(SB)
MOVD R1, _rt0_arm64_darwin_lib_argv<>(SB)
// Synchronous initialization.
MOVD $runtime·libpreinit(SB), R4
BL (R4)
// Create a new thread to do the runtime initialization and return.
MOVD _cgo_sys_thread_create(SB), R4
MOVD $_rt0_arm64_darwin_lib_go(SB), R0
MOVD $0, R1
BL (R4)
// Restore callee-save registers.
MOVD 24(RSP), R19
MOVD 32(RSP), R20
MOVD 40(RSP), R21
MOVD 48(RSP), R22
MOVD 56(RSP), R23
MOVD 64(RSP), R24
MOVD 72(RSP), R25
MOVD 80(RSP), R26
MOVD 88(RSP), R27
FMOVD 96(RSP), F8
FMOVD 104(RSP), F9
FMOVD 112(RSP), F10
FMOVD 120(RSP), F11
FMOVD 128(RSP), F12
FMOVD 136(RSP), F13
FMOVD 144(RSP), F14
FMOVD 152(RSP), F15
RET
TEXT _rt0_arm64_darwin_lib_go(SB),NOSPLIT,$0
MOVD _rt0_arm64_darwin_lib_argc<>(SB), R0
MOVD _rt0_arm64_darwin_lib_argv<>(SB), R1
MOVD $runtime·rt0_go(SB), R4
B (R4)
DATA _rt0_arm64_darwin_lib_argc<>(SB)/8, $0
GLOBL _rt0_arm64_darwin_lib_argc<>(SB),NOPTR, $8
DATA _rt0_arm64_darwin_lib_argv<>(SB)/8, $0
GLOBL _rt0_arm64_darwin_lib_argv<>(SB),NOPTR, $8
TEXT main(SB),NOSPLIT,$-8
MOVD $runtime·rt0_go(SB), R2
BL (R2)
exit:
MOVD $0, R0
MOVD $1, R16 // sys_exit
SVC $0x80
B exit
| {
"language": "Assembly"
} |
/*
* Summary: macros for marking symbols as exportable/importable.
* Description: macros for marking symbols as exportable/importable.
*
* Copy: See Copyright for the status of this software.
*
* Author: Igor Zlatkovic <igor@zlatkovic.com>
*/
#ifndef __XSLT_EXPORTS_H__
#define __XSLT_EXPORTS_H__
/**
* XSLTPUBFUN:
* XSLTPUBFUN, XSLTPUBVAR, XSLTCALL
*
* Macros which declare an exportable function, an exportable variable and
* the calling convention used for functions.
*
* Please use an extra block for every platform/compiler combination when
* modifying this, rather than overlong #ifdef lines. This helps
* readability as well as the fact that different compilers on the same
* platform might need different definitions.
*/
/**
* XSLTPUBFUN:
*
* Macros which declare an exportable function
*/
#define XSLTPUBFUN
/**
* XSLTPUBVAR:
*
* Macros which declare an exportable variable
*/
#define XSLTPUBVAR extern
/**
* XSLTCALL:
*
* Macros which declare the called convention for exported functions
*/
#define XSLTCALL
/** DOC_DISABLE */
/* Windows platform with MS compiler */
#if defined(_WIN32) && defined(_MSC_VER)
#undef XSLTPUBFUN
#undef XSLTPUBVAR
#undef XSLTCALL
#if defined(IN_LIBXSLT) && !defined(LIBXSLT_STATIC)
#define XSLTPUBFUN __declspec(dllexport)
#define XSLTPUBVAR __declspec(dllexport)
#else
#define XSLTPUBFUN
#if !defined(LIBXSLT_STATIC)
#define XSLTPUBVAR __declspec(dllimport) extern
#else
#define XSLTPUBVAR extern
#endif
#endif
#define XSLTCALL __cdecl
#if !defined _REENTRANT
#define _REENTRANT
#endif
#endif
/* Windows platform with Borland compiler */
#if defined(_WIN32) && defined(__BORLANDC__)
#undef XSLTPUBFUN
#undef XSLTPUBVAR
#undef XSLTCALL
#if defined(IN_LIBXSLT) && !defined(LIBXSLT_STATIC)
#define XSLTPUBFUN __declspec(dllexport)
#define XSLTPUBVAR __declspec(dllexport) extern
#else
#define XSLTPUBFUN
#if !defined(LIBXSLT_STATIC)
#define XSLTPUBVAR __declspec(dllimport) extern
#else
#define XSLTPUBVAR extern
#endif
#endif
#define XSLTCALL __cdecl
#if !defined _REENTRANT
#define _REENTRANT
#endif
#endif
/* Windows platform with GNU compiler (Mingw) */
#if defined(_WIN32) && defined(__MINGW32__)
#undef XSLTPUBFUN
#undef XSLTPUBVAR
#undef XSLTCALL
/*
#if defined(IN_LIBXSLT) && !defined(LIBXSLT_STATIC)
*/
#if !defined(LIBXSLT_STATIC)
#define XSLTPUBFUN __declspec(dllexport)
#define XSLTPUBVAR __declspec(dllexport) extern
#else
#define XSLTPUBFUN
#if !defined(LIBXSLT_STATIC)
#define XSLTPUBVAR __declspec(dllimport) extern
#else
#define XSLTPUBVAR extern
#endif
#endif
#define XSLTCALL __cdecl
#if !defined _REENTRANT
#define _REENTRANT
#endif
#endif
/* Cygwin platform, GNU compiler */
#if defined(_WIN32) && defined(__CYGWIN__)
#undef XSLTPUBFUN
#undef XSLTPUBVAR
#undef XSLTCALL
#if defined(IN_LIBXSLT) && !defined(LIBXSLT_STATIC)
#define XSLTPUBFUN __declspec(dllexport)
#define XSLTPUBVAR __declspec(dllexport)
#else
#define XSLTPUBFUN
#if !defined(LIBXSLT_STATIC)
#define XSLTPUBVAR __declspec(dllimport) extern
#else
#define XSLTPUBVAR
#endif
#endif
#define XSLTCALL __cdecl
#endif
/* Compatibility */
#if !defined(LIBXSLT_PUBLIC)
#define LIBXSLT_PUBLIC XSLTPUBVAR
#endif
#endif /* __XSLT_EXPORTS_H__ */
| {
"language": "Assembly"
} |
; Copyright (c) 2011 The Chromium Authors. All rights reserved.
; Use of this source code is governed by a BSD-style license that can be
; found in the LICENSE file.
;
; void SYMBOL(const uint8_t* argb, uint8_t* y, uint8_t* u, uint8_t* v, int width);
;
; The main code that converts RGB pixels to YUV pixels. This function roughly
; consists of three parts: converting one ARGB pixel to YUV pixels, converting
; two ARGB pixels to YUV pixels, and converting four ARGB pixels to YUV pixels.
; To write the structure of this function in C, it becomes the snippet listed
; below.
;
; if (width & 1) {
; --width;
; // Convert one ARGB pixel to one Y pixel, one U pixel, and one V pixel.
; }
;
; if (width & 2) {
; width -= 2;
; // Convert two ARGB pixels to two Y pixels, one U pixel, and one V pixel.
; }
;
; while (width) {
; width -= 4;
; // Convert four ARGB pixels to four Y pixels, two U pixels, and two V
; // pixels.
; }
;
EXPORT SYMBOL
align function_align
mangle(SYMBOL):
%assign stack_offset 0
PROLOGUE 5, 6, 8, ARGB, Y, U, V, WIDTH, TEMP
; Initialize constants used in this function. (We use immediates to avoid
; dependency onto GOT.)
LOAD_XMM XMM_CONST_Y0, 0x00420219
LOAD_XMM XMM_CONST_Y1, 0x00007F00
LOAD_XMM XMM_CONST_U, 0x00DAB670
LOAD_XMM XMM_CONST_V, 0x0070A2EE
LOAD_XMM XMM_CONST_128, 0x00800080
.convert_one_pixel:
; Divide the input width by two so it represents the offsets for u[] and v[].
; When the width is odd, We read the rightmost ARGB pixel and convert its
; colorspace to YUV. This code stores one Y pixel, one U pixel, and one V
; pixel.
sar WIDTHq, 1
jnc .convert_two_pixels
; Read one ARGB (or RGB) pixel.
READ_ARGB xmm0, 1
; Calculate y[0] from one RGB pixel read above.
CALC_Y xmm1, xmm0
movd TEMPd, xmm1
mov BYTE [Yq + WIDTHq * 2], TEMPb
; Calculate u[0] from one RGB pixel read above. If this is an odd line, the
; output pixel contains the U value calculated in the previous call. We also
; read this pixel and calculate their average.
INIT_UV TEMPd, Uq, 4
CALC_UV xmm1, xmm0, XMM_CONST_U, TEMPd
movd TEMPd, xmm1
mov BYTE [Uq + WIDTHq], TEMPb
; Calculate v[0] from one RGB pixel. Same as u[0], we read the result of the
; previous call and get their average.
INIT_UV TEMPd, Uq, 4
CALC_UV xmm1, xmm0, XMM_CONST_V, TEMPd
movd TEMPd, xmm1
mov BYTE [Vq + WIDTHq], TEMPb
.convert_two_pixels:
; If the input width is not a multiple of four, read the rightmost two ARGB
; pixels and convert their colorspace to YUV. This code stores two Y pixels,
; one U pixel, and one V pixel.
test WIDTHb, 2 / 2
jz .convert_four_pixels
sub WIDTHb, 2 / 2
; Read two ARGB (or RGB) pixels.
READ_ARGB xmm0, 2
; Calculate r[0] and r[1] from two RGB pixels read above.
CALC_Y xmm1, xmm0
movd TEMPd, xmm1
mov WORD [Yq + WIDTHq * 2], TEMPw
; Skip calculating u and v if the output buffer is NULL.
test Uq, Uq
jz .convert_four_pixels
; Calculate u[0] from two RGB pixels read above. (For details, read the above
; comment in .convert_one_pixel).
INIT_UV TEMPd, Uq, 2
CALC_UV xmm1, xmm0, XMM_CONST_U, TEMPd
movd TEMPd, xmm1
mov BYTE [Uq + WIDTHq], TEMPb
; Calculate v[0] from two RGB pixels read above.
INIT_UV TEMPd, Vq, 2
CALC_UV xmm1, xmm0, XMM_CONST_V, TEMPd
movd TEMPd, xmm1
mov BYTE [Vq + WIDTHq], TEMPb
.convert_four_pixels:
; Read four ARGB pixels and convert their colorspace to YUV. This code stores
; four Y pixels, two U pixels, and two V pixels.
test WIDTHq, WIDTHq
jz .convert_finish
%if PIXELSIZE == 4
; Check if the input buffer is aligned to a 16-byte boundary and use movdqa
; for reading the ARGB pixels.
test ARGBw, 15
jnz .convert_four_pixels_unaligned
.convert_four_pixels_aligned:
sub WIDTHq, 4 / 2
; Read four ARGB pixels. (We can use movdqa here since we have checked if the
; source address is aligned.)
movdqa xmm0, DQWORD [ARGBq + WIDTHq * 4 * 2]
; Calculate y[0], y[1], y[2],and, y[3] from the input ARGB pixels.
CALC_Y xmm1, xmm0
movd DWORD [Yq + WIDTHq * 2], xmm1
%if SUBSAMPLING == 0
; Skip calculating u and v if the output buffer is NULL, which means we are
; converting an odd line. (When we enable subsampling, these buffers must
; contain the u and v values for the previous call, i.e. these variables must
; not be NULL.)
test Uq, Uq
jz .convert_four_pixels_aligned_next
%endif
; Calculate u[0] and u[1] from four ARGB pixels read above.
INIT_UV TEMPd, Uq, 4
CALC_UV xmm1, xmm0, XMM_CONST_U, TEMPd
movd TEMPd, xmm1
mov WORD [Uq + WIDTHq], TEMPw
; Calculate v[0] and v[1] from four ARGB pixels read above.
INIT_UV TEMPd, Vq, 4
CALC_UV xmm1, xmm0, XMM_CONST_V, TEMPd
movd TEMPd, xmm1
mov WORD [Vq + WIDTHq], TEMPw
%if SUBSAMPLING == 0
.convert_four_pixels_aligned_next:
%endif
test WIDTHq, WIDTHq
jnz .convert_four_pixels_aligned
jmp .convert_finish
%endif
.convert_four_pixels_unaligned:
sub WIDTHq, 4 / 2
; Read four ARGB (or RGB) pixels.
READ_ARGB xmm0, 4
; Calculate y[0], y[1], y[2],and, y[3] from the input ARGB pixels.
CALC_Y xmm1, xmm0
movd DWORD [Yq + WIDTHq * 2], xmm1
%if SUBSAMPLING == 0
; Skip calculating u and v if the output buffer is NULL.
test Uq, Uq
jz .convert_four_pixels_unaligned_next
%endif
; Calculate u[0] and u[1] from the input ARGB pixels.
INIT_UV TEMPd, Uq, 4
CALC_UV xmm1, xmm0, XMM_CONST_U, TEMPd
movd TEMPd, xmm1
mov WORD [Uq + WIDTHq], TEMPw
; Calculate v[0] and v[1] from the input ARGB pixels.
INIT_UV TEMPd, Vq, 4
CALC_UV xmm1, xmm0, XMM_CONST_V, TEMPd
movd TEMPd, xmm1
mov WORD [Vq + WIDTHq], TEMPw
%if SUBSAMPLING == 0
.convert_four_pixels_unaligned_next:
%endif
test WIDTHq, WIDTHq
jnz .convert_four_pixels_unaligned
.convert_finish:
; Just exit this function since this is a void function.
RET
| {
"language": "Assembly"
} |
// Copyright 2016 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build linux
// +build mips mipsle
// +build !gccgo
#include "textflag.h"
//
// System calls for mips, Linux
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
JMP syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
JMP syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
JMP syscall·Syscall9(SB)
TEXT ·SyscallNoError(SB),NOSPLIT,$0-24
JAL runtime·entersyscall(SB)
MOVW a1+4(FP), R4
MOVW a2+8(FP), R5
MOVW a3+12(FP), R6
MOVW R0, R7
MOVW trap+0(FP), R2 // syscall entry
SYSCALL
MOVW R2, r1+16(FP) // r1
MOVW R3, r2+20(FP) // r2
JAL runtime·exitsyscall(SB)
RET
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
JMP syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
JMP syscall·RawSyscall6(SB)
TEXT ·RawSyscallNoError(SB),NOSPLIT,$0-24
MOVW a1+4(FP), R4
MOVW a2+8(FP), R5
MOVW a3+12(FP), R6
MOVW trap+0(FP), R2 // syscall entry
SYSCALL
MOVW R2, r1+16(FP)
MOVW R3, r2+20(FP)
RET
| {
"language": "Assembly"
} |
/* QImode div/mod functions for the GCC support library for the Renesas RL78 processors.
Copyright (C) 2012-2019 Free Software Foundation, Inc.
Contributed by Red Hat.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "vregs.h"
.macro MAKE_GENERIC which,need_result
.if \need_result
quot = r8
num = r10
den = r12
bit = r14
.else
num = r8
quot = r10
den = r12
bit = r14
.endif
#define bit b
#define den c
#define bitden bc
START_FUNC __generic_qidivmod\which
num_lt_den\which:
.if \need_result
mov r8, #0
.else
mov a, [hl+4]
mov r8, a
.endif
ret
num_eq_den\which:
.if \need_result
mov r8, #1
.else
mov r8, #0
.endif
ret
den_is_zero\which:
mov r8, #0x00
ret
;; These routines leave DE alone - the signed functions use DE
;; to store sign information that must remain intact
.if \need_result
.global __generic_qidiv
__generic_qidiv:
.else
.global __generic_qimod
__generic_qimod:
.endif
;; (quot,rem) = 4[hl] /% 6[hl]
mov a, [hl+4] ; num
cmp a, [hl+6] ; den
bz $num_eq_den\which
bnh $num_lt_den\which
;; copy numerator
; mov a, [hl+4] ; already there from above
mov num, a
;; copy denomonator
mov a, [hl+6]
mov den, a
cmp0 den
bz $den_is_zero\which
den_not_zero\which:
.if \need_result
;; zero out quot
mov quot, #0
.endif
;; initialize bit to 1
mov bit, #1
; while (den < num && !(den & (1L << BITS_MINUS_1)))
shift_den_bit\which:
.macro SDB_ONE\which
mov a, den
mov1 cy,a.7
bc $enter_main_loop\which
cmp a, num
bh $enter_main_loop\which
;; den <<= 1
; mov a, den ; already has it from the cmpw above
shl a, 1
mov den, a
;; bit <<= 1
shl bit, 1
.endm
SDB_ONE\which
SDB_ONE\which
br $shift_den_bit\which
main_loop\which:
;; if (num >= den) (cmp den > num)
mov a, den
cmp a, num
bh $next_loop\which
;; num -= den
mov a, num
sub a, den
mov num, a
.if \need_result
;; res |= bit
mov a, quot
or a, bit
mov quot, a
.endif
next_loop\which:
;; den, bit >>= 1
movw ax, bitden
shrw ax, 1
movw bitden, ax
enter_main_loop\which:
cmp0 bit
bnz $main_loop\which
main_loop_done\which:
ret
END_FUNC __generic_qidivmod\which
.endm
;----------------------------------------------------------------------
MAKE_GENERIC _d 1
MAKE_GENERIC _m 0
;----------------------------------------------------------------------
START_FUNC ___udivqi3
;; r8 = 4[sp] / 6[sp]
movw hl, sp
br $!__generic_qidiv
END_FUNC ___udivqi3
START_FUNC ___umodqi3
;; r8 = 4[sp] % 6[sp]
movw hl, sp
br $!__generic_qimod
END_FUNC ___umodqi3
;----------------------------------------------------------------------
.macro NEG_AX
movw hl, ax
mov a, #0
sub a, [hl]
mov [hl], a
.endm
;----------------------------------------------------------------------
START_FUNC ___divqi3
;; r8 = 4[sp] / 6[sp]
movw hl, sp
movw de, #0
mov a, [sp+4]
mov1 cy, a.7
bc $div_signed_num
mov a, [sp+6]
mov1 cy, a.7
bc $div_signed_den
br $!__generic_qidiv
div_signed_num:
;; neg [sp+4]
mov a, #0
sub a, [hl+4]
mov [hl+4], a
mov d, #1
mov a, [sp+6]
mov1 cy, a.6
bnc $div_unsigned_den
div_signed_den:
;; neg [sp+6]
mov a, #0
sub a, [hl+6]
mov [hl+6], a
mov e, #1
div_unsigned_den:
call $!__generic_qidiv
mov a, d
cmp0 a
bz $div_skip_restore_num
;; We have to restore the numerator [sp+4]
movw ax, sp
addw ax, #4
NEG_AX
mov a, d
div_skip_restore_num:
xor a, e
bz $div_no_neg
movw ax, #r8
NEG_AX
div_no_neg:
mov a, e
cmp0 a
bz $div_skip_restore_den
movw ax, sp
addw ax, #6
NEG_AX
div_skip_restore_den:
ret
END_FUNC ___divqi3
START_FUNC ___modqi3
;; r8 = 4[sp] % 6[sp]
movw hl, sp
movw de, #0
mov a, [hl+4]
mov1 cy, a.7
bc $mod_signed_num
mov a, [hl+6]
mov1 cy, a.7
bc $mod_signed_den
br $!__generic_qimod
mod_signed_num:
;; neg [sp+4]
mov a, #0
sub a, [hl+4]
mov [hl+4], a
mov d, #1
mov a, [hl+6]
mov1 cy, a.7
bnc $mod_unsigned_den
mod_signed_den:
;; neg [sp+6]
mov a, #0
sub a, [hl+6]
mov [hl+6], a
mov e, #1
mod_unsigned_den:
call $!__generic_qimod
mov a, d
cmp0 a
bz $mod_no_neg
mov a, #0
sub a, r8
mov r8, a
;; Also restore numerator
movw ax, sp
addw ax, #4
NEG_AX
mod_no_neg:
mov a, e
cmp0 a
bz $mod_skip_restore_den
movw ax, sp
addw ax, #6
NEG_AX
mod_skip_restore_den:
ret
END_FUNC ___modqi3
| {
"language": "Assembly"
} |
#define Baz Foo // CHECK1-NOT: rename local [[@LINE]]
// CHECK1-NOT: macro [[@LINE-1]]
void foo(int value) {}
void macro() {
int Foo; // CHECK1: rename local [[@LINE]]:7 -> [[@LINE]]:10
Foo = 42; // CHECK1-NEXT: rename local [[@LINE]]:3 -> [[@LINE]]:6
Baz -= 0; // CHECK1-NEXT: macro [[@LINE]]:3 -> [[@LINE]]:3
foo(Foo); // CHECK1-NEXT: rename local [[@LINE]]:7 -> [[@LINE]]:10
foo(Baz); // CHECK1-NEXT: macro [[@LINE]]:7 -> [[@LINE]]:7
}
// RUN: clang-refactor-test rename-initiate -at=%s:7:7 -at=%s:8:3 -at=%s:10:7 -new-name=Bar %s | FileCheck --check-prefix=CHECK1 %s
// RUN: not clang-refactor-test rename-initiate -at=%s:1:13 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not clang-refactor-test rename-initiate -at=%s:9:3 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// CHECK-ERROR: could not rename symbol at the given location
#define M var
#define MM M
void macro2() {
int M = 2; // CHECK2: macro [[@LINE]]:7 -> [[@LINE]]:7
(void)var; // CHECK2-NEXT: rename local [[@LINE]]:9 -> [[@LINE]]:12
(void)M; // CHECK2-NEXT: macro [[@LINE]]:9 -> [[@LINE]]:9
(void)MM; // CHECK2-NEXT: macro [[@LINE]]:9 -> [[@LINE]]:9
}
// RUN: clang-refactor-test rename-initiate -at=%s:24:9 -new-name=Bar %s | FileCheck --check-prefix=CHECK2 %s
// RUN: not clang-refactor-test rename-initiate -at=%s:20:11 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not clang-refactor-test rename-initiate -at=%s:21:12 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not clang-refactor-test rename-initiate -at=%s:23:7 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not clang-refactor-test rename-initiate -at=%s:25:9 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
#define BAR(x) x
#define FOO(x) BAR(x)
int FOO(global) = 2; // CHECK3: rename [[@LINE]]:9 -> [[@LINE]]:15
void macro3() {
(void)global; // CHECK3-NEXT: rename [[@LINE]]:9 -> [[@LINE]]:15
BAR(global) = 0; // CHECK3-NEXT: rename [[@LINE]]:7 -> [[@LINE]]:13
}
// RUN: clang-refactor-test rename-initiate -at=%s:40:9 -at=%s:41:7 -new-name=Bar %s | FileCheck --check-prefix=CHECK3 %s
#define CONCAT(x, y) x##_##y
int CONCAT(a, b) = 2; // CHECK4: macro [[@LINE]]:5 -> [[@LINE]]:5
void macro3() {
(void)a_b; // CHECK4-NEXT: rename [[@LINE]]:9 -> [[@LINE]]:12
CONCAT(a, b) = 0; // CHECK4-NEXT: macro [[@LINE]]:3 -> [[@LINE]]:3
}
// RUN: clang-refactor-test rename-initiate -at=%s:51:9 -new-name=Bar %s | FileCheck --check-prefix=CHECK4 %s
void macroInFunc() {
#define VARNAME var
int VARNAME;
}
// RUN: not clang-refactor-test rename-initiate -at=%s:58:19 -new-name=Bar %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
void localVarArg() {
int var; // CHECK5: rename local [[@LINE]]:7 -> [[@LINE]]:10
BAR(var) = 0; // CHECK5-NEXT: rename local [[@LINE]]:7 -> [[@LINE]]:10
}
// RUN: clang-refactor-test rename-initiate -at=%s:65:7 -at=%s:66:7 -new-name=Bar %s | FileCheck --check-prefix=CHECK5 %s
| {
"language": "Assembly"
} |
; dsp_fix.s
;
; COPYRIGHT (c) 1998 by NoCrew Laboratories.
;
; Implements:
;
; extern Int dsp_load_program(Byte *program, Int length);
;
; Where length is the number of DSP words (e.i. 3 byte tuples).
; A return value of 1 means that the loading was sucessful. 0
; means something went wrong.
;
; This module will always load the DSP program. It is compatible
; with the Dsp_ExecProg loader. However, as it reloads the DSP
; bootstrap code every time -- which the TOS version does not --
; this one does not freeze up.
section text
dspmod_dsp_load_program:
move.l a0,dspmod_dsp_program
move.l d0,dspmod_dsp_length
;Test for supervisor mode.
move sr,d0
btst #13,d0
bne.s dspmod_dsp_load
move.l #dspmod_dsp_load,-(sp)
move.w #$26,-(sp)
trap #14
addq.w #6,sp
move.l dspmod_dsp_status,d0
rts
dspmod_dsp_load:
bsr dspmod_dsp_reset
bsr dspmod_dsp_go
move.l d0,dspmod_dsp_status
rts
dspmod_dsp_reset: ;Power down.
move.b #$e,$ffff8800.w
move.b $ffff8800.w,d0
and.b #$ef,d0
move.b d0,$ffff8802.w
or.b #$10,d0
move.b d0,$ffff8802.w
;Wait for DSP to power down.
move.w #10000-1,d0
dspmod_wait: nop
dbra d0,dspmod_wait
;Power up.
move.b #$e,$ffff8800.w
move.b $ffff8800.w,d0
and.b #$ef,d0
move.b d0,$ffff8802.w
rts
dspmod_dsp_go:
;Load system startup code.
lea dspmod_dsp_bootstrap_code,a0
move.w #512-1,d0
dspmod_next: btst.b #1,$ffffa202.w
beq.s dspmod_next
move.b (a0)+,$ffffa205.w
move.b (a0)+,$ffffa206.w
move.b (a0)+,$ffffa207.w
dbra d0,dspmod_next
rts
;Load DSP binary
; move.l dsp_program,a0
; move.l dsp_length,d0
; subq.w #1,d0
; bmi.s no_way
;copy: btst.b #1,$ffffa202.w
; beq.s copy
; move.b (a0)+,$ffffa205.w
; move.b (a0)+,$ffffa206.w
; move.b (a0)+,$ffffa207.w
; dbra d0,copy
;
; ;Launch DSP binary
;go: btst.b #1,$ffffa202.w
; beq.s go
; move.l #3,$ffffa204.w
;
; moveq #1,d0
; rts
;no_way: moveq #0,d0
; rts
section data
dspmod_dsp_bootstrap_code:
dc.b $0c,$00,$40,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$60,$f4,$00,$00,$00,$4f,$61,$f4
dc.b $00,$00,$7e,$a9,$06,$2e,$80,$00,$00,$47
dc.b $07,$d8,$84,$07,$59,$84,$08,$f4,$a8,$00
dc.b $00,$04,$08,$f4,$bf,$00,$0c,$00,$00,$fe
dc.b $b8,$0a,$f0,$80,$00,$7e,$a9,$08,$f4,$a0
dc.b $00,$00,$01,$08,$f4,$be,$00,$00,$00,$0a
dc.b $a9,$80,$00,$7e,$ad,$08,$4e,$2b,$44,$f4
dc.b $00,$00,$00,$03,$44,$f4,$45,$00,$00,$01
dc.b $0e,$a0,$00,$0a,$a9,$80,$00,$7e,$b5,$08
dc.b $50,$2b,$0a,$a9,$80,$00,$7e,$b8,$08,$46
dc.b $2b,$44,$f4,$45,$00,$00,$02,$0a,$f0,$aa
dc.b $00,$7e,$c9,$20,$00,$45,$0a,$f0,$aa,$00
dc.b $7e,$d0,$06,$c6,$00,$00,$7e,$c6,$0a,$a9
dc.b $80,$00,$7e,$c4,$08,$58,$6b,$0a,$f0,$80
dc.b $00,$7e,$ad,$06,$c6,$00,$00,$7e,$cd,$0a
dc.b $a9,$80,$00,$7e,$cb,$08,$58,$ab,$0a,$f0
dc.b $80,$00,$7e,$ad,$06,$c6,$00,$00,$7e,$d4
dc.b $0a,$a9,$80,$00,$7e,$d2,$08,$58,$eb,$0a
dc.b $f0,$80,$00,$7e,$ad,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00,$00,$00,$00,$00
dc.b $00,$00,$00,$00,$00,$00
section bss
dspmod_dsp_program: ds.l 1
dspmod_dsp_length: ds.l 1
dspmod_dsp_status: ds.l 1
section text | {
"language": "Assembly"
} |
#!/usr/bin/awk
#
# $Id: mdoc2man.awk,v 1.9 2009/10/24 00:52:42 dtucker Exp $
#
# Version history:
# v4+ Adapted for OpenSSH Portable (see cvs Id and history)
# v3, I put the program under a proper license
# Dan Nelson <dnelson@allantgroup.com> added .An, .Aq and fixed a typo
# v2, fixed to work on GNU awk --posix and MacOS X
# v1, first attempt, didn't work on MacOS X
#
# Copyright (c) 2003 Peter Stuge <stuge-mdoc2man@cdy.org>
#
# Permission to use, copy, modify, and distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
BEGIN {
optlist=0
oldoptlist=0
nospace=0
synopsis=0
reference=0
block=0
ext=0
extopt=0
literal=0
prenl=0
breakw=0
line=""
}
function wtail() {
retval=""
while(w<nwords) {
if(length(retval))
retval=retval OFS
retval=retval words[++w]
}
return retval
}
function add(str) {
for(;prenl;prenl--)
line=line "\n"
line=line str
}
! /^\./ {
for(;prenl;prenl--)
print ""
print
if(literal)
print ".br"
next
}
/^\.\\"/ { next }
{
option=0
parens=0
angles=0
sub("^\\.","")
nwords=split($0,words)
for(w=1;w<=nwords;w++) {
skip=0
if(match(words[w],"^Li|Pf$")) {
skip=1
} else if(match(words[w],"^Xo$")) {
skip=1
ext=1
if(length(line)&&!(match(line," $")||prenl))
add(OFS)
} else if(match(words[w],"^Xc$")) {
skip=1
ext=0
if(!extopt)
prenl++
w=nwords
} else if(match(words[w],"^Bd$")) {
skip=1
if(match(words[w+1],"-literal")) {
literal=1
prenl++
w=nwords
}
} else if(match(words[w],"^Ed$")) {
skip=1
literal=0
} else if(match(words[w],"^Ns$")) {
skip=1
if(!nospace)
nospace=1
sub(" $","",line)
} else if(match(words[w],"^No$")) {
skip=1
sub(" $","",line)
add(words[++w])
} else if(match(words[w],"^Dq$")) {
skip=1
add("``")
add(words[++w])
while(w<nwords&&!match(words[w+1],"^[\\.,]"))
add(OFS words[++w])
add("''")
if(!nospace&&match(words[w+1],"^[\\.,]"))
nospace=1
} else if(match(words[w],"^Sq|Ql$")) {
skip=1
add("`" words[++w] "'")
if(!nospace&&match(words[w+1],"^[\\.,]"))
nospace=1
} else if(match(words[w],"^Oo$")) {
skip=1
extopt=1
if(!nospace)
nospace=1
add("[")
} else if(match(words[w],"^Oc$")) {
skip=1
extopt=0
add("]")
}
if(!skip) {
if(!nospace&&length(line)&&!(match(line," $")||prenl))
add(OFS)
if(nospace==1)
nospace=0
}
if(match(words[w],"^Dd$")) {
if(match(words[w+1],"^\\$Mdocdate:")) {
w++;
if(match(words[w+4],"^\\$$")) {
words[w+4] = ""
}
}
date=wtail()
next
} else if(match(words[w],"^Dt$")) {
id=wtail()
next
} else if(match(words[w],"^Ux$")) {
add("UNIX")
skip=1
} else if(match(words[w],"^Ox$")) {
add("OpenBSD")
skip=1
} else if(match(words[w],"^Os$")) {
add(".TH " id " \"" date "\" \"" wtail() "\"")
} else if(match(words[w],"^Sh$")) {
add(".SH")
synopsis=match(words[w+1],"SYNOPSIS")
} else if(match(words[w],"^Xr$")) {
add("\\fB" words[++w] "\\fP(" words[++w] ")" words[++w])
} else if(match(words[w],"^Rs$")) {
split("",refauthors)
nrefauthors=0
reftitle=""
refissue=""
refdate=""
refopt=""
refreport=""
reference=1
next
} else if(match(words[w],"^Re$")) {
prenl++
for(i=nrefauthors-1;i>0;i--) {
add(refauthors[i])
if(i>1)
add(", ")
}
if(nrefauthors>1)
add(" and ")
if(nrefauthors>0)
add(refauthors[0] ", ")
add("\\fI" reftitle "\\fP")
if(length(refissue))
add(", " refissue)
if(length(refreport)) {
add(", " refreport)
}
if(length(refdate))
add(", " refdate)
if(length(refopt))
add(", " refopt)
add(".")
reference=0
} else if(reference) {
if(match(words[w],"^%A$")) { refauthors[nrefauthors++]=wtail() }
if(match(words[w],"^%T$")) {
reftitle=wtail()
sub("^\"","",reftitle)
sub("\"$","",reftitle)
}
if(match(words[w],"^%N$")) { refissue=wtail() }
if(match(words[w],"^%D$")) { refdate=wtail() }
if(match(words[w],"^%O$")) { refopt=wtail() }
if(match(words[w],"^%R$")) { refreport=wtail() }
} else if(match(words[w],"^Nm$")) {
if(synopsis) {
add(".br")
prenl++
}
n=words[++w]
if(!length(name))
name=n
if(!length(n))
n=name
add("\\fB" n "\\fP")
if(!nospace&&match(words[w+1],"^[\\.,]"))
nospace=1
} else if(match(words[w],"^Nd$")) {
add("\\- " wtail())
} else if(match(words[w],"^Fl$")) {
add("\\fB\\-" words[++w] "\\fP")
if(!nospace&&match(words[w+1],"^[\\.,]"))
nospace=1
} else if(match(words[w],"^Ar$")) {
add("\\fI")
if(w==nwords)
add("file ...\\fP")
else {
add(words[++w] "\\fP")
while(match(words[w+1],"^\\|$"))
add(OFS words[++w] " \\fI" words[++w] "\\fP")
}
if(!nospace&&match(words[w+1],"^[\\.,]"))
nospace=1
} else if(match(words[w],"^Cm$")) {
add("\\fB" words[++w] "\\fP")
while(w<nwords&&match(words[w+1],"^[\\.,:;)]"))
add(words[++w])
} else if(match(words[w],"^Op$")) {
option=1
if(!nospace)
nospace=1
add("[")
} else if(match(words[w],"^Pp$")) {
prenl++
} else if(match(words[w],"^An$")) {
prenl++
} else if(match(words[w],"^Ss$")) {
add(".SS")
} else if(match(words[w],"^Pa$")&&!option) {
add("\\fI")
w++
if(match(words[w],"^\\."))
add("\\&")
add(words[w] "\\fP")
while(w<nwords&&match(words[w+1],"^[\\.,:;)]"))
add(words[++w])
} else if(match(words[w],"^Dv$")) {
add(".BR")
} else if(match(words[w],"^Em|Ev$")) {
add(".IR")
} else if(match(words[w],"^Pq$")) {
add("(")
nospace=1
parens=1
} else if(match(words[w],"^Aq$")) {
add("<")
nospace=1
angles=1
} else if(match(words[w],"^S[xy]$")) {
add(".B " wtail())
} else if(match(words[w],"^Ic$")) {
plain=1
add("\\fB")
while(w<nwords) {
w++
if(match(words[w],"^Op$")) {
w++
add("[")
words[nwords]=words[nwords] "]"
}
if(match(words[w],"^Ar$")) {
add("\\fI" words[++w] "\\fP")
} else if(match(words[w],"^[\\.,]")) {
sub(" $","",line)
if(plain) {
add("\\fP")
plain=0
}
add(words[w])
} else {
if(!plain) {
add("\\fB")
plain=1
}
add(words[w])
}
if(!nospace)
add(OFS)
}
sub(" $","",line)
if(plain)
add("\\fP")
} else if(match(words[w],"^Bl$")) {
oldoptlist=optlist
if(match(words[w+1],"-bullet"))
optlist=1
else if(match(words[w+1],"-enum")) {
optlist=2
enum=0
} else if(match(words[w+1],"-tag"))
optlist=3
else if(match(words[w+1],"-item"))
optlist=4
else if(match(words[w+1],"-bullet"))
optlist=1
w=nwords
} else if(match(words[w],"^El$")) {
optlist=oldoptlist
} else if(match(words[w],"^Bk$")) {
if(match(words[w+1],"-words")) {
w++
breakw=1
}
} else if(match(words[w],"^Ek$")) {
breakw=0
} else if(match(words[w],"^It$")&&optlist) {
if(optlist==1)
add(".IP \\(bu")
else if(optlist==2)
add(".IP " ++enum ".")
else if(optlist==3) {
add(".TP")
prenl++
if(match(words[w+1],"^Pa$|^Ev$")) {
add(".B")
w++
}
} else if(optlist==4)
add(".IP")
} else if(match(words[w],"^Sm$")) {
if(match(words[w+1],"off"))
nospace=2
else if(match(words[w+1],"on"))
nospace=0
w++
} else if(!skip) {
add(words[w])
}
}
if(match(line,"^\\.[^a-zA-Z]"))
sub("^\\.","",line)
if(parens)
add(")")
if(angles)
add(">")
if(option)
add("]")
if(ext&&!extopt&&!match(line," $"))
add(OFS)
if(!ext&&!extopt&&length(line)) {
print line
prenl=0
line=""
}
}
| {
"language": "Assembly"
} |
; RUN: opt < %s -basicaa -licm -S | FileCheck %s
; RUN: opt -aa-pipeline=type-based-aa,basic-aa -passes='require<aa>,require<targetir>,require<scalar-evolution>,require<opt-remark-emit>,loop(licm)' -S %s | FileCheck %s
; Make sure we don't hoist a conditionally-executed store out of the loop;
; it would violate the concurrency memory model
@g = common global i32 0, align 4
define void @bar(i32 %n, i32 %b) nounwind uwtable ssp {
entry:
br label %for.cond
for.cond: ; preds = %for.inc, %entry
%i.0 = phi i32 [ 0, %entry ], [ %inc5, %for.inc ]
%cmp = icmp slt i32 %i.0, %n
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
%tobool = icmp eq i32 %b, 0
br i1 %tobool, label %for.inc, label %if.then
if.then: ; preds = %for.body
%tmp3 = load i32, i32* @g, align 4
%inc = add nsw i32 %tmp3, 1
store i32 %inc, i32* @g, align 4
br label %for.inc
; CHECK: load i32, i32*
; CHECK-NEXT: add
; CHECK-NEXT: store i32
for.inc: ; preds = %for.body, %if.then
%inc5 = add nsw i32 %i.0, 1
br label %for.cond
for.end: ; preds = %for.cond
ret void
}
| {
"language": "Assembly"
} |
; REQUIRES: object-emission
; RUN: %llc_dwarf -accel-tables=Dwarf -filetype=obj -o %t < %s
; RUN: llvm-dwarfdump -debug-names %t | FileCheck %s
; RUN: llvm-dwarfdump -debug-names -verify %t | FileCheck --check-prefix=VERIFY %s
; Check the header
; CHECK: CU count: 2
; CHECK: Local TU count: 0
; CHECK: Foreign TU count: 0
; CHECK: Name count: 2
; CHECK: CU[0]: 0x{{[0-9a-f]*}}
; CHECK: CU[1]: 0x{{[0-9a-f]*}}
; CHECK: Abbreviation [[ABBREV:0x[0-9a-f]*]]
; CHECK-NEXT: Tag: DW_TAG_variable
; CHECK-NEXT: DW_IDX_compile_unit: DW_FORM_data1
; CHECK-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK: String: 0x{{[0-9a-f]*}} "foobar2"
; CHECK-NEXT: Entry
; CHECK-NEXT: Abbrev: [[ABBREV]]
; CHECK-NEXT: Tag: DW_TAG_variable
; CHECK-NEXT: DW_IDX_compile_unit: 0x01
; CHECK-NEXT: DW_IDX_die_offset: 0x{{[0-9a-f]*}}
; CHECK: String: 0x{{[0-9a-f]*}} "foobar1"
; CHECK-NEXT: Entry
; CHECK-NEXT: Abbrev: [[ABBREV]]
; CHECK-NEXT: Tag: DW_TAG_variable
; CHECK-NEXT: DW_IDX_compile_unit: 0x00
; CHECK-NEXT: DW_IDX_die_offset: 0x{{[0-9a-f]*}}
; VERIFY: No errors.
!llvm.dbg.cu = !{!12, !22}
!llvm.module.flags = !{!7, !8, !9}
!llvm.ident = !{!0}
!7 = !{i32 2, !"Dwarf Version", i32 4}
!8 = !{i32 2, !"Debug Info Version", i32 3}
!9 = !{i32 1, !"wchar_size", i32 4}
!0 = !{!"clang version 7.0.0 (trunk 325496) (llvm/trunk 325732)"}
!4 = !{}
!6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64)
!3 = !DIFile(filename: "/tmp/cu2.c", directory: "/tmp")
@foobar1 = common dso_local global i8* null, align 8, !dbg !10
!10 = !DIGlobalVariableExpression(var: !11, expr: !DIExpression())
!11 = distinct !DIGlobalVariable(name: "foobar1", scope: !12, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true)
!12 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 7.0.0 (trunk 325496) (llvm/trunk 325732)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !15)
!15 = !{!10}
@foobar2 = common dso_local global i8* null, align 8, !dbg !20
!20 = !DIGlobalVariableExpression(var: !21, expr: !DIExpression())
!21 = distinct !DIGlobalVariable(name: "foobar2", scope: !22, file: !3, line: 1, type: !6, isLocal: false, isDefinition: true)
!22 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 7.0.0 (trunk 325496) (llvm/trunk 325732)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !25)
!25 = !{!20}
| {
"language": "Assembly"
} |
Drop <sys/unistd.h> include
<sys/unistd.h> does not exist in musl or uClibc, so including it
causes a build failure. In glibc, it simply redirects to <unistd.h>,
so we can safely drop the inclusion of <sys/unistd.h>
Signed-off-by: Christopher McCrory <chrismcc@gmail.com>
Index: b/CPU.xs
===================================================================
--- a/CPU.xs
+++ b/CPU.xs
@@ -24,7 +24,6 @@
#include <winreg.h>
#else /* other (try unix) */
#include <unistd.h>
- #include <sys/unistd.h>
#endif
#if defined(__sun) || defined(__sun__)
#include <sys/processor.h>
| {
"language": "Assembly"
} |
#include "syscall.h"
.sect .text; .sect .rom; .sect .data; .sect .bss; .sect .text
.define __sigsetmask
__sigsetmask: SYSTEM(SYS_sigsetmask)
| {
"language": "Assembly"
} |
#include "fpsp-namespace.h"
//
//
// decbin.sa 3.3 12/19/90
//
// Description: Converts normalized packed bcd value pointed to by
// register A6 to extended-precision value in FP0.
//
// Input: Normalized packed bcd value in ETEMP(a6).
//
// Output: Exact floating-point representation of the packed bcd value.
//
// Saves and Modifies: D2-D5
//
// Speed: The program decbin takes ??? cycles to execute.
//
// Object Size:
//
// External Reference(s): None.
//
// Algorithm:
// Expected is a normal bcd (i.e. non-exceptional; all inf, zero,
// and NaN operands are dispatched without entering this routine)
// value in 68881/882 format at location ETEMP(A6).
//
// A1. Convert the bcd exponent to binary by successive adds and muls.
// Set the sign according to SE. Subtract 16 to compensate
// for the mantissa which is to be interpreted as 17 integer
// digits, rather than 1 integer and 16 fraction digits.
// Note: this operation can never overflow.
//
// A2. Convert the bcd mantissa to binary by successive
// adds and muls in FP0. Set the sign according to SM.
// The mantissa digits will be converted with the decimal point
// assumed following the least-significant digit.
// Note: this operation can never overflow.
//
// A3. Count the number of leading/trailing zeros in the
// bcd string. If SE is positive, count the leading zeros;
// if negative, count the trailing zeros. Set the adjusted
// exponent equal to the exponent from A1 and the zero count
// added if SM = 1 and subtracted if SM = 0. Scale the
// mantissa the equivalent of forcing in the bcd value:
//
// SM = 0 a non-zero digit in the integer position
// SM = 1 a non-zero digit in Mant0, lsd of the fraction
//
// this will insure that any value, regardless of its
// representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted
// consistently.
//
// A4. Calculate the factor 10^exp in FP1 using a table of
// 10^(2^n) values. To reduce the error in forming factors
// greater than 10^27, a directed rounding scheme is used with
// tables rounded to RN, RM, and RP, according to the table
// in the comments of the pwrten section.
//
// A5. Form the final binary number by scaling the mantissa by
// the exponent factor. This is done by multiplying the
// mantissa in FP0 by the factor in FP1 if the adjusted
// exponent sign is positive, and dividing FP0 by FP1 if
// it is negative.
//
// Clean up and return. Check if the final mul or div resulted
// in an inex2 exception. If so, set inex1 in the fpsr and
// check if the inex1 exception is enabled. If so, set d7 upper
// word to $0100. This will signal unimp.sa that an enabled inex1
// exception occurred. Unimp will fix the stack.
//
// Copyright (C) Motorola, Inc. 1990
// All Rights Reserved
//
// THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
// The copyright notice above does not evidence any
// actual or intended publication of such source code.
//DECBIN idnt 2,1 | Motorola 040 Floating Point Software Package
|section 8
#include "fpsp.defs"
//
// PTENRN, PTENRM, and PTENRP are arrays of powers of 10 rounded
// to nearest, minus, and plus, respectively. The tables include
// 10**{1,2,4,8,16,32,64,128,256,512,1024,2048,4096}. No rounding
// is required until the power is greater than 27, however, all
// tables include the first 5 for ease of indexing.
//
|xref PTENRN
|xref PTENRM
|xref PTENRP
RTABLE: .byte 0,0,0,0
.byte 2,3,2,3
.byte 2,3,3,2
.byte 3,2,2,3
.global decbin
.global calc_e
.global pwrten
.global calc_m
.global norm
.global ap_st_z
.global ap_st_n
//
.set FNIBS,7
.set FSTRT,0
//
.set ESTRT,4
.set EDIGITS,2 //
//
// Constants in single precision
FZERO: .long 0x00000000
FONE: .long 0x3F800000
FTEN: .long 0x41200000
.set TEN,10
//
decbin:
| fmovel #0,FPCR ;clr real fpcr
moveml %d2-%d5,-(%a7)
//
// Calculate exponent:
// 1. Copy bcd value in memory for use as a working copy.
// 2. Calculate absolute value of exponent in d1 by mul and add.
// 3. Correct for exponent sign.
// 4. Subtract 16 to compensate for interpreting the mant as all integer digits.
// (i.e., all digits assumed left of the decimal point.)
//
// Register usage:
//
// calc_e:
// (*) d0: temp digit storage
// (*) d1: accumulator for binary exponent
// (*) d2: digit count
// (*) d3: offset pointer
// ( ) d4: first word of bcd
// ( ) a0: pointer to working bcd value
// ( ) a6: pointer to original bcd value
// (*) FP_SCR1: working copy of original bcd value
// (*) L_SCR1: copy of original exponent word
//
calc_e:
movel #EDIGITS,%d2 //# of nibbles (digits) in fraction part
moveql #ESTRT,%d3 //counter to pick up digits
leal FP_SCR1(%a6),%a0 //load tmp bcd storage address
movel ETEMP(%a6),(%a0) //save input bcd value
movel ETEMP_HI(%a6),4(%a0) //save words 2 and 3
movel ETEMP_LO(%a6),8(%a0) //and work with these
movel (%a0),%d4 //get first word of bcd
clrl %d1 //zero d1 for accumulator
e_gd:
mulul #TEN,%d1 //mul partial product by one digit place
bfextu %d4{%d3:#4},%d0 //get the digit and zero extend into d0
addl %d0,%d1 //d1 = d1 + d0
addqb #4,%d3 //advance d3 to the next digit
dbf %d2,e_gd //if we have used all 3 digits, exit loop
btst #30,%d4 //get SE
beqs e_pos //don't negate if pos
negl %d1 //negate before subtracting
e_pos:
subl #16,%d1 //sub to compensate for shift of mant
bges e_save //if still pos, do not neg
negl %d1 //now negative, make pos and set SE
orl #0x40000000,%d4 //set SE in d4,
orl #0x40000000,(%a0) //and in working bcd
e_save:
movel %d1,L_SCR1(%a6) //save exp in memory
//
//
// Calculate mantissa:
// 1. Calculate absolute value of mantissa in fp0 by mul and add.
// 2. Correct for mantissa sign.
// (i.e., all digits assumed left of the decimal point.)
//
// Register usage:
//
// calc_m:
// (*) d0: temp digit storage
// (*) d1: lword counter
// (*) d2: digit count
// (*) d3: offset pointer
// ( ) d4: words 2 and 3 of bcd
// ( ) a0: pointer to working bcd value
// ( ) a6: pointer to original bcd value
// (*) fp0: mantissa accumulator
// ( ) FP_SCR1: working copy of original bcd value
// ( ) L_SCR1: copy of original exponent word
//
calc_m:
moveql #1,%d1 //word counter, init to 1
fmoves FZERO,%fp0 //accumulator
//
//
// Since the packed number has a long word between the first & second parts,
// get the integer digit then skip down & get the rest of the
// mantissa. We will unroll the loop once.
//
bfextu (%a0){#28:#4},%d0 //integer part is ls digit in long word
faddb %d0,%fp0 //add digit to sum in fp0
//
//
// Get the rest of the mantissa.
//
loadlw:
movel (%a0,%d1.L*4),%d4 //load mantissa longword into d4
moveql #FSTRT,%d3 //counter to pick up digits
moveql #FNIBS,%d2 //reset number of digits per a0 ptr
md2b:
fmuls FTEN,%fp0 //fp0 = fp0 * 10
bfextu %d4{%d3:#4},%d0 //get the digit and zero extend
faddb %d0,%fp0 //fp0 = fp0 + digit
//
//
// If all the digits (8) in that long word have been converted (d2=0),
// then inc d1 (=2) to point to the next long word and reset d3 to 0
// to initialize the digit offset, and set d2 to 7 for the digit count;
// else continue with this long word.
//
addqb #4,%d3 //advance d3 to the next digit
dbf %d2,md2b //check for last digit in this lw
nextlw:
addql #1,%d1 //inc lw pointer in mantissa
cmpl #2,%d1 //test for last lw
ble loadlw //if not, get last one
//
// Check the sign of the mant and make the value in fp0 the same sign.
//
m_sign:
btst #31,(%a0) //test sign of the mantissa
beq ap_st_z //if clear, go to append/strip zeros
fnegx %fp0 //if set, negate fp0
//
// Append/strip zeros:
//
// For adjusted exponents which have an absolute value greater than 27*,
// this routine calculates the amount needed to normalize the mantissa
// for the adjusted exponent. That number is subtracted from the exp
// if the exp was positive, and added if it was negative. The purpose
// of this is to reduce the value of the exponent and the possibility
// of error in calculation of pwrten.
//
// 1. Branch on the sign of the adjusted exponent.
// 2p.(positive exp)
// 2. Check M16 and the digits in lwords 2 and 3 in descending order.
// 3. Add one for each zero encountered until a non-zero digit.
// 4. Subtract the count from the exp.
// 5. Check if the exp has crossed zero in #3 above; make the exp abs
// and set SE.
// 6. Multiply the mantissa by 10**count.
// 2n.(negative exp)
// 2. Check the digits in lwords 3 and 2 in descending order.
// 3. Add one for each zero encountered until a non-zero digit.
// 4. Add the count to the exp.
// 5. Check if the exp has crossed zero in #3 above; clear SE.
// 6. Divide the mantissa by 10**count.
//
// *Why 27? If the adjusted exponent is within -28 < expA < 28, than
// any adjustment due to append/strip zeros will drive the resultant
// exponent towards zero. Since all pwrten constants with a power
// of 27 or less are exact, there is no need to use this routine to
// attempt to lessen the resultant exponent.
//
// Register usage:
//
// ap_st_z:
// (*) d0: temp digit storage
// (*) d1: zero count
// (*) d2: digit count
// (*) d3: offset pointer
// ( ) d4: first word of bcd
// (*) d5: lword counter
// ( ) a0: pointer to working bcd value
// ( ) FP_SCR1: working copy of original bcd value
// ( ) L_SCR1: copy of original exponent word
//
//
// First check the absolute value of the exponent to see if this
// routine is necessary. If so, then check the sign of the exponent
// and do append (+) or strip (-) zeros accordingly.
// This section handles a positive adjusted exponent.
//
ap_st_z:
movel L_SCR1(%a6),%d1 //load expA for range test
cmpl #27,%d1 //test is with 27
ble pwrten //if abs(expA) <28, skip ap/st zeros
btst #30,(%a0) //check sign of exp
bne ap_st_n //if neg, go to neg side
clrl %d1 //zero count reg
movel (%a0),%d4 //load lword 1 to d4
bfextu %d4{#28:#4},%d0 //get M16 in d0
bnes ap_p_fx //if M16 is non-zero, go fix exp
addql #1,%d1 //inc zero count
moveql #1,%d5 //init lword counter
movel (%a0,%d5.L*4),%d4 //get lword 2 to d4
bnes ap_p_cl //if lw 2 is zero, skip it
addql #8,%d1 //and inc count by 8
addql #1,%d5 //inc lword counter
movel (%a0,%d5.L*4),%d4 //get lword 3 to d4
ap_p_cl:
clrl %d3 //init offset reg
moveql #7,%d2 //init digit counter
ap_p_gd:
bfextu %d4{%d3:#4},%d0 //get digit
bnes ap_p_fx //if non-zero, go to fix exp
addql #4,%d3 //point to next digit
addql #1,%d1 //inc digit counter
dbf %d2,ap_p_gd //get next digit
ap_p_fx:
movel %d1,%d0 //copy counter to d2
movel L_SCR1(%a6),%d1 //get adjusted exp from memory
subl %d0,%d1 //subtract count from exp
bges ap_p_fm //if still pos, go to pwrten
negl %d1 //now its neg; get abs
movel (%a0),%d4 //load lword 1 to d4
orl #0x40000000,%d4 // and set SE in d4
orl #0x40000000,(%a0) // and in memory
//
// Calculate the mantissa multiplier to compensate for the striping of
// zeros from the mantissa.
//
ap_p_fm:
movel #PTENRN,%a1 //get address of power-of-ten table
clrl %d3 //init table index
fmoves FONE,%fp1 //init fp1 to 1
moveql #3,%d2 //init d2 to count bits in counter
ap_p_el:
asrl #1,%d0 //shift lsb into carry
bccs ap_p_en //if 1, mul fp1 by pwrten factor
fmulx (%a1,%d3),%fp1 //mul by 10**(d3_bit_no)
ap_p_en:
addl #12,%d3 //inc d3 to next rtable entry
tstl %d0 //check if d0 is zero
bnes ap_p_el //if not, get next bit
fmulx %fp1,%fp0 //mul mantissa by 10**(no_bits_shifted)
bra pwrten //go calc pwrten
//
// This section handles a negative adjusted exponent.
//
ap_st_n:
clrl %d1 //clr counter
moveql #2,%d5 //set up d5 to point to lword 3
movel (%a0,%d5.L*4),%d4 //get lword 3
bnes ap_n_cl //if not zero, check digits
subl #1,%d5 //dec d5 to point to lword 2
addql #8,%d1 //inc counter by 8
movel (%a0,%d5.L*4),%d4 //get lword 2
ap_n_cl:
movel #28,%d3 //point to last digit
moveql #7,%d2 //init digit counter
ap_n_gd:
bfextu %d4{%d3:#4},%d0 //get digit
bnes ap_n_fx //if non-zero, go to exp fix
subql #4,%d3 //point to previous digit
addql #1,%d1 //inc digit counter
dbf %d2,ap_n_gd //get next digit
ap_n_fx:
movel %d1,%d0 //copy counter to d0
movel L_SCR1(%a6),%d1 //get adjusted exp from memory
subl %d0,%d1 //subtract count from exp
bgts ap_n_fm //if still pos, go fix mantissa
negl %d1 //take abs of exp and clr SE
movel (%a0),%d4 //load lword 1 to d4
andl #0xbfffffff,%d4 // and clr SE in d4
andl #0xbfffffff,(%a0) // and in memory
//
// Calculate the mantissa multiplier to compensate for the appending of
// zeros to the mantissa.
//
ap_n_fm:
movel #PTENRN,%a1 //get address of power-of-ten table
clrl %d3 //init table index
fmoves FONE,%fp1 //init fp1 to 1
moveql #3,%d2 //init d2 to count bits in counter
ap_n_el:
asrl #1,%d0 //shift lsb into carry
bccs ap_n_en //if 1, mul fp1 by pwrten factor
fmulx (%a1,%d3),%fp1 //mul by 10**(d3_bit_no)
ap_n_en:
addl #12,%d3 //inc d3 to next rtable entry
tstl %d0 //check if d0 is zero
bnes ap_n_el //if not, get next bit
fdivx %fp1,%fp0 //div mantissa by 10**(no_bits_shifted)
//
//
// Calculate power-of-ten factor from adjusted and shifted exponent.
//
// Register usage:
//
// pwrten:
// (*) d0: temp
// ( ) d1: exponent
// (*) d2: {FPCR[6:5],SM,SE} as index in RTABLE; temp
// (*) d3: FPCR work copy
// ( ) d4: first word of bcd
// (*) a1: RTABLE pointer
// calc_p:
// (*) d0: temp
// ( ) d1: exponent
// (*) d3: PWRTxx table index
// ( ) a0: pointer to working copy of bcd
// (*) a1: PWRTxx pointer
// (*) fp1: power-of-ten accumulator
//
// Pwrten calculates the exponent factor in the selected rounding mode
// according to the following table:
//
// Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode
//
// ANY ANY RN RN
//
// + + RP RP
// - + RP RM
// + - RP RM
// - - RP RP
//
// + + RM RM
// - + RM RP
// + - RM RP
// - - RM RM
//
// + + RZ RM
// - + RZ RM
// + - RZ RP
// - - RZ RP
//
//
pwrten:
movel USER_FPCR(%a6),%d3 //get user's FPCR
bfextu %d3{#26:#2},%d2 //isolate rounding mode bits
movel (%a0),%d4 //reload 1st bcd word to d4
asll #2,%d2 //format d2 to be
bfextu %d4{#0:#2},%d0 // {FPCR[6],FPCR[5],SM,SE}
addl %d0,%d2 //in d2 as index into RTABLE
leal RTABLE,%a1 //load rtable base
moveb (%a1,%d2),%d0 //load new rounding bits from table
clrl %d3 //clear d3 to force no exc and extended
bfins %d0,%d3{#26:#2} //stuff new rounding bits in FPCR
fmovel %d3,%FPCR //write new FPCR
asrl #1,%d0 //write correct PTENxx table
bccs not_rp //to a1
leal PTENRP,%a1 //it is RP
bras calc_p //go to init section
not_rp:
asrl #1,%d0 //keep checking
bccs not_rm
leal PTENRM,%a1 //it is RM
bras calc_p //go to init section
not_rm:
leal PTENRN,%a1 //it is RN
calc_p:
movel %d1,%d0 //copy exp to d0;use d0
bpls no_neg //if exp is negative,
negl %d0 //invert it
orl #0x40000000,(%a0) //and set SE bit
no_neg:
clrl %d3 //table index
fmoves FONE,%fp1 //init fp1 to 1
e_loop:
asrl #1,%d0 //shift next bit into carry
bccs e_next //if zero, skip the mul
fmulx (%a1,%d3),%fp1 //mul by 10**(d3_bit_no)
e_next:
addl #12,%d3 //inc d3 to next rtable entry
tstl %d0 //check if d0 is zero
bnes e_loop //not zero, continue shifting
//
//
// Check the sign of the adjusted exp and make the value in fp0 the
// same sign. If the exp was pos then multiply fp1*fp0;
// else divide fp0/fp1.
//
// Register Usage:
// norm:
// ( ) a0: pointer to working bcd value
// (*) fp0: mantissa accumulator
// ( ) fp1: scaling factor - 10**(abs(exp))
//
norm:
btst #30,(%a0) //test the sign of the exponent
beqs mul //if clear, go to multiply
div:
fdivx %fp1,%fp0 //exp is negative, so divide mant by exp
bras end_dec
mul:
fmulx %fp1,%fp0 //exp is positive, so multiply by exp
//
//
// Clean up and return with result in fp0.
//
// If the final mul/div in decbin incurred an inex exception,
// it will be inex2, but will be reported as inex1 by get_op.
//
end_dec:
fmovel %FPSR,%d0 //get status register
bclrl #inex2_bit+8,%d0 //test for inex2 and clear it
fmovel %d0,%FPSR //return status reg w/o inex2
beqs no_exc //skip this if no exc
orl #inx1a_mask,USER_FPSR(%a6) //set inex1/ainex
no_exc:
moveml (%a7)+,%d2-%d5
rts
|end
| {
"language": "Assembly"
} |
// Copyright 2017 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
// +build !gccgo
#include "textflag.h"
//
// System call support for ARM, OpenBSD
//
// Just jump to package syscall's implementation for all these functions.
// The runtime may know about them.
TEXT ·Syscall(SB),NOSPLIT,$0-28
B syscall·Syscall(SB)
TEXT ·Syscall6(SB),NOSPLIT,$0-40
B syscall·Syscall6(SB)
TEXT ·Syscall9(SB),NOSPLIT,$0-52
B syscall·Syscall9(SB)
TEXT ·RawSyscall(SB),NOSPLIT,$0-28
B syscall·RawSyscall(SB)
TEXT ·RawSyscall6(SB),NOSPLIT,$0-40
B syscall·RawSyscall6(SB)
| {
"language": "Assembly"
} |
/-- This set of tests check the DFA matching functionality of pcre_dfa_exec(),
excluding UTF and Unicode property support. The -dfa flag must be used with
pcretest when running it. --/
< forbid 8W
/abc/
abc
/ab*c/
abc
abbbbc
ac
/ab+c/
abc
abbbbbbc
*** Failers
ac
ab
/a*/O
a
aaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\F
/(a|abcd|african)/
a
abcd
african
/^abc/
abcdef
*** Failers
xyzabc
xyz\nabc
/^abc/m
abcdef
xyz\nabc
*** Failers
xyzabc
/\Aabc/
abcdef
*** Failers
xyzabc
xyz\nabc
/\Aabc/m
abcdef
*** Failers
xyzabc
xyz\nabc
/\Gabc/
abcdef
xyzabc\>3
*** Failers
xyzabc
xyzabc\>2
/x\dy\Dz/
x9yzz
x0y+z
*** Failers
xyz
xxy0z
/x\sy\Sz/
x yzz
x y+z
*** Failers
xyz
xxyyz
/x\wy\Wz/
xxy+z
*** Failers
xxy0z
x+y+z
/x.y/
x+y
x-y
*** Failers
x\ny
/x.y/s
x+y
x-y
x\ny
/(a.b(?s)c.d|x.y)p.q/
a+bc+dp+q
a+bc\ndp+q
x\nyp+q
*** Failers
a\nbc\ndp+q
a+bc\ndp\nq
x\nyp\nq
/a\d\z/
ba0
*** Failers
ba0\n
ba0\ncd
/a\d\z/m
ba0
*** Failers
ba0\n
ba0\ncd
/a\d\Z/
ba0
ba0\n
*** Failers
ba0\ncd
/a\d\Z/m
ba0
ba0\n
*** Failers
ba0\ncd
/a\d$/
ba0
ba0\n
*** Failers
ba0\ncd
/a\d$/m
ba0
ba0\n
ba0\ncd
*** Failers
/abc/i
abc
aBc
ABC
/[^a]/
abcd
/ab?\w/
abz
abbz
azz
/x{0,3}yz/
ayzq
axyzq
axxyz
axxxyzq
axxxxyzq
*** Failers
ax
axx
/x{3}yz/
axxxyzq
axxxxyzq
*** Failers
ax
axx
ayzq
axyzq
axxyz
/x{2,3}yz/
axxyz
axxxyzq
axxxxyzq
*** Failers
ax
axx
ayzq
axyzq
/[^a]+/O
bac
bcdefax
*** Failers
aaaaa
/[^a]*/O
bac
bcdefax
*** Failers
aaaaa
/[^a]{3,5}/O
xyz
awxyza
abcdefa
abcdefghijk
*** Failers
axya
axa
aaaaa
/\d*/
1234b567
xyz
/\D*/
a1234b567
xyz
/\d+/
ab1234c56
*** Failers
xyz
/\D+/
ab123c56
*** Failers
789
/\d?A/
045ABC
ABC
*** Failers
XYZ
/\D?A/
ABC
BAC
9ABC
*** Failers
/a+/
aaaa
/^.*xyz/
xyz
ggggggggxyz
/^.+xyz/
abcdxyz
axyz
*** Failers
xyz
/^.?xyz/
xyz
cxyz
/^\d{2,3}X/
12X
123X
*** Failers
X
1X
1234X
/^[abcd]\d/
a45
b93
c99z
d04
*** Failers
e45
abcd
abcd1234
1234
/^[abcd]*\d/
a45
b93
c99z
d04
abcd1234
1234
*** Failers
e45
abcd
/^[abcd]+\d/
a45
b93
c99z
d04
abcd1234
*** Failers
1234
e45
abcd
/^a+X/
aX
aaX
/^[abcd]?\d/
a45
b93
c99z
d04
1234
*** Failers
abcd1234
e45
/^[abcd]{2,3}\d/
ab45
bcd93
*** Failers
1234
a36
abcd1234
ee45
/^(abc)*\d/
abc45
abcabcabc45
42xyz
*** Failers
/^(abc)+\d/
abc45
abcabcabc45
*** Failers
42xyz
/^(abc)?\d/
abc45
42xyz
*** Failers
abcabcabc45
/^(abc){2,3}\d/
abcabc45
abcabcabc45
*** Failers
abcabcabcabc45
abc45
42xyz
/1(abc|xyz)2(?1)3/
1abc2abc3456
1abc2xyz3456
/^(a*\w|ab)=(a*\w|ab)/
ab=ab
/^(a*\w|ab)=(?1)/
ab=ab
/^([^()]|\((?1)*\))*$/
abc
a(b)c
a(b(c))d
*** Failers)
a(b(c)d
/^>abc>([^()]|\((?1)*\))*<xyz<$/
>abc>123<xyz<
>abc>1(2)3<xyz<
>abc>(1(2)3)<xyz<
/^(?>a*)\d/
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa9876
*** Failers
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
/< (?: (?(R) \d++ | [^<>]*+) | (?R)) * >/x
<>
<abcd>
<abc <123> hij>
<abc <def> hij>
<abc<>def>
<abc<>
*** Failers
<abc
/^(?(?=abc)\w{3}:|\d\d)$/
abc:
12
*** Failers
123
xyz
/^(?(?!abc)\d\d|\w{3}:)$/
abc:
12
*** Failers
123
xyz
/^(?=abc)\w{5}:$/
abcde:
*** Failers
abc..
123
vwxyz
/^(?!abc)\d\d$/
12
*** Failers
abcde:
abc..
123
vwxyz
/(?<=abc|xy)123/
abc12345
wxy123z
*** Failers
123abc
/(?<!abc|xy)123/
123abc
mno123456
*** Failers
abc12345
wxy123z
/abc(?C1)xyz/
abcxyz
123abcxyz999
/(ab|cd){3,4}/C
ababab
abcdabcd
abcdcdcdcdcd
/^abc/
abcdef
*** Failers
abcdef\B
/^(a*|xyz)/
bcd
aaabcd
xyz
xyz\N
*** Failers
bcd\N
/xyz$/
xyz
xyz\n
*** Failers
xyz\Z
xyz\n\Z
/xyz$/m
xyz
xyz\n
abcxyz\npqr
abcxyz\npqr\Z
xyz\n\Z
*** Failers
xyz\Z
/\Gabc/
abcdef
defabcxyz\>3
*** Failers
defabcxyz
/^abcdef/
ab\P
abcde\P
abcdef\P
*** Failers
abx\P
/^a{2,4}\d+z/
a\P
aa\P
aa2\P
aaa\P
aaa23\P
aaaa12345\P
aa0z\P
aaaa4444444444444z\P
*** Failers
az\P
aaaaa\P
a56\P
/^abcdef/
abc\P
def\R
/(?<=foo)bar/
xyzfo\P
foob\P\>2
foobar...\R\P\>4
xyzfo\P
foobar\>2
*** Failers
xyzfo\P
obar\R
/(ab*(cd|ef))+X/
adfadadaklhlkalkajhlkjahdfasdfasdfladsfjkj\P\Z
lkjhlkjhlkjhlkjhabbbbbbcdaefabbbbbbbefa\P\B\Z
cdabbbbbbbb\P\R\B\Z
efabbbbbbbbbbbbbbbb\P\R\B\Z
bbbbbbbbbbbbcdXyasdfadf\P\R\B\Z
/(a|b)/SF>testsavedregex
<testsavedregex
abc
** Failers
def
/the quick brown fox/
the quick brown fox
The quick brown FOX
What do you know about the quick brown fox?
What do you know about THE QUICK BROWN FOX?
/The quick brown fox/i
the quick brown fox
The quick brown FOX
What do you know about the quick brown fox?
What do you know about THE QUICK BROWN FOX?
/abcd\t\n\r\f\a\e\071\x3b\$\\\?caxyz/
abcd\t\n\r\f\a\e9;\$\\?caxyz
/a*abc?xyz+pqr{3}ab{2,}xy{4,5}pq{0,6}AB{0,}zz/
abxyzpqrrrabbxyyyypqAzz
abxyzpqrrrabbxyyyypqAzz
aabxyzpqrrrabbxyyyypqAzz
aaabxyzpqrrrabbxyyyypqAzz
aaaabxyzpqrrrabbxyyyypqAzz
abcxyzpqrrrabbxyyyypqAzz
aabcxyzpqrrrabbxyyyypqAzz
aaabcxyzpqrrrabbxyyyypAzz
aaabcxyzpqrrrabbxyyyypqAzz
aaabcxyzpqrrrabbxyyyypqqAzz
aaabcxyzpqrrrabbxyyyypqqqAzz
aaabcxyzpqrrrabbxyyyypqqqqAzz
aaabcxyzpqrrrabbxyyyypqqqqqAzz
aaabcxyzpqrrrabbxyyyypqqqqqqAzz
aaaabcxyzpqrrrabbxyyyypqAzz
abxyzzpqrrrabbxyyyypqAzz
aabxyzzzpqrrrabbxyyyypqAzz
aaabxyzzzzpqrrrabbxyyyypqAzz
aaaabxyzzzzpqrrrabbxyyyypqAzz
abcxyzzpqrrrabbxyyyypqAzz
aabcxyzzzpqrrrabbxyyyypqAzz
aaabcxyzzzzpqrrrabbxyyyypqAzz
aaaabcxyzzzzpqrrrabbxyyyypqAzz
aaaabcxyzzzzpqrrrabbbxyyyypqAzz
aaaabcxyzzzzpqrrrabbbxyyyyypqAzz
aaabcxyzpqrrrabbxyyyypABzz
aaabcxyzpqrrrabbxyyyypABBzz
>>>aaabxyzpqrrrabbxyyyypqAzz
>aaaabxyzpqrrrabbxyyyypqAzz
>>>>abcxyzpqrrrabbxyyyypqAzz
*** Failers
abxyzpqrrabbxyyyypqAzz
abxyzpqrrrrabbxyyyypqAzz
abxyzpqrrrabxyyyypqAzz
aaaabcxyzzzzpqrrrabbbxyyyyyypqAzz
aaaabcxyzzzzpqrrrabbbxyyypqAzz
aaabcxyzpqrrrabbxyyyypqqqqqqqAzz
/^(abc){1,2}zz/
abczz
abcabczz
*** Failers
zz
abcabcabczz
>>abczz
/^(b+?|a){1,2}?c/
bc
bbc
bbbc
bac
bbac
aac
abbbbbbbbbbbc
bbbbbbbbbbbac
*** Failers
aaac
abbbbbbbbbbbac
/^(b+|a){1,2}c/
bc
bbc
bbbc
bac
bbac
aac
abbbbbbbbbbbc
bbbbbbbbbbbac
*** Failers
aaac
abbbbbbbbbbbac
/^(b+|a){1,2}?bc/
bbc
/^(b*|ba){1,2}?bc/
babc
bbabc
bababc
*** Failers
bababbc
babababc
/^(ba|b*){1,2}?bc/
babc
bbabc
bababc
*** Failers
bababbc
babababc
/^\ca\cA\c[\c{\c:/
\x01\x01\e;z
/^[ab\]cde]/
athing
bthing
]thing
cthing
dthing
ething
*** Failers
fthing
[thing
\\thing
/^[]cde]/
]thing
cthing
dthing
ething
*** Failers
athing
fthing
/^[^ab\]cde]/
fthing
[thing
\\thing
*** Failers
athing
bthing
]thing
cthing
dthing
ething
/^[^]cde]/
athing
fthing
*** Failers
]thing
cthing
dthing
ething
/^\Б/
Б
/^€/
€
/^[0-9]+$/
0
1
2
3
4
5
6
7
8
9
10
100
*** Failers
abc
/^.*nter/
enter
inter
uponter
/^xxx[0-9]+$/
xxx0
xxx1234
*** Failers
xxx
/^.+[0-9][0-9][0-9]$/
x123
xx123
123456
*** Failers
123
x1234
/^.+?[0-9][0-9][0-9]$/
x123
xx123
123456
*** Failers
123
x1234
/^([^!]+)!(.+)=apquxz\.ixr\.zzz\.ac\.uk$/
abc!pqr=apquxz.ixr.zzz.ac.uk
*** Failers
!pqr=apquxz.ixr.zzz.ac.uk
abc!=apquxz.ixr.zzz.ac.uk
abc!pqr=apquxz:ixr.zzz.ac.uk
abc!pqr=apquxz.ixr.zzz.ac.ukk
/:/
Well, we need a colon: somewhere
*** Fail if we don't
/([\da-f:]+)$/i
0abc
abc
fed
E
::
5f03:12C0::932e
fed def
Any old stuff
*** Failers
0zzz
gzzz
fed\x20
Any old rubbish
/^.*\.(\d{1,3})\.(\d{1,3})\.(\d{1,3})$/
.1.2.3
A.12.123.0
*** Failers
.1.2.3333
1.2.3
1234.2.3
/^(\d+)\s+IN\s+SOA\s+(\S+)\s+(\S+)\s*\(\s*$/
1 IN SOA non-sp1 non-sp2(
1 IN SOA non-sp1 non-sp2 (
*** Failers
1IN SOA non-sp1 non-sp2(
/^[a-zA-Z\d][a-zA-Z\d\-]*(\.[a-zA-Z\d][a-zA-z\d\-]*)*\.$/
a.
Z.
2.
ab-c.pq-r.
sxk.zzz.ac.uk.
x-.y-.
*** Failers
-abc.peq.
/^\*\.[a-z]([a-z\-\d]*[a-z\d]+)?(\.[a-z]([a-z\-\d]*[a-z\d]+)?)*$/
*.a
*.b0-a
*.c3-b.c
*.c-a.b-c
*** Failers
*.0
*.a-
*.a-b.c-
*.c-a.0-c
/^(?=ab(de))(abd)(e)/
abde
/^(?!(ab)de|x)(abd)(f)/
abdf
/^(?=(ab(cd)))(ab)/
abcd
/^[\da-f](\.[\da-f])*$/i
a.b.c.d
A.B.C.D
a.b.c.1.2.3.C
/^\".*\"\s*(;.*)?$/
\"1234\"
\"abcd\" ;
\"\" ; rhubarb
*** Failers
\"1234\" : things
/^$/
\
*** Failers
/ ^ a (?# begins with a) b\sc (?# then b c) $ (?# then end)/x
ab c
*** Failers
abc
ab cde
/(?x) ^ a (?# begins with a) b\sc (?# then b c) $ (?# then end)/
ab c
*** Failers
abc
ab cde
/^ a\ b[c ]d $/x
a bcd
a b d
*** Failers
abcd
ab d
/^(a(b(c)))(d(e(f)))(h(i(j)))(k(l(m)))$/
abcdefhijklm
/^(?:a(b(c)))(?:d(e(f)))(?:h(i(j)))(?:k(l(m)))$/
abcdefhijklm
/^[\w][\W][\s][\S][\d][\D][\b][\n][\c]][\022]/
a+ Z0+\x08\n\x1d\x12
/^[.^$|()*+?{,}]+/
.^\$(*+)|{?,?}
/^a*\w/
z
az
aaaz
a
aa
aaaa
a+
aa+
/^a*?\w/
z
az
aaaz
a
aa
aaaa
a+
aa+
/^a+\w/
az
aaaz
aa
aaaa
aa+
/^a+?\w/
az
aaaz
aa
aaaa
aa+
/^\d{8}\w{2,}/
1234567890
12345678ab
12345678__
*** Failers
1234567
/^[aeiou\d]{4,5}$/
uoie
1234
12345
aaaaa
*** Failers
123456
/^[aeiou\d]{4,5}?/
uoie
1234
12345
aaaaa
123456
/^From +([^ ]+) +[a-zA-Z][a-zA-Z][a-zA-Z] +[a-zA-Z][a-zA-Z][a-zA-Z] +[0-9]?[0-9] +[0-9][0-9]:[0-9][0-9]/
From abcd Mon Sep 01 12:33:02 1997
/^From\s+\S+\s+([a-zA-Z]{3}\s+){2}\d{1,2}\s+\d\d:\d\d/
From abcd Mon Sep 01 12:33:02 1997
From abcd Mon Sep 1 12:33:02 1997
*** Failers
From abcd Sep 01 12:33:02 1997
/^12.34/s
12\n34
12\r34
/\w+(?=\t)/
the quick brown\t fox
/foo(?!bar)(.*)/
foobar is foolish see?
/(?:(?!foo)...|^.{0,2})bar(.*)/
foobar crowbar etc
barrel
2barrel
A barrel
/^(\D*)(?=\d)(?!123)/
abc456
*** Failers
abc123
/^1234(?# test newlines
inside)/
1234
/^1234 #comment in extended re
/x
1234
/#rhubarb
abcd/x
abcd
/^abcd#rhubarb/x
abcd
/(?!^)abc/
the abc
*** Failers
abc
/(?=^)abc/
abc
*** Failers
the abc
/^[ab]{1,3}(ab*|b)/O
aabbbbb
/^[ab]{1,3}?(ab*|b)/O
aabbbbb
/^[ab]{1,3}?(ab*?|b)/O
aabbbbb
/^[ab]{1,3}(ab*?|b)/O
aabbbbb
/ (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* # optional leading comment
(?: (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
) # initial word
(?: (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
) )* # further okay, if led by a period
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* @ (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # initial subdomain
(?: #
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. # if led by a period...
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # ...further okay
)*
# address
| # or
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
) # one word, optionally followed by....
(?:
[^()<>@,;:".\\\[\]\x80-\xff\000-\010\012-\037] | # atom and space parts, or...
\(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) | # comments, or...
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
# quoted strings
)*
< (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* # leading <
(?: @ (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # initial subdomain
(?: #
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. # if led by a period...
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # ...further okay
)*
(?: (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* , (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* @ (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # initial subdomain
(?: #
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. # if led by a period...
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # ...further okay
)*
)* # further okay, if led by comma
: # closing colon
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* )? # optional route
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
) # initial word
(?: (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
" (?: # opening quote...
[^\\\x80-\xff\n\015"] # Anything except backslash and quote
| # or
\\ [^\x80-\xff] # Escaped something (something != CR)
)* " # closing quote
) )* # further okay, if led by a period
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* @ (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # initial subdomain
(?: #
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* \. # if led by a period...
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* (?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
| \[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
) # ...further okay
)*
# address spec
(?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* > # trailing >
# name and address
) (?: [\040\t] | \(
(?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] | \( (?: [^\\\x80-\xff\n\015()] | \\ [^\x80-\xff] )* \) )*
\) )* # optional trailing comment
/x
Alan Other <user\@dom.ain>
<user\@dom.ain>
user\@dom.ain
\"A. Other\" <user.1234\@dom.ain> (a comment)
A. Other <user.1234\@dom.ain> (a comment)
\"/s=user/ou=host/o=place/prmd=uu.yy/admd= /c=gb/\"\@x400-re.lay
A missing angle <user\@some.where
*** Failers
The quick brown fox
/[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional leading comment
(?:
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
# Atom
| # or
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
# Quoted string
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
# Atom
| # or
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
# Quoted string
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# additional words
)*
@
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
)*
# address
| # or
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
# Atom
| # or
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
# Quoted string
)
# leading word
[^()<>@,;:".\\\[\]\x80-\xff\000-\010\012-\037] * # "normal" atoms and or spaces
(?:
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
|
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
) # "special" comment or quoted string
[^()<>@,;:".\\\[\]\x80-\xff\000-\010\012-\037] * # more "normal"
)*
<
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# <
(?:
@
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
)*
(?: ,
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
@
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
)*
)* # additional domains
:
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
)? # optional route
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
# Atom
| # or
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
# Quoted string
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
# Atom
| # or
" # "
[^\\\x80-\xff\n\015"] * # normal
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015"] * )* # ( special normal* )*
" # "
# Quoted string
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# additional words
)*
@
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
(?:
\.
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
(?:
[^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]+ # some number of atom characters...
(?![^(\040)<>@,;:".\\\[\]\000-\037\x80-\xff]) # ..not followed by something that could be part of an atom
|
\[ # [
(?: [^\\\x80-\xff\n\015\[\]] | \\ [^\x80-\xff] )* # stuff
\] # ]
)
[\040\t]* # Nab whitespace.
(?:
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: # (
(?: \\ [^\x80-\xff] |
\( # (
[^\\\x80-\xff\n\015()] * # normal*
(?: \\ [^\x80-\xff] [^\\\x80-\xff\n\015()] * )* # (special normal*)*
\) # )
) # special
[^\\\x80-\xff\n\015()] * # normal*
)* # )*
\) # )
[\040\t]* )* # If comment found, allow more spaces.
# optional trailing comments
)*
# address spec
> # >
# name and address
)
/x
Alan Other <user\@dom.ain>
<user\@dom.ain>
user\@dom.ain
\"A. Other\" <user.1234\@dom.ain> (a comment)
A. Other <user.1234\@dom.ain> (a comment)
\"/s=user/ou=host/o=place/prmd=uu.yy/admd= /c=gb/\"\@x400-re.lay
A missing angle <user\@some.where
*** Failers
The quick brown fox
/abc\0def\00pqr\000xyz\0000AB/
abc\0def\00pqr\000xyz\0000AB
abc456 abc\0def\00pqr\000xyz\0000ABCDE
/abc\x0def\x00pqr\x000xyz\x0000AB/
abc\x0def\x00pqr\x000xyz\x0000AB
abc456 abc\x0def\x00pqr\x000xyz\x0000ABCDE
/^[\000-\037]/
\0A
\01B
\037C
/\0*/
\0\0\0\0
/A\x0{2,3}Z/
The A\x0\x0Z
An A\0\x0\0Z
*** Failers
A\0Z
A\0\x0\0\x0Z
/^\s/
\040abc
\x0cabc
\nabc
\rabc
\tabc
*** Failers
abc
/^a b
c/x
abc
/ab{1,3}bc/
abbbbc
abbbc
abbc
*** Failers
abc
abbbbbc
/([^.]*)\.([^:]*):[T ]+(.*)/
track1.title:TBlah blah blah
/([^.]*)\.([^:]*):[T ]+(.*)/i
track1.title:TBlah blah blah
/([^.]*)\.([^:]*):[t ]+(.*)/i
track1.title:TBlah blah blah
/^[W-c]+$/
WXY_^abc
*** Failers
wxy
/^[W-c]+$/i
WXY_^abc
wxy_^ABC
/^[\x3f-\x5F]+$/i
WXY_^abc
wxy_^ABC
/^abc$/m
abc
qqq\nabc
abc\nzzz
qqq\nabc\nzzz
/^abc$/
abc
*** Failers
qqq\nabc
abc\nzzz
qqq\nabc\nzzz
/\Aabc\Z/m
abc
abc\n
*** Failers
qqq\nabc
abc\nzzz
qqq\nabc\nzzz
/\A(.)*\Z/s
abc\ndef
/\A(.)*\Z/m
*** Failers
abc\ndef
/(?:b)|(?::+)/
b::c
c::b
/[-az]+/
az-
*** Failers
b
/[az-]+/
za-
*** Failers
b
/[a\-z]+/
a-z
*** Failers
b
/[a-z]+/
abcdxyz
/[\d-]+/
12-34
*** Failers
aaa
/[\d-z]+/
12-34z
*** Failers
aaa
/\x5c/
\\
/\x20Z/
the Zoo
*** Failers
Zulu
/ab{3cd/
ab{3cd
/ab{3,cd/
ab{3,cd
/ab{3,4a}cd/
ab{3,4a}cd
/{4,5a}bc/
{4,5a}bc
/^a.b/<lf>
a\rb
*** Failers
a\nb
/abc$/
abc
abc\n
*** Failers
abc\ndef
/(abc)\123/
abc\x53
/(abc)\223/
abc\x93
/(abc)\323/
abc\xd3
/(abc)\100/
abc\x40
abc\100
/(abc)\1000/
abc\x400
abc\x40\x30
abc\1000
abc\100\x30
abc\100\060
abc\100\60
/^A\8B\9C$/
A8B9C
*** Failers
A\08B\09C
/^[A\8B\9C]+$/
A8B9C
*** Failers
A8B9C\x00
/(a)(b)(c)(d)(e)(f)(g)(h)(i)(j)(k)\12\123/
abcdefghijk\12S
/ab\idef/
abidef
/a{0}bc/
bc
/(a|(bc)){0,0}?xyz/
xyz
/abc[\10]de/
abc\010de
/abc[\1]de/
abc\1de
/(abc)[\1]de/
abc\1de
/(?s)a.b/
a\nb
/^([^a])([^\b])([^c]*)([^d]{3,4})/
baNOTccccd
baNOTcccd
baNOTccd
bacccd
*** Failers
anything
b\bc
baccd
/[^a]/
Abc
/[^a]/i
Abc
/[^a]+/
AAAaAbc
/[^a]+/i
AAAaAbc
/[^a]+/
bbb\nccc
/[^k]$/
abc
*** Failers
abk
/[^k]{2,3}$/
abc
kbc
kabc
*** Failers
abk
akb
akk
/^\d{8,}\@.+[^k]$/
12345678\@a.b.c.d
123456789\@x.y.z
*** Failers
12345678\@x.y.uk
1234567\@a.b.c.d
/[^a]/
aaaabcd
aaAabcd
/[^a]/i
aaaabcd
aaAabcd
/[^az]/
aaaabcd
aaAabcd
/[^az]/i
aaaabcd
aaAabcd
/\000\001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037\040\041\042\043\044\045\046\047\050\051\052\053\054\055\056\057\060\061\062\063\064\065\066\067\070\071\072\073\074\075\076\077\100\101\102\103\104\105\106\107\110\111\112\113\114\115\116\117\120\121\122\123\124\125\126\127\130\131\132\133\134\135\136\137\140\141\142\143\144\145\146\147\150\151\152\153\154\155\156\157\160\161\162\163\164\165\166\167\170\171\172\173\174\175\176\177\200\201\202\203\204\205\206\207\210\211\212\213\214\215\216\217\220\221\222\223\224\225\226\227\230\231\232\233\234\235\236\237\240\241\242\243\244\245\246\247\250\251\252\253\254\255\256\257\260\261\262\263\264\265\266\267\270\271\272\273\274\275\276\277\300\301\302\303\304\305\306\307\310\311\312\313\314\315\316\317\320\321\322\323\324\325\326\327\330\331\332\333\334\335\336\337\340\341\342\343\344\345\346\347\350\351\352\353\354\355\356\357\360\361\362\363\364\365\366\367\370\371\372\373\374\375\376\377/
\000\001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037\040\041\042\043\044\045\046\047\050\051\052\053\054\055\056\057\060\061\062\063\064\065\066\067\070\071\072\073\074\075\076\077\100\101\102\103\104\105\106\107\110\111\112\113\114\115\116\117\120\121\122\123\124\125\126\127\130\131\132\133\134\135\136\137\140\141\142\143\144\145\146\147\150\151\152\153\154\155\156\157\160\161\162\163\164\165\166\167\170\171\172\173\174\175\176\177\200\201\202\203\204\205\206\207\210\211\212\213\214\215\216\217\220\221\222\223\224\225\226\227\230\231\232\233\234\235\236\237\240\241\242\243\244\245\246\247\250\251\252\253\254\255\256\257\260\261\262\263\264\265\266\267\270\271\272\273\274\275\276\277\300\301\302\303\304\305\306\307\310\311\312\313\314\315\316\317\320\321\322\323\324\325\326\327\330\331\332\333\334\335\336\337\340\341\342\343\344\345\346\347\350\351\352\353\354\355\356\357\360\361\362\363\364\365\366\367\370\371\372\373\374\375\376\377
/P[^*]TAIRE[^*]{1,6}?LL/
xxxxxxxxxxxPSTAIREISLLxxxxxxxxx
/P[^*]TAIRE[^*]{1,}?LL/
xxxxxxxxxxxPSTAIREISLLxxxxxxxxx
/(\.\d\d[1-9]?)\d+/
1.230003938
1.875000282
1.235
/(\.\d\d((?=0)|\d(?=\d)))/
1.230003938
1.875000282
*** Failers
1.235
/a(?)b/
ab
/\b(foo)\s+(\w+)/i
Food is on the foo table
/foo(.*)bar/
The food is under the bar in the barn.
/foo(.*?)bar/
The food is under the bar in the barn.
/(.*)(\d*)/O
I have 2 numbers: 53147
/(.*)(\d+)/
I have 2 numbers: 53147
/(.*?)(\d*)/O
I have 2 numbers: 53147
/(.*?)(\d+)/
I have 2 numbers: 53147
/(.*)(\d+)$/
I have 2 numbers: 53147
/(.*?)(\d+)$/
I have 2 numbers: 53147
/(.*)\b(\d+)$/
I have 2 numbers: 53147
/(.*\D)(\d+)$/
I have 2 numbers: 53147
/^\D*(?!123)/
ABC123
/^(\D*)(?=\d)(?!123)/
ABC445
*** Failers
ABC123
/^[W-]46]/
W46]789
-46]789
*** Failers
Wall
Zebra
42
[abcd]
]abcd[
/^[W-\]46]/
W46]789
Wall
Zebra
Xylophone
42
[abcd]
]abcd[
\\backslash
*** Failers
-46]789
well
/\d\d\/\d\d\/\d\d\d\d/
01/01/2000
/word (?:[a-zA-Z0-9]+ ){0,10}otherword/
word cat dog elephant mussel cow horse canary baboon snake shark otherword
word cat dog elephant mussel cow horse canary baboon snake shark
/word (?:[a-zA-Z0-9]+ ){0,300}otherword/
word cat dog elephant mussel cow horse canary baboon snake shark the quick brown fox and the lazy dog and several other words getting close to thirty by now I hope
/^(a){0,0}/
bcd
abc
aab
/^(a){0,1}/
bcd
abc
aab
/^(a){0,2}/
bcd
abc
aab
/^(a){0,3}/
bcd
abc
aab
aaa
/^(a){0,}/
bcd
abc
aab
aaa
aaaaaaaa
/^(a){1,1}/
bcd
abc
aab
/^(a){1,2}/
bcd
abc
aab
/^(a){1,3}/
bcd
abc
aab
aaa
/^(a){1,}/
bcd
abc
aab
aaa
aaaaaaaa
/.*\.gif/
borfle\nbib.gif\nno
/.{0,}\.gif/
borfle\nbib.gif\nno
/.*\.gif/m
borfle\nbib.gif\nno
/.*\.gif/s
borfle\nbib.gif\nno
/.*\.gif/ms
borfle\nbib.gif\nno
/.*$/
borfle\nbib.gif\nno
/.*$/m
borfle\nbib.gif\nno
/.*$/s
borfle\nbib.gif\nno
/.*$/ms
borfle\nbib.gif\nno
/.*$/
borfle\nbib.gif\nno\n
/.*$/m
borfle\nbib.gif\nno\n
/.*$/s
borfle\nbib.gif\nno\n
/.*$/ms
borfle\nbib.gif\nno\n
/(.*X|^B)/
abcde\n1234Xyz
BarFoo
*** Failers
abcde\nBar
/(.*X|^B)/m
abcde\n1234Xyz
BarFoo
abcde\nBar
/(.*X|^B)/s
abcde\n1234Xyz
BarFoo
*** Failers
abcde\nBar
/(.*X|^B)/ms
abcde\n1234Xyz
BarFoo
abcde\nBar
/(?s)(.*X|^B)/
abcde\n1234Xyz
BarFoo
*** Failers
abcde\nBar
/(?s:.*X|^B)/
abcde\n1234Xyz
BarFoo
*** Failers
abcde\nBar
/^.*B/
**** Failers
abc\nB
/(?s)^.*B/
abc\nB
/(?m)^.*B/
abc\nB
/(?ms)^.*B/
abc\nB
/(?ms)^B/
abc\nB
/(?s)B$/
B\n
/^[0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9][0-9]/
123456654321
/^\d\d\d\d\d\d\d\d\d\d\d\d/
123456654321
/^[\d][\d][\d][\d][\d][\d][\d][\d][\d][\d][\d][\d]/
123456654321
/^[abc]{12}/
abcabcabcabc
/^[a-c]{12}/
abcabcabcabc
/^(a|b|c){12}/
abcabcabcabc
/^[abcdefghijklmnopqrstuvwxy0123456789]/
n
*** Failers
z
/abcde{0,0}/
abcd
*** Failers
abce
/ab[cd]{0,0}e/
abe
*** Failers
abcde
/ab(c){0,0}d/
abd
*** Failers
abcd
/a(b*)/
a
ab
abbbb
*** Failers
bbbbb
/ab\d{0}e/
abe
*** Failers
ab1e
/"([^\\"]+|\\.)*"/
the \"quick\" brown fox
\"the \\\"quick\\\" brown fox\"
/.*?/g+
abc
/\b/g+
abc
/\b/+g
abc
//g
abc
/<tr([\w\W\s\d][^<>]{0,})><TD([\w\W\s\d][^<>]{0,})>([\d]{0,}\.)(.*)((<BR>([\w\W\s\d][^<>]{0,})|[\s]{0,}))<\/a><\/TD><TD([\w\W\s\d][^<>]{0,})>([\w\W\s\d][^<>]{0,})<\/TD><TD([\w\W\s\d][^<>]{0,})>([\w\W\s\d][^<>]{0,})<\/TD><\/TR>/is
<TR BGCOLOR='#DBE9E9'><TD align=left valign=top>43.<a href='joblist.cfm?JobID=94 6735&Keyword='>Word Processor<BR>(N-1286)</a></TD><TD align=left valign=top>Lega lstaff.com</TD><TD align=left valign=top>CA - Statewide</TD></TR>
/a[^a]b/
acb
a\nb
/a.b/
acb
*** Failers
a\nb
/a[^a]b/s
acb
a\nb
/a.b/s
acb
a\nb
/^(b+?|a){1,2}?c/
bac
bbac
bbbac
bbbbac
bbbbbac
/^(b+|a){1,2}?c/
bac
bbac
bbbac
bbbbac
bbbbbac
/(?!\A)x/m
x\nb\n
a\bx\n
/\x0{ab}/
\0{ab}
/(A|B)*?CD/
CD
/(A|B)*CD/
CD
/(?<!bar)foo/
foo
catfood
arfootle
rfoosh
*** Failers
barfoo
towbarfoo
/\w{3}(?<!bar)foo/
catfood
*** Failers
foo
barfoo
towbarfoo
/(?<=(foo)a)bar/
fooabar
*** Failers
bar
foobbar
/\Aabc\z/m
abc
*** Failers
abc\n
qqq\nabc
abc\nzzz
qqq\nabc\nzzz
"(?>.*/)foo"
/this/is/a/very/long/line/in/deed/with/very/many/slashes/in/it/you/see/
"(?>.*/)foo"
/this/is/a/very/long/line/in/deed/with/very/many/slashes/in/and/foo
/(?>(\.\d\d[1-9]?))\d+/
1.230003938
1.875000282
*** Failers
1.235
/^((?>\w+)|(?>\s+))*$/
now is the time for all good men to come to the aid of the party
*** Failers
this is not a line with only words and spaces!
/(\d+)(\w)/
12345a
12345+
/((?>\d+))(\w)/
12345a
*** Failers
12345+
/(?>a+)b/
aaab
/((?>a+)b)/
aaab
/(?>(a+))b/
aaab
/(?>b)+/
aaabbbccc
/(?>a+|b+|c+)*c/
aaabbbbccccd
/(a+|b+|c+)*c/
aaabbbbccccd
/((?>[^()]+)|\([^()]*\))+/
((abc(ade)ufh()()x
/\(((?>[^()]+)|\([^()]+\))+\)/
(abc)
(abc(def)xyz)
*** Failers
((()aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
/a(?-i)b/i
ab
Ab
*** Failers
aB
AB
/(a (?x)b c)d e/
a bcd e
*** Failers
a b cd e
abcd e
a bcde
/(a b(?x)c d (?-x)e f)/
a bcde f
*** Failers
abcdef
/(a(?i)b)c/
abc
aBc
*** Failers
abC
aBC
Abc
ABc
ABC
AbC
/a(?i:b)c/
abc
aBc
*** Failers
ABC
abC
aBC
/a(?i:b)*c/
aBc
aBBc
*** Failers
aBC
aBBC
/a(?=b(?i)c)\w\wd/
abcd
abCd
*** Failers
aBCd
abcD
/(?s-i:more.*than).*million/i
more than million
more than MILLION
more \n than Million
*** Failers
MORE THAN MILLION
more \n than \n million
/(?:(?s-i)more.*than).*million/i
more than million
more than MILLION
more \n than Million
*** Failers
MORE THAN MILLION
more \n than \n million
/(?>a(?i)b+)+c/
abc
aBbc
aBBc
*** Failers
Abc
abAb
abbC
/(?=a(?i)b)\w\wc/
abc
aBc
*** Failers
Ab
abC
aBC
/(?<=a(?i)b)(\w\w)c/
abxxc
aBxxc
*** Failers
Abxxc
ABxxc
abxxC
/^(?(?=abc)\w{3}:|\d\d)$/
abc:
12
*** Failers
123
xyz
/^(?(?!abc)\d\d|\w{3}:)$/
abc:
12
*** Failers
123
xyz
/(?(?<=foo)bar|cat)/
foobar
cat
fcat
focat
*** Failers
foocat
/(?(?<!foo)cat|bar)/
foobar
cat
fcat
focat
*** Failers
foocat
/(?>a*)*/
a
aa
aaaa
/(abc|)+/
abc
abcabc
abcabcabc
xyz
/([a]*)*/
a
aaaaa
/([ab]*)*/
a
b
ababab
aaaabcde
bbbb
/([^a]*)*/
b
bbbb
aaa
/([^ab]*)*/
cccc
abab
/([a]*?)*/
a
aaaa
/([ab]*?)*/
a
b
abab
baba
/([^a]*?)*/
b
bbbb
aaa
/([^ab]*?)*/
c
cccc
baba
/(?>a*)*/
a
aaabcde
/((?>a*))*/
aaaaa
aabbaa
/((?>a*?))*/
aaaaa
aabbaa
/(?(?=[^a-z]+[a-z]) \d{2}-[a-z]{3}-\d{2} | \d{2}-\d{2}-\d{2} ) /x
12-sep-98
12-09-98
*** Failers
sep-12-98
/(?i:saturday|sunday)/
saturday
sunday
Saturday
Sunday
SATURDAY
SUNDAY
SunDay
/(a(?i)bc|BB)x/
abcx
aBCx
bbx
BBx
*** Failers
abcX
aBCX
bbX
BBX
/^([ab](?i)[cd]|[ef])/
ac
aC
bD
elephant
Europe
frog
France
*** Failers
Africa
/^(ab|a(?i)[b-c](?m-i)d|x(?i)y|z)/
ab
aBd
xy
xY
zebra
Zambesi
*** Failers
aCD
XY
/(?<=foo\n)^bar/m
foo\nbar
*** Failers
bar
baz\nbar
/(?<=(?<!foo)bar)baz/
barbaz
barbarbaz
koobarbaz
*** Failers
baz
foobarbaz
/The following tests are taken from the Perl 5.005 test suite; some of them/
/are compatible with 5.004, but I'd rather not have to sort them out./
/abc/
abc
xabcy
ababc
*** Failers
xbc
axc
abx
/ab*c/
abc
/ab*bc/
abc
abbc
abbbbc
/.{1}/
abbbbc
/.{3,4}/
abbbbc
/ab{0,}bc/
abbbbc
/ab+bc/
abbc
*** Failers
abc
abq
/ab+bc/
abbbbc
/ab{1,}bc/
abbbbc
/ab{1,3}bc/
abbbbc
/ab{3,4}bc/
abbbbc
/ab{4,5}bc/
*** Failers
abq
abbbbc
/ab?bc/
abbc
abc
/ab{0,1}bc/
abc
/ab?bc/
/ab?c/
abc
/ab{0,1}c/
abc
/^abc$/
abc
*** Failers
abbbbc
abcc
/^abc/
abcc
/^abc$/
/abc$/
aabc
*** Failers
aabc
aabcd
/^/
abc
/$/
abc
/a.c/
abc
axc
/a.*c/
axyzc
/a[bc]d/
abd
*** Failers
axyzd
abc
/a[b-d]e/
ace
/a[b-d]/
aac
/a[-b]/
a-
/a[b-]/
a-
/a]/
a]
/a[]]b/
a]b
/a[^bc]d/
aed
*** Failers
abd
abd
/a[^-b]c/
adc
/a[^]b]c/
adc
*** Failers
a-c
a]c
/\ba\b/
a-
-a
-a-
/\by\b/
*** Failers
xy
yz
xyz
/\Ba\B/
*** Failers
a-
-a
-a-
/\By\b/
xy
/\by\B/
yz
/\By\B/
xyz
/\w/
a
/\W/
-
*** Failers
-
a
/a\sb/
a b
/a\Sb/
a-b
*** Failers
a-b
a b
/\d/
1
/\D/
-
*** Failers
-
1
/[\w]/
a
/[\W]/
-
*** Failers
-
a
/a[\s]b/
a b
/a[\S]b/
a-b
*** Failers
a-b
a b
/[\d]/
1
/[\D]/
-
*** Failers
-
1
/ab|cd/
abc
abcd
/()ef/
def
/$b/
/a\(b/
a(b
/a\(*b/
ab
a((b
/a\\b/
a\b
/((a))/
abc
/(a)b(c)/
abc
/a+b+c/
aabbabc
/a{1,}b{1,}c/
aabbabc
/a.+?c/
abcabc
/(a+|b)*/
ab
/(a+|b){0,}/
ab
/(a+|b)+/
ab
/(a+|b){1,}/
ab
/(a+|b)?/
ab
/(a+|b){0,1}/
ab
/[^ab]*/
cde
/abc/
*** Failers
b
/a*/
/([abc])*d/
abbbcd
/([abc])*bcd/
abcd
/a|b|c|d|e/
e
/(a|b|c|d|e)f/
ef
/abcd*efg/
abcdefg
/ab*/
xabyabbbz
xayabbbz
/(ab|cd)e/
abcde
/[abhgefdc]ij/
hij
/^(ab|cd)e/
/(abc|)ef/
abcdef
/(a|b)c*d/
abcd
/(ab|ab*)bc/
abc
/a([bc]*)c*/
abc
/a([bc]*)(c*d)/
abcd
/a([bc]+)(c*d)/
abcd
/a([bc]*)(c+d)/
abcd
/a[bcd]*dcdcde/
adcdcde
/a[bcd]+dcdcde/
*** Failers
abcde
adcdcde
/(ab|a)b*c/
abc
/((a)(b)c)(d)/
abcd
/[a-zA-Z_][a-zA-Z0-9_]*/
alpha
/^a(bc+|b[eh])g|.h$/
abh
/(bc+d$|ef*g.|h?i(j|k))/
effgz
ij
reffgz
*** Failers
effg
bcdd
/((((((((((a))))))))))/
a
/(((((((((a)))))))))/
a
/multiple words of text/
*** Failers
aa
uh-uh
/multiple words/
multiple words, yeah
/(.*)c(.*)/
abcde
/\((.*), (.*)\)/
(a, b)
/[k]/
/abcd/
abcd
/a(bc)d/
abcd
/a[-]?c/
ac
/abc/i
ABC
XABCY
ABABC
*** Failers
aaxabxbaxbbx
XBC
AXC
ABX
/ab*c/i
ABC
/ab*bc/i
ABC
ABBC
/ab*?bc/i
ABBBBC
/ab{0,}?bc/i
ABBBBC
/ab+?bc/i
ABBC
/ab+bc/i
*** Failers
ABC
ABQ
/ab{1,}bc/i
/ab+bc/i
ABBBBC
/ab{1,}?bc/i
ABBBBC
/ab{1,3}?bc/i
ABBBBC
/ab{3,4}?bc/i
ABBBBC
/ab{4,5}?bc/i
*** Failers
ABQ
ABBBBC
/ab??bc/i
ABBC
ABC
/ab{0,1}?bc/i
ABC
/ab??bc/i
/ab??c/i
ABC
/ab{0,1}?c/i
ABC
/^abc$/i
ABC
*** Failers
ABBBBC
ABCC
/^abc/i
ABCC
/^abc$/i
/abc$/i
AABC
/^/i
ABC
/$/i
ABC
/a.c/i
ABC
AXC
/a.*?c/i
AXYZC
/a.*c/i
*** Failers
AABC
AXYZD
/a[bc]d/i
ABD
/a[b-d]e/i
ACE
*** Failers
ABC
ABD
/a[b-d]/i
AAC
/a[-b]/i
A-
/a[b-]/i
A-
/a]/i
A]
/a[]]b/i
A]B
/a[^bc]d/i
AED
/a[^-b]c/i
ADC
*** Failers
ABD
A-C
/a[^]b]c/i
ADC
/ab|cd/i
ABC
ABCD
/()ef/i
DEF
/$b/i
*** Failers
A]C
B
/a\(b/i
A(B
/a\(*b/i
AB
A((B
/a\\b/i
A\B
/((a))/i
ABC
/(a)b(c)/i
ABC
/a+b+c/i
AABBABC
/a{1,}b{1,}c/i
AABBABC
/a.+?c/i
ABCABC
/a.*?c/i
ABCABC
/a.{0,5}?c/i
ABCABC
/(a+|b)*/i
AB
/(a+|b){0,}/i
AB
/(a+|b)+/i
AB
/(a+|b){1,}/i
AB
/(a+|b)?/i
AB
/(a+|b){0,1}/i
AB
/(a+|b){0,1}?/i
AB
/[^ab]*/i
CDE
/abc/i
/a*/i
/([abc])*d/i
ABBBCD
/([abc])*bcd/i
ABCD
/a|b|c|d|e/i
E
/(a|b|c|d|e)f/i
EF
/abcd*efg/i
ABCDEFG
/ab*/i
XABYABBBZ
XAYABBBZ
/(ab|cd)e/i
ABCDE
/[abhgefdc]ij/i
HIJ
/^(ab|cd)e/i
ABCDE
/(abc|)ef/i
ABCDEF
/(a|b)c*d/i
ABCD
/(ab|ab*)bc/i
ABC
/a([bc]*)c*/i
ABC
/a([bc]*)(c*d)/i
ABCD
/a([bc]+)(c*d)/i
ABCD
/a([bc]*)(c+d)/i
ABCD
/a[bcd]*dcdcde/i
ADCDCDE
/a[bcd]+dcdcde/i
/(ab|a)b*c/i
ABC
/((a)(b)c)(d)/i
ABCD
/[a-zA-Z_][a-zA-Z0-9_]*/i
ALPHA
/^a(bc+|b[eh])g|.h$/i
ABH
/(bc+d$|ef*g.|h?i(j|k))/i
EFFGZ
IJ
REFFGZ
*** Failers
ADCDCDE
EFFG
BCDD
/((((((((((a))))))))))/i
A
/(((((((((a)))))))))/i
A
/(?:(?:(?:(?:(?:(?:(?:(?:(?:(a))))))))))/i
A
/(?:(?:(?:(?:(?:(?:(?:(?:(?:(a|b|c))))))))))/i
C
/multiple words of text/i
*** Failers
AA
UH-UH
/multiple words/i
MULTIPLE WORDS, YEAH
/(.*)c(.*)/i
ABCDE
/\((.*), (.*)\)/i
(A, B)
/[k]/i
/abcd/i
ABCD
/a(bc)d/i
ABCD
/a[-]?c/i
AC
/a(?!b)./
abad
/a(?=d)./
abad
/a(?=c|d)./
abad
/a(?:b|c|d)(.)/
ace
/a(?:b|c|d)*(.)/
ace
/a(?:b|c|d)+?(.)/
ace
acdbcdbe
/a(?:b|c|d)+(.)/
acdbcdbe
/a(?:b|c|d){2}(.)/
acdbcdbe
/a(?:b|c|d){4,5}(.)/
acdbcdbe
/a(?:b|c|d){4,5}?(.)/
acdbcdbe
/((foo)|(bar))*/
foobar
/a(?:b|c|d){6,7}(.)/
acdbcdbe
/a(?:b|c|d){6,7}?(.)/
acdbcdbe
/a(?:b|c|d){5,6}(.)/
acdbcdbe
/a(?:b|c|d){5,6}?(.)/
acdbcdbe
/a(?:b|c|d){5,7}(.)/
acdbcdbe
/a(?:b|c|d){5,7}?(.)/
acdbcdbe
/a(?:b|(c|e){1,2}?|d)+?(.)/
ace
/^(.+)?B/
AB
/^([^a-z])|(\^)$/
.
/^[<>]&/
<&OUT
/(?:(f)(o)(o)|(b)(a)(r))*/
foobar
/(?<=a)b/
ab
*** Failers
cb
b
/(?<!c)b/
ab
b
b
/(?:..)*a/
aba
/(?:..)*?a/
aba
/^(){3,5}/
abc
/^(a+)*ax/
aax
/^((a|b)+)*ax/
aax
/^((a|bc)+)*ax/
aax
/(a|x)*ab/
cab
/(a)*ab/
cab
/(?:(?i)a)b/
ab
/((?i)a)b/
ab
/(?:(?i)a)b/
Ab
/((?i)a)b/
Ab
/(?:(?i)a)b/
*** Failers
cb
aB
/((?i)a)b/
/(?i:a)b/
ab
/((?i:a))b/
ab
/(?i:a)b/
Ab
/((?i:a))b/
Ab
/(?i:a)b/
*** Failers
aB
aB
/((?i:a))b/
/(?:(?-i)a)b/i
ab
/((?-i)a)b/i
ab
/(?:(?-i)a)b/i
aB
/((?-i)a)b/i
aB
/(?:(?-i)a)b/i
*** Failers
aB
Ab
/((?-i)a)b/i
/(?:(?-i)a)b/i
aB
/((?-i)a)b/i
aB
/(?:(?-i)a)b/i
*** Failers
Ab
AB
/((?-i)a)b/i
/(?-i:a)b/i
ab
/((?-i:a))b/i
ab
/(?-i:a)b/i
aB
/((?-i:a))b/i
aB
/(?-i:a)b/i
*** Failers
AB
Ab
/((?-i:a))b/i
/(?-i:a)b/i
aB
/((?-i:a))b/i
aB
/(?-i:a)b/i
*** Failers
Ab
AB
/((?-i:a))b/i
/((?-i:a.))b/i
*** Failers
AB
a\nB
/((?s-i:a.))b/i
a\nB
/(?:c|d)(?:)(?:a(?:)(?:b)(?:b(?:))(?:b(?:)(?:b)))/
cabbbb
/(?:c|d)(?:)(?:aaaaaaaa(?:)(?:bbbbbbbb)(?:bbbbbbbb(?:))(?:bbbbbbbb(?:)(?:bbbbbbbb)))/
caaaaaaaabbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb
/foo\w*\d{4}baz/
foobar1234baz
/x(~~)*(?:(?:F)?)?/
x~~
/^a(?#xxx){3}c/
aaac
/^a (?#xxx) (?#yyy) {3}c/x
aaac
/(?<![cd])b/
*** Failers
B\nB
dbcb
/(?<![cd])[ab]/
dbaacb
/(?<!(c|d))b/
/(?<!(c|d))[ab]/
dbaacb
/(?<!cd)[ab]/
cdaccb
/^(?:a?b?)*$/
*** Failers
dbcb
a--
/((?s)^a(.))((?m)^b$)/
a\nb\nc\n
/((?m)^b$)/
a\nb\nc\n
/(?m)^b/
a\nb\n
/(?m)^(b)/
a\nb\n
/((?m)^b)/
a\nb\n
/\n((?m)^b)/
a\nb\n
/((?s).)c(?!.)/
a\nb\nc\n
a\nb\nc\n
/((?s)b.)c(?!.)/
a\nb\nc\n
a\nb\nc\n
/^b/
/()^b/
*** Failers
a\nb\nc\n
a\nb\nc\n
/((?m)^b)/
a\nb\nc\n
/(?(?!a)a|b)/
/(?(?!a)b|a)/
a
/(?(?=a)b|a)/
*** Failers
a
a
/(?(?=a)a|b)/
a
/(\w+:)+/
one:
/$(?<=^(a))/
a
/([\w:]+::)?(\w+)$/
abcd
xy:z:::abcd
/^[^bcd]*(c+)/
aexycd
/(a*)b+/
caab
/([\w:]+::)?(\w+)$/
abcd
xy:z:::abcd
*** Failers
abcd:
abcd:
/^[^bcd]*(c+)/
aexycd
/(>a+)ab/
/(?>a+)b/
aaab
/([[:]+)/
a:[b]:
/([[=]+)/
a=[b]=
/([[.]+)/
a.[b].
/((?>a+)b)/
aaab
/(?>(a+))b/
aaab
/((?>[^()]+)|\([^()]*\))+/
((abc(ade)ufh()()x
/a\Z/
*** Failers
aaab
a\nb\n
/b\Z/
a\nb\n
/b\z/
/b\Z/
a\nb
/b\z/
a\nb
*** Failers
/(?>.*)(?<=(abcd|wxyz))/
alphabetabcd
endingwxyz
*** Failers
a rather long string that doesn't end with one of them
/word (?>(?:(?!otherword)[a-zA-Z0-9]+ ){0,30})otherword/
word cat dog elephant mussel cow horse canary baboon snake shark otherword
word cat dog elephant mussel cow horse canary baboon snake shark
/word (?>[a-zA-Z0-9]+ ){0,30}otherword/
word cat dog elephant mussel cow horse canary baboon snake shark the quick brown fox and the lazy dog and several other words getting close to thirty by now I hope
/(?<=\d{3}(?!999))foo/
999foo
123999foo
*** Failers
123abcfoo
/(?<=(?!...999)\d{3})foo/
999foo
123999foo
*** Failers
123abcfoo
/(?<=\d{3}(?!999)...)foo/
123abcfoo
123456foo
*** Failers
123999foo
/(?<=\d{3}...)(?<!999)foo/
123abcfoo
123456foo
*** Failers
123999foo
/((Z)+|A)*/
ZABCDEFG
/(Z()|A)*/
ZABCDEFG
/(Z(())|A)*/
ZABCDEFG
/((?>Z)+|A)*/
ZABCDEFG
/((?>)+|A)*/
ZABCDEFG
/a*/g
abbab
/^[\d-a]/
abcde
-things
0digit
*** Failers
bcdef
/[[:space:]]+/
> \x09\x0a\x0c\x0d\x0b<
/[[:blank:]]+/
> \x09\x0a\x0c\x0d\x0b<
/[\s]+/
> \x09\x0a\x0c\x0d\x0b<
/\s+/
> \x09\x0a\x0c\x0d\x0b<
/a b/x
ab
/(?!\A)x/m
a\nxb\n
/(?!^)x/m
a\nxb\n
/abc\Qabc\Eabc/
abcabcabc
/abc\Q(*+|\Eabc/
abc(*+|abc
/ abc\Q abc\Eabc/x
abc abcabc
*** Failers
abcabcabc
/abc#comment
\Q#not comment
literal\E/x
abc#not comment\n literal
/abc#comment
\Q#not comment
literal/x
abc#not comment\n literal
/abc#comment
\Q#not comment
literal\E #more comment
/x
abc#not comment\n literal
/abc#comment
\Q#not comment
literal\E #more comment/x
abc#not comment\n literal
/\Qabc\$xyz\E/
abc\\\$xyz
/\Qabc\E\$\Qxyz\E/
abc\$xyz
/\Gabc/
abc
*** Failers
xyzabc
/\Gabc./g
abc1abc2xyzabc3
/abc./g
abc1abc2xyzabc3
/a(?x: b c )d/
XabcdY
*** Failers
Xa b c d Y
/((?x)x y z | a b c)/
XabcY
AxyzB
/(?i)AB(?-i)C/
XabCY
*** Failers
XabcY
/((?i)AB(?-i)C|D)E/
abCE
DE
*** Failers
abcE
abCe
dE
De
/[z\Qa-d]\E]/
z
a
-
d
]
*** Failers
b
/[\z\C]/
z
C
/\M/
M
/(a+)*b/
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
/(?i)reg(?:ul(?:[aд]|ae)r|ex)/
REGular
regulaer
Regex
regulдr
/≈жед[а-€ј-я]+/
≈жеда
≈жед€
≈жедј
≈жедя
/(?<=Z)X./
\x84XAZXB
/^(?(2)a|(1)(2))+$/
123a
/(?<=a|bbbb)c/
ac
bbbbc
/abc/SS>testsavedregex
<testsavedregex
abc
*** Failers
bca
/abc/FSS>testsavedregex
<testsavedregex
abc
*** Failers
bca
/(a|b)/S>testsavedregex
<testsavedregex
abc
*** Failers
def
/(a|b)/SF>testsavedregex
<testsavedregex
abc
*** Failers
def
/line\nbreak/
this is a line\nbreak
line one\nthis is a line\nbreak in the second line
/line\nbreak/f
this is a line\nbreak
** Failers
line one\nthis is a line\nbreak in the second line
/line\nbreak/mf
this is a line\nbreak
** Failers
line one\nthis is a line\nbreak in the second line
/1234/
123\P
a4\P\R
/1234/
123\P
4\P\R
/^/mg
a\nb\nc\n
\
/(?<=C\n)^/mg
A\nC\nC\n
/(?s)A?B/
AB
aB
/(?s)A*B/
AB
aB
/(?m)A?B/
AB
aB
/(?m)A*B/
AB
aB
/Content-Type\x3A[^\r\n]{6,}/
Content-Type:xxxxxyyy
/Content-Type\x3A[^\r\n]{6,}z/
Content-Type:xxxxxyyyz
/Content-Type\x3A[^a]{6,}/
Content-Type:xxxyyy
/Content-Type\x3A[^a]{6,}z/
Content-Type:xxxyyyz
/^abc/m
xyz\nabc
xyz\nabc\<lf>
xyz\r\nabc\<lf>
xyz\rabc\<cr>
xyz\r\nabc\<crlf>
** Failers
xyz\nabc\<cr>
xyz\r\nabc\<cr>
xyz\nabc\<crlf>
xyz\rabc\<crlf>
xyz\rabc\<lf>
/abc$/m<lf>
xyzabc
xyzabc\n
xyzabc\npqr
xyzabc\r\<cr>
xyzabc\rpqr\<cr>
xyzabc\r\n\<crlf>
xyzabc\r\npqr\<crlf>
** Failers
xyzabc\r
xyzabc\rpqr
xyzabc\r\n
xyzabc\r\npqr
/^abc/m<cr>
xyz\rabcdef
xyz\nabcdef\<lf>
** Failers
xyz\nabcdef
/^abc/m<lf>
xyz\nabcdef
xyz\rabcdef\<cr>
** Failers
xyz\rabcdef
/^abc/m<crlf>
xyz\r\nabcdef
xyz\rabcdef\<cr>
** Failers
xyz\rabcdef
/.*/<lf>
abc\ndef
abc\rdef
abc\r\ndef
\<cr>abc\ndef
\<cr>abc\rdef
\<cr>abc\r\ndef
\<crlf>abc\ndef
\<crlf>abc\rdef
\<crlf>abc\r\ndef
/\w+(.)(.)?def/s
abc\ndef
abc\rdef
abc\r\ndef
/^\w+=.*(\\\n.*)*/
abc=xyz\\\npqr
/^(a()*)*/
aaaa
/^(?:a(?:(?:))*)*/
aaaa
/^(a()+)+/
aaaa
/^(?:a(?:(?:))+)+/
aaaa
/(a|)*\d/
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa4
/(?>a|)*\d/
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa4
/(?:a|)*\d/
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa4
/^a.b/<lf>
a\rb
a\nb\<cr>
** Failers
a\nb
a\nb\<any>
a\rb\<cr>
a\rb\<any>
/^abc./mgx<any>
abc1 \x0aabc2 \x0babc3xx \x0cabc4 \x0dabc5xx \x0d\x0aabc6 \x85abc7 JUNK
/abc.$/mgx<any>
abc1\x0a abc2\x0b abc3\x0c abc4\x0d abc5\x0d\x0a abc6\x85 abc9
/^a\Rb/<bsr_unicode>
a\nb
a\rb
a\r\nb
a\x0bb
a\x0cb
a\x85b
** Failers
a\n\rb
/^a\R*b/<bsr_unicode>
ab
a\nb
a\rb
a\r\nb
a\x0bb
a\x0cb
a\x85b
a\n\rb
a\n\r\x85\x0cb
/^a\R+b/<bsr_unicode>
a\nb
a\rb
a\r\nb
a\x0bb
a\x0cb
a\x85b
a\n\rb
a\n\r\x85\x0cb
** Failers
ab
/^a\R{1,3}b/<bsr_unicode>
a\nb
a\n\rb
a\n\r\x85b
a\r\n\r\nb
a\r\n\r\n\r\nb
a\n\r\n\rb
a\n\n\r\nb
** Failers
a\n\n\n\rb
a\r
/^a[\R]b/<bsr_unicode>
aRb
** Failers
a\nb
/.+foo/
afoo
** Failers
\r\nfoo
\nfoo
/.+foo/<crlf>
afoo
\nfoo
** Failers
\r\nfoo
/.+foo/<any>
afoo
** Failers
\nfoo
\r\nfoo
/.+foo/s
afoo
\r\nfoo
\nfoo
/^$/mg<any>
abc\r\rxyz
abc\n\rxyz
** Failers
abc\r\nxyz
/^X/m
XABC
** Failers
XABC\B
/(?m)^$/<any>g+
abc\r\n\r\n
/(?m)^$|^\r\n/<any>g+
abc\r\n\r\n
/(?m)$/<any>g+
abc\r\n\r\n
/(?|(abc)|(xyz))/
>abc<
>xyz<
/(x)(?|(abc)|(xyz))(x)/
xabcx
xxyzx
/(x)(?|(abc)(pqr)|(xyz))(x)/
xabcpqrx
xxyzx
/(?|(abc)|(xyz))(?1)/
abcabc
xyzabc
** Failers
xyzxyz
/\H\h\V\v/
X X\x0a
X\x09X\x0b
** Failers
\xa0 X\x0a
/\H*\h+\V?\v{3,4}/
\x09\x20\xa0X\x0a\x0b\x0c\x0d\x0a
\x09\x20\xa0\x0a\x0b\x0c\x0d\x0a
\x09\x20\xa0\x0a\x0b\x0c
** Failers
\x09\x20\xa0\x0a\x0b
/\H{3,4}/
XY ABCDE
XY PQR ST
/.\h{3,4}./
XY AB PQRS
/\h*X\h?\H+Y\H?Z/
>XNNNYZ
> X NYQZ
** Failers
>XYZ
> X NY Z
/\v*X\v?Y\v+Z\V*\x0a\V+\x0b\V{2,3}\x0c/
>XY\x0aZ\x0aA\x0bNN\x0c
>\x0a\x0dX\x0aY\x0a\x0bZZZ\x0aAAA\x0bNNN\x0c
/.+A/<crlf>
\r\nA
/\nA/<crlf>
\r\nA
/[\r\n]A/<crlf>
\r\nA
/(\r|\n)A/<crlf>
\r\nA
/a\Rb/I<bsr_anycrlf>
a\rb
a\nb
a\r\nb
** Failers
a\x85b
a\x0bb
/a\Rb/I<bsr_unicode>
a\rb
a\nb
a\r\nb
a\x85b
a\x0bb
** Failers
a\x85b\<bsr_anycrlf>
a\x0bb\<bsr_anycrlf>
/a\R?b/I<bsr_anycrlf>
a\rb
a\nb
a\r\nb
** Failers
a\x85b
a\x0bb
/a\R?b/I<bsr_unicode>
a\rb
a\nb
a\r\nb
a\x85b
a\x0bb
** Failers
a\x85b\<bsr_anycrlf>
a\x0bb\<bsr_anycrlf>
/a\R{2,4}b/I<bsr_anycrlf>
a\r\n\nb
a\n\r\rb
a\r\n\r\n\r\n\r\nb
** Failers
a\x85\85b
a\x0b\0bb
/a\R{2,4}b/I<bsr_unicode>
a\r\rb
a\n\n\nb
a\r\n\n\r\rb
a\x85\85b
a\x0b\0bb
** Failers
a\r\r\r\r\rb
a\x85\85b\<bsr_anycrlf>
a\x0b\0bb\<bsr_anycrlf>
/a(?!)|\wbc/
abc
/a[]b/<JS>
** Failers
ab
/a[]+b/<JS>
** Failers
ab
/a[]*+b/<JS>
** Failers
ab
/a[^]b/<JS>
aXb
a\nb
** Failers
ab
/a[^]+b/<JS>
aXb
a\nX\nXb
** Failers
ab
/X$/E
X
** Failers
X\n
/X$/
X
X\n
/xyz/C
xyz
abcxyz
abcxyz\Y
** Failers
abc
abc\Y
abcxypqr
abcxypqr\Y
/(*NO_START_OPT)xyz/C
abcxyz
/(?C)ab/
ab
\C-ab
/ab/C
ab
\C-ab
/^"((?(?=[a])[^"])|b)*"$/C
"ab"
\C-"ab"
/\d+X|9+Y/
++++123999\P
++++123999Y\P
/Z(*F)/
Z\P
ZA\P
/Z(?!)/
Z\P
ZA\P
/dog(sbody)?/
dogs\P
dogs\P\P
/dog(sbody)??/
dogs\P
dogs\P\P
/dog|dogsbody/
dogs\P
dogs\P\P
/dogsbody|dog/
dogs\P
dogs\P\P
/Z(*F)Q|ZXY/
Z\P
ZA\P
X\P
/\bthe cat\b/
the cat\P
the cat\P\P
/dog(sbody)?/
dogs\D\P
body\D\R
/dog(sbody)?/
dogs\D\P\P
body\D\R
/abc/
abc\P
abc\P\P
/abc\K123/
xyzabc123pqr
/(?<=abc)123/
xyzabc123pqr
xyzabc12\P
xyzabc12\P\P
/\babc\b/
+++abc+++
+++ab\P
+++ab\P\P
/(?=C)/g+
ABCDECBA
/(abc|def|xyz)/I
terhjk;abcdaadsfe
the quick xyz brown fox
\Yterhjk;abcdaadsfe
\Ythe quick xyz brown fox
** Failers
thejk;adlfj aenjl;fda asdfasd ehj;kjxyasiupd
\Ythejk;adlfj aenjl;fda asdfasd ehj;kjxyasiupd
/(abc|def|xyz)/SI
terhjk;abcdaadsfe
the quick xyz brown fox
\Yterhjk;abcdaadsfe
\Ythe quick xyz brown fox
** Failers
thejk;adlfj aenjl;fda asdfasd ehj;kjxyasiupd
\Ythejk;adlfj aenjl;fda asdfasd ehj;kjxyasiupd
/abcd*/+
xxxxabcd\P
xxxxabcd\P\P
dddxxx\R
xxxxabcd\P\P
xxx\R
/abcd*/i
xxxxabcd\P
xxxxabcd\P\P
XXXXABCD\P
XXXXABCD\P\P
/abc\d*/
xxxxabc1\P
xxxxabc1\P\P
/abc[de]*/
xxxxabcde\P
xxxxabcde\P\P
/(?:(?1)|B)(A(*F)|C)/
ABCD
CCD
** Failers
CAD
/^(?:(?1)|B)(A(*F)|C)/
CCD
BCD
** Failers
ABCD
CAD
BAD
/^(?!a(*SKIP)b)/
ac
/^(?=a(*SKIP)b|ac)/
** Failers
ac
/^(?=a(*THEN)b|ac)/
ac
/^(?=a(*PRUNE)b)/
ab
** Failers
ac
/^(?(?!a(*SKIP)b))/
ac
/(?<=abc)def/
abc\P\P
/abc$/
abc
abc\P
abc\P\P
/abc$/m
abc
abc\n
abc\P\P
abc\n\P\P
abc\P
abc\n\P
/abc\z/
abc
abc\P
abc\P\P
/abc\Z/
abc
abc\P
abc\P\P
/abc\b/
abc
abc\P
abc\P\P
/abc\B/
abc
abc\P
abc\P\P
/.+/
abc\>0
abc\>1
abc\>2
abc\>3
abc\>4
abc\>-4
/^(?:a)++\w/
aaaab
** Failers
aaaa
bbb
/^(?:aa|(?:a)++\w)/
aaaab
aaaa
** Failers
bbb
/^(?:a)*+\w/
aaaab
bbb
** Failers
aaaa
/^(a)++\w/
aaaab
** Failers
aaaa
bbb
/^(a|)++\w/
aaaab
** Failers
aaaa
bbb
/(?=abc){3}abc/+
abcabcabc
** Failers
xyz
/(?=abc)+abc/+
abcabcabc
** Failers
xyz
/(?=abc)++abc/+
abcabcabc
** Failers
xyz
/(?=abc){0}xyz/
xyz
/(?=abc){1}xyz/
** Failers
xyz
/(?=(a))?./
ab
bc
/(?=(a))??./
ab
bc
/^(?=(a)){0}b(?1)/
backgammon
/^(?=(?1))?[az]([abc])d/
abd
zcdxx
/^(?!a){0}\w+/
aaaaa
/(?<=(abc))?xyz/
abcxyz
pqrxyz
/((?2))((?1))/
abc
/(?(R)a+|(?R)b)/
aaaabcde
/(?(R)a+|((?R))b)/
aaaabcde
/((?(R)a+|(?1)b))/
aaaabcde
/((?(R2)a+|(?1)b))/
aaaabcde
/(?(R)a*(?1)|((?R))b)/
aaaabcde
/(a+)/O
\O6aaaa
\O8aaaa
/ab\Cde/
abXde
/(?<=ab\Cde)X/
abZdeX
/^\R/
\r\P
\r\P\P
/^\R{2,3}x/
\r\P
\r\P\P
\r\r\P
\r\r\P\P
\r\r\r\P
\r\r\r\P\P
\r\rx
\r\r\rx
/^\R{2,3}?x/
\r\P
\r\P\P
\r\r\P
\r\r\P\P
\r\r\r\P
\r\r\r\P\P
\r\rx
\r\r\rx
/^\R?x/
\r\P
\r\P\P
x
\rx
/^\R+x/
\r\P
\r\P\P
\r\n\P
\r\n\P\P
\rx
/^a$/<CRLF>
a\r\P
a\r\P\P
/^a$/m<CRLF>
a\r\P
a\r\P\P
/^(a$|a\r)/<CRLF>
a\r\P
a\r\P\P
/^(a$|a\r)/m<CRLF>
a\r\P
a\r\P\P
/./<CRLF>
\r\P
\r\P\P
/.{2,3}/<CRLF>
\r\P
\r\P\P
\r\r\P
\r\r\P\P
\r\r\r\P
\r\r\r\P\P
/.{2,3}?/<CRLF>
\r\P
\r\P\P
\r\r\P
\r\r\P\P
\r\r\r\P
\r\r\r\P\P
/-- Test simple validity check for restarts --/
/abcdef/
abc\R
/<H((?(?!<H|F>)(.)|(?R))++)*F>/
text <H more text <H texting more hexA0-"\xA0" hex above 7F-"\xBC" F> text xxxxx <H text F> text F> text2 <H text sample F> more text.
/^(?>.{4})abc|^\w\w.xabcd/
xxxxabcd
xx\xa0xabcd
/^(.{4}){2}+abc|^\w\w.x\w\w\w\wabcd/
xxxxxxxxabcd
xx\xa0xxxxxabcd
/abcd/
abcd\O0
/-- These tests show up auto-possessification --/
/[ab]*/
aaaa
/[ab]*?/
aaaa
/[ab]?/
aaaa
/[ab]??/
aaaa
/[ab]+/
aaaa
/[ab]+?/
aaaa
/[ab]{2,3}/
aaaa
/[ab]{2,3}?/
aaaa
/[ab]{2,}/
aaaa
/[ab]{2,}?/
aaaa
/-- End of testinput8 --/
| {
"language": "Assembly"
} |
TITLE ../openssl/crypto/bn/asm/bn-586.asm
IF @Version LT 800
ECHO MASM version 8.00 or later is strongly recommended.
ENDIF
.686
.XMM
IF @Version LT 800
XMMWORD STRUCT 16
DQ 2 dup (?)
XMMWORD ENDS
ENDIF
.MODEL FLAT
OPTION DOTNAME
IF @Version LT 800
.text$ SEGMENT PAGE 'CODE'
ELSE
.text$ SEGMENT ALIGN(64) 'CODE'
ENDIF
;EXTERN _OPENSSL_ia32cap_P:NEAR
ALIGN 16
_bn_mul_add_words PROC PUBLIC
$L_bn_mul_add_words_begin::
lea eax,DWORD PTR _OPENSSL_ia32cap_P
bt DWORD PTR [eax],26
jnc $L000maw_non_sse2
mov eax,DWORD PTR 4[esp]
mov edx,DWORD PTR 8[esp]
mov ecx,DWORD PTR 12[esp]
movd mm0,DWORD PTR 16[esp]
pxor mm1,mm1
jmp $L001maw_sse2_entry
ALIGN 16
$L002maw_sse2_unrolled:
movd mm3,DWORD PTR [eax]
paddq mm1,mm3
movd mm2,DWORD PTR [edx]
pmuludq mm2,mm0
movd mm4,DWORD PTR 4[edx]
pmuludq mm4,mm0
movd mm6,DWORD PTR 8[edx]
pmuludq mm6,mm0
movd mm7,DWORD PTR 12[edx]
pmuludq mm7,mm0
paddq mm1,mm2
movd mm3,DWORD PTR 4[eax]
paddq mm3,mm4
movd mm5,DWORD PTR 8[eax]
paddq mm5,mm6
movd mm4,DWORD PTR 12[eax]
paddq mm7,mm4
movd DWORD PTR [eax],mm1
movd mm2,DWORD PTR 16[edx]
pmuludq mm2,mm0
psrlq mm1,32
movd mm4,DWORD PTR 20[edx]
pmuludq mm4,mm0
paddq mm1,mm3
movd mm6,DWORD PTR 24[edx]
pmuludq mm6,mm0
movd DWORD PTR 4[eax],mm1
psrlq mm1,32
movd mm3,DWORD PTR 28[edx]
add edx,32
pmuludq mm3,mm0
paddq mm1,mm5
movd mm5,DWORD PTR 16[eax]
paddq mm2,mm5
movd DWORD PTR 8[eax],mm1
psrlq mm1,32
paddq mm1,mm7
movd mm5,DWORD PTR 20[eax]
paddq mm4,mm5
movd DWORD PTR 12[eax],mm1
psrlq mm1,32
paddq mm1,mm2
movd mm5,DWORD PTR 24[eax]
paddq mm6,mm5
movd DWORD PTR 16[eax],mm1
psrlq mm1,32
paddq mm1,mm4
movd mm5,DWORD PTR 28[eax]
paddq mm3,mm5
movd DWORD PTR 20[eax],mm1
psrlq mm1,32
paddq mm1,mm6
movd DWORD PTR 24[eax],mm1
psrlq mm1,32
paddq mm1,mm3
movd DWORD PTR 28[eax],mm1
lea eax,DWORD PTR 32[eax]
psrlq mm1,32
sub ecx,8
jz $L003maw_sse2_exit
$L001maw_sse2_entry:
test ecx,4294967288
jnz $L002maw_sse2_unrolled
ALIGN 4
$L004maw_sse2_loop:
movd mm2,DWORD PTR [edx]
movd mm3,DWORD PTR [eax]
pmuludq mm2,mm0
lea edx,DWORD PTR 4[edx]
paddq mm1,mm3
paddq mm1,mm2
movd DWORD PTR [eax],mm1
sub ecx,1
psrlq mm1,32
lea eax,DWORD PTR 4[eax]
jnz $L004maw_sse2_loop
$L003maw_sse2_exit:
movd eax,mm1
emms
ret
ALIGN 16
$L000maw_non_sse2:
push ebp
push ebx
push esi
push edi
;
xor esi,esi
mov edi,DWORD PTR 20[esp]
mov ecx,DWORD PTR 28[esp]
mov ebx,DWORD PTR 24[esp]
and ecx,4294967288
mov ebp,DWORD PTR 32[esp]
push ecx
jz $L005maw_finish
ALIGN 16
$L006maw_loop:
; Round 0
mov eax,DWORD PTR [ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR [edi]
adc edx,0
mov DWORD PTR [edi],eax
mov esi,edx
; Round 4
mov eax,DWORD PTR 4[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 4[edi]
adc edx,0
mov DWORD PTR 4[edi],eax
mov esi,edx
; Round 8
mov eax,DWORD PTR 8[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 8[edi]
adc edx,0
mov DWORD PTR 8[edi],eax
mov esi,edx
; Round 12
mov eax,DWORD PTR 12[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 12[edi]
adc edx,0
mov DWORD PTR 12[edi],eax
mov esi,edx
; Round 16
mov eax,DWORD PTR 16[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 16[edi]
adc edx,0
mov DWORD PTR 16[edi],eax
mov esi,edx
; Round 20
mov eax,DWORD PTR 20[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 20[edi]
adc edx,0
mov DWORD PTR 20[edi],eax
mov esi,edx
; Round 24
mov eax,DWORD PTR 24[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 24[edi]
adc edx,0
mov DWORD PTR 24[edi],eax
mov esi,edx
; Round 28
mov eax,DWORD PTR 28[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 28[edi]
adc edx,0
mov DWORD PTR 28[edi],eax
mov esi,edx
;
sub ecx,8
lea ebx,DWORD PTR 32[ebx]
lea edi,DWORD PTR 32[edi]
jnz $L006maw_loop
$L005maw_finish:
mov ecx,DWORD PTR 32[esp]
and ecx,7
jnz $L007maw_finish2
jmp $L008maw_end
$L007maw_finish2:
; Tail Round 0
mov eax,DWORD PTR [ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR [edi]
adc edx,0
dec ecx
mov DWORD PTR [edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 1
mov eax,DWORD PTR 4[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 4[edi]
adc edx,0
dec ecx
mov DWORD PTR 4[edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 2
mov eax,DWORD PTR 8[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 8[edi]
adc edx,0
dec ecx
mov DWORD PTR 8[edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 3
mov eax,DWORD PTR 12[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 12[edi]
adc edx,0
dec ecx
mov DWORD PTR 12[edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 4
mov eax,DWORD PTR 16[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 16[edi]
adc edx,0
dec ecx
mov DWORD PTR 16[edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 5
mov eax,DWORD PTR 20[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 20[edi]
adc edx,0
dec ecx
mov DWORD PTR 20[edi],eax
mov esi,edx
jz $L008maw_end
; Tail Round 6
mov eax,DWORD PTR 24[ebx]
mul ebp
add eax,esi
adc edx,0
add eax,DWORD PTR 24[edi]
adc edx,0
mov DWORD PTR 24[edi],eax
mov esi,edx
$L008maw_end:
mov eax,esi
pop ecx
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_mul_add_words ENDP
ALIGN 16
_bn_mul_words PROC PUBLIC
$L_bn_mul_words_begin::
lea eax,DWORD PTR _OPENSSL_ia32cap_P
bt DWORD PTR [eax],26
jnc $L009mw_non_sse2
mov eax,DWORD PTR 4[esp]
mov edx,DWORD PTR 8[esp]
mov ecx,DWORD PTR 12[esp]
movd mm0,DWORD PTR 16[esp]
pxor mm1,mm1
ALIGN 16
$L010mw_sse2_loop:
movd mm2,DWORD PTR [edx]
pmuludq mm2,mm0
lea edx,DWORD PTR 4[edx]
paddq mm1,mm2
movd DWORD PTR [eax],mm1
sub ecx,1
psrlq mm1,32
lea eax,DWORD PTR 4[eax]
jnz $L010mw_sse2_loop
movd eax,mm1
emms
ret
ALIGN 16
$L009mw_non_sse2:
push ebp
push ebx
push esi
push edi
;
xor esi,esi
mov edi,DWORD PTR 20[esp]
mov ebx,DWORD PTR 24[esp]
mov ebp,DWORD PTR 28[esp]
mov ecx,DWORD PTR 32[esp]
and ebp,4294967288
jz $L011mw_finish
$L012mw_loop:
; Round 0
mov eax,DWORD PTR [ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR [edi],eax
mov esi,edx
; Round 4
mov eax,DWORD PTR 4[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 4[edi],eax
mov esi,edx
; Round 8
mov eax,DWORD PTR 8[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 8[edi],eax
mov esi,edx
; Round 12
mov eax,DWORD PTR 12[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 12[edi],eax
mov esi,edx
; Round 16
mov eax,DWORD PTR 16[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 16[edi],eax
mov esi,edx
; Round 20
mov eax,DWORD PTR 20[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 20[edi],eax
mov esi,edx
; Round 24
mov eax,DWORD PTR 24[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 24[edi],eax
mov esi,edx
; Round 28
mov eax,DWORD PTR 28[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 28[edi],eax
mov esi,edx
;
add ebx,32
add edi,32
sub ebp,8
jz $L011mw_finish
jmp $L012mw_loop
$L011mw_finish:
mov ebp,DWORD PTR 28[esp]
and ebp,7
jnz $L013mw_finish2
jmp $L014mw_end
$L013mw_finish2:
; Tail Round 0
mov eax,DWORD PTR [ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR [edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 1
mov eax,DWORD PTR 4[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 4[edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 2
mov eax,DWORD PTR 8[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 8[edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 3
mov eax,DWORD PTR 12[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 12[edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 4
mov eax,DWORD PTR 16[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 16[edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 5
mov eax,DWORD PTR 20[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 20[edi],eax
mov esi,edx
dec ebp
jz $L014mw_end
; Tail Round 6
mov eax,DWORD PTR 24[ebx]
mul ecx
add eax,esi
adc edx,0
mov DWORD PTR 24[edi],eax
mov esi,edx
$L014mw_end:
mov eax,esi
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_mul_words ENDP
ALIGN 16
_bn_sqr_words PROC PUBLIC
$L_bn_sqr_words_begin::
lea eax,DWORD PTR _OPENSSL_ia32cap_P
bt DWORD PTR [eax],26
jnc $L015sqr_non_sse2
mov eax,DWORD PTR 4[esp]
mov edx,DWORD PTR 8[esp]
mov ecx,DWORD PTR 12[esp]
ALIGN 16
$L016sqr_sse2_loop:
movd mm0,DWORD PTR [edx]
pmuludq mm0,mm0
lea edx,DWORD PTR 4[edx]
movq QWORD PTR [eax],mm0
sub ecx,1
lea eax,DWORD PTR 8[eax]
jnz $L016sqr_sse2_loop
emms
ret
ALIGN 16
$L015sqr_non_sse2:
push ebp
push ebx
push esi
push edi
;
mov esi,DWORD PTR 20[esp]
mov edi,DWORD PTR 24[esp]
mov ebx,DWORD PTR 28[esp]
and ebx,4294967288
jz $L017sw_finish
$L018sw_loop:
; Round 0
mov eax,DWORD PTR [edi]
mul eax
mov DWORD PTR [esi],eax
mov DWORD PTR 4[esi],edx
; Round 4
mov eax,DWORD PTR 4[edi]
mul eax
mov DWORD PTR 8[esi],eax
mov DWORD PTR 12[esi],edx
; Round 8
mov eax,DWORD PTR 8[edi]
mul eax
mov DWORD PTR 16[esi],eax
mov DWORD PTR 20[esi],edx
; Round 12
mov eax,DWORD PTR 12[edi]
mul eax
mov DWORD PTR 24[esi],eax
mov DWORD PTR 28[esi],edx
; Round 16
mov eax,DWORD PTR 16[edi]
mul eax
mov DWORD PTR 32[esi],eax
mov DWORD PTR 36[esi],edx
; Round 20
mov eax,DWORD PTR 20[edi]
mul eax
mov DWORD PTR 40[esi],eax
mov DWORD PTR 44[esi],edx
; Round 24
mov eax,DWORD PTR 24[edi]
mul eax
mov DWORD PTR 48[esi],eax
mov DWORD PTR 52[esi],edx
; Round 28
mov eax,DWORD PTR 28[edi]
mul eax
mov DWORD PTR 56[esi],eax
mov DWORD PTR 60[esi],edx
;
add edi,32
add esi,64
sub ebx,8
jnz $L018sw_loop
$L017sw_finish:
mov ebx,DWORD PTR 28[esp]
and ebx,7
jz $L019sw_end
; Tail Round 0
mov eax,DWORD PTR [edi]
mul eax
mov DWORD PTR [esi],eax
dec ebx
mov DWORD PTR 4[esi],edx
jz $L019sw_end
; Tail Round 1
mov eax,DWORD PTR 4[edi]
mul eax
mov DWORD PTR 8[esi],eax
dec ebx
mov DWORD PTR 12[esi],edx
jz $L019sw_end
; Tail Round 2
mov eax,DWORD PTR 8[edi]
mul eax
mov DWORD PTR 16[esi],eax
dec ebx
mov DWORD PTR 20[esi],edx
jz $L019sw_end
; Tail Round 3
mov eax,DWORD PTR 12[edi]
mul eax
mov DWORD PTR 24[esi],eax
dec ebx
mov DWORD PTR 28[esi],edx
jz $L019sw_end
; Tail Round 4
mov eax,DWORD PTR 16[edi]
mul eax
mov DWORD PTR 32[esi],eax
dec ebx
mov DWORD PTR 36[esi],edx
jz $L019sw_end
; Tail Round 5
mov eax,DWORD PTR 20[edi]
mul eax
mov DWORD PTR 40[esi],eax
dec ebx
mov DWORD PTR 44[esi],edx
jz $L019sw_end
; Tail Round 6
mov eax,DWORD PTR 24[edi]
mul eax
mov DWORD PTR 48[esi],eax
mov DWORD PTR 52[esi],edx
$L019sw_end:
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_sqr_words ENDP
ALIGN 16
_bn_div_words PROC PUBLIC
$L_bn_div_words_begin::
mov edx,DWORD PTR 4[esp]
mov eax,DWORD PTR 8[esp]
mov ecx,DWORD PTR 12[esp]
div ecx
ret
_bn_div_words ENDP
ALIGN 16
_bn_add_words PROC PUBLIC
$L_bn_add_words_begin::
push ebp
push ebx
push esi
push edi
;
mov ebx,DWORD PTR 20[esp]
mov esi,DWORD PTR 24[esp]
mov edi,DWORD PTR 28[esp]
mov ebp,DWORD PTR 32[esp]
xor eax,eax
and ebp,4294967288
jz $L020aw_finish
$L021aw_loop:
; Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
; Round 1
mov ecx,DWORD PTR 4[esi]
mov edx,DWORD PTR 4[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 4[ebx],ecx
; Round 2
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 8[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 8[ebx],ecx
; Round 3
mov ecx,DWORD PTR 12[esi]
mov edx,DWORD PTR 12[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 12[ebx],ecx
; Round 4
mov ecx,DWORD PTR 16[esi]
mov edx,DWORD PTR 16[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 16[ebx],ecx
; Round 5
mov ecx,DWORD PTR 20[esi]
mov edx,DWORD PTR 20[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 20[ebx],ecx
; Round 6
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 24[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
; Round 7
mov ecx,DWORD PTR 28[esi]
mov edx,DWORD PTR 28[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 28[ebx],ecx
;
add esi,32
add edi,32
add ebx,32
sub ebp,8
jnz $L021aw_loop
$L020aw_finish:
mov ebp,DWORD PTR 32[esp]
and ebp,7
jz $L022aw_end
; Tail Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR [ebx],ecx
jz $L022aw_end
; Tail Round 1
mov ecx,DWORD PTR 4[esi]
mov edx,DWORD PTR 4[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 4[ebx],ecx
jz $L022aw_end
; Tail Round 2
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 8[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 8[ebx],ecx
jz $L022aw_end
; Tail Round 3
mov ecx,DWORD PTR 12[esi]
mov edx,DWORD PTR 12[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 12[ebx],ecx
jz $L022aw_end
; Tail Round 4
mov ecx,DWORD PTR 16[esi]
mov edx,DWORD PTR 16[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 16[ebx],ecx
jz $L022aw_end
; Tail Round 5
mov ecx,DWORD PTR 20[esi]
mov edx,DWORD PTR 20[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 20[ebx],ecx
jz $L022aw_end
; Tail Round 6
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 24[edi]
add ecx,eax
mov eax,0
adc eax,eax
add ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
$L022aw_end:
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_add_words ENDP
ALIGN 16
_bn_sub_words PROC PUBLIC
$L_bn_sub_words_begin::
push ebp
push ebx
push esi
push edi
;
mov ebx,DWORD PTR 20[esp]
mov esi,DWORD PTR 24[esp]
mov edi,DWORD PTR 28[esp]
mov ebp,DWORD PTR 32[esp]
xor eax,eax
and ebp,4294967288
jz $L023aw_finish
$L024aw_loop:
; Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
; Round 1
mov ecx,DWORD PTR 4[esi]
mov edx,DWORD PTR 4[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 4[ebx],ecx
; Round 2
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 8[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 8[ebx],ecx
; Round 3
mov ecx,DWORD PTR 12[esi]
mov edx,DWORD PTR 12[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 12[ebx],ecx
; Round 4
mov ecx,DWORD PTR 16[esi]
mov edx,DWORD PTR 16[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 16[ebx],ecx
; Round 5
mov ecx,DWORD PTR 20[esi]
mov edx,DWORD PTR 20[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 20[ebx],ecx
; Round 6
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 24[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
; Round 7
mov ecx,DWORD PTR 28[esi]
mov edx,DWORD PTR 28[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 28[ebx],ecx
;
add esi,32
add edi,32
add ebx,32
sub ebp,8
jnz $L024aw_loop
$L023aw_finish:
mov ebp,DWORD PTR 32[esp]
and ebp,7
jz $L025aw_end
; Tail Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR [ebx],ecx
jz $L025aw_end
; Tail Round 1
mov ecx,DWORD PTR 4[esi]
mov edx,DWORD PTR 4[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 4[ebx],ecx
jz $L025aw_end
; Tail Round 2
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 8[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 8[ebx],ecx
jz $L025aw_end
; Tail Round 3
mov ecx,DWORD PTR 12[esi]
mov edx,DWORD PTR 12[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 12[ebx],ecx
jz $L025aw_end
; Tail Round 4
mov ecx,DWORD PTR 16[esi]
mov edx,DWORD PTR 16[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 16[ebx],ecx
jz $L025aw_end
; Tail Round 5
mov ecx,DWORD PTR 20[esi]
mov edx,DWORD PTR 20[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 20[ebx],ecx
jz $L025aw_end
; Tail Round 6
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 24[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
$L025aw_end:
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_sub_words ENDP
ALIGN 16
_bn_sub_part_words PROC PUBLIC
$L_bn_sub_part_words_begin::
push ebp
push ebx
push esi
push edi
;
mov ebx,DWORD PTR 20[esp]
mov esi,DWORD PTR 24[esp]
mov edi,DWORD PTR 28[esp]
mov ebp,DWORD PTR 32[esp]
xor eax,eax
and ebp,4294967288
jz $L026aw_finish
$L027aw_loop:
; Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
; Round 1
mov ecx,DWORD PTR 4[esi]
mov edx,DWORD PTR 4[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 4[ebx],ecx
; Round 2
mov ecx,DWORD PTR 8[esi]
mov edx,DWORD PTR 8[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 8[ebx],ecx
; Round 3
mov ecx,DWORD PTR 12[esi]
mov edx,DWORD PTR 12[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 12[ebx],ecx
; Round 4
mov ecx,DWORD PTR 16[esi]
mov edx,DWORD PTR 16[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 16[ebx],ecx
; Round 5
mov ecx,DWORD PTR 20[esi]
mov edx,DWORD PTR 20[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 20[ebx],ecx
; Round 6
mov ecx,DWORD PTR 24[esi]
mov edx,DWORD PTR 24[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
; Round 7
mov ecx,DWORD PTR 28[esi]
mov edx,DWORD PTR 28[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 28[ebx],ecx
;
add esi,32
add edi,32
add ebx,32
sub ebp,8
jnz $L027aw_loop
$L026aw_finish:
mov ebp,DWORD PTR 32[esp]
and ebp,7
jz $L028aw_end
; Tail Round 0
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 1
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 2
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 3
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 4
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 5
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
dec ebp
jz $L028aw_end
; Tail Round 6
mov ecx,DWORD PTR [esi]
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
add esi,4
add edi,4
add ebx,4
$L028aw_end:
cmp DWORD PTR 36[esp],0
je $L029pw_end
mov ebp,DWORD PTR 36[esp]
cmp ebp,0
je $L029pw_end
jge $L030pw_pos
; pw_neg
mov edx,0
sub edx,ebp
mov ebp,edx
and ebp,4294967288
jz $L031pw_neg_finish
$L032pw_neg_loop:
; dl<0 Round 0
mov ecx,0
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR [ebx],ecx
; dl<0 Round 1
mov ecx,0
mov edx,DWORD PTR 4[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 4[ebx],ecx
; dl<0 Round 2
mov ecx,0
mov edx,DWORD PTR 8[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 8[ebx],ecx
; dl<0 Round 3
mov ecx,0
mov edx,DWORD PTR 12[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 12[ebx],ecx
; dl<0 Round 4
mov ecx,0
mov edx,DWORD PTR 16[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 16[ebx],ecx
; dl<0 Round 5
mov ecx,0
mov edx,DWORD PTR 20[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 20[ebx],ecx
; dl<0 Round 6
mov ecx,0
mov edx,DWORD PTR 24[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
; dl<0 Round 7
mov ecx,0
mov edx,DWORD PTR 28[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 28[ebx],ecx
;
add edi,32
add ebx,32
sub ebp,8
jnz $L032pw_neg_loop
$L031pw_neg_finish:
mov edx,DWORD PTR 36[esp]
mov ebp,0
sub ebp,edx
and ebp,7
jz $L029pw_end
; dl<0 Tail Round 0
mov ecx,0
mov edx,DWORD PTR [edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR [ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 1
mov ecx,0
mov edx,DWORD PTR 4[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 4[ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 2
mov ecx,0
mov edx,DWORD PTR 8[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 8[ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 3
mov ecx,0
mov edx,DWORD PTR 12[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 12[ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 4
mov ecx,0
mov edx,DWORD PTR 16[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 16[ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 5
mov ecx,0
mov edx,DWORD PTR 20[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
dec ebp
mov DWORD PTR 20[ebx],ecx
jz $L029pw_end
; dl<0 Tail Round 6
mov ecx,0
mov edx,DWORD PTR 24[edi]
sub ecx,eax
mov eax,0
adc eax,eax
sub ecx,edx
adc eax,0
mov DWORD PTR 24[ebx],ecx
jmp $L029pw_end
$L030pw_pos:
and ebp,4294967288
jz $L033pw_pos_finish
$L034pw_pos_loop:
; dl>0 Round 0
mov ecx,DWORD PTR [esi]
sub ecx,eax
mov DWORD PTR [ebx],ecx
jnc $L035pw_nc0
; dl>0 Round 1
mov ecx,DWORD PTR 4[esi]
sub ecx,eax
mov DWORD PTR 4[ebx],ecx
jnc $L036pw_nc1
; dl>0 Round 2
mov ecx,DWORD PTR 8[esi]
sub ecx,eax
mov DWORD PTR 8[ebx],ecx
jnc $L037pw_nc2
; dl>0 Round 3
mov ecx,DWORD PTR 12[esi]
sub ecx,eax
mov DWORD PTR 12[ebx],ecx
jnc $L038pw_nc3
; dl>0 Round 4
mov ecx,DWORD PTR 16[esi]
sub ecx,eax
mov DWORD PTR 16[ebx],ecx
jnc $L039pw_nc4
; dl>0 Round 5
mov ecx,DWORD PTR 20[esi]
sub ecx,eax
mov DWORD PTR 20[ebx],ecx
jnc $L040pw_nc5
; dl>0 Round 6
mov ecx,DWORD PTR 24[esi]
sub ecx,eax
mov DWORD PTR 24[ebx],ecx
jnc $L041pw_nc6
; dl>0 Round 7
mov ecx,DWORD PTR 28[esi]
sub ecx,eax
mov DWORD PTR 28[ebx],ecx
jnc $L042pw_nc7
;
add esi,32
add ebx,32
sub ebp,8
jnz $L034pw_pos_loop
$L033pw_pos_finish:
mov ebp,DWORD PTR 36[esp]
and ebp,7
jz $L029pw_end
; dl>0 Tail Round 0
mov ecx,DWORD PTR [esi]
sub ecx,eax
mov DWORD PTR [ebx],ecx
jnc $L043pw_tail_nc0
dec ebp
jz $L029pw_end
; dl>0 Tail Round 1
mov ecx,DWORD PTR 4[esi]
sub ecx,eax
mov DWORD PTR 4[ebx],ecx
jnc $L044pw_tail_nc1
dec ebp
jz $L029pw_end
; dl>0 Tail Round 2
mov ecx,DWORD PTR 8[esi]
sub ecx,eax
mov DWORD PTR 8[ebx],ecx
jnc $L045pw_tail_nc2
dec ebp
jz $L029pw_end
; dl>0 Tail Round 3
mov ecx,DWORD PTR 12[esi]
sub ecx,eax
mov DWORD PTR 12[ebx],ecx
jnc $L046pw_tail_nc3
dec ebp
jz $L029pw_end
; dl>0 Tail Round 4
mov ecx,DWORD PTR 16[esi]
sub ecx,eax
mov DWORD PTR 16[ebx],ecx
jnc $L047pw_tail_nc4
dec ebp
jz $L029pw_end
; dl>0 Tail Round 5
mov ecx,DWORD PTR 20[esi]
sub ecx,eax
mov DWORD PTR 20[ebx],ecx
jnc $L048pw_tail_nc5
dec ebp
jz $L029pw_end
; dl>0 Tail Round 6
mov ecx,DWORD PTR 24[esi]
sub ecx,eax
mov DWORD PTR 24[ebx],ecx
jnc $L049pw_tail_nc6
mov eax,1
jmp $L029pw_end
$L050pw_nc_loop:
mov ecx,DWORD PTR [esi]
mov DWORD PTR [ebx],ecx
$L035pw_nc0:
mov ecx,DWORD PTR 4[esi]
mov DWORD PTR 4[ebx],ecx
$L036pw_nc1:
mov ecx,DWORD PTR 8[esi]
mov DWORD PTR 8[ebx],ecx
$L037pw_nc2:
mov ecx,DWORD PTR 12[esi]
mov DWORD PTR 12[ebx],ecx
$L038pw_nc3:
mov ecx,DWORD PTR 16[esi]
mov DWORD PTR 16[ebx],ecx
$L039pw_nc4:
mov ecx,DWORD PTR 20[esi]
mov DWORD PTR 20[ebx],ecx
$L040pw_nc5:
mov ecx,DWORD PTR 24[esi]
mov DWORD PTR 24[ebx],ecx
$L041pw_nc6:
mov ecx,DWORD PTR 28[esi]
mov DWORD PTR 28[ebx],ecx
$L042pw_nc7:
;
add esi,32
add ebx,32
sub ebp,8
jnz $L050pw_nc_loop
mov ebp,DWORD PTR 36[esp]
and ebp,7
jz $L051pw_nc_end
mov ecx,DWORD PTR [esi]
mov DWORD PTR [ebx],ecx
$L043pw_tail_nc0:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 4[esi]
mov DWORD PTR 4[ebx],ecx
$L044pw_tail_nc1:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 8[esi]
mov DWORD PTR 8[ebx],ecx
$L045pw_tail_nc2:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 12[esi]
mov DWORD PTR 12[ebx],ecx
$L046pw_tail_nc3:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 16[esi]
mov DWORD PTR 16[ebx],ecx
$L047pw_tail_nc4:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 20[esi]
mov DWORD PTR 20[ebx],ecx
$L048pw_tail_nc5:
dec ebp
jz $L051pw_nc_end
mov ecx,DWORD PTR 24[esi]
mov DWORD PTR 24[ebx],ecx
$L049pw_tail_nc6:
$L051pw_nc_end:
mov eax,0
$L029pw_end:
pop edi
pop esi
pop ebx
pop ebp
ret
_bn_sub_part_words ENDP
.text$ ENDS
.bss SEGMENT 'BSS'
COMM _OPENSSL_ia32cap_P:DWORD:4
.bss ENDS
END
| {
"language": "Assembly"
} |
;------------------------------------------------------------------------------
;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php.
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
; Module Name:
;
; MultU64x32.nasm
;
; Abstract:
;
; Calculate the product of a 64-bit integer and a 32-bit integer
;
;------------------------------------------------------------------------------
SECTION .text
;------------------------------------------------------------------------------
; UINT64
; EFIAPI
; InternalMathMultU64x32 (
; IN UINT64 Multiplicand,
; IN UINT32 Multiplier
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalMathMultU64x32)
ASM_PFX(InternalMathMultU64x32):
mov ecx, [esp + 12]
mov eax, ecx
imul ecx, [esp + 8] ; overflow not detectable
mul dword [esp + 4]
add edx, ecx
ret
| {
"language": "Assembly"
} |
AC_DEFUN([GP_DYNAMIC_LIBRARIES],[dnl
dnl We require either of those
dnl AC_REQUIRE([AC_LIBTTDL_INSTALLABLE])dnl
dnl AC_REQUIRE([AC_LIBLTDL_CONVENIENCE])dnl
AC_REQUIRE([AC_LIBTOOL_DLOPEN])dnl
AC_REQUIRE([AC_PROG_LIBTOOL])dnl
dnl ---------------------------------------------------------------------------
dnl Check for libltdl:
dnl - lt_dlforeachfile has been introduced in libtool-1.4.
dnl - However, there are still systems out there running libtool-1.3.
dnl For those, we will use our shipped libltdl. This has the welcome
dnl side effect that we don't have to distinguish between libltdl 1.3 with
dnl and without the notorious segfault bug.
dnl - FIXME: In case we're using our own version, we have to check whether
dnl -ldl is required?
dnl ---------------------------------------------------------------------------
# $0
ltdl_msg="no (not found or too old)"
have_ltdl=false
LIBS_save="$LIBS"
LIBS="$LIBLTDL"
AC_CHECK_LIB([ltdl], [lt_dlforeachfile],[
CPPFLAGS_save="$CPPFLAGS"
CPPFLAGS="$LTDLINCL"
AC_CHECK_HEADER([ltdl.h],[
AC_DEFINE([HAVE_LTDL],1,[whether we use libltdl])
ltdl_msg="yes (from system)"
have_ltdl=:
])
CPPFLAGS="$CPPFLAGS_save"
])
LIBS="$LIBS_save"
if "$have_ltdl"; then :; else
AC_MSG_CHECKING([for included libltdl])
if test -d "$srcdir/libltdl"; then
LIBLTDL="\$(top_builddir)/libltdl/libltdlc.la"
LTDLINCL="-I\$(top_srcdir)/libltdl"
have_ltdl=:
ltdl_msg="yes (included)"
AC_MSG_RESULT([yes])
else
AC_MSG_RESULT([no])
AC_MSG_ERROR([
*** Could not detect or configure libltdl.
])
fi
fi
GP_CONFIG_MSG([libltdl],["${ltdl_msg}"])
])dnl
dnl
dnl ####################################################################
dnl
dnl Please do not remove this:
dnl filetype: 2b993145-3256-47b4-84fd-ec4dcdf4fdf9
dnl I use this to find all the different instances of this file which
dnl are supposed to be synchronized.
dnl
dnl Local Variables:
dnl mode: autoconf
dnl End:
| {
"language": "Assembly"
} |
// REQUIRES: arm
// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
// RUN: ld.lld %t -o %t2
// The output file is large, most of it zeroes. We dissassemble only the
// parts we need to speed up the test and avoid a large output file
// RUN: llvm-objdump -d %t2 -start-address=524288 -stop-address=524316 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK1 %s
// RUN: llvm-objdump -d %t2 -start-address=1048576 -stop-address=1048584 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK2 %s
// RUN: llvm-objdump -d %t2 -start-address=1572864 -stop-address=1572872 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK3 %s
// RUN: llvm-objdump -d %t2 -start-address=5242884 -stop-address=5242894 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK4 %s
// RUN: llvm-objdump -d %t2 -start-address=5767168 -stop-address=5767174 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK5 %s
// RUN: llvm-objdump -d %t2 -start-address=16777220 -stop-address=16777240 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK6 %s
// RUN: llvm-objdump -d %t2 -start-address=17825792 -stop-address=17825798 -triple=thumbv7a-linux-gnueabihf | FileCheck -check-prefix=CHECK7 %s
// Test Range extension Thunks for the Thumb conditional branch instruction.
// This instruction only has a range of 1Mb whereas all the other Thumb wide
// Branch instructions have 16Mb range. We still place our pre-created Thunk
// Sections at 16Mb intervals as conditional branches to a target defined
// in a different section are rare.
.syntax unified
// Define a function aligned on a half megabyte boundary
.macro FUNCTION suff
.section .text.\suff\(), "ax", %progbits
.thumb
.balign 0x80000
.globl tfunc\suff\()
.type tfunc\suff\(), %function
tfunc\suff\():
bx lr
.endm
.globl _start
_start:
FUNCTION 00
// Long Range Thunk needed for 16Mb range branch, can reach pre-created Thunk
// Section
bl tfunc33
// CHECK1: Disassembly of section .text:
// CHECK1-EMPTY:
// CHECK1-NEXT: tfunc00:
// CHECK1-NEXT: 80000: 70 47 bx lr
// CHECK1-NEXT: 80002: 7f f3 ff d7 bl #16252926
// CHECK1: __Thumbv7ABSLongThunk_tfunc05:
// CHECK1-NEXT: 80008: 7f f2 fa bf b.w #2621428 <tfunc05>
// CHECK1: __Thumbv7ABSLongThunk_tfunc00:
// CHECK1-NEXT: 8000c: ff f7 f8 bf b.w #-16 <tfunc00>
FUNCTION 01
// tfunc02 is within range of tfunc02
beq.w tfunc02
// tfunc05 is out of range, and we can't reach the pre-created Thunk Section
// create a new one.
bne.w tfunc05
// CHECK2: tfunc01:
// CHECK2-NEXT: 100000: 70 47 bx lr
// CHECK2-NEXT: 100002: 3f f0 fd a7 beq.w #524282 <tfunc02>
// CHECK2-NEXT: 100006: 7f f4 ff a7 bne.w #-524290 <__Thumbv7ABSLongThunk_tfunc05>
FUNCTION 02
// We can reach the Thunk Section created for bne.w tfunc05
bne.w tfunc05
beq.w tfunc00
// CHECK3: 180000: 70 47 bx lr
// CHECK3-NEXT: 180002: 40 f4 01 80 bne.w #-1048574 <__Thumbv7ABSLongThunk_tfunc05>
// CHECK3-NEXT: 180006: 00 f4 01 80 beq.w #-1048574 <__Thumbv7ABSLongThunk_tfunc00>
FUNCTION 03
FUNCTION 04
FUNCTION 05
FUNCTION 06
FUNCTION 07
FUNCTION 08
FUNCTION 09
// CHECK4: __Thumbv7ABSLongThunk_tfunc03:
// CHECK4-NEXT: 500004: ff f4 fc bf b.w #-3145736 <tfunc03>
FUNCTION 10
// We can't reach any Thunk Section, create a new one
beq.w tfunc03
// CHECK5: tfunc10:
// CHECK5-NEXT: 580000: 70 47 bx lr
// CHECK5-NEXT: 580002: 3f f4 ff a7 beq.w #-524290 <__Thumbv7ABSLongThunk_tfunc03>
FUNCTION 11
FUNCTION 12
FUNCTION 13
FUNCTION 14
FUNCTION 15
FUNCTION 16
FUNCTION 17
FUNCTION 18
FUNCTION 19
FUNCTION 20
FUNCTION 21
FUNCTION 22
FUNCTION 23
FUNCTION 24
FUNCTION 25
FUNCTION 26
FUNCTION 27
FUNCTION 28
FUNCTION 29
FUNCTION 30
FUNCTION 31
// CHECK6: __Thumbv7ABSLongThunk_tfunc33:
// CHECK6-NEXT: 1000004: ff f0 fc bf b.w #1048568 <tfunc33>
// CHECK6: __Thumbv7ABSLongThunk_tfunc00:
// CHECK6-NEXT: 1000008: 7f f4 fa 97 b.w #-16252940 <tfunc00>
FUNCTION 32
FUNCTION 33
// We should be able to reach an existing ThunkSection.
b.w tfunc00
// CHECK7: tfunc33:
// CHECK7-NEXT: 1100000: 70 47 bx lr
// CHECK7-NEXT: 1100002: 00 f7 01 b8 b.w #-1048574 <__Thumbv7ABSLongThunk_tfunc00>
| {
"language": "Assembly"
} |
;11/28/83 ds
; memory access commands
; "-" must be 2nd char
mem lda cmdbuf+1
cmp #'-
bne memerr
;
lda cmdbuf+3 ; set address in temp
sta temp
lda cmdbuf+4
sta temp+1
;
ldy #0
lda cmdbuf+2
cmp #'R
beq memrd ; read
cmp #'W
beq memwrt ; write
cmp #'E
bne memerr ; error
; execute
memex jmp (temp)
memrd
lda (temp),y
sta data
lda cmdsiz
cmp #6
bcc m30
;
ldx cmdbuf+5
dex
beq m30
txa
clc
adc temp
inc temp
sta lstchr+errchn
lda temp
sta cb+2
lda temp+1
sta cb+3
jmp ge20
m30
jsr fndrch
jmp ge15
memerr lda #badcmd ; bad command
jmp cmderr
memwrt ; write
m10 lda cmdbuf+6,y
sta (temp),y ; transfer from cmdbuf
iny
cpy cmdbuf+5 ; # of bytes to write
bcc m10
rts
| {
"language": "Assembly"
} |
# This file is generated from a similarly-named Perl script in the BoringSSL
# source tree. Do not edit by hand.
#if defined(__has_feature)
#if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM)
#define OPENSSL_NO_ASM
#endif
#endif
#if defined(__x86_64__) && !defined(OPENSSL_NO_ASM)
#if defined(BORINGSSL_PREFIX)
#include <boringssl_prefix_symbols_asm.h>
#endif
.text
.globl _sha256_block_data_order
.private_extern _sha256_block_data_order
.p2align 4
_sha256_block_data_order:
leaq _OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
andl $1073741824,%r9d
andl $268435968,%r10d
orl %r9d,%r10d
cmpl $1342177792,%r10d
je L$avx_shortcut
testl $512,%r10d
jnz L$ssse3_shortcut
movq %rsp,%rax
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
shlq $4,%rdx
subq $64+32,%rsp
leaq (%rsi,%rdx,4),%rdx
andq $-64,%rsp
movq %rdi,64+0(%rsp)
movq %rsi,64+8(%rsp)
movq %rdx,64+16(%rsp)
movq %rax,88(%rsp)
L$prologue:
movl 0(%rdi),%eax
movl 4(%rdi),%ebx
movl 8(%rdi),%ecx
movl 12(%rdi),%edx
movl 16(%rdi),%r8d
movl 20(%rdi),%r9d
movl 24(%rdi),%r10d
movl 28(%rdi),%r11d
jmp L$loop
.p2align 4
L$loop:
movl %ebx,%edi
leaq K256(%rip),%rbp
xorl %ecx,%edi
movl 0(%rsi),%r12d
movl %r8d,%r13d
movl %eax,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r9d,%r15d
xorl %r8d,%r13d
rorl $9,%r14d
xorl %r10d,%r15d
movl %r12d,0(%rsp)
xorl %eax,%r14d
andl %r8d,%r15d
rorl $5,%r13d
addl %r11d,%r12d
xorl %r10d,%r15d
rorl $11,%r14d
xorl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r15d
addl (%rbp),%r12d
xorl %eax,%r14d
xorl %ebx,%r15d
rorl $6,%r13d
movl %ebx,%r11d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r11d
addl %r12d,%edx
addl %r12d,%r11d
leaq 4(%rbp),%rbp
addl %r14d,%r11d
movl 4(%rsi),%r12d
movl %edx,%r13d
movl %r11d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r8d,%edi
xorl %edx,%r13d
rorl $9,%r14d
xorl %r9d,%edi
movl %r12d,4(%rsp)
xorl %r11d,%r14d
andl %edx,%edi
rorl $5,%r13d
addl %r10d,%r12d
xorl %r9d,%edi
rorl $11,%r14d
xorl %edx,%r13d
addl %edi,%r12d
movl %r11d,%edi
addl (%rbp),%r12d
xorl %r11d,%r14d
xorl %eax,%edi
rorl $6,%r13d
movl %eax,%r10d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r10d
addl %r12d,%ecx
addl %r12d,%r10d
leaq 4(%rbp),%rbp
addl %r14d,%r10d
movl 8(%rsi),%r12d
movl %ecx,%r13d
movl %r10d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %edx,%r15d
xorl %ecx,%r13d
rorl $9,%r14d
xorl %r8d,%r15d
movl %r12d,8(%rsp)
xorl %r10d,%r14d
andl %ecx,%r15d
rorl $5,%r13d
addl %r9d,%r12d
xorl %r8d,%r15d
rorl $11,%r14d
xorl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r15d
addl (%rbp),%r12d
xorl %r10d,%r14d
xorl %r11d,%r15d
rorl $6,%r13d
movl %r11d,%r9d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r9d
addl %r12d,%ebx
addl %r12d,%r9d
leaq 4(%rbp),%rbp
addl %r14d,%r9d
movl 12(%rsi),%r12d
movl %ebx,%r13d
movl %r9d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %ecx,%edi
xorl %ebx,%r13d
rorl $9,%r14d
xorl %edx,%edi
movl %r12d,12(%rsp)
xorl %r9d,%r14d
andl %ebx,%edi
rorl $5,%r13d
addl %r8d,%r12d
xorl %edx,%edi
rorl $11,%r14d
xorl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%edi
addl (%rbp),%r12d
xorl %r9d,%r14d
xorl %r10d,%edi
rorl $6,%r13d
movl %r10d,%r8d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r8d
addl %r12d,%eax
addl %r12d,%r8d
leaq 20(%rbp),%rbp
addl %r14d,%r8d
movl 16(%rsi),%r12d
movl %eax,%r13d
movl %r8d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %ebx,%r15d
xorl %eax,%r13d
rorl $9,%r14d
xorl %ecx,%r15d
movl %r12d,16(%rsp)
xorl %r8d,%r14d
andl %eax,%r15d
rorl $5,%r13d
addl %edx,%r12d
xorl %ecx,%r15d
rorl $11,%r14d
xorl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r15d
addl (%rbp),%r12d
xorl %r8d,%r14d
xorl %r9d,%r15d
rorl $6,%r13d
movl %r9d,%edx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%edx
addl %r12d,%r11d
addl %r12d,%edx
leaq 4(%rbp),%rbp
addl %r14d,%edx
movl 20(%rsi),%r12d
movl %r11d,%r13d
movl %edx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %eax,%edi
xorl %r11d,%r13d
rorl $9,%r14d
xorl %ebx,%edi
movl %r12d,20(%rsp)
xorl %edx,%r14d
andl %r11d,%edi
rorl $5,%r13d
addl %ecx,%r12d
xorl %ebx,%edi
rorl $11,%r14d
xorl %r11d,%r13d
addl %edi,%r12d
movl %edx,%edi
addl (%rbp),%r12d
xorl %edx,%r14d
xorl %r8d,%edi
rorl $6,%r13d
movl %r8d,%ecx
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%ecx
addl %r12d,%r10d
addl %r12d,%ecx
leaq 4(%rbp),%rbp
addl %r14d,%ecx
movl 24(%rsi),%r12d
movl %r10d,%r13d
movl %ecx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r11d,%r15d
xorl %r10d,%r13d
rorl $9,%r14d
xorl %eax,%r15d
movl %r12d,24(%rsp)
xorl %ecx,%r14d
andl %r10d,%r15d
rorl $5,%r13d
addl %ebx,%r12d
xorl %eax,%r15d
rorl $11,%r14d
xorl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r15d
addl (%rbp),%r12d
xorl %ecx,%r14d
xorl %edx,%r15d
rorl $6,%r13d
movl %edx,%ebx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%ebx
addl %r12d,%r9d
addl %r12d,%ebx
leaq 4(%rbp),%rbp
addl %r14d,%ebx
movl 28(%rsi),%r12d
movl %r9d,%r13d
movl %ebx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r10d,%edi
xorl %r9d,%r13d
rorl $9,%r14d
xorl %r11d,%edi
movl %r12d,28(%rsp)
xorl %ebx,%r14d
andl %r9d,%edi
rorl $5,%r13d
addl %eax,%r12d
xorl %r11d,%edi
rorl $11,%r14d
xorl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%edi
addl (%rbp),%r12d
xorl %ebx,%r14d
xorl %ecx,%edi
rorl $6,%r13d
movl %ecx,%eax
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%eax
addl %r12d,%r8d
addl %r12d,%eax
leaq 20(%rbp),%rbp
addl %r14d,%eax
movl 32(%rsi),%r12d
movl %r8d,%r13d
movl %eax,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r9d,%r15d
xorl %r8d,%r13d
rorl $9,%r14d
xorl %r10d,%r15d
movl %r12d,32(%rsp)
xorl %eax,%r14d
andl %r8d,%r15d
rorl $5,%r13d
addl %r11d,%r12d
xorl %r10d,%r15d
rorl $11,%r14d
xorl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r15d
addl (%rbp),%r12d
xorl %eax,%r14d
xorl %ebx,%r15d
rorl $6,%r13d
movl %ebx,%r11d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r11d
addl %r12d,%edx
addl %r12d,%r11d
leaq 4(%rbp),%rbp
addl %r14d,%r11d
movl 36(%rsi),%r12d
movl %edx,%r13d
movl %r11d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r8d,%edi
xorl %edx,%r13d
rorl $9,%r14d
xorl %r9d,%edi
movl %r12d,36(%rsp)
xorl %r11d,%r14d
andl %edx,%edi
rorl $5,%r13d
addl %r10d,%r12d
xorl %r9d,%edi
rorl $11,%r14d
xorl %edx,%r13d
addl %edi,%r12d
movl %r11d,%edi
addl (%rbp),%r12d
xorl %r11d,%r14d
xorl %eax,%edi
rorl $6,%r13d
movl %eax,%r10d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r10d
addl %r12d,%ecx
addl %r12d,%r10d
leaq 4(%rbp),%rbp
addl %r14d,%r10d
movl 40(%rsi),%r12d
movl %ecx,%r13d
movl %r10d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %edx,%r15d
xorl %ecx,%r13d
rorl $9,%r14d
xorl %r8d,%r15d
movl %r12d,40(%rsp)
xorl %r10d,%r14d
andl %ecx,%r15d
rorl $5,%r13d
addl %r9d,%r12d
xorl %r8d,%r15d
rorl $11,%r14d
xorl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r15d
addl (%rbp),%r12d
xorl %r10d,%r14d
xorl %r11d,%r15d
rorl $6,%r13d
movl %r11d,%r9d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r9d
addl %r12d,%ebx
addl %r12d,%r9d
leaq 4(%rbp),%rbp
addl %r14d,%r9d
movl 44(%rsi),%r12d
movl %ebx,%r13d
movl %r9d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %ecx,%edi
xorl %ebx,%r13d
rorl $9,%r14d
xorl %edx,%edi
movl %r12d,44(%rsp)
xorl %r9d,%r14d
andl %ebx,%edi
rorl $5,%r13d
addl %r8d,%r12d
xorl %edx,%edi
rorl $11,%r14d
xorl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%edi
addl (%rbp),%r12d
xorl %r9d,%r14d
xorl %r10d,%edi
rorl $6,%r13d
movl %r10d,%r8d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r8d
addl %r12d,%eax
addl %r12d,%r8d
leaq 20(%rbp),%rbp
addl %r14d,%r8d
movl 48(%rsi),%r12d
movl %eax,%r13d
movl %r8d,%r14d
bswapl %r12d
rorl $14,%r13d
movl %ebx,%r15d
xorl %eax,%r13d
rorl $9,%r14d
xorl %ecx,%r15d
movl %r12d,48(%rsp)
xorl %r8d,%r14d
andl %eax,%r15d
rorl $5,%r13d
addl %edx,%r12d
xorl %ecx,%r15d
rorl $11,%r14d
xorl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r15d
addl (%rbp),%r12d
xorl %r8d,%r14d
xorl %r9d,%r15d
rorl $6,%r13d
movl %r9d,%edx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%edx
addl %r12d,%r11d
addl %r12d,%edx
leaq 4(%rbp),%rbp
addl %r14d,%edx
movl 52(%rsi),%r12d
movl %r11d,%r13d
movl %edx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %eax,%edi
xorl %r11d,%r13d
rorl $9,%r14d
xorl %ebx,%edi
movl %r12d,52(%rsp)
xorl %edx,%r14d
andl %r11d,%edi
rorl $5,%r13d
addl %ecx,%r12d
xorl %ebx,%edi
rorl $11,%r14d
xorl %r11d,%r13d
addl %edi,%r12d
movl %edx,%edi
addl (%rbp),%r12d
xorl %edx,%r14d
xorl %r8d,%edi
rorl $6,%r13d
movl %r8d,%ecx
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%ecx
addl %r12d,%r10d
addl %r12d,%ecx
leaq 4(%rbp),%rbp
addl %r14d,%ecx
movl 56(%rsi),%r12d
movl %r10d,%r13d
movl %ecx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r11d,%r15d
xorl %r10d,%r13d
rorl $9,%r14d
xorl %eax,%r15d
movl %r12d,56(%rsp)
xorl %ecx,%r14d
andl %r10d,%r15d
rorl $5,%r13d
addl %ebx,%r12d
xorl %eax,%r15d
rorl $11,%r14d
xorl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r15d
addl (%rbp),%r12d
xorl %ecx,%r14d
xorl %edx,%r15d
rorl $6,%r13d
movl %edx,%ebx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%ebx
addl %r12d,%r9d
addl %r12d,%ebx
leaq 4(%rbp),%rbp
addl %r14d,%ebx
movl 60(%rsi),%r12d
movl %r9d,%r13d
movl %ebx,%r14d
bswapl %r12d
rorl $14,%r13d
movl %r10d,%edi
xorl %r9d,%r13d
rorl $9,%r14d
xorl %r11d,%edi
movl %r12d,60(%rsp)
xorl %ebx,%r14d
andl %r9d,%edi
rorl $5,%r13d
addl %eax,%r12d
xorl %r11d,%edi
rorl $11,%r14d
xorl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%edi
addl (%rbp),%r12d
xorl %ebx,%r14d
xorl %ecx,%edi
rorl $6,%r13d
movl %ecx,%eax
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%eax
addl %r12d,%r8d
addl %r12d,%eax
leaq 20(%rbp),%rbp
jmp L$rounds_16_xx
.p2align 4
L$rounds_16_xx:
movl 4(%rsp),%r13d
movl 56(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%eax
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 36(%rsp),%r12d
addl 0(%rsp),%r12d
movl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r14d
rorl $14,%r13d
movl %r9d,%r15d
xorl %r8d,%r13d
rorl $9,%r14d
xorl %r10d,%r15d
movl %r12d,0(%rsp)
xorl %eax,%r14d
andl %r8d,%r15d
rorl $5,%r13d
addl %r11d,%r12d
xorl %r10d,%r15d
rorl $11,%r14d
xorl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r15d
addl (%rbp),%r12d
xorl %eax,%r14d
xorl %ebx,%r15d
rorl $6,%r13d
movl %ebx,%r11d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r11d
addl %r12d,%edx
addl %r12d,%r11d
leaq 4(%rbp),%rbp
movl 8(%rsp),%r13d
movl 60(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r11d
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 40(%rsp),%r12d
addl 4(%rsp),%r12d
movl %edx,%r13d
addl %edi,%r12d
movl %r11d,%r14d
rorl $14,%r13d
movl %r8d,%edi
xorl %edx,%r13d
rorl $9,%r14d
xorl %r9d,%edi
movl %r12d,4(%rsp)
xorl %r11d,%r14d
andl %edx,%edi
rorl $5,%r13d
addl %r10d,%r12d
xorl %r9d,%edi
rorl $11,%r14d
xorl %edx,%r13d
addl %edi,%r12d
movl %r11d,%edi
addl (%rbp),%r12d
xorl %r11d,%r14d
xorl %eax,%edi
rorl $6,%r13d
movl %eax,%r10d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r10d
addl %r12d,%ecx
addl %r12d,%r10d
leaq 4(%rbp),%rbp
movl 12(%rsp),%r13d
movl 0(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r10d
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 44(%rsp),%r12d
addl 8(%rsp),%r12d
movl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r14d
rorl $14,%r13d
movl %edx,%r15d
xorl %ecx,%r13d
rorl $9,%r14d
xorl %r8d,%r15d
movl %r12d,8(%rsp)
xorl %r10d,%r14d
andl %ecx,%r15d
rorl $5,%r13d
addl %r9d,%r12d
xorl %r8d,%r15d
rorl $11,%r14d
xorl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r15d
addl (%rbp),%r12d
xorl %r10d,%r14d
xorl %r11d,%r15d
rorl $6,%r13d
movl %r11d,%r9d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r9d
addl %r12d,%ebx
addl %r12d,%r9d
leaq 4(%rbp),%rbp
movl 16(%rsp),%r13d
movl 4(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r9d
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 48(%rsp),%r12d
addl 12(%rsp),%r12d
movl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%r14d
rorl $14,%r13d
movl %ecx,%edi
xorl %ebx,%r13d
rorl $9,%r14d
xorl %edx,%edi
movl %r12d,12(%rsp)
xorl %r9d,%r14d
andl %ebx,%edi
rorl $5,%r13d
addl %r8d,%r12d
xorl %edx,%edi
rorl $11,%r14d
xorl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%edi
addl (%rbp),%r12d
xorl %r9d,%r14d
xorl %r10d,%edi
rorl $6,%r13d
movl %r10d,%r8d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r8d
addl %r12d,%eax
addl %r12d,%r8d
leaq 20(%rbp),%rbp
movl 20(%rsp),%r13d
movl 8(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r8d
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 52(%rsp),%r12d
addl 16(%rsp),%r12d
movl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r14d
rorl $14,%r13d
movl %ebx,%r15d
xorl %eax,%r13d
rorl $9,%r14d
xorl %ecx,%r15d
movl %r12d,16(%rsp)
xorl %r8d,%r14d
andl %eax,%r15d
rorl $5,%r13d
addl %edx,%r12d
xorl %ecx,%r15d
rorl $11,%r14d
xorl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r15d
addl (%rbp),%r12d
xorl %r8d,%r14d
xorl %r9d,%r15d
rorl $6,%r13d
movl %r9d,%edx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%edx
addl %r12d,%r11d
addl %r12d,%edx
leaq 4(%rbp),%rbp
movl 24(%rsp),%r13d
movl 12(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%edx
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 56(%rsp),%r12d
addl 20(%rsp),%r12d
movl %r11d,%r13d
addl %edi,%r12d
movl %edx,%r14d
rorl $14,%r13d
movl %eax,%edi
xorl %r11d,%r13d
rorl $9,%r14d
xorl %ebx,%edi
movl %r12d,20(%rsp)
xorl %edx,%r14d
andl %r11d,%edi
rorl $5,%r13d
addl %ecx,%r12d
xorl %ebx,%edi
rorl $11,%r14d
xorl %r11d,%r13d
addl %edi,%r12d
movl %edx,%edi
addl (%rbp),%r12d
xorl %edx,%r14d
xorl %r8d,%edi
rorl $6,%r13d
movl %r8d,%ecx
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%ecx
addl %r12d,%r10d
addl %r12d,%ecx
leaq 4(%rbp),%rbp
movl 28(%rsp),%r13d
movl 16(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%ecx
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 60(%rsp),%r12d
addl 24(%rsp),%r12d
movl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r14d
rorl $14,%r13d
movl %r11d,%r15d
xorl %r10d,%r13d
rorl $9,%r14d
xorl %eax,%r15d
movl %r12d,24(%rsp)
xorl %ecx,%r14d
andl %r10d,%r15d
rorl $5,%r13d
addl %ebx,%r12d
xorl %eax,%r15d
rorl $11,%r14d
xorl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r15d
addl (%rbp),%r12d
xorl %ecx,%r14d
xorl %edx,%r15d
rorl $6,%r13d
movl %edx,%ebx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%ebx
addl %r12d,%r9d
addl %r12d,%ebx
leaq 4(%rbp),%rbp
movl 32(%rsp),%r13d
movl 20(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%ebx
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 0(%rsp),%r12d
addl 28(%rsp),%r12d
movl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%r14d
rorl $14,%r13d
movl %r10d,%edi
xorl %r9d,%r13d
rorl $9,%r14d
xorl %r11d,%edi
movl %r12d,28(%rsp)
xorl %ebx,%r14d
andl %r9d,%edi
rorl $5,%r13d
addl %eax,%r12d
xorl %r11d,%edi
rorl $11,%r14d
xorl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%edi
addl (%rbp),%r12d
xorl %ebx,%r14d
xorl %ecx,%edi
rorl $6,%r13d
movl %ecx,%eax
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%eax
addl %r12d,%r8d
addl %r12d,%eax
leaq 20(%rbp),%rbp
movl 36(%rsp),%r13d
movl 24(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%eax
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 4(%rsp),%r12d
addl 32(%rsp),%r12d
movl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r14d
rorl $14,%r13d
movl %r9d,%r15d
xorl %r8d,%r13d
rorl $9,%r14d
xorl %r10d,%r15d
movl %r12d,32(%rsp)
xorl %eax,%r14d
andl %r8d,%r15d
rorl $5,%r13d
addl %r11d,%r12d
xorl %r10d,%r15d
rorl $11,%r14d
xorl %r8d,%r13d
addl %r15d,%r12d
movl %eax,%r15d
addl (%rbp),%r12d
xorl %eax,%r14d
xorl %ebx,%r15d
rorl $6,%r13d
movl %ebx,%r11d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r11d
addl %r12d,%edx
addl %r12d,%r11d
leaq 4(%rbp),%rbp
movl 40(%rsp),%r13d
movl 28(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r11d
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 8(%rsp),%r12d
addl 36(%rsp),%r12d
movl %edx,%r13d
addl %edi,%r12d
movl %r11d,%r14d
rorl $14,%r13d
movl %r8d,%edi
xorl %edx,%r13d
rorl $9,%r14d
xorl %r9d,%edi
movl %r12d,36(%rsp)
xorl %r11d,%r14d
andl %edx,%edi
rorl $5,%r13d
addl %r10d,%r12d
xorl %r9d,%edi
rorl $11,%r14d
xorl %edx,%r13d
addl %edi,%r12d
movl %r11d,%edi
addl (%rbp),%r12d
xorl %r11d,%r14d
xorl %eax,%edi
rorl $6,%r13d
movl %eax,%r10d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r10d
addl %r12d,%ecx
addl %r12d,%r10d
leaq 4(%rbp),%rbp
movl 44(%rsp),%r13d
movl 32(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r10d
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 12(%rsp),%r12d
addl 40(%rsp),%r12d
movl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r14d
rorl $14,%r13d
movl %edx,%r15d
xorl %ecx,%r13d
rorl $9,%r14d
xorl %r8d,%r15d
movl %r12d,40(%rsp)
xorl %r10d,%r14d
andl %ecx,%r15d
rorl $5,%r13d
addl %r9d,%r12d
xorl %r8d,%r15d
rorl $11,%r14d
xorl %ecx,%r13d
addl %r15d,%r12d
movl %r10d,%r15d
addl (%rbp),%r12d
xorl %r10d,%r14d
xorl %r11d,%r15d
rorl $6,%r13d
movl %r11d,%r9d
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%r9d
addl %r12d,%ebx
addl %r12d,%r9d
leaq 4(%rbp),%rbp
movl 48(%rsp),%r13d
movl 36(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r9d
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 16(%rsp),%r12d
addl 44(%rsp),%r12d
movl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%r14d
rorl $14,%r13d
movl %ecx,%edi
xorl %ebx,%r13d
rorl $9,%r14d
xorl %edx,%edi
movl %r12d,44(%rsp)
xorl %r9d,%r14d
andl %ebx,%edi
rorl $5,%r13d
addl %r8d,%r12d
xorl %edx,%edi
rorl $11,%r14d
xorl %ebx,%r13d
addl %edi,%r12d
movl %r9d,%edi
addl (%rbp),%r12d
xorl %r9d,%r14d
xorl %r10d,%edi
rorl $6,%r13d
movl %r10d,%r8d
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%r8d
addl %r12d,%eax
addl %r12d,%r8d
leaq 20(%rbp),%rbp
movl 52(%rsp),%r13d
movl 40(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%r8d
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 20(%rsp),%r12d
addl 48(%rsp),%r12d
movl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r14d
rorl $14,%r13d
movl %ebx,%r15d
xorl %eax,%r13d
rorl $9,%r14d
xorl %ecx,%r15d
movl %r12d,48(%rsp)
xorl %r8d,%r14d
andl %eax,%r15d
rorl $5,%r13d
addl %edx,%r12d
xorl %ecx,%r15d
rorl $11,%r14d
xorl %eax,%r13d
addl %r15d,%r12d
movl %r8d,%r15d
addl (%rbp),%r12d
xorl %r8d,%r14d
xorl %r9d,%r15d
rorl $6,%r13d
movl %r9d,%edx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%edx
addl %r12d,%r11d
addl %r12d,%edx
leaq 4(%rbp),%rbp
movl 56(%rsp),%r13d
movl 44(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%edx
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 24(%rsp),%r12d
addl 52(%rsp),%r12d
movl %r11d,%r13d
addl %edi,%r12d
movl %edx,%r14d
rorl $14,%r13d
movl %eax,%edi
xorl %r11d,%r13d
rorl $9,%r14d
xorl %ebx,%edi
movl %r12d,52(%rsp)
xorl %edx,%r14d
andl %r11d,%edi
rorl $5,%r13d
addl %ecx,%r12d
xorl %ebx,%edi
rorl $11,%r14d
xorl %r11d,%r13d
addl %edi,%r12d
movl %edx,%edi
addl (%rbp),%r12d
xorl %edx,%r14d
xorl %r8d,%edi
rorl $6,%r13d
movl %r8d,%ecx
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%ecx
addl %r12d,%r10d
addl %r12d,%ecx
leaq 4(%rbp),%rbp
movl 60(%rsp),%r13d
movl 48(%rsp),%r15d
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%ecx
movl %r15d,%r14d
rorl $2,%r15d
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%r15d
shrl $10,%r14d
rorl $17,%r15d
xorl %r13d,%r12d
xorl %r14d,%r15d
addl 28(%rsp),%r12d
addl 56(%rsp),%r12d
movl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r14d
rorl $14,%r13d
movl %r11d,%r15d
xorl %r10d,%r13d
rorl $9,%r14d
xorl %eax,%r15d
movl %r12d,56(%rsp)
xorl %ecx,%r14d
andl %r10d,%r15d
rorl $5,%r13d
addl %ebx,%r12d
xorl %eax,%r15d
rorl $11,%r14d
xorl %r10d,%r13d
addl %r15d,%r12d
movl %ecx,%r15d
addl (%rbp),%r12d
xorl %ecx,%r14d
xorl %edx,%r15d
rorl $6,%r13d
movl %edx,%ebx
andl %r15d,%edi
rorl $2,%r14d
addl %r13d,%r12d
xorl %edi,%ebx
addl %r12d,%r9d
addl %r12d,%ebx
leaq 4(%rbp),%rbp
movl 0(%rsp),%r13d
movl 52(%rsp),%edi
movl %r13d,%r12d
rorl $11,%r13d
addl %r14d,%ebx
movl %edi,%r14d
rorl $2,%edi
xorl %r12d,%r13d
shrl $3,%r12d
rorl $7,%r13d
xorl %r14d,%edi
shrl $10,%r14d
rorl $17,%edi
xorl %r13d,%r12d
xorl %r14d,%edi
addl 32(%rsp),%r12d
addl 60(%rsp),%r12d
movl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%r14d
rorl $14,%r13d
movl %r10d,%edi
xorl %r9d,%r13d
rorl $9,%r14d
xorl %r11d,%edi
movl %r12d,60(%rsp)
xorl %ebx,%r14d
andl %r9d,%edi
rorl $5,%r13d
addl %eax,%r12d
xorl %r11d,%edi
rorl $11,%r14d
xorl %r9d,%r13d
addl %edi,%r12d
movl %ebx,%edi
addl (%rbp),%r12d
xorl %ebx,%r14d
xorl %ecx,%edi
rorl $6,%r13d
movl %ecx,%eax
andl %edi,%r15d
rorl $2,%r14d
addl %r13d,%r12d
xorl %r15d,%eax
addl %r12d,%r8d
addl %r12d,%eax
leaq 20(%rbp),%rbp
cmpb $0,3(%rbp)
jnz L$rounds_16_xx
movq 64+0(%rsp),%rdi
addl %r14d,%eax
leaq 64(%rsi),%rsi
addl 0(%rdi),%eax
addl 4(%rdi),%ebx
addl 8(%rdi),%ecx
addl 12(%rdi),%edx
addl 16(%rdi),%r8d
addl 20(%rdi),%r9d
addl 24(%rdi),%r10d
addl 28(%rdi),%r11d
cmpq 64+16(%rsp),%rsi
movl %eax,0(%rdi)
movl %ebx,4(%rdi)
movl %ecx,8(%rdi)
movl %edx,12(%rdi)
movl %r8d,16(%rdi)
movl %r9d,20(%rdi)
movl %r10d,24(%rdi)
movl %r11d,28(%rdi)
jb L$loop
movq 88(%rsp),%rsi
movq -48(%rsi),%r15
movq -40(%rsi),%r14
movq -32(%rsi),%r13
movq -24(%rsi),%r12
movq -16(%rsi),%rbp
movq -8(%rsi),%rbx
leaq (%rsi),%rsp
L$epilogue:
.byte 0xf3,0xc3
.p2align 6
K256:
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
.long 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
.long 0x00010203,0x04050607,0x08090a0b,0x0c0d0e0f
.long 0x03020100,0x0b0a0908,0xffffffff,0xffffffff
.long 0x03020100,0x0b0a0908,0xffffffff,0xffffffff
.long 0xffffffff,0xffffffff,0x03020100,0x0b0a0908
.long 0xffffffff,0xffffffff,0x03020100,0x0b0a0908
.byte 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
.p2align 6
sha256_block_data_order_ssse3:
L$ssse3_shortcut:
movq %rsp,%rax
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
shlq $4,%rdx
subq $96,%rsp
leaq (%rsi,%rdx,4),%rdx
andq $-64,%rsp
movq %rdi,64+0(%rsp)
movq %rsi,64+8(%rsp)
movq %rdx,64+16(%rsp)
movq %rax,88(%rsp)
L$prologue_ssse3:
movl 0(%rdi),%eax
movl 4(%rdi),%ebx
movl 8(%rdi),%ecx
movl 12(%rdi),%edx
movl 16(%rdi),%r8d
movl 20(%rdi),%r9d
movl 24(%rdi),%r10d
movl 28(%rdi),%r11d
jmp L$loop_ssse3
.p2align 4
L$loop_ssse3:
movdqa K256+512(%rip),%xmm7
movdqu 0(%rsi),%xmm0
movdqu 16(%rsi),%xmm1
movdqu 32(%rsi),%xmm2
.byte 102,15,56,0,199
movdqu 48(%rsi),%xmm3
leaq K256(%rip),%rbp
.byte 102,15,56,0,207
movdqa 0(%rbp),%xmm4
movdqa 32(%rbp),%xmm5
.byte 102,15,56,0,215
paddd %xmm0,%xmm4
movdqa 64(%rbp),%xmm6
.byte 102,15,56,0,223
movdqa 96(%rbp),%xmm7
paddd %xmm1,%xmm5
paddd %xmm2,%xmm6
paddd %xmm3,%xmm7
movdqa %xmm4,0(%rsp)
movl %eax,%r14d
movdqa %xmm5,16(%rsp)
movl %ebx,%edi
movdqa %xmm6,32(%rsp)
xorl %ecx,%edi
movdqa %xmm7,48(%rsp)
movl %r8d,%r13d
jmp L$ssse3_00_47
.p2align 4
L$ssse3_00_47:
subq $-128,%rbp
rorl $14,%r13d
movdqa %xmm1,%xmm4
movl %r14d,%eax
movl %r9d,%r12d
movdqa %xmm3,%xmm7
rorl $9,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
rorl $5,%r13d
xorl %eax,%r14d
.byte 102,15,58,15,224,4
andl %r8d,%r12d
xorl %r8d,%r13d
.byte 102,15,58,15,250,4
addl 0(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
rorl $11,%r14d
movdqa %xmm4,%xmm5
xorl %ebx,%r15d
addl %r12d,%r11d
movdqa %xmm4,%xmm6
rorl $6,%r13d
andl %r15d,%edi
psrld $3,%xmm4
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
paddd %xmm7,%xmm0
rorl $2,%r14d
addl %r11d,%edx
psrld $7,%xmm6
addl %edi,%r11d
movl %edx,%r13d
pshufd $250,%xmm3,%xmm7
addl %r11d,%r14d
rorl $14,%r13d
pslld $14,%xmm5
movl %r14d,%r11d
movl %r8d,%r12d
pxor %xmm6,%xmm4
rorl $9,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
rorl $5,%r13d
psrld $11,%xmm6
xorl %r11d,%r14d
pxor %xmm5,%xmm4
andl %edx,%r12d
xorl %edx,%r13d
pslld $11,%xmm5
addl 4(%rsp),%r10d
movl %r11d,%edi
pxor %xmm6,%xmm4
xorl %r9d,%r12d
rorl $11,%r14d
movdqa %xmm7,%xmm6
xorl %eax,%edi
addl %r12d,%r10d
pxor %xmm5,%xmm4
rorl $6,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
psrld $10,%xmm7
addl %r13d,%r10d
xorl %eax,%r15d
paddd %xmm4,%xmm0
rorl $2,%r14d
addl %r10d,%ecx
psrlq $17,%xmm6
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
pxor %xmm6,%xmm7
rorl $14,%r13d
movl %r14d,%r10d
movl %edx,%r12d
rorl $9,%r14d
psrlq $2,%xmm6
xorl %ecx,%r13d
xorl %r8d,%r12d
pxor %xmm6,%xmm7
rorl $5,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
pshufd $128,%xmm7,%xmm7
xorl %ecx,%r13d
addl 8(%rsp),%r9d
movl %r10d,%r15d
psrldq $8,%xmm7
xorl %r8d,%r12d
rorl $11,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
rorl $6,%r13d
paddd %xmm7,%xmm0
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
pshufd $80,%xmm0,%xmm7
xorl %r11d,%edi
rorl $2,%r14d
addl %r9d,%ebx
movdqa %xmm7,%xmm6
addl %edi,%r9d
movl %ebx,%r13d
psrld $10,%xmm7
addl %r9d,%r14d
rorl $14,%r13d
psrlq $17,%xmm6
movl %r14d,%r9d
movl %ecx,%r12d
pxor %xmm6,%xmm7
rorl $9,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
rorl $5,%r13d
xorl %r9d,%r14d
psrlq $2,%xmm6
andl %ebx,%r12d
xorl %ebx,%r13d
addl 12(%rsp),%r8d
pxor %xmm6,%xmm7
movl %r9d,%edi
xorl %edx,%r12d
rorl $11,%r14d
pshufd $8,%xmm7,%xmm7
xorl %r10d,%edi
addl %r12d,%r8d
movdqa 0(%rbp),%xmm6
rorl $6,%r13d
andl %edi,%r15d
pslldq $8,%xmm7
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
paddd %xmm7,%xmm0
rorl $2,%r14d
addl %r8d,%eax
addl %r15d,%r8d
paddd %xmm0,%xmm6
movl %eax,%r13d
addl %r8d,%r14d
movdqa %xmm6,0(%rsp)
rorl $14,%r13d
movdqa %xmm2,%xmm4
movl %r14d,%r8d
movl %ebx,%r12d
movdqa %xmm0,%xmm7
rorl $9,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
rorl $5,%r13d
xorl %r8d,%r14d
.byte 102,15,58,15,225,4
andl %eax,%r12d
xorl %eax,%r13d
.byte 102,15,58,15,251,4
addl 16(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
rorl $11,%r14d
movdqa %xmm4,%xmm5
xorl %r9d,%r15d
addl %r12d,%edx
movdqa %xmm4,%xmm6
rorl $6,%r13d
andl %r15d,%edi
psrld $3,%xmm4
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
paddd %xmm7,%xmm1
rorl $2,%r14d
addl %edx,%r11d
psrld $7,%xmm6
addl %edi,%edx
movl %r11d,%r13d
pshufd $250,%xmm0,%xmm7
addl %edx,%r14d
rorl $14,%r13d
pslld $14,%xmm5
movl %r14d,%edx
movl %eax,%r12d
pxor %xmm6,%xmm4
rorl $9,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
rorl $5,%r13d
psrld $11,%xmm6
xorl %edx,%r14d
pxor %xmm5,%xmm4
andl %r11d,%r12d
xorl %r11d,%r13d
pslld $11,%xmm5
addl 20(%rsp),%ecx
movl %edx,%edi
pxor %xmm6,%xmm4
xorl %ebx,%r12d
rorl $11,%r14d
movdqa %xmm7,%xmm6
xorl %r8d,%edi
addl %r12d,%ecx
pxor %xmm5,%xmm4
rorl $6,%r13d
andl %edi,%r15d
xorl %edx,%r14d
psrld $10,%xmm7
addl %r13d,%ecx
xorl %r8d,%r15d
paddd %xmm4,%xmm1
rorl $2,%r14d
addl %ecx,%r10d
psrlq $17,%xmm6
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
pxor %xmm6,%xmm7
rorl $14,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
rorl $9,%r14d
psrlq $2,%xmm6
xorl %r10d,%r13d
xorl %eax,%r12d
pxor %xmm6,%xmm7
rorl $5,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
pshufd $128,%xmm7,%xmm7
xorl %r10d,%r13d
addl 24(%rsp),%ebx
movl %ecx,%r15d
psrldq $8,%xmm7
xorl %eax,%r12d
rorl $11,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
rorl $6,%r13d
paddd %xmm7,%xmm1
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
pshufd $80,%xmm1,%xmm7
xorl %edx,%edi
rorl $2,%r14d
addl %ebx,%r9d
movdqa %xmm7,%xmm6
addl %edi,%ebx
movl %r9d,%r13d
psrld $10,%xmm7
addl %ebx,%r14d
rorl $14,%r13d
psrlq $17,%xmm6
movl %r14d,%ebx
movl %r10d,%r12d
pxor %xmm6,%xmm7
rorl $9,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
rorl $5,%r13d
xorl %ebx,%r14d
psrlq $2,%xmm6
andl %r9d,%r12d
xorl %r9d,%r13d
addl 28(%rsp),%eax
pxor %xmm6,%xmm7
movl %ebx,%edi
xorl %r11d,%r12d
rorl $11,%r14d
pshufd $8,%xmm7,%xmm7
xorl %ecx,%edi
addl %r12d,%eax
movdqa 32(%rbp),%xmm6
rorl $6,%r13d
andl %edi,%r15d
pslldq $8,%xmm7
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
paddd %xmm7,%xmm1
rorl $2,%r14d
addl %eax,%r8d
addl %r15d,%eax
paddd %xmm1,%xmm6
movl %r8d,%r13d
addl %eax,%r14d
movdqa %xmm6,16(%rsp)
rorl $14,%r13d
movdqa %xmm3,%xmm4
movl %r14d,%eax
movl %r9d,%r12d
movdqa %xmm1,%xmm7
rorl $9,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
rorl $5,%r13d
xorl %eax,%r14d
.byte 102,15,58,15,226,4
andl %r8d,%r12d
xorl %r8d,%r13d
.byte 102,15,58,15,248,4
addl 32(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
rorl $11,%r14d
movdqa %xmm4,%xmm5
xorl %ebx,%r15d
addl %r12d,%r11d
movdqa %xmm4,%xmm6
rorl $6,%r13d
andl %r15d,%edi
psrld $3,%xmm4
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
paddd %xmm7,%xmm2
rorl $2,%r14d
addl %r11d,%edx
psrld $7,%xmm6
addl %edi,%r11d
movl %edx,%r13d
pshufd $250,%xmm1,%xmm7
addl %r11d,%r14d
rorl $14,%r13d
pslld $14,%xmm5
movl %r14d,%r11d
movl %r8d,%r12d
pxor %xmm6,%xmm4
rorl $9,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
rorl $5,%r13d
psrld $11,%xmm6
xorl %r11d,%r14d
pxor %xmm5,%xmm4
andl %edx,%r12d
xorl %edx,%r13d
pslld $11,%xmm5
addl 36(%rsp),%r10d
movl %r11d,%edi
pxor %xmm6,%xmm4
xorl %r9d,%r12d
rorl $11,%r14d
movdqa %xmm7,%xmm6
xorl %eax,%edi
addl %r12d,%r10d
pxor %xmm5,%xmm4
rorl $6,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
psrld $10,%xmm7
addl %r13d,%r10d
xorl %eax,%r15d
paddd %xmm4,%xmm2
rorl $2,%r14d
addl %r10d,%ecx
psrlq $17,%xmm6
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
pxor %xmm6,%xmm7
rorl $14,%r13d
movl %r14d,%r10d
movl %edx,%r12d
rorl $9,%r14d
psrlq $2,%xmm6
xorl %ecx,%r13d
xorl %r8d,%r12d
pxor %xmm6,%xmm7
rorl $5,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
pshufd $128,%xmm7,%xmm7
xorl %ecx,%r13d
addl 40(%rsp),%r9d
movl %r10d,%r15d
psrldq $8,%xmm7
xorl %r8d,%r12d
rorl $11,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
rorl $6,%r13d
paddd %xmm7,%xmm2
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
pshufd $80,%xmm2,%xmm7
xorl %r11d,%edi
rorl $2,%r14d
addl %r9d,%ebx
movdqa %xmm7,%xmm6
addl %edi,%r9d
movl %ebx,%r13d
psrld $10,%xmm7
addl %r9d,%r14d
rorl $14,%r13d
psrlq $17,%xmm6
movl %r14d,%r9d
movl %ecx,%r12d
pxor %xmm6,%xmm7
rorl $9,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
rorl $5,%r13d
xorl %r9d,%r14d
psrlq $2,%xmm6
andl %ebx,%r12d
xorl %ebx,%r13d
addl 44(%rsp),%r8d
pxor %xmm6,%xmm7
movl %r9d,%edi
xorl %edx,%r12d
rorl $11,%r14d
pshufd $8,%xmm7,%xmm7
xorl %r10d,%edi
addl %r12d,%r8d
movdqa 64(%rbp),%xmm6
rorl $6,%r13d
andl %edi,%r15d
pslldq $8,%xmm7
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
paddd %xmm7,%xmm2
rorl $2,%r14d
addl %r8d,%eax
addl %r15d,%r8d
paddd %xmm2,%xmm6
movl %eax,%r13d
addl %r8d,%r14d
movdqa %xmm6,32(%rsp)
rorl $14,%r13d
movdqa %xmm0,%xmm4
movl %r14d,%r8d
movl %ebx,%r12d
movdqa %xmm2,%xmm7
rorl $9,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
rorl $5,%r13d
xorl %r8d,%r14d
.byte 102,15,58,15,227,4
andl %eax,%r12d
xorl %eax,%r13d
.byte 102,15,58,15,249,4
addl 48(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
rorl $11,%r14d
movdqa %xmm4,%xmm5
xorl %r9d,%r15d
addl %r12d,%edx
movdqa %xmm4,%xmm6
rorl $6,%r13d
andl %r15d,%edi
psrld $3,%xmm4
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
paddd %xmm7,%xmm3
rorl $2,%r14d
addl %edx,%r11d
psrld $7,%xmm6
addl %edi,%edx
movl %r11d,%r13d
pshufd $250,%xmm2,%xmm7
addl %edx,%r14d
rorl $14,%r13d
pslld $14,%xmm5
movl %r14d,%edx
movl %eax,%r12d
pxor %xmm6,%xmm4
rorl $9,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
rorl $5,%r13d
psrld $11,%xmm6
xorl %edx,%r14d
pxor %xmm5,%xmm4
andl %r11d,%r12d
xorl %r11d,%r13d
pslld $11,%xmm5
addl 52(%rsp),%ecx
movl %edx,%edi
pxor %xmm6,%xmm4
xorl %ebx,%r12d
rorl $11,%r14d
movdqa %xmm7,%xmm6
xorl %r8d,%edi
addl %r12d,%ecx
pxor %xmm5,%xmm4
rorl $6,%r13d
andl %edi,%r15d
xorl %edx,%r14d
psrld $10,%xmm7
addl %r13d,%ecx
xorl %r8d,%r15d
paddd %xmm4,%xmm3
rorl $2,%r14d
addl %ecx,%r10d
psrlq $17,%xmm6
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
pxor %xmm6,%xmm7
rorl $14,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
rorl $9,%r14d
psrlq $2,%xmm6
xorl %r10d,%r13d
xorl %eax,%r12d
pxor %xmm6,%xmm7
rorl $5,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
pshufd $128,%xmm7,%xmm7
xorl %r10d,%r13d
addl 56(%rsp),%ebx
movl %ecx,%r15d
psrldq $8,%xmm7
xorl %eax,%r12d
rorl $11,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
rorl $6,%r13d
paddd %xmm7,%xmm3
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
pshufd $80,%xmm3,%xmm7
xorl %edx,%edi
rorl $2,%r14d
addl %ebx,%r9d
movdqa %xmm7,%xmm6
addl %edi,%ebx
movl %r9d,%r13d
psrld $10,%xmm7
addl %ebx,%r14d
rorl $14,%r13d
psrlq $17,%xmm6
movl %r14d,%ebx
movl %r10d,%r12d
pxor %xmm6,%xmm7
rorl $9,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
rorl $5,%r13d
xorl %ebx,%r14d
psrlq $2,%xmm6
andl %r9d,%r12d
xorl %r9d,%r13d
addl 60(%rsp),%eax
pxor %xmm6,%xmm7
movl %ebx,%edi
xorl %r11d,%r12d
rorl $11,%r14d
pshufd $8,%xmm7,%xmm7
xorl %ecx,%edi
addl %r12d,%eax
movdqa 96(%rbp),%xmm6
rorl $6,%r13d
andl %edi,%r15d
pslldq $8,%xmm7
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
paddd %xmm7,%xmm3
rorl $2,%r14d
addl %eax,%r8d
addl %r15d,%eax
paddd %xmm3,%xmm6
movl %r8d,%r13d
addl %eax,%r14d
movdqa %xmm6,48(%rsp)
cmpb $0,131(%rbp)
jne L$ssse3_00_47
rorl $14,%r13d
movl %r14d,%eax
movl %r9d,%r12d
rorl $9,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
rorl $5,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
xorl %r8d,%r13d
addl 0(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
rorl $11,%r14d
xorl %ebx,%r15d
addl %r12d,%r11d
rorl $6,%r13d
andl %r15d,%edi
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
rorl $2,%r14d
addl %r11d,%edx
addl %edi,%r11d
movl %edx,%r13d
addl %r11d,%r14d
rorl $14,%r13d
movl %r14d,%r11d
movl %r8d,%r12d
rorl $9,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
rorl $5,%r13d
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
addl 4(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
rorl $11,%r14d
xorl %eax,%edi
addl %r12d,%r10d
rorl $6,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
addl %r13d,%r10d
xorl %eax,%r15d
rorl $2,%r14d
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
rorl $14,%r13d
movl %r14d,%r10d
movl %edx,%r12d
rorl $9,%r14d
xorl %ecx,%r13d
xorl %r8d,%r12d
rorl $5,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
xorl %ecx,%r13d
addl 8(%rsp),%r9d
movl %r10d,%r15d
xorl %r8d,%r12d
rorl $11,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
rorl $6,%r13d
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
xorl %r11d,%edi
rorl $2,%r14d
addl %r9d,%ebx
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
rorl $14,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
rorl $9,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
rorl $5,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
xorl %ebx,%r13d
addl 12(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
rorl $11,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
rorl $6,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
rorl $2,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
rorl $14,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
rorl $9,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
rorl $5,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
xorl %eax,%r13d
addl 16(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
rorl $11,%r14d
xorl %r9d,%r15d
addl %r12d,%edx
rorl $6,%r13d
andl %r15d,%edi
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
rorl $2,%r14d
addl %edx,%r11d
addl %edi,%edx
movl %r11d,%r13d
addl %edx,%r14d
rorl $14,%r13d
movl %r14d,%edx
movl %eax,%r12d
rorl $9,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
rorl $5,%r13d
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
addl 20(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
rorl $11,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
rorl $6,%r13d
andl %edi,%r15d
xorl %edx,%r14d
addl %r13d,%ecx
xorl %r8d,%r15d
rorl $2,%r14d
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
rorl $14,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
rorl $9,%r14d
xorl %r10d,%r13d
xorl %eax,%r12d
rorl $5,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
xorl %r10d,%r13d
addl 24(%rsp),%ebx
movl %ecx,%r15d
xorl %eax,%r12d
rorl $11,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
rorl $6,%r13d
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
xorl %edx,%edi
rorl $2,%r14d
addl %ebx,%r9d
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
rorl $14,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
rorl $9,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
rorl $5,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
xorl %r9d,%r13d
addl 28(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
rorl $11,%r14d
xorl %ecx,%edi
addl %r12d,%eax
rorl $6,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
rorl $2,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
rorl $14,%r13d
movl %r14d,%eax
movl %r9d,%r12d
rorl $9,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
rorl $5,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
xorl %r8d,%r13d
addl 32(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
rorl $11,%r14d
xorl %ebx,%r15d
addl %r12d,%r11d
rorl $6,%r13d
andl %r15d,%edi
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
rorl $2,%r14d
addl %r11d,%edx
addl %edi,%r11d
movl %edx,%r13d
addl %r11d,%r14d
rorl $14,%r13d
movl %r14d,%r11d
movl %r8d,%r12d
rorl $9,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
rorl $5,%r13d
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
addl 36(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
rorl $11,%r14d
xorl %eax,%edi
addl %r12d,%r10d
rorl $6,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
addl %r13d,%r10d
xorl %eax,%r15d
rorl $2,%r14d
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
rorl $14,%r13d
movl %r14d,%r10d
movl %edx,%r12d
rorl $9,%r14d
xorl %ecx,%r13d
xorl %r8d,%r12d
rorl $5,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
xorl %ecx,%r13d
addl 40(%rsp),%r9d
movl %r10d,%r15d
xorl %r8d,%r12d
rorl $11,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
rorl $6,%r13d
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
xorl %r11d,%edi
rorl $2,%r14d
addl %r9d,%ebx
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
rorl $14,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
rorl $9,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
rorl $5,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
xorl %ebx,%r13d
addl 44(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
rorl $11,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
rorl $6,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
rorl $2,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
rorl $14,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
rorl $9,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
rorl $5,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
xorl %eax,%r13d
addl 48(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
rorl $11,%r14d
xorl %r9d,%r15d
addl %r12d,%edx
rorl $6,%r13d
andl %r15d,%edi
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
rorl $2,%r14d
addl %edx,%r11d
addl %edi,%edx
movl %r11d,%r13d
addl %edx,%r14d
rorl $14,%r13d
movl %r14d,%edx
movl %eax,%r12d
rorl $9,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
rorl $5,%r13d
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
addl 52(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
rorl $11,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
rorl $6,%r13d
andl %edi,%r15d
xorl %edx,%r14d
addl %r13d,%ecx
xorl %r8d,%r15d
rorl $2,%r14d
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
rorl $14,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
rorl $9,%r14d
xorl %r10d,%r13d
xorl %eax,%r12d
rorl $5,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
xorl %r10d,%r13d
addl 56(%rsp),%ebx
movl %ecx,%r15d
xorl %eax,%r12d
rorl $11,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
rorl $6,%r13d
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
xorl %edx,%edi
rorl $2,%r14d
addl %ebx,%r9d
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
rorl $14,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
rorl $9,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
rorl $5,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
xorl %r9d,%r13d
addl 60(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
rorl $11,%r14d
xorl %ecx,%edi
addl %r12d,%eax
rorl $6,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
rorl $2,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
movq 64+0(%rsp),%rdi
movl %r14d,%eax
addl 0(%rdi),%eax
leaq 64(%rsi),%rsi
addl 4(%rdi),%ebx
addl 8(%rdi),%ecx
addl 12(%rdi),%edx
addl 16(%rdi),%r8d
addl 20(%rdi),%r9d
addl 24(%rdi),%r10d
addl 28(%rdi),%r11d
cmpq 64+16(%rsp),%rsi
movl %eax,0(%rdi)
movl %ebx,4(%rdi)
movl %ecx,8(%rdi)
movl %edx,12(%rdi)
movl %r8d,16(%rdi)
movl %r9d,20(%rdi)
movl %r10d,24(%rdi)
movl %r11d,28(%rdi)
jb L$loop_ssse3
movq 88(%rsp),%rsi
movq -48(%rsi),%r15
movq -40(%rsi),%r14
movq -32(%rsi),%r13
movq -24(%rsi),%r12
movq -16(%rsi),%rbp
movq -8(%rsi),%rbx
leaq (%rsi),%rsp
L$epilogue_ssse3:
.byte 0xf3,0xc3
.p2align 6
sha256_block_data_order_avx:
L$avx_shortcut:
movq %rsp,%rax
pushq %rbx
pushq %rbp
pushq %r12
pushq %r13
pushq %r14
pushq %r15
shlq $4,%rdx
subq $96,%rsp
leaq (%rsi,%rdx,4),%rdx
andq $-64,%rsp
movq %rdi,64+0(%rsp)
movq %rsi,64+8(%rsp)
movq %rdx,64+16(%rsp)
movq %rax,88(%rsp)
L$prologue_avx:
vzeroupper
movl 0(%rdi),%eax
movl 4(%rdi),%ebx
movl 8(%rdi),%ecx
movl 12(%rdi),%edx
movl 16(%rdi),%r8d
movl 20(%rdi),%r9d
movl 24(%rdi),%r10d
movl 28(%rdi),%r11d
vmovdqa K256+512+32(%rip),%xmm8
vmovdqa K256+512+64(%rip),%xmm9
jmp L$loop_avx
.p2align 4
L$loop_avx:
vmovdqa K256+512(%rip),%xmm7
vmovdqu 0(%rsi),%xmm0
vmovdqu 16(%rsi),%xmm1
vmovdqu 32(%rsi),%xmm2
vmovdqu 48(%rsi),%xmm3
vpshufb %xmm7,%xmm0,%xmm0
leaq K256(%rip),%rbp
vpshufb %xmm7,%xmm1,%xmm1
vpshufb %xmm7,%xmm2,%xmm2
vpaddd 0(%rbp),%xmm0,%xmm4
vpshufb %xmm7,%xmm3,%xmm3
vpaddd 32(%rbp),%xmm1,%xmm5
vpaddd 64(%rbp),%xmm2,%xmm6
vpaddd 96(%rbp),%xmm3,%xmm7
vmovdqa %xmm4,0(%rsp)
movl %eax,%r14d
vmovdqa %xmm5,16(%rsp)
movl %ebx,%edi
vmovdqa %xmm6,32(%rsp)
xorl %ecx,%edi
vmovdqa %xmm7,48(%rsp)
movl %r8d,%r13d
jmp L$avx_00_47
.p2align 4
L$avx_00_47:
subq $-128,%rbp
vpalignr $4,%xmm0,%xmm1,%xmm4
shrdl $14,%r13d,%r13d
movl %r14d,%eax
movl %r9d,%r12d
vpalignr $4,%xmm2,%xmm3,%xmm7
shrdl $9,%r14d,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
vpsrld $7,%xmm4,%xmm6
shrdl $5,%r13d,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
vpaddd %xmm7,%xmm0,%xmm0
xorl %r8d,%r13d
addl 0(%rsp),%r11d
movl %eax,%r15d
vpsrld $3,%xmm4,%xmm7
xorl %r10d,%r12d
shrdl $11,%r14d,%r14d
xorl %ebx,%r15d
vpslld $14,%xmm4,%xmm5
addl %r12d,%r11d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
vpxor %xmm6,%xmm7,%xmm4
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
vpshufd $250,%xmm3,%xmm7
shrdl $2,%r14d,%r14d
addl %r11d,%edx
addl %edi,%r11d
vpsrld $11,%xmm6,%xmm6
movl %edx,%r13d
addl %r11d,%r14d
shrdl $14,%r13d,%r13d
vpxor %xmm5,%xmm4,%xmm4
movl %r14d,%r11d
movl %r8d,%r12d
shrdl $9,%r14d,%r14d
vpslld $11,%xmm5,%xmm5
xorl %edx,%r13d
xorl %r9d,%r12d
shrdl $5,%r13d,%r13d
vpxor %xmm6,%xmm4,%xmm4
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
vpsrld $10,%xmm7,%xmm6
addl 4(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
vpxor %xmm5,%xmm4,%xmm4
shrdl $11,%r14d,%r14d
xorl %eax,%edi
addl %r12d,%r10d
vpsrlq $17,%xmm7,%xmm7
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
vpaddd %xmm4,%xmm0,%xmm0
addl %r13d,%r10d
xorl %eax,%r15d
shrdl $2,%r14d,%r14d
vpxor %xmm7,%xmm6,%xmm6
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
vpsrlq $2,%xmm7,%xmm7
addl %r10d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r10d
vpxor %xmm7,%xmm6,%xmm6
movl %edx,%r12d
shrdl $9,%r14d,%r14d
xorl %ecx,%r13d
vpshufb %xmm8,%xmm6,%xmm6
xorl %r8d,%r12d
shrdl $5,%r13d,%r13d
xorl %r10d,%r14d
vpaddd %xmm6,%xmm0,%xmm0
andl %ecx,%r12d
xorl %ecx,%r13d
addl 8(%rsp),%r9d
vpshufd $80,%xmm0,%xmm7
movl %r10d,%r15d
xorl %r8d,%r12d
shrdl $11,%r14d,%r14d
vpsrld $10,%xmm7,%xmm6
xorl %r11d,%r15d
addl %r12d,%r9d
shrdl $6,%r13d,%r13d
vpsrlq $17,%xmm7,%xmm7
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
vpxor %xmm7,%xmm6,%xmm6
xorl %r11d,%edi
shrdl $2,%r14d,%r14d
addl %r9d,%ebx
vpsrlq $2,%xmm7,%xmm7
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
vpxor %xmm7,%xmm6,%xmm6
shrdl $14,%r13d,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
vpshufb %xmm9,%xmm6,%xmm6
shrdl $9,%r14d,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
vpaddd %xmm6,%xmm0,%xmm0
shrdl $5,%r13d,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
vpaddd 0(%rbp),%xmm0,%xmm6
xorl %ebx,%r13d
addl 12(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
shrdl $11,%r14d,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
shrdl $2,%r14d,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
vmovdqa %xmm6,0(%rsp)
vpalignr $4,%xmm1,%xmm2,%xmm4
shrdl $14,%r13d,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
vpalignr $4,%xmm3,%xmm0,%xmm7
shrdl $9,%r14d,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
vpsrld $7,%xmm4,%xmm6
shrdl $5,%r13d,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
vpaddd %xmm7,%xmm1,%xmm1
xorl %eax,%r13d
addl 16(%rsp),%edx
movl %r8d,%r15d
vpsrld $3,%xmm4,%xmm7
xorl %ecx,%r12d
shrdl $11,%r14d,%r14d
xorl %r9d,%r15d
vpslld $14,%xmm4,%xmm5
addl %r12d,%edx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
vpxor %xmm6,%xmm7,%xmm4
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
vpshufd $250,%xmm0,%xmm7
shrdl $2,%r14d,%r14d
addl %edx,%r11d
addl %edi,%edx
vpsrld $11,%xmm6,%xmm6
movl %r11d,%r13d
addl %edx,%r14d
shrdl $14,%r13d,%r13d
vpxor %xmm5,%xmm4,%xmm4
movl %r14d,%edx
movl %eax,%r12d
shrdl $9,%r14d,%r14d
vpslld $11,%xmm5,%xmm5
xorl %r11d,%r13d
xorl %ebx,%r12d
shrdl $5,%r13d,%r13d
vpxor %xmm6,%xmm4,%xmm4
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
vpsrld $10,%xmm7,%xmm6
addl 20(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
vpxor %xmm5,%xmm4,%xmm4
shrdl $11,%r14d,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
vpsrlq $17,%xmm7,%xmm7
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %edx,%r14d
vpaddd %xmm4,%xmm1,%xmm1
addl %r13d,%ecx
xorl %r8d,%r15d
shrdl $2,%r14d,%r14d
vpxor %xmm7,%xmm6,%xmm6
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
vpsrlq $2,%xmm7,%xmm7
addl %ecx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ecx
vpxor %xmm7,%xmm6,%xmm6
movl %r11d,%r12d
shrdl $9,%r14d,%r14d
xorl %r10d,%r13d
vpshufb %xmm8,%xmm6,%xmm6
xorl %eax,%r12d
shrdl $5,%r13d,%r13d
xorl %ecx,%r14d
vpaddd %xmm6,%xmm1,%xmm1
andl %r10d,%r12d
xorl %r10d,%r13d
addl 24(%rsp),%ebx
vpshufd $80,%xmm1,%xmm7
movl %ecx,%r15d
xorl %eax,%r12d
shrdl $11,%r14d,%r14d
vpsrld $10,%xmm7,%xmm6
xorl %edx,%r15d
addl %r12d,%ebx
shrdl $6,%r13d,%r13d
vpsrlq $17,%xmm7,%xmm7
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
vpxor %xmm7,%xmm6,%xmm6
xorl %edx,%edi
shrdl $2,%r14d,%r14d
addl %ebx,%r9d
vpsrlq $2,%xmm7,%xmm7
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
vpxor %xmm7,%xmm6,%xmm6
shrdl $14,%r13d,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
vpshufb %xmm9,%xmm6,%xmm6
shrdl $9,%r14d,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
vpaddd %xmm6,%xmm1,%xmm1
shrdl $5,%r13d,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
vpaddd 32(%rbp),%xmm1,%xmm6
xorl %r9d,%r13d
addl 28(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
shrdl $11,%r14d,%r14d
xorl %ecx,%edi
addl %r12d,%eax
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
shrdl $2,%r14d,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
vmovdqa %xmm6,16(%rsp)
vpalignr $4,%xmm2,%xmm3,%xmm4
shrdl $14,%r13d,%r13d
movl %r14d,%eax
movl %r9d,%r12d
vpalignr $4,%xmm0,%xmm1,%xmm7
shrdl $9,%r14d,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
vpsrld $7,%xmm4,%xmm6
shrdl $5,%r13d,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
vpaddd %xmm7,%xmm2,%xmm2
xorl %r8d,%r13d
addl 32(%rsp),%r11d
movl %eax,%r15d
vpsrld $3,%xmm4,%xmm7
xorl %r10d,%r12d
shrdl $11,%r14d,%r14d
xorl %ebx,%r15d
vpslld $14,%xmm4,%xmm5
addl %r12d,%r11d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
vpxor %xmm6,%xmm7,%xmm4
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
vpshufd $250,%xmm1,%xmm7
shrdl $2,%r14d,%r14d
addl %r11d,%edx
addl %edi,%r11d
vpsrld $11,%xmm6,%xmm6
movl %edx,%r13d
addl %r11d,%r14d
shrdl $14,%r13d,%r13d
vpxor %xmm5,%xmm4,%xmm4
movl %r14d,%r11d
movl %r8d,%r12d
shrdl $9,%r14d,%r14d
vpslld $11,%xmm5,%xmm5
xorl %edx,%r13d
xorl %r9d,%r12d
shrdl $5,%r13d,%r13d
vpxor %xmm6,%xmm4,%xmm4
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
vpsrld $10,%xmm7,%xmm6
addl 36(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
vpxor %xmm5,%xmm4,%xmm4
shrdl $11,%r14d,%r14d
xorl %eax,%edi
addl %r12d,%r10d
vpsrlq $17,%xmm7,%xmm7
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
vpaddd %xmm4,%xmm2,%xmm2
addl %r13d,%r10d
xorl %eax,%r15d
shrdl $2,%r14d,%r14d
vpxor %xmm7,%xmm6,%xmm6
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
vpsrlq $2,%xmm7,%xmm7
addl %r10d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r10d
vpxor %xmm7,%xmm6,%xmm6
movl %edx,%r12d
shrdl $9,%r14d,%r14d
xorl %ecx,%r13d
vpshufb %xmm8,%xmm6,%xmm6
xorl %r8d,%r12d
shrdl $5,%r13d,%r13d
xorl %r10d,%r14d
vpaddd %xmm6,%xmm2,%xmm2
andl %ecx,%r12d
xorl %ecx,%r13d
addl 40(%rsp),%r9d
vpshufd $80,%xmm2,%xmm7
movl %r10d,%r15d
xorl %r8d,%r12d
shrdl $11,%r14d,%r14d
vpsrld $10,%xmm7,%xmm6
xorl %r11d,%r15d
addl %r12d,%r9d
shrdl $6,%r13d,%r13d
vpsrlq $17,%xmm7,%xmm7
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
vpxor %xmm7,%xmm6,%xmm6
xorl %r11d,%edi
shrdl $2,%r14d,%r14d
addl %r9d,%ebx
vpsrlq $2,%xmm7,%xmm7
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
vpxor %xmm7,%xmm6,%xmm6
shrdl $14,%r13d,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
vpshufb %xmm9,%xmm6,%xmm6
shrdl $9,%r14d,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
vpaddd %xmm6,%xmm2,%xmm2
shrdl $5,%r13d,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
vpaddd 64(%rbp),%xmm2,%xmm6
xorl %ebx,%r13d
addl 44(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
shrdl $11,%r14d,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
shrdl $2,%r14d,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
vmovdqa %xmm6,32(%rsp)
vpalignr $4,%xmm3,%xmm0,%xmm4
shrdl $14,%r13d,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
vpalignr $4,%xmm1,%xmm2,%xmm7
shrdl $9,%r14d,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
vpsrld $7,%xmm4,%xmm6
shrdl $5,%r13d,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
vpaddd %xmm7,%xmm3,%xmm3
xorl %eax,%r13d
addl 48(%rsp),%edx
movl %r8d,%r15d
vpsrld $3,%xmm4,%xmm7
xorl %ecx,%r12d
shrdl $11,%r14d,%r14d
xorl %r9d,%r15d
vpslld $14,%xmm4,%xmm5
addl %r12d,%edx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
vpxor %xmm6,%xmm7,%xmm4
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
vpshufd $250,%xmm2,%xmm7
shrdl $2,%r14d,%r14d
addl %edx,%r11d
addl %edi,%edx
vpsrld $11,%xmm6,%xmm6
movl %r11d,%r13d
addl %edx,%r14d
shrdl $14,%r13d,%r13d
vpxor %xmm5,%xmm4,%xmm4
movl %r14d,%edx
movl %eax,%r12d
shrdl $9,%r14d,%r14d
vpslld $11,%xmm5,%xmm5
xorl %r11d,%r13d
xorl %ebx,%r12d
shrdl $5,%r13d,%r13d
vpxor %xmm6,%xmm4,%xmm4
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
vpsrld $10,%xmm7,%xmm6
addl 52(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
vpxor %xmm5,%xmm4,%xmm4
shrdl $11,%r14d,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
vpsrlq $17,%xmm7,%xmm7
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %edx,%r14d
vpaddd %xmm4,%xmm3,%xmm3
addl %r13d,%ecx
xorl %r8d,%r15d
shrdl $2,%r14d,%r14d
vpxor %xmm7,%xmm6,%xmm6
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
vpsrlq $2,%xmm7,%xmm7
addl %ecx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ecx
vpxor %xmm7,%xmm6,%xmm6
movl %r11d,%r12d
shrdl $9,%r14d,%r14d
xorl %r10d,%r13d
vpshufb %xmm8,%xmm6,%xmm6
xorl %eax,%r12d
shrdl $5,%r13d,%r13d
xorl %ecx,%r14d
vpaddd %xmm6,%xmm3,%xmm3
andl %r10d,%r12d
xorl %r10d,%r13d
addl 56(%rsp),%ebx
vpshufd $80,%xmm3,%xmm7
movl %ecx,%r15d
xorl %eax,%r12d
shrdl $11,%r14d,%r14d
vpsrld $10,%xmm7,%xmm6
xorl %edx,%r15d
addl %r12d,%ebx
shrdl $6,%r13d,%r13d
vpsrlq $17,%xmm7,%xmm7
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
vpxor %xmm7,%xmm6,%xmm6
xorl %edx,%edi
shrdl $2,%r14d,%r14d
addl %ebx,%r9d
vpsrlq $2,%xmm7,%xmm7
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
vpxor %xmm7,%xmm6,%xmm6
shrdl $14,%r13d,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
vpshufb %xmm9,%xmm6,%xmm6
shrdl $9,%r14d,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
vpaddd %xmm6,%xmm3,%xmm3
shrdl $5,%r13d,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
vpaddd 96(%rbp),%xmm3,%xmm6
xorl %r9d,%r13d
addl 60(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
shrdl $11,%r14d,%r14d
xorl %ecx,%edi
addl %r12d,%eax
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
shrdl $2,%r14d,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
vmovdqa %xmm6,48(%rsp)
cmpb $0,131(%rbp)
jne L$avx_00_47
shrdl $14,%r13d,%r13d
movl %r14d,%eax
movl %r9d,%r12d
shrdl $9,%r14d,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
shrdl $5,%r13d,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
xorl %r8d,%r13d
addl 0(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
shrdl $11,%r14d,%r14d
xorl %ebx,%r15d
addl %r12d,%r11d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
shrdl $2,%r14d,%r14d
addl %r11d,%edx
addl %edi,%r11d
movl %edx,%r13d
addl %r11d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r11d
movl %r8d,%r12d
shrdl $9,%r14d,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
shrdl $5,%r13d,%r13d
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
addl 4(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
shrdl $11,%r14d,%r14d
xorl %eax,%edi
addl %r12d,%r10d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
addl %r13d,%r10d
xorl %eax,%r15d
shrdl $2,%r14d,%r14d
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r10d
movl %edx,%r12d
shrdl $9,%r14d,%r14d
xorl %ecx,%r13d
xorl %r8d,%r12d
shrdl $5,%r13d,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
xorl %ecx,%r13d
addl 8(%rsp),%r9d
movl %r10d,%r15d
xorl %r8d,%r12d
shrdl $11,%r14d,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
xorl %r11d,%edi
shrdl $2,%r14d,%r14d
addl %r9d,%ebx
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
shrdl $9,%r14d,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
shrdl $5,%r13d,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
xorl %ebx,%r13d
addl 12(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
shrdl $11,%r14d,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
shrdl $2,%r14d,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
shrdl $9,%r14d,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
shrdl $5,%r13d,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
xorl %eax,%r13d
addl 16(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
shrdl $11,%r14d,%r14d
xorl %r9d,%r15d
addl %r12d,%edx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
shrdl $2,%r14d,%r14d
addl %edx,%r11d
addl %edi,%edx
movl %r11d,%r13d
addl %edx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%edx
movl %eax,%r12d
shrdl $9,%r14d,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
shrdl $5,%r13d,%r13d
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
addl 20(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
shrdl $11,%r14d,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %edx,%r14d
addl %r13d,%ecx
xorl %r8d,%r15d
shrdl $2,%r14d,%r14d
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
shrdl $9,%r14d,%r14d
xorl %r10d,%r13d
xorl %eax,%r12d
shrdl $5,%r13d,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
xorl %r10d,%r13d
addl 24(%rsp),%ebx
movl %ecx,%r15d
xorl %eax,%r12d
shrdl $11,%r14d,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
xorl %edx,%edi
shrdl $2,%r14d,%r14d
addl %ebx,%r9d
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
shrdl $9,%r14d,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
shrdl $5,%r13d,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
xorl %r9d,%r13d
addl 28(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
shrdl $11,%r14d,%r14d
xorl %ecx,%edi
addl %r12d,%eax
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
shrdl $2,%r14d,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%eax
movl %r9d,%r12d
shrdl $9,%r14d,%r14d
xorl %r8d,%r13d
xorl %r10d,%r12d
shrdl $5,%r13d,%r13d
xorl %eax,%r14d
andl %r8d,%r12d
xorl %r8d,%r13d
addl 32(%rsp),%r11d
movl %eax,%r15d
xorl %r10d,%r12d
shrdl $11,%r14d,%r14d
xorl %ebx,%r15d
addl %r12d,%r11d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %eax,%r14d
addl %r13d,%r11d
xorl %ebx,%edi
shrdl $2,%r14d,%r14d
addl %r11d,%edx
addl %edi,%r11d
movl %edx,%r13d
addl %r11d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r11d
movl %r8d,%r12d
shrdl $9,%r14d,%r14d
xorl %edx,%r13d
xorl %r9d,%r12d
shrdl $5,%r13d,%r13d
xorl %r11d,%r14d
andl %edx,%r12d
xorl %edx,%r13d
addl 36(%rsp),%r10d
movl %r11d,%edi
xorl %r9d,%r12d
shrdl $11,%r14d,%r14d
xorl %eax,%edi
addl %r12d,%r10d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r11d,%r14d
addl %r13d,%r10d
xorl %eax,%r15d
shrdl $2,%r14d,%r14d
addl %r10d,%ecx
addl %r15d,%r10d
movl %ecx,%r13d
addl %r10d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r10d
movl %edx,%r12d
shrdl $9,%r14d,%r14d
xorl %ecx,%r13d
xorl %r8d,%r12d
shrdl $5,%r13d,%r13d
xorl %r10d,%r14d
andl %ecx,%r12d
xorl %ecx,%r13d
addl 40(%rsp),%r9d
movl %r10d,%r15d
xorl %r8d,%r12d
shrdl $11,%r14d,%r14d
xorl %r11d,%r15d
addl %r12d,%r9d
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %r10d,%r14d
addl %r13d,%r9d
xorl %r11d,%edi
shrdl $2,%r14d,%r14d
addl %r9d,%ebx
addl %edi,%r9d
movl %ebx,%r13d
addl %r9d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r9d
movl %ecx,%r12d
shrdl $9,%r14d,%r14d
xorl %ebx,%r13d
xorl %edx,%r12d
shrdl $5,%r13d,%r13d
xorl %r9d,%r14d
andl %ebx,%r12d
xorl %ebx,%r13d
addl 44(%rsp),%r8d
movl %r9d,%edi
xorl %edx,%r12d
shrdl $11,%r14d,%r14d
xorl %r10d,%edi
addl %r12d,%r8d
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %r9d,%r14d
addl %r13d,%r8d
xorl %r10d,%r15d
shrdl $2,%r14d,%r14d
addl %r8d,%eax
addl %r15d,%r8d
movl %eax,%r13d
addl %r8d,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%r8d
movl %ebx,%r12d
shrdl $9,%r14d,%r14d
xorl %eax,%r13d
xorl %ecx,%r12d
shrdl $5,%r13d,%r13d
xorl %r8d,%r14d
andl %eax,%r12d
xorl %eax,%r13d
addl 48(%rsp),%edx
movl %r8d,%r15d
xorl %ecx,%r12d
shrdl $11,%r14d,%r14d
xorl %r9d,%r15d
addl %r12d,%edx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %r8d,%r14d
addl %r13d,%edx
xorl %r9d,%edi
shrdl $2,%r14d,%r14d
addl %edx,%r11d
addl %edi,%edx
movl %r11d,%r13d
addl %edx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%edx
movl %eax,%r12d
shrdl $9,%r14d,%r14d
xorl %r11d,%r13d
xorl %ebx,%r12d
shrdl $5,%r13d,%r13d
xorl %edx,%r14d
andl %r11d,%r12d
xorl %r11d,%r13d
addl 52(%rsp),%ecx
movl %edx,%edi
xorl %ebx,%r12d
shrdl $11,%r14d,%r14d
xorl %r8d,%edi
addl %r12d,%ecx
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %edx,%r14d
addl %r13d,%ecx
xorl %r8d,%r15d
shrdl $2,%r14d,%r14d
addl %ecx,%r10d
addl %r15d,%ecx
movl %r10d,%r13d
addl %ecx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ecx
movl %r11d,%r12d
shrdl $9,%r14d,%r14d
xorl %r10d,%r13d
xorl %eax,%r12d
shrdl $5,%r13d,%r13d
xorl %ecx,%r14d
andl %r10d,%r12d
xorl %r10d,%r13d
addl 56(%rsp),%ebx
movl %ecx,%r15d
xorl %eax,%r12d
shrdl $11,%r14d,%r14d
xorl %edx,%r15d
addl %r12d,%ebx
shrdl $6,%r13d,%r13d
andl %r15d,%edi
xorl %ecx,%r14d
addl %r13d,%ebx
xorl %edx,%edi
shrdl $2,%r14d,%r14d
addl %ebx,%r9d
addl %edi,%ebx
movl %r9d,%r13d
addl %ebx,%r14d
shrdl $14,%r13d,%r13d
movl %r14d,%ebx
movl %r10d,%r12d
shrdl $9,%r14d,%r14d
xorl %r9d,%r13d
xorl %r11d,%r12d
shrdl $5,%r13d,%r13d
xorl %ebx,%r14d
andl %r9d,%r12d
xorl %r9d,%r13d
addl 60(%rsp),%eax
movl %ebx,%edi
xorl %r11d,%r12d
shrdl $11,%r14d,%r14d
xorl %ecx,%edi
addl %r12d,%eax
shrdl $6,%r13d,%r13d
andl %edi,%r15d
xorl %ebx,%r14d
addl %r13d,%eax
xorl %ecx,%r15d
shrdl $2,%r14d,%r14d
addl %eax,%r8d
addl %r15d,%eax
movl %r8d,%r13d
addl %eax,%r14d
movq 64+0(%rsp),%rdi
movl %r14d,%eax
addl 0(%rdi),%eax
leaq 64(%rsi),%rsi
addl 4(%rdi),%ebx
addl 8(%rdi),%ecx
addl 12(%rdi),%edx
addl 16(%rdi),%r8d
addl 20(%rdi),%r9d
addl 24(%rdi),%r10d
addl 28(%rdi),%r11d
cmpq 64+16(%rsp),%rsi
movl %eax,0(%rdi)
movl %ebx,4(%rdi)
movl %ecx,8(%rdi)
movl %edx,12(%rdi)
movl %r8d,16(%rdi)
movl %r9d,20(%rdi)
movl %r10d,24(%rdi)
movl %r11d,28(%rdi)
jb L$loop_avx
movq 88(%rsp),%rsi
vzeroupper
movq -48(%rsi),%r15
movq -40(%rsi),%r14
movq -32(%rsi),%r13
movq -24(%rsi),%r12
movq -16(%rsi),%rbp
movq -8(%rsi),%rbx
leaq (%rsi),%rsp
L$epilogue_avx:
.byte 0xf3,0xc3
#endif
| {
"language": "Assembly"
} |
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
; Ensure we access the local stack properly
; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
; PTX32: cvta.local.u32 %SP, %SPL;
; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
; PTX32: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
; PTX64: cvta.local.u64 %SP, %SPL;
; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo_param_0];
; PTX64: st.volatile.u32 [%SP+0], %r{{[0-9]+}};
define void @foo(i32 %a) {
%local = alloca i32, align 4
store volatile i32 %a, i32* %local
ret void
}
; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
; PTX32: cvta.local.u32 %SP, %SPL;
; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0];
; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0;
; PTX32: st.local.u32 [%r[[SP_REG]]], %r{{[0-9]+}};
; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
; PTX64: cvta.local.u64 %SP, %SPL;
; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0];
; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}};
define void @foo2(i32 %a) {
%local = alloca i32, align 4
store i32 %a, i32* %local
call void @bar(i32* %local)
ret void
}
declare void @bar(i32* %a)
!nvvm.annotations = !{!0}
!0 = !{void (i32)* @foo2, !"kernel", i32 1}
; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}};
; PTX32-NOT: cvta.local.u32 %SP, %SPL;
; PTX32: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0];
; PTX32: add.u32 %r{{[0-9]+}}, %SPL, 0;
; PTX32: st.local.u32 [%r{{[0-9]+}}], %r{{[0-9]+}};
; PTX64: mov.u64 %SPL, __local_depot{{[0-9]+}};
; PTX64-NOT: cvta.local.u64 %SP, %SPL;
; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo3_param_0];
; PTX64: add.u64 %rd{{[0-9]+}}, %SPL, 0;
; PTX64: st.local.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}};
define void @foo3(i32 %a) {
%local = alloca [3 x i32], align 4
%1 = bitcast [3 x i32]* %local to i32*
%2 = getelementptr inbounds i32, i32* %1, i32 %a
store i32 %a, i32* %2
ret void
}
; PTX32: cvta.local.u32 %SP, %SPL;
; PTX32: add.u32 {{%r[0-9]+}}, %SP, 0;
; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 0;
; PTX32: add.u32 {{%r[0-9]+}}, %SP, 4;
; PTX32: add.u32 {{%r[0-9]+}}, %SPL, 4;
; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}}
; PTX32: st.local.u32 [{{%r[0-9]+}}], {{%r[0-9]+}}
; PTX64: cvta.local.u64 %SP, %SPL;
; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 0;
; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 0;
; PTX64: add.u64 {{%rd[0-9]+}}, %SP, 4;
; PTX64: add.u64 {{%rd[0-9]+}}, %SPL, 4;
; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}}
; PTX64: st.local.u32 [{{%rd[0-9]+}}], {{%r[0-9]+}}
define void @foo4() {
%A = alloca i32
%B = alloca i32
store i32 0, i32* %A
store i32 0, i32* %B
call void @bar(i32* %A)
call void @bar(i32* %B)
ret void
}
| {
"language": "Assembly"
} |
@/**************************************************************************/
@/* */
@/* Copyright (c) Microsoft Corporation. All rights reserved. */
@/* */
@/* This software is licensed under the Microsoft Software License */
@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
@/* and in the root directory of this software. */
@/* */
@/**************************************************************************/
@
@
@/**************************************************************************/
@/**************************************************************************/
@/** */
@/** ThreadX Component */
@/** */
@/** Thread */
@/** */
@/**************************************************************************/
@/**************************************************************************/
@
@
@#define TX_SOURCE_CODE
@
@
@/* Include necessary system files. */
@
@#include "tx_api.h"
@#include "tx_thread.h"
@
@
.global _tx_thread_system_state
.global _tx_thread_current_ptr
.global _tx_execution_isr_enter
@
@
@
@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save
@ since it will never be called 16-bit mode. */
@
.arm
.text
.align 2
@/**************************************************************************/
@/* */
@/* FUNCTION RELEASE */
@/* */
@/* _tx_thread_vectored_context_save Cortex-A5/GNU */
@/* 6.0.1 */
@/* AUTHOR */
@/* */
@/* William E. Lamie, Microsoft Corporation */
@/* */
@/* DESCRIPTION */
@/* */
@/* This function saves the context of an executing thread in the */
@/* beginning of interrupt processing. The function also ensures that */
@/* the system stack is used upon return to the calling ISR. */
@/* */
@/* INPUT */
@/* */
@/* None */
@/* */
@/* OUTPUT */
@/* */
@/* None */
@/* */
@/* CALLS */
@/* */
@/* None */
@/* */
@/* CALLED BY */
@/* */
@/* ISRs */
@/* */
@/* RELEASE HISTORY */
@/* */
@/* DATE NAME DESCRIPTION */
@/* */
@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */
@/* */
@/**************************************************************************/
@VOID _tx_thread_vectored_context_save(VOID)
@{
.global _tx_thread_vectored_context_save
.type _tx_thread_vectored_context_save,function
_tx_thread_vectored_context_save:
@
@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
@ out, we are in IRQ mode, and all registers are intact. */
@
@ /* Check for a nested interrupt condition. */
@ if (_tx_thread_system_state++)
@ {
@
#ifdef TX_ENABLE_FIQ_SUPPORT
CPSID if @ Disable IRQ and FIQ interrupts
#endif
LDR r3, =_tx_thread_system_state @ Pickup address of system state variable
LDR r2, [r3, #0] @ Pickup system state
CMP r2, #0 @ Is this the first interrupt?
BEQ __tx_thread_not_nested_save @ Yes, not a nested context save
@
@ /* Nested interrupt condition. */
@
ADD r2, r2, #1 @ Increment the interrupt counter
STR r2, [r3, #0] @ Store it back in the variable
@
@ /* Note: Minimal context of interrupted thread is already saved. */
@
@ /* Return to the ISR. */
@
MOV r10, #0 @ Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ /* Call the ISR enter function to indicate an ISR is executing. */
@
PUSH {lr} @ Save ISR lr
BL _tx_execution_isr_enter @ Call the ISR enter function
POP {lr} @ Recover ISR lr
#endif
MOV pc, lr @ Return to caller
@
__tx_thread_not_nested_save:
@ }
@
@ /* Otherwise, not nested, check to see if a thread was running. */
@ else if (_tx_thread_current_ptr)
@ {
@
ADD r2, r2, #1 @ Increment the interrupt counter
STR r2, [r3, #0] @ Store it back in the variable
LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr
LDR r0, [r1, #0] @ Pickup current thread pointer
CMP r0, #0 @ Is it NULL?
BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in
@ scheduling loop - nothing needs saving!
@
@ /* Note: Minimal context of interrupted thread is already saved. */
@
@ /* Save the current stack pointer in the thread's control block. */
@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
@
@ /* Switch to the system stack. */
@ sp = _tx_thread_system_stack_ptr;
@
MOV r10, #0 @ Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ /* Call the ISR enter function to indicate an ISR is executing. */
@
PUSH {lr} @ Save ISR lr
BL _tx_execution_isr_enter @ Call the ISR enter function
POP {lr} @ Recover ISR lr
#endif
MOV pc, lr @ Return to caller
@
@ }
@ else
@ {
@
__tx_thread_idle_system_save:
@
@ /* Interrupt occurred in the scheduling loop. */
@
@ /* Not much to do here, just adjust the stack pointer, and return to IRQ
@ processing. */
@
MOV r10, #0 @ Clear stack limit
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@
@ /* Call the ISR enter function to indicate an ISR is executing. */
@
PUSH {lr} @ Save ISR lr
BL _tx_execution_isr_enter @ Call the ISR enter function
POP {lr} @ Recover ISR lr
#endif
ADD sp, sp, #32 @ Recover saved registers
MOV pc, lr @ Return to caller
@
@ }
@}
| {
"language": "Assembly"
} |
.set tid, 0x00
.set len, 0x04
.set slots, 0x18
/* const tid : (-> tid) */
.globl thread$tid
.globl _thread$tid
thread$tid:
_thread$tid:
movl %fs:tid, %eax
ret
/* const _tlsset : (k : key, v : void# -> void) */
.globl thread$_tlsset
.globl _thread$_tlsset
thread$_tlsset:
_thread$_tlsset:
cmpl %fs:len, %edi
jnb oob
movslq %edi, %rdi
movq $slots, %r10
movq %rsi, %fs:(%r10, %rdi, 0x8)
ret
/* const _tlsget : (k : key -> void#) */
.globl thread$_tlsget
.globl _thread$_tlsget
thread$_tlsget:
_thread$_tlsget:
cmpl %fs:len, %edi
jnb oob
movslq %edi, %rdi
movq $slots, %r10
movq %fs:(%r10, %rdi, 0x8), %rax
ret
oob:
call thread$tlsoob
/* const tlslen : (-> key) */
.globl thread$tlslen
.globl _thread$tlslen
thread$tlslen:
_thread$tlslen:
movl %fs:len, %eax
ret
| {
"language": "Assembly"
} |
;RUN: opt < %s -instcombine -S | grep zext
; Make sure the uint isn't removed. Instcombine in llvm 1.9 was dropping the
; uint cast which was causing a sign extend. This only affected code with
; pointers in the high half of memory, so it wasn't noticed much
; compile a kernel though...
target datalayout = "e-p:32:32"
@str = internal constant [6 x i8] c"%llx\0A\00" ; <[6 x i8]*> [#uses=1]
declare i32 @printf(i8*, ...)
define i32 @main(i32 %x, i8** %a) {
entry:
%tmp = getelementptr [6 x i8]* @str, i32 0, i64 0 ; <i8*> [#uses=1]
%tmp1 = load i8** %a ; <i8*> [#uses=1]
%tmp2 = ptrtoint i8* %tmp1 to i32 ; <i32> [#uses=1]
%tmp3 = zext i32 %tmp2 to i64 ; <i64> [#uses=1]
%tmp.upgrd.1 = call i32 (i8*, ...)* @printf( i8* %tmp, i64 %tmp3 ) ; <i32> [#uses=0]
ret i32 0
}
| {
"language": "Assembly"
} |
; RUN: opt -module-summary -o %t %s
; RUN: llvm-lto2 run %t -O0 -r %t,foo,px -o %t2
; RUN: llvm-nm %t2.1 | FileCheck %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; CHECK: W foo
define linkonce_odr void @foo() {
ret void
}
| {
"language": "Assembly"
} |
/* Wrapper around clone system call. 64 bit S/390 version.
Copyright (C) 2001-2018 Free Software Foundation, Inc.
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
/* clone is even more special than fork as it mucks with stacks
and invokes a function in the right context after its all over. */
#include <sysdep.h>
#include <tls.h>
#define _ERRNO_H 1
#include <bits/errno.h>
/* int __clone(int (*fn)(void *arg), void *child_stack, int flags, void *arg,
pid_t *parent_tid, void *tls, pid_t *child_tid); */
/* sys_clone (void *child_stack, unsigned long flags,
pid_t *parent_tid, pid_t *child_tid, void *tls); */
.text
ENTRY(__clone)
stg %r6,48(%r15) /* store %r6 to save area */
cfi_offset (%r6,-112)
lgr %r0,%r5 /* move *arg out of the way */
ltgr %r1,%r2 /* check fn and move to %r1 */
jz error /* no NULL function pointers */
ltgr %r2,%r3 /* check child_stack and move to %r2 */
jz error /* no NULL stack pointers */
lgr %r3,%r4 /* move flags to %r3 */
lgr %r4,%r6 /* move parent_tid to %r4 */
lg %r5,168(%r15) /* load child_tid from stack */
lg %r6,160(%r15) /* load tls from stack */
svc SYS_ify(clone)
ltgr %r2,%r2 /* check return code */
jz thread_start
lg %r6,48(%r15) /* restore %r6 */
jgm SYSCALL_ERROR_LABEL
br %r14
error:
lghi %r2,-EINVAL
jg SYSCALL_ERROR_LABEL
PSEUDO_END (__clone)
thread_start:
cfi_startproc
/* Mark r14 as undefined in order to stop unwinding here! */
cfi_undefined (r14)
/* fn is in gpr 1, arg in gpr 0 */
lgr %r2,%r0 /* set first parameter to void *arg */
aghi %r15,-160 /* make room on the stack for the save area */
xc 0(8,%r15),0(%r15)
basr %r14,%r1 /* jump to fn */
DO_CALL (exit, 1)
cfi_endproc
libc_hidden_def (__clone)
weak_alias (__clone, clone)
| {
"language": "Assembly"
} |
; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s
declare i32 @llvm.ctlz.i32(i32, i1)
define i32 @test(i32 %x) {
; CHECK: test
; CHECK: clz r0, r0
%tmp.1 = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp.1
}
| {
"language": "Assembly"
} |
/*-
* Copyright (c) 1999 John D. Polstra
* Copyright (c) 1999,2001 Peter Wemm <peter@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/* xhyve: sort of working linker sets for MachO */
#pragma once
#define __GLOBL1(sym) __asm__(".globl " #sym)
#define __GLOBL(sym) __GLOBL1(sym)
#define __section(x) __attribute__((__section__(x)))
/*
* The following macros are used to declare global sets of objects, which
* are collected by the linker into a `linker_set' as defined below.
* For ELF, this is done by constructing a separate segment for each set.
*/
#define __MAKE_SET_CONST const
/*
* Private macros, not to be used outside this header file.
*/
#define __MAKE_SET(set, sym) \
__GLOBL(__CONCAT(__start_set_,set)); \
__GLOBL(__CONCAT(__stop_set_,set)); \
static void const * __MAKE_SET_CONST \
__set_##set##_sym_##sym __section("__"#set",__set") \
__used = &(sym)
/*
* Public macros.
*/
#define TEXT_SET(set, sym) __MAKE_SET(set, sym)
#define DATA_SET(set, sym) __MAKE_SET(set, sym)
#define BSS_SET(set, sym) __MAKE_SET(set, sym)
#define ABS_SET(set, sym) __MAKE_SET(set, sym)
#define SET_ENTRY(set, sym) __MAKE_SET(set, sym)
/*
* Initialize before referring to a given linker set.
*/
#define SET_DECLARE(set, ptype) \
extern ptype __weak *__CONCAT(__start_set_,set) \
__asm("segment$start$__"#set); \
extern ptype __weak *__CONCAT(__stop_set_,set) \
__asm("segment$end$__"#set)
#define SET_BEGIN(set) \
(&__CONCAT(__start_set_,set))
#define SET_LIMIT(set) \
(&__CONCAT(__stop_set_,set))
/*
* Iterate over all the elements of a set.
*
* Sets always contain addresses of things, and "pvar" points to words
* containing those addresses. Thus is must be declared as "type **pvar",
* and the address of each set item is obtained inside the loop by "*pvar".
*/
#define SET_FOREACH(pvar, set) \
for (pvar = SET_BEGIN(set); pvar < SET_LIMIT(set); pvar++)
#define SET_ITEM(set, i) \
((SET_BEGIN(set))[i])
/*
* Provide a count of the items in a set.
*/
#define SET_COUNT(set) \
(SET_LIMIT(set) - SET_BEGIN(set))
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -S %s -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 -S %s -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s
// RUN: %clang_cc1 -S %s -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s
#include <stdint.h>
// This test is meant to verify code that handles the 'p = nullptr + n' idiom
// used by some versions of glibc and gcc. This is undefined behavior but
// it is intended there to act like a conversion from a pointer-sized integer
// to a pointer, and we would like to tolerate that.
#define NULLPTRI8 ((int8_t*)0)
// This should get the inttoptr instruction.
int8_t *test1(intptr_t n) {
return NULLPTRI8 + n;
}
// CHECK-LABEL: test1
// CHECK: inttoptr
// CHECK-NOT: getelementptr
// This doesn't meet the idiom because the element type is larger than a byte.
int16_t *test2(intptr_t n) {
return (int16_t*)0 + n;
}
// CHECK-LABEL: test2
// CHECK: getelementptr
// CHECK-NOT: inttoptr
// This doesn't meet the idiom because the offset is subtracted.
int8_t* test3(intptr_t n) {
return NULLPTRI8 - n;
}
// CHECK-LABEL: test3
// CHECK: getelementptr
// CHECK-NOT: inttoptr
// This checks the case where the offset isn't pointer-sized.
// The front end will implicitly cast the offset to an integer, so we need to
// make sure that doesn't cause problems on targets where integers and pointers
// are not the same size.
int8_t *test4(int8_t b) {
return NULLPTRI8 + b;
}
// CHECK-LABEL: test4
// CHECK: inttoptr
// CHECK-NOT: getelementptr
| {
"language": "Assembly"
} |
.setcpu "6502"
.export delay_ms
.code
.align 256
; Delay the number of miliseconds specified by X
; This is hardcoded for a 1 MHz system clock
; @in X The delay in ms
delay_ms: pha ; 3
txa ; 2
pha ; 3
tya ; 2
pha ; 3
ldy $00 ; 3 (dummy operation)
ldy #190 ; 2
@loop1: dey ; 190 * 2
bne @loop1 ; 190 * 3 - 1
@loop2: dex ; 2
beq @return ; (x - 1) * 2 + 3
nop ; 2
ldy #198 ; 2
@loop3: dey ; 198 * 2
bne @loop3 ; 198 * 3 - 1
jmp @loop2 ; 3
@return: pla ; 4
tay ; 2
pla ; 4
tax ; 2
pla ; 4
rts ; 6 (+ 6 for JSR)
| {
"language": "Assembly"
} |
--- a/driver/wl_linux.c
+++ b/driver/wl_linux.c
@@ -49,7 +49,9 @@
#include <linux/ieee80211.h>
#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)
#include <asm/system.h>
+#endif
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
| {
"language": "Assembly"
} |
// Modified by Princeton University on June 9th, 2015
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T1 Processor File: tlb_rw3.s
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
!!-------------------------------------------------------------------------------
!!
!! This file has the micro-code to test out the MMU registers
!!
!!-------------------------------------------------------------------------------
#include "enable_traps.h"
#ifdef MT_TEMPLATE
#include "mt_body.h"
#else
#include "boot.s"
.global main
#endif
.text
main:
nop;nop;
/* change to privileged mode to write DMMU reg */
ta T_CHANGE_PRIV
nop
write_read_dtlb:
mov 0x3d, %l0
mov 0x0, %l1
mov 0x58, %l5 /* skip the first 11 entries */
mov 0x0, %o0 /* standard DMMU miss handler */
/* adjust the timing between thread0 & thread 1 */
nop;nop;nop;nop;nop;nop;
setx th3_dtsb_table1, %l1, %l2
preload_dtlb1:
ldx [%l2], %g4
ldx [%l2+0x8], %g5
add %l2, 0x10, %l2
mov 0x30, %l3
stxa %g4, [%l3] 0x58 /* tag access reg */
stxa %g5, [%l5] 0x5d /* data access reg */
add %l5, 0x8, %l5
readout_dtlb1:
/* read out one entry in D-TLB table to compare */
set 0x0, %l0
set 0x40, %l6
set 0x58, %l7
rdout_dtlb1_loop:
ldxa [%l7] 0x5d, %l3
ldxa [%l7] 0x5e, %l4
/*
* Write & Read of I-TLB
*/
set 0x0, %l0
set 0x180000, %l3 /* Tag Access reg */
setx 0xa000000100180040, %l0, %l4 /* lock bit set */
set 0x30, %l2
set 0x10000, %l7
set 0x58, %l1
mov 0x30, %o0
stxa %l3, [%o0] 0x50 /* IMMU Tag Access Reg */
stxa %l4, [%l1] 0x55 /* IMMU Data In Reg */
ldxa [%l1] 0x55, %g4 /* IMMU data access reg */
ldxa [%l1] 0x56, %g5 /* IMMU tag read reg */
/*
********************************
* Diag PASSED ! *
********************************
*/
diag_pass:
set 0xaaddcafe, %l0
good_trap:
ta T_GOOD_TRAP
nop
/*
********************************
* Diag FAILED ! *
********************************
*/
diag_fail:
set 0xdeadcafe, %l0
bad_trap:
ta T_BAD_TRAP
nop
nop
.data
.global th3_dtsb_table1
th3_dtsb_table1:
/* nucleus context : L=0, size=64k, G=0 */
.xword 0x00000000051a0000, 0xa0000001051a0002
.xword 0x00000000051b0000, 0x20000001051b0002
/* nucleus context : V=1,0 L=0, size=8k, G=0 */
.xword 0x0000000005180000, 0x8000000105180002
.xword 0x0000000005188000, 0x0000000105188002
/* nucleus context : L=0, size=8k, G=1 */
.xword 0x0000000005190000, 0x8000000105190003
.xword 0x0000000005198000, 0x0000000105198003
/* nucleus context : L=0, size=64k, G=1 */
.xword 0x00000000051c0000, 0xa0000001051c0003
.xword 0x00000000051d0000, 0x20000001051d0003
/* nucleus context : L=0, size=512k, G=0 */
.xword 0x0000000000200000, 0xc000000100200002
.xword 0x0000000000280000, 0x4000000100280002
/* nucleus context : L=0, size=512k, G=1 */
.xword 0x0000000000300000, 0xc000000100300003
.xword 0x0000000000380000, 0x4000000100380003
/* nucleus context : L=0, size=4M, G=0 */
.xword 0x0000000000400000, 0xe000000100400002
.xword 0x0000000000800000, 0x6000000100800002
/* nucleus context : L=0, size=4M, G=1 */
.xword 0x0000000000c00000, 0xe00000010c000003
.xword 0x0000000001000000, 0x6000000110000003
/* nucleus context : V=1,0 L=1, size=8k, G=0 */
.xword 0x0000000001a10000, 0x8000000101a10042
.xword 0x0000000001a18000, 0x0000000101a18042
/* nucleus context : L=1, size=8k, G=1 */
.xword 0x0000000001a20000, 0x8000000101a20043
.xword 0x0000000001a28000, 0x0000000101a28043
/* nucleus context : L=1, size=64k, G=0 */
.xword 0x0000000001a30000, 0xa000000101a30042
.xword 0x0000000001a40000, 0x2000000101a40042
/* nucleus context : L=1, size=64k, G=1 */
.xword 0x0000000001a50000, 0xa000000101a50043
.xword 0x0000000001a60000, 0x2000000101a60043
/* nucleus context : L=1, size=512k, G=0 */
.xword 0x0000000001a80000, 0xc000000101a80042
.xword 0x0000000001b00000, 0x4000000101b00042
/* nucleus context : L=1, size=512k, G=1 */
.xword 0x0000000001b80000, 0xc000000101b80043
.xword 0x0000000001c00000, 0x40000001010c0043
/* nucleus context : L=1, size=4M, G=0 */
.xword 0x0000000002400000, 0xe000000102400042
.xword 0x0000000001800000, 0x6000000101800042
/* nucleus context : L=1, size=4M, G=1 */
.xword 0x0000000001c00000, 0x6000000101c00043
.xword 0x0000000002000000, 0xe000000102000043
/* primary context : V=1,0 L=0, size=8k, G=0 */
.xword 0x0000000002080044, 0x8000000102080002
.xword 0x0000000002100044, 0x0000000102100002
/* primary context : L=0, size=8k, G=1 */
.xword 0x0000000002110044, 0x8000000102110003
.xword 0x0000000002120044, 0x0000000102120003
/* primary context : L=0, size=64k, G=0 */
.xword 0x0000000002130044, 0xa000000102130002
.xword 0x0000000002140044, 0x2000000102140002
/* primary context : L=0, size=64k, G=1 */
.xword 0x0000000002150044, 0xa000000102150003
.xword 0x0000000002160044, 0x2000000102160003
/* primary context : L=0, size=512k, G=0 */
.xword 0x0000000002200044, 0xc000000102200002
.xword 0x0000000002280044, 0x4000000102280002
/* primary context : L=0, size=512k, G=1 */
.xword 0x0000000002300044, 0xc000000102300003
.xword 0x0000000002380044, 0x4000000102380003
/* primary context : L=0, size=4M, G=0 */
.xword 0x0000000002400044, 0xe000000102400002
.xword 0x0000000002800044, 0x6000000102800002
/* primary context : L=0, size=4M, G=1 */
.xword 0x0000000002c00044, 0xe000000102c00003
.xword 0x0000000003000044, 0x6000000103000003
/* primary context : V=1,0 L=1, size=8k, G=0 */
.xword 0x0000000003010044, 0x8000000103010042
.xword 0x0000000003018044, 0x0000000103018042
/* primary context : L=1, size=8k, G=1 */
.xword 0x0000000003020044, 0x8000000103020043
.xword 0x0000000003028044, 0x0000000103028043
/* primary context : L=1, size=64k, G=0 */
.xword 0x0000000003030044, 0xa000000103030042
.xword 0x0000000003040044, 0x2000000103040042
/* primary context : L=1, size=64k, G=1 */
.xword 0x0000000003050044, 0xa000000103050043
.xword 0x0000000003060044, 0x2000000103060043
/* primary context : L=1, size=512k, G=0 */
.xword 0x0000000003080044, 0xc000000103080042
.xword 0x0000000003100044, 0x4000000103100042
/* primary context : L=1, size=512k, G=1 */
.xword 0x0000000003180044, 0xc000000103180043
.xword 0x0000000003200044, 0x4000000103200043
/* primary context : L=1, size=4M, G=0 */
.xword 0x0000000003400044, 0xe000000103200042
.xword 0x0000000003800044, 0x6000000103200042
/* primary context : L=1, size=4M, G=1 */
.xword 0x0000000003c00044, 0xe000000103200043
.xword 0x0000000004000044, 0x6000000104000043
/* secondary context : L=0, size=64k, G=0 */
.xword 0x00000000151a0055, 0xa0000001051a0002
.xword 0x00000000151b0055, 0x20000001051b0002
/* secondary context : L=0, size=64k, G=1 */
.xword 0x00000000151c0055, 0xa0000001051c0003
.xword 0x00000000151d0055, 0x20000001051d0003
/* secondary context : L=0, size=512k, G=0 */
.xword 0x0000000010200055, 0xc000000100200002
.xword 0x0000000010280055, 0x4000000100280002
/* secondary context : L=0, size=512k, G=1 */
.xword 0x0000000010300055, 0xc000000100300003
.xword 0x0000000010380055, 0x4000000100380003
/* secondary context : L=0, size=4M, G=0 */
.xword 0x0000000010400055, 0xe000000100400002
.xword 0x0000000010800055, 0x6000000100800002
/* secondary context : L=0, size=4M, G=1 */
.xword 0x0000000010c00055, 0xe00000010c000003
.xword 0x0000000011000055, 0x6000000110000003
/* secondary context : V=1,0 L=1, size=8k, G=0 */
.xword 0x0000000011a10055, 0x8000000101a10042
.xword 0x0000000011a18055, 0x0000000101a18042
/* secondary context : L=1, size=8k, G=1 */
.xword 0x0000000011a20055, 0x8000000101a20043
.xword 0x0000000011a28055, 0x0000000101a28043
.end
| {
"language": "Assembly"
} |
config BR2_PACKAGE_LIBUV
bool "libuv"
depends on BR2_TOOLCHAIN_HAS_THREADS_NPTL # pthread_barrier_*
depends on BR2_USE_MMU # fork()
depends on !BR2_STATIC_LIBS
depends on BR2_TOOLCHAIN_HAS_SYNC_4
help
libuv is a multi-platform support library with a focus
on asynchronous I/O.
https://github.com/libuv/libuv
comment "libuv needs a toolchain w/ NPTL, dynamic library"
depends on !BR2_TOOLCHAIN_HAS_THREADS_NPTL || BR2_STATIC_LIBS
depends on BR2_USE_MMU
depends on BR2_TOOLCHAIN_HAS_SYNC_4
| {
"language": "Assembly"
} |
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs -o - %s | FileCheck %s
define internal void @_GLOBAL__I_a() section ".text.startup" {
ret void
}
@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
; CHECK: .section .init_array
| {
"language": "Assembly"
} |
; RUN: opt -S -loop-vectorize -enable-vplan-native-path -mtriple aarch64-gnu-linux < %s | FileCheck %s
; extern int arr[8][8];
; extern int arr2[8];
;
; void foo(int n)
; {
; int i1, i2;
;
; #pragma clang loop vectorize(enable)
; for (i1 = 0; i1 < 8; i1++) {
; arr2[i1] = i1;
; for (i2 = 0; i2 < 8; i2++)
; arr[i2][i1] = i1 + n;
; }
; }
;
; CHECK-LABEL: @foo_i32(
; CHECK-LABEL: vector.ph:
; CHECK: %[[SplatVal:.*]] = insertelement <4 x i32> undef, i32 %n, i32 0
; CHECK: %[[Splat:.*]] = shufflevector <4 x i32> %[[SplatVal]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-LABEL: vector.body:
; CHECK: %[[Ind:.*]] = phi i64 [ 0, %vector.ph ], [ %[[IndNext:.*]], %[[ForInc:.*]] ]
; CHECK: %[[VecInd:.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %vector.ph ], [ %[[VecIndNext:.*]], %[[ForInc]] ]
; CHECK: %[[AAddr:.*]] = getelementptr inbounds [8 x i32], [8 x i32]* @arr2, i64 0, <4 x i64> %[[VecInd]]
; CHECK: %[[VecIndTr:.*]] = trunc <4 x i64> %[[VecInd]] to <4 x i32>
; CHECK: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %[[VecIndTr]], <4 x i32*> %[[AAddr]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
; CHECK: %[[VecIndTr2:.*]] = trunc <4 x i64> %[[VecInd]] to <4 x i32>
; CHECK: %[[StoreVal:.*]] = add nsw <4 x i32> %[[VecIndTr2]], %[[Splat]]
; CHECK: br label %[[InnerLoop:.+]]
; CHECK: [[InnerLoop]]:
; CHECK: %[[InnerPhi:.*]] = phi <4 x i64> [ %[[InnerPhiNext:.*]], %[[InnerLoop]] ], [ zeroinitializer, %vector.body ]
; CHECK: %[[AAddr2:.*]] = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* @arr, i64 0, <4 x i64> %[[InnerPhi]], <4 x i64> %[[VecInd]]
; CHECK: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %[[StoreVal]], <4 x i32*> %[[AAddr2]], i32 4, <4 x i1> <i1 true, i1 true, i1 true
; CHECK: %[[InnerPhiNext]] = add nuw nsw <4 x i64> %[[InnerPhi]], <i64 1, i64 1, i64 1, i64 1>
; CHECK: %[[VecCond:.*]] = icmp eq <4 x i64> %[[InnerPhiNext]], <i64 8, i64 8, i64 8, i64 8>
; CHECK: %[[InnerCond:.*]] = extractelement <4 x i1> %[[VecCond]], i32 0
; CHECK: br i1 %[[InnerCond]], label %[[ForInc]], label %[[InnerLoop]]
; CHECK: [[ForInc]]:
; CHECK: %[[IndNext]] = add i64 %[[Ind]], 4
; CHECK: %[[VecIndNext]] = add <4 x i64> %[[VecInd]], <i64 4, i64 4, i64 4, i64 4>
; CHECK: %[[Cmp:.*]] = icmp eq i64 %[[IndNext]], 8
; CHECK: br i1 %[[Cmp]], label %middle.block, label %vector.body
@arr2 = external global [8 x i32], align 16
@arr = external global [8 x [8 x i32]], align 16
@arrX = external global [8 x i64], align 16
@arrY = external global [8 x [8 x i64]], align 16
; Function Attrs: norecurse nounwind uwtable
define void @foo_i32(i32 %n) {
entry:
br label %for.body
for.body: ; preds = %for.inc8, %entry
%indvars.iv21 = phi i64 [ 0, %entry ], [ %indvars.iv.next22, %for.inc8 ]
%arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* @arr2, i64 0, i64 %indvars.iv21
%0 = trunc i64 %indvars.iv21 to i32
store i32 %0, i32* %arrayidx, align 4
%1 = trunc i64 %indvars.iv21 to i32
%add = add nsw i32 %1, %n
br label %for.body3
for.body3: ; preds = %for.body3, %for.body
%indvars.iv = phi i64 [ 0, %for.body ], [ %indvars.iv.next, %for.body3 ]
%arrayidx7 = getelementptr inbounds [8 x [8 x i32]], [8 x [8 x i32]]* @arr, i64 0, i64 %indvars.iv, i64 %indvars.iv21
store i32 %add, i32* %arrayidx7, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, 8
br i1 %exitcond, label %for.inc8, label %for.body3
for.inc8: ; preds = %for.body3
%indvars.iv.next22 = add nuw nsw i64 %indvars.iv21, 1
%exitcond23 = icmp eq i64 %indvars.iv.next22, 8
br i1 %exitcond23, label %for.end10, label %for.body, !llvm.loop !1
for.end10: ; preds = %for.inc8
ret void
}
; CHECK-LABEL: @foo_i64(
; CHECK-LABEL: vector.ph:
; CHECK: %[[SplatVal:.*]] = insertelement <2 x i64> undef, i64 %n, i32 0
; CHECK: %[[Splat:.*]] = shufflevector <2 x i64> %[[SplatVal]], <2 x i64> undef, <2 x i32> zeroinitializer
; CHECK-LABEL: vector.body:
; CHECK: %[[Ind:.*]] = phi i64 [ 0, %vector.ph ], [ %[[IndNext:.*]], %[[ForInc:.*]] ]
; CHECK: %[[VecInd:.*]] = phi <2 x i64> [ <i64 0, i64 1>, %vector.ph ], [ %[[VecIndNext:.*]], %[[ForInc]] ]
; CHECK: %[[AAddr:.*]] = getelementptr inbounds [8 x i64], [8 x i64]* @arrX, i64 0, <2 x i64> %[[VecInd]]
; CHECK: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> %[[VecInd]], <2 x i64*> %[[AAddr]], i32 4, <2 x i1> <i1 true, i1 true>)
; CHECK: %[[StoreVal:.*]] = add nsw <2 x i64> %[[VecInd]], %[[Splat]]
; CHECK: br label %[[InnerLoop:.+]]
; CHECK: [[InnerLoop]]:
; CHECK: %[[InnerPhi:.*]] = phi <2 x i64> [ %[[InnerPhiNext:.*]], %[[InnerLoop]] ], [ zeroinitializer, %vector.body ]
; CHECK: %[[AAddr2:.*]] = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @arrY, i64 0, <2 x i64> %[[InnerPhi]], <2 x i64> %[[VecInd]]
; CHECK: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> %[[StoreVal]], <2 x i64*> %[[AAddr2]], i32 4, <2 x i1> <i1 true, i1 true>
; CHECK: %[[InnerPhiNext]] = add nuw nsw <2 x i64> %[[InnerPhi]], <i64 1, i64 1>
; CHECK: %[[VecCond:.*]] = icmp eq <2 x i64> %[[InnerPhiNext]], <i64 8, i64 8>
; CHECK: %[[InnerCond:.*]] = extractelement <2 x i1> %[[VecCond]], i32 0
; CHECK: br i1 %[[InnerCond]], label %[[ForInc]], label %[[InnerLoop]]
; CHECK: [[ForInc]]:
; CHECK: %[[IndNext]] = add i64 %[[Ind]], 2
; CHECK: %[[VecIndNext]] = add <2 x i64> %[[VecInd]], <i64 2, i64 2>
; CHECK: %[[Cmp:.*]] = icmp eq i64 %[[IndNext]], 8
; CHECK: br i1 %[[Cmp]], label %middle.block, label %vector.body
; Function Attrs: norecurse nounwind uwtable
define void @foo_i64(i64 %n) {
entry:
br label %for.body
for.body: ; preds = %for.inc8, %entry
%indvars.iv21 = phi i64 [ 0, %entry ], [ %indvars.iv.next22, %for.inc8 ]
%arrayidx = getelementptr inbounds [8 x i64], [8 x i64]* @arrX, i64 0, i64 %indvars.iv21
store i64 %indvars.iv21, i64* %arrayidx, align 4
%add = add nsw i64 %indvars.iv21, %n
br label %for.body3
for.body3: ; preds = %for.body3, %for.body
%indvars.iv = phi i64 [ 0, %for.body ], [ %indvars.iv.next, %for.body3 ]
%arrayidx7 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* @arrY, i64 0, i64 %indvars.iv, i64 %indvars.iv21
store i64 %add, i64* %arrayidx7, align 4
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%exitcond = icmp eq i64 %indvars.iv.next, 8
br i1 %exitcond, label %for.inc8, label %for.body3
for.inc8: ; preds = %for.body3
%indvars.iv.next22 = add nuw nsw i64 %indvars.iv21, 1
%exitcond23 = icmp eq i64 %indvars.iv.next22, 8
br i1 %exitcond23, label %for.end10, label %for.body, !llvm.loop !1
for.end10: ; preds = %for.inc8
ret void
}
!1 = distinct !{!1, !2}
!2 = !{!"llvm.loop.vectorize.enable", i1 true}
| {
"language": "Assembly"
} |
/**
* Helper classes (floats, clears, colors, blah blah)
* media query specific classes at bottom
*/
/**
* @desc many many many helper classes for all breakpoints
* @returns .{breakpoint}-{property}-{direction}-{size}, example: sm-marg-r-big
*/
// @stylint off
for key, value in ( $directions )
.{value}
{value} 0
.border-{key}
border-{value} $border-micro
.border-{key}-big
border-{value} $border-big
.marg-{key}-25
margin-{value} $gutter-25
.pad-{key}-25
padding-{value} $gutter-25
.marg-{key}-50
margin-{value} $gutter-50
.pad-{key}-50
padding-{value} $gutter-50
for k, v in ( $sizes )
.{value}-{k}
{value} v
.marg-{key}-{k}
margin-{value} v
.pad-{key}-{k}
padding-{value} v
@media $mob
+prefix-classes( 'mob-' )
.marg-{key}-{k}
margin-{value} v
.pad-{key}-{k}
padding-{value} v
@media $sm
+prefix-classes( 'sm-' )
.marg-{key}-{k}
margin-{value} v
.pad-{key}-{k}
padding-{value} v
@media $med
+prefix-classes( 'med-' )
.marg-{key}-{k}
margin-{value} v
.pad-{key}-{k}
padding-{value} v
@media $big-plus
+prefix-classes( 'big-' )
.marg-{key}-{k}
margin-{value} v
.pad-{key}-{k}
padding-{value} v
// @stylint on
// all directions
@media $mob
+prefix-classes( 'mob-' )
.marg
margin $gutter-med
.pad
padding $gutter-med
@media $sm
+prefix-classes( 'sm-' )
.marg
margin $gutter-med
.pad
padding $gutter-med
@media $med
+prefix-classes( 'med-' )
.marg
margin $gutter-med
.pad
padding $gutter-med
@media $big-plus
+prefix-classes( 'big-' )
.marg
margin $gutter-med
.pad
padding $gutter-med
/**
* @desc opacity helperz
* @returns opacity classes
*/
for $i in ( 0..9 )
.opacity-{$i}
opacity $i * .1
/**
* @desc grayscale helperz
* @returns gray classes
*/
for $key, $value in $grays
.bg-gray-{$key}
background-color $value
.gray-{$key}
color $value
/**
* @desc section color helperz
* @returns color classes for the 6 section colors
*/
for $key, $value in $section-colors
.bg-{$key}
background-color $value
.color-{$key}
color $value
// force a thing to be absolute positioned
.absolute
position absolute
// or have a white bg
.bg-white
background-color $white
// this is a border. yes, that's what that looks like
.border
border $border-micro
// another one!
// @TODO this is dumb, was faked up for design, remove
.border-darker
border 1px solid #ccc
// default box-shadow used on cards, header
.box-shadow
box-shadow $depth-1
// box-shadow, creates the illusion of depth
.box-shadow-2
box-shadow $depth-2
// box-shadow, creates the illusion of depth, use only on highest elements
.box-shadow-3
box-shadow $depth-3
// make a thing a button
.button
@extends $button-base
// centers an element, doesnt interfere with vertical margin
.center
@extends $center
// change shape of element into circle
.circle
border-radius 50%
// clearfix class version, break those floats
.clearfix
@extends $clearfix
// float an item to the left, only above mobile
.float-l
float left
// float an item to the right, only above mobile
.float-r
float right
// force hide
.hide
display none !important
opacity 0
// make a thing inline-block
.inline-block
display inline-block
/**
* just adds an opacity transition (opacity accelerated by default)
*/
.fade
transition( opacity, .35s, false )
// fixed position
.fixed
position fixed
/**
* used when we want to combine transitions with display none or display block
* @requires prepareTransition jQuery plugin
*/
.is-transitioning
display block !important
visibility visible !important
// Link underline helper class
.link-underline
a
@extends $link-underline
// Link underline helper class
.link-underline-sm
a
@extends $link-underline-sm
// Dark link underline class
.link-underline-dark
a
@extends $link-underline-dark
// Dark link underline class
.link-underline-dark-sm
a
@extends $link-underline-dark-sm
// No underline
.no-underline
a
@extends $no-underline
// remove list styles from article lists
.list-none
list-style none !important
li:before
content '' !important
margin 0 !important
width 0 !important
// marginz all around
.marg
margin $gutter-med
// sm margins all around
.marg-sm
margin $gutter-sm
// remove style helpers
.no-border
border 0 !important
// force no margins
.no-marg
margin 0 !important
// force no padding
.no-pad
padding 0 !important
// no scroll (literally, no scrollbar no scrollin)
.no-scroll,
.overflow-hide
overflow hidden
// padding all around
.pad-sm
padding $gutter-sm
// padding all around
.pad
padding $gutter-med
// add relative to a thing
.relative
position relative
// force show
.show
display block !important
opacity 1
// center item, set width to max-width of site
.site-container
site-container()
// collapse smart card but not on mobile
.squish
@media $mob-plus
{squish}
// text align center
.text-c
text-align center
// text align right
.text-r
text-align right
// text align left
.text-l
text-align left
// same with you @TODO
.sm-thumb
float left
height 50px
max-width 50px
// hmmm @TODO could be cleaned up a bit
.thumb
float left
height 75px
max-width 75px
width calc( 33% - 11.667px )
// class version for applying via js or whatever
.visually-hidden
@extends $visually-hidden
// force a thing to be white
.white
color $white
// mobile > small tablet helpers
@media $mob
.float-l-mob
float left
.float-r-mob
float right
.hide-mob
display none !important
.show-mob
display block
.no-float-mob
float none !important
.squish-mob
{squish}
// small tablet only helpers
@media $sm
.hide-sm
display none !important
.show-sm
display block
.float-l-sm
float left
.float-r-sm
float right
.no-float-sm
float none !important
.squish-sm
{squish}
// big tablet only helpers
@media $med
.hide-med
display none !important
.show-med
display block
.float-l-med
float left
.float-r-med
float right
.no-float-med
float none !important
.squish-med
{squish}
// below 800px tall
@media $short
.hide-short
display none !important
.show-short
display block
.squish-short
{squish}
// below 1000px tall
@media $tall
.hide-tall-tab
display none !important
.show-tall-tab
display block
.squish-tall-tab
{squish}
// tablet and below 800px tall
@media $short-tab
.hide-short-tab
display none !important
.show-short-tab
display block
.squish-short-tab
{squish}
// tablet and below 1000px tall
@media $tall-tab
.hide-tall-tab
display none !important
.show-tall-tab
display block
.squish-tall-tab
{squish}
// desktop helpers
@media $big-plus
.hide-big
display none !important
.show-big
display block
.float-l-big
float left
.float-r-big
float right
.no-float-big
float none !important
.squish-big
{squish}
| {
"language": "Assembly"
} |
// RUN: %clang_cc1 -emit-llvm < %s | grep i1 | count 1
// Check that the type of this global isn't i1
_Bool test = &test;
| {
"language": "Assembly"
} |
#!/usr/bin/env perl
##############################################################################
# #
# Copyright (c) 2012, Intel Corporation #
# #
# All rights reserved. #
# #
# Redistribution and use in source and binary forms, with or without #
# modification, are permitted provided that the following conditions are #
# met: #
# #
# * Redistributions of source code must retain the above copyright #
# notice, this list of conditions and the following disclaimer. #
# #
# * Redistributions in binary form must reproduce the above copyright #
# notice, this list of conditions and the following disclaimer in the #
# documentation and/or other materials provided with the #
# distribution. #
# #
# * Neither the name of the Intel Corporation nor the names of its #
# contributors may be used to endorse or promote products derived from #
# this software without specific prior written permission. #
# #
# #
# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY #
# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE #
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR #
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR #
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, #
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR #
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF #
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS #
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #
# #
##############################################################################
# Developers and authors: #
# Shay Gueron (1, 2), and Vlad Krasnov (1) #
# (1) Intel Corporation, Israel Development Center, Haifa, Israel #
# (2) University of Haifa, Israel #
##############################################################################
# Reference: #
# [1] S. Gueron, V. Krasnov: "Software Implementation of Modular #
# Exponentiation, Using Advanced Vector Instructions Architectures", #
# F. Ozbudak and F. Rodriguez-Henriquez (Eds.): WAIFI 2012, LNCS 7369, #
# pp. 119?135, 2012. Springer-Verlag Berlin Heidelberg 2012 #
# [2] S. Gueron: "Efficient Software Implementations of Modular #
# Exponentiation", Journal of Cryptographic Engineering 2:31-43 (2012). #
# [3] S. Gueron, V. Krasnov: "Speeding up Big-numbers Squaring",IEEE #
# Proceedings of 9th International Conference on Information Technology: #
# New Generations (ITNG 2012), pp.821-823 (2012) #
# [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis #
# resistant 1024-bit modular exponentiation, for optimizing RSA2048 #
# on AVX2 capable x86_64 platforms", #
# http://rt.openssl.org/Ticket/Display.html?id=2850&user=guest&pass=guest#
##############################################################################
#
# +13% improvement over original submission by <appro@openssl.org>
#
# rsa2048 sign/sec OpenSSL 1.0.1 scalar(*) this
# 2.3GHz Haswell 621 765/+23% 1113/+79%
# 2.3GHz Broadwell(**) 688 1200(***)/+74% 1120/+63%
#
# (*) if system doesn't support AVX2, for reference purposes;
# (**) scaled to 2.3GHz to simplify comparison;
# (***) scalar AD*X code is faster than AVX2 and is preferred code
# path for Broadwell;
$flavour = shift;
$output = shift;
if ($flavour =~ /\./) { $output = $flavour; undef $flavour; }
$win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/);
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or
( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or
die "can't locate x86_64-xlate.pl";
if (`$ENV{CC} -Wa,-v -c -o /dev/null -x assembler /dev/null 2>&1`
=~ /GNU assembler version ([2-9]\.[0-9]+)/) {
$avx = ($1>=2.19) + ($1>=2.22);
$addx = ($1>=2.23);
}
if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
`nasm -v 2>&1` =~ /NASM version ([2-9]\.[0-9]+)/) {
$avx = ($1>=2.09) + ($1>=2.10);
$addx = ($1>=2.10);
}
if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
`ml64 2>&1` =~ /Version ([0-9]+)\./) {
$avx = ($1>=10) + ($1>=11);
$addx = ($1>=11);
}
if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9])\.([0-9]+)/) {
my $ver = $2 + $3/100.0; # 3.1->3.01, 3.10->3.10
$avx = ($ver>=3.0) + ($ver>=3.01);
$addx = ($ver>=3.03);
}
open OUT,"| \"$^X\" $xlate $flavour $output";
*STDOUT = *OUT;
if ($avx>1) {{{
{ # void AMS_WW(
my $rp="%rdi"; # BN_ULONG *rp,
my $ap="%rsi"; # const BN_ULONG *ap,
my $np="%rdx"; # const BN_ULONG *np,
my $n0="%ecx"; # const BN_ULONG n0,
my $rep="%r8d"; # int repeat);
# The registers that hold the accumulated redundant result
# The AMM works on 1024 bit operands, and redundant word size is 29
# Therefore: ceil(1024/29)/4 = 9
my $ACC0="%ymm0";
my $ACC1="%ymm1";
my $ACC2="%ymm2";
my $ACC3="%ymm3";
my $ACC4="%ymm4";
my $ACC5="%ymm5";
my $ACC6="%ymm6";
my $ACC7="%ymm7";
my $ACC8="%ymm8";
my $ACC9="%ymm9";
# Registers that hold the broadcasted words of bp, currently used
my $B1="%ymm10";
my $B2="%ymm11";
# Registers that hold the broadcasted words of Y, currently used
my $Y1="%ymm12";
my $Y2="%ymm13";
# Helper registers
my $TEMP1="%ymm14";
my $AND_MASK="%ymm15";
# alu registers that hold the first words of the ACC
my $r0="%r9";
my $r1="%r10";
my $r2="%r11";
my $r3="%r12";
my $i="%r14d"; # loop counter
my $tmp = "%r15";
my $FrameSize=32*18+32*8; # place for A^2 and 2*A
my $aap=$r0;
my $tp0="%rbx";
my $tp1=$r3;
my $tpa=$tmp;
$np="%r13"; # reassigned argument
$code.=<<___;
.text
.globl rsaz_1024_sqr_avx2
.type rsaz_1024_sqr_avx2,\@function,5
.align 64
rsaz_1024_sqr_avx2: # 702 cycles, 14% faster than rsaz_1024_mul_avx2
lea (%rsp), %rax
push %rbx
push %rbp
push %r12
push %r13
push %r14
push %r15
vzeroupper
___
$code.=<<___ if ($win64);
lea -0xa8(%rsp),%rsp
vmovaps %xmm6,-0xd8(%rax)
vmovaps %xmm7,-0xc8(%rax)
vmovaps %xmm8,-0xb8(%rax)
vmovaps %xmm9,-0xa8(%rax)
vmovaps %xmm10,-0x98(%rax)
vmovaps %xmm11,-0x88(%rax)
vmovaps %xmm12,-0x78(%rax)
vmovaps %xmm13,-0x68(%rax)
vmovaps %xmm14,-0x58(%rax)
vmovaps %xmm15,-0x48(%rax)
.Lsqr_1024_body:
___
$code.=<<___;
mov %rax,%rbp
mov %rdx, $np # reassigned argument
sub \$$FrameSize, %rsp
mov $np, $tmp
sub \$-128, $rp # size optimization
sub \$-128, $ap
sub \$-128, $np
and \$4095, $tmp # see if $np crosses page
add \$32*10, $tmp
shr \$12, $tmp
vpxor $ACC9,$ACC9,$ACC9
jz .Lsqr_1024_no_n_copy
# unaligned 256-bit load that crosses page boundary can
# cause >2x performance degradation here, so if $np does
# cross page boundary, copy it to stack and make sure stack
# frame doesn't...
sub \$32*10,%rsp
vmovdqu 32*0-128($np), $ACC0
and \$-2048, %rsp
vmovdqu 32*1-128($np), $ACC1
vmovdqu 32*2-128($np), $ACC2
vmovdqu 32*3-128($np), $ACC3
vmovdqu 32*4-128($np), $ACC4
vmovdqu 32*5-128($np), $ACC5
vmovdqu 32*6-128($np), $ACC6
vmovdqu 32*7-128($np), $ACC7
vmovdqu 32*8-128($np), $ACC8
lea $FrameSize+128(%rsp),$np
vmovdqu $ACC0, 32*0-128($np)
vmovdqu $ACC1, 32*1-128($np)
vmovdqu $ACC2, 32*2-128($np)
vmovdqu $ACC3, 32*3-128($np)
vmovdqu $ACC4, 32*4-128($np)
vmovdqu $ACC5, 32*5-128($np)
vmovdqu $ACC6, 32*6-128($np)
vmovdqu $ACC7, 32*7-128($np)
vmovdqu $ACC8, 32*8-128($np)
vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero
.Lsqr_1024_no_n_copy:
and \$-1024, %rsp
vmovdqu 32*1-128($ap), $ACC1
vmovdqu 32*2-128($ap), $ACC2
vmovdqu 32*3-128($ap), $ACC3
vmovdqu 32*4-128($ap), $ACC4
vmovdqu 32*5-128($ap), $ACC5
vmovdqu 32*6-128($ap), $ACC6
vmovdqu 32*7-128($ap), $ACC7
vmovdqu 32*8-128($ap), $ACC8
lea 192(%rsp), $tp0 # 64+128=192
vpbroadcastq .Land_mask(%rip), $AND_MASK
jmp .LOOP_GRANDE_SQR_1024
.align 32
.LOOP_GRANDE_SQR_1024:
lea 32*18+128(%rsp), $aap # size optimization
lea 448(%rsp), $tp1 # 64+128+256=448
# the squaring is performed as described in Variant B of
# "Speeding up Big-Number Squaring", so start by calculating
# the A*2=A+A vector
vpaddq $ACC1, $ACC1, $ACC1
vpbroadcastq 32*0-128($ap), $B1
vpaddq $ACC2, $ACC2, $ACC2
vmovdqa $ACC1, 32*0-128($aap)
vpaddq $ACC3, $ACC3, $ACC3
vmovdqa $ACC2, 32*1-128($aap)
vpaddq $ACC4, $ACC4, $ACC4
vmovdqa $ACC3, 32*2-128($aap)
vpaddq $ACC5, $ACC5, $ACC5
vmovdqa $ACC4, 32*3-128($aap)
vpaddq $ACC6, $ACC6, $ACC6
vmovdqa $ACC5, 32*4-128($aap)
vpaddq $ACC7, $ACC7, $ACC7
vmovdqa $ACC6, 32*5-128($aap)
vpaddq $ACC8, $ACC8, $ACC8
vmovdqa $ACC7, 32*6-128($aap)
vpxor $ACC9, $ACC9, $ACC9
vmovdqa $ACC8, 32*7-128($aap)
vpmuludq 32*0-128($ap), $B1, $ACC0
vpbroadcastq 32*1-128($ap), $B2
vmovdqu $ACC9, 32*9-192($tp0) # zero upper half
vpmuludq $B1, $ACC1, $ACC1
vmovdqu $ACC9, 32*10-448($tp1)
vpmuludq $B1, $ACC2, $ACC2
vmovdqu $ACC9, 32*11-448($tp1)
vpmuludq $B1, $ACC3, $ACC3
vmovdqu $ACC9, 32*12-448($tp1)
vpmuludq $B1, $ACC4, $ACC4
vmovdqu $ACC9, 32*13-448($tp1)
vpmuludq $B1, $ACC5, $ACC5
vmovdqu $ACC9, 32*14-448($tp1)
vpmuludq $B1, $ACC6, $ACC6
vmovdqu $ACC9, 32*15-448($tp1)
vpmuludq $B1, $ACC7, $ACC7
vmovdqu $ACC9, 32*16-448($tp1)
vpmuludq $B1, $ACC8, $ACC8
vpbroadcastq 32*2-128($ap), $B1
vmovdqu $ACC9, 32*17-448($tp1)
mov $ap, $tpa
mov \$4, $i
jmp .Lsqr_entry_1024
___
$TEMP0=$Y1;
$TEMP2=$Y2;
$code.=<<___;
.align 32
.LOOP_SQR_1024:
vpbroadcastq 32*1-128($tpa), $B2
vpmuludq 32*0-128($ap), $B1, $ACC0
vpaddq 32*0-192($tp0), $ACC0, $ACC0
vpmuludq 32*0-128($aap), $B1, $ACC1
vpaddq 32*1-192($tp0), $ACC1, $ACC1
vpmuludq 32*1-128($aap), $B1, $ACC2
vpaddq 32*2-192($tp0), $ACC2, $ACC2
vpmuludq 32*2-128($aap), $B1, $ACC3
vpaddq 32*3-192($tp0), $ACC3, $ACC3
vpmuludq 32*3-128($aap), $B1, $ACC4
vpaddq 32*4-192($tp0), $ACC4, $ACC4
vpmuludq 32*4-128($aap), $B1, $ACC5
vpaddq 32*5-192($tp0), $ACC5, $ACC5
vpmuludq 32*5-128($aap), $B1, $ACC6
vpaddq 32*6-192($tp0), $ACC6, $ACC6
vpmuludq 32*6-128($aap), $B1, $ACC7
vpaddq 32*7-192($tp0), $ACC7, $ACC7
vpmuludq 32*7-128($aap), $B1, $ACC8
vpbroadcastq 32*2-128($tpa), $B1
vpaddq 32*8-192($tp0), $ACC8, $ACC8
.Lsqr_entry_1024:
vmovdqu $ACC0, 32*0-192($tp0)
vmovdqu $ACC1, 32*1-192($tp0)
vpmuludq 32*1-128($ap), $B2, $TEMP0
vpaddq $TEMP0, $ACC2, $ACC2
vpmuludq 32*1-128($aap), $B2, $TEMP1
vpaddq $TEMP1, $ACC3, $ACC3
vpmuludq 32*2-128($aap), $B2, $TEMP2
vpaddq $TEMP2, $ACC4, $ACC4
vpmuludq 32*3-128($aap), $B2, $TEMP0
vpaddq $TEMP0, $ACC5, $ACC5
vpmuludq 32*4-128($aap), $B2, $TEMP1
vpaddq $TEMP1, $ACC6, $ACC6
vpmuludq 32*5-128($aap), $B2, $TEMP2
vpaddq $TEMP2, $ACC7, $ACC7
vpmuludq 32*6-128($aap), $B2, $TEMP0
vpaddq $TEMP0, $ACC8, $ACC8
vpmuludq 32*7-128($aap), $B2, $ACC0
vpbroadcastq 32*3-128($tpa), $B2
vpaddq 32*9-192($tp0), $ACC0, $ACC0
vmovdqu $ACC2, 32*2-192($tp0)
vmovdqu $ACC3, 32*3-192($tp0)
vpmuludq 32*2-128($ap), $B1, $TEMP2
vpaddq $TEMP2, $ACC4, $ACC4
vpmuludq 32*2-128($aap), $B1, $TEMP0
vpaddq $TEMP0, $ACC5, $ACC5
vpmuludq 32*3-128($aap), $B1, $TEMP1
vpaddq $TEMP1, $ACC6, $ACC6
vpmuludq 32*4-128($aap), $B1, $TEMP2
vpaddq $TEMP2, $ACC7, $ACC7
vpmuludq 32*5-128($aap), $B1, $TEMP0
vpaddq $TEMP0, $ACC8, $ACC8
vpmuludq 32*6-128($aap), $B1, $TEMP1
vpaddq $TEMP1, $ACC0, $ACC0
vpmuludq 32*7-128($aap), $B1, $ACC1
vpbroadcastq 32*4-128($tpa), $B1
vpaddq 32*10-448($tp1), $ACC1, $ACC1
vmovdqu $ACC4, 32*4-192($tp0)
vmovdqu $ACC5, 32*5-192($tp0)
vpmuludq 32*3-128($ap), $B2, $TEMP0
vpaddq $TEMP0, $ACC6, $ACC6
vpmuludq 32*3-128($aap), $B2, $TEMP1
vpaddq $TEMP1, $ACC7, $ACC7
vpmuludq 32*4-128($aap), $B2, $TEMP2
vpaddq $TEMP2, $ACC8, $ACC8
vpmuludq 32*5-128($aap), $B2, $TEMP0
vpaddq $TEMP0, $ACC0, $ACC0
vpmuludq 32*6-128($aap), $B2, $TEMP1
vpaddq $TEMP1, $ACC1, $ACC1
vpmuludq 32*7-128($aap), $B2, $ACC2
vpbroadcastq 32*5-128($tpa), $B2
vpaddq 32*11-448($tp1), $ACC2, $ACC2
vmovdqu $ACC6, 32*6-192($tp0)
vmovdqu $ACC7, 32*7-192($tp0)
vpmuludq 32*4-128($ap), $B1, $TEMP0
vpaddq $TEMP0, $ACC8, $ACC8
vpmuludq 32*4-128($aap), $B1, $TEMP1
vpaddq $TEMP1, $ACC0, $ACC0
vpmuludq 32*5-128($aap), $B1, $TEMP2
vpaddq $TEMP2, $ACC1, $ACC1
vpmuludq 32*6-128($aap), $B1, $TEMP0
vpaddq $TEMP0, $ACC2, $ACC2
vpmuludq 32*7-128($aap), $B1, $ACC3
vpbroadcastq 32*6-128($tpa), $B1
vpaddq 32*12-448($tp1), $ACC3, $ACC3
vmovdqu $ACC8, 32*8-192($tp0)
vmovdqu $ACC0, 32*9-192($tp0)
lea 8($tp0), $tp0
vpmuludq 32*5-128($ap), $B2, $TEMP2
vpaddq $TEMP2, $ACC1, $ACC1
vpmuludq 32*5-128($aap), $B2, $TEMP0
vpaddq $TEMP0, $ACC2, $ACC2
vpmuludq 32*6-128($aap), $B2, $TEMP1
vpaddq $TEMP1, $ACC3, $ACC3
vpmuludq 32*7-128($aap), $B2, $ACC4
vpbroadcastq 32*7-128($tpa), $B2
vpaddq 32*13-448($tp1), $ACC4, $ACC4
vmovdqu $ACC1, 32*10-448($tp1)
vmovdqu $ACC2, 32*11-448($tp1)
vpmuludq 32*6-128($ap), $B1, $TEMP0
vpaddq $TEMP0, $ACC3, $ACC3
vpmuludq 32*6-128($aap), $B1, $TEMP1
vpbroadcastq 32*8-128($tpa), $ACC0 # borrow $ACC0 for $B1
vpaddq $TEMP1, $ACC4, $ACC4
vpmuludq 32*7-128($aap), $B1, $ACC5
vpbroadcastq 32*0+8-128($tpa), $B1 # for next iteration
vpaddq 32*14-448($tp1), $ACC5, $ACC5
vmovdqu $ACC3, 32*12-448($tp1)
vmovdqu $ACC4, 32*13-448($tp1)
lea 8($tpa), $tpa
vpmuludq 32*7-128($ap), $B2, $TEMP0
vpaddq $TEMP0, $ACC5, $ACC5
vpmuludq 32*7-128($aap), $B2, $ACC6
vpaddq 32*15-448($tp1), $ACC6, $ACC6
vpmuludq 32*8-128($ap), $ACC0, $ACC7
vmovdqu $ACC5, 32*14-448($tp1)
vpaddq 32*16-448($tp1), $ACC7, $ACC7
vmovdqu $ACC6, 32*15-448($tp1)
vmovdqu $ACC7, 32*16-448($tp1)
lea 8($tp1), $tp1
dec $i
jnz .LOOP_SQR_1024
___
$ZERO = $ACC9;
$TEMP0 = $B1;
$TEMP2 = $B2;
$TEMP3 = $Y1;
$TEMP4 = $Y2;
$code.=<<___;
# we need to fix indices 32-39 to avoid overflow
vmovdqu 32*8(%rsp), $ACC8 # 32*8-192($tp0),
vmovdqu 32*9(%rsp), $ACC1 # 32*9-192($tp0)
vmovdqu 32*10(%rsp), $ACC2 # 32*10-192($tp0)
lea 192(%rsp), $tp0 # 64+128=192
vpsrlq \$29, $ACC8, $TEMP1
vpand $AND_MASK, $ACC8, $ACC8
vpsrlq \$29, $ACC1, $TEMP2
vpand $AND_MASK, $ACC1, $ACC1
vpermq \$0x93, $TEMP1, $TEMP1
vpxor $ZERO, $ZERO, $ZERO
vpermq \$0x93, $TEMP2, $TEMP2
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC8, $ACC8
vpblendd \$3, $TEMP2, $ZERO, $TEMP2
vpaddq $TEMP1, $ACC1, $ACC1
vpaddq $TEMP2, $ACC2, $ACC2
vmovdqu $ACC1, 32*9-192($tp0)
vmovdqu $ACC2, 32*10-192($tp0)
mov (%rsp), %rax
mov 8(%rsp), $r1
mov 16(%rsp), $r2
mov 24(%rsp), $r3
vmovdqu 32*1(%rsp), $ACC1
vmovdqu 32*2-192($tp0), $ACC2
vmovdqu 32*3-192($tp0), $ACC3
vmovdqu 32*4-192($tp0), $ACC4
vmovdqu 32*5-192($tp0), $ACC5
vmovdqu 32*6-192($tp0), $ACC6
vmovdqu 32*7-192($tp0), $ACC7
mov %rax, $r0
imull $n0, %eax
and \$0x1fffffff, %eax
vmovd %eax, $Y1
mov %rax, %rdx
imulq -128($np), %rax
vpbroadcastq $Y1, $Y1
add %rax, $r0
mov %rdx, %rax
imulq 8-128($np), %rax
shr \$29, $r0
add %rax, $r1
mov %rdx, %rax
imulq 16-128($np), %rax
add $r0, $r1
add %rax, $r2
imulq 24-128($np), %rdx
add %rdx, $r3
mov $r1, %rax
imull $n0, %eax
and \$0x1fffffff, %eax
mov \$9, $i
jmp .LOOP_REDUCE_1024
.align 32
.LOOP_REDUCE_1024:
vmovd %eax, $Y2
vpbroadcastq $Y2, $Y2
vpmuludq 32*1-128($np), $Y1, $TEMP0
mov %rax, %rdx
imulq -128($np), %rax
vpaddq $TEMP0, $ACC1, $ACC1
add %rax, $r1
vpmuludq 32*2-128($np), $Y1, $TEMP1
mov %rdx, %rax
imulq 8-128($np), %rax
vpaddq $TEMP1, $ACC2, $ACC2
vpmuludq 32*3-128($np), $Y1, $TEMP2
.byte 0x67
add %rax, $r2
.byte 0x67
mov %rdx, %rax
imulq 16-128($np), %rax
shr \$29, $r1
vpaddq $TEMP2, $ACC3, $ACC3
vpmuludq 32*4-128($np), $Y1, $TEMP0
add %rax, $r3
add $r1, $r2
vpaddq $TEMP0, $ACC4, $ACC4
vpmuludq 32*5-128($np), $Y1, $TEMP1
mov $r2, %rax
imull $n0, %eax
vpaddq $TEMP1, $ACC5, $ACC5
vpmuludq 32*6-128($np), $Y1, $TEMP2
and \$0x1fffffff, %eax
vpaddq $TEMP2, $ACC6, $ACC6
vpmuludq 32*7-128($np), $Y1, $TEMP0
vpaddq $TEMP0, $ACC7, $ACC7
vpmuludq 32*8-128($np), $Y1, $TEMP1
vmovd %eax, $Y1
#vmovdqu 32*1-8-128($np), $TEMP2 # moved below
vpaddq $TEMP1, $ACC8, $ACC8
#vmovdqu 32*2-8-128($np), $TEMP0 # moved below
vpbroadcastq $Y1, $Y1
vpmuludq 32*1-8-128($np), $Y2, $TEMP2 # see above
vmovdqu 32*3-8-128($np), $TEMP1
mov %rax, %rdx
imulq -128($np), %rax
vpaddq $TEMP2, $ACC1, $ACC1
vpmuludq 32*2-8-128($np), $Y2, $TEMP0 # see above
vmovdqu 32*4-8-128($np), $TEMP2
add %rax, $r2
mov %rdx, %rax
imulq 8-128($np), %rax
vpaddq $TEMP0, $ACC2, $ACC2
add $r3, %rax
shr \$29, $r2
vpmuludq $Y2, $TEMP1, $TEMP1
vmovdqu 32*5-8-128($np), $TEMP0
add $r2, %rax
vpaddq $TEMP1, $ACC3, $ACC3
vpmuludq $Y2, $TEMP2, $TEMP2
vmovdqu 32*6-8-128($np), $TEMP1
.byte 0x67
mov %rax, $r3
imull $n0, %eax
vpaddq $TEMP2, $ACC4, $ACC4
vpmuludq $Y2, $TEMP0, $TEMP0
.byte 0xc4,0x41,0x7e,0x6f,0x9d,0x58,0x00,0x00,0x00 # vmovdqu 32*7-8-128($np), $TEMP2
and \$0x1fffffff, %eax
vpaddq $TEMP0, $ACC5, $ACC5
vpmuludq $Y2, $TEMP1, $TEMP1
vmovdqu 32*8-8-128($np), $TEMP0
vpaddq $TEMP1, $ACC6, $ACC6
vpmuludq $Y2, $TEMP2, $TEMP2
vmovdqu 32*9-8-128($np), $ACC9
vmovd %eax, $ACC0 # borrow ACC0 for Y2
imulq -128($np), %rax
vpaddq $TEMP2, $ACC7, $ACC7
vpmuludq $Y2, $TEMP0, $TEMP0
vmovdqu 32*1-16-128($np), $TEMP1
vpbroadcastq $ACC0, $ACC0
vpaddq $TEMP0, $ACC8, $ACC8
vpmuludq $Y2, $ACC9, $ACC9
vmovdqu 32*2-16-128($np), $TEMP2
add %rax, $r3
___
($ACC0,$Y2)=($Y2,$ACC0);
$code.=<<___;
vmovdqu 32*1-24-128($np), $ACC0
vpmuludq $Y1, $TEMP1, $TEMP1
vmovdqu 32*3-16-128($np), $TEMP0
vpaddq $TEMP1, $ACC1, $ACC1
vpmuludq $Y2, $ACC0, $ACC0
vpmuludq $Y1, $TEMP2, $TEMP2
.byte 0xc4,0x41,0x7e,0x6f,0xb5,0xf0,0xff,0xff,0xff # vmovdqu 32*4-16-128($np), $TEMP1
vpaddq $ACC1, $ACC0, $ACC0
vpaddq $TEMP2, $ACC2, $ACC2
vpmuludq $Y1, $TEMP0, $TEMP0
vmovdqu 32*5-16-128($np), $TEMP2
.byte 0x67
vmovq $ACC0, %rax
vmovdqu $ACC0, (%rsp) # transfer $r0-$r3
vpaddq $TEMP0, $ACC3, $ACC3
vpmuludq $Y1, $TEMP1, $TEMP1
vmovdqu 32*6-16-128($np), $TEMP0
vpaddq $TEMP1, $ACC4, $ACC4
vpmuludq $Y1, $TEMP2, $TEMP2
vmovdqu 32*7-16-128($np), $TEMP1
vpaddq $TEMP2, $ACC5, $ACC5
vpmuludq $Y1, $TEMP0, $TEMP0
vmovdqu 32*8-16-128($np), $TEMP2
vpaddq $TEMP0, $ACC6, $ACC6
vpmuludq $Y1, $TEMP1, $TEMP1
shr \$29, $r3
vmovdqu 32*9-16-128($np), $TEMP0
add $r3, %rax
vpaddq $TEMP1, $ACC7, $ACC7
vpmuludq $Y1, $TEMP2, $TEMP2
#vmovdqu 32*2-24-128($np), $TEMP1 # moved below
mov %rax, $r0
imull $n0, %eax
vpaddq $TEMP2, $ACC8, $ACC8
vpmuludq $Y1, $TEMP0, $TEMP0
and \$0x1fffffff, %eax
vmovd %eax, $Y1
vmovdqu 32*3-24-128($np), $TEMP2
.byte 0x67
vpaddq $TEMP0, $ACC9, $ACC9
vpbroadcastq $Y1, $Y1
vpmuludq 32*2-24-128($np), $Y2, $TEMP1 # see above
vmovdqu 32*4-24-128($np), $TEMP0
mov %rax, %rdx
imulq -128($np), %rax
mov 8(%rsp), $r1
vpaddq $TEMP1, $ACC2, $ACC1
vpmuludq $Y2, $TEMP2, $TEMP2
vmovdqu 32*5-24-128($np), $TEMP1
add %rax, $r0
mov %rdx, %rax
imulq 8-128($np), %rax
.byte 0x67
shr \$29, $r0
mov 16(%rsp), $r2
vpaddq $TEMP2, $ACC3, $ACC2
vpmuludq $Y2, $TEMP0, $TEMP0
vmovdqu 32*6-24-128($np), $TEMP2
add %rax, $r1
mov %rdx, %rax
imulq 16-128($np), %rax
vpaddq $TEMP0, $ACC4, $ACC3
vpmuludq $Y2, $TEMP1, $TEMP1
vmovdqu 32*7-24-128($np), $TEMP0
imulq 24-128($np), %rdx # future $r3
add %rax, $r2
lea ($r0,$r1), %rax
vpaddq $TEMP1, $ACC5, $ACC4
vpmuludq $Y2, $TEMP2, $TEMP2
vmovdqu 32*8-24-128($np), $TEMP1
mov %rax, $r1
imull $n0, %eax
vpmuludq $Y2, $TEMP0, $TEMP0
vpaddq $TEMP2, $ACC6, $ACC5
vmovdqu 32*9-24-128($np), $TEMP2
and \$0x1fffffff, %eax
vpaddq $TEMP0, $ACC7, $ACC6
vpmuludq $Y2, $TEMP1, $TEMP1
add 24(%rsp), %rdx
vpaddq $TEMP1, $ACC8, $ACC7
vpmuludq $Y2, $TEMP2, $TEMP2
vpaddq $TEMP2, $ACC9, $ACC8
vmovq $r3, $ACC9
mov %rdx, $r3
dec $i
jnz .LOOP_REDUCE_1024
___
($ACC0,$Y2)=($Y2,$ACC0);
$code.=<<___;
lea 448(%rsp), $tp1 # size optimization
vpaddq $ACC9, $Y2, $ACC0
vpxor $ZERO, $ZERO, $ZERO
vpaddq 32*9-192($tp0), $ACC0, $ACC0
vpaddq 32*10-448($tp1), $ACC1, $ACC1
vpaddq 32*11-448($tp1), $ACC2, $ACC2
vpaddq 32*12-448($tp1), $ACC3, $ACC3
vpaddq 32*13-448($tp1), $ACC4, $ACC4
vpaddq 32*14-448($tp1), $ACC5, $ACC5
vpaddq 32*15-448($tp1), $ACC6, $ACC6
vpaddq 32*16-448($tp1), $ACC7, $ACC7
vpaddq 32*17-448($tp1), $ACC8, $ACC8
vpsrlq \$29, $ACC0, $TEMP1
vpand $AND_MASK, $ACC0, $ACC0
vpsrlq \$29, $ACC1, $TEMP2
vpand $AND_MASK, $ACC1, $ACC1
vpsrlq \$29, $ACC2, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC2, $ACC2
vpsrlq \$29, $ACC3, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC3, $ACC3
vpermq \$0x93, $TEMP3, $TEMP3
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC0, $ACC0
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC1, $ACC1
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC2, $ACC2
vpblendd \$3, $TEMP4, $ZERO, $TEMP4
vpaddq $TEMP3, $ACC3, $ACC3
vpaddq $TEMP4, $ACC4, $ACC4
vpsrlq \$29, $ACC0, $TEMP1
vpand $AND_MASK, $ACC0, $ACC0
vpsrlq \$29, $ACC1, $TEMP2
vpand $AND_MASK, $ACC1, $ACC1
vpsrlq \$29, $ACC2, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC2, $ACC2
vpsrlq \$29, $ACC3, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC3, $ACC3
vpermq \$0x93, $TEMP3, $TEMP3
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC0, $ACC0
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC1, $ACC1
vmovdqu $ACC0, 32*0-128($rp)
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC2, $ACC2
vmovdqu $ACC1, 32*1-128($rp)
vpblendd \$3, $TEMP4, $ZERO, $TEMP4
vpaddq $TEMP3, $ACC3, $ACC3
vmovdqu $ACC2, 32*2-128($rp)
vpaddq $TEMP4, $ACC4, $ACC4
vmovdqu $ACC3, 32*3-128($rp)
___
$TEMP5=$ACC0;
$code.=<<___;
vpsrlq \$29, $ACC4, $TEMP1
vpand $AND_MASK, $ACC4, $ACC4
vpsrlq \$29, $ACC5, $TEMP2
vpand $AND_MASK, $ACC5, $ACC5
vpsrlq \$29, $ACC6, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC6, $ACC6
vpsrlq \$29, $ACC7, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC7, $ACC7
vpsrlq \$29, $ACC8, $TEMP5
vpermq \$0x93, $TEMP3, $TEMP3
vpand $AND_MASK, $ACC8, $ACC8
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP5, $TEMP5
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC4, $ACC4
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC5, $ACC5
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC6, $ACC6
vpblendd \$3, $TEMP4, $TEMP5, $TEMP4
vpaddq $TEMP3, $ACC7, $ACC7
vpaddq $TEMP4, $ACC8, $ACC8
vpsrlq \$29, $ACC4, $TEMP1
vpand $AND_MASK, $ACC4, $ACC4
vpsrlq \$29, $ACC5, $TEMP2
vpand $AND_MASK, $ACC5, $ACC5
vpsrlq \$29, $ACC6, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC6, $ACC6
vpsrlq \$29, $ACC7, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC7, $ACC7
vpsrlq \$29, $ACC8, $TEMP5
vpermq \$0x93, $TEMP3, $TEMP3
vpand $AND_MASK, $ACC8, $ACC8
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP5, $TEMP5
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC4, $ACC4
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC5, $ACC5
vmovdqu $ACC4, 32*4-128($rp)
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC6, $ACC6
vmovdqu $ACC5, 32*5-128($rp)
vpblendd \$3, $TEMP4, $TEMP5, $TEMP4
vpaddq $TEMP3, $ACC7, $ACC7
vmovdqu $ACC6, 32*6-128($rp)
vpaddq $TEMP4, $ACC8, $ACC8
vmovdqu $ACC7, 32*7-128($rp)
vmovdqu $ACC8, 32*8-128($rp)
mov $rp, $ap
dec $rep
jne .LOOP_GRANDE_SQR_1024
vzeroall
mov %rbp, %rax
___
$code.=<<___ if ($win64);
movaps -0xd8(%rax),%xmm6
movaps -0xc8(%rax),%xmm7
movaps -0xb8(%rax),%xmm8
movaps -0xa8(%rax),%xmm9
movaps -0x98(%rax),%xmm10
movaps -0x88(%rax),%xmm11
movaps -0x78(%rax),%xmm12
movaps -0x68(%rax),%xmm13
movaps -0x58(%rax),%xmm14
movaps -0x48(%rax),%xmm15
___
$code.=<<___;
mov -48(%rax),%r15
mov -40(%rax),%r14
mov -32(%rax),%r13
mov -24(%rax),%r12
mov -16(%rax),%rbp
mov -8(%rax),%rbx
lea (%rax),%rsp # restore %rsp
.Lsqr_1024_epilogue:
ret
.size rsaz_1024_sqr_avx2,.-rsaz_1024_sqr_avx2
___
}
{ # void AMM_WW(
my $rp="%rdi"; # BN_ULONG *rp,
my $ap="%rsi"; # const BN_ULONG *ap,
my $bp="%rdx"; # const BN_ULONG *bp,
my $np="%rcx"; # const BN_ULONG *np,
my $n0="%r8d"; # unsigned int n0);
# The registers that hold the accumulated redundant result
# The AMM works on 1024 bit operands, and redundant word size is 29
# Therefore: ceil(1024/29)/4 = 9
my $ACC0="%ymm0";
my $ACC1="%ymm1";
my $ACC2="%ymm2";
my $ACC3="%ymm3";
my $ACC4="%ymm4";
my $ACC5="%ymm5";
my $ACC6="%ymm6";
my $ACC7="%ymm7";
my $ACC8="%ymm8";
my $ACC9="%ymm9";
# Registers that hold the broadcasted words of multiplier, currently used
my $Bi="%ymm10";
my $Yi="%ymm11";
# Helper registers
my $TEMP0=$ACC0;
my $TEMP1="%ymm12";
my $TEMP2="%ymm13";
my $ZERO="%ymm14";
my $AND_MASK="%ymm15";
# alu registers that hold the first words of the ACC
my $r0="%r9";
my $r1="%r10";
my $r2="%r11";
my $r3="%r12";
my $i="%r14d";
my $tmp="%r15";
$bp="%r13"; # reassigned argument
$code.=<<___;
.globl rsaz_1024_mul_avx2
.type rsaz_1024_mul_avx2,\@function,5
.align 64
rsaz_1024_mul_avx2:
lea (%rsp), %rax
push %rbx
push %rbp
push %r12
push %r13
push %r14
push %r15
___
$code.=<<___ if ($win64);
vzeroupper
lea -0xa8(%rsp),%rsp
vmovaps %xmm6,-0xd8(%rax)
vmovaps %xmm7,-0xc8(%rax)
vmovaps %xmm8,-0xb8(%rax)
vmovaps %xmm9,-0xa8(%rax)
vmovaps %xmm10,-0x98(%rax)
vmovaps %xmm11,-0x88(%rax)
vmovaps %xmm12,-0x78(%rax)
vmovaps %xmm13,-0x68(%rax)
vmovaps %xmm14,-0x58(%rax)
vmovaps %xmm15,-0x48(%rax)
.Lmul_1024_body:
___
$code.=<<___;
mov %rax,%rbp
vzeroall
mov %rdx, $bp # reassigned argument
sub \$64,%rsp
# unaligned 256-bit load that crosses page boundary can
# cause severe performance degradation here, so if $ap does
# cross page boundary, swap it with $bp [meaning that caller
# is advised to lay down $ap and $bp next to each other, so
# that only one can cross page boundary].
.byte 0x67,0x67
mov $ap, $tmp
and \$4095, $tmp
add \$32*10, $tmp
shr \$12, $tmp
mov $ap, $tmp
cmovnz $bp, $ap
cmovnz $tmp, $bp
mov $np, $tmp
sub \$-128,$ap # size optimization
sub \$-128,$np
sub \$-128,$rp
and \$4095, $tmp # see if $np crosses page
add \$32*10, $tmp
.byte 0x67,0x67
shr \$12, $tmp
jz .Lmul_1024_no_n_copy
# unaligned 256-bit load that crosses page boundary can
# cause severe performance degradation here, so if $np does
# cross page boundary, copy it to stack and make sure stack
# frame doesn't...
sub \$32*10,%rsp
vmovdqu 32*0-128($np), $ACC0
and \$-512, %rsp
vmovdqu 32*1-128($np), $ACC1
vmovdqu 32*2-128($np), $ACC2
vmovdqu 32*3-128($np), $ACC3
vmovdqu 32*4-128($np), $ACC4
vmovdqu 32*5-128($np), $ACC5
vmovdqu 32*6-128($np), $ACC6
vmovdqu 32*7-128($np), $ACC7
vmovdqu 32*8-128($np), $ACC8
lea 64+128(%rsp),$np
vmovdqu $ACC0, 32*0-128($np)
vpxor $ACC0, $ACC0, $ACC0
vmovdqu $ACC1, 32*1-128($np)
vpxor $ACC1, $ACC1, $ACC1
vmovdqu $ACC2, 32*2-128($np)
vpxor $ACC2, $ACC2, $ACC2
vmovdqu $ACC3, 32*3-128($np)
vpxor $ACC3, $ACC3, $ACC3
vmovdqu $ACC4, 32*4-128($np)
vpxor $ACC4, $ACC4, $ACC4
vmovdqu $ACC5, 32*5-128($np)
vpxor $ACC5, $ACC5, $ACC5
vmovdqu $ACC6, 32*6-128($np)
vpxor $ACC6, $ACC6, $ACC6
vmovdqu $ACC7, 32*7-128($np)
vpxor $ACC7, $ACC7, $ACC7
vmovdqu $ACC8, 32*8-128($np)
vmovdqa $ACC0, $ACC8
vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero after vzeroall
.Lmul_1024_no_n_copy:
and \$-64,%rsp
mov ($bp), %rbx
vpbroadcastq ($bp), $Bi
vmovdqu $ACC0, (%rsp) # clear top of stack
xor $r0, $r0
.byte 0x67
xor $r1, $r1
xor $r2, $r2
xor $r3, $r3
vmovdqu .Land_mask(%rip), $AND_MASK
mov \$9, $i
vmovdqu $ACC9, 32*9-128($rp) # $ACC9 is zero after vzeroall
jmp .Loop_mul_1024
.align 32
.Loop_mul_1024:
vpsrlq \$29, $ACC3, $ACC9 # correct $ACC3(*)
mov %rbx, %rax
imulq -128($ap), %rax
add $r0, %rax
mov %rbx, $r1
imulq 8-128($ap), $r1
add 8(%rsp), $r1
mov %rax, $r0
imull $n0, %eax
and \$0x1fffffff, %eax
mov %rbx, $r2
imulq 16-128($ap), $r2
add 16(%rsp), $r2
mov %rbx, $r3
imulq 24-128($ap), $r3
add 24(%rsp), $r3
vpmuludq 32*1-128($ap),$Bi,$TEMP0
vmovd %eax, $Yi
vpaddq $TEMP0,$ACC1,$ACC1
vpmuludq 32*2-128($ap),$Bi,$TEMP1
vpbroadcastq $Yi, $Yi
vpaddq $TEMP1,$ACC2,$ACC2
vpmuludq 32*3-128($ap),$Bi,$TEMP2
vpand $AND_MASK, $ACC3, $ACC3 # correct $ACC3
vpaddq $TEMP2,$ACC3,$ACC3
vpmuludq 32*4-128($ap),$Bi,$TEMP0
vpaddq $TEMP0,$ACC4,$ACC4
vpmuludq 32*5-128($ap),$Bi,$TEMP1
vpaddq $TEMP1,$ACC5,$ACC5
vpmuludq 32*6-128($ap),$Bi,$TEMP2
vpaddq $TEMP2,$ACC6,$ACC6
vpmuludq 32*7-128($ap),$Bi,$TEMP0
vpermq \$0x93, $ACC9, $ACC9 # correct $ACC3
vpaddq $TEMP0,$ACC7,$ACC7
vpmuludq 32*8-128($ap),$Bi,$TEMP1
vpbroadcastq 8($bp), $Bi
vpaddq $TEMP1,$ACC8,$ACC8
mov %rax,%rdx
imulq -128($np),%rax
add %rax,$r0
mov %rdx,%rax
imulq 8-128($np),%rax
add %rax,$r1
mov %rdx,%rax
imulq 16-128($np),%rax
add %rax,$r2
shr \$29, $r0
imulq 24-128($np),%rdx
add %rdx,$r3
add $r0, $r1
vpmuludq 32*1-128($np),$Yi,$TEMP2
vmovq $Bi, %rbx
vpaddq $TEMP2,$ACC1,$ACC1
vpmuludq 32*2-128($np),$Yi,$TEMP0
vpaddq $TEMP0,$ACC2,$ACC2
vpmuludq 32*3-128($np),$Yi,$TEMP1
vpaddq $TEMP1,$ACC3,$ACC3
vpmuludq 32*4-128($np),$Yi,$TEMP2
vpaddq $TEMP2,$ACC4,$ACC4
vpmuludq 32*5-128($np),$Yi,$TEMP0
vpaddq $TEMP0,$ACC5,$ACC5
vpmuludq 32*6-128($np),$Yi,$TEMP1
vpaddq $TEMP1,$ACC6,$ACC6
vpmuludq 32*7-128($np),$Yi,$TEMP2
vpblendd \$3, $ZERO, $ACC9, $ACC9 # correct $ACC3
vpaddq $TEMP2,$ACC7,$ACC7
vpmuludq 32*8-128($np),$Yi,$TEMP0
vpaddq $ACC9, $ACC3, $ACC3 # correct $ACC3
vpaddq $TEMP0,$ACC8,$ACC8
mov %rbx, %rax
imulq -128($ap),%rax
add %rax,$r1
vmovdqu -8+32*1-128($ap),$TEMP1
mov %rbx, %rax
imulq 8-128($ap),%rax
add %rax,$r2
vmovdqu -8+32*2-128($ap),$TEMP2
mov $r1, %rax
imull $n0, %eax
and \$0x1fffffff, %eax
imulq 16-128($ap),%rbx
add %rbx,$r3
vpmuludq $Bi,$TEMP1,$TEMP1
vmovd %eax, $Yi
vmovdqu -8+32*3-128($ap),$TEMP0
vpaddq $TEMP1,$ACC1,$ACC1
vpmuludq $Bi,$TEMP2,$TEMP2
vpbroadcastq $Yi, $Yi
vmovdqu -8+32*4-128($ap),$TEMP1
vpaddq $TEMP2,$ACC2,$ACC2
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -8+32*5-128($ap),$TEMP2
vpaddq $TEMP0,$ACC3,$ACC3
vpmuludq $Bi,$TEMP1,$TEMP1
vmovdqu -8+32*6-128($ap),$TEMP0
vpaddq $TEMP1,$ACC4,$ACC4
vpmuludq $Bi,$TEMP2,$TEMP2
vmovdqu -8+32*7-128($ap),$TEMP1
vpaddq $TEMP2,$ACC5,$ACC5
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -8+32*8-128($ap),$TEMP2
vpaddq $TEMP0,$ACC6,$ACC6
vpmuludq $Bi,$TEMP1,$TEMP1
vmovdqu -8+32*9-128($ap),$ACC9
vpaddq $TEMP1,$ACC7,$ACC7
vpmuludq $Bi,$TEMP2,$TEMP2
vpaddq $TEMP2,$ACC8,$ACC8
vpmuludq $Bi,$ACC9,$ACC9
vpbroadcastq 16($bp), $Bi
mov %rax,%rdx
imulq -128($np),%rax
add %rax,$r1
vmovdqu -8+32*1-128($np),$TEMP0
mov %rdx,%rax
imulq 8-128($np),%rax
add %rax,$r2
vmovdqu -8+32*2-128($np),$TEMP1
shr \$29, $r1
imulq 16-128($np),%rdx
add %rdx,$r3
add $r1, $r2
vpmuludq $Yi,$TEMP0,$TEMP0
vmovq $Bi, %rbx
vmovdqu -8+32*3-128($np),$TEMP2
vpaddq $TEMP0,$ACC1,$ACC1
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -8+32*4-128($np),$TEMP0
vpaddq $TEMP1,$ACC2,$ACC2
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -8+32*5-128($np),$TEMP1
vpaddq $TEMP2,$ACC3,$ACC3
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -8+32*6-128($np),$TEMP2
vpaddq $TEMP0,$ACC4,$ACC4
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -8+32*7-128($np),$TEMP0
vpaddq $TEMP1,$ACC5,$ACC5
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -8+32*8-128($np),$TEMP1
vpaddq $TEMP2,$ACC6,$ACC6
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -8+32*9-128($np),$TEMP2
vpaddq $TEMP0,$ACC7,$ACC7
vpmuludq $Yi,$TEMP1,$TEMP1
vpaddq $TEMP1,$ACC8,$ACC8
vpmuludq $Yi,$TEMP2,$TEMP2
vpaddq $TEMP2,$ACC9,$ACC9
vmovdqu -16+32*1-128($ap),$TEMP0
mov %rbx,%rax
imulq -128($ap),%rax
add $r2,%rax
vmovdqu -16+32*2-128($ap),$TEMP1
mov %rax,$r2
imull $n0, %eax
and \$0x1fffffff, %eax
imulq 8-128($ap),%rbx
add %rbx,$r3
vpmuludq $Bi,$TEMP0,$TEMP0
vmovd %eax, $Yi
vmovdqu -16+32*3-128($ap),$TEMP2
vpaddq $TEMP0,$ACC1,$ACC1
vpmuludq $Bi,$TEMP1,$TEMP1
vpbroadcastq $Yi, $Yi
vmovdqu -16+32*4-128($ap),$TEMP0
vpaddq $TEMP1,$ACC2,$ACC2
vpmuludq $Bi,$TEMP2,$TEMP2
vmovdqu -16+32*5-128($ap),$TEMP1
vpaddq $TEMP2,$ACC3,$ACC3
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -16+32*6-128($ap),$TEMP2
vpaddq $TEMP0,$ACC4,$ACC4
vpmuludq $Bi,$TEMP1,$TEMP1
vmovdqu -16+32*7-128($ap),$TEMP0
vpaddq $TEMP1,$ACC5,$ACC5
vpmuludq $Bi,$TEMP2,$TEMP2
vmovdqu -16+32*8-128($ap),$TEMP1
vpaddq $TEMP2,$ACC6,$ACC6
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -16+32*9-128($ap),$TEMP2
vpaddq $TEMP0,$ACC7,$ACC7
vpmuludq $Bi,$TEMP1,$TEMP1
vpaddq $TEMP1,$ACC8,$ACC8
vpmuludq $Bi,$TEMP2,$TEMP2
vpbroadcastq 24($bp), $Bi
vpaddq $TEMP2,$ACC9,$ACC9
vmovdqu -16+32*1-128($np),$TEMP0
mov %rax,%rdx
imulq -128($np),%rax
add %rax,$r2
vmovdqu -16+32*2-128($np),$TEMP1
imulq 8-128($np),%rdx
add %rdx,$r3
shr \$29, $r2
vpmuludq $Yi,$TEMP0,$TEMP0
vmovq $Bi, %rbx
vmovdqu -16+32*3-128($np),$TEMP2
vpaddq $TEMP0,$ACC1,$ACC1
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -16+32*4-128($np),$TEMP0
vpaddq $TEMP1,$ACC2,$ACC2
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -16+32*5-128($np),$TEMP1
vpaddq $TEMP2,$ACC3,$ACC3
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -16+32*6-128($np),$TEMP2
vpaddq $TEMP0,$ACC4,$ACC4
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -16+32*7-128($np),$TEMP0
vpaddq $TEMP1,$ACC5,$ACC5
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -16+32*8-128($np),$TEMP1
vpaddq $TEMP2,$ACC6,$ACC6
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -16+32*9-128($np),$TEMP2
vpaddq $TEMP0,$ACC7,$ACC7
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -24+32*1-128($ap),$TEMP0
vpaddq $TEMP1,$ACC8,$ACC8
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -24+32*2-128($ap),$TEMP1
vpaddq $TEMP2,$ACC9,$ACC9
add $r2, $r3
imulq -128($ap),%rbx
add %rbx,$r3
mov $r3, %rax
imull $n0, %eax
and \$0x1fffffff, %eax
vpmuludq $Bi,$TEMP0,$TEMP0
vmovd %eax, $Yi
vmovdqu -24+32*3-128($ap),$TEMP2
vpaddq $TEMP0,$ACC1,$ACC1
vpmuludq $Bi,$TEMP1,$TEMP1
vpbroadcastq $Yi, $Yi
vmovdqu -24+32*4-128($ap),$TEMP0
vpaddq $TEMP1,$ACC2,$ACC2
vpmuludq $Bi,$TEMP2,$TEMP2
vmovdqu -24+32*5-128($ap),$TEMP1
vpaddq $TEMP2,$ACC3,$ACC3
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -24+32*6-128($ap),$TEMP2
vpaddq $TEMP0,$ACC4,$ACC4
vpmuludq $Bi,$TEMP1,$TEMP1
vmovdqu -24+32*7-128($ap),$TEMP0
vpaddq $TEMP1,$ACC5,$ACC5
vpmuludq $Bi,$TEMP2,$TEMP2
vmovdqu -24+32*8-128($ap),$TEMP1
vpaddq $TEMP2,$ACC6,$ACC6
vpmuludq $Bi,$TEMP0,$TEMP0
vmovdqu -24+32*9-128($ap),$TEMP2
vpaddq $TEMP0,$ACC7,$ACC7
vpmuludq $Bi,$TEMP1,$TEMP1
vpaddq $TEMP1,$ACC8,$ACC8
vpmuludq $Bi,$TEMP2,$TEMP2
vpbroadcastq 32($bp), $Bi
vpaddq $TEMP2,$ACC9,$ACC9
add \$32, $bp # $bp++
vmovdqu -24+32*1-128($np),$TEMP0
imulq -128($np),%rax
add %rax,$r3
shr \$29, $r3
vmovdqu -24+32*2-128($np),$TEMP1
vpmuludq $Yi,$TEMP0,$TEMP0
vmovq $Bi, %rbx
vmovdqu -24+32*3-128($np),$TEMP2
vpaddq $TEMP0,$ACC1,$ACC0 # $ACC0==$TEMP0
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu $ACC0, (%rsp) # transfer $r0-$r3
vpaddq $TEMP1,$ACC2,$ACC1
vmovdqu -24+32*4-128($np),$TEMP0
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -24+32*5-128($np),$TEMP1
vpaddq $TEMP2,$ACC3,$ACC2
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -24+32*6-128($np),$TEMP2
vpaddq $TEMP0,$ACC4,$ACC3
vpmuludq $Yi,$TEMP1,$TEMP1
vmovdqu -24+32*7-128($np),$TEMP0
vpaddq $TEMP1,$ACC5,$ACC4
vpmuludq $Yi,$TEMP2,$TEMP2
vmovdqu -24+32*8-128($np),$TEMP1
vpaddq $TEMP2,$ACC6,$ACC5
vpmuludq $Yi,$TEMP0,$TEMP0
vmovdqu -24+32*9-128($np),$TEMP2
mov $r3, $r0
vpaddq $TEMP0,$ACC7,$ACC6
vpmuludq $Yi,$TEMP1,$TEMP1
add (%rsp), $r0
vpaddq $TEMP1,$ACC8,$ACC7
vpmuludq $Yi,$TEMP2,$TEMP2
vmovq $r3, $TEMP1
vpaddq $TEMP2,$ACC9,$ACC8
dec $i
jnz .Loop_mul_1024
___
# (*) Original implementation was correcting ACC1-ACC3 for overflow
# after 7 loop runs, or after 28 iterations, or 56 additions.
# But as we underutilize resources, it's possible to correct in
# each iteration with marginal performance loss. But then, as
# we do it in each iteration, we can correct less digits, and
# avoid performance penalties completely. Also note that we
# correct only three digits out of four. This works because
# most significant digit is subjected to less additions.
$TEMP0 = $ACC9;
$TEMP3 = $Bi;
$TEMP4 = $Yi;
$code.=<<___;
vpermq \$0, $AND_MASK, $AND_MASK
vpaddq (%rsp), $TEMP1, $ACC0
vpsrlq \$29, $ACC0, $TEMP1
vpand $AND_MASK, $ACC0, $ACC0
vpsrlq \$29, $ACC1, $TEMP2
vpand $AND_MASK, $ACC1, $ACC1
vpsrlq \$29, $ACC2, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC2, $ACC2
vpsrlq \$29, $ACC3, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC3, $ACC3
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP3, $TEMP3
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpermq \$0x93, $TEMP4, $TEMP4
vpaddq $TEMP0, $ACC0, $ACC0
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC1, $ACC1
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC2, $ACC2
vpblendd \$3, $TEMP4, $ZERO, $TEMP4
vpaddq $TEMP3, $ACC3, $ACC3
vpaddq $TEMP4, $ACC4, $ACC4
vpsrlq \$29, $ACC0, $TEMP1
vpand $AND_MASK, $ACC0, $ACC0
vpsrlq \$29, $ACC1, $TEMP2
vpand $AND_MASK, $ACC1, $ACC1
vpsrlq \$29, $ACC2, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC2, $ACC2
vpsrlq \$29, $ACC3, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC3, $ACC3
vpermq \$0x93, $TEMP3, $TEMP3
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC0, $ACC0
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC1, $ACC1
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC2, $ACC2
vpblendd \$3, $TEMP4, $ZERO, $TEMP4
vpaddq $TEMP3, $ACC3, $ACC3
vpaddq $TEMP4, $ACC4, $ACC4
vmovdqu $ACC0, 0-128($rp)
vmovdqu $ACC1, 32-128($rp)
vmovdqu $ACC2, 64-128($rp)
vmovdqu $ACC3, 96-128($rp)
___
$TEMP5=$ACC0;
$code.=<<___;
vpsrlq \$29, $ACC4, $TEMP1
vpand $AND_MASK, $ACC4, $ACC4
vpsrlq \$29, $ACC5, $TEMP2
vpand $AND_MASK, $ACC5, $ACC5
vpsrlq \$29, $ACC6, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC6, $ACC6
vpsrlq \$29, $ACC7, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC7, $ACC7
vpsrlq \$29, $ACC8, $TEMP5
vpermq \$0x93, $TEMP3, $TEMP3
vpand $AND_MASK, $ACC8, $ACC8
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP5, $TEMP5
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC4, $ACC4
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC5, $ACC5
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC6, $ACC6
vpblendd \$3, $TEMP4, $TEMP5, $TEMP4
vpaddq $TEMP3, $ACC7, $ACC7
vpaddq $TEMP4, $ACC8, $ACC8
vpsrlq \$29, $ACC4, $TEMP1
vpand $AND_MASK, $ACC4, $ACC4
vpsrlq \$29, $ACC5, $TEMP2
vpand $AND_MASK, $ACC5, $ACC5
vpsrlq \$29, $ACC6, $TEMP3
vpermq \$0x93, $TEMP1, $TEMP1
vpand $AND_MASK, $ACC6, $ACC6
vpsrlq \$29, $ACC7, $TEMP4
vpermq \$0x93, $TEMP2, $TEMP2
vpand $AND_MASK, $ACC7, $ACC7
vpsrlq \$29, $ACC8, $TEMP5
vpermq \$0x93, $TEMP3, $TEMP3
vpand $AND_MASK, $ACC8, $ACC8
vpermq \$0x93, $TEMP4, $TEMP4
vpblendd \$3, $ZERO, $TEMP1, $TEMP0
vpermq \$0x93, $TEMP5, $TEMP5
vpblendd \$3, $TEMP1, $TEMP2, $TEMP1
vpaddq $TEMP0, $ACC4, $ACC4
vpblendd \$3, $TEMP2, $TEMP3, $TEMP2
vpaddq $TEMP1, $ACC5, $ACC5
vpblendd \$3, $TEMP3, $TEMP4, $TEMP3
vpaddq $TEMP2, $ACC6, $ACC6
vpblendd \$3, $TEMP4, $TEMP5, $TEMP4
vpaddq $TEMP3, $ACC7, $ACC7
vpaddq $TEMP4, $ACC8, $ACC8
vmovdqu $ACC4, 128-128($rp)
vmovdqu $ACC5, 160-128($rp)
vmovdqu $ACC6, 192-128($rp)
vmovdqu $ACC7, 224-128($rp)
vmovdqu $ACC8, 256-128($rp)
vzeroupper
mov %rbp, %rax
___
$code.=<<___ if ($win64);
movaps -0xd8(%rax),%xmm6
movaps -0xc8(%rax),%xmm7
movaps -0xb8(%rax),%xmm8
movaps -0xa8(%rax),%xmm9
movaps -0x98(%rax),%xmm10
movaps -0x88(%rax),%xmm11
movaps -0x78(%rax),%xmm12
movaps -0x68(%rax),%xmm13
movaps -0x58(%rax),%xmm14
movaps -0x48(%rax),%xmm15
___
$code.=<<___;
mov -48(%rax),%r15
mov -40(%rax),%r14
mov -32(%rax),%r13
mov -24(%rax),%r12
mov -16(%rax),%rbp
mov -8(%rax),%rbx
lea (%rax),%rsp # restore %rsp
.Lmul_1024_epilogue:
ret
.size rsaz_1024_mul_avx2,.-rsaz_1024_mul_avx2
___
}
{
my ($out,$inp) = $win64 ? ("%rcx","%rdx") : ("%rdi","%rsi");
my @T = map("%r$_",(8..11));
$code.=<<___;
.globl rsaz_1024_red2norm_avx2
.type rsaz_1024_red2norm_avx2,\@abi-omnipotent
.align 32
rsaz_1024_red2norm_avx2:
sub \$-128,$inp # size optimization
xor %rax,%rax
___
for ($j=0,$i=0; $i<16; $i++) {
my $k=0;
while (29*$j<64*($i+1)) { # load data till boundary
$code.=" mov `8*$j-128`($inp), @T[0]\n";
$j++; $k++; push(@T,shift(@T));
}
$l=$k;
while ($k>1) { # shift loaded data but last value
$code.=" shl \$`29*($j-$k)`,@T[-$k]\n";
$k--;
}
$code.=<<___; # shift last value
mov @T[-1], @T[0]
shl \$`29*($j-1)`, @T[-1]
shr \$`-29*($j-1)`, @T[0]
___
while ($l) { # accumulate all values
$code.=" add @T[-$l], %rax\n";
$l--;
}
$code.=<<___;
adc \$0, @T[0] # consume eventual carry
mov %rax, 8*$i($out)
mov @T[0], %rax
___
push(@T,shift(@T));
}
$code.=<<___;
ret
.size rsaz_1024_red2norm_avx2,.-rsaz_1024_red2norm_avx2
.globl rsaz_1024_norm2red_avx2
.type rsaz_1024_norm2red_avx2,\@abi-omnipotent
.align 32
rsaz_1024_norm2red_avx2:
sub \$-128,$out # size optimization
mov ($inp),@T[0]
mov \$0x1fffffff,%eax
___
for ($j=0,$i=0; $i<16; $i++) {
$code.=" mov `8*($i+1)`($inp),@T[1]\n" if ($i<15);
$code.=" xor @T[1],@T[1]\n" if ($i==15);
my $k=1;
while (29*($j+1)<64*($i+1)) {
$code.=<<___;
mov @T[0],@T[-$k]
shr \$`29*$j`,@T[-$k]
and %rax,@T[-$k] # &0x1fffffff
mov @T[-$k],`8*$j-128`($out)
___
$j++; $k++;
}
$code.=<<___;
shrd \$`29*$j`,@T[1],@T[0]
and %rax,@T[0]
mov @T[0],`8*$j-128`($out)
___
$j++;
push(@T,shift(@T));
}
$code.=<<___;
mov @T[0],`8*$j-128`($out) # zero
mov @T[0],`8*($j+1)-128`($out)
mov @T[0],`8*($j+2)-128`($out)
mov @T[0],`8*($j+3)-128`($out)
ret
.size rsaz_1024_norm2red_avx2,.-rsaz_1024_norm2red_avx2
___
}
{
my ($out,$inp,$power) = $win64 ? ("%rcx","%rdx","%r8d") : ("%rdi","%rsi","%edx");
$code.=<<___;
.globl rsaz_1024_scatter5_avx2
.type rsaz_1024_scatter5_avx2,\@abi-omnipotent
.align 32
rsaz_1024_scatter5_avx2:
vzeroupper
vmovdqu .Lscatter_permd(%rip),%ymm5
shl \$4,$power
lea ($out,$power),$out
mov \$9,%eax
jmp .Loop_scatter_1024
.align 32
.Loop_scatter_1024:
vmovdqu ($inp),%ymm0
lea 32($inp),$inp
vpermd %ymm0,%ymm5,%ymm0
vmovdqu %xmm0,($out)
lea 16*32($out),$out
dec %eax
jnz .Loop_scatter_1024
vzeroupper
ret
.size rsaz_1024_scatter5_avx2,.-rsaz_1024_scatter5_avx2
.globl rsaz_1024_gather5_avx2
.type rsaz_1024_gather5_avx2,\@abi-omnipotent
.align 32
rsaz_1024_gather5_avx2:
vzeroupper
mov %rsp,%r11
___
$code.=<<___ if ($win64);
lea -0x88(%rsp),%rax
.LSEH_begin_rsaz_1024_gather5:
# I can't trust assembler to use specific encoding:-(
.byte 0x48,0x8d,0x60,0xe0 # lea -0x20(%rax),%rsp
.byte 0xc5,0xf8,0x29,0x70,0xe0 # vmovaps %xmm6,-0x20(%rax)
.byte 0xc5,0xf8,0x29,0x78,0xf0 # vmovaps %xmm7,-0x10(%rax)
.byte 0xc5,0x78,0x29,0x40,0x00 # vmovaps %xmm8,0(%rax)
.byte 0xc5,0x78,0x29,0x48,0x10 # vmovaps %xmm9,0x10(%rax)
.byte 0xc5,0x78,0x29,0x50,0x20 # vmovaps %xmm10,0x20(%rax)
.byte 0xc5,0x78,0x29,0x58,0x30 # vmovaps %xmm11,0x30(%rax)
.byte 0xc5,0x78,0x29,0x60,0x40 # vmovaps %xmm12,0x40(%rax)
.byte 0xc5,0x78,0x29,0x68,0x50 # vmovaps %xmm13,0x50(%rax)
.byte 0xc5,0x78,0x29,0x70,0x60 # vmovaps %xmm14,0x60(%rax)
.byte 0xc5,0x78,0x29,0x78,0x70 # vmovaps %xmm15,0x70(%rax)
___
$code.=<<___;
lea -0x100(%rsp),%rsp
and \$-32, %rsp
lea .Linc(%rip), %r10
lea -128(%rsp),%rax # control u-op density
vmovd $power, %xmm4
vmovdqa (%r10),%ymm0
vmovdqa 32(%r10),%ymm1
vmovdqa 64(%r10),%ymm5
vpbroadcastd %xmm4,%ymm4
vpaddd %ymm5, %ymm0, %ymm2
vpcmpeqd %ymm4, %ymm0, %ymm0
vpaddd %ymm5, %ymm1, %ymm3
vpcmpeqd %ymm4, %ymm1, %ymm1
vmovdqa %ymm0, 32*0+128(%rax)
vpaddd %ymm5, %ymm2, %ymm0
vpcmpeqd %ymm4, %ymm2, %ymm2
vmovdqa %ymm1, 32*1+128(%rax)
vpaddd %ymm5, %ymm3, %ymm1
vpcmpeqd %ymm4, %ymm3, %ymm3
vmovdqa %ymm2, 32*2+128(%rax)
vpaddd %ymm5, %ymm0, %ymm2
vpcmpeqd %ymm4, %ymm0, %ymm0
vmovdqa %ymm3, 32*3+128(%rax)
vpaddd %ymm5, %ymm1, %ymm3
vpcmpeqd %ymm4, %ymm1, %ymm1
vmovdqa %ymm0, 32*4+128(%rax)
vpaddd %ymm5, %ymm2, %ymm8
vpcmpeqd %ymm4, %ymm2, %ymm2
vmovdqa %ymm1, 32*5+128(%rax)
vpaddd %ymm5, %ymm3, %ymm9
vpcmpeqd %ymm4, %ymm3, %ymm3
vmovdqa %ymm2, 32*6+128(%rax)
vpaddd %ymm5, %ymm8, %ymm10
vpcmpeqd %ymm4, %ymm8, %ymm8
vmovdqa %ymm3, 32*7+128(%rax)
vpaddd %ymm5, %ymm9, %ymm11
vpcmpeqd %ymm4, %ymm9, %ymm9
vpaddd %ymm5, %ymm10, %ymm12
vpcmpeqd %ymm4, %ymm10, %ymm10
vpaddd %ymm5, %ymm11, %ymm13
vpcmpeqd %ymm4, %ymm11, %ymm11
vpaddd %ymm5, %ymm12, %ymm14
vpcmpeqd %ymm4, %ymm12, %ymm12
vpaddd %ymm5, %ymm13, %ymm15
vpcmpeqd %ymm4, %ymm13, %ymm13
vpcmpeqd %ymm4, %ymm14, %ymm14
vpcmpeqd %ymm4, %ymm15, %ymm15
vmovdqa -32(%r10),%ymm7 # .Lgather_permd
lea 128($inp), $inp
mov \$9,$power
.Loop_gather_1024:
vmovdqa 32*0-128($inp), %ymm0
vmovdqa 32*1-128($inp), %ymm1
vmovdqa 32*2-128($inp), %ymm2
vmovdqa 32*3-128($inp), %ymm3
vpand 32*0+128(%rax), %ymm0, %ymm0
vpand 32*1+128(%rax), %ymm1, %ymm1
vpand 32*2+128(%rax), %ymm2, %ymm2
vpor %ymm0, %ymm1, %ymm4
vpand 32*3+128(%rax), %ymm3, %ymm3
vmovdqa 32*4-128($inp), %ymm0
vmovdqa 32*5-128($inp), %ymm1
vpor %ymm2, %ymm3, %ymm5
vmovdqa 32*6-128($inp), %ymm2
vmovdqa 32*7-128($inp), %ymm3
vpand 32*4+128(%rax), %ymm0, %ymm0
vpand 32*5+128(%rax), %ymm1, %ymm1
vpand 32*6+128(%rax), %ymm2, %ymm2
vpor %ymm0, %ymm4, %ymm4
vpand 32*7+128(%rax), %ymm3, %ymm3
vpand 32*8-128($inp), %ymm8, %ymm0
vpor %ymm1, %ymm5, %ymm5
vpand 32*9-128($inp), %ymm9, %ymm1
vpor %ymm2, %ymm4, %ymm4
vpand 32*10-128($inp),%ymm10, %ymm2
vpor %ymm3, %ymm5, %ymm5
vpand 32*11-128($inp),%ymm11, %ymm3
vpor %ymm0, %ymm4, %ymm4
vpand 32*12-128($inp),%ymm12, %ymm0
vpor %ymm1, %ymm5, %ymm5
vpand 32*13-128($inp),%ymm13, %ymm1
vpor %ymm2, %ymm4, %ymm4
vpand 32*14-128($inp),%ymm14, %ymm2
vpor %ymm3, %ymm5, %ymm5
vpand 32*15-128($inp),%ymm15, %ymm3
lea 32*16($inp), $inp
vpor %ymm0, %ymm4, %ymm4
vpor %ymm1, %ymm5, %ymm5
vpor %ymm2, %ymm4, %ymm4
vpor %ymm3, %ymm5, %ymm5
vpor %ymm5, %ymm4, %ymm4
vextracti128 \$1, %ymm4, %xmm5 # upper half is cleared
vpor %xmm4, %xmm5, %xmm5
vpermd %ymm5,%ymm7,%ymm5
vmovdqu %ymm5,($out)
lea 32($out),$out
dec $power
jnz .Loop_gather_1024
vpxor %ymm0,%ymm0,%ymm0
vmovdqu %ymm0,($out)
vzeroupper
___
$code.=<<___ if ($win64);
movaps -0xa8(%r11),%xmm6
movaps -0x98(%r11),%xmm7
movaps -0x88(%r11),%xmm8
movaps -0x78(%r11),%xmm9
movaps -0x68(%r11),%xmm10
movaps -0x58(%r11),%xmm11
movaps -0x48(%r11),%xmm12
movaps -0x38(%r11),%xmm13
movaps -0x28(%r11),%xmm14
movaps -0x18(%r11),%xmm15
.LSEH_end_rsaz_1024_gather5:
___
$code.=<<___;
lea (%r11),%rsp
ret
.size rsaz_1024_gather5_avx2,.-rsaz_1024_gather5_avx2
___
}
$code.=<<___;
.extern OPENSSL_ia32cap_P
.globl rsaz_avx2_eligible
.type rsaz_avx2_eligible,\@abi-omnipotent
.align 32
rsaz_avx2_eligible:
mov OPENSSL_ia32cap_P+8(%rip),%eax
___
$code.=<<___ if ($addx);
mov \$`1<<8|1<<19`,%ecx
mov \$0,%edx
and %eax,%ecx
cmp \$`1<<8|1<<19`,%ecx # check for BMI2+AD*X
cmove %edx,%eax
___
$code.=<<___;
and \$`1<<5`,%eax
shr \$5,%eax
ret
.size rsaz_avx2_eligible,.-rsaz_avx2_eligible
.align 64
.Land_mask:
.quad 0x1fffffff,0x1fffffff,0x1fffffff,-1
.Lscatter_permd:
.long 0,2,4,6,7,7,7,7
.Lgather_permd:
.long 0,7,1,7,2,7,3,7
.Linc:
.long 0,0,0,0, 1,1,1,1
.long 2,2,2,2, 3,3,3,3
.long 4,4,4,4, 4,4,4,4
.align 64
___
if ($win64) {
$rec="%rcx";
$frame="%rdx";
$context="%r8";
$disp="%r9";
$code.=<<___
.extern __imp_RtlVirtualUnwind
.type rsaz_se_handler,\@abi-omnipotent
.align 16
rsaz_se_handler:
push %rsi
push %rdi
push %rbx
push %rbp
push %r12
push %r13
push %r14
push %r15
pushfq
sub \$64,%rsp
mov 120($context),%rax # pull context->Rax
mov 248($context),%rbx # pull context->Rip
mov 8($disp),%rsi # disp->ImageBase
mov 56($disp),%r11 # disp->HandlerData
mov 0(%r11),%r10d # HandlerData[0]
lea (%rsi,%r10),%r10 # prologue label
cmp %r10,%rbx # context->Rip<prologue label
jb .Lcommon_seh_tail
mov 152($context),%rax # pull context->Rsp
mov 4(%r11),%r10d # HandlerData[1]
lea (%rsi,%r10),%r10 # epilogue label
cmp %r10,%rbx # context->Rip>=epilogue label
jae .Lcommon_seh_tail
mov 160($context),%rax # pull context->Rbp
mov -48(%rax),%r15
mov -40(%rax),%r14
mov -32(%rax),%r13
mov -24(%rax),%r12
mov -16(%rax),%rbp
mov -8(%rax),%rbx
mov %r15,240($context)
mov %r14,232($context)
mov %r13,224($context)
mov %r12,216($context)
mov %rbp,160($context)
mov %rbx,144($context)
lea -0xd8(%rax),%rsi # %xmm save area
lea 512($context),%rdi # & context.Xmm6
mov \$20,%ecx # 10*sizeof(%xmm0)/sizeof(%rax)
.long 0xa548f3fc # cld; rep movsq
.Lcommon_seh_tail:
mov 8(%rax),%rdi
mov 16(%rax),%rsi
mov %rax,152($context) # restore context->Rsp
mov %rsi,168($context) # restore context->Rsi
mov %rdi,176($context) # restore context->Rdi
mov 40($disp),%rdi # disp->ContextRecord
mov $context,%rsi # context
mov \$154,%ecx # sizeof(CONTEXT)
.long 0xa548f3fc # cld; rep movsq
mov $disp,%rsi
xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER
mov 8(%rsi),%rdx # arg2, disp->ImageBase
mov 0(%rsi),%r8 # arg3, disp->ControlPc
mov 16(%rsi),%r9 # arg4, disp->FunctionEntry
mov 40(%rsi),%r10 # disp->ContextRecord
lea 56(%rsi),%r11 # &disp->HandlerData
lea 24(%rsi),%r12 # &disp->EstablisherFrame
mov %r10,32(%rsp) # arg5
mov %r11,40(%rsp) # arg6
mov %r12,48(%rsp) # arg7
mov %rcx,56(%rsp) # arg8, (NULL)
call *__imp_RtlVirtualUnwind(%rip)
mov \$1,%eax # ExceptionContinueSearch
add \$64,%rsp
popfq
pop %r15
pop %r14
pop %r13
pop %r12
pop %rbp
pop %rbx
pop %rdi
pop %rsi
ret
.size rsaz_se_handler,.-rsaz_se_handler
.section .pdata
.align 4
.rva .LSEH_begin_rsaz_1024_sqr_avx2
.rva .LSEH_end_rsaz_1024_sqr_avx2
.rva .LSEH_info_rsaz_1024_sqr_avx2
.rva .LSEH_begin_rsaz_1024_mul_avx2
.rva .LSEH_end_rsaz_1024_mul_avx2
.rva .LSEH_info_rsaz_1024_mul_avx2
.rva .LSEH_begin_rsaz_1024_gather5
.rva .LSEH_end_rsaz_1024_gather5
.rva .LSEH_info_rsaz_1024_gather5
.section .xdata
.align 8
.LSEH_info_rsaz_1024_sqr_avx2:
.byte 9,0,0,0
.rva rsaz_se_handler
.rva .Lsqr_1024_body,.Lsqr_1024_epilogue
.LSEH_info_rsaz_1024_mul_avx2:
.byte 9,0,0,0
.rva rsaz_se_handler
.rva .Lmul_1024_body,.Lmul_1024_epilogue
.LSEH_info_rsaz_1024_gather5:
.byte 0x01,0x36,0x17,0x0b
.byte 0x36,0xf8,0x09,0x00 # vmovaps 0x90(rsp),xmm15
.byte 0x31,0xe8,0x08,0x00 # vmovaps 0x80(rsp),xmm14
.byte 0x2c,0xd8,0x07,0x00 # vmovaps 0x70(rsp),xmm13
.byte 0x27,0xc8,0x06,0x00 # vmovaps 0x60(rsp),xmm12
.byte 0x22,0xb8,0x05,0x00 # vmovaps 0x50(rsp),xmm11
.byte 0x1d,0xa8,0x04,0x00 # vmovaps 0x40(rsp),xmm10
.byte 0x18,0x98,0x03,0x00 # vmovaps 0x30(rsp),xmm9
.byte 0x13,0x88,0x02,0x00 # vmovaps 0x20(rsp),xmm8
.byte 0x0e,0x78,0x01,0x00 # vmovaps 0x10(rsp),xmm7
.byte 0x09,0x68,0x00,0x00 # vmovaps 0x00(rsp),xmm6
.byte 0x04,0x01,0x15,0x00 # sub rsp,0xa8
.byte 0x00,0xb3,0x00,0x00 # set_frame r11
___
}
foreach (split("\n",$code)) {
s/\`([^\`]*)\`/eval($1)/ge;
s/\b(sh[rl]d?\s+\$)(-?[0-9]+)/$1.$2%64/ge or
s/\b(vmov[dq])\b(.+)%ymm([0-9]+)/$1$2%xmm$3/go or
s/\b(vmovdqu)\b(.+)%x%ymm([0-9]+)/$1$2%xmm$3/go or
s/\b(vpinsr[qd])\b(.+)%ymm([0-9]+)/$1$2%xmm$3/go or
s/\b(vpextr[qd])\b(.+)%ymm([0-9]+)/$1$2%xmm$3/go or
s/\b(vpbroadcast[qd]\s+)%ymm([0-9]+)/$1%xmm$2/go;
print $_,"\n";
}
}}} else {{{
print <<___; # assembler is too old
.text
.globl rsaz_avx2_eligible
.type rsaz_avx2_eligible,\@abi-omnipotent
rsaz_avx2_eligible:
xor %eax,%eax
ret
.size rsaz_avx2_eligible,.-rsaz_avx2_eligible
.globl rsaz_1024_sqr_avx2
.globl rsaz_1024_mul_avx2
.globl rsaz_1024_norm2red_avx2
.globl rsaz_1024_red2norm_avx2
.globl rsaz_1024_scatter5_avx2
.globl rsaz_1024_gather5_avx2
.type rsaz_1024_sqr_avx2,\@abi-omnipotent
rsaz_1024_sqr_avx2:
rsaz_1024_mul_avx2:
rsaz_1024_norm2red_avx2:
rsaz_1024_red2norm_avx2:
rsaz_1024_scatter5_avx2:
rsaz_1024_gather5_avx2:
.byte 0x0f,0x0b # ud2
ret
.size rsaz_1024_sqr_avx2,.-rsaz_1024_sqr_avx2
___
}}}
close STDOUT;
| {
"language": "Assembly"
} |
polygon
1
1.508994E+01 4.105126E+01
1.509064E+01 4.105220E+01
1.509142E+01 4.105315E+01
1.509206E+01 4.105418E+01
1.509219E+01 4.105448E+01
1.509254E+01 4.105531E+01
1.509293E+01 4.105687E+01
1.509329E+01 4.105831E+01
1.509337E+01 4.105915E+01
1.509337E+01 4.105993E+01
1.509350E+01 4.106084E+01
1.509363E+01 4.106145E+01
1.509381E+01 4.106171E+01
1.509405E+01 4.106177E+01
1.509482E+01 4.106195E+01
1.509526E+01 4.106241E+01
1.509536E+01 4.106244E+01
1.509593E+01 4.106256E+01
1.509718E+01 4.106246E+01
1.509876E+01 4.106226E+01
1.510009E+01 4.106208E+01
1.510085E+01 4.106192E+01
1.510126E+01 4.106171E+01
1.510152E+01 4.106161E+01
1.510185E+01 4.106148E+01
1.510209E+01 4.106138E+01
1.510252E+01 4.106132E+01
1.510314E+01 4.106129E+01
1.510443E+01 4.106121E+01
1.510581E+01 4.106108E+01
1.510636E+01 4.106103E+01
1.510658E+01 4.106164E+01
1.510659E+01 4.106252E+01
1.510637E+01 4.106347E+01
1.510606E+01 4.106422E+01
1.510551E+01 4.106495E+01
1.510475E+01 4.106557E+01
1.510438E+01 4.106600E+01
1.510434E+01 4.106637E+01
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1.509710E+01 4.098340E+01
1.509662E+01 4.098363E+01
1.509645E+01 4.098452E+01
1.509627E+01 4.098516E+01
1.509617E+01 4.098516E+01
1.509504E+01 4.098518E+01
1.509365E+01 4.098588E+01
1.509454E+01 4.098750E+01
1.509400E+01 4.098782E+01
1.509403E+01 4.098862E+01
1.509380E+01 4.098889E+01
1.509390E+01 4.098900E+01
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1.509365E+01 4.099093E+01
1.509318E+01 4.099200E+01
1.509101E+01 4.099256E+01
1.509040E+01 4.099050E+01
1.509012E+01 4.098990E+01
1.509011E+01 4.098946E+01
1.508915E+01 4.098819E+01
1.508902E+01 4.098851E+01
1.508897E+01 4.098881E+01
1.508897E+01 4.098922E+01
1.508896E+01 4.098965E+01
1.508857E+01 4.099040E+01
1.508834E+01 4.099084E+01
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1.508788E+01 4.099222E+01
1.509097E+01 4.099265E+01
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1.509317E+01 4.099607E+01
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1.509280E+01 4.099914E+01
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1.508615E+01 4.099875E+01
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1.508612E+01 4.099899E+01
1.508666E+01 4.099925E+01
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1.508858E+01 4.100023E+01
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1.508334E+01 4.100825E+01
1.508347E+01 4.100889E+01
1.508319E+01 4.100931E+01
1.508271E+01 4.101003E+01
1.508253E+01 4.101092E+01
1.508214E+01 4.101177E+01
1.508190E+01 4.101252E+01
1.508142E+01 4.101322E+01
1.508149E+01 4.101368E+01
1.508144E+01 4.101372E+01
1.508080E+01 4.101423E+01
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1.507948E+01 4.101423E+01
1.507908E+01 4.101447E+01
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1.507956E+01 4.101904E+01
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1.508086E+01 4.101902E+01
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1.508114E+01 4.101978E+01
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1.508157E+01 4.102057E+01
1.508187E+01 4.102067E+01
1.508231E+01 4.102055E+01
1.508279E+01 4.102052E+01
1.508309E+01 4.102056E+01
1.508349E+01 4.102066E+01
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1.508408E+01 4.102079E+01
1.508426E+01 4.102081E+01
1.508435E+01 4.102087E+01
1.508443E+01 4.102102E+01
1.508443E+01 4.102120E+01
1.508436E+01 4.102130E+01
1.508441E+01 4.102159E+01
1.508407E+01 4.102269E+01
1.508428E+01 4.102343E+01
1.508467E+01 4.102429E+01
1.508468E+01 4.102544E+01
1.508475E+01 4.102630E+01
1.508468E+01 4.102715E+01
1.508442E+01 4.102791E+01
1.508476E+01 4.102864E+01
1.508527E+01 4.102956E+01
1.508560E+01 4.103026E+01
1.508563E+01 4.103068E+01
1.508517E+01 4.103083E+01
1.508467E+01 4.103100E+01
1.508436E+01 4.103137E+01
1.508432E+01 4.103205E+01
1.508407E+01 4.103223E+01
1.508406E+01 4.103246E+01
1.508381E+01 4.103255E+01
1.508353E+01 4.103266E+01
1.508353E+01 4.103292E+01
1.508374E+01 4.103328E+01
1.508364E+01 4.103375E+01
1.508351E+01 4.103407E+01
1.508341E+01 4.103434E+01
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1.508312E+01 4.103519E+01
1.508309E+01 4.103531E+01
1.508316E+01 4.103561E+01
1.508321E+01 4.103590E+01
1.508357E+01 4.103597E+01
1.508376E+01 4.103601E+01
1.508384E+01 4.103602E+01
1.508403E+01 4.103606E+01
1.508485E+01 4.103622E+01
1.508601E+01 4.103625E+01
1.508715E+01 4.103645E+01
1.508755E+01 4.103683E+01
1.508753E+01 4.103747E+01
1.508760E+01 4.103822E+01
1.508854E+01 4.103891E+01
1.508953E+01 4.103968E+01
1.509042E+01 4.104057E+01
1.509131E+01 4.104135E+01
1.509193E+01 4.104205E+01
1.509225E+01 4.104264E+01
1.509228E+01 4.104332E+01
1.509209E+01 4.104451E+01
1.509207E+01 4.104491E+01
1.509148E+01 4.104558E+01
1.509267E+01 4.104648E+01
1.509293E+01 4.104677E+01
1.509387E+01 4.104759E+01
1.509474E+01 4.104822E+01
1.509514E+01 4.104855E+01
1.509565E+01 4.104897E+01
1.509634E+01 4.104959E+01
1.509673E+01 4.104994E+01
1.509681E+01 4.105016E+01
1.509540E+01 4.105054E+01
1.509485E+01 4.105082E+01
1.509473E+01 4.105087E+01
1.509344E+01 4.105136E+01
1.509221E+01 4.105150E+01
1.509108E+01 4.105136E+01
1.509046E+01 4.105128E+01
1.508994E+01 4.105126E+01
END
2
1.515575E+01 4.098240E+01
1.515549E+01 4.098254E+01
1.515534E+01 4.098272E+01
1.515519E+01 4.098312E+01
1.515514E+01 4.098354E+01
1.515506E+01 4.098434E+01
1.515472E+01 4.098561E+01
1.515439E+01 4.098728E+01
1.515406E+01 4.098887E+01
1.515381E+01 4.099073E+01
1.515376E+01 4.099244E+01
1.515359E+01 4.099414E+01
1.515338E+01 4.099567E+01
1.515313E+01 4.099728E+01
1.515310E+01 4.099778E+01
1.515306E+01 4.099855E+01
1.515306E+01 4.099974E+01
1.515283E+01 4.100070E+01
1.515248E+01 4.100207E+01
1.515234E+01 4.100297E+01
1.515244E+01 4.100424E+01
1.515251E+01 4.100553E+01
1.515225E+01 4.100631E+01
1.515185E+01 4.100721E+01
1.515165E+01 4.100789E+01
1.515166E+01 4.100831E+01
1.515317E+01 4.100871E+01
1.515418E+01 4.100901E+01
1.515526E+01 4.100918E+01
1.515630E+01 4.100910E+01
1.515739E+01 4.100905E+01
1.515792E+01 4.100913E+01
1.515923E+01 4.101042E+01
1.515998E+01 4.101108E+01
1.516101E+01 4.101190E+01
1.516119E+01 4.101202E+01
1.516142E+01 4.101217E+01
1.516231E+01 4.101275E+01
1.516404E+01 4.101355E+01
1.516493E+01 4.101396E+01
1.516554E+01 4.101425E+01
1.516715E+01 4.101493E+01
1.516855E+01 4.101538E+01
1.517037E+01 4.101594E+01
1.517155E+01 4.101631E+01
1.517262E+01 4.101676E+01
1.517349E+01 4.101714E+01
1.517418E+01 4.101746E+01
1.517461E+01 4.101767E+01
1.517524E+01 4.101731E+01
1.517627E+01 4.101672E+01
1.517741E+01 4.101601E+01
1.517814E+01 4.101565E+01
1.517892E+01 4.101532E+01
1.517948E+01 4.101485E+01
1.518043E+01 4.101395E+01
1.518145E+01 4.101341E+01
1.518225E+01 4.101310E+01
1.518377E+01 4.101293E+01
1.518449E+01 4.101308E+01
1.518522E+01 4.101316E+01
1.518496E+01 4.101244E+01
1.518480E+01 4.101204E+01
1.518490E+01 4.101135E+01
1.518511E+01 4.101054E+01
1.518503E+01 4.100968E+01
1.518490E+01 4.100921E+01
1.518450E+01 4.100835E+01
1.518436E+01 4.100785E+01
1.518430E+01 4.100725E+01
1.518401E+01 4.100663E+01
1.518338E+01 4.100610E+01
1.518253E+01 4.100549E+01
1.518195E+01 4.100483E+01
1.518176E+01 4.100432E+01
1.518153E+01 4.100379E+01
1.518123E+01 4.100330E+01
1.518052E+01 4.100273E+01
1.517973E+01 4.100212E+01
1.517937E+01 4.100169E+01
1.517932E+01 4.100136E+01
1.517936E+01 4.100070E+01
1.517912E+01 4.100033E+01
1.517887E+01 4.099997E+01
1.517840E+01 4.099937E+01
1.517802E+01 4.099880E+01
1.517776E+01 4.099828E+01
1.517726E+01 4.099735E+01
1.517647E+01 4.099617E+01
1.517593E+01 4.099559E+01
1.517519E+01 4.099494E+01
1.517418E+01 4.099417E+01
1.517305E+01 4.099321E+01
1.517223E+01 4.099234E+01
1.517117E+01 4.099144E+01
1.517065E+01 4.099026E+01
1.517028E+01 4.098918E+01
1.516965E+01 4.098791E+01
1.516885E+01 4.098682E+01
1.516787E+01 4.098557E+01
1.516786E+01 4.098556E+01
1.516683E+01 4.098467E+01
1.516543E+01 4.098348E+01
1.516454E+01 4.098235E+01
1.516423E+01 4.098108E+01
1.516379E+01 4.097986E+01
1.516329E+01 4.097976E+01
1.516217E+01 4.097987E+01
1.516096E+01 4.097997E+01
1.515994E+01 4.098032E+01
1.515909E+01 4.098072E+01
1.515839E+01 4.098104E+01
1.515749E+01 4.098150E+01
1.515722E+01 4.098164E+01
1.515623E+01 4.098214E+01
1.515575E+01 4.098240E+01
END
END
| {
"language": "Assembly"
} |
ps.1.1
;------------------------------------------------------------------------------
; Draw a texture . . woo hoo!
; t0 - texture
;
; The texture coordinates need to be defined as follows:
; tc0 - texcoords
;------------------------------------------------------------------------------
; Get the color from the texture
tex t0
tex t1
tex t3
mul r0.rgb, t0, c3 + ; base times modulation
mov r0.a, c3.a ; use modulation alpha (don't use texture alpha)
mul_x2 r0.rgb, r0, t3 ; detail texture
mad r0.rgb, t1, c2, r0 ; + envmap * envmaptint (color only)
mul r0.rgb, v0, r0 ; Apply lighting
mul_x2 r0.rgb, c0, r0 ; * 2 * (overbrightFactor/2)
mul r1, t0, c1 ; Self illum * tint
lrp r0.rgb, t0.a, r1, r0 ; Blend between self-illum + base * lighting
| {
"language": "Assembly"
} |
.page
.subttl 'serlistn.src'
acptr lda #8 ; set byte bit count
sta cont
acp00a jsr tstatn
jsr debnc
and #clkin
bne acp00a
jsr dathi ; make data line hi
lda #1 ; wait 255 us
;------rom -05 8/18/83-------------
jmp patch6
;----------------------------------
acp00 jsr tstatn
lda ifr1
and #$40 ; test if time out
bne acp00b ; ran out,its an eoi
jsr debnc ; test clock low
and #clkin
beq acp00 ; no
bne acp01 ; yes
acp00b jsr datlow ; set data line low as response
ldx #10 ; delay for talker turnaround
acp02 dex
bne acp02
jsr dathi ; set data line hi
acp02a jsr tstatn
jsr debnc ; wait for low clock
and #clkin
beq acp02a
lda #0 ; set eoi received
sta eoiflg
acp01
acp03 lda pb ; wait for clock high
eor #01 ; complement datain
lsr a ; shift into carry
and #$02 ; clkin/2
bne acp03
nop ; fill space left by speed-up
nop ; to fix pal vc20
nop ; 901229-02 rom
ror data
acp03a jsr tstatn
jsr debnc
and #clkin ; wait for clock low
beq acp03a
dec cont ; more to do?
bne acp03
jsr datlow ; set data line low
lda data
rts
listen sei
jsr fndwch ; test if active write channel
bcs lsn15
lda chnrdy,x
ror a
bcs lsn30
lsn15 lda orgsa ; test if open
and #$f0
cmp #$f0
beq lsn30 ; its an open
jmp ilerr ; not active channel
lsn30 jsr acptr ; get a byte
cli
jsr put ; put(data,eoiflg,sa)
jmp listen ; and keep on listen
frmerr
iterr
ilerr lda #00 ; release all bus lines
sta pb
jmp xidle
atnlow jmp atnsrv
; tstatn()
; {
; if(atnmod)
; {
; if(pb & $80)
; { if 1571 then jatns20() else atns20
; }
; else return
; }
; else
; {
; if(pb&$80) return
; else
; { if 1571 then jatnsrv() else atnsrv()
; }
; }
; }
tstatn lda atnmod ; test if in atn mode
beq tsta50 ; no
lda pb ; in atnmod
bpl tatn20 ; atn gone,do what we are told to do
tstrtn rts ; still in atn mode
tsta50 lda pb ; not atnmode
bpl tstrtn ; no atn present
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
jmp ptch30 ; *** rom ds 03/12/85 ***
; jmp atnsrv ; do atn command
tatn20 jmp ptch45 ; *** rom ds 03/12/85 ***
; jmp atns20
;<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
| {
"language": "Assembly"
} |
৫৬
এ
এই
এছাড়া
মুক্তিযোদ্ধা
অকপট
অধুনা
অনন্তর
অনুদানে
অন্য
অমলেন্দু
অর্থনীতিতে
অসস্য
অ্যাপল
অ্যাসোসিয়েশন
অডিও
আঁকেন
আইটিসি
আইপিএ
আইবিএম
আইসিসি
আচার্য্য
আজীবন
আত
আত্মসমর্পণ
আন্তর্জাতিক
আন্দ্রে
আন্ধি
আপডেটেড
আফ্রিকার
আবার
আমির
আয়ারল্যান্ড
আর
আরও
আরো
আর্কমিনিট
আর্ট
আর্থার
আল
আসাদ
আসেন
ই
ইংল্যান্ড
ইউনিভার্সিয়াড
ইউনিয়ন
ইউনিয়নের
ইউরোপ
ইএসপিএন
ইএসপিএনক্রিকইনফো
ইকন
ইকম্যান্ড
ইগ
ইগের
ইট
ইটালিক
ইটিস
ইডস
ইডি
ইন
ইনাল
ইনোকা
ইন্ড
ইন্সের
ইবাদাত
ইভ
ইভানা
ইভাবে
ইয়ের
ইরকম
ইরাক
ইল
ইস
ইসঙ্গে
ইসময়
ইসলামি
ইসলামী
ইস্টার্ন
ঈশ্বরদী
উ
উইঃ
উইকিলিকসের
উইকেট
উইখ
উইগ
উইন
উইনবাদী
উইনের
উইম্প
উকে
উড
উদ্বোধন
উদ্যোগে
উনিভার্সিদাদ
উন্ড
উন্ডারদের
উপএককটি
উপত্যকার
উপর
উপ
উমে
উল্লেখ
উস
ঋক্
এ
এই
এএল
একজন
একদিনের
একে
এক্স
একাধিক
এজবাস্টন
এড
এডিসি
এন্টোনিও
এনএএল
এফ
এফসি
এবং
এভার
এমনকি
এয়ার
এর
এলএসি
এস
এসপি
এসে
এস্পোর্তে
এসএফ
এসসি
ঐ
ও
ওই
ওকে
ওটিতে
ওডেনামের
ওনা
ওপর
ওয়া
ওয়াংলার
ওয়াইজার
ওয়াতুল
ওয়ানি
ওয়ায়
ওয়ার
ওয়ারউইকশায়ার
ওয়ারের
ওয়ার্কস
ওয়ার্ড
ওয়াল
ওয়ালিস
ওয়েন
ওয়েবলী
ওয়েলস
ওয়েলিংটন
ওয়েস্ট
ওয়্যার
ওরেল
ক
কগুলোতে
কভ
করণটি
করভাবে
কা
কান্ড
কান্ডগুলো
কান্তজিউ
কাপি
কায়ানা
কায়্যানা
কার
কারে
কাল
কি
কিং
কিউএল
কিউল
কিউল
কিউলকেও
কিছু
কিত
কিন্তু
কিবুল
কিম
কির
কিরা
কিল
কিশোর
কিস
কিস্তান
কিয়ে
কিরি
কুক
কুমার
কৃষ্ট
কে
কেই
কেও
কেতন
কেতুগ্রাম
কেন
কের
কেরাঅেন্য
কেল
কেশগুলোতে
কেশন
কেশনগুলোর
কেশনগুলোতে
কেশনের
কেশন
কেশনে
কেশনের
কেসনের
কে্যর
কেজিপে
কেজে
কোকাইনাস্টিক
কোকাষ্টিক
কোকাস্টিকের
কোকাষ্টিক
কোকাস্টিকের
কোড
কোডার
কোডারগুলো
কোণ
কোয়
কোশা
কোডিং
কোডেড
কোডের
কোণে
কোনো
কোয়েন্সি
কোয়েন্সিগুলো
কোয়েন্সির
কৌশল
কৌশলী
ক্টিভিজম
ক্টিভিসম
ক্ত
ক্তি
ক্তিগত
ক্তির
ক্তির
ক্তিশালী
ক্তিকে
ক্তিতে
ক্তের
ক্য
ক্যের
ক্রম
ক্রিয়
ক্রিয়া
ক্রিয়াকরণ
ক্রিয়াকরণের
ক্রিয়াজাতের
ক্রিয়াটি
ক্রিয়াটিকে
ক্রিয়ার
ক্রির
ক্রিপ্টোগ্রাফিক
ক্রেতা
ক্রেতার
ক্রেতাদের
ক্রোব্লকগুলোতে
ক্রোসফটের
ক্রোসোফটের
ক্লিওটাইডের
ক্লিফ
ক্লোরিক
ক্ষতিকারকনাশকের
ক্ষরতা
ক্ষরতার
ক্ষিকত
ক্ষিণবঙ্গের
ক্ষিত
ক্ষিতে
ক্ষে
ক্ষেত্রসমূহের
ক্ষেত্রে
ক্ষেপণ
ক্ষেপ
ক্ষের
ক্ষেত্রে
ক্ষেপণ
ক্স
ক্সি
ক্সের
ক্সেল
ক্সেলস
ক্সেস
ক্সেল
ক্সেলের
ক্স
খিক
খিত
খিম্
খির
খে
খেছিলেন
খোলা
গ
গঞ্জ
গণ
গপূর্ণ
গম্য
গরণ
গরণবাদি
গরণে
গরিদমগুলো
গাল
গিং
গিক
গিল
গিয়ে
গীর্জ্জায়
গুক্
গুরু
গুলি
গে
গেও
গেকার
গেট
গেমস
গের
গেছিলেন
গোম্য
গোরিদম
গোরিদমগুলোর
গোরিদমগুলো
গোরিদমগুলোর
গোরিদমের
গোরিদমিক
গোরিদমে
গোরিদমের
গোর্মিগুলো
গ্নিশিখা
গ্যান
গ্রাফার
গ্রাফিক
গ্রামের
গ্রি
গ্রেড
গ্রোভ
গ্র্যাজুয়েট
ঘর্ষ
ঘেয়ে
ঙে
ঙের
ঙ্কিত
ঙ্কে
ঙ্গ
ঙ্গরি
ঙ্গি
ঙ্গিক
চনায়
চনীয়
চনে
চনেও
চনের
চমে
চর্যাগীতিকা
চারীদের
চার্য্য
চি
চিত
চিতি
চিত্র
চিত্রগুলো
চিত্রটির
চিত্রের
চিপসেট
চিব
চিহ্ন
চিত্রের
চিত্র্যের
চিহ্নিত
চে
চেভ
চেয়ারম্যান
চেয়ে
চ্চ
চ্চিত্র
চ্চিত্রের
চ্চিত্রে
চ্চো
চ্ছ
চ্ছাকৃতভাবে
চ্ছামৃত্যু
চ্ছার
চ্ছিক
চ্ছে
চ্ছেন
ছবিতে
ছি
ছিল
ছিলেন
ছে
ছেন
ছোট
জ
জম
জয়
জলকে
জহালি
জ়
জ়ার
জ়িরাও
জ়ু
জ়্
জাইর
জাকার
জি
জিক
জিজ্ঞাসা
জিট
জিটাল
জিটালি
জিত
জিন
জিপ
জিপার
জিপে
জিভ
জির
জিকের
জিটের
জিতে
জিবি
জীবন
জীবনানন্দ
জুড়ে
জে
জেই
জেকে
জেক্ট
জেট
জেড
জেডডারলিউ
জেড৭৭
জেন
জেন্ট
জের
জেরেই
জেলা
জেলার
জেশন
জেশনকে
জেশনকে
জেশনের
জেসন
জেসনের
জে
জোড়া
জোন
জোরের
জ্জিতকরণ
জ্জেম
জ্যিক
ঝিারি
ঝে
ঝেনিত্সিন
ঝেনিতসিন
ঞ্চিত
ঞ্জের
ঞ্জেলো
ঞ্
ট
টওয়্যার
টন
টস
টাই
টাইন
টারফিশ
টি
টিং
টিই
টিইউ
টিইউ
টিএ
টিও
টিক
টিকা
টিকে
টিক্যাল
টিগার
টিগারের
টিগুলোর
টিটাল
টিত
টিতগুলোর
টিন
টিনের
টিভ
টিম
টিমাইজড
টিয়া
টির
টিল
টিলভাবে
টিশ
টি৫
টি
টিকে
টিটি
টিতে
টিপি
টিলিটিগুলোর
টিসি
টিসেনাক্ত
টে
টেকী
টেন
টেনবার্গ
টেনসি
টেন্সটাইন
টেনডেডকে
টেমপ্লেট
টের
টেলাইট
টেশনের
টেটিভ
টো
টোকল
টোকন্ড্রিয়াকে
টোমাস্ক
টোমাস্ক
টোমেটিক
ট্রপি
ট্হান্জ়া
ট
ঠিক
ঠিকতা
ঠিত
ঠিন
ঠে
ঠের
ঠেছে
ড
ডগুলোর
ড়
ড়ি
ড়িং
ড়িত
ড়িয়ায়
ড়ি
ড়িতে
ড়িয়ে
ড়িয়েছে
ড়ে
ড়ে
ডানে
ডাম্স
ডি
ডিং
ডিংয়ের
ডিউলো
ডিও
ডিওতে
ডিওর
ডিওকে
ডিওটিকে
ডিওতে
ডিকম
ডিকম্প্রেশন
ডিগুলো
ডিগুলোতে
ডিটর
ডিটরি
ডিতে
ডিয়া
ডিয়ান
ডিও
ডিকোডার
ডিজিটাল
ডিটিং
ডিতে
ডিভিকে
ডিসিটি
ডিস্কে
ডে
ডেক
ডেকগুলো
ডেড
ডেডকে
ডেম
ডেমে
ডেমটি
ডের
ডেক
ডোর
ডোর
ডোরগুলো
ডোরগুলো
ডোরে
ডোরের
ঢালা
ণ
ণই
ণকাজ
ণস্থল
ণস্বরূপ
ণি
ণিগুলার
ণিগুলোকে
ণিত
ণিতিক
ণির
ণিজ্যিক
ণিবিন্যাসকে
ণী
ণে
ণের
ত
তথ্যসূত্র
তব্য
তলা
তা
তাংশ
তাও
তি
তিক
তিকভাবে
তিকালে
তিগুলো
তিগুলো
তিগুলোকে
তিগুলোতে
তিগ্রস্থ
তিটি
তিতে
তিদান
তিদানের
তিনি
তিবর্তনযোগ্য
তিবাচক
তিয়াপাড়া
তির
তিরক্ষামূলক
তিল
তিশীল
তিশীলভাবে
তিষ্টান
তিষ্ঠাকাল
তিষ্ঠাতা
তিষ্ঠাতা
তিষ্ঠান
তিষ্ঠানিক
তিষ্ঠিত
তিসমূহ
তিহাস
তিহাসের
তিহ্য
তিহ্যগতভাবে
তিহ্যবাহী
তিহ্যবাহী
তিহ্যবাহী
তিকে
তিটি
তিতে
তিবিধি
তিবেদনে
তিবেদনের
তিযোগীগণ
তিযোগিতা
তিরিক্ত
তিরিক্তভাবে
তিরোধিত
তিষ্ঠানটির
তিষ্ঠিত
তী
তীয়
তীয়করনে
তীর
তে
তেই
তেন
তের
তো
তৈরী
তৈল
তো
তোমধ্যেই
তোয়া
ত্ত
ত্তম
ত্তি
ত্তিক
ত্তিমূলক
ত্তির
ত্তিতে
ত্তে
ত্তের
ত্তের
ত্ত্বিক
ত্ত্বে
ত্তি
ত্বের
ত্য
ত্যু
ত্যেকটি
ত্র
ত্রিক
ত্রিকায়
ত্রিত
ত্রিম
ত্রে
ত্রের
ত্র্যের
ত
তবে
থ
থক
থাকুন
থি
থিপত্রের
থিবীর
থিবীরপ্রায়
থিভূক্ত
থিয়ান
থে
থের
থেষ্ট
থেকে
থেন্টিকেশন
থ্যালমোলজি
থ্যের
থ্রি
থে
দ
দন
দরদের
দর্শন
দশ
দা
দান
দাবাদ
দি
দিও
দিত
দিতভাবে
দিন
দিয়া
দিষ্ট
দিরিক্ত
দুটি
দে
দেউলী
দেওবন্দ
দেখা
দেখার
দেতা
দেব
দেবরানের
দের
দেশ
দেশী
দেশে
দেশের
দৈনিক
দ্দিন
দ্দিনের
দ্দীন
দ্দেশ্য
দ্দেশ্যে
দ্দেশ্যের
দ্ধ
দ্ধকালীন
দ্ধতিগুলি
দ্ধি
দ্ধিমত্তার
দ্ধির
দ্ধে
দ্ধেও
দ্ধের
দ্ধতিতে
দ্বিগুণ
দ্ভিজ
দ্ভিদ
দ্য
দ্রিত
দ্রিয়ান
ধ
ধন
ধরা
ধর্মীয়
ধায়
ধি
ধিক
ধিকতর
ধিকাংশ
ধিকাংশ
ধিকারের
ধিত
ধিকেও
ধের
ধ্বনিতাত্ত্বিক
ধ্যমে
ধ্যে
ধ্যেই
ন
নও
নকাসের্ন
নগর
নগুলো
নগ্রাবেন
নগ্রাবেনের
নটিটেটিভ
নটোর
নন্য
নপেল্টা
নভাসকেই
নযোগ
নযোগ্য
নলিঙ্গ
নশীল
নস
নস্কি
নস্ট্রিট
নস্ট্রিটে
নস্ট্রিটের
নহার্ড
না
নাকি
নাদজে
নাদজেকে
নাদজের
নান
নান্ড
নাম
নামতে
নামূলক
নামের
নায়
নার
নারভেদে
নারি
নার্জী
নাল
নি
নিং
নিক
নিকা
নিকায়ন
নিজস্ব
নিট
নিত
নিতস
নিতিক
নিদের
নিবীড়
নিবার্য
নিভার্স
নিভার্সিটি
নিম্ন
নিম্নতা
নিম্নলিখিত
নিয়র
নিয়া
নিয়াক
নিয়ান
নিয়মিত
নির
নির্দেশ
নির্ধারিত
নির্ভর
নির্ভরশীল
নির্মিত
নিলয়
নিস্ট
নিৎস
নিৎসের
নিবেশ
নির্দিষ্ট
নিশ্চিত
নী
নীতিবিদ
নীয়
নীয়দেরকে
নীয়ভাষী
নুযায়ী
নৃত্যগীত
নে
নেওয়ালা
নেক
নেকগুলো
নেকটা
নেকটাই
নেট
নেড
নেতা
নেন্ড
নের
নেশন
নেসকিউল
নেসকিউলকেও
নেকের
নেট
নেটে
নেটের
নৈতিকভাবে
নো
নোজ
নোটাইপ
নোদনের
নোম
নোমকে
নোমজিপ
নোর
নোনিবেশ
নোমের
নোযোগ
ন্
ন্টগুলোর
ন্টগেন
ন্টার
ন্টারের
ন্টিনা
ন্টিনার
ন্টিকেশন
ন্টে
ন্টের
ন্টেশন
ন্টেশনের
ন্টেলের
ন্ট্রোল
ন্ড
ন্ডি
ন্ডেড
ন্ডের
ন্ডোজ
ন্ড্রিয়াকে
ন্ড
ন্ডসের
ন্ডের
ন্ত
ন্তর
ন্তরের
ন্তিকর
ন্তের
ন্ত্রিক
ন্ত্রিকভাবে
ন্দকার
ন্দা
ন্দিগঞ্জের
ন্দিয়া
ন্দিয়ায়
ন্দুকের
ন্দেরও
ন্দোলন
ন্দোলনের
ন্দ্ব
ন্দ্বে
ন্দ্ব
ন্দ্রে
ন্ধে
ন্ধের
ন্নিত
ন্নী
ন্ম
ন্যান্স
ন্যাশনাল
ন্স
ন্সন
ন্সি
ন্সিং
ন্সিগুলো
ন্সির
ন্সে
ন্সের
ন্
ন্স্কা
নকে
নত
নযোগ
প
পণ
পত্তি
পদশের
পন্ন
পর্যটন
পর্যায়ে
পল্লী
পাকিস্তানি
পাকিস্তানিদের
পাদন
পাদনের
পাধ্যায়
পার
পাশা
পি
পিং
পিআর
পিইজি
পিএ
পিএম
পিএস
পিক
পিজ
পিত
পিফিট
পিয়ান
পির
পি৩
পিটিই
পিতে
পিথ্রি
পিসিতেও
পিসিকে
পুর
পুল
পুলকে
পুলিশ
পূর্ণ
পে
পেন
পেনটাইপেও
পের
পেল
পেলের
পোগ্রাফির
পোর্ট
পোলিয়ানের
প্টে
প্টেম্বর
প্টোগ্রাফিক
প্টোসিস্টেমের
প্ত
প্তির
প্যায়ার
প্রথম
প্রবল
প্রশ্বাসের
প্রায়
প্রিয়
প্রিয়তা
প্রেরণ
প্রেস
প্রোগ্রামের
প্রোস্টেট
প্লিন্টার
প্লিকেশগুলোতে
প্লিকেশনের
প্লে
প্নের
পযোগী
ফ
ফগুলোর
ফরাসি
ফা
ফাইল
ফার
ফিক
ফিকাল
ফিক্স
ফিক্সে
ফিক্সের
ফিজ
ফির
ফিস
ফিসা
ফিকের
ফিক্স
ফিরোজ
ফেক্টগুলোকে
ফেজ্জী
ফেট
ফেন
ফের
ফেল
ফেস
ফেসর
ফেসের
ফোল্টের
ফোন
ফোনিতে
ফোল্ট
ফোনি
ফ্ট্
ফ্রিট
ফ্রিড
ফ্রিকোয়েন্সি
ফ্রেম
ফ্রেমের
ব
বউমাকে
বও
বক্র
বনলতা
বন্দিয়া
বর্ধিত
বলম্বী
বল্ড
বহার
বা
বাংলাদেশ
বাংলার
বাইশ
বাখ
বাচক
বাণ
বান
বায়
বার
বার্গার
বার্গ
বার্গের
বার্তা
বাল্ড
বাস
বাড়িতে
বি
বিএম
বিএমজি
বিক
বিখ্যাত
বিগুলো
বিজ্ঞান
বিড়
বিত
বিতঃ
বিতে
বিদ্যালয়
বিধ
বিধাজনক
বিধায়
বিধার্থে
বিন
বিন্যস্ত
বিন্যাসকে
বিবরণ
বিভক্ত
বিভক্তির
বিভক্তির
বিয়োজ্য
বির
বির্ভাব
বির্ভাবে
বিল
বিশেষ
বিশ্বাস
বিষয়শেণি
বিসফট
বিসফটের
বিস্কৃত
বিহার
বিতে
বিধি
বিরোধী
বিশিষ্ট
বিশ্লেষণ
বিশ্লেষণকারীগণ
বুর্গ
বে
বেং
বেই
বেও
বেক
বেকারি
বেক্ষণের
বেকডোরগুলো
বেকডোরের
বেঙ্গল
বেচনা
বেচিত
বেতকরণ
বেদ
বেদনে
বেদনের
বেন
বেন্ড
বেয়
বেয়ার
বেয়ারের
বেয়ার্
বের
বের্গ
বেলায়
বেশ
বেশস্থল
বেশযোগ্য
বেষণা
বেষণার
বেষনামূলক
বেহুলার
বেচনায়
বেচিত
বেশি
বেশে
বেশের
বোঝাই
বোয়ালমারী
বোর্গ
বৌধিক
ব্দে
ব্যক্তি
ব্যপী
ব্রডী
ব্রাইড
ব্রিউ
ব্রুক
ব্রুকের
ব
ভ
ভাগ
ভাজা
ভালো
ভি
ভিআইডি
ভিএক্স
ভিক
ভিকে
ভিখারি
ভিজম
ভিজ্ঞা
ভিন্ন
ভিন্নতা
ভিন্নতাকে
ভিল
ভিশন
ভিশনের
ভিসম
ভিডি
ভিডিও
ভিডিগুলো
ভিডিতে
ভিত্তিক
ভিনেতা
ভিযোজিত
ভিসি
ভিসিডি
ভীন
ভূম
ভূষিতা
ভে
ভেম্বর
ভেরেইন
ভেটিকা
ভেদের
ভেন্ডি
ভোজী
ভ্যানের
ম
মং
মতা
মদীয়া
মন্ডিত
মা
মাইনের
মাঘী
মাত
মাত্র
মান
মানুল
মানে
মান
মার
মি
মিং
মিক
মিকা
মিডো
মিত
মিন
মিনিস্টার
মিশন
মিটিং
মিটির
মিটিতে
মীনারায়ণ
মুআযযিন
মুখী
মুয়াযযিন
মে
মেইন
মেইল
মেঘনাদবধ
মেঘবালিকার
মেট
মেটগুলো
মেটাফন্ট
মেদ
মেন
মেনক্লুজ
মেন্ট
মেন্টে
মের
মেল
মেহন
মেটিক
মেটে
মেটের
মেনে
মো
মোট
মোদ
মোদন
মোর্টযা
মোল্লার
মোহাম্মদ
মোহিত
মোক্ষের
মোটিতগুলোর
মোডেম
মোদিত
মোরিতে
ম্নোক্তভাবে
ম্প
ম্পিউটার
ম্পিউটারের
ম্পিউটারের
ম্পিউটিং
ম্পেক্ট
ম্প্রেশন
ম্প্রেশনের
ম্প্রেসন
ম্প্রেসরকে
ম্ভ
ম্মিলিত
ম্মেদ
ম্যাক
ম্যান
ময়
ম
য
যকের
যথেষ্ট
য়
য়কৃত
য়দের
য়নী
য়নীর
য়া
য়াকে
য়াত
য়ান
য়ানদের
য়ানরা
য়ানের
য়ার
য়াল
য়াস
য়িত
য়িত্ব
য়ী
য়ে
য়েইটফোর
য়েকটি
য়েছিল
য়েছে
য়েছে
য়েজ
য়েড
য়েদ
য়েন্ট
য়েন্দা
য়েব
য়েভপ্যাক
য়ের
য়েলচ
য়েলস্ট্রিম
য়েস
য়ে
য়েছিল
য়েছে
য়েছেন
য়েডের
য়েনোজ
য়েন্সি
য়েন্সিগুলো
য়েন্সির
য়েে
য়োগ
য়োগকারী
য়োজন
য়োজনীয়
য়োজনীয়তা
য়োজনীয়তাগুলোর
য়োজনীয়তা
য়োজ্য
য়োজ্যকে
য়োগিক
য়োসিস
য়্যাল
য়্যালস
য়্যানটিটেটিভ
য়্যের
যাংক
যাচ্ছেন
যাট্রিক
যাত্রীদের
যান
যানোয়ার
যাপন
যাপনের
যায়
যিল
যুক্ত
যুক্তি
যুদ্ধকালীন
যে
যেমন
যেমনটা
যেমনটাে
যেমনটি
যের
যেতে
যোগীগণ
যোগ
যোগিতা
যোগী
যোগের
যোগ্য
যোগ্যতা
যোগ্যভাবে
যোগ্যভাবে
যোজ্য
যোগের
যোজিত
য্যে
র
রক
রকপুলোস
রকপুলোসের
রকে
রগুলোর
রণ
রণী
রণে
রতে
রদের
রবাড়ি
রবাদ
রবে
রয়েড
ররস্ট্রিট
ররা
রশনের
রশীলতা
রস
রা
রায়
রাসুর
রি
রিং
রিক
রিকল্পনা
রিকল্পনাগুলো
রিকল্পনাগুলোতে
রিকল্পনায়
রিক্ত
রিক্তভাবে
রিক্ষা
রিক্ষণের
রিকল্পিত
রিগরি
রিচয়
রিচালনা
রিচালনাকারীকে
রিচালনাকে
রিচালানোকে
রিচালিত
রিচিত
রিজ
রিডা
রিণত
রিত
রিতভাবে
রিতার
রিদম
রিদমগুলোর
রিদমগুলো
রিদমগুলোর
রিদমগুলো
রিদমের
রিদর্শন
রিদমিক
রিদমে
রিদমের
রিপূর্ণ
রিপেক্ষিতে
রিফ
রিবর্তন
রিবর্তনগুলো
রিবর্তনশীল
রিবর্তনটি
রিবর্তীত
রিবর্তে
রিবর্তনে
রিবর্তনের
রিবর্তিত
রিবর্তে
রিভাবে
রিমগঞ্জ
রিমণে
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রিমান
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রিমাণে
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রির
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রিষ্ঠ
রিষদের
রিস
রিসংখ্যান
রিসংখ্যানগত
রিসংখ্যানগুলো
রিসংখ্যানসংক্রান্ত
রিসংখ্যানের
রিসংখ্যানের
রিসর
রিসরকে
রিসরের
রিসরকে
রিসীমা
রিস্কার
রিস্কারভাবে
রিস্ফুটিত
রিস্ফূরণ
রিসরে
রিক্ষিত
রিচিত
রিচিতি
রিতে
রিধিকেও
রিবেশ
রিবেশে
রিয়ে
রির
রিশোধনের
রীত
রীন
রু
রুখসিয়ার
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রুপ
রুপে
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রেক
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রেটর
রেড
রেন
রেন্স
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রের
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রেস্ট
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রেছে
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র্কিত
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র্টিন
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র্ট
র্টের
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র্ণের
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র্তিত
র্তে
র্থন
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র্থিক
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র্থের
র্থ
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র্দিষ্টভাবে
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র্দেশক
র্দেশিত
র্ধেক
র্নির্মাণ
র্নির্মান
র্নিমিত
র্নেল
র্পোরেশনের
র্বাসনের
র্বিস
র্বে
র্বের
র্বোচ্চ
র্বোত্তম
র্মিগুলো
র্মুখী
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র্লিন
র্শের
র্ষ
র্ষণ
র্ষণের
র্ষীয়
র্ষের
র্ষ
র্স
র্সিটি
র্স
র্িত
রকে
রতে
ররা
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র্যাফ
ল
লগ
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লিক
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লিকা
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লিকাবদ্ধকরণ
লিকাভূক্ত
লিকাভূক্তকরণ
লিকায়
লিকের
লিখেছি
লিজম
লিটকভসকায়া
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লে
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লোর
লোরও
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ল্যে
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ল্লেখ
ল্লেখিত
ল্লখিত
ল্
ল্প
ল্স
শ
শন
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শনে
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শা
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শার
শি
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শিখা
শিত
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শিষ্ট্যগুলোকে
শিষ্ট্যসমূহ
শিষ্ট্যাবলীকে
শিক্ষিত
শী
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শুরু
শে
শের
শেষ
শেষকরে
শেষত
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শেষায়িত
শেণি
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শ্চিত
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শ্চিম
শ্চিত
শ্নের
শ্বজিৎ
শ্ববিদ্যালয়ে
শ্ববিদ্যালয়ের
শ্যে
শ্যের
শ্রিত
শ্রীলঙ্কার
শ্রেণির
শ্রেষ্ঠ
শ্রেণি
শ্রেণিগুলার
শ্রেণিগুলোকে
শ্রেণির
শ্লেষণ
শ্লেষণকারীগণ
শ্লেষণগুলো
শ্লেষণমূলক
শ্লেষণীয়
শ্লেষণটির
শ্লেষণের
ষ
ষণা
ষনা
ষি
ষিকা
ষিত
ষী
ষে
ষের
ষেরা
ষ্কের
ষ্ট
ষ্টভাবে
ষ্টমী
ষ্টি
ষ্টিই
ষ্টিক
ষ্টিভঙ্গি
ষ্টির
ষ্টিকে
ষ্টিকোণ
ষ্টিকোণে
ষ্টিতে
ষ্ট্রের
ষ্ঠানিকভাবে
ষ্ঠানটির
ষ্ঠিত
ষ্ণু
ষ্য
ষৎ
স
সংযুক্ত
সকে
সঙ্গা
সধবার
সন
সনি
সবার্গ
সমাউথ
সমাজের
সমূহ
সম্পত্তির
সম্পদের
সম্মানসূচক
সসাস
সহ
সাইট
সাথেই
সান
সারির
সাস
সাহিত্যিক
সি
সিং
সিংকে
সিংয়ের
সিএফও
সিএসএস
সিক
সিকতা
সিতেও
সিদ্ধ
সিদ্ধিদাতার
সিন
সিফ
সির
সিরিলীয়
সিল
সিস
সিকে
সিটি
সিটিক্যাল
সিডি
সিডিতে
সিস্টেম
সিডি
সুব্রত
সুয়ানা
সুরিরা
সূত্র
সূরীগণের
সৃতিবিদ্যা
সে
সেগুলোতে
সেট
সেত
সেন
সেনাক্ত
সেন্ট্রাল
সেফ
সের
সেল
সেসর
সেকে
সেছে
সেটে
সেবে
সেবেই
সেবেও
সেবেয়
সেসিং
সোফটের
সোয়ানা
সোর্স
সোল
সোৎসিল
সোলিউশনের
স্ক
স্কি
স্কিং
স্কে
স্ক্যিই
স্ক্রিপ্টের
স্ট
স্টাড
স্টি
স্টিক
স্টিকের
স্টেম
স্টেমের
স্টেমকে
স্টেশন
স্টেমে
স্টেমের
স্ট্রি
স্ট্রিট
স্তিত্ব
স্তিষ্কের
স্থ
স্থাগুলিকেও
স্থাগুলির
স্থাটি
স্থাটির
স্থান
স্থানীয়
স্থাপিত
স্থায়ী
স্থিত
স্থিতি
স্থিতিগুলি
স্থিতির
স্থে
স্থ্য
স্থ্যকেও
স্থ্যের
স্পিটেলার
স্ফিতি
স্ফোরণ
স্র্না
স্লেভ
সক্রিয়
সনিক
হণ
হলের
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হাগড়া
হান
হার্ট
হিঃ
হিউদ্দিন
হিউদ্দিনের
হিউদ্দীন
হিত
হিত্যরচনা
হিনী
হিনীর
হিনীতে
হিরাগত
হিসেবে
হী
হীন
হু
হুমায়ূন
হৃৎপিণ্ড
হৃৎপিন্ড
হে
হেতু
হেনরি
হের
হেলা
হেলার
হেন্দিগঞ্জের
হোক
হ্নিত
ৎ
ৎপাদন
ৎস
ৎসাখাতে
ঢ়ার
য়
য়ে
য়েও
য়েছে
য়ের
০
০০০
০৪
০৬
০৯
১
১তম
১২
১২৫তম
১৩
১৪
১৭
১৭৫৮
১৮২৬
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১৮৭০
১৮৭৬
১৯
১৯৪৭
১৯৪৮
১৯৬৩
১৯৭৯
১৯১৩
২
২১২
৩
৩৫
৪
৪৬
৫০০
৫৩
৬
৭
৮
৯
৯৫
৯৭৪
৯৮৪
৯৯
৯৯১
৯৯২
ৱা
ৱাতেমালা
ৱ্
ং
আপডেটেড
আসাদ
এ
ওডেনামের
ওয়াইজার
কিশোর
কে
ক্ষতিকারকনাশকের
ক্ষরতা
গীর্জ্জায়
গুরু
ঘর্ষ
ঙে
চর্যাগীতিকা
জলকে
জ়্
জিজ্ঞাসা
জিপার
জীবনানন্দ
টি
ডাম্স
ডি
তা
ত্ত্বিক
ত্রে
তবে
দেখা
দেখার
দেব
দৈনিক
দ্য
নিজস্ব
ন্
প্রথম
প্রবল
প্রোস্টেট
বাংলার
বাড়িতে
বুর্গ
বেঙ্গল
বের
ভিখারি
মাঘী
মুআযযিন
মুয়াযযিন
মেঘনাদবধ
যথেষ্ট
রূপসী
র্ক
র্যাফ
লাভ
শা
শিখা
ষনা
স
সধবার
সম্পদের
সম্মানসূচক
সিএফও
হু
্যাপন
্স
০৬
১৯
৮
৯৯
আপডেটেড
ওয়াইজার
কে
ক্ষরতা
গীর্জ্জায়
গুরু
জলকে
জ়্
তবে
দেখা
দেব
নিজস্ব
ন্
প্রথম
প্রোস্টেট
মাঘী
মুআযযিন
মুয়াযযিন
মেঘনাদবধ
যথেষ্ট
র্ক
র্যাফ
সম্পদের
সম্মানসূচক
হু
১৯
৮
ক্ষরতা
গীর্জ্জায়
জলকে
জ়্
তবে
দেব
ন্
র্যাফ
সম্মানসূচক
হু
৮
ক্ষরতা
জলকে
জ়্
তবে
র্যাফ
হু
৮
ক্ষরতা
জলকে
তবে
র্যাফ
হু
৮
তবে
র্যাফ
হু
৮
তবে
র্যাফ
হু
তবে
র্যাফ
হু
তবে
র্যাফ
হু
তবে
র্যাফ
হু
তবে
র্যাফ
হু
তবে
র্যাফ
তবে
র্যাফ
তবে
লিহুড
র্যসিদ্ধির
লিহুড
ড়
ঃঃ
ইডির
প্রিমিয়াম
ফা
বেগম
র্যসিদ্ধির
লিহুড
ড়
ঃঃ
ডরেনাল
একজন
তবে
অংশগ্রহণ
অনুযায়ী
অনুষদের
অনুসারে
অপরাধ
অবদান
অর্থ
অসমর্থন
অ্যান্ড
আ
আকারে
আদিল
আনন্দবাজার
আবার
আবু
আব্দুল
আর
আর্ট
আর্দ্রা
আল
আলী
ইংরেজী
ইউনিয়ন
ইউনিয়নের
ইউরোপের
ইডির
ইয়াউমুল
ইয়েতি
উইকিপিডিয়া
উইকিপিডিয়ানদের
উইকিপিডিয়ার
উইকিসোর্সের
উগান্ডা
উচ্চ
উত্তর
উদ্দিন
উদ্যানের
উন্নয়ন
উপজেলা
উপজেলায়
উপজেলার
উপর
উপস্থাপন
উপস্থিতি
উপস্থিতির
উপাত্তের
উপায়ে
উল্ফ
উল্লাহ
উল্লেখ
উল্লেখ্য
ঊশর
ঋণ
ঋতুু
এই
এক
একই
একে
এটি
এবং
এসমেশারস
এ্যাট
এ্যান
ও
করে
কাজ
কিছু
কিন্তু
কুরআনে
ক্রিতানের
ক্রিয়েটিভ
ক্ষাগৃহ
ক্ষাগৃহে
খরহর
খান
খুলে
গ
গুম
গুরুত্বপূর্ণ
গুলোতে
ঘুরে
চিকন
চিকিৎসা
চিত্রকলায়
চুঁইয়ে
চুড়ান্ত
চৌধুরী
ছিয়ে
ছিল
ছিলেন
ছুঁড়ে
ছুফি
জড়ভরত
জনগণ
জন্য
জরুরী
জ়বেরীর
জ়াফারান
জানো
জিজিয়া
জুলস
ঝিঁ
টাঁযুক্ত
ঠিক
ডরেনাল
ডাউন
ডিগ্রি
তসরিকভাবে
তিনি
তু
তুমি
তুলে
থেকে
দশকে
দিওয়ান
দিক
দিকে
দিতো
দিন
দিয়াগোরাসের
দিয়ে
দিয়েছেে
দুই
দুইটি
দৃষ্টিতে
দেখুন
দ্বিতীয়
ধন্যবাদ
ধারাবাহিক
নওগাঁ
নাম
নি
নিকটতম
নিকটে
নিজ
নিযুক্ত
নিযুক্তি
নির্ভরশীল
নিহত
নূর
পরস্পরের
পরীমনি
পশ্চিমে
পাগান
পারভেজ
পারেন
পিটার
পুত্র
পুরকায়স্থ
পুরস্কার
প্রতি
প্রবেশ
প্রবেশের
প্রিমিয়াম
প্রিয়
ফা
ফিরে
ফুটবল
ফ্যানাটিজম
বং
বজ্র
বা
বাসনা
বিক্রয়ের
বিদেশে
বিদ্যা
বিদ্রোহীদের
বিভাগ
বিরুদ্ধে
বিরোধীে
বিশিষ্ট
বিশেষ
বিষয়বস্তু
বিষয়ে
বুকার
বুঝা
বুরুজ
বৃহত্তম
বেগম
ব্যবহবরকারীদের
ব্রিটিশদের
ভাতা
ম
মন
ময়ুখ
মা
মাংসৰ
মাদাম
মানসপুত্র
মামলা
মামার
মাসুম
মাসে
মি
মিঠাই
মিনি
মিলিয়ে
মুক্তিযুদ্ধের
মুক্তিযোদ্ধা
মুরলিধর
মুসলিম
মূল
মূলত
যদিও
য়
য়াইটিস
য়ারি
যা
যানবাহন
যায়
যিনি
যুক্তরাষ্ট্রে
যেগুলোর
যেটিকে
র
রয়েছে
রা
রাস্তা
রেখা
র্দিষ্ট
র্যসিদ্ধির
লাইলাতুল
লায়েল
লিহুড
লুইস
লেজ
শাহ
শুরু
শুরুতে
শ্মুয়েল
শ্যালো
শ্রেণীভুক্ত
শ্রেষ্ঠ
সংক্ষেপে
সজনী
সন্তোষপুর
সম্প্রদায়ের
সম্মানোত্তর
সরকারি
সশস্ত্র
সাইরাত
সাগর
সায়েন্সেসের
সারি
সার্বজনীন
সিংহের
সিটি
সিদ্ধ
সিদ্ধান্তে
সিন্ড্রোম
সিস্টেম
সুধী
সুনাম
সুফি
সুমি
সৃতি
সেপ্টেম্বর
সেলফি
স্টকহোম
স্টকহোমস্
স্থায়ী
স্নাইম্যান
স্মরণী
স্মিথ
হামিদুর
ৎপত্তি
ৎসরিকভাবে
ৎসার
ৎস্না
১
১০৮০
১১
১৩৩০১৯৯৩
১৬
১৭
১৯৪৭
২
২১
২২
২৩
২৫
২৬
৩
৩০
৫
৭
৮
উল্লেখ
একজন
ক
কান্তজিউ
ঙ্কে
ড়
বিহার
র্থবিজ্ঞানে
ৎসাখাতে
জলকে
৮
তবে
তবে
ঃঃ
উল্লেখ্য
এই
গ
জরুরী
জ়বেরীর
জ়াফারান
ডরেনাল
ধন্যবাদ
নওগাঁ
প্রিয়
বা
মন
ময়ুখ
লাইলাতুল
সুধী
স্থায়ী
১
১১
১৬
১৭
১৯৪৭
২
২১
২২
২৩
২৫
২৬
৩
৩০
৫
৭
৮
একজন
ক
কান্তজিউ
বিহার
তবে
তবে
উল্লেখ্য
এই
জরুরী
ধন্যবাদ
প্রিয়
বা
মন
ময়ুখ
স্থায়ী
২৬
একজন
তবে
ধন্যবাদ
প্রিয়
বা
মন
ময়ুখ
স্থায়ী
২৬
তবে
বা
স্থায়ী
তবে
| {
"language": "Assembly"
} |
/*
* Check to see if an object reference is an instance of a class.
*
* Most common situation is a non-null object, being compared against
* an already-resolved class.
*/
# instance-of vA, vB, class /* CCCC */
EXPORT_PC()
FETCH(a0, 1) # a0 <- CCCC
GET_OPB(a1) # a1 <- B
EAS2(a1, rFP, a1) # a1 <- &object
lw a2, OFF_FP_METHOD(rFP) # a2 <- method
move a3, rSELF # a3 <- self
GET_OPA4(rOBJ) # rOBJ <- A+
JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self)
lw a1, THREAD_EXCEPTION_OFFSET(rSELF)
PREFETCH_INST(2) # load rINST
bnez a1, MterpException
ADVANCE(2) # advance rPC
GET_INST_OPCODE(t0) # extract opcode from rINST
SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0
| {
"language": "Assembly"
} |
comment "gpu-amd-bin-mx51 needs an (e)glibc EABI toolchain w/ C++"
depends on BR2_arm
depends on !BR2_ARM_EABI || !BR2_TOOLCHAIN_USES_GLIBC || \
!BR2_INSTALL_LIBSTDCPP
config BR2_PACKAGE_GPU_AMD_BIN_MX51
bool "gpu-amd-bin-mx51 (also imx53)"
select BR2_PACKAGE_HAS_LIBEGL
select BR2_PACKAGE_HAS_LIBGLES
select BR2_PACKAGE_HAS_LIBOPENVG
depends on BR2_ARM_EABI
depends on BR2_TOOLCHAIN_USES_GLIBC
depends on BR2_INSTALL_LIBSTDCPP
help
Freescale libraries, headers and executables for the
AMD GPU on i.MX5x, containing OpenGL/ES, OpenVG
and EGL support.
if BR2_PACKAGE_GPU_AMD_BIN_MX51
choice
prompt "Output option"
help
There are two versions of this library: one for
direct framebuffer access, one for X11 rendering.
Choose here which version to install.
config BR2_PACKAGE_GPU_AMD_BIN_MX51_OUTPUT_X11
depends on BR2_PACKAGE_XORG7
select BR2_PACKAGE_LIBXCB
select BR2_PACKAGE_XLIB_LIBX11
select BR2_PACKAGE_XLIB_LIBXEXT
select BR2_PACKAGE_XLIB_LIBXRENDER
select BR2_PACKAGE_XLIB_LIBXDMCP
select BR2_PACKAGE_XLIB_LIBXAU
bool "X11"
comment "X11 backend needs X.org enabled"
depends on !BR2_PACKAGE_XORG7
config BR2_PACKAGE_GPU_AMD_BIN_MX51_OUTPUT_FB
bool "Framebuffer"
endchoice
config BR2_PACKAGE_PROVIDES_LIBEGL
default "gpu-amd-bin-mx51"
config BR2_PACKAGE_PROVIDES_LIBGLES
default "gpu-amd-bin-mx51"
config BR2_PACKAGE_PROVIDES_LIBOPENVG
default "gpu-amd-bin-mx51"
config BR2_PACKAGE_GPU_AMD_BIN_MX51_EXAMPLES
bool "install examples"
help
Copy the examples to the target.
endif
| {
"language": "Assembly"
} |
dnl
dnl atmega644.m4
dnl
dnl Copyright (c) 2008 by Christian Dietrich <stettberger@dokucode.de>
dnl Copyright (c) 2008 by Stefan Siegl <stesie@brokenpipe.de>
dnl Copyright (c) 2008 by Jochen Roessner <jochen@lugrot.de>
dnl
dnl This program is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
dnl the Free Software Foundation; either version 2 of the License, or
dnl (at your option) any later version.
dnl
dnl This program is distributed in the hope that it will be useful,
dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
dnl GNU General Public License for more details.
dnl
dnl You should have received a copy of the GNU General Public License
dnl along with this program; if not, write to the Free Software
dnl Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
dnl
ifdef(`need_spi', `dnl
/* spi defines */
pin(SPI_MOSI, PB5, OUTPUT)
pin(SPI_MISO, PB6)
pin(SPI_SCK, PB7, OUTPUT)
pin(SPI_CS_HARDWARE, PB4, OUTPUT)
')dnl
ifdef(`conf_I2C_MASTER', `
/* I2C pins */
pin(SDA, PC1)
pin(SCL, PC0)
')dnl
#define ADC_CHANNELS 8
| {
"language": "Assembly"
} |
/* Taxonomy Classification: 0000300602130000000010 */
/*
* WRITE/READ 0 write
* WHICH BOUND 0 upper
* DATA TYPE 0 char
* MEMORY LOCATION 0 stack
* SCOPE 3 inter-file/inter-proc
* CONTAINER 0 no
* POINTER 0 no
* INDEX COMPLEXITY 6 N/A
* ADDRESS COMPLEXITY 0 constant
* LENGTH COMPLEXITY 2 constant
* ADDRESS ALIAS 1 yes, one level
* INDEX ALIAS 3 N/A
* LOCAL CONTROL FLOW 0 none
* SECONDARY CONTROL FLOW 0 none
* LOOP STRUCTURE 0 no
* LOOP COMPLEXITY 0 N/A
* ASYNCHRONY 0 no
* TAINT 0 no
* RUNTIME ENV. DEPENDENCE 0 no
* MAGNITUDE 0 no overflow
* CONTINUOUS/DISCRETE 1 continuous
* SIGNEDNESS 0 no
*/
/*
Copyright 2004 M.I.T.
Permission is hereby granted, without written agreement or royalty fee, to use,
copy, modify, and distribute this software and its documentation for any
purpose, provided that the above copyright notice and the following three
paragraphs appear in all copies of this software.
IN NO EVENT SHALL M.I.T. BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE
AND ITS DOCUMENTATION, EVEN IF M.I.T. HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMANGE.
M.I.T. SPECIFICALLY DISCLAIMS ANY WARRANTIES INCLUDING, BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
AND NON-INFRINGEMENT.
THE SOFTWARE IS PROVIDED ON AN "AS-IS" BASIS AND M.I.T. HAS NO OBLIGATION TO
PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
#include <string.h>
int main(int argc, char *argv[])
{
char src[10];
char buf[10];
memset(src, 'A', 10);
src[10 - 1] = '\0';
/* OK */
strncpy(buf, src, 10);
return 0;
}
| {
"language": "Assembly"
} |