text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185 values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "softfloat.h"
float64 softfloat_roundPackToF64(bool sign, int16_t exp, uint64_t sig, struct softfloat_status_t *status)
{
uint8_t roundingMode;
bool roundNearEven;
uint16_t roundIncrement, roundBits;
bool isTiny;
uint64_t uiZ;
uint64_t sigRef;
/*your_sha256_hash--------
*your_sha256_hash--------*/
roundingMode = softfloat_getRoundingMode(status);
roundNearEven = (roundingMode == softfloat_round_near_even);
roundIncrement = 0x200;
if (! roundNearEven && (roundingMode != softfloat_round_near_maxMag)) {
roundIncrement =
(roundingMode == (sign ? softfloat_round_min : softfloat_round_max)) ? 0x3FF : 0;
}
roundBits = sig & 0x3FF;
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (0x7FD <= (uint16_t) exp) {
if (exp < 0) {
/*your_sha256_hash
*your_sha256_hash*/
isTiny = (exp < -1) || (sig + roundIncrement < UINT64_C(0x8000000000000000));
if (isTiny && ! softfloat_isMaskedException(status, softfloat_flag_underflow)) {
softfloat_raiseFlags(status, softfloat_flag_underflow);
exp += 1536;
}
else {
sig = softfloat_shiftRightJam64(sig, -exp);
exp = 0;
roundBits = sig & 0x3FF;
if (isTiny) {
if (softfloat_flushUnderflowToZero(status)) {
softfloat_raiseFlags(status, softfloat_flag_underflow | softfloat_flag_inexact);
return packToF64UI(sign, 0, 0);
}
if (roundBits) softfloat_raiseFlags(status, softfloat_flag_underflow);
}
}
} else if ((0x7FD < exp) || (UINT64_C(0x8000000000000000) <= sig + roundIncrement)) {
/*your_sha256_hash
*your_sha256_hash*/
softfloat_raiseFlags(status, softfloat_flag_overflow);
if (roundBits || softfloat_isMaskedException(status, softfloat_flag_overflow)) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
if (roundIncrement != 0) softfloat_setRoundingUp(status);
}
uiZ = packToF64UI(sign, 0x7FF, 0) - ! roundIncrement;
return uiZ;
}
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
sigRef = sig;
sig = (sig + roundIncrement)>>10;
sig &= ~(uint64_t) (! (roundBits ^ 0x200) & roundNearEven);
if (! sig) exp = 0;
if (roundBits) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
if ((sig << 10) > sigRef) softfloat_setRoundingUp(status);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
return packToF64UI(sign, exp, sig);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_roundPackToF64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,059 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
struct exp32_sig128 softfloat_normSubnormalF128Sig(uint64_t sig64, uint64_t sig0)
{
int8_t shiftDist;
struct exp32_sig128 z;
if (! sig64) {
shiftDist = softfloat_countLeadingZeros64(sig0) - 15;
z.exp = -63 - shiftDist;
if (shiftDist < 0) {
z.sig.v64 = sig0>>-shiftDist;
z.sig.v0 = sig0<<(shiftDist & 63);
} else {
z.sig.v64 = sig0<<shiftDist;
z.sig.v0 = 0;
}
} else {
shiftDist = softfloat_countLeadingZeros64(sig64) - 15;
z.exp = 1 - shiftDist;
z.sig = softfloat_shortShiftLeft128(sig64, sig0, shiftDist);
}
return z;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_normSubnormalF128Sig.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 545 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "softfloat_types.h"
#ifndef softfloat_sub128
struct uint128 softfloat_sub128(uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0)
{
struct uint128 z;
z.v0 = a0 - b0;
z.v64 = a64 - b64 - (a0 < b0);
return z;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/s_sub128.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 419 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
float16 f32_to_f16(float32 a, struct softfloat_status_t *status)
{
bool sign;
int16_t exp;
uint32_t frac;
struct commonNaN commonNaN;
uint16_t uiZ, frac16;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF32UI(a);
exp = expF32UI(a);
frac = fracF32UI(a);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (exp == 0xFF) {
if (frac) {
softfloat_f32UIToCommonNaN(a, &commonNaN, status);
uiZ = softfloat_commonNaNToF16UI(&commonNaN);
} else {
uiZ = packToF16UI(sign, 0x1F, 0);
}
return uiZ;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (!exp && frac) {
if (softfloat_denormalsAreZeros(status))
return packToF16UI(sign, 0, 0);
softfloat_raiseFlags(status, softfloat_flag_denormal);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
frac16 = frac>>9 | ((frac & 0x1FF) != 0);
if (! (exp | frac16)) {
return packToF16UI(sign, 0, 0);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
return softfloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f32_to_f16.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 717 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
extFloat80_t softfloat_normRoundPackToExtF80(bool sign, int32_t exp,
uint64_t sig,
uint64_t sigExtra,
uint8_t roundingPrecision,
struct softfloat_status_t *status)
{
int8_t shiftDist;
struct uint128 sig128;
if (! sig) {
exp -= 64;
sig = sigExtra;
sigExtra = 0;
}
shiftDist = softfloat_countLeadingZeros64(sig);
exp -= shiftDist;
if (shiftDist) {
sig128 = softfloat_shortShiftLeft128(sig, sigExtra, shiftDist);
sig = sig128.v64;
sigExtra = sig128.v0;
}
return softfloat_roundPackToExtF80(sign, exp, sig, sigExtra, roundingPrecision, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_normRoundPackToExtF80.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 524 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "primitiveTypes.h"
#include "softfloat.h"
#include "specialize.h"
float128_t f128_mulAdd(float128_t a, float128_t b, float128_t c, uint8_t op, struct softfloat_status_t *status)
{
bool signA;
int32_t expA;
struct uint128 sigA;
bool signB;
int32_t expB;
struct uint128 sigB;
bool signC;
int32_t expC;
struct uint128 sigC;
bool signZ;
uint64_t magBits;
struct uint128 uiZ;
struct exp32_sig128 normExpSig;
int32_t expZ;
uint64_t sig256Z[4];
struct uint128 sigZ;
int32_t shiftDist, expDiff;
struct uint128 x128;
uint64_t sig256C[4];
static uint64_t zero256[4] = INIT_UINTM4(0, 0, 0, 0);
uint64_t sigZExtra, sig256Z0;
uint64_t uiA64, uiA0;
uint64_t uiB64, uiB0;
uint64_t uiC64, uiC0;
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiA64 = a.v64;
uiA0 = a.v0;
uiB64 = b.v64;
uiB0 = b.v0;
uiC64 = c.v64;
uiC0 = c.v0;
/*your_sha256_hash--------
*your_sha256_hash--------*/
signA = signF128UI64(uiA64);
expA = expF128UI64(uiA64);
sigA.v64 = fracF128UI64(uiA64);
sigA.v0 = uiA0;
signB = signF128UI64(uiB64);
expB = expF128UI64(uiB64);
sigB.v64 = fracF128UI64(uiB64);
sigB.v0 = uiB0;
signC = signF128UI64(uiC64) ^ ((op & softfloat_mulAdd_subC) != 0);
expC = expF128UI64(uiC64);
sigC.v64 = fracF128UI64(uiC64);
sigC.v0 = uiC0;
signZ = signA ^ signB ^ ((op & softfloat_mulAdd_subProd) != 0);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (expA == 0x7FFF) {
if ((sigA.v64 | sigA.v0) || ((expB == 0x7FFF) && (sigB.v64 | sigB.v0))) {
goto propagateNaN_ABC;
}
magBits = expB | sigB.v64 | sigB.v0;
goto infProdArg;
}
if (expB == 0x7FFF) {
if (sigB.v64 | sigB.v0) goto propagateNaN_ABC;
magBits = expA | sigA.v64 | sigA.v0;
goto infProdArg;
}
if (expC == 0x7FFF) {
if (sigC.v64 | sigC.v0) {
uiZ.v64 = 0;
uiZ.v0 = 0;
goto propagateNaN_ZC;
}
uiZ.v64 = uiC64;
uiZ.v0 = uiC0;
return uiZ;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! expA) {
if (! (sigA.v64 | sigA.v0)) goto zeroProd;
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF128Sig(sigA.v64, sigA.v0);
expA = normExpSig.exp;
sigA = normExpSig.sig;
}
if (! expB) {
if (! (sigB.v64 | sigB.v0)) goto zeroProd;
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF128Sig(sigB.v64, sigB.v0);
expB = normExpSig.exp;
sigB = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expZ = expA + expB - 0x3FFE;
sigA.v64 |= UINT64_C(0x0001000000000000);
sigB.v64 |= UINT64_C(0x0001000000000000);
sigA = softfloat_shortShiftLeft128(sigA.v64, sigA.v0, 8);
sigB = softfloat_shortShiftLeft128(sigB.v64, sigB.v0, 15);
softfloat_mul128To256M(sigA.v64, sigA.v0, sigB.v64, sigB.v0, sig256Z);
sigZ.v64 = sig256Z[indexWord(4, 3)];
sigZ.v0 = sig256Z[indexWord(4, 2)];
shiftDist = 0;
if (! (sigZ.v64 & UINT64_C(0x0100000000000000))) {
--expZ;
shiftDist = -1;
}
if (! expC) {
if (! (sigC.v64 | sigC.v0)) {
shiftDist += 8;
goto sigZ;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF128Sig(sigC.v64, sigC.v0);
expC = normExpSig.exp;
sigC = normExpSig.sig;
}
sigC.v64 |= UINT64_C(0x0001000000000000);
sigC = softfloat_shortShiftLeft128(sigC.v64, sigC.v0, 8);
/*your_sha256_hash--------
*your_sha256_hash--------*/
expDiff = expZ - expC;
if (expDiff < 0) {
expZ = expC;
if ((signZ == signC) || (expDiff < -1)) {
shiftDist -= expDiff;
if (shiftDist) {
sigZ = softfloat_shiftRightJam128(sigZ.v64, sigZ.v0, shiftDist);
}
} else {
if (! shiftDist) {
x128 = softfloat_shortShiftRight128(sig256Z[indexWord(4, 1)], sig256Z[indexWord(4, 0)], 1);
sig256Z[indexWord(4, 1)] = (sigZ.v0<<63) | x128.v64;
sig256Z[indexWord(4, 0)] = x128.v0;
sigZ = softfloat_shortShiftRight128(sigZ.v64, sigZ.v0, 1);
sig256Z[indexWord(4, 3)] = sigZ.v64;
sig256Z[indexWord(4, 2)] = sigZ.v0;
}
}
} else {
if (shiftDist) softfloat_add256M(sig256Z, sig256Z, sig256Z);
if (! expDiff) {
sigZ.v64 = sig256Z[indexWord(4, 3)];
sigZ.v0 = sig256Z[indexWord(4, 2)];
} else {
sig256C[indexWord(4, 3)] = sigC.v64;
sig256C[indexWord(4, 2)] = sigC.v0;
sig256C[indexWord(4, 1)] = 0;
sig256C[indexWord(4, 0)] = 0;
softfloat_shiftRightJam256M(sig256C, expDiff, sig256C);
}
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = 8;
if (signZ == signC) {
/*your_sha256_hash----
*your_sha256_hash----*/
if (expDiff <= 0) {
sigZ = softfloat_add128(sigC.v64, sigC.v0, sigZ.v64, sigZ.v0);
} else {
softfloat_add256M(sig256Z, sig256C, sig256Z);
sigZ.v64 = sig256Z[indexWord(4, 3)];
sigZ.v0 = sig256Z[indexWord(4, 2)];
}
if (sigZ.v64 & UINT64_C(0x0200000000000000)) {
++expZ;
shiftDist = 9;
}
} else {
/*your_sha256_hash----
*your_sha256_hash----*/
if (expDiff < 0) {
signZ = signC;
if (expDiff < -1) {
sigZ = softfloat_sub128(sigC.v64, sigC.v0, sigZ.v64, sigZ.v0);
sigZExtra = sig256Z[indexWord(4, 1)] | sig256Z[indexWord(4, 0)];
if (sigZExtra) {
sigZ = softfloat_sub128(sigZ.v64, sigZ.v0, 0, 1);
}
if (! (sigZ.v64 & UINT64_C(0x0100000000000000))) {
--expZ;
shiftDist = 7;
}
goto shiftRightRoundPack;
} else {
sig256C[indexWord(4, 3)] = sigC.v64;
sig256C[indexWord(4, 2)] = sigC.v0;
sig256C[indexWord(4, 1)] = 0;
sig256C[indexWord(4, 0)] = 0;
softfloat_sub256M(sig256C, sig256Z, sig256Z);
}
} else if (! expDiff) {
sigZ = softfloat_sub128(sigZ.v64, sigZ.v0, sigC.v64, sigC.v0);
if (! (sigZ.v64 | sigZ.v0) && ! sig256Z[indexWord(4, 1)] && ! sig256Z[indexWord(4, 0)]) {
goto completeCancellation;
}
sig256Z[indexWord(4, 3)] = sigZ.v64;
sig256Z[indexWord(4, 2)] = sigZ.v0;
if (sigZ.v64 & UINT64_C(0x8000000000000000)) {
signZ = ! signZ;
softfloat_sub256M(zero256, sig256Z, sig256Z);
}
} else {
softfloat_sub256M(sig256Z, sig256C, sig256Z);
if (1 < expDiff) {
sigZ.v64 = sig256Z[indexWord(4, 3)];
sigZ.v0 = sig256Z[indexWord(4, 2)];
if (! (sigZ.v64 & UINT64_C(0x0100000000000000))) {
--expZ;
shiftDist = 7;
}
goto sigZ;
}
}
/*your_sha256_hash----
*your_sha256_hash----*/
sigZ.v64 = sig256Z[indexWord(4, 3)];
sigZ.v0 = sig256Z[indexWord(4, 2)];
sigZExtra = sig256Z[indexWord(4, 1)];
sig256Z0 = sig256Z[indexWord(4, 0)];
if (sigZ.v64) {
if (sig256Z0) sigZExtra |= 1;
} else {
expZ -= 64;
sigZ.v64 = sigZ.v0;
sigZ.v0 = sigZExtra;
sigZExtra = sig256Z0;
if (! sigZ.v64) {
expZ -= 64;
sigZ.v64 = sigZ.v0;
sigZ.v0 = sigZExtra;
sigZExtra = 0;
if (! sigZ.v64) {
expZ -= 64;
sigZ.v64 = sigZ.v0;
sigZ.v0 = 0;
}
}
}
shiftDist = softfloat_countLeadingZeros64(sigZ.v64);
expZ += 7 - shiftDist;
shiftDist = 15 - shiftDist;
if (0 < shiftDist) goto shiftRightRoundPack;
if (shiftDist) {
shiftDist = -shiftDist;
sigZ = softfloat_shortShiftLeft128(sigZ.v64, sigZ.v0, shiftDist);
x128 = softfloat_shortShiftLeft128(0, sigZExtra, shiftDist);
sigZ.v0 |= x128.v64;
sigZExtra = x128.v0;
}
goto roundPack;
}
sigZ:
sigZExtra = sig256Z[indexWord(4, 1)] | sig256Z[indexWord(4, 0)];
shiftRightRoundPack:
sigZExtra = (uint64_t) (sigZ.v0<<(64 - shiftDist)) | (sigZExtra != 0);
sigZ = softfloat_shortShiftRight128(sigZ.v64, sigZ.v0, shiftDist);
roundPack:
return softfloat_roundPackToF128(signZ, expZ - 1, sigZ.v64, sigZ.v0, sigZExtra, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN_ABC:
uiZ = softfloat_propagateNaNF128UI(uiA64, uiA0, uiB64, uiB0, status);
goto propagateNaN_ZC;
/*your_sha256_hash--------
*your_sha256_hash--------*/
infProdArg:
if ((sigC.v64 | sigC.v0) && expC == 0x7FFF) goto propagateNaN_ZC;
if (magBits) {
uiZ.v64 = packToF128UI64(signZ, 0x7FFF, 0);
uiZ.v0 = 0;
if (expC != 0x7FFF) return uiZ;
if (signZ == signC) return uiZ;
}
softfloat_raiseFlags(status, softfloat_flag_invalid);
uiZ.v64 = defaultNaNF128UI64;
uiZ.v0 = defaultNaNF128UI0;
propagateNaN_ZC:
uiZ = softfloat_propagateNaNF128UI(uiZ.v64, uiZ.v0, uiC64, uiC0, status);
return uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
zeroProd:
uiZ.v64 = uiC64;
uiZ.v0 = uiC0;
if (! (expC | sigC.v64 | sigC.v0) && (signZ != signC)) {
completeCancellation:
uiZ.v64 = packToF128UI64((softfloat_getRoundingMode(status) == softfloat_round_min), 0, 0);
uiZ.v0 = 0;
}
return uiZ;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f128_mulAdd.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,697 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
uint32_t f32_to_ui32(float32 a, uint8_t roundingMode, bool exact, struct softfloat_status_t *status)
{
bool sign;
int16_t exp;
uint32_t sig;
uint64_t sig64;
int16_t shiftDist;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF32UI(a);
exp = expF32UI(a);
sig = fracF32UI(a);
if (softfloat_denormalsAreZeros(status))
if (!exp && sig) sig = 0;
/*your_sha256_hash--------
*your_sha256_hash--------*/
#if (ui32_fromNaN != ui32_fromPosOverflow) || (ui32_fromNaN != ui32_fromNegOverflow)
if ((exp == 0xFF) && sig) {
#if (ui32_fromNaN == ui32_fromPosOverflow)
sign = 0;
#elif (ui32_fromNaN == ui32_fromNegOverflow)
sign = 1;
#else
softfloat_raiseFlags(status, softfloat_flag_invalid);
return ui32_fromNaN;
#endif
}
#endif
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (exp) sig |= 0x00800000;
else if (softfloat_denormalsAreZeros(status)) sig = 0;
sig64 = (uint64_t) sig<<32;
shiftDist = 0xAA - exp;
if (0 < shiftDist) sig64 = softfloat_shiftRightJam64(sig64, shiftDist);
return softfloat_roundToUI32(sign, sig64, roundingMode, exact, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f32_to_ui32.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 726 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "primitives.h"
const uint_least8_t softfloat_countLeadingZeros8[256] = {
8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
``` | /content/code_sandbox/src/cpu/softfloat3e/s_countLeadingZeros8.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,137 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
float32 f32_sqrt(float32 a, struct softfloat_status_t *status)
{
bool signA;
int16_t expA;
uint32_t sigA;
struct exp16_sig32 normExpSig;
int16_t expZ;
uint32_t sigZ, shiftedSigZ;
uint32_t negRem;
/*your_sha256_hash--------
*your_sha256_hash--------*/
signA = signF32UI(a);
expA = expF32UI(a);
sigA = fracF32UI(a);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (expA == 0xFF) {
if (sigA) {
return softfloat_propagateNaNF32UI(a, 0, status);
}
if (! signA) return a;
goto invalid;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) {
sigA = 0;
a = packToF32UI(signA, 0, 0);
}
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (signA) {
if (! (expA | sigA)) return a;
goto invalid;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! expA) {
if (! sigA) return a;
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF32Sig(sigA);
expA = normExpSig.exp;
sigA = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expZ = ((expA - 0x7F)>>1) + 0x7E;
expA &= 1;
sigA = (sigA | 0x00800000)<<8;
sigZ =
((uint64_t) sigA * softfloat_approxRecipSqrt32_1(expA, sigA))>>32;
if (expA) sigZ >>= 1;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sigZ += 2;
if ((sigZ & 0x3F) < 2) {
shiftedSigZ = sigZ>>2;
negRem = shiftedSigZ * shiftedSigZ;
sigZ &= ~3;
if (negRem & 0x80000000) {
sigZ |= 1;
} else {
if (negRem) --sigZ;
}
}
return softfloat_roundPackToF32(0, expZ, sigZ, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
invalid:
softfloat_raiseFlags(status, softfloat_flag_invalid);
return defaultNaNF32UI;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f32_sqrt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,002 |
```c++
/*============================================================================
This source file is an extension to the SoftFloat IEC/IEEE Floating-point
Arithmetic Package, Release 2b, written for Bochs (x86 achitecture simulator)
floating point emulation.
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
Derivative works are acceptable, even for commercial purposes, so long as
(1) the source code for the derivative work includes prominent notice that
the work is derivative, and (2) the source code includes prominent notice with
these four paragraphs for those parts of this code that are retained.
=============================================================================*/
/*============================================================================
* Written for Bochs (x86 achitecture simulator) by
* Stanislav Shwartsman [sshwarts at sourceforge net]
* ==========================================================================*/
#define FLOAT128
#include "config.h"
#include "softfloat.h"
#include "specialize.h"
#include "fpu_trans.h"
#include "fpu_constant.h"
#include "poly.h"
#define FPATAN_ARR_SIZE 11
static const float128_t float128_one =
packFloat128(BX_CONST64(0x3fff000000000000), BX_CONST64(0x0000000000000000));
static const float128_t float128_sqrt3 =
packFloat128(BX_CONST64(0x3fffbb67ae8584ca), BX_CONST64(0xa73b25742d7078b8));
static const floatx80 floatx80_pi =
packFloatx80(0, 0x4000, BX_CONST64(0xc90fdaa22168c235));
static const float128_t float128_pi2 =
packFloat128(BX_CONST64(0x3fff921fb54442d1), BX_CONST64(0x8469898CC5170416));
static const float128_t float128_pi4 =
packFloat128(BX_CONST64(0x3ffe921fb54442d1), BX_CONST64(0x8469898CC5170416));
static const float128_t float128_pi6 =
packFloat128(BX_CONST64(0x3ffe0c152382d736), BX_CONST64(0x58465BB32E0F580F));
static float128_t atan_arr[FPATAN_ARR_SIZE] =
{
PACK_FLOAT_128(0x3fff000000000000, 0x0000000000000000), /* 1 */
PACK_FLOAT_128(0xbffd555555555555, 0x5555555555555555), /* 3 */
PACK_FLOAT_128(0x3ffc999999999999, 0x999999999999999a), /* 5 */
PACK_FLOAT_128(0xbffc249249249249, 0x2492492492492492), /* 7 */
PACK_FLOAT_128(0x3ffbc71c71c71c71, 0xc71c71c71c71c71c), /* 9 */
PACK_FLOAT_128(0xbffb745d1745d174, 0x5d1745d1745d1746), /* 11 */
PACK_FLOAT_128(0x3ffb3b13b13b13b1, 0x3b13b13b13b13b14), /* 13 */
PACK_FLOAT_128(0xbffb111111111111, 0x1111111111111111), /* 15 */
PACK_FLOAT_128(0x3ffae1e1e1e1e1e1, 0xe1e1e1e1e1e1e1e2), /* 17 */
PACK_FLOAT_128(0xbffaaf286bca1af2, 0x86bca1af286bca1b), /* 19 */
PACK_FLOAT_128(0x3ffa861861861861, 0x8618618618618618) /* 21 */
};
extern float128_t OddPoly(float128_t x, const float128_t *arr, int n, softfloat_status_t &status);
/* |x| < 1/4 */
static float128_t poly_atan(float128_t x1, softfloat_status_t &status)
{
/*
// 3 5 7 9 11 13 15 17
// x x x x x x x x
// atan(x) ~ x - --- + --- - --- + --- - ---- + ---- - ---- + ----
// 3 5 7 9 11 13 15 17
//
// 2 4 6 8 10 12 14 16
// x x x x x x x x
// = x * [ 1 - --- + --- - --- + --- - ---- + ---- - ---- + ---- ]
// 3 5 7 9 11 13 15 17
//
// 5 5
// -- 4k -- 4k+2
// p(x) = > C * x q(x) = > C * x
// -- 2k -- 2k+1
// k=0 k=0
//
// 2
// atan(x) ~ x * [ p(x) + x * q(x) ]
//
*/
return OddPoly(x1, (const float128_t*) atan_arr, FPATAN_ARR_SIZE, status);
}
// =================================================
// FPATAN Compute arctan(y/x)
// =================================================
//
// Uses the following identities:
//
// 1. ----------------------------------------------------------
//
// atan(-x) = -atan(x)
//
// 2. ----------------------------------------------------------
//
// x + y
// atan(x) + atan(y) = atan -------, xy < 1
// 1-xy
//
// x + y
// atan(x) + atan(y) = atan ------- + PI, x > 0, xy > 1
// 1-xy
//
// x + y
// atan(x) + atan(y) = atan ------- - PI, x < 0, xy > 1
// 1-xy
//
// 3. ----------------------------------------------------------
//
// atan(x) = atan(INF) + atan(- 1/x)
//
// x-1
// atan(x) = PI/4 + atan( ----- )
// x+1
//
// x * sqrt(3) - 1
// atan(x) = PI/6 + atan( ----------------- )
// x + sqrt(3)
//
// 4. ----------------------------------------------------------
// 3 5 7 9 2n+1
// x x x x n x
// atan(x) = x - --- + --- - --- + --- - ... + (-1) ------ + ...
// 3 5 7 9 2n+1
//
floatx80 fpatan(floatx80 a, floatx80 b, softfloat_status_t &status)
{
/*your_sha256_hash------------
| The pattern for a default generated extended double-precision NaN.
*your_sha256_hash------------*/
const floatx80 floatx80_default_nan =
packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
// handle unsupported extended double-precision floating encodings
if (extF80_isUnsupported(a) || extF80_isUnsupported(b)) {
softfloat_raiseFlags(&status, softfloat_flag_invalid);
return floatx80_default_nan;
}
uint64_t aSig = extF80_fraction(a);
int32_t aExp = extF80_exp(a);
int aSign = extF80_sign(a);
uint64_t bSig = extF80_fraction(b);
int32_t bExp = extF80_exp(b);
int bSign = extF80_sign(b);
int zSign = aSign ^ bSign;
if (bExp == 0x7FFF)
{
if (bSig<<1)
return softfloat_propagateNaNExtF80UI(a.signExp, aSig, b.signExp, bSig, &status);
if (aExp == 0x7FFF) {
if (aSig<<1)
return softfloat_propagateNaNExtF80UI(a.signExp, aSig, b.signExp, bSig, &status);
if (aSign) /* return 3PI/4 */
return softfloat_roundPackToExtF80(bSign, FLOATX80_3PI4_EXP, FLOAT_3PI4_HI, FLOAT_3PI4_LO, 80, &status);
else /* return PI/4 */
return softfloat_roundPackToExtF80(bSign, FLOATX80_PI4_EXP, FLOAT_PI_HI, FLOAT_PI_LO, 80, &status);
}
if (aSig && ! aExp)
softfloat_raiseFlags(&status, softfloat_flag_denormal);
/* return PI/2 */
return softfloat_roundPackToExtF80(bSign, FLOATX80_PI2_EXP, FLOAT_PI_HI, FLOAT_PI_LO, 80, &status);
}
if (aExp == 0x7FFF)
{
if (aSig<<1)
return softfloat_propagateNaNExtF80UI(a.signExp, aSig, b.signExp, bSig, &status);
if (bSig && ! bExp)
softfloat_raiseFlags(&status, softfloat_flag_denormal);
return_PI_or_ZERO:
if (aSign) /* return PI */
return softfloat_roundPackToExtF80(bSign, FLOATX80_PI_EXP, FLOAT_PI_HI, FLOAT_PI_LO, 80, &status);
else /* return 0 */
return packToExtF80(bSign, 0, 0);
}
if (! bExp)
{
if (! bSig) {
if (aSig && ! aExp) softfloat_raiseFlags(&status, softfloat_flag_denormal);
goto return_PI_or_ZERO;
}
softfloat_raiseFlags(&status, softfloat_flag_denormal);
struct exp32_sig64 normExpSig = softfloat_normSubnormalExtF80Sig(bSig);
bExp = normExpSig.exp + 1;
bSig = normExpSig.sig;
}
if (! aExp)
{
if (! aSig) /* return PI/2 */
return softfloat_roundPackToExtF80(bSign, FLOATX80_PI2_EXP, FLOAT_PI_HI, FLOAT_PI_LO, 80, &status);
softfloat_raiseFlags(&status, softfloat_flag_denormal);
struct exp32_sig64 normExpSig = softfloat_normSubnormalExtF80Sig(aSig);
aExp = normExpSig.exp + 1;
aSig = normExpSig.sig;
}
softfloat_raiseFlags(&status, softfloat_flag_inexact);
/* |a| = |b| ==> return PI/4 */
if (aSig == bSig && aExp == bExp) {
if (aSign)
return softfloat_roundPackToExtF80(bSign, FLOATX80_3PI4_EXP, FLOAT_3PI4_HI, FLOAT_3PI4_LO, 80, &status);
else
return softfloat_roundPackToExtF80(bSign, FLOATX80_PI4_EXP, FLOAT_PI_HI, FLOAT_PI_LO, 80, &status);
}
/* ******************************** */
/* using float128 for approximation */
/* ******************************** */
float128_t a128 = softfloat_normRoundPackToF128(0, aExp-0x10, aSig, 0, &status);
float128_t b128 = softfloat_normRoundPackToF128(0, bExp-0x10, bSig, 0, &status);
float128_t x;
int swap = 0, add_pi6 = 0, add_pi4 = 0;
if (aExp > bExp || (aExp == bExp && aSig > bSig))
{
x = f128_div(b128, a128, &status);
}
else {
x = f128_div(a128, b128, &status);
swap = 1;
}
int32_t xExp = expF128UI64(x.v64);
if (xExp <= FLOATX80_EXP_BIAS-40)
goto approximation_completed;
if (x.v64 >= BX_CONST64(0x3ffe800000000000)) // 3/4 < x < 1
{
/*
arctan(x) = arctan((x-1)/(x+1)) + pi/4
*/
float128_t t1 = f128_sub(x, float128_one, &status);
float128_t t2 = f128_add(x, float128_one, &status);
x = f128_div(t1, t2, &status);
add_pi4 = 1;
}
else
{
/* argument correction */
if (xExp >= 0x3FFD) // 1/4 < x < 3/4
{
/*
arctan(x) = arctan((x*sqrt(3)-1)/(x+sqrt(3))) + pi/6
*/
float128_t t1 = f128_mul(x, float128_sqrt3, &status);
float128_t t2 = f128_add(x, float128_sqrt3, &status);
x = f128_sub(t1, float128_one, &status);
x = f128_div(x, t2, &status);
add_pi6 = 1;
}
}
x = poly_atan(x, status);
if (add_pi6) x = f128_add(x, float128_pi6, &status);
if (add_pi4) x = f128_add(x, float128_pi4, &status);
approximation_completed:
if (swap) x = f128_sub(float128_pi2, x, &status);
floatx80 result = f128_to_extF80(x, &status);
if (zSign) floatx80_chs(result);
int rSign = extF80_sign(result);
if (!bSign && rSign)
return extF80_add(result, floatx80_pi, &status);
if (bSign && !rSign)
return extF80_sub(result, floatx80_pi, &status);
return result;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/fpatan.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,384 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
#define SOFTFLOAT_FAST_DIV32TO16 1
extern const uint16_t softfloat_approxRecip_1k0s[];
extern const uint16_t softfloat_approxRecip_1k1s[];
float16 f16_div(float16 a, float16 b, struct softfloat_status_t *status)
{
bool signA;
int8_t expA;
uint16_t sigA;
bool signB;
int8_t expB;
uint16_t sigB;
bool signZ;
struct exp8_sig16 normExpSig;
int8_t expZ;
#ifdef SOFTFLOAT_FAST_DIV32TO16
uint32_t sig32A;
uint16_t sigZ;
#endif
/*your_sha256_hash--------
*your_sha256_hash--------*/
signA = signF16UI(a);
expA = expF16UI(a);
sigA = fracF16UI(a);
signB = signF16UI(b);
expB = expF16UI(b);
sigB = fracF16UI(b);
signZ = signA ^ signB;
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) sigA = 0;
if (!expB) sigB = 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (expA == 0x1F) {
if (sigA) goto propagateNaN;
if (expB == 0x1F) {
if (sigB) goto propagateNaN;
goto invalid;
}
if (sigB && !expB)
softfloat_raiseFlags(status, softfloat_flag_denormal);
goto infinity;
}
if (expB == 0x1F) {
if (sigB) goto propagateNaN;
if (sigA && !expA)
softfloat_raiseFlags(status, softfloat_flag_denormal);
goto zero;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! expB) {
if (! sigB) {
if (! (expA | sigA)) goto invalid;
softfloat_raiseFlags(status, softfloat_flag_infinite);
goto infinity;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF16Sig(sigB);
expB = normExpSig.exp;
sigB = normExpSig.sig;
}
if (! expA) {
if (! sigA) goto zero;
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF16Sig(sigA);
expA = normExpSig.exp;
sigA = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expZ = expA - expB + 0xE;
sigA |= 0x0400;
sigB |= 0x0400;
#ifdef SOFTFLOAT_FAST_DIV32TO16
if (sigA < sigB) {
--expZ;
sig32A = (uint32_t) sigA<<15;
} else {
sig32A = (uint32_t) sigA<<14;
}
sigZ = sig32A / sigB;
if (! (sigZ & 7)) sigZ |= ((uint32_t) sigB * sigZ != sig32A);
#endif
return softfloat_roundPackToF16(signZ, expZ, sigZ, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN:
return softfloat_propagateNaNF16UI(a, b, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
invalid:
softfloat_raiseFlags(status, softfloat_flag_invalid);
return defaultNaNF16UI;
/*your_sha256_hash--------
*your_sha256_hash--------*/
infinity:
return packToF16UI(signZ, 0x1F, 0);
/*your_sha256_hash--------
*your_sha256_hash--------*/
zero:
return packToF16UI(signZ, 0, 0);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_div.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,284 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "primitives.h"
#include "specialize.h"
/*your_sha256_hash------------
| Converts the common NaN pointed to by `aPtr' into a 128-bit floating-point
| NaN, and returns the bit pattern of this value as an unsigned integer.
*your_sha256_hash------------*/
struct uint128 softfloat_commonNaNToF128UI(const struct commonNaN *aPtr)
{
struct uint128 uiZ;
uiZ = softfloat_shortShiftRight128(aPtr->v64, aPtr->v0, 16);
uiZ.v64 |= (uint64_t) aPtr->sign<<63 | UINT64_C(0x7FFF800000000000);
return uiZ;
}
/*your_sha256_hash------------
| Assuming the unsigned integer formed from concatenating `uiA64' and `uiA0'
| has the bit pattern of a 128-bit floating-point NaN, converts this NaN to
| the common NaN form, and stores the resulting common NaN at the location
| pointed to by `zPtr'. If the NaN is a signaling NaN, the invalid exception
| is raised.
*your_sha256_hash------------*/
void
softfloat_f128UIToCommonNaN(uint64_t uiA64, uint64_t uiA0, struct commonNaN *zPtr, struct softfloat_status_t *status)
{
struct uint128 NaNSig;
if (softfloat_isSigNaNF128UI(uiA64, uiA0)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
}
NaNSig = softfloat_shortShiftLeft128(uiA64, uiA0, 16);
zPtr->sign = uiA64>>63;
zPtr->v64 = NaNSig.v64;
zPtr->v0 = NaNSig.v0;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_commonNaNToF128UI.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 716 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
int32_t extF80_to_i32(extFloat80_t a, uint8_t roundingMode, bool exact, struct softfloat_status_t *status)
{
uint16_t uiA64;
bool sign;
int32_t exp;
uint64_t sig;
int32_t shiftDist;
// handle unsupported extended double-precision floating encodings
if (extF80_isUnsupported(a)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
return i32_fromNaN;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiA64 = a.signExp;
sign = signExtF80UI64(uiA64);
exp = expExtF80UI64(uiA64);
sig = a.signif;
/*your_sha256_hash--------
*your_sha256_hash--------*/
#if (i32_fromNaN != i32_fromPosOverflow) || (i32_fromNaN != i32_fromNegOverflow)
if ((exp == 0x7FFF) && (sig & UINT64_C(0x7FFFFFFFFFFFFFFF))) {
#if (i32_fromNaN == i32_fromPosOverflow)
sign = 0;
#elif (i32_fromNaN == i32_fromNegOverflow)
sign = 1;
#else
softfloat_raiseFlags(status, softfloat_flag_invalid);
return i32_fromNaN;
#endif
}
#endif
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = 0x4032 - exp;
if (shiftDist <= 0) shiftDist = 1;
sig = softfloat_shiftRightJam64(sig, shiftDist);
return softfloat_roundToI32(sign, sig, roundingMode, exact, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/extF80_to_i32.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 733 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Extracts the exponent portion of double-precision floating-point value 'a',
| and returns the result as a double-precision floating-point value
| representing unbiased integer exponent. The operation is performed according
| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
*your_sha256_hash------------*/
float64 f64_getExp(float64 a, struct softfloat_status_t *status)
{
int16_t expA;
uint64_t sigA;
struct exp16_sig64 normExpSig;
expA = expF64UI(a);
sigA = fracF64UI(a);
if (expA == 0x7FF) {
if (sigA) return softfloat_propagateNaNF64UI(a, 0, status);
return packToF64UI(0, 0x7FF, 0);
}
if (! expA) {
if (! sigA || softfloat_denormalsAreZeros(status))
return packToF64UI(1, 0x7FF, 0);
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF64Sig(sigA);
expA = normExpSig.exp;
}
return i32_to_f64((int32_t)(expA) - 0x3FF);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f64_getExp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 649 |
```objective-c
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
//
// You should have received a copy of the GNU Lesser General Public
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#ifndef _FPU_TRANS_H_
#define _FPU_TRANS_H_
#include "softfloat.h"
#include "softfloat-specialize.h"
#ifdef __cplusplus
extern "C" {
#endif
/*your_sha256_hash------------
| Software IEC/IEEE extended double-precision operations.
*your_sha256_hash------------*/
int floatx80_remainder(floatx80 a, floatx80 b, floatx80 *r, uint64_t *q, struct softfloat_status_t *status);
int floatx80_ieee754_remainder(floatx80 a, floatx80 b, floatx80 *r, uint64_t *q, struct softfloat_status_t *status);
floatx80 f2xm1(floatx80 a, struct softfloat_status_t *status);
#ifdef __cplusplus
floatx80 fyl2x(floatx80 a, floatx80 b, softfloat_status_t &status);
floatx80 fyl2xp1(floatx80 a, floatx80 b, softfloat_status_t &status);
floatx80 fpatan(floatx80 a, floatx80 b, softfloat_status_t &status);
/*your_sha256_hash------------
| Software IEC/IEEE extended double-precision trigonometric functions.
*your_sha256_hash------------*/
int fsincos(floatx80 a, floatx80 *sin_a, floatx80 *cos_a, softfloat_status_t &status);
int fsin(floatx80 &a, softfloat_status_t &status);
int fcos(floatx80 &a, softfloat_status_t &status);
int ftan(floatx80 &a, softfloat_status_t &status);
#else
floatx80 fyl2x(floatx80 a, floatx80 b, struct softfloat_status_t *status);
floatx80 fyl2xp1(floatx80 a, floatx80 b, struct softfloat_status_t *status);
floatx80 fpatan(floatx80 a, floatx80 b, struct softfloat_status_t *status);
/*your_sha256_hash------------
| Software IEC/IEEE extended double-precision trigonometric functions.
*your_sha256_hash------------*/
int fsincos(floatx80 a, floatx80 *sin_a, floatx80 *cos_a, struct softfloat_status_t *status);
int fsin(floatx80 *a, struct softfloat_status_t *status);
int fcos(floatx80 *a, struct softfloat_status_t *status);
int ftan(floatx80 *a, struct softfloat_status_t *status);
#endif
#ifdef __cplusplus
}
#endif
/*your_sha256_hash-------------
| Calculates the absolute value of the extended double-precision floating-point
| value `a'. The operation is performed according to the IEC/IEEE Standard
| for Binary Floating-Point Arithmetic.
*your_sha256_hash------------*/
#ifdef __cplusplus
static __inline floatx80 &floatx80_abs(floatx80 ®)
#else
static __inline floatx80 floatx80_abs(floatx80 reg)
#endif
{
reg.signExp &= 0x7FFF;
return reg;
}
/*your_sha256_hash-------------
| Changes the sign of the extended double-precision floating-point value 'a'.
| The operation is performed according to the IEC/IEEE Standard for Binary
| Floating-Point Arithmetic.
*your_sha256_hash------------*/
#ifdef __cplusplus
static __inline floatx80 &floatx80_chs(floatx80 ®)
#else
static __inline floatx80 floatx80_chs(floatx80 reg)
#endif
{
reg.signExp ^= 0x8000;
return reg;
}
#ifdef __cplusplus
static __inline floatx80 FPU_round_const(const floatx80 &a, int adj)
#else
static __inline floatx80 FPU_round_const(const floatx80 a, int adj)
#endif
{
floatx80 result = a;
result.signif += adj;
return result;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/fpu_trans.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 975 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#ifndef softfloat_countLeadingZeros64
#define softfloat_countLeadingZeros64 softfloat_countLeadingZeros64
#include "primitives.h"
uint8_t softfloat_countLeadingZeros64(uint64_t a)
{
uint8_t count;
uint32_t a32;
count = 0;
a32 = a>>32;
if (! a32) {
count = 32;
a32 = a;
}
/*your_sha256_hash--------
| From here, result is current count + count leading zeros of `a32'.
*your_sha256_hash--------*/
if (a32 < 0x10000) {
count += 16;
a32 <<= 16;
}
if (a32 < 0x1000000) {
count += 8;
a32 <<= 8;
}
count += softfloat_countLeadingZeros8[a32>>24];
return count;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/s_countLeadingZeros64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 540 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Interpreting the unsigned integer formed from concatenating `uiA64' and
| `uiA0' as a 128-bit floating-point value, and likewise interpreting the
| unsigned integer formed from concatenating `uiB64' and `uiB0' as another
| 128-bit floating-point value, and assuming at least on of these floating-
| point values is a NaN, returns the bit pattern of the combined NaN result.
| If either original floating-point value is a signaling NaN, the invalid
| exception is raised.
*your_sha256_hash------------*/
struct uint128
softfloat_propagateNaNF128UI(
uint64_t uiA64,
uint64_t uiA0,
uint64_t uiB64,
uint64_t uiB0,
struct softfloat_status_t *status
)
{
bool isSigNaNA;
struct uint128 uiZ;
isSigNaNA = softfloat_isSigNaNF128UI(uiA64, uiA0);
if (isSigNaNA || softfloat_isSigNaNF128UI(uiB64, uiB0)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
if (isSigNaNA) goto returnNonsigA;
}
if (isNaNF128UI(uiA64, uiA0)) {
returnNonsigA:
uiZ.v64 = uiA64;
uiZ.v0 = uiA0;
} else {
uiZ.v64 = uiB64;
uiZ.v0 = uiB0;
}
uiZ.v64 |= UINT64_C(0x0000800000000000);
return uiZ;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_propagateNaNF128UI.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 719 |
```html
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat Package Overview</TITLE>
</HEAD>
<BODY>
<H1>Package Overview for Berkeley SoftFloat Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<P>
Berkeley SoftFloat is a software implementation of binary floating-point that
conforms to the IEEE Standard for Floating-Point Arithmetic.
SoftFloat is distributed in the form of C source code.
Building the SoftFloat sources generates a library file (typically
<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) containing the
floating-point subroutines.
</P>
<P>
The SoftFloat package is documented in the following files in the
<CODE>doc</CODE> subdirectory:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD><A HREF="doc/SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A></TD>
<TD>Documentation for using the SoftFloat functions.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-source.html"><NOBR><CODE>SoftFloat-source.html</CODE></NOBR></A></TD>
<TD>Documentation for building SoftFloat.</TD>
</TR>
<TR>
<TD><A HREF="doc/SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></A><CODE> </CODE></NOBR></TD>
<TD>History of the major changes to SoftFloat.</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
Other files in the package comprise the source code for SoftFloat.
</P>
</BODY>
``` | /content/code_sandbox/src/cpu/softfloat3e/README.html | html | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 368 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
float32 softfloat_normRoundPackToF32(bool sign, int16_t exp, uint32_t sig, struct softfloat_status_t *status)
{
int8_t shiftDist = softfloat_countLeadingZeros32(sig) - 1;
exp -= shiftDist;
if ((7 <= shiftDist) && ((unsigned int) exp < 0xFD)) {
return packToF32UI(sign, sig ? exp : 0, sig<<(shiftDist - 7));
} else {
return softfloat_roundPackToF32(sign, exp, sig<<shiftDist, status);
}
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_normRoundPackToF32.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 470 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "softfloat_types.h"
#ifndef softfloat_mul128By32
struct uint128 softfloat_mul128By32(uint64_t a64, uint64_t a0, uint32_t b)
{
struct uint128 z;
uint64_t mid;
uint32_t carry;
z.v0 = a0 * b;
mid = (uint64_t) (uint32_t) (a0>>32) * b;
carry = (uint32_t) ((uint32_t) (z.v0>>32) - (uint32_t) mid);
z.v64 = a64 * b + (uint32_t) ((mid + carry)>>32);
return z;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/s_mul128By32.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 481 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Extracts the fractional portion of single-precision floating-point value `a',
| and returns the result as a single-precision floating-point value. The
| fractional results are precise. The operation is performed according to the
| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
*your_sha256_hash------------*/
float32 f32_frc(float32 a, struct softfloat_status_t *status)
{
int roundingMode = softfloat_getRoundingMode(status);
bool signA;
int16_t expA;
uint32_t sigA;
uint32_t lastBitMask;
uint32_t roundBitsMask;
signA = signF32UI(a);
expA = expF32UI(a);
sigA = fracF32UI(a);
if (expA == 0xFF) {
if (sigA) return softfloat_propagateNaNF32UI(a, 0, status);
softfloat_raiseFlags(status, softfloat_flag_invalid);
return defaultNaNF32UI;
}
if (expA >= 0x96) {
return packToF32UI(roundingMode == softfloat_round_down, 0, 0);
}
if (expA < 0x7F) {
if (! expA) {
if (! sigA || softfloat_denormalsAreZeros(status))
return packToF32UI(roundingMode == softfloat_round_down, 0, 0);
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (! softfloat_isMaskedException(status, softfloat_flag_underflow))
softfloat_raiseFlags(status, softfloat_flag_underflow);
if (softfloat_flushUnderflowToZero(status)) {
softfloat_raiseFlags(status, softfloat_flag_underflow | softfloat_flag_inexact);
return packToF32UI(signA, 0, 0);
}
}
return a;
}
lastBitMask = 1 << (0x96 - expA);
roundBitsMask = lastBitMask - 1;
sigA &= roundBitsMask;
sigA <<= 7;
expA--;
if (! sigA)
return packToF32UI(roundingMode == softfloat_round_down, 0, 0);
return softfloat_normRoundPackToF32(signA, expA, sigA, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f32_frc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 870 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
extern extFloat80_t softfloat_addMagsExtF80(uint16_t, uint64_t, uint16_t, uint64_t, bool, struct softfloat_status_t *);
extern extFloat80_t softfloat_subMagsExtF80(uint16_t, uint64_t, uint16_t, uint64_t, bool, struct softfloat_status_t *);
extFloat80_t extF80_add(extFloat80_t a, extFloat80_t b, struct softfloat_status_t *status)
{
uint16_t uiA64;
uint64_t uiA0;
bool signA;
uint16_t uiB64;
uint64_t uiB0;
bool signB;
// handle unsupported extended double-precision floating encodings
if (extF80_isUnsupported(a) || extF80_isUnsupported(b)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
a.signExp = defaultNaNExtF80UI64;
a.signif = defaultNaNExtF80UI0;
return a;
}
uiA64 = a.signExp;
uiA0 = a.signif;
signA = signExtF80UI64(uiA64);
uiB64 = b.signExp;
uiB0 = b.signif;
signB = signExtF80UI64(uiB64);
if (signA == signB) {
return softfloat_addMagsExtF80(uiA64, uiA0, uiB64, uiB0, signA, status);
} else {
return softfloat_subMagsExtF80(uiA64, uiA0, uiB64, uiB0, signA, status);
}
}
extFloat80_t extF80_sub(extFloat80_t a, extFloat80_t b, struct softfloat_status_t *status)
{
uint16_t uiA64;
uint64_t uiA0;
bool signA;
uint16_t uiB64;
uint64_t uiB0;
bool signB;
// handle unsupported extended double-precision floating encodings
if (extF80_isUnsupported(a) || extF80_isUnsupported(b)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
a.signExp = defaultNaNExtF80UI64;
a.signif = defaultNaNExtF80UI0;
return a;
}
uiA64 = a.signExp;
uiA0 = a.signif;
signA = signExtF80UI64(uiA64);
uiB64 = b.signExp;
uiB0 = b.signif;
signB = signExtF80UI64(uiB64);
if (signA == signB) {
return softfloat_subMagsExtF80(uiA64, uiA0, uiB64, uiB0, signA, status);
} else {
return softfloat_addMagsExtF80(uiA64, uiA0, uiB64, uiB0, signA, status);
}
}
``` | /content/code_sandbox/src/cpu/softfloat3e/extF80_addsub.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,003 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Compare between two half precision floating point numbers and return the
| smaller of them.
*your_sha256_hash------------*/
float16 f16_min(float16 a, float16 b, struct softfloat_status_t *status)
{
if (softfloat_denormalsAreZeros(status)) {
a = f16_denormal_to_zero(a);
b = f16_denormal_to_zero(b);
}
return (f16_compare_normal(a, b, status) == softfloat_relation_less) ? a : b;
}
/*your_sha256_hash------------
| Compare between two half precision floating point numbers and return the
| larger of them.
*your_sha256_hash------------*/
float16 f16_max(float16 a, float16 b, struct softfloat_status_t *status)
{
if (softfloat_denormalsAreZeros(status)) {
a = f16_denormal_to_zero(a);
b = f16_denormal_to_zero(b);
}
return (f16_compare_normal(a, b, status) == softfloat_relation_greater) ? a : b;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_minmax.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 581 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "softfloat_types.h"
#ifndef softfloat_shiftRightJam64Extra
struct uint64_extra
softfloat_shiftRightJam64Extra(uint64_t a, uint64_t extra, uint32_t dist)
{
struct uint64_extra z;
if (dist < 64) {
z.v = a>>dist;
z.extra = a<<(-dist & 63);
} else {
z.v = 0;
z.extra = (dist == 64) ? a : (a != 0);
}
z.extra |= (extra != 0);
return z;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/s_shiftRightJam64Extra.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 461 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
float16 softfloat_addMagsF16(uint16_t uiA, uint16_t uiB, struct softfloat_status_t *status)
{
int8_t expA;
uint16_t sigA;
int8_t expB;
uint16_t sigB;
int8_t expDiff;
uint16_t uiZ;
bool signZ;
int8_t expZ;
uint16_t sigZ;
uint16_t sigX, sigY;
int8_t shiftDist;
uint32_t sig32Z;
int8_t roundingMode;
/*your_sha256_hash--------
*your_sha256_hash--------*/
expA = expF16UI(uiA);
sigA = fracF16UI(uiA);
expB = expF16UI(uiB);
sigB = fracF16UI(uiB);
signZ = signF16UI(uiA);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) {
sigA = 0;
uiA = packToF16UI(signZ, 0, 0);
}
if (!expB) sigB = 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expDiff = expA - expB;
if (! expDiff) {
/*your_sha256_hash----
*your_sha256_hash----*/
if (! expA) {
uiZ = uiA + sigB;
if (sigA | sigB) {
softfloat_raiseFlags(status, softfloat_flag_denormal);
bool isTiny = (expF16UI(uiZ) == 0);
if (isTiny) {
if (softfloat_flushUnderflowToZero(status)) {
softfloat_raiseFlags(status, softfloat_flag_underflow | softfloat_flag_inexact);
return packToF16UI(signZ, 0, 0);
}
if (! softfloat_isMaskedException(status, softfloat_flag_underflow)) {
softfloat_raiseFlags(status, softfloat_flag_underflow);
}
}
}
return uiZ;
}
if (expA == 0x1F) {
if (sigA | sigB) goto propagateNaN;
return uiA;
}
expZ = expA;
sigZ = 0x0800 + sigA + sigB;
if (! (sigZ & 1) && (expZ < 0x1E)) {
sigZ >>= 1;
goto pack;
}
sigZ <<= 3;
} else {
/*your_sha256_hash----
*your_sha256_hash----*/
if (expDiff < 0) {
/*your_sha256_hash
*your_sha256_hash*/
if (expB == 0x1F) {
if (sigB) goto propagateNaN;
if (sigA && !expA) softfloat_raiseFlags(status, softfloat_flag_denormal);
return packToF16UI(signZ, 0x1F, 0);
}
if ((!expA && sigA) || (!expB && sigB))
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (expDiff <= -13) {
uiZ = packToF16UI(signZ, expB, sigB);
if (expA | sigA) goto addEpsilon;
return uiZ;
}
expZ = expB;
sigX = sigB | 0x0400;
sigY = sigA + (expA ? 0x0400 : sigA);
shiftDist = 19 + expDiff;
} else {
/*your_sha256_hash
*your_sha256_hash*/
uiZ = uiA;
if (expA == 0x1F) {
if (sigA) goto propagateNaN;
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
return uiZ;
}
if ((!expA && sigA) || (!expB && sigB))
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (13 <= expDiff) {
if (expB | sigB) goto addEpsilon;
return uiZ;
}
expZ = expA;
sigX = sigA | 0x0400;
sigY = sigB + (expB ? 0x0400 : sigB);
shiftDist = 19 - expDiff;
}
sig32Z = ((uint32_t) sigX<<19) + ((uint32_t) sigY<<shiftDist);
if (sig32Z < 0x40000000) {
--expZ;
sig32Z <<= 1;
}
sigZ = sig32Z>>16;
if (sig32Z & 0xFFFF) {
sigZ |= 1;
} else {
if (! (sigZ & 0xF) && (expZ < 0x1E)) {
sigZ >>= 4;
goto pack;
}
}
}
return softfloat_roundPackToF16(signZ, expZ, sigZ, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN:
return softfloat_propagateNaNF16UI(uiA, uiB, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
addEpsilon:
roundingMode = softfloat_getRoundingMode(status);
if (roundingMode != softfloat_round_near_even) {
if (roundingMode == (signF16UI(uiZ) ? softfloat_round_min : softfloat_round_max)) {
++uiZ;
if ((uint16_t) (uiZ<<1) == 0xF800) {
softfloat_raiseFlags(status, softfloat_flag_overflow | softfloat_flag_inexact);
}
}
}
softfloat_raiseFlags(status, softfloat_flag_inexact);
return uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
pack:
return packToF16UI(signZ, expZ, sigZ);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_addMagsF16.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,709 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
float16 f64_to_f16(float64 a, struct softfloat_status_t *status)
{
bool sign;
int16_t exp;
uint64_t frac;
struct commonNaN commonNaN;
uint16_t uiZ, frac16;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF64UI(a);
exp = expF64UI(a);
frac = fracF64UI(a);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (exp == 0x7FF) {
if (frac) {
softfloat_f64UIToCommonNaN(a, &commonNaN, status);
uiZ = softfloat_commonNaNToF16UI(&commonNaN);
} else {
uiZ = packToF16UI(sign, 0x1F, 0);
}
return uiZ;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (!exp && frac) {
if (softfloat_denormalsAreZeros(status))
return packToF16UI(sign, 0, 0);
softfloat_raiseFlags(status, softfloat_flag_denormal);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
frac16 = softfloat_shortShiftRightJam64(frac, 38);
if (! (exp | frac16)) {
return packToF16UI(sign, 0, 0);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
return softfloat_roundPackToF16(sign, exp - 0x3F1, frac16 | 0x4000, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f64_to_f16.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 723 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "primitiveTypes.h"
#ifndef softfloat_shiftRightJam256M
static void softfloat_shortShiftRightJamM(uint8_t size_words, const uint64_t *aPtr, uint8_t dist, uint64_t *zPtr)
{
uint8_t uNegDist;
unsigned int index, lastIndex;
uint64_t partWordZ, wordA;
uNegDist = -dist;
index = indexWordLo(size_words);
lastIndex = indexWordHi(size_words);
wordA = aPtr[index];
partWordZ = wordA>>dist;
if (partWordZ<<dist != wordA) partWordZ |= 1;
while (index != lastIndex) {
wordA = aPtr[index + wordIncr];
zPtr[index] = wordA<<(uNegDist & 63) | partWordZ;
index += wordIncr;
partWordZ = wordA>>dist;
}
zPtr[index] = partWordZ;
}
void softfloat_shiftRightJam256M(const uint64_t *aPtr, uint32_t dist, uint64_t *zPtr)
{
uint64_t wordJam;
uint32_t wordDist;
uint64_t *ptr;
uint8_t i, innerDist;
wordJam = 0;
wordDist = dist>>6;
if (wordDist) {
if (4 < wordDist) wordDist = 4;
ptr = (uint64_t *) (aPtr + indexMultiwordLo(4, wordDist));
i = wordDist;
do {
wordJam = *ptr++;
if (wordJam) break;
--i;
} while (i);
ptr = zPtr;
}
if (wordDist < 4) {
aPtr += indexMultiwordHiBut(4, wordDist);
innerDist = dist & 63;
if (innerDist) {
softfloat_shortShiftRightJamM(
4 - wordDist,
aPtr,
innerDist,
zPtr + indexMultiwordLoBut(4, wordDist)
);
if (! wordDist) goto wordJam;
} else {
aPtr += indexWordLo(4 - wordDist);
ptr = zPtr + indexWordLo(4);
for (i = 4 - wordDist; i; --i) {
*ptr = *aPtr;
aPtr += wordIncr;
ptr += wordIncr;
}
}
ptr = zPtr + indexMultiwordHi(4, wordDist);
}
do {
*ptr++ = 0;
--wordDist;
} while (wordDist);
wordJam:
if (wordJam) zPtr[indexWordLo(4)] |= 1;
}
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/s_shiftRightJam256M.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 932 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All Rights Reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "softfloat.h"
float16 ui64_to_f16(uint64_t a, struct softfloat_status_t *status)
{
int8_t shiftDist;
uint16_t sig;
shiftDist = softfloat_countLeadingZeros64(a) - 53;
if (0 <= shiftDist) {
return a ? packToF16UI(0, 0x18 - shiftDist, (uint16_t) a<<shiftDist) : 0;
} else {
shiftDist += 4;
sig = (shiftDist < 0) ? softfloat_shortShiftRightJam64(a, -shiftDist)
: (uint16_t) a<<shiftDist;
return softfloat_roundPackToF16(0, 0x1C - shiftDist, sig, status);
}
}
``` | /content/code_sandbox/src/cpu/softfloat3e/ui64_to_f16.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 517 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
extFloat80_t f16_to_extF80(float16 a, struct softfloat_status_t *status)
{
bool sign;
int8_t exp;
uint16_t frac;
struct commonNaN commonNaN;
struct uint128 uiZ;
uint16_t uiZ64;
uint64_t uiZ0;
struct exp8_sig16 normExpSig;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF16UI(a);
exp = expF16UI(a);
frac = fracF16UI(a);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (exp == 0x1F) {
if (frac) {
softfloat_f16UIToCommonNaN(a, &commonNaN, status);
uiZ = softfloat_commonNaNToExtF80UI(&commonNaN);
uiZ64 = uiZ.v64;
uiZ0 = uiZ.v0;
} else {
uiZ64 = packToExtF80UI64(sign, 0x7FFF);
uiZ0 = UINT64_C(0x8000000000000000);
}
return packToExtF80_twoargs(uiZ64, uiZ0);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! exp) {
if (! frac) {
return packToExtF80(sign, 0, 0);
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF16Sig(frac);
exp = normExpSig.exp;
frac = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiZ64 = packToExtF80UI64(sign, exp + 0x3FF0);
uiZ0 = (uint64_t) (frac | 0x0400)<<53;
return packToExtF80_twoargs(uiZ64, uiZ0);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_to_extF80.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 798 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Interpreting `uiA' and `uiB' as the bit patterns of two 16-bit floating-
| point values, at least one of which is a NaN, returns the bit pattern of
| the combined NaN result. If either `uiA' or `uiB' has the pattern of a
| signaling NaN, the invalid exception is raised.
*your_sha256_hash------------*/
uint16_t softfloat_propagateNaNF16UI(uint16_t uiA, uint16_t uiB, struct softfloat_status_t *status)
{
bool isSigNaNA;
isSigNaNA = softfloat_isSigNaNF16UI(uiA);
if (isSigNaNA || softfloat_isSigNaNF16UI(uiB)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
if (isSigNaNA) return uiA | 0x0200;
}
return (isNaNF16UI(uiA) ? uiA : uiB) | 0x0200;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_propagateNaNF16UI.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 573 |
```objective-c
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#ifndef _SOFTFLOAT_EXTRA_H_
#define _SOFTFLOAT_EXTRA_H_
#include "config.h"
#include "internals.h"
// ======= float16 ======= //
static __inline bool f16_sign(float16 a)
{
return signF16UI(a);
}
static __inline int8_t f16_exp(float16 a)
{
return expF16UI(a);
}
static __inline uint16_t f16_fraction(float16 a)
{
return fracF16UI(a);
}
static __inline float16 f16_denormal_to_zero(float16 a)
{
if (! expF16UI(a) && fracF16UI(a))
return a & 0x8000;
return a;
}
// ======= float32 ======= //
static __inline bool f32_sign(float32 a)
{
return signF32UI(a);
}
static __inline int16_t f32_exp(float32 a)
{
return expF32UI(a);
}
static __inline uint32_t f32_fraction(float32 a)
{
return fracF32UI(a);
}
static __inline float32 f32_denormal_to_zero(float32 a)
{
if (! expF32UI(a) && fracF32UI(a))
return a & 0x80000000;
return a;
}
// ======= float64 ======= //
static __inline bool f64_sign(float64 a)
{
return signF64UI(a);
}
static __inline int16_t f64_exp(float64 a)
{
return expF64UI(a);
}
static __inline uint64_t f64_fraction(float64 a)
{
return fracF64UI(a);
}
static __inline float64 f64_denormal_to_zero(float64 a)
{
if (! expF64UI(a) && fracF64UI(a))
return a & ((uint64_t)(1) << 63);
return a;
}
// ======= floatx80 ======= //
#ifdef __cplusplus
extern "C" {
#endif
static __inline bool extF80_isUnsupported(extFloat80_t a)
{
return ((a.signExp & 0x7FFF) && !(a.signif & BX_CONST64(0x8000000000000000)));
}
static __inline bool extF80_sign(extFloat80_t a)
{
return signExtF80UI64(a.signExp);
}
static __inline int16_t extF80_exp(extFloat80_t a)
{
return expExtF80UI64(a.signExp);
}
static __inline uint64_t extF80_fraction(extFloat80_t a)
{
return a.signif;
}
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/softfloat-extra.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 880 |
```objective-c
/*============================================================================
This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
Arithmetic Package, Release 2b.
Written by John R. Hauser. This work was made possible in part by the
International Computer Science Institute, located at Suite 600, 1947 Center
Street, Berkeley, California 94704. Funding was partially provided by the
National Science Foundation under grant MIP-9311980. The original version
of this code was written as part of a project to build a fixed-point vector
processor in collaboration with the University of California at Berkeley,
overseen by Profs. Nelson Morgan and John Wawrzynek. More information
is available through the Web page `path_to_url~jhauser/
arithmetic/SoftFloat.html'.
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
Derivative works are acceptable, even for commercial purposes, so long as
(1) the source code for the derivative work includes prominent notice that
the work is derivative, and (2) the source code includes prominent notice with
these four paragraphs for those parts of this code that are retained.
=============================================================================*/
#ifndef _SOFTFLOAT_SPECIALIZE_H_
#define _SOFTFLOAT_SPECIALIZE_H_
#include "config.h"
#include "softfloat.h"
#include "softfloat_types.h"
/*============================================================================
* Adapted for Bochs (x86 achitecture simulator) by
* Stanislav Shwartsman [sshwarts at sourceforge net]
* ==========================================================================*/
extern const int16_t int16_indefinite;
extern const int32_t int32_indefinite;
extern const int64_t int64_indefinite;
extern const uint16_t uint16_indefinite;
extern const uint32_t uint32_indefinite;
extern const uint64_t uint64_indefinite;
/*your_sha256_hash------------
| Commonly used half-precision floating point constants
*your_sha256_hash------------*/
extern const float16 float16_negative_inf;
extern const float16 float16_positive_inf;
extern const float16 float16_negative_zero;
extern const float16 float16_positive_zero;
/*your_sha256_hash------------
| The pattern for a default generated half-precision NaN.
*your_sha256_hash------------*/
extern const float16 float16_default_nan;
#define FLOAT16_EXP_BIAS 0xF
/*your_sha256_hash------------
| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
| single-precision floating-point value, returning the result. After being
| shifted into the proper positions, the three fields are simply added
| together to form the result. This means that any integer portion of `zSig'
| will be added into the exponent. Since a properly normalized significand
| will have an integer portion equal to 1, the `zExp' input should be 1 less
| than the desired result exponent whenever `zSig' is a complete, normalized
| significand.
*your_sha256_hash------------*/
static __inline float16 packFloat16(int zSign, int zExp, uint16_t zSig)
{
return (((uint16_t) zSign)<<15) + (((uint16_t) zExp)<<10) + zSig;
}
/*your_sha256_hash------------
| Commonly used single-precision floating point constants
*your_sha256_hash------------*/
extern const float32 float32_negative_inf;
extern const float32 float32_positive_inf;
extern const float32 float32_negative_zero;
extern const float32 float32_positive_zero;
extern const float32 float32_negative_one;
extern const float32 float32_positive_one;
extern const float32 float32_max_float;
extern const float32 float32_min_float;
/*your_sha256_hash------------
| The pattern for a default generated single-precision NaN.
*your_sha256_hash------------*/
extern const float32 float32_default_nan;
#define FLOAT32_EXP_BIAS 0x7F
/*your_sha256_hash------------
| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
| single-precision floating-point value, returning the result. After being
| shifted into the proper positions, the three fields are simply added
| together to form the result. This means that any integer portion of `zSig'
| will be added into the exponent. Since a properly normalized significand
| will have an integer portion equal to 1, the `zExp' input should be 1 less
| than the desired result exponent whenever `zSig' is a complete, normalized
| significand.
*your_sha256_hash------------*/
static __inline float32 packFloat32(int zSign, int16_t zExp, uint32_t zSig)
{
return (((uint32_t) zSign)<<31) + (((uint32_t) zExp)<<23) + zSig;
}
/*your_sha256_hash------------
| Commonly used single-precision floating point constants
*your_sha256_hash------------*/
extern const float64 float64_negative_inf;
extern const float64 float64_positive_inf;
extern const float64 float64_negative_zero;
extern const float64 float64_positive_zero;
extern const float64 float64_negative_one;
extern const float64 float64_positive_one;
extern const float64 float64_max_float;
extern const float64 float64_min_float;
/*your_sha256_hash------------
| The pattern for a default generated double-precision NaN.
*your_sha256_hash------------*/
extern const float64 float64_default_nan;
#define FLOAT64_EXP_BIAS 0x3FF
/*your_sha256_hash------------
| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a
| double-precision floating-point value, returning the result. After being
| shifted into the proper positions, the three fields are simply added
| together to form the result. This means that any integer portion of `zSig'
| will be added into the exponent. Since a properly normalized significand
| will have an integer portion equal to 1, the `zExp' input should be 1 less
| than the desired result exponent whenever `zSig' is a complete, normalized
| significand.
*your_sha256_hash------------*/
static __inline float64 packFloat64(int zSign, int16_t zExp, uint64_t zSig)
{
return (((uint64_t) zSign)<<63) + (((uint64_t) zExp)<<52) + zSig;
}
/*your_sha256_hash-------------
| Commonly used extended double-precision floating-point constants.
*your_sha256_hash------------*/
extern const floatx80 Const_Z;
extern const floatx80 Const_1;
extern const floatx80 Const_L2T;
extern const floatx80 Const_L2E;
extern const floatx80 Const_PI;
extern const floatx80 Const_LG2;
extern const floatx80 Const_LN2;
extern const floatx80 Const_INF;
/*your_sha256_hash------------
| The pattern for a default generated extended double-precision NaN. The
| `high' and `low' values hold the most- and least-significant bits,
| respectively.
*your_sha256_hash------------*/
#define floatx80_default_nan_exp 0xFFFF
#define floatx80_default_nan_fraction BX_CONST64(0xC000000000000000)
#define FLOATX80_EXP_BIAS 0x3FFF
/*your_sha256_hash------------
| Packs the sign `zSign', exponent `zExp', and significand `zSig' into an
| extended double-precision floating-point value, returning the result.
*your_sha256_hash------------*/
static __inline floatx80 packFloatx80(int zSign, int32_t zExp, uint64_t zSig)
{
floatx80 z;
z.signif = zSig;
z.signExp = (zSign << 15) + zExp;
return z;
}
#ifdef FLOAT128
/*your_sha256_hash------------
| Packs the sign `zSign', the exponent `zExp', and the significand formed
| by the concatenation of `zSig0' and `zSig1' into a quadruple-precision
| floating-point value, returning the result. After being shifted into the
| proper positions, the three fields `zSign', `zExp', and `zSig0' are simply
| added together to form the most significant 32 bits of the result. This
| means that any integer portion of `zSig0' will be added into the exponent.
| Since a properly normalized significand will have an integer portion equal
| to 1, the `zExp' input should be 1 less than the desired result exponent
| whenever `zSig0' and `zSig1' concatenated form a complete, normalized
| significand.
*your_sha256_hash------------*/
static __inline float128_t packFloat128(int zSign, int32_t zExp, uint64_t zSig0, uint64_t zSig1)
{
float128_t z;
z.v0 = zSig1;
z.v64 = (((uint64_t) zSign)<<63) + (((uint64_t) zExp)<<48) + zSig0;
return z;
}
/*your_sha256_hash------------
| Packs two 64-bit precision integers into into the quadruple-precision
| floating-point value, returning the result.
*your_sha256_hash------------*/
static __inline float128_t packFloat128(uint64_t zHi, uint64_t zLo)
{
float128_t z;
z.v0 = zLo;
z.v64 = zHi;
return z;
}
#define PACK_FLOAT_128(hi,lo) packFloat128(BX_CONST64(hi),BX_CONST64(lo))
#endif
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/softfloat-specialize.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,210 |
```c
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include "primitives.h"
/*your_sha256_hash------------
| This function is the same as 'softfloat_shiftRightJam128Extra' (below),
| except that 'dist' must be in the range 1 to 63.
*your_sha256_hash------------*/
struct uint128_extra softfloat_shortShiftRightJam128Extra(uint64_t a64, uint64_t a0, uint64_t extra, uint8_t dist)
{
uint8_t negDist = -dist;
struct uint128_extra z;
z.v.v64 = a64>>dist;
z.v.v0 = a64<<(negDist & 63) | a0>>dist;
z.extra = a0<<(negDist & 63) | (extra != 0);
return z;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/primitives.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 493 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
int64_t f32_to_i64(float32 a, uint8_t roundingMode, bool exact, struct softfloat_status_t *status)
{
bool sign;
int16_t exp;
uint32_t sig;
int16_t shiftDist;
uint64_t sig64, extra;
struct uint64_extra sig64Extra;
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF32UI(a);
exp = expF32UI(a);
sig = fracF32UI(a);
if (softfloat_denormalsAreZeros(status))
if (!exp && sig) sig = 0;
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = 0xBE - exp;
if (shiftDist < 0) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
return (exp == 0xFF) && sig
? i64_fromNaN
: sign ? i64_fromNegOverflow : i64_fromPosOverflow;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (exp) sig |= 0x00800000;
sig64 = (uint64_t) sig<<40;
extra = 0;
if (shiftDist) {
sig64Extra = softfloat_shiftRightJam64Extra(sig64, 0, shiftDist);
sig64 = sig64Extra.v;
extra = sig64Extra.extra;
}
return softfloat_roundToI64(sign, sig64, extra, roundingMode, exact, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f32_to_i64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 705 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
float128_t
f128_roundToInt(float128_t a, uint8_t roundingMode, bool exact, struct softfloat_status_t *status)
{
uint64_t uiA64, uiA0;
int32_t exp;
struct uint128 uiZ;
uint64_t lastBitMask0, roundBitsMask;
bool roundNearEven;
uint64_t lastBitMask64;
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiA64 = a.v64;
uiA0 = a.v0;
exp = expF128UI64(uiA64);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (0x402F <= exp) {
/*your_sha256_hash----
*your_sha256_hash----*/
if (0x406F <= exp) {
if ((exp == 0x7FFF) && (fracF128UI64(uiA64) | uiA0)) {
uiZ = softfloat_propagateNaNF128UI(uiA64, uiA0, 0, 0, status);
return uiZ;
}
return a;
}
/*your_sha256_hash----
*your_sha256_hash----*/
lastBitMask0 = (uint64_t) 2<<(0x406E - exp);
roundBitsMask = lastBitMask0 - 1;
uiZ.v64 = uiA64;
uiZ.v0 = uiA0;
roundNearEven = (roundingMode == softfloat_round_near_even);
if (roundNearEven || (roundingMode == softfloat_round_near_maxMag)) {
if (exp == 0x402F) {
if (UINT64_C(0x8000000000000000) <= uiZ.v0) {
++uiZ.v64;
if (roundNearEven && (uiZ.v0 == UINT64_C(0x8000000000000000))) {
uiZ.v64 &= ~1;
}
}
} else {
uiZ = softfloat_add128(uiZ.v64, uiZ.v0, 0, lastBitMask0>>1);
if (roundNearEven && !(uiZ.v0 & roundBitsMask)) {
uiZ.v0 &= ~lastBitMask0;
}
}
} else if (roundingMode == (signF128UI64(uiZ.v64) ? softfloat_round_min : softfloat_round_max)) {
uiZ = softfloat_add128(uiZ.v64, uiZ.v0, 0, roundBitsMask);
}
uiZ.v0 &= ~roundBitsMask;
lastBitMask64 = !lastBitMask0;
} else {
/*your_sha256_hash----
*your_sha256_hash----*/
if (exp < 0x3FFF) {
if (!((uiA64 & UINT64_C(0x7FFFFFFFFFFFFFFF)) | uiA0)) return a;
if (exact) softfloat_raiseFlags(status, softfloat_flag_inexact);
uiZ.v64 = uiA64 & packToF128UI64(1, 0, 0);
uiZ.v0 = 0;
switch (roundingMode) {
case softfloat_round_near_even:
if (!(fracF128UI64(uiA64) | uiA0)) break;
case softfloat_round_near_maxMag:
if (exp == 0x3FFE) uiZ.v64 |= packToF128UI64(0, 0x3FFF, 0);
break;
case softfloat_round_min:
if (uiZ.v64) uiZ.v64 = packToF128UI64(1, 0x3FFF, 0);
break;
case softfloat_round_max:
if (!uiZ.v64) uiZ.v64 = packToF128UI64(0, 0x3FFF, 0);
break;
}
return uiZ;
}
/*your_sha256_hash----
*your_sha256_hash----*/
uiZ.v64 = uiA64;
uiZ.v0 = 0;
lastBitMask64 = (uint64_t) 1<<(0x402F - exp);
roundBitsMask = lastBitMask64 - 1;
if (roundingMode == softfloat_round_near_maxMag) {
uiZ.v64 += lastBitMask64>>1;
} else if (roundingMode == softfloat_round_near_even) {
uiZ.v64 += lastBitMask64>>1;
if (!((uiZ.v64 & roundBitsMask) | uiA0)) {
uiZ.v64 &= ~lastBitMask64;
}
} else if (roundingMode == (signF128UI64(uiZ.v64) ? softfloat_round_min : softfloat_round_max)) {
uiZ.v64 = (uiZ.v64 | (uiA0 != 0)) + roundBitsMask;
}
uiZ.v64 &= ~roundBitsMask;
lastBitMask0 = 0;
}
if ((uiZ.v64 != uiA64) || (uiZ.v0 != uiA0)) {
if (exact) softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return uiZ;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f128_roundToInt.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,513 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
/*your_sha256_hash------------
| Extracts the fractional portion of double-precision floating-point value `a',
| and returns the result as a double-precision floating-point value. The
| fractional results are precise. The operation is performed according to the
| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
*your_sha256_hash------------*/
float64 f64_frc(float64 a, struct softfloat_status_t *status)
{
int roundingMode = softfloat_getRoundingMode(status);
bool signA;
int16_t expA;
uint64_t sigA;
uint64_t lastBitMask;
uint64_t roundBitsMask;
signA = signF64UI(a);
expA = expF64UI(a);
sigA = fracF64UI(a);
if (expA == 0x7FF) {
if (sigA) return softfloat_propagateNaNF64UI(a, 0, status);
softfloat_raiseFlags(status, softfloat_flag_invalid);
return defaultNaNF64UI;
}
if (expA >= 0x433) {
return packToF64UI(roundingMode == softfloat_round_down, 0, 0);
}
if (expA < 0x3FF) {
if (! expA) {
if (! sigA || softfloat_denormalsAreZeros(status))
return packToF64UI(roundingMode == softfloat_round_down, 0, 0);
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (! softfloat_isMaskedException(status, softfloat_flag_underflow))
softfloat_raiseFlags(status, softfloat_flag_underflow);
if (softfloat_flushUnderflowToZero(status)) {
softfloat_raiseFlags(status, softfloat_flag_underflow | softfloat_flag_inexact);
return packToF64UI(signA, 0, 0);
}
}
return a;
}
lastBitMask = UINT64_C(1) << (0x433 - expA);
roundBitsMask = lastBitMask - 1;
sigA &= roundBitsMask;
sigA <<= 10;
expA--;
if (! sigA)
return packToF64UI(roundingMode == softfloat_round_down, 0, 0);
return softfloat_normRoundPackToF64(signA, expA, sigA, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f64_frc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 876 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
float16 softfloat_subMagsF16(uint16_t uiA, uint16_t uiB, struct softfloat_status_t *status)
{
int8_t expA;
uint16_t sigA;
int8_t expB;
uint16_t sigB;
int8_t expDiff;
uint16_t uiZ;
int16_t sigDiff;
bool signZ;
int8_t shiftDist, expZ;
uint16_t sigZ, sigX, sigY;
uint32_t sig32Z;
int8_t roundingMode;
/*your_sha256_hash--------
*your_sha256_hash--------*/
expA = expF16UI(uiA);
sigA = fracF16UI(uiA);
expB = expF16UI(uiB);
sigB = fracF16UI(uiB);
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) sigA = 0;
if (!expB) sigB = 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expDiff = expA - expB;
if (! expDiff) {
/*your_sha256_hash----
*your_sha256_hash----*/
if (expA == 0x1F) {
if (sigA | sigB) goto propagateNaN;
softfloat_raiseFlags(status, softfloat_flag_invalid);
return defaultNaNF16UI;
}
if (!expA && (sigA | sigB)) softfloat_raiseFlags(status, softfloat_flag_denormal);
sigDiff = sigA - sigB;
if (! sigDiff) {
return packToF16UI((softfloat_getRoundingMode(status) == softfloat_round_min), 0, 0);
}
if (expA) --expA;
signZ = signF16UI(uiA);
if (sigDiff < 0) {
signZ = ! signZ;
sigDiff = -sigDiff;
}
shiftDist = softfloat_countLeadingZeros16(sigDiff) - 5;
expZ = expA - shiftDist;
if (expZ < 0) {
shiftDist = expA;
expZ = 0;
}
sigZ = sigDiff<<shiftDist;
if (!expZ && sigDiff) {
if (softfloat_flushUnderflowToZero(status)) {
softfloat_raiseFlags(status, softfloat_flag_underflow | softfloat_flag_inexact);
return packToF16UI(signZ, 0, 0);
}
if (! softfloat_isMaskedException(status, softfloat_flag_underflow)) {
softfloat_raiseFlags(status, softfloat_flag_underflow);
}
}
goto pack;
} else {
/*your_sha256_hash----
*your_sha256_hash----*/
signZ = signF16UI(uiA);
if (expDiff < 0) {
/*your_sha256_hash
*your_sha256_hash*/
signZ = ! signZ;
if (expB == 0x1F) {
if (sigB) goto propagateNaN;
if (sigA && !expA) softfloat_raiseFlags(status, softfloat_flag_denormal);
return packToF16UI(signZ, 0x1F, 0);
}
if ((sigA && !expA) || (sigB && !expB))
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (expDiff <= -13) {
uiZ = packToF16UI(signZ, expB, sigB);
if (expA | sigA) goto subEpsilon;
return uiZ;
}
expZ = expA + 19;
sigX = sigB | 0x0400;
sigY = sigA + (expA ? 0x0400 : sigA);
expDiff = -expDiff;
} else {
/*your_sha256_hash
*your_sha256_hash*/
uiZ = uiA;
if (expA == 0x1F) {
if (sigA) goto propagateNaN;
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
return uiZ;
}
if ((sigA && !expA) || (sigB && !expB))
softfloat_raiseFlags(status, softfloat_flag_denormal);
if (13 <= expDiff) {
if (expB | sigB) goto subEpsilon;
return uiZ;
}
expZ = expB + 19;
sigX = sigA | 0x0400;
sigY = sigB + (expB ? 0x0400 : sigB);
}
sig32Z = ((uint32_t) sigX<<expDiff) - sigY;
shiftDist = softfloat_countLeadingZeros32(sig32Z) - 1;
sig32Z <<= shiftDist;
expZ -= shiftDist;
sigZ = sig32Z>>16;
if (sig32Z & 0xFFFF) {
sigZ |= 1;
} else {
if (! (sigZ & 0xF) && ((unsigned int) expZ < 0x1E)) {
sigZ >>= 4;
goto pack;
}
}
return softfloat_roundPackToF16(signZ, expZ, sigZ, status);
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN:
return softfloat_propagateNaNF16UI(uiA, uiB, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
subEpsilon:
roundingMode = softfloat_getRoundingMode(status);
if (roundingMode != softfloat_round_near_even) {
if ((roundingMode == softfloat_round_minMag)
|| (roundingMode == (signF16UI(uiZ) ? softfloat_round_max : softfloat_round_min))) {
--uiZ;
}
}
softfloat_raiseFlags(status, softfloat_flag_inexact);
return uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
pack:
return packToF16UI(signZ, expZ, sigZ);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_subMagsF16.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,742 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
uint32_t f16_to_ui32_r_minMag(float16 a, bool exact, struct softfloat_status_t *status)
{
int8_t exp;
uint16_t frac;
int8_t shiftDist;
bool sign;
uint32_t alignedSig;
/*your_sha256_hash--------
*your_sha256_hash--------*/
exp = expF16UI(a);
frac = fracF16UI(a);
if (softfloat_denormalsAreZeros(status))
if (!exp && frac) frac = 0;
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = exp - 0x0F;
if (shiftDist < 0) {
if (exact && (exp | frac)) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF16UI(a);
if (sign || (exp == 0x1F)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
return (exp == 0x1F) && frac
? ui32_fromNaN
: sign ? ui32_fromNegOverflow : ui32_fromPosOverflow;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
alignedSig = (uint32_t) (frac | 0x0400)<<shiftDist;
if (exact && (alignedSig & 0x3FF)) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return alignedSig>>10;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_to_ui32_r_minMag.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 706 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
struct exp32_sig64 softfloat_normSubnormalExtF80Sig(uint64_t sig)
{
int8_t shiftDist;
struct exp32_sig64 z;
shiftDist = softfloat_countLeadingZeros64(sig);
z.exp = -shiftDist;
z.sig = sig<<shiftDist;
return z;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/s_normSubnormalExtF80Sig.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 415 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
uint64_t extF80_to_ui64(extFloat80_t a, uint8_t roundingMode, bool exact, struct softfloat_status_t *status)
{
uint16_t uiA64;
bool sign;
int32_t exp;
uint64_t sig;
int32_t shiftDist;
uint64_t sigExtra;
struct uint64_extra sig64Extra;
// handle unsupported extended double-precision floating encodings
if (extF80_isUnsupported(a)) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
return ui64_fromNaN;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiA64 = a.signExp;
sign = signExtF80UI64(uiA64);
exp = expExtF80UI64(uiA64);
sig = a.signif;
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = 0x403E - exp;
if (shiftDist < 0) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
return
(exp == 0x7FFF) && (sig & UINT64_C(0x7FFFFFFFFFFFFFFF))
? ui64_fromNaN
: sign ? ui64_fromNegOverflow : ui64_fromPosOverflow;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
sigExtra = 0;
if (shiftDist) {
sig64Extra = softfloat_shiftRightJam64Extra(sig, 0, shiftDist);
sig = sig64Extra.v;
sigExtra = sig64Extra.extra;
}
return softfloat_roundToUI64(sign, sig, sigExtra, roundingMode, exact, status);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/extF80_to_ui64.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 733 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "softfloat.h"
softfloat_class_t f16_class(float16 a)
{
bool signA;
int8_t expA;
uint16_t sigA;
signA = signF16UI(a);
expA = expF16UI(a);
sigA = fracF16UI(a);
if (expA == 0x1F) {
if (sigA == 0)
return (signA) ? softfloat_negative_inf : softfloat_positive_inf;
return (sigA & 0x200) ? softfloat_QNaN : softfloat_SNaN;
}
if (expA == 0) {
if (sigA == 0) return softfloat_zero;
return softfloat_denormal;
}
return softfloat_normalized;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_class.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 515 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
float16 f16_mul(float16 a, float16 b, struct softfloat_status_t *status)
{
bool signA;
int8_t expA;
uint16_t sigA;
bool signB;
int8_t expB;
uint16_t sigB;
bool signZ;
uint16_t magBits;
struct exp8_sig16 normExpSig;
int8_t expZ;
uint32_t sig32Z;
uint16_t sigZ, uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
signA = signF16UI(a);
expA = expF16UI(a);
sigA = fracF16UI(a);
signB = signF16UI(b);
expB = expF16UI(b);
sigB = fracF16UI(b);
signZ = signA ^ signB;
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) sigA = 0;
if (!expB) sigB = 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (expA == 0x1F) {
if (sigA || ((expB == 0x1F) && sigB)) goto propagateNaN;
magBits = expB | sigB;
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto infArg;
}
if (expB == 0x1F) {
if (sigB) goto propagateNaN;
magBits = expA | sigA;
if (sigA && !expA) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto infArg;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! expA) {
if (! sigA) {
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto zero;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF16Sig(sigA);
expA = normExpSig.exp;
sigA = normExpSig.sig;
}
if (! expB) {
if (! sigB) {
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto zero;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF16Sig(sigB);
expB = normExpSig.exp;
sigB = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expZ = expA + expB - 0xF;
sigA = (sigA | 0x0400)<<4;
sigB = (sigB | 0x0400)<<5;
sig32Z = (uint32_t) sigA * sigB;
sigZ = sig32Z>>16;
if (sig32Z & 0xFFFF) sigZ |= 1;
if (sigZ < 0x4000) {
--expZ;
sigZ <<= 1;
}
return softfloat_roundPackToF16(signZ, expZ, sigZ, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN:
return softfloat_propagateNaNF16UI(a, b, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
infArg:
if (! magBits) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
uiZ = defaultNaNF16UI;
} else {
uiZ = packToF16UI(signZ, 0x1F, 0);
}
return uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
zero:
return packToF16UI(signZ, 0, 0);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f16_mul.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,251 |
```c
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "primitives.h"
#include "specialize.h"
#include "softfloat.h"
float64 f64_mul(float64 a, float64 b, struct softfloat_status_t *status)
{
bool signA;
int16_t expA;
uint64_t sigA;
bool signB;
int16_t expB;
uint64_t sigB;
bool signZ;
uint64_t magBits;
struct exp16_sig64 normExpSig;
int16_t expZ;
struct uint128 sig128Z;
uint64_t sigZ, uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
signA = signF64UI(a);
expA = expF64UI(a);
sigA = fracF64UI(a);
signB = signF64UI(b);
expB = expF64UI(b);
sigB = fracF64UI(b);
signZ = signA ^ signB;
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (softfloat_denormalsAreZeros(status)) {
if (!expA) sigA = 0;
if (!expB) sigB = 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (expA == 0x7FF) {
if (sigA || ((expB == 0x7FF) && sigB)) goto propagateNaN;
magBits = expB | sigB;
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto infArg;
}
if (expB == 0x7FF) {
if (sigB) goto propagateNaN;
magBits = expA | sigA;
if (sigA && !expA) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto infArg;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
if (! expA) {
if (! sigA) {
if (sigB && !expB) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto zero;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF64Sig(sigA);
expA = normExpSig.exp;
sigA = normExpSig.sig;
}
if (! expB) {
if (! sigB) {
if (sigA && !expA) softfloat_raiseFlags(status, softfloat_flag_denormal);
goto zero;
}
softfloat_raiseFlags(status, softfloat_flag_denormal);
normExpSig = softfloat_normSubnormalF64Sig(sigB);
expB = normExpSig.exp;
sigB = normExpSig.sig;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
expZ = expA + expB - 0x3FF;
sigA = (sigA | UINT64_C(0x0010000000000000))<<10;
sigB = (sigB | UINT64_C(0x0010000000000000))<<11;
sig128Z = softfloat_mul64To128(sigA, sigB);
sigZ = sig128Z.v64 | (sig128Z.v0 != 0);
if (sigZ < UINT64_C(0x4000000000000000)) {
--expZ;
sigZ <<= 1;
}
return softfloat_roundPackToF64(signZ, expZ, sigZ, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
propagateNaN:
return softfloat_propagateNaNF64UI(a, b, status);
/*your_sha256_hash--------
*your_sha256_hash--------*/
infArg:
if (! magBits) {
softfloat_raiseFlags(status, softfloat_flag_invalid);
uiZ = defaultNaNF64UI;
} else {
uiZ = packToF64UI(signZ, 0x7FF, 0);
}
return uiZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
zero:
return packToF64UI(signZ, 0, 0);
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f64_mul.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,273 |
```c++
/*============================================================================
This C source file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
#include <stdbool.h>
#include <stdint.h>
#include "internals.h"
#include "specialize.h"
#include "softfloat.h"
int32_t f128_to_i32_r_minMag(float128_t a, bool exact, struct softfloat_status_t *status)
{
uint64_t uiA64, uiA0;
int32_t exp;
uint64_t sig64;
int32_t shiftDist;
bool sign;
int32_t absZ;
/*your_sha256_hash--------
*your_sha256_hash--------*/
uiA64 = a.v64;
uiA0 = a.v0;
exp = expF128UI64(uiA64);
sig64 = fracF128UI64(uiA64) | (uiA0 != 0);
/*your_sha256_hash--------
*your_sha256_hash--------*/
shiftDist = 0x402F - exp;
if (49 <= shiftDist) {
if (exact && (exp | sig64)) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return 0;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
sign = signF128UI64(uiA64);
if (shiftDist < 18) {
if (sign && (shiftDist == 17) && (sig64 < UINT64_C(0x0000000000020000))) {
if (exact && sig64) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return -0x7FFFFFFF - 1;
}
softfloat_raiseFlags(status, softfloat_flag_invalid);
return
(exp == 0x7FFF) && sig64 ? i32_fromNaN
: sign ? i32_fromNegOverflow : i32_fromPosOverflow;
}
/*your_sha256_hash--------
*your_sha256_hash--------*/
sig64 |= UINT64_C(0x0001000000000000);
absZ = sig64>>shiftDist;
if (exact && ((uint64_t) (uint32_t) absZ<<shiftDist != sig64)) {
softfloat_raiseFlags(status, softfloat_flag_inexact);
}
return sign ? -absZ : absZ;
}
``` | /content/code_sandbox/src/cpu/softfloat3e/f128_to_i32_r_minMag.cc | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 817 |
```objective-c
/*============================================================================
This C header file is part of the SoftFloat IEEE Floating-Point Arithmetic
Package, Release 3e, by John R. Hauser.
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*============================================================================
| Note: If SoftFloat is made available as a general library for programs to
| use, it is strongly recommended that a platform-specific version of this
| header, "softfloat.h", be created that folds in "softfloat_types.h" and that
| eliminates all dependencies on compile-time macros.
*============================================================================*/
#ifndef _SOFTFLOAT_H_
#define _SOFTFLOAT_H_
#include <stdint.h>
#include "softfloat_types.h"
#include "softfloat-extra.h"
struct softfloat_status_t
{
uint8_t softfloat_roundingMode;
int softfloat_exceptionFlags;
int softfloat_exceptionMasks;
int softfloat_suppressException;
bool softfloat_denormals_are_zeros;
bool softfloat_flush_underflow_to_zero;
/*your_sha256_hash------------
| Rounding precision for 80-bit extended double-precision floating-point.
| Valid values are 32, 64, and 80.
*your_sha256_hash------------*/
uint8_t extF80_roundingPrecision;
};
/*your_sha256_hash------------
| Software floating-point rounding mode.
*your_sha256_hash------------*/
enum {
softfloat_round_near_even = 0,
softfloat_round_min = 1,
softfloat_round_down = softfloat_round_min,
softfloat_round_max = 2,
softfloat_round_up = softfloat_round_max,
softfloat_round_minMag = 3,
softfloat_round_to_zero = softfloat_round_minMag,
softfloat_round_near_maxMag = 4
};
/*your_sha256_hash------------
| Software floating-point exception flags.
*your_sha256_hash------------*/
enum softfloat_exception_flag_t {
softfloat_flag_invalid = 0x01,
softfloat_flag_denormal = 0x02,
softfloat_flag_divbyzero = 0x04,
softfloat_flag_infinite = softfloat_flag_divbyzero,
softfloat_flag_overflow = 0x08,
softfloat_flag_underflow = 0x10,
softfloat_flag_inexact = 0x20
};
static const unsigned softfloat_all_exceptions_mask = 0x3f;
#define FLOATX80
#ifdef FLOATX80
#define RAISE_SW_C1 0x0200
#endif
/*your_sha256_hash------------
| Software IEC/IEEE floating-point ordering relations
*your_sha256_hash------------*/
enum {
softfloat_relation_less = -1,
softfloat_relation_equal = 0,
softfloat_relation_greater = 1,
softfloat_relation_unordered = 2
};
/*your_sha256_hash------------
| Software IEC/IEEE floating-point class.
*your_sha256_hash------------*/
typedef enum {
softfloat_zero,
softfloat_SNaN,
softfloat_QNaN,
softfloat_negative_inf,
softfloat_positive_inf,
softfloat_denormal,
softfloat_normalized
} softfloat_class_t;
/*your_sha256_hash------------
| Options to indicate which negations to perform in f*_muladd()
| Using these differs from negating an input or output before calling
| the muladd function in that this means that a NaN doesn't have its
| sign bit inverted before it is propagated.
*your_sha256_hash------------*/
enum {
softfloat_mulAdd_subC = 1,
softfloat_muladd_negate_c = softfloat_mulAdd_subC,
softfloat_mulAdd_subProd = 2,
softfloat_muladd_negate_product = softfloat_mulAdd_subProd,
softfloat_muladd_negate_result = softfloat_muladd_negate_c | softfloat_muladd_negate_product
};
static __inline void softfloat_setFlags(struct softfloat_status_t *status, int flags) {
status->softfloat_exceptionFlags = flags;
}
/*your_sha256_hash------------
| Routine to raise any or all of the software floating-point exception flags.
*your_sha256_hash------------*/
static __inline void softfloat_raiseFlags(struct softfloat_status_t *status, int flags) {
status->softfloat_exceptionFlags |= flags;
}
/*your_sha256_hash------------
| Check if exception is masked.
*your_sha256_hash------------*/
static __inline int softfloat_isMaskedException(const struct softfloat_status_t *status, int flags) {
return status->softfloat_exceptionMasks & flags;
}
/*your_sha256_hash------------
| Suppress generation of these exceptions.
*your_sha256_hash------------*/
static __inline void softfloat_suppressException(struct softfloat_status_t *status, int flags) {
status->softfloat_suppressException |= flags;
}
/*your_sha256_hash------------
| Obtain current rounding mode.
*your_sha256_hash------------*/
static __inline uint8_t softfloat_getRoundingMode(const struct softfloat_status_t *status) {
return status->softfloat_roundingMode;
}
/*your_sha256_hash------------
| Read denormals-are-zeroes flag.
*your_sha256_hash------------*/
static __inline bool softfloat_denormalsAreZeros(const struct softfloat_status_t *status) {
return status->softfloat_denormals_are_zeros;
}
/*your_sha256_hash------------
| Read flush-underflow-to-zero flag.
*your_sha256_hash------------*/
static __inline bool softfloat_flushUnderflowToZero(const struct softfloat_status_t *status) {
return status->softfloat_flush_underflow_to_zero;
}
/*your_sha256_hash------------
| Obtain current rounding precision for F80.
*your_sha256_hash------------*/
static __inline uint8_t softfloat_extF80_roundingPrecision(const struct softfloat_status_t *status) {
return status->extF80_roundingPrecision;
}
/*your_sha256_hash------------
| Returns raised IEC/IEEE floating-point exception flags.
*your_sha256_hash------------*/
static __inline int softfloat_getExceptionFlags(const struct softfloat_status_t *status) {
return status->softfloat_exceptionFlags & ~status->softfloat_suppressException;
}
/*your_sha256_hash------------
| Raise floating point precision lost up flag (floatx80 only).
*your_sha256_hash------------*/
#ifdef FLOATX80
static __inline void softfloat_setRoundingUp(struct softfloat_status_t *status) {
status->softfloat_exceptionFlags |= RAISE_SW_C1;
}
#endif
/*your_sha256_hash------------
| Integer-to-floating-point conversion routines.
*your_sha256_hash------------*/
float16 ui32_to_f16(uint32_t, struct softfloat_status_t *);
float32 ui32_to_f32(uint32_t, struct softfloat_status_t *);
float64 ui32_to_f64(uint32_t);
float16 ui64_to_f16(uint64_t, struct softfloat_status_t *);
float32 ui64_to_f32(uint64_t, struct softfloat_status_t *);
float64 ui64_to_f64(uint64_t, struct softfloat_status_t *);
float16 i32_to_f16(int32_t, struct softfloat_status_t *);
float32 i32_to_f32(int32_t, struct softfloat_status_t *);
float64 i32_to_f64(int32_t);
float16 i64_to_f16(int64_t, struct softfloat_status_t *);
float32 i64_to_f32(int64_t, struct softfloat_status_t *);
float64 i64_to_f64(int64_t, struct softfloat_status_t *);
static __inline float16 i16_to_f16(int16_t a, struct softfloat_status_t *status) {
return i32_to_f16((int32_t)(a), status);
}
static __inline float16 ui16_to_f16(uint16_t a, struct softfloat_status_t *status) {
return ui32_to_f16((uint32_t)(a), status);
}
/*your_sha256_hash------------
| 16-bit (half-precision) floating-point operations.
*your_sha256_hash------------*/
uint32_t f16_to_ui32(float16, uint8_t, bool, struct softfloat_status_t *);
uint64_t f16_to_ui64(float16, uint8_t, bool, struct softfloat_status_t *);
int32_t f16_to_i32(float16, uint8_t, bool, struct softfloat_status_t *);
int64_t f16_to_i64(float16, uint8_t, bool, struct softfloat_status_t *);
uint32_t f16_to_ui32_r_minMag(float16, bool, struct softfloat_status_t *);
uint64_t f16_to_ui64_r_minMag(float16, bool, struct softfloat_status_t *);
int32_t f16_to_i32_r_minMag(float16, bool, struct softfloat_status_t *);
int64_t f16_to_i64_r_minMag(float16, bool, struct softfloat_status_t *);
float32 f16_to_f32(float16, struct softfloat_status_t *);
float64 f16_to_f64(float16, struct softfloat_status_t *);
float16 f16_roundToInt(float16, uint8_t, uint8_t, bool, struct softfloat_status_t *);
float16 f16_add(float16, float16, struct softfloat_status_t *);
float16 f16_sub(float16, float16, struct softfloat_status_t *);
float16 f16_mul(float16, float16, struct softfloat_status_t *);
float16 f16_mulAdd(float16, float16, float16, uint8_t op, struct softfloat_status_t *);
float16 f16_div(float16, float16, struct softfloat_status_t *);
float16 f16_min(float16, float16, struct softfloat_status_t *);
float16 f16_max(float16, float16, struct softfloat_status_t *);
float16 f16_getExp(float16, struct softfloat_status_t *);
float16 f16_getMant(float16, struct softfloat_status_t *, int, int);
float16 f16_range(float16, float16, bool is_max, bool is_abs, int sign_ctrl, struct softfloat_status_t *);
int f16_compare(float16, float16, bool, struct softfloat_status_t *);
float16 f16_sqrt(float16, struct softfloat_status_t *);
softfloat_class_t f16_class(float16);
#ifdef __cplusplus
extern "C" {
#endif
bool f16_isSignalingNaN(float16);
bool f16_isNaN(float16);
#ifdef __cplusplus
}
#endif
bool f16_sign(float16);
int8_t f16_exp(float16);
uint16_t f16_fraction(float16);
float16 f16_denormal_to_zero(float16);
static __inline int f16_compare_normal(float16 a, float16 b, struct softfloat_status_t *status) {
return f16_compare(a, b, 0, status);
}
static __inline int f16_compare_quiet(float16 a, float16 b, struct softfloat_status_t *status) {
return f16_compare(a, b, 1, status);
}
static __inline float16 f16_roundToInt_normal(float16 a, uint8_t scale, struct softfloat_status_t *status) {
return f16_roundToInt(a, scale, softfloat_getRoundingMode(status), true, status);
}
static __inline float16 f16_roundToInt_noscale(float16 a, struct softfloat_status_t *status) {
return f16_roundToInt(a, 0, softfloat_getRoundingMode(status), true, status);
}
static __inline int64_t f16_to_i64_normal(float16 a, struct softfloat_status_t *status) {
return f16_to_i64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t f16_to_i32_normal(float16 a, struct softfloat_status_t *status) {
return f16_to_i32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int16_t f16_to_i16(float16 a, struct softfloat_status_t *status)
{
int32_t val_32 = f16_to_i32_normal(a, status);
int16_t val_16 = (int16_t) val_32;
if ((int32_t)(val_16) != val_32) {
softfloat_setFlags(status, softfloat_flag_invalid);
return (int16_t) 0x8000;
}
return val_16;
}
static __inline int64_t f16_to_i64_round_to_zero(float16 a, struct softfloat_status_t *status) {
return f16_to_i64_r_minMag(a, true, status);
}
static __inline int32_t f16_to_i32_round_to_zero(float16 a, struct softfloat_status_t *status) {
return f16_to_i32_r_minMag(a, true, status);
}
static __inline int16_t f16_to_i16_round_to_zero(float16 a, struct softfloat_status_t *status)
{
int32_t val_32 = f16_to_i32_round_to_zero(a, status);
int16_t val_16 = (int16_t) val_32;
if ((int32_t)(val_16) != val_32) {
softfloat_setFlags(status, softfloat_flag_invalid);
return (int16_t) 0x8000;
}
return val_16;
}
static __inline uint64_t f16_to_ui64_normal(float16 a, struct softfloat_status_t *status) {
return f16_to_ui64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint32_t f16_to_ui32_normal(float16 a, struct softfloat_status_t *status) {
return f16_to_ui32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint16_t f16_to_ui16(float16 a, struct softfloat_status_t *status)
{
uint32_t val_32 = f16_to_ui32_normal(a, status);
if (val_32 > 0xFFFF) {
softfloat_setFlags(status, softfloat_flag_invalid);
return 0xFFFF;
}
return (uint16_t) val_32;
}
static __inline uint64_t f16_to_ui64_round_to_zero(float16 a, struct softfloat_status_t *status) {
return f16_to_ui64_r_minMag(a, true, status);
}
static __inline uint32_t f16_to_ui32_round_to_zero(float16 a, struct softfloat_status_t *status) {
return f16_to_ui32_r_minMag(a, true, status);
}
static __inline uint16_t f16_to_ui16_round_to_zero(float16 a, struct softfloat_status_t *status)
{
uint32_t val_32 = f16_to_ui32_round_to_zero(a, status);
if (val_32 > 0xFFFF) {
softfloat_setFlags(status, softfloat_flag_invalid);
return 0xFFFF;
}
return (uint16_t) val_32;
}
static __inline float16 f16_fmadd(float16 a, float16 b, float16 c, struct softfloat_status_t *status) {
return f16_mulAdd(a, b, c, 0, status);
}
static __inline float16 f16_fmsub(float16 a, float16 b, float16 c, struct softfloat_status_t *status) {
return f16_mulAdd(a, b, c, softfloat_muladd_negate_c, status);
}
static __inline float16 f16_fnmadd(float16 a, float16 b, float16 c, struct softfloat_status_t *status) {
return f16_mulAdd(a, b, c, softfloat_muladd_negate_product, status);
}
static __inline float16 f16_fnmsub(float16 a, float16 b, float16 c, struct softfloat_status_t *status) {
return f16_mulAdd(a, b, c, softfloat_muladd_negate_result, status);
}
/*your_sha256_hash------------
| 32-bit (single-precision) floating-point operations.
*your_sha256_hash------------*/
uint32_t f32_to_ui32(float32, uint8_t, bool, struct softfloat_status_t *);
uint64_t f32_to_ui64(float32, uint8_t, bool, struct softfloat_status_t *);
int32_t f32_to_i32(float32, uint8_t, bool, struct softfloat_status_t *);
int64_t f32_to_i64(float32, uint8_t, bool, struct softfloat_status_t *);
uint32_t f32_to_ui32_r_minMag(float32, bool, struct softfloat_status_t *);
uint64_t f32_to_ui64_r_minMag(float32, bool, struct softfloat_status_t *);
int32_t f32_to_i32_r_minMag(float32, bool, struct softfloat_status_t *);
int64_t f32_to_i64_r_minMag(float32, bool, struct softfloat_status_t *);
float16 f32_to_f16(float32, struct softfloat_status_t *);
float64 f32_to_f64(float32, struct softfloat_status_t *);
float32 f32_roundToInt(float32, uint8_t, uint8_t, bool, struct softfloat_status_t *);
float32 f32_add(float32, float32, struct softfloat_status_t *);
float32 f32_sub(float32, float32, struct softfloat_status_t *);
float32 f32_mul(float32, float32, struct softfloat_status_t *);
float32 f32_mulAdd(float32, float32, float32, uint8_t op, struct softfloat_status_t *);
float32 f32_div(float32, float32, struct softfloat_status_t *);
float32 f32_min(float32, float32, struct softfloat_status_t *);
float32 f32_max(float32, float32, struct softfloat_status_t *);
float32 f32_scalef(float32, float32, struct softfloat_status_t *);
float32 f32_getExp(float32, struct softfloat_status_t *);
float32 f32_getMant(float32, struct softfloat_status_t *, int, int);
float32 f32_range(float32, float32, bool is_max, bool is_abs, int sign_ctrl, struct softfloat_status_t *);
float32 f32_frc(float32, struct softfloat_status_t *);
int f32_compare(float32, float32, bool, struct softfloat_status_t *);
float32 f32_sqrt(float32, struct softfloat_status_t *);
softfloat_class_t f32_class(float32);
#ifdef __cplusplus
extern "C" {
#endif
bool f32_isSignalingNaN(float32);
bool f32_isNaN(float32);
#ifdef __cplusplus
}
#endif
bool f32_sign(float32);
int16_t f32_exp(float32);
uint32_t f32_fraction(float32);
float32 f32_denormal_to_zero(float32);
static __inline int f32_compare_normal(float32 a, float32 b, struct softfloat_status_t *status) {
return f32_compare(a, b, 0, status);
}
static __inline int f32_compare_quiet(float32 a, float32 b, struct softfloat_status_t *status) {
return f32_compare(a, b, 1, status);
}
static __inline float32 f32_roundToInt_normal(float32 a, uint8_t scale, struct softfloat_status_t *status) {
return f32_roundToInt(a, scale, softfloat_getRoundingMode(status), true, status);
}
static __inline float32 f32_roundToInt_noscale(float32 a, struct softfloat_status_t *status) {
return f32_roundToInt(a, 0, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t f32_to_i32_normal(float32 a, struct softfloat_status_t *status) {
return f32_to_i32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int64_t f32_to_i64_normal(float32 a, struct softfloat_status_t *status) {
return f32_to_i64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t f32_to_i32_round_to_zero(float32 a, struct softfloat_status_t *status) {
return f32_to_i32_r_minMag(a, true, status);
}
static __inline int64_t f32_to_i64_round_to_zero(float32 a, struct softfloat_status_t *status) {
return f32_to_i64_r_minMag(a, true, status);
}
static __inline uint32_t f32_to_ui32_normal(float32 a, struct softfloat_status_t *status) {
return f32_to_ui32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint64_t f32_to_ui64_normal(float32 a, struct softfloat_status_t *status) {
return f32_to_ui64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint32_t f32_to_ui32_round_to_zero(float32 a, struct softfloat_status_t *status) {
return f32_to_ui32_r_minMag(a, true, status);
}
static __inline uint64_t f32_to_ui64_round_to_zero(float32 a, struct softfloat_status_t *status) {
return f32_to_ui64_r_minMag(a, true, status);
}
static __inline float32 f32_fmadd(float32 a, float32 b, float32 c, struct softfloat_status_t *status) {
return f32_mulAdd(a, b, c, 0, status);
}
static __inline float32 f32_fmsub(float32 a, float32 b, float32 c, struct softfloat_status_t *status) {
return f32_mulAdd(a, b, c, softfloat_muladd_negate_c, status);
}
static __inline float32 f32_fnmadd(float32 a, float32 b, float32 c, struct softfloat_status_t *status) {
return f32_mulAdd(a, b, c, softfloat_muladd_negate_product, status);
}
static __inline float32 f32_fnmsub(float32 a, float32 b, float32 c, struct softfloat_status_t *status) {
return f32_mulAdd(a, b, c, softfloat_muladd_negate_result, status);
}
/*your_sha256_hash------------
| 64-bit (double-precision) floating-point operations.
*your_sha256_hash------------*/
uint32_t f64_to_ui32(float64, uint8_t, bool, struct softfloat_status_t *);
uint64_t f64_to_ui64(float64, uint8_t, bool, struct softfloat_status_t *);
int32_t f64_to_i32(float64, uint8_t, bool, struct softfloat_status_t *);
int64_t f64_to_i64(float64, uint8_t, bool, struct softfloat_status_t *);
uint32_t f64_to_ui32_r_minMag(float64, bool, struct softfloat_status_t *);
uint64_t f64_to_ui64_r_minMag(float64, bool, struct softfloat_status_t *);
int32_t f64_to_i32_r_minMag(float64, bool, struct softfloat_status_t *);
int64_t f64_to_i64_r_minMag(float64, bool, struct softfloat_status_t *);
float16 f64_to_f16(float64, struct softfloat_status_t *);
float32 f64_to_f32(float64, struct softfloat_status_t *);
float64 f64_roundToInt(float64, uint8_t, uint8_t, bool, struct softfloat_status_t *);
float64 f64_add(float64, float64, struct softfloat_status_t *);
float64 f64_sub(float64, float64, struct softfloat_status_t *);
float64 f64_mul(float64, float64, struct softfloat_status_t *);
float64 f64_mulAdd(float64, float64, float64, uint8_t op, struct softfloat_status_t *);
float64 f64_div(float64, float64, struct softfloat_status_t *);
float64 f64_min(float64, float64, struct softfloat_status_t *);
float64 f64_max(float64, float64, struct softfloat_status_t *);
float64 f64_scalef(float64, float64, struct softfloat_status_t *);
float64 f64_getExp(float64, struct softfloat_status_t *);
float64 f64_getMant(float64, struct softfloat_status_t *, int, int);
float64 f64_range(float64, float64, bool is_max, bool is_abs, int sign_ctrl, struct softfloat_status_t *);
float64 f64_frc(float64, struct softfloat_status_t *);
int f64_compare(float64, float64, bool, struct softfloat_status_t *);
float64 f64_sqrt(float64, struct softfloat_status_t *);
softfloat_class_t f64_class(float64);
#ifdef __cplusplus
extern "C" {
#endif
bool f64_isSignalingNaN(float64);
bool f64_isNaN(float64);
#ifdef __cplusplus
}
#endif
bool f64_sign(float64);
int16_t f64_exp(float64);
uint64_t f64_fraction(float64);
float64 f64_denormal_to_zero(float64);
static __inline int f64_compare_normal(float64 a, float64 b, struct softfloat_status_t *status) {
return f64_compare(a, b, 0, status);
}
static __inline int f64_compare_quiet(float64 a, float64 b, struct softfloat_status_t *status) {
return f64_compare(a, b, 1, status);
}
static __inline float64 f64_roundToInt_normal(float64 a, uint8_t scale, struct softfloat_status_t *status) {
return f64_roundToInt(a, scale, softfloat_getRoundingMode(status), true, status);
}
static __inline float64 f64_roundToInt_noscale(float64 a, struct softfloat_status_t *status) {
return f64_roundToInt(a, 0, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t f64_to_i32_normal(float64 a, struct softfloat_status_t *status) {
return f64_to_i32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int64_t f64_to_i64_normal(float64 a, struct softfloat_status_t *status) {
return f64_to_i64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t f64_to_i32_round_to_zero(float64 a, struct softfloat_status_t *status) {
return f64_to_i32_r_minMag(a, true, status);
}
static __inline int64_t f64_to_i64_round_to_zero(float64 a, struct softfloat_status_t *status) {
return f64_to_i64_r_minMag(a, true, status);
}
static __inline uint32_t f64_to_ui32_normal(float64 a, struct softfloat_status_t *status) {
return f64_to_ui32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint64_t f64_to_ui64_normal(float64 a, struct softfloat_status_t *status) {
return f64_to_ui64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline uint32_t f64_to_ui32_round_to_zero(float64 a, struct softfloat_status_t *status) {
return f64_to_ui32_r_minMag(a, true, status);
}
static __inline uint64_t f64_to_ui64_round_to_zero(float64 a, struct softfloat_status_t *status) {
return f64_to_ui64_r_minMag(a, true, status);
}
static __inline float64 f64_fmadd(float64 a, float64 b, float64 c, struct softfloat_status_t *status) {
return f64_mulAdd(a, b, c, 0, status);
}
static __inline float64 f64_fmsub(float64 a, float64 b, float64 c, struct softfloat_status_t *status) {
return f64_mulAdd(a, b, c, softfloat_muladd_negate_c, status);
}
static __inline float64 f64_fnmadd(float64 a, float64 b, float64 c, struct softfloat_status_t *status) {
return f64_mulAdd(a, b, c, softfloat_muladd_negate_product, status);
}
static __inline float64 f64_fnmsub(float64 a, float64 b, float64 c, struct softfloat_status_t *status) {
return f64_mulAdd(a, b, c, softfloat_muladd_negate_result, status);
}
#ifdef __cplusplus
extern "C" {
#endif
/*your_sha256_hash------------
| 80-bit extended double-precision floating-point operations.
*your_sha256_hash------------*/
extFloat80_t f16_to_extF80(float16, struct softfloat_status_t *);
extFloat80_t f32_to_extF80(float32, struct softfloat_status_t *);
extFloat80_t f64_to_extF80(float64, struct softfloat_status_t *);
extFloat80_t i32_to_extF80(int32_t);
extFloat80_t i64_to_extF80(int64_t);
extFloat80_t ui32_to_extF80(uint32_t);
extFloat80_t ui64_to_extF80(uint64_t);
uint32_t extF80_to_ui32(extFloat80_t, uint8_t, bool, struct softfloat_status_t *);
uint64_t extF80_to_ui64(extFloat80_t, uint8_t, bool, struct softfloat_status_t *);
int32_t extF80_to_i32(extFloat80_t, uint8_t, bool, struct softfloat_status_t *);
int64_t extF80_to_i64(extFloat80_t, uint8_t, bool, struct softfloat_status_t *);
uint32_t extF80_to_ui32_r_minMag(extFloat80_t, bool, struct softfloat_status_t *);
uint64_t extF80_to_ui64_r_minMag(extFloat80_t, bool, struct softfloat_status_t *);
int32_t extF80_to_i32_r_minMag(extFloat80_t, bool, struct softfloat_status_t *);
int64_t extF80_to_i64_r_minMag(extFloat80_t, bool, struct softfloat_status_t *);
float16 extF80_to_f16(extFloat80_t, struct softfloat_status_t *);
float32 extF80_to_f32(extFloat80_t, struct softfloat_status_t *);
float64 extF80_to_f64(extFloat80_t, struct softfloat_status_t *);
float128_t extF80_to_f128(extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_roundToInt(extFloat80_t, uint8_t, bool, struct softfloat_status_t *);
extFloat80_t extF80_add(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_sub(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_mul(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_div(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_rem(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_scale(extFloat80_t, extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_sqrt(extFloat80_t, struct softfloat_status_t *);
extFloat80_t extF80_extract(extFloat80_t *, struct softfloat_status_t *);
int extF80_compare(extFloat80_t, extFloat80_t, int, struct softfloat_status_t *);
softfloat_class_t extF80_class(extFloat80_t);
static __inline int extF80_compare_normal(extFloat80_t a, extFloat80_t b, struct softfloat_status_t *status) {
return extF80_compare(a, b, 0, status);
}
static __inline int extF80_compare_quiet(extFloat80_t a, extFloat80_t b, struct softfloat_status_t *status) {
return extF80_compare(a, b, 1, status);
}
static __inline extFloat80_t extF80_roundToInt_normal(extFloat80_t a, struct softfloat_status_t *status) {
return extF80_roundToInt(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int64_t extF80_to_i64_normal(extFloat80_t a, struct softfloat_status_t *status) {
return extF80_to_i64(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int32_t extF80_to_i32_normal(extFloat80_t a, struct softfloat_status_t *status) {
return extF80_to_i32(a, softfloat_getRoundingMode(status), true, status);
}
static __inline int16_t extF80_to_i16(extFloat80_t a, struct softfloat_status_t *status)
{
int32_t v32 = extF80_to_i32_normal(a, status);
int16_t v16 = (int16_t) v32;
if ((int32_t)(v16) != v32) {
softfloat_setFlags(status, softfloat_flag_invalid);
return (int16_t) 0x8000;
}
return v16;
}
static __inline int64_t extF80_to_i64_round_to_zero(extFloat80_t a, struct softfloat_status_t *status) {
return extF80_to_i64_r_minMag(a, true, status);
}
static __inline int32_t extF80_to_i32_round_to_zero(extFloat80_t a, struct softfloat_status_t *status) {
return extF80_to_i32_r_minMag(a, true, status);
}
static __inline int16_t extF80_to_i16_round_to_zero(extFloat80_t a, struct softfloat_status_t *status)
{
int32_t v32 = extF80_to_i32_round_to_zero(a, status);
int16_t v16 = (int16_t) v32;
if ((int32_t)(v16) != v32) {
softfloat_setFlags(status, softfloat_flag_invalid);
return (int16_t) 0x8000;
}
return v16;
}
bool extF80_isUnsupported(extFloat80_t);
bool extF80_isSignalingNaN(extFloat80_t);
bool extF80_isNaN(extFloat80_t);
bool extF80_sign(extFloat80_t);
int16_t extF80_exp(extFloat80_t);
uint64_t extF80_fraction(extFloat80_t);
/*your_sha256_hash------------
| 128-bit (quadruple-precision) floating-point operations.
*your_sha256_hash------------*/
float128_t f32_to_f128(float32, struct softfloat_status_t *);
float128_t f64_to_f128(float64, struct softfloat_status_t *);
float128_t i32_to_f128(int32_t);
float128_t i64_to_f128(int64_t);
float128_t ui32_to_f128(uint32_t);
float128_t ui64_to_f128(uint64_t);
uint32_t f128_to_ui32(float128_t, uint8_t, bool, struct softfloat_status_t *);
uint64_t f128_to_ui64(float128_t, uint8_t, bool, struct softfloat_status_t *);
int32_t f128_to_i32(float128_t, uint8_t, bool, struct softfloat_status_t *);
int64_t f128_to_i64(float128_t, uint8_t, bool, struct softfloat_status_t *);
uint32_t f128_to_ui32_r_minMag(float128_t, bool, struct softfloat_status_t *);
uint64_t f128_to_ui64_r_minMag(float128_t, bool, struct softfloat_status_t *);
int32_t f128_to_i32_r_minMag(float128_t, bool, struct softfloat_status_t *);
int64_t f128_to_i64_r_minMag(float128_t, bool, struct softfloat_status_t *);
float32 f128_to_f32(float128_t, struct softfloat_status_t *);
float64 f128_to_f64(float128_t, struct softfloat_status_t *);
extFloat80_t f128_to_extF80(float128_t, struct softfloat_status_t *);
float128_t f128_roundToInt(float128_t, uint8_t, bool, struct softfloat_status_t *);
float128_t f128_add(float128_t, float128_t, struct softfloat_status_t *);
float128_t f128_sub(float128_t, float128_t, struct softfloat_status_t *);
float128_t f128_mul(float128_t, float128_t, struct softfloat_status_t *);
float128_t f128_mulAdd(float128_t, float128_t, float128_t, uint8_t op, struct softfloat_status_t *);
float128_t f128_div(float128_t, float128_t, struct softfloat_status_t *);
float128_t f128_sqrt(float128_t, struct softfloat_status_t *);
bool f128_isSignalingNaN(float128_t);
bool f128_isNaN(float128_t);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/src/cpu/softfloat3e/softfloat.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,241 |
```html
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat History</TITLE>
</HEAD>
<BODY>
<H1>History of Berkeley SoftFloat, to Release 3e</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<H3>Release 3e (2018 January)</H3>
<UL>
<LI>
Changed the default numeric code for optional rounding mode <CODE>odd</CODE>
(round to odd, also known as <EM>jamming</EM>) from 5 to 6.
<LI>
Modified the behavior of rounding mode <CODE>odd</CODE> when rounding to an
integer value (either conversion to an integer format or a
‘<CODE>roundToInt</CODE>’ function).
Previously, for those cases only, rounding mode <CODE>odd</CODE> acted the same
as rounding to minimum magnitude.
Now all operations are rounded consistently.
<LI>
Fixed some errors in the specialization code modeling Intel x86 floating-point,
specifically the integers returned on invalid operations and the propagation of
NaN payloads in a few rare cases.
<LI>
Added specialization code modeling ARM floating-point, conforming to VFPv2 or
later.
<LI>
Added an example target for ARM processors.
<LI>
Fixed a minor bug whereby function <CODE>f16_to_ui64</CODE> might return a
different integer than expected in the case that the floating-point operand is
negative.
<LI>
Added example target-specific optimization for GCC, employing GCC instrinsics
and support for <NOBR>128-bit</NOBR> integer arithmetic.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3d (2017 August)</H3>
<UL>
<LI>
Fixed bugs in the square root functions for <NOBR>64-bit</NOBR>
double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
<NOBR>128-bit</NOBR> quadruple-precision.
For <NOBR>64-bit</NOBR> double-precision (<CODE>f64_sqrt</CODE>), the result
could sometimes be off by <NOBR>1 unit</NOBR> in the last place
(<NOBR>1 ulp</NOBR>) from what it should be.
For the larger formats, the square root could be wrong in a large portion of
the less-significant bits.
(A bug in <CODE>f128_sqrt</CODE> was first reported by Alexei Sibidanov.)
</UL>
<H3>Release 3c (2017 February)</H3>
<UL>
<LI>
Added optional rounding mode <CODE>odd</CODE> (round to odd, also known as
<EM>jamming</EM>).
<LI>
Corrected the documentation concerning non-canonical representations in
<NOBR>80-bit</NOBR> double-extended-precision.
</UL>
<H3>Release 3b (2016 July)</H3>
<UL>
<LI>
Implemented the common <NOBR>16-bit</NOBR> “half-precision”
floating-point format (<CODE>float16_t</CODE>).
<LI>
Made the integer values returned on invalid conversions to integer formats
be determined by the port-specific specialization instead of being the same for
all ports.
<LI>
Added preprocessor macro <CODE>THREAD_LOCAL</CODE> to allow the floating-point
state (modes and exception flags) to be made per-thread.
<LI>
Modified the provided Makefiles to allow some options to be overridden from the
<CODE>make</CODE> command.
<LI>
Made other minor improvements.
</UL>
<H3>Release 3a (2015 October)</H3>
<UL>
<LI>
Replaced the license text supplied by the University of California, Berkeley.
</UL>
<H3>Release 3 (2015 February)</H3>
<UL>
<LI>
Complete rewrite, funded by the University of California, Berkeley, and
consequently having a different use license than earlier releases.
Major changes included renaming most types and functions, upgrading some
algorithms, restructuring the source files, and making SoftFloat into a true
library.
<LI>
Added functions to convert between floating-point and unsigned integers, both
<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> (<CODE>uint32_t</CODE> and
<CODE>uint64_t</CODE>).
<LI>
Added functions for fused multiply-add, for all supported floating-point
formats except <NOBR>80-bit</NOBR> double-extended-precision.
<LI>
Added support for a fifth rounding mode, <CODE>near_maxMag</CODE> (round to
nearest, with ties to maximum magnitude, away from zero).
<LI>
Dropped the <CODE>timesoftfloat</CODE> program (now part of the Berkeley
TestFloat package).
</UL>
<H3>Release 2c (2015 January)</H3>
<UL>
<LI>
Fixed mistakes affecting some <NOBR>64-bit</NOBR> processors.
<LI>
Further improved the documentation and the wording for the legal restrictions
on using SoftFloat releases <NOBR>through 2c</NOBR> (not applicable to
<NOBR>Release 3</NOBR> or later).
</UL>
<H3>Release 2b (2002 May)</H3>
<UL>
<LI>
Made minor updates to the documentation, including improved wording for the
legal restrictions on using SoftFloat.
</UL>
<H3>Release 2a (1998 December)</H3>
<UL>
<LI>
Added functions to convert between <NOBR>64-bit</NOBR> integers
(<CODE>int64</CODE>) and all supported floating-point formats.
<LI>
Fixed a bug in all <NOBR>64-bit</NOBR>-version square root functions except
<CODE>float32_sqrt</CODE> that caused the result sometimes to be off by
<NOBR>1 unit</NOBR> in the last place (<NOBR>1 ulp</NOBR>) from what it should
be.
(Bug discovered by Paul Donahue.)
<LI>
Improved the Makefiles.
</UL>
<H3>Release 2 (1997 June)</H3>
<UL>
<LI>
Created the <NOBR>64-bit</NOBR> (<CODE>bits64</CODE>) version, adding the
<CODE>floatx80</CODE> and <CODE>float128</CODE> formats.
<LI>
Changed the source directory structure, splitting the sources into a
<CODE>bits32</CODE> and a <CODE>bits64</CODE> version.
Renamed <CODE>environment.h</CODE> to <CODE>milieu.h</CODE> to avoid confusion
with environment variables.
<LI>
Fixed a small error that caused <CODE>float64_round_to_int</CODE> often to
round the wrong way in nearest/even mode when the operand was between
2<SUP>20</SUP> and 2<SUP>21</SUP> and halfway between two integers.
</UL>
<H3>Release 1a (1996 July)</H3>
<UL>
<LI>
Corrected a mistake that caused borderline underflow cases not to raise the
underflow flag when they should have.
(Problem reported by Doug Priest.)
<LI>
Added the <CODE>float_detect_tininess</CODE> variable to control whether
tininess is detected before or after rounding.
</UL>
<H3>Release 1 (1996 July)</H3>
<UL>
<LI>
Original release, based on work done for the International Computer Science
Institute (ICSI) in Berkeley, California.
</UL>
</BODY>
``` | /content/code_sandbox/src/cpu/softfloat3e/doc/SoftFloat-history.html | html | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,670 |
```html
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat Source Documentation</TITLE>
</HEAD>
<BODY>
<H1>Berkeley SoftFloat Release 3e: Source Documentation</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<H2>Contents</H2>
<BLOCKQUOTE>
<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
<COL WIDTH=25>
<COL WIDTH=*>
<TR><TD COLSPAN=2>1. Introduction</TD></TR>
<TR><TD COLSPAN=2>2. Limitations</TD></TR>
<TR><TD COLSPAN=2>4. SoftFloat Package Directory Structure</TD></TR>
<TR><TD COLSPAN=2>5. Issues for Porting SoftFloat to a New Target</TD></TR>
<TR>
<TD></TD>
<TD>5.1. Standard Headers <CODE><stdbool.h></CODE> and
<CODE><stdint.h></CODE></TD>
</TR>
<TR><TD></TD><TD>5.2. Specializing Floating-Point Behavior</TD></TR>
<TR><TD></TD><TD>5.3. Macros for Build Options</TD></TR>
<TR><TD></TD><TD>5.4. Adapting a Template Target Directory</TD></TR>
<TR>
<TD></TD><TD>5.5. Target-Specific Optimization of Primitive Functions</TD>
</TR>
<TR><TD COLSPAN=2>6. Testing SoftFloat</TD></TR>
<TR>
<TD COLSPAN=2>7. Providing SoftFloat as a Common Library for Applications</TD>
</TR>
<TR><TD COLSPAN=2>8. Contact Information</TD></TR>
</TABLE>
</BLOCKQUOTE>
<H2>1. Introduction</H2>
<P>
This document gives information needed for compiling and/or porting Berkeley
SoftFloat, a library of C functions implementing binary floating-point
conforming to the IEEE Standard for Floating-Point Arithmetic.
For basic documentation about SoftFloat refer to
<A HREF="SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A>.
</P>
<P>
The source code for SoftFloat is intended to be relatively machine-independent
and should be compilable with any ISO-Standard C compiler that also supports
<NOBR>64-bit</NOBR> integers.
SoftFloat has been successfully compiled with the GNU C Compiler
(<CODE>gcc</CODE>) for several platforms.
</P>
<P>
<NOBR>Release 3</NOBR> of SoftFloat was a complete rewrite relative to
<NOBR>Release 2</NOBR> or earlier.
Changes to the interface of SoftFloat functions are documented in
<A HREF="SoftFloat.html"><NOBR><CODE>SoftFloat.html</CODE></NOBR></A>.
The current version of SoftFloat is <NOBR>Release 3e</NOBR>.
</P>
<H2>2. Limitations</H2>
<P>
SoftFloat assumes the computer has an addressable byte size of either 8 or
<NOBR>16 bits</NOBR>.
(Nearly all computers in use today have <NOBR>8-bit</NOBR> bytes.)
</P>
<P>
SoftFloat is written in C and is designed to work with other C code.
The C compiler used must conform at a minimum to the 1989 ANSI standard for the
C language (same as the 1990 ISO standard) and must in addition support basic
arithmetic on <NOBR>64-bit</NOBR> integers.
Earlier releases of SoftFloat included implementations of <NOBR>32-bit</NOBR>
single-precision and <NOBR>64-bit</NOBR> double-precision floating-point that
did not require <NOBR>64-bit</NOBR> integers, but this option is not supported
starting with <NOBR>Release 3</NOBR>.
Since 1999, ISO standards for C have mandated compiler support for
<NOBR>64-bit</NOBR> integers.
A compiler conforming to the 1999 C Standard or later is recommended but not
strictly required.
</P>
<P>
<NOBR>C Standard</NOBR> header files <CODE><stdbool.h></CODE> and
<CODE><stdint.h></CODE> are required for defining standard Boolean and
integer types.
If these headers are not supplied with the C compiler, minimal substitutes must
be provided.
SoftFloat’s dependence on these headers is detailed later in
<NOBR>section 5.1</NOBR>, <I>Standard Headers <CODE><stdbool.h></CODE>
and <CODE><stdint.h></CODE></I>.
</P>
<P>
The SoftFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
<NOBR>Release 3</NOBR> of SoftFloat was a completely new implementation
supplanting earlier releases.
The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
done in the employ of the University of California, Berkeley, within the
Department of Electrical Engineering and Computer Sciences, first for the
Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
The work was officially overseen by Prof. Krste Asanovic, with funding provided
by these sources:
<BLOCKQUOTE>
<TABLE>
<COL>
<COL WIDTH=10>
<COL>
<TR>
<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
<TD></TD>
<TD>
Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
NVIDIA, Oracle, and Samsung.
</TD>
</TR>
<TR>
<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
<TD></TD>
<TD>
DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
Oracle, and Samsung.
</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
</P>
<P>
The following applies to the whole of SoftFloat <NOBR>Release 3e</NOBR> as well
as to each source file individually.
</P>
<P>
University of California.
All rights reserved.
</P>
<P>
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
<OL>
<LI>
<P>
Redistributions of source code must retain the above copyright notice, this
list of conditions, and the following disclaimer.
</P>
<LI>
<P>
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions, and the following disclaimer in the documentation and/or
other materials provided with the distribution.
</P>
<LI>
<P>
Neither the name of the University nor the names of its contributors may be
used to endorse or promote products derived from this software without specific
prior written permission.
</P>
</OL>
</P>
<P>
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS “AS IS”,
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED.
IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
</P>
<H2>4. SoftFloat Package Directory Structure</H2>
<P>
Because SoftFloat is targeted to multiple platforms, its source code is
slightly scattered between target-specific and target-independent directories
and files.
The supplied directory structure is as follows:
<BLOCKQUOTE>
<PRE>
doc
source
include
8086
8086-SSE
ARM-VFPv2
ARM-VFPv2-defaultNaN
build
template-FAST_INT64
template-not-FAST_INT64
Linux-386-GCC
Linux-386-SSE2-GCC
Linux-x86_64-GCC
Linux-ARM-VFPv2-GCC
Win32-MinGW
Win32-SSE2-MinGW
Win64-MinGW-w64
</PRE>
</BLOCKQUOTE>
The majority of the SoftFloat sources are provided in the <CODE>source</CODE>
directory.
The <CODE>include</CODE> subdirectory contains several header files
(unsurprisingly), while the other subdirectories of <CODE>source</CODE> contain
source files that specialize the floating-point behavior to match particular
processor families:
<BLOCKQUOTE>
<DL>
<DT><CODE>8086</CODE></DT>
<DD>
Intel’s older, 8087-derived floating-point, extended to all supported
floating-point types
</DD>
<DT><CODE>8086-SSE</CODE></DT>
<DD>
Intel’s x86 processors with Streaming SIMD Extensions (SSE) and later
compatible extensions, having 8087 behavior for <NOBR>80-bit</NOBR>
double-extended-precision (<CODE>extFloat80_t</CODE>) and SSE behavior for
other floating-point types
</DD>
<DT><CODE>ARM-VFPv2</CODE></DT>
<DD>
ARM’s VFPv2 or later floating-point, with NaN payload propagation
</DD>
<DT><CODE>ARM-VFPv2-defaultNaN</CODE></DT>
<DD>
ARM’s VFPv2 or later floating-point, with the “default NaN”
option
</DD>
</DL>
</BLOCKQUOTE>
If other specializations are attempted, these would be expected to be other
subdirectories of <CODE>source</CODE> alongside the ones listed above.
Specialization is covered later, in <NOBR>section 5.2</NOBR>, <I>Specializing
Floating-Point Behavior</I>.
</P>
<P>
The <CODE>build</CODE> directory is intended to contain a subdirectory for each
target platform for which a build of the SoftFloat library may be created.
For each build target, the target’s subdirectory is where all derived
object files and the completed SoftFloat library (typically
<CODE>softfloat.a</CODE> or <CODE>libsoftfloat.a</CODE>) are created.
The two <CODE>template</CODE> subdirectories are not actual build targets but
contain sample files for creating new target directories.
(The meaning of <CODE>FAST_INT64</CODE> will be explained later.)
</P>
<P>
Ignoring the <CODE>template</CODE> directories, the supplied target directories
are intended to follow a naming system of
<NOBR><CODE><<I>execution-environment</I>>-<<I>compiler</I>></CODE></NOBR>.
For the example targets,
<NOBR><CODE><<I>execution-environment</I>></CODE></NOBR> is
<NOBR><CODE>Linux-386</CODE></NOBR>, <NOBR><CODE>Linux-386-SSE2</CODE></NOBR>,
<NOBR><CODE>Linux-x86_64</CODE></NOBR>,
<NOBR><CODE>Linux-ARM-VFPv2</CODE></NOBR>, <CODE>Win32</CODE>,
<NOBR><CODE>Win32-SSE2</CODE></NOBR>, or <CODE>Win64</CODE>, and
<NOBR><CODE><<I>compiler</I>></CODE></NOBR> is <CODE>GCC</CODE>,
<CODE>MinGW</CODE>, or <NOBR><CODE>MinGW-w64</CODE></NOBR>.
</P>
<P>
All of the supplied target directories are merely examples that may or may not
be correct for compiling on any particular system.
Despite requests, there are currently no plans to include and maintain in the
SoftFloat package the build files needed for a great many users’
compilation environments, which can span a huge range of operating systems,
compilers, and other tools.
</P>
<P>
As supplied, each target directory contains two files:
<BLOCKQUOTE>
<PRE>
Makefile
platform.h
</PRE>
</BLOCKQUOTE>
The provided <CODE>Makefile</CODE> is written for GNU <CODE>make</CODE>.
A build of SoftFloat for the specific target is begun by executing the
<CODE>make</CODE> command with the target directory as the current directory.
A completely different build tool can be used if an appropriate
<CODE>Makefile</CODE> equivalent is created.
</P>
<P>
The <CODE>platform.h</CODE> header file exists to provide a location for
additional C declarations specific to the build target.
Every C source file of SoftFloat contains a <CODE>#include</CODE> for
<CODE>platform.h</CODE>.
In many cases, the contents of <CODE>platform.h</CODE> can be as simple as one
or two lines of code.
At the other extreme, to get maximal performance from SoftFloat, it may be
desirable to include in header <CODE>platform.h</CODE> (directly or via
<CODE>#include</CODE>) declarations for numerous target-specific optimizations.
Such possibilities are discussed in the next section, <I>Issues for Porting
SoftFloat to a New Target</I>.
If the target’s compiler or library has bugs or other shortcomings,
workarounds for these issues may also be possible with target-specific
declarations in <CODE>platform.h</CODE>, avoiding the need to modify the main
SoftFloat sources.
</P>
<H2>5. Issues for Porting SoftFloat to a New Target</H2>
<H3>5.1. Standard Headers <CODE><stdbool.h></CODE> and <CODE><stdint.h></CODE></H3>
<P>
The SoftFloat sources make use of standard headers
<CODE><stdbool.h></CODE> and <CODE><stdint.h></CODE>, which have
been part of the ISO C Standard Library since 1999.
With any recent compiler, these standard headers are likely to be supported,
even if the compiler does not claim complete conformance to the latest ISO C
Standard.
For older or nonstandard compilers, substitutes for
<CODE><stdbool.h></CODE> and <CODE><stdint.h></CODE> may need to be
created.
SoftFloat depends on these names from <CODE><stdbool.h></CODE>:
<BLOCKQUOTE>
<PRE>
bool
true
false
</PRE>
</BLOCKQUOTE>
and on these names from <CODE><stdint.h></CODE>:
<BLOCKQUOTE>
<PRE>
uint16_t
uint32_t
uint64_t
int32_t
int64_t
UINT64_C
INT64_C
uint_least8_t
uint_fast8_t
uint_fast16_t
uint_fast32_t
uint_fast64_t
int_fast8_t
int_fast16_t
int_fast32_t
int_fast64_t
</PRE>
</BLOCKQUOTE>
</P>
<H3>5.2. Specializing Floating-Point Behavior</H3>
<P>
The IEEE Floating-Point Standard allows for some flexibility in a conforming
implementation, particularly concerning NaNs.
The SoftFloat <CODE>source</CODE> directory is supplied with some
<I>specialization</I> subdirectories containing possible definitions for this
implementation-specific behavior.
For example, the <CODE>8086</CODE> and <NOBR><CODE>8086-SSE</CODE></NOBR>
subdirectories have source files that specialize SoftFloat’s behavior to
match that of Intel’s x86 line of processors.
The files in a specialization subdirectory must determine:
<UL>
<LI>
whether tininess for underflow is detected before or after rounding by default;
<LI>
how signaling NaNs are distinguished from quiet NaNs;
<LI>
what (if anything) special happens when exceptions are raised;
<LI>
the default generated quiet NaNs;
<LI>
how NaNs are propagated from function inputs to output; and
<LI>
the integer results returned when conversions to integer type raise the
<I>invalid</I> exception.
</UL>
</P>
<P>
As provided, the build process for a target expects to involve exactly
<EM>one</EM> specialization directory that defines <EM>all</EM> of these
implementation-specific details for the target.
A specialization directory such as <CODE>8086</CODE> is expected to contain a
header file called <CODE>specialize.h</CODE>, together with whatever other
source files are needed to complete the specialization.
</P>
<P>
A new build target may use an existing specialization, such as the ones
provided by the <CODE>8086</CODE> and <NOBR><CODE>8086-SSE</CODE></NOBR>
subdirectories.
If a build target needs a new specialization, different from any existing ones,
it is recommended that a new specialization directory be created for this
purpose.
The <CODE>specialize.h</CODE> header file from any of the provided
specialization subdirectories can be used as a model for what definitions are
needed.
</P>
<H3>5.3. Macros for Build Options</H3>
<P>
The SoftFloat source files adapt the floating-point implementation according to
several C preprocessor macros:
<BLOCKQUOTE>
<DL>
<DT><CODE>LITTLEENDIAN</CODE>
<DD>
Must be defined for little-endian machines; must not be defined for big-endian
machines.
<DT><CODE>INLINE</CODE>
<DD>
Specifies the sequence of tokens used to indicate that a C function should be
inlined.
If macro <CODE>INLINE_LEVEL</CODE> is defined with a value of 1 or higher, this
macro must be defined; otherwise, this macro is ignored and need not be
defined.
For compilers that conform to the C Standard’s rules for inline
functions, this macro can be defined as the single keyword <CODE>inline</CODE>.
For other compilers that follow a convention pre-dating the standardization of
<CODE>inline</CODE>, this macro may need to be defined to <CODE>extern</CODE>
<CODE>inline</CODE>.
<DT><CODE>THREAD_LOCAL</CODE>
<DD>
Can be defined to a sequence of tokens that, when appearing at the start of a
variable declaration, indicates to the C compiler that the variable is
<I>per-thread</I>, meaning that each execution thread gets its own separate
instance of the variable.
This macro is used in header <CODE>softfloat.h</CODE> in the declarations of
variables <CODE>softfloat_roundingMode</CODE>,
<CODE>softfloat_detectTininess</CODE>, <CODE>extF80_roundingPrecision</CODE>,
and <CODE>softfloat_exceptionFlags</CODE>.
If macro <CODE>THREAD_LOCAL</CODE> is left undefined, these variables will
default to being ordinary global variables.
Depending on the compiler, possible valid definitions of this macro include
<CODE>_Thread_local</CODE> and <CODE>__thread</CODE>.
</DL>
<DL>
<DT><CODE>SOFTFLOAT_ROUND_ODD</CODE>
<DD>
Can be defined to enable support for optional rounding mode
<CODE>softfloat_round_odd</CODE>.
</DL>
<DL>
<DT><CODE>INLINE_LEVEL</CODE>
<DD>
Can be defined to an integer to determine the degree of inlining requested of
the compiler.
Larger numbers request that more inlining be done.
If this macro is not defined or is defined to a value less <NOBR>than 1</NOBR>
(zero or negative), no inlining is requested.
The maximum effective value is no higher <NOBR>than 5</NOBR>.
Defining this macro to a value greater than 5 is the same as defining it
<NOBR>to 5</NOBR>.
<DT><CODE>SOFTFLOAT_FAST_INT64</CODE>
<DD>
Can be defined to indicate that the build target’s implementation of
<NOBR>64-bit</NOBR> arithmetic is efficient.
For newer <NOBR>64-bit</NOBR> processors, this macro should usually be defined.
For very small microprocessors whose buses and registers are <NOBR>8-bit</NOBR>
or <NOBR>16-bit</NOBR> in size, this macro should usually not be defined.
Whether this macro should be defined for a <NOBR>32-bit</NOBR> processor may
depend on the target machine and the applications that will use SoftFloat.
<DT><CODE>SOFTFLOAT_FAST_DIV32TO16</CODE>
<DD>
Can be defined to indicate that the target’s division operator
<NOBR>in C</NOBR> (written as <CODE>/</CODE>) is reasonably efficient for
dividing a <NOBR>32-bit</NOBR> unsigned integer by a <NOBR>16-bit</NOBR>
unsigned integer.
Setting this macro may affect the performance of function <CODE>f16_div</CODE>.
<DT><CODE>SOFTFLOAT_FAST_DIV64TO32</CODE>
<DD>
Can be defined to indicate that the target’s division operator
<NOBR>in C</NOBR> (written as <CODE>/</CODE>) is reasonably efficient for
dividing a <NOBR>64-bit</NOBR> unsigned integer by a <NOBR>32-bit</NOBR>
unsigned integer.
Setting this macro may affect the performance of division, remainder, and
square root operations other than <CODE>f16_div</CODE>.
</DL>
</BLOCKQUOTE>
</P>
<P>
Following the usual custom <NOBR>for C</NOBR>, for most of these macros (all
except <CODE>INLINE</CODE>, <CODE>THREAD_LOCAL</CODE>, and
<CODE>INLINE_LEVEL</CODE>), the content of any definition is irrelevant;
what matters is a macro’s effect on <CODE>#ifdef</CODE> directives.
</P>
<P>
It is recommended that any definitions of macros <CODE>LITTLEENDIAN</CODE>,
<CODE>INLINE</CODE>, and <CODE>THREAD_LOCAL</CODE> be made in a build
target’s <CODE>platform.h</CODE> header file, because these macros are
expected to be determined inflexibly by the target machine and compiler.
The other five macros select options and control optimization, and thus might
be better located in the target’s Makefile (or its equivalent).
</P>
<H3>5.4. Adapting a Template Target Directory</H3>
<P>
In the <CODE>build</CODE> directory, two <CODE>template</CODE> subdirectories
provide models for new target directories.
Two different templates exist because different functions are needed in the
SoftFloat library depending on whether macro <CODE>SOFTFLOAT_FAST_INT64</CODE>
is defined.
If macro <CODE>SOFTFLOAT_FAST_INT64</CODE> will be defined,
<NOBR><CODE>template-FAST_INT64</CODE></NOBR> is the template to use;
otherwise, <NOBR><CODE>template-not-FAST_INT64</CODE></NOBR> is the appropriate
template.
A new target directory can be created by copying the correct template directory
and editing the files inside.
To avoid confusion, it would be wise to refrain from editing the files within a
template directory directly.
</P>
<H3>5.5. Target-Specific Optimization of Primitive Functions</H3>
<P>
Header file <CODE>primitives.h</CODE> (in directory
<CODE>source/include</CODE>) declares macros and functions for numerous
underlying arithmetic operations upon which many of SoftFloat’s
floating-point functions are ultimately built.
The SoftFloat sources include implementations of all of these functions/macros,
written as standard C code, so a complete and correct SoftFloat library can be
created using only the supplied code for all functions.
However, for many targets, SoftFloat’s performance can be improved by
substituting target-specific implementations of some of the functions/macros
declared in <CODE>primitives.h</CODE>.
</P>
<P>
For example, <CODE>primitives.h</CODE> declares a function called
<CODE>softfloat_countLeadingZeros32</CODE> that takes an unsigned
<NOBR>32-bit</NOBR> integer as an argument and returns the number of the
integer’s most-significant bits that are zeros.
While the SoftFloat sources include an implementation of this function written
in <NOBR>standard C</NOBR>, many processors can perform this same function
directly in only one or two machine instructions.
An alternative, target-specific implementation that maps to those instructions
is likely to be more efficient than the generic C code from the SoftFloat
package.
</P>
<P>
A build target can replace the supplied version of any function or macro of
<CODE>primitives.h</CODE> by defining a macro with the same name in the
target’s <CODE>platform.h</CODE> header file.
For this purpose, it may be helpful for <CODE>platform.h</CODE> to
<CODE>#include</CODE> header file <CODE>primitiveTypes.h</CODE>, which defines
types used for arguments and results of functions declared in
<CODE>primitives.h</CODE>.
When a desired replacement implementation is a function, not a macro, it is
sufficient for <CODE>platform.h</CODE> to include the line
<BLOCKQUOTE>
<PRE>
#define <<I>function-name</I>> <<I>function-name</I>>
</PRE>
</BLOCKQUOTE>
where <NOBR><CODE><<I>function-name</I>></CODE></NOBR> is the name of the
function.
This technically defines <NOBR><CODE><<I>function-name</I>></CODE></NOBR>
as a macro, but one that resolves to the same name, which may then be a
function.
(A preprocessor that conforms to the C Standard is required to limit recursive
macro expansion from being applied more than once.)
</P>
<P>
The supplied header file <CODE>opts-GCC.h</CODE> (in directory
<CODE>source/include</CODE>) provides an example of target-specific
optimization for the GCC compiler.
Each GCC target example in the <CODE>build</CODE> directory has
<BLOCKQUOTE>
<CODE>#include "opts-GCC.h"</CODE>
</BLOCKQUOTE>
in its <CODE>platform.h</CODE> header file.
Before <CODE>opts-GCC.h</CODE> is included, the following macros must be
defined (or not) to control which features are invoked:
<BLOCKQUOTE>
<DL>
<DT><CODE>SOFTFLOAT_BUILTIN_CLZ</CODE></DT>
<DD>
If defined, SoftFloat’s internal
‘<CODE>countLeadingZeros</CODE>’ functions use intrinsics
<CODE>__builtin_clz</CODE> and <CODE>__builtin_clzll</CODE>.
</DD>
<DT><CODE>SOFTFLOAT_INTRINSIC_INT128</CODE></DT>
<DD>
If defined, SoftFloat makes use of GCC’s nonstandard <NOBR>128-bit</NOBR>
integer type <CODE>__int128</CODE>.
</DD>
</DL>
</BLOCKQUOTE>
On some machines, these improvements are observed to increase the speeds of
<CODE>f64_mul</CODE> and <CODE>f128_mul</CODE> by around 20 to 25%, although
other functions receive less dramatic boosts, or none at all.
Results can vary greatly across different platforms.
</P>
<H2>6. Testing SoftFloat</H2>
<P>
SoftFloat can be tested using the <CODE>testsoftfloat</CODE> program by the
same author.
This program is part of the Berkeley TestFloat package available at the Web
page
<A HREF="path_to_url"><NOBR><CODE>path_to_url
The TestFloat package also has a program called <CODE>timesoftfloat</CODE> that
measures the speed of SoftFloat’s floating-point functions.
</P>
<H2>7. Providing SoftFloat as a Common Library for Applications</H2>
<P>
Header file <CODE>softfloat.h</CODE> defines the SoftFloat interface as seen by
clients.
If the SoftFloat library will be made a common library for programs on a
system, the supplied <CODE>softfloat.h</CODE> has a couple of deficiencies for
this purpose:
<UL>
<LI>
As supplied, <CODE>softfloat.h</CODE> depends on another header,
<CODE>softfloat_types.h</CODE>, that is not intended for public use but which
must also be visible to the programmer’s compiler.
<LI>
More troubling, at the time <CODE>softfloat.h</CODE> is included in a C source
file, macros <CODE>SOFTFLOAT_FAST_INT64</CODE> and <CODE>THREAD_LOCAL</CODE>
must be defined, or not defined, consistent with how these macro were defined
when the SoftFloat library was built.
</UL>
In the situation that new programs may regularly <CODE>#include</CODE> header
file <CODE>softfloat.h</CODE>, it is recommended that a custom, self-contained
version of this header file be created that eliminates these issues.
</P>
<H2>8. Contact Information</H2>
<P>
At the time of this writing, the most up-to-date information about SoftFloat
and the latest release can be found at the Web page
<A HREF="path_to_url"><NOBR><CODE>path_to_url
</P>
</BODY>
``` | /content/code_sandbox/src/cpu/softfloat3e/doc/SoftFloat-source.html | html | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,598 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5511 Host to PCI bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#include <86box/agpgart.h>
#ifdef ENABLE_SIS_5511_HOST_TO_PCI_LOG
int sis_5511_host_to_pci_do_log = ENABLE_SIS_5511_HOST_TO_PCI_LOG;
static void
sis_5511_host_to_pci_log(const char *fmt, ...)
{
va_list ap;
if (sis_5511_host_to_pci_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5511_host_to_pci_log(fmt, ...)
#endif
typedef struct sis_5511_host_to_pci_t {
uint8_t pci_conf[256];
uint8_t states[7];
uint8_t slic_regs[4096];
sis_55xx_common_t *sis;
smram_t *smram;
mem_mapping_t slic_mapping;
} sis_5511_host_to_pci_t;
static void
sis_5511_shadow_recalc(sis_5511_host_to_pci_t *dev)
{
int state;
uint32_t base;
for (uint8_t i = 0x80; i <= 0x86; i++) {
if (i == 0x86) {
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xf0000, 0x10000, state);
sis_5511_host_to_pci_log("000F0000-000FFFFF\n");
}
} else {
base = ((i & 0x07) << 15) + 0xc0000;
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x4000, state);
sis_5511_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
}
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0x0a) {
state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base + 0x4000, 0x4000, state);
sis_5511_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
}
}
dev->states[i & 0x0f] = dev->pci_conf[i];
}
flushmmucache_nopc();
}
static void
sis_5511_smram_recalc(sis_5511_host_to_pci_t *dev)
{
smram_disable_all();
switch (dev->pci_conf[0x65] >> 6) {
case 0:
smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
break;
case 1:
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
break;
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
}
void
sis_5511_host_to_pci_write(int addr, uint8_t val, void *priv)
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
sis_5511_host_to_pci_log("SiS 5511 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= 0xb0;
break;
case 0x50:
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates();
break;
case 0x51:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x52:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x53:
case 0x54:
dev->pci_conf[addr] = val;
break;
case 0x55:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x56 ... 0x59:
dev->pci_conf[addr] = val;
break;
case 0x5a:
/* TODO: Fast Gate A20 Emulation and Fast Reset Emulation on the KBC.
The former (bit 7) means the chipset intercepts D1h to 64h and 00h to 60h.
The latter (bit 6) means the chipset intercepts all odd FXh to 64h.
Bit 5 sets fast reset latency. This should be fixed on the other SiS
chipsets as well. */
dev->pci_conf[addr] = val;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0xf7;
break;
case 0x5c:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0x5d:
dev->pci_conf[addr] = val;
break;
case 0x5e:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x60:
dev->pci_conf[addr] = val & 0x3e;
if ((dev->pci_conf[0x68] & 1) && (val & 2)) {
smi_raise();
dev->pci_conf[0x69] |= 1;
}
break;
case 0x61 ... 0x64:
dev->pci_conf[addr] = val;
break;
case 0x65:
dev->pci_conf[addr] = val & 0xd0;
sis_5511_smram_recalc(dev);
break;
case 0x66:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x67:
case 0x68:
dev->pci_conf[addr] = val;
break;
case 0x69:
dev->pci_conf[addr] &= val;
break;
case 0x6a ... 0x6e:
dev->pci_conf[addr] = val;
break;
case 0x6f:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x70: /* DRAM Bank Register 0-0 */
case 0x72: /* DRAM Bank Register 0-1 */
case 0x74: /* DRAM Bank Register 1-0 */
case 0x76: /* DRAM Bank Register 1-1 */
case 0x78: /* DRAM Bank Register 2-0 */
case 0x7a: /* DRAM Bank Register 2-1 */
case 0x7c: /* DRAM Bank Register 3-0 */
case 0x7e: /* DRAM Bank Register 3-1 */
spd_write_drbs(dev->pci_conf, 0x70, 0x7e, 0x82);
break;
case 0x71: /* DRAM Bank Register 0-0 */
dev->pci_conf[addr] = val;
break;
case 0x75: /* DRAM Bank Register 1-0 */
case 0x79: /* DRAM Bank Register 2-0 */
case 0x7d: /* DRAM Bank Register 3-0 */
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x73: /* DRAM Bank Register 0-1 */
case 0x77: /* DRAM Bank Register 1-1 */
case 0x7b: /* DRAM Bank Register 2-1 */
case 0x7f: /* DRAM Bank Register 3-1 */
dev->pci_conf[addr] = val & 0x83;
break;
case 0x80 ... 0x85:
dev->pci_conf[addr] = val & 0xee;
sis_5511_shadow_recalc(dev);
break;
case 0x86:
dev->pci_conf[addr] = val & 0xe8;
sis_5511_shadow_recalc(dev);
break;
case 0x90 ... 0x93: /* 5512 General Purpose Register Index */
dev->pci_conf[addr] = val;
break;
}
}
uint8_t
sis_5511_host_to_pci_read(int addr, void *priv)
{
const sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5511_host_to_pci_log("SiS 5511 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5511_slic_write(uint32_t addr, uint8_t val, void *priv)
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
addr &= 0x00000fff;
switch (addr) {
case 0x00000000:
case 0x00000008: /* 0x00000008 is a SiS 5512 register. */
dev->slic_regs[addr] = val;
break;
case 0x00000010:
case 0x00000018:
case 0x00000028:
case 0x00000038:
dev->slic_regs[addr] = val & 0x01;
break;
case 0x00000030:
dev->slic_regs[addr] = val & 0x0f;
mem_mapping_set_addr(&dev->slic_mapping,
(((uint32_t) (val & 0x0f)) << 28) | 0x0fc00000, 0x00001000);
break;
}
}
static uint8_t
sis_5511_slic_read(uint32_t addr, void *priv)
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
uint8_t ret = 0xff;
addr &= 0x00000fff;
switch (addr) {
case 0x00000008: /* 0x00000008 is a SiS 5512 register. */
ret = dev->slic_regs[addr];
break;
}
return ret;
}
static void
sis_5511_host_to_pci_reset(void *priv)
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x11;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x05] = dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x00;
dev->pci_conf[0x09] = dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x50] = dev->pci_conf[0x51] = 0x00;
dev->pci_conf[0x52] = 0x20;
dev->pci_conf[0x53] = dev->pci_conf[0x54] = 0x00;
dev->pci_conf[0x55] = dev->pci_conf[0x56] = 0x00;
dev->pci_conf[0x57] = dev->pci_conf[0x58] = 0x00;
dev->pci_conf[0x59] = dev->pci_conf[0x5a] = 0x00;
dev->pci_conf[0x5b] = dev->pci_conf[0x5c] = 0x00;
dev->pci_conf[0x5d] = dev->pci_conf[0x5e] = 0x00;
dev->pci_conf[0x5f] = dev->pci_conf[0x60] = 0x00;
dev->pci_conf[0x61] = dev->pci_conf[0x62] = 0xff;
dev->pci_conf[0x63] = 0xff;
dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x66] = 0x00;
dev->pci_conf[0x67] = 0xff;
dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6a] = 0x00;
dev->pci_conf[0x6b] = dev->pci_conf[0x6c] = 0xff;
dev->pci_conf[0x6d] = dev->pci_conf[0x6e] = 0xff;
dev->pci_conf[0x6f] = 0x00;
dev->pci_conf[0x70] = dev->pci_conf[0x72] = 0x04;
dev->pci_conf[0x74] = dev->pci_conf[0x76] = 0x04;
dev->pci_conf[0x78] = dev->pci_conf[0x7a] = 0x04;
dev->pci_conf[0x7c] = dev->pci_conf[0x7e] = 0x04;
dev->pci_conf[0x71] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x73] = dev->pci_conf[0x77] = 0x80;
dev->pci_conf[0x79] = dev->pci_conf[0x7d] = 0x00;
dev->pci_conf[0x7b] = dev->pci_conf[0x7f] = 0x80;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x82] = dev->pci_conf[0x83] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x85] = 0x00;
dev->pci_conf[0x86] = 0x00;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
sis_5511_smram_recalc(dev);
sis_5511_shadow_recalc(dev);
flushmmucache();
memset(dev->slic_regs, 0x00, 4096 * sizeof(uint8_t));
dev->slic_regs[0x18] = 0x0f;
mem_mapping_set_addr(&dev->slic_mapping, 0xffc00000, 0x00001000);
}
static void
sis_5511_host_to_pci_close(void *priv)
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5511_host_to_pci_init(UNUSED(const device_t *info))
{
sis_5511_host_to_pci_t *dev = (sis_5511_host_to_pci_t *) calloc(1, sizeof(sis_5511_host_to_pci_t));
dev->sis = device_get_common_priv();
/* SLiC Memory Mapped Registers */
mem_mapping_add(&dev->slic_mapping,
0xffc00000, 0x00001000,
sis_5511_slic_read,
NULL,
NULL,
sis_5511_slic_write,
NULL,
NULL,
NULL, MEM_MAPPING_EXTERNAL,
dev);
/* SMRAM */
dev->smram = smram_add();
sis_5511_host_to_pci_reset(dev);
return dev;
}
const device_t sis_5511_h2p_device = {
.name = "SiS 5511 Host to PCI bridge",
.internal_name = "sis_5511_host_to_pci",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5511_host_to_pci_init,
.close = sis_5511_host_to_pci_close,
.reset = sis_5511_host_to_pci_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5511_h2p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,548 |
```html
<HTML>
<HEAD>
<TITLE>Berkeley SoftFloat Library Interface</TITLE>
</HEAD>
<BODY>
<H1>Berkeley SoftFloat Release 3e: Library Interface</H1>
<P>
John R. Hauser<BR>
2018 January 20<BR>
</P>
<H2>Contents</H2>
<BLOCKQUOTE>
<TABLE BORDER=0 CELLSPACING=0 CELLPADDING=0>
<COL WIDTH=25>
<COL WIDTH=*>
<TR><TD COLSPAN=2>1. Introduction</TD></TR>
<TR><TD COLSPAN=2>2. Limitations</TD></TR>
<TR><TD COLSPAN=2>4. Types and Functions</TD></TR>
<TR><TD></TD><TD>4.1. Boolean and Integer Types</TD></TR>
<TR><TD></TD><TD>4.2. Floating-Point Types</TD></TR>
<TR><TD></TD><TD>4.3. Supported Floating-Point Functions</TD></TR>
<TR>
<TD></TD>
<TD>4.4. Non-canonical Representations in <CODE>extFloat80_t</CODE></TD>
</TR>
<TR><TD></TD><TD>4.5. Conventions for Passing Arguments and Results</TD></TR>
<TR><TD COLSPAN=2>5. Reserved Names</TD></TR>
<TR><TD COLSPAN=2>6. Mode Variables</TD></TR>
<TR><TD></TD><TD>6.1. Rounding Mode</TD></TR>
<TR><TD></TD><TD>6.2. Underflow Detection</TD></TR>
<TR>
<TD></TD>
<TD>6.3. Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</TD>
</TR>
<TR><TD COLSPAN=2>7. Exceptions and Exception Flags</TD></TR>
<TR><TD COLSPAN=2>8. Function Details</TD></TR>
<TR><TD></TD><TD>8.1. Conversions from Integer to Floating-Point</TD></TR>
<TR><TD></TD><TD>8.2. Conversions from Floating-Point to Integer</TD></TR>
<TR><TD></TD><TD>8.3. Conversions Among Floating-Point Types</TD></TR>
<TR><TD></TD><TD>8.4. Basic Arithmetic Functions</TD></TR>
<TR><TD></TD><TD>8.5. Fused Multiply-Add Functions</TD></TR>
<TR><TD></TD><TD>8.6. Remainder Functions</TD></TR>
<TR><TD></TD><TD>8.7. Round-to-Integer Functions</TD></TR>
<TR><TD></TD><TD>8.8. Comparison Functions</TD></TR>
<TR><TD></TD><TD>8.9. Signaling NaN Test Functions</TD></TR>
<TR><TD></TD><TD>8.10. Raise-Exception Function</TD></TR>
<TR><TD COLSPAN=2>9. Changes from SoftFloat <NOBR>Release 2</NOBR></TD></TR>
<TR><TD></TD><TD>9.1. Name Changes</TD></TR>
<TR><TD></TD><TD>9.2. Changes to Function Arguments</TD></TR>
<TR><TD></TD><TD>9.3. Added Capabilities</TD></TR>
<TR><TD></TD><TD>9.4. Better Compatibility with the C Language</TD></TR>
<TR><TD></TD><TD>9.5. New Organization as a Library</TD></TR>
<TR><TD></TD><TD>9.6. Optimization Gains (and Losses)</TD></TR>
<TR><TD COLSPAN=2>10. Future Directions</TD></TR>
<TR><TD COLSPAN=2>11. Contact Information</TD></TR>
</TABLE>
</BLOCKQUOTE>
<H2>1. Introduction</H2>
<P>
Berkeley SoftFloat is a software implementation of binary floating-point that
conforms to the IEEE Standard for Floating-Point Arithmetic.
The current release supports five binary formats: <NOBR>16-bit</NOBR>
half-precision, <NOBR>32-bit</NOBR> single-precision, <NOBR>64-bit</NOBR>
double-precision, <NOBR>80-bit</NOBR> double-extended-precision, and
<NOBR>128-bit</NOBR> quadruple-precision.
The following functions are supported for each format:
<UL>
<LI>
addition, subtraction, multiplication, division, and square root;
<LI>
fused multiply-add as defined by the IEEE Standard, except for
<NOBR>80-bit</NOBR> double-extended-precision;
<LI>
remainder as defined by the IEEE Standard;
<LI>
round to integral value;
<LI>
comparisons;
<LI>
conversions to/from other supported formats; and
<LI>
conversions to/from <NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> integers,
signed and unsigned.
</UL>
All operations required by the original 1985 version of the IEEE Floating-Point
Standard are implemented, except for conversions to and from decimal.
</P>
<P>
This document gives information about the types defined and the routines
implemented by SoftFloat.
It does not attempt to define or explain the IEEE Floating-Point Standard.
Information about the standard is available elsewhere.
</P>
<P>
The current version of SoftFloat is <NOBR>Release 3e</NOBR>.
This release modifies the behavior of the rarely used <I>odd</I> rounding mode
(<I>round to odd</I>, also known as <I>jamming</I>), and also adds some new
specialization and optimization examples for those compiling SoftFloat.
</P>
<P>
The previous <NOBR>Release 3d</NOBR> fixed bugs that were found in the square
root functions for the <NOBR>64-bit</NOBR>, <NOBR>80-bit</NOBR>, and
<NOBR>128-bit</NOBR> floating-point formats.
(Thanks to Alexei Sibidanov at the University of Victoria for reporting an
incorrect result.)
The bugs affected all prior <NOBR>Release-3</NOBR> versions of SoftFloat
<NOBR>through 3c</NOBR>.
The flaw in the <NOBR>64-bit</NOBR> floating-point square root function was of
very minor impact, causing a <NOBR>1-ulp</NOBR> error (<NOBR>1 unit</NOBR> in
the last place) a few times out of a billion.
The bugs in the <NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> square root
functions were more serious.
Although incorrect results again occurred only a few times out of a billion,
when they did occur a large portion of the less-significant bits could be
wrong.
</P>
<P>
Among earlier releases, 3b was notable for adding support for the
<NOBR>16-bit</NOBR> half-precision format.
For more about the evolution of SoftFloat releases, see
<A HREF="SoftFloat-history.html"><NOBR><CODE>SoftFloat-history.html</CODE></NOBR></A>.
</P>
<P>
The functional interface of SoftFloat <NOBR>Release 3</NOBR> and later differs
in many details from the releases that came before.
For specifics of these differences, see <NOBR>section 9</NOBR> below,
<I>Changes from SoftFloat <NOBR>Release 2</NOBR></I>.
</P>
<H2>2. Limitations</H2>
<P>
SoftFloat assumes the computer has an addressable byte size of 8 or
<NOBR>16 bits</NOBR>.
(Nearly all computers in use today have <NOBR>8-bit</NOBR> bytes.)
</P>
<P>
SoftFloat is written in C and is designed to work with other C code.
The C compiler used must conform at a minimum to the 1989 ANSI standard for the
C language (same as the 1990 ISO standard) and must in addition support basic
arithmetic on <NOBR>64-bit</NOBR> integers.
Earlier releases of SoftFloat included implementations of <NOBR>32-bit</NOBR>
single-precision and <NOBR>64-bit</NOBR> double-precision floating-point that
did not require <NOBR>64-bit</NOBR> integers, but this option is not supported
starting with <NOBR>Release 3</NOBR>.
Since 1999, ISO standards for C have mandated compiler support for
<NOBR>64-bit</NOBR> integers.
A compiler conforming to the 1999 C Standard or later is recommended but not
strictly required.
</P>
<P>
Most operations not required by the original 1985 version of the IEEE
Floating-Point Standard but added in the 2008 version are not yet supported in
SoftFloat <NOBR>Release 3e</NOBR>.
</P>
<P>
The SoftFloat package was written by me, <NOBR>John R.</NOBR> Hauser.
<NOBR>Release 3</NOBR> of SoftFloat was a completely new implementation
supplanting earlier releases.
The project to create <NOBR>Release 3</NOBR> (now <NOBR>through 3e</NOBR>) was
done in the employ of the University of California, Berkeley, within the
Department of Electrical Engineering and Computer Sciences, first for the
Parallel Computing Laboratory (Par Lab) and then for the ASPIRE Lab.
The work was officially overseen by Prof. Krste Asanovic, with funding provided
by these sources:
<BLOCKQUOTE>
<TABLE>
<COL>
<COL WIDTH=10>
<COL>
<TR>
<TD VALIGN=TOP><NOBR>Par Lab:</NOBR></TD>
<TD></TD>
<TD>
Microsoft (Award #024263), Intel (Award #024894), and U.C. Discovery
(Award #DIG07-10227), with additional support from Par Lab affiliates Nokia,
NVIDIA, Oracle, and Samsung.
</TD>
</TR>
<TR>
<TD VALIGN=TOP><NOBR>ASPIRE Lab:</NOBR></TD>
<TD></TD>
<TD>
DARPA PERFECT program (Award #HR0011-12-2-0016), with additional support from
ASPIRE industrial sponsor Intel and ASPIRE affiliates Google, Nokia, NVIDIA,
Oracle, and Samsung.
</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
</P>
<P>
The following applies to the whole of SoftFloat <NOBR>Release 3e</NOBR> as well
as to each source file individually.
</P>
<P>
University of California.
All rights reserved.
</P>
<P>
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
<OL>
<LI>
<P>
Redistributions of source code must retain the above copyright notice, this
list of conditions, and the following disclaimer.
</P>
<LI>
<P>
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions, and the following disclaimer in the documentation and/or
other materials provided with the distribution.
</P>
<LI>
<P>
Neither the name of the University nor the names of its contributors may be
used to endorse or promote products derived from this software without specific
prior written permission.
</P>
</OL>
</P>
<P>
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS “AS IS”,
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED.
IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
</P>
<H2>4. Types and Functions</H2>
<P>
The types and functions of SoftFloat are declared in header file
<CODE>softfloat.h</CODE>.
</P>
<H3>4.1. Boolean and Integer Types</H3>
<P>
Header file <CODE>softfloat.h</CODE> depends on standard headers
<CODE><stdbool.h></CODE> and <CODE><stdint.h></CODE> to define type
<CODE>bool</CODE> and several integer types.
These standard headers have been part of the ISO C Standard Library since 1999.
With any recent compiler, they are likely to be supported, even if the compiler
does not claim complete conformance to the latest ISO C Standard.
For older or nonstandard compilers, a port of SoftFloat may have substitutes
for these headers.
Header <CODE>softfloat.h</CODE> depends only on the name <CODE>bool</CODE> from
<CODE><stdbool.h></CODE> and on these type names from
<CODE><stdint.h></CODE>:
<BLOCKQUOTE>
<PRE>
uint16_t
uint32_t
uint64_t
int32_t
int64_t
uint_fast8_t
uint_fast32_t
uint_fast64_t
int_fast32_t
int_fast64_t
</PRE>
</BLOCKQUOTE>
</P>
<H3>4.2. Floating-Point Types</H3>
<P>
The <CODE>softfloat.h</CODE> header defines five floating-point types:
<BLOCKQUOTE>
<TABLE CELLSPACING=0 CELLPADDING=0>
<TR>
<TD><CODE>float16_t</CODE></TD>
<TD><NOBR>16-bit</NOBR> half-precision binary format</TD>
</TR>
<TR>
<TD><CODE>float32_t</CODE></TD>
<TD><NOBR>32-bit</NOBR> single-precision binary format</TD>
</TR>
<TR>
<TD><CODE>float64_t</CODE></TD>
<TD><NOBR>64-bit</NOBR> double-precision binary format</TD>
</TR>
<TR>
<TD><CODE>extFloat80_t </CODE></TD>
<TD><NOBR>80-bit</NOBR> double-extended-precision binary format (old Intel or
Motorola format)</TD>
</TR>
<TR>
<TD><CODE>float128_t</CODE></TD>
<TD><NOBR>128-bit</NOBR> quadruple-precision binary format</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
The non-extended types are each exactly the size specified:
<NOBR>16 bits</NOBR> for <CODE>float16_t</CODE>, <NOBR>32 bits</NOBR> for
<CODE>float32_t</CODE>, <NOBR>64 bits</NOBR> for <CODE>float64_t</CODE>, and
<NOBR>128 bits</NOBR> for <CODE>float128_t</CODE>.
Aside from these size requirements, the definitions of all these types may
differ for different ports of SoftFloat to specific systems.
A given port of SoftFloat may or may not define some of the floating-point
types as aliases for the C standard types <CODE>float</CODE>,
<CODE>double</CODE>, and <CODE>long</CODE> <CODE>double</CODE>.
</P>
<P>
Header file <CODE>softfloat.h</CODE> also defines a structure,
<CODE>struct</CODE> <CODE>extFloat80M</CODE>, for the representation of
<NOBR>80-bit</NOBR> double-extended-precision floating-point values in memory.
This structure is the same size as type <CODE>extFloat80_t</CODE> and contains
at least these two fields (not necessarily in this order):
<BLOCKQUOTE>
<PRE>
uint16_t signExp;
uint64_t signif;
</PRE>
</BLOCKQUOTE>
Field <CODE>signExp</CODE> contains the sign and exponent of the floating-point
value, with the sign in the most significant bit (<NOBR>bit 15</NOBR>) and the
encoded exponent in the other <NOBR>15 bits</NOBR>.
Field <CODE>signif</CODE> is the complete <NOBR>64-bit</NOBR> significand of
the floating-point value.
(In the usual encoding for <NOBR>80-bit</NOBR> extended floating-point, the
leading <NOBR>1 bit</NOBR> of normalized numbers is not implicit but is stored
in the most significant bit of the significand.)
</P>
<H3>4.3. Supported Floating-Point Functions</H3>
<P>
SoftFloat implements these arithmetic operations for its floating-point types:
<UL>
<LI>
conversions between any two floating-point formats;
<LI>
for each floating-point format, conversions to and from signed and unsigned
<NOBR>32-bit</NOBR> and <NOBR>64-bit</NOBR> integers;
<LI>
for each format, the usual addition, subtraction, multiplication, division, and
square root operations;
<LI>
for each format except <CODE>extFloat80_t</CODE>, the fused multiply-add
operation defined by the IEEE Standard;
<LI>
for each format, the floating-point remainder operation defined by the IEEE
Standard;
<LI>
for each format, a “round to integer” operation that rounds to the
nearest integer value in the same format; and
<LI>
comparisons between two values in the same floating-point format.
</UL>
</P>
<P>
The following operations required by the 2008 IEEE Floating-Point Standard are
not supported in SoftFloat <NOBR>Release 3e</NOBR>:
<UL>
<LI>
<B>nextUp</B>, <B>nextDown</B>, <B>minNum</B>, <B>maxNum</B>, <B>minNumMag</B>,
<B>maxNumMag</B>, <B>scaleB</B>, and <B>logB</B>;
<LI>
conversions between floating-point formats and decimal or hexadecimal character
sequences;
<LI>
all “quiet-computation” operations (<B>copy</B>, <B>negate</B>,
<B>abs</B>, and <B>copySign</B>, which all involve only simple copying and/or
manipulation of the floating-point sign bit); and
<LI>
all “non-computational” operations other than <B>isSignaling</B>
(which is supported).
</UL>
</P>
<H3>4.4. Non-canonical Representations in <CODE>extFloat80_t</CODE></H3>
<P>
Because the <NOBR>80-bit</NOBR> double-extended-precision format,
<CODE>extFloat80_t</CODE>, stores an explicit leading significand bit, many
finite floating-point numbers are encodable in this type in multiple equivalent
forms.
Of these multiple encodings, there is always a unique one with the least
encoded exponent value, and this encoding is considered the <I>canonical</I>
representation of the floating-point number.
Any other equivalent representations (having a higher encoded exponent value)
are <I>non-canonical</I>.
For a value in the subnormal range (including zero), the canonical
representation always has an encoded exponent of zero and a leading significand
bit <NOBR>of 0</NOBR>.
For finite values outside the subnormal range, the canonical representation
always has an encoded exponent that is nonzero and a leading significand bit
<NOBR>of 1</NOBR>.
</P>
<P>
For an infinity or NaN, the leading significand bit is similarly expected to
<NOBR>be 1</NOBR>.
An infinity or NaN with a leading significand bit <NOBR>of 0</NOBR> is again
considered non-canonical.
Hence, altogether, to be canonical, a value of type <CODE>extFloat80_t</CODE>
must have a leading significand bit <NOBR>of 1</NOBR>, unless the value is
subnormal or zero, in which case the leading significand bit and the encoded
exponent must both be zero.
</P>
<P>
SoftFloat’s functions are not guaranteed to operate as expected when
inputs of type <CODE>extFloat80_t</CODE> are non-canonical.
Assuming all of a function’s <CODE>extFloat80_t</CODE> inputs (if any)
are canonical, function outputs of type <CODE>extFloat80_t</CODE> will always
be canonical.
</P>
<H3>4.5. Conventions for Passing Arguments and Results</H3>
<P>
Values that are at most <NOBR>64 bits</NOBR> in size (i.e., not the
<NOBR>80-bit</NOBR> or <NOBR>128-bit</NOBR> floating-point formats) are in all
cases passed as function arguments by value.
Likewise, when an output of a function is no more than <NOBR>64 bits</NOBR>, it
is always returned directly as the function result.
Thus, for example, the SoftFloat function for adding two <NOBR>64-bit</NOBR>
floating-point values has this simple signature:
<BLOCKQUOTE>
<CODE>float64_t f64_add( float64_t, float64_t );</CODE>
</BLOCKQUOTE>
</P>
<P>
The story is more complex when function inputs and outputs are
<NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> floating-point.
For these types, SoftFloat always provides a function that passes these larger
values into or out of the function indirectly, via pointers.
For example, for adding two <NOBR>128-bit</NOBR> floating-point values,
SoftFloat supplies this function:
<BLOCKQUOTE>
<CODE>void f128M_add( const float128_t *, const float128_t *, float128_t * );</CODE>
</BLOCKQUOTE>
The first two arguments point to the values to be added, and the last argument
points to the location where the sum will be stored.
The <CODE>M</CODE> in the name <CODE>f128M_add</CODE> is mnemonic for the fact
that the <NOBR>128-bit</NOBR> inputs and outputs are “in memory”,
pointed to by pointer arguments.
</P>
<P>
All ports of SoftFloat implement these <I>pass-by-pointer</I> functions for
types <CODE>extFloat80_t</CODE> and <CODE>float128_t</CODE>.
At the same time, SoftFloat ports may also implement alternate versions of
these same functions that pass <CODE>extFloat80_t</CODE> and
<CODE>float128_t</CODE> by value, like the smaller formats.
Thus, besides the function with name <CODE>f128M_add</CODE> shown above, a
SoftFloat port may also supply an equivalent function with this signature:
<BLOCKQUOTE>
<CODE>float128_t f128_add( float128_t, float128_t );</CODE>
</BLOCKQUOTE>
</P>
<P>
As a general rule, on computers where the machine word size is
<NOBR>32 bits</NOBR> or smaller, only the pass-by-pointer versions of functions
(e.g., <CODE>f128M_add</CODE>) are provided for types <CODE>extFloat80_t</CODE>
and <CODE>float128_t</CODE>, because passing such large types directly can have
significant extra cost.
On computers where the word size is <NOBR>64 bits</NOBR> or larger, both
function versions (<CODE>f128M_add</CODE> and <CODE>f128_add</CODE>) are
provided, because the cost of passing by value is then more reasonable.
Applications that must be portable accross both classes of computers must use
the pointer-based functions, as these are always implemented.
However, if it is known that SoftFloat includes the by-value functions for all
platforms of interest, programmers can use whichever version they prefer.
</P>
<H2>5. Reserved Names</H2>
<P>
In addition to the variables and functions documented here, SoftFloat defines
some symbol names for its own private use.
These private names always begin with the prefix
‘<CODE>softfloat_</CODE>’.
When a program includes header <CODE>softfloat.h</CODE> or links with the
SoftFloat library, all names with prefix ‘<CODE>softfloat_</CODE>’
are reserved for possible use by SoftFloat.
Applications that use SoftFloat should not define their own names with this
prefix, and should reference only such names as are documented.
</P>
<H2>6. Mode Variables</H2>
<P>
The following global variables control rounding mode, underflow detection, and
the <NOBR>80-bit</NOBR> extended format’s rounding precision:
<BLOCKQUOTE>
<CODE>softfloat_roundingMode</CODE><BR>
<CODE>softfloat_detectTininess</CODE><BR>
<CODE>extF80_roundingPrecision</CODE>
</BLOCKQUOTE>
These mode variables are covered in the next several subsections.
For some SoftFloat ports, these variables may be <I>per-thread</I> (declared
<CODE>thread_local</CODE>), meaning that different execution threads have their
own separate copies of the variables.
</P>
<H3>6.1. Rounding Mode</H3>
<P>
All five rounding modes defined by the 2008 IEEE Floating-Point Standard are
implemented for all operations that require rounding.
Some ports of SoftFloat may also implement the <I>round-to-odd</I> mode.
</P>
<P>
The rounding mode is selected by the global variable
<BLOCKQUOTE>
<CODE>uint_fast8_t softfloat_roundingMode;</CODE>
</BLOCKQUOTE>
This variable may be set to one of the values
<BLOCKQUOTE>
<TABLE CELLSPACING=0 CELLPADDING=0>
<TR>
<TD><CODE>softfloat_round_near_even</CODE></TD>
<TD>round to nearest, with ties to even</TD>
</TR>
<TR>
<TD><CODE>softfloat_round_near_maxMag </CODE></TD>
<TD>round to nearest, with ties to maximum magnitude (away from zero)</TD>
</TR>
<TR>
<TD><CODE>softfloat_round_minMag</CODE></TD>
<TD>round to minimum magnitude (toward zero)</TD>
</TR>
<TR>
<TD><CODE>softfloat_round_min</CODE></TD>
<TD>round to minimum (down)</TD>
</TR>
<TR>
<TD><CODE>softfloat_round_max</CODE></TD>
<TD>round to maximum (up)</TD>
</TR>
<TR>
<TD><CODE>softfloat_round_odd</CODE></TD>
<TD>round to odd (jamming), if supported by the SoftFloat port</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
Variable <CODE>softfloat_roundingMode</CODE> is initialized to
<CODE>softfloat_round_near_even</CODE>.
</P>
<P>
When <CODE>softfloat_round_odd</CODE> is the rounding mode for a function that
rounds to an integer value (either conversion to an integer format or a
‘<CODE>roundToInt</CODE>’ function), if the input is not already an
integer, the rounded result is the closest <EM>odd</EM> integer.
For other operations, this rounding mode acts as though the floating-point
result is first rounded to minimum magnitude, the same as
<CODE>softfloat_round_minMag</CODE>, and then, if the result is inexact, the
least-significant bit of the result is set <NOBR>to 1</NOBR>.
Rounding to odd is also known as <EM>jamming</EM>.
</P>
<H3>6.2. Underflow Detection</H3>
<P>
In the terminology of the IEEE Standard, SoftFloat can detect tininess for
underflow either before or after rounding.
The choice is made by the global variable
<BLOCKQUOTE>
<CODE>uint_fast8_t softfloat_detectTininess;</CODE>
</BLOCKQUOTE>
which can be set to either
<BLOCKQUOTE>
<CODE>softfloat_tininess_beforeRounding</CODE><BR>
<CODE>softfloat_tininess_afterRounding</CODE>
</BLOCKQUOTE>
Detecting tininess after rounding is usually better because it results in fewer
spurious underflow signals.
The other option is provided for compatibility with some systems.
Like most systems (and as required by the newer 2008 IEEE Standard), SoftFloat
always detects loss of accuracy for underflow as an inexact result.
</P>
<H3>6.3. Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</H3>
<P>
For <CODE>extFloat80_t</CODE> only, the rounding precision of the basic
arithmetic operations is controlled by the global variable
<BLOCKQUOTE>
<CODE>uint_fast8_t extF80_roundingPrecision;</CODE>
</BLOCKQUOTE>
The operations affected are:
<BLOCKQUOTE>
<CODE>extF80_add</CODE><BR>
<CODE>extF80_sub</CODE><BR>
<CODE>extF80_mul</CODE><BR>
<CODE>extF80_div</CODE><BR>
<CODE>extF80_sqrt</CODE>
</BLOCKQUOTE>
When <CODE>extF80_roundingPrecision</CODE> is set to its default value of 80,
these operations are rounded to the full precision of the <NOBR>80-bit</NOBR>
double-extended-precision format, like occurs for other formats.
Setting <CODE>extF80_roundingPrecision</CODE> to 32 or to 64 causes the
operations listed to be rounded to <NOBR>32-bit</NOBR> precision (equivalent to
<CODE>float32_t</CODE>) or to <NOBR>64-bit</NOBR> precision (equivalent to
<CODE>float64_t</CODE>), respectively.
When rounding to reduced precision, additional bits in the result significand
beyond the rounding point are set to zero.
The consequences of setting <CODE>extF80_roundingPrecision</CODE> to a value
other than 32, 64, or 80 is not specified.
Operations other than the ones listed above are not affected by
<CODE>extF80_roundingPrecision</CODE>.
</P>
<H2>7. Exceptions and Exception Flags</H2>
<P>
All five exception flags required by the IEEE Floating-Point Standard are
implemented.
Each flag is stored as a separate bit in the global variable
<BLOCKQUOTE>
<CODE>uint_fast8_t softfloat_exceptionFlags;</CODE>
</BLOCKQUOTE>
The positions of the exception flag bits within this variable are determined by
the bit masks
<BLOCKQUOTE>
<CODE>softfloat_flag_inexact</CODE><BR>
<CODE>softfloat_flag_underflow</CODE><BR>
<CODE>softfloat_flag_overflow</CODE><BR>
<CODE>softfloat_flag_infinite</CODE><BR>
<CODE>softfloat_flag_invalid</CODE>
</BLOCKQUOTE>
Variable <CODE>softfloat_exceptionFlags</CODE> is initialized to all zeros,
meaning no exceptions.
</P>
<P>
For some SoftFloat ports, <CODE>softfloat_exceptionFlags</CODE> may be
<I>per-thread</I> (declared <CODE>thread_local</CODE>), meaning that different
execution threads have their own separate instances of it.
</P>
<P>
An individual exception flag can be cleared with the statement
<BLOCKQUOTE>
<CODE>softfloat_exceptionFlags &= ~softfloat_flag_<<I>exception</I>>;</CODE>
</BLOCKQUOTE>
where <CODE><<I>exception</I>></CODE> is the appropriate name.
To raise a floating-point exception, function <CODE>softfloat_raiseFlags</CODE>
should normally be used.
</P>
<P>
When SoftFloat detects an exception other than <I>inexact</I>, it calls
<CODE>softfloat_raiseFlags</CODE>.
The default version of this function simply raises the corresponding exception
flags.
Particular ports of SoftFloat may support alternate behavior, such as exception
traps, by modifying the default <CODE>softfloat_raiseFlags</CODE>.
A program may also supply its own <CODE>softfloat_raiseFlags</CODE> function to
override the one from the SoftFloat library.
</P>
<P>
Because inexact results occur frequently under most circumstances (and thus are
hardly exceptional), SoftFloat does not ordinarily call
<CODE>softfloat_raiseFlags</CODE> for <I>inexact</I> exceptions.
It does always raise the <I>inexact</I> exception flag as required.
</P>
<H2>8. Function Details</H2>
<P>
In this section, <CODE><<I>float</I>></CODE> appears in function names as
a substitute for one of these abbreviations:
<BLOCKQUOTE>
<TABLE CELLSPACING=0 CELLPADDING=0>
<TR>
<TD><CODE>f16</CODE></TD>
<TD>indicates <CODE>float16_t</CODE>, passed by value</TD>
</TR>
<TR>
<TD><CODE>f32</CODE></TD>
<TD>indicates <CODE>float32_t</CODE>, passed by value</TD>
</TR>
<TR>
<TD><CODE>f64</CODE></TD>
<TD>indicates <CODE>float64_t</CODE>, passed by value</TD>
</TR>
<TR>
<TD><CODE>extF80M </CODE></TD>
<TD>indicates <CODE>extFloat80_t</CODE>, passed indirectly via pointers</TD>
</TR>
<TR>
<TD><CODE>extF80</CODE></TD>
<TD>indicates <CODE>extFloat80_t</CODE>, passed by value</TD>
</TR>
<TR>
<TD><CODE>f128M</CODE></TD>
<TD>indicates <CODE>float128_t</CODE>, passed indirectly via pointers</TD>
</TR>
<TR>
<TD><CODE>f128</CODE></TD>
<TD>indicates <CODE>float128_t</CODE>, passed by value</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
The circumstances under which values of floating-point types
<CODE>extFloat80_t</CODE> and <CODE>float128_t</CODE> may be passed either by
value or indirectly via pointers was discussed earlier in
<NOBR>section 4.5</NOBR>, <I>Conventions for Passing Arguments and Results</I>.
</P>
<H3>8.1. Conversions from Integer to Floating-Point</H3>
<P>
All conversions from a <NOBR>32-bit</NOBR> or <NOBR>64-bit</NOBR> integer,
signed or unsigned, to a floating-point format are supported.
Functions performing these conversions have these names:
<BLOCKQUOTE>
<CODE>ui32_to_<<I>float</I>></CODE><BR>
<CODE>ui64_to_<<I>float</I>></CODE><BR>
<CODE>i32_to_<<I>float</I>></CODE><BR>
<CODE>i64_to_<<I>float</I>></CODE>
</BLOCKQUOTE>
Conversions from <NOBR>32-bit</NOBR> integers to <NOBR>64-bit</NOBR>
double-precision and larger formats are always exact, and likewise conversions
from <NOBR>64-bit</NOBR> integers to <NOBR>80-bit</NOBR>
double-extended-precision and <NOBR>128-bit</NOBR> quadruple-precision are also
always exact.
</P>
<P>
Each conversion function takes one input of the appropriate type and generates
one output.
The following illustrates the signatures of these functions in cases when the
floating-point result is passed either by value or via pointers:
<BLOCKQUOTE>
<PRE>
float64_t i32_to_f64( int32_t <I>a</I> );
</PRE>
<PRE>
void i32_to_f128M( int32_t <I>a</I>, float128_t *<I>destPtr</I> );
</PRE>
</BLOCKQUOTE>
</P>
<H3>8.2. Conversions from Floating-Point to Integer</H3>
<P>
Conversions from a floating-point format to a <NOBR>32-bit</NOBR> or
<NOBR>64-bit</NOBR> integer, signed or unsigned, are supported with these
functions:
<BLOCKQUOTE>
<CODE><<I>float</I>>_to_ui32</CODE><BR>
<CODE><<I>float</I>>_to_ui64</CODE><BR>
<CODE><<I>float</I>>_to_i32</CODE><BR>
<CODE><<I>float</I>>_to_i64</CODE>
</BLOCKQUOTE>
The functions have signatures as follows, depending on whether the
floating-point input is passed by value or via pointers:
<BLOCKQUOTE>
<PRE>
int_fast32_t f64_to_i32( float64_t <I>a</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
</PRE>
<PRE>
int_fast32_t
f128M_to_i32( const float128_t *<I>aPtr</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
</PRE>
</BLOCKQUOTE>
</P>
<P>
The <CODE><I>roundingMode</I></CODE> argument specifies the rounding mode for
the conversion.
The variable that usually indicates rounding mode,
<CODE>softfloat_roundingMode</CODE>, is ignored.
Argument <CODE><I>exact</I></CODE> determines whether the <I>inexact</I>
exception flag is raised if the conversion is not exact.
If <CODE><I>exact</I></CODE> is <CODE>true</CODE>, the <I>inexact</I> flag may
be raised;
otherwise, it will not be, even if the conversion is inexact.
</P>
<P>
A conversion from floating-point to integer format raises the <I>invalid</I>
exception if the source value cannot be rounded to a representable integer of
the desired size (32 or 64 bits).
In such circumstances, the integer result returned is determined by the
particular port of SoftFloat, although typically this value will be either the
maximum or minimum value of the integer format.
The functions that convert to integer types never raise the floating-point
<I>overflow</I> exception.
</P>
<P>
Because languages such <NOBR>as C</NOBR> require that conversions to integers
be rounded toward zero, the following functions are provided for improved speed
and convenience:
<BLOCKQUOTE>
<CODE><<I>float</I>>_to_ui32_r_minMag</CODE><BR>
<CODE><<I>float</I>>_to_ui64_r_minMag</CODE><BR>
<CODE><<I>float</I>>_to_i32_r_minMag</CODE><BR>
<CODE><<I>float</I>>_to_i64_r_minMag</CODE>
</BLOCKQUOTE>
These functions round only toward zero (to minimum magnitude).
The signatures for these functions are the same as above without the redundant
<CODE><I>roundingMode</I></CODE> argument:
<BLOCKQUOTE>
<PRE>
int_fast32_t f64_to_i32_r_minMag( float64_t <I>a</I>, bool <I>exact</I> );
</PRE>
<PRE>
int_fast32_t f128M_to_i32_r_minMag( const float128_t *<I>aPtr</I>, bool <I>exact</I> );
</PRE>
</BLOCKQUOTE>
</P>
<H3>8.3. Conversions Among Floating-Point Types</H3>
<P>
Conversions between floating-point formats are done by functions with these
names:
<BLOCKQUOTE>
<CODE><<I>float</I>>_to_<<I>float</I>></CODE>
</BLOCKQUOTE>
All combinations of source and result type are supported where the source and
result are different formats.
There are four different styles of signature for these functions, depending on
whether the input and the output floating-point values are passed by value or
via pointers:
<BLOCKQUOTE>
<PRE>
float32_t f64_to_f32( float64_t <I>a</I> );
</PRE>
<PRE>
float32_t f128M_to_f32( const float128_t *<I>aPtr</I> );
</PRE>
<PRE>
void f32_to_f128M( float32_t <I>a</I>, float128_t *<I>destPtr</I> );
</PRE>
<PRE>
void extF80M_to_f128M( const extFloat80_t *<I>aPtr</I>, float128_t *<I>destPtr</I> );
</PRE>
</BLOCKQUOTE>
</P>
<P>
Conversions from a smaller to a larger floating-point format are always exact
and so require no rounding.
</P>
<H3>8.4. Basic Arithmetic Functions</H3>
<P>
The following basic arithmetic functions are provided:
<BLOCKQUOTE>
<CODE><<I>float</I>>_add</CODE><BR>
<CODE><<I>float</I>>_sub</CODE><BR>
<CODE><<I>float</I>>_mul</CODE><BR>
<CODE><<I>float</I>>_div</CODE><BR>
<CODE><<I>float</I>>_sqrt</CODE>
</BLOCKQUOTE>
Each floating-point operation takes two operands, except for <CODE>sqrt</CODE>
(square root) which takes only one.
The operands and result are all of the same floating-point format.
Signatures for these functions take the following forms:
<BLOCKQUOTE>
<PRE>
float64_t f64_add( float64_t <I>a</I>, float64_t <I>b</I> );
</PRE>
<PRE>
void
f128M_add(
const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I>, float128_t *<I>destPtr</I> );
</PRE>
<PRE>
float64_t f64_sqrt( float64_t <I>a</I> );
</PRE>
<PRE>
void f128M_sqrt( const float128_t *<I>aPtr</I>, float128_t *<I>destPtr</I> );
</PRE>
</BLOCKQUOTE>
When floating-point values are passed indirectly through pointers, arguments
<CODE><I>aPtr</I></CODE> and <CODE><I>bPtr</I></CODE> point to the input
operands, and the last argument, <CODE><I>destPtr</I></CODE>, points to the
location where the result is stored.
</P>
<P>
Rounding of the <NOBR>80-bit</NOBR> double-extended-precision
(<CODE>extFloat80_t</CODE>) functions is affected by variable
<CODE>extF80_roundingPrecision</CODE>, as explained earlier in
<NOBR>section 6.3</NOBR>,
<I>Rounding Precision for the <NOBR>80-Bit</NOBR> Extended Format</I>.
</P>
<H3>8.5. Fused Multiply-Add Functions</H3>
<P>
The 2008 version of the IEEE Floating-Point Standard defines a <I>fused
multiply-add</I> operation that does a combined multiplication and addition
with only a single rounding.
SoftFloat implements fused multiply-add with functions
<BLOCKQUOTE>
<CODE><<I>float</I>>_mulAdd</CODE>
</BLOCKQUOTE>
Unlike other operations, fused multiple-add is not supported for the
<NOBR>80-bit</NOBR> double-extended-precision format,
<CODE>extFloat80_t</CODE>.
</P>
<P>
Depending on whether floating-point values are passed by value or via pointers,
the fused multiply-add functions have signatures of these forms:
<BLOCKQUOTE>
<PRE>
float64_t f64_mulAdd( float64_t <I>a</I>, float64_t <I>b</I>, float64_t <I>c</I> );
</PRE>
<PRE>
void
f128M_mulAdd(
const float128_t *<I>aPtr</I>,
const float128_t *<I>bPtr</I>,
const float128_t *<I>cPtr</I>,
float128_t *<I>destPtr</I>
);
</PRE>
</BLOCKQUOTE>
The functions compute
<NOBR>(<CODE><I>a</I></CODE> × <CODE><I>b</I></CODE>)
+ <CODE><I>c</I></CODE></NOBR>
with a single rounding.
When floating-point values are passed indirectly through pointers, arguments
<CODE><I>aPtr</I></CODE>, <CODE><I>bPtr</I></CODE>, and
<CODE><I>cPtr</I></CODE> point to operands <CODE><I>a</I></CODE>,
<CODE><I>b</I></CODE>, and <CODE><I>c</I></CODE> respectively, and
<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
</P>
<P>
If one of the multiplication operands <CODE><I>a</I></CODE> and
<CODE><I>b</I></CODE> is infinite and the other is zero, these functions raise
the invalid exception even if operand <CODE><I>c</I></CODE> is a quiet NaN.
</P>
<H3>8.6. Remainder Functions</H3>
<P>
For each format, SoftFloat implements the remainder operation defined by the
IEEE Floating-Point Standard.
The remainder functions have names
<BLOCKQUOTE>
<CODE><<I>float</I>>_rem</CODE>
</BLOCKQUOTE>
Each remainder operation takes two floating-point operands of the same format
and returns a result in the same format.
Depending on whether floating-point values are passed by value or via pointers,
the remainder functions have signatures of these forms:
<BLOCKQUOTE>
<PRE>
float64_t f64_rem( float64_t <I>a</I>, float64_t <I>b</I> );
</PRE>
<PRE>
void
f128M_rem(
const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I>, float128_t *<I>destPtr</I> );
</PRE>
</BLOCKQUOTE>
When floating-point values are passed indirectly through pointers, arguments
<CODE><I>aPtr</I></CODE> and <CODE><I>bPtr</I></CODE> point to operands
<CODE><I>a</I></CODE> and <CODE><I>b</I></CODE> respectively, and
<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
</P>
<P>
The IEEE Standard remainder operation computes the value
<NOBR><CODE><I>a</I></CODE>
− <I>n</I> × <CODE><I>b</I></CODE></NOBR>,
where <I>n</I> is the integer closest to
<NOBR><CODE><I>a</I></CODE> ÷ <CODE><I>b</I></CODE></NOBR>.
If <NOBR><CODE><I>a</I></CODE> ÷ <CODE><I>b</I></CODE></NOBR> is exactly
halfway between two integers, <I>n</I> is the <EM>even</EM> integer closest to
<NOBR><CODE><I>a</I></CODE> ÷ <CODE><I>b</I></CODE></NOBR>.
The IEEE Standard’s remainder operation is always exact and so requires
no rounding.
</P>
<P>
Depending on the relative magnitudes of the operands, the remainder
functions can take considerably longer to execute than the other SoftFloat
functions.
This is an inherent characteristic of the remainder operation itself and is not
a flaw in the SoftFloat implementation.
</P>
<H3>8.7. Round-to-Integer Functions</H3>
<P>
For each format, SoftFloat implements the round-to-integer operation specified
by the IEEE Floating-Point Standard.
These functions are named
<BLOCKQUOTE>
<CODE><<I>float</I>>_roundToInt</CODE>
</BLOCKQUOTE>
Each round-to-integer operation takes a single floating-point operand.
This operand is rounded to an integer according to a specified rounding mode,
and the resulting integer value is returned in the same floating-point format.
(Note that the result is not an integer type.)
</P>
<P>
The signatures of the round-to-integer functions are similar to those for
conversions to an integer type:
<BLOCKQUOTE>
<PRE>
float64_t f64_roundToInt( float64_t <I>a</I>, uint_fast8_t <I>roundingMode</I>, bool <I>exact</I> );
</PRE>
<PRE>
void
f128M_roundToInt(
const float128_t *<I>aPtr</I>,
uint_fast8_t <I>roundingMode</I>,
bool <I>exact</I>,
float128_t *<I>destPtr</I>
);
</PRE>
</BLOCKQUOTE>
When floating-point values are passed indirectly through pointers,
<CODE><I>aPtr</I></CODE> points to the input operand and
<CODE><I>destPtr</I></CODE> points to the location where the result is stored.
</P>
<P>
The <CODE><I>roundingMode</I></CODE> argument specifies the rounding mode to
apply.
The variable that usually indicates rounding mode,
<CODE>softfloat_roundingMode</CODE>, is ignored.
Argument <CODE><I>exact</I></CODE> determines whether the <I>inexact</I>
exception flag is raised if the conversion is not exact.
If <CODE><I>exact</I></CODE> is <CODE>true</CODE>, the <I>inexact</I> flag may
be raised;
otherwise, it will not be, even if the conversion is inexact.
</P>
<H3>8.8. Comparison Functions</H3>
<P>
For each format, the following floating-point comparison functions are
provided:
<BLOCKQUOTE>
<CODE><<I>float</I>>_eq</CODE><BR>
<CODE><<I>float</I>>_le</CODE><BR>
<CODE><<I>float</I>>_lt</CODE>
</BLOCKQUOTE>
Each comparison takes two operands of the same type and returns a Boolean.
The abbreviation <CODE>eq</CODE> stands for “equal” (=);
<CODE>le</CODE> stands for “less than or equal” (≤);
and <CODE>lt</CODE> stands for “less than” (<).
Depending on whether the floating-point operands are passed by value or via
pointers, the comparison functions have signatures of these forms:
<BLOCKQUOTE>
<PRE>
bool f64_eq( float64_t <I>a</I>, float64_t <I>b</I> );
</PRE>
<PRE>
bool f128M_eq( const float128_t *<I>aPtr</I>, const float128_t *<I>bPtr</I> );
</PRE>
</BLOCKQUOTE>
</P>
<P>
The usual greater-than (>), greater-than-or-equal (≥), and not-equal
(≠) comparisons are easily obtained from the functions provided.
The not-equal function is just the logical complement of the equal function.
The greater-than-or-equal function is identical to the less-than-or-equal
function with the arguments in reverse order, and likewise the greater-than
function is identical to the less-than function with the arguments reversed.
</P>
<P>
The IEEE Floating-Point Standard specifies that the less-than-or-equal and
less-than comparisons by default raise the <I>invalid</I> exception if either
operand is any kind of NaN.
Equality comparisons, on the other hand, are defined by default to raise the
<I>invalid</I> exception only for signaling NaNs, not quiet NaNs.
For completeness, SoftFloat provides these complementary functions:
<BLOCKQUOTE>
<CODE><<I>float</I>>_eq_signaling</CODE><BR>
<CODE><<I>float</I>>_le_quiet</CODE><BR>
<CODE><<I>float</I>>_lt_quiet</CODE>
</BLOCKQUOTE>
The <CODE>signaling</CODE> equality comparisons are identical to the default
equality comparisons except that the <I>invalid</I> exception is raised for any
NaN input, not just for signaling NaNs.
Similarly, the <CODE>quiet</CODE> comparison functions are identical to their
default counterparts except that the <I>invalid</I> exception is not raised for
quiet NaNs.
</P>
<H3>8.9. Signaling NaN Test Functions</H3>
<P>
Functions for testing whether a floating-point value is a signaling NaN are
provided with these names:
<BLOCKQUOTE>
<CODE><<I>float</I>>_isSignalingNaN</CODE>
</BLOCKQUOTE>
The functions take one floating-point operand and return a Boolean indicating
whether the operand is a signaling NaN.
Accordingly, the functions have the forms
<BLOCKQUOTE>
<PRE>
bool f64_isSignalingNaN( float64_t <I>a</I> );
</PRE>
<PRE>
bool f128M_isSignalingNaN( const float128_t *<I>aPtr</I> );
</PRE>
</BLOCKQUOTE>
</P>
<H3>8.10. Raise-Exception Function</H3>
<P>
SoftFloat provides a single function for raising floating-point exceptions:
<BLOCKQUOTE>
<PRE>
void softfloat_raiseFlags( uint_fast8_t <I>exceptions</I> );
</PRE>
</BLOCKQUOTE>
The <CODE><I>exceptions</I></CODE> argument is a mask indicating the set of
exceptions to raise.
(See earlier section 7, <I>Exceptions and Exception Flags</I>.)
In addition to setting the specified exception flags in variable
<CODE>softfloat_exceptionFlags</CODE>, the <CODE>softfloat_raiseFlags</CODE>
function may cause a trap or abort appropriate for the current system.
</P>
<H2>9. Changes from SoftFloat <NOBR>Release 2</NOBR></H2>
<P>
Apart from a change in the legal use license, <NOBR>Release 3</NOBR> of
SoftFloat introduced numerous technical differences compared to earlier
releases.
</P>
<H3>9.1. Name Changes</H3>
<P>
The most obvious and pervasive difference compared to <NOBR>Release 2</NOBR>
is that the names of most functions and variables have changed, even when the
behavior has not.
First, the floating-point types, the mode variables, the exception flags
variable, the function to raise exceptions, and various associated constants
have been renamed as follows:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD>old name, Release 2:</TD>
<TD>new name, Release 3:</TD>
</TR>
<TR>
<TD><CODE>float32</CODE></TD>
<TD><CODE>float32_t</CODE></TD>
</TR>
<TR>
<TD><CODE>float64</CODE></TD>
<TD><CODE>float64_t</CODE></TD>
</TR>
<TR>
<TD><CODE>floatx80</CODE></TD>
<TD><CODE>extFloat80_t</CODE></TD>
</TR>
<TR>
<TD><CODE>float128</CODE></TD>
<TD><CODE>float128_t</CODE></TD>
</TR>
<TR>
<TD><CODE>float_rounding_mode</CODE></TD>
<TD><CODE>softfloat_roundingMode</CODE></TD>
</TR>
<TR>
<TD><CODE>float_round_nearest_even</CODE></TD>
<TD><CODE>softfloat_round_near_even</CODE></TD>
</TR>
<TR>
<TD><CODE>float_round_to_zero</CODE></TD>
<TD><CODE>softfloat_round_minMag</CODE></TD>
</TR>
<TR>
<TD><CODE>float_round_down</CODE></TD>
<TD><CODE>softfloat_round_min</CODE></TD>
</TR>
<TR>
<TD><CODE>float_round_up</CODE></TD>
<TD><CODE>softfloat_round_max</CODE></TD>
</TR>
<TR>
<TD><CODE>float_detect_tininess</CODE></TD>
<TD><CODE>softfloat_detectTininess</CODE></TD>
</TR>
<TR>
<TD><CODE>float_tininess_before_rounding </CODE></TD>
<TD><CODE>softfloat_tininess_beforeRounding</CODE></TD>
</TR>
<TR>
<TD><CODE>float_tininess_after_rounding</CODE></TD>
<TD><CODE>softfloat_tininess_afterRounding</CODE></TD>
</TR>
<TR>
<TD><CODE>floatx80_rounding_precision</CODE></TD>
<TD><CODE>extF80_roundingPrecision</CODE></TD>
</TR>
<TR>
<TD><CODE>float_exception_flags</CODE></TD>
<TD><CODE>softfloat_exceptionFlags</CODE></TD>
</TR>
<TR>
<TD><CODE>float_flag_inexact</CODE></TD>
<TD><CODE>softfloat_flag_inexact</CODE></TD>
</TR>
<TR>
<TD><CODE>float_flag_underflow</CODE></TD>
<TD><CODE>softfloat_flag_underflow</CODE></TD>
</TR>
<TR>
<TD><CODE>float_flag_overflow</CODE></TD>
<TD><CODE>softfloat_flag_overflow</CODE></TD>
</TR>
<TR>
<TD><CODE>float_flag_divbyzero</CODE></TD>
<TD><CODE>softfloat_flag_infinite</CODE></TD>
</TR>
<TR>
<TD><CODE>float_flag_invalid</CODE></TD>
<TD><CODE>softfloat_flag_invalid</CODE></TD>
</TR>
<TR>
<TD><CODE>float_raise</CODE></TD>
<TD><CODE>softfloat_raiseFlags</CODE></TD>
</TR>
</TABLE>
</BLOCKQUOTE>
</P>
<P>
Furthermore, <NOBR>Release 3</NOBR> adopted the following new abbreviations for
function names:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD>used in names in Release 2:<CODE> </CODE></TD>
<TD>used in names in Release 3:</TD>
</TR>
<TR> <TD><CODE>int32</CODE></TD> <TD><CODE>i32</CODE></TD> </TR>
<TR> <TD><CODE>int64</CODE></TD> <TD><CODE>i64</CODE></TD> </TR>
<TR> <TD><CODE>float32</CODE></TD> <TD><CODE>f32</CODE></TD> </TR>
<TR> <TD><CODE>float64</CODE></TD> <TD><CODE>f64</CODE></TD> </TR>
<TR> <TD><CODE>floatx80</CODE></TD> <TD><CODE>extF80</CODE></TD> </TR>
<TR> <TD><CODE>float128</CODE></TD> <TD><CODE>f128</CODE></TD> </TR>
</TABLE>
</BLOCKQUOTE>
Thus, for example, the function to add two <NOBR>32-bit</NOBR> floating-point
numbers, previously called <CODE>float32_add</CODE> in <NOBR>Release 2</NOBR>,
is now <CODE>f32_add</CODE>.
Lastly, there have been a few other changes to function names:
<BLOCKQUOTE>
<TABLE>
<TR>
<TD>used in names in Release 2:<CODE> </CODE></TD>
<TD>used in names in Release 3:<CODE> </CODE></TD>
<TD>relevant functions:</TD>
</TR>
<TR>
<TD><CODE>_round_to_zero</CODE></TD>
<TD><CODE>_r_minMag</CODE></TD>
<TD>conversions from floating-point to integer (<NOBR>section 8.2</NOBR>)</TD>
</TR>
<TR>
<TD><CODE>round_to_int</CODE></TD>
<TD><CODE>roundToInt</CODE></TD>
<TD>round-to-integer functions (<NOBR>section 8.7</NOBR>)</TD>
</TR>
<TR>
<TD><CODE>is_signaling_nan </CODE></TD>
<TD><CODE>isSignalingNaN</CODE></TD>
<TD>signaling NaN test functions (<NOBR>section 8.9</NOBR>)</TD>
</TR>
</TABLE>
</BLOCKQUOTE>
</P>
<H3>9.2. Changes to Function Arguments</H3>
<P>
Besides simple name changes, some operations were given a different interface
in <NOBR>Release 3</NOBR> than they had in <NOBR>Release 2</NOBR>:
<UL>
<LI>
<P>
Since <NOBR>Release 3</NOBR>, integer arguments and results of functions have
standard types from header <CODE><stdint.h></CODE>, such as
<CODE>uint32_t</CODE>, whereas previously their types could be defined
differently for each port of SoftFloat, usually using traditional C types such
as <CODE>unsigned</CODE> <CODE>int</CODE>.
Likewise, functions in <NOBR>Release 3</NOBR> and later pass Booleans as
standard type <CODE>bool</CODE> from <CODE><stdbool.h></CODE>, whereas
previously these were again passed as a port-specific type (usually
<CODE>int</CODE>).
</P>
<LI>
<P>
As explained earlier in <NOBR>section 4.5</NOBR>, <I>Conventions for Passing
Arguments and Results</I>, SoftFloat functions in <NOBR>Release 3</NOBR> and
later may pass <NOBR>80-bit</NOBR> and <NOBR>128-bit</NOBR> floating-point
values through pointers, meaning that functions take pointer arguments and then
read or write floating-point values at the locations indicated by the pointers.
In <NOBR>Release 2</NOBR>, floating-point arguments and results were always
passed by value, regardless of their size.
</P>
<LI>
<P>
Functions that round to an integer have additional
<CODE><I>roundingMode</I></CODE> and <CODE><I>exact</I></CODE> arguments that
they did not have in <NOBR>Release 2</NOBR>.
Refer to sections 8.2 <NOBR>and 8.7</NOBR> for descriptions of these functions
since <NOBR>Release 3</NOBR>.
For <NOBR>Release 2</NOBR>, the rounding mode, when needed, was taken from the
same global variable that affects the basic arithmetic operations (now called
<CODE>softfloat_roundingMode</CODE> but previously known as
<CODE>float_rounding_mode</CODE>).
Also, for <NOBR>Release 2</NOBR>, if the original floating-point input was not
an exact integer value, and if the <I>invalid</I> exception was not raised by
the function, the <I>inexact</I> exception was always raised.
<NOBR>Release 2</NOBR> had no option to suppress raising <I>inexact</I> in this
case.
Applications using SoftFloat <NOBR>Release 3</NOBR> or later can get the same
effect as <NOBR>Release 2</NOBR> by passing variable
<CODE>softfloat_roundingMode</CODE> for argument
<CODE><I>roundingMode</I></CODE> and <CODE>true</CODE> for argument
<CODE><I>exact</I></CODE>.
</P>
</UL>
</P>
<H3>9.3. Added Capabilities</H3>
<P>
With <NOBR>Release 3</NOBR>, some new features have been added that were not
present in <NOBR>Release 2</NOBR>:
<UL>
<LI>
<P>
A port of SoftFloat can now define any of the floating-point types
<CODE>float32_t</CODE>, <CODE>float64_t</CODE>, <CODE>extFloat80_t</CODE>, and
<CODE>float128_t</CODE> as aliases for C’s standard floating-point types
<CODE>float</CODE>, <CODE>double</CODE>, and <CODE>long</CODE>
<CODE>double</CODE>, using either <CODE>#define</CODE> or <CODE>typedef</CODE>.
This potential convenience was not supported under <NOBR>Release 2</NOBR>.
</P>
<P>
(Note, however, that there may be a performance cost to defining
SoftFloat’s floating-point types this way, depending on the platform and
the applications using SoftFloat.
Ports of SoftFloat may choose to forgo the convenience in favor of better
speed.)
</P>
<P>
<LI>
As of <NOBR>Release 3b</NOBR>, <NOBR>16-bit</NOBR> half-precision,
<CODE>float16_t</CODE>, is supported.
</P>
<P>
<LI>
Functions have been added for converting between the floating-point types and
unsigned integers.
<NOBR>Release 2</NOBR> supported only signed integers, not unsigned.
</P>
<P>
<LI>
Fused multiply-add functions have been added for all floating-point formats
except <NOBR>80-bit</NOBR> double-extended-precision,
<CODE>extFloat80_t</CODE>.
</P>
<P>
<LI>
New rounding modes are supported:
<CODE>softfloat_round_near_maxMag</CODE> (round to nearest, with ties to
maximum magnitude, away from zero), and, as of <NOBR>Release 3c</NOBR>,
optional <CODE>softfloat_round_odd</CODE> (round to odd, also known as
jamming).
</P>
</UL>
</P>
<H3>9.4. Better Compatibility with the C Language</H3>
<P>
<NOBR>Release 3</NOBR> of SoftFloat was written to conform better to the ISO C
Standard’s rules for portability.
For example, older releases of SoftFloat employed type conversions in ways
that, while commonly practiced, are not fully defined by the C Standard.
Such problematic type conversions have generally been replaced by the use of
unions, the behavior around which is more strictly regulated these days.
</P>
<H3>9.5. New Organization as a Library</H3>
<P>
Starting with <NOBR>Release 3</NOBR>, SoftFloat now builds as a library.
Previously, SoftFloat compiled into a single, monolithic object file containing
all the SoftFloat functions, with the consequence that a program linking with
SoftFloat would get every SoftFloat function in its binary file even if only a
few functions were actually used.
With SoftFloat in the form of a library, a program that is linked by a standard
linker will include only those functions of SoftFloat that it needs and no
others.
</P>
<H3>9.6. Optimization Gains (and Losses)</H3>
<P>
Individual SoftFloat functions have been variously improved in
<NOBR>Release 3</NOBR> compared to earlier releases.
In particular, better, faster algorithms have been deployed for the operations
of division, square root, and remainder.
For functions operating on the larger <NOBR>80-bit</NOBR> and
<NOBR>128-bit</NOBR> formats, <CODE>extFloat80_t</CODE> and
<CODE>float128_t</CODE>, code size has also generally been reduced.
</P>
<P>
However, because <NOBR>Release 2</NOBR> compiled all of SoftFloat together as a
single object file, compilers could make optimizations across function calls
when one SoftFloat function calls another.
Now that the functions of SoftFloat are compiled separately and only afterward
linked together into a program, there is not usually the same opportunity to
optimize across function calls.
Some loss of speed has been observed due to this change.
</P>
<H2>10. Future Directions</H2>
<P>
The following improvements are anticipated for future releases of SoftFloat:
<UL>
<LI>
more functions from the 2008 version of the IEEE Floating-Point Standard;
<LI>
consistent, defined behavior for non-canonical representations of extended
format <CODE>extFloat80_t</CODE> (discussed in <NOBR>section 4.4</NOBR>,
<I>Non-canonical Representations in <CODE>extFloat80_t</CODE></I>).
</UL>
</P>
<H2>11. Contact Information</H2>
<P>
At the time of this writing, the most up-to-date information about SoftFloat
and the latest release can be found at the Web page
<A HREF="path_to_url"><NOBR><CODE>path_to_url
</P>
</BODY>
``` | /content/code_sandbox/src/cpu/softfloat3e/doc/SoftFloat.html | html | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 15,448 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VIA VT82C49X chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct vt82c49x_t {
uint8_t has_ide;
uint8_t index;
uint8_t regs[256];
smram_t *smram_smm;
smram_t *smram_low;
smram_t *smram_high;
} vt82c49x_t;
#ifdef ENABLE_VT82C49X_LOG
int vt82c49x_do_log = ENABLE_VT82C49X_LOG;
static void
vt82c49x_log(const char *fmt, ...)
{
va_list ap;
if (vt82c49x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define vt82c49x_log(fmt, ...)
#endif
static void
vt82c49x_recalc(vt82c49x_t *dev)
{
int relocate;
uint8_t reg;
uint8_t bit;
uint32_t base;
uint32_t state;
uint32_t shadow_bitmap = 0x00000000;
relocate = (dev->regs[0x33] >> 2) & 0x03;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 14);
reg = 0x30 + (i >> 2);
bit = (i & 3) << 1;
if ((base >= 0xc0000) && (base <= 0xc7fff)) {
if (dev->regs[0x40] & 0x80)
state = MEM_WRITE_DISABLED;
else if ((dev->regs[reg]) & (1 << bit))
state = MEM_WRITE_INTERNAL;
else
state = (dev->regs[0x33] & 0x40) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL;
if ((dev->regs[reg]) & (1 << (bit + 1)))
state |= MEM_READ_INTERNAL;
else
state |= (dev->regs[0x33] & 0x40) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL;
}
if ((base >= 0xc8000) && (base <= 0xcffff)) {
if ((dev->regs[reg]) & (1 << bit))
state = MEM_WRITE_INTERNAL;
else
state = (dev->regs[0x33] & 0x80) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL;
if ((dev->regs[reg]) & (1 << (bit + 1)))
state |= MEM_READ_INTERNAL;
else
state |= (dev->regs[0x33] & 0x80) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL;
} else {
state = ((dev->regs[reg]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
state |= ((dev->regs[reg]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
}
vt82c49x_log("(%02X=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n",
reg, dev->regs[reg], bit, base, base + 0x3fff,
((dev->regs[reg]) & (1 << bit)) ? "en" : "dis", ((dev->regs[reg]) & (1 << (bit + 1))) ? "en" : "dis");
if ((dev->regs[reg]) & (1 << bit))
shadow_bitmap |= (1 << i);
if ((dev->regs[reg]) & (1 << (bit + 1)))
shadow_bitmap |= (1 << (i + 16));
mem_set_mem_state_both(base, 0x4000, state);
}
for (uint8_t i = 0; i < 4; i++) {
base = 0xe0000 + (i << 15);
bit = 6 - (i & 2);
if ((base >= 0xe0000) && (base <= 0xe7fff)) {
if (dev->regs[0x40] & 0x20)
state = MEM_WRITE_DISABLED;
else if ((dev->regs[0x32]) & (1 << bit))
state = MEM_WRITE_INTERNAL;
else
state = (dev->regs[0x33] & 0x10) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL;
if ((dev->regs[0x32]) & (1 << (bit + 1)))
state |= MEM_READ_INTERNAL;
else
state |= (dev->regs[0x33] & 0x10) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL;
} else if ((base >= 0xe8000) && (base <= 0xeffff)) {
if (dev->regs[0x40] & 0x20)
state = MEM_WRITE_DISABLED;
else if ((dev->regs[0x32]) & (1 << bit))
state = MEM_WRITE_INTERNAL;
else
state = (dev->regs[0x33] & 0x20) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL;
if ((dev->regs[0x32]) & (1 << (bit + 1)))
state |= MEM_READ_INTERNAL;
else
state |= (dev->regs[0x33] & 0x20) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL;
} else {
if (dev->regs[0x40] & 0x40)
state = MEM_WRITE_DISABLED;
else if ((dev->regs[0x32]) & (1 << bit))
state = ((dev->regs[0x32]) & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
state |= ((dev->regs[0x32]) & (1 << (bit + 1))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
}
vt82c49x_log("(32=%02X, %i) Setting %08X-%08X to: write %sabled, read %sabled\n",
dev->regs[0x32], bit, base, base + 0x7fff,
((dev->regs[0x32]) & (1 << bit)) ? "en" : "dis", ((dev->regs[0x32]) & (1 << (bit + 1))) ? "en" : "dis");
if ((dev->regs[0x32]) & (1 << bit)) {
shadow_bitmap |= (0xf << ((i << 2) + 8));
shadowbios_write |= 1;
}
if ((dev->regs[0x32]) & (1 << (bit + 1))) {
shadow_bitmap |= (0xf << ((i << 2) + 24));
shadowbios |= 1;
}
mem_set_mem_state_both(base, 0x8000, state);
}
vt82c49x_log("Shadow bitmap: %08X\n", shadow_bitmap);
mem_remap_top(0);
switch (relocate) {
case 0x02:
if (!(shadow_bitmap & 0xfff0fff0))
mem_remap_top(256);
break;
case 0x03:
if (!shadow_bitmap)
mem_remap_top(384);
break;
default:
break;
}
}
static void
vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
{
vt82c49x_t *dev = (vt82c49x_t *) priv;
uint8_t valxor;
switch (addr) {
case 0xa8:
dev->index = val;
break;
case 0xa9:
valxor = (val ^ dev->regs[dev->index]);
if (dev->index == 0x55)
dev->regs[dev->index] &= ~val;
else
dev->regs[dev->index] = val;
vt82c49x_log("dev->regs[0x%02x] = %02x\n", dev->index, val);
switch (dev->index) {
/* Wait States */
case 0x03:
cpu_update_waitstates();
break;
/* Shadow RAM and top of RAM relocation */
case 0x30:
case 0x31:
case 0x32:
case 0x33:
case 0x40:
vt82c49x_recalc(dev);
break;
/* External Cache Enable(Based on the 486-VC-HD BIOS) */
case 0x50:
cpu_cache_ext_enabled = (val & 0x84);
break;
/* Software SMI */
case 0x54:
if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) {
if (dev->regs[0x5b] & 0x20)
smi_raise();
else
picint(1 << 15);
dev->regs[0x55] = 0x01;
}
break;
/* SMRAM */
case 0x5b:
smram_disable_all();
if (val & 0x80) {
smram_enable(dev->smram_smm, (val & 0x40) ? 0x00060000 : 0x00030000, 0x000a0000, 0x00020000,
0, (val & 0x10));
smram_enable(dev->smram_high, 0x000a0000, 0x000a0000, 0x00020000,
(val & 0x08), (val & 0x08));
smram_enable(dev->smram_low, 0x00030000, 0x000a0000, 0x00020000,
(val & 0x02), 0);
}
break;
/* Edge/Level IRQ Control */
case 0x62:
case 0x63:
if (dev->index == 0x63)
pic_elcr_write(dev->index, val & 0xde, &pic2);
else {
pic_elcr_write(dev->index, val & 0xf8, &pic);
pic_elcr_set_enabled(val & 0x01);
}
break;
/* Local Bus IDE Controller */
case 0x71:
if (dev->has_ide) {
ide_pri_disable();
ide_set_base(0, (val & 0x40) ? 0x170 : 0x1f0);
ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6);
if (val & 0x01)
ide_pri_enable();
vt82c49x_log("VT82C496 IDE now %sabled as %sary\n", (val & 0x01) ? "en" : "dis",
(val & 0x40) ? "second" : "prim");
}
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
vt82c49x_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
const vt82c49x_t *dev = (vt82c49x_t *) priv;
switch (addr) {
case 0xa9:
/* Register 64h is jumper readout. */
if (dev->index == 0x64)
ret = 0xff;
else if (dev->index == 0x63)
ret = pic_elcr_read(dev->index, &pic2) | (dev->regs[dev->index] & 0x01);
else if (dev->index == 0x62)
ret = pic_elcr_read(dev->index, &pic) | (dev->regs[dev->index] & 0x07);
else if (dev->index < 0x80)
ret = dev->regs[dev->index];
break;
default:
break;
}
return ret;
}
static void
vt82c49x_reset(void *priv)
{
for (uint16_t i = 0; i < 256; i++)
vt82c49x_write(i, 0x00, priv);
}
static void
vt82c49x_close(void *priv)
{
vt82c49x_t *dev = (vt82c49x_t *) priv;
smram_del(dev->smram_high);
smram_del(dev->smram_low);
smram_del(dev->smram_smm);
free(dev);
}
static void *
vt82c49x_init(const device_t *info)
{
vt82c49x_t *dev = (vt82c49x_t *) malloc(sizeof(vt82c49x_t));
memset(dev, 0x00, sizeof(vt82c49x_t));
dev->smram_smm = smram_add();
dev->smram_low = smram_add();
dev->smram_high = smram_add();
dev->has_ide = info->local & 1;
if (dev->has_ide) {
device_add(&ide_vlb_2ch_device);
ide_sec_disable();
}
device_add(&port_92_device);
io_sethandler(0x0a8, 0x0002, vt82c49x_read, NULL, NULL, vt82c49x_write, NULL, NULL, dev);
pic_elcr_io_handler(0);
pic_elcr_set_enabled(1);
vt82c49x_recalc(dev);
return dev;
}
const device_t via_vt82c49x_device = {
.name = "VIA VT82C49X",
.internal_name = "via_vt82c49x",
.flags = 0,
.local = 0,
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c49x_pci_device = {
.name = "VIA VT82C49X PCI",
.internal_name = "via_vt82c49x_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = vt82c49x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c49x_ide_device = {
.name = "VIA VT82C49X (With IDE)",
.internal_name = "via_vt82c49x_ide",
.flags = 0,
.local = 1,
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c49x_pci_ide_device = {
.name = "VIA VT82C49X PCI (With IDE)",
.internal_name = "via_vt82c49x_pci_ide",
.flags = DEVICE_PCI,
.local = 1,
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = vt82c49x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/via_vt82c49x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,846 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Chips&Technology's SCAT (82C235) chipset.
*
* Re-worked version based on the 82C235 datasheet and errata.
*
*
*
* Authors: Original by GreatPsycho for PCem.
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include "x86.h"
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/port_92.h>
#include <86box/rom.h>
#include <86box/chipset.h>
#define SCAT_DMA_WAIT_STATE_CONTROL 0x01
#define SCAT_VERSION 0x40
#define SCAT_CLOCK_CONTROL 0x41
#define SCAT_PERIPHERAL_CONTROL 0x44
#define SCAT_MISCELLANEOUS_STATUS 0x45
#define SCAT_POWER_MANAGEMENT 0x46
#define SCAT_ROM_ENABLE 0x48
#define SCAT_RAM_WRITE_PROTECT 0x49
#define SCAT_SHADOW_RAM_ENABLE_1 0x4A
#define SCAT_SHADOW_RAM_ENABLE_2 0x4B
#define SCAT_SHADOW_RAM_ENABLE_3 0x4C
#define SCAT_DRAM_CONFIGURATION 0x4D
#define SCAT_EXTENDED_BOUNDARY 0x4E
#define SCAT_EMS_CONTROL 0x4F
#define SCATSX_LAPTOP_FEATURES 0x60
#define SCATSX_FAST_VIDEO_CONTROL 0x61
#define SCATSX_FAST_VIDEORAM_ENABLE 0x62
#define SCATSX_HIGH_PERFORMANCE_REFRESH 0x63
#define SCATSX_CAS_TIMING_FOR_DMA 0x64
typedef struct ems_page_t {
uint8_t valid;
uint8_t pad;
uint8_t regs_2x8;
uint8_t regs_2x9;
struct scat_t *scat;
} ems_page_t;
typedef struct scat_t {
uint8_t max_reg;
uint8_t reg_2xA;
uint8_t regs[256];
uint32_t xms_bound;
int type;
int indx;
int external_is_RAS;
ems_page_t null_page;
ems_page_t page[32];
mem_mapping_t low_mapping[32];
mem_mapping_t remap_mapping[6];
mem_mapping_t efff_mapping[44];
mem_mapping_t ems_mapping[32];
} scat_t;
static const uint8_t max_map[32] = {
// clang-format off
0, 1, 1, 1, 2, 3, 4, 8,
4, 8, 12, 16, 20, 24, 28, 32,
0, 5, 9, 13, 6, 10, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
// clang-format om
};
static const uint8_t max_map_sx[32] = {
// clang-format off
0, 1, 2, 1, 3, 4, 6, 10,
5, 9, 13, 4, 8, 12, 16, 14,
18, 22, 26, 20, 24, 28, 32, 18,
20, 32, 0, 0, 0, 0, 0, 0
// clang-format om
};
static const uint8_t scatsx_external_is_RAS[33] = {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 0, 1, 1,
0, 0, 0, 0, 0, 0, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
0
};
static uint8_t scat_in(uint16_t port, void *priv);
static void scat_out(uint16_t port, uint8_t val, void *priv);
static void
shadow_state_update(scat_t *dev)
{
int val;
uint32_t base;
uint32_t bit;
uint32_t romcs;
uint32_t shflags = 0;
shadowbios = shadowbios_write = 0;
for (uint8_t i = 0; i < 24; i++) {
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) < 4)
val = 0;
else
val = (dev->regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1;
base = 0xa0000 + (i << 14);
bit = (base - 0xc0000) >> 15;
romcs = 0;
if (base >= 0xc0000)
romcs = dev->regs[SCAT_ROM_ENABLE] & (1 << bit);
if (base >= 0xe0000) {
shadowbios |= val;
shadowbios_write |= val;
}
shflags = val ? MEM_READ_INTERNAL : (romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL);
shflags |= (val ? MEM_WRITE_INTERNAL : (romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL));
mem_set_mem_state(base, 0x4000, shflags);
}
flushmmucache();
}
static void
set_xms_bound(scat_t *dev, uint8_t val)
{
uint32_t xms_max = ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && ((val & 0x10) != 0)) || (dev->regs[SCAT_VERSION] >= 4) ? 0xfe0000 : 0xfc0000;
switch (val & 0x0f) {
case 1:
dev->xms_bound = 0x100000;
break;
case 2:
dev->xms_bound = 0x140000;
break;
case 3:
dev->xms_bound = 0x180000;
break;
case 4:
dev->xms_bound = 0x200000;
break;
case 5:
dev->xms_bound = 0x300000;
break;
case 6:
dev->xms_bound = 0x400000;
break;
case 7:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x600000 : 0x500000;
break;
case 8:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x800000 : 0x700000;
break;
case 9:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xa00000 : 0x800000;
break;
case 10:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xc00000 : 0x900000;
break;
case 11:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0xe00000 : 0xa00000;
break;
case 12:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xb00000;
break;
case 13:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xc00000;
break;
case 14:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xd00000;
break;
case 15:
dev->xms_bound = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? xms_max : 0xf00000;
break;
default:
dev->xms_bound = xms_max;
break;
}
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (val & 0x40) == 0 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) {
if ((val & 0x0f) == 0 || dev->xms_bound > 0x160000)
dev->xms_bound = 0x160000;
if (dev->xms_bound > 0x100000)
mem_set_mem_state(0x100000, dev->xms_bound - 0x100000,
MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if (dev->xms_bound < 0x160000)
mem_set_mem_state(dev->xms_bound, 0x160000 - dev->xms_bound,
MEM_READ_EXTANY | MEM_WRITE_EXTANY);
} else {
if (dev->xms_bound > xms_max)
dev->xms_bound = xms_max;
if (dev->xms_bound > 0x100000)
mem_set_mem_state(0x100000, dev->xms_bound - 0x100000,
MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if (dev->xms_bound < ((uint32_t) mem_size << 10))
mem_set_mem_state(dev->xms_bound, (mem_size << 10) - dev->xms_bound,
MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000,
((dev->regs[SCAT_VERSION] & 0xf0) != 0 && ((val & 0x10) != 0)) || (dev->regs[SCAT_VERSION] >= 4) ? 0x60000 : 0x40000);
if (dev->regs[SCAT_VERSION] & 0xf0) {
for (uint8_t i = 0; i < 8; i++) {
if (val & 0x10)
mem_mapping_disable(&bios_high_mapping);
else
mem_mapping_enable(&bios_high_mapping);
}
}
}
static uint32_t
get_addr(scat_t *dev, uint32_t addr, ems_page_t *p)
{
#if 1
int nbanks_2048k;
int nbanks_512k;
uint32_t addr2;
int nbank;
#else
uint32_t nbanks_2048k, nbanks_512k, addr2, nbank;
#endif
if (p && p->valid && (dev->regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
addr = (addr & 0x3fff) | (((p->regs_2x9 & 3) << 8) | p->regs_2x8) << 14;
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
switch ((dev->regs[SCAT_EXTENDED_BOUNDARY] & ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 0x40 : 0)) | (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f)) {
case 0x41:
nbank = addr >> 19;
if (nbank < 4)
nbank = 1;
else if (nbank == 4)
nbank = 0;
else
nbank -= 3;
break;
case 0x42:
nbank = addr >> 19;
if (nbank < 8)
nbank = 1 + (nbank >> 2);
else if (nbank == 8)
nbank = 0;
else
nbank -= 6;
break;
case 0x43:
nbank = addr >> 19;
if (nbank < 12)
nbank = 1 + (nbank >> 2);
else if (nbank == 12)
nbank = 0;
else
nbank -= 9;
break;
case 0x44:
nbank = addr >> 19;
if (nbank < 4)
nbank = 2;
else if (nbank < 6)
nbank -= 4;
else
nbank -= 3;
break;
case 0x45:
nbank = addr >> 19;
if (nbank < 8)
nbank = 2 + (nbank >> 2);
else if (nbank < 10)
nbank -= 8;
else
nbank -= 6;
break;
default:
nbank = addr >> (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8 && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) ? 19 : 21);
break;
}
nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3;
if ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3 && nbank == 2 && (addr & 0x7ffff) < 0x60000 && mem_size > 640) {
nbank = 1;
addr ^= 0x70000;
}
if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) {
if (nbank == 3)
nbank = 7;
else
return 0xffffffff;
} else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) {
switch (nbank) {
case 7:
nbank = 3;
break;
/* Note - In the following cases, the chipset accesses multiple memory banks
at the same time, so it's impossible to predict which memory bank
is actually accessed. */
case 5:
case 1:
nbank = 1;
break;
case 3:
nbank = 2;
break;
default:
nbank = 0;
break;
}
}
if ((dev->regs[SCAT_VERSION] & 0x0f) > 3 && (mem_size > 2048) && (mem_size & 1536)) {
if ((mem_size & 1536) == 512) {
if (nbank == 0)
addr &= 0x7ffff;
else
addr = 0x80000 + ((addr & 0x1fffff) | ((nbank - 1) << 21));
} else {
if (nbank < 2)
addr = (addr & 0x7ffff) | (nbank << 19);
else
addr = 0x100000 + ((addr & 0x1fffff) | ((nbank - 2) << 21));
}
} else {
if (mem_size <= ((dev->regs[SCAT_VERSION] & 0x0f) > 3 ? 2048 : 4096) && (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) < 8) || dev->external_is_RAS)) {
nbanks_2048k = 0;
nbanks_512k = mem_size >> 9;
} else {
nbanks_2048k = mem_size >> 11;
nbanks_512k = (mem_size & 1536) >> 9;
}
if (nbank < nbanks_2048k || (nbanks_2048k > 0 && nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7))) {
addr &= 0x1fffff;
addr |= (nbank << 21);
} else if (nbank < nbanks_2048k + nbanks_512k || nbank >= nbanks_2048k + nbanks_512k + ((mem_size & 511) >> 7)) {
addr &= 0x7ffff;
addr |= (nbanks_2048k << 21) | ((nbank - nbanks_2048k) << 19);
} else {
addr &= 0x1ffff;
addr |= (nbanks_2048k << 21) | (nbanks_512k << 19) | ((nbank - nbanks_2048k - nbanks_512k) << 17);
}
}
} else {
switch (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) {
case 0x02:
case 0x04:
nbank = addr >> 19;
if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else
addr2 = addr >> 10;
break;
case 0x03:
nbank = addr >> 19;
if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) == 2 && (addr & 0x7ffff) < 0x60000) {
addr ^= 0x1f0000;
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else
addr2 = addr >> 10;
break;
case 0x05:
nbank = addr >> 19;
if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) {
nbank = (addr >> 10) & 3;
addr2 = addr >> 12;
} else
addr2 = addr >> 10;
break;
case 0x06:
nbank = addr >> 19;
if (nbank < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else {
nbank = 2 + ((addr - 0x100000) >> 21);
addr2 = (addr - 0x100000) >> 11;
}
break;
case 0x07:
case 0x0f:
nbank = addr >> 19;
if (nbank < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else if (nbank < 10) {
nbank = 2 + (((addr - 0x100000) >> 11) & 1);
addr2 = (addr - 0x100000) >> 12;
} else {
nbank = 4 + ((addr - 0x500000) >> 21);
addr2 = (addr - 0x500000) >> 11;
}
break;
case 0x08:
nbank = addr >> 19;
if (nbank < 4) {
nbank = 1;
addr2 = addr >> 11;
} else if (nbank == 4) {
nbank = 0;
addr2 = addr >> 10;
} else {
nbank -= 3;
addr2 = addr >> 10;
}
break;
case 0x09:
nbank = addr >> 19;
if (nbank < 8) {
nbank = 1 + ((addr >> 11) & 1);
addr2 = addr >> 12;
} else if (nbank == 8) {
nbank = 0;
addr2 = addr >> 10;
} else {
nbank -= 6;
addr2 = addr >> 10;
}
break;
case 0x0a:
nbank = addr >> 19;
if (nbank < 8) {
nbank = 1 + ((addr >> 11) & 1);
addr2 = addr >> 12;
} else if (nbank < 12) {
nbank = 3;
addr2 = addr >> 11;
} else if (nbank == 12) {
nbank = 0;
addr2 = addr >> 10;
} else {
nbank -= 9;
addr2 = addr >> 10;
}
break;
case 0x0b:
nbank = addr >> 21;
addr2 = addr >> 11;
break;
case 0x0c:
case 0x0d:
nbank = addr >> 21;
if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 2) {
nbank = (addr >> 11) & 1;
addr2 = addr >> 12;
} else
addr2 = addr >> 11;
break;
case 0x0e:
case 0x13:
nbank = addr >> 21;
if ((nbank & (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80 ? 7 : 3)) < 4) {
nbank = (addr >> 11) & 3;
addr2 = addr >> 13;
} else
addr2 = addr >> 11;
break;
case 0x10:
case 0x11:
nbank = addr >> 19;
if (nbank < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else if (nbank < 10) {
nbank = 2 + (((addr - 0x100000) >> 11) & 1);
addr2 = (addr - 0x100000) >> 12;
} else if (nbank < 18) {
nbank = 4 + (((addr - 0x500000) >> 11) & 1);
addr2 = (addr - 0x500000) >> 12;
} else {
nbank = 6 + ((addr - 0x900000) >> 21);
addr2 = (addr - 0x900000) >> 11;
}
break;
case 0x12:
nbank = addr >> 19;
if (nbank < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else if (nbank < 10) {
nbank = 2 + (((addr - 0x100000) >> 11) & 1);
addr2 = (addr - 0x100000) >> 12;
} else {
nbank = 4 + (((addr - 0x500000) >> 11) & 3);
addr2 = (addr - 0x500000) >> 13;
}
break;
case 0x14:
case 0x15:
nbank = addr >> 21;
if ((nbank & 7) < 4) {
nbank = (addr >> 11) & 3;
addr2 = addr >> 13;
} else if ((nbank & 7) < 6) {
nbank = 4 + (((addr - 0x800000) >> 11) & 1);
addr2 = (addr - 0x800000) >> 12;
} else {
nbank = 6 + (((addr - 0xc00000) >> 11) & 3);
addr2 = (addr - 0xc00000) >> 13;
}
break;
case 0x16:
nbank = ((addr >> 21) & 4) | ((addr >> 11) & 3);
addr2 = addr >> 13;
break;
case 0x17:
if (dev->external_is_RAS && (addr & 0x800) == 0)
return 0xffffffff;
nbank = addr >> 19;
if (nbank < 2) {
nbank = (addr >> 10) & 1;
addr2 = addr >> 11;
} else {
nbank = 2 + ((addr - 0x100000) >> 23);
addr2 = (addr - 0x100000) >> 12;
}
break;
case 0x18:
if (dev->external_is_RAS && (addr & 0x800) == 0)
return 0xffffffff;
nbank = addr >> 21;
if (nbank < 4) {
nbank = 1;
addr2 = addr >> 12;
} else if (nbank == 4) {
nbank = 0;
addr2 = addr >> 11;
} else {
nbank -= 3;
addr2 = addr >> 11;
}
break;
case 0x19:
if (dev->external_is_RAS && (addr & 0x800) == 0)
return 0xffffffff;
nbank = addr >> 23;
if ((nbank & 3) < 2) {
nbank = (addr >> 12) & 1;
addr2 = addr >> 13;
} else
addr2 = addr >> 12;
break;
default:
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6) {
nbank = addr >> 19;
addr2 = (addr >> 10) & 0x1ff;
} else if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) {
nbank = addr >> 21;
addr2 = (addr >> 11) & 0x3ff;
} else {
nbank = addr >> 23;
addr2 = (addr >> 12) & 0x7ff;
}
break;
}
nbank &= (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) ? 7 : 3;
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 0x16 && nbank == 3)
return 0xffffffff;
if (dev->external_is_RAS && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) == 0) {
if (nbank == 3)
nbank = 7;
else
return 0xffffffff;
} else if (!dev->external_is_RAS && dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x80) {
switch (nbank) {
case 7:
nbank = 3;
break;
/* Note - In the following cases, the chipset accesses multiple memory banks
at the same time, so it's impossible to predict which memory bank
is actually accessed. */
case 5:
case 1:
nbank = 1;
break;
case 3:
nbank = 2;
break;
default:
nbank = 0;
break;
}
}
switch (mem_size & ~511) {
case 1024:
case 1536:
addr &= 0x3ff;
if (nbank < 2)
addr |= (nbank << 10) | ((addr2 & 0x1ff) << 11);
else
addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19);
break;
case 2048:
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 5) {
addr &= 0x3ff;
if (nbank < 4)
addr |= (nbank << 10) | ((addr2 & 0x1ff) << 12);
else
addr |= ((addr2 & 0x1ff) << 10) | (nbank << 19);
} else {
addr &= 0x7ff;
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
}
break;
case 2560:
if (nbank == 0)
addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10);
else {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21));
}
break;
case 3072:
if (nbank < 2)
addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11);
else
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21));
break;
case 4096:
case 6144:
addr &= 0x7ff;
if (nbank < 2)
addr |= (nbank << 11) | ((addr2 & 0x3ff) << 12);
else
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
break;
case 4608:
if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) {
if (nbank == 0)
addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10);
else if (nbank < 3)
addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12));
else
addr = 0x480000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 3) << 19));
} else if (nbank == 0)
addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10);
else {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr = addr + 0x80000 + ((addr2 << 11) | ((nbank - 1) << 21));
}
break;
case 5120:
case 7168:
if (nbank < 2)
addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11);
else if (nbank < 4)
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11));
else
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21));
break;
case 6656:
if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) >= 8 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) <= 0x0a) || ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 0x18)) {
if (nbank == 0)
addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10);
else if (nbank < 3)
addr = 0x80000 + ((addr & 0x7ff) | ((nbank - 1) << 11) | ((addr2 & 0x3ff) << 12));
else if (nbank == 3)
addr = 0x480000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11));
else
addr = 0x680000 + ((addr & 0x3ff) | ((addr2 & 0x1ff) << 10) | ((nbank - 4) << 19));
} else if (nbank == 0)
addr = (addr & 0x3ff) | ((addr2 & 0x1ff) << 10);
else if (nbank == 1) {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr = addr + 0x80000 + (addr2 << 11);
} else {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr = addr + 0x280000 + ((addr2 << 12) | ((nbank & 1) << 11) | (((nbank - 2) & 6) << 21));
}
break;
case 8192:
addr &= 0x7ff;
if (nbank < 4)
addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13);
else
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
break;
case 9216:
if (nbank < 2)
addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11);
else if (dev->external_is_RAS) {
if (nbank < 6)
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11));
else
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21));
} else
addr = 0x100000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23));
break;
case 10240:
if (dev->external_is_RAS) {
addr &= 0x7ff;
if (nbank < 4)
addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13);
else
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
} else if (nbank == 0)
addr = (addr & 0x7ff) | ((addr2 & 0x3ff) << 11);
else {
addr &= 0xfff;
addr2 &= 0x7ff;
addr = addr + 0x200000 + ((addr2 << 12) | ((nbank - 1) << 23));
}
break;
case 11264:
if (nbank < 2)
addr = (addr & 0x3ff) | (nbank << 10) | ((addr2 & 0x1ff) << 11);
else if (nbank < 6)
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 12) | ((nbank & 1) << 11));
else
addr = 0x100000 + ((addr & 0x7ff) | ((addr2 & 0x3ff) << 11) | ((nbank - 2) << 21));
break;
case 12288:
if (dev->external_is_RAS) {
addr &= 0x7ff;
if (nbank < 4)
addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13);
else if (nbank < 6)
addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21);
else
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
} else {
if (nbank < 2)
addr = (addr & 0x7ff) | (nbank << 11) | ((addr2 & 0x3ff) << 12);
else
addr = 0x400000 + ((addr & 0xfff) | ((addr2 & 0x7ff) << 12) | ((nbank - 2) << 23));
}
break;
case 13312:
if (nbank < 2)
addr = (addr & 0x3FF) | (nbank << 10) | ((addr2 & 0x1FF) << 11);
else if (nbank < 4)
addr = 0x100000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 12) | ((nbank & 1) << 11));
else
addr = 0x500000 + ((addr & 0x7FF) | ((addr2 & 0x3FF) << 13) | ((nbank & 3) << 11));
break;
case 14336:
addr &= 0x7ff;
if (nbank < 4)
addr |= (nbank << 11) | ((addr2 & 0x3ff) << 13);
else if (nbank < 6)
addr |= ((nbank & 1) << 11) | ((addr2 & 0x3ff) << 12) | ((nbank & 4) << 21);
else
addr |= ((addr2 & 0x3ff) << 11) | (nbank << 21);
break;
case 16384:
if (dev->external_is_RAS) {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr |= ((nbank & 3) << 11) | (addr2 << 13) | ((nbank & 4) << 21);
} else {
addr &= 0xfff;
addr2 &= 0x7ff;
if (nbank < 2)
addr |= (addr2 << 13) | (nbank << 12);
else
addr |= (addr2 << 12) | (nbank << 23);
}
break;
default:
if (mem_size < 2048 || ((mem_size & 1536) == 512) || (mem_size == 2048 && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 6)) {
addr &= 0x3ff;
addr2 &= 0x1ff;
addr |= (addr2 << 10) | (nbank << 19);
} else if (mem_size < 8192 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 0x17) {
addr &= 0x7ff;
addr2 &= 0x3ff;
addr |= (addr2 << 11) | (nbank << 21);
} else {
addr &= 0xfff;
addr2 &= 0x7ff;
addr |= (addr2 << 12) | (nbank << 23);
}
break;
}
}
return addr;
}
static void
set_global_EMS_state(scat_t *dev, int state)
{
uint32_t base_addr;
uint32_t virt_addr;
int conf;
for (uint32_t i = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 24; i < 32; i++) {
base_addr = (i + 16) << 14;
if (i >= 24)
base_addr += 0x30000;
if (state && (dev->page[i].regs_2x9 & 0x80)) {
virt_addr = get_addr(dev, base_addr, &dev->page[i]);
if (i < 24)
mem_mapping_disable(&dev->efff_mapping[i]);
else
mem_mapping_disable(&dev->efff_mapping[i + 12]);
mem_mapping_enable(&dev->ems_mapping[i]);
if (virt_addr < ((uint32_t) mem_size << 10))
mem_mapping_set_exec(&dev->ems_mapping[i], ram + virt_addr);
else
mem_mapping_set_exec(&dev->ems_mapping[i], NULL);
} else {
mem_mapping_set_exec(&dev->ems_mapping[i], ram + base_addr);
mem_mapping_disable(&dev->ems_mapping[i]);
conf = (dev->regs[SCAT_VERSION] & 0xf0) ? (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f)
: (dev->regs[SCAT_DRAM_CONFIGURATION] & 0xf) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2);
if (i < 24) {
if (conf > 1 || (conf == 1 && i < 16))
mem_mapping_enable(&dev->efff_mapping[i]);
else
mem_mapping_disable(&dev->efff_mapping[i]);
} else if (conf > 3 || ((dev->regs[SCAT_VERSION] & 0xf0) != 0 && conf == 2))
mem_mapping_enable(&dev->efff_mapping[i + 12]);
else
mem_mapping_disable(&dev->efff_mapping[i + 12]);
}
}
flushmmucache();
}
static void
memmap_state_update(scat_t *dev)
{
uint32_t addr;
for (uint8_t i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) {
addr = get_addr(dev, 0x40000 + (i << 14), &dev->null_page);
mem_mapping_set_exec(&dev->efff_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
}
addr = get_addr(dev, 0, &dev->null_page);
mem_mapping_set_exec(&dev->low_mapping[0],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
addr = get_addr(dev, 0xf0000, &dev->null_page);
mem_mapping_set_exec(&dev->low_mapping[1],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
for (uint8_t i = 2; i < 32; i++) {
addr = get_addr(dev, i << 19, &dev->null_page);
mem_mapping_set_exec(&dev->low_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
}
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
uint8_t j = 0;
for (j = 0; j < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; j++)
mem_mapping_enable(&dev->low_mapping[j]);
for (; j < 32; j++)
mem_mapping_disable(&dev->low_mapping[j]);
for (j = 24; j < 36; j++) {
if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40)) < 4)
mem_mapping_disable(&dev->efff_mapping[j]);
else
mem_mapping_enable(&dev->efff_mapping[j]);
}
} else {
uint8_t j = 0;
for (j = 0; j < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; j++)
mem_mapping_enable(&dev->low_mapping[j]);
for (; j < 32; j++)
mem_mapping_disable(&dev->low_mapping[j]);
for (j = 24; j < 36; j++) {
if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 2 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)
mem_mapping_disable(&dev->efff_mapping[j]);
else
mem_mapping_enable(&dev->efff_mapping[j]);
}
}
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) == 0) || ((dev->regs[SCAT_VERSION] & 0xf0) != 0)) {
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) {
mem_mapping_disable(&dev->low_mapping[2]);
for (uint8_t i = 0; i < 6; i++) {
addr = get_addr(dev, 0x100000 + (i << 16), &dev->null_page);
mem_mapping_set_exec(&dev->remap_mapping[i],
addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
mem_mapping_enable(&dev->remap_mapping[i]);
}
} else {
for (uint8_t i = 0; i < 6; i++)
mem_mapping_disable(&dev->remap_mapping[i]);
if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) > 4) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 3))
mem_mapping_enable(&dev->low_mapping[2]);
}
} else {
for (uint8_t i = 0; i < 6; i++)
mem_mapping_disable(&dev->remap_mapping[i]);
mem_mapping_enable(&dev->low_mapping[2]);
}
set_global_EMS_state(dev, dev->regs[SCAT_EMS_CONTROL] & 0x80);
flushmmucache_nopc();
}
static void
scat_out(uint16_t port, uint8_t val, void *priv)
{
scat_t *dev = (scat_t *) priv;
uint8_t reg_valid = 0;
uint8_t shadow_update = 0;
uint8_t map_update = 0;
uint8_t indx;
uint32_t base_addr;
uint32_t virt_addr;
switch (port) {
case 0x22:
dev->indx = val;
break;
case 0x23:
switch (dev->indx) {
case SCAT_DMA_WAIT_STATE_CONTROL:
case SCAT_CLOCK_CONTROL:
case SCAT_PERIPHERAL_CONTROL:
reg_valid = 1;
break;
case SCAT_EMS_CONTROL:
io_removehandler(0x0208, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev);
io_removehandler(0x0218, 0x0003, scat_in, NULL, NULL, scat_out, NULL, NULL, dev);
if (val & 0x40) {
if (val & 1)
io_sethandler(0x0218, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev);
else
io_sethandler(0x0208, 3, scat_in, NULL, NULL, scat_out, NULL, NULL, dev);
}
set_global_EMS_state(dev, val & 0x80);
reg_valid = 1;
break;
case SCAT_POWER_MANAGEMENT:
/* TODO - Only use AUX parity disable bit for this version.
Other bits should be implemented later. */
val &= (dev->regs[SCAT_VERSION] & 0xf0) == 0 ? 0x40 : 0x60;
reg_valid = 1;
break;
case SCAT_DRAM_CONFIGURATION:
map_update = 1;
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
cpu_update_waitstates();
}
reg_valid = 1;
break;
case SCAT_EXTENDED_BOUNDARY:
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
if (dev->regs[SCAT_VERSION] < 4) {
val &= 0xbf;
set_xms_bound(dev, val & 0x0f);
} else {
val = (val & 0x7f) | 0x80;
set_xms_bound(dev, val & 0x4f);
}
} else
set_xms_bound(dev, val & 0x1f);
mem_set_mem_state(0x40000, 0x60000, (val & 0x20) ? MEM_READ_EXTANY | MEM_WRITE_EXTANY : MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if ((val ^ dev->regs[SCAT_EXTENDED_BOUNDARY]) & 0xc0)
map_update = 1;
reg_valid = 1;
break;
case SCAT_ROM_ENABLE:
case SCAT_RAM_WRITE_PROTECT:
case SCAT_SHADOW_RAM_ENABLE_1:
case SCAT_SHADOW_RAM_ENABLE_2:
case SCAT_SHADOW_RAM_ENABLE_3:
reg_valid = 1;
shadow_update = 1;
break;
case SCATSX_LAPTOP_FEATURES:
if ((dev->regs[SCAT_VERSION] & 0xf0) != 0) {
val = (val & ~8) | (dev->regs[SCATSX_LAPTOP_FEATURES] & 8);
reg_valid = 1;
}
break;
case SCATSX_FAST_VIDEO_CONTROL:
case SCATSX_FAST_VIDEORAM_ENABLE:
case SCATSX_HIGH_PERFORMANCE_REFRESH:
case SCATSX_CAS_TIMING_FOR_DMA:
if ((dev->regs[SCAT_VERSION] & 0xf0) != 0)
reg_valid = 1;
break;
default:
break;
}
if (reg_valid)
dev->regs[dev->indx] = val;
if (shadow_update)
shadow_state_update(dev);
if (map_update)
memmap_state_update(dev);
break;
case 0x208:
case 0x218:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0)
indx = dev->reg_2xA & 0x1f;
else
indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24;
dev->page[indx].regs_2x8 = val;
base_addr = (indx + 16) << 14;
if (indx >= 24)
base_addr += 0x30000;
if ((dev->regs[SCAT_EMS_CONTROL] & 0x80) && (dev->page[indx].regs_2x9 & 0x80)) {
virt_addr = get_addr(dev, base_addr, &dev->page[indx]);
if (virt_addr < ((uint32_t) mem_size << 10))
mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr);
else
mem_mapping_set_exec(&dev->ems_mapping[indx], NULL);
flushmmucache();
}
}
break;
case 0x209:
case 0x219:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0)
indx = dev->reg_2xA & 0x1f;
else
indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24;
dev->page[indx].regs_2x9 = val;
base_addr = (indx + 16) << 14;
if (indx >= 24)
base_addr += 0x30000;
if (dev->regs[SCAT_EMS_CONTROL] & 0x80) {
if (val & 0x80) {
virt_addr = get_addr(dev, base_addr, &dev->page[indx]);
if (indx < 24)
mem_mapping_disable(&dev->efff_mapping[indx]);
else
mem_mapping_disable(&dev->efff_mapping[indx + 12]);
if (virt_addr < ((uint32_t) mem_size << 10))
mem_mapping_set_exec(&dev->ems_mapping[indx], ram + virt_addr);
else
mem_mapping_set_exec(&dev->ems_mapping[indx], NULL);
mem_mapping_enable(&dev->ems_mapping[indx]);
} else {
mem_mapping_set_exec(&dev->ems_mapping[indx], ram + base_addr);
mem_mapping_disable(&dev->ems_mapping[indx]);
if (indx < 24)
mem_mapping_enable(&dev->efff_mapping[indx]);
else
mem_mapping_enable(&dev->efff_mapping[indx + 12]);
}
flushmmucache();
}
if (dev->reg_2xA & 0x80)
dev->reg_2xA = (dev->reg_2xA & 0xe0) | ((dev->reg_2xA + 1) & (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0x1f : 3));
}
break;
case 0x20a:
case 0x21a:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3;
break;
default:
break;
}
}
static uint8_t
scat_in(uint16_t port, void *priv)
{
const scat_t *dev = (scat_t *) priv;
uint8_t ret = 0xff;
uint8_t indx;
switch (port) {
case 0x23:
switch (dev->indx) {
case SCAT_MISCELLANEOUS_STATUS:
ret = (dev->regs[dev->indx] & 0x3f) | (~nmi_mask & 0x80) | ((mem_a20_key & 2) << 5);
break;
case SCAT_DRAM_CONFIGURATION:
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0)
ret = (dev->regs[dev->indx] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
else
ret = dev->regs[dev->indx];
break;
case SCAT_EXTENDED_BOUNDARY:
ret = dev->regs[dev->indx];
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
if ((dev->regs[SCAT_VERSION] & 0x0f) >= 4)
ret |= 0x80;
else
ret &= 0xaf;
}
break;
default:
if (dev->indx <= dev->max_reg)
ret = dev->regs[dev->indx];
break;
}
break;
case 0x208:
case 0x218:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0)
indx = dev->reg_2xA & 0x1f;
else
indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24;
ret = dev->page[indx].regs_2x8;
}
break;
case 0x209:
case 0x219:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4))) {
if ((dev->regs[SCAT_VERSION] & 0xf0) == 0)
indx = dev->reg_2xA & 0x1f;
else
indx = ((dev->reg_2xA & 0x40) >> 4) + (dev->reg_2xA & 0x3) + 24;
ret = dev->page[indx].regs_2x9;
}
break;
case 0x20a:
case 0x21a:
if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
ret = dev->reg_2xA;
break;
default:
break;
}
return ret;
}
static uint8_t
mem_read_scatb(uint32_t addr, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint8_t val = 0xff;
addr = get_addr(dev, addr, page);
if (addr < ((uint32_t) mem_size << 10))
val = ram[addr];
return val;
}
static uint16_t
mem_read_scatw(uint32_t addr, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint16_t val = 0xffff;
addr = get_addr(dev, addr, page);
if (addr < ((uint32_t) mem_size << 10))
val = *(uint16_t *) &ram[addr];
return val;
}
static uint32_t
mem_read_scatl(uint32_t addr, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint32_t val = 0xffffffff;
addr = get_addr(dev, addr, page);
if (addr < ((uint32_t) mem_size << 10))
val = *(uint32_t *) &ram[addr];
return val;
}
static void
mem_write_scatb(uint32_t addr, uint8_t val, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint32_t oldaddr = addr;
uint32_t chkaddr;
addr = get_addr(dev, addr, page);
chkaddr = page->valid ? addr : oldaddr;
if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) {
if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15)))
return;
}
if (addr < ((uint32_t) mem_size << 10))
ram[addr] = val;
}
static void
mem_write_scatw(uint32_t addr, uint16_t val, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint32_t oldaddr = addr;
uint32_t chkaddr;
addr = get_addr(dev, addr, page);
chkaddr = page->valid ? addr : oldaddr;
if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) {
if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15)))
return;
}
if (addr < ((uint32_t) mem_size << 10))
*(uint16_t *) &ram[addr] = val;
}
static void
mem_write_scatl(uint32_t addr, uint32_t val, void *priv)
{
ems_page_t *page = (ems_page_t *) priv;
scat_t *dev = (scat_t *) page->scat;
uint32_t oldaddr = addr;
uint32_t chkaddr;
addr = get_addr(dev, addr, page);
chkaddr = page->valid ? addr : oldaddr;
if ((chkaddr >= 0xc0000) && (chkaddr < 0x100000)) {
if (dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << ((chkaddr - 0xc0000) >> 15)))
return;
}
if (addr < ((uint32_t) mem_size << 10))
*(uint32_t *) &ram[addr] = val;
}
static void
scat_close(void *priv)
{
scat_t *dev = (scat_t *) priv;
free(dev);
}
static void *
scat_init(const device_t *info)
{
scat_t *dev;
uint32_t j;
uint32_t k;
int sx;
dev = (scat_t *) malloc(sizeof(scat_t));
memset(dev, 0x00, sizeof(scat_t));
dev->type = info->local;
sx = (dev->type == 32) ? 1 : 0;
dev->max_reg = sx ? 0x64 : 0x4f;
for (uint32_t i = 0; i < sizeof(dev->regs); i++)
dev->regs[i] = 0xff;
if (sx) {
dev->regs[SCAT_VERSION] = 0x13;
dev->regs[SCAT_CLOCK_CONTROL] = 6;
dev->regs[SCAT_PERIPHERAL_CONTROL] = 0;
dev->regs[SCAT_DRAM_CONFIGURATION] = 1;
dev->regs[SCATSX_LAPTOP_FEATURES] = 0;
dev->regs[SCATSX_FAST_VIDEO_CONTROL] = 0;
dev->regs[SCATSX_FAST_VIDEORAM_ENABLE] = 0;
dev->regs[SCATSX_HIGH_PERFORMANCE_REFRESH] = 8;
dev->regs[SCATSX_CAS_TIMING_FOR_DMA] = 3;
} else {
switch (dev->type) {
case 4:
dev->regs[SCAT_VERSION] = 4;
break;
default:
dev->regs[SCAT_VERSION] = 1;
break;
}
dev->regs[SCAT_CLOCK_CONTROL] = 2;
dev->regs[SCAT_PERIPHERAL_CONTROL] = 0x80;
dev->regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12;
}
dev->regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
dev->regs[SCAT_MISCELLANEOUS_STATUS] = 0x37;
dev->regs[SCAT_ROM_ENABLE] = 0xc0;
dev->regs[SCAT_RAM_WRITE_PROTECT] = 0;
dev->regs[SCAT_POWER_MANAGEMENT] = 0;
dev->regs[SCAT_SHADOW_RAM_ENABLE_1] = 0;
dev->regs[SCAT_SHADOW_RAM_ENABLE_2] = 0;
dev->regs[SCAT_SHADOW_RAM_ENABLE_3] = 0;
dev->regs[SCAT_EXTENDED_BOUNDARY] = 0;
dev->regs[SCAT_EMS_CONTROL] = 0;
/* Disable all system mappings, we will override them. */
mem_mapping_disable(&ram_low_mapping);
if (!sx)
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
k = sx ? 0x80000 : 0x40000;
dev->null_page.valid = 0;
dev->null_page.regs_2x8 = 0xff;
dev->null_page.regs_2x9 = 0xff;
dev->null_page.scat = dev;
mem_mapping_add(&dev->low_mapping[0], 0, k,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram, MEM_MAPPING_INTERNAL, &dev->null_page);
mem_mapping_add(&dev->low_mapping[1], 0xf0000, 0x10000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram + 0xf0000, MEM_MAPPING_INTERNAL, &dev->null_page);
for (uint8_t i = 2; i < 32; i++) {
mem_mapping_add(&dev->low_mapping[i], (i << 19), 0x80000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram + (i << 19), MEM_MAPPING_INTERNAL, &dev->null_page);
}
if (sx) {
j = 16;
k = 0x40000;
} else {
j = 0;
k = (dev->regs[SCAT_VERSION] < 4) ? 0x40000 : 0x60000;
}
mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000, k);
for (; j < 44; j++) {
mem_mapping_add(&dev->efff_mapping[j], 0x40000 + (j << 14), 0x4000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
mem_size > (256 + (j << 4)) ? ram + 0x40000 + (j << 14) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_page);
if (sx)
mem_mapping_enable(&dev->efff_mapping[j]);
}
if (sx) {
for (uint8_t i = 24; i < 32; i++) {
dev->page[i].valid = 1;
dev->page[i].regs_2x8 = 0xff;
dev->page[i].regs_2x9 = 0x03;
dev->page[i].scat = dev;
mem_mapping_add(&dev->ems_mapping[i], (i + 28) << 14, 0x04000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram + ((i + 28) << 14), 0, &dev->page[i]);
mem_mapping_disable(&dev->ems_mapping[i]);
}
} else {
for (uint8_t i = 0; i < 32; i++) {
dev->page[i].valid = 1;
dev->page[i].regs_2x8 = 0xff;
dev->page[i].regs_2x9 = 0x03;
dev->page[i].scat = dev;
mem_mapping_add(&dev->ems_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
ram + ((i + (i >= 24 ? 28 : 16)) << 14),
0, &dev->page[i]);
}
}
for (uint8_t i = 0; i < 6; i++) {
mem_mapping_add(&dev->remap_mapping[i], 0x100000 + (i << 16), 0x10000,
mem_read_scatb, mem_read_scatw, mem_read_scatl,
mem_write_scatb, mem_write_scatw, mem_write_scatl,
mem_size >= 1024 ? ram + get_addr(dev, 0x100000 + (i << 16), &dev->null_page) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_page);
}
if (sx) {
dev->external_is_RAS = scatsx_external_is_RAS[mem_size >> 9];
} else {
dev->external_is_RAS = (dev->regs[SCAT_VERSION] > 3) || (((mem_size & ~2047) >> 11) + ((mem_size & 1536) >> 9) + ((mem_size & 511) >> 7)) > 4;
}
set_xms_bound(dev, 0);
memmap_state_update(dev);
shadow_state_update(dev);
io_sethandler(0x0022, 2,
scat_in, NULL, NULL, scat_out, NULL, NULL, dev);
device_add(&port_92_device);
return dev;
}
const device_t scat_device = {
.name = "C&T SCAT (v1)",
.internal_name = "scat",
.flags = 0,
.local = 0,
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t scat_4_device = {
.name = "C&T SCAT (v4)",
.internal_name = "scat_4",
.flags = 0,
.local = 4,
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t scat_sx_device = {
.name = "C&T SCATsx",
.internal_name = "scat_sx",
.flags = 0,
.local = 32,
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/scat.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 16,902 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Chips & Technologies CS4031 chipset.
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct cs4031_t {
uint8_t index;
uint8_t regs[256];
port_92_t *port_92;
} cs4031_t;
#ifdef ENABLE_CS4031_LOG
int cs4031_do_log = ENABLE_CS4031_LOG;
static void
cs4031_log(const char *fmt, ...)
{
va_list ap;
if (cs4031_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cs4031_log(fmt, ...)
#endif
static void
cs4031_shadow_recalc(cs4031_t *dev)
{
mem_set_mem_state_both(0xa0000, 0x10000, (dev->regs[0x18] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xb0000, 0x10000, (dev->regs[0x18] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
for (uint32_t i = 0; i < 7; i++) {
if (i < 4)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
else
mem_set_mem_state_both(0xd0000 + ((i - 4) << 16), 0x10000, ((dev->regs[0x19] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x1a] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
shadowbios = !!(dev->regs[0x19] & 0x40);
shadowbios_write = !!(dev->regs[0x1a] & 0x40);
}
static void
cs4031_write(uint16_t addr, uint8_t val, void *priv)
{
cs4031_t *dev = (cs4031_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
cs4031_log("CS4031: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
case 0x05:
dev->regs[dev->index] = val & 0x3f;
break;
case 0x06:
dev->regs[dev->index] = val & 0xbc;
break;
case 0x07:
dev->regs[dev->index] = val & 0x0f;
break;
case 0x10:
dev->regs[dev->index] = val & 0x3d;
break;
case 0x11:
dev->regs[dev->index] = val & 0x8d;
break;
case 0x12:
case 0x13:
dev->regs[dev->index] = val & 0x8d;
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
dev->regs[dev->index] = val & 0x7f;
break;
case 0x18:
dev->regs[dev->index] = val & 0xf3;
cs4031_shadow_recalc(dev);
break;
case 0x19:
case 0x1a:
dev->regs[dev->index] = val & 0x7f;
cs4031_shadow_recalc(dev);
break;
case 0x1b:
dev->regs[dev->index] = val;
break;
case 0x1c:
dev->regs[dev->index] = val & 0xb3;
port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
cs4031_read(uint16_t addr, void *priv)
{
const cs4031_t *dev = (cs4031_t *) priv;
return (addr == 0x23) ? dev->regs[dev->index] : 0xff;
}
static void
cs4031_close(void *priv)
{
cs4031_t *dev = (cs4031_t *) priv;
free(dev);
}
static void *
cs4031_init(UNUSED(const device_t *info))
{
cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
memset(dev, 0, sizeof(cs4031_t));
dev->port_92 = device_add(&port_92_device);
dev->regs[0x05] = 0x05;
dev->regs[0x1b] = 0x60;
io_sethandler(0x0022, 0x0002, cs4031_read, NULL, NULL, cs4031_write, NULL, NULL, dev);
return dev;
}
const device_t cs4031_device = {
.name = "Chips & Technogies CS4031",
.internal_name = "cs4031",
.flags = 0,
.local = 0,
.init = cs4031_init,
.close = cs4031_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/cs4031.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,534 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of C&T CS8121 ("NEAT") 82C206/211/212/215 chipset.
*
* Note: The datasheet mentions that the chipset supports up to 8MB
* of DRAM. This is intepreted as 'being able to refresh up to
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#define NEAT_DEBUG 0
#define EMS_MAXPAGE 4
#define EMS_PGSIZE 16384
/* CS8221 82C211 controller registers. */
#define REG_RA0 0x60 /* PROCCLK selector */
#define RA0_MASK 0x34 /* RR11 X1XR */
#define RA0_READY 0x01 /* local bus READY timeout */
#define RA0_RDYNMIEN 0x04 /* local bus READY tmo NMI enable */
#define RA0_PROCCLK 0x10 /* PROCCLK=BCLK (1) or CLK2IN (0) */
#define RA0_ALTRST 0x20 /* alternate CPU reset (1) */
#define RA0_REV 0xc0 /* chip revision ID */
#define RA0_REV_SH 6
#define RA0_REV_ID 2 /* faked revision# for 82C211 */
#define REG_RA1 0x61 /* Command Delay */
#define RA1_MASK 0xff /* 1111 1111 */
#define RA1_BUSDLY 0x03 /* AT BUS command delay */
#define RA1_BUSDLY_SH 0
#define RA1_BUS8DLY 0x0c /* AT BUS 8bit command delay */
#define RA1_BUS8DLY_SH 2
#define RA1_MEMDLY 0x30 /* AT BUS 16bit memory delay */
#define RA1_MEMDLY_SH 4
#define RA1_QUICKEN 0x40 /* Quick Mode enable */
#define RA1_HOLDDLY 0x80 /* Hold Time Delay */
#define REG_RA2 0x62 /* Wait State / BCLK selector */
#define RA2_MASK 0x3f /* XX11 1111 */
#define RA2_BCLK 0x03 /* BCLK select */
#define RA2_BCLK_SH 0
#define BCLK_IN2 0 /* BCLK = CLK2IN/2 */
#define BCLK_IN 1 /* BCLK = CLK2IN */
#define BCLK_AT 2 /* BCLK = ATCLK */
#define RA2_AT8WS 0x0c /* AT 8-bit wait states */
#define RA2_AT8WS_SH 2
#define AT8WS_2 0 /* 2 wait states */
#define AT8WS_3 1 /* 3 wait states */
#define AT8WS_4 2 /* 4 wait states */
#define AT8WS_5 4 /* 5 wait states */
#define RA2_ATWS 0x30 /* AT 16-bit wait states */
#define RA2_ATWS_SH 4
#define ATWS_2 0 /* 2 wait states */
#define ATWS_3 1 /* 3 wait states */
#define ATWS_4 2 /* 4 wait states */
#define ATWS_5 4 /* 5 wait states */
/* CS8221 82C212 controller registers. */
#define REG_RB0 0x64 /* Version ID */
#define RB0_MASK 0x60 /* R11X XXXX */
#define RB0_REV 0x60 /* Chip revsion number */
#define RB0_REV_SH 5
#define RB0_REV_ID 2 /* faked revision# for 82C212 */
#define RB0_VERSION 0x80 /* Chip version (0=82C212) */
#define REG_RB1 0x65 /* ROM configuration */
#define RB1_MASK 0xff /* 1111 1111 */
#define RB1_ROMF0 0x01 /* ROM F0000 enabled (0) */
#define RB1_ROME0 0x02 /* ROM E0000 disabled (1) */
#define RB1_ROMD0 0x04 /* ROM D0000 disabled (1) */
#define RB1_ROMC0 0x08 /* ROM C0000 disabled (1) */
#define RB1_SHADOWF0 0x10 /* Shadow F0000 R/W (0) */
#define RB1_SHADOWE0 0x20 /* Shadow E0000 R/W (0) */
#define RB1_SHADOWD0 0x40 /* Shadow D0000 R/W (0) */
#define RB1_SHADOWC0 0x80 /* Shadow C0000 R/W (0) */
#define REG_RB2 0x66 /* Memory Enable 1 */
#define RB2_MASK 0x80 /* 1XXX XXXX */
#define RB2_TOP128 0x80 /* top 128K is on sysboard (1) */
#define REG_RB3 0x67 /* Memory Enable 2 */
#define RB3_MASK 0xff /* 1111 1111 */
#define RB3_SHENB0 0x01 /* enable B0000-B3FFF shadow (1) */
#define RB3_SHENB4 0x02 /* enable B4000-B7FFF shadow (1) */
#define RB3_SHENB8 0x04 /* enable B8000-BBFFF shadow (1) */
#define RB3_SHENBC 0x08 /* enable BC000-BFFFF shadow (1) */
#define RB3_SHENA0 0x10 /* enable A0000-A3FFF shadow (1) */
#define RB3_SHENA4 0x20 /* enable A4000-A7FFF shadow (1) */
#define RB3_SHENA8 0x40 /* enable A8000-ABFFF shadow (1) */
#define RB3_SHENAC 0x80 /* enable AC000-AFFFF shadow (1) */
#define REG_RB4 0x68 /* Memory Enable 3 */
#define RB4_MASK 0xff /* 1111 1111 */
#define RB4_SHENC0 0x01 /* enable C0000-C3FFF shadow (1) */
#define RB4_SHENC4 0x02 /* enable C4000-C7FFF shadow (1) */
#define RB4_SHENC8 0x04 /* enable C8000-CBFFF shadow (1) */
#define RB4_SHENCC 0x08 /* enable CC000-CFFFF shadow (1) */
#define RB4_SHEND0 0x10 /* enable D0000-D3FFF shadow (1) */
#define RB4_SHEND4 0x20 /* enable D4000-D7FFF shadow (1) */
#define RB4_SHEND8 0x40 /* enable D8000-DBFFF shadow (1) */
#define RB4_SHENDC 0x80 /* enable DC000-DFFFF shadow (1) */
#define REG_RB5 0x69 /* Memory Enable 4 */
#define RB5_MASK 0xff /* 1111 1111 */
#define RB5_SHENE0 0x01 /* enable E0000-E3FFF shadow (1) */
#define RB5_SHENE4 0x02 /* enable E4000-E7FFF shadow (1) */
#define RB5_SHENE8 0x04 /* enable E8000-EBFFF shadow (1) */
#define RB5_SHENEC 0x08 /* enable EC000-EFFFF shadow (1) */
#define RB5_SHENF0 0x10 /* enable F0000-F3FFF shadow (1) */
#define RB5_SHENF4 0x20 /* enable F4000-F7FFF shadow (1) */
#define RB5_SHENF8 0x40 /* enable F8000-FBFFF shadow (1) */
#define RB5_SHENFC 0x80 /* enable FC000-FFFFF shadow (1) */
#define REG_RB6 0x6a /* Bank 0/1 Enable */
#define RB6_MASK 0xe0 /* 111R RRRR */
#define RB6_BANKS 0x20 /* #banks used (1=two) */
#define RB6_RTYPE 0xc0 /* DRAM chip size used */
#define RTYPE_SH 6
#define RTYPE_NONE 0 /* Disabled */
#define RTYPE_MIXED 1 /* 64K/256K mixed (for 640K) */
#define RTYPE_256K 2 /* 256K (default) */
#define RTYPE_1M 3 /* 1M */
#define REG_RB7 0x6b /* DRAM configuration */
#define RB7_MASK 0xff /* 1111 1111 */
#define RB7_ROMWS 0x03 /* ROM access wait states */
#define RB7_ROMWS_SH 0
#define ROMWS_0 0 /* 0 wait states */
#define ROMWS_1 1 /* 1 wait states */
#define ROMWS_2 2 /* 2 wait states */
#define ROMWS_3 3 /* 3 wait states (default) */
#define RB7_EMSWS 0x0c /* EMS access wait states */
#define RB7_EMSWS_SH 2
#define EMSWS_0 0 /* 0 wait states */
#define EMSWS_1 1 /* 1 wait states */
#define EMSWS_2 2 /* 2 wait states */
#define EMSWS_3 3 /* 3 wait states (default) */
#define RB7_EMSEN 0x10 /* enable EMS (1=on) */
#define RB7_RAMWS 0x20 /* RAM access wait state (1=1ws) */
#define RB7_UMAREL 0x40 /* relocate 640-1024K to 1M */
#define RB7_PAGEEN 0x80 /* enable Page/Interleaved mode */
#define REG_RB8 0x6c /* Bank 2/3 Enable */
#define RB8_MASK 0xf0 /* 1111 RRRR */
#define RB8_4WAY 0x10 /* enable 4-way interleave mode */
#define RB8_BANKS 0x20 /* enable 2 banks (1) */
#define RB8_RTYPE 0xc0 /* DRAM chip size used */
#define RB8_RTYPE_SH 6
#define REG_RB9 0x6d /* EMS base address */
#define RB9_MASK 0xff /* 1111 1111 */
#define RB9_BASE 0x0f /* I/O base address selection */
#define RB9_BASE_SH 0
#define RB9_FRAME 0xf0 /* frame address selection */
#define RB9_FRAME_SH 4
#define REG_RB10 0x6e /* EMS address extension */
#define RB10_MASK 0xff /* 1111 1111 */
#define RB10_P3EXT 0x03 /* page 3 extension */
#define RB10_P3EXT_SH 0
#define PEXT_0M 0 /* page is at 0-2M */
#define PEXT_2M 1 /* page is at 2-4M */
#define PEXT_4M 2 /* page is at 4-6M */
#define PEXT_6M 3 /* page is at 6-8M */
#define RB10_P2EXT 0x0c /* page 2 extension */
#define RB10_P2EXT_SH 2
#define RB10_P1EXT 0x30 /* page 1 extension */
#define RB10_P1EXT_SH 4
#define RB10_P0EXT 0xc0 /* page 0 extension */
#define RB10_P0EXT_SH 6
#define REG_RB11 0x6f /* Miscellaneous */
#define RB11_MASK 0xe6 /* 111R R11R */
#define RB11_GA20 0x02 /* gate for A20 */
#define RB11_RASTMO 0x04 /* enable RAS timeout counter */
#define RB11_EMSLEN 0xe0 /* EMS memory chunk size */
#define RB11_EMSLEN_SH 5
typedef struct emspage_t {
int8_t enabled; /* 1=ENABLED */
char pad;
uint16_t page; /* selected page in EMS block */
uint32_t start; /* start of EMS in RAM */
uint8_t *addr; /* start addr in EMS RAM */
mem_mapping_t mapping; /* mapping entry for page */
} emspage_t;
typedef struct neat_t {
uint8_t regs[128]; /* all the CS8221 registers */
uint8_t indx; /* programmed index into registers */
char pad;
uint16_t ems_base; /* configured base address */
uint16_t ems_oldbase;
uint32_t ems_frame; /* configured frame address */
uint32_t ems_oldframe;
uint16_t ems_size; /* EMS size in KB */
uint16_t ems_pages; /* EMS size in pages */
emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */
} neat_t;
#ifdef ENABLE_NEAT_LOG
int neat_do_log = ENABLE_NEAT_LOG;
static void
neat_log(const char *fmt, ...)
{
va_list ap;
if (neat_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define neat_log(fmt, ...)
#endif
/* Read one byte from paged RAM. */
static uint8_t
ems_readb(uint32_t addr, void *priv)
{
neat_t *dev = (neat_t *) priv;
uint8_t ret = 0xff;
/* Grab the data. */
ret = *(uint8_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff));
return ret;
}
/* Read one word from paged RAM. */
static uint16_t
ems_readw(uint32_t addr, void *priv)
{
neat_t *dev = (neat_t *) priv;
uint16_t ret = 0xffff;
/* Grab the data. */
ret = *(uint16_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff));
return ret;
}
/* Write one byte to paged RAM. */
static void
ems_writeb(uint32_t addr, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *) priv;
/* Write the data. */
*(uint8_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)) = val;
}
/* Write one word to paged RAM. */
static void
ems_writew(uint32_t addr, uint16_t val, void *priv)
{
neat_t *dev = (neat_t *) priv;
/* Write the data. */
*(uint16_t *) (dev->ems[(addr & 0xffff) >> 14].addr + (addr & 0x3fff)) = val;
}
/* Re-calculate the active-page physical address. */
static void
ems_recalc(neat_t *dev, emspage_t *ems)
{
if (ems->page >= dev->ems_pages) {
/* That page does not exist. */
ems->enabled = 0;
}
/* Pre-calculate the page address in EMS RAM. */
ems->addr = ram + ems->start + (ems->page * EMS_PGSIZE);
if (ems->enabled) {
/* Update the EMS RAM address for this page. */
mem_mapping_set_exec(&ems->mapping, ems->addr);
/* Enable this page. */
mem_mapping_enable(&ems->mapping);
#if NEAT_DEBUG > 1
neat_log("NEAT EMS: page %d set to %08lx, %sabled)\n",
ems->page, ems->addr - ram, ems->enabled ? "en" : "dis");
#endif
} else {
/* Disable this page. */
mem_mapping_disable(&ems->mapping);
}
}
static void
ems_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *) priv;
emspage_t *ems;
int vpage;
#if NEAT_DEBUG > 1
neat_log("NEAT: ems_write(%04x, %02x)\n", port, val);
#endif
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
ems = &dev->ems[vpage];
switch (port & 0x000f) {
case 0x0008:
case 0x0009:
ems->enabled = !!(val & 0x80);
ems->page &= 0x0180; /* clear lower bits */
ems->page |= (val & 0x7f); /* add new bits */
ems_recalc(dev, ems);
break;
default:
break;
}
}
static uint8_t
ems_read(uint16_t port, void *priv)
{
const neat_t *dev = (neat_t *) priv;
uint8_t ret = 0xff;
int vpage;
/* Get the viewport page number. */
vpage = (port / EMS_PGSIZE);
switch (port & 0x000f) {
case 0x0008: /* page number register */
ret = dev->ems[vpage].page & 0x7f;
if (dev->ems[vpage].enabled)
ret |= 0x80;
break;
default:
break;
}
#if NEAT_DEBUG > 1
neat_log("NEAT: ems_read(%04x) = %02x\n", port, ret);
#endif
return ret;
}
/* Initialize the EMS module. */
static void
ems_init(neat_t *dev, int en)
{
uint8_t j;
/* Remove if needed. */
if (!en) {
if (dev->ems_base > 0)
for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Remove I/O handler. */
io_removehandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read, NULL, NULL, ems_write, NULL, NULL, dev);
}
#ifdef ENABLE_NEAT_LOG
neat_log("NEAT: EMS disabled\n");
#endif
return;
}
/* Get configured I/O address. */
j = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
dev->ems_base = 0x0208 + (0x10 * j);
/* Get configured frame address. */
j = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
dev->ems_frame = 0xC0000 + (EMS_PGSIZE * j);
/*
* For each supported page (we can have a maximum of 4),
* create, initialize and disable the mappings, and set
* up the I/O control handler.
*/
for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
/* Create and initialize a page mapping. */
mem_mapping_add(&dev->ems[i].mapping,
dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE,
ems_readb, ems_readw, NULL,
ems_writeb, ems_writew, NULL,
ram, MEM_MAPPING_EXTERNAL,
dev);
/* Disable for now. */
mem_mapping_disable(&dev->ems[i].mapping);
/* Set up an I/O port handler. */
io_sethandler(dev->ems_base + (i * EMS_PGSIZE), 2,
ems_read, NULL, NULL, ems_write, NULL, NULL, dev);
/*
* TODO: update the 'high_mem' mapping to reflect that we now
* have NN MB less extended memory available..
*/
}
neat_log("NEAT: EMS enabled, I/O=%04xH, Frame=%05XH\n",
dev->ems_base, dev->ems_frame);
}
static void
neat_write(uint16_t port, uint8_t val, void *priv)
{
neat_t *dev = (neat_t *) priv;
uint8_t xval;
uint8_t *reg;
int i;
#if NEAT_DEBUG > 2
neat_log("NEAT: write(%04x, %02x)\n", port, val);
#endif
switch (port) {
case 0x22:
dev->indx = val;
break;
case 0x23:
reg = &dev->regs[dev->indx];
xval = *reg ^ val;
switch (dev->indx) {
case REG_RA0:
val &= RA0_MASK;
*reg = (*reg & ~RA0_MASK) | val | (RA0_REV_ID << RA0_REV_SH);
#if NEAT_DEBUG > 1
neat_log("NEAT: RA0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA1:
val &= RA1_MASK;
*reg = (*reg & ~RA1_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RA1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RA2:
val &= RA2_MASK;
*reg = (*reg & ~RA2_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RA2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB0:
val &= RB0_MASK;
*reg = (*reg & ~RB0_MASK) | val | (RB0_REV_ID << RB0_REV_SH);
#if NEAT_DEBUG > 1
neat_log("NEAT: RB0=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB1:
val &= RB1_MASK;
*reg = (*reg & ~RB1_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB1=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB2:
val &= RB2_MASK;
*reg = (*reg & ~RB2_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB2=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB3:
val &= RB3_MASK;
*reg = (*reg & ~RB3_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB3=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB4:
val &= RB4_MASK;
*reg = (*reg & ~RB4_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB4=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB5:
val &= RB5_MASK;
*reg = (*reg & ~RB5_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB5=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB6:
val &= RB6_MASK;
*reg = (*reg & ~RB6_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB6=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB7:
val &= RB7_MASK;
*reg = val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB7=%02x(%02x)\n", val, *reg);
#endif
if (val & RB7_EMSEN)
ems_init(dev, 1);
else if (xval & RB7_EMSEN)
ems_init(dev, 0);
if (xval & RB7_UMAREL) {
if (val & RB7_UMAREL)
mem_remap_top(384);
else
mem_remap_top(0);
}
break;
case REG_RB8:
val &= RB8_MASK;
*reg = (*reg & ~RB8_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB8=%02x(%02x)\n", val, *reg);
#endif
break;
case REG_RB9:
val &= RB9_MASK;
*reg = (*reg & ~RB9_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB9=%02x(%02x)\n", val, *reg);
#endif
if (dev->regs[REG_RB7] & RB7_EMSEN) {
ems_init(dev, 0);
ems_init(dev, 1);
}
break;
case REG_RB10:
val &= RB10_MASK;
*reg = (*reg & ~RB10_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB10=%02x(%02x)\n", val, *reg);
#endif
dev->ems[3].start = ((val & RB10_P3EXT) >> RB10_P3EXT_SH) << 21;
dev->ems[2].start = ((val & RB10_P2EXT) >> RB10_P2EXT_SH) << 21;
dev->ems[1].start = ((val & RB10_P1EXT) >> RB10_P1EXT_SH) << 21;
dev->ems[0].start = ((val & RB10_P0EXT) >> RB10_P0EXT_SH) << 21;
for (i = 0; i < EMS_MAXPAGE; i++)
ems_recalc(dev, &dev->ems[i]);
break;
case REG_RB11:
val &= RB11_MASK;
*reg = (*reg & ~RB11_MASK) | val;
#if NEAT_DEBUG > 1
neat_log("NEAT: RB11=%02x(%02x)\n", val, *reg);
#endif
i = (val & RB11_EMSLEN) >> RB11_EMSLEN_SH;
switch (i) {
case 0: /* "less than 2MB" */
dev->ems_size = 512;
break;
case 1: /* 1 MB */
case 2: /* 2 MB */
case 3: /* 3 MB */
case 4: /* 4 MB */
case 5: /* 5 MB */
case 6: /* 6 MB */
case 7: /* 7 MB */
dev->ems_size = i << 10;
break;
default:
break;
}
dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE;
if (dev->regs[REG_RB7] & RB7_EMSEN) {
neat_log("NEAT: EMS %iKB (%i pages)\n",
dev->ems_size, dev->ems_pages);
}
break;
default:
neat_log("NEAT: inv write to reg %02x (%02x)\n",
dev->indx, val);
break;
}
break;
default:
break;
}
}
static uint8_t
neat_read(uint16_t port, void *priv)
{
const neat_t *dev = (neat_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x22:
ret = dev->indx;
break;
case 0x23:
if ((dev->indx >= 0x60) && (dev->indx <= 0x6f))
ret = dev->regs[dev->indx];
break;
default:
break;
}
#if NEAT_DEBUG > 2
neat_log("NEAT: read(%04x) = %02x\n", port, ret);
#endif
return ret;
}
static void
neat_close(void *priv)
{
neat_t *dev = (neat_t *) priv;
free(dev);
}
static void *
neat_init(UNUSED(const device_t *info))
{
neat_t *dev;
uint8_t dram_mode = 0;
uint8_t i;
/* Create an instance. */
dev = (neat_t *) malloc(sizeof(neat_t));
memset(dev, 0x00, sizeof(neat_t));
/* Initialize some of the registers to specific defaults. */
for (i = REG_RA0; i <= REG_RB11; i++) {
dev->indx = i;
neat_write(0x0023, 0x00, dev);
}
/*
* Based on the value of mem_size, we have to set up
* a proper DRAM configuration (so that EMS works.)
*
* TODO: We might also want to set 'valid' waitstate
* bits, based on our cpu speed.
*/
switch (mem_size) {
case 512: /* 512KB */
/* 256K, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
dram_mode = 2;
break;
case 640: /* 640KB */
/* 256K, 64K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
dram_mode = 4;
break;
case 1024: /* 1MB */
/* 256K, 256K, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
dram_mode = 5;
break;
case 1536: /* 1.5MB */
/* 256K, 256K, 256K, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dram_mode = 7;
break;
case 1664: /* 1.64MB */
/* 256K, 64K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dram_mode = 10;
break;
case 2048: /* 2MB */
#if 1
/* 256K, 256K, 256K, 256K */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
dram_mode = 11;
#else
/* 1M, 0, 0, 0 */
dev->regs[REG_RB6] &= ~RB6_BANKS; /* one bank */
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
dram_mode = 3;
#endif
break;
case 3072: /* 3MB */
/* 256K, 256K, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dram_mode = 8;
break;
case 4096: /* 4MB */
/* 1M, 1M, 0, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
dram_mode = 6;
break;
case 4224: /* 4.64MB */
/* 256K, 64K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dram_mode = 12;
break;
case 5120: /* 5MB */
/* 256K, 256K, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dram_mode = 13;
break;
case 6144: /* 6MB */
/* 1M, 1M, 1M, 0 */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] &= ~RB8_BANKS; /* one bank */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dram_mode = 9;
break;
case 8192: /* 8MB */
/* 1M, 1M, 1M, 1M */
dev->regs[REG_RB6] |= RB6_BANKS; /* two banks */
dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_BANKS; /* two banks */
dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
dev->regs[REG_RB8] |= RB8_4WAY; /* 4way intl */
dram_mode = 14;
break;
default:
neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size);
}
if (dram_mode > 0) {
neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size);
}
/* Set up an I/O handler for the chipset. */
io_sethandler(0x0022, 2,
neat_read, NULL, NULL, neat_write, NULL, NULL, dev);
return dev;
}
const device_t neat_device = {
.name = "C&T CS8121 (NEAT)",
.internal_name = "neat",
.flags = 0,
.local = 0,
.init = neat_init,
.close = neat_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/neat.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,778 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Compaq 386 memory controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/machine.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#define RAM_DIAG_L_BASE_MEM_640KB 0x00
#define RAM_DIAG_L_BASE_MEM_INV 0x10
#define RAM_DIAG_L_BASE_MEM_512KB 0x20
#define RAM_DIAG_L_BASE_MEM_256KB 0x30
#define RAM_DIAG_L_BASE_MEM_MASK 0x30
#define RAM_DIAG_L_PERMA_BITS 0x80
#define RAM_DIAG_H_SYS_RAM_4MB 0x01
#define RAM_DIAG_H_SYS_RAM_1MB 0x02
#define RAM_DIAG_H_SYS_RAM_NONE 0x03
#define RAM_DIAG_H_SYS_RAM_MASK 0x03
#define RAM_DIAG_H_MOD_A_RAM_4MB 0x04
#define RAM_DIAG_H_MOD_A_RAM_1MB 0x08
#define RAM_DIAG_H_MOD_A_RAM_NONE 0x0c
#define RAM_DIAG_H_MOD_A_RAM_MASK 0x0c
#define RAM_DIAG_H_MOD_B_RAM_4MB 0x10
#define RAM_DIAG_H_MOD_B_RAM_1MB 0x20
#define RAM_DIAG_H_MOD_B_RAM_NONE 0x30
#define RAM_DIAG_H_MOD_B_RAM_MASK 0x30
#define RAM_DIAG_H_MOD_C_RAM_4MB 0x40
#define RAM_DIAG_H_MOD_C_RAM_1MB 0x80
#define RAM_DIAG_H_MOD_C_RAM_NONE 0xc0
#define RAM_DIAG_H_MOD_C_RAM_MASK 0xc0
#define MEM_STATE_BUS 0x00
#define MEM_STATE_SYS 0x01
#define MEM_STATE_SYS_RELOC 0x02
#define MEM_STATE_MOD_A 0x04
#define MEM_STATE_MOD_B 0x08
#define MEM_STATE_MOD_C 0x10
#define MEM_STATE_MASK (MEM_STATE_SYS | MEM_STATE_MOD_A | MEM_STATE_MOD_B | MEM_STATE_MOD_C)
#define MEM_STATE_WP 0x20
typedef struct cpq_ram_t {
uint8_t wp;
uint32_t phys_base;
uint32_t virt_base;
mem_mapping_t mapping;
} cpq_ram_t;
typedef struct cpq_386_t {
uint8_t regs[8];
uint8_t old_state[256];
uint8_t mem_state[256];
uint32_t ram_bases[4];
uint32_t ram_sizes[4];
uint32_t ram_map_sizes[4];
cpq_ram_t ram[4][64];
cpq_ram_t high_ram[16];
mem_mapping_t regs_mapping;
} cpq_386_t;
static uint8_t
cpq_read_ram(uint32_t addr, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
uint8_t ret = 0xff;
addr = (addr - dev->virt_base) + dev->phys_base;
if (addr < (mem_size << 10))
ret = mem_read_ram(addr, priv);
return ret;
}
static uint16_t
cpq_read_ramw(uint32_t addr, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
uint16_t ret = 0xffff;
addr = (addr - dev->virt_base) + dev->phys_base;
if (addr < (mem_size << 10))
ret = mem_read_ramw(addr, priv);
return ret;
}
static uint32_t
cpq_read_raml(uint32_t addr, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
uint32_t ret = 0xffffffff;
addr = (addr - dev->virt_base) + dev->phys_base;
if (addr < (mem_size << 10))
ret = mem_read_raml(addr, priv);
return ret;
}
static void
cpq_write_ram(uint32_t addr, uint8_t val, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
addr = (addr - dev->virt_base) + dev->phys_base;
if (!dev->wp && (addr < (mem_size << 10)))
mem_write_ram(addr, val, priv);
}
static void
cpq_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
addr = (addr - dev->virt_base) + dev->phys_base;
if (!dev->wp && (addr < (mem_size << 10)))
mem_write_ramw(addr, val, priv);
}
static void
cpq_write_raml(uint32_t addr, uint32_t val, void *priv)
{
const cpq_ram_t *dev = (cpq_ram_t *) priv;
addr = (addr - dev->virt_base) + dev->phys_base;
if (!dev->wp && (addr < (mem_size << 10)))
mem_write_raml(addr, val, priv);
}
static uint8_t
cpq_read_regs(uint32_t addr, void *priv)
{
const cpq_386_t *dev = (cpq_386_t *) priv;
uint8_t ret = 0xff;
addr &= 0x00000fff;
switch (addr) {
case 0x00000000:
case 0x00000001:
/* RAM Diagnostics (Read Only) */
case 0x00000002:
case 0x00000003:
/* RAM Setup Port (Read/Write) */
ret = dev->regs[addr];
break;
default:
break;
}
return ret;
}
static uint16_t
cpq_read_regsw(uint32_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = cpq_read_regs(addr, priv);
ret |= (((uint16_t) cpq_read_regs(addr + 1, priv)) << 8);
return ret;
}
static uint32_t
cpq_read_regsl(uint32_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = cpq_read_regsw(addr, priv);
ret |= (((uint32_t) cpq_read_regsw(addr + 2, priv)) << 16);
return ret;
}
static void
cpq_recalc_state(cpq_386_t *dev, uint8_t i)
{
uint32_t addr;
addr = ((uint32_t) i) << 16;
if (dev->mem_state[i] == 0x00)
mem_set_mem_state(addr, 0x00010000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else if (dev->mem_state[i] == MEM_STATE_WP)
mem_set_mem_state(addr, 0x00010000, MEM_READ_EXTANY | MEM_WRITE_DISABLED);
else if (dev->mem_state[i] & MEM_STATE_WP)
mem_set_mem_state(addr, 0x00010000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(addr, 0x00010000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
dev->old_state[i] = dev->mem_state[i];
}
static void
cpq_recalc_states(cpq_386_t *dev)
{
/* Recalculate the entire 16 MB space. */
for (uint16_t i = 0; i < 256; i++) {
if (dev->mem_state[i] != dev->old_state[i])
cpq_recalc_state(dev, i);
}
flushmmucache_nopc();
}
static void
cpq_recalc_cache(cpq_386_t *dev)
{
cpu_cache_ext_enabled = (dev->regs[0x00000002] & 0x40);
cpu_update_waitstates();
}
static void
cpq_recalc_ram(cpq_386_t *dev)
{
uint8_t sys_ram = (dev->regs[0x00000001] & RAM_DIAG_H_SYS_RAM_MASK) & 0x01;
uint8_t setup_port = dev->regs[0x00000002] & 0x0f;
uint8_t sys_min_high = sys_ram ? 0xfa : 0xf4;
uint8_t ram_states[4] = { MEM_STATE_SYS, MEM_STATE_MOD_A,
MEM_STATE_MOD_B, MEM_STATE_MOD_C };
uint8_t ram_bases[4][2][16] = { { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x10, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10 } },
{ { 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00 },
{ 0x40, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40 } },
{ { 0x00, 0x00, 0x00, 0x20, 0x20, 0x00, 0x20, 0x20,
0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 },
{ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x50,
0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 } },
{ { 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x60,
0x00, 0x00, 0x90, 0x90, 0x90, 0x90, 0x00, 0x00 },
{ 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
0x00, 0x00, 0x90, 0x00, 0x00, 0xc0, 0xc0, 0xc0 } } };
uint8_t ram_sizes[4][2][16] = { { { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x30, 0x00, 0x10, 0x20, 0x30, 0x30, 0x30, 0x30,
0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30 } },
{ { 0x00, 0x00, 0x10, 0x10, 0x10, 0x40, 0x10, 0x10,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00 },
{ 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x10,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40 } },
{ { 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 0x40, 0x40,
0x30, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00 },
{ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x10,
0x00, 0x10, 0x10, 0x30, 0x40, 0x40, 0x40, 0x40 } },
{ { 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x10,
0x00, 0x00, 0x10, 0x20, 0x30, 0x40, 0x00, 0x00 },
{ 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
0x00, 0x00, 0x10, 0x00, 0x00, 0x10, 0x20, 0x30 } } };
uint8_t size;
uint8_t start;
uint8_t end;
uint8_t k;
uint32_t virt_base;
cpq_ram_t *cram;
for (uint16_t i = 0x10; i < sys_min_high; i++)
dev->mem_state[i] &= ~MEM_STATE_MASK;
for (uint8_t i = 0; i < 4; i++) {
for (uint8_t j = 0; j <= 64; j++) {
if ((i >= 1) || (j >= 0x10))
mem_mapping_disable(&dev->ram[i][j].mapping);
}
}
for (uint8_t i = 0; i < 4; i++) {
size = ram_sizes[i][sys_ram][setup_port];
if (size > 0x00) {
start = ram_bases[i][sys_ram][setup_port];
end = start + (size - 1);
virt_base = ((uint32_t) start) << 16;
for (uint16_t j = start; j <= end; j++) {
k = j - start;
if (i == 0)
k += 0x10;
cram = &(dev->ram[i][k]);
dev->mem_state[j] |= ram_states[i];
cram->virt_base = ((uint32_t) j) << 16;
cram->phys_base = cram->virt_base - virt_base + dev->ram_bases[i];
mem_mapping_set_addr(&cram->mapping, cram->virt_base, 0x00010000);
mem_mapping_set_exec(&cram->mapping, &(ram[cram->phys_base]));
}
}
}
/* Recalculate the entire 16 MB space. */
cpq_recalc_states(dev);
}
static void
cpq_write_regs(uint32_t addr, uint8_t val, void *priv)
{
cpq_386_t *dev = (cpq_386_t *) priv;
addr &= 0x00000fff;
switch (addr) {
case 0x00000000:
case 0x00000001:
/* RAM Relocation (Write Only) */
dev->regs[addr + 4] = val;
if (addr == 0x00000000) {
dev->mem_state[0x0e] &= ~(MEM_STATE_SYS | MEM_STATE_WP);
dev->mem_state[0x0f] &= ~(MEM_STATE_SYS | MEM_STATE_WP);
dev->mem_state[0xfe] &= ~MEM_STATE_WP;
dev->mem_state[0xff] &= ~MEM_STATE_WP;
if (!(val & 0x01)) {
dev->mem_state[0x0e] |= MEM_STATE_SYS;
dev->mem_state[0x0f] |= MEM_STATE_SYS;
}
if (!(val & 0x02)) {
dev->mem_state[0x0e] |= MEM_STATE_WP;
dev->mem_state[0x0f] |= MEM_STATE_WP;
dev->mem_state[0xfe] |= MEM_STATE_WP;
dev->mem_state[0xff] |= MEM_STATE_WP;
}
cpq_recalc_state(dev, 0x0e);
cpq_recalc_state(dev, 0x0f);
cpq_recalc_state(dev, 0xfe);
cpq_recalc_state(dev, 0xff);
flushmmucache_nopc();
}
break;
case 0x00000002:
case 0x00000003:
/* RAM Setup Port (Read/Write) */
dev->regs[addr] = val;
if (addr == 0x00000002) {
cpq_recalc_ram(dev);
cpq_recalc_cache(dev);
}
break;
default:
break;
}
}
static void
cpq_write_regsw(uint32_t addr, uint16_t val, void *priv)
{
cpq_write_regs(addr, val & 0xff, priv);
cpq_write_regs(addr + 1, (val >> 8) & 0xff, priv);
}
static void
cpq_write_regsl(uint32_t addr, uint32_t val, void *priv)
{
cpq_write_regsw(addr, val & 0xff, priv);
cpq_write_regsw(addr + 2, (val >> 16) & 0xff, priv);
}
static void
compaq_ram_init(cpq_ram_t *dev)
{
mem_mapping_add(&dev->mapping,
0x00000000,
0x00010000,
cpq_read_ram,
cpq_read_ramw,
cpq_read_raml,
cpq_write_ram,
cpq_write_ramw,
cpq_write_raml,
NULL,
MEM_MAPPING_INTERNAL,
dev);
mem_mapping_disable(&dev->mapping);
}
static void
compaq_ram_diags_parse(cpq_386_t *dev)
{
uint8_t val = dev->regs[0x00000001];
uint32_t accum = 0x00100000;
for (uint8_t i = 0; i < 4; i++) {
dev->ram_bases[i] = accum;
switch (val & 0x03) {
case RAM_DIAG_H_SYS_RAM_1MB:
dev->ram_sizes[i] = 0x00100000;
break;
case RAM_DIAG_H_SYS_RAM_4MB:
dev->ram_sizes[i] = 0x00400000;
break;
default:
break;
}
if (i == 0)
dev->ram_sizes[i] -= 0x00100000;
dev->ram_map_sizes[i] = dev->ram_sizes[i];
accum += dev->ram_sizes[i];
if (accum >= (mem_size << 10)) {
dev->ram_sizes[i] = (mem_size << 10) - dev->ram_bases[i];
break;
}
val >>= 2;
}
}
static void
compaq_recalc_base_ram(cpq_386_t *dev)
{
uint8_t base_mem = dev->regs[0x00000000] & RAM_DIAG_L_BASE_MEM_MASK;
uint8_t sys_ram = dev->regs[0x00000001] & RAM_DIAG_H_SYS_RAM_MASK;
uint8_t low_start = 0x00;
uint8_t low_end = 0x00;
uint8_t high_start = 0x00;
uint8_t high_end = 0x00;
cpq_ram_t *cram;
switch (base_mem) {
case RAM_DIAG_L_BASE_MEM_256KB:
switch (sys_ram) {
case RAM_DIAG_H_SYS_RAM_1MB:
low_start = 0x00;
low_end = 0x03;
high_start = 0xf4;
high_end = 0xff;
break;
case RAM_DIAG_H_SYS_RAM_4MB:
low_start = 0x00;
low_end = 0x03;
high_start = 0xfa;
high_end = 0xff;
break;
default:
fatal("Compaq 386 - Invalid configuation: %02X %02X\n", base_mem, sys_ram);
return;
}
break;
case RAM_DIAG_L_BASE_MEM_512KB:
switch (sys_ram) {
case RAM_DIAG_H_SYS_RAM_1MB:
low_start = 0x00;
low_end = 0x07;
high_start = 0xf8;
high_end = 0xff;
break;
case RAM_DIAG_H_SYS_RAM_4MB:
low_start = 0x00;
low_end = 0x07;
high_start = 0xfa;
high_end = 0xff;
break;
default:
fatal("Compaq 386 - Invalid configuation: %02X %02X\n", base_mem, sys_ram);
return;
}
break;
case RAM_DIAG_L_BASE_MEM_640KB:
switch (sys_ram) {
case RAM_DIAG_H_SYS_RAM_1MB:
low_start = 0x00;
low_end = 0x09;
high_start = 0xfa;
high_end = 0xff;
break;
case RAM_DIAG_H_SYS_RAM_4MB:
low_start = 0x00;
low_end = 0x09;
high_start = 0xfa;
high_end = 0xff;
break;
default:
fatal("Compaq 386 - Invalid configuation: %02X %02X\n", base_mem, sys_ram);
return;
}
break;
default:
fatal("Compaq 386 - Invalid configuation: %02X %02X\n", base_mem, sys_ram);
return;
}
switch (sys_ram) {
case RAM_DIAG_H_SYS_RAM_1MB:
if (mem_size < 1024)
dev->regs[0x00000002] = 0x01;
else if (mem_size == 8192)
dev->regs[0x00000002] = 0x09;
else if (mem_size >= 11264)
dev->regs[0x00000002] = 0x0d;
else
dev->regs[0x00000002] = (mem_size >> 10);
break;
case RAM_DIAG_H_SYS_RAM_4MB:
if (mem_size < 4096)
dev->regs[0x00000002] = 0x04;
else if (mem_size == 11264)
dev->regs[0x00000002] = 0x0c;
else if (mem_size >= 16384)
dev->regs[0x00000002] = 0x00;
else if (mem_size > 13312)
dev->regs[0x00000002] = 0x0d;
else
dev->regs[0x00000002] = (mem_size >> 10);
break;
default:
fatal("Compaq 386 - Invalid configuation: %02X\n", sys_ram);
return;
}
/* The base 640 kB. */
for (uint8_t i = low_start; i <= low_end; i++) {
cram = &(dev->ram[0][i]);
cram->phys_base = cram->virt_base = ((uint32_t) i) << 16;
dev->mem_state[i] |= MEM_STATE_SYS;
mem_mapping_set_addr(&cram->mapping, cram->virt_base, 0x00010000);
mem_mapping_set_exec(&cram->mapping, &(ram[cram->phys_base]));
cpq_recalc_state(dev, i);
}
/* The relocated 128 kB. */
for (uint8_t i = 0x0e; i <= 0x0f; i++) {
cram = &(dev->ram[0][i]);
cram->phys_base = cram->virt_base = ((uint32_t) i) << 16;
mem_mapping_set_addr(&cram->mapping, cram->virt_base, 0x00010000);
mem_mapping_set_exec(&cram->mapping, &(ram[cram->phys_base]));
}
/* Blocks FA-FF. */
for (uint16_t i = high_start; i <= high_end; i++) {
cram = &(dev->high_ram[i & 0x0f]);
cram->phys_base = ((uint32_t) (i & 0x0f)) << 16;
cram->virt_base = ((uint32_t) i) << 16;
dev->mem_state[i] |= MEM_STATE_SYS;
mem_mapping_set_addr(&cram->mapping, cram->virt_base, 0x00010000);
mem_mapping_set_exec(&cram->mapping, &(ram[cram->phys_base]));
cpq_recalc_state(dev, i);
}
}
static void
compaq_386_close(void *priv)
{
cpq_386_t *dev = (cpq_386_t *) priv;
free(dev);
}
static void *
compaq_386_init(UNUSED(const device_t *info))
{
cpq_386_t *dev = (cpq_386_t *) calloc(1, sizeof(cpq_386_t));
mem_mapping_add(&dev->regs_mapping,
0x80c00000,
0x00001000,
cpq_read_regs,
cpq_read_regsw,
cpq_read_regsl,
cpq_write_regs,
cpq_write_regsw,
cpq_write_regsl,
NULL,
MEM_MAPPING_INTERNAL,
dev);
mem_set_mem_state(0x80c00000, 0x00001000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
dev->regs[0x00000000] = RAM_DIAG_L_PERMA_BITS;
if (mem_size >= 640)
dev->regs[0x00000000] |= RAM_DIAG_L_BASE_MEM_640KB;
else if (mem_size >= 512)
dev->regs[0x00000000] |= RAM_DIAG_L_BASE_MEM_512KB;
else if (mem_size >= 256)
dev->regs[0x00000000] |= RAM_DIAG_L_BASE_MEM_256KB;
else
dev->regs[0x00000000] |= RAM_DIAG_L_BASE_MEM_INV;
/* Indicate no parity error. */
dev->regs[0x00000000] |= 0x0f;
if (mem_size >= 1024) {
switch (mem_size) {
case 1024:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_NONE |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 2048:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_NONE |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 3072:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_NONE |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 4096:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_NONE |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 5120:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_1MB |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 6144:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_1MB |
RAM_DIAG_H_MOD_B_RAM_1MB | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 7168:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_1MB |
RAM_DIAG_H_MOD_B_RAM_1MB | RAM_DIAG_H_MOD_C_RAM_1MB;
break;
case 8192:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 9216:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_1MB | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 10240:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_1MB | RAM_DIAG_H_MOD_C_RAM_1MB;
break;
case 11264:
case 12288:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_4MB | RAM_DIAG_H_MOD_C_RAM_NONE;
break;
case 13312:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_4MB | RAM_DIAG_H_MOD_C_RAM_1MB;
break;
case 14336:
case 15360:
case 16384:
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_4MB | RAM_DIAG_H_MOD_A_RAM_4MB |
RAM_DIAG_H_MOD_B_RAM_4MB | RAM_DIAG_H_MOD_C_RAM_4MB;
break;
default:
break;
}
} else
dev->regs[0x00000001] = RAM_DIAG_H_SYS_RAM_1MB | RAM_DIAG_H_MOD_A_RAM_NONE |
RAM_DIAG_H_MOD_B_RAM_NONE | RAM_DIAG_H_MOD_C_RAM_NONE;
dev->regs[0x00000003] = 0xfc;
dev->regs[0x00000004] = dev->regs[0x00000005] = 0xff;
compaq_ram_diags_parse(dev);
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
/* Should never be the case, but you never know what a user may set. */
if (mem_size > 1048576)
mem_mapping_disable(&ram_2gb_mapping);
#endif
/* Initialize in reverse order for memory mapping precedence
reasons. */
for (int8_t i = 3; i >= 0; i--) {
for (uint8_t j = 0; j < 64; j++)
compaq_ram_init(&(dev->ram[i][j]));
}
for (uint8_t i = 0; i < 16; i++)
compaq_ram_init(&(dev->high_ram[i]));
/* First, set the entire 256 MB of space to invalid states. */
for (uint16_t i = 0; i < 256; i++)
dev->old_state[i] = 0xff;
/* Then, recalculate the base RAM mappings. */
compaq_recalc_base_ram(dev);
/* Enable the external cache. */
dev->regs[0x00000002] |= 0x40;
cpq_recalc_cache(dev);
/* Recalculate the rest of the RAM mapping. */
cpq_recalc_ram(dev);
return dev;
}
static void
compaq_genoa_outw(uint16_t port, uint16_t val, void *priv)
{
if (port == 0x0c02)
cpq_write_regs(0x80c00000, val, priv);
}
static void *
compaq_genoa_init(UNUSED(const device_t *info))
{
void *cpq = device_add(&compaq_386_device);
io_sethandler(0x0c02, 2, NULL, NULL, NULL, NULL, compaq_genoa_outw, NULL, cpq);
return ram;
}
const device_t compaq_386_device = {
.name = "Compaq 386 Memory Control",
.internal_name = "compaq_386",
.flags = 0,
.local = 0,
.init = compaq_386_init,
.close = compaq_386_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t compaq_genoa_device = {
.name = "Compaq Genoa Memory Control",
.internal_name = "compaq_genoa",
.flags = 0,
.local = 0,
.init = compaq_genoa_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/compaq_386.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,122 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of Intel 82420EX chipset that acts as both the
* northbridge and the southbridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#define USE_DRB_HACK
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#ifndef USE_DRB_HACK
#include <86box/row.h>
#endif
#define MEM_STATE_SHADOW_R 0x01
#define MEM_STATE_SHADOW_W 0x02
#define MEM_STATE_SMRAM 0x04
typedef struct i420ex_t {
uint8_t has_ide;
uint8_t smram_locked;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[256];
uint16_t timer_base;
uint16_t timer_latch;
smram_t *smram;
double fast_off_period;
pc_timer_t timer;
pc_timer_t fast_off_timer;
apm_t *apm;
port_92_t *port_92;
} i420ex_t;
#ifdef ENABLE_I420EX_LOG
int i420ex_do_log = ENABLE_I420EX_LOG;
static void
i420ex_log(const char *fmt, ...)
{
va_list ap;
if (i420ex_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i420ex_log(fmt, ...)
#endif
static void
i420ex_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3) {
case 0:
mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
}
static void
i420ex_smram_handler_phase0(void)
{
/* Disable low extended SMRAM. */
smram_disable_all();
}
static void
i420ex_smram_handler_phase1(i420ex_t *dev)
{
const uint8_t *regs = (uint8_t *) dev->regs;
uint32_t host_base = 0x000a0000;
uint32_t ram_base = 0x000a0000;
uint32_t size = 0x00010000;
switch (regs[0x70] & 0x07) {
default:
case 0:
case 1:
host_base = ram_base = 0x00000000;
size = 0x00000000;
break;
case 2:
host_base = 0x000a0000;
ram_base = 0x000a0000;
break;
case 3:
host_base = 0x000b0000;
ram_base = 0x000b0000;
break;
case 4:
host_base = 0x000c0000;
ram_base = 0x000a0000;
break;
case 5:
host_base = 0x000d0000;
ram_base = 0x000a0000;
break;
case 6:
host_base = 0x000e0000;
ram_base = 0x000a0000;
break;
case 7:
host_base = 0x000f0000;
ram_base = 0x000a0000;
break;
}
smram_enable(dev->smram, host_base, ram_base, size,
(regs[0x70] & 0x70) == 0x40, !(regs[0x70] & 0x20));
}
#ifndef USE_DRB_HACK
static void
i420ex_drb_recalc(i420ex_t *dev)
{
uint32_t boundary;
for (int8_t i = 4; i >= 0; i--)
row_disable(i);
for (uint8_t i = 0; i <= 4; i++) {
boundary = ((uint32_t) dev->regs[0x60 + i]) & 0xff;
row_set_boundary(i, boundary);
}
flushmmucache();
}
#endif
static void
i420ex_write(int func, int addr, uint8_t val, void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
if (func > 0)
return;
if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40))
return;
switch (addr) {
case 0x05:
dev->regs[addr] = (val & 0x01);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0xf0);
break;
case 0x40:
dev->regs[addr] = (val & 0x7f);
break;
case 0x44:
dev->regs[addr] = (val & 0x07);
break;
case 0x48:
dev->regs[addr] = (val & 0x3f);
if (dev->has_ide) {
ide_pri_disable();
switch (val & 0x03) {
case 0x01:
ide_set_base(0, 0x01f0);
ide_set_side(0, 0x03f6);
ide_pri_enable();
break;
case 0x02:
ide_set_base(0, 0x0170);
ide_set_side(0, 0x0376);
ide_pri_enable();
break;
default:
break;
}
}
break;
case 0x49:
case 0x53:
dev->regs[addr] = (val & 0x1f);
break;
case 0x4c:
case 0x51:
case 0x57:
case 0x68:
case 0x69:
dev->regs[addr] = val;
if (addr == 0x4c) {
dma_alias_remove();
if (!(val & 0x80))
dma_alias_set();
}
break;
case 0x4d:
dev->regs[addr] = (dev->regs[addr] & 0xef) | (val & 0x10);
break;
case 0x4e:
dev->regs[addr] = (val & 0xf7);
break;
case 0x50:
dev->regs[addr] = (val & 0x0f);
break;
case 0x52:
dev->regs[addr] = (val & 0x7f);
break;
case 0x56:
dev->regs[addr] = (val & 0x3e);
break;
case 0x59: /* PAM0 */
if ((dev->regs[0x59] ^ val) & 0xf0) {
i420ex_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
dev->regs[0x59] = val & 0xf0;
break;
case 0x5a: /* PAM1 */
if ((dev->regs[0x5a] ^ val) & 0x0f)
i420ex_map(0xc0000, 0x04000, val & 0xf);
if ((dev->regs[0x5a] ^ val) & 0xf0)
i420ex_map(0xc4000, 0x04000, val >> 4);
dev->regs[0x5a] = val;
break;
case 0x5b: /*PAM2 */
if ((dev->regs[0x5b] ^ val) & 0x0f)
i420ex_map(0xc8000, 0x04000, val & 0xf);
if ((dev->regs[0x5b] ^ val) & 0xf0)
i420ex_map(0xcc000, 0x04000, val >> 4);
dev->regs[0x5b] = val;
break;
case 0x5c: /*PAM3 */
if ((dev->regs[0x5c] ^ val) & 0x0f)
i420ex_map(0xd0000, 0x04000, val & 0xf);
if ((dev->regs[0x5c] ^ val) & 0xf0)
i420ex_map(0xd4000, 0x04000, val >> 4);
dev->regs[0x5c] = val;
break;
case 0x5d: /* PAM4 */
if ((dev->regs[0x5d] ^ val) & 0x0f)
i420ex_map(0xd8000, 0x04000, val & 0xf);
if ((dev->regs[0x5d] ^ val) & 0xf0)
i420ex_map(0xdc000, 0x04000, val >> 4);
dev->regs[0x5d] = val;
break;
case 0x5e: /* PAM5 */
if ((dev->regs[0x5e] ^ val) & 0x0f)
i420ex_map(0xe0000, 0x04000, val & 0xf);
if ((dev->regs[0x5e] ^ val) & 0xf0)
i420ex_map(0xe4000, 0x04000, val >> 4);
dev->regs[0x5e] = val;
break;
case 0x5f: /* PAM6 */
if ((dev->regs[0x5f] ^ val) & 0x0f)
i420ex_map(0xe8000, 0x04000, val & 0xf);
if ((dev->regs[0x5f] ^ val) & 0xf0)
i420ex_map(0xec000, 0x04000, val >> 4);
dev->regs[0x5f] = val;
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
case 0x64:
#ifdef USE_DRB_HACK
spd_write_drbs(dev->regs, 0x60, 0x64, 1);
#else
dev->regs[addr] = val;
i420ex_drb_recalc(dev);
#endif
break;
case 0x66:
case 0x67:
i420ex_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x01), val);
dev->regs[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr & 0x01), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr & 0x01), val & 0xf);
break;
case 0x70: /* SMRAM */
i420ex_smram_handler_phase0();
if (dev->smram_locked)
dev->regs[0x70] = (dev->regs[0x70] & 0xdf) | (val & 0x20);
else {
dev->regs[0x70] = (dev->regs[0x70] & 0x88) | (val & 0x77);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
dev->regs[0x70] &= 0xbf;
}
i420ex_smram_handler_phase1(dev);
break;
case 0xa0:
dev->regs[addr] = val & 0x1f;
apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80));
switch ((val & 0x18) >> 3) {
case 0x00:
dev->fast_off_period = PCICLK * 32768.0 * 60000.0;
break;
case 0x01:
default:
dev->fast_off_period = 0.0;
break;
case 0x02:
dev->fast_off_period = PCICLK;
break;
case 0x03:
dev->fast_off_period = PCICLK * 32768.0;
break;
}
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
break;
case 0xa2:
dev->regs[addr] = val & 0xff;
apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80));
break;
case 0xaa:
dev->regs[addr] &= (val & 0xff);
break;
case 0xac:
case 0xae:
dev->regs[addr] = val & 0xff;
break;
case 0xa4:
dev->regs[addr] = val & 0xfb;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr];
break;
case 0xa5:
dev->regs[addr] = val;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8);
break;
case 0xa7:
dev->regs[addr] = val & 0xe0;
cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24);
break;
case 0xa8:
dev->regs[addr] = val & 0xff;
cpu_fast_off_val = val;
cpu_fast_off_count = val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
break;
default:
break;
}
}
static uint8_t
i420ex_read(int func, int addr, void *priv)
{
const i420ex_t *dev = (i420ex_t *) priv;
uint8_t ret;
ret = 0xff;
if (func == 0)
ret = dev->regs[addr];
return ret;
}
static void
i420ex_reset_hard(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
memset(dev->regs, 0, 256);
dev->regs[0x00] = 0x86;
dev->regs[0x01] = 0x80; /*Intel*/
dev->regs[0x02] = 0x86;
dev->regs[0x03] = 0x04; /*82378IB (I420EX)*/
dev->regs[0x04] = 0x07;
dev->regs[0x07] = 0x02;
dev->regs[0x4c] = 0x4d;
dev->regs[0x4e] = 0x03;
/* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */
if (cpu_busspeed >= 33333333)
dev->regs[0x50] |= 0x02;
dev->regs[0x51] = 0x80;
dev->regs[0x60] = dev->regs[0x61] = dev->regs[0x62] = dev->regs[0x63] = dev->regs[0x64] = 0x01;
dev->regs[0x66] = 0x80;
dev->regs[0x67] = 0x80;
dev->regs[0x69] = 0x02;
dev->regs[0xa0] = 0x08;
dev->regs[0xa8] = 0x0f;
mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
if (dev->has_ide)
ide_pri_disable();
}
static void
i420ex_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
if (dev->apm->do_smi)
dev->regs[0xaa] |= 0x80;
}
static void
i420ex_fast_off_count(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
cpu_fast_off_count--;
smi_raise();
dev->regs[0xaa] |= 0x20;
}
static void
i420ex_reset(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
i420ex_write(0, 0x48, 0x00, priv);
/* Disable the PIC mouse latch. */
i420ex_write(0, 0x4e, 0x03, priv);
for (uint8_t i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, priv);
for (uint8_t i = 0; i <= 4; i++)
dev->regs[0x60 + i] = 0x01;
dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
dev->smram_locked = 0;
i420ex_write(0, 0x70, 0x00, priv);
mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
i420ex_write(0, 0xa0, 0x08, priv);
i420ex_write(0, 0xa2, 0x00, priv);
i420ex_write(0, 0xa4, 0x00, priv);
i420ex_write(0, 0xa5, 0x00, priv);
i420ex_write(0, 0xa6, 0x00, priv);
i420ex_write(0, 0xa7, 0x00, priv);
i420ex_write(0, 0xa8, 0x0f, priv);
}
static void
i420ex_close(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void
i420ex_speed_changed(void *priv)
{
i420ex_t *dev = (i420ex_t *) priv;
int te;
te = timer_is_enabled(&dev->timer);
timer_disable(&dev->timer);
if (te)
timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
te = timer_is_on(&dev->fast_off_timer);
timer_stop(&dev->fast_off_timer);
if (te)
timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
}
static void *
i420ex_init(const device_t *info)
{
i420ex_t *dev = (i420ex_t *) malloc(sizeof(i420ex_t));
memset(dev, 0, sizeof(i420ex_t));
dev->smram = smram_add();
pci_add_card(PCI_ADD_NORTHBRIDGE, i420ex_read, i420ex_write, dev, &dev->pci_slot);
dev->has_ide = info->local;
timer_add(&dev->fast_off_timer, i420ex_fast_off_count, dev, 0);
cpu_fast_off_flags = 0x00000000;
cpu_fast_off_val = dev->regs[0xa8];
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_register_fast_off_handler(&dev->fast_off_timer);
dev->apm = device_add(&apm_pci_device);
/* APM intercept handler to update 82420EX SMI status on APM SMI. */
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, i420ex_apm_out, NULL, NULL, dev);
dev->port_92 = device_add(&port_92_pci_device);
dma_alias_set();
device_add(&ide_pci_2ch_device);
#ifndef USE_DRB_HACK
row_device.local = 4 | (1 << 8) | (0x01 << 16) | (8 << 24);
device_add((const device_t *) &row_device);
#endif
i420ex_reset_hard(dev);
return dev;
}
const device_t i420ex_device = {
.name = "Intel 82420EX",
.internal_name = "i420ex",
.flags = DEVICE_PCI,
.local = 0x00,
.init = i420ex_init,
.close = i420ex_close,
.reset = i420ex_reset,
{ .available = NULL },
.speed_changed = i420ex_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t i420ex_ide_device = {
.name = "Intel 82420EX (With IDE)",
.internal_name = "i420ex_ide",
.flags = DEVICE_PCI,
.local = 0x01,
.init = i420ex_init,
.close = i420ex_close,
.reset = i420ex_reset,
{ .available = NULL },
.speed_changed = i420ex_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_420ex.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,432 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1543 Desktop South Bridge.
*
*
*
* Authors: Tiseno100,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/ddma.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/sio.h>
#include <86box/smbus.h>
#include <86box/usb.h>
#include <86box/acpi.h>
#include <86box/chipset.h>
typedef struct ali1543_t {
uint8_t mirq_states[8];
uint8_t pci_conf[256];
uint8_t pmu_conf[256];
uint8_t usb_conf[256];
uint8_t ide_conf[256];
uint8_t pci_slot;
uint8_t ide_slot;
uint8_t usb_slot;
uint8_t pmu_slot;
uint8_t usb_dev_enable;
uint8_t ide_dev_enable;
uint8_t pmu_dev_enable;
uint8_t type;
int offset;
apm_t *apm;
acpi_t *acpi;
ddma_t *ddma;
nvr_t *nvr;
port_92_t *port_92;
sff8038i_t *ide_controller[2];
smbus_ali7101_t *smbus;
usb_t *usb;
} ali1543_t;
/*
Notes:
- Power Managment isn't functioning properly
- IDE isn't functioning properly
- 1543C differences have to be examined
- Some Chipset functionality might be missing
- Device numbers and types might be incorrect
- Code quality is abysmal and needs lot's of cleanup.
*/
int ali1533_irq_routing[16] = { PCI_IRQ_DISABLED, 9, 3, 10, 4, 5, 7, 6,
1, 11, PCI_IRQ_DISABLED, 12, PCI_IRQ_DISABLED, 14, PCI_IRQ_DISABLED, 15 };
#ifdef ENABLE_ALI1543_LOG
int ali1543_do_log = ENABLE_ALI1543_LOG;
static void
ali1543_log(const char *fmt, ...)
{
va_list ap;
if (ali1543_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1543_log(fmt, ...)
#endif
static void
ali1533_ddma_handler(UNUSED(ali1543_t *dev))
{
/* TODO: Find any documentation that actually explains the ALi southbridge DDMA mapping. */
}
static void ali5229_ide_handler(ali1543_t *dev);
static void ali5229_ide_irq_handler(ali1543_t *dev);
static void ali5229_write(int func, int addr, uint8_t val, void *priv);
static void ali7101_write(int func, int addr, uint8_t val, void *priv);
static uint8_t ali7101_read(int func, int addr, void *priv);
static void
ali1533_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
switch (addr) {
case 0x04: /* Command Register */
if (dev->type == 1) {
if (dev->pci_conf[0x5f] & 0x08)
dev->pci_conf[0x04] = val & 0x0f;
else
dev->pci_conf[0x04] = val;
} else {
if (!(dev->pci_conf[0x5f] & 0x08))
dev->pci_conf[0x04] = val;
}
break;
case 0x05: /* Command Register */
if (!(dev->pci_conf[0x5f] & 0x08))
dev->pci_conf[0x04] = val & 0x03;
break;
case 0x07: /* Status Byte */
dev->pci_conf[addr] &= ~(val & 0x30);
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (!(dev->pci_conf[0x74] & 0x40))
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x41:
dev->pci_conf[addr] = val;
break;
case 0x42: /* ISA Bus Speed */
dev->pci_conf[addr] = val & 0xcf;
switch (val & 7) {
case 0:
cpu_set_isa_speed(7159091);
break;
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
cpu_set_isa_pci_div((val & 7) + 1);
break;
default:
break;
}
break;
case 0x43:
dev->pci_conf[addr] = val;
if (val & 0x80)
port_92_add(dev->port_92);
else
port_92_remove(dev->port_92);
break;
/* We're going to cheat a little bit here and use MIRQ's as a substitute for the ALi's INTAJ's,
as they work pretty much the same - specifically, we're going to use MIRQ2 and MIRQ3 for them,
as MIRQ0 and MIRQ1 map to the ALi's MBIRQ0 and MBIRQ1. */
case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */
dev->pci_conf[addr] = val & 0xdf;
soft_reset_pci = !!(val & 0x80);
pci_set_mirq_level(PCI_MIRQ0, !(val & 0x10));
pci_set_mirq_level(PCI_MIRQ2, !(val & 0x10));
ali1543_log("INTAJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ2, ali1533_irq_routing[val & 0x0f]);
break;
/* TODO: Implement a ROMCS# assertion bitmask for I/O ports. */
case 0x45: /* DDMA Enable */
dev->pci_conf[addr] = val & 0xcb;
ali1533_ddma_handler(dev);
break;
/* TODO: For 0x47, we need a way to obtain the memory state for an address
and toggle ROMCS#. */
case 0x47: /* BIOS chip select control */
dev->pci_conf[addr] = val;
break;
/* PCI IRQ Routing */
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
dev->pci_conf[addr] = val;
pci_set_irq_routing(((addr & 0x03) << 1) + 2, ali1533_irq_routing[(val >> 4) & 0x0f]);
pci_set_irq_routing(((addr & 0x03) << 1) + 1, ali1533_irq_routing[val & 0x0f]);
break;
case 0x4c: /* PCI INT to ISA Level to Edge transfer */
dev->pci_conf[addr] = val;
for (uint8_t irq = 1; irq < 9; irq++)
pci_set_irq_level(irq, !(val & (1 << (irq - 1))));
break;
case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */
if (dev->type == 0) {
dev->pci_conf[addr] = val;
ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
#if 0
pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
#endif
}
break;
/* I/O cycle posted-write first port definition */
case 0x50:
dev->pci_conf[addr] = val;
break;
case 0x51:
dev->pci_conf[addr] = val & 0x8f;
break;
/* I/O cycle posted-write second port definition */
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53:
if (dev->type == 1)
dev->pci_conf[addr] = val;
else
dev->pci_conf[addr] = val & 0xcf;
/* This actually enables/disables the USB *device* rather than the interface itself. */
dev->usb_dev_enable = !(val & 0x40);
if (dev->type == 1) {
nvr_at_index_read_handler(0, 0x0070, dev->nvr);
nvr_at_index_read_handler(0, 0x0072, dev->nvr);
if (val & 0x20) {
nvr_at_index_read_handler(1, 0x0070, dev->nvr);
nvr_at_index_read_handler(1, 0x0072, dev->nvr);
}
}
break;
/* Hardware setting status bits, read-only (register 0x54) */
/* Programmable chip select (pin PCSJ) address define */
case 0x55:
case 0x56:
dev->pci_conf[addr] = val;
break;
case 0x57:
if (dev->type == 1)
dev->pci_conf[addr] = val & 0xf0;
else
dev->pci_conf[addr] = val & 0xe0;
break;
/* IDE interface control */
case 0x58:
dev->pci_conf[addr] = val & 0x7f;
ali1543_log("PCI58: %02X\n", val);
dev->ide_dev_enable = !!(val & 0x40);
switch (val & 0x30) {
case 0x00:
dev->ide_slot = 0x10; /* A27 = slot 16 */
break;
case 0x10:
dev->ide_slot = 0x0f; /* A26 = slot 15 */
break;
case 0x20:
dev->ide_slot = 0x0e; /* A25 = slot 14 */
break;
case 0x30:
dev->ide_slot = 0x0d; /* A24 = slot 13 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_IDE, ((int) dev->ide_slot) + dev->offset);
ali1543_log("IDE slot = %02X (A%0i)\n", ((int) dev->ide_slot) + dev->offset, dev->ide_slot + 11);
ali5229_ide_irq_handler(dev);
break;
/* General Purpose input multiplexed pin(GPI) select */
case 0x59:
dev->pci_conf[addr] = val & 0x0e;
break;
/* General Purpose output multiplexed pin(GPO) select low */
case 0x5a:
dev->pci_conf[addr] = val & 0x0f;
break;
/* General Purpose output multiplexed pin(GPO) select high */
case 0x5b:
dev->pci_conf[addr] = val & 0x02;
break;
case 0x5c:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x02;
break;
case 0x5e:
if (dev->type == 1)
dev->pci_conf[addr] = val & 0xe1;
else
dev->pci_conf[addr] = val & 0xe0;
break;
case 0x5f:
dev->pci_conf[addr] = val;
dev->pmu_dev_enable = !(val & 0x04);
break;
case 0x6c: /* Deleted - no idea what it used to do */
dev->pci_conf[addr] = val;
break;
case 0x6d:
dev->pci_conf[addr] = val & 0xbf;
break;
case 0x6e:
case 0x70:
dev->pci_conf[addr] = val;
break;
case 0x71:
dev->pci_conf[addr] = val & 0xef;
break;
case 0x72:
dev->pci_conf[addr] = val & 0xef;
switch (val & 0x0c) {
case 0x00:
dev->pmu_slot = 0x11; /* A28 = slot 17 */
break;
case 0x04:
dev->pmu_slot = 0x12; /* A29 = slot 18 */
break;
case 0x08:
dev->pmu_slot = 0x03; /* A14 = slot 03 */
break;
case 0x0c:
dev->pmu_slot = 0x04; /* A15 = slot 04 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_PMU, ((int) dev->pmu_slot) + dev->offset);
ali1543_log("PMU slot = %02X (A%0i)\n", ((int) dev->pmu_slot) + dev->offset, dev->pmu_slot + 11);
switch (val & 0x03) {
case 0x00:
dev->usb_slot = 0x14; /* A31 = slot 20 */
break;
case 0x01:
dev->usb_slot = 0x13; /* A30 = slot 19 */
break;
case 0x02:
dev->usb_slot = 0x02; /* A13 = slot 02 */
break;
case 0x03:
dev->usb_slot = 0x01; /* A12 = slot 01 */
break;
default:
break;
}
pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_USB, ((int) dev->usb_slot) + dev->offset);
ali1543_log("USB slot = %02X (A%0i)\n", ((int) dev->usb_slot) + dev->offset, dev->usb_slot + 11);
break;
case 0x73: /* DDMA Base Address */
dev->pci_conf[addr] = val;
ali1533_ddma_handler(dev);
break;
case 0x74: /* USB IRQ Routing - we cheat and use MIRQ4 */
dev->pci_conf[addr] = val & 0xdf;
/* TODO: MIRQ level/edge control - if bit 4 = 1, it's level */
pci_set_mirq_level(PCI_MIRQ4, !(val & 0x10));
pci_set_mirq_routing(PCI_MIRQ4, ali1533_irq_routing[val & 0x0f]);
break;
case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */
dev->pci_conf[addr] = val & 0x1f;
pci_set_mirq_level(PCI_MIRQ1, !(val & 0x10));
pci_set_mirq_level(PCI_MIRQ3, !(val & 0x10));
ali1543_log("INTBJ = IRQ %i\n", ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
pci_set_mirq_routing(PCI_MIRQ3, ali1533_irq_routing[val & 0x0f]);
break;
case 0x76: /* PMU IRQ Routing - we cheat and use MIRQ5 */
if (dev->type == 1)
dev->pci_conf[addr] = val & 0x9f;
else
dev->pci_conf[addr] = val & 0x1f;
acpi_set_mirq_is_level(dev->acpi, !!(val & 0x10));
if ((dev->type == 1) && (val & 0x80))
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ5, ali1533_irq_routing[val & 0x0f]);
/* TODO: Tell ACPI to use MIRQ5 */
break;
case 0x77: /* SMBus IRQ Routing - we cheat and use MIRQ6 */
dev->pci_conf[addr] = val & 0x1f;
pci_set_mirq_routing(PCI_MIRQ6, ali1533_irq_routing[val & 0x0f]);
break;
case 0x78:
if (dev->type == 1) {
ali1543_log("PCI78 = %02X\n", val);
dev->pci_conf[addr] = val & 0x33;
}
break;
case 0x7c ... 0xff:
if ((dev->type == 1) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ali7101_write(func, addr, val, priv);
dev->pmu_dev_enable = 0;
}
break;
default:
break;
}
}
static uint8_t
ali1533_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
if (func == 0) {
if (((dev->pci_conf[0x42] & 0x80) && (addr >= 0x40)) || ((dev->pci_conf[0x5f] & 8) && (addr == 4)))
ret = 0x00;
else {
ret = dev->pci_conf[addr];
if (addr == 0x58)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ret = ali7101_read(func, addr, priv);
dev->pmu_dev_enable = 0;
}
}
}
return ret;
}
static void
ali5229_ide_irq_handler(ali1543_t *dev)
{
int ctl = 0;
int bit = 0;
if (dev->ide_conf[0x52] & 0x10) {
ctl ^= 1;
bit ^= 5;
}
if (dev->ide_conf[0x09] & (1 ^ bit)) {
/* Primary IDE is native. */
ali1543_log("Primary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->ide_controller[ctl], IRQ_MODE_ALI_ALADDIN);
} else {
/* Primary IDE is legacy. */
switch (dev->pci_conf[0x58] & 0x03) {
case 0x00:
/* SIRQI, SIRQII */
ali1543_log("Primary IDE IRQ mode: SIRQI, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_1 : IRQ_MODE_MIRQ_0);
break;
case 0x01:
/* IRQ14, IRQ15 */
ali1543_log("Primary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->ide_controller[ctl], IRQ_MODE_LEGACY);
break;
case 0x02:
/* IRQ14, SIRQII */
ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_1 : IRQ_MODE_LEGACY);
break;
case 0x03:
/* IRQ14, SIRQI */
ali1543_log("Primary IDE IRQ mode: IRQ14, SIRQI\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_0 : IRQ_MODE_LEGACY);
break;
default:
break;
}
}
ctl ^= 1;
if (dev->ide_conf[0x09] & (4 ^ bit)) {
/* Secondary IDE is native. */
ali1543_log("Secondary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->ide_controller[ctl], IRQ_MODE_ALI_ALADDIN);
} else {
/* Secondary IDE is legacy. */
switch (dev->pci_conf[0x58] & 0x03) {
case 0x00:
/* SIRQI, SIRQII */
ali1543_log("Secondary IDE IRQ mode: SIRQI, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_1 : IRQ_MODE_MIRQ_0);
break;
case 0x01:
/* IRQ14, IRQ15 */
ali1543_log("Secondary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->ide_controller[ctl], IRQ_MODE_LEGACY);
break;
case 0x02:
/* IRQ14, SIRQII */
ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQII\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_1 : IRQ_MODE_LEGACY);
break;
case 0x03:
/* IRQ14, SIRQI */
ali1543_log("Secondary IDE IRQ mode: IRQ14, SIRQI\n");
sff_set_irq_mode(dev->ide_controller[ctl], ctl ? IRQ_MODE_MIRQ_0 : IRQ_MODE_LEGACY);
break;
default:
break;
}
}
}
static void
ali5229_ide_handler(ali1543_t *dev)
{
uint32_t ch = 0;
uint16_t native_base_pri_addr = (dev->ide_conf[0x11] | dev->ide_conf[0x10] << 8) & 0xfffe;
uint16_t native_side_pri_addr = (dev->ide_conf[0x15] | dev->ide_conf[0x14] << 8) & 0xfffe;
uint16_t native_base_sec_addr = (dev->ide_conf[0x19] | dev->ide_conf[0x18] << 8) & 0xfffe;
uint16_t native_side_sec_addr = (dev->ide_conf[0x1c] | dev->ide_conf[0x1b] << 8) & 0xfffe;
uint16_t comp_base_pri_addr = 0x01f0;
uint16_t comp_side_pri_addr = 0x03f6;
uint16_t comp_base_sec_addr = 0x0170;
uint16_t comp_side_sec_addr = 0x0376;
uint16_t current_pri_base;
uint16_t current_pri_side;
uint16_t current_sec_base;
uint16_t current_sec_side;
/* Primary Channel Programming */
if (dev->ide_conf[0x52] & 0x10) {
current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_sec_addr : native_base_sec_addr;
current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_sec_addr : native_side_sec_addr;
} else {
current_pri_base = (!(dev->ide_conf[0x09] & 1)) ? comp_base_pri_addr : native_base_pri_addr;
current_pri_side = (!(dev->ide_conf[0x09] & 1)) ? comp_side_pri_addr : native_side_pri_addr;
}
/* Secondary Channel Programming */
if (dev->ide_conf[0x52] & 0x10) {
current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_pri_addr : native_base_pri_addr;
current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_pri_addr : native_side_pri_addr;
} else {
current_sec_base = (!(dev->ide_conf[0x09] & 4)) ? comp_base_sec_addr : native_base_sec_addr;
current_sec_side = (!(dev->ide_conf[0x09] & 4)) ? comp_side_sec_addr : native_side_sec_addr;
}
if (dev->ide_conf[0x52] & 0x10)
ch ^= 8;
ali1543_log("ali5229_ide_handler(): Disabling primary IDE...\n");
ide_pri_disable();
ali1543_log("ali5229_ide_handler(): Disabling secondary IDE...\n");
ide_sec_disable();
if (dev->ide_conf[0x04] & 0x01) {
/* Primary Channel Setup */
if ((dev->ide_conf[0x09] & 0x20) || (dev->ide_conf[0x4d] & 0x80)) {
ali1543_log("ali5229_ide_handler(): Primary IDE base now %04X...\n", current_pri_base);
ide_set_base(0, current_pri_base);
ali1543_log("ali5229_ide_handler(): Primary IDE side now %04X...\n", current_pri_side);
ide_set_side(0, current_pri_side);
ali1543_log("ali5229_ide_handler(): Enabling primary IDE...\n");
ide_pri_enable();
ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side);
}
/* Secondary Channel Setup */
if ((dev->ide_conf[0x09] & 0x10) || (dev->ide_conf[0x4d] & 0x80)) {
ali1543_log("ali5229_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base);
ide_set_base(1, current_sec_base);
ali1543_log("ali5229_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side);
ide_set_side(1, current_sec_side);
ali1543_log("ali5229_ide_handler(): Enabling secondary IDE...\n");
ide_sec_enable();
ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side);
}
}
sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x04] & 0x01,
((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (0 ^ ch));
sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x04] & 0x01,
((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + (8 ^ ch));
}
static void
ali5229_chip_reset(ali1543_t *dev)
{
/* M5229 */
memset(dev->ide_conf, 0x00, sizeof(dev->pmu_conf));
dev->ide_conf[0x00] = 0xb9;
dev->ide_conf[0x01] = 0x10;
dev->ide_conf[0x02] = 0x29;
dev->ide_conf[0x03] = 0x52;
dev->ide_conf[0x06] = 0x80;
dev->ide_conf[0x07] = 0x02;
dev->ide_conf[0x08] = 0x20;
dev->ide_conf[0x0a] = 0x01;
dev->ide_conf[0x0b] = 0x01;
dev->ide_conf[0x10] = 0xf1;
dev->ide_conf[0x11] = 0x01;
dev->ide_conf[0x14] = 0xf5;
dev->ide_conf[0x15] = 0x03;
dev->ide_conf[0x18] = 0x71;
dev->ide_conf[0x19] = 0x01;
dev->ide_conf[0x1c] = 0x75;
dev->ide_conf[0x1d] = 0x03;
dev->ide_conf[0x20] = 0x01;
dev->ide_conf[0x21] = 0xf0;
dev->ide_conf[0x3d] = 0x01;
dev->ide_conf[0x3e] = 0x02;
dev->ide_conf[0x3f] = 0x04;
dev->ide_conf[0x53] = 0x03;
dev->ide_conf[0x54] = 0x55;
dev->ide_conf[0x55] = 0x55;
dev->ide_conf[0x63] = 0x01;
dev->ide_conf[0x64] = 0x02;
dev->ide_conf[0x67] = 0x01;
dev->ide_conf[0x78] = 0x21;
if (dev->type == 1) {
dev->ide_conf[0x08] = 0xc1;
dev->ide_conf[0x43] = 0x00;
dev->ide_conf[0x4b] = 0x4a;
dev->ide_conf[0x4e] = 0xba;
dev->ide_conf[0x4f] = 0x1a;
}
ali5229_write(0, 0x04, 0x05, dev);
ali5229_write(0, 0x10, 0xf1, dev);
ali5229_write(0, 0x11, 0x01, dev);
ali5229_write(0, 0x14, 0xf5, dev);
ali5229_write(0, 0x15, 0x03, dev);
ali5229_write(0, 0x18, 0x71, dev);
ali5229_write(0, 0x19, 0x01, dev);
ali5229_write(0, 0x1a, 0x75, dev);
ali5229_write(0, 0x1b, 0x03, dev);
ali5229_write(0, 0x20, 0x01, dev);
ali5229_write(0, 0x21, 0xf0, dev);
ali5229_write(0, 0x4d, 0x00, dev);
dev->ide_conf[0x09] = 0xfa;
ali5229_write(0, 0x09, 0xfa, dev);
ali5229_write(0, 0x52, 0x00, dev);
ali5229_write(0, 0x50, 0x02, dev);
sff_set_slot(dev->ide_controller[0], dev->ide_slot);
sff_set_slot(dev->ide_controller[1], dev->ide_slot);
sff_bus_master_reset(dev->ide_controller[0]);
sff_bus_master_reset(dev->ide_controller[1]);
ali5229_ide_handler(dev);
}
static void
ali5229_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5229: [W] dev->ide_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->ide_dev_enable)
return;
switch (addr) {
case 0x04: /* COM - Command Register */
ali1543_log("IDE04: %02X\n", val);
dev->ide_conf[addr] = val & 0x45;
ali5229_ide_handler(dev);
break;
case 0x05:
dev->ide_conf[addr] = val & 0x01;
break;
case 0x07:
dev->ide_conf[addr] &= ~(val & 0xf1);
break;
case 0x09: /* Control */
ali1543_log("IDE09: %02X\n", val);
if (dev->type == 1) {
val &= ~(dev->ide_conf[0x43]);
val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]);
}
if (dev->ide_conf[0x4d] & 0x80)
dev->ide_conf[addr] = (dev->ide_conf[addr] & 0xfa) | (val & 0x05);
else
dev->ide_conf[addr] = (dev->ide_conf[addr] & 0x8a) | (val & 0x75);
ali5229_ide_handler(dev);
ali5229_ide_irq_handler(dev);
break;
case 0x0d: /* LT - Latency Timer */
dev->ide_conf[addr] = val;
break;
/* Primary Base Address */
case 0x10:
case 0x11:
case 0x14:
case 0x15:
/* FALLTHROUGH */
/* Secondary Base Address */
case 0x18:
case 0x19:
case 0x1c:
case 0x1d:
/* FALLTHROUGH */
/* Bus Mastering Base Address */
case 0x20:
case 0x21:
/* Datasheet erratum: the PCI BAR's actually have different sizes. */
if (addr == 0x20)
dev->ide_conf[addr] = (val & 0xe0) | 0x01;
else if ((addr & 0x07) == 0x00)
dev->ide_conf[addr] = (val & 0xf8) | 0x01;
else if ((addr & 0x07) == 0x04)
dev->ide_conf[addr] = (val & 0xfc) | 0x01;
else
dev->ide_conf[addr] = val;
ali5229_ide_handler(dev);
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (!(dev->ide_conf[0x53] & 0x80))
dev->ide_conf[addr] = val;
break;
case 0x3c: /* Interrupt Line */
case 0x3d: /* Interrupt Pin */
dev->ide_conf[addr] = val;
break;
/* The machines don't touch anything beyond that point so we avoid any programming */
case 0x43:
if (dev->type == 1)
dev->ide_conf[addr] = val & 0x7f;
break;
case 0x4b:
if (dev->type == 1)
dev->ide_conf[addr] = val;
break;
case 0x4d:
dev->ide_conf[addr] = val & 0x80;
ali5229_ide_handler(dev);
break;
case 0x4f:
if (dev->type == 0)
dev->ide_conf[addr] = val & 0x3f;
break;
case 0x50: /* Configuration */
ali1543_log("IDE50: %02X\n", val);
dev->ide_conf[addr] = val & 0x2b;
dev->ide_dev_enable = !!(val & 0x01);
break;
case 0x51:
dev->ide_conf[addr] = val & 0xf7;
if (val & 0x80)
ali5229_chip_reset(dev);
else if (val & 0x40) {
sff_bus_master_reset(dev->ide_controller[0]);
sff_bus_master_reset(dev->ide_controller[1]);
}
break;
case 0x52: /* FCS - Flexible Channel Setting Register */
dev->ide_conf[addr] = val;
ali5229_ide_handler(dev);
ali5229_ide_irq_handler(dev);
break;
case 0x53: /* Subsystem Vendor ID */
dev->ide_conf[addr] = val & 0x8b;
break;
case 0x54: /* FIFO threshold of primary channel drive 0 and drive 1 */
case 0x55: /* FIFO threshold of secondary channel drive 0 and drive 1 */
case 0x56: /* Ultra DMA /33 setting for Primary drive 0 and drive 1 */
case 0x57: /* Ultra DMA /33 setting for Secondary drive 0 and drive 1 */
case 0x78: /* IDE clock's frequency (default value is 33 = 21H) */
dev->ide_conf[addr] = val;
break;
case 0x58:
dev->ide_conf[addr] = val & 3;
break;
case 0x59:
case 0x5a:
case 0x5b:
dev->ide_conf[addr] = val & 0x7f;
break;
case 0x5c:
dev->ide_conf[addr] = val & 3;
break;
case 0x5d:
case 0x5e:
case 0x5f:
dev->ide_conf[addr] = val & 0x7f;
break;
default:
break;
}
}
static uint8_t
ali5229_read(int func, int addr, void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
if (dev->ide_dev_enable && (func == 0)) {
ret = dev->ide_conf[addr];
if ((addr == 0x09) && !(dev->ide_conf[0x50] & 0x02))
ret = (ret & 0x0f) | 0x80;
else if (addr == 0x50)
ret = (ret & 0xfe) | (dev->ide_dev_enable ? 0x01 : 0x00);
else if (addr == 0x75)
ret = ide_read_ali_75();
else if (addr == 0x76)
ret = ide_read_ali_76();
ali1543_log("M5229: [R] dev->ide_conf[%02x] = %02x\n", addr, ret);
}
return ret;
}
static void
ali5237_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M5237: dev->usb_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->usb_dev_enable)
return;
switch (addr) {
case 0x04: /* USB Enable */
dev->usb_conf[addr] = val & 0x5f;
ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1);
break;
case 0x05:
dev->usb_conf[addr] = 0x01;
break;
case 0x07:
dev->usb_conf[addr] &= ~(val & 0xc9);
break;
case 0x0c: /* Cache Line Size */
case 0x0d: /* Latency Timer */
dev->usb_conf[addr] = val;
break;
case 0x3c: /* Interrupt Line Register */
dev->usb_conf[addr] = val;
break;
case 0x42: /* Test Mode Register */
dev->usb_conf[addr] = val & 0x10;
break;
case 0x43:
if (dev->type == 1)
dev->usb_conf[addr] = val & 0x04;
break;
/* USB Base I/O */
case 0x11:
dev->usb_conf[addr] = val & 0xf0;
ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1);
break;
case 0x12:
case 0x13:
dev->usb_conf[addr] = val;
ohci_update_mem_mapping(dev->usb, dev->usb_conf[0x11], dev->usb_conf[0x12], dev->usb_conf[0x13], dev->usb_conf[0x04] & 1);
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (!(dev->usb_conf[0x42] & 0x10))
dev->usb_conf[addr] = val;
break;
default:
break;
}
}
static uint8_t
ali5237_read(int func, int addr, void *priv)
{
const ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
if (dev->usb_dev_enable && (func == 0))
ret = dev->usb_conf[addr];
return ret;
}
static void
ali7101_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
ali1543_log("M7101: [W] dev->pmu_conf[%02x] = %02x\n", addr, val);
if (func > 0)
return;
if (!dev->pmu_dev_enable)
return;
if ((dev->pmu_conf[0xc9] & 0x01) && (addr >= 0x40) && (addr != 0xc9))
return;
switch (addr) {
case 0x04: /* Enable PMU */
ali1543_log("PMU04: %02X\n", val);
dev->pmu_conf[addr] = val & 0x01;
if (!(dev->pmu_conf[0x5b] & 0x02))
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1);
if (!(dev->pmu_conf[0x5b] & 0x04)) {
if (dev->type == 1)
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
else
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
}
break;
/* PMU Base I/O */
case 0x10:
case 0x11:
if (!(dev->pmu_conf[0x5b] & 0x02)) {
if (addr == 0x10)
dev->pmu_conf[addr] = (val & 0xc0) | 1;
else if (addr == 0x11)
dev->pmu_conf[addr] = val;
ali1543_log("New ACPI base address: %08X\n", (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0));
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1);
}
break;
/* SMBus Base I/O */
case 0x14:
case 0x15:
if (!(dev->pmu_conf[0x5b] & 0x04)) {
if (addr == 0x14) {
if (dev->type == 1)
dev->pmu_conf[addr] = (val & 0xc0) | 1;
else
dev->pmu_conf[addr] = (val & 0xe0) | 1;
} else if (addr == 0x15)
dev->pmu_conf[addr] = val;
if (dev->type == 1) {
ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0));
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
} else {
ali1543_log("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0));
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
}
}
break;
/* Subsystem Vendor ID */
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
if (!(dev->pmu_conf[0xd8] & 0x08))
dev->pmu_conf[addr] = val;
break;
case 0x40:
dev->pmu_conf[addr] = val & 0x1f;
nvr_smi_enable((dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x08), dev->nvr);
break;
case 0x41:
dev->pmu_conf[addr] = val & 0x10;
ali1543_log("PMU41: %02X\n", val);
apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10));
break;
/* TODO: Is the status R/W or R/WC? */
case 0x42:
dev->pmu_conf[addr] &= ~(val & 0x1f);
if (val & 0x08)
nvr_smi_status_clear(dev->nvr);
break;
case 0x43:
dev->pmu_conf[addr] &= ~(val & 0x10);
if (val & 0x10)
acpi_ali_soft_smi_status_write(dev->acpi, 0);
break;
case 0x44:
dev->pmu_conf[addr] = val;
break;
case 0x45:
dev->pmu_conf[addr] = val & 0x9f;
break;
case 0x46:
dev->pmu_conf[addr] = val & 0x18;
break;
/* TODO: Is the status R/W or R/WC? */
case 0x48:
dev->pmu_conf[addr] &= ~val;
break;
case 0x49:
dev->pmu_conf[addr] &= ~(val & 0x9f);
break;
case 0x4a:
dev->pmu_conf[addr] &= ~(val & 0x38);
break;
case 0x4c:
dev->pmu_conf[addr] = val & 5;
break;
case 0x4d:
dev->pmu_conf[addr] = val & 1;
break;
/* TODO: Is the status R/W or R/WC? */
case 0x4e:
dev->pmu_conf[addr] &= ~(val & 5);
break;
case 0x4f:
dev->pmu_conf[addr] &= ~(val & 1);
break;
case 0x50:
case 0x51:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x52:
case 0x53:
if (dev->type == 1)
dev->pmu_conf[addr] &= ~val;
break;
case 0x54: /* Standby timer */
dev->pmu_conf[addr] = val;
break;
case 0x55: /* APM Timer */
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x59: /* Global display timer. */
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x5b: /* ACPI/SMB Base I/O Control */
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x87;
else
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x60:
dev->pmu_conf[addr] = val;
break;
case 0x61:
dev->pmu_conf[addr] = val & 0x13;
break;
case 0x62:
dev->pmu_conf[addr] = val & 0xf1;
break;
case 0x63:
dev->pmu_conf[addr] = val & 0x07;
break;
case 0x64:
dev->pmu_conf[addr] = val;
break;
case 0x65:
dev->pmu_conf[addr] = val & 0x11;
break;
case 0x68:
dev->pmu_conf[addr] = val & 0x07;
break;
case 0x6c:
case 0x6d:
dev->pmu_conf[addr] = val;
break;
case 0x6e:
dev->pmu_conf[addr] = val & 0xbf;
break;
case 0x6f:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x1e;
else
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x70:
dev->pmu_conf[addr] = val;
break;
case 0x71:
dev->pmu_conf[addr] = val & 0x3f;
break;
case 0x72:
dev->pmu_conf[addr] = val & 0x0f;
break;
/* TODO: Is the status R/W or R/WC? */
case 0x74:
dev->pmu_conf[addr] &= ~(val & 0x33);
break;
case 0x75:
dev->pmu_conf[addr] = val;
break;
case 0x76:
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x77:
/* TODO: If bit 1 is clear, then status bit is set even if SMI is disabled. */
dev->pmu_conf[addr] = val;
ali1543_log("PMU77: %02X\n", val);
nvr_smi_enable((dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x40] & 0x08), dev->nvr);
apm_set_do_smi(dev->acpi->apm, (dev->pmu_conf[0x77] & 0x08) && (dev->pmu_conf[0x41] & 0x10));
break;
case 0x78:
dev->pmu_conf[addr] = val;
break;
case 0x79:
dev->pmu_conf[addr] = val & 0x0f;
break;
case 0x7a:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x07;
else
dev->pmu_conf[addr] = val & 0x02;
break;
case 0x7b:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
else
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x7c ... 0x7f:
dev->pmu_conf[addr] = val;
break;
case 0x81:
dev->pmu_conf[addr] = val & 0xf0;
break;
case 0x82:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x01;
break;
case 0x84 ... 0x87:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x88 ... 0x8b:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x8c:
case 0x8d:
dev->pmu_conf[addr] = val & 0x0f;
break;
case 0x90:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x0f;
else
dev->pmu_conf[addr] = val & 0x01;
break;
case 0x91:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x02;
break;
case 0x94:
dev->pmu_conf[addr] = val & 0xf0;
break;
case 0x95 ... 0x97:
dev->pmu_conf[addr] = val;
break;
case 0x98:
case 0x99:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0xa4:
case 0xa5:
dev->pmu_conf[addr] = val;
break;
case 0xb2:
dev->pmu_conf[addr] = val & 0x01;
break;
case 0xb3:
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0xb4:
dev->pmu_conf[addr] = val & 0x7c;
break;
case 0xb5:
case 0xb7:
dev->pmu_conf[addr] = val & 0x0f;
break;
case 0xb8:
case 0xb9:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0xbc:
outb(0x70, val);
break;
case 0xbd:
dev->pmu_conf[addr] = val & 0x0f;
acpi_set_timer32(dev->acpi, val & 0x04);
break;
case 0xbe:
dev->pmu_conf[addr] = val & 0x03;
break;
/* Continue Further Later */
/* GPO Registers */
case 0xc0:
dev->pmu_conf[addr] = val & 0x0f;
acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00);
break;
case 0xc1:
dev->pmu_conf[addr] = val & 0x12;
acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00);
break;
case 0xc2:
dev->pmu_conf[addr] = val & 0x1c;
acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00);
break;
case 0xc3:
dev->pmu_conf[addr] = val & 0x06;
acpi_init_gporeg(dev->acpi, dev->pmu_conf[0xc0], dev->pmu_conf[0xc1], dev->pmu_conf[0xc2] | (dev->pmu_conf[0xc3] << 5), 0x00);
break;
case 0xc6:
dev->pmu_conf[addr] = val & 0x06;
break;
case 0xc8:
case 0xc9:
dev->pmu_conf[addr] = val & 0x01;
break;
case 0xca:
/* TODO: Write to this port causes a beep. */
dev->pmu_conf[addr] = val;
break;
case 0xcc:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0xcd:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x33;
break;
case 0xd4:
dev->pmu_conf[addr] = val & 0x01;
break;
case 0xd8:
dev->pmu_conf[addr] = val & 0xfd;
break;
case 0xd9:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x3f;
break;
case 0xe0:
dev->pmu_conf[addr] = val & 0x03;
if (dev->type == 1)
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
else
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0xe1:
dev->pmu_conf[addr] = val;
break;
case 0xe2:
dev->pmu_conf[addr] = val & 0xf8;
break;
default:
dev->pmu_conf[addr] = val;
break;
}
}
static uint8_t
ali7101_read(int func, int addr, void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
uint8_t ret = 0xff;
if (dev->pmu_dev_enable && (func == 0)) {
if (!(dev->pmu_conf[0xc9] & 0x01) || (addr < 0x40) || (addr == 0xc9)) {
/* TODO: C4, C5 = GPIREG (masks: 0D, 0E) */
switch (addr) {
default:
ret = dev->pmu_conf[addr];
break;
case 0x10 ... 0x13:
if (dev->pmu_conf[0x5b] & 0x02)
ret = 0x00;
else
ret = dev->pmu_conf[addr];
break;
case 0x14 ... 0x17:
if (dev->pmu_conf[0x5b] & 0x04)
ret = 0x00;
else
ret = dev->pmu_conf[addr];
break;
case 0x42:
ret = (dev->pmu_conf[addr] & 0xf7) | (nvr_smi_status(dev->nvr) ? 0x08 : 0x00);
break;
case 0x43:
ret = acpi_ali_soft_smi_status_read(dev->acpi) ? 0x10 : 0x00;
break;
case 0x7f:
ret = 0x80;
break;
case 0xbc:
ret = inb(0x70);
break;
}
if (dev->pmu_conf[0x77] & 0x10) {
switch (addr) {
case 0x42:
dev->pmu_conf[addr] &= 0xe0;
break;
case 0x43:
dev->pmu_conf[addr] &= 0xef;
acpi_ali_soft_smi_status_write(dev->acpi, 0);
break;
case 0x48:
dev->pmu_conf[addr] = 0x00;
break;
case 0x49:
dev->pmu_conf[addr] &= 0x60;
break;
case 0x4a:
dev->pmu_conf[addr] &= 0xc7;
break;
case 0x4e:
dev->pmu_conf[addr] &= 0xfa;
break;
case 0x4f:
dev->pmu_conf[addr] &= 0xfe;
break;
case 0x74:
dev->pmu_conf[addr] &= 0xcc;
break;
default:
break;
}
}
}
}
ali1543_log("M7101: [R] dev->pmu_conf[%02x] = %02x\n", addr, ret);
return ret;
}
static void
ali1543_reset(void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
/* Temporarily enable everything. Register writes will disable the devices. */
dev->ide_dev_enable = 1;
dev->usb_dev_enable = 1;
dev->pmu_dev_enable = 1;
/* M5229 */
ali5229_chip_reset(dev);
/* M5237 */
memset(dev->usb_conf, 0x00, sizeof(dev->usb_conf));
dev->usb_conf[0x00] = 0xb9;
dev->usb_conf[0x01] = 0x10;
dev->usb_conf[0x02] = 0x37;
dev->usb_conf[0x03] = 0x52;
dev->usb_conf[0x06] = 0x80;
dev->usb_conf[0x07] = 0x02;
dev->usb_conf[0x08] = 0x03;
dev->usb_conf[0x09] = 0x10;
dev->usb_conf[0x0a] = 0x03;
dev->usb_conf[0x0b] = 0x0c;
dev->usb_conf[0x3d] = 0x01;
ali5237_write(0, 0x04, 0x00, dev);
ali5237_write(0, 0x10, 0x00, dev);
ali5237_write(0, 0x11, 0x00, dev);
ali5237_write(0, 0x12, 0x00, dev);
ali5237_write(0, 0x13, 0x00, dev);
/* M7101 */
memset(dev->pmu_conf, 0x00, sizeof(dev->pmu_conf));
dev->pmu_conf[0x00] = 0xb9;
dev->pmu_conf[0x01] = 0x10;
dev->pmu_conf[0x02] = 0x01;
dev->pmu_conf[0x03] = 0x71;
dev->pmu_conf[0x05] = 0x00;
dev->pmu_conf[0x0a] = 0x01;
dev->pmu_conf[0x0b] = 0x06;
dev->pmu_conf[0xe2] = 0x20;
acpi_set_slot(dev->acpi, dev->pmu_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
ali7101_write(0, 0x04, 0x0f, dev);
ali7101_write(0, 0x10, 0x01, dev);
ali7101_write(0, 0x11, 0x00, dev);
ali7101_write(0, 0x12, 0x00, dev);
ali7101_write(0, 0x13, 0x00, dev);
ali7101_write(0, 0x14, 0x01, dev);
ali7101_write(0, 0x15, 0x00, dev);
ali7101_write(0, 0x16, 0x00, dev);
ali7101_write(0, 0x17, 0x00, dev);
ali7101_write(0, 0x40, 0x00, dev);
ali7101_write(0, 0x41, 0x00, dev);
ali7101_write(0, 0x42, 0x00, dev);
ali7101_write(0, 0x43, 0x00, dev);
ali7101_write(0, 0x77, 0x00, dev);
ali7101_write(0, 0xbd, 0x00, dev);
ali7101_write(0, 0xc0, 0x00, dev);
ali7101_write(0, 0xc1, 0x00, dev);
ali7101_write(0, 0xc2, 0x00, dev);
ali7101_write(0, 0xc3, 0x00, dev);
ali7101_write(0, 0xe0, 0x00, dev);
/* Do the bridge last due to device deactivations. */
/* M1533 */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x33;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x0f;
dev->pci_conf[0x07] = 0x02;
if (dev->type == 1)
dev->pci_conf[0x08] = 0xc0;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x41, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);
ali1533_write(0, 0x58, 0x00, dev);
ali1533_write(0, 0x5f, 0x00, dev);
ali1533_write(0, 0x72, 0x00, dev);
ali1533_write(0, 0x74, 0x00, dev);
ali1533_write(0, 0x75, 0x00, dev);
ali1533_write(0, 0x76, 0x00, dev);
if (dev->type == 1)
ali1533_write(0, 0x78, 0x00, dev);
unmask_a20_in_smm = 1;
}
static void
ali1543_close(void *priv)
{
ali1543_t *dev = (ali1543_t *) priv;
free(dev);
}
static void *
ali1543_init(const device_t *info)
{
ali1543_t *dev = (ali1543_t *) malloc(sizeof(ali1543_t));
memset(dev, 0, sizeof(ali1543_t));
/* Device 02: M1533 Southbridge */
pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev, &dev->pci_slot);
/* Device 0B: M5229 IDE Controller*/
pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, ali5229_read, ali5229_write, dev, &dev->ide_slot);
/* Device 0C: M7101 Power Managment Controller */
pci_add_card(PCI_ADD_SOUTHBRIDGE_PMU, ali7101_read, ali7101_write, dev, &dev->pmu_slot);
/* Device 0F: M5237 USB */
pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, ali5237_read, ali5237_write, dev, &dev->usb_slot);
/* ACPI */
dev->acpi = device_add(&acpi_ali_device);
dev->nvr = device_add(&piix4_nvr_device);
/* DMA */
dma_alias_set();
dma_set_sg_base(0x04);
dma_set_params(1, 0xffffffff);
dma_ext_mode_init();
dma_high_page_init();
/* DDMA */
dev->ddma = device_add(&ddma_device);
/* IDE Controllers */
dev->ide_controller[0] = device_add_inst(&sff8038i_device, 1);
dev->ide_controller[1] = device_add_inst(&sff8038i_device, 2);
/* Port 92h */
dev->port_92 = device_add(&port_92_pci_device);
/* Standard SMBus */
dev->smbus = device_add(&ali7101_smbus_device);
/* USB */
dev->usb = device_add(&usb_device);
dev->type = info->local & 0xff;
dev->offset = (info->local >> 8) & 0x7f;
if (info->local & 0x8000)
dev->offset = -dev->offset;
ali1543_log("Offset = %i\n", dev->offset);
pci_enable_mirq(0);
pci_enable_mirq(1);
pci_enable_mirq(2);
pci_enable_mirq(3);
pci_enable_mirq(4);
pci_enable_mirq(5);
pci_enable_mirq(6);
/* Super I/O chip */
device_add(&ali5123_device);
ali1543_reset(dev);
return dev;
}
const device_t ali1543_device = {
.name = "ALi M1543 Desktop South Bridge",
.internal_name = "ali1543",
.flags = DEVICE_PCI,
.local = 0x8500, /* -5 slot offset, we can do this because we currently
have no case of M1543 non-C with a different offset */
.init = ali1543_init,
.close = ali1543_close,
.reset = ali1543_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ali1543c_device = {
.name = "ALi M1543C Desktop South Bridge",
.internal_name = "ali1543c",
.flags = DEVICE_PCI,
.local = 1,
.init = ali1543_init,
.close = ali1543_close,
.reset = ali1543_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1543.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 17,315 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5513 PCI to ISA bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5513_PCI_TO_ISA_LOG
int sis_5513_pci_to_isa_do_log = ENABLE_SIS_5513_PCI_TO_ISA_LOG;
static void
sis_5513_pci_to_isa_log(const char *fmt, ...)
{
va_list ap;
if (sis_5513_pci_to_isa_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5513_pci_to_isa_log(fmt, ...)
#endif
typedef struct sis_5513_pci_to_isa_t {
uint8_t rev;
uint8_t index;
uint8_t dam_index;
uint8_t irq_state;
uint8_t dam_enable;
uint8_t dam_irq_enable;
uint8_t ddma_enable;
uint8_t pci_conf[256];
uint8_t regs[16];
uint8_t dam_regs[256];
uint8_t apc_regs[256];
uint16_t dam_base;
uint16_t ddma_base;
uint16_t acpi_io_base;
sis_55xx_common_t *sis;
port_92_t *port_92;
void *pit;
nvr_t *nvr;
char *fn;
ddma_t *ddma;
acpi_t *acpi;
void *smbus;
uint8_t (*pit_read_reg)(void *priv, uint8_t reg);
} sis_5513_pci_to_isa_t;
static void
sis_5595_acpi_recalc(sis_5513_pci_to_isa_t *dev)
{
dev->acpi_io_base = (dev->pci_conf[0x91] << 8) | (dev->pci_conf[0x90] & 0xc0);
acpi_update_io_mapping(dev->sis->acpi, dev->acpi_io_base, (dev->pci_conf[0x40] & 0x80));
}
static void
sis_5513_apc_reset(sis_5513_pci_to_isa_t *dev)
{
memset(dev->apc_regs, 0x00, sizeof(dev->apc_regs));
if (dev->rev == 0b0) {
dev->apc_regs[0x03] = 0x80;
dev->apc_regs[0x04] = 0x38;
dev->apc_regs[0x07] = 0x01;
} else
dev->apc_regs[0x04] = 0x08;
}
static void
sis_5513_apc_write(uint16_t addr, uint8_t val, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t nvr_index = nvr_get_index(dev->nvr, 0);
sis_5513_pci_to_isa_log("SiS 5595 APC: [W] %04X = %02X\n", addr, val);
switch (nvr_index) {
case 0x02 ... 0x04:
dev->apc_regs[nvr_index] = val;
break;
case 0x05:
case 0x07 ... 0x08:
if (dev->rev == 0xb0)
dev->apc_regs[nvr_index] = val;
break;
}
}
static uint8_t
sis_5513_apc_read(uint16_t addr, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t nvr_index = nvr_get_index(dev->nvr, 0);
uint8_t ret = 0xff;
ret = dev->apc_regs[nvr_index];
if (nvr_index == 0x06)
dev->apc_regs[nvr_index] = 0x00;
sis_5513_pci_to_isa_log("SiS 5595 APC: [R] %04X = %02X\n", addr, ret);
return ret;
}
void
sis_5513_apc_recalc(sis_5513_pci_to_isa_t *dev, uint8_t apc_on)
{
nvr_at_data_port(!apc_on, dev->nvr);
io_removehandler(0x0071, 0x0001,
sis_5513_apc_read, NULL, NULL, sis_5513_apc_write, NULL, NULL, dev);
if (apc_on)
io_removehandler(0x0071, 0x0001,
sis_5513_apc_read, NULL, NULL, sis_5513_apc_write, NULL, NULL, dev);
}
static void
sis_5595_do_nmi(sis_5513_pci_to_isa_t *dev, int set)
{
if (set)
nmi_raise();
dev->irq_state = set;
}
static void
sis_5595_dam_reset(sis_5513_pci_to_isa_t *dev)
{
if (dev->irq_state) {
if (dev->dam_regs[0x40] & 0x20)
sis_5595_do_nmi(dev, 0);
else if (dev->dam_irq_enable)
pci_clear_mirq(6, 1, &dev->irq_state);
}
memset(dev->dam_regs, 0x00, sizeof(dev->dam_regs));
dev->dam_regs[0x40] = 0x08;
dev->dam_regs[0x47] = 0x50;
}
static void
sis_5595_dam_write(uint16_t addr, uint8_t val, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint16_t reg = addr - dev->dam_base;
uint8_t old;
sis_5513_pci_to_isa_log("SiS 5595 DAM: [W] %04X = %02X\n", addr, val);
switch (reg) {
case 0x05:
dev->dam_index = (dev->index & 0x80) | (val & 0x7f);
break;
case 0x06:
switch (dev->dam_index) {
case 0x40:
old = dev->dam_regs[0x40];
dev->dam_regs[0x40] = val & 0xef;
if (val & 0x80) {
sis_5595_dam_reset(dev);
return;
}
if (dev->irq_state) {
if (!(old & 0x20) && (val & 0x20)) {
if (dev->dam_irq_enable)
pci_clear_mirq(6, 1, &dev->irq_state);
sis_5595_do_nmi(dev, 1);
} else if ((old & 0x20) && !(val & 0x20)) {
sis_5595_do_nmi(dev, 0);
if (dev->dam_irq_enable)
pci_set_mirq(6, 1, &dev->irq_state);
}
}
if ((val & 0x08) && dev->dam_irq_enable)
pci_clear_mirq(6, 1, &dev->irq_state);
break;
case 0x43 ... 0x47:
dev->dam_regs[dev->dam_index] = val;
break;
case 0x2b ... 0x34:
case 0x6b ... 0x74:
case 0x3b ... 0x3c:
case 0x7b ... 0x7c:
dev->dam_regs[dev->dam_index & 0x3f] = val;
break;
}
break;
}
}
static uint8_t
sis_5595_dam_read(uint16_t addr, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint16_t reg = addr - dev->dam_base;
uint8_t ret = 0xff;
switch (reg) {
case 0x05:
ret = dev->dam_index;
break;
case 0x06:
switch (dev->dam_index) {
default:
ret = dev->dam_regs[dev->dam_index];
break;
case 0x20 ... 0x29:
case 0x2b ... 0x3f:
ret = dev->dam_regs[dev->dam_index & 0x3f];
break;
case 0x2a:
case 0x6a:
ret = dev->pci_conf[0x78];
break;
}
break;
}
sis_5513_pci_to_isa_log("SiS 5595 DAM: [R] %04X = %02X\n", addr, ret);
return ret;
}
static void
sis_5595_dam_recalc(sis_5513_pci_to_isa_t *dev)
{
if (dev->dam_enable && (dev->dam_base != 0x0000))
io_removehandler(dev->dam_base, 0x0008,
sis_5595_dam_read, NULL, NULL, sis_5595_dam_write, NULL, NULL, dev);
dev->dam_base = dev->pci_conf[0x68] | (dev->pci_conf[0x69] << 16);
dev->dam_enable = !!(dev->pci_conf[0x7b] & 0x80);
if (dev->dam_enable && (dev->dam_base != 0x0000))
io_sethandler(dev->dam_base, 0x0008,
sis_5595_dam_read, NULL, NULL, sis_5595_dam_write, NULL, NULL, dev);
}
static void
sis_5595_ddma_recalc(sis_5513_pci_to_isa_t *dev)
{
uint16_t ch_base;
dev->ddma_base = (dev->pci_conf[0x80] & 0xf0) | (dev->pci_conf[0x81] << 16);
dev->ddma_enable = !!(dev->pci_conf[0x80] & 0x01);
for (uint8_t i = 0; i < 8; i++) {
ch_base = dev->ddma_base + (i << 4);
ddma_update_io_mapping(dev->ddma, i, ch_base & 0xff, (ch_base >> 8),
dev->ddma_enable && (dev->pci_conf[0x84] & (1 << i)) &&
(dev->ddma_base != 0x0000));
}
}
static void
sis_5513_00_pci_to_isa_write(int addr, uint8_t val, sis_5513_pci_to_isa_t *dev)
{
switch (addr) {
case 0x60: /* MIRQ0 Remapping Control Register */
case 0x61: /* MIRQ1 Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: MIRQ%i -> %02X\n", addr & 0x01, val);
dev->pci_conf[addr] = val & 0xcf;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf);
break;
case 0x62: /* On-board Device DMA Control Register */
dev->pci_conf[addr] = val;
break;
case 0x63: /* IDEIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: IDEIRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0x8f;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ2, val & 0xf);
break;
case 0x64: /* GPIO0 Control Register */
dev->pci_conf[addr] = val & 0xef;
break;
case 0x65:
dev->pci_conf[addr] = val & 0x80;
break;
case 0x66: /* GPIO0 Output Mode Control Register */
case 0x67: /* GPIO0 Output Mode Control Register */
dev->pci_conf[addr] = val;
break;
case 0x6a: /* GPIO Status Register */
dev->pci_conf[addr] |= (val & 0x10);
dev->pci_conf[addr] &= ~(val & 0x01);
break;
default:
break;
}
}
static void
sis_5513_01_pci_to_isa_write(int addr, uint8_t val, sis_5513_pci_to_isa_t *dev)
{
uint8_t old;
switch (addr) {
/* Simply skip MIRQ0, so we can reuse the SiS 551x IDEIRQ infrastructure. */
case 0x61: /* MIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: MIRQ%i -> %02X\n", addr & 0x01, val);
dev->pci_conf[addr] = val & 0xcf;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf);
break;
case 0x62: /* On-board Device DMA Control Register */
dev->pci_conf[addr] = val;
break;
case 0x63: /* IDEIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: IDEIRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0x8f;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ2, val & 0xf);
break;
case 0x64: /* GPIO Control Register */
dev->pci_conf[addr] = val & 0xef;
break;
case 0x65:
dev->pci_conf[addr] = val & 0x1b;
break;
case 0x66: /* GPIO Output Mode Control Register */
case 0x67: /* GPIO Output Mode Control Register */
dev->pci_conf[addr] = val;
break;
case 0x68: /* USBIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: USBIRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0xcf;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ3, val & 0xf);
break;
case 0x69:
dev->pci_conf[addr] = val;
break;
case 0x6a:
dev->pci_conf[addr] = val & 0xfc;
break;
case 0x6b:
dev->pci_conf[addr] = val;
break;
case 0x6c:
dev->pci_conf[addr] = val & 0x02;
break;
case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */
old = dev->pci_conf[addr];
picint((val ^ old) & val);
picintc((val ^ old) & ~val);
dev->pci_conf[addr] = val;
break;
case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */
old = dev->pci_conf[addr];
picint(((val ^ old) & val) << 8);
picintc(((val ^ old) & ~val) << 8);
dev->pci_conf[addr] = val;
break;
case 0x70:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x02) | (val & 0xdc);
break;
case 0x71: /* Type-F DMA Control Register */
dev->pci_conf[addr] = val & 0xef;
break;
case 0x72: /* SMI Triggered By IRQ/GPIO Control */
case 0x73: /* SMI Triggered By IRQ/GPIO Control */
dev->pci_conf[addr] = val;
break;
case 0x74: /* System Standby Timer Reload,
System Standby State Exit And Throttling State Exit Control */
case 0x75: /* System Standby Timer Reload,
System Standby State Exit And Throttling State Exit Control */
case 0x76: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
static void
sis_5513_11_pci_to_isa_write(int addr, uint8_t val, sis_5513_pci_to_isa_t *dev)
{
uint8_t old;
switch (addr) {
case 0x61: /* IDEIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: IDEIRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0xcf;
dev->sis->ide_bits_1_3_writable = !!(val & 0x40);
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ2, val & 0xf);
break;
case 0x62: /* USBIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: USBIRQ -> %02X\n", val);
dev->pci_conf[addr] = val;
dev->sis->usb_enabled = !!(val & 0x40);
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ3, val & 0xf);
break;
case 0x63: /* GPCS0 Control Register */
case 0x64: /* GPCS1 Control Register */
case 0x65: /* GPCS0 Output Mode Control Register */
case 0x66: /* GPCS0 Output Mode Control Register */
case 0x67: /* GPCS1 Output Mode Control Register */
case 0x68: /* GPCS1 Output Mode Control Register */
case 0x6b:
case 0x6c:
dev->pci_conf[addr] = val;
break;
case 0x69: /* GPCS0/1 De-Bounce Control Register */
dev->pci_conf[addr] = val & 0xdf;
if ((dev->apc_regs[0x03] & 0x40) && (val & 0x10)) {
plat_power_off();
return;
}
break;
case 0x6a: /* ACPI/SCI IRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: ACPI/SCI IRQ -> %02X\n", val);
dev->pci_conf[addr] = val;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ5, val & 0xf);
break;
case 0x6d: /* I2C Bus Control Register */
dev->pci_conf[addr] = val;
/* TODO: Keyboard/mouse swapping and keyboard hot key. */
break;
case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */
old = dev->pci_conf[addr];
picint((val ^ old) & val);
picintc((val ^ old) & ~val);
dev->pci_conf[addr] = val;
break;
case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */
old = dev->pci_conf[addr];
picint(((val ^ old) & val) << 8);
picintc(((val ^ old) & ~val) << 8);
dev->pci_conf[addr] = val;
break;
case 0x70: /* Misc. Controller Register */
dev->pci_conf[addr] = val;
/* TODO: Keyboard Lock Enable/Disable. */
break;
case 0x71: /* Type F DMA Control Register */
dev->pci_conf[addr] = val & 0xef;
break;
case 0x72: /* SMI Triggered By IRQ Control */
dev->pci_conf[addr] = val & 0xfa;
break;
case 0x73: /* SMI Triggered By IRQ Control */
case 0x75: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit */
case 0x77: /* Monoitor Standby Timer Reload And Monoitor Standby State Exit Control */
dev->pci_conf[addr] = val;
break;
case 0x74: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit */
case 0x76: /* Monoitor Standby Timer Reload And Monoitor Standby State Exit Control */
dev->pci_conf[addr] = val & 0xfb;
break;
dev->pci_conf[addr] = val;
break;
case 0x80: /* Distributed DMA Master Configuration Register */
case 0x81: /* Distributed DMA Master Configuration Register */
dev->pci_conf[addr] = val;
sis_5595_ddma_recalc(dev);
break;
case 0x84: /* Individual Distributed DMA Channel Enable */
dev->pci_conf[addr] = val;
sis_5595_ddma_recalc(dev);
break;
case 0x88: /* Serial Interrupt Control Register */
case 0x89: /* Serial Interrupt Enable Register 1 */
case 0x8a: /* Serial Interrupt Enable Register 2 */
dev->pci_conf[addr] = val;
break;
case 0x90: /* ACPI Base Address Register */
dev->pci_conf[addr] = val & 0xc0;
sis_5595_acpi_recalc(dev);
break;
case 0x91: /* ACPI Base Address Register */
dev->pci_conf[addr] = val;
sis_5595_acpi_recalc(dev);
break;
default:
break;
}
}
static void
sis_5513_b0_pci_to_isa_write(int addr, uint8_t val, sis_5513_pci_to_isa_t *dev)
{
uint8_t old;
switch (addr) {
case 0x61: /* IDEIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: IDEIRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0xdf;
sff_set_mirq(dev->sis->bm[0], (val & 0x10) ? 7 : 2);
sff_set_mirq(dev->sis->bm[1], (val & 0x10) ? 2 : 7);
pci_set_mirq_routing(PCI_MIRQ7, 14 + (!!(val & 0x10)));
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ2, val & 0xf);
break;
case 0x62: /* USBIRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: USBIRQ -> %02X\n", val);
dev->pci_conf[addr] = val;
dev->sis->usb_enabled = !!(val & 0x40);
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ3, val & 0xf);
break;
case 0x63: /* PCI OutputBuffer Current Strength Register */
dev->pci_conf[addr] = val;
if ((dev->apc_regs[0x03] & 0x40) && (val & 0x04)) {
plat_power_off();
return;
}
if ((val & 0x18) == 0x18) {
dma_reset();
dma_set_at(1);
device_reset_all(DEVICE_ALL);
cpu_alt_reset = 0;
pci_reset();
mem_a20_alt = 0;
mem_a20_recalc();
flushmmucache();
resetx86();
}
break;
case 0x64: /* INIT Enable Register */
dev->pci_conf[addr] = val;
cpu_cpurst_on_sr = !(val & 0x20);
break;
case 0x65: /* PHOLD# Timer */
case 0x66: /* Priority Timer */
case 0x67: /* Respond to C/D Segments Register */
case 0x6b: /* Test Mode Register I */
case 0x6c: /* Test Mode Register II */
case 0x71: /* Reserved */
case 0x72: /* Individual PC/PCI DMA Channel Enable */
case 0x7c: /* Data Acquisition Module ADC Calibration */
case 0x7d: /* Data Acquisition Module ADC Calibration */
case 0x88: /* Serial Interrupt Control Register */
case 0x89: /* Serial Interrupt Enable Register 1 */
case 0x8a: /* Serial Interrupt Enable Register 2 */
case 0x8c: /* Serial Interrupt Enable Register 3 */
dev->pci_conf[addr] = val;
break;
case 0x68: /* Data Acquistion Module Base Address */
dev->pci_conf[addr] = val & 0xf8;
sis_5595_dam_recalc(dev);
break;
case 0x6a: /* ACPI/SCI IRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: ACPI/SCI IRQ -> %02X\n", val);
dev->pci_conf[addr] = val & 0x8f;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ5, val & 0xf);
break;
case 0x6d: /* I2C Bus Control Register */
dev->pci_conf[addr] = val;
/* TODO: Keyboard/mouse swapping and keyboard hot key. */
break;
case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */
old = dev->pci_conf[addr];
picint((val ^ old) & val);
picintc((val ^ old) & ~val);
dev->pci_conf[addr] = val;
break;
case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */
old = dev->pci_conf[addr];
picint(((val ^ old) & val) << 8);
picintc(((val ^ old) & ~val) << 8);
dev->pci_conf[addr] = val;
break;
case 0x70: /* Misc. Controller Register */
dev->pci_conf[addr] = val;
/* TODO: Keyboard Lock Enable/Disable. */
break;
case 0x73:
case 0x75 ... 0x79:
if (dev->rev == 0x81)
dev->pci_conf[addr] = val;
break;
case 0x7a: /* Data Acquisition Module Function Selection Register */
if (dev->rev == 0x81)
dev->pci_conf[addr] = val;
else
dev->pci_conf[addr] = val & 0x90;
break;
case 0x7b: /* Data Acquisition Module Control Register */
dev->pci_conf[addr] = val;
sis_5595_dam_recalc(dev);
break;
case 0x7e: /* Data Acquisition Module and SMBUS IRQ Remapping Control Register */
sis_5513_pci_to_isa_log("Set MIRQ routing: DAM/SMBUS IRQ -> %02X\n", val);
if (dev->rev == 0x81)
dev->pci_conf[addr] = val & 0x8f;
else {
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x10) | (val & 0xef);
dev->dam_irq_enable = ((val & 0xc0) == 0x40);
smbus_sis5595_irq_enable(dev->smbus, (val & 0xa0) == 0x20);
}
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ6, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ6, val & 0xf);
break;
case 0x80: /* Distributed DMA Master Configuration Register */
case 0x81: /* Distributed DMA Master Configuration Register */
dev->pci_conf[addr] = val;
sis_5595_ddma_recalc(dev);
break;
case 0x84: /* Individual Distributed DMA Channel Enable */
dev->pci_conf[addr] = val;
sis_5595_ddma_recalc(dev);
break;
case 0x90: /* ACPI Base Address Register */
dev->pci_conf[addr] = val & 0xc0;
sis_5595_acpi_recalc(dev);
break;
case 0x91: /* ACPI Base Address Register */
dev->pci_conf[addr] = val;
sis_5595_acpi_recalc(dev);
break;
default:
break;
}
}
void
sis_5513_pci_to_isa_write(int addr, uint8_t val, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
sis_5513_pci_to_isa_log("SiS 5513 P2I: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
case 0x04: /* Command */
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x07: /* Status */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x06) & ~(val & 0x30);
break;
case 0x0d: /* Master Latency Timer */
if (dev->rev >= 0x11)
dev->pci_conf[addr] = val;
break;
case 0x40: /* BIOS Control Register */
if (dev->rev >= 0x11) {
dev->pci_conf[addr] = val;
sis_5595_acpi_recalc(dev);
} else
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x41: /* INTA# Remapping Control Register */
case 0x42: /* INTB# Remapping Control Register */
case 0x43: /* INTC# Remapping Control Register */
dev->pci_conf[addr] = val & 0x8f;
pci_set_irq_routing(addr & 0x07, (val & 0x80) ? PCI_IRQ_DISABLED : (val & 0x0f));
break;
case 0x44: /* INTD# Remapping Control Register */
if (dev->rev == 0x11) {
dev->pci_conf[addr] = val & 0xcf;
sis_5513_apc_recalc(dev, val & 0x10);
} else
dev->pci_conf[addr] = val & 0x8f;
pci_set_irq_routing(addr & 0x07, (val & 0x80) ? PCI_IRQ_DISABLED : (val & 0x0f));
break;
case 0x45: /* ISA Bus Control Register I */
if (dev->rev >= 0x01) {
if (dev->rev == 0x01)
dev->pci_conf[addr] = val & 0xec;
else
dev->pci_conf[addr] = val;
switch (val >> 6) {
case 0:
cpu_set_isa_speed(7159091);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
nvr_bank_set(0, !!(val & 0x08), dev->nvr);
if (dev->rev == 0xb0)
sis_5513_apc_recalc(dev, val & 0x02);
}
break;
case 0x46: /* ISA Bus Control Register II */
if (dev->rev >= 0x11)
dev->pci_conf[addr] = val;
else if (dev->rev == 0x00)
dev->pci_conf[addr] = val & 0xec;
break;
case 0x47: /* DMA Clock and Wait State Control Register */
switch (dev->rev) {
case 0x01:
dev->pci_conf[addr] = val & 0x3e;
break;
case 0x11:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0xb0:
dev->pci_conf[addr] = val & 0xfd;
break;
}
break;
case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf[addr] = val;
break;
default:
switch (dev->rev) {
case 0x00:
sis_5513_00_pci_to_isa_write(addr, val, priv);
break;
case 0x01:
sis_5513_01_pci_to_isa_write(addr, val, priv);
break;
case 0x11:
sis_5513_11_pci_to_isa_write(addr, val, priv);
break;
case 0x81:
case 0xb0:
sis_5513_b0_pci_to_isa_write(addr, val, priv);
break;
}
break;
}
}
uint8_t
sis_5513_pci_to_isa_read(int addr, void *priv)
{
const sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
default:
ret = dev->pci_conf[addr];
break;
case 0x4c ... 0x4f:
ret = pic_read_icw(0, addr & 0x03);
break;
case 0x50 ... 0x53:
ret = pic_read_icw(1, addr & 0x03);
break;
case 0x54 ... 0x55:
ret = pic_read_ocw(0, addr & 0x01);
break;
case 0x56 ... 0x57:
ret = pic_read_ocw(1, addr & 0x01);
break;
case 0x58 ... 0x5f:
ret = dev->pit_read_reg(dev->pit, addr & 0x07);
break;
case 0x60:
if (dev->rev >= 0x01)
ret = inb(0x0070);
else
ret = dev->pci_conf[addr];
break;
}
sis_5513_pci_to_isa_log("SiS 5513 P2I: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
switch (addr) {
case 0x22:
dev->index = val - 0x50;
break;
case 0x23:
sis_5513_pci_to_isa_log("SiS 5513 ISA: [W] dev->regs[%02X] = %02X\n", dev->index + 0x50, val);
switch (dev->index) {
case 0x00:
dev->regs[dev->index] = val & 0xed;
switch (val >> 6) {
case 0:
cpu_set_isa_speed(7159091);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
nvr_bank_set(0, !!(val & 0x08), dev->nvr);
break;
case 0x01:
dev->regs[dev->index] = val & 0xf4;
break;
case 0x03:
dev->regs[dev->index] = val & 3;
break;
case 0x04: /* BIOS Register */
dev->regs[dev->index] = val;
break;
case 0x05:
dev->regs[dev->index] = val;
outb(0x70, val);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
sis_5513_isa_read(uint16_t addr, void *priv)
{
const sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t ret = 0xff;
if (addr == 0x23) {
if (dev->index == 0x05)
ret = inb(0x70);
else
ret = dev->regs[dev->index];
sis_5513_pci_to_isa_log("SiS 5513 ISA: [R] dev->regs[%02X] = %02X\n", dev->index + 0x50, ret);
}
return ret;
}
static void
sis_5513_00_pci_to_isa_reset(sis_5513_pci_to_isa_t *dev)
{
dev->pci_conf[0x60] = dev->pci_conf[0x61] = 0x80;
dev->pci_conf[0x62] = 0x00;
dev->pci_conf[0x63] = 0x80;
dev->pci_conf[0x64] = 0x00;
dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x66] = dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6a] = 0x04;
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
dev->regs[0x00] = dev->regs[0x01] = 0x00;
dev->regs[0x03] = dev->regs[0x04] = 0x00;
dev->regs[0x05] = 0x00;
dev->regs[0x08] = dev->regs[0x09] = 0x00;
dev->regs[0x0a] = dev->regs[0x0b] = 0x00;
}
static void
sis_5513_01_pci_to_isa_reset(sis_5513_pci_to_isa_t *dev)
{
dev->pci_conf[0x45] = dev->pci_conf[0x46] = 0x00;
dev->pci_conf[0x47] = 0x00;
dev->pci_conf[0x61] = 0x80;
dev->pci_conf[0x62] = 0x00;
dev->pci_conf[0x63] = 0x80;
dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x66] = dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0x68] = 0x80;
dev->pci_conf[0x69] = dev->pci_conf[0x6a] = 0x00;
dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = 0x02;
dev->pci_conf[0x6d] = 0x00;
dev->pci_conf[0x6e] = dev->pci_conf[0x6f] = 0x00;
dev->pci_conf[0x70] = dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x76] = dev->pci_conf[0x77] = 0x00;
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
}
static void
sis_5513_11_pci_to_isa_reset(sis_5513_pci_to_isa_t *dev)
{
dev->pci_conf[0x45] = dev->pci_conf[0x46] = 0x00;
dev->pci_conf[0x47] = 0x00;
dev->pci_conf[0x61] = dev->pci_conf[0x62] = 0x80;
dev->pci_conf[0x63] = dev->pci_conf[0x64] = 0x00;
dev->pci_conf[0x65] = dev->pci_conf[0x66] = 0x00;
dev->pci_conf[0x67] = dev->pci_conf[0x68] = 0x00;
dev->pci_conf[0x69] = 0x01;
dev->pci_conf[0x6a] = 0x80;
dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = 0x20;
dev->pci_conf[0x6d] = 0x19;
dev->pci_conf[0x6e] = dev->pci_conf[0x6f] = 0x00;
dev->pci_conf[0x70] = 0x12;
dev->pci_conf[0x71] = dev->pci_conf[0x72] = 0x00;
dev->pci_conf[0x73] = dev->pci_conf[0x74] = 0x00;
dev->pci_conf[0x75] = dev->pci_conf[0x76] = 0x00;
dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x88] = 0x00;
dev->pci_conf[0x89] = dev->pci_conf[0x8a] = 0x00;
dev->pci_conf[0x90] = dev->pci_conf[0x91] = 0x00;
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
picint_common(0xffff, 0, 0, NULL);
sis_5595_ddma_recalc(dev);
sis_5595_acpi_recalc(dev);
dev->sis->ide_bits_1_3_writable = 0;
dev->sis->usb_enabled = 0;
sis_5513_apc_recalc(dev, 0);
}
static void
sis_5513_b0_pci_to_isa_reset(sis_5513_pci_to_isa_t *dev)
{
dev->pci_conf[0x45] = dev->pci_conf[0x46] = 0x00;
dev->pci_conf[0x47] = 0x00;
dev->pci_conf[0x61] = dev->pci_conf[0x62] = 0x80;
dev->pci_conf[0x63] = dev->pci_conf[0x64] = 0x00;
dev->pci_conf[0x65] = 0x01;
dev->pci_conf[0x66] = dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0x68] = 0x90;
dev->pci_conf[0x69] = 0x02;
dev->pci_conf[0x6a] = 0x80;
dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = 0x20;
dev->pci_conf[0x6d] = 0x19;
dev->pci_conf[0x6e] = dev->pci_conf[0x6f] = 0x00;
dev->pci_conf[0x70] = 0x12;
dev->pci_conf[0x71] = dev->pci_conf[0x72] = 0x00;
dev->pci_conf[0x7a] = dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x7c] = dev->pci_conf[0x7d] = 0x00;
dev->pci_conf[0x7e] = 0x80;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x88] = 0x00;
dev->pci_conf[0x89] = dev->pci_conf[0x8a] = 0x00;
dev->pci_conf[0x8b] = dev->pci_conf[0x8c] = 0x00;
dev->pci_conf[0x90] = dev->pci_conf[0x91] = 0x00;
pci_set_mirq_routing(PCI_MIRQ3, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ6, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ7, 15);
sff_set_mirq(dev->sis->bm[0], 2);
sff_set_mirq(dev->sis->bm[1], 7);
picint_common(0xffff, 0, 0, NULL);
sis_5595_ddma_recalc(dev);
sis_5595_acpi_recalc(dev);
/* SiS 5595 Data Acquisition Module */
sis_5595_dam_recalc(dev);
sis_5595_dam_reset(dev);
dev->dam_irq_enable = 0;
cpu_cpurst_on_sr = 1;
dev->sis->usb_enabled = 0;
sis_5513_apc_recalc(dev, 0);
if (dev->rev == 0x81)
dev->dam_irq_enable = 1;
}
static void
sis_5513_pci_to_isa_reset(void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x08;
dev->pci_conf[0x03] = 0x00;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x05] = dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x02;
if ((dev->rev == 0x11) || (dev->rev == 0x81))
dev->pci_conf[0x08] = 0x01;
else
dev->pci_conf[0x08] = dev->rev;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0e] = 0x80;
dev->pci_conf[0x40] = 0x00;
dev->pci_conf[0x41] = dev->pci_conf[0x42] = 0x80;
dev->pci_conf[0x43] = dev->pci_conf[0x44] = 0x80;
dev->pci_conf[0x48] = dev->pci_conf[0x49] = 0x00;
dev->pci_conf[0x4a] = dev->pci_conf[0x4b] = 0x00;
switch (dev->rev) {
case 0x00:
sis_5513_00_pci_to_isa_reset(dev);
break;
case 0x01:
sis_5513_01_pci_to_isa_reset(dev);
break;
case 0x11:
sis_5513_11_pci_to_isa_reset(dev);
break;
case 0x81:
case 0xb0:
sis_5513_b0_pci_to_isa_reset(dev);
break;
}
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
cpu_set_isa_speed(7159091);
nvr_bank_set(0, 0, dev->nvr);
}
static void
sis_5513_pci_to_isa_close(void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
FILE *fp = NULL;
if (dev->fn != NULL)
fp = nvr_fopen(dev->fn, "wb");
if (fp != NULL) {
(void) fwrite(dev->apc_regs, 256, 1, fp);
fclose(fp);
}
if (dev->fn != NULL)
free(dev->fn);
free(dev);
}
static void *
sis_5513_pci_to_isa_init(UNUSED(const device_t *info))
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) calloc(1, sizeof(sis_5513_pci_to_isa_t));
uint8_t pit_is_fast = (((pit_mode == -1) && is486) || (pit_mode == 1));
FILE *fp = NULL;
int c;
dev->rev = info->local;
dev->sis = device_get_common_priv();
/* IDEIRQ */
pci_enable_mirq(2);
/* Port 92h */
dev->port_92 = device_add(&port_92_device);
/* PIT */
dev->pit = device_find_first_priv(DEVICE_PIT);
dev->pit_read_reg = pit_is_fast ? pitf_read_reg : pit_read_reg;
/* NVR */
dev->nvr = device_add(&at_mb_nvr_device);
switch (dev->rev) {
case 0x00:
/* MIRQ */
pci_enable_mirq(0);
pci_enable_mirq(1);
/* Ports 22h-23h: SiS 5513 ISA */
io_sethandler(0x0022, 0x0002,
sis_5513_isa_read, NULL, NULL, sis_5513_isa_write, NULL, NULL, dev);
break;
case 0x01:
/* MIRQ */
pci_enable_mirq(1);
break;
case 0x11:
case 0x81:
case 0xb0:
/* USBIRQ */
pci_enable_mirq(3);
/* ACPI/SCI IRQ */
pci_enable_mirq(5);
if (dev->rev == 0xb0) {
/* Data Acquisition Module and SMBUS IRQ */
pci_enable_mirq(6);
/* Non-remapped native IDE IRQ */
pci_enable_mirq(7);
}
dev->ddma = device_add(&ddma_device);
switch (dev->rev) {
case 0x11:
dev->sis->acpi = device_add(&acpi_sis_5582_device);
break;
case 0x81:
dev->sis->acpi = device_add(&acpi_sis_5595_1997_device);
break;
case 0xb0:
dev->sis->acpi = device_add(&acpi_sis_5595_device);
dev->smbus = acpi_get_smbus(dev->sis->acpi);
break;
}
dev->sis->acpi->priv = dev->sis;
acpi_set_slot(dev->sis->acpi, dev->sis->sb_pci_slot);
acpi_set_nvr(dev->sis->acpi, dev->nvr);
/* Set up the NVR file's name. */
c = strlen(machine_get_internal_name()) + 9;
dev->fn = (char *) malloc(c + 1);
sprintf(dev->fn, "%s_apc.nvr", machine_get_internal_name());
fp = nvr_fopen(dev->fn, "rb");
memset(dev->apc_regs, 0x00, sizeof(dev->apc_regs));
sis_5513_apc_reset(dev);
if (fp != NULL) {
if (fread(dev->apc_regs, 1, 256, fp) != 256)
fatal("sis_5513_pci_to_isa_init(): Error reading APC data\n");
fclose(fp);
}
acpi_set_irq_mode(dev->sis->acpi, 2);
break;
}
sis_5513_pci_to_isa_reset(dev);
return dev;
}
const device_t sis_5513_p2i_device = {
.name = "SiS 5513 PCI to ISA bridge",
.internal_name = "sis_5513_pci_to_isa",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5572_p2i_device = {
.name = "SiS 5572 PCI to ISA bridge",
.internal_name = "sis_5572_pci_to_isa",
.flags = DEVICE_PCI,
.local = 0x01,
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5582_p2i_device = {
.name = "SiS 5582 PCI to ISA bridge",
.internal_name = "sis_5582_pci_to_isa",
.flags = DEVICE_PCI,
.local = 0x11, /* Actually, 0x01, but we need to somehow distinguish it
from SiS 5572 and SiS 5595 1997, which are also revision 0x01. */
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5595_1997_p2i_device = {
.name = "SiS 5595 (1997) PCI to ISA bridge",
.internal_name = "sis_5595_1997_pci_to_isa",
.flags = DEVICE_PCI,
.local = 0x81, /* Actually, 0x01, but we need to somehow distinguish it
from SiS 5572 and SiS 5582, which are also revision 0x01. */
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5595_p2i_device = {
.name = "SiS 5595 PCI to ISA bridge",
.internal_name = "sis_5595_pci_to_isa",
.flags = DEVICE_PCI,
.local = 0xb0,
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5513_p2i.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 13,820 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M6117 SoC.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/port_92.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/chipset.h>
#include <86box/plat_fallthrough.h>
typedef struct ali6117_t {
uint32_t local;
/* Main registers (port 22h/23h) */
uint8_t unlocked;
uint8_t mode;
uint8_t reg_offset;
uint8_t regs[256];
} ali6117_t;
/* Total size, Bank 0 size, Bank 1 size, Bank 2 size, Bank 3 size. */
static uint32_t ali6117_modes[32][5] = {
// clang-format off
{ 1024, 512, 512, 0, 0 },
{ 2048, 512, 512, 512, 512 },
{ 3072, 512, 512, 2048, 0 },
{ 5120, 512, 512, 2048, 2048 },
{ 9216, 512, 512, 8192, 0 },
{ 1024, 1024, 0, 0, 0 },
{ 2048, 1024, 1024, 0, 0 },
{ 4096, 1024, 1024, 2048, 0 },
{ 6144, 1024, 1024, 2048, 2048 },
{ 10240, 1024, 1024, 8192, 0 },
{ 18432, 1024, 1024, 8192, 8192 },
{ 3072, 1024, 2048, 0, 0 },
{ 5120, 1024, 2048, 2048, 0 },
{ 9216, 1024, 8192, 0, 0 },
{ 2048, 2048, 0, 0, 0 },
{ 4096, 2048, 2048, 0, 0 },
{ 6144, 2048, 2048, 2048, 0 },
{ 8192, 2048, 2048, 2048, 2048 },
{ 12288, 2048, 2048, 8192, 0 },
{ 20480, 2048, 2048, 8192, 8192 },
{ 10240, 2048, 8192, 0, 0 },
{ 18432, 2048, 8192, 8192, 0 },
{ 26624, 2048, 8192, 8192, 8192 },
{ 4096, 4096, 0, 0, 0 },
{ 8192, 4096, 4096, 0, 0 },
{ 24576, 4096, 4096, 8192, 8192 },
{ 12288, 4096, 8192, 0, 0 },
{ 8192, 8192, 0, 0, 0 },
{ 16384, 8192, 8192, 0, 0 },
{ 24576, 8192, 8192, 8192, 0 },
{ 32768, 8192, 8192, 8192, 8192 },
{ 65536, 32768, 32768, 0, 0 }
// clang-format on
};
#ifdef ENABLE_ALI6117_LOG
int ali6117_do_log = ENABLE_ALI6117_LOG;
static void
ali6117_log(const char *fmt, ...)
{
va_list ap;
if (ali6117_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali6117_log(fmt, ...)
#endif
static void
ali6117_recalcmapping(ali6117_t *dev)
{
uint32_t base;
uint32_t size;
int state;
shadowbios = 0;
shadowbios_write = 0;
ali6117_log("ALI6117: Shadowing for A0000-BFFFF (reg 12 bit 1) = %s\n", (dev->regs[0x12] & 0x02) ? "on" : "off");
mem_set_mem_state(0xa0000, 0x20000, (dev->regs[0x12] & 0x02) ? (MEM_WRITE_INTERNAL | MEM_READ_INTERNAL) : (MEM_WRITE_EXTANY | MEM_READ_EXTANY));
for (uint8_t reg = 0; reg <= 1; reg++) {
for (uint8_t bitpair = 0; bitpair <= 3; bitpair++) {
size = 0x8000;
base = 0xc0000 + (size * ((reg * 4) + bitpair));
ali6117_log("ALI6117: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x14 + reg, bitpair, 1 << ((bitpair * 2) + 1), 1 << (bitpair * 2));
state = 0;
if (dev->regs[0x14 + reg] & (1 << ((bitpair * 2) + 1))) {
ali6117_log(" w on");
state |= MEM_WRITE_INTERNAL;
if (base >= 0xe0000)
shadowbios_write |= 1;
} else {
ali6117_log(" w off");
state |= MEM_WRITE_EXTANY;
}
if (dev->regs[0x14 + reg] & (1 << (bitpair * 2))) {
ali6117_log("; r on\n");
state |= MEM_READ_INTERNAL;
if (base >= 0xe0000)
shadowbios |= 1;
} else {
ali6117_log("; r off\n");
state |= MEM_READ_EXTANY;
}
mem_set_mem_state(base, size, state);
}
}
flushmmucache_nopc();
}
static void
ali6117_bank_recalc(ali6117_t *dev)
{
uint32_t bank;
uint32_t addr;
for (uint32_t i = 0x00000000; i < (mem_size << 10); i += 4096) {
if ((i >= 0x000a0000) && (i < 0x00100000))
continue;
if (!is6117 && (i >= 0x00f00000) && (i < 0x01000000))
continue;
if (is6117 && (i >= 0x03f00000) && (i < 0x04000000))
continue;
switch (dev->regs[0x10] & 0xf8) {
case 0xe8:
bank = (i >> 12) & 3;
addr = (i & 0xfff) | ((i >> 14) << 12);
ali6117_log("E8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024);
if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024))
mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0xf8:
bank = (i >> 12) & 1;
addr = (i & 0xfff) | ((i >> 13) << 12);
ali6117_log("F8 (%08X): Bank %i, address %08X vs. bank size %08X\n", i, bank, addr, ali6117_modes[dev->mode][bank + 1] * 1024);
if (addr < (ali6117_modes[dev->mode][bank + 1] * 1024))
mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(i, 4096, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
default:
mem_set_mem_state_both(i, 4096, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
}
flushmmucache();
}
static void
ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
{
ali6117_t *dev = (ali6117_t *) priv;
ali6117_log("ALI6117: reg_write(%04X, %02X)\n", addr, val);
if (addr == 0x22)
dev->reg_offset = val;
else if (dev->reg_offset == 0x13)
dev->unlocked = (val == 0xc5);
else if (dev->unlocked) {
ali6117_log("ALI6117: regs[%02X] = %02X\n", dev->reg_offset, val);
if (!(dev->local & 0x08) || (dev->reg_offset < 0x30))
switch (dev->reg_offset) {
case 0x30:
case 0x34:
case 0x35:
case 0x3e:
case 0x3f:
case 0x46:
case 0x4c:
case 0x6a:
case 0x73:
return; /* read-only registers */
case 0x10:
refresh_at_enable = !(val & 0x02) || !!(dev->regs[0x20] & 0x80);
dev->regs[dev->reg_offset] = val;
if (dev->local != 0x8) {
if (val & 0x04)
mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else
mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
ali6117_bank_recalc(dev);
}
break;
case 0x12:
val &= 0xf7;
fallthrough;
case 0x14:
case 0x15:
dev->regs[dev->reg_offset] = val;
ali6117_recalcmapping(dev);
break;
case 0x1e:
val &= 0x07;
switch (val) {
/* Half PIT clock. */
case 0x0:
cpu_set_isa_speed(7159091);
break;
/* Divisors on the input clock PCLK2, which is double the CPU clock. */
case 0x1:
cpu_set_isa_speed(cpu_busspeed / 1.5);
break;
case 0x2:
cpu_set_isa_speed(cpu_busspeed / 2);
break;
case 0x3:
cpu_set_isa_speed(cpu_busspeed / 2.5);
break;
case 0x4:
cpu_set_isa_speed(cpu_busspeed / 3);
break;
case 0x5:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 0x6:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
case 0x7:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
default:
break;
}
break;
case 0x20:
val &= 0xbf;
refresh_at_enable = !(dev->regs[0x10] & 0x02) || !!(val & 0x80);
break;
case 0x31:
/* TODO: fast gate A20 (bit 0) */
val &= 0x21;
break;
case 0x32:
val &= 0xc1;
break;
case 0x33:
val &= 0xfd;
break;
case 0x36:
val &= 0xf0;
val |= dev->regs[dev->reg_offset];
break;
case 0x37:
val &= 0xf5;
break;
case 0x3c:
val &= 0x8f;
ide_pri_disable();
ide_set_base(1, (val & 0x01) ? 0x170 : 0x1f0);
ide_set_side(1, (val & 0x01) ? 0x376 : 0x3f6);
ide_pri_enable();
break;
case 0x44:
case 0x45:
val &= 0x3f;
break;
case 0x4a:
val &= 0xfe;
break;
case 0x55:
val &= 0x03;
break;
case 0x56:
val &= 0xc7;
break;
case 0x58:
val &= 0xc3;
break;
case 0x59:
val &= 0x60;
break;
case 0x5b:
val &= 0x1f;
break;
case 0x64:
val &= 0xf7;
break;
case 0x66:
val &= 0xe3;
break;
case 0x67:
val &= 0xdf;
break;
case 0x69:
val &= 0x50;
break;
case 0x6b:
val &= 0x7f;
break;
case 0x6e:
case 0x6f:
val &= 0x03;
break;
case 0x71:
val &= 0x1f;
break;
default:
break;
}
dev->regs[dev->reg_offset] = val;
}
}
static uint8_t
ali6117_reg_read(uint16_t addr, void *priv)
{
const ali6117_t *dev = (ali6117_t *) priv;
uint8_t ret;
if (addr == 0x22)
ret = dev->reg_offset;
else
ret = dev->regs[dev->reg_offset];
ali6117_log("ALI6117: reg_read(%04X) = %02X\n", dev->reg_offset, ret);
return ret;
}
static void
ali6117_reset(void *priv)
{
ali6117_t *dev = (ali6117_t *) priv;
ali6117_log("ALI6117: reset()\n");
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x11] = 0xf8;
dev->regs[0x12] = 0x20;
dev->regs[0x17] = 0xff;
dev->regs[0x18] = 0xf0;
dev->regs[0x1a] = 0xff;
dev->regs[0x1b] = 0xf0;
dev->regs[0x1d] = 0xff;
dev->regs[0x20] = 0x80;
if (dev->local & 0x08) {
dev->regs[0x30] = 0x08;
dev->regs[0x31] = 0x01;
dev->regs[0x34] = 0x04; /* enable internal RTC */
dev->regs[0x35] = 0x20; /* enable internal KBC */
dev->regs[0x36] = dev->local & 0x07; /* M6117D ID */
}
cpu_set_isa_speed(7159091);
refresh_at_enable = 1;
if (dev->local != 0x8) {
/* On-board memory 15-16M is enabled by default. */
mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
ali6117_bank_recalc(dev);
}
}
static void
ali6117_setup(ali6117_t *dev)
{
ali6117_log("ALI6117: setup()\n");
/* Main register interface */
io_sethandler(0x22, 2,
ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev);
}
static void
ali6117_close(void *priv)
{
ali6117_t *dev = (ali6117_t *) priv;
ali6117_log("ALI6117: close()\n");
io_removehandler(0x22, 2,
ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev);
free(dev);
}
static void *
ali6117_init(const device_t *info)
{
int last_match = 0;
ali6117_log("ALI6117: init()\n");
ali6117_t *dev = (ali6117_t *) malloc(sizeof(ali6117_t));
memset(dev, 0, sizeof(ali6117_t));
dev->local = info->local;
if (!(dev->local & 0x08))
device_add(&ide_isa_device);
ali6117_setup(dev);
for (int8_t i = 31; i >= 0; i--) {
if ((mem_size >= ali6117_modes[i][0]) && (ali6117_modes[i][0] > last_match)) {
last_match = ali6117_modes[i][0];
dev->mode = i;
}
}
ali6117_reset(dev);
if (!(dev->local & 0x08))
pic_elcr_io_handler(0);
return dev;
}
const device_t ali1217_device = {
.name = "ALi M1217",
.internal_name = "ali1217",
.flags = DEVICE_AT,
.local = 0x8,
.init = ali6117_init,
.close = ali6117_close,
.reset = ali6117_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ali6117d_device = {
.name = "ALi M6117D",
.internal_name = "ali6117d",
.flags = DEVICE_AT,
.local = 0x2,
.init = ali6117_init,
.close = ali6117_close,
.reset = ali6117_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali6117.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,641 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 82335(KU82335) chipset.
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
/* Shadow capabilities */
#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#define ENABLED_SHADOW ((LOCK_STATUS) ? RO_SHADOW : RW_SHADOW)
#define RW_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define RO_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_DISABLED)
/* Granularity Register Enable & Recalc */
#define EXTENDED_GRANULARITY_ENABLED (dev->regs[0x2c] & 0x01)
#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i + 8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW)
/* R/W operator for the Video RAM region */
#define DETERMINE_VIDEO_RAM_WRITE_ACCESS ((dev->regs[0x22] & (0x08 << 8)) ? RW_SHADOW : RO_SHADOW)
/* Base System 512/640KB switch */
#define ENABLE_TOP_128KB (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define DISABLE_TOP_128KB (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
/* ROM size determination */
#define ROM_SIZE ((dev->regs[0x22] & (0x01 << 8)) ? 0xe0000 : 0xf0000)
/* Lock status */
#define LOCK_STATUS (dev->regs[0x22] & (0x80 << 8))
/* Define Memory Remap Sizes */
#define DEFINE_RC1_REMAP_SIZE ((dev->regs[0x24] & 0x02) ? 128 : 256)
#define DEFINE_RC2_REMAP_SIZE ((dev->regs[0x26] & 0x02) ? 128 : 256)
typedef struct intel_82335_t {
uint16_t regs[256];
uint16_t cfg_locked;
} intel_82335_t;
#ifdef ENABLE_INTEL_82335_LOG
int intel_82335_do_log = ENABLE_INTEL_82335_LOG;
static void
intel_82335_log(const char *fmt, ...)
{
va_list ap;
if (intel_82335_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define intel_82335_log(fmt, ...)
#endif
static void
intel_82335_write(uint16_t addr, uint16_t val, void *priv)
{
intel_82335_t *dev = (intel_82335_t *) priv;
uint32_t romsize = 0;
uint32_t base = 0;
uint32_t rc1_remap = 0;
uint32_t rc2_remap = 0;
dev->regs[addr] = val;
if (!dev->cfg_locked) {
intel_82335_log("Register %02x: Write %04x\n", addr, val);
switch (addr) {
case 0x22: /* Memory Controller */
/* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */
romsize = ROM_SIZE;
if (!EXTENDED_GRANULARITY_ENABLED) {
shadowbios = !!(dev->regs[0x22] & 0x01);
shadowbios_write = !!(dev->regs[0x22] & 0x01);
/* Base System 512/640KB set */
#if 0
mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
#endif
/* Video RAM shadow*/
mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW);
/* Option ROM shadow */
mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW);
/* System ROM shadow */
mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW);
}
break;
case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */
case 0x26:
rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0;
rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0;
mem_remap_top(rc1_remap + rc2_remap);
break;
case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */
if (EXTENDED_GRANULARITY_ENABLED) {
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
shadowbios = (dev->regs[0x2e] & (1 << (i + 8))) && (base == romsize);
shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize);
mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC);
}
}
break;
default:
break;
}
}
/* Unlock/Lock configuration registers */
dev->cfg_locked = LOCK_STATUS;
}
static uint16_t
intel_82335_read(uint16_t addr, void *priv)
{
const intel_82335_t *dev = (intel_82335_t *) priv;
intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]);
return dev->regs[addr];
}
static void
intel_82335_close(void *priv)
{
intel_82335_t *dev = (intel_82335_t *) priv;
free(dev);
}
static void *
intel_82335_init(UNUSED(const device_t *info))
{
intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t));
memset(dev, 0, sizeof(intel_82335_t));
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x22] = 0x08;
dev->regs[0x28] = 0xf9;
dev->cfg_locked = 0;
/* Memory Configuration */
io_sethandler(0x0022, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
/* Roll Comparison */
io_sethandler(0x0024, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
io_sethandler(0x0026, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
/* Address Range Comparison */
io_sethandler(0x0028, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
io_sethandler(0x002a, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
/* Granularity Enable */
io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
/* Extended Granularity */
io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
return dev;
}
const device_t intel_82335_device = {
.name = "Intel 82335",
.internal_name = "intel_82335",
.flags = 0,
.local = 0,
.init = intel_82335_init,
.close = intel_82335_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_82335.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,084 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 55xx common structure.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#ifdef ENABLE_SIS_55XX_COMMON_LOG
int sis_55xx_common_do_log = ENABLE_SIS_55XX_COMMON_LOG;
static void
sis_55xx_common_log(const char *fmt, ...)
{
va_list ap;
if (sis_55xx_common_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_55xx_common_log(fmt, ...)
#endif
static void
sis_55xx_common_close(void *priv)
{
sis_55xx_common_t *dev = (sis_55xx_common_t *) priv;
free(dev);
}
static void *
sis_55xx_common_init(UNUSED(const device_t *info))
{
sis_55xx_common_t *dev = (sis_55xx_common_t *) calloc(1, sizeof(sis_55xx_common_t));
return dev;
}
const device_t sis_55xx_common_device = {
.name = "SiS 55xx Common Structure",
.internal_name = "sis_55xx_common",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_55xx_common_init,
.close = sis_55xx_common_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_55xx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 680 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1409 chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering.
*
*
*
* Authors: Jose Phillips, <jose@latinol.com>
* Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_ALI1409_LOG
int ali1409_do_log = ENABLE_ALI1409_LOG;
static void
ali1409_log(const char *fmt, ...)
{
va_list ap;
if (ali1409_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1409_log(fmt, ...)
#endif
typedef struct ali_1409_t {
uint8_t is_g;
uint8_t index;
uint8_t cfg_locked;
uint8_t reg_57h;
uint8_t regs[256];
uint8_t last_reg;
} ali1409_t;
static void
ali1409_write(uint16_t addr, uint8_t val, void *priv)
{
ali1409_t *dev = (ali1409_t *) priv;
ali1409_log ("INPUT:addr %02x ,Value %02x \n" , addr , val);
if (addr & 1) {
if (dev->cfg_locked) {
if (dev->last_reg == 0x14 && val == 0x09)
dev->cfg_locked = 0;
dev->last_reg = val;
return;
}
if (dev->index == 0xff && val == 0xff)
dev->cfg_locked = 1;
else {
ali1409_log("Write reg %02x %02x %08x\n", dev->index, val, cs);
dev->regs[dev->index] = val;
switch (dev->index) {
case 0xa:
switch ((val >> 4) & 3) {
case 0:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
break;
case 0xb:
switch ((val >> 4) & 3) {
case 0:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY| MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
break;
}
}
} else
dev->index = val;
}
static uint8_t
ali1409_read(uint16_t addr, void *priv)
{
ali1409_log ("reading at %02X\n",addr);
const ali1409_t *dev = (ali1409_t *) priv;
uint8_t ret = 0xff;
if (dev->cfg_locked)
ret = 0xff;
if (addr & 1) {
if ((dev->index >= 0xc0 || dev->index == 0x20) && cpu_iscyrix)
ret = 0xff;
ret = dev->regs[dev->index];
} else
ret = dev->index;
return ret;
}
static void
ali1409_close(void *priv)
{
ali1409_t *dev = (ali1409_t *) priv;
free(dev);
}
static void *
ali1409_init(const device_t *info)
{
ali1409_t *dev = (ali1409_t *) malloc(sizeof(ali1409_t));
memset(dev, 0, sizeof(ali1409_t));
dev->cfg_locked = 1;
/* M1409 Ports:
22h Index Port
23h Data Port
*/
ali1409_log ("Bus speed: %i",cpu_busspeed);
io_sethandler(0x0022, 0x0002, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
io_sethandler(0x037f, 0x0001, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
io_sethandler(0x03f3, 0x0001, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
return dev;
}
const device_t ali1409_device = {
.name = "ALi M1409",
.internal_name = "ali1409",
.flags = 0,
.local = 0,
.init = ali1409_init,
.close = ali1409_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1409.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,439 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the HEADLAND AT286 chipset.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Fred N. van Kempen, <decwiz@yahoo.com>
* Original by GreatPsycho for PCem.
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include "x86.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
enum {
HEADLAND_GC103 = 0x00,
HEADLAND_GC113 = 0x10,
HEADLAND_HT18_A = 0x11,
HEADLAND_HT18_B = 0x12,
HEADLAND_HT18_C = 0x18,
HEADLAND_HT21_C_D = 0x31,
HEADLAND_HT21_E = 0x32,
};
#define HEADLAND_REV_MASK 0x0F
#define HEADLAND_HAS_CRI 0x10
#define HEADLAND_HAS_SLEEP 0x20
typedef struct headland_mr_t {
uint8_t valid;
uint8_t enabled;
uint16_t mr;
uint32_t virt_base;
struct headland_t *headland;
} headland_mr_t;
typedef struct headland_t {
uint8_t revision;
uint8_t has_cri;
uint8_t has_sleep;
uint8_t cri;
uint8_t cr[7];
uint8_t indx;
uint8_t regs[256];
uint8_t ems_mar;
headland_mr_t null_mr;
headland_mr_t ems_mr[64];
mem_mapping_t low_mapping;
mem_mapping_t ems_mapping[64];
mem_mapping_t mid_mapping;
mem_mapping_t high_mapping;
mem_mapping_t shadow_mapping[2];
mem_mapping_t upper_mapping[24];
} headland_t;
/* TODO - Headland chipset's memory address mapping emulation isn't fully implemented yet,
so memory configuration is hardcoded now. */
static const int mem_conf_cr0[41] = {
0x00, 0x00, 0x20, 0x40, 0x60, 0xA0, 0x40, 0xE0,
0xA0, 0xC0, 0xE0, 0xE0, 0xC0, 0xE0, 0xE0, 0xE0,
0xE0, 0x20, 0x40, 0x40, 0xA0, 0xC0, 0xE0, 0xE0,
0xC0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
0x20, 0x40, 0x60, 0x60, 0xC0, 0xE0, 0xE0, 0xE0,
0xE0
};
static const int mem_conf_cr1[41] = {
0x00, 0x40, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40,
0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x00, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
0x00, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
0x40
};
static uint32_t
get_addr(headland_t *dev, uint32_t addr, headland_mr_t *mr)
{
uint32_t bank_base[4];
uint32_t bank_shift[4];
uint32_t shift;
uint32_t other_shift;
uint32_t bank;
if ((addr >= 0x0e0000) && (addr <= 0x0fffff))
return addr;
else if ((addr >= 0xfe0000) && (addr <= 0xffffff))
return addr & 0x0fffff;
if (dev->revision == 8) {
shift = (dev->cr[0] & 0x80) ? 21 : ((dev->cr[6] & 0x01) ? 23 : 19);
other_shift = (dev->cr[0] & 0x80) ? ((dev->cr[6] & 0x01) ? 19 : 23) : 21;
} else {
shift = (dev->cr[0] & 0x80) ? 21 : 19;
other_shift = (dev->cr[0] & 0x80) ? 21 : 19;
}
/* Bank size = 1 << (bank shift + 2) . */
bank_shift[0] = bank_shift[1] = shift;
bank_base[0] = 0x00000000;
bank_base[1] = bank_base[0] + (1 << shift);
bank_base[2] = bank_base[1] + (1 << shift);
if ((dev->revision > 0) && (dev->revision < 8) && (dev->cr[1] & 0x40)) {
bank_shift[2] = bank_shift[3] = other_shift;
bank_base[3] = bank_base[2] + (1 << other_shift);
/* First address after the memory is bank_base[3] + (1 << other_shift) */
} else {
bank_shift[2] = bank_shift[3] = shift;
bank_base[3] = bank_base[2] + (1 << shift);
/* First address after the memory is bank_base[3] + (1 << shift) */
}
if (mr && mr->valid && (dev->cr[0] & 2) && (mr->mr & 0x200)) {
addr = (addr & 0x3fff) | ((mr->mr & 0x1F) << 14);
bank = (mr->mr >> 7) & 3;
if (bank_shift[bank] >= 21)
addr |= (mr->mr & 0x060) << 14;
if ((dev->revision == 8) && (bank_shift[bank] == 23))
addr |= (mr->mr & 0xc00) << 11;
addr |= bank_base[(mr->mr >> 7) & 3];
} else if (((mr == NULL) || !mr->valid) && (mem_size >= 1024) && (addr >= 0x100000) && ((dev->cr[0] & 4) == 0))
addr -= 0x60000;
return addr;
}
static void
hl_ems_disable(headland_t *dev, uint8_t mar, uint32_t base_addr, uint8_t indx)
{
if (base_addr < (mem_size << 10))
mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + base_addr);
else
mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL);
mem_mapping_disable(&dev->ems_mapping[mar & 0x3f]);
if (indx < 24) {
mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_enable(&dev->upper_mapping[indx]);
} else
mem_set_mem_state(base_addr, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
static void
hl_ems_update(headland_t *dev, uint8_t mar)
{
uint32_t base_addr;
uint32_t virt_addr;
uint8_t indx = mar & 0x1f;
base_addr = (indx + 16) << 14;
if (indx >= 24)
base_addr += 0x20000;
hl_ems_disable(dev, mar, base_addr, indx);
dev->ems_mr[mar & 0x3f].enabled = 0;
dev->ems_mr[mar & 0x3f].virt_base = base_addr;
if ((dev->cr[0] & 2) && ((dev->cr[0] & 1) == ((mar & 0x20) >> 5)) && (dev->ems_mr[mar & 0x3f].mr & 0x200)) {
mem_set_mem_state(base_addr, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
virt_addr = get_addr(dev, base_addr, &dev->ems_mr[mar & 0x3f]);
dev->ems_mr[mar & 0x3f].enabled = 1;
dev->ems_mr[mar & 0x3f].virt_base = virt_addr;
if (indx < 24)
mem_mapping_disable(&dev->upper_mapping[indx]);
if (virt_addr < (mem_size << 10))
mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], ram + virt_addr);
else
mem_mapping_set_exec(&dev->ems_mapping[mar & 0x3f], NULL);
mem_mapping_enable(&dev->ems_mapping[mar & 0x3f]);
}
flushmmucache();
}
static void
set_global_EMS_state(headland_t *dev, UNUSED(int state))
{
for (uint8_t i = 0; i < 32; i++) {
hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20));
hl_ems_update(dev, i | ((dev->cr[0] & 0x01) << 5));
}
}
static void
memmap_state_default(headland_t *dev, uint8_t ht_romcs)
{
mem_mapping_disable(&dev->mid_mapping);
if (ht_romcs)
mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS);
else
mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_ROMCS | MEM_WRITE_ROMCS);
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_disable(&dev->shadow_mapping[1]);
}
static void
memmap_state_update(headland_t *dev)
{
uint32_t addr;
uint8_t ht_cr0 = dev->cr[0];
uint8_t ht_romcs = !(dev->cr[4] & 0x01);
if (dev->revision <= 1)
ht_romcs = 1;
if (!(dev->cr[0] & 0x04))
ht_cr0 &= ~0x18;
for (uint8_t i = 0; i < 24; i++) {
addr = get_addr(dev, 0x40000 + (i << 14), NULL);
mem_mapping_set_exec(&dev->upper_mapping[i], addr < (mem_size << 10) ? ram + addr : NULL);
}
memmap_state_default(dev, ht_romcs);
if (mem_size > 640) {
if (ht_cr0 & 0x04) {
mem_mapping_set_addr(&dev->mid_mapping, 0xA0000, 0x40000);
mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000);
mem_mapping_disable(&dev->mid_mapping);
if (mem_size > 1024) {
mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_set_addr(&dev->high_mapping, 0x100000, (mem_size - 1024) << 10);
mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000);
}
} else {
/* 1 MB - 1 MB + 384k: RAM pointing to A0000-FFFFF
1 MB + 384k: Any ram pointing 1 MB onwards. */
/* First, do the addresses above 1 MB. */
mem_mapping_set_addr(&dev->mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
mem_mapping_set_exec(&dev->mid_mapping, ram + 0xA0000);
if (mem_size > 1024) {
/* We have ram above 1 MB, we need to relocate that. */
mem_set_mem_state((mem_size << 10), 0x60000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_mapping_set_addr(&dev->high_mapping, 0x160000, (mem_size - 1024) << 10);
mem_mapping_set_exec(&dev->high_mapping, ram + 0x100000);
}
}
}
switch (ht_cr0) {
case 0x18:
if ((mem_size << 10) > 0xe0000) {
mem_set_mem_state(0x0e0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x20000);
mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000);
mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x20000);
mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000);
} else {
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_disable(&dev->shadow_mapping[1]);
}
break;
case 0x10:
if ((mem_size << 10) > 0xf0000) {
mem_set_mem_state(0x0f0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_set_mem_state(0xff0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0f0000, 0x10000);
mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xf0000);
mem_mapping_set_addr(&dev->shadow_mapping[1], 0xff0000, 0x10000);
mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xf0000);
} else {
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_disable(&dev->shadow_mapping[1]);
}
break;
case 0x08:
if ((mem_size << 10) > 0xe0000) {
mem_set_mem_state(0x0e0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_set_mem_state(0xfe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
mem_mapping_set_addr(&dev->shadow_mapping[0], 0x0e0000, 0x10000);
mem_mapping_set_exec(&dev->shadow_mapping[0], ram + 0xe0000);
mem_mapping_set_addr(&dev->shadow_mapping[1], 0xfe0000, 0x10000);
mem_mapping_set_exec(&dev->shadow_mapping[1], ram + 0xe0000);
} else {
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_disable(&dev->shadow_mapping[1]);
}
break;
case 0x00:
default:
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_disable(&dev->shadow_mapping[1]);
break;
}
set_global_EMS_state(dev, ht_cr0 & 3);
}
static void
hl_write(uint16_t addr, uint8_t val, void *priv)
{
headland_t *dev = (headland_t *) priv;
switch (addr) {
case 0x01ec:
dev->ems_mr[dev->ems_mar & 0x3f].mr = val | 0xff00;
hl_ems_update(dev, dev->ems_mar & 0x3f);
if (dev->ems_mar & 0x80)
dev->ems_mar++;
break;
case 0x01ed:
if (dev->has_cri)
dev->cri = val;
break;
case 0x01ee:
dev->ems_mar = val;
break;
case 0x01ef:
switch (dev->cri & 0x07) {
case 0:
dev->cr[0] = (val & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
memmap_state_update(dev);
break;
case 1:
dev->cr[1] = (val & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
memmap_state_update(dev);
break;
case 2:
case 3:
dev->cr[dev->cri] = val;
memmap_state_update(dev);
break;
case 5:
if (dev->has_sleep)
dev->cr[dev->cri] = val;
else
dev->cr[dev->cri] = val & 0x0f;
memmap_state_update(dev);
break;
case 4:
dev->cr[4] = (dev->cr[4] & 0xf0) | (val & 0x0f);
memmap_state_update(dev);
break;
case 6:
if (dev->revision == 8) {
dev->cr[dev->cri] = (val & 0xfe) | (mem_size > 8192 ? 1 : 0);
memmap_state_update(dev);
}
break;
default:
break;
}
break;
default:
break;
}
}
static void
hl_writew(uint16_t addr, uint16_t val, void *priv)
{
headland_t *dev = (headland_t *) priv;
switch (addr) {
case 0x01ec:
dev->ems_mr[dev->ems_mar & 0x3f].mr = val;
hl_ems_update(dev, dev->ems_mar & 0x3f);
if (dev->ems_mar & 0x80)
dev->ems_mar++;
break;
default:
break;
}
}
static void
hl_writel(uint16_t addr, uint32_t val, void *priv)
{
hl_writew(addr, val, priv);
hl_writew(addr + 2, val >> 16, priv);
}
static uint8_t
hl_read(uint16_t addr, void *priv)
{
headland_t *dev = (headland_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x01ec:
ret = (uint8_t) dev->ems_mr[dev->ems_mar & 0x3f].mr;
if (dev->ems_mar & 0x80)
dev->ems_mar++;
break;
case 0x01ed:
if (dev->has_cri)
ret = dev->cri;
break;
case 0x01ee:
ret = dev->ems_mar;
break;
case 0x01ef:
switch (dev->cri & 0x07) {
case 0:
ret = (dev->cr[0] & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
break;
case 1:
ret = (dev->cr[1] & 0xbf) | mem_conf_cr1[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
break;
case 6:
if (dev->revision == 8)
ret = (dev->cr[6] & 0xfe) | (mem_size > 8192 ? 1 : 0);
else
ret = 0;
break;
default:
ret = dev->cr[dev->cri];
break;
}
break;
default:
break;
}
return ret;
}
static uint16_t
hl_readw(uint16_t addr, void *priv)
{
headland_t *dev = (headland_t *) priv;
uint16_t ret = 0xffff;
switch (addr) {
case 0x01ec:
ret = dev->ems_mr[dev->ems_mar & 0x3f].mr | ((dev->cr[4] & 0x80) ? 0xf000 : 0xfc00);
if (dev->ems_mar & 0x80)
dev->ems_mar++;
break;
default:
break;
}
return ret;
}
static uint32_t
hl_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = hl_readw(addr, priv);
ret |= (hl_readw(addr + 2, priv) << 16);
return ret;
}
static uint8_t
mem_read_b(uint32_t addr, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
uint8_t ret = 0xff;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
ret = ram[addr];
return ret;
}
static uint16_t
mem_read_w(uint32_t addr, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
uint16_t ret = 0xffff;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
ret = *(uint16_t *) &ram[addr];
return ret;
}
static uint32_t
mem_read_l(uint32_t addr, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
uint32_t ret = 0xffffffff;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
ret = *(uint32_t *) &ram[addr];
return ret;
}
static void
mem_write_b(uint32_t addr, uint8_t val, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
ram[addr] = val;
}
static void
mem_write_w(uint32_t addr, uint16_t val, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
*(uint16_t *) &ram[addr] = val;
}
static void
mem_write_l(uint32_t addr, uint32_t val, void *priv)
{
headland_mr_t *mr = (headland_mr_t *) priv;
headland_t *dev = mr->headland;
addr = get_addr(dev, addr, mr);
if (addr < (mem_size << 10))
*(uint32_t *) &ram[addr] = val;
}
static void
headland_close(void *priv)
{
headland_t *dev = (headland_t *) priv;
free(dev);
}
static void *
headland_init(const device_t *info)
{
headland_t *dev;
int ht386 = 0;
dev = (headland_t *) malloc(sizeof(headland_t));
memset(dev, 0x00, sizeof(headland_t));
dev->has_cri = (info->local & HEADLAND_HAS_CRI);
dev->has_sleep = (info->local & HEADLAND_HAS_SLEEP);
dev->revision = info->local & HEADLAND_REV_MASK;
if (dev->revision > 0)
ht386 = 1;
dev->cr[0] = 0x04;
dev->cr[4] = dev->revision << 4;
if (ht386)
device_add(&port_92_inv_device);
io_sethandler(0x01ec, 4,
hl_read, hl_readw, hl_readl, hl_write, hl_writew, hl_writel, dev);
dev->null_mr.valid = 0;
dev->null_mr.mr = 0xff;
dev->null_mr.headland = dev;
for (uint8_t i = 0; i < 64; i++) {
dev->ems_mr[i].valid = 1;
dev->ems_mr[i].mr = 0x00;
dev->ems_mr[i].headland = dev;
}
/* Turn off mem.c mappings. */
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
mem_mapping_add(&dev->low_mapping, 0, 0x40000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
ram, MEM_MAPPING_INTERNAL, &dev->null_mr);
if (mem_size > 640) {
mem_mapping_add(&dev->mid_mapping, 0xa0000, 0x60000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
ram + 0xa0000, MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_disable(&dev->mid_mapping);
}
if (mem_size > 1024) {
mem_mapping_add(&dev->high_mapping, 0x100000, ((mem_size - 1024) * 1024),
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
ram + 0x100000, MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_enable(&dev->high_mapping);
}
for (uint8_t i = 0; i < 24; i++) {
mem_mapping_add(&dev->upper_mapping[i],
0x40000 + (i << 14), 0x4000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
mem_size > (256 + (i << 4)) ? (ram + 0x40000 + (i << 14)) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_enable(&dev->upper_mapping[i]);
}
mem_mapping_add(&dev->shadow_mapping[0],
0xe0000, 0x20000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_disable(&dev->shadow_mapping[0]);
mem_mapping_add(&dev->shadow_mapping[1],
0xfe0000, 0x20000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
((mem_size << 10) > 0xe0000) ? (ram + 0xe0000) : NULL,
MEM_MAPPING_INTERNAL, &dev->null_mr);
mem_mapping_disable(&dev->shadow_mapping[1]);
for (uint8_t i = 0; i < 64; i++) {
dev->ems_mr[i].mr = 0x00;
mem_mapping_add(&dev->ems_mapping[i],
((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000,
mem_read_b, mem_read_w, mem_read_l,
mem_write_b, mem_write_w, mem_write_l,
ram + (((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14),
MEM_MAPPING_INTERNAL, &dev->ems_mr[i]);
mem_mapping_disable(&dev->ems_mapping[i]);
}
memmap_state_update(dev);
return dev;
}
const device_t headland_gc10x_device = {
.name = "Headland GC101/102/103",
.internal_name = "headland_gc10x",
.flags = 0,
.local = HEADLAND_GC103,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_gc113_device = {
.name = "Headland GC101/102/113",
.internal_name = "headland_gc113",
.flags = 0,
.local = HEADLAND_GC113,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_ht18a_device = {
.name = "Headland HT18 Rev. A",
.internal_name = "headland_ht18a",
.flags = 0,
.local = HEADLAND_HT18_A,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_ht18b_device = {
.name = "Headland HT18 Rev. B",
.internal_name = "headland_ht18b",
.flags = 0,
.local = HEADLAND_HT18_B,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_ht18c_device = {
.name = "Headland HT18 Rev. C",
.internal_name = "headland_ht18c",
.flags = 0,
.local = HEADLAND_HT18_C,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_ht21c_d_device = {
.name = "Headland HT21 Rev. C/D",
.internal_name = "headland_ht21cd",
.flags = 0,
.local = HEADLAND_HT21_C_D,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t headland_ht21e_device = {
.name = "Headland HT21 Rev. E",
.internal_name = "headland_ht21",
.flags = 0,
.local = HEADLAND_HT21_E,
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/headland.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,528 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5591 Host to PCI bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#include <86box/agpgart.h>
#ifdef ENABLE_SIS_5591_HOST_TO_PCI_LOG
int sis_5591_host_to_pci_do_log = ENABLE_SIS_5591_HOST_TO_PCI_LOG;
static void
sis_5591_host_to_pci_log(const char *fmt, ...)
{
va_list ap;
if (sis_5591_host_to_pci_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5591_host_to_pci_log(fmt, ...)
#endif
typedef struct {
uint8_t installed;
uint8_t code;
uint32_t phys_size;
} ram_bank_t;
typedef struct sis_5591_host_to_pci_t {
uint8_t pci_conf[256];
uint8_t states[7];
uint8_t states_bus[7];
ram_bank_t ram_banks[3];
sis_55xx_common_t *sis;
smram_t *smram;
agpgart_t *agpgart;
} sis_5591_host_to_pci_t;
static uint8_t bank_codes[6] = { 0x00, 0x20, 0x24, 0x22, 0x26, 0x2a };
static uint32_t bank_sizes[6] = { 0x00800000, /* 8 MB */
0x01000000, /* 16 MB */
0x02000000, /* 32 MB */
0x04000000, /* 64 MB */
0x08000000, /* 128 MB */
0x10000000 }; /* 256 MB */
static void
sis_5591_shadow_recalc(sis_5591_host_to_pci_t *dev)
{
uint32_t base;
uint32_t state;
uint8_t val;
for (uint8_t i = 0x70; i <= 0x76; i++) {
if (i == 0x76) {
val = dev->pci_conf[i];
if ((dev->states[i & 0x0f] ^ val) & 0xa0) {
state = (val & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_cpu_both(0xf0000, 0x10000, state);
sis_5591_host_to_pci_log("000F0000-000FFFFF\n");
dev->states[i & 0x0f] = val;
}
if (!(dev->pci_conf[0x76] & 0x08))
val &= 0x5f;
if ((dev->states_bus[i & 0x0f] ^ val) & 0xa0) {
state = (val & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_bus_both(0xf0000, 0x10000, state);
sis_5591_host_to_pci_log("000F0000-000FFFFF\n");
dev->states_bus[i & 0x0f] = val;
}
} else {
base = ((i & 0x07) << 15) + 0xc0000;
val = dev->pci_conf[i];
if ((dev->states[i & 0x0f] ^ val) & 0xa0) {
state = (val & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_cpu_both(base, 0x4000, state);
sis_5591_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
dev->states[i & 0x0f] = (dev->states[i & 0x0f] & 0x0f) | (val & 0xf0);
}
if ((dev->states[i & 0x0f] ^ val) & 0x0a) {
state = (val & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_cpu_both(base + 0x4000, 0x4000, state);
sis_5591_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
dev->states[i & 0x0f] = (dev->states[i & 0x0f] & 0xf0) | (val & 0x0f);
}
if (!(dev->pci_conf[0x76] & 0x08))
val &= 0x55;
if ((dev->states_bus[i & 0x0f] ^ val) & 0xa0) {
state = (val & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_bus_both(base, 0x4000, state);
sis_5591_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
dev->states_bus[i & 0x0f] = (dev->states_bus[i & 0x0f] & 0x0f) | (val & 0xf0);
}
if ((dev->states_bus[i & 0x0f] ^ val) & 0x0a) {
state = (val & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (val & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_bus_both(base + 0x4000, 0x4000, state);
sis_5591_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
dev->states_bus[i & 0x0f] = (dev->states_bus[i & 0x0f] & 0xf0) | (val & 0x0f);
}
}
}
flushmmucache_nopc();
}
static void
sis_5591_smram_recalc(sis_5591_host_to_pci_t *dev)
{
smram_disable_all();
switch (dev->pci_conf[0x68] >> 6) {
case 0:
smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x68] & 0x10, 1);
break;
case 1:
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x68] & 0x10, 1);
break;
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x68] & 0x10, 1);
break;
case 3:
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0x68] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
}
static void
sis_5591_mask_bar(uint8_t *regs, void *agpgart)
{
uint32_t bar;
uint32_t sizes[8] = { 0x00400000, 0x00800000, 0x01000000, 0x02000000, 0x04000000, 0x08000000,
0x10000000, 0x00000000 } ;
/* Make sure the aperture's base is aligned to its size. */
bar = (regs[0x13] << 24) | (regs[0x12] << 16);
bar &= (sizes[(regs[0x94] >> 4) & 0x07] | 0xf0000000);
regs[0x12] = (bar >> 16) & 0xff;
regs[0x13] = (bar >> 24) & 0xff;
if (!agpgart)
return;
/* Map aperture and GART. */
agpgart_set_aperture(agpgart,
bar,
sizes[(regs[0x94] >> 4) & 0x07],
!!(regs[0x94] & 0x02));
if (regs[0x94] & 0x01)
agpgart_set_gart(agpgart, (regs[0x91] << 8) | (regs[0x92] << 16) | (regs[0x93] << 24));
else
agpgart_set_gart(agpgart, 0x00000000);
}
void
sis_5591_host_to_pci_write(int addr, uint8_t val, void *priv)
{
sis_5591_host_to_pci_t *dev = (sis_5591_host_to_pci_t *) priv;
sis_5591_host_to_pci_log("SiS 5591 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x04: /* Command - Low Byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfd) | (val & 0x02);
break;
case 0x05: /* Command - High Byte */
dev->pci_conf[addr] = val & 0x03;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= ~(val & 0xf0);
break;
case 0x12:
dev->pci_conf[addr] = val & 0xc0;
sis_5591_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x13:
dev->pci_conf[addr] = val;
sis_5591_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x51:
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 0x80);
cpu_update_waitstates();
break;
case 0x60 ... 0x62:
dev->pci_conf[addr] = dev->ram_banks[addr & 0x0f].code | 0xc0;
break;
case 0x63:
dev->pci_conf[addr] = dev->ram_banks[0].installed |
(dev->ram_banks[1].installed << 1) |
(dev->ram_banks[2].installed << 2);
break;
case 0x68:
dev->pci_conf[addr] = val;
sis_5591_smram_recalc(dev);
break;
case 0x70 ... 0x75:
dev->pci_conf[addr] = val & 0xee;
sis_5591_shadow_recalc(dev);
break;
case 0x76:
dev->pci_conf[addr] = val & 0xe8;
sis_5591_shadow_recalc(dev);
break;
case 0x0d: /* Master latency timer */
case 0x50:
case 0x52:
case 0x54 ... 0x5a:
case 0x5c ... 0x5f:
case 0x64 ... 0x65:
case 0x69 ... 0x6c:
case 0x77 ... 0x7b:
case 0x80 ... 0x8d:
case 0x90:
case 0x97 ... 0xab:
case 0xb0:
case 0xc8 ... 0xcb:
case 0xd4 ... 0xda:
case 0xe0 ... 0xe3:
case 0xef:
dev->pci_conf[addr] = val;
break;
case 0x91 ... 0x93:
dev->pci_conf[addr] = val;
sis_5591_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x94:
dev->pci_conf[addr] = val & 0x7f;
sis_5591_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0xb2:
dev->pci_conf[addr] &= ~(val & 0x01);
break;
}
}
uint8_t
sis_5591_host_to_pci_read(int addr, void *priv)
{
const sis_5591_host_to_pci_t *dev = (sis_5591_host_to_pci_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5591_host_to_pci_log("SiS 5591 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5591_host_to_pci_reset(void *priv)
{
sis_5591_host_to_pci_t *dev = (sis_5591_host_to_pci_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x91;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = 0x05;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x02;
dev->pci_conf[0x09] = dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0xff;
dev->pci_conf[0x0e] = 0x80;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x10] = dev->pci_conf[0x11] = 0x00;
dev->pci_conf[0x12] = dev->pci_conf[0x13] = 0x00;
dev->pci_conf[0x34] = 0xc0;
dev->pci_conf[0x50] = 0x00;
dev->pci_conf[0x51] = 0x18;
dev->pci_conf[0x52] = dev->pci_conf[0x54] = 0x00;
dev->pci_conf[0x55] = 0x0e;
dev->pci_conf[0x56] = 0x40;
dev->pci_conf[0x57] = 0x00;
dev->pci_conf[0x58] = 0x50;
dev->pci_conf[0x59] = dev->pci_conf[0x5a] = 0x00;
dev->pci_conf[0x5c] = dev->pci_conf[0x5d] = 0x00;
dev->pci_conf[0x5e] = dev->pci_conf[0x5f] = 0x00;
dev->pci_conf[0x60] = dev->pci_conf[0x61] = 0x00;
dev->pci_conf[0x62] = 0x00;
dev->pci_conf[0x63] = 0xff;
dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6a] = dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = 0x00;
dev->pci_conf[0x70] = dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x76] = dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x78] = dev->pci_conf[0x79] = 0x00;
dev->pci_conf[0x7a] = dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x82] = dev->pci_conf[0x83] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x85] = 0xff;
dev->pci_conf[0x86] = 0xff;
dev->pci_conf[0x87] = 0x00;
dev->pci_conf[0x88] = dev->pci_conf[0x89] = 0x00;
dev->pci_conf[0x8a] = dev->pci_conf[0x8b] = 0x00;
dev->pci_conf[0x8c] = dev->pci_conf[0x8d] = 0x00;
dev->pci_conf[0x90] = dev->pci_conf[0x91] = 0x00;
dev->pci_conf[0x92] = dev->pci_conf[0x93] = 0x00;
dev->pci_conf[0x94] = dev->pci_conf[0x97] = 0x00;
dev->pci_conf[0x98] = dev->pci_conf[0x99] = 0x00;
dev->pci_conf[0x9a] = dev->pci_conf[0x9b] = 0x00;
dev->pci_conf[0x9c] = dev->pci_conf[0x9d] = 0x00;
dev->pci_conf[0x9e] = dev->pci_conf[0x9f] = 0x00;
dev->pci_conf[0xa0] = dev->pci_conf[0xa1] = 0x00;
dev->pci_conf[0xa2] = dev->pci_conf[0xa3] = 0x00;
dev->pci_conf[0xa4] = dev->pci_conf[0xa5] = 0x00;
dev->pci_conf[0xa6] = dev->pci_conf[0xa7] = 0x00;
dev->pci_conf[0xa8] = dev->pci_conf[0xa9] = 0x00;
dev->pci_conf[0xaa] = dev->pci_conf[0xab] = 0x00;
dev->pci_conf[0xb0] = dev->pci_conf[0xb2] = 0x00;
dev->pci_conf[0xc0] = 0x02;
dev->pci_conf[0xc1] = 0x00;
dev->pci_conf[0xc2] = 0x10;
dev->pci_conf[0xc3] = 0x00;
dev->pci_conf[0xc4] = 0x03;
dev->pci_conf[0xc5] = 0x02;
dev->pci_conf[0xc6] = 0x00;
dev->pci_conf[0xc7] = 0x1f;
dev->pci_conf[0xc8] = dev->pci_conf[0xc9] = 0x00;
dev->pci_conf[0xca] = dev->pci_conf[0xcb] = 0x00;
dev->pci_conf[0xd4] = dev->pci_conf[0xd5] = 0x00;
dev->pci_conf[0xd6] = dev->pci_conf[0xd7] = 0x00;
dev->pci_conf[0xd8] = dev->pci_conf[0xd9] = 0x00;
dev->pci_conf[0xda] = 0x00;
dev->pci_conf[0xe0] = dev->pci_conf[0xe1] = 0x00;
dev->pci_conf[0xe2] = dev->pci_conf[0xe3] = 0x00;
dev->pci_conf[0xef] = 0x00;
sis_5591_mask_bar(dev->pci_conf, dev->agpgart);
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
sis_5591_shadow_recalc(dev);
sis_5591_smram_recalc(dev);
}
static void
sis_5591_host_to_pci_close(void *priv)
{
sis_5591_host_to_pci_t *dev = (sis_5591_host_to_pci_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5591_host_to_pci_init(UNUSED(const device_t *info))
{
sis_5591_host_to_pci_t *dev = (sis_5591_host_to_pci_t *) calloc(1, sizeof(sis_5591_host_to_pci_t));
uint32_t total_mem = mem_size << 10;
ram_bank_t *rb;
dev->sis = device_get_common_priv();
/* Calculate the physical RAM banks. */
for (uint8_t i = 0; i < 3; i++) {
rb = &(dev->ram_banks[i]);
uint32_t size = 0x00000000;
uint8_t index = 0;
for (int8_t j = 5; j >= 0; j--) {
uint32_t *bs = &(bank_sizes[j]);
if (*bs <= total_mem) {
size = *bs;
index = j;
break;
}
}
if (size != 0x00000000) {
rb->installed = 1;
rb->code = bank_codes[index];
rb->phys_size = size;
total_mem -= size;
} else
rb->installed = 0;
}
/* SMRAM */
dev->smram = smram_add();
device_add(&sis_5xxx_agp_device);
dev->agpgart = device_add(&agpgart_device);
sis_5591_host_to_pci_reset(dev);
return dev;
}
const device_t sis_5591_h2p_device = {
.name = "SiS 5591 Host to PCI bridge",
.internal_name = "sis_5591_host_to_pci",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5591_host_to_pci_init,
.close = sis_5591_host_to_pci_close,
.reset = sis_5591_host_to_pci_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5591_h2p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,785 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the G2 GC100/GC100A chipset.
*
* NOTE: As documentation is currently available only for the
* GC100 chipset, the GC100A chipset has been reverese-engineered.
* Thus, its behavior may not be fully accurate.
*
*
*
* Authors: EngiNerd, <webmaster.crrc@yahoo.it>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/nmi.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/gameport.h>
#include <86box/ibm_5161.h>
#include <86box/keyboard.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/io.h>
#include <86box/video.h>
typedef struct gc100_t {
uint8_t reg[0x10];
} gc100_t;
#ifdef ENABLE_GC100_LOG
int gc100_do_log = ENABLE_GC100_LOG;
static void
gc100_log(const char *fmt, ...)
{
va_list ap;
if (gc100_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define gc100_log(fmt, ...)
#endif
static uint8_t
get_fdd_switch_settings(void)
{
uint8_t fdd_count = 0;
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
}
if (!fdd_count)
return 0x00;
else
return ((fdd_count - 1) << 6) | 0x01;
}
static uint8_t
get_videomode_switch_settings(void)
{
if (video_is_mda())
return 0x30;
else if (video_is_cga())
return 0x20; /* 0x10 would be 40x25 */
else
return 0x00;
}
static void
gc100_write(uint16_t port, uint8_t val, void *priv)
{
gc100_t *dev = (gc100_t *) priv;
uint16_t addr = port & 0xf;
dev->reg[addr] = val;
switch (addr) {
/* addr 0x2
* bits 5-7: not used
* bit 4: intenal memory wait states
* bits 2-3: external memory wait states
* bits 0-1: i/o access wait states
*/
case 2:
break;
/* addr 0x3
* bits 1-7: not used
* bit 0: turbo 0 xt 1
*/
case 3:
if (val & 1)
cpu_dynamic_switch(0);
else
cpu_dynamic_switch(cpu);
break;
/* addr 0x5
* programmable dip-switches
* bits 6-7: floppy drive number
* bits 4-5: video mode
* bits 2-3: memory size
* bit 1: fpu
* bit 0: not used
*/
/* addr 0x6 */
/* addr 0x7 */
default:
break;
}
gc100_log("GC100: Write %02x at %02x\n", val, port);
}
static uint8_t
gc100_read(uint16_t port, void *priv)
{
const gc100_t *dev = (gc100_t *) priv;
uint8_t ret = 0xff;
uint16_t addr = port & 0xf;
ret = dev->reg[addr];
gc100_log("GC100: Read %02x at %02x\n", ret, port);
switch (addr) {
/* addr 0x2
* bits 5-7: not used
* bit 4: intenal memory wait states
* bits 2-3: external memory wait states
* bits 0-1: i/o access wait states
*/
case 0x2:
break;
/* addr 0x3
* bits 1-7: not used
* bit 0: turbo 0 xt 1
*/
case 0x3:
break;
/* addr 0x5
* programmable dip-switches
* bits 6-7: floppy drive number
* bits 4-5: video mode
* bits 2-3: memory size
* bit 1: fpu
* bit 0: not used
*/
case 0x5:
ret = ret & 0x0c;
ret |= get_fdd_switch_settings();
ret |= get_videomode_switch_settings();
if (hasfpu)
ret |= 0x02;
break;
/* addr 0x6 */
/* addr 0x7 */
default:
break;
}
return ret;
}
static void
gc100_close(void *priv)
{
gc100_t *dev = (gc100_t *) priv;
free(dev);
}
static void *
gc100_init(const device_t *info)
{
gc100_t *dev = (gc100_t *) malloc(sizeof(gc100_t));
memset(dev, 0, sizeof(gc100_t));
dev->reg[0x2] = 0xff;
dev->reg[0x3] = 0x0;
dev->reg[0x5] = 0x0;
dev->reg[0x6] = 0x0;
dev->reg[0x7] = 0x0;
if (info->local) {
/* GC100A */
io_sethandler(0x0c2, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
io_sethandler(0x0c5, 0x03, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
} else {
/* GC100 */
io_sethandler(0x022, 0x02, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
io_sethandler(0x025, 0x01, gc100_read, NULL, NULL, gc100_write, NULL, NULL, dev);
}
return dev;
}
const device_t gc100_device = {
.name = "G2 GC100",
.internal_name = "gc100",
.flags = 0,
.local = 0,
.init = gc100_init,
.close = gc100_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t gc100a_device = {
.name = "G2 GC100A",
.internal_name = "gc100a",
.flags = 0,
.local = 1,
.init = gc100_init,
.close = gc100_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/gc100.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,800 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the SiS 85c401/85c402, 85c460, 85c461, and
* 85c407/85c471 chipsets.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pic.h>
#include <86box/machine.h>
#include <86box/chipset.h>
typedef struct sis_85c4xx_t {
uint8_t cur_reg;
uint8_t tries;
uint8_t reg_base;
uint8_t reg_last;
uint8_t reg_00;
uint8_t is_471;
uint8_t force_flush;
uint8_t shadowed;
uint8_t smram_enabled;
uint8_t pad;
uint8_t regs[39];
uint8_t scratch[2];
uint32_t mem_state[8];
smram_t *smram;
port_92_t *port_92;
} sis_85c4xx_t;
static void
sis_85c4xx_recalcremap(sis_85c4xx_t *dev)
{
if (dev->is_471) {
if ((mem_size > 8192) || (dev->shadowed & 0x3c) || (dev->regs[0x0b] & 0x02))
mem_remap_top(0);
else
mem_remap_top(-256);
}
}
static void
sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
{
uint32_t base;
uint32_t n = 0;
uint32_t shflags = 0;
uint32_t readext;
uint32_t writeext;
uint8_t romcs = 0xc0;
uint8_t cur_romcs;
dev->shadowed = 0x00;
shadowbios = 0;
shadowbios_write = 0;
if (dev->regs[0x03] & 0x40)
romcs |= 0x01;
if (dev->regs[0x03] & 0x80)
romcs |= 0x30;
if (dev->regs[0x08] & 0x04)
romcs |= 0x02;
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
cur_romcs = romcs & (1 << i);
readext = cur_romcs ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
writeext = cur_romcs ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
if ((i > 5) || (dev->regs[0x02] & (1 << i))) {
shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80);
shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : readext;
shflags |= (dev->regs[0x02] & 0x40) ? writeext : MEM_WRITE_INTERNAL;
if (dev->regs[0x02] & 0x80)
dev->shadowed |= (1 << i);
if (!(dev->regs[0x02] & 0x40))
dev->shadowed |= (1 << i);
if (dev->force_flush || (dev->mem_state[i] != shflags)) {
n++;
mem_set_mem_state_both(base, 0x8000, shflags);
if ((base >= 0xf0000) && (dev->mem_state[i] & MEM_READ_INTERNAL) && !(shflags & MEM_READ_INTERNAL))
mem_invalidate_range(base, base + 0x7fff);
dev->mem_state[i] = shflags;
}
} else {
shflags = readext | writeext;
if (dev->force_flush || (dev->mem_state[i] != shflags)) {
n++;
mem_set_mem_state_both(base, 0x8000, shflags);
dev->mem_state[i] = shflags;
}
}
}
if (dev->force_flush) {
flushmmucache();
dev->force_flush = 0;
} else if (n > 0)
flushmmucache_nopc();
sis_85c4xx_recalcremap(dev);
}
static void
sis_85c4xx_sw_smi_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
if (dev->regs[0x18] & 0x02) {
if (dev->regs[0x0b] & 0x10)
smi_raise();
else
picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12));
soft_reset_mask = 1;
dev->regs[0x19] |= 0x02;
}
}
static void
sis_85c4xx_sw_smi_handler(sis_85c4xx_t *dev)
{
uint16_t addr;
if (!dev->is_471)
return;
addr = dev->regs[0x14] | (dev->regs[0x15] << 8);
io_handler((dev->regs[0x0b] & 0x80) && (dev->regs[0x18] & 0x02), addr, 0x0001,
NULL, NULL, NULL, sis_85c4xx_sw_smi_out, NULL, NULL, dev);
}
static void
sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
uint8_t rel_reg = dev->cur_reg - dev->reg_base;
uint8_t valxor = 0x00;
uint32_t host_base = 0x000e0000;
uint32_t ram_base = 0x000a0000;
switch (port) {
case 0x22:
dev->cur_reg = val;
break;
case 0x23:
if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) {
valxor = val ^ dev->regs[rel_reg];
if (rel_reg == 0x00)
dev->regs[rel_reg] = (dev->regs[rel_reg] & 0x1f) | (val & 0xe0);
else
dev->regs[rel_reg] = val;
switch (rel_reg) {
case 0x01:
cpu_cache_ext_enabled = ((val & 0x84) == 0x84);
cpu_update_waitstates();
break;
case 0x02:
case 0x03:
case 0x08:
if (valxor)
sis_85c4xx_recalcmapping(dev);
break;
case 0x0b:
sis_85c4xx_sw_smi_handler(dev);
if (valxor & 0x02)
sis_85c4xx_recalcremap(dev);
break;
case 0x13:
if (dev->is_471 && (valxor & 0xf0)) {
smram_disable(dev->smram);
host_base = (val & 0x80) ? 0x00060000 : 0x000e0000;
switch ((val >> 5) & 0x03) {
case 0x00:
ram_base = 0x000a0000;
break;
case 0x01:
ram_base = 0x000b0000;
break;
case 0x02:
ram_base = (val & 0x80) ? 0x00000000 : 0x000e0000;
break;
default:
ram_base = 0x00000000;
break;
}
dev->smram_enabled = (ram_base != 0x00000000);
if (ram_base != 0x00000000)
smram_enable(dev->smram, host_base, ram_base, 0x00010000, (val & 0x10), 1);
sis_85c4xx_recalcremap(dev);
}
break;
case 0x14:
case 0x15:
case 0x18:
sis_85c4xx_sw_smi_handler(dev);
break;
case 0x1c:
if (dev->is_471)
soft_reset_mask = 0;
break;
case 0x22:
if (dev->is_471 && (valxor & 0x01)) {
port_92_remove(dev->port_92);
if (val & 0x01)
port_92_add(dev->port_92);
}
break;
default:
break;
}
} else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
dev->reg_00 = val;
dev->cur_reg = 0x00;
break;
case 0xe1:
case 0xe2:
dev->scratch[port - 0xe1] = val;
return;
default:
break;
}
}
static uint8_t
sis_85c4xx_in(uint16_t port, void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
uint8_t rel_reg = dev->cur_reg - dev->reg_base;
uint8_t ret = 0xff;
switch (port) {
case 0x23:
if (dev->is_471 && (dev->cur_reg == 0x1c))
ret = inb(0x70);
/* On the SiS 40x, the shadow RAM read and write enable bits are write-only! */
if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x62))
ret = dev->regs[rel_reg] & 0x3f;
else if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last))
ret = dev->regs[rel_reg];
else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
ret = dev->reg_00;
if (dev->reg_base != 0x60)
dev->cur_reg = 0x00;
break;
case 0xe1:
case 0xe2:
ret = dev->scratch[port - 0xe1];
break;
default:
break;
}
return ret;
}
static void
sis_85c4xx_reset(void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
int mem_size_mb = mem_size >> 10;
static uint8_t ram_4xx[64] = { 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x00, 0x0b, 0x00, 0x00, 0x00,
0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09, 0x04, 0x04, 0x05, 0x05, 0x0b, 0x0b, 0x0b, 0x0b,
0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e,
0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e };
memset(dev->regs, 0x00, sizeof(dev->regs));
if (cpu_s->rspeed < 25000000)
dev->regs[0x08] = 0x80;
if (dev->is_471) {
dev->regs[0x09] = 0x40;
if (mem_size_mb >= 64) {
if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[0x09] |= 0x22;
else
dev->regs[0x09] |= 0x24;
} else
dev->regs[0x09] |= ram_471[mem_size_mb];
dev->regs[0x11] = 0x09;
dev->regs[0x12] = 0xff;
dev->regs[0x1f] = 0x20; /* Video access enabled. */
dev->regs[0x23] = 0xf0;
dev->regs[0x26] = 0x01;
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x00010000, 0, 1);
port_92_remove(dev->port_92);
soft_reset_mask = 0;
} else {
/* Bits 6 and 7 must be clear on the SiS 40x. */
if (dev->reg_base == 0x60)
dev->reg_00 = 0x24;
if (mem_size_mb == 64)
dev->regs[0x00] = 0x1f;
else if (mem_size_mb < 64)
dev->regs[0x00] = ram_4xx[mem_size_mb];
dev->regs[0x11] = 0x01;
}
dev->scratch[0] = dev->scratch[1] = 0xff;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
dev->force_flush = 1;
sis_85c4xx_recalcmapping(dev);
}
static void
sis_85c4xx_close(void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
if (dev->is_471)
smram_del(dev->smram);
free(dev);
}
static void *
sis_85c4xx_init(const device_t *info)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) malloc(sizeof(sis_85c4xx_t));
memset(dev, 0, sizeof(sis_85c4xx_t));
dev->is_471 = (info->local >> 8) & 0xff;
dev->reg_base = info->local & 0xff;
if (dev->is_471) {
dev->reg_last = dev->reg_base + 0x76;
dev->smram = smram_add();
dev->port_92 = device_add(&port_92_device);
} else
dev->reg_last = dev->reg_base + 0x11;
io_sethandler(0x0022, 0x0002,
sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
io_sethandler(0x00e1, 0x0002,
sis_85c4xx_in, NULL, NULL, sis_85c4xx_out, NULL, NULL, dev);
sis_85c4xx_reset(dev);
return dev;
}
const device_t sis_85c401_device = {
.name = "SiS 85c401/85c402",
.internal_name = "sis_85c401",
.flags = 0,
.local = 0x060,
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_85c460_device = {
.name = "SiS 85c460",
.internal_name = "sis_85c460",
.flags = 0,
.local = 0x050,
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* TODO: Log to make sure the registers are correct. */
const device_t sis_85c461_device = {
.name = "SiS 85c461",
.internal_name = "sis_85c461",
.flags = 0,
.local = 0x050,
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_85c471_device = {
.name = "SiS 85c407/85c471",
.internal_name = "sis_85c471",
.flags = 0,
.local = 0x150,
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_85c4xx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,781 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS (5)600 Host to PCI bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#include <86box/agpgart.h>
#ifdef ENABLE_SIS_5600_HOST_TO_PCI_LOG
int sis_5600_host_to_pci_do_log = ENABLE_SIS_5600_HOST_TO_PCI_LOG;
static void
sis_5600_host_to_pci_log(const char *fmt, ...)
{
va_list ap;
if (sis_5600_host_to_pci_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5600_host_to_pci_log(fmt, ...)
#endif
typedef struct {
uint8_t installed;
uint8_t code;
uint32_t phys_size;
} ram_bank_t;
typedef struct sis_5600_host_to_pci_t {
uint8_t pci_conf[256];
uint8_t states[7];
ram_bank_t ram_banks[3];
sis_55xx_common_t *sis;
smram_t *smram;
agpgart_t *agpgart;
} sis_5600_host_to_pci_t;
static uint8_t bank_codes[7] = { 0x00, 0x20, 0x24, 0x22, 0x26, 0x2a, 0x2b };
static uint32_t bank_sizes[7] = { 0x00800000, /* 8 MB */
0x01000000, /* 16 MB */
0x02000000, /* 32 MB */
0x04000000, /* 64 MB */
0x08000000, /* 128 MB */
0x10000000, /* 256 MB */
0x20000000 }; /* 512 MB */
static void
sis_5600_shadow_recalc(sis_5600_host_to_pci_t *dev)
{
int state;
uint32_t base;
for (uint8_t i = 0; i < 8; i++) {
base = 0x000c0000 + (i << 14);
state = (dev->pci_conf[0x70] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[0x72] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
if (((dev->pci_conf[0x70] ^ dev->states[0]) & (1 << i)) ||
((dev->pci_conf[0x72] ^ dev->states[2]) & (1 << i))) {
mem_set_mem_state_both(base, 0x4000, state);
sis_5600_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
}
}
for (uint8_t i = 0; i < 4; i++) {
base = 0x000e0000 + (i << 14);
state = (dev->pci_conf[0x71] & (1 << i)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[0x73] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
if (((dev->pci_conf[0x71] ^ dev->states[1]) & (1 << i)) ||
((dev->pci_conf[0x73] ^ dev->states[3]) & (1 << i))) {
mem_set_mem_state_both(base, 0x4000, state);
sis_5600_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
}
}
base = 0x000f0000;
state = (dev->pci_conf[0x71] & (1 << 4)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[0x73] & (1 << 4)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
if (((dev->pci_conf[0x71] ^ dev->states[1]) & (1 << 4)) ||
((dev->pci_conf[0x73] ^ dev->states[3]) & (1 << 4))) {
mem_set_mem_state_both(base, 0x10000, state);
sis_5600_host_to_pci_log("%08X-%08X\n", base, base + 0xffff);
}
for (uint8_t i = 0; i < 4; i++)
dev->states[i] = dev->pci_conf[0x70 + i];
flushmmucache_nopc();
}
static void
sis_5600_smram_recalc(sis_5600_host_to_pci_t *dev)
{
smram_disable_all();
switch (dev->pci_conf[0x6a] >> 6) {
case 0:
smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x6a] & 0x10, 1);
break;
case 1:
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0x6a] & 0x10, 1);
break;
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x6a] & 0x10, 1);
break;
case 3:
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0x6a] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
}
static void
sis_5600_mask_bar(uint8_t *regs, void *agpgart)
{
uint32_t bar;
uint32_t sizes[8] = { 0x00400000, 0x00800000, 0x01000000, 0x02000000, 0x04000000, 0x08000000,
0x10000000, 0x00000000 } ;
/* Make sure the aperture's base is aligned to its size. */
bar = (regs[0x13] << 24) | (regs[0x12] << 16);
bar &= (sizes[(regs[0x94] >> 4) & 0x07] | 0xf0000000);
regs[0x12] = (bar >> 16) & 0xff;
regs[0x13] = (bar >> 24) & 0xff;
if (!agpgart)
return;
/* Map aperture and GART. */
agpgart_set_aperture(agpgart,
bar,
sizes[(regs[0x94] >> 4) & 0x07],
!!(regs[0x94] & 0x02));
if (regs[0x94] & 0x01)
agpgart_set_gart(agpgart, (regs[0x91] << 8) | (regs[0x92] << 16) | (regs[0x93] << 24));
else
agpgart_set_gart(agpgart, 0x00000000);
}
void
sis_5600_host_to_pci_write(int addr, uint8_t val, void *priv)
{
sis_5600_host_to_pci_t *dev = (sis_5600_host_to_pci_t *) priv;
sis_5600_host_to_pci_log("SiS 5600 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x04: /* Command - Low Byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfd) | (val & 0x02);
break;
case 0x05: /* Command - High Byte */
dev->pci_conf[addr] = val & 0x03;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & ~(val & 0x70)) | (val & 0x01);
break;
case 0x0d: /* Master latency timer */
case 0x50 ... 0x5a:
case 0x64 ... 0x69:
case 0x6b ... 0x6c:
case 0x74 ... 0x75:
case 0x77 ... 0x80:
case 0x82 ... 0x8f:
case 0x97 ... 0x9b:
case 0xc8 ... 0xcb:
case 0xd4 ... 0xd8:
case 0xda:
case 0xe0:
case 0xe2 ... 0xe3:
dev->pci_conf[addr] = val;
break;
case 0x12:
dev->pci_conf[addr] = val & 0xc0;
sis_5600_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x13:
dev->pci_conf[addr] = val;
sis_5600_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x60 ... 0x62:
dev->pci_conf[addr] = dev->ram_banks[addr & 0x0f].code | 0xc0;
break;
case 0x63:
dev->pci_conf[addr] = dev->ram_banks[0].installed |
(dev->ram_banks[1].installed << 1) |
(dev->ram_banks[2].installed << 2);
break;
case 0x6a:
dev->pci_conf[addr] = val;
sis_5600_smram_recalc(dev);
break;
case 0x70 ... 0x73:
dev->pci_conf[addr] = val;
sis_5600_shadow_recalc(dev);
break;
case 0x91 ... 0x93:
dev->pci_conf[addr] = val;
sis_5600_mask_bar(dev->pci_conf, dev->agpgart);
break;
case 0x94:
dev->pci_conf[addr] = val & 0x7f;
sis_5600_mask_bar(dev->pci_conf, dev->agpgart);
break;
}
}
uint8_t
sis_5600_host_to_pci_read(int addr, void *priv)
{
const sis_5600_host_to_pci_t *dev = (sis_5600_host_to_pci_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5600_host_to_pci_log("SiS 5600 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5600_host_to_pci_reset(void *priv)
{
sis_5600_host_to_pci_t *dev = (sis_5600_host_to_pci_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x00;
dev->pci_conf[0x03] = 0x56;
dev->pci_conf[0x04] = 0x05;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x10;
dev->pci_conf[0x09] = dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0xff;
dev->pci_conf[0x0e] = 0x80;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x10] = dev->pci_conf[0x11] = 0x00;
dev->pci_conf[0x12] = dev->pci_conf[0x13] = 0x00;
dev->pci_conf[0x34] = 0xc0;
dev->pci_conf[0x50] = dev->pci_conf[0x51] = 0x02;
dev->pci_conf[0x52] = dev->pci_conf[0x53] = 0x00;
dev->pci_conf[0x54] = dev->pci_conf[0x55] = 0x00;
dev->pci_conf[0x56] = dev->pci_conf[0x57] = 0x00;
dev->pci_conf[0x58] = dev->pci_conf[0x59] = 0x00;
dev->pci_conf[0x5a] = 0x00;
dev->pci_conf[0x60] = dev->pci_conf[0x61] = 0x00;
dev->pci_conf[0x62] = 0x00;
dev->pci_conf[0x63] = 0xff;
dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x66] = dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6a] = dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = 0x00;
dev->pci_conf[0x70] = dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x78] = dev->pci_conf[0x79] = 0x00;
dev->pci_conf[0x7a] = dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x7c] = dev->pci_conf[0x7d] = 0x00;
dev->pci_conf[0x7e] = dev->pci_conf[0x7f] = 0x00;
dev->pci_conf[0x80] = 0x00;
dev->pci_conf[0x82] = dev->pci_conf[0x83] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x85] = 0xff;
dev->pci_conf[0x86] = 0xff;
dev->pci_conf[0x87] = 0x00;
dev->pci_conf[0x88] = dev->pci_conf[0x89] = 0x00;
dev->pci_conf[0x8a] = dev->pci_conf[0x8b] = 0x00;
dev->pci_conf[0x8c] = 0x00;
dev->pci_conf[0x8d] = 0x62;
dev->pci_conf[0x8e] = dev->pci_conf[0x8f] = 0x00;
dev->pci_conf[0x90] = dev->pci_conf[0x91] = 0x00;
dev->pci_conf[0x92] = dev->pci_conf[0x93] = 0x00;
dev->pci_conf[0x94] = dev->pci_conf[0x97] = 0x00;
dev->pci_conf[0x98] = dev->pci_conf[0x99] = 0x00;
dev->pci_conf[0x9a] = dev->pci_conf[0x9b] = 0x00;
dev->pci_conf[0xc0] = 0x02;
dev->pci_conf[0xc1] = 0x00;
dev->pci_conf[0xc2] = 0x10;
dev->pci_conf[0xc3] = 0x00;
dev->pci_conf[0xc4] = 0x03;
dev->pci_conf[0xc5] = 0x02;
dev->pci_conf[0xc6] = 0x00;
dev->pci_conf[0xc7] = 0x1f;
dev->pci_conf[0xc8] = dev->pci_conf[0xc9] = 0x00;
dev->pci_conf[0xca] = dev->pci_conf[0xcb] = 0x00;
dev->pci_conf[0xd4] = dev->pci_conf[0xd5] = 0x00;
dev->pci_conf[0xd6] = dev->pci_conf[0xd7] = 0x00;
dev->pci_conf[0xd8] = dev->pci_conf[0xda] = 0x00;
dev->pci_conf[0xe0] = 0x00;
dev->pci_conf[0xe2] = dev->pci_conf[0xe3] = 0x00;
sis_5600_mask_bar(dev->pci_conf, dev->agpgart);
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
sis_5600_shadow_recalc(dev);
sis_5600_smram_recalc(dev);
}
static void
sis_5600_host_to_pci_close(void *priv)
{
sis_5600_host_to_pci_t *dev = (sis_5600_host_to_pci_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5600_host_to_pci_init(UNUSED(const device_t *info))
{
sis_5600_host_to_pci_t *dev = (sis_5600_host_to_pci_t *) calloc(1, sizeof(sis_5600_host_to_pci_t));
uint32_t total_mem = mem_size << 10;
ram_bank_t *rb;
dev->sis = device_get_common_priv();
/* Calculate the physical RAM banks. */
for (uint8_t i = 0; i < 3; i++) {
rb = &(dev->ram_banks[i]);
uint32_t size = 0x00000000;
uint8_t index = 0;
for (int8_t j = 6; j >= 0; j--) {
uint32_t *bs = &(bank_sizes[j]);
if (*bs <= total_mem) {
size = *bs;
index = j;
break;
}
}
if (size != 0x00000000) {
rb->installed = 1;
rb->code = bank_codes[index];
rb->phys_size = size;
total_mem -= size;
} else
rb->installed = 0;
}
/* SMRAM */
dev->smram = smram_add();
device_add(&sis_5xxx_agp_device);
dev->agpgart = device_add(&agpgart_device);
sis_5600_host_to_pci_reset(dev);
return dev;
}
const device_t sis_5600_h2p_device = {
.name = "SiS (5)600 Host to PCI bridge",
.internal_name = "sis_5600_host_to_pci",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5600_host_to_pci_init,
.close = sis_5600_host_to_pci_close,
.reset = sis_5600_host_to_pci_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5600_h2p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,002 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VIA Apollo series of chips.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
* Tiseno100,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#include <86box/agpgart.h>
#define VIA_585 0x05851000
#define VIA_595 0x05950000
#define VIA_597 0x05970100
#define VIA_598 0x05980000
#define VIA_691 0x06910600
#define VIA_693A 0x06914400
#define VIA_694 0x0691c200
#define VIA_8601 0x86010500
typedef struct via_apollo_t {
uint8_t drb_unit;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf[256];
uint32_t id;
smram_t *smram;
agpgart_t *agpgart;
} via_apollo_t;
static void
apollo_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3) {
case 0:
mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state_both(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 2:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 3:
mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
}
static void
apollo_smram_map(via_apollo_t *dev, int smm, uint32_t host_base, uint32_t size, int is_smram)
{
if (((is_smram & 0x03) == 0x01) || ((is_smram & 0x03) == 0x02))
smram_enable(dev->smram, host_base, 0x000a0000, size, 0, 1);
mem_set_mem_state_smram_ex(smm, host_base, size, is_smram & 0x03);
flushmmucache();
}
static void
apollo_agp_map(via_apollo_t *dev)
{
/* Make sure the aperture's base is aligned to its size. */
dev->pci_conf[0x12] &= dev->pci_conf[0x84] << 4;
dev->pci_conf[0x13] &= 0xf0 | (dev->pci_conf[0x84] >> 4);
if (!dev->agpgart)
return;
/* Map aperture and GART. */
agpgart_set_aperture(dev->agpgart,
(dev->pci_conf[0x12] << 16) | (dev->pci_conf[0x13] << 24),
((uint32_t) (uint8_t) ~dev->pci_conf[0x84] + 1) << 20,
!!(dev->pci_conf[0x88] & 0x02));
agpgart_set_gart(dev->agpgart, (dev->pci_conf[0x89] << 8) | (dev->pci_conf[0x8a] << 16) | (dev->pci_conf[0x8b] << 24));
}
static void
via_apollo_setup(via_apollo_t *dev)
{
/* Host Bridge */
dev->pci_conf[0x00] = 0x06; /*VIA*/
dev->pci_conf[0x01] = 0x11;
dev->pci_conf[0x02] = dev->id >> 16;
dev->pci_conf[0x03] = dev->id >> 24;
dev->pci_conf[0x04] = 6;
dev->pci_conf[0x05] = 0;
if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x06] = 0xa0;
else
dev->pci_conf[0x06] = 0x90;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = dev->id >> 8;
dev->pci_conf[0x09] = 0;
dev->pci_conf[0x0a] = 0;
dev->pci_conf[0x0b] = 6;
dev->pci_conf[0x0c] = 0;
dev->pci_conf[0x0d] = 0;
dev->pci_conf[0x0e] = 0;
dev->pci_conf[0x0f] = 0;
if (dev->id >= VIA_597) {
dev->pci_conf[0x10] = 0x08;
dev->pci_conf[0x34] = 0xa0;
}
if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x52] = 0x02;
else if (dev->id >= VIA_694)
dev->pci_conf[0x52] = (dev->id == VIA_694) ? 0x90 : 0x10;
if (dev->id >= VIA_693A)
dev->pci_conf[0x53] = 0x10;
if (dev->id == VIA_691) {
dev->pci_conf[0x56] = 0x01;
dev->pci_conf[0x57] = 0x01;
}
if (dev->id >= VIA_694)
dev->pci_conf[0x58] = 0x40;
else if (dev->id >= VIA_585)
dev->pci_conf[0x58] = 0x05;
if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x59] = 0x02;
dev->pci_conf[0x5a] = 0x01;
dev->pci_conf[0x5b] = 0x01;
dev->pci_conf[0x5c] = 0x01;
dev->pci_conf[0x5d] = 0x01;
dev->pci_conf[0x5e] = 0x01;
dev->pci_conf[0x5f] = 0x01;
dev->pci_conf[0x64] = ((dev->id >= VIA_585) || (dev->id < VIA_597)) ? 0xab : 0xec;
if (dev->id >= VIA_597) {
dev->pci_conf[0x65] = 0xec;
dev->pci_conf[0x66] = 0xec;
}
if (dev->id >= VIA_691)
dev->pci_conf[0x67] = 0xec; /* DRAM Timing for Banks 6, 7 */
if (dev->id >= VIA_693A) {
if (cpu_busspeed < 95000000) { /* 66 MHz */
cpu_set_pci_speed(cpu_busspeed / 2);
cpu_set_agp_speed(cpu_busspeed);
dev->pci_conf[0x68] |= 0x00;
} else if (cpu_busspeed < 124000000) { /* 100 MHz */
cpu_set_pci_speed(cpu_busspeed / 3);
cpu_set_agp_speed(cpu_busspeed / 1.5);
dev->pci_conf[0x68] |= 0x01;
} else { /* 133 MHz */
cpu_set_pci_speed(cpu_busspeed / 4);
cpu_set_agp_speed(cpu_busspeed / 2);
dev->pci_conf[0x68] |= (dev->id == VIA_8601) ? 0x03 : 0x02;
}
} else if (dev->id >= VIA_598) {
if (cpu_busspeed < ((dev->id >= VIA_691) ? 100000000 : 75000000)) { /* 66 MHz */
cpu_set_pci_speed(cpu_busspeed / 2);
cpu_set_agp_speed(cpu_busspeed);
dev->pci_conf[0x68] |= 0x00;
} else if (cpu_busspeed < 100000000) { /* 75/83 MHz (not available on 691) */
cpu_set_pci_speed(cpu_busspeed / 2.5);
cpu_set_agp_speed(cpu_busspeed / 1.25);
dev->pci_conf[0x68] |= 0x03;
} else { /* 100 MHz */
cpu_set_pci_speed(cpu_busspeed / 3);
cpu_set_agp_speed(cpu_busspeed / 1.5);
dev->pci_conf[0x68] |= 0x01;
}
}
dev->pci_conf[0x6b] = 0x01;
if (dev->id >= VIA_597) {
dev->pci_conf[0xa0] = 0x02;
dev->pci_conf[0xa2] = 0x10;
dev->pci_conf[0xa4] = 0x03;
dev->pci_conf[0xa5] = 0x02;
dev->pci_conf[0xa7] = 0x07;
if (dev->id == VIA_693A) {
dev->pci_conf[0xac] = 0x08;
dev->pci_conf[0xad] = 0x02;
}
if (dev->id == VIA_694) {
dev->pci_conf[0xb0] = 0x80; /* The datasheet refers it as 8xh */
dev->pci_conf[0xb1] = 0x63;
}
}
}
static void
via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
{
via_apollo_t *dev = (via_apollo_t *) priv;
if (func)
return;
/*Read-only addresses*/
if ((addr < 4) || ((addr > 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr != 0x0f) && (addr < 0x12)) || ((addr >= 0x14) && (addr < 0x50)) || ((addr > 0x7a) && (addr < 0x7e)) || ((addr >= 0x81) && (addr < 0x84)) || ((addr >= 0x85) && (addr < 0x88)) || ((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xaa) && (addr < 0xac)) || ((addr > 0xad) && (addr < 0xf0)) || ((addr >= 0xf8) && (addr < 0xfc)))
return;
if (((addr == 0x12) || (addr == 0x13)) && (dev->id < VIA_597))
return;
if (((addr == 0x78) || (addr >= 0xad)) && (dev->id == VIA_597))
return;
if (((addr == 0x67) || ((addr >= 0xf0) && (addr < 0xfc))) && (dev->id < VIA_691))
return;
switch (addr) {
case 0x04:
dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40);
break;
case 0x05:
if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x05] = (dev->pci_conf[0x05] & ~0x03) | (val & 0x03);
else
dev->pci_conf[0x05] = val;
break;
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0xb0);
break;
case 0x0d:
if (dev->id == VIA_8601)
dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07);
else if (dev->id == VIA_694)
dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0xf8) | (val & 0xf8);
else
dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07);
dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0x30) | ((val & 0x06) << 3);
break;
case 0x0f:
if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x0f] = (dev->pci_conf[0x0f] & ~0xcf) | (val & 0x0cf);
else
dev->pci_conf[0x0f] = val;
break;
case 0x12: /* Graphics Aperture Base */
dev->pci_conf[0x12] = (val & 0xf0);
apollo_agp_map(dev);
break;
case 0x13: /* Graphics Aperture Base */
dev->pci_conf[0x13] = val;
apollo_agp_map(dev);
break;
case 0x50: /* Cache Control 1 */
if (dev->id == VIA_8601)
dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd3) | (val & 0xd3);
else if (dev->id >= VIA_693A)
dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xd1) | (val & 0xd1);
else if (dev->id == VIA_595)
dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xfb) | (val & 0xfb);
else if ((dev->id == VIA_585) || (dev->id == VIA_691))
dev->pci_conf[0x50] = val;
else
dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xf8) | (val & 0xf8);
break;
case 0x51: /* Cache Control 2 */
if (dev->id == VIA_694)
dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xdd) | (val & 0xdd);
else if (dev->id >= VIA_693A)
dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xd9) | (val & 0xd9);
else if (dev->id >= VIA_691)
dev->pci_conf[0x51] = val;
else if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0x2b) | (val & 0x2b);
else
dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xeb) | (val & 0xeb);
break;
case 0x52: /* Non_Cacheable Control */
if (dev->id == VIA_8601)
dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xdf) | (val & 0xdf);
else if (dev->id >= VIA_693A)
dev->pci_conf[0x52] = val;
else if (dev->id == VIA_691)
dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0x9f) | (val & 0x9f);
else
dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xf5) | (val & 0xf5);
break;
case 0x53: /* System Performance Control */
if (dev->id == VIA_8601)
dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xfc) | (val & 0xfc);
else if ((dev->id == VIA_691) || (dev->id == VIA_694))
dev->pci_conf[0x53] = val;
else if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_693A))
dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf8) | (val & 0xf8);
else
dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0);
break;
case 0x54:
if (dev->id == VIA_585)
dev->pci_conf[0x54] = val;
else
dev->pci_conf[0x54] = (dev->pci_conf[0x54] & ~0x07) | (val & 0x07);
break;
case 0x56:
case 0x57:
case 0x5a:
case 0x5b:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f: /* DRAM Row Ending Address */
if ((dev->id >= VIA_691) && (dev->id != VIA_8601))
spd_write_drbs(dev->pci_conf, 0x5a, 0x56, dev->drb_unit);
else if (addr >= 0x5a)
spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, dev->drb_unit);
break;
case 0x58:
if ((dev->id >= VIA_585) || (dev->id < VIA_597) || (dev->id == VIA_597) || ((dev->id >= VIA_693A) || (dev->id < VIA_8601)))
dev->pci_conf[0x58] = (dev->pci_conf[0x58] & ~0xee) | (val & 0xee);
else
dev->pci_conf[0x58] = val;
break;
case 0x59:
if (dev->id >= VIA_693A)
dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xee) | (val & 0xee);
else if (dev->id == VIA_691)
dev->pci_conf[0x59] = val;
else if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xe7) | (val & 0xe7);
else
dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xf0) | (val & 0xf0);
break;
case 0x61: /* Shadow RAM Control 1 */
apollo_map(0xc0000, 0x04000, val & 0x03);
apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4);
apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0x61] = val;
break;
case 0x62: /* Shadow RAM Control 2 */
apollo_map(0xd0000, 0x04000, val & 0x03);
apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4);
apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0x62] = val;
break;
case 0x63: /* Shadow RAM Control 3 */
shadowbios = 0;
shadowbios_write = 0;
apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4);
shadowbios = (((val & 0x30) >> 4) & 0x02);
shadowbios_write = (((val & 0x30) >> 4) & 0x01);
apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
shadowbios |= (((val & 0xc0) >> 6) & 0x02);
shadowbios_write |= (((val & 0xc0) >> 6) & 0x01);
dev->pci_conf[0x63] = val;
smram_disable_all();
if (dev->id >= VIA_691)
switch (val & 0x03) {
default:
case 0x00:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */
break;
case 0x01:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1); /* Non-SMM: Code DRAM, Data DRAM */
break;
case 0x02:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3); /* SMM: Code Invalid, Data Invalid */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 2); /* Non-SMM: Code DRAM, Data PCI */
break;
case 0x03:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3); /* Non-SMM: Code Invalid, Data Invalid */
break;
}
else if (dev->id >= VIA_597)
switch (val & 0x03) {
default:
case 0x00:
/* Disable SMI Address Redirection (default) */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
case 0x01:
/* Allow access to DRAM Axxxx-Bxxxx for both normal and SMI cycles */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1);
break;
case 0x02:
/* Reserved */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
if (dev->id == VIA_597) {
/* SMI 3xxxx-4xxxx redirect to Axxxx-Bxxxx. */
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
}
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
case 0x03:
/* Allow SMI Axxxx-Bxxxx DRAM access */
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
}
else if (dev->id == VIA_595)
switch (val & 0x03) {
case 0x00:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
case 0x01:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
break;
case 0x02:
apollo_smram_map(dev, 1, 0x00030000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
case 0x03:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 1);
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
break;
default:
break;
}
else {
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x00020000,
(dev->pci_conf[0x6d] & 0x10) && (dev->pci_conf[0x63] & 0x01),
dev->pci_conf[0x63] & 0x01);
flushmmucache();
}
break;
case 0x65:
if (dev->id == VIA_585)
dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xfd) | (val & 0xfd);
else if (dev->id == VIA_595)
dev->pci_conf[0x65] = (dev->pci_conf[0x65] & ~0xf9) | (val & 0xf9);
else
dev->pci_conf[0x65] = val;
break;
case 0x66:
if (dev->id == VIA_585)
dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0xaf) | (val & 0xaf);
else if (dev->id == VIA_595)
dev->pci_conf[0x66] = (dev->pci_conf[0x66] & ~0x8f) | (val & 0x8f);
else
dev->pci_conf[0x66] = val;
break;
case 0x68:
if (dev->id != VIA_595) {
if (dev->id == VIA_597)
dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfe) | (val & 0xfe);
else if ((dev->id == VIA_693A) || (dev->id == VIA_694))
dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xdc) | (val & 0xdc);
else
dev->pci_conf[0x68] = (dev->pci_conf[0x68] & ~0xfc) | (val & 0xfc);
}
break;
case 0x69:
if ((dev->id != VIA_585) || (dev->id != VIA_595)) {
if ((dev->id == VIA_693A) || (dev->id < VIA_8601))
dev->pci_conf[0x69] = (dev->pci_conf[0x69] & ~0xfe) | (val & 0xfe);
else
dev->pci_conf[0x69] = val;
}
break;
case 0x6b:
if ((dev->id == VIA_693A) || (dev->id < VIA_8601))
dev->pci_conf[0x6b] = val;
else if (dev->id == VIA_691)
dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xcf) | (val & 0xcf);
else if (dev->id == VIA_595)
dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc0) | (val & 0xc0);
else if (dev->id == VIA_585)
dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc4) | (val & 0xc4);
else
dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc1) | (val & 0xc1);
break;
case 0x6c:
if ((dev->id == VIA_597) || ((dev->id == VIA_693A) || (dev->id < VIA_8601)))
dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x1f) | (val & 0x1f);
else if (dev->id == VIA_598)
dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x7f) | (val & 0x7f);
else if (dev->id == VIA_585)
dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0xef) | (val & 0xef);
else
dev->pci_conf[0x6c] = val;
break;
case 0x6d:
if ((dev->id == VIA_597) || (dev->id == VIA_694))
dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x0f) | (val & 0x0f);
else if ((dev->id == VIA_598) || (dev->id == VIA_693A) || (dev->id == VIA_8601))
dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x7f) | (val & 0x7f);
else
dev->pci_conf[0x6d] = val;
if (dev->id == VIA_585) {
smram_disable_all();
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x00020000,
(dev->pci_conf[0x6d] & 0x10) && (dev->pci_conf[0x63] & 0x01),
dev->pci_conf[0x63] & 0x01);
flushmmucache();
}
break;
case 0x6e:
if ((dev->id == VIA_595) || (dev->id == VIA_694))
dev->pci_conf[0x6e] = val;
else
dev->pci_conf[0x6e] = (dev->pci_conf[0x6e] & ~0xb7) | (val & 0xb7);
break;
case 0x70:
if (dev->id >= VIA_693A)
dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xdf) | (val & 0xdf);
else if (dev->id == VIA_597)
dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xf1) | (val & 0xf1);
else if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xe3) | (val & 0xe3);
else
dev->pci_conf[0x70] = val;
break;
case 0x71:
if ((dev->id >= VIA_585) || (dev->id == VIA_694))
dev->pci_conf[0x71] = (dev->pci_conf[0x71] & ~0xdf) | (val & 0xdf);
else
dev->pci_conf[0x71] = val;
break;
case 0x73:
if (dev->id >= VIA_693A)
dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0x7f) | (val & 0x7f);
else if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x73] = (dev->pci_conf[0x73] & ~0xef) | (val & 0xef);
else
dev->pci_conf[0x73] = val;
break;
case 0x74:
if ((dev->id == VIA_693A) || (dev->id == VIA_8601))
dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xdf) | (val & 0xdf);
else if (dev->id == VIA_694)
dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0x9f) | (val & 0x9f);
else
dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xc0) | (val & 0xc0);
break;
case 0x75:
if (dev->id >= VIA_693A)
dev->pci_conf[0x75] = val;
else
dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0xcf) | (val & 0xcf);
break;
case 0x76:
if (dev->id >= VIA_693A)
dev->pci_conf[0x76] = val;
else if ((dev->id >= VIA_585) || (dev->id < VIA_597))
dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xb0) | (val & 0xb0);
else
dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xf0) | (val & 0xf0);
break;
case 0x77:
if (dev->id < VIA_693A)
dev->pci_conf[0x77] = (dev->pci_conf[0x77] & ~0xc0) | (val & 0xc0);
break;
case 0x78:
dev->pci_conf[0x78] = (dev->pci_conf[0x78] & ~0xd5) | (val & 0xd5);
break;
case 0x79:
dev->pci_conf[0x79] = (dev->pci_conf[0x79] & ~0xfc) | (val & 0xfc);
break;
case 0x7a:
dev->pci_conf[0x7a] = (dev->pci_conf[0x7a] & ~0x89) | (val & 0x89);
break;
case 0x7e:
if ((dev->id != VIA_8601) || (dev->id != VIA_694))
dev->pci_conf[0x7e] = (dev->pci_conf[0x7e] & ~0x3f) | (val & 0x3f);
break;
case 0x80:
dev->pci_conf[0x80] = (dev->pci_conf[0x80] & ~0x8f) | (val & 0x8f);
break;
case 0x84:
/* The datasheet first mentions 7-0 but then says 3-0 are reserved -
- minimum of 16 MB for the graphics aperture? 8601 datasheet doesn't refer it. */
if (dev->id >= VIA_693A)
dev->pci_conf[0x84] = val;
else
dev->pci_conf[0x84] = (dev->pci_conf[0x84] & ~0xf0) | (val & 0xf0);
apollo_agp_map(dev);
break;
case 0x88:
if ((dev->id == VIA_693A) || (dev->id == VIA_8601))
dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x06) | (val & 0x06);
else
dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x07) | (val & 0x07);
apollo_agp_map(dev);
break;
case 0x89:
dev->pci_conf[0x89] = val & 0xf0;
apollo_agp_map(dev);
break;
case 0x8a:
case 0x8b:
dev->pci_conf[addr] = val;
apollo_agp_map(dev);
break;
case 0xa8:
if (dev->id == VIA_694)
dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x33) | (val & 0x33);
else
dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x03) | (val & 0x03);
break;
case 0xa9:
dev->pci_conf[0xa9] = (dev->pci_conf[0xa9] & ~0x03) | (val & 0x03);
break;
case 0xac:
if (dev->id == VIA_8601)
dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x7f) | (val & 0x7f);
else
dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f);
break;
case 0xad:
dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f);
break;
case 0xfc:
if (dev->id == VIA_8601)
dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x03) | (val & 0x03);
else if (dev->id > VIA_597)
dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x01) | (val & 0x01);
break;
case 0xfd:
if (dev->id == VIA_8601)
dev->pci_conf[0xfd] = (dev->pci_conf[0xfd] & ~0x07) | (val & 0x07);
else
dev->pci_conf[0xfd] = val;
break;
default:
dev->pci_conf[addr] = val;
break;
}
}
static uint8_t
via_apollo_read(int func, int addr, void *priv)
{
const via_apollo_t *dev = (via_apollo_t *) priv;
uint8_t ret = 0xff;
switch (func) {
case 0:
ret = dev->pci_conf[addr];
break;
default:
break;
}
return ret;
}
static void
via_apollo_write(int func, int addr, uint8_t val, void *priv)
{
switch (func) {
case 0:
via_apollo_host_bridge_write(func, addr, val, priv);
break;
default:
break;
}
}
static void
via_apollo_reset(void *priv)
{
via_apollo_write(0, 0x61, 0x00, priv);
via_apollo_write(0, 0x62, 0x00, priv);
via_apollo_write(0, 0x63, 0x00, priv);
}
static void *
via_apollo_init(const device_t *info)
{
via_apollo_t *dev = (via_apollo_t *) malloc(sizeof(via_apollo_t));
memset(dev, 0, sizeof(via_apollo_t));
dev->smram = smram_add();
if (dev->id != VIA_8601)
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev, &dev->pci_slot);
dev->id = info->local;
switch (dev->id) {
case VIA_597:
device_add(&via_vp3_agp_device);
break;
case VIA_691:
device_add(&via_apro_agp_device);
break;
case VIA_8601:
device_add(&via_vt8601_agp_device);
break;
case VIA_598:
case VIA_693A:
case VIA_694:
device_add(&via_mvp3_agp_device);
break;
default:
break;
}
if (dev->id >= VIA_597)
dev->agpgart = device_add(&agpgart_device);
if ((dev->id >= VIA_694) && (dev->id != VIA_8601))
dev->drb_unit = 16;
else if (dev->id >= VIA_597)
dev->drb_unit = 8;
else
dev->drb_unit = 4;
via_apollo_setup(dev);
via_apollo_reset(dev);
return dev;
}
static void
via_apollo_close(void *priv)
{
via_apollo_t *dev = (via_apollo_t *) priv;
smram_del(dev->smram);
free(dev);
}
const device_t via_vpx_device = {
.name = "VIA Apollo VPX",
.internal_name = "via_vpx",
.flags = DEVICE_PCI,
.local = VIA_585, /*VT82C585*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t amd640_device = {
.name = "AMD 640 System Controller",
.internal_name = "amd640",
.flags = DEVICE_PCI,
.local = VIA_595, /*VT82C595*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vp3_device = {
.name = "VIA Apollo VP3",
.internal_name = "via_vp3",
.flags = DEVICE_PCI,
.local = VIA_597, /*VT82C597*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_mvp3_device = {
.name = "VIA Apollo MVP3",
.internal_name = "via_mvp3",
.flags = DEVICE_PCI,
.local = VIA_598, /*VT82C598MVP*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_apro_device = {
.name = "VIA Apollo Pro",
.internal_name = "via_apro",
.flags = DEVICE_PCI,
.local = VIA_691, /*VT82C691*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_apro133_device = {
.name = "VIA Apollo Pro133",
.internal_name = "via_apro133",
.flags = DEVICE_PCI,
.local = VIA_693A, /*VT82C693A*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_apro133a_device = {
.name = "VIA Apollo Pro133A",
.internal_name = "via_apro_133a",
.flags = DEVICE_PCI,
.local = VIA_694, /*VT82C694X*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt8601_device = {
.name = "VIA Apollo ProMedia",
.internal_name = "via_vt8601",
.flags = DEVICE_PCI,
.local = VIA_8601, /*VT8601*/
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/via_apollo.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 11,148 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1541/2 CPU-to-PCI Bridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1541_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram;
void *agp_bridge;
} ali1541_t;
#ifdef ENABLE_ALI1541_LOG
int ali1541_do_log = ENABLE_ALI1541_LOG;
static void
ali1541_log(const char *fmt, ...)
{
va_list ap;
if (ali1541_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1541_log(fmt, ...)
#endif
static void
ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
{
smram_disable_all();
if (val & 1) {
switch (val & 0x0c) {
case 0x00:
ali1541_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break;
case 0x04:
ali1541_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break;
case 0x08:
ali1541_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
default:
break;
}
}
flushmmucache_nopc();
}
static void
ali1541_shadow_recalc(UNUSED(int cur_reg), ali1541_t *dev)
{
int bit;
int r_reg;
int w_reg;
uint32_t base;
uint32_t flags = 0;
shadowbios = shadowbios_write = 0;
for (uint8_t i = 0; i < 16; i++) {
base = 0x000c0000 + (i << 14);
bit = i & 7;
r_reg = 0x56 + (i >> 3);
w_reg = 0x58 + (i >> 3);
flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[r_reg] & (1 << bit))
shadowbios |= 1;
if (dev->pci_conf[w_reg] & (1 << bit))
shadowbios_write |= 1;
}
ali1541_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
flushmmucache_nopc();
}
static void
ali1541_mask_bar(ali1541_t *dev)
{
uint32_t bar;
uint32_t mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
default:
case 0x00:
mask = 0x00000000;
break;
case 0x01:
mask = 0xfff00000;
break;
case 0x02:
mask = 0xffe00000;
break;
case 0x03:
mask = 0xffc00000;
break;
case 0x04:
mask = 0xff800000;
break;
case 0x06:
mask = 0xff000000;
break;
case 0x07:
mask = 0xfe000000;
break;
case 0x08:
mask = 0xfc000000;
break;
case 0x09:
mask = 0xf8000000;
break;
case 0x0a:
mask = 0xf0000000;
break;
}
bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask;
dev->pci_conf[0x12] = (bar >> 16) & 0xff;
dev->pci_conf[0x13] = (bar >> 24) & 0xff;
}
static void
ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf8);
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x12:
dev->pci_conf[0x12] = (val & 0xc0);
ali1541_mask_bar(dev);
break;
case 0x13:
dev->pci_conf[0x13] = val;
ali1541_mask_bar(dev);
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0x34:
if (dev->pci_conf[0x90] & 0x02)
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x41:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* PLCTL-Pipe Line Control */
dev->pci_conf[addr] = val & 0xf7;
break;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
case 0x46:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0x47:
dev->pci_conf[addr] = val;
break;
case 0x48:
dev->pci_conf[addr] = val;
break;
case 0x49:
dev->pci_conf[addr] = val;
break;
case 0x4a:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x4b:
dev->pci_conf[addr] = val;
break;
case 0x4c:
dev->pci_conf[addr] = val;
break;
case 0x4d:
dev->pci_conf[addr] = val;
break;
case 0x4e:
dev->pci_conf[addr] = val;
break;
case 0x4f:
dev->pci_conf[addr] = val;
break;
case 0x50:
dev->pci_conf[addr] = val & 0x71;
break;
case 0x51:
dev->pci_conf[addr] = val;
break;
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53:
dev->pci_conf[addr] = val;
break;
case 0x54:
dev->pci_conf[addr] = val & 0x3c;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
flushmmucache_nopc();
break;
case 0x55: /* SMRAM */
dev->pci_conf[addr] = val & 0x1f;
ali1541_smram_recalc(val, dev);
break;
case 0x56 ... 0x59: /* Shadow RAM */
dev->pci_conf[addr] = val;
ali1541_shadow_recalc(val, dev);
break;
case 0x5a:
case 0x5b:
dev->pci_conf[addr] = val;
break;
case 0x5c:
dev->pci_conf[addr] = val;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x17;
break;
case 0x5e:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xc1;
break;
case 0x60 ... 0x6f: /* DRB's */
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70:
dev->pci_conf[addr] = val;
break;
case 0x71:
dev->pci_conf[addr] = val;
break;
case 0x72:
dev->pci_conf[addr] = val & 0xc7;
break;
case 0x73:
dev->pci_conf[addr] = val & 0x1f;
break;
case 0x84:
case 0x85:
dev->pci_conf[addr] = val;
break;
case 0x86:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x87: /* H2PO */
dev->pci_conf[addr] = val;
/* Find where the Shut-down Special cycle is initiated. */
#if 0
if (!(val & 0x20))
outb(0x92, 0x01);
#endif
break;
case 0x88:
dev->pci_conf[addr] = val;
break;
case 0x89:
dev->pci_conf[addr] = val;
break;
case 0x8a:
dev->pci_conf[addr] = val;
break;
case 0x8b:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x8c:
dev->pci_conf[addr] = val;
break;
case 0x8d:
dev->pci_conf[addr] = val;
break;
case 0x8e:
dev->pci_conf[addr] = val;
break;
case 0x8f:
dev->pci_conf[addr] = val;
break;
case 0x90:
dev->pci_conf[addr] = val;
pci_bridge_set_ctl(dev->agp_bridge, val);
break;
case 0x91:
dev->pci_conf[addr] = val;
break;
case 0xb4:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb5:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x02;
break;
case 0xb7:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0xb8:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb9:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xbb:
dev->pci_conf[addr] = val;
break;
case 0xbc:
dev->pci_conf[addr] = val & 0x0f;
ali1541_mask_bar(dev);
break;
case 0xbd:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0xbe:
case 0xbf:
dev->pci_conf[addr] = val;
break;
case 0xc0:
dev->pci_conf[addr] = val & 0x90;
break;
case 0xc1:
case 0xc2:
case 0xc3:
dev->pci_conf[addr] = val;
break;
case 0xc8:
case 0xc9:
dev->pci_conf[addr] = val;
break;
case 0xd1:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0xd2:
case 0xd3:
dev->pci_conf[addr] = val;
break;
case 0xe0:
case 0xe1:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe2:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xe3:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xfe;
break;
case 0xe4:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xe5:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe6:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xc0;
break;
case 0xe7:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe8:
case 0xe9:
if (dev->pci_conf[0x90] & 0x04)
dev->pci_conf[addr] = val;
break;
case 0xea:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xeb:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xec:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xed:
dev->pci_conf[addr] = val;
break;
case 0xee:
dev->pci_conf[addr] = val & 0x3e;
break;
case 0xef:
dev->pci_conf[addr] = val;
break;
case 0xf3:
dev->pci_conf[addr] = val & 0x08;
break;
case 0xf5:
dev->pci_conf[addr] = val;
break;
case 0xf6:
dev->pci_conf[addr] = val;
break;
case 0xf7:
dev->pci_conf[addr] = val & 0x43;
break;
default:
break;
}
}
static uint8_t
ali1541_read(UNUSED(int func), int addr, void *priv)
{
const ali1541_t *dev = (ali1541_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
}
static void
ali1541_reset(void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x41;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0x00;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0x20;
dev->pci_conf[0x0e] = 0x00;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x2c] = 0xb9;
dev->pci_conf[0x2d] = 0x10;
dev->pci_conf[0x2e] = 0x41;
dev->pci_conf[0x2f] = 0x15;
dev->pci_conf[0x34] = 0xb0;
dev->pci_conf[0x89] = 0x20;
dev->pci_conf[0x8a] = 0x20;
dev->pci_conf[0x91] = 0x13;
dev->pci_conf[0xb0] = 0x02;
dev->pci_conf[0xb1] = 0xe0;
dev->pci_conf[0xb2] = 0x10;
dev->pci_conf[0xb4] = 0x03;
dev->pci_conf[0xb5] = 0x02;
dev->pci_conf[0xb7] = 0x1c;
dev->pci_conf[0xc8] = 0xbf;
dev->pci_conf[0xc9] = 0x0a;
dev->pci_conf[0xe0] = 0x01;
cpu_cache_int_enabled = 1;
ali1541_write(0, 0x42, 0x00, dev);
ali1541_write(0, 0x54, 0x00, dev);
ali1541_write(0, 0x55, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1541_write(0, 0x56 + i, 0x00, dev);
ali1541_write(0, 0x60, 0x07, dev);
ali1541_write(0, 0x61, 0x40, dev);
for (uint8_t i = 0; i < 14; i += 2) {
ali1541_write(0, 0x62 + i, 0x00, dev);
ali1541_write(0, 0x63 + i, 0x00, dev);
}
}
static void
ali1541_close(void *priv)
{
ali1541_t *dev = (ali1541_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1541_init(UNUSED(const device_t *info))
{
ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t));
memset(dev, 0, sizeof(ali1541_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev, &dev->pci_slot);
dev->smram = smram_add();
ali1541_reset(dev);
dev->agp_bridge = device_add(&ali5243_agp_device);
return dev;
}
const device_t ali1541_device = {
.name = "ALi M1541 CPU-to-PCI Bridge",
.internal_name = "ali1541",
.flags = DEVICE_PCI,
.local = 0,
.init = ali1541_init,
.close = ali1541_close,
.reset = ali1541_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1541.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,403 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Chips&Technology's 82C100 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include "x86.h"
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/rom.h>
#include <86box/chipset.h>
typedef struct ems_page_t {
int enabled;
uint32_t virt;
uint32_t phys;
} ems_page_t;
typedef struct ct_82c100_t {
uint8_t index;
uint8_t access;
uint16_t ems_io_base;
uint32_t ems_window_base;
uint8_t ems_page_regs[4];
uint8_t regs[256];
ems_page_t ems_pages[4];
mem_mapping_t ems_mappings[4];
} ct_82c100_t;
#ifdef ENABLE_CT_82C100_LOG
int ct_82c100_do_log = ENABLE_CT_82C100_LOG;
static void
ct_82c100_log(const char *fmt, ...)
{
va_list ap;
if (ct_82c100_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ct_82c100_log(fmt, ...)
#endif
static void
ct_82c100_ems_pages_recalc(ct_82c100_t *dev)
{
uint32_t page_base;
for (uint8_t i = 0; i < 4; i++) {
page_base = dev->ems_window_base + (i << 14);
if ((i == 1) || (i == 2))
page_base ^= 0xc000;
if (dev->ems_page_regs[i] & 0x80) {
dev->ems_pages[i].virt = page_base;
dev->ems_pages[i].phys = 0xa0000 + (((uint32_t) (dev->ems_page_regs[i] & 0x7f)) << 14);
ct_82c100_log("Enabling EMS page %i: %08X-%08X -> %08X-%08X\n", i,
dev->ems_pages[i].virt, dev->ems_pages[i].virt + 0x00003fff,
dev->ems_pages[i].phys, dev->ems_pages[i].phys + 0x00003fff);
mem_mapping_set_addr(&(dev->ems_mappings[i]), dev->ems_pages[i].virt, 0x4000);
mem_mapping_set_exec(&(dev->ems_mappings[i]), &(ram[dev->ems_pages[i].phys]));
mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else {
ct_82c100_log("Disabling EMS page %i\n", i);
mem_mapping_disable(&(dev->ems_mappings[i]));
mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
flushmmucache_nopc();
}
static void
ct_82c100_ems_out(uint16_t port, uint8_t val, void *priv)
{
ct_82c100_t *dev = (ct_82c100_t *) priv;
ct_82c100_log("[%04X] dev->ems_page_regs[%i] = %02X\n", port, port >> 14, val);
dev->ems_page_regs[port >> 14] = val;
ct_82c100_ems_pages_recalc(dev);
}
static uint8_t
ct_82c100_ems_in(uint16_t port, void *priv)
{
const ct_82c100_t *dev = (ct_82c100_t *) priv;
uint8_t ret = 0xff;
ret = dev->ems_page_regs[port >> 14];
return ret;
}
static void
ct_82c100_ems_update(ct_82c100_t *dev)
{
for (uint8_t i = 0; i < 4; i++) {
ct_82c100_log("Disabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
io_handler(0, dev->ems_io_base + (i << 14), 1,
ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
}
dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0);
for (uint8_t i = 0; i < 4; i++) {
ct_82c100_log("Enabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
io_handler(1, dev->ems_io_base + (i << 14), 1,
ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
}
dev->ems_window_base = 0xc0000 + (((uint32_t) (dev->regs[0x4c] & 0x0f)) << 14);
ct_82c100_ems_pages_recalc(dev);
}
static void
ct_82c100_reset(void *priv)
{
ct_82c100_t *dev = (ct_82c100_t *) priv;
ct_82c100_log("Reset\n");
memset(dev->regs, 0x00, sizeof(dev->regs));
memset(dev->ems_page_regs, 0x00, sizeof(dev->ems_page_regs));
dev->index = dev->access = 0x00;
/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
dev->regs[0x40] = 0x01; /* Defaults to 8086/V30 mode. */
dev->regs[0x43] = 0x30;
dev->regs[0x48] = 0x01;
use_custom_nmi_vector = 0;
ct_82c100_ems_update(dev);
/* ADDITIONAL I/O REGISTERS */
}
static void
ct_82c100_out(uint16_t port, uint8_t val, void *priv)
{
ct_82c100_t *dev = (ct_82c100_t *) priv;
if (port == 0x0022) {
dev->index = val;
dev->access = 1;
} else if (port == 0x0023) {
if (dev->access) {
switch (dev->index) {
/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
case 0x40:
dev->regs[0x40] = val & 0xc7;
/* TODO: Clock stuff - needs CPU speed change functionality that's
going to be implemented in 86box v4.0.
Bit 0 is 0 for 8088/V20 and 1 for 8086/V30. */
break;
case 0x41:
dev->regs[0x41] = val & 0xed;
/* TODO: Where is the Software Reset Function that's enabled by
setting bit 6 to 1? */
break;
case 0x42:
dev->regs[0x42] = val & 0x01;
break;
case 0x43:
dev->regs[0x43] = val;
break;
case 0x44:
dev->regs[0x44] = val;
custom_nmi_vector = (custom_nmi_vector & 0xffffff00) | ((uint32_t) val);
break;
case 0x45:
dev->regs[0x45] = val;
custom_nmi_vector = (custom_nmi_vector & 0xffff00ff) | (((uint32_t) val) << 8);
break;
case 0x46:
dev->regs[0x46] = val;
custom_nmi_vector = (custom_nmi_vector & 0xff00ffff) | (((uint32_t) val) << 16);
break;
case 0x47:
dev->regs[0x47] = val;
custom_nmi_vector = (custom_nmi_vector & 0x00ffffff) | (((uint32_t) val) << 24);
break;
case 0x48:
case 0x49:
dev->regs[dev->index] = val;
break;
case 0x4b:
dev->regs[0x4b] = val;
use_custom_nmi_vector = !!(val & 0x40);
break;
case 0x4c:
ct_82c100_log("CS4C: %02X\n", val);
dev->regs[0x4c] = val;
ct_82c100_ems_update(dev);
break;
default:
break;
}
dev->access = 0;
}
} else if (port == 0x72)
dev->regs[0x72] = val & 0x7e;
else if (port == 0x7e)
dev->regs[0x7e] = val;
else if (port == 0x7f) {
/* Bit 3 is Software Controlled Reset, asserted if set. Will be
done in the feature/machine_and_kb branch using hardresetx86(). */
dev->regs[0x7f] = val;
if ((dev->regs[0x41] & 0x40) && (val & 0x08)) {
softresetx86();
cpu_set_edx();
ct_82c100_reset(dev);
}
}
}
static uint8_t
ct_82c100_in(uint16_t port, void *priv)
{
ct_82c100_t *dev = (ct_82c100_t *) priv;
uint8_t ret = 0xff;
if (port == 0x0022)
ret = dev->index;
else if (port == 0x0023) {
if (dev->access) {
switch (dev->index) {
/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
case 0x40 ... 0x49:
case 0x4b:
case 0x4c:
ret = dev->regs[dev->index];
break;
default:
break;
}
dev->access = 0;
}
} else if (port == 0x72)
ret = dev->regs[0x72];
else if (port == 0x7e)
ret = dev->regs[0x7e];
else if (port == 0x7f)
ret = dev->regs[0x7f];
return ret;
}
static uint8_t
mem_read_emsb(uint32_t addr, void *priv)
{
const ems_page_t *page = (ems_page_t *) priv;
uint8_t ret = 0xff;
#ifdef ENABLE_CT_82C100_LOG
uint32_t old_addr = addr;
#endif
addr = addr - page->virt + page->phys;
if (addr < (mem_size << 10))
ret = ram[addr];
ct_82c100_log("mem_read_emsb(%08X = %08X): %02X\n", old_addr, addr, ret);
return ret;
}
static uint16_t
mem_read_emsw(uint32_t addr, void *priv)
{
const ems_page_t *page = (ems_page_t *) priv;
uint16_t ret = 0xffff;
#ifdef ENABLE_CT_82C100_LOG
uint32_t old_addr = addr;
#endif
addr = addr - page->virt + page->phys;
if (addr < (mem_size << 10))
ret = *(uint16_t *) &ram[addr];
ct_82c100_log("mem_read_emsw(%08X = %08X): %04X\n", old_addr, addr, ret);
return ret;
}
static void
mem_write_emsb(uint32_t addr, uint8_t val, void *priv)
{
const ems_page_t *page = (ems_page_t *) priv;
#ifdef ENABLE_CT_82C100_LOG
uint32_t old_addr = addr;
#endif
addr = addr - page->virt + page->phys;
if (addr < (mem_size << 10))
ram[addr] = val;
ct_82c100_log("mem_write_emsb(%08X = %08X, %02X)\n", old_addr, addr, val);
}
static void
mem_write_emsw(uint32_t addr, uint16_t val, void *priv)
{
const ems_page_t *page = (ems_page_t *) priv;
#ifdef ENABLE_CT_82C100_LOG
uint32_t old_addr = addr;
#endif
addr = addr - page->virt + page->phys;
if (addr < (mem_size << 10))
*(uint16_t *) &ram[addr] = val;
ct_82c100_log("mem_write_emsw(%08X = %08X, %04X)\n", old_addr, addr, val);
}
static void
ct_82c100_close(void *priv)
{
ct_82c100_t *dev = (ct_82c100_t *) priv;
free(dev);
}
static void *
ct_82c100_init(UNUSED(const device_t *info))
{
ct_82c100_t *dev;
dev = (ct_82c100_t *) malloc(sizeof(ct_82c100_t));
memset(dev, 0x00, sizeof(ct_82c100_t));
ct_82c100_reset(dev);
io_sethandler(0x0022, 2,
ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
io_sethandler(0x0072, 1,
ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
io_sethandler(0x007e, 2,
ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
for (uint8_t i = 0; i < 4; i++) {
mem_mapping_add(&(dev->ems_mappings[i]), (i + 28) << 14, 0x04000,
mem_read_emsb, mem_read_emsw, NULL,
mem_write_emsb, mem_write_emsw, NULL,
ram + 0xa0000 + (i << 14), MEM_MAPPING_INTERNAL, &dev->ems_pages[i]);
mem_mapping_disable(&(dev->ems_mappings[i]));
}
mem_mapping_disable(&ram_mid_mapping);
device_add(&port_92_device);
return dev;
}
const device_t ct_82c100_device = {
.name = "C&T 82C100",
.internal_name = "ct_82c100",
.flags = 0,
.local = 0,
.init = ct_82c100_init,
.close = ct_82c100_close,
.reset = ct_82c100_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/82c100.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,601 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ETEQ Cheetah ET6000 chipset.
*
*
*
* Authors: Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#define INDEX (dev->index - 0x10)
typedef struct et6000_t {
uint8_t index;
uint8_t regs[256];
} et6000_t;
#ifdef ENABLE_ET6000_LOG
int et6000_do_log = ENABLE_ET6000_LOG;
static void
et6000_log(const char *fmt, ...)
{
va_list ap;
if (et6000_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define et6000_log(fmt, ...)
#endif
static void
et6000_shadow_control(int base, int size, int can_read, int can_write)
{
mem_set_mem_state_both(base, size, (can_read ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (can_write ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
flushmmucache_nopc();
}
static void
et6000_write(uint16_t addr, uint8_t val, void *priv)
{
et6000_t *dev = (et6000_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
switch (INDEX) {
case 0: /* System Configuration Register */
dev->regs[INDEX] = val & 0xdf;
et6000_shadow_control(0xa0000, 0x20000, val & 1, val & 1);
refresh_at_enable = !(val & 0x10);
break;
case 1: /* CACHE Configuration and Non-Cacheable Block Size */
dev->regs[INDEX] = val & 0xf0;
break;
case 2: /* Non-Cacheable Block Address Register */
dev->regs[INDEX] = val & 0xfe;
break;
case 3: /* DRAM Bank and Type Configuration Register */
dev->regs[INDEX] = val;
break;
case 4: /* DRAM Configuration Register */
dev->regs[INDEX] = val;
et6000_shadow_control(0xc0000, 0x10000, (dev->regs[0x15] & 2) && (val & 0x20), (dev->regs[0x15] & 2) && (val & 0x20) && (dev->regs[0x15] & 1));
et6000_shadow_control(0xd0000, 0x10000, (dev->regs[0x15] & 8) && (val & 0x20), (dev->regs[0x15] & 8) && (val & 0x20) && (dev->regs[0x15] & 4));
break;
case 5: /* Shadow RAM Configuration Register */
dev->regs[INDEX] = val;
et6000_shadow_control(0xc0000, 0x10000, (val & 2) && (dev->regs[0x14] & 0x20), (val & 2) && (dev->regs[0x14] & 0x20) && (val & 1));
et6000_shadow_control(0xd0000, 0x10000, (val & 8) && (dev->regs[0x14] & 0x20), (val & 8) && (dev->regs[0x14] & 0x20) && (val & 4));
et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10));
et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40));
break;
default:
break;
}
et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]);
break;
default:
break;
}
}
static uint8_t
et6000_read(uint16_t addr, void *priv)
{
const et6000_t *dev = (et6000_t *) priv;
return ((addr == 0x23) && (INDEX >= 0) && (INDEX <= 5)) ? dev->regs[INDEX] : 0xff;
}
static void
et6000_close(void *priv)
{
et6000_t *dev = (et6000_t *) priv;
free(dev);
}
static void *
et6000_init(UNUSED(const device_t *info))
{
et6000_t *dev = (et6000_t *) malloc(sizeof(et6000_t));
memset(dev, 0, sizeof(et6000_t));
/* Port 92h */
device_add(&port_92_device);
/* Defaults */
dev->regs[3] = 1;
/* Shadow Programming */
et6000_shadow_control(0xf0000, 0x10000, 0, 1);
io_sethandler(0x0022, 2, et6000_read, NULL, NULL, et6000_write, NULL, NULL, dev); /* Ports 22h-23h: ETEQ Cheetah ET6000 */
return dev;
}
const device_t et6000_device = {
.name = "ETEQ Cheetah ET6000",
.internal_name = "et6000",
.flags = 0,
.local = 0,
.init = et6000_init,
.close = et6000_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/et6000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,493 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 85c496/85c497 chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#define USE_DRB_HACK
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/nvr.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#ifndef USE_DRB_HACK
#include <86box/row.h>
#endif
typedef struct sis_85c496_t {
uint8_t cur_reg;
uint8_t rmsmiblk_count;
uint8_t pci_slot;
uint8_t pad;
#ifndef USE_DRB_HACK
uint8_t drb_default;
uint8_t drb_bits;
uint8_t pad0;
uint8_t pad1;
#endif
uint8_t regs[127];
uint8_t pci_conf[256];
smram_t *smram;
pc_timer_t rmsmiblk_timer;
port_92_t *port_92;
nvr_t *nvr;
} sis_85c496_t;
#ifdef ENABLE_SIS_85C496_LOG
int sis_85c496_do_log = ENABLE_SIS_85C496_LOG;
void
sis_85c496_log(const char *fmt, ...)
{
va_list ap;
if (sis_85c496_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_85c496_log(fmt, ...)
#endif
static void
sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
sis_85c496_log("[%04X:%08X] ISA Write %02X to %04X\n", CS, cpu_state.pc, val, port);
if (port == 0x22)
dev->cur_reg = val;
else if (port == 0x23)
switch (dev->cur_reg) {
case 0x01: /* Built-in 206 Timing Control */
dev->regs[dev->cur_reg] = val;
break;
case 0x70: /* ISA Bus Clock Selection */
dev->regs[dev->cur_reg] = val & 0xc0;
break;
case 0x71: /* ISA Bus Timing Control */
dev->regs[dev->cur_reg] = val & 0xf6;
break;
case 0x72:
case 0x76: /* SMOUT */
case 0x74: /* BIOS Timer */
dev->regs[dev->cur_reg] = val;
break;
case 0x73: /* BIOS Timer */
dev->regs[dev->cur_reg] = val & 0xfd;
break;
case 0x75: /* DMA / Deturbo Control */
dev->regs[dev->cur_reg] = val & 0xfc;
dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff);
break;
default:
break;
}
}
static uint8_t
sis_85c497_isa_read(uint16_t port, void *priv)
{
const sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t ret = 0xff;
if ((port == 0x23) && (dev->cur_reg < 0xc0))
ret = dev->regs[dev->cur_reg];
else if (port == 0x33)
ret = 0x3c /*random_generate()*/;
sis_85c496_log("[%04X:%08X] ISA Read %02X from %04X\n", CS, cpu_state.pc, ret, port);
return ret;
}
static void
sis_85c496_recalcmapping(sis_85c496_t *dev)
{
uint32_t base;
uint32_t shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
if (dev->pci_conf[0x44] & (1 << i)) {
shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02);
shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01);
shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state_both(base, 0x8000, shflags);
} else
mem_set_mem_state_both(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
flushmmucache_nopc();
}
static void
sis_85c496_ide_handler(sis_85c496_t *dev)
{
uint8_t ide_cfg[2];
ide_cfg[0] = dev->pci_conf[0x58];
ide_cfg[1] = dev->pci_conf[0x59];
ide_pri_disable();
ide_sec_disable();
if (ide_cfg[1] & 0x02) {
ide_set_base(0, 0x0170);
ide_set_side(0, 0x0376);
ide_set_base(1, 0x01f0);
ide_set_side(1, 0x03f6);
if (ide_cfg[1] & 0x01) {
if (!(ide_cfg[0] & 0x40))
ide_pri_enable();
if (!(ide_cfg[0] & 0x80))
ide_sec_enable();
}
} else {
ide_set_base(0, 0x01f0);
ide_set_side(0, 0x03f6);
ide_set_base(1, 0x0170);
ide_set_side(1, 0x0376);
if (ide_cfg[1] & 0x01) {
if (!(ide_cfg[0] & 0x40))
ide_sec_enable();
if (!(ide_cfg[0] & 0x80))
ide_pri_enable();
}
}
}
#ifndef USE_DRB_HACK
static void
sis_85c496_drb_recalc(sis_85c496_t *dev)
{
int i;
uint32_t boundary;
for (i = 7; i >= 0; i--)
row_disable(i);
for (i = 0; i <= 7; i++) {
boundary = ((uint32_t) dev->pci_conf[0x48 + i]);
row_set_boundary(i, boundary);
}
flushmmucache();
}
#endif
/* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
static void
sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t old;
uint8_t valxor;
uint8_t smm_irq[4] = { 10, 11, 12, 15 };
uint32_t host_base;
uint32_t ram_base;
uint32_t size;
old = dev->pci_conf[addr];
valxor = (dev->pci_conf[addr]) ^ val;
sis_85c496_log("[%04X:%08X] PCI Write %02X to %02X:%02X\n", CS, cpu_state.pc, val, func, addr);
switch (addr) {
/* PCI Configuration Header Registers (00h ~ 3Fh) */
case 0x04: /* PCI Device Command */
dev->pci_conf[addr] = val & 0x40;
break;
case 0x05: /* PCI Device Command */
dev->pci_conf[addr] = val & 0x03;
break;
case 0x07: /* Device Status */
dev->pci_conf[addr] &= ~(val & 0xf1);
break;
/* 86C496 Specific Registers (40h ~ 7Fh) */
case 0x40: /* CPU Configuration */
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x41: /* DRAM Configuration */
dev->pci_conf[addr] = val;
break;
case 0x42: /* Cache Configure */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x01);
cpu_update_waitstates();
break;
case 0x43: /* Cache Configure */
dev->pci_conf[addr] = val & 0x8f;
break;
case 0x44: /* Shadow Configure */
dev->pci_conf[addr] = val;
if (valxor & 0xff) {
sis_85c496_recalcmapping(dev);
if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x30))
flushmmucache_nopc();
else if (((old & 0xf0) == 0xf0) && ((val & 0xf0) == 0x00))
flushmmucache_nopc();
else
flushmmucache();
}
break;
case 0x45: /* Shadow Configure */
dev->pci_conf[addr] = val & 0x0f;
if (valxor & 0x03)
sis_85c496_recalcmapping(dev);
break;
case 0x46: /* Cacheable Control */
dev->pci_conf[addr] = val;
break;
case 0x47: /* 85C496 Address Decoder */
dev->pci_conf[addr] = val & 0x1f;
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b: /* DRAM Boundary */
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f:
#ifdef USE_DRB_HACK
spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1);
#else
dev->pci_conf[addr] = val;
sis_85c496_drb_recalc(dev);
#endif
break;
case 0x50:
case 0x51: /* Exclusive Area 0 Setup */
dev->pci_conf[addr] = val;
break;
case 0x52:
case 0x53: /* Exclusive Area 1 Setup */
dev->pci_conf[addr] = val;
break;
case 0x54: /* Exclusive Area 2 Setup */
dev->pci_conf[addr] = val;
break;
case 0x55: /* Exclusive Area 3 Setup */
dev->pci_conf[addr] = val & 0xf0;
break;
case 0x56: /* PCI / Keyboard Configure */
dev->pci_conf[addr] = val;
if (valxor & 0x02) {
port_92_remove(dev->port_92);
if (val & 0x02)
port_92_add(dev->port_92);
}
break;
case 0x57: /* Output Pin Configuration */
dev->pci_conf[addr] = val;
break;
case 0x58: /* Build-in IDE Controller / VESA Bus Configuration */
dev->pci_conf[addr] = val & 0xd7;
if (valxor & 0xc0)
sis_85c496_ide_handler(dev);
break;
case 0x59: /* Build-in IDE Controller / VESA Bus Configuration */
dev->pci_conf[addr] = val;
if (valxor & 0x03)
sis_85c496_ide_handler(dev);
break;
case 0x5a: /* SMRAM Remapping Configuration */
dev->pci_conf[addr] = val & 0xbe;
if (valxor & 0x3e) {
unmask_a20_in_smm = !!(val & 0x20);
smram_disable_all();
if (val & 0x02) {
host_base = 0x00060000;
ram_base = 0x000a0000;
size = 0x00010000;
switch ((val >> 3) & 0x03) {
case 0x00:
host_base = 0x00060000;
ram_base = 0x000a0000;
break;
case 0x01:
host_base = 0x00060000;
ram_base = 0x000b0000;
break;
case 0x02:
host_base = 0x000e0000;
ram_base = 0x000a0000;
break;
case 0x03:
host_base = 0x000e0000;
ram_base = 0x000b0000;
break;
default:
break;
}
smram_enable(dev->smram, host_base, ram_base, size,
((val & 0x06) == 0x06), (val & 0x02));
}
}
break;
case 0x5b: /* Programmable I/O Traps Configure */
case 0x5c:
case 0x5d: /* Programmable I/O Trap 0 Base */
case 0x5e:
case 0x5f: /* Programmable I/O Trap 0 Base */
case 0x60:
case 0x61: /* IDE Controller Channel 0 Configuration */
case 0x62:
case 0x63: /* IDE Controller Channel 1 Configuration */
case 0x64:
case 0x65: /* Exclusive Area 3 Setup */
case 0x66: /* EDO DRAM Configuration */
case 0x68:
case 0x69: /* Asymmetry DRAM Configuration */
dev->pci_conf[addr] = val;
break;
case 0x67: /* Miscellaneous Control */
dev->pci_conf[addr] = val & 0xf9;
cpu_cpurst_on_sr = ((val & 0xa0) == 0x80) && !(dev->pci_conf[0xc6] & 0x08);
break;
/* 86C497 Specific Registers (80h ~ FFh) */
case 0x80: /* PMU Configuration */
case 0x85: /* STPCLK# Event Control */
case 0x86:
case 0x87: /* STPCLK# Deassertion IRQ Selection */
case 0x89: /* Fast Timer Count */
case 0x8a: /* Generic Timer Count */
case 0x8b: /* Slow Timer Count */
case 0x8e: /* Clock Throttling On Timer Count */
case 0x8f: /* Clock Throttling Off Timer Count */
case 0x90: /* Clock Throttling On Timer Reload Condition */
case 0x92: /* Fast Timer Reload Condition */
case 0x94: /* Generic Timer Reload Condition */
case 0x96: /* Slow Timer Reload Condition */
case 0x98:
case 0x99: /* Fast Timer Reload IRQ Selection */
case 0x9a:
case 0x9b: /* Generic Timer Reload IRQ Selection */
case 0x9c:
case 0x9d: /* Slow Timer Reload IRQ Selection */
case 0xa2: /* SMI Request Status Selection */
case 0xa4:
case 0xa5: /* SMI Request IRQ Selection */
case 0xa6:
case 0xa7: /* Clock Throttlign On Timer Reload IRQ Selection */
case 0xa8: /* GPIO Control */
case 0xaa: /* GPIO DeBounce Count */
case 0xd2: /* Exclusive Area 2 Base Address */
dev->pci_conf[addr] = val;
break;
case 0x81: /* PMU CPU Type Configuration */
dev->pci_conf[addr] = val & 0x9f;
break;
case 0x88: /* Timer Control */
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x8d: /* RMSMIBLK Timer Count */
dev->pci_conf[addr] = val;
dev->rmsmiblk_count = val;
timer_stop(&dev->rmsmiblk_timer);
if (val >= 0x02)
timer_on_auto(&dev->rmsmiblk_timer, 35.0);
break;
case 0x91: /* Clock Throttling On Timer Reload Condition */
case 0x93: /* Fast Timer Reload Condition */
case 0x95: /* Generic Timer Reload Condition */
dev->pci_conf[addr] = val & 0x03;
break;
case 0x97: /* Slow Timer Reload Condition */
dev->pci_conf[addr] = val & 0xc3;
break;
case 0x9e: /* Soft-SMI Generation / RMSMIBLK Trigger */
if (!smi_block && (val & 0x01) && (dev->pci_conf[0x80] & 0x80) && (dev->pci_conf[0xa2] & 0x10)) {
if (dev->pci_conf[0x80] & 0x10)
picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]);
else
smi_raise();
smi_block = 1;
dev->pci_conf[0xa0] |= 0x10;
}
if (val & 0x02) {
timer_stop(&dev->rmsmiblk_timer);
if (dev->rmsmiblk_count >= 0x02)
timer_on_auto(&dev->rmsmiblk_timer, 35.0);
}
break;
case 0xa0:
case 0xa1: /* SMI Request Status */
dev->pci_conf[addr] &= ~val;
break;
case 0xa3: /* SMI Request Status Selection */
dev->pci_conf[addr] = val & 0x7f;
break;
case 0xa9: /* GPIO SMI Request Status */
dev->pci_conf[addr] = ~(val & 0x03);
break;
case 0xc0: /* PCI INTA# -to-IRQ Link */
case 0xc1: /* PCI INTB# -to-IRQ Link */
case 0xc2: /* PCI INTC# -to-IRQ Link */
case 0xc3: /* PCI INTD# -to-IRQ Link */
dev->pci_conf[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf);
else
pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED);
break;
case 0xc6: /* 85C497 Post / INIT Configuration */
dev->pci_conf[addr] = val & 0x0f;
cpu_cpurst_on_sr = ((dev->pci_conf[0x67] & 0xa0) == 0x80) && !(val & 0x08);
soft_reset_pci = !!(val & 0x04);
break;
case 0xc8:
case 0xc9:
case 0xca:
case 0xcb: /* Mail Box */
dev->pci_conf[addr] = val;
break;
case 0xd0: /* ISA BIOS Configuration */
dev->pci_conf[addr] = val & 0xfb;
break;
case 0xd1: /* ISA Address Decoder */
if (dev->pci_conf[0xd0] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0xd3: /* Exclusive Area 2 Base Address */
dev->pci_conf[addr] = val & 0xf0;
break;
case 0xd4: /* Miscellaneous Configuration */
dev->pci_conf[addr] = val & 0x6e;
nvr_bank_set(0, !!(val & 0x40), dev->nvr);
break;
default:
break;
}
}
static uint8_t
sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
{
const sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t ret = dev->pci_conf[addr];
switch (addr) {
case 0xa0:
ret &= 0x10;
break;
case 0xa1:
ret = 0x00;
break;
case 0x82: /*Port 22h Mirror*/
ret = dev->cur_reg;
break;
case 0x83: /*Port 70h Mirror*/
ret = inb(0x70);
break;
default:
break;
}
sis_85c496_log("[%04X:%08X] PCI Read %02X from %02X:%02X\n", CS, cpu_state.pc, ret, func, addr);
return ret;
}
static void
sis_85c496_rmsmiblk_count(void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
dev->rmsmiblk_count--;
if (dev->rmsmiblk_count == 1) {
smi_block = 0;
dev->rmsmiblk_count = 0;
timer_stop(&dev->rmsmiblk_timer);
} else
timer_on_auto(&dev->rmsmiblk_timer, 35.0);
}
static void
sis_85c497_isa_reset(sis_85c496_t *dev)
{
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x01] = 0xc0;
dev->regs[0x71] = 0x01;
dev->regs[0x72] = 0xff;
dev->regs[0x76] = 0xff;
dma_set_mask(0x00ffffff);
io_removehandler(0x0022, 0x0002,
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
io_removehandler(0x0033, 0x0001,
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
io_sethandler(0x0022, 0x0002,
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
io_sethandler(0x0033, 0x0001,
sis_85c497_isa_read, NULL, NULL, sis_85c497_isa_write, NULL, NULL, dev);
}
static void
sis_85c496_reset(void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
sis_85c49x_pci_write(0, 0x44, 0x00, dev);
sis_85c49x_pci_write(0, 0x45, 0x00, dev);
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
for (uint8_t i = 0; i < 8; i++)
dev->pci_conf[0x48 + i] = 0x02;
sis_85c49x_pci_write(0, 0x80, 0x00, dev);
sis_85c49x_pci_write(0, 0x81, 0x00, dev);
sis_85c49x_pci_write(0, 0x9e, 0x00, dev);
sis_85c49x_pci_write(0, 0x8d, 0x00, dev);
sis_85c49x_pci_write(0, 0xa0, 0xff, dev);
sis_85c49x_pci_write(0, 0xa1, 0xff, dev);
sis_85c49x_pci_write(0, 0xc0, 0x00, dev);
sis_85c49x_pci_write(0, 0xc1, 0x00, dev);
sis_85c49x_pci_write(0, 0xc2, 0x00, dev);
sis_85c49x_pci_write(0, 0xc3, 0x00, dev);
sis_85c49x_pci_write(0, 0xc8, 0x00, dev);
sis_85c49x_pci_write(0, 0xc9, 0x00, dev);
sis_85c49x_pci_write(0, 0xca, 0x00, dev);
sis_85c49x_pci_write(0, 0xcb, 0x00, dev);
sis_85c49x_pci_write(0, 0xd0, 0x79, dev);
sis_85c49x_pci_write(0, 0xd1, 0xff, dev);
sis_85c49x_pci_write(0, 0xd0, 0x78, dev);
sis_85c49x_pci_write(0, 0xd4, 0x00, dev);
dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0xc6] = 0x00;
ide_pri_disable();
ide_sec_disable();
nvr_bank_set(0, 0, dev->nvr);
sis_85c497_isa_reset(dev);
cpu_cpurst_on_sr = 0;
soft_reset_pci = 0;
}
static void
sis_85c496_close(void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void
*
sis_85c496_init(const device_t *info)
{
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
memset(dev, 0x00, sizeof(sis_85c496_t));
dev->smram = smram_add();
/* PCI Configuration Header Registers (00h ~ 3Fh) */
dev->pci_conf[0x00] = 0x39; /* SiS */
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x96; /* 496/497 */
dev->pci_conf[0x03] = 0x04;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x06] = 0x80;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x02; /* Device revision */
dev->pci_conf[0x09] = 0x00; /* Device class (PCI bridge) */
dev->pci_conf[0x0b] = 0x06;
/* 86C496 Specific Registers (40h ~ 7Fh) */
/* 86C497 Specific Registers (80h ~ FFh) */
dev->pci_conf[0xd0] = 0x78; /* ROM at E0000-FFFFF, Flash enable. */
dev->pci_conf[0xd1] = 0xff;
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev, &dev->pci_slot);
#if 0
sis_85c497_isa_reset(dev);
#endif
dev->port_92 = device_add(&port_92_device);
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
port_92_set_features(dev->port_92, 0, 0);
sis_85c496_recalcmapping(dev);
ide_pri_disable();
ide_sec_disable();
if (info->local)
dev->nvr = device_add(&ami_1994_nvr_device);
else
dev->nvr = device_add(&at_nvr_device);
dma_high_page_init();
timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
#ifndef USE_DRB_HACK
row_device.local = 7 | (1 << 8) | (0x02 << 16) | (8 << 24);
device_add((const device_t *) &row_device);
#endif
sis_85c496_reset(dev);
return dev;
}
const device_t sis_85c496_device = {
.name = "SiS 85c496/85c497",
.internal_name = "sis_85c496",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_85c496_init,
.close = sis_85c496_close,
.reset = sis_85c496_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_85c496_ls486e_device = {
.name = "SiS 85c496/85c497 (Lucky Star LS-486E)",
.internal_name = "sis_85c496_ls486e",
.flags = DEVICE_PCI,
.local = 1,
.init = sis_85c496_init,
.close = sis_85c496_close,
.reset = sis_85c496_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_85c496.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,219 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5513 IDE controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5513_IDE_LOG
int sis_5513_ide_do_log = ENABLE_SIS_5513_IDE_LOG;
static void
sis_5513_ide_log(const char *fmt, ...)
{
va_list ap;
if (sis_5513_ide_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5513_ide_log(fmt, ...)
#endif
typedef struct sis_5513_ide_t {
uint8_t rev;
uint8_t pci_conf[256];
sis_55xx_common_t *sis;
} sis_5513_ide_t;
static void
sis_5513_ide_irq_handler(sis_5513_ide_t *dev)
{
if (dev->pci_conf[0x09] & 0x01) {
/* Primary IDE is native. */
sis_5513_ide_log("Primary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->sis->bm[0], IRQ_MODE_SIS_551X);
} else {
/* Primary IDE is legacy. */
sis_5513_ide_log("Primary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->sis->bm[0], IRQ_MODE_LEGACY);
}
if (dev->pci_conf[0x09] & 0x04) {
/* Secondary IDE is native. */
sis_5513_ide_log("Secondary IDE IRQ mode: Native, Native\n");
sff_set_irq_mode(dev->sis->bm[1], IRQ_MODE_SIS_551X);
} else {
/* Secondary IDE is legacy. */
sis_5513_ide_log("Secondary IDE IRQ mode: IRQ14, IRQ15\n");
sff_set_irq_mode(dev->sis->bm[1], IRQ_MODE_LEGACY);
}
}
static void
sis_5513_ide_handler(sis_5513_ide_t *dev)
{
uint8_t ide_io_on = dev->pci_conf[0x04] & 0x01;
uint16_t native_base_pri_addr = (dev->pci_conf[0x11] | dev->pci_conf[0x10] << 8) & 0xfffe;
uint16_t native_side_pri_addr = (dev->pci_conf[0x15] | dev->pci_conf[0x14] << 8) & 0xfffe;
uint16_t native_base_sec_addr = (dev->pci_conf[0x19] | dev->pci_conf[0x18] << 8) & 0xfffe;
uint16_t native_side_sec_addr = (dev->pci_conf[0x1c] | dev->pci_conf[0x1b] << 8) & 0xfffe;
uint16_t current_pri_base;
uint16_t current_pri_side;
uint16_t current_sec_base;
uint16_t current_sec_side;
/* Primary Channel Programming */
current_pri_base = (!(dev->pci_conf[0x09] & 1)) ? 0x01f0 : native_base_pri_addr;
current_pri_side = (!(dev->pci_conf[0x09] & 1)) ? 0x03f6 : native_side_pri_addr;
/* Secondary Channel Programming */
current_sec_base = (!(dev->pci_conf[0x09] & 4)) ? 0x0170 : native_base_sec_addr;
current_sec_side = (!(dev->pci_conf[0x09] & 4)) ? 0x0376 : native_side_sec_addr;
sis_5513_ide_log("sis_5513_ide_handler(): Disabling primary IDE...\n");
ide_pri_disable();
sis_5513_ide_log("sis_5513_ide_handler(): Disabling secondary IDE...\n");
ide_sec_disable();
if (ide_io_on) {
/* Primary Channel Setup */
if (dev->pci_conf[0x4a] & 0x02) {
sis_5513_ide_log("sis_5513_ide_handler(): Primary IDE base now %04X...\n", current_pri_base);
ide_set_base(0, current_pri_base);
sis_5513_ide_log("sis_5513_ide_handler(): Primary IDE side now %04X...\n", current_pri_side);
ide_set_side(0, current_pri_side);
sis_5513_ide_log("sis_5513_ide_handler(): Enabling primary IDE...\n");
ide_pri_enable();
sis_5513_ide_log("SiS 5513 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side);
}
/* Secondary Channel Setup */
if (dev->pci_conf[0x4a] & 0x04) {
sis_5513_ide_log("sis_5513_ide_handler(): Secondary IDE base now %04X...\n", current_sec_base);
ide_set_base(1, current_sec_base);
sis_5513_ide_log("sis_5513_ide_handler(): Secondary IDE side now %04X...\n", current_sec_side);
ide_set_side(1, current_sec_side);
sis_5513_ide_log("sis_5513_ide_handler(): Enabling secondary IDE...\n");
ide_sec_enable();
sis_5513_ide_log("SiS 5513: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side);
}
}
sff_bus_master_handler(dev->sis->bm[0], ide_io_on,
((dev->pci_conf[0x20] & 0xf0) | (dev->pci_conf[0x21] << 8)) + 0);
sff_bus_master_handler(dev->sis->bm[1], ide_io_on,
((dev->pci_conf[0x20] & 0xf0) | (dev->pci_conf[0x21] << 8)) + 8);
}
void
sis_5513_ide_write(int addr, uint8_t val, void *priv)
{
sis_5513_ide_t *dev = (sis_5513_ide_t *) priv;
sis_5513_ide_log("SiS 5513 IDE: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
case 0x04: /* Command low byte */
dev->pci_conf[addr] = val & 0x05;
sis_5513_ide_handler(dev);
break;
case 0x06: /* Status low byte */
dev->pci_conf[addr] = val & 0x20;
break;
case 0x07: /* Status high byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x06) & ~(val & 0x38);
break;
case 0x09: /* Programming Interface Byte */
switch (dev->rev) {
case 0xd0:
if (dev->sis->ide_bits_1_3_writable)
val |= 0x0a;
fallthrough;
case 0x00:
case 0xd1:
val &= 0xbf;
fallthrough;
case 0xc0:
switch (val & 0x0a) {
case 0x00:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x85) | (val & 0x4a);
break;
case 0x02:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x84) | (val & 0x4b);
break;
case 0x08:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x81) | (val & 0x4e);
break;
case 0x0a:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x80) | (val & 0x4f);
break;
}
break;
}
sis_5513_ide_irq_handler(dev);
sis_5513_ide_handler(dev);
break;
case 0x0d: /* Latency Timer */
dev->pci_conf[addr] = val;
break;
/* Primary Base Address */
case 0x10 ... 0x11:
case 0x14 ... 0x15:
fallthrough;
/* Secondary Base Address */
case 0x18 ... 0x19:
case 0x1c ... 0x1d:
fallthrough;
/* Bus Mastering Base Address */
case 0x20 ... 0x21:
if (addr == 0x20)
dev->pci_conf[addr] = (val & 0xe0) | 0x01;
else if ((addr & 0x07) == 0x00)
dev->pci_conf[addr] = (val & 0xf8) | 0x01;
else if ((addr & 0x07) == 0x04)
dev->pci_conf[addr] = (val & 0xfc) | 0x01;
else
dev->pci_conf[addr] = val;
sis_5513_ide_handler(dev);
break;
case 0x2c ... 0x2f:
if (dev->rev >= 0xd0)
dev->pci_conf[addr] = val;
break;
case 0x30 ... 0x33: /* Expansion ROM Base Address */
#ifdef DATASHEET
dev->pci_conf[addr] = val;
#else
if (dev->rev == 0x00)
dev->pci_conf[addr] = val;
#endif
break;
case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */
if (dev->rev >= 0xd0)
dev->pci_conf[addr] = val & 0xcf;
else
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */
case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */
case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */
case 0x48: /* IDE Command Recovery Time Control */
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */
case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */
case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */
case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */
if (dev->rev >= 0xd0)
dev->pci_conf[addr] = val & 0xe7;
else
dev->pci_conf[addr] = val & 0x07;
break;
case 0x49: /* IDE Command Active Time Control */
dev->pci_conf[addr] = val & 0x07;
break;
case 0x4a: /* IDE General Control Register 0 */
switch (dev->rev) {
case 0x00:
dev->pci_conf[addr] = val & 0x9e;
break;
case 0xc0:
dev->pci_conf[addr] = val & 0xaf;
break;
case 0xd0:
dev->pci_conf[addr] = val;
break;
}
sis_5513_ide_handler(dev);
break;
case 0x4b: /* IDE General Control Register 1 */
if (dev->rev >= 0xc0)
dev->pci_conf[addr] = val;
else
dev->pci_conf[addr] = val & 0xef;
break;
case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */
case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */
case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf[addr] = val;
break;
case 0x50:
case 0x51:
if (dev->rev >= 0xd0)
dev->pci_conf[addr] = val;
break;
case 0x52:
if (dev->rev >= 0xd0)
dev->pci_conf[addr] = val & 0x0f;
break;
default:
break;
}
}
uint8_t
sis_5513_ide_read(int addr, void *priv)
{
const sis_5513_ide_t *dev = (sis_5513_ide_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
default:
ret = dev->pci_conf[addr];
break;
case 0x09:
ret = dev->pci_conf[addr];
if (dev->rev >= 0xc0) {
if (dev->pci_conf[0x09] & 0x40)
ret |= ((dev->pci_conf[0x4a] & 0x06) << 3);
if ((dev->rev == 0xd0) && dev->sis->ide_bits_1_3_writable)
ret |= 0x0a;
}
break;
case 0x3d:
if (dev->rev >= 0xc0)
ret = (dev->pci_conf[0x09] & 0x05) ? PCI_INTA : 0x00;
else
ret = (((dev->pci_conf[0x4b] & 0xc0) == 0xc0) ||
(dev->pci_conf[0x09] & 0x05)) ? PCI_INTA : 0x00;
break;
}
sis_5513_ide_log("SiS 5513 IDE: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5513_ide_reset(void *priv)
{
sis_5513_ide_t *dev = (sis_5513_ide_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x13;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = dev->pci_conf[0x07] = 0x00;
dev->pci_conf[0x08] = (dev->rev == 0xd1) ? 0xd0 : dev->rev;
dev->pci_conf[0x09] = 0x8a;
dev->pci_conf[0x0a] = dev->pci_conf[0x0b] = 0x01;
dev->pci_conf[0x0c] = dev->pci_conf[0x0d] = 0x00;
dev->pci_conf[0x0e] = 0x80;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x10] = 0xf1;
dev->pci_conf[0x11] = 0x01;
dev->pci_conf[0x14] = 0xf5;
dev->pci_conf[0x15] = 0x03;
dev->pci_conf[0x18] = 0x71;
dev->pci_conf[0x19] = 0x01;
dev->pci_conf[0x1c] = 0x75;
dev->pci_conf[0x1d] = 0x03;
dev->pci_conf[0x20] = 0x01;
dev->pci_conf[0x21] = 0xf0;
dev->pci_conf[0x22] = dev->pci_conf[0x23] = 0x00;
dev->pci_conf[0x24] = dev->pci_conf[0x25] = 0x00;
dev->pci_conf[0x26] = dev->pci_conf[0x27] = 0x00;
dev->pci_conf[0x28] = dev->pci_conf[0x29] = 0x00;
dev->pci_conf[0x2a] = dev->pci_conf[0x2b] = 0x00;
switch (dev->rev) {
case 0x00:
case 0xd0:
case 0xd1:
dev->pci_conf[0x2c] = dev->pci_conf[0x2d] = 0x00;
break;
case 0xc0:
#ifdef DATASHEET
dev->pci_conf[0x2c] = dev->pci_conf[0x2d] = 0x00;
#else
/* The only Linux lspci listing I could find of this chipset,
shows a subsystem of 0058:0000. */
dev->pci_conf[0x2c] = 0x58;
dev->pci_conf[0x2d] = 0x00;
#endif
break;
}
dev->pci_conf[0x2e] = dev->pci_conf[0x2f] = 0x00;
dev->pci_conf[0x30] = dev->pci_conf[0x31] = 0x00;
dev->pci_conf[0x32] = dev->pci_conf[0x33] = 0x00;
dev->pci_conf[0x40] = dev->pci_conf[0x41] = 0x00;
dev->pci_conf[0x42] = dev->pci_conf[0x43] = 0x00;
dev->pci_conf[0x44] = dev->pci_conf[0x45] = 0x00;
dev->pci_conf[0x46] = dev->pci_conf[0x47] = 0x00;
dev->pci_conf[0x48] = dev->pci_conf[0x49] = 0x00;
dev->pci_conf[0x4a] = 0x06;
dev->pci_conf[0x4b] = 0x00;
dev->pci_conf[0x4c] = dev->pci_conf[0x4d] = 0x00;
dev->pci_conf[0x4e] = dev->pci_conf[0x4f] = 0x00;
sis_5513_ide_irq_handler(dev);
sis_5513_ide_handler(dev);
sff_bus_master_reset(dev->sis->bm[0]);
sff_bus_master_reset(dev->sis->bm[1]);
}
static void
sis_5513_ide_close(void *priv)
{
sis_5513_ide_t *dev = (sis_5513_ide_t *) priv;
free(dev);
}
static void *
sis_5513_ide_init(UNUSED(const device_t *info))
{
sis_5513_ide_t *dev = (sis_5513_ide_t *) calloc(1, sizeof(sis_5513_ide_t));
dev->rev = info->local;
dev->sis = device_get_common_priv();
/* SFF IDE */
dev->sis->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->sis->bm[1] = device_add_inst(&sff8038i_device, 2);
sis_5513_ide_reset(dev);
return dev;
}
const device_t sis_5513_ide_device = {
.name = "SiS 5513 IDE controller",
.internal_name = "sis_5513_ide",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5572_ide_device = {
.name = "SiS 5572 IDE controller",
.internal_name = "sis_5572_ide",
.flags = DEVICE_PCI,
.local = 0xc0,
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5582_ide_device = {
.name = "SiS 5582 IDE controller",
.internal_name = "sis_5582_ide",
.flags = DEVICE_PCI,
.local = 0xd0,
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5591_5600_ide_device = {
.name = "SiS 5591/(5)600 IDE controller",
.internal_name = "sis_5591_5600_ide",
.flags = DEVICE_PCI,
.local = 0xd1, /* D0, but we need to distinguish them. */
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5513_ide.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,383 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1531B CPU-to-PCI Bridge.
*
*
*
* Authors: Tiseno100,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1531_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram;
} ali1531_t;
#ifdef ENABLE_ALI1531_LOG
int ali1531_do_log = ENABLE_ALI1531_LOG;
static void
ali1531_log(const char *fmt, ...)
{
va_list ap;
if (ali1531_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1531_log(fmt, ...)
#endif
static void
ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
{
smram_disable_all();
if (val & 1) {
switch (val & 0x0c) {
case 0x00:
ali1531_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break;
case 0x04:
ali1531_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break;
case 0x08:
ali1531_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
default:
break;
}
}
flushmmucache_nopc();
}
static void
ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev)
{
int bit;
int r_reg;
int w_reg;
uint32_t base;
uint32_t flags = 0;
shadowbios = shadowbios_write = 0;
for (uint8_t i = 0; i < 16; i++) {
base = 0x000c0000 + (i << 14);
bit = i & 7;
r_reg = 0x4c + (i >> 3);
w_reg = 0x4e + (i >> 3);
flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[r_reg] & (1 << bit))
shadowbios |= 1;
if (dev->pci_conf[w_reg] & (1 << bit))
shadowbios_write |= 1;
}
ali1531_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
flushmmucache_nopc();
}
static void
ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf8);
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pci_conf[0x70] & 0x08)
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0x41:
dev->pci_conf[addr] = (val & 0xd6) | 0x08;
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val & 0xf7;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* L1 Cache */
dev->pci_conf[addr] = val;
cpu_cache_int_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
case 0x46:
dev->pci_conf[addr] = val;
break;
case 0x47:
dev->pci_conf[addr] = val & 0xfc;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
flushmmucache_nopc();
break;
case 0x48: /* SMRAM */
dev->pci_conf[addr] = val;
ali1531_smram_recalc(val, dev);
break;
case 0x49:
dev->pci_conf[addr] = val & 0x73;
break;
case 0x4a:
dev->pci_conf[addr] = val;
break;
case 0x4c ... 0x4f: /* Shadow RAM */
dev->pci_conf[addr] = val;
ali1531_shadow_recalc(val, dev);
break;
case 0x50:
case 0x51:
case 0x52:
case 0x54:
case 0x55:
case 0x56:
dev->pci_conf[addr] = val;
break;
case 0x57: /* H2PO */
dev->pci_conf[addr] = val & 0x60;
/* Find where the Shut-down Special cycle is initiated. */
#if 0
if (!(val & 0x20))
outb(0x92, 0x01);
#endif
break;
case 0x58:
dev->pci_conf[addr] = val & 0x86;
break;
case 0x59:
case 0x5a:
case 0x5c:
dev->pci_conf[addr] = val;
break;
case 0x5b:
dev->pci_conf[addr] = val & 0x4f;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x53;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x60 ... 0x6f: /* DRB's */
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70:
case 0x71:
dev->pci_conf[addr] = val;
break;
case 0x72:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x74:
dev->pci_conf[addr] = val & 0x2b;
break;
case 0x76:
case 0x77:
dev->pci_conf[addr] = val;
break;
case 0x80:
dev->pci_conf[addr] = val & 0x84;
break;
case 0x81:
dev->pci_conf[addr] = val & 0x81;
break;
case 0x83:
dev->pci_conf[addr] = val & 0x10;
break;
default:
break;
}
}
static uint8_t
ali1531_read(UNUSED(int func), int addr, void *priv)
{
const ali1531_t *dev = (ali1531_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
}
static void
ali1531_reset(void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x31;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0xb0;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0x20;
dev->pci_conf[0x0e] = 0x00;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x2c] = 0xb9;
dev->pci_conf[0x2d] = 0x10;
dev->pci_conf[0x2e] = 0x31;
dev->pci_conf[0x2f] = 0x15;
dev->pci_conf[0x52] = 0xf0;
dev->pci_conf[0x54] = 0xff;
dev->pci_conf[0x55] = 0xff;
dev->pci_conf[0x59] = 0x20;
dev->pci_conf[0x5a] = 0x20;
dev->pci_conf[0x70] = 0x22;
ali1531_write(0, 0x42, 0x00, dev);
ali1531_write(0, 0x43, 0x00, dev);
ali1531_write(0, 0x47, 0x00, dev);
ali1531_write(0, 0x48, 0x00, dev);
for (uint8_t i = 0; i < 4; i++)
ali1531_write(0, 0x4c + i, 0x00, dev);
for (uint8_t i = 0; i < 16; i += 2) {
ali1531_write(0, 0x60 + i, 0x08, dev);
ali1531_write(0, 0x61 + i, 0x40, dev);
}
}
static void
ali1531_close(void *priv)
{
ali1531_t *dev = (ali1531_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1531_init(UNUSED(const device_t *info))
{
ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t));
memset(dev, 0, sizeof(ali1531_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev, &dev->pci_slot);
dev->smram = smram_add();
ali1531_reset(dev);
return dev;
}
const device_t ali1531_device = {
.name = "ALi M1531 CPU-to-PCI Bridge",
.internal_name = "ali1531",
.flags = DEVICE_PCI,
.local = 0,
.init = ali1531_init,
.close = ali1531_close,
.reset = ali1531_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1531.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,437 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Olivetti EVA (98/86) Gate Array.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: EngiNerd <webmaster.crrc@yahoo.it>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/video.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
typedef struct olivetti_eva_t {
uint8_t reg_065;
uint8_t reg_067;
uint8_t reg_069;
} olivetti_eva_t;
#ifdef ENABLE_OLIVETTI_EVA_LOG
int olivetti_eva_do_log = ENABLE_OLIVETTI_EVA_LOG;
static void
olivetti_eva_log(const char *fmt, ...)
{
va_list ap;
if (olivetti_eva_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define olivetti_eva_log(fmt, ...)
#endif
static void
olivetti_eva_write(uint16_t addr, uint8_t val, void *priv)
{
olivetti_eva_t *dev = (olivetti_eva_t *) priv;
olivetti_eva_log("Olivetti EVA Gate Array: Write %02x at %02x\n", val, addr);
switch (addr) {
case 0x065:
dev->reg_065 = val;
break;
case 0x067:
dev->reg_067 = val;
break;
case 0x069:
dev->reg_069 = val;
/*
* Unfortunately, if triggered, the BIOS remapping function fails causing
* a fatal error. Therefore, this code section is currently commented.
*/
#if 0
if (val & 1) {
/*
* Set the register to 7 or above for the BIOS to trigger the
* memory remapping function if shadowing is active.
*/
dev->reg_069 = 0x7;
}
if (val & 8) {
/*
* Activate shadowing for region e0000-fffff
*/
mem_remap_top(256);
mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
#endif
break;
default:
break;
}
}
static uint8_t
olivetti_eva_read(uint16_t addr, void *priv)
{
const olivetti_eva_t *dev = (olivetti_eva_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x065:
ret = dev->reg_065;
break;
case 0x067:
/* never happens */
ret = dev->reg_067;
break;
case 0x069:
ret = dev->reg_069;
break;
default:
break;
}
olivetti_eva_log("Olivetti EVA Gate Array: Read %02x at %02x\n", ret, addr);
return ret;
}
static void
olivetti_eva_close(void *priv)
{
olivetti_eva_t *dev = (olivetti_eva_t *) priv;
free(dev);
}
static void *
olivetti_eva_init(UNUSED(const device_t *info))
{
olivetti_eva_t *dev = (olivetti_eva_t *) malloc(sizeof(olivetti_eva_t));
memset(dev, 0, sizeof(olivetti_eva_t));
/* GA98 registers */
dev->reg_065 = 0x00;
/* RAM page registers: never read, only set */
dev->reg_067 = 0x00;
/* RAM enable registers */
dev->reg_069 = 0x0;
io_sethandler(0x0065, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
io_sethandler(0x0067, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
io_sethandler(0x0069, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
/* When shadowing is not enabled in BIOS, all upper memory is available as XMS */
mem_remap_top(384);
/*
* Default settings when NVRAM is cleared activate shadowing.
* Thus, to avoid boot errors, remap only 256k from UMB to XMS.
* Remove this block once BIOS memory remapping works.
*/
mem_remap_top(256);
return dev;
}
const device_t olivetti_eva_device = {
.name = "Olivetti EVA Gate Array",
.internal_name = "olivetta_eva",
.flags = 0,
.local = 0,
.init = olivetti_eva_init,
.close = olivetti_eva_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/olivetti_eva.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,347 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C802G/82C895 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct opti895_t {
uint8_t idx;
uint8_t forced_green;
uint8_t is_pci;
uint8_t regs[256];
uint8_t scratch[2];
smram_t *smram;
} opti895_t;
static uint8_t masks[0x10] = { 0x3f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
0xe3, 0xff, 0xe3, 0xff, 0x00, 0xff, 0xff, 0xff };
#ifdef ENABLE_OPTI895_LOG
int opti895_do_log = ENABLE_OPTI895_LOG;
static void
opti895_log(const char *fmt, ...)
{
va_list ap;
if (opti895_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti895_log(fmt, ...)
#endif
static void
opti895_recalc(opti895_t *dev)
{
uint32_t base;
uint32_t shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
if (dev->regs[0x22] & 0x80) {
shadowbios = 1;
shadowbios_write = 0;
shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
} else {
shadowbios = 0;
shadowbios_write = 1;
shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
}
if (dev->is_pci)
mem_set_mem_state_cpu_both(0xf0000, 0x10000, shflags);
else
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if (dev->regs[0x23] & (1 << i)) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
shflags = (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
if (dev->regs[0x26] & 0x40)
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
else {
if (dev->regs[0x26] & 0x80)
shflags |= (dev->regs[0x2d] & (1 << ((i >> 1) + 2))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
else
shflags |= MEM_WRITE_EXTERNAL;
}
}
if (dev->is_pci)
mem_set_mem_state_cpu_both(base, 0x4000, shflags);
else
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if (dev->regs[0x26] & (1 << i)) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
shflags = (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
if (dev->regs[0x26] & 0x40)
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
else {
if (dev->regs[0x26] & 0x80)
shflags |= (dev->regs[0x2d] & (1 << (i >> 1))) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
else
shflags |= MEM_WRITE_EXTERNAL;
}
}
if (dev->is_pci)
mem_set_mem_state_cpu_both(base, 0x4000, shflags);
else
mem_set_mem_state_both(base, 0x4000, shflags);
}
flushmmucache_nopc();
}
static void
opti895_write(uint16_t addr, uint8_t val, void *priv)
{
opti895_t *dev = (opti895_t *) priv;
opti895_log("opti895_write(%04X, %08X)\n", addr, val);
switch (addr) {
case 0x22:
dev->idx = val;
break;
case 0x23:
if (dev->idx == 0x01) {
dev->regs[dev->idx] = val;
opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val);
}
break;
case 0x24:
if (((dev->idx >= 0x20) && (dev->idx <= 0x2f) && (dev->idx != 0x2c)) ||
((dev->idx >= 0xe0) && (dev->idx <= 0xef))) {
if (dev->idx > 0x2f)
dev->regs[dev->idx] = val;
else
dev->regs[dev->idx] = val & masks[dev->idx - 0x20];
opti895_log("dev->regs[%04x] = %08x\n", dev->idx, val);
/* TODO: Registers 0x30-0x3F for OPTi 802GP and 898. */
switch (dev->idx) {
case 0x21:
cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10);
cpu_update_waitstates();
break;
case 0x22:
case 0x23:
case 0x26:
case 0x2d:
opti895_recalc(dev);
break;
case 0x24:
smram_state_change(dev->smram, 0, !!(val & 0x80));
break;
case 0xe0:
if (!(val & 0x01))
dev->forced_green = 0;
break;
case 0xe1:
if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) {
smi_raise();
dev->forced_green = 1;
break;
}
break;
default:
break;
}
}
break;
case 0xe1:
case 0xe2:
dev->scratch[addr - 0xe1] = val;
break;
default:
break;
}
}
static uint8_t
opti895_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
const opti895_t *dev = (opti895_t *) priv;
switch (addr) {
case 0x23:
if (dev->idx == 0x01)
ret = dev->regs[dev->idx];
break;
case 0x24:
/* TODO: Registers 0x30-0x3F for OPTi 802GP and 898. */
if (((dev->idx >= 0x20) && (dev->idx <= 0x2f) && (dev->idx != 0x2c)) ||
((dev->idx >= 0xe0) && (dev->idx <= 0xef))) {
ret = dev->regs[dev->idx];
if (dev->idx == 0xe0)
ret = (ret & 0xf6) | (in_smm ? 0x00 : 0x08) | !!dev->forced_green;
}
break;
case 0xe1:
case 0xe2:
ret = dev->scratch[addr - 0xe1];
break;
default:
break;
}
opti895_log("opti895_read(%04X) = %02X\n", addr, ret);
return ret;
}
static void
opti895_close(void *priv)
{
opti895_t *dev = (opti895_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
opti895_init(const device_t *info)
{
opti895_t *dev = (opti895_t *) malloc(sizeof(opti895_t));
memset(dev, 0, sizeof(opti895_t));
device_add(&port_92_device);
io_sethandler(0x0022, 0x0003, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
dev->is_pci = info->local;
dev->scratch[0] = dev->scratch[1] = 0xff;
dev->regs[0x01] = 0xc0;
dev->regs[0x22] = 0xc4;
dev->regs[0x25] = 0x7c;
dev->regs[0x26] = 0x10;
dev->regs[0x27] = 0xde;
dev->regs[0x28] = 0xf8;
dev->regs[0x29] = 0x10;
dev->regs[0x2a] = 0xe0;
dev->regs[0x2b] = 0x10;
dev->regs[0x2d] = 0xc0;
dev->regs[0xe8] = 0x08;
dev->regs[0xe9] = 0x08;
dev->regs[0xeb] = 0xff;
dev->regs[0xef] = 0x40;
opti895_recalc(dev);
io_sethandler(0x00e1, 0x0002, opti895_read, NULL, NULL, opti895_write, NULL, NULL, dev);
dev->smram = smram_add();
smram_enable(dev->smram, 0x00030000, 0x000b0000, 0x00010000, 0, 1);
return dev;
}
const device_t opti802g_device = {
.name = "OPTi 82C802G",
.internal_name = "opti802g",
.flags = 0,
.local = 0,
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti802g_pci_device = {
.name = "OPTi 82C802G (PCI)",
.internal_name = "opti802g_pci",
.flags = 0,
.local = 1,
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti895_device = {
.name = "OPTi 82C895",
.internal_name = "opti895",
.flags = 0,
.local = 0,
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti895.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,926 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VIA VT82C505 VL/PCI Bridge Controller.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/device.h>
#include <86box/chipset.h>
typedef struct vt82c505_t {
uint8_t index;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf[256];
} vt82c505_t;
static void
vt82c505_write(int func, int addr, uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t irq;
const uint8_t irq_array[8] = { 0, 5, 9, 10, 11, 14, 15, 0 };
if (func != 0)
return;
switch (addr) {
/* RX00-07h: Mandatory header field */
case 0x04:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xbf) | (val & 0x40);
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0x90);
break;
/* RX80-9F: VT82C505 internal configuration registers */
case 0x80:
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0x0f) | (val & 0xf0);
break;
case 0x81:
case 0x84:
case 0x85:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f:
case 0x92:
case 0x94:
dev->pci_conf[addr] = val;
break;
case 0x82:
dev->pci_conf[addr] = val & 0xdb;
break;
case 0x83:
dev->pci_conf[addr] = val & 0xf9;
break;
case 0x86:
dev->pci_conf[addr] = val & 0xef;
/* Bit 7 switches between the two PCI configuration mechanisms:
0 = configuration mechanism 1, 1 = configuration mechanism 2 */
pci_set_pmc(!(val & 0x80));
break;
case 0x90:
dev->pci_conf[addr] = val;
irq = irq_array[val & 0x07];
if ((val & 0x08) && (irq != 0))
pci_set_irq_routing(PCI_INTC, irq);
else
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
irq = irq_array[(val & 0x70) >> 4];
if ((val & 0x80) && (irq != 0))
pci_set_irq_routing(PCI_INTD, irq);
else
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
break;
case 0x91:
dev->pci_conf[addr] = val;
irq = irq_array[val & 0x07];
if ((val & 0x08) && (irq != 0))
pci_set_irq_routing(PCI_INTA, irq);
else
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
irq = irq_array[(val & 0x70) >> 4];
if ((val & 0x80) && (irq != 0))
pci_set_irq_routing(PCI_INTB, irq);
else
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
break;
case 0x93:
dev->pci_conf[addr] = val & 0xe0;
break;
default:
break;
}
}
static uint8_t
vt82c505_read(int func, int addr, void *priv)
{
const vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
if (func != 0)
return ret;
ret = dev->pci_conf[addr];
return ret;
}
static void
vt82c505_out(uint16_t addr, uint8_t val, void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
if (addr == 0xa8)
dev->index = val;
else if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
vt82c505_write(0, dev->index, val, priv);
}
static uint8_t
vt82c505_in(uint16_t addr, void *priv)
{
const vt82c505_t *dev = (vt82c505_t *) priv;
uint8_t ret = 0xff;
if ((addr == 0xa9) && (dev->index >= 0x80) && (dev->index <= 0x9f))
ret = vt82c505_read(0, dev->index, priv);
return ret;
}
static void
vt82c505_reset(void *priv)
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x00;
for (uint8_t i = 0x80; i <= 0x9f; i++) {
switch (i) {
case 0x81:
vt82c505_write(0, i, 0x01, priv);
break;
case 0x84:
vt82c505_write(0, i, 0x03, priv);
break;
case 0x93:
vt82c505_write(0, i, 0x40, priv);
break;
default:
vt82c505_write(0, i, 0x00, priv);
break;
}
}
pic_reset();
pic_set_pci_flag(1);
}
static void
vt82c505_close(void *priv)
{
vt82c505_t *dev = (vt82c505_t *) priv;
free(dev);
}
static void *
vt82c505_init(UNUSED(const device_t *info))
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev, &dev->pci_slot);
dev->pci_conf[0x00] = 0x06;
dev->pci_conf[0x01] = 0x11;
dev->pci_conf[0x02] = 0x05;
dev->pci_conf[0x03] = 0x05;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x00;
dev->pci_conf[0x81] = 0x01;
dev->pci_conf[0x84] = 0x03;
dev->pci_conf[0x93] = 0x40;
io_sethandler(0x0a8, 0x0002, vt82c505_in, NULL, NULL, vt82c505_out, NULL, NULL, dev);
return dev;
}
const device_t via_vt82c505_device = {
.name = "VIA VT82C505",
.internal_name = "via_vt82c505",
.flags = DEVICE_PCI,
.local = 0,
.init = vt82c505_init,
.close = vt82c505_close,
.reset = vt82c505_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/via_vt82c505.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,004 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5572 USB controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#ifdef ENABLE_SIS_5595_PMU_LOG
int sis_5595_pmu_do_log = ENABLE_SIS_5595_PMU_LOG;
static void
sis_5595_pmu_log(const char *fmt, ...)
{
va_list ap;
if (sis_5595_pmu_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5595_pmu_log(fmt, ...)
#endif
typedef struct sis_5595_pmu_io_trap_t {
void *priv;
void *trap;
uint8_t flags, mask;
uint8_t *sts_reg, sts_mask;
uint16_t addr;
} sis_5595_pmu_io_trap_t;
typedef struct sis_5595_pmu_t {
uint8_t is_1997;
uint8_t pci_conf[256];
sis_5595_pmu_io_trap_t io_traps[22];
sis_55xx_common_t *sis;
} sis_5595_pmu_t;
static void
sis_5595_pmu_trap_io(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val),
void *priv)
{
sis_5595_pmu_io_trap_t *trap = (sis_5595_pmu_io_trap_t *) priv;
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) trap->priv;
trap->sts_reg[0x04] |= trap->sts_mask;
if (trap->sts_reg[0x00] & trap->sts_mask)
acpi_sis5595_pmu_event(dev->sis->acpi);
if (trap->sts_reg[0x20] & trap->sts_mask)
acpi_update_irq(dev->sis->acpi);
}
static void
sis_5595_pmu_trap_io_ide(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
sis_5595_pmu_io_trap_t *trap = (sis_5595_pmu_io_trap_t *) priv;
/* IDE traps are per drive, not per channel. */
if (ide_drives[trap->flags & 0x03]->selected)
sis_5595_pmu_trap_io(size, addr, write, val, priv);
}
static void
sis_5595_pmu_trap_io_mask(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
sis_5595_pmu_io_trap_t *trap = (sis_5595_pmu_io_trap_t *) priv;
if ((addr & trap->mask) == (trap->addr & trap->mask))
sis_5595_pmu_trap_io(size, addr, write, val, priv);
}
static void
sis_5595_pmu_trap_io_ide_bm(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
sis_5595_pmu_io_trap_t *trap = (sis_5595_pmu_io_trap_t *) priv;
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) trap->priv;
if (trap->flags & 0x01) {
dev->pci_conf[0x67] |= 0x01;
dev->pci_conf[0x64] |= 0x08;
} else {
dev->pci_conf[0x67] |= 0x02;
dev->pci_conf[0x64] |= 0x10;
}
acpi_sis5595_pmu_event(dev->sis->acpi);
}
static void
sis_5595_pmu_trap_update_devctl(sis_5595_pmu_t *dev, uint8_t trap_id, uint8_t enable,
uint8_t flags, uint8_t mask, uint8_t *sts_reg, uint8_t sts_mask,
uint16_t addr, uint16_t size)
{
sis_5595_pmu_io_trap_t *trap = &dev->io_traps[trap_id];
/* Set up Device I/O traps dynamically. */
if (enable && !trap->trap) {
trap->priv = (void *) dev;
trap->flags = flags;
trap->mask = mask;
trap->addr = addr;
if (flags & 0x10)
trap->trap = io_trap_add(sis_5595_pmu_trap_io_ide_bm, trap);
else if (flags & 0x08)
trap->trap = io_trap_add(sis_5595_pmu_trap_io_mask, trap);
else if (flags & 0x04)
trap->trap = io_trap_add(sis_5595_pmu_trap_io_ide, trap);
else
trap->trap = io_trap_add(sis_5595_pmu_trap_io, trap);
trap->sts_reg = sts_reg;
trap->sts_mask = sts_mask;
}
/* Remap I/O trap. */
io_trap_remap(trap->trap, enable, addr, size);
}
static void
sis_5595_pmu_trap_update(void *priv)
{
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) priv;
uint8_t trap_id = 0;
uint8_t *fregs = dev->pci_conf;
uint16_t temp;
uint8_t mask;
uint8_t on;
temp = (fregs[0x7e] | (fregs[0x7f] << 8)) & 0xffe0;
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
fregs[0x7e] & 0x08, 0x10, 0xff, NULL, 0xff, temp, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
fregs[0x7e] & 0x04, 0x10, 0xff, NULL, 0xff, temp + 8, 0x08);
on = fregs[0x63] | fregs[0x83];
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x04, 0xff, &(fregs[0x63]), 0x02, 0x1f0, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x01, 0x06, 0xff, &(fregs[0x63]), 0x01, 0x170, 0x08);
on = fregs[0x62] | fregs[0x82];
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x80, 0x00, 0xff, &(fregs[0x62]), 0x80, 0x064, 0x01);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x80, 0x00, 0xff, &(fregs[0x62]), 0x80, 0x060, 0x01);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x40, 0x00, 0xff, &(fregs[0x62]), 0x40, 0x3f8, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x20, 0x00, 0xff, &(fregs[0x62]), 0x20, 0x2f8, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x00, 0xff, &(fregs[0x62]), 0x10, 0x378, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x00, 0xff, &(fregs[0x62]), 0x10, 0x278, 0x08);
temp = (fregs[0x5c] | (fregs[0x5d] << 8)) & 0x03ff;
mask = fregs[0x5d] >> 2;
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x04, 0x08, mask, &(fregs[0x62]), 0x04, temp, 0x40);
temp = fregs[0x5e] | (fregs[0x5f] << 8);
if (dev->is_1997) {
mask = fregs[0x4d] & 0x1f;
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x08, mask, &(fregs[0x62]), 0x02, temp, 0x20);
} else {
mask = fregs[0x4d];
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x08, mask, &(fregs[0x62]), 0x02, temp, 0x100);
}
on = fregs[0x61] | fregs[0x81];
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x40, 0x00, 0xff, &(fregs[0x61]), 0x40, 0x3b0, 0x30);
switch ((fregs[0x4c] >> 6) & 0x03) {
case 0x00:
temp = 0xf40;
break;
case 0x01:
temp = 0xe80;
break;
case 0x02:
temp = 0x604;
break;
default:
temp = 0x530;
break;
}
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x00, 0xff, &(fregs[0x61]), 0x10, temp, 0x08);
switch ((fregs[0x4c] >> 4) & 0x03) {
case 0x00:
temp = 0x280;
break;
case 0x01:
temp = 0x260;
break;
case 0x02:
temp = 0x240;
break;
default:
temp = 0x220;
break;
}
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x08, 0x00, 0xff, &(fregs[0x61]), 0x08, temp, 0x14);
switch ((fregs[0x4c] >> 2) & 0x03) {
case 0x00:
temp = 0x330;
break;
case 0x01:
temp = 0x320;
break;
case 0x02:
temp = 0x310;
break;
default:
temp = 0x300;
break;
}
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x04, 0x00, 0xff, &(fregs[0x61]), 0x04, temp, 0x04);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x00, 0xff, &(fregs[0x61]), 0x02, 0x200, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x00, 0xff, &(fregs[0x61]), 0x02, 0x388, 0x04);
on = fregs[0x60] | fregs[0x80];
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x20, 0x00, 0xff, &(fregs[0x60]), 0x20, 0x3f0, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x20, 0x00, 0xff, &(fregs[0x60]), 0x20, 0x370, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x05, 0xff, &(fregs[0x60]), 0x10, 0x1f0, 0x08);
sis_5595_pmu_trap_update_devctl(dev, trap_id++,
on & 0x08, 0x07, 0xff, &(fregs[0x60]), 0x08, 0x170, 0x08);
}
void
sis_5595_pmu_write(int addr, uint8_t val, void *priv)
{
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) priv;
sis_5595_pmu_log("SiS 5595 PMU: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (dev->sis->usb_enabled) switch (addr) {
default:
break;
case 0x40 ... 0x4b:
case 0x50 ... 0x5b:
case 0x68 ... 0x7b:
case 0x7d:
dev->pci_conf[addr] = val;
break;
case 0x4c ... 0x4d:
case 0x5c ... 0x63:
case 0x7e ... 0x7f:
case 0x80 ... 0x83:
dev->pci_conf[addr] = val;
sis_5595_pmu_trap_update(dev);
break;
case 0x64 ... 0x67:
dev->pci_conf[addr] &= ~val;
break;
case 0x7c:
dev->pci_conf[addr] = val;
if (val & 0x02) {
dev->pci_conf[0x64] |= 0x04;
if (dev->pci_conf[0x60] & 0x04)
acpi_sis5595_pmu_event(dev->sis->acpi);
}
break;
}
}
uint8_t
sis_5595_pmu_read(int addr, void *priv)
{
const sis_5595_pmu_t *dev = (sis_5595_pmu_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5595_pmu_log("SiS 5595 PMU: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5595_pmu_reset(void *priv)
{
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x09;
dev->pci_conf[0x03] = 0x00;
dev->pci_conf[0x04] = dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0xff;
dev->pci_conf[0x0c] = dev->pci_conf[0x0d] = 0x00;
dev->pci_conf[0x0e] = 0x80;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x40] = dev->pci_conf[0x41] = 0x00;
dev->pci_conf[0x42] = dev->pci_conf[0x43] = 0x00;
dev->pci_conf[0x44] = dev->pci_conf[0x45] = 0x00;
dev->pci_conf[0x46] = dev->pci_conf[0x47] = 0x00;
dev->pci_conf[0x48] = dev->pci_conf[0x49] = 0x00;
dev->pci_conf[0x4a] = dev->pci_conf[0x4b] = 0x00;
dev->pci_conf[0x4c] = dev->pci_conf[0x4d] = 0x00;
dev->pci_conf[0x4e] = dev->pci_conf[0x4f] = 0x00;
dev->pci_conf[0x50] = dev->pci_conf[0x51] = 0x00;
dev->pci_conf[0x52] = dev->pci_conf[0x53] = 0x00;
dev->pci_conf[0x54] = dev->pci_conf[0x55] = 0x00;
dev->pci_conf[0x56] = dev->pci_conf[0x57] = 0x00;
dev->pci_conf[0x58] = dev->pci_conf[0x59] = 0x00;
dev->pci_conf[0x5a] = dev->pci_conf[0x5b] = 0x00;
dev->pci_conf[0x5c] = dev->pci_conf[0x5d] = 0x00;
dev->pci_conf[0x5e] = dev->pci_conf[0x5f] = 0x00;
dev->pci_conf[0x60] = dev->pci_conf[0x61] = 0x00;
dev->pci_conf[0x62] = dev->pci_conf[0x63] = 0x00;
dev->pci_conf[0x64] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x66] = dev->pci_conf[0x67] = 0x00;
dev->pci_conf[0x68] = dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6a] = dev->pci_conf[0x6b] = 0x00;
dev->pci_conf[0x6c] = dev->pci_conf[0x6d] = 0x00;
dev->pci_conf[0x6e] = dev->pci_conf[0x6f] = 0x00;
dev->pci_conf[0x70] = dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x76] = dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x78] = dev->pci_conf[0x79] = 0x00;
dev->pci_conf[0x7a] = dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x7c] = dev->pci_conf[0x7d] = 0x00;
dev->pci_conf[0x7e] = dev->pci_conf[0x7f] = 0x00;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x82] = dev->pci_conf[0x83] = 0x00;
sis_5595_pmu_trap_update(dev);
acpi_update_irq(dev->sis->acpi);
}
static void
sis_5595_pmu_close(void *priv)
{
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) priv;
free(dev);
}
static void *
sis_5595_pmu_init(UNUSED(const device_t *info))
{
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) calloc(1, sizeof(sis_5595_pmu_t));
dev->sis = device_get_common_priv();
dev->sis->pmu_regs = dev->pci_conf;
dev->is_1997 = info->local;
sis_5595_pmu_reset(dev);
return dev;
}
const device_t sis_5595_1997_pmu_device = {
.name = "SiS 5595 (1997) PMU",
.internal_name = "sis_5595_1997_pmu",
.flags = DEVICE_PCI,
.local = 0x01,
.init = sis_5595_pmu_init,
.close = sis_5595_pmu_close,
.reset = sis_5595_pmu_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5595_pmu_device = {
.name = "SiS 5595 PMU",
.internal_name = "sis_5595_pmu",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5595_pmu_init,
.close = sis_5595_pmu_close,
.reset = sis_5595_pmu_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5595_pmu.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,469 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5581/5582 Pentium PCI/ISA Chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5581_LOG
int sis_5581_do_log = ENABLE_SIS_5581_LOG;
static void
sis_5581_log(const char *fmt, ...)
{
va_list ap;
if (sis_5581_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5581_log(fmt, ...)
#endif
typedef struct sis_5581_t {
uint8_t nb_slot;
uint8_t sb_slot;
void *h2p;
void *p2i;
void *ide;
void *usb;
sis_55xx_common_t *sis;
} sis_5581_t;
static void
sis_5581_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
sis_5581_log("SiS 5581: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5581_host_to_pci_write(addr, val, dev->h2p);
}
static uint8_t
sis_5581_read(int func, int addr, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5581_host_to_pci_read(addr, dev->h2p);
sis_5581_log("SiS 5581: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5582_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
sis_5581_log("SiS 5582: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (func) {
case 0x00:
sis_5513_pci_to_isa_write(addr, val, dev->p2i);
break;
case 0x01:
sis_5513_ide_write(addr, val, dev->ide);
break;
case 0x02:
sis_5572_usb_write(addr, val, dev->usb);
break;
}
}
static uint8_t
sis_5582_read(int func, int addr, void *priv)
{
const sis_5581_t *dev = (sis_5581_t *) priv;
uint8_t ret = 0xff;
switch (func) {
case 0x00:
ret = sis_5513_pci_to_isa_read(addr, dev->p2i);
break;
case 0x01:
ret = sis_5513_ide_read(addr, dev->ide);
break;
case 0x02:
ret = sis_5572_usb_read(addr, dev->usb);
break;
}
sis_5581_log("SiS 5582: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5581_close(void *priv)
{
sis_5581_t *dev = (sis_5581_t *) priv;
free(dev);
}
static void *
sis_5581_init(UNUSED(const device_t *info))
{
sis_5581_t *dev = (sis_5581_t *) calloc(1, sizeof(sis_5581_t));
/* Device 0: SiS 5581 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5581_read, sis_5581_write, dev, &dev->nb_slot);
/* Device 1: SiS 5582 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5582_read, sis_5582_write, dev, &dev->sb_slot);
dev->sis = device_add(&sis_55xx_common_device);
dev->p2i = device_add_linked(&sis_5582_p2i_device, dev->sis);
dev->h2p = device_add_linked(&sis_5581_h2p_device, dev->sis);
dev->ide = device_add_linked(&sis_5582_ide_device, dev->sis);
dev->usb = device_add_linked(&sis_5582_usb_device, dev->sis);
return dev;
}
const device_t sis_5581_device = {
.name = "SiS 5581",
.internal_name = "sis_5581",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5581_init,
.close = sis_5581_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5581.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,465 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS (5)600 Pentium PCI/ISA Chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5600_LOG
int sis_5600_do_log = ENABLE_SIS_5600_LOG;
static void
sis_5600_log(const char *fmt, ...)
{
va_list ap;
if (sis_5600_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5600_log(fmt, ...)
#endif
typedef struct sis_5600_t {
uint8_t nb_slot;
uint8_t sb_slot;
void *h2p;
void *p2i;
void *ide;
void *usb;
void *pmu;
sis_55xx_common_t *sis;
} sis_5600_t;
static void
sis_5600_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
sis_5600_log("SiS 5600: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5600_host_to_pci_write(addr, val, dev->h2p);
else if (func == 0x01)
sis_5513_ide_write(addr, val, dev->ide);
}
static uint8_t
sis_5600_read(int func, int addr, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5600_host_to_pci_read(addr, dev->h2p);
else if (func == 0x01)
ret = sis_5513_ide_read(addr, dev->ide);
sis_5600_log("SiS 5600: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
sis_5600_log("SiS 5595: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (func) {
case 0x00:
sis_5513_pci_to_isa_write(addr, val, dev->p2i);
break;
case 0x01:
sis_5595_pmu_write(addr, val, dev->pmu);
break;
case 0x02:
sis_5572_usb_write(addr, val, dev->usb);
break;
}
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
{
const sis_5600_t *dev = (sis_5600_t *) priv;
uint8_t ret = 0xff;
switch (func) {
case 0x00:
ret = sis_5513_pci_to_isa_read(addr, dev->p2i);
break;
case 0x01:
ret = sis_5595_pmu_read(addr, dev->pmu);
break;
case 0x02:
ret = sis_5572_usb_read(addr, dev->usb);
break;
}
sis_5600_log("SiS 5602: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5600_close(void *priv)
{
sis_5600_t *dev = (sis_5600_t *) priv;
free(dev);
}
static void *
sis_5600_init(UNUSED(const device_t *info))
{
sis_5600_t *dev = (sis_5600_t *) calloc(1, sizeof(sis_5600_t));
/* Device 0: SiS 5600 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5600_read, sis_5600_write, dev, &dev->nb_slot);
/* Device 1: SiS 5595 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5595_read, sis_5595_write, dev, &dev->sb_slot);
dev->sis = device_add(&sis_55xx_common_device);
dev->ide = device_add_linked(&sis_5591_5600_ide_device, dev->sis);
if (info->local)
dev->p2i = device_add_linked(&sis_5595_1997_p2i_device, dev->sis);
else
dev->p2i = device_add_linked(&sis_5595_p2i_device, dev->sis);
dev->h2p = device_add_linked(&sis_5600_h2p_device, dev->sis);
dev->usb = device_add_linked(&sis_5595_usb_device, dev->sis);
if (info->local)
dev->pmu = device_add_linked(&sis_5595_1997_pmu_device, dev->sis);
else
dev->pmu = device_add_linked(&sis_5595_pmu_device, dev->sis);
return dev;
}
const device_t sis_5600_1997_device = {
.name = "SiS (5)600 (1997)",
.internal_name = "sis_5600_1997",
.flags = DEVICE_PCI,
.local = 1,
.init = sis_5600_init,
.close = sis_5600_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5600_device = {
.name = "SiS (5)600",
.internal_name = "sis_5600",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5600_init,
.close = sis_5600_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5600.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,743 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the STMicroelectronics STPC series of SoCs.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/usb.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/serial.h>
#include <86box/lpt.h>
#include <86box/chipset.h>
#define STPC_CONSUMER2 0x104a020b
#define STPC_ATLAS 0x104a0210
#define STPC_ELITE 0x104a021a
#define STPC_CLIENT 0x100e55cc
typedef struct stpc_t {
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t ide_slot;
uint8_t usb_slot;
uint32_t local;
/* Main registers (port 22h/23h) */
uint8_t reg_offset;
uint8_t regs[256];
/* Host bus interface */
uint16_t host_base;
uint8_t host_offset;
uint8_t usb_irq_state;
uint8_t host_regs[256];
/* Local bus */
uint16_t localbus_base;
uint8_t localbus_offset;
uint8_t pad0;
uint8_t localbus_regs[256];
/* PCI devices */
uint8_t pci_conf[4][256];
smram_t *smram;
usb_t *usb;
sff8038i_t *bm[2];
} stpc_t;
typedef struct stpc_serial_t {
serial_t *uart[2];
} stpc_serial_t;
typedef struct stpc_lpt_t {
uint8_t unlocked;
uint8_t offset;
uint8_t reg1;
uint8_t reg4;
} stpc_lpt_t;
#ifdef ENABLE_STPC_LOG
int stpc_do_log = ENABLE_STPC_LOG;
static void
stpc_log(const char *fmt, ...)
{
va_list ap;
if (stpc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define stpc_log(fmt, ...)
#endif
static void
stpc_recalcmapping(stpc_t *dev)
{
uint32_t base;
uint32_t size;
int state;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t reg = 0; reg <= 3; reg++) {
for (uint8_t bitpair = 0; bitpair <= ((reg == 3) ? 0 : 3); bitpair++) {
if (reg == 3) {
size = 0x10000;
base = 0xf0000;
} else {
size = 0x4000;
base = 0xc0000 + (size * ((reg * 4) + bitpair));
}
stpc_log("STPC: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
state = 0;
if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
stpc_log(" w on");
state |= MEM_WRITE_INTERNAL;
if (base >= 0xe0000)
shadowbios_write |= 1;
} else {
stpc_log(" w off");
state |= MEM_WRITE_EXTANY;
}
if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) {
stpc_log("; r on\n");
state |= MEM_READ_INTERNAL;
if (base >= 0xe0000)
shadowbios |= 1;
} else {
stpc_log("; r off\n");
state |= MEM_READ_EXTANY;
}
mem_set_mem_state(base, size, state);
}
}
flushmmucache_nopc();
}
static void
stpc_host_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: host_write(%04X, %02X)\n", addr, val);
if (addr == dev->host_base)
dev->host_offset = val;
else if (addr == (dev->host_base + 4))
dev->host_regs[dev->host_offset] = val;
}
static uint8_t
stpc_host_read(uint16_t addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->host_base)
ret = dev->host_offset;
else if (addr == (dev->host_base + 4))
ret = dev->host_regs[dev->host_offset];
else
ret = 0xff;
stpc_log("STPC: host_read(%04X) = %02X\n", addr, ret);
return ret;
}
static void
stpc_localbus_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: localbus_write(%04X, %02X)\n", addr, val);
if (addr == dev->localbus_base)
dev->localbus_offset = val;
else if (addr == (dev->localbus_base + 4))
dev->localbus_regs[addr] = val;
}
static uint8_t
stpc_localbus_read(uint16_t addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == dev->localbus_base)
ret = dev->localbus_offset;
else if (addr == (dev->localbus_base + 4))
ret = dev->localbus_regs[dev->localbus_offset];
else
ret = 0xff;
stpc_log("STPC: localbus_read(%04X) = %02X\n", addr, ret);
return ret;
}
static void
stpc_nb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: nb_write(%d, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0e:
case 0x51:
case 0x53:
case 0x54:
return;
case 0x05:
val &= 0x01;
break;
case 0x50:
val &= 0x1f;
break;
case 0x52:
val &= 0x70;
break;
default:
break;
}
dev->pci_conf[0][addr] = val;
}
static uint8_t
stpc_nb_read(int func, int addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[0][addr];
stpc_log("STPC: nb_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
stpc_ide_handlers(stpc_t *dev, int bus)
{
uint16_t main;
uint16_t side;
if (bus & 0x01) {
ide_pri_disable();
if (dev->pci_conf[2][0x09] & 0x01) {
main = (dev->pci_conf[2][0x11] << 8) | (dev->pci_conf[2][0x10] & 0xf8);
side = ((dev->pci_conf[2][0x15] << 8) | (dev->pci_conf[2][0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
stpc_log("STPC: IDE primary main %04X side %04X enable ", main, side);
if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x04)) {
stpc_log("1\n");
ide_pri_enable();
} else {
stpc_log("0\n");
}
}
if (bus & 0x02) {
ide_sec_disable();
if (dev->pci_conf[2][0x09] & 0x04) {
main = (dev->pci_conf[2][0x19] << 8) | (dev->pci_conf[2][0x18] & 0xf8);
side = ((dev->pci_conf[2][0x1d] << 8) | (dev->pci_conf[2][0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
stpc_log("STPC: IDE secondary main %04X side %04X enable ", main, side);
if ((dev->pci_conf[2][0x04] & 0x01) && !(dev->pci_conf[2][0x48] & 0x08)) {
stpc_log("1\n");
ide_sec_enable();
} else {
stpc_log("0\n");
}
}
}
static void
stpc_ide_bm_handlers(stpc_t *dev)
{
uint16_t base = (dev->pci_conf[2][0x20] & 0xf0) | (dev->pci_conf[2][0x21] << 8);
sff_bus_master_handler(dev->bm[0], dev->pci_conf[2][0x04] & 1, base);
sff_bus_master_handler(dev->bm[1], dev->pci_conf[2][0x04] & 1, base + 8);
}
static void
stpc_ide_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: ide_write(%d, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x04:
dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0xbe) | (val & 0x41);
stpc_ide_handlers(dev, 0x03);
stpc_ide_bm_handlers(dev);
break;
case 0x05:
dev->pci_conf[2][addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[2][addr] &= ~(val & 0x70);
break;
case 0x09:
dev->pci_conf[2][addr] = (dev->pci_conf[2][addr] & 0x8a) | (val & 0x05);
stpc_ide_handlers(dev, 0x03);
break;
case 0x10:
dev->pci_conf[2][addr] = (val & 0xf8) | 1;
stpc_ide_handlers(dev, 0x01);
break;
case 0x11:
dev->pci_conf[2][addr] = val;
stpc_ide_handlers(dev, 0x01);
break;
case 0x14:
dev->pci_conf[2][addr] = (val & 0xfc) | 1;
stpc_ide_handlers(dev, 0x01);
break;
case 0x15:
dev->pci_conf[2][addr] = val;
stpc_ide_handlers(dev, 0x01);
break;
case 0x18:
dev->pci_conf[2][addr] = (val & 0xf8) | 1;
stpc_ide_handlers(dev, 0x02);
break;
case 0x19:
dev->pci_conf[2][addr] = val;
stpc_ide_handlers(dev, 0x02);
break;
case 0x1c:
dev->pci_conf[2][addr] = (val & 0xfc) | 1;
stpc_ide_handlers(dev, 0x02);
break;
case 0x1d:
dev->pci_conf[2][addr] = val;
stpc_ide_handlers(dev, 0x02);
break;
case 0x20:
dev->pci_conf[2][0x20] = (val & 0xf0) | 1;
stpc_ide_bm_handlers(dev);
break;
case 0x21:
dev->pci_conf[2][0x21] = val;
stpc_ide_bm_handlers(dev);
break;
case 0x3c:
dev->pci_conf[2][addr] = val;
break;
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
dev->pci_conf[2][addr] = val;
break;
case 0x48:
dev->pci_conf[2][addr] = (val & 0x8c) & ~(val & 0x03);
stpc_ide_handlers(dev, 0x03);
if (val & 0x02) {
sff_bus_master_set_irq(0x01, dev->bm[0]);
sff_bus_master_set_irq(0x01, dev->bm[1]);
}
if (val & 0x01) {
sff_bus_master_set_irq(0x00, dev->bm[0]);
sff_bus_master_set_irq(0x00, dev->bm[1]);
}
break;
default:
break;
}
}
static uint8_t
stpc_ide_read(int func, int addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else {
ret = dev->pci_conf[2][addr];
if (addr == 0x48) {
ret &= 0xfc;
ret |= !!(dev->bm[0]->status & 0x04);
ret |= (!!(dev->bm[1]->status & 0x04)) << 1;
}
}
stpc_log("STPC: ide_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
stpc_isab_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
if ((func == 1) && (dev->local != STPC_ATLAS)) {
stpc_ide_write(0, addr, val, priv);
return;
}
stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0e:
return;
case 0x05:
val &= 0x01;
break;
default:
break;
}
dev->pci_conf[1][addr] = val;
}
static uint8_t
stpc_isab_read(int func, int addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if ((func == 1) && (dev->local != STPC_ATLAS))
ret = stpc_ide_read(0, addr, priv);
else if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[1][addr];
stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
stpc_usb_write(int func, int addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: usb_write(%d, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0e:
case 0x10:
return;
case 0x05:
val &= 0x01;
break;
case 0x11:
dev->pci_conf[3][addr] = val & 0xf0;
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
break;
case 0x12:
case 0x13:
dev->pci_conf[3][addr] = val;
ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
break;
default:
break;
}
dev->pci_conf[3][addr] = val;
}
static uint8_t
stpc_usb_read(int func, int addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (func > 0)
ret = 0xff;
else
ret = dev->pci_conf[3][addr];
stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
stpc_remap_host(stpc_t *dev, uint16_t host_base)
{
stpc_log("STPC: Remapping host bus from %04X to %04X\n", dev->host_base, host_base);
io_removehandler(dev->host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
if (host_base) {
io_sethandler(host_base, 5,
stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev);
}
dev->host_base = host_base;
}
static void
stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base)
{
stpc_log("STPC: Remapping local bus from %04X to %04X\n", dev->localbus_base, localbus_base);
io_removehandler(dev->localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
if (localbus_base) {
io_sethandler(localbus_base, 5,
stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev);
}
dev->localbus_base = localbus_base;
}
static uint8_t
stpc_serial_handlers(uint8_t val)
{
const stpc_serial_t *dev = device_get_priv(&stpc_serial_device);
if (!dev) {
stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
return 0;
}
uint16_t uart0_io = 0x3f8;
uint16_t uart1_io = 0x3f8;
uint8_t uart0_irq = 4;
uint8_t uart1_irq = 3;
if (val & 0x10)
uart1_io &= 0xfeff;
if (val & 0x20)
uart1_io &= 0xffef;
if (val & 0x40)
uart0_io &= 0xfeff;
if (val & 0x80)
uart0_io &= 0xffef;
if (uart0_io == uart1_io) {
/* Apply defaults if both UARTs are set to the same address. */
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
uart0_io = 0x3f8;
uart1_io = 0x2f8;
}
if (!(uart0_io & 0x100)) {
/* The address for UART0 establishes the IRQs for both ports. */
uart0_irq = 3;
uart1_irq = 4;
}
stpc_log("STPC: Remapping UART0 to %04X %d and UART1 to %04X %d (raw %02X)\n", uart0_io, uart0_irq, uart1_io, uart1_irq, val);
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], uart0_io, uart0_irq);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], uart1_io, uart1_irq);
return 1;
}
static void
stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: reg_write(%04X, %02X)\n", addr, val);
if (addr == 0x22) {
dev->reg_offset = val;
} else {
stpc_log("STPC: regs[%02X] = %02X\n", dev->reg_offset, val);
switch (dev->reg_offset) {
case 0x12:
if (dev->regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0xff00) | val);
else if (dev->regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val);
break;
case 0x13:
if (dev->regs[0x10] == 0x07)
stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8));
else if (dev->regs[0x10] == 0x06)
stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8));
break;
case 0x21:
val &= 0xfe;
break;
case 0x22:
val &= 0x7f;
break;
case 0x25:
case 0x26:
case 0x27:
case 0x28:
if (dev->reg_offset == 0x28) {
val &= 0xe3;
smram_state_change(dev->smram, 0, !!(val & 0x80));
}
dev->regs[dev->reg_offset] = val;
stpc_recalcmapping(dev);
break;
case 0x29:
val &= 0x0f;
break;
case 0x36:
val &= 0x3f;
break;
case 0x52:
case 0x53:
case 0x54:
case 0x55:
stpc_log("STPC: Set IRQ routing: INT %c -> %d\n", 0x41 + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : -1);
val &= 0x8f;
pci_set_irq_routing(PCI_INTA + ((dev->reg_offset - 2) & 0x03), (val & 0x80) ? (val & 0xf) : PCI_IRQ_DISABLED);
break;
case 0x56:
case 0x57:
pic_elcr_write(dev->reg_offset, val, (dev->reg_offset & 1) ? &pic2 : &pic);
if (dev->reg_offset == 0x57)
refresh_at_enable = (val & 0x01);
break;
case 0x59:
val &= 0xf1;
stpc_serial_handlers(val);
break;
default:
break;
}
dev->regs[dev->reg_offset] = val;
}
}
static uint8_t
stpc_reg_read(uint16_t addr, void *priv)
{
const stpc_t *dev = (stpc_t *) priv;
uint8_t ret;
if (addr == 0x22)
ret = dev->reg_offset;
else if (dev->reg_offset >= 0xc0)
return 0xff; /* let the CPU code handle Cyrix CPU registers */
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
/* ELCR registers. */
ret = pic_elcr_read(dev->reg_offset, (dev->reg_offset & 1) ? &pic2 : &pic);
if (dev->reg_offset == 0x57)
ret |= (dev->regs[dev->reg_offset] & 0x01);
} else
ret = dev->regs[dev->reg_offset];
stpc_log("STPC: reg_read(%04X) = %02X\n", dev->reg_offset, ret);
return ret;
}
static void
stpc_reset(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: reset()\n");
memset(dev->regs, 0, sizeof(dev->regs));
dev->regs[0x7b] = 0xff;
if (device_get_priv(&stpc_lpt_device))
dev->regs[0x4c] |= 0x80; /* LPT strap */
if (stpc_serial_handlers(0x00))
dev->regs[0x4c] |= 0x03; /* UART straps */
}
static void
stpc_setup(stpc_t *dev)
{
stpc_log("STPC: setup()\n");
/* Main register interface */
io_sethandler(0x22, 2,
stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev);
/* Northbridge */
if (dev->local & STPC_CLIENT) {
dev->pci_conf[0][0x00] = 0x0e;
dev->pci_conf[0][0x01] = 0x10;
dev->pci_conf[0][0x02] = 0x64;
dev->pci_conf[0][0x03] = 0x05;
} else {
dev->pci_conf[0][0x00] = 0x4a;
dev->pci_conf[0][0x01] = 0x10;
dev->pci_conf[0][0x02] = 0x0a;
dev->pci_conf[0][0x03] = 0x02;
}
dev->pci_conf[0][0x04] = 0x07;
dev->pci_conf[0][0x06] = 0x80;
dev->pci_conf[0][0x07] = 0x02;
dev->pci_conf[0][0x0b] = 0x06;
/* ISA Bridge */
dev->pci_conf[1][0x00] = dev->local >> 16;
dev->pci_conf[1][0x01] = dev->local >> 24;
dev->pci_conf[1][0x02] = dev->local;
dev->pci_conf[1][0x03] = dev->local >> 8;
dev->pci_conf[1][0x04] = 0x0f;
dev->pci_conf[1][0x06] = 0x80;
dev->pci_conf[1][0x07] = 0x02;
dev->pci_conf[1][0x0a] = 0x01;
dev->pci_conf[1][0x0b] = 0x06;
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
dev->pci_conf[1][0x0e] = /*0x40*/ 0x80;
/* IDE */
dev->pci_conf[2][0x00] = dev->local >> 16;
dev->pci_conf[2][0x01] = dev->local >> 24;
if (dev->local == STPC_ATLAS) {
dev->pci_conf[2][0x02] = 0x28;
dev->pci_conf[2][0x03] = 0x02;
} else {
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
}
dev->pci_conf[2][0x06] = 0x80;
dev->pci_conf[2][0x07] = 0x02;
dev->pci_conf[2][0x09] = 0x8a;
dev->pci_conf[2][0x0a] = 0x01;
dev->pci_conf[2][0x0b] = 0x01;
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
dev->pci_conf[2][0x0e] = /*0x40*/ 0x80;
dev->pci_conf[2][0x10] = 0x01;
dev->pci_conf[2][0x14] = 0x01;
dev->pci_conf[2][0x18] = 0x01;
dev->pci_conf[2][0x1c] = 0x01;
dev->pci_conf[2][0x20] = 0x01;
dev->pci_conf[2][0x40] = 0x60;
dev->pci_conf[2][0x41] = 0x97;
dev->pci_conf[2][0x42] = 0x60;
dev->pci_conf[2][0x43] = 0x97;
dev->pci_conf[2][0x44] = 0x60;
dev->pci_conf[2][0x45] = 0x97;
dev->pci_conf[2][0x46] = 0x60;
dev->pci_conf[2][0x47] = 0x97;
/* USB */
if (dev->usb) {
dev->pci_conf[3][0x00] = dev->local >> 16;
dev->pci_conf[3][0x01] = dev->local >> 24;
dev->pci_conf[3][0x02] = 0x30;
dev->pci_conf[3][0x03] = 0x02;
dev->pci_conf[3][0x06] = 0x80;
dev->pci_conf[3][0x07] = 0x02;
dev->pci_conf[3][0x09] = 0x10;
dev->pci_conf[3][0x0a] = 0x03;
dev->pci_conf[3][0x0b] = 0x0c;
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
indicates as well), and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
}
/* PCI setup */
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
}
static void
stpc_close(void *priv)
{
stpc_t *dev = (stpc_t *) priv;
stpc_log("STPC: close()\n");
smram_del(dev->smram);
free(dev);
}
static void *
stpc_init(const device_t *info)
{
stpc_log("STPC: init()\n");
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
memset(dev, 0, sizeof(stpc_t));
dev->local = info->local;
pci_add_card(PCI_ADD_NORTHBRIDGE, stpc_nb_read, stpc_nb_write, dev, &dev->nb_slot);
pci_add_card(PCI_ADD_SOUTHBRIDGE, stpc_isab_read, stpc_isab_write, dev, &dev->sb_slot);
if (dev->local == STPC_ATLAS) {
pci_add_card(PCI_ADD_SOUTHBRIDGE_IDE, stpc_ide_read, stpc_ide_write, dev, &dev->ide_slot);
dev->usb = device_add(&usb_device);
pci_add_card(PCI_ADD_SOUTHBRIDGE_USB, stpc_usb_read, stpc_usb_write, dev, &dev->usb_slot);
}
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
stpc_setup(dev);
stpc_reset(dev);
dev->smram = smram_add();
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x00020000, 0, 1);
device_add(&port_92_pci_device);
pic_elcr_io_handler(0);
refresh_at_enable = 0;
return dev;
}
static void
stpc_serial_close(void *priv)
{
stpc_serial_t *dev = (stpc_serial_t *) priv;
stpc_log("STPC: serial_close()\n");
free(dev);
}
static void *
stpc_serial_init(UNUSED(const device_t *info))
{
stpc_log("STPC: serial_init()\n");
stpc_serial_t *dev = (stpc_serial_t *) malloc(sizeof(stpc_serial_t));
memset(dev, 0, sizeof(stpc_serial_t));
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
/* Initialization is performed by stpc_reset */
return dev;
}
static void
stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
{
uint8_t old_addr = (dev->reg1 & 0x03);
uint8_t new_addr = (val & 0x03);
switch (old_addr) {
case 0x1:
lpt3_remove();
break;
case 0x2:
lpt1_remove();
break;
case 0x3:
lpt2_remove();
break;
default:
break;
}
switch (new_addr) {
case 0x1:
stpc_log("STPC: Remapping parallel port to LPT3\n");
lpt3_init(0x3bc);
break;
case 0x2:
stpc_log("STPC: Remapping parallel port to LPT1\n");
lpt1_init(0x378);
break;
case 0x3:
stpc_log("STPC: Remapping parallel port to LPT2\n");
lpt2_init(0x278);
break;
default:
stpc_log("STPC: Disabling parallel port\n");
break;
}
dev->reg1 = (val & 0x08);
dev->reg1 |= new_addr;
dev->reg1 |= 0x84; /* reserved bits that default to 1; hardwired? */
}
static void
stpc_lpt_write(uint16_t addr, uint8_t val, void *priv)
{
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
if (dev->unlocked < 2) {
/* Cheat a little bit: in reality, any write to any
I/O port is supposed to reset the unlock counter. */
if ((addr == 0x3f0) && (val == 0x55))
dev->unlocked++;
else
dev->unlocked = 0;
} else if (addr == 0x3f0) {
if (val == 0xaa)
dev->unlocked = 0;
else
dev->offset = val;
} else if (dev->offset == 1) {
/* dev->reg1 is set by stpc_lpt_handlers */
stpc_lpt_handlers(dev, val);
} else if (dev->offset == 4) {
dev->reg4 = (val & 0x03);
}
}
static void
stpc_lpt_reset(void *priv)
{
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
stpc_log("STPC: lpt_reset()\n");
dev->unlocked = 0;
dev->offset = 0x00;
dev->reg1 = 0x9f;
dev->reg4 = 0x00;
stpc_lpt_handlers(dev, dev->reg1);
}
static void
stpc_lpt_close(void *priv)
{
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
stpc_log("STPC: lpt_close()\n");
free(dev);
}
static void *
stpc_lpt_init(UNUSED(const device_t *info))
{
stpc_log("STPC: lpt_init()\n");
stpc_lpt_t *dev = (stpc_lpt_t *) malloc(sizeof(stpc_lpt_t));
memset(dev, 0, sizeof(stpc_lpt_t));
stpc_lpt_reset(dev);
io_sethandler(0x3f0, 2,
NULL, NULL, NULL, stpc_lpt_write, NULL, NULL, dev);
return dev;
}
/* STPC SoCs */
const device_t stpc_client_device = {
.name = "STPC Client",
.internal_name = "stpc_client",
.flags = DEVICE_PCI,
.local = STPC_CLIENT,
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stpc_consumer2_device = {
.name = "STPC Consumer-II",
.internal_name = "stpc_consumer2",
.flags = DEVICE_PCI,
.local = STPC_CONSUMER2,
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stpc_elite_device = {
.name = "STPC Elite",
.internal_name = "stpc_elite",
.flags = DEVICE_PCI,
.local = STPC_ELITE,
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stpc_atlas_device = {
.name = "STPC Atlas",
.internal_name = "stpc_atlas",
.flags = DEVICE_PCI,
.local = STPC_ATLAS,
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/* Auxiliary devices */
const device_t stpc_serial_device = {
.name = "STPC Serial UARTs",
.internal_name = "stpc_serial",
.flags = 0,
.local = 0,
.init = stpc_serial_init,
.close = stpc_serial_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stpc_lpt_device = {
.name = "STPC Parallel Port",
.internal_name = "stpc_lpt",
.flags = 0,
.local = 0,
.init = stpc_lpt_init,
.close = stpc_lpt_close,
.reset = stpc_lpt_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/stpc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,029 |
```c
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct rabbit_t {
uint8_t cur_reg;
uint8_t tries;
uint8_t regs[258];
} rabbit_t;
static void
rabbit_recalcmapping(rabbit_t *dev)
{
uint32_t shread;
uint32_t shwrite;
uint32_t shflags = 0;
shread = !!(dev->regs[0x101] & 0x40);
shwrite = !!(dev->regs[0x100] & 0x02);
shflags = shread ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= shwrite ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shadowbios = !!shread;
shadowbios_write = !!shwrite;
#ifdef USE_SHADOW_C0000
mem_set_mem_state(0x000c0000, 0x00040000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
#else
mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
#endif
switch (dev->regs[0x100] & 0x09) {
case 0x01:
/* The one BIOS we use seems to use something else to control C0000-DFFFF shadow,
no idea what. */
#ifdef USE_SHADOW_C0000
/* 64K at 0C0000-0CFFFF */
mem_set_mem_state(0x000c0000, 0x00010000, shflags);
/* FALLTHROUGH */
#endif
case 0x00:
/* 64K at 0F0000-0FFFFF */
mem_set_mem_state(0x000f0000, 0x00010000, shflags);
break;
case 0x09:
#ifdef USE_SHADOW_C0000
/* 128K at 0C0000-0DFFFF */
mem_set_mem_state(0x000c0000, 0x00020000, shflags);
/* FALLTHROUGH */
#endif
case 0x08:
/* 128K at 0E0000-0FFFFF */
mem_set_mem_state(0x000e0000, 0x00020000, shflags);
break;
default:
break;
}
flushmmucache();
}
static void
rabbit_write(uint16_t addr, uint8_t val, void *priv)
{
rabbit_t *dev = (rabbit_t *) priv;
switch (addr) {
case 0x22:
dev->cur_reg = val;
dev->tries = 0;
break;
case 0x23:
if (dev->cur_reg == 0x83) {
if (dev->tries < 0x02) {
dev->regs[dev->tries++ | 0x100] = val;
if (dev->tries == 0x02)
rabbit_recalcmapping(dev);
}
} else
dev->regs[dev->cur_reg] = val;
break;
default:
break;
}
}
static uint8_t
rabbit_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
rabbit_t *dev = (rabbit_t *) priv;
switch (addr) {
case 0x23:
if (dev->cur_reg == 0x83) {
if (dev->tries < 0x02)
ret = dev->regs[dev->tries++ | 0x100];
} else
ret = dev->regs[dev->cur_reg];
break;
default:
break;
}
return ret;
}
static void
rabbit_close(void *priv)
{
rabbit_t *dev = (rabbit_t *) priv;
free(dev);
}
static void *
rabbit_init(UNUSED(const device_t *info))
{
rabbit_t *dev = (rabbit_t *) malloc(sizeof(rabbit_t));
memset(dev, 0, sizeof(rabbit_t));
io_sethandler(0x0022, 0x0002, rabbit_read, NULL, NULL, rabbit_write, NULL, NULL, dev);
return dev;
}
const device_t rabbit_device = {
.name = "SiS Rabbit",
.internal_name = "rabbit",
.flags = 0,
.local = 0,
.init = rabbit_init,
.close = rabbit_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_85c310.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,099 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C822 VESA Local Bus to PCI
* Bridge Interface.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/spd.h>
typedef struct opti822_t {
uint8_t irq_convert;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_regs[256];
} opti822_t;
// #define ENABLE_OPTI822_LOG 1
#ifdef ENABLE_OPTI822_LOG
int opti822_do_log = ENABLE_OPTI822_LOG;
static void
opti822_log(const char *fmt, ...)
{
va_list ap;
if (opti822_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti822_log(fmt, ...)
#endif
/* NOTE: We currently cheat and pass all PCI shadow RAM accesses to ISA as well.
This is because we currently do not have separate access mappings for
PCI and ISA at all. */
static void
opti822_recalc(opti822_t *dev)
{
int reg;
int bit_r;
int bit_w;
int state;
uint32_t base;
for (uint8_t i = 0; i < 12; i++) {
base = 0x000c0000 + (i << 14);
reg = 0x44 + ((i >> 2) ^ 3);
bit_w = (i & 3);
bit_r = bit_w + 4;
bit_w = 1 << bit_w;
bit_r = 1 << bit_r;
state = (dev->pci_regs[reg] & bit_w) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
state |= (dev->pci_regs[reg] & bit_r) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
mem_set_mem_state_bus_both(base, 0x00004000, state);
}
state = (dev->pci_regs[0x44] & 0x01) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
state |= (dev->pci_regs[0x44] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
mem_set_mem_state_bus_both(0x000f0000, 0x00010000, state);
}
/* NOTE: We cheat here. The real ALi M1435 uses a level to edge triggered IRQ converter
when the most siginificant bit is set. We work around that by manipulating the
emulated PIC's ELCR register. */
static void
opti822_update_irqs(opti822_t *dev, int set)
{
uint8_t val;
int reg;
int shift;
int irq;
int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
pic_t *temp_pic;
#if 0
dev->irq_convert = (dev->pci_regs[0x53] & 0x08);
#endif
dev->irq_convert = 1;
for (uint8_t i = 0; i < 16; i++) {
reg = 0x88 + (i >> 1);
shift = (i & 1) << 2;
val = (dev->pci_regs[reg] >> shift) & 0x0f;
irq = irq_map[val & 0x07];
if (irq == -1)
continue;
temp_pic = (irq >= 8) ? &pic2 : &pic;
irq &= 7;
if (dev->irq_convert && set && (val & 0x08))
temp_pic->elcr |= (1 << irq);
else
temp_pic->elcr &= ~(1 << irq);
}
}
static void
opti822_pci_write(int func, int addr, uint8_t val, void *priv)
{
opti822_t *dev = (opti822_t *) priv;
int irq;
int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
int pin;
int slot;
opti822_log("opti822_write(%02X, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
switch (addr) {
/* Command Register */
case 0x04:
dev->pci_regs[addr] = (val & 0x40) | 0x07;
break;
/* Status Register */
case 0x06:
if (!(dev->pci_regs[0x52] & 0x04))
dev->pci_regs[addr] = (val & 0x80);
break;
case 0x07:
dev->pci_regs[addr] &= ~(val & 0xf9);
break;
/* Master Latency Timer Register */
case 0x0d:
dev->pci_regs[addr] = val;
break;
case 0x40:
dev->pci_regs[addr] = (val & 0xc0) | 0x01;
break;
case 0x41:
/* TODO: Bit 15th enable the PCI Bridge when 1. */
dev->pci_regs[addr] = val & 0xcf;
break;
case 0x42:
dev->pci_regs[addr] = val & 0xf8;
break;
case 0x43:
dev->pci_regs[addr] = val;
break;
case 0x44:
dev->pci_regs[addr] = val & 0xcb;
opti822_recalc(dev);
break;
case 0x45 ... 0x47:
dev->pci_regs[addr] = val;
opti822_recalc(dev);
break;
/* Memory hole stuff. */
case 0x48 ... 0x51:
dev->pci_regs[addr] = val;
break;
case 0x52:
dev->pci_regs[addr] = val;
break;
case 0x53:
dev->pci_regs[addr] = val;
opti822_update_irqs(dev, 0);
opti822_update_irqs(dev, 1);
break;
case 0x54 ... 0x57:
dev->pci_regs[addr] = val;
break;
case 0x58:
dev->pci_regs[addr] = val & 0xfc;
break;
case 0x59 ... 0x5b:
dev->pci_regs[addr] = val;
break;
case 0x5c ... 0x5f:
dev->pci_regs[addr] = val;
break;
case 0x60:
dev->pci_regs[addr] = val & 0xfc;
break;
case 0x61 ... 0x63:
dev->pci_regs[addr] = val;
break;
case 0x64 ... 0x67:
dev->pci_regs[addr] = val;
break;
case 0x68:
dev->pci_regs[addr] = val & 0xfc;
break;
case 0x69 ... 0x6b:
dev->pci_regs[addr] = val;
break;
case 0x6c ... 0x6f:
dev->pci_regs[addr] = val;
break;
case 0x70:
dev->pci_regs[addr] = val & 0xfc;
break;
case 0x71 ... 0x73:
dev->pci_regs[addr] = val;
break;
case 0x74:
dev->pci_regs[addr] = val & 0xf8;
break;
/* ROMCS# and NVMCS# stuff. */
case 0x75:
dev->pci_regs[addr] = val;
break;
case 0x76:
dev->pci_regs[addr] = val;
break;
case 0x77:
dev->pci_regs[addr] = val;
break;
/* Enabling of memory blocks at ISA bus. */
case 0x78:
dev->pci_regs[addr] = val;
break;
case 0x79:
dev->pci_regs[addr] = val & 0xfc;
break;
case 0x7a:
dev->pci_regs[addr] = val;
break;
case 0x7b ... 0x7c:
dev->pci_regs[addr] = val;
break;
case 0x7d ... 0x7e:
dev->pci_regs[addr] = val;
break;
case 0x7f:
dev->pci_regs[addr] = val & 0x03;
break;
case 0x80 ... 0x81:
dev->pci_regs[addr] = val;
break;
case 0x82:
dev->pci_regs[addr] = val;
break;
case 0x84 ... 0x85:
dev->pci_regs[addr] = val;
break;
case 0x86:
dev->pci_regs[addr] = val;
break;
case 0x88 ... 0x8f:
dev->pci_regs[addr] = val;
opti822_update_irqs(dev, 0);
irq = irq_map[val & 0x07];
pin = 4 - ((addr & 0x01) << 1);
slot = ((addr & 0x06) >> 1);
if (irq >= 0) {
opti822_log("Set IRQ routing: INT %c%c -> %02X\n", pin + 0x40, slot + 0x31, irq);
pci_set_irq_routing(pin + (slot << 2), irq);
pci_set_irq_level(pin + (slot << 2), !!(val & 0x07));
} else {
opti822_log("Set IRQ routing: INT %c%c -> FF\n", pin + 0x40, slot + 0x31);
pci_set_irq_routing(pin + (slot << 2), PCI_IRQ_DISABLED);
}
irq = irq_map[(val >> 4) & 0x07];
pin = 3 - ((addr & 0x01) << 1);
slot = ((addr & 0x06) >> 1);
if (irq >= 0) {
opti822_log("Set IRQ routing: INT %c%c -> %02X\n", pin + 0x40, slot + 0x31, irq);
pci_set_irq_routing(pin + (slot << 2), irq);
pci_set_irq_level(pin + (slot << 2), !!((val >> 4) & 0x07));
} else {
opti822_log("Set IRQ routing: INT %c%c -> FF\n", pin + 0x40, slot + 0x31);
pci_set_irq_routing(pin + (slot << 2), PCI_IRQ_DISABLED);
}
opti822_update_irqs(dev, 1);
break;
default:
break;
}
}
static uint8_t
opti822_pci_read(int func, int addr, void *priv)
{
const opti822_t *dev = (opti822_t *) priv;
uint8_t ret;
ret = 0xff;
if (func == 0)
ret = dev->pci_regs[addr];
opti822_log("opti822_read(%02X, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
opti822_reset(void *priv)
{
opti822_t *dev = (opti822_t *) priv;
memset(dev->pci_regs, 0, 256);
dev->pci_regs[0x00] = 0x45;
dev->pci_regs[0x01] = 0x10; /*OPTi*/
dev->pci_regs[0x02] = 0x22;
dev->pci_regs[0x03] = 0xc8; /*82C822 PCIB*/
dev->pci_regs[0x04] = 0x07;
dev->pci_regs[0x06] = 0x80;
dev->pci_regs[0x07] = 0x02;
dev->pci_regs[0x08] = 0x01;
dev->pci_regs[0x0b] = 0x06;
dev->pci_regs[0x0d] = 0x20;
dev->pci_regs[0x40] = 0x01;
dev->pci_regs[0x41] = 0x0c;
dev->pci_regs[0x43] = 0x02;
dev->pci_regs[0x52] = 0x06;
dev->pci_regs[0x53] = 0x90;
dev->irq_convert = 1 /*0*/;
for (uint8_t i = 0; i < 16; i++)
pci_set_irq_routing(PCI_INTA + i, PCI_IRQ_DISABLED);
}
static void
opti822_close(void *priv)
{
opti822_t *dev = (opti822_t *) priv;
free(dev);
}
static void *
opti822_init(UNUSED(const device_t *info))
{
opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t));
memset(dev, 0, sizeof(opti822_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_pci_read, opti822_pci_write, dev, &dev->pci_slot);
opti822_reset(dev);
return dev;
}
const device_t opti822_device = {
.name = "OPTi 82C822 PCIB",
.internal_name = "opti822",
.flags = DEVICE_PCI,
.local = 0,
.init = opti822_init,
.close = opti822_close,
.reset = opti822_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti822.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,479 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1429 chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
/*
ALi M1429/M1429G Configuration Registers
Notes: Incorporated sometimes with a M1435 PCI-to-VLB Bridge
M1429G is just a 1429 with Green Functionality
SMM in it's entirety needs more research
Warning: Register documentation may be inaccurate!
Register 03h: Write C5h to unlock the configuration registers
Register 10h & 11h: DRAM Bank Configuration
Register 12h:
Bit 2: Memory Remapping Enable (128KB)
Register 13h:
Bit 7: Shadow RAM Enable for F8000-FFFFF
Bit 6: Shadow RAM Enable for F0000-F7FFF
Bit 5: Shadow RAM Enable for E8000-FFFFF
Bit 4: Shadow RAM Enable for E0000-F7FFF
Bit 3: Shadow RAM Enable for D8000-FFFFF
Bit 2: Shadow RAM Enable for D0000-F7FFF
Bit 1: Shadow RAM Enable for C8000-FFFFF
Bit 0: Shadow RAM Enable for C0000-F7FFF
Register 14h:
Bit 1: Shadow RAM Write for Enabled Segments
Bit 0: Shadow RAM Read for Enabled Segments
Register 18h:
Bit 6-5-4 (Cache Size)
0 0 0 32KB
0 0 1 128KB
0 1 0 256KB
0 1 1 512KB
1 0 0 64KB
1 0 1 256KB
1 1 0 512KB
1 1 1 1MB
Bit 1: L2 Cache Enable
Register 20h:
Bits 2-1-0: Bus Clock Speed
0 0 0: 7.1519Mhz (ATCLK2)
0 0 1: CLK2IN/4
0 1 0: CLK2IN/5
0 1 1: CLK2IN/6
1 0 0: CLK2IN/8
1 0 1: CLK2IN/10
1 1 0: CLK2IN/12
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#define GREEN dev->is_g /* Is G Variant */
#ifdef ENABLE_ALI1429_LOG
int ali1429_do_log = ENABLE_ALI1429_LOG;
static void
ali1429_log(const char *fmt, ...)
{
va_list ap;
if (ali1429_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1429_log(fmt, ...)
#endif
typedef struct ali_1429_t {
uint8_t is_g;
uint8_t index;
uint8_t cfg_locked;
uint8_t reg_57h;
uint8_t regs[90];
} ali1429_t;
static void
ali1429_shadow_recalc(ali1429_t *dev)
{
uint32_t base;
uint32_t can_write;
uint32_t can_read;
shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01);
shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02);
can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
for (uint8_t i = 0; i < 8; i++) {
base = 0xc0000 + (i << 15);
if (dev->regs[0x13] & (1 << i))
mem_set_mem_state_both(base, 0x8000, can_read | can_write);
else
mem_set_mem_state_both(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
flushmmucache_nopc();
}
static void
ali1429_write(uint16_t addr, uint8_t val, void *priv)
{
ali1429_t *dev = (ali1429_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
#ifdef ENABLE_ALI1429_LOG
if (dev->index != 0x03)
ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
#endif
if (dev->index == 0x03)
dev->cfg_locked = (val != 0xc5);
if (!dev->cfg_locked) {
ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
/* Common M1429 Registers */
switch (dev->index) {
case 0x10:
case 0x11:
dev->regs[dev->index] = val;
break;
case 0x12:
dev->regs[dev->index] = val;
if (val & 4)
mem_remap_top(128);
else
mem_remap_top(0);
break;
case 0x13:
case 0x14:
dev->regs[dev->index] = val;
ali1429_shadow_recalc(dev);
break;
case 0x15:
case 0x16:
case 0x17:
dev->regs[dev->index] = val;
break;
case 0x18:
dev->regs[dev->index] = (val & 0x8f) | 0x20;
cpu_cache_ext_enabled = !!(val & 2);
cpu_update_waitstates();
break;
case 0x19:
case 0x1a:
case 0x1e:
dev->regs[dev->index] = val;
break;
case 0x20:
dev->regs[dev->index] = val;
switch (val & 7) {
case 0:
case 7: /* Illegal */
cpu_set_isa_speed(7159091);
break;
case 1:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 2:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
case 3:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
case 4:
cpu_set_isa_speed(cpu_busspeed / 8);
break;
case 5:
cpu_set_isa_speed(cpu_busspeed / 10);
break;
case 6:
cpu_set_isa_speed(cpu_busspeed / 12);
break;
default:
break;
}
break;
case 0x21 ... 0x27:
dev->regs[dev->index] = val;
break;
default:
break;
}
/* M1429G Only Registers */
if (GREEN) {
switch (dev->index) {
case 0x30 ... 0x41:
case 0x43:
case 0x45:
case 0x4a:
dev->regs[dev->index] = val;
break;
case 0x57:
dev->reg_57h = val;
break;
default:
break;
}
}
}
break;
default:
break;
}
}
static uint8_t
ali1429_read(uint16_t addr, void *priv)
{
const ali1429_t *dev = (ali1429_t *) priv;
uint8_t ret = 0xff;
if ((addr == 0x23) && (dev->index >= 0x10) && (dev->index <= 0x4a))
ret = dev->regs[dev->index];
else if ((addr == 0x23) && (dev->index == 0x57))
ret = dev->reg_57h;
else if (addr == 0x22)
ret = dev->index;
return ret;
}
static void
ali1429_close(void *priv)
{
ali1429_t *dev = (ali1429_t *) priv;
free(dev);
}
static void
ali1429_defaults(ali1429_t *dev)
{
/* M1429 Defaults */
dev->regs[0x10] = 0xf0;
dev->regs[0x11] = 0xff;
dev->regs[0x12] = 0x10;
dev->regs[0x14] = 0x48;
dev->regs[0x15] = 0x40;
dev->regs[0x17] = 0x7a;
dev->regs[0x1a] = 0x80;
dev->regs[0x22] = 0x80;
dev->regs[0x23] = 0x57;
dev->regs[0x25] = 0xc0;
dev->regs[0x27] = 0x30;
/* M1429G Default Registers */
if (GREEN) {
dev->regs[0x31] = 0x88;
dev->regs[0x32] = 0xc0;
dev->regs[0x38] = 0xe5;
dev->regs[0x40] = 0xe3;
dev->regs[0x41] = 2;
dev->regs[0x45] = 0x80;
}
}
static void *
ali1429_init(const device_t *info)
{
ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t));
memset(dev, 0, sizeof(ali1429_t));
dev->cfg_locked = 1;
GREEN = info->local;
/* M1429 Ports:
22h Index Port
23h Data Port
*/
io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev);
device_add(&port_92_device);
ali1429_defaults(dev);
return dev;
}
const device_t ali1429_device = {
.name = "ALi M1429",
.internal_name = "ali1429",
.flags = 0,
.local = 0,
.init = ali1429_init,
.close = ali1429_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ali1429g_device = {
.name = "ALi M1429G",
.internal_name = "ali1429g",
.flags = 0,
.local = 1,
.init = ali1429_init,
.close = ali1429_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1429.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,847 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C283 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI283_LOG
int opti283_do_log = ENABLE_OPTI283_LOG;
static void
opti283_log(const char *fmt, ...)
{
va_list ap;
if (opti283_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti283_log(fmt, ...)
#endif
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct opti283_t {
uint8_t index;
uint8_t shadow_high;
uint8_t regs[256];
mem_remapping_t mem_remappings[2];
mem_mapping_t mem_mappings[2];
} opti283_t;
static uint8_t
opti283_read_remapped_ram(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_ram((addr - dev->virt) + dev->phys, priv);
}
static uint16_t
opti283_read_remapped_ramw(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_ramw((addr - dev->virt) + dev->phys, priv);
}
static uint32_t
opti283_read_remapped_raml(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_raml((addr - dev->virt) + dev->phys, priv);
}
static void
opti283_write_remapped_ram(uint32_t addr, uint8_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_ram((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti283_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_ramw((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti283_write_remapped_raml(uint32_t addr, uint32_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_raml((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti283_shadow_recalc(opti283_t *dev)
{
uint32_t base;
uint32_t rbase;
uint8_t sh_enable;
uint8_t sh_mode;
uint8_t rom;
uint8_t sh_copy;
shadowbios = shadowbios_write = 0;
dev->shadow_high = 0;
opti283_log("OPTI 283: %02X %02X %02X %02X\n", dev->regs[0x11], dev->regs[0x12], dev->regs[0x13], dev->regs[0x14]);
if (dev->regs[0x11] & 0x80) {
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n");
shadowbios_write = 1;
} else {
shadowbios = 1;
if (dev->regs[0x14] & 0x80) {
mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_INTERNAL\n");
shadowbios_write = 1;
} else {
mem_set_mem_state_both(0xf0000, 0x01000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
opti283_log("OPTI 283: F0000-F0FFF READ_INTERNAL, WRITE_DISABLED\n");
}
mem_set_mem_state_both(0xf1000, 0x0f000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
opti283_log("OPTI 283: F1000-FFFFF READ_INTERNAL, WRITE_DISABLED\n");
}
sh_copy = dev->regs[0x11] & 0x08;
for (uint8_t i = 0; i < 12; i++) {
base = 0xc0000 + (i << 14);
if (i >= 4)
sh_enable = dev->regs[0x12] & (1 << (i - 4));
else
sh_enable = dev->regs[0x13] & (1 << (i + 4));
sh_mode = dev->regs[0x11] & (1 << (i >> 2));
rom = dev->regs[0x11] & (1 << ((i >> 2) + 4));
opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4)));
if (sh_enable && rom) {
if (base >= 0x000e0000)
shadowbios |= 1;
if (base >= 0x000d0000)
dev->shadow_high |= 1;
if (sh_mode) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
} else {
if (base >= 0x000e0000)
shadowbios_write |= 1;
if (sh_copy) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff);
}
}
} else {
if (base >= 0xe0000) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED);
opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED);
opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
}
}
}
rbase = ((uint32_t) (dev->regs[0x13] & 0x0f)) << 20;
if (rbase > 0) {
dev->mem_remappings[0].virt = rbase;
mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000);
if (!dev->shadow_high) {
rbase += 0x00020000;
dev->mem_remappings[1].virt = rbase;
mem_mapping_set_addr(&dev->mem_mappings[1], rbase, 0x00020000);
} else
mem_mapping_disable(&dev->mem_mappings[1]);
} else {
mem_mapping_disable(&dev->mem_mappings[0]);
mem_mapping_disable(&dev->mem_mappings[1]);
}
flushmmucache_nopc();
}
static void
opti283_write(uint16_t addr, uint8_t val, void *priv)
{
opti283_t *dev = (opti283_t *) priv;
switch (addr) {
default:
break;
case 0x22:
dev->index = val;
break;
case 0x23:
if (dev->index == 0x01)
dev->regs[dev->index] = val;
break;
case 0x24:
opti283_log("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
default:
break;
case 0x10:
dev->regs[dev->index] = (dev->regs[dev->index] & 0x80) | (val & 0x7f);
break;
case 0x14:
reset_on_hlt = !!(val & 0x40);
fallthrough;
case 0x11:
case 0x12:
case 0x13:
dev->regs[dev->index] = val;
opti283_shadow_recalc(dev);
break;
}
dev->index = 0xff;
break;
}
}
static uint8_t
opti283_read(uint16_t addr, void *priv)
{
opti283_t *dev = (opti283_t *) priv;
uint8_t ret = 0xff;
if ((addr == 0x23) && (dev->index == 0x01))
ret = dev->regs[dev->index];
else if (addr == 0x24) {
if ((dev->index >= 0x10) && (dev->index <= 0x14))
ret = dev->regs[dev->index];
dev->index = 0xff;
}
return ret;
}
static void
opti283_close(void *priv)
{
opti283_t *dev = (opti283_t *) priv;
free(dev);
}
static void *
opti283_init(UNUSED(const device_t *info))
{
opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
memset(dev, 0x00, sizeof(opti283_t));
io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x0023, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
dev->regs[0x10] = 0x3f;
dev->regs[0x11] = 0xf0;
dev->mem_remappings[0].phys = 0x000a0000;
dev->mem_remappings[1].phys = 0x000d0000;
mem_mapping_add(&dev->mem_mappings[0], 0, 0x00020000,
opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml,
opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml,
&ram[dev->mem_remappings[0].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[0]);
mem_mapping_disable(&dev->mem_mappings[0]);
mem_mapping_add(&dev->mem_mappings[1], 0, 0x00020000,
opti283_read_remapped_ram, opti283_read_remapped_ramw, opti283_read_remapped_raml,
opti283_write_remapped_ram, opti283_write_remapped_ramw, opti283_write_remapped_raml,
&ram[dev->mem_remappings[1].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[1]);
mem_mapping_disable(&dev->mem_mappings[1]);
opti283_shadow_recalc(dev);
device_add(&port_92_device);
return dev;
}
const device_t opti283_device = {
.name = "OPTi 82C283",
.internal_name = "opti283",
.flags = 0,
.local = 0,
.init = opti283_init,
.close = opti283_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti283.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,062 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of C&T CS8230 ("386/AT") chipset.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
typedef struct cs8230_t {
int idx;
uint8_t regs[256];
} cs8230_t;
static void
shadow_control(uint32_t addr, uint32_t size, int state)
{
switch (state) {
case 0x00:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x01:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x10:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 0x11:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
default:
break;
}
flushmmucache_nopc();
}
static void
rethink_shadow_mappings(cs8230_t *cs8230)
{
for (uint8_t c = 0; c < 32; c++) {
/* Addresses 40000-bffff in 16k blocks */
if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7)))
mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /* I/O channel */
else
mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /* System board */
}
for (uint8_t c = 0; c < 16; c++) {
/* Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here */
if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7)))
mem_set_mem_state(0xc0000 + (c << 14), 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /* I/O channel */
else
shadow_control(0xc0000 + (c << 14), 0x4000, (cs8230->regs[9] >> (3 - (c >> 2))) & 0x11);
}
}
static uint8_t
cs8230_read(uint16_t port, void *priv)
{
const cs8230_t *cs8230 = (cs8230_t *) priv;
uint8_t ret = 0xff;
if (port & 1) {
switch (cs8230->idx) {
case 0x04: /* 82C301 ID/version */
ret = cs8230->regs[cs8230->idx] & ~0xe3;
break;
case 0x08: /* 82C302 ID/Version */
ret = cs8230->regs[cs8230->idx] & ~0xe0;
break;
case 0x05:
case 0x06: /* 82C301 registers */
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c: /* 82C302 registers */
case 0x0d:
case 0x0e:
case 0x0f:
case 0x10:
case 0x11:
case 0x12:
case 0x13:
case 0x28:
case 0x29:
case 0x2a:
ret = cs8230->regs[cs8230->idx];
break;
default:
break;
}
}
return ret;
}
static void
cs8230_write(uint16_t port, uint8_t val, void *priv)
{
cs8230_t *cs8230 = (cs8230_t *) priv;
if (!(port & 1))
cs8230->idx = val;
else {
cs8230->regs[cs8230->idx] = val;
switch (cs8230->idx) {
case 0x09: /* RAM/ROM Configuration in boot area */
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f: /* Address maps */
rethink_shadow_mappings(cs8230);
break;
default:
break;
}
}
}
static void
cs8230_close(void *priv)
{
cs8230_t *cs8230 = (cs8230_t *) priv;
free(cs8230);
}
static void *
cs8230_init(UNUSED(const device_t *info))
{
cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t));
memset(cs8230, 0, sizeof(cs8230_t));
io_sethandler(0x0022, 0x0002, cs8230_read, NULL, NULL, cs8230_write, NULL, NULL, cs8230);
if (mem_size > 768) {
mem_mapping_set_addr(&ram_mid_mapping, 0xa0000, mem_size > 1024 ? 0x60000 : 0x20000 + (mem_size - 768) * 1024);
mem_mapping_set_exec(&ram_mid_mapping, ram + 0xa0000);
}
return cs8230;
}
const device_t cs8230_device = {
.name = "C&T CS8230 (386/AT)",
.internal_name = "cs8230",
.flags = 0,
.local = 0,
.init = cs8230_init,
.close = cs8230_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/cs8230.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,514 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 85C50x and 550x Chipsets.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/apm.h>
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat_unused.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/spd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_85C50X_LOG
int sis_85c50x_do_log = ENABLE_SIS_85C50X_LOG;
static void
sis_85c50x_log(const char *fmt, ...)
{
va_list ap;
if (sis_85c50x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_85c50x_log(fmt, ...)
#endif
typedef struct sis_85c50x_t {
uint8_t index;
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t type;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[256];
uint8_t pci_conf_ide[256];
uint8_t regs[256];
uint32_t states[13];
smram_t *smram[2];
port_92_t *port_92;
void *pit;
nvr_t *nvr;
uint8_t (*pit_read_reg)(void *priv, uint8_t reg);
} sis_85c50x_t;
static void
sis_85c50x_shadow_recalc(sis_85c50x_t *dev)
{
uint32_t base;
uint32_t can_read;
uint32_t can_write;
uint32_t state;
can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
state = can_read | can_write;
if (dev->states[12] != state) {
mem_set_mem_state_both(0x000f0000, 0x00010000, state);
sis_85c50x_log("F0000-FFFFF: R%c, W%c\n",
(dev->pci_conf[0x53] & 0x40) ? 'I' : 'E',
(dev->pci_conf[0x53] & 0x20) ? 'P' : 'I');
dev->states[12] = state;
}
for (uint8_t i = 0; i < 4; i++) {
base = 0x000e0000 + (i << 14);
state = (dev->pci_conf[0x54] & (0x80 >> i)) ?
(can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->states[8 + i] != state) {
mem_set_mem_state_both(base, 0x00004000, state);
sis_85c50x_log("%05X-%05X: R%c, W%c\n", base, base + 0x3fff,
(dev->pci_conf[0x54] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x40) ? 'I' : 'D') : 'E',
(dev->pci_conf[0x54] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x20) ? 'P' : 'I') : 'E');
dev->states[8 + i] = state;
}
base = 0x000d0000 + (i << 14);
state = (dev->pci_conf[0x55] & (0x80 >> i)) ?
(can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->states[4 + i] != state) {
mem_set_mem_state_both(base, 0x00004000, state);
sis_85c50x_log("%05X-%05X: R%c, W%c\n", base, base + 0x3fff,
(dev->pci_conf[0x55] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x40) ? 'I' : 'D') : 'E',
(dev->pci_conf[0x55] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x20) ? 'P' : 'I') : 'E');
dev->states[4 + i] = state;
}
base = 0x000c0000 + (i << 14);
state = (dev->pci_conf[0x56] & (0x80 >> i)) ?
(can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->states[i] != state) {
mem_set_mem_state_both(base, 0x00004000, state);
sis_85c50x_log("%05X-%05X: R%c, W%c\n", base, base + 0x3fff,
(dev->pci_conf[0x56] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x40) ? 'I' : 'D') : 'E',
(dev->pci_conf[0x56] & (0x80 >> i)) ?
((dev->pci_conf[0x53] & 0x20) ? 'P' : 'I') : 'E');
dev->states[i] = state;
}
}
flushmmucache_nopc();
}
static void
sis_85c50x_smm_recalc(sis_85c50x_t *dev)
{
/* NOTE: Naming mismatch - what the datasheet calls "host address" is what we call ram_base. */
uint32_t host_base = (dev->pci_conf[0x64] << 20) | ((dev->pci_conf[0x65] & 0x07) << 28);
smram_disable_all();
if ((((dev->pci_conf[0x65] & 0xe0) >> 5) != 0x00) && (host_base == 0x00000000))
return;
switch ((dev->pci_conf[0x65] & 0xe0) >> 5) {
case 0x00:
sis_85c50x_log("SiS 50x SMRAM: 000E0000-000E7FFF -> 000E0000-000E7FFF\n");
smram_enable(dev->smram[0], 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x01:
host_base |= 0x000b0000;
sis_85c50x_log("SiS 50x SMRAM: %08X-%08X -> 000B0000-000BFFFF\n",
host_base, host_base + 0x10000 - 1);
smram_enable(dev->smram[0], host_base, 0xb0000, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xb0000,
0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x02:
host_base |= 0x000a0000;
sis_85c50x_log("SiS 50x SMRAM: %08X-%08X -> 000A0000-000AFFFF\n",
host_base, host_base + 0x10000 - 1);
smram_enable(dev->smram[0], host_base, 0xa0000, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xa0000,
0x10000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x04:
host_base |= 0x000a0000;
sis_85c50x_log("SiS 50x SMRAM: %08X-%08X -> 000A0000-000AFFFF\n",
host_base, host_base + 0x8000 - 1);
smram_enable(dev->smram[0], host_base, 0xa0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xa0000,
0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x06:
host_base |= 0x000b0000;
sis_85c50x_log("SiS 50x SMRAM: %08X-%08X -> 000B0000-000BFFFF\n",
host_base, host_base + 0x8000 - 1);
smram_enable(dev->smram[0], host_base, 0xb0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xa0000,
0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
default:
break;
}
}
static void
sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_log("85C501: [W] (%02X, %02X) = %02X\n", func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04: /* Command - low byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b);
break;
case 0x07: /* Status - high byte */
dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06);
break;
case 0x50:
if (dev->type & 1)
dev->pci_conf[addr] = val & 0xf7;
else
dev->pci_conf[addr] = val;
break;
case 0x51: /* Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53: /* Shadow RAM */
case 0x54:
case 0x55:
case 0x56:
dev->pci_conf[addr] = val;
sis_85c50x_shadow_recalc(dev);
break;
case 0x57:
case 0x58:
case 0x59:
case 0x5a:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x61:
case 0x62:
case 0x63:
case 0x67:
case 0x68:
case 0x6a:
case 0x6b:
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x5b:
dev->pci_conf[addr] = val;
kbc_at_set_fast_reset(!!(val & 0x40));
break;
case 0x60: /* SMI */
if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
dev->pci_conf[0x69] |= 0x01;
smi_raise();
}
dev->pci_conf[addr] = val & 0x3e;
break;
case 0x64: /* SMRAM */
case 0x65:
dev->pci_conf[addr] = val;
sis_85c50x_smm_recalc(dev);
break;
case 0x66:
dev->pci_conf[addr] = (val & 0x7f);
break;
case 0x69:
dev->pci_conf[addr] &= ~val;
break;
case 0x70 ... 0x77:
if (dev->type & 1)
spd_write_drbs(dev->pci_conf, 0x70, 0x77, 2);
break;
case 0x78:
case 0x7c ... 0x7e:
if (dev->type & 1)
dev->pci_conf[addr] = val;
break;
case 0x79:
if (dev->type & 1) {
spd_write_drbs(dev->pci_conf, 0xf8, 0xff, 4);
dev->pci_conf[addr] = 0x00;
for (uint8_t i = 0; i < 8; i++)
if (dev->pci_conf[0xf8 + i] & 0x80) dev->pci_conf[addr] |= (1 << i);
}
break;
case 0x7a:
if (dev->type & 1)
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x7b:
if (dev->type & 1)
dev->pci_conf[addr] = val & 0xe0;
break;
default:
break;
}
}
static uint8_t
sis_85c50x_read(int func, int addr, void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) {
if (addr >= 0xf8)
ret = 0x00;
else
ret = dev->pci_conf[addr];
}
sis_85c50x_log("85C501: [R] (%02X, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
sis_85c50x_ide_recalc(sis_85c50x_t *dev)
{
ide_pri_disable();
ide_set_base(0, (dev->pci_conf_ide[0x40] & 0x80) ? 0x0170 : 0x01f0);
ide_set_side(0, (dev->pci_conf_ide[0x40] & 0x80) ? 0x0376 : 0x03f6);
ide_pri_enable();
ide_sec_disable();
ide_set_base(1, (dev->pci_conf_ide[0x40] & 0x80) ? 0x01f0 : 0x0170);
ide_set_side(1, (dev->pci_conf_ide[0x40] & 0x80) ? 0x03f6 : 0x0376);
if (dev->pci_conf_ide[0x41] & 0x01)
ide_sec_enable();
}
static void
sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_log("85C503: [W] (%02X, %02X) = %02X\n", func, addr, val);
if (func == 0x00) switch (addr) {
case 0x04: /* Command */
dev->pci_conf_sb[addr] = val & 0x0f;
break;
case 0x07: /* Status */
dev->pci_conf_sb[addr] &= ~(val & 0x30);
break;
case 0x40: /* BIOS Control Register */
dev->pci_conf_sb[addr] = val & 0x3f;
break;
case 0x41:
case 0x42:
case 0x43:
case 0x44:
/* INTA/B/C/D# Remapping Control Register */
dev->pci_conf_sb[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf);
break;
case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[addr] = val;
break;
default:
break;
} else if ((dev->type & 2) && !(dev->regs[0x81] & 0x02) && (func == 0x01)) switch (addr) {
case 0x40:
case 0x41:
dev->pci_conf_ide[addr] = val;
sis_85c50x_ide_recalc(dev);
break;
default:
break;
}
}
static uint8_t
sis_85c50x_sb_read(int func, int addr, void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) switch (addr) {
default:
ret = dev->pci_conf_sb[addr];
break;
case 0x4c ... 0x4f:
if (dev->type & 2)
ret = pic_read_icw(0, addr & 0x03);
else
ret = dev->pci_conf_sb[addr];
break;
case 0x50 ... 0x53:
if (dev->type & 2)
ret = pic_read_icw(1, addr & 0x03);
else
ret = dev->pci_conf_sb[addr];
break;
case 0x54 ... 0x55:
if (dev->type & 2)
ret = pic_read_ocw(0, addr & 0x01);
else
ret = dev->pci_conf_sb[addr];
break;
case 0x56 ... 0x57:
if (dev->type & 2)
ret = pic_read_ocw(1, addr & 0x01);
else
ret = dev->pci_conf_sb[addr];
break;
case 0x58 ... 0x5f:
if (dev->type & 2)
ret = dev->pit_read_reg(dev->pit, addr & 0x07);
else
ret = dev->pci_conf_sb[addr];
break;
} else if ((dev->type & 2) && !(dev->regs[0x81] & 0x02) && (func == 0x01))
ret = dev->pci_conf_ide[addr];
sis_85c50x_log("85C503: [W] (%02X, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
sis_85c50x_log("85C503 ISA: [W] (%04X) = %02X\n", addr, val);
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
switch (dev->index) {
case 0x80:
if (dev->type & 2) {
dev->regs[dev->index] = val;
nvr_bank_set(0, !!(val & 0x08), dev->nvr);
} else
dev->regs[dev->index] = val & 0xe7;
switch (val >> 6) {
case 0:
cpu_set_isa_speed(7159091);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
break;
case 0x81:
if (dev->type & 2)
dev->regs[dev->index] = val & 0xf6;
else
dev->regs[dev->index] = val & 0xf4;
break;
case 0x82:
if (dev->type & 2)
dev->regs[dev->index] = val;
break;
case 0x83:
if (dev->type & 2)
dev->regs[dev->index] = val & 0x03;
break;
case 0x84:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
dev->regs[dev->index] = val;
break;
case 0x85:
outb(0x70, val);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
sis_85c50x_isa_read(uint16_t addr, void *priv)
{
const sis_85c50x_t *dev = (sis_85c50x_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x22:
ret = dev->index;
break;
case 0x23:
if (dev->index == 0x85)
ret = inb(0x70);
else
ret = dev->regs[dev->index];
break;
default:
break;
}
sis_85c50x_log("85C503 ISA: [R] (%04X) = %02X\n", addr, ret);
return ret;
}
static void
sis_85c50x_reset(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
/* North Bridge (SiS 85C501/502) */
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x06;
dev->pci_conf[0x03] = 0x04;
dev->pci_conf[0x04] = 0x04;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
sis_85c50x_write(0, 0x51, 0x00, dev);
sis_85c50x_write(0, 0x53, 0x00, dev);
sis_85c50x_write(0, 0x54, 0x00, dev);
sis_85c50x_write(0, 0x55, 0x00, dev);
sis_85c50x_write(0, 0x56, 0x00, dev);
sis_85c50x_write(0, 0x5b, 0x00, dev);
sis_85c50x_write(0, 0x60, 0x00, dev);
sis_85c50x_write(0, 0x64, 0x00, dev);
sis_85c50x_write(0, 0x65, 0x00, dev);
sis_85c50x_write(0, 0x68, 0x00, dev);
sis_85c50x_write(0, 0x69, 0xff, dev);
if (dev->type & 1) {
for (uint8_t i = 0; i < 8; i++)
dev->pci_conf[0x70 + i] = 0x00;
dev->pci_conf[0x79] = 0x00;
}
/* South Bridge (SiS 85C503) */
dev->pci_conf_sb[0x00] = 0x39;
dev->pci_conf_sb[0x01] = 0x10;
dev->pci_conf_sb[0x02] = 0x08;
dev->pci_conf_sb[0x03] = 0x00;
dev->pci_conf_sb[0x04] = 0x07;
dev->pci_conf_sb[0x05] = 0x00;
dev->pci_conf_sb[0x06] = 0x00;
dev->pci_conf_sb[0x07] = 0x02;
dev->pci_conf_sb[0x08] = 0x00;
dev->pci_conf_sb[0x09] = 0x00;
dev->pci_conf_sb[0x0a] = 0x01;
dev->pci_conf_sb[0x0b] = 0x06;
if (dev->type & 2)
dev->pci_conf_sb[0x0e] = 0x80;
sis_85c50x_sb_write(0, 0x41, 0x80, dev);
sis_85c50x_sb_write(0, 0x42, 0x80, dev);
sis_85c50x_sb_write(0, 0x43, 0x80, dev);
sis_85c50x_sb_write(0, 0x44, 0x80, dev);
if (dev->type & 2) {
/* IDE (SiS 5503) */
dev->pci_conf_ide[0x00] = 0x39;
dev->pci_conf_ide[0x01] = 0x10;
dev->pci_conf_ide[0x02] = 0x01;
dev->pci_conf_ide[0x03] = 0x06;
dev->pci_conf_ide[0x04] = 0x89;
dev->pci_conf_ide[0x05] = 0x00;
dev->pci_conf_ide[0x06] = 0x00;
dev->pci_conf_ide[0x07] = 0x00;
dev->pci_conf_ide[0x08] = 0x00;
dev->pci_conf_ide[0x09] = 0x00;
dev->pci_conf_ide[0x0a] = 0x01;
dev->pci_conf_ide[0x0b] = 0x01;
dev->pci_conf_ide[0x0c] = 0x00;
dev->pci_conf_ide[0x0d] = 0x00;
dev->pci_conf_ide[0x0e] = 0x80;
dev->pci_conf_ide[0x0f] = 0x00;
dev->pci_conf_ide[0x10] = 0x71;
dev->pci_conf_ide[0x11] = 0x01;
dev->pci_conf_ide[0x14] = 0xf1;
dev->pci_conf_ide[0x15] = 0x01;
dev->pci_conf_ide[0x18] = 0x71;
dev->pci_conf_ide[0x19] = 0x03;
dev->pci_conf_ide[0x1c] = 0xf1;
dev->pci_conf_ide[0x1d] = 0x03;
dev->pci_conf_ide[0x20] = 0x01;
dev->pci_conf_ide[0x24] = 0x01;
dev->pci_conf_ide[0x40] = 0x00;
dev->pci_conf_ide[0x41] = 0x40;
sis_85c50x_ide_recalc(dev);
}
cpu_set_isa_speed(7159091);
if (dev->type & 2)
nvr_bank_set(0, 0, dev->nvr);
}
static void
sis_85c50x_close(void *priv)
{
sis_85c50x_t *dev = (sis_85c50x_t *) priv;
smram_del(dev->smram[1]);
smram_del(dev->smram[0]);
free(dev);
}
static void *
sis_85c50x_init(UNUSED(const device_t *info))
{
sis_85c50x_t *dev = (sis_85c50x_t *) calloc(1, sizeof(sis_85c50x_t));
uint8_t pit_is_fast = (((pit_mode == -1) && is486) || (pit_mode == 1));
dev->type = info->local;
/* 501/502 (Northbridge) */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev, &dev->nb_slot);
/* 503 (Southbridge) */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev, &dev->sb_slot);
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();
dev->port_92 = device_add(&port_92_device);
if (dev->type & 2) {
/* PIT */
dev->pit = device_find_first_priv(DEVICE_PIT);
dev->pit_read_reg = pit_is_fast ? pitf_read_reg : pit_read_reg;
/* NVR */
dev->nvr = device_add(&at_mb_nvr_device);
device_add(&ide_pci_2ch_device);
}
sis_85c50x_reset(dev);
return dev;
}
const device_t sis_85c50x_device = {
.name = "SiS 85C50x",
.internal_name = "sis_85c50x",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_550x_85c503_device = {
.name = "SiS 550x",
.internal_name = "sis_550x",
.flags = DEVICE_PCI,
.local = 1,
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_85c50x_5503_device = {
.name = "SiS 85C50x",
.internal_name = "sis_85c50x",
.flags = DEVICE_PCI,
.local = 2,
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_550x_device = {
.name = "SiS 550x",
.internal_name = "sis_550x",
.flags = DEVICE_PCI,
.local = 3,
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_85c50x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,943 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C291 chipset.
*
*
*
* Authors: plant/nerd73, Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI291_LOG
int opti291_do_log = ENABLE_OPTI291_LOG;
static void
opti291_log(const char *fmt, ...)
{
va_list ap;
if (opti291_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti291_log(fmt, ...)
#endif
typedef struct opti291_t {
uint8_t index;
uint8_t regs[256];
port_92_t *port_92;
} opti291_t;
static void
opti291_recalc(opti291_t *dev)
{
mem_set_mem_state_both(0xf0000, 0x10000, (!(dev->regs[0x23] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
for (uint32_t i = 0; i < 4; i++) {
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x26] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : ((dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, ((dev->regs[0x25] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : ((dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, ((dev->regs[0x24] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : ((dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
}
flushmmucache();
}
static void
opti291_write(uint16_t addr, uint8_t val, void *priv)
{
opti291_t *dev = (opti291_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x24:
opti291_log("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val);
switch (dev->index) {
case 0x20:
dev->regs[dev->index] = val & 0x3f;
break;
case 0x21:
dev->regs[dev->index] = val & 0xf3;
break;
case 0x22:
dev->regs[dev->index] = val;
break;
case 0x23:
case 0x24:
case 0x25:
case 0x26:
dev->regs[dev->index] = val;
opti291_recalc(dev);
break;
case 0x27:
case 0x28:
dev->regs[dev->index] = val;
break;
case 0x29:
dev->regs[dev->index] = val & 0x0f;
break;
case 0x2a:
case 0x2b:
case 0x2c:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
opti291_read(uint16_t addr, void *priv)
{
const opti291_t *dev = (opti291_t *) priv;
return (addr == 0x24) ? dev->regs[dev->index] : 0xff;
}
static void
opti291_close(void *priv)
{
opti291_t *dev = (opti291_t *) priv;
free(dev);
}
static void *
opti291_init(UNUSED(const device_t *info))
{
opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t));
memset(dev, 0, sizeof(opti291_t));
io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
dev->regs[0x22] = 0xf0;
dev->regs[0x23] = 0x40;
dev->regs[0x28] = 0x08;
dev->regs[0x29] = 0xa0;
device_add(&port_92_device);
opti291_recalc(dev);
return dev;
}
const device_t opti291_device = {
.name = "OPTi 82C291",
.internal_name = "opti291",
.flags = 0,
.local = 0,
.init = opti291_init,
.close = opti291_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti291.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,498 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5511/5512/5513 Pentium PCI/ISA Chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5511_LOG
int sis_5511_do_log = ENABLE_SIS_5511_LOG;
static void
sis_5511_log(const char *fmt, ...)
{
va_list ap;
if (sis_5511_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5511_log(fmt, ...)
#endif
typedef struct sis_5511_t {
uint8_t nb_slot;
uint8_t sb_slot;
void *h2p;
void *p2i;
void *ide;
sis_55xx_common_t *sis;
} sis_5511_t;
static void
sis_5511_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
sis_5511_log("SiS 5511: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5511_host_to_pci_write(addr, val, dev->h2p);
}
static uint8_t
sis_5511_read(int func, int addr, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5511_host_to_pci_read(addr, dev->h2p);
sis_5511_log("SiS 5511: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5513_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
sis_5511_log("SiS 5513: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5513_pci_to_isa_write(addr, val, dev->p2i);
else if (func == 0x01)
sis_5513_ide_write(addr, val, dev->ide);
}
static uint8_t
sis_5513_read(int func, int addr, void *priv)
{
const sis_5511_t *dev = (sis_5511_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5513_pci_to_isa_read(addr, dev->p2i);
else if (func == 0x01)
ret = sis_5513_ide_read(addr, dev->ide);
sis_5511_log("SiS 5513: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5511_close(void *priv)
{
sis_5511_t *dev = (sis_5511_t *) priv;
free(dev);
}
static void *
sis_5511_init(UNUSED(const device_t *info))
{
sis_5511_t *dev = (sis_5511_t *) calloc(1, sizeof(sis_5511_t));
/* Device 0: SiS 5511 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5511_read, sis_5511_write, dev, &dev->nb_slot);
/* Device 1: SiS 5513 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5513_read, sis_5513_write, dev, &dev->sb_slot);
dev->sis = device_add(&sis_55xx_common_device);
dev->h2p = device_add_linked(&sis_5511_h2p_device, dev->sis);
dev->p2i = device_add_linked(&sis_5513_p2i_device, dev->sis);
dev->ide = device_add_linked(&sis_5513_ide_device, dev->sis);
return dev;
}
const device_t sis_5511_device = {
.name = "SiS 5511",
.internal_name = "sis_5511",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5511_init,
.close = sis_5511_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5511.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,385 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C493/82C499 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct opti499_t {
uint8_t idx;
uint8_t regs[256];
uint8_t scratch[2];
} opti499_t;
/* According to The Last Byte, register 2Dh bit 7 must still be writable, even if it is unused. */
static uint8_t masks[0x0e] = { 0x3f, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xe3, 0xff, 0xfb, 0xff, 0x00, 0xff };
#ifdef ENABLE_OPTI499_LOG
int opti499_do_log = ENABLE_OPTI499_LOG;
static void
opti499_log(const char *fmt, ...)
{
va_list ap;
if (opti499_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti499_log(fmt, ...)
#endif
static void
opti499_recalc(opti499_t *dev)
{
uint32_t base;
uint32_t shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
if (dev->regs[0x22] & 0x80) {
shadowbios = 1;
shadowbios_write = 0;
shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
} else {
shadowbios = 0;
shadowbios_write = 1;
shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
}
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
if (dev->regs[0x2d] & (1 << ((i >> 1) + 2)))
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
else
shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL;
}
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
if (dev->regs[0x26] & 0x40) {
if (dev->regs[0x2d] & (1 << (i >> 1)))
shflags = MEM_READ_EXTANY;
else
shflags = MEM_READ_EXTERNAL;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
if (dev->regs[0x2d] & (1 << (i >> 1)))
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
else
shflags = MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL;
}
}
mem_set_mem_state_both(base, 0x4000, shflags);
}
flushmmucache_nopc();
}
static void
opti499_write(uint16_t addr, uint8_t val, void *priv)
{
opti499_t *dev = (opti499_t *) priv;
switch (addr) {
default:
break;
case 0x22:
opti499_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val);
dev->idx = val;
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) {
opti499_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val);
dev->regs[dev->idx] = val & masks[dev->idx - 0x20];
if (dev->idx == 0x2a)
dev->regs[dev->idx] |= 0x04;
switch (dev->idx) {
default:
break;
case 0x20:
reset_on_hlt = !(val & 0x02);
break;
case 0x21:
cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10);
cpu_update_waitstates();
break;
case 0x22:
case 0x23:
case 0x26:
case 0x2d:
opti499_recalc(dev);
break;
}
}
dev->idx = 0xff;
break;
case 0xe1:
case 0xe2:
dev->scratch[~addr & 0x01] = val;
break;
}
}
static uint8_t
opti499_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti499_t *dev = (opti499_t *) priv;
switch (addr) {
default:
break;
case 0x22:
opti499_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret);
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= 0x2d) && (dev->idx != 0x2c)) {
ret = dev->regs[dev->idx];
opti499_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret);
}
dev->idx = 0xff;
break;
case 0xe1:
case 0xe2:
ret = dev->scratch[~addr & 0x01];
break;
}
return ret;
}
static void
opti499_reset(void *priv)
{
opti499_t *dev = (opti499_t *) priv;
memset(dev->regs, 0xff, sizeof(dev->regs));
memset(&(dev->regs[0x20]), 0x00, 14 * sizeof(uint8_t));
dev->scratch[0] = dev->scratch[1] = 0xff;
dev->regs[0x22] = 0x84;
dev->regs[0x24] = 0x87;
dev->regs[0x25] = 0xf0;
dev->regs[0x27] = 0xd1;
dev->regs[0x28] = dev->regs[0x2a] = 0x80;
dev->regs[0x29] = dev->regs[0x2b] = 0x10;
dev->regs[0x2d] = 0x40;
reset_on_hlt = 1;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
opti499_recalc(dev);
}
static void
opti499_close(void *priv)
{
opti499_t *dev = (opti499_t *) priv;
free(dev);
}
static void *
opti499_init(UNUSED(const device_t *info))
{
opti499_t *dev = (opti499_t *) malloc(sizeof(opti499_t));
memset(dev, 0, sizeof(opti499_t));
device_add(&port_92_device);
io_sethandler(0x0022, 0x0001, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
opti499_reset(dev);
io_sethandler(0x00e1, 0x0002, opti499_read, NULL, NULL, opti499_write, NULL, NULL, dev);
return dev;
}
const device_t opti499_device = {
.name = "OPTi 82C499",
.internal_name = "opti499",
.flags = 0,
.local = 1,
.init = opti499_init,
.close = opti499_close,
.reset = opti499_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti499.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,306 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of Intel System I/O PCI chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/port_92.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
typedef struct sio_t {
uint8_t id;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t regs[256];
uint16_t timer_base;
uint16_t timer_latch;
double fast_off_period;
pc_timer_t timer;
pc_timer_t fast_off_timer;
apm_t *apm;
port_92_t *port_92;
} sio_t;
#ifdef ENABLE_SIO_LOG
int sio_do_log = ENABLE_SIO_LOG;
static void
sio_log(const char *fmt, ...)
{
va_list ap;
if (sio_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sio_log(fmt, ...)
#endif
static void
sio_timer_write(uint16_t addr, uint8_t val, void *priv)
{
sio_t *dev = (sio_t *) priv;
if (!(addr & 0x0002)) {
if (addr & 0x0001)
dev->timer_latch = (dev->timer_latch & 0xff) | (val << 8);
else
dev->timer_latch = (dev->timer_latch & 0xff00) | val;
timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
}
}
static void
sio_timer_writew(uint16_t addr, uint16_t val, void *priv)
{
sio_t *dev = (sio_t *) priv;
if (!(addr & 0x0002)) {
dev->timer_latch = val;
timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
}
}
static uint8_t
sio_timer_read(uint16_t addr, void *priv)
{
sio_t *dev = (sio_t *) priv;
uint16_t sio_timer_latch;
uint8_t ret = 0xff;
if (!(addr & 0x0002)) {
cycles -= ((int) (PITCONST >> 32));
sio_timer_latch = timer_get_remaining_us(&dev->timer);
if (addr & 0x0001)
ret = sio_timer_latch >> 8;
else
ret = sio_timer_latch & 0xff;
}
return ret;
}
static uint16_t
sio_timer_readw(uint16_t addr, void *priv)
{
sio_t *dev = (sio_t *) priv;
uint16_t ret = 0xffff;
if (!(addr & 0x0002)) {
cycles -= ((int) (PITCONST >> 32));
ret = timer_get_remaining_us(&dev->timer);
}
return ret;
}
static void
sio_write(int func, int addr, uint8_t val, void *priv)
{
sio_t *dev = (sio_t *) priv;
uint8_t old;
if (func > 0)
return;
if (((addr >= 0x0f) && (addr < 0x4c)) && (addr != 0x40))
return;
/* The IB (original) variant of the SIO has no PCI IRQ steering. */
if ((addr >= 0x60) && (addr <= 0x63) && (dev->id < 0x03))
return;
old = dev->regs[addr];
switch (addr) {
case 0x04: /*Command register*/
if (dev->id == 0x03)
dev->regs[addr] = (dev->regs[addr] & 0xf7) | (val & 0x08);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0x38);
break;
case 0x40:
if (dev->id == 0x03) {
dev->regs[addr] = (val & 0x7f);
if (!((val ^ old) & 0x40))
return;
dma_alias_remove();
if (!(val & 0x40))
dma_alias_set();
} else
dev->regs[addr] = (val & 0x3f);
break;
case 0x41:
case 0x44:
dev->regs[addr] = (val & 0x1f);
break;
case 0x42:
if (dev->id == 0x03)
dev->regs[addr] = val;
else
dev->regs[addr] = (val & 0x77);
break;
case 0x43:
if (dev->id == 0x03)
dev->regs[addr] = (val & 0x01);
break;
case 0x45:
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
case 0x4e:
case 0x54:
case 0x55:
case 0x56:
dev->regs[addr] = val;
break;
case 0x4c:
dev->regs[addr] = (val & 0x7f);
break;
case 0x4d:
dev->regs[addr] = (val & 0x7f);
break;
case 0x4f:
dev->regs[addr] = val;
if (!((val ^ old) & 0x40))
return;
port_92_remove(dev->port_92);
if (val & 0x40)
port_92_add(dev->port_92);
break;
case 0x57:
dev->regs[addr] = val;
dma_remove_sg();
dma_set_sg_base(val);
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
if (dev->id == 0x03) {
sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
dev->regs[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf);
}
break;
case 0x80:
case 0x81:
if (addr == 0x80)
dev->regs[addr] = val & 0xfd;
else
dev->regs[addr] = val;
if (dev->timer_base & 0x01) {
io_removehandler(dev->timer_base & 0xfffc, 0x0004,
sio_timer_read, sio_timer_readw, NULL,
sio_timer_write, sio_timer_writew, NULL, dev);
}
dev->timer_base = (dev->regs[0x81] << 8) | (dev->regs[0x80] & 0xfd);
if (dev->timer_base & 0x01) {
io_sethandler(dev->timer_base & 0xfffc, 0x0004,
sio_timer_read, sio_timer_readw, NULL,
sio_timer_write, sio_timer_writew, NULL, dev);
}
break;
case 0xa0:
if (dev->id == 0x03) {
dev->regs[addr] = val & 0x1f;
apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(dev->regs[0xa2] & 0x80));
switch ((val & 0x18) >> 3) {
case 0x00:
dev->fast_off_period = PCICLK * 32768.0 * 60000.0;
break;
case 0x01:
default:
dev->fast_off_period = 0.0;
break;
case 0x02:
dev->fast_off_period = PCICLK;
break;
case 0x03:
dev->fast_off_period = PCICLK * 32768.0;
break;
}
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
}
break;
case 0xa2:
if (dev->id == 0x03) {
dev->regs[addr] = val & 0xff;
apm_set_do_smi(dev->apm, !!(dev->regs[0xa0] & 0x01) && !!(val & 0x80));
}
break;
case 0xaa:
if (dev->id == 0x03)
dev->regs[addr] &= (val & 0xff);
break;
case 0xac:
case 0xae:
if (dev->id == 0x03)
dev->regs[addr] = val & 0xff;
break;
case 0xa4:
if (dev->id == 0x03) {
dev->regs[addr] = val & 0xfb;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | dev->regs[addr];
}
break;
case 0xa5:
if (dev->id == 0x03) {
dev->regs[addr] = val & 0xff;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (dev->regs[addr] << 8);
}
break;
case 0xa7:
if (dev->id == 0x03) {
dev->regs[addr] = val & 0xa0;
cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (dev->regs[addr] << 24);
}
break;
case 0xa8:
dev->regs[addr] = val & 0xff;
cpu_fast_off_val = val;
cpu_fast_off_count = val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
break;
default:
break;
}
}
static uint8_t
sio_read(int func, int addr, void *priv)
{
const sio_t *dev = (sio_t *) priv;
uint8_t ret;
ret = 0xff;
if (func == 0)
ret = dev->regs[addr];
return ret;
}
static void
sio_config_write(UNUSED(uint16_t addr), UNUSED(uint8_t val), UNUSED(void *priv))
{
//
}
static uint8_t
sio_config_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0x00;
switch (port & 0x000f) {
case 3:
ret = 0xff;
break;
case 5:
ret = 0xd3;
switch (cpu_pci_speed) {
case 20000000:
ret |= 0x0c;
break;
case 25000000:
default:
ret |= 0x00;
break;
case 30000000:
ret |= 0x08;
break;
case 33333333:
ret |= 0x04;
break;
}
break;
default:
break;
}
return ret;
}
static void
sio_reset_hard(void *priv)
{
sio_t *dev = (sio_t *) priv;
memset(dev->regs, 0, 256);
dev->regs[0x00] = 0x86;
dev->regs[0x01] = 0x80; /*Intel*/
dev->regs[0x02] = 0x84;
dev->regs[0x03] = 0x04; /*82378IB (SIO)*/
dev->regs[0x04] = 0x07;
dev->regs[0x07] = 0x02;
dev->regs[0x08] = dev->id;
dev->regs[0x40] = 0x20;
dev->regs[0x41] = 0x00;
dev->regs[0x42] = 0x04;
dev->regs[0x45] = 0x10;
dev->regs[0x46] = 0x0f;
dev->regs[0x48] = 0x01;
dev->regs[0x4a] = 0x10;
dev->regs[0x4b] = 0x0f;
dev->regs[0x4c] = 0x56;
dev->regs[0x4d] = 0x40;
dev->regs[0x4e] = 0x07;
dev->regs[0x4f] = 0x4f;
dev->regs[0x57] = 0x04;
if (dev->id == 0x03) {
dev->regs[0x60] = 0x80;
dev->regs[0x61] = 0x80;
dev->regs[0x62] = 0x80;
dev->regs[0x63] = 0x80;
}
dev->regs[0x80] = 0x78;
if (dev->id == 0x03) {
dev->regs[0xa0] = 0x08;
dev->regs[0xa8] = 0x0f;
}
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
if (dev->timer_base & 0x0001) {
io_removehandler(dev->timer_base & 0xfffc, 0x0004,
sio_timer_read, sio_timer_readw, NULL,
sio_timer_write, sio_timer_writew, NULL, dev);
}
dev->timer_base = 0x0078;
}
static void
sio_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
sio_t *dev = (sio_t *) priv;
if (dev->apm->do_smi)
dev->regs[0xaa] |= 0x80;
}
static void
sio_fast_off_count(void *priv)
{
sio_t *dev = (sio_t *) priv;
smi_raise();
dev->regs[0xaa] |= 0x20;
}
static void
sio_reset(void *priv)
{
const sio_t *dev = (sio_t *) priv;
/* Disable the PIC mouse latch. */
sio_write(0, 0x4d, 0x40, priv);
sio_write(0, 0x57, 0x04, priv);
dma_set_params(1, 0xffffffff);
if (dev->id == 0x03) {
sio_write(0, 0xa0, 0x08, priv);
sio_write(0, 0xa2, 0x00, priv);
sio_write(0, 0xa4, 0x00, priv);
sio_write(0, 0xa5, 0x00, priv);
sio_write(0, 0xa6, 0x00, priv);
sio_write(0, 0xa7, 0x00, priv);
sio_write(0, 0xa8, 0x0f, priv);
}
}
static void
sio_close(void *priv)
{
sio_t *dev = (sio_t *) priv;
free(dev);
}
static void
sio_speed_changed(void *priv)
{
sio_t *dev = (sio_t *) priv;
int te;
te = timer_is_enabled(&dev->timer);
timer_disable(&dev->timer);
if (te)
timer_set_delay_u64(&dev->timer, ((uint64_t) dev->timer_latch) * TIMER_USEC);
if (dev->id == 0x03) {
te = timer_is_on(&dev->fast_off_timer);
timer_stop(&dev->fast_off_timer);
if (te)
timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
}
}
static void *
sio_init(const device_t *info)
{
sio_t *dev = (sio_t *) malloc(sizeof(sio_t));
memset(dev, 0, sizeof(sio_t));
pci_add_card(PCI_ADD_SOUTHBRIDGE, sio_read, sio_write, dev, &dev->pci_slot);
dev->id = info->local;
if (dev->id == 0x03)
timer_add(&dev->fast_off_timer, sio_fast_off_count, dev, 0);
sio_reset_hard(dev);
cpu_fast_off_flags = 0x00000000;
if (dev->id == 0x03) {
cpu_fast_off_val = dev->regs[0xa8];
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_register_fast_off_handler(&dev->fast_off_timer);
} else
cpu_fast_off_val = cpu_fast_off_count = 0;
if (dev->id == 0x03) {
dev->apm = device_add(&apm_pci_device);
/* APM intercept handler to update 82378ZB SMI status on APM SMI. */
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, sio_apm_out, NULL, NULL, dev);
}
dev->port_92 = device_add(&port_92_pci_device);
dma_set_sg_base(0x04);
dma_set_params(1, 0xffffffff);
dma_ext_mode_init();
dma_high_page_init();
if (dev->id == 0x03)
dma_alias_set();
io_sethandler(0x0073, 0x0001,
sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev);
io_sethandler(0x0075, 0x0001,
sio_config_read, NULL, NULL, sio_config_write, NULL, NULL, dev);
timer_add(&dev->timer, NULL, NULL, 0);
#if 0
device_add(&i8254_sec_device);
#endif
return dev;
}
const device_t sio_device = {
.name = "Intel 82378IB (SIO)",
.internal_name = "sio",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sio_init,
.close = sio_close,
.reset = sio_reset,
{ .available = NULL },
.speed_changed = sio_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t sio_zb_device = {
.name = "Intel 82378ZB (SIO)",
.internal_name = "sio_zb",
.flags = DEVICE_PCI,
.local = 0x03,
.init = sio_init,
.close = sio_close,
.reset = sio_reset,
{ .available = NULL },
.speed_changed = sio_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_sio.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,754 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5591/5592 Pentium PCI/ISA Chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5591_LOG
int sis_5591_do_log = ENABLE_SIS_5591_LOG;
static void
sis_5591_log(const char *fmt, ...)
{
va_list ap;
if (sis_5591_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5591_log(fmt, ...)
#endif
typedef struct sis_5591_t {
uint8_t nb_slot;
uint8_t sb_slot;
void *h2p;
void *p2i;
void *ide;
void *usb;
void *pmu;
sis_55xx_common_t *sis;
} sis_5591_t;
static void
sis_5591_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
sis_5591_log("SiS 5591: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5591_host_to_pci_write(addr, val, dev->h2p);
else if (func == 0x01)
sis_5513_ide_write(addr, val, dev->ide);
}
static uint8_t
sis_5591_read(int func, int addr, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5591_host_to_pci_read(addr, dev->h2p);
else if (func == 0x01)
ret = sis_5513_ide_read(addr, dev->ide);
sis_5591_log("SiS 5591: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5595_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
sis_5591_log("SiS 5595: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (func) {
case 0x00:
sis_5513_pci_to_isa_write(addr, val, dev->p2i);
break;
case 0x01:
sis_5595_pmu_write(addr, val, dev->pmu);
break;
case 0x02:
sis_5572_usb_write(addr, val, dev->usb);
break;
}
}
static uint8_t
sis_5595_read(int func, int addr, void *priv)
{
const sis_5591_t *dev = (sis_5591_t *) priv;
uint8_t ret = 0xff;
switch (func) {
case 0x00:
ret = sis_5513_pci_to_isa_read(addr, dev->p2i);
break;
case 0x01:
ret = sis_5595_pmu_read(addr, dev->pmu);
break;
case 0x02:
ret = sis_5572_usb_read(addr, dev->usb);
break;
}
sis_5591_log("SiS 5592: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5591_close(void *priv)
{
sis_5591_t *dev = (sis_5591_t *) priv;
free(dev);
}
static void *
sis_5591_init(UNUSED(const device_t *info))
{
sis_5591_t *dev = (sis_5591_t *) calloc(1, sizeof(sis_5591_t));
/* Device 0: SiS 5591 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5591_read, sis_5591_write, dev, &dev->nb_slot);
/* Device 1: SiS 5595 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5595_read, sis_5595_write, dev, &dev->sb_slot);
dev->sis = device_add(&sis_55xx_common_device);
dev->ide = device_add_linked(&sis_5591_5600_ide_device, dev->sis);
if (info->local)
dev->p2i = device_add_linked(&sis_5595_1997_p2i_device, dev->sis);
else
dev->p2i = device_add_linked(&sis_5595_p2i_device, dev->sis);
dev->h2p = device_add_linked(&sis_5591_h2p_device, dev->sis);
dev->usb = device_add_linked(&sis_5595_usb_device, dev->sis);
if (info->local)
dev->pmu = device_add_linked(&sis_5595_1997_pmu_device, dev->sis);
else
dev->pmu = device_add_linked(&sis_5595_pmu_device, dev->sis);
return dev;
}
const device_t sis_5591_1997_device = {
.name = "SiS 5591 (1997)",
.internal_name = "sis_5591_1997",
.flags = DEVICE_PCI,
.local = 1,
.init = sis_5591_init,
.close = sis_5591_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5591_device = {
.name = "SiS 5591",
.internal_name = "sis_5591",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5591_init,
.close = sis_5591_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5591.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,743 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 8890 Chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC_8890_LOG
int umc_8890_do_log = ENABLE_UMC_8890_LOG;
static void
umc_8890_log(const char *fmt, ...)
{
va_list ap;
if (umc_8890_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define umc_8890_log(fmt, ...)
#endif
typedef struct umc_8890_t {
uint8_t pci_slot;
uint8_t pci_conf[256]; /* PCI Registers */
int mem_state[2];
uint32_t smram_base;
smram_t *smram; /* SMRAM Handler */
} umc_8890_t;
static void
um8890_shadow(umc_8890_t *dev)
{
uint8_t flag;
uint16_t state;
flag = (dev->pci_conf[0x5f] & 0x0c) >> 2;
state = (flag & 1) ? (MEM_READ_INTERNAL | ((flag & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) :
(MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if ((dev->mem_state[1] ^ dev->pci_conf[0x5f]) & 0x0c) {
mem_set_mem_state_both(0xe0000, 0x10000, state);
dev->mem_state[1] = (dev->mem_state[1] & 0xf0) | (dev->pci_conf[0x5f] & 0x0f);
}
flag = (dev->pci_conf[0x5f] & 0xc0) >> 6;
state = (flag & 1) ? (MEM_READ_INTERNAL | ((flag & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) :
(MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if ((dev->mem_state[1] ^ dev->pci_conf[0x5f]) & 0xc0) {
mem_set_mem_state_both(0xf0000, 0x10000, state);
dev->mem_state[1] = (dev->mem_state[1] & 0x0f) | (dev->pci_conf[0x5f] & 0xf0);
}
for (uint8_t i = 0; i < 8; i++) {
state = (dev->pci_conf[0x5d] & (1 << i)) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) :
(MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if ((dev->mem_state[0] ^ dev->pci_conf[0x5d]) & (1 << i)) {
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, state);
dev->mem_state[0] = (dev->mem_state[0] & ~(1 << i)) | (dev->pci_conf[0x5d] & (1 << i));
}
}
flushmmucache_nopc();
}
static void
um8890_smram(umc_8890_t *dev)
{
smram_disable_all();
/* Bit 4, if set, enables SMRAM access outside SMM. SMRAM appears to be always enabled
in SMM, and is always set to A0000-BFFFF. */
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x20000, dev->pci_conf[0x65] & 0x10, 1);
}
static void
um8890_write(int func, int addr, uint8_t val, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
if (func == 0) switch (addr) {
case 0x04 ... 0x05:
case 0x0c ... 0x0d:
case 0x40 ... 0x5b:
case 0x60 ... 0x63:
case 0x66 ... 0xff:
dev->pci_conf[addr] = val;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf9);
break;
case 0x5c ... 0x5f:
dev->pci_conf[addr] = val;
um8890_shadow(dev);
break;
/* Register 64h, 16-bit:
Bit 12: SMRAM enabled outside SMM (1 = yes, 0 = no);
Bit 10: ???? (set by Award BIOS);
Bits 7- 0: SMM handler offset to SMBASE, shifted to the right by 14.
*/
case 0x64: case 0x65:
dev->pci_conf[addr] = val;
if (addr == 0x65)
um8890_smram(dev);
break;
}
umc_8890_log("UM8890: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
}
static uint8_t
um8890_read(int func, int addr, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
uint8_t ret = 0xff;
if (func == 0)
ret = dev->pci_conf[addr];
return ret;
}
static void
umc_8890_reset(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
/* Defaults */
dev->pci_conf[0x00] = 0x60; /* UMC */
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x91; /* 8891F */
dev->pci_conf[0x03] = 0x88;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x01;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x5c] = 0x00;
dev->pci_conf[0x5d] = 0x00;
dev->pci_conf[0x5e] = 0x00;
dev->pci_conf[0x5f] = 0x00;
dev->pci_conf[0x64] = 0x00;
dev->pci_conf[0x65] = 0x00;
um8890_shadow(dev);
um8890_smram(dev);
}
static void
umc_8890_close(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
umc_8890_init(const device_t *info)
{
umc_8890_t *dev = (umc_8890_t *) calloc(1, sizeof(umc_8890_t));
/* Device 0: UMC 8890 */
pci_add_card(PCI_ADD_NORTHBRIDGE, um8890_read, um8890_write, dev, &dev->pci_slot);
/* Port 92 */
device_add(&port_92_pci_device);
dev->smram = smram_add();
umc_8890_reset(dev);
return dev;
}
const device_t umc_8890_device = {
.name = "UMC 8890(8891BF/8892BF)",
.internal_name = "umc_8890",
.flags = DEVICE_PCI,
.local = 0x886a,
.init = umc_8890_init,
.close = umc_8890_close,
.reset = umc_8890_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/umc_8890.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,140 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ACC 2046/2168 chipset
*
*
*
* Authors: Sarah Walker, <path_to_url
* Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#define ENABLED_SHADOW (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL))
#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#define SHADOW_ADDR ((i <= 1) ? (0xc0000 + (i << 15)) : (0xd0000 + ((i - 2) << 16)))
#define SHADOW_SIZE ((i <= 1) ? 0x8000 : 0x10000)
#define SHADOW_RECALC ((dev->regs[0x02] & (1 << i)) ? ENABLED_SHADOW : DISABLED_SHADOW)
#ifdef ENABLE_ACC2168_LOG
int acc2168_do_log = ENABLE_ACC2168_LOG;
static void
acc2168_log(const char *fmt, ...)
{
va_list ap;
if (acc2168_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define acc2168_log(fmt, ...)
#endif
typedef struct acc2168_t {
uint8_t reg_idx;
uint8_t regs[256];
} acc2168_t;
static void
acc2168_shadow_recalc(acc2168_t *dev)
{
for (uint8_t i = 0; i < 5; i++)
mem_set_mem_state_both(SHADOW_ADDR, SHADOW_SIZE, SHADOW_RECALC);
}
static void
acc2168_write(uint16_t addr, uint8_t val, void *priv)
{
acc2168_t *dev = (acc2168_t *) priv;
switch (addr) {
case 0xf2:
dev->reg_idx = val;
break;
case 0xf3:
acc2168_log("ACC2168: dev->regs[%02x] = %02x\n", dev->reg_idx, val);
switch (dev->reg_idx) {
case 0x00:
dev->regs[dev->reg_idx] = val;
break;
case 0x01:
dev->regs[dev->reg_idx] = val & 0xd3;
cpu_update_waitstates();
break;
case 0x02:
dev->regs[dev->reg_idx] = val & 0x7f;
acc2168_shadow_recalc(dev);
break;
case 0x03:
dev->regs[dev->reg_idx] = val & 0x1f;
break;
case 0x04:
dev->regs[dev->reg_idx] = val;
cpu_cache_ext_enabled = !!(val & 0x01);
cpu_update_waitstates();
break;
case 0x05:
dev->regs[dev->reg_idx] = val & 0xf3;
break;
case 0x06:
case 0x07:
dev->regs[dev->reg_idx] = val & 0x1f;
break;
case 0x08:
dev->regs[dev->reg_idx] = val & 0x0f;
break;
case 0x09:
dev->regs[dev->reg_idx] = val & 0x03;
break;
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
case 0x10:
case 0x11:
dev->regs[dev->reg_idx] = val;
break;
case 0x12:
dev->regs[dev->reg_idx] = val & 0xbb;
break;
case 0x18:
dev->regs[dev->reg_idx] = val & 0x77;
break;
case 0x19:
dev->regs[dev->reg_idx] = val & 0xfb;
break;
case 0x1a:
dev->regs[dev->reg_idx] = val;
cpu_cache_int_enabled = !(val & 0x40);
cpu_update_waitstates();
break;
case 0x1b:
dev->regs[dev->reg_idx] = val & 0xef;
break;
default: /* ACC 2168 has way more registers which we haven't documented */
dev->regs[dev->reg_idx] = val;
break;
}
break;
default:
break;
}
}
static uint8_t
acc2168_read(uint16_t addr, void *priv)
{
const acc2168_t *dev = (acc2168_t *) priv;
return (addr == 0xf3) ? dev->regs[dev->reg_idx] : dev->reg_idx;
}
static void
acc2168_close(void *priv)
{
acc2168_t *dev = (acc2168_t *) priv;
free(dev);
}
static void *
acc2168_init(UNUSED(const device_t *info))
{
acc2168_t *dev = (acc2168_t *) malloc(sizeof(acc2168_t));
memset(dev, 0, sizeof(acc2168_t));
device_add(&port_92_device);
io_sethandler(0x00f2, 0x0002, acc2168_read, NULL, NULL, acc2168_write, NULL, NULL, dev);
return dev;
}
const device_t acc2168_device = {
.name = "ACC 2046/2168",
.internal_name = "acc2168",
.flags = 0,
.local = 0,
.init = acc2168_init,
.close = acc2168_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/acc2168.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,515 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5571 Host to PCI bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#include <86box/agpgart.h>
#ifdef ENABLE_SIS_5571_HOST_TO_PCI_LOG
int sis_5571_host_to_pci_do_log = ENABLE_SIS_5571_HOST_TO_PCI_LOG;
static void
sis_5571_host_to_pci_log(const char *fmt, ...)
{
va_list ap;
if (sis_5571_host_to_pci_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5571_host_to_pci_log(fmt, ...)
#endif
typedef struct sis_5571_host_to_pci_t {
uint8_t pci_conf[256];
uint8_t states[7];
sis_55xx_common_t *sis;
smram_t *smram;
} sis_5571_host_to_pci_t;
static void
sis_5571_shadow_recalc(sis_5571_host_to_pci_t *dev)
{
int state;
uint32_t base;
for (uint8_t i = 0x70; i <= 0x76; i++) {
if (i == 0x76) {
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xf0000, 0x10000, state);
sis_5571_host_to_pci_log("000F0000-000FFFFF\n");
}
} else {
base = ((i & 0x07) << 15) + 0xc0000;
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x4000, state);
sis_5571_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
}
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0x0a) {
state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base + 0x4000, 0x4000, state);
sis_5571_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
}
}
dev->states[i & 0x0f] = dev->pci_conf[i];
}
flushmmucache_nopc();
}
static void
sis_5571_smram_recalc(sis_5571_host_to_pci_t *dev)
{
smram_disable_all();
switch (dev->pci_conf[0xa3] >> 6) {
case 0:
smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 1:
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 3:
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0xa3] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
}
void
sis_5571_host_to_pci_write(int addr, uint8_t val, void *priv)
{
sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
sis_5571_host_to_pci_log("SiS 5571 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x04: /* Command - low byte */
case 0x05: /* Command - high byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfd) | (val & 0x02);
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= ~(val & 0xb8);
break;
case 0x0d: /* Master latency timer */
dev->pci_conf[addr] = val;
break;
case 0x50: /* Host Interface and DRAM arbiter */
dev->pci_conf[addr] = val & 0xec;
break;
case 0x51: /* CACHE */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val & 0xd0;
break;
case 0x53: /* DRAM */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x54: /* FP/EDO */
dev->pci_conf[addr] = val;
break;
case 0x55:
dev->pci_conf[addr] = val & 0xe0;
break;
case 0x56: /* MDLE delay */
dev->pci_conf[addr] = val & 0x07;
break;
case 0x57: /* SDRAM */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x59: /* Buffer strength and current rating */
dev->pci_conf[addr] = val;
break;
case 0x5a:
dev->pci_conf[addr] = val & 0x03;
break;
/* Undocumented - DRAM bank registers, the exact layout is currently unknown. */
case 0x60 ... 0x6b:
dev->pci_conf[addr] = val;
break;
case 0x70 ... 0x75:
dev->pci_conf[addr] = val & 0xee;
sis_5571_shadow_recalc(dev);
break;
case 0x76:
dev->pci_conf[addr] = val & 0xe8;
sis_5571_shadow_recalc(dev);
break;
case 0x77: /* Characteristics of non-cacheable area */
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x78: /* Allocation of Non-Cacheable area #1 */
case 0x79: /* NCA1REG2 */
case 0x7a: /* Allocation of Non-Cacheable area #2 */
case 0x7b: /* NCA2REG2 */
dev->pci_conf[addr] = val;
break;
case 0x80: /* PCI master characteristics */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x81:
dev->pci_conf[addr] = val & 0xcc;
break;
case 0x82:
dev->pci_conf[addr] = val;
break;
case 0x83: /* CPU to PCI characteristics */
dev->pci_conf[addr] = val;
/* TODO: Implement Fast A20 and Fast reset stuff on the KBC already! */
break;
case 0x84 ... 0x86:
dev->pci_conf[addr] = val;
break;
case 0x87: /* Miscellanea */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x90: /* PMU control register */
case 0x91: /* Address trap for green function */
case 0x92:
dev->pci_conf[addr] = val;
break;
case 0x93: /* STPCLK# and APM SMI control */
dev->pci_conf[addr] = val;
if ((dev->pci_conf[0x9b] & 0x01) && (val & 0x02)) {
smi_raise();
dev->pci_conf[0x9d] |= 0x01;
}
break;
case 0x94: /* 6x86 and Green function control */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x95: /* Test mode control */
case 0x96: /* Time slot and Programmable 10-bit I/O port definition */
dev->pci_conf[addr] = val & 0xfb;
break;
case 0x97: /* programmable 10-bit I/O port address */
case 0x98: /* Programmable 16-bit I/O port */
case 0x99 ... 0x9c:
dev->pci_conf[addr] = val;
break;
case 0x9d:
dev->pci_conf[addr] &= val;
break;
case 0x9e: /* STPCLK# Assertion Timer */
case 0x9f: /* STPCLK# De-assertion Timer */
case 0xa0 ... 0xa2:
dev->pci_conf[addr] = val;
break;
case 0xa3: /* SMRAM access control and Power supply control */
dev->pci_conf[addr] = val & 0xd0;
sis_5571_smram_recalc(dev);
break;
}
}
uint8_t
sis_5571_host_to_pci_read(int addr, void *priv)
{
const sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5571_host_to_pci_log("SiS 5571 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5571_host_to_pci_reset(void *priv)
{
sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x71;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = 0x05;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x00;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0x00;
dev->pci_conf[0x0e] = 0x00;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x50] = 0x00;
dev->pci_conf[0x51] = 0x00;
dev->pci_conf[0x52] = 0x00;
dev->pci_conf[0x53] = 0x00;
dev->pci_conf[0x54] = 0x54;
dev->pci_conf[0x55] = 0x54;
dev->pci_conf[0x56] = 0x03;
dev->pci_conf[0x57] = 0x00;
dev->pci_conf[0x58] = 0x00;
dev->pci_conf[0x59] = 0x00;
dev->pci_conf[0x5a] = 0x00;
/* Undocumented DRAM bank registers. */
dev->pci_conf[0x60] = dev->pci_conf[0x62] = 0x04;
dev->pci_conf[0x64] = dev->pci_conf[0x66] = 0x04;
dev->pci_conf[0x68] = dev->pci_conf[0x6a] = 0x04;
dev->pci_conf[0x61] = dev->pci_conf[0x65] = 0x00;
dev->pci_conf[0x63] = dev->pci_conf[0x67] = 0x80;
dev->pci_conf[0x69] = 0x00;
dev->pci_conf[0x6b] = 0x80;
dev->pci_conf[0x70] = 0x00;
dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = 0x00;
dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = 0x00;
dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x76] = 0x00;
dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x78] = 0x00;
dev->pci_conf[0x79] = 0x00;
dev->pci_conf[0x7a] = 0x00;
dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x80] = 0x00;
dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x82] = 0x00;
dev->pci_conf[0x83] = 0x00;
dev->pci_conf[0x84] = 0x00;
dev->pci_conf[0x85] = 0x00;
dev->pci_conf[0x86] = 0x00;
dev->pci_conf[0x87] = 0x00;
dev->pci_conf[0x8c] = 0x00;
dev->pci_conf[0x8d] = 0x00;
dev->pci_conf[0x8e] = 0x00;
dev->pci_conf[0x8f] = 0x00;
dev->pci_conf[0x90] = 0x00;
dev->pci_conf[0x91] = 0x00;
dev->pci_conf[0x92] = 0x00;
dev->pci_conf[0x93] = 0x00;
dev->pci_conf[0x93] = 0x00;
dev->pci_conf[0x94] = 0x00;
dev->pci_conf[0x95] = 0x00;
dev->pci_conf[0x96] = 0x00;
dev->pci_conf[0x97] = 0x00;
dev->pci_conf[0x98] = 0x00;
dev->pci_conf[0x99] = 0x00;
dev->pci_conf[0x9a] = 0x00;
dev->pci_conf[0x9b] = 0x00;
dev->pci_conf[0x9c] = 0x00;
dev->pci_conf[0x9d] = 0x00;
dev->pci_conf[0x9e] = 0xff;
dev->pci_conf[0x9f] = 0xff;
dev->pci_conf[0xa0] = 0xff;
dev->pci_conf[0xa1] = 0x00;
dev->pci_conf[0xa2] = 0xff;
dev->pci_conf[0xa3] = 0x00;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
sis_5571_smram_recalc(dev);
sis_5571_shadow_recalc(dev);
flushmmucache();
}
static void
sis_5571_host_to_pci_close(void *priv)
{
sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5571_host_to_pci_init(UNUSED(const device_t *info))
{
sis_5571_host_to_pci_t *dev = (sis_5571_host_to_pci_t *) calloc(1, sizeof(sis_5571_host_to_pci_t));
dev->sis = device_get_common_priv();
/* SMRAM */
dev->smram = smram_add();
sis_5571_host_to_pci_reset(dev);
return dev;
}
const device_t sis_5571_h2p_device = {
.name = "SiS 5571 Host to PCI bridge",
.internal_name = "sis_5571_host_to_pci",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5571_host_to_pci_init,
.close = sis_5571_host_to_pci_close,
.reset = sis_5571_host_to_pci_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5571_h2p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,539 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 450KX Mars Chipset.
*
* i450GX is way more popular of an option but needs more stuff.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
#ifdef ENABLE_450KX_LOG
int i450kx_do_log = ENABLE_450KX_LOG;
static void
i450kx_log(const char *fmt, ...)
{
va_list ap;
if (i450kx_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i450kx_log(fmt, ...)
#endif
/* TODO: Finish the bus index stuff. */
typedef struct i450kx_t {
smram_t *smram[2];
uint8_t bus_index;
uint8_t pb_slot;
uint8_t mc_slot;
uint8_t pad;
uint8_t pb_pci_conf[256];
uint8_t mc_pci_conf[256];
uint8_t mem_state[2][256];
} i450kx_t;
static void
i450kx_map(i450kx_t *dev, int bus, uint32_t addr, uint32_t size, int state)
{
uint32_t base = addr >> 12;
int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY,
MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL };
state &= 3;
if (dev->mem_state[bus][base] != state) {
if (bus)
mem_set_mem_state_bus_both(addr, size, states[state]);
else
mem_set_mem_state_cpu_both(addr, size, states[state]);
dev->mem_state[bus][base] = state;
flushmmucache_nopc();
}
}
static void
i450kx_smram_recalc(i450kx_t *dev, int bus)
{
const uint8_t *regs = bus ? dev->pb_pci_conf : dev->mc_pci_conf;
uint32_t addr;
uint32_t size;
int enable = bus ? !(regs[0x57] & 0x08) : (regs[0x57] & 0x08);
smram_disable(dev->smram[bus]);
addr = ((uint32_t) regs[0xb8] << 16) | ((uint32_t) regs[0xb9] << 24);
size = (((uint32_t) ((regs[0xbb] >> 4) & 0x0f)) << 16) + 0x00010000;
if ((addr != 0x00000000) && enable) {
if (bus)
smram_enable_ex(dev->smram[bus], addr, addr, size, 0, 0, 0, enable);
else
smram_enable_ex(dev->smram[bus], addr, addr, size, 0, 0, enable, 0);
}
flushmmucache();
}
static void
i450kx_vid_buf_recalc(i450kx_t *dev, int bus)
{
const uint8_t *regs = bus ? dev->pb_pci_conf : dev->mc_pci_conf;
int state = (regs[0x58] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) :
(MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (bus)
mem_set_mem_state_bus_both(0x000a0000, 0x00020000, state);
else
mem_set_mem_state_cpu_both(0x000a0000, 0x00020000, state);
flushmmucache_nopc();
}
static void
pb_write(int func, int addr, uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
if (func == 0) {
i450kx_log("[%04X:%08X] i450KX-PB: [W] dev->pb_pci_conf[%02X] = %02X\n", CS, cpu_state.pc,
addr, val);
switch (addr) {
case 0x04:
dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x04) | (val & 0x53);
break;
case 0x05:
dev->pb_pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pb_pci_conf[addr] &= ~(val & 0xf9);
break;
case 0x0d:
dev->pb_pci_conf[addr] = val;
break;
case 0x0f:
dev->pb_pci_conf[addr] = val & 0xcf;
break;
case 0x40:
case 0x41:
dev->pb_pci_conf[addr] = val;
break;
case 0x43:
dev->pb_pci_conf[addr] = val & 0x80;
break;
case 0x48:
dev->pb_pci_conf[addr] = val & 0x06;
break;
case 0x4a:
case 0x4b:
dev->pb_pci_conf[addr] = val;
#if 0
if (addr == 0x4a)
pci_remap_bus(dev->bus_index, val);
#endif
break;
case 0x4c:
dev->pb_pci_conf[addr] = (dev->pb_pci_conf[addr] & 0x01) | (val & 0xd8);
break;
case 0x51:
dev->pb_pci_conf[addr] = val;
break;
case 0x53:
dev->pb_pci_conf[addr] = val & 0x02;
break;
case 0x54:
dev->pb_pci_conf[addr] = val & 0x7b;
break;
case 0x55:
dev->pb_pci_conf[addr] = val & 0x03;
break;
case 0x57:
dev->pb_pci_conf[addr] = val & 0x08;
i450kx_smram_recalc(dev, 1);
break;
case 0x58:
dev->pb_pci_conf[addr] = val & 0x02;
i450kx_vid_buf_recalc(dev, 1);
break;
case 0x59: /* PAM0 */
if ((dev->pb_pci_conf[0x59] ^ val) & 0x0f)
i450kx_map(dev, 1, 0x80000, 0x20000, val & 0x0f);
if ((dev->pb_pci_conf[0x59] ^ val) & 0xf0) {
i450kx_map(dev, 1, 0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
dev->pb_pci_conf[0x59] = val & 0x33;
break;
case 0x5a: /* PAM1 */
if ((dev->pb_pci_conf[0x5a] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xc0000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5a] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xc4000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5a] = val & 0x33;
break;
case 0x5b: /*PAM2 */
if ((dev->pb_pci_conf[0x5b] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xc8000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5b] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xcc000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5b] = val & 0x33;
break;
case 0x5c: /*PAM3 */
if ((dev->pb_pci_conf[0x5c] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xd0000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5c] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xd4000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5c] = val & 0x33;
break;
case 0x5d: /* PAM4 */
if ((dev->pb_pci_conf[0x5d] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xd8000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5d] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xdc000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5d] = val & 0x33;
break;
case 0x5e: /* PAM5 */
if ((dev->pb_pci_conf[0x5e] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xe0000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5e] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xe4000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5e] = val & 0x33;
break;
case 0x5f: /* PAM6 */
if ((dev->pb_pci_conf[0x5f] ^ val) & 0x0f)
i450kx_map(dev, 1, 0xe8000, 0x04000, val & 0xf);
if ((dev->pb_pci_conf[0x5f] ^ val) & 0xf0)
i450kx_map(dev, 1, 0xec000, 0x04000, val >> 4);
dev->pb_pci_conf[0x5f] = val & 0x33;
break;
case 0x70:
dev->pb_pci_conf[addr] = val & 0xf8;
break;
case 0x71:
dev->pb_pci_conf[addr] = val & 0x71;
break;
case 0x78:
dev->pb_pci_conf[addr] = val & 0xf0;
break;
case 0x79:
dev->pb_pci_conf[addr] = val & 0xfc;
break;
case 0x7a:
dev->pb_pci_conf[addr] = val;
break;
case 0x7b:
dev->pb_pci_conf[addr] = val & 0x0f;
break;
case 0x7c:
dev->pb_pci_conf[addr] = val & 0x9f;
break;
case 0x7d:
dev->pb_pci_conf[addr] = val & 0x1a;
break;
case 0x7e:
dev->pb_pci_conf[addr] = val & 0xf0;
break;
case 0x7f:
dev->pb_pci_conf[addr] = val;
break;
case 0x88:
case 0x89:
dev->pb_pci_conf[addr] = val;
break;
case 0x8b:
dev->pb_pci_conf[addr] = val & 0x80;
break;
case 0x8c:
case 0x8d:
dev->pb_pci_conf[addr] = val;
break;
case 0x9c:
dev->pb_pci_conf[addr] = val & 0x01;
break;
case 0xa4:
dev->pb_pci_conf[addr] = val & 0xf8;
break;
case 0xa5:
case 0xa6:
dev->pb_pci_conf[addr] = val;
break;
case 0xa7:
dev->pb_pci_conf[addr] = val & 0x0f;
break;
case 0xb0:
dev->pb_pci_conf[addr] = val & 0xe0;
break;
case 0xb1:
dev->pb_pci_conf[addr] = val & /*0x1a*/ 0x1f;
break;
case 0xb8:
case 0xb9:
dev->pb_pci_conf[addr] = val;
i450kx_smram_recalc(dev, 1);
break;
case 0xbb:
dev->pb_pci_conf[addr] = val & 0xf0;
i450kx_smram_recalc(dev, 1);
break;
case 0xbc:
dev->pb_pci_conf[addr] = val & 0x11;
break;
case 0xc0:
dev->pb_pci_conf[addr] = val & 0xdf;
break;
case 0xc1:
dev->pb_pci_conf[addr] = val & 0x3f;
break;
case 0xc4:
dev->pb_pci_conf[addr] &= ~(val & 0x0f);
break;
case 0xc5:
dev->pb_pci_conf[addr] &= ~(val & 0x0a);
break;
case 0xc6:
dev->pb_pci_conf[addr] &= ~(val & 0x1f);
break;
case 0xc8:
dev->pb_pci_conf[addr] = val & 0x1f;
break;
case 0xca:
case 0xcb:
dev->pb_pci_conf[addr] = val;
break;
default:
break;
}
}
}
static uint8_t
pb_read(int func, int addr, void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
if (func == 0) {
ret = dev->pb_pci_conf[addr];
i450kx_log("[%04X:%08X] i450KX-PB: [R] dev->pb_pci_conf[%02X] = %02X\n", CS, cpu_state.pc,
addr, ret);
}
return ret;
}
/* A way to use spd_write_drbs_interlaved() and convert the output to what we need. */
static void
mc_fill_drbs(i450kx_t *dev)
{
spd_write_drbs_interleaved(dev->mc_pci_conf, 0x60, 0x6f, 4);
for (uint8_t i = 0x60; i <= 0x6f; i++) {
if (i & 0x01)
dev->mc_pci_conf[i] = 0x00;
else
dev->mc_pci_conf[i] &= 0x7f;
}
}
static void
mc_write(int func, int addr, uint8_t val, void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
if (func == 0) {
i450kx_log("[%04X:%08X] i450KX-MC: [W] dev->mc_pci_conf[%02X] = %02X\n", CS, cpu_state.pc,
addr, val);
switch (addr) {
case 0x4c:
dev->mc_pci_conf[addr] = val & 0xdf;
break;
case 0x4d:
dev->mc_pci_conf[addr] = val & 0xff;
break;
case 0x57:
dev->mc_pci_conf[addr] = val & 0x08;
i450kx_smram_recalc(dev, 0);
break;
case 0x58:
dev->mc_pci_conf[addr] = val & 0x02;
i450kx_vid_buf_recalc(dev, 0);
break;
case 0x59: /* PAM0 */
if ((dev->mc_pci_conf[0x59] ^ val) & 0x0f)
i450kx_map(dev, 0, 0x80000, 0x20000, val & 0x0f);
if ((dev->mc_pci_conf[0x59] ^ val) & 0xf0) {
i450kx_map(dev, 0, 0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
dev->mc_pci_conf[0x59] = val & 0x33;
break;
case 0x5a: /* PAM1 */
if ((dev->mc_pci_conf[0x5a] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xc0000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5a] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xc4000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5a] = val & 0x33;
break;
case 0x5b: /*PAM2 */
if ((dev->mc_pci_conf[0x5b] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xc8000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5b] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xcc000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5b] = val & 0x33;
break;
case 0x5c: /*PAM3 */
if ((dev->mc_pci_conf[0x5c] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xd0000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5c] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xd4000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5c] = val & 0x33;
break;
case 0x5d: /* PAM4 */
if ((dev->mc_pci_conf[0x5d] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xd8000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5d] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xdc000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5d] = val & 0x33;
break;
case 0x5e: /* PAM5 */
if ((dev->mc_pci_conf[0x5e] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xe0000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5e] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xe4000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5e] = val & 0x33;
break;
case 0x5f: /* PAM6 */
if ((dev->mc_pci_conf[0x5f] ^ val) & 0x0f)
i450kx_map(dev, 0, 0xe8000, 0x04000, val & 0xf);
if ((dev->mc_pci_conf[0x5f] ^ val) & 0xf0)
i450kx_map(dev, 0, 0xec000, 0x04000, val >> 4);
dev->mc_pci_conf[0x5f] = val & 0x33;
break;
case 0x60 ... 0x6f:
dev->mc_pci_conf[addr] = ((addr & 0x0f) & 0x01) ? 0x00 : (val & 0x7f);
mc_fill_drbs(dev);
break;
case 0x74 ... 0x77:
dev->mc_pci_conf[addr] = val;
break;
case 0x78:
dev->mc_pci_conf[addr] = val & 0xf0;
break;
case 0x79:
dev->mc_pci_conf[addr] = val & 0xfe;
break;
case 0x7a:
dev->mc_pci_conf[addr] = val;
break;
case 0x7b:
dev->mc_pci_conf[addr] = val & 0x0f;
break;
case 0x7c:
dev->mc_pci_conf[addr] = val & 0x1f;
break;
case 0x7d:
dev->mc_pci_conf[addr] = val & 0x0c;
break;
case 0x7e:
dev->mc_pci_conf[addr] = val & 0xf0;
break;
case 0x7f:
dev->mc_pci_conf[addr] = val;
break;
case 0x88:
case 0x89:
dev->mc_pci_conf[addr] = val;
break;
case 0x8b:
dev->mc_pci_conf[addr] = val & 0x80;
break;
case 0x8c:
case 0x8d:
dev->mc_pci_conf[addr] = val;
break;
case 0xa4:
dev->mc_pci_conf[addr] = val & 0x01;
break;
case 0xa5:
dev->pb_pci_conf[addr] = val & 0xf0;
break;
case 0xa6:
dev->mc_pci_conf[addr] = val;
break;
case 0xa7:
dev->mc_pci_conf[addr] = val & 0x0f;
break;
case 0xa8:
dev->mc_pci_conf[addr] = val & 0xfe;
break;
case 0xa9 ... 0xab:
dev->mc_pci_conf[addr] = val;
break;
case 0xac ... 0xae:
dev->mc_pci_conf[addr] = val;
break;
case 0xaf:
dev->mc_pci_conf[addr] = val & 0x7f;
break;
case 0xb8:
case 0xb9:
dev->mc_pci_conf[addr] = val;
i450kx_smram_recalc(dev, 0);
break;
case 0xbb:
dev->mc_pci_conf[addr] = val & 0xf0;
i450kx_smram_recalc(dev, 0);
break;
case 0xbc:
dev->mc_pci_conf[addr] = val & 0x01;
break;
case 0xc0:
dev->mc_pci_conf[addr] = val & 0x07;
break;
case 0xc2:
dev->mc_pci_conf[addr] &= ~(val & 0x03);
break;
case 0xc4:
dev->mc_pci_conf[addr] = val & 0xbf;
break;
case 0xc5:
dev->mc_pci_conf[addr] = val & 0x03;
break;
case 0xc6:
dev->mc_pci_conf[addr] &= ~(val & 0x19);
break;
case 0xc8:
dev->mc_pci_conf[addr] = val & 0x1f;
break;
case 0xca:
case 0xcb:
dev->mc_pci_conf[addr] = val;
break;
default:
break;
}
}
}
static uint8_t
mc_read(int func, int addr, void *priv)
{
const i450kx_t *dev = (i450kx_t *) priv;
uint8_t ret = 0xff;
if (func == 0) {
ret = dev->mc_pci_conf[addr];
i450kx_log("[%04X:%08X] i450KX-MC: [R] dev->mc_pci_conf[%02X] = %02X\n", CS, cpu_state.pc,
addr, ret);
}
return ret;
}
static void
i450kx_reset(void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
uint32_t i;
/* Defaults PB */
dev->pb_pci_conf[0x00] = 0x86;
dev->pb_pci_conf[0x01] = 0x80;
dev->pb_pci_conf[0x02] = 0xc4;
dev->pb_pci_conf[0x03] = 0x84;
dev->pb_pci_conf[0x04] = 0x07;
dev->pb_pci_conf[0x05] = 0x00;
dev->pb_pci_conf[0x06] = 0x40;
dev->pb_pci_conf[0x07] = 0x02;
dev->pb_pci_conf[0x08] = 0x02;
dev->pb_pci_conf[0x09] = 0x00;
dev->pb_pci_conf[0x0a] = 0x00;
dev->pb_pci_conf[0x0b] = 0x06;
dev->pb_pci_conf[0x0c] = 0x08;
dev->pb_pci_conf[0x0d] = 0x20;
dev->pb_pci_conf[0x0e] = 0x00;
dev->pb_pci_conf[0x0f] = 0x00;
dev->pb_pci_conf[0x40] = 0x00;
dev->pb_pci_conf[0x41] = 0x00;
dev->pb_pci_conf[0x42] = 0x00;
dev->pb_pci_conf[0x43] = 0x00;
dev->pb_pci_conf[0x48] = 0x06;
dev->pb_pci_conf[0x49] = 0x19;
dev->pb_pci_conf[0x4a] = 0x00;
dev->pb_pci_conf[0x4b] = 0x00;
dev->pb_pci_conf[0x4c] = 0x19;
dev->pb_pci_conf[0x51] = 0x80;
dev->pb_pci_conf[0x53] = 0x00;
dev->pb_pci_conf[0x54] = 0x00;
dev->pb_pci_conf[0x55] = 0x00;
dev->pb_pci_conf[0x57] = 0x00;
dev->pb_pci_conf[0x58] = 0x02;
dev->pb_pci_conf[0x70] = 0x00;
dev->pb_pci_conf[0x71] = 0x00;
dev->pb_pci_conf[0x78] = 0x00;
dev->pb_pci_conf[0x79] = 0x00;
dev->pb_pci_conf[0x7a] = 0x00;
dev->pb_pci_conf[0x7b] = 0x00;
dev->pb_pci_conf[0x7c] = 0x00;
dev->pb_pci_conf[0x7d] = 0x00;
dev->pb_pci_conf[0x7e] = 0x00;
dev->pb_pci_conf[0x7f] = 0x00;
dev->pb_pci_conf[0x88] = 0x00;
dev->pb_pci_conf[0x89] = 0x00;
dev->pb_pci_conf[0x8a] = 0x00;
dev->pb_pci_conf[0x8b] = 0x00;
dev->pb_pci_conf[0x8c] = 0x00;
dev->pb_pci_conf[0x8d] = 0x00;
dev->pb_pci_conf[0x8e] = 0x00;
dev->pb_pci_conf[0x8f] = 0x00;
dev->pb_pci_conf[0x9c] = 0x00;
dev->pb_pci_conf[0xa4] = 0x01;
dev->pb_pci_conf[0xa5] = 0xc0;
dev->pb_pci_conf[0xa6] = 0xfe;
dev->pb_pci_conf[0xa7] = 0x00;
/* Note: Do NOT reset these two registers on programmed (TRC) hard reset! */
#if 0
dev->pb_pci_conf[0xb0] = 0x00;
dev->pb_pci_conf[0xb1] = 0x00;
#endif
dev->pb_pci_conf[0xb4] = 0xff;
dev->pb_pci_conf[0xb5] = 0x00;
dev->pb_pci_conf[0xb8] = 0x05;
dev->pb_pci_conf[0xb9] = 0x00;
dev->pb_pci_conf[0xba] = 0x00;
dev->pb_pci_conf[0xbb] = 0x00;
dev->pb_pci_conf[0xbc] = 0x01;
dev->pb_pci_conf[0xc0] = 0x02;
dev->pb_pci_conf[0xc1] = 0x00;
dev->pb_pci_conf[0xc2] = 0x00;
dev->pb_pci_conf[0xc3] = 0x00;
dev->pb_pci_conf[0xc4] = 0x00;
dev->pb_pci_conf[0xc5] = 0x00;
dev->pb_pci_conf[0xc6] = 0x00;
dev->pb_pci_conf[0xc7] = 0x00;
dev->pb_pci_conf[0xc8] = 0x03;
dev->pb_pci_conf[0xc9] = 0x00;
dev->pb_pci_conf[0xca] = 0x00;
dev->pb_pci_conf[0xcb] = 0x00;
#if 0
pci_remap_bus(dev->bus_index, 0x00);
#endif
i450kx_smram_recalc(dev, 1);
i450kx_vid_buf_recalc(dev, 1);
pb_write(0, 0x59, 0x30, dev);
for (i = 0x5a; i <= 0x5f; i++)
pb_write(0, i, 0x33, dev);
/* Defaults MC */
dev->mc_pci_conf[0x00] = 0x86;
dev->mc_pci_conf[0x01] = 0x80;
dev->mc_pci_conf[0x02] = 0xc5;
dev->mc_pci_conf[0x03] = 0x84;
dev->mc_pci_conf[0x04] = 0x00;
dev->mc_pci_conf[0x05] = 0x00;
dev->mc_pci_conf[0x06] = 0x80;
dev->mc_pci_conf[0x07] = 0x00;
dev->mc_pci_conf[0x08] = 0x04;
dev->mc_pci_conf[0x09] = 0x00;
dev->mc_pci_conf[0x0a] = 0x00;
dev->mc_pci_conf[0x0b] = 0x05;
dev->mc_pci_conf[0x49] = 0x14;
dev->mc_pci_conf[0x4c] = 0x0b;
dev->mc_pci_conf[0x4d] = 0x08;
dev->mc_pci_conf[0x4e] = 0x00;
dev->mc_pci_conf[0x4f] = 0x00;
dev->mc_pci_conf[0x57] = 0x00;
dev->mc_pci_conf[0x58] = 0x00;
dev->mc_pci_conf[0x74] = 0x00;
dev->mc_pci_conf[0x75] = 0x00;
dev->mc_pci_conf[0x76] = 0x00;
dev->mc_pci_conf[0x77] = 0x00;
dev->mc_pci_conf[0x78] = 0x10;
dev->mc_pci_conf[0x79] = 0x00;
dev->mc_pci_conf[0x7a] = 0x00;
dev->mc_pci_conf[0x7b] = 0x00;
dev->mc_pci_conf[0x7c] = 0x00;
dev->mc_pci_conf[0x7d] = 0x00;
dev->mc_pci_conf[0x7e] = 0x10;
dev->mc_pci_conf[0x7f] = 0x00;
dev->mc_pci_conf[0x88] = 0x00;
dev->mc_pci_conf[0x89] = 0x00;
dev->mc_pci_conf[0x8a] = 0x00;
dev->mc_pci_conf[0x8b] = 0x00;
dev->mc_pci_conf[0x8c] = 0x00;
dev->mc_pci_conf[0x8d] = 0x00;
dev->mc_pci_conf[0x8e] = 0x00;
dev->mc_pci_conf[0x8f] = 0x00;
dev->mc_pci_conf[0xa4] = 0x01;
dev->mc_pci_conf[0xa5] = 0xc0;
dev->mc_pci_conf[0xa6] = 0xfe;
dev->mc_pci_conf[0xa7] = 0x00;
dev->mc_pci_conf[0xa8] = 0x00;
dev->mc_pci_conf[0xa9] = 0x00;
dev->mc_pci_conf[0xaa] = 0x00;
dev->mc_pci_conf[0xab] = 0x00;
dev->mc_pci_conf[0xac] = 0x16;
dev->mc_pci_conf[0xad] = 0x35;
dev->mc_pci_conf[0xae] = 0xdf;
dev->mc_pci_conf[0xaf] = 0x30;
dev->mc_pci_conf[0xb8] = 0x0a;
dev->mc_pci_conf[0xb9] = 0x00;
dev->mc_pci_conf[0xba] = 0x00;
dev->mc_pci_conf[0xbb] = 0x00;
dev->mc_pci_conf[0xbc] = 0x01;
dev->mc_pci_conf[0xc0] = 0x00;
dev->mc_pci_conf[0xc1] = 0x00;
dev->mc_pci_conf[0xc2] = 0x00;
dev->mc_pci_conf[0xc3] = 0x00;
dev->mc_pci_conf[0xc4] = 0x00;
dev->mc_pci_conf[0xc5] = 0x00;
dev->mc_pci_conf[0xc6] = 0x00;
dev->mc_pci_conf[0xc7] = 0x00;
i450kx_smram_recalc(dev, 0);
i450kx_vid_buf_recalc(dev, 0);
mc_write(0, 0x59, 0x03, dev);
for (i = 0x5a; i <= 0x5f; i++)
mc_write(0, i, 0x00, dev);
for (i = 0x60; i <= 0x6f; i++)
dev->mc_pci_conf[i] = 0x01;
}
static void
i450kx_close(void *priv)
{
i450kx_t *dev = (i450kx_t *) priv;
smram_del(dev->smram[1]);
smram_del(dev->smram[0]);
free(dev);
}
static void *
i450kx_init(UNUSED(const device_t *info))
{
i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t));
memset(dev, 0, sizeof(i450kx_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev, &dev->pb_slot); /* Device 19h: Intel 450KX PCI Bridge PB */
pci_add_card(PCI_ADD_NORTHBRIDGE_SEC, mc_read, mc_write, dev, &dev->mc_slot); /* Device 14h: Intel 450KX Memory Controller MC */
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();
cpu_cache_int_enabled = 1;
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
i450kx_reset(dev);
return dev;
}
const device_t i450kx_device = {
.name = "Intel 450KX (Mars)",
.internal_name = "i450kx",
.flags = DEVICE_PCI,
.local = 0,
.init = i450kx_init,
.close = i450kx_close,
.reset = i450kx_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_i450kx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,067 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Contaq/Cypress 82C596(A) and 597 chipsets.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_CONTAQ_82C59X_LOG
int contaq_82c59x_do_log = ENABLE_CONTAQ_82C59X_LOG;
static void
contaq_82c59x_log(const char *fmt, ...)
{
va_list ap;
if (contaq_82c59x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define contaq_82c59x_log(fmt, ...)
#endif
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct contaq_82c59x_t {
uint8_t index;
uint8_t green;
uint8_t smi_status_set;
uint8_t regs[256];
uint8_t smi_status[2];
smram_t *smram[2];
} contaq_82c59x_t;
static void
contaq_82c59x_isa_speed_recalc(contaq_82c59x_t *dev)
{
if (dev->regs[0x1c] & 0x02)
cpu_set_isa_speed(7159091);
else {
/* TODO: ISA clock dividers for 386 and alt. 486. */
switch (dev->regs[0x10] & 0x03) {
case 0x00:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 0x01:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
case 0x02:
cpu_set_isa_speed(cpu_busspeed / 8);
break;
case 0x03:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
default:
break;
}
}
}
static void
contaq_82c59x_shadow_recalc(contaq_82c59x_t *dev)
{
uint32_t i;
uint32_t base;
uint8_t bit;
shadowbios = shadowbios_write = 0;
/* F0000-FFFFF */
if (dev->regs[0x15] & 0x80) {
shadowbios |= 1;
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
} else {
shadowbios_write |= 1;
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
/* C0000-CFFFF */
if (dev->regs[0x15] & 0x01)
mem_set_mem_state_both(0xc0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else {
for (i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
bit = 1 << (i + 2);
if (dev->regs[0x15] & bit) {
if (dev->regs[0x15] & 0x02)
mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
else
mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
} else
mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
if (dev->green) {
/* D0000-DFFFF */
if (dev->regs[0x6e] & 0x01)
mem_set_mem_state_both(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else {
for (i = 0; i < 4; i++) {
base = 0xd0000 + (i << 14);
bit = 1 << (i + 2);
if (dev->regs[0x6e] & bit) {
if (dev->regs[0x6e] & 0x02)
mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
else
mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else
mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
/* E0000-EFFFF */
if (dev->regs[0x6f] & 0x01)
mem_set_mem_state_both(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else {
for (i = 0; i < 4; i++) {
base = 0xe0000 + (i << 14);
bit = 1 << (i + 2);
if (dev->regs[0x6f] & bit) {
shadowbios |= 1;
if (dev->regs[0x6f] & 0x02)
mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
else {
shadowbios_write |= 1;
mem_set_mem_state_both(base, 0x04000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
} else
mem_set_mem_state_both(base, 0x04000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
}
}
}
}
static void
contaq_82c59x_smram_recalc(contaq_82c59x_t *dev)
{
smram_disable(dev->smram[1]);
if (dev->regs[0x70] & 0x04)
smram_enable(dev->smram[1], 0x00040000, 0x000a0000, 0x00020000, 1, 1);
}
static void
contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
{
contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
contaq_82c59x_log("Contaq 82C59x: dev->regs[%02x] = %02x\n", dev->index, val);
if ((dev->index >= 0x60) && !dev->green)
return;
switch (dev->index) {
/* Registers common to 82C596(A) and 82C597. */
case 0x10:
dev->regs[dev->index] = val;
contaq_82c59x_isa_speed_recalc(dev);
break;
case 0x11:
dev->regs[dev->index] = val;
cpu_cache_int_enabled = !!(val & 0x01);
cpu_update_waitstates();
break;
case 0x12:
case 0x13:
dev->regs[dev->index] = val;
break;
case 0x14:
dev->regs[dev->index] = val;
reset_on_hlt = !!(val & 0x80);
break;
case 0x15:
dev->regs[dev->index] = val;
contaq_82c59x_shadow_recalc(dev);
break;
case 0x16 ... 0x1b:
dev->regs[dev->index] = val;
break;
case 0x1c:
/* TODO: What's NPRST (generated if bit 3 is set)? */
dev->regs[dev->index] = val;
contaq_82c59x_isa_speed_recalc(dev);
break;
case 0x1d ... 0x1f:
dev->regs[dev->index] = val;
break;
/* Green (82C597-specific) registers. */
case 0x60 ... 0x63:
dev->regs[dev->index] = val;
break;
case 0x64:
dev->regs[dev->index] = val;
if (val & 0x80) {
if (dev->regs[0x65] & 0x80)
smi_raise();
dev->smi_status[0] |= 0x10;
}
break;
case 0x65 ... 0x69:
dev->regs[dev->index] = val;
break;
case 0x6a:
dev->regs[dev->index] = val;
dev->smi_status_set = !!(val & 0x80);
break;
case 0x6b ... 0x6d:
dev->regs[dev->index] = val;
break;
case 0x6e:
case 0x6f:
dev->regs[dev->index] = val;
contaq_82c59x_shadow_recalc(dev);
break;
case 0x70:
dev->regs[dev->index] = val;
contaq_82c59x_smram_recalc(dev);
break;
case 0x71 ... 0x79:
dev->regs[dev->index] = val;
break;
case 0x7b:
case 0x7c:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
contaq_82c59x_read(uint16_t addr, void *priv)
{
contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
uint8_t ret = 0xff;
if (addr == 0x23) {
if (dev->index == 0x6a) {
ret = dev->smi_status[dev->smi_status_set];
/* I assume it's cleared on read. */
dev->smi_status[dev->smi_status_set] = 0x00;
} else
ret = dev->regs[dev->index];
}
return ret;
}
static void
contaq_82c59x_close(void *priv)
{
contaq_82c59x_t *dev = (contaq_82c59x_t *) priv;
if (dev->green) {
smram_del(dev->smram[1]);
smram_del(dev->smram[0]);
}
free(dev);
}
static void *
contaq_82c59x_init(const device_t *info)
{
contaq_82c59x_t *dev = (contaq_82c59x_t *) malloc(sizeof(contaq_82c59x_t));
memset(dev, 0x00, sizeof(contaq_82c59x_t));
dev->green = info->local;
io_sethandler(0x0022, 0x0002, contaq_82c59x_read, NULL, NULL, contaq_82c59x_write, NULL, NULL, dev);
contaq_82c59x_isa_speed_recalc(dev);
cpu_cache_int_enabled = 0;
cpu_update_waitstates();
reset_on_hlt = 0;
contaq_82c59x_shadow_recalc(dev);
if (dev->green) {
/* SMRAM 0: Fixed A0000-BFFFF to A0000-BFFFF DRAM. */
dev->smram[0] = smram_add();
smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x00020000, 0, 1);
/* SMRAM 1: Optional. */
dev->smram[1] = smram_add();
contaq_82c59x_smram_recalc(dev);
}
return dev;
}
const device_t contaq_82c596a_device = {
.name = "Contaq 82C596A",
.internal_name = "contaq_82c596a",
.flags = 0,
.local = 0,
.init = contaq_82c59x_init,
.close = contaq_82c59x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t contaq_82c597_device = {
.name = "Contaq 82C597",
.internal_name = "contaq_82c597",
.flags = 0,
.local = 1,
.init = contaq_82c59x_init,
.close = contaq_82c59x_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/contaq_82c59x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,130 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the VIA PIPC southbridges.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/scsi_device.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/acpi.h>
#include <86box/ddma.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/usb.h>
#include <86box/machine.h>
#include <86box/smbus.h>
#include <86box/chipset.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/gameport.h>
#include <86box/sound.h>
#include <86box/snd_ac97.h>
#include <86box/snd_sb.h>
#include <86box/nmi.h>
/* Most revision numbers (PCI-ISA bridge or otherwise) were lifted from PCI device
listings on forums, as VIA's datasheets are not very helpful regarding those. */
#define VIA_PIPC_586A 0x05862500
#define VIA_PIPC_586B 0x05864700
#define VIA_PIPC_596A 0x05960900
#define VIA_PIPC_596B 0x05962300
#define VIA_PIPC_686A 0x06861400
#define VIA_PIPC_686B 0x06864000
#define VIA_PIPC_8231 0x82311000
#define VIA_PIPC_FM_EMULATION 1
enum {
TRAP_DRQ = 0,
TRAP_PIRQ,
TRAP_PIDE_MAIN,
TRAP_PIDE_SIDE,
TRAP_SIDE_MAIN,
TRAP_SIDE_SIDE,
TRAP_FLP_MAIN,
TRAP_FLP_SIDE,
TRAP_COM1,
TRAP_COM3,
TRAP_COM2,
TRAP_COM4,
TRAP_LPT1,
TRAP_LPT2,
TRAP_VGA,
TRAP_KBC,
TRAP_AUD_MIDI_0,
TRAP_AUD_MIDI_1,
TRAP_AUD_MIDI_2,
TRAP_AUD_MIDI_3,
TRAP_AUD_SB_0,
TRAP_AUD_SB_1,
TRAP_AUD_SB_2,
TRAP_AUD_SB_3,
TRAP_AUD_GAME,
TRAP_AUD_WSS_0,
TRAP_AUD_WSS_1,
TRAP_AUD_WSS_2,
TRAP_AUD_WSS_3,
TRAP_GR0,
TRAP_GR1,
TRAP_GR2,
TRAP_GR3,
TRAP_MAX
};
typedef struct {
struct _pipc_ *dev;
void *trap;
uint32_t *sts_reg;
uint32_t *en_reg;
uint32_t mask;
} pipc_io_trap_t;
typedef struct _pipc_ {
uint8_t max_func;
uint8_t max_pcs;
uint8_t pci_slot;
uint8_t pad;
uint8_t pci_isa_regs[256];
uint8_t ide_regs[256];
uint8_t usb_regs[2][256];
uint8_t power_regs[256];
uint8_t ac97_regs[2][256];
uint8_t fmnmi_regs[4];
uint8_t fmnmi_status;
uint32_t local;
sff8038i_t *bm[2];
nvr_t *nvr;
int nvr_enabled;
ddma_t *ddma;
smbus_piix4_t *smbus;
usb_t *usb[2];
acpi_t *acpi;
pipc_io_trap_t io_traps[TRAP_MAX];
void *gameport;
void *ac97;
void *sio;
void *hwm;
sb_t *sb;
uint16_t midigame_base;
uint16_t sb_base;
uint16_t fmnmi_base;
} pipc_t;
#ifdef ENABLE_PIPC_LOG
int pipc_do_log = ENABLE_PIPC_LOG;
static void
pipc_log(const char *fmt, ...)
{
va_list ap;
if (pipc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pipc_log(fmt, ...)
#endif
static void pipc_sgd_handlers(pipc_t *dev, uint8_t modem);
static void pipc_codec_handlers(pipc_t *dev, uint8_t modem);
static void pipc_sb_handlers(pipc_t *dev, uint8_t modem);
static uint8_t pipc_read(int func, int addr, void *priv);
static void pipc_write(int func, int addr, uint8_t val, void *priv);
static void
pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;
if (*(trap->en_reg) & trap->mask) {
*(trap->sts_reg) |= trap->mask;
trap->dev->acpi->regs.glbsts |= 0x0001;
if (trap->dev->acpi->regs.glben & 0x0001)
acpi_raise_smi(trap->dev->acpi, 1);
}
}
static void
pipc_io_trap_glb(UNUSED(int size), UNUSED(uint16_t addr), uint8_t write, UNUSED(uint8_t val), void *priv)
{
pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;
if (*(trap->en_reg) & trap->mask) {
*(trap->sts_reg) |= trap->mask;
if (trap->dev->local >= VIA_PIPC_686A) {
if (write)
trap->dev->acpi->regs.extsmi_val |= 0x1000;
else
trap->dev->acpi->regs.extsmi_val &= ~0x1000;
}
acpi_raise_smi(trap->dev->acpi, 1);
}
}
static void
pipc_reset_hard(void *priv)
{
int i;
pipc_log("PIPC: reset_hard()\n");
pipc_t *dev = (pipc_t *) priv;
sff_bus_master_reset(dev->bm[0]);
sff_bus_master_reset(dev->bm[1]);
memset(dev->pci_isa_regs, 0, 256);
memset(dev->ide_regs, 0, 256);
memset(dev->usb_regs, 0, 512);
memset(dev->power_regs, 0, 256);
memset(dev->ac97_regs, 0, 512);
/* PCI-ISA bridge registers. */
dev->pci_isa_regs[0x00] = 0x06;
dev->pci_isa_regs[0x01] = 0x11;
dev->pci_isa_regs[0x02] = dev->local >> 16;
dev->pci_isa_regs[0x03] = dev->local >> 24;
dev->pci_isa_regs[0x04] = (dev->local <= VIA_PIPC_586B) ? 0x0f : 0x87;
dev->pci_isa_regs[0x07] = 0x02;
dev->pci_isa_regs[0x08] = dev->local >> 8;
dev->pci_isa_regs[0x0a] = 0x01;
dev->pci_isa_regs[0x0b] = 0x06;
dev->pci_isa_regs[0x0e] = 0x80;
dev->pci_isa_regs[0x48] = 0x01;
dev->pci_isa_regs[0x4a] = 0x04;
dev->pci_isa_regs[0x4f] = 0x03;
/* 686A/B default value does not line up with default bits */
dev->pci_isa_regs[0x50] = (dev->local >= VIA_PIPC_686A) ? 0x0e : 0x24;
dev->pci_isa_regs[0x59] = 0x04;
if (dev->local >= VIA_PIPC_686A)
dev->pci_isa_regs[0x5a] = dev->pci_isa_regs[0x5f] = 0x04;
dma_e = 0x00;
for (i = 0; i < 8; i++) {
dma[i].ab &= 0xffff000f;
dma[i].ac &= 0xffff000f;
}
pic_set_shadow(0);
dev->max_pcs = (dev->local >= VIA_PIPC_686A) ? 3 : 1;
/* IDE registers. */
dev->max_func++;
dev->ide_regs[0x00] = 0x06;
dev->ide_regs[0x01] = 0x11;
dev->ide_regs[0x02] = 0x71;
dev->ide_regs[0x03] = 0x05;
dev->ide_regs[0x04] = 0x80;
dev->ide_regs[0x06] = (dev->local == VIA_PIPC_686A) ? 0x90 : 0x80;
dev->ide_regs[0x07] = 0x02;
dev->ide_regs[0x08] = (dev->local == VIA_PIPC_596B) ? 0x10 : 0x06; /* only 596B has rev 0x10? */
dev->ide_regs[0x09] = 0x85;
dev->ide_regs[0x0a] = 0x01;
dev->ide_regs[0x0b] = 0x01;
dev->ide_regs[0x10] = 0xf1;
dev->ide_regs[0x11] = 0x01;
dev->ide_regs[0x14] = 0xf5;
dev->ide_regs[0x15] = 0x03;
dev->ide_regs[0x18] = 0x71;
dev->ide_regs[0x19] = 0x01;
dev->ide_regs[0x1c] = 0x75;
dev->ide_regs[0x1d] = 0x03;
dev->ide_regs[0x20] = 0x01;
dev->ide_regs[0x21] = 0xcc;
if (dev->local >= VIA_PIPC_686A)
dev->ide_regs[0x34] = 0xc0;
dev->ide_regs[0x3c] = 0x0e;
if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[0x40] = 0x04;
dev->ide_regs[0x41] = (dev->local == VIA_PIPC_686B) ? 0x06 : 0x02;
dev->ide_regs[0x42] = 0x09;
dev->ide_regs[0x43] = (dev->local >= VIA_PIPC_686A) ? 0x0a : 0x3a;
dev->ide_regs[0x44] = 0x68;
if (dev->local == VIA_PIPC_686B)
dev->ide_regs[0x45] = 0x20;
else if (dev->local >= VIA_PIPC_8231)
dev->ide_regs[0x45] = 0x03;
dev->ide_regs[0x46] = 0xc0;
dev->ide_regs[0x48] = 0xa8;
dev->ide_regs[0x49] = 0xa8;
dev->ide_regs[0x4a] = 0xa8;
dev->ide_regs[0x4b] = 0xa8;
dev->ide_regs[0x4c] = 0xff;
if (dev->local != VIA_PIPC_686B)
dev->ide_regs[0x4e] = dev->ide_regs[0x4f] = 0xff;
dev->ide_regs[0x50] = dev->ide_regs[0x51] = dev->ide_regs[0x52] = dev->ide_regs[0x53] = ((dev->local == VIA_PIPC_686A) || (dev->local == VIA_PIPC_686B)) ? 0x07 : 0x03;
if (dev->local >= VIA_PIPC_596A)
dev->ide_regs[0x54] = ((dev->local == VIA_PIPC_686A) || (dev->local == VIA_PIPC_686B)) ? 0x04 : 0x06;
dev->ide_regs[0x61] = 0x02;
dev->ide_regs[0x69] = 0x02;
if (dev->local >= VIA_PIPC_686A) {
dev->ide_regs[0xc0] = 0x01;
dev->ide_regs[0xc2] = 0x02;
}
/* USB registers. */
for (i = 0; i <= (dev->local >= VIA_PIPC_686A); i++) {
dev->max_func++;
dev->usb_regs[i][0x00] = 0x06;
dev->usb_regs[i][0x01] = 0x11;
dev->usb_regs[i][0x02] = 0x38;
dev->usb_regs[i][0x03] = 0x30;
dev->usb_regs[i][0x04] = 0x00;
dev->usb_regs[i][0x05] = 0x00;
dev->usb_regs[i][0x06] = 0x00;
dev->usb_regs[i][0x07] = 0x02;
switch (dev->local) {
case VIA_PIPC_586A:
case VIA_PIPC_586B:
case VIA_PIPC_596A:
dev->usb_regs[i][0x08] = 0x02;
break;
case VIA_PIPC_596B:
dev->usb_regs[i][0x08] = 0x08;
break;
case VIA_PIPC_686A:
dev->usb_regs[i][0x08] = 0x06;
break;
case VIA_PIPC_686B:
dev->usb_regs[i][0x08] = 0x1a;
break;
case VIA_PIPC_8231:
dev->usb_regs[i][0x08] = 0x1e;
break;
default:
break;
}
dev->usb_regs[i][0x0a] = 0x03;
dev->usb_regs[i][0x0b] = 0x0c;
dev->usb_regs[i][0x0d] = 0x16;
dev->usb_regs[i][0x20] = 0x01;
dev->usb_regs[i][0x21] = 0x03;
if (dev->local == VIA_PIPC_686B)
dev->usb_regs[i][0x34] = 0x80;
dev->usb_regs[i][0x3d] = 0x04;
dev->usb_regs[i][0x60] = 0x10;
if (dev->local >= VIA_PIPC_686A) {
dev->usb_regs[i][0x80] = 0x01;
dev->usb_regs[i][0x82] = 0x02;
}
dev->usb_regs[i][0xc1] = 0x20;
}
/* Power management registers. */
if (dev->acpi) {
dev->max_func++;
dev->power_regs[0x00] = 0x06;
dev->power_regs[0x01] = 0x11;
if (dev->local >= VIA_PIPC_8231) {
/* The VT8231 preliminary datasheet lists *two* inaccurate
device IDs (3068 and 3057). Real dumps have 8235. */
dev->power_regs[0x02] = 0x35;
dev->power_regs[0x03] = 0x82;
} else {
if (dev->local <= VIA_PIPC_586B)
dev->power_regs[0x02] = 0x40;
else if (dev->local <= VIA_PIPC_596B)
dev->power_regs[0x02] = 0x50;
else
dev->power_regs[0x02] = 0x57;
dev->power_regs[0x03] = 0x30;
}
dev->power_regs[0x04] = 0x00;
dev->power_regs[0x05] = 0x00;
dev->power_regs[0x06] = (dev->local == VIA_PIPC_686B) ? 0x90 : 0x80;
dev->power_regs[0x07] = 0x02;
switch (dev->local) {
case VIA_PIPC_586B:
case VIA_PIPC_686A:
case VIA_PIPC_8231:
dev->power_regs[0x08] = 0x10;
break;
case VIA_PIPC_596A:
dev->power_regs[0x08] = 0x20;
break;
case VIA_PIPC_596B:
dev->power_regs[0x08] = 0x30;
break;
case VIA_PIPC_686B:
dev->power_regs[0x08] = 0x40;
break;
default:
break;
}
if (dev->local == VIA_PIPC_686B)
dev->power_regs[0x34] = 0x68;
dev->power_regs[0x40] = 0x20;
dev->power_regs[0x42] = 0x50;
dev->power_regs[0x48] = 0x01;
if (dev->local == VIA_PIPC_686B) {
dev->power_regs[0x68] = 0x01;
dev->power_regs[0x6a] = 0x02;
}
if (dev->local >= VIA_PIPC_686A)
dev->power_regs[0x70] = 0x01;
if (dev->local == VIA_PIPC_596A)
dev->power_regs[0x80] = 0x01;
else if (dev->local >= VIA_PIPC_596B)
dev->power_regs[0x90] = 0x01;
/* Set up PCS I/O traps. */
pipc_io_trap_t *trap;
for (i = 0; i <= dev->max_pcs; i++) {
trap = &dev->io_traps[TRAP_GR0 + i];
trap->dev = dev;
trap->trap = io_trap_add(pipc_io_trap_glb, trap);
if (i & 2) {
trap->sts_reg = (uint32_t *) &dev->acpi->regs.extiotrapsts;
trap->en_reg = (uint32_t *) &dev->acpi->regs.extiotrapen;
trap->mask = 0x01 << (i & 1);
} else {
trap->sts_reg = &dev->acpi->regs.glbsts;
trap->en_reg = &dev->acpi->regs.glben;
trap->mask = 0x4000 << i;
}
}
}
/* AC97/MC97 registers. */
if (dev->local >= VIA_PIPC_686A) {
for (i = 0; i <= 1; i++) {
dev->max_func++;
dev->ac97_regs[i][0x00] = 0x06;
dev->ac97_regs[i][0x01] = 0x11;
dev->ac97_regs[i][0x02] = 0x58 + (0x10 * i);
dev->ac97_regs[i][0x03] = 0x30;
dev->ac97_regs[i][0x06] = 0x10 * (1 - i);
dev->ac97_regs[i][0x07] = 0x02;
switch (dev->local) {
case VIA_PIPC_686A:
dev->ac97_regs[i][0x08] = (i == 0) ? 0x12 : 0x01;
break;
case VIA_PIPC_686B:
dev->ac97_regs[i][0x08] = (i == 0) ? 0x50 : 0x30;
break;
case VIA_PIPC_8231:
dev->ac97_regs[i][0x08] = (i == 0) ? 0x40 : 0x20;
break;
default:
break;
}
if (i == 0) {
dev->ac97_regs[i][0x0a] = 0x01;
dev->ac97_regs[i][0x0b] = 0x04;
} else {
dev->ac97_regs[i][0x0a] = 0x80;
dev->ac97_regs[i][0x0b] = 0x07;
}
dev->ac97_regs[i][0x10] = 0x01;
if (i == 0) {
dev->ac97_regs[i][0x14] = 0x01;
dev->ac97_regs[i][0x18] = 0x01;
}
dev->ac97_regs[i][0x1c] = 0x01;
dev->ac97_regs[i][0x3d] = 0x03;
if (i == 0)
dev->ac97_regs[i][0x40] = 0x01;
dev->ac97_regs[i][0x43] = 0x1c;
dev->ac97_regs[i][0x48] = 0x01;
dev->ac97_regs[i][0x4b] = 0x02;
pipc_sgd_handlers(dev, i);
pipc_codec_handlers(dev, i);
pipc_sb_handlers(dev, i);
}
}
if (dev->gameport)
gameport_remap(dev->gameport, 0x200);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
if (dev->local <= VIA_PIPC_586B) {
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
if (dev->local == VIA_PIPC_586B)
pci_set_mirq_routing(PCI_MIRQ2, PCI_IRQ_DISABLED);
}
ide_pri_disable();
ide_sec_disable();
nvr_via_wp_set(0x00, 0x32, dev->nvr);
nvr_via_wp_set(0x00, 0x0d, dev->nvr);
}
static void
pipc_ide_handlers(pipc_t *dev)
{
uint16_t main;
uint16_t side;
ide_pri_disable();
ide_sec_disable();
if (dev->ide_regs[0x09] & 0x01) {
main = (dev->ide_regs[0x11] << 8) | (dev->ide_regs[0x10] & 0xf8);
side = ((dev->ide_regs[0x15] << 8) | (dev->ide_regs[0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
if (dev->ide_regs[0x09] & 0x04) {
main = (dev->ide_regs[0x19] << 8) | (dev->ide_regs[0x18] & 0xf8);
side = ((dev->ide_regs[0x1d] << 8) | (dev->ide_regs[0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
if (dev->ide_regs[0x04] & PCI_COMMAND_IO) {
if (dev->ide_regs[0x40] & 0x02)
ide_pri_enable();
if (dev->ide_regs[0x40] & 0x01)
ide_sec_enable();
}
}
static void
pipc_ide_irqs(pipc_t *dev)
{
int irq_mode[2] = { IRQ_MODE_LEGACY, IRQ_MODE_LEGACY };
if (dev->ide_regs[0x09] & 0x01)
irq_mode[0] = (dev->ide_regs[0x3d] & 0x01) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
if (dev->ide_regs[0x09] & 0x04)
irq_mode[1] = (dev->ide_regs[0x3d] & 0x01) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
sff_set_irq_mode(dev->bm[0], irq_mode[0]);
sff_set_irq_mode(dev->bm[1], irq_mode[1]);
}
static void
pipc_bus_master_handlers(pipc_t *dev)
{
uint16_t base = (dev->ide_regs[0x20] & 0xf0) | (dev->ide_regs[0x21] << 8);
sff_bus_master_handler(dev->bm[0], (dev->ide_regs[0x04] & 1), base);
sff_bus_master_handler(dev->bm[1], (dev->ide_regs[0x04] & 1), base + 8);
}
static void
pipc_pcs_update(pipc_t *dev)
{
uint8_t io_base_reg;
uint8_t io_mask_reg;
uint8_t io_mask_shift;
uint8_t enable;
uint16_t io_base;
uint16_t io_mask;
for (uint8_t i = 0; i <= dev->max_pcs; i++) {
if (i & 2) {
io_base_reg = 0x8c;
io_mask_reg = 0x8a;
} else {
io_base_reg = 0x78;
io_mask_reg = 0x80;
}
io_base_reg |= (i & 1) << 1;
io_mask_shift = (i & 1) << 2;
if (dev->local <= VIA_PIPC_596B)
enable = dev->pci_isa_regs[0x76] & (0x10 << i);
else
enable = dev->pci_isa_regs[0x8b] & (0x01 << i);
io_base = dev->pci_isa_regs[io_base_reg] | (dev->pci_isa_regs[io_base_reg | 1] << 8);
io_mask = (dev->pci_isa_regs[io_mask_reg] >> io_mask_shift) & 0x000f;
pipc_log("PIPC: Mapping PCS%d to %04X-%04X (enable %d)\n", i, io_base, io_base + io_mask, enable);
io_trap_remap(dev->io_traps[TRAP_GR0 + i].trap, enable, io_base & ~io_mask, io_mask + 1);
}
}
static void
pipc_trap_update_paden(pipc_t *dev, uint8_t trap_id,
uint32_t paden_mask, uint8_t enable,
uint16_t addr, uint16_t size)
{
pipc_io_trap_t *trap = &dev->io_traps[trap_id];
enable = (dev->acpi->regs.paden & paden_mask) && enable;
/* Set up Primary Activity Detect I/O traps dynamically. */
if (enable && !trap->trap) {
trap->dev = dev;
trap->trap = io_trap_add(pipc_io_trap_pact, trap);
trap->sts_reg = &dev->acpi->regs.padsts;
trap->en_reg = &dev->acpi->regs.paden;
trap->mask = paden_mask;
}
/* Remap I/O trap. */
io_trap_remap(trap->trap, enable, addr, size);
}
static void
pipc_trap_update_586(void *priv)
{
pipc_t *dev = (pipc_t *) priv;
/* TRAP_DRQ (00000001) and TRAP_PIRQ (00000002) not implemented. */
pipc_trap_update_paden(dev, TRAP_PIDE_MAIN, 0x00000008, 1, 0x1f0, 8);
pipc_trap_update_paden(dev, TRAP_SIDE_MAIN, 0x00000008, 1, 0x170, 8);
pipc_trap_update_paden(dev, TRAP_FLP_MAIN, 0x00000008, 1, 0x3f5, 1);
pipc_trap_update_paden(dev, TRAP_VGA, 0x00000010, 1, 0x3b0, 48);
/* [A0000:BFFFF] memory trap not implemented. */
pipc_trap_update_paden(dev, TRAP_LPT1, 0x00000020, 1, 0x378, 8);
pipc_trap_update_paden(dev, TRAP_LPT2, 0x00000020, 1, 0x278, 8);
pipc_trap_update_paden(dev, TRAP_COM1, 0x00000040, 1, 0x3f8, 8);
pipc_trap_update_paden(dev, TRAP_COM2, 0x00000040, 1, 0x2f8, 8);
pipc_trap_update_paden(dev, TRAP_COM3, 0x00000040, 1, 0x3e8, 8);
pipc_trap_update_paden(dev, TRAP_COM4, 0x00000040, 1, 0x2e8, 8);
pipc_trap_update_paden(dev, TRAP_KBC, 0x00000080, 1, 0x60, 1);
}
static void
pipc_trap_update_596(void *priv)
{
pipc_t *dev = (pipc_t *) priv;
/* TRAP_DRQ (00000001) and TRAP_PIRQ (00000002) not implemented. */
pipc_trap_update_paden(dev, TRAP_PIDE_MAIN, 0x00000004, 1, 0x1f0, 8);
pipc_trap_update_paden(dev, TRAP_PIDE_SIDE, 0x00000004, 1, 0x3f6, 1);
pipc_trap_update_paden(dev, TRAP_SIDE_MAIN, 0x00000008, 1, 0x170, 8);
pipc_trap_update_paden(dev, TRAP_SIDE_SIDE, 0x00000008, 1, 0x376, 1);
pipc_trap_update_paden(dev, TRAP_FLP_MAIN, 0x00000010, 1, 0x3f0, 6);
pipc_trap_update_paden(dev, TRAP_FLP_SIDE, 0x00000010, 1, 0x3f7, 1);
pipc_trap_update_paden(dev, TRAP_COM1, 0x00000020, 1, 0x3f8, 8);
pipc_trap_update_paden(dev, TRAP_COM3, 0x00000020, 1, 0x3e8, 8);
pipc_trap_update_paden(dev, TRAP_COM2, 0x00000040, 1, 0x2f8, 8);
pipc_trap_update_paden(dev, TRAP_COM4, 0x00000040, 1, 0x2e8, 8);
pipc_trap_update_paden(dev, TRAP_LPT1, 0x00000080, 1, 0x378, 8);
pipc_trap_update_paden(dev, TRAP_LPT2, 0x00000080, 1, 0x278, 8);
pipc_trap_update_paden(dev, TRAP_VGA, 0x00000100, 1, 0x3b0, 48);
/* [A0000:BFFFF] memory trap not implemented. */
pipc_trap_update_paden(dev, TRAP_KBC, 0x00000200, 1, 0x60, 1);
/* The following traps are poorly documented and assumed to operate on all ranges allowed
by the Positive Decoding Control registers. I couldn't probe this behavior on hardware.
It's better to be safe and cover all of them than to assume Intel-like behavior (one range). */
for (uint8_t i = 0; i < 3; i++) {
pipc_trap_update_paden(dev, TRAP_AUD_MIDI_0 + i,
0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x01),
0x300 + (0x10 * i), 4);
pipc_trap_update_paden(dev, TRAP_AUD_SB_0 + i,
0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x02),
0x220 + (0x20 * i), 20);
}
pipc_trap_update_paden(dev, TRAP_AUD_GAME, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x04), 0x200, 8);
pipc_trap_update_paden(dev, TRAP_AUD_WSS_0, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x08), 0x530, 8);
pipc_trap_update_paden(dev, TRAP_AUD_WSS_1, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x08), 0x604, 8);
pipc_trap_update_paden(dev, TRAP_AUD_WSS_2, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x08), 0xe80, 8);
pipc_trap_update_paden(dev, TRAP_AUD_WSS_3, 0x00000400, (dev->local <= VIA_PIPC_596B) || (dev->power_regs[0x40] & 0x08), 0xf40, 8);
}
static void
pipc_sgd_handlers(pipc_t *dev, uint8_t modem)
{
if (!dev->ac97)
return;
if (modem)
ac97_via_remap_modem_sgd(dev->ac97, dev->ac97_regs[1][0x11] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO);
else
ac97_via_remap_audio_sgd(dev->ac97, dev->ac97_regs[0][0x11] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO);
}
static void
pipc_codec_handlers(pipc_t *dev, uint8_t modem)
{
if (!dev->ac97)
return;
if (modem)
ac97_via_remap_modem_codec(dev->ac97, dev->ac97_regs[1][0x1d] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO);
else
ac97_via_remap_audio_codec(dev->ac97, dev->ac97_regs[0][0x1d] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO);
}
static uint8_t
pipc_fmnmi_read(uint16_t addr, void *priv)
{
const pipc_t *dev = (pipc_t *) priv;
uint8_t ret = dev->fmnmi_regs[addr & 0x03];
pipc_log("PIPC: fmnmi_read(%02X) = %02X\n", addr & 0x03, ret);
#ifdef VIA_PIPC_FM_EMULATION
/* Clear NMI/SMI if enabled. */
if (dev->ac97_regs[0][0x48] & 0x01) {
if (dev->ac97_regs[0][0x48] & 0x04)
smi_line = 0;
else
nmi = 0;
}
#endif
return ret;
}
static void
pipc_fmnmi_handlers(pipc_t *dev, uint8_t modem)
{
if (!dev->ac97 || modem)
return;
if (dev->fmnmi_base)
io_removehandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev);
dev->fmnmi_base = (dev->ac97_regs[0][0x15] << 8) | (dev->ac97_regs[0][0x14] & 0xfc);
if (dev->fmnmi_base && (dev->ac97_regs[0][0x04] & PCI_COMMAND_IO))
io_sethandler(dev->fmnmi_base, 4, pipc_fmnmi_read, NULL, NULL, NULL, NULL, NULL, dev);
}
static uint8_t
pipc_fm_read(uint16_t addr, void *priv)
{
const pipc_t *dev = (pipc_t *) priv;
#ifdef VIA_PIPC_FM_EMULATION
uint8_t ret = ((addr & 0x03) == 0x00) ? dev->fmnmi_status : 0x00;
#else
uint8_t ret = dev->sb->opl.read(addr, dev->sb->opl.priv);
#endif
pipc_log("PIPC: fm_read(%02X) = %02X\n", addr & 0x03, ret);
return ret;
}
static void
pipc_fm_write(uint16_t addr, uint8_t val, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
pipc_log("PIPC: fm_write(%02X, %02X)\n", addr & 0x03, val);
#ifdef VIA_PIPC_FM_EMULATION
/* Real 686B only updates the bank ID register when writing to the
index port, and only fires NMI/SMI when writing to the data port. */
if (!(addr & 0x01)) {
dev->fmnmi_regs[0x00] = (addr & 0x02) ? 0x02 : 0x01;
dev->fmnmi_regs[0x02] = val;
} else {
dev->fmnmi_regs[0x01] = val;
/* TODO: Probe how real hardware handles OPL timers. This assumed implementation
just sets the relevant interrupt flags as soon as a timer is started. */
if (!(addr & 0x02) && (dev->fmnmi_regs[0x02] == 0x04)) {
if (val & 0x80)
dev->fmnmi_status = 0x00;
if ((val & 0x41) == 0x01)
dev->fmnmi_status |= 0x40;
if ((val & 0x22) == 0x02)
dev->fmnmi_status |= 0x20;
if (dev->fmnmi_status & 0x60)
dev->fmnmi_status |= 0x80;
}
/* Fire NMI/SMI if enabled. */
if (dev->ac97_regs[0][0x48] & 0x01) {
pipc_log("PIPC: Raising %s\n", (dev->ac97_regs[0][0x48] & 0x04) ? "SMI" : "NMI");
if (dev->ac97_regs[0][0x48] & 0x04)
smi_raise();
else
nmi_raise();
}
}
#else
dev->sb->opl.write(addr, val, dev->sb->opl.priv);
#endif
}
static void
pipc_sb_handlers(pipc_t *dev, uint8_t modem)
{
if (!dev->ac97 || modem)
return;
sb_dsp_setaddr(&dev->sb->dsp, 0);
if (dev->sb_base) {
io_removehandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_removehandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_removehandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb);
}
mpu401_change_addr(dev->sb->mpu, 0);
mpu401_setirq(dev->sb->mpu, 0);
io_removehandler(0x388, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
if (dev->ac97_regs[0][0x42] & 0x01) {
dev->sb_base = 0x220 + (0x20 * (dev->ac97_regs[0][0x43] & 0x03));
sb_dsp_setaddr(&dev->sb->dsp, dev->sb_base);
if (dev->ac97_regs[0][0x42] & 0x04) {
io_sethandler(dev->sb_base, 4, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_sethandler(dev->sb_base + 8, 2, dev->sb->opl.read, NULL, NULL, dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
}
io_sethandler(dev->sb_base + 4, 2, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, dev->sb);
uint8_t irq = 5 + (2 * ((dev->ac97_regs[0][0x43] >> 6) & 0x03));
sb_dsp_setirq(&dev->sb->dsp, (irq == 11) ? 10 : irq);
sb_dsp_setdma8(&dev->sb->dsp, (dev->ac97_regs[0][0x43] >> 4) & 0x03);
/* Set up CD audio filter. This might not actually work if VIAUDIO writes to CD volume through AC97. */
sound_set_cd_audio_filter(sbpro_filter_cd_audio, dev->sb);
}
if (dev->ac97_regs[0][0x42] & 0x02) {
/* BAR 2 is a mess. The MPU and game port remapping registers that VIA claims to be there don't
seem to actually exist on a real 686B. Remapping the MPU to BAR 2 itself does work, though. */
if (dev->ac97_regs[0][0x42] & 0x80)
mpu401_change_addr(dev->sb->mpu, (dev->ac97_regs[0][0x19] << 8) | (dev->ac97_regs[0][0x18] & 0xfc));
else
mpu401_change_addr(dev->sb->mpu, 0x300 | ((dev->ac97_regs[0][0x43] << 2) & 0x30));
if (!(dev->ac97_regs[0][0x42] & 0x40))
mpu401_setirq(dev->sb->mpu, dev->sb->dsp.sb_irqnum);
}
if (dev->ac97_regs[0][0x42] & 0x04) {
io_sethandler(0x388, 4, pipc_fm_read, NULL, NULL, pipc_fm_write, NULL, NULL, dev);
#ifndef VIA_PIPC_FM_EMULATION
dev->sb->opl_enabled = 1;
} else {
dev->sb->opl_enabled = 0;
#endif
}
}
static void
pipc_sb_get_buffer(int32_t *buffer, int len, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
/* Poll SB audio only if the legacy block is enabled. */
#ifdef VIA_PIPC_FM_EMULATION
if (dev->ac97_regs[0][0x42] & 0x01)
#else
if (dev->ac97_regs[0][0x42] & 0x05)
#endif
sb_get_buffer_sbpro(buffer, len, dev->sb);
}
static uint8_t
pipc_read(int func, int addr, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
uint8_t ret = 0xff;
int c;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
if (func > dev->max_func)
return ret;
else if (func == 0) { /* PCI-ISA bridge */
if ((addr >= 0x60) && (addr <= 0x6f)) { /* DMA shadow registers */
c = (addr & 0x0e) >> 1;
if (addr & 0x01)
ret = (dma[c].ab & 0x0000ff00) >> 8;
else {
ret = (dma[c].ab & 0x000000f0);
ret |= (!!(dma_e & (1 << c)) << 3);
}
} else
ret = dev->pci_isa_regs[addr];
} else if ((func == 1) && !(dev->pci_isa_regs[0x48] & 0x02)) { /* IDE */
ret = dev->ide_regs[addr];
if ((addr >= 0x50) && (addr <= 0x53)) { /* UDMA timing registers */
/* Set or clear bit 5 according to UDMA mode. Documentation is unclear, but a real
686B does set bit 5 when UDMA is enabled through the method specified in bit 7. */
c = 0x53 - addr;
if (ret & 0x80) /* bit 7 set = use bit 6 */
c = ret & 0x40;
else if (ide_drives[c]) /* bit 7 clear = use SET FEATURES mode */
c = (ide_drives[c]->mdma_mode & 0x300) == 0x300;
else /* no drive here */
c = 0;
/* 586A/B datasheet claims bit 5 must be clear for UDMA, unlike later models where
it must be set, but the Windows driver doesn't care and always checks if it's set. */
if (c)
ret |= 0x20;
else
ret &= ~0x20;
}
} else if ((func < pm_func) && !((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10))) /* USB */
ret = dev->usb_regs[func - 2][addr];
else if (func == pm_func) { /* Power */
ret = dev->power_regs[addr];
if (addr == 0x42) {
if (dev->nvr->regs[0x0d] & 0x80)
ret |= 0x10;
else
ret &= ~0x10;
} else if ((addr == 0xd2) && (dev->local == VIA_PIPC_686B)) {
/* SMBus clock select bit. */
if (dev->smbus->clock == 16384)
ret &= ~0x10;
else
ret |= 0x10;
}
} else if ((func <= (pm_func + 2)) && !(dev->pci_isa_regs[0x85] & ((func == (pm_func + 1)) ? 0x04 : 0x08))) { /* AC97 / MC97 */
if (addr == 0x40)
ret = ac97_via_read_status(dev->ac97, func - pm_func - 1);
else
ret = dev->ac97_regs[func - pm_func - 1][addr];
}
pipc_log("PIPC: read(%d, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
nvr_update_io_mapping(pipc_t *dev)
{
if (dev->nvr_enabled)
nvr_at_handler(0, 0x0074, dev->nvr);
if ((dev->pci_isa_regs[0x5b] & 0x02) || (dev->pci_isa_regs[0x48] & 0x08))
nvr_at_handler(1, 0x0074, dev->nvr);
}
static void
usb_update_io_mapping(pipc_t *dev, int func)
{
uhci_update_io_mapping(dev->usb[func - 2], dev->usb_regs[func - 2][0x20] & ~0x1f, dev->usb_regs[func - 2][0x21], dev->usb_regs[func - 2][PCI_REG_COMMAND] & PCI_COMMAND_IO);
}
static void
pipc_ddma_update(pipc_t *dev, int addr)
{
uint32_t base;
if (dev->local >= VIA_PIPC_8231)
return;
base = (dev->pci_isa_regs[addr] & 0xf0) | (((uint32_t) dev->pci_isa_regs[addr | 0x01]) << 8);
ddma_update_io_mapping(dev->ddma, (addr & 0x0e) >> 1, (dev->pci_isa_regs[addr] & 0xf0), dev->pci_isa_regs[addr | 0x01], (dev->pci_isa_regs[addr] & 0x08) && (base != 0x0000));
}
static void
pipc_write(int func, int addr, uint8_t val, void *priv)
{
pipc_t *dev = (pipc_t *) priv;
int c;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
if (func > dev->max_func)
return;
pipc_log("PIPC: write(%d, %02X, %02X)\n", func, addr, val);
if (func == 0) { /* PCI-ISA bridge */
/* Read-only addresses. */
if ((addr < 4) || (addr == 5) || ((addr >= 8) && (addr < 0x40)) || (addr == 0x49) || (addr == 0x4b) || (addr == 0x53) || ((addr >= 0x5d) && (addr < 0x5f)) || (addr >= 0x90))
return;
if ((dev->local <= VIA_PIPC_586A) && ((addr >= 0x58) && (addr < 0x80)))
return;
if ((dev->local <= VIA_PIPC_586B) && (addr >= 0x74))
return;
if ((dev->local <= VIA_PIPC_596A) && ((addr == 0x51) || (addr == 0x52) || (addr == 0x5f) || (addr == 0x85) || (addr == 0x86) || ((addr >= 0x8a) && (addr < 0x90))))
return;
switch (addr) {
case 0x04:
dev->pci_isa_regs[0x04] = (val & 8) | 7;
break;
case 0x07:
dev->pci_isa_regs[0x07] &= ~(val & 0xb0);
break;
case 0x42:
dev->pci_isa_regs[0x42] = val & 0xcf;
switch (val & 0xf) {
/* Divisors on the PCI clock. */
case 0x8:
cpu_set_isa_pci_div(3);
break;
case 0x9:
cpu_set_isa_pci_div(2);
break;
/* case 0xa: same as default */
case 0xb:
cpu_set_isa_pci_div(6);
break;
case 0xc:
cpu_set_isa_pci_div(5);
break;
case 0xd:
cpu_set_isa_pci_div(10);
break;
case 0xe:
cpu_set_isa_pci_div(12);
break;
/* Half oscillator clock. */
case 0xf:
cpu_set_isa_speed(7159091);
break;
/* Divisor 4 on the PCI clock whenever bit 3 is clear. */
default:
cpu_set_isa_pci_div(4);
break;
}
break;
case 0x44:
dev->pci_isa_regs[0x44] = val;
break;
case 0x47:
if (val & 0x01)
pci_write(0x0cf9, (val & 0x80) ? 0x06 : 0x04, NULL);
pic_set_shadow(!!(val & 0x10));
pic_elcr_io_handler(!!(val & 0x20));
dev->pci_isa_regs[0x47] = val & 0xfe;
break;
case 0x48:
dev->pci_isa_regs[0x48] = val;
nvr_update_io_mapping(dev);
break;
case 0x50:
case 0x51:
case 0x52:
case 0x85:
dev->pci_isa_regs[addr] = val;
/* Forward Super I/O-related registers to sio_vt82c686.c */
if (dev->sio)
vt82c686_sio_write(addr, val, dev->sio);
break;
case 0x54:
pci_set_irq_level(PCI_INTA, !(val & 8));
pci_set_irq_level(PCI_INTB, !(val & 4));
pci_set_irq_level(PCI_INTC, !(val & 2));
pci_set_irq_level(PCI_INTD, !(val & 1));
dev->pci_isa_regs[0x54] = val & 0x0f;
break;
case 0x55:
pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'A' : 'D', val >> 4);
pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTA : PCI_INTD, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED);
if (dev->local <= VIA_PIPC_586B) {
pipc_log("PIPC: Steering MIRQ0 to IRQ %d\n", val & 0x0f);
pci_set_mirq_routing(PCI_MIRQ0, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED);
}
dev->pci_isa_regs[0x55] = val;
break;
case 0x56:
pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'C' : 'A', val >> 4);
pipc_log("PIPC: Steering PIRQB to IRQ %d\n", val & 0x0f);
pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTC : PCI_INTA, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED);
dev->pci_isa_regs[0x56] = val;
break;
case 0x57:
pipc_log("PIPC: Steering PIRQ%c to IRQ %d\n", (dev->local >= VIA_PIPC_596A) ? 'D' : 'C', val >> 4);
pci_set_irq_routing((dev->local >= VIA_PIPC_596A) ? PCI_INTD : PCI_INTC, (val & 0xf0) ? (val >> 4) : PCI_IRQ_DISABLED);
if (dev->local <= VIA_PIPC_586B) {
pipc_log("PIPC: Steering MIRQ1 to IRQ %d\n", val & 0x0f);
pci_set_mirq_routing(PCI_MIRQ1, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED);
}
dev->pci_isa_regs[0x57] = val;
break;
case 0x58:
if (dev->local == VIA_PIPC_586B) {
pipc_log("PIPC: Steering MIRQ2 to IRQ %d\n", val & 0x0f);
pci_set_mirq_routing(PCI_MIRQ2, (val & 0x0f) ? (val & 0x0f) : PCI_IRQ_DISABLED);
}
dev->pci_isa_regs[0x58] = val;
break;
case 0x5b:
dev->pci_isa_regs[0x5b] = val;
nvr_update_io_mapping(dev);
break;
case 0x60:
case 0x62:
case 0x64:
case 0x66:
case 0x6a:
case 0x6c:
case 0x6e:
dev->pci_isa_regs[addr] = val & 0xf8;
pipc_ddma_update(dev, addr);
break;
case 0x61:
case 0x63:
case 0x65:
case 0x67:
case 0x6b:
case 0x6d:
case 0x6f:
dev->pci_isa_regs[addr] = val;
pipc_ddma_update(dev, addr & 0xfe);
break;
case 0x70:
case 0x71:
case 0x72:
case 0x73:
dev->pci_isa_regs[addr - 0x44] = val;
break;
case 0x74:
case 0x8b:
case 0x78:
case 0x79:
case 0x7a:
case 0x7b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f:
case 0x80:
case 0x8a:
dev->pci_isa_regs[addr] = val;
pipc_pcs_update(dev);
break;
case 0x77:
if ((dev->local >= VIA_PIPC_686A) && (val & 0x10))
pclog("PIPC: Warning: Internal I/O APIC enabled.\n");
nvr_via_wp_set(!!(val & 0x04), 0x32, dev->nvr);
nvr_via_wp_set(!!(val & 0x02), 0x0d, dev->nvr);
break;
default:
dev->pci_isa_regs[addr] = val;
break;
}
} else if (func == 1) { /* IDE */
/* Read-only addresses. */
if ((addr < 4) || (addr == 5) || (addr == 8) || ((addr >= 0xa) && (addr < 0x0d)) || ((addr >= 0x0e) && (addr < 0x10)) || ((addr >= 0x12) && (addr < 0x13)) || ((addr >= 0x16) && (addr < 0x17)) || ((addr >= 0x1a) && (addr < 0x1b)) || ((addr >= 0x1e) && (addr < 0x1f)) || ((addr >= 0x22) && (addr < 0x3c)) || ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x55) && (addr < 0x60)) || ((addr >= 0x62) && (addr < 0x68)) || ((addr >= 0x6a) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || (addr == 0x76) || (addr == 0x77) || (addr == 0x7a) || (addr == 0x7b) || (addr == 0x7e) || (addr == 0x7f) || ((addr >= 0x84) && (addr < 0x88)) || (addr >= 0x8c))
return;
if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x54) || (addr >= 0x70)))
return;
/* Check disable bit. */
if (dev->pci_isa_regs[0x48] & 0x02)
return;
switch (addr) {
case 0x04:
dev->ide_regs[0x04] = val & 0x85;
pipc_ide_handlers(dev);
pipc_bus_master_handlers(dev);
break;
case 0x07:
dev->ide_regs[0x07] &= ~(val & 0xf1);
break;
case 0x09:
dev->ide_regs[0x09] = (val & 0x05) | 0x8a;
pipc_ide_handlers(dev);
pipc_ide_irqs(dev);
break;
case 0x10:
dev->ide_regs[0x10] = (val & 0xf8) | 1;
pipc_ide_handlers(dev);
break;
case 0x11:
dev->ide_regs[0x11] = val;
pipc_ide_handlers(dev);
break;
case 0x14:
dev->ide_regs[0x14] = (val & 0xfc) | 1;
pipc_ide_handlers(dev);
break;
case 0x15:
dev->ide_regs[0x15] = val;
pipc_ide_handlers(dev);
break;
case 0x18:
dev->ide_regs[0x18] = (val & 0xf8) | 1;
pipc_ide_handlers(dev);
break;
case 0x19:
dev->ide_regs[0x19] = val;
pipc_ide_handlers(dev);
break;
case 0x1c:
dev->ide_regs[0x1c] = (val & 0xfc) | 1;
pipc_ide_handlers(dev);
break;
case 0x1d:
dev->ide_regs[0x1d] = val;
pipc_ide_handlers(dev);
break;
case 0x20:
dev->ide_regs[0x20] = (val & 0xf0) | 1;
pipc_bus_master_handlers(dev);
break;
case 0x21:
dev->ide_regs[0x21] = val;
pipc_bus_master_handlers(dev);
break;
case 0x3d:
dev->ide_regs[0x3d] = val & 0x01;
pipc_ide_irqs(dev);
break;
case 0x40:
if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[0x40] = (val & 0x03) | 0x04;
else
dev->ide_regs[0x40] = val & 0x0f;
pipc_ide_handlers(dev);
break;
case 0x41:
if (dev->local <= VIA_PIPC_686A)
dev->ide_regs[0x41] = val;
else if (dev->local == VIA_PIPC_8231)
dev->ide_regs[0x41] = val & 0xf6;
else
dev->ide_regs[0x41] = val & 0xf2;
break;
case 0x43:
if (dev->local <= VIA_PIPC_586A)
dev->ide_regs[0x43] = (val & 0x6f) | 0x10;
else if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[0x43] = (val & 0xef) | 0x10;
else
dev->ide_regs[0x43] = val & 0x0f;
break;
case 0x44:
if (dev->local <= VIA_PIPC_586A)
dev->ide_regs[0x44] = val & 0x78;
else if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[0x44] = val & 0x7b;
else if (dev->local <= VIA_PIPC_596B)
dev->ide_regs[0x44] = val & 0x7f;
else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231))
dev->ide_regs[0x44] = val & 0x69;
else
dev->ide_regs[0x44] = val & 0x7d;
break;
case 0x45:
if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[0x45] = val & 0x40;
else if ((dev->local <= VIA_PIPC_596B) || (dev->local == VIA_PIPC_8231))
dev->ide_regs[0x45] = val & 0x4f;
else if (dev->local <= VIA_PIPC_686A)
dev->ide_regs[0x45] = val & 0x5f;
else
dev->ide_regs[0x45] = (val & 0x5c) | 0x20;
break;
case 0x46:
if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231))
dev->ide_regs[0x46] = val & 0xf3;
else
dev->ide_regs[0x46] = val & 0xc0;
break;
case 0x50:
case 0x51:
case 0x52:
case 0x53:
if (dev->local <= VIA_PIPC_586B)
dev->ide_regs[addr] = val & 0xc3;
else if (dev->local <= VIA_PIPC_596B)
dev->ide_regs[addr] = val & ((addr & 1) ? 0xc3 : 0xcb);
else if ((dev->local <= VIA_PIPC_686A) || (dev->local == VIA_PIPC_8231))
dev->ide_regs[addr] = val & ((addr & 1) ? 0xc7 : 0xcf);
else
dev->ide_regs[addr] = val & 0xd7;
break;
case 0x61:
case 0x69:
dev->ide_regs[addr] = val & 0x0f;
break;
default:
dev->ide_regs[addr] = val;
break;
}
} else if (func < pm_func) { /* USB */
/* Read-only addresses. */
if ((addr < 4) || (addr == 5) || (addr == 6) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x20)) || ((addr >= 0x22) && (addr < 0x3c)) || ((addr >= 0x3e) && (addr < 0x40)) || ((addr >= 0x42) && (addr < 0x44)) || ((addr >= 0x46) && (addr < 0x84)) || ((addr >= 0x85) && (addr < 0xc0)) || (addr >= 0xc2))
return;
if ((dev->local <= VIA_PIPC_596B) && (addr == 0x84))
return;
/* Check disable bits for both controllers. */
if ((func == 2) ? (dev->pci_isa_regs[0x48] & 0x04) : (dev->pci_isa_regs[0x85] & 0x10))
return;
switch (addr) {
case 0x04:
dev->usb_regs[func - 2][0x04] = val & 0x97;
usb_update_io_mapping(dev, func);
break;
case 0x07:
dev->usb_regs[func - 2][0x07] &= ~(val & 0x78);
break;
case 0x20:
dev->usb_regs[func - 2][0x20] = (val & ~0x1f) | 1;
usb_update_io_mapping(dev, func);
break;
case 0x21:
dev->usb_regs[func - 2][0x21] = val;
usb_update_io_mapping(dev, func);
break;
default:
dev->usb_regs[func - 2][addr] = val;
break;
}
} else if (func == pm_func) { /* Power */
/* Read-only addresses */
if ((addr < 0xd) || ((addr >= 0xe) && (addr < 0x40)) || (addr == 0x43) || (addr == 0x4a) || (addr == 0x4b) || (addr == 0x4e) || (addr == 0x4f) || (addr == 0x56) || (addr == 0x57) || ((addr >= 0x5c) && (addr < 0x61)) || ((addr >= 0x64) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || ((addr >= 0x75) && (addr < 0x80)) || (addr == 0x83) || ((addr >= 0x85) && (addr < 0x90)) || ((addr >= 0x92) && (addr < 0xd2)) || (addr >= 0xd7))
return;
if ((dev->local <= VIA_PIPC_586B) && ((addr == 0x48) || (addr == 0x4c) || (addr == 0x4d) || (addr >= 0x54)))
return;
if ((dev->local <= VIA_PIPC_596B) && ((addr >= 0x64) && (addr < (dev->local == VIA_PIPC_596A ? 0x80 : 0x85))))
return;
switch (addr) {
case 0x41:
case 0x48:
case 0x49:
if (addr == 0x48) {
if (dev->local >= VIA_PIPC_596A)
val = (val & 0x80) | 0x01;
else
val = 0x01;
}
dev->power_regs[addr] = val;
c = (dev->power_regs[0x49] << 8);
if (dev->local >= VIA_PIPC_596A)
c |= (dev->power_regs[0x48] & 0x80);
/* Workaround for P3V133 BIOS in 596B mode mapping ACPI to E800 (same as SMBus) instead of E400. */
if ((dev->local == VIA_PIPC_596B) && (c == ((dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0))) && (dev->power_regs[0xd2] & 0x01))
c -= 0x400;
acpi_set_timer32(dev->acpi, dev->power_regs[0x41] & 0x08);
acpi_update_io_mapping(dev->acpi, c, dev->power_regs[0x41] & 0x80);
break;
case 0x42:
dev->power_regs[addr] = (dev->power_regs[addr] & 0xf0) | (val & 0x0f);
acpi_set_irq_line(dev->acpi, dev->power_regs[addr] & 0x0f);
break;
case 0x54:
if (dev->local <= VIA_PIPC_596B)
dev->power_regs[addr] = val; /* write-only on 686A+ */
else
smbus_piix4_setclock(dev->smbus, (val & 0x80) ? 65536 : 16384); /* final clock undocumented on 686A, assume RTC*2 like 686B */
break;
case 0x61:
case 0x62:
case 0x63:
dev->power_regs[addr - 0x58] = val;
break;
case 0x70:
case 0x71:
case 0x74:
dev->power_regs[addr] = val;
/* Forward hardware monitor-related registers to hwm_vt82c686.c */
if (dev->hwm)
vt82c686_hwm_write(addr, val, dev->hwm);
break;
case 0x80:
case 0x81:
case 0x84: /* 596A has the SMBus I/O base and enable bit here instead. */
dev->power_regs[addr] = val;
smbus_piix4_remap(dev->smbus, (dev->power_regs[0x81] << 8) | (dev->power_regs[0x80] & 0xf0), dev->power_regs[0x84] & 0x01);
break;
case 0xd2:
if (dev->local == VIA_PIPC_686B)
smbus_piix4_setclock(dev->smbus, (val & 0x04) ? 65536 : 16384);
fallthrough;
case 0x90:
case 0x91:
dev->power_regs[addr] = val;
smbus_piix4_remap(dev->smbus, (dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0), dev->power_regs[0xd2] & 0x01);
break;
default:
dev->power_regs[addr] = val;
break;
}
} else if (func <= pm_func + 2) { /* AC97 / MC97 */
/* Read-only addresses. */
if ((addr < 0x4) || ((addr >= 0x6) && (addr < 0x9)) || ((addr >= 0xc) && (addr < 0x11)) || (addr == 0x16) || (addr == 0x17) || (addr == 0x1a) || (addr == 0x1b) || ((addr >= 0x1e) && (addr < 0x2c)) || ((addr >= 0x30) && (addr < 0x34)) || ((addr >= 0x35) && (addr < 0x3c)) || ((addr >= 0x3d) && (addr < 0x41)) || ((addr >= 0x45) && (addr < 0x4a)) || (addr >= 0x4c))
return;
/* Small shortcut. */
func = func - pm_func - 1;
/* Check disable bits and specific read-only addresses for both controllers. */
if ((func == 0) && (((addr >= 0x09) && (addr < 0xc)) || (addr == 0x44) || (dev->pci_isa_regs[0x85] & 0x04)))
return;
if ((func == 1) && ((addr == 0x14) || (addr == 0x15) || (addr == 0x18) || (addr == 0x19) || (addr == 0x42) || (addr == 0x43) || (addr == 0x48) || (addr == 0x4a) || (addr == 0x4b) || (dev->pci_isa_regs[0x85] & 0x08)))
return;
switch (addr) {
case 0x04:
dev->ac97_regs[func][addr] = val;
pipc_sgd_handlers(dev, func);
pipc_codec_handlers(dev, func);
pipc_fmnmi_handlers(dev, func);
break;
case 0x09:
case 0x0a:
case 0x0b:
if (dev->ac97_regs[func][0x44] & 0x20)
dev->ac97_regs[func][addr] = val;
break;
case 0x10:
case 0x11:
dev->ac97_regs[func][addr] = val;
pipc_sgd_handlers(dev, func);
break;
case 0x14:
case 0x15:
if (addr == 0x14)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_fmnmi_handlers(dev, func);
break;
case 0x18:
case 0x19:
if (addr == 0x18)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_sb_handlers(dev, func);
break;
case 0x1c:
case 0x1d:
dev->ac97_regs[func][addr] = val;
pipc_codec_handlers(dev, func);
break;
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
if ((func == 0) && (dev->ac97_regs[func][0x42] & 0x20))
dev->ac97_regs[func][addr] = val;
break;
case 0x41:
dev->ac97_regs[func][addr] = val;
ac97_via_write_control(dev->ac97, func, val);
break;
case 0x42:
case 0x4a:
case 0x4b:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val;
gameport_remap(dev->gameport, (dev->ac97_regs[0][0x42] & 0x08) ? ((dev->ac97_regs[0][0x4b] << 8) | (dev->ac97_regs[0][0x4a] & 0xf8)) : 0);
if (addr == 0x42)
pipc_sb_handlers(dev, func);
break;
case 0x43:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val;
break;
case 0x44:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0xf0;
break;
case 0x45:
case 0x48:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0x0f;
break;
default:
dev->ac97_regs[func][addr] = val;
break;
}
}
}
static void
pipc_reset(void *priv)
{
pipc_t *dev = (pipc_t *) priv;
uint8_t pm_func = dev->usb[1] ? 4 : 3;
pipc_write(pm_func, 0x41, 0x00, priv);
pipc_write(pm_func, 0x48, 0x01, priv);
pipc_write(pm_func, 0x49, 0x00, priv);
pipc_write(1, 0x04, 0x80, priv);
pipc_write(1, 0x09, 0x85, priv);
pipc_write(1, 0x10, 0xf1, priv);
pipc_write(1, 0x11, 0x01, priv);
pipc_write(1, 0x14, 0xf5, priv);
pipc_write(1, 0x15, 0x03, priv);
pipc_write(1, 0x18, 0x71, priv);
pipc_write(1, 0x19, 0x01, priv);
pipc_write(1, 0x1c, 0x75, priv);
pipc_write(1, 0x1d, 0x03, priv);
pipc_write(1, 0x20, 0x01, priv);
pipc_write(1, 0x21, 0xcc, priv);
if (dev->local <= VIA_PIPC_586B)
pipc_write(1, 0x40, 0x04, priv);
else
pipc_write(1, 0x40, 0x00, priv);
if (dev->local < VIA_PIPC_586B)
pipc_write(0, 0x44, 0x00, priv);
pipc_write(0, 0x77, 0x00, priv);
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
if (dev->local >= VIA_PIPC_686A)
ac97_via_set_slot(dev->ac97, dev->pci_slot, PCI_INTC);
if (dev->acpi)
acpi_set_slot(dev->acpi, dev->pci_slot);
}
static void *
pipc_init(const device_t *info)
{
pipc_t *dev = (pipc_t *) malloc(sizeof(pipc_t));
memset(dev, 0, sizeof(pipc_t));
pipc_log("PIPC: init()\n");
dev->local = info->local;
pci_add_card(PCI_ADD_SOUTHBRIDGE, pipc_read, pipc_write, dev, &dev->pci_slot);
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
sff_set_irq_pin(dev->bm[0], PCI_INTA);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
sff_set_irq_pin(dev->bm[1], PCI_INTA);
if (dev->local == VIA_PIPC_686B)
dev->smbus = device_add(&via_smbus_device);
else if (dev->local >= VIA_PIPC_596A)
dev->smbus = device_add(&piix4_smbus_device);
dev->nvr = device_add(&via_nvr_device);
if (dev->local >= VIA_PIPC_596A) {
dev->acpi = device_add(&acpi_via_596b_device);
acpi_set_trap_update(dev->acpi, pipc_trap_update_596, dev);
} else if (dev->local >= VIA_PIPC_586B) {
dev->acpi = device_add(&acpi_via_device);
acpi_set_trap_update(dev->acpi, pipc_trap_update_586, dev);
}
dev->usb[0] = device_add_inst(&usb_device, 1);
if (dev->local >= VIA_PIPC_686A) {
dev->usb[1] = device_add_inst(&usb_device, 2);
dev->ac97 = device_add(&ac97_via_device);
dev->sb = device_add_inst(&sb_pro_compat_device, 2);
sound_add_handler(pipc_sb_get_buffer, dev);
dev->gameport = gameport_add(&gameport_sio_device);
dev->sio = device_add(&via_vt82c686_sio_device);
dev->hwm = device_add(&via_vt82c686_hwm_device);
}
pipc_reset_hard(dev);
device_add(&port_92_pci_device);
cpu_set_isa_pci_div(4);
dma_alias_set();
if (dev->local <= VIA_PIPC_586B) {
pci_enable_mirq(0);
pci_enable_mirq(1);
if (dev->local == VIA_PIPC_586B)
pci_enable_mirq(2);
}
if (dev->local < VIA_PIPC_8231)
dev->ddma = device_add(&ddma_device);
if (dev->acpi) {
acpi_set_nvr(dev->acpi, dev->nvr);
acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f);
}
return dev;
}
static void
pipc_close(void *priv)
{
pipc_t *dev = (pipc_t *) priv;
pipc_log("PIPC: close()\n");
for (uint8_t i = 0; i < TRAP_MAX; i++)
io_trap_remove(dev->io_traps[i].trap);
free(dev);
}
const device_t via_vt82c586b_device = {
.name = "VIA VT82C586B",
.internal_name = "via_vt82c586b",
.flags = DEVICE_PCI,
.local = VIA_PIPC_586B,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c596a_device = {
.name = "VIA VT82C596A",
.internal_name = "via_vt82c596a",
.flags = DEVICE_PCI,
.local = VIA_PIPC_596A,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c596b_device = {
.name = "VIA VT82C596B",
.internal_name = "via_vt82c596b",
.flags = DEVICE_PCI,
.local = VIA_PIPC_596B,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c686a_device = {
.name = "VIA VT82C686A",
.internal_name = "via_vt82c686a",
.flags = DEVICE_PCI,
.local = VIA_PIPC_686A,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt82c686b_device = {
.name = "VIA VT82C686B",
.internal_name = "via_vt82c686b",
.flags = DEVICE_PCI,
.local = VIA_PIPC_686B,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t via_vt8231_device = {
.name = "VIA VT8231",
.internal_name = "via_vt8231",
.flags = DEVICE_PCI,
.local = VIA_PIPC_8231,
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/via_pipc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 20,724 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of ALi M1435 chipset that acts as both the
* southbridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/apm.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#define MEM_STATE_SHADOW_R 0x01
#define MEM_STATE_SHADOW_W 0x02
#define MEM_STATE_SMRAM 0x04
typedef struct ali_1435_t {
uint8_t index;
uint8_t cfg_locked;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[16];
uint8_t pci_regs[256];
} ali1435_t;
#ifdef ENABLE_ALI1435_LOG
int ali1435_do_log = ENABLE_ALI1435_LOG;
static void
ali1435_log(const char *fmt, ...)
{
va_list ap;
if (ali1435_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1435_log(fmt, ...)
#endif
/* NOTE: We cheat here. The real ALi M1435 uses a level to edge triggered IRQ converter
when the most siginificant bit is set. We work around that by manipulating the
emulated PIC's ELCR register. */
static void
ali1435_update_irqs(ali1435_t *dev, int set)
{
uint8_t val;
int reg;
int shift;
int irq;
int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
pic_t *temp_pic;
for (uint8_t i = 0; i < 4; i++) {
reg = 0x80 + (i >> 1);
shift = (i & 1) << 2;
val = (dev->pci_regs[reg] >> shift) & 0x0f;
irq = irq_map[val & 0x07];
if (irq == -1)
continue;
temp_pic = (irq >= 8) ? &pic2 : &pic;
irq &= 7;
if (set && (val & 0x08))
temp_pic->elcr |= (1 << irq);
else
temp_pic->elcr &= ~(1 << irq);
}
}
static void
ali1435_pci_write(int func, int addr, uint8_t val, void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
int irq;
int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
ali1435_log("ali1435_write(%02X, %02X, %02X)\n", func, addr, val);
if (func > 0)
return;
if ((addr < 0x04) || (addr == 0x06) || ((addr >= 0x08) && (addr <= 0x0b)))
return;
if ((addr >= 0x0f) && (addr < 0x30))
return;
if ((addr >= 0x34) && (addr < 0x40))
return;
switch (addr) {
/* Dummy PCI Config */
case 0x04:
dev->pci_regs[addr] = (val & 0x7f) | 0x07;
break;
case 0x05:
dev->pci_regs[addr] = (val & 0x01);
break;
/* Dummy PCI Status */
case 0x07:
dev->pci_regs[addr] &= ~(val & 0xb8);
break;
case 0x80:
case 0x81:
dev->pci_regs[addr] = val;
ali1435_update_irqs(dev, 0);
irq = irq_map[val & 0x07];
if (irq >= 0) {
ali1435_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + ((addr & 0x01) << 1), irq);
pci_set_irq_routing(PCI_INTA + ((addr & 0x01) << 1), irq);
} else {
ali1435_log("Set IRQ routing: INT %c -> FF\n", 0x41 + ((addr & 0x01) << 1));
pci_set_irq_routing(PCI_INTA + ((addr & 0x01) << 1), PCI_IRQ_DISABLED);
}
irq = irq_map[(val >> 4) & 0x07];
if (irq >= 0) {
ali1435_log("Set IRQ routing: INT %c -> %02X\n", 0x42 + ((addr & 0x01) << 1), irq);
pci_set_irq_routing(PCI_INTB + ((addr & 0x01) << 1), irq);
} else {
ali1435_log("Set IRQ routing: INT %c -> FF\n", 0x42 + ((addr & 0x01) << 1));
pci_set_irq_routing(PCI_INTB + ((addr & 0x01) << 1), PCI_IRQ_DISABLED);
}
ali1435_update_irqs(dev, 1);
break;
default:
dev->pci_regs[addr] = val;
break;
}
}
static uint8_t
ali1435_pci_read(int func, int addr, void *priv)
{
const ali1435_t *dev = (ali1435_t *) priv;
uint8_t ret;
ret = 0xff;
if (func == 0)
ret = dev->pci_regs[addr];
ali1435_log("ali1435_read(%02X, %02X) = %02X\n", func, addr, ret);
return ret;
}
static void
ali1435_write(uint16_t addr, uint8_t val, void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
if (dev->index == 0x03)
dev->cfg_locked = (val != 0x69);
#ifdef ENABLE_ALI1435_LOG
else
ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
#endif
if (!dev->cfg_locked) {
switch (dev->index) {
/* PCI Mechanism select? */
case 0x00:
dev->regs[dev->index] = val;
ali1435_log("PMC = %i\n", val != 0xc8);
pci_key_write(((val & 0xc8) == 0xc8) ? 0xf0 : 0x00);
break;
/* ???? */
case 0x06:
dev->regs[dev->index] = val;
break;
/* ???? */
case 0x07:
dev->regs[dev->index] = val;
break;
default:
break;
}
}
break;
default:
break;
}
}
static uint8_t
ali1435_read(uint16_t addr, void *priv)
{
const ali1435_t *dev = (ali1435_t *) priv;
uint8_t ret = 0xff;
if ((addr == 0x23) && (dev->index < 0x10))
ret = dev->regs[dev->index];
else if (addr == 0x22)
ret = dev->index;
return ret;
}
static void
ali1435_reset(void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
memset(dev->regs, 0, 16);
dev->regs[0x00] = 0xff;
dev->cfg_locked = 1;
memset(dev->pci_regs, 0, 256);
dev->pci_regs[0x00] = 0x25;
dev->pci_regs[0x01] = 0x10; /*ALi*/
dev->pci_regs[0x02] = 0x35;
dev->pci_regs[0x03] = 0x14; /*M1435*/
dev->pci_regs[0x04] = 0x07;
dev->pci_regs[0x07] = 0x04;
dev->pci_regs[0x0b] = 0x06;
dev->pci_regs[0x80] = 0x80;
dev->pci_regs[0x81] = 0x00;
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
}
static void
ali1435_close(void *priv)
{
ali1435_t *dev = (ali1435_t *) priv;
free(dev);
}
static void *
ali1435_init(UNUSED(const device_t *info))
{
ali1435_t *dev = (ali1435_t *) malloc(sizeof(ali1435_t));
memset(dev, 0, sizeof(ali1435_t));
dev->cfg_locked = 1;
/* M1435 Ports:
22h Index Port
23h Data Port
*/
io_sethandler(0x0022, 0x0002, ali1435_read, NULL, NULL, ali1435_write, NULL, NULL, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1435_pci_read, ali1435_pci_write, dev, &dev->pci_slot);
ali1435_reset(dev);
return dev;
}
const device_t ali1435_device = {
.name = "Intel ALi M1435",
.internal_name = "ali1435",
.flags = DEVICE_PCI,
.local = 0x00,
.init = ali1435_init,
.close = ali1435_close,
.reset = ali1435_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1435.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,554 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5572 USB controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#ifdef ENABLE_SIS_5572_USB_LOG
int sis_5572_usb_do_log = ENABLE_SIS_5572_USB_LOG;
static void
sis_5572_usb_log(const char *fmt, ...)
{
va_list ap;
if (sis_5572_usb_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5572_usb_log(fmt, ...)
#endif
typedef struct sis_5572_usb_t {
uint8_t rev;
uint8_t usb_unk_regs[256];
uint8_t pci_conf[256];
uint16_t usb_unk_base;
usb_t *usb;
sis_55xx_common_t *sis;
} sis_5572_usb_t;
/* SiS 5572 unknown I/O port (second USB PCI BAR). */
static void
sis_5572_usb_unk_write(uint16_t addr, uint8_t val, void *priv)
{
sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
addr = (addr - dev->usb_unk_base) & 0x07;
sis_5572_usb_log("SiS 5572 USB UNK: [W] dev->usb_unk_regs[%02X] = %02X\n", addr, val);
dev->usb_unk_regs[addr] = val;
}
static uint8_t
sis_5572_usb_unk_read(uint16_t addr, void *priv)
{
const sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
uint8_t ret = 0xff;
addr = (addr - dev->usb_unk_base) & 0x07;
ret = dev->usb_unk_regs[addr & 0x07];
sis_5572_usb_log("SiS 5572 USB UNK: [R] dev->usb_unk_regs[%02X] = %02X\n", addr, ret);
return ret;
}
void
sis_5572_usb_write(int addr, uint8_t val, void *priv)
{
sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
sis_5572_usb_log("SiS 5572 USB: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (dev->sis->usb_enabled) switch (addr) {
default:
break;
case 0x04: /* Command - Low Byte */
if (dev->rev == 0xb0)
dev->pci_conf[addr] = val & 0x47;
else
dev->pci_conf[addr] = val & 0x57;
if (dev->usb_unk_base != 0x0000) {
io_removehandler(dev->usb_unk_base, 0x0002,
sis_5572_usb_unk_read, NULL, NULL,
sis_5572_usb_unk_write, NULL, NULL, dev);
if (dev->pci_conf[0x04] & 0x01)
io_sethandler(dev->usb_unk_base, 0x0002,
sis_5572_usb_unk_read, NULL, NULL,
sis_5572_usb_unk_write, NULL, NULL, dev);
}
ohci_update_mem_mapping(dev->usb,
dev->pci_conf[0x11], dev->pci_conf[0x12],
dev->pci_conf[0x13], dev->pci_conf[0x04] & 0x02);
break;
case 0x05: /* Command - High Byte */
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= ~(val & 0xf9);
break;
case 0x0d: /* Latency Timer */
dev->pci_conf[addr] = val;
break;
case 0x11 ... 0x13: /* Memory Space Base Address Register */
dev->pci_conf[addr] = val & ((addr == 0x11) ? 0xf0 : 0xff);
ohci_update_mem_mapping(dev->usb,
dev->pci_conf[0x11], dev->pci_conf[0x12],
dev->pci_conf[0x13], dev->pci_conf[4] & 0x02);
break;
case 0x14 ... 0x15: /* IO Space Base Address Register */
if (dev->rev == 0xb0) {
if (dev->usb_unk_base != 0x0000) {
io_removehandler(dev->usb_unk_base, 0x0002,
sis_5572_usb_unk_read, NULL, NULL,
sis_5572_usb_unk_write, NULL, NULL, dev);
}
dev->pci_conf[addr] = val;
dev->usb_unk_base = (dev->pci_conf[0x14] & 0xf8) |
(dev->pci_conf[0x15] << 8);
if (dev->usb_unk_base != 0x0000) {
io_sethandler(dev->usb_unk_base, 0x0002,
sis_5572_usb_unk_read, NULL, NULL,
sis_5572_usb_unk_write, NULL, NULL, dev);
}
}
break;
case 0x2c ... 0x2f:
if (dev->rev == 0x11)
dev->pci_conf[addr] = val;
break;
case 0x3c: /* Interrupt Line */
dev->pci_conf[addr] = val;
break;
}
}
uint8_t
sis_5572_usb_read(int addr, void *priv)
{
const sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
uint8_t ret = 0xff;
if (dev->sis->usb_enabled) {
ret = dev->pci_conf[addr];
sis_5572_usb_log("SiS 5572 USB: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
}
return ret;
}
static void
sis_5572_usb_reset(void *priv)
{
sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x01;
dev->pci_conf[0x03] = 0x70;
dev->pci_conf[0x04] = dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = (dev->rev == 0xb0) ? 0x00 : 0x80;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = dev->rev;
dev->pci_conf[0x09] = 0x10;
dev->pci_conf[0x0a] = 0x03;
dev->pci_conf[0x0b] = 0x0c;
dev->pci_conf[0x0c] = dev->pci_conf[0x0d] = 0x00;
dev->pci_conf[0x0e] = 0x80 /* 0x10 - Datasheet erratum - header type 0x10 is invalid! */;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x10] = 0x00;
dev->pci_conf[0x11] = 0x00;
dev->pci_conf[0x12] = 0x00;
dev->pci_conf[0x13] = 0x00;
if (dev->rev == 0xb0) {
dev->pci_conf[0x14] = 0x01;
dev->pci_conf[0x15] = 0x00;
dev->pci_conf[0x16] = 0x00;
dev->pci_conf[0x17] = 0x00;
} else if (dev->rev == 0x11) {
dev->pci_conf[0x2c] = 0x00;
dev->pci_conf[0x2d] = 0x00;
dev->pci_conf[0x2e] = 0x00;
dev->pci_conf[0x2f] = 0x00;
}
dev->pci_conf[0x3c] = 0x00;
dev->pci_conf[0x3d] = PCI_INTA;
dev->pci_conf[0x3e] = 0x00;
dev->pci_conf[0x3f] = 0x00;
if (dev->rev == 0xb0) {
ohci_update_mem_mapping(dev->usb,
dev->pci_conf[0x11], dev->pci_conf[0x12],
dev->pci_conf[0x13], dev->pci_conf[0x04] & 0x02);
if (dev->usb_unk_base != 0x0000) {
io_removehandler(dev->usb_unk_base, 0x0002,
sis_5572_usb_unk_read, NULL, NULL,
sis_5572_usb_unk_write, NULL, NULL, dev);
}
dev->usb_unk_base = 0x0000;
memset(dev->usb_unk_regs, 0x00, sizeof(dev->usb_unk_regs));
}
}
static void
sis_5572_usb_close(void *priv)
{
sis_5572_usb_t *dev = (sis_5572_usb_t *) priv;
free(dev);
}
static void *
sis_5572_usb_init(UNUSED(const device_t *info))
{
sis_5572_usb_t *dev = (sis_5572_usb_t *) calloc(1, sizeof(sis_5572_usb_t));
dev->rev = info->local;
dev->sis = device_get_common_priv();
/* USB */
dev->usb = device_add(&usb_device);
sis_5572_usb_reset(dev);
return dev;
}
const device_t sis_5572_usb_device = {
.name = "SiS 5572 USB controller",
.internal_name = "sis_5572_usb",
.flags = DEVICE_PCI,
.local = 0xb0,
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5582_usb_device = {
.name = "SiS 5582 USB controller",
.internal_name = "sis_5582_usb",
.flags = DEVICE_PCI,
.local = 0xe0,
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sis_5595_usb_device = {
.name = "SiS 5595 USB controller",
.internal_name = "sis_5595_usb",
.flags = DEVICE_PCI,
.local = 0x11,
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5572_usb.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,049 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5571 Chipset.
*
*
*
* Authors: Tiseno100,
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/smram.h>
#include <86box/usb.h>
#include <86box/chipset.h>
/* Shadow RAM */
#define LSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
#define LSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
#define MSB_READ ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
#define MSB_WRITE ((dev->pci_conf[0x70 + (cur_reg & 0x07)] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
#define SYSTEM_READ ((dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
#define SYSTEM_WRITE ((dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
/* IDE Flags (1 Native / 0 Compatibility)*/
#define PRIMARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 1)
#define SECONDARY_COMP_NAT_SWITCH (dev->pci_conf_sb[1][9] & 4)
#define PRIMARY_NATIVE_BASE (dev->pci_conf_sb[1][0x11] << 8) | (dev->pci_conf_sb[1][0x10] & 0xf8)
#define PRIMARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x15] << 8) | (dev->pci_conf_sb[1][0x14] & 0xfc)) + 2)
#define SECONDARY_NATIVE_BASE (dev->pci_conf_sb[1][0x19] << 8) | (dev->pci_conf_sb[1][0x18] & 0xf8)
#define SECONDARY_NATIVE_SIDE (((dev->pci_conf_sb[1][0x1d] << 8) | (dev->pci_conf_sb[1][0x1c] & 0xfc)) + 2)
#define BUS_MASTER_BASE ((dev->pci_conf_sb[1][0x20] & 0xf0) | (dev->pci_conf_sb[1][0x21] << 8))
#ifdef ENABLE_SIS_5571_LOG
int sis_5571_do_log = ENABLE_SIS_5571_LOG;
static void
sis_5571_log(const char *fmt, ...)
{
va_list ap;
if (sis_5571_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5571_log(fmt, ...)
#endif
typedef struct sis_5571_t {
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t pad;
uint8_t usb_irq_state;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[3][256];
port_92_t *port_92;
sff8038i_t *ide_drive[2];
smram_t *smram;
usb_t *usb;
} sis_5571_t;
static void
sis_5571_shadow_recalc(int cur_reg, sis_5571_t *dev)
{
if (cur_reg != 0x76) {
mem_set_mem_state_both(0xc0000 + (0x8000 * (cur_reg & 0x07)), 0x4000, LSB_READ | LSB_WRITE);
mem_set_mem_state_both(0xc4000 + (0x8000 * (cur_reg & 0x07)), 0x4000, MSB_READ | MSB_WRITE);
} else
mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE);
flushmmucache_nopc();
}
static void
sis_5571_smm_recalc(sis_5571_t *dev)
{
smram_disable_all();
switch ((dev->pci_conf[0xa3] & 0xc0) >> 6) {
case 0x00:
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
case 0x01:
smram_enable(dev->smram, 0xe0000, 0xa0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
case 0x02:
smram_enable(dev->smram, 0xe0000, 0xb0000, 0x8000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
case 0x03:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1);
break;
default:
break;
}
flushmmucache();
}
void
sis_5571_ide_handler(sis_5571_t *dev)
{
ide_pri_disable();
ide_sec_disable();
if (dev->pci_conf_sb[1][4] & 1) {
if (dev->pci_conf_sb[1][0x4a] & 4) {
ide_set_base(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_BASE : 0x1f0);
ide_set_side(0, PRIMARY_COMP_NAT_SWITCH ? PRIMARY_NATIVE_SIDE : 0x3f6);
ide_pri_enable();
}
if (dev->pci_conf_sb[1][0x4a] & 2) {
ide_set_base(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_BASE : 0x170);
ide_set_side(1, SECONDARY_COMP_NAT_SWITCH ? SECONDARY_NATIVE_SIDE : 0x376);
ide_sec_enable();
}
}
}
void
sis_5571_bm_handler(sis_5571_t *dev)
{
sff_bus_master_handler(dev->ide_drive[0], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE);
sff_bus_master_handler(dev->ide_drive[1], dev->pci_conf_sb[1][4] & 4, BUS_MASTER_BASE + 8);
}
static void
memory_pci_bridge_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
switch (addr) {
case 0x04: /* Command - low byte */
case 0x05: /* Command - high byte */
dev->pci_conf[addr] |= val;
break;
case 0x06: /* Status - Low Byte */
dev->pci_conf[addr] &= val;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= val & 0xbe;
break;
case 0x0d: /* Master latency timer */
dev->pci_conf[addr] = val;
break;
case 0x50: /* Host Interface and DRAM arbiter */
dev->pci_conf[addr] = val & 0xec;
break;
case 0x51: /* CACHE */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val & 0xd0;
break;
case 0x53: /* DRAM */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x54: /* FP/EDO */
dev->pci_conf[addr] = val;
break;
case 0x55:
dev->pci_conf[addr] = val & 0xe0;
break;
case 0x56: /* MDLE delay */
case 0x57: /* SDRAM */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x59: /* Buffer strength and current rating */
dev->pci_conf[addr] = val;
break;
case 0x5a:
dev->pci_conf[addr] = val & 0x03;
break;
case 0x60: /* Undocumented */
case 0x61: /* Undocumented */
case 0x62: /* Undocumented */
case 0x63: /* Undocumented */
case 0x64: /* Undocumented */
case 0x65: /* Undocumented */
case 0x66: /* Undocumented */
case 0x67: /* Undocumented */
case 0x68: /* Undocumented */
case 0x69: /* Undocumented */
case 0x6a: /* Undocumented */
case 0x6b: /* Undocumented */
dev->pci_conf[addr] = val;
break;
case 0x70:
case 0x71:
case 0x72:
case 0x73:
case 0x74:
case 0x75:
case 0x76: /* Attribute of shadow RAM for BIOS area */
dev->pci_conf[addr] = val & ((addr != 0x76) ? 0xee : 0xe8);
sis_5571_shadow_recalc(addr, dev);
sis_5571_smm_recalc(dev);
break;
case 0x77: /* Characteristics of non-cacheable area */
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x78: /* Allocation of Non-Cacheable area #1 */
case 0x79: /* NCA1REG2 */
case 0x7a: /* Allocation of Non-Cacheable area #2 */
case 0x7b: /* NCA2REG2 */
dev->pci_conf[addr] = val;
break;
case 0x80: /* PCI master characteristics */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x81:
dev->pci_conf[addr] = val & 0xcc;
break;
case 0x82:
dev->pci_conf[addr] = val;
break;
case 0x83: /* CPU to PCI characteristics */
dev->pci_conf[addr] = val;
port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
break;
case 0x84:
case 0x85:
case 0x86:
dev->pci_conf[addr] = val;
break;
case 0x87: /* Miscellanea */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x90: /* PMU control register */
case 0x91: /* Address trap for green function */
case 0x92:
dev->pci_conf[addr] = val;
break;
case 0x93: /* STPCLK# and APM SMI control */
dev->pci_conf[addr] = val;
if ((dev->pci_conf[0x9b] & 1) && !!(val & 2)) {
smi_raise();
dev->pci_conf[0x9d] |= 1;
}
break;
case 0x94: /* 6x86 and Green function control */
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x95: /* Test mode control */
case 0x96: /* Time slot and Programmable 10-bit I/O port definition */
dev->pci_conf[addr] = val & 0xfb;
break;
case 0x97: /* programmable 10-bit I/O port address */
case 0x98: /* Programmable 16-bit I/O port */
case 0x99:
case 0x9a:
case 0x9b:
case 0x9c:
dev->pci_conf[addr] = val;
break;
case 0x9d:
dev->pci_conf[addr] &= val;
break;
case 0x9e: /* STPCLK# Assertion Timer */
case 0x9f: /* STPCLK# De-assertion Timer */
case 0xa0:
case 0xa1:
case 0xa2:
dev->pci_conf[addr] = val;
break;
case 0xa3: /* SMRAM access control and Power supply control */
dev->pci_conf[addr] = val & 0xd0;
sis_5571_smm_recalc(dev);
break;
default:
break;
}
sis_5571_log("SiS5571: dev->pci_conf[%02x] = %02x\n", addr, val);
}
static uint8_t
memory_pci_bridge_read(UNUSED(int func), int addr, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
sis_5571_log("SiS5571: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
return dev->pci_conf[addr];
}
static void
pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
switch (func) {
case 0: /* Bridge */
switch (addr) {
case 0x04: /* Command */
dev->pci_conf_sb[0][addr] |= val & 0x0f;
break;
case 0x06: /* Status */
dev->pci_conf_sb[0][addr] &= val;
break;
case 0x40: /* BIOS Control Register */
dev->pci_conf_sb[0][addr] = val & 0x3f;
break;
case 0x41: /* INTA# Remapping Control Register */
case 0x42: /* INTB# Remapping Control Register */
case 0x43: /* INTC# Remapping Control Register */
case 0x44: /* INTD# Remapping Control Register */
dev->pci_conf_sb[0][addr] = val & 0x8f;
pci_set_irq_routing((addr & 0x07), !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break;
case 0x45:
dev->pci_conf_sb[0][addr] = val & 0xec;
switch ((val & 0xc0) >> 6) {
case 0:
cpu_set_isa_speed(7159091);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(3);
break;
default:
break;
}
break;
case 0x46:
dev->pci_conf_sb[0][addr] = val & 0xec;
break;
case 0x47: /* DMA Clock and Wait State Control Register */
dev->pci_conf_sb[0][addr] = val & 0x3e;
break;
case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
dev->pci_conf_sb[0][addr] = val;
break;
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f:
case 0x50:
case 0x51:
case 0x52:
case 0x53:
case 0x54:
case 0x55:
case 0x56:
case 0x57:
case 0x58:
case 0x59:
case 0x5a:
case 0x5b:
case 0x5c:
case 0x5d:
case 0x5e:
dev->pci_conf_sb[0][addr] = val;
break;
case 0x5f:
dev->pci_conf_sb[0][addr] = val & 0x3f;
break;
case 0x60:
dev->pci_conf_sb[0][addr] = val;
break;
case 0x61: /* MIRQ Remapping Control Register */
dev->pci_conf_sb[0][addr] = val;
pci_set_mirq_routing(PCI_MIRQ0, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
break;
case 0x62: /* On-board Device DMA Control Register */
dev->pci_conf_sb[0][addr] = val & 0x0f;
dma_set_drq((val & 0x07), 1);
break;
case 0x63: /* IDEIRQ Remapping Control Register */
dev->pci_conf_sb[0][addr] = val & 0x8f;
if (val & 0x80) {
sff_set_irq_line(dev->ide_drive[0], val & 0x0f);
sff_set_irq_line(dev->ide_drive[1], val & 0x0f);
}
break;
case 0x64: /* GPIO Control Register */
dev->pci_conf_sb[0][addr] = val & 0xef;
break;
case 0x65:
dev->pci_conf_sb[0][addr] = val & 0x1b;
break;
case 0x66: /* GPIO Output Mode Control Register */
case 0x67: /* GPIO Output Mode Control Register */
dev->pci_conf_sb[0][addr] = val;
break;
case 0x68: /* USBIRQ Remapping Control Register */
dev->pci_conf_sb[0][addr] = val & 0x1b;
break;
case 0x69:
dev->pci_conf_sb[0][addr] = val;
break;
case 0x6a:
dev->pci_conf_sb[0][addr] = val & 0xfc;
break;
case 0x6b:
dev->pci_conf_sb[0][addr] = val;
break;
case 0x6c:
dev->pci_conf_sb[0][addr] = val & 0x03;
break;
case 0x6e: /* Software-Controlled Interrupt Request, Channels 7-0 */
case 0x6f: /* Software-Controlled Interrupt Request, channels 15-8 */
dev->pci_conf_sb[0][addr] = val;
break;
case 0x70:
dev->pci_conf_sb[0][addr] = val & 0xde;
break;
case 0x71: /* Type-F DMA Control Register */
dev->pci_conf_sb[0][addr] = val & 0xfe;
break;
case 0x72: /* SMI Triggered By IRQ/GPIO Control */
case 0x73: /* SMI Triggered By IRQ/GPIO Control */
dev->pci_conf_sb[0][addr] = (addr == 0x72) ? val & 0xfe : val;
break;
case 0x74: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */
case 0x75: /* System Standby Timer Reload, System Standby State Exit And Throttling State Exit Control */
case 0x76: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
dev->pci_conf_sb[0][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] = %02x\n", addr, val);
break;
case 1: /* IDE Controller */
switch (addr) {
case 0x04: /* Command low byte */
dev->pci_conf_sb[1][addr] = val & 0x05;
sis_5571_ide_handler(dev);
sis_5571_bm_handler(dev);
break;
case 0x07: /* Status high byte */
dev->pci_conf_sb[1][addr] &= val;
break;
case 0x09: /* Programming Interface Byte */
dev->pci_conf_sb[1][addr] = val & 0xcf;
sis_5571_ide_handler(dev);
break;
case 0x0d: /* Latency Time */
case 0x10: /* Primary Channel Base Address Register */
case 0x11: /* Primary Channel Base Address Register */
case 0x12: /* Primary Channel Base Address Register */
case 0x13: /* Primary Channel Base Address Register */
case 0x14: /* Primary Channel Base Address Register */
case 0x15: /* Primary Channel Base Address Register */
case 0x16: /* Primary Channel Base Address Register */
case 0x17: /* Primary Channel Base Address Register */
case 0x18: /* Secondary Channel Base Address Register */
case 0x19: /* Secondary Channel Base Address Register */
case 0x1a: /* Secondary Channel Base Address Register */
case 0x1b: /* Secondary Channel Base Address Register */
case 0x1c: /* Secondary Channel Base Address Register */
case 0x1d: /* Secondary Channel Base Address Register */
case 0x1e: /* Secondary Channel Base Address Register */
case 0x1f: /* Secondary Channel Base Address Register */
dev->pci_conf_sb[1][addr] = val;
sis_5571_ide_handler(dev);
break;
case 0x20: /* Bus Master IDE Control Register Base Address */
case 0x21: /* Bus Master IDE Control Register Base Address */
case 0x22: /* Bus Master IDE Control Register Base Address */
case 0x23: /* Bus Master IDE Control Register Base Address */
dev->pci_conf_sb[1][addr] = val;
sis_5571_bm_handler(dev);
break;
case 0x30: /* Expansion ROM Base Address */
case 0x31: /* Expansion ROM Base Address */
case 0x32: /* Expansion ROM Base Address */
case 0x33: /* Expansion ROM Base Address */
case 0x40: /* IDE Primary Channel/Master Drive Data Recovery Time Control */
case 0x41: /* IDE Primary Channel/Master Drive DataActive Time Control */
case 0x42: /* IDE Primary Channel/Slave Drive Data Recovery Time Control */
case 0x43: /* IDE Primary Channel/Slave Drive Data Active Time Control */
case 0x44: /* IDE Secondary Channel/Master Drive Data Recovery Time Control */
case 0x45: /* IDE Secondary Channel/Master Drive Data Active Time Control */
case 0x46: /* IDE Secondary Channel/Slave Drive Data Recovery Time Control */
case 0x47: /* IDE Secondary Channel/Slave Drive Data Active Time Control */
case 0x48: /* IDE Command Recovery Time Control */
case 0x49: /* IDE Command Active Time Control */
dev->pci_conf_sb[1][addr] = val;
break;
case 0x4a: /* IDE General Control Register 0 */
dev->pci_conf_sb[1][addr] = val & 0xaf;
sis_5571_ide_handler(dev);
break;
case 0x4b: /* IDE General Control register 1 */
case 0x4c: /* Prefetch Count of Primary Channel (Low Byte) */
case 0x4d: /* Prefetch Count of Primary Channel (High Byte) */
case 0x4e: /* Prefetch Count of Secondary Channel (Low Byte) */
case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
dev->pci_conf_sb[1][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val);
break;
case 2: /* USB Controller */
switch (addr) {
case 0x04: /* Command - Low Byte */
dev->pci_conf_sb[2][addr] = val;
ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1);
break;
case 0x05: /* Command - High Byte */
dev->pci_conf_sb[2][addr] = val & 0x03;
break;
case 0x06: /* Status - Low Byte */
dev->pci_conf_sb[2][addr] &= val & 0xc0;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf_sb[2][addr] &= val;
break;
case 0x10: /* Memory Space Base Address Register */
case 0x11: /* Memory Space Base Address Register */
case 0x12: /* Memory Space Base Address Register */
case 0x13: /* Memory Space Base Address Register */
dev->pci_conf_sb[2][addr] = val & ((addr == 0x11) ? 0x0f : 0xff);
ohci_update_mem_mapping(dev->usb, dev->pci_conf_sb[2][0x11], dev->pci_conf_sb[2][0x12], dev->pci_conf_sb[2][0x13], dev->pci_conf_sb[2][4] & 1);
break;
case 0x14: /* IO Space Base Address Register */
case 0x15: /* IO Space Base Address Register */
case 0x16: /* IO Space Base Address Register */
case 0x17: /* IO Space Base Address Register */
case 0x3c: /* Interrupt Line */
dev->pci_conf_sb[2][addr] = val;
break;
default:
break;
}
sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val);
break;
default:
break;
}
}
static uint8_t
pci_isa_bridge_read(int func, int addr, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
switch (func) {
case 0:
sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[0][addr]);
return dev->pci_conf_sb[0][addr];
case 1:
sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[1][addr]);
return dev->pci_conf_sb[1][addr];
case 2:
sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[2][addr]);
return dev->pci_conf_sb[2][addr];
default:
return 0xff;
}
}
static void
sis_5571_reset(void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
/* Memory/PCI Bridge */
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x71;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = 0xfd;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x9e] = 0xff;
dev->pci_conf[0x9f] = 0xff;
dev->pci_conf[0xa2] = 0xff;
/* PCI to ISA bridge */
dev->pci_conf_sb[0][0x00] = 0x39;
dev->pci_conf_sb[0][0x01] = 0x10;
dev->pci_conf_sb[0][0x02] = 0x08;
dev->pci_conf_sb[0][0x04] = 0xfd;
dev->pci_conf_sb[0][0x08] = 0x01;
dev->pci_conf_sb[0][0x0a] = 0x01;
dev->pci_conf_sb[0][0x0b] = 0x06;
/* IDE Controller */
dev->pci_conf_sb[1][0x00] = 0x39;
dev->pci_conf_sb[1][0x01] = 0x10;
dev->pci_conf_sb[1][0x02] = 0x13;
dev->pci_conf_sb[1][0x03] = 0x55;
dev->pci_conf_sb[1][0x08] = 0xc0;
dev->pci_conf_sb[1][0x0a] = 0x01;
dev->pci_conf_sb[1][0x0b] = 0x01;
dev->pci_conf_sb[1][0x0e] = 0x80;
dev->pci_conf_sb[1][0x4a] = 0x06;
sff_set_slot(dev->ide_drive[0], dev->sb_slot);
sff_set_slot(dev->ide_drive[1], dev->sb_slot);
sff_bus_master_reset(dev->ide_drive[0]);
sff_bus_master_reset(dev->ide_drive[1]);
/* USB Controller */
dev->pci_conf_sb[2][0x00] = 0x39;
dev->pci_conf_sb[2][0x01] = 0x10;
dev->pci_conf_sb[2][0x02] = 0x01;
dev->pci_conf_sb[2][0x03] = 0x70;
dev->pci_conf_sb[2][0x08] = 0xb0;
dev->pci_conf_sb[2][0x09] = 0x10;
dev->pci_conf_sb[2][0x0a] = 0x03;
dev->pci_conf_sb[2][0x0b] = 0xc0;
dev->pci_conf_sb[2][0x0e] = 0x80;
dev->pci_conf_sb[2][0x14] = 0x01;
dev->pci_conf_sb[2][0x3d] = 0x01;
}
static void
sis_5571_close(void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5571_init(UNUSED(const device_t *info))
{
sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t));
memset(dev, 0x00, sizeof(sis_5571_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev, &dev->nb_slot);
pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev, &dev->sb_slot);
/* MIRQ */
pci_enable_mirq(0);
/* Port 92 & SMRAM */
dev->port_92 = device_add(&port_92_pci_device);
dev->smram = smram_add();
/* SFF IDE */
dev->ide_drive[0] = device_add_inst(&sff8038i_device, 1);
dev->ide_drive[1] = device_add_inst(&sff8038i_device, 2);
/* USB */
dev->usb = device_add(&usb_device);
sis_5571_reset(dev);
return dev;
}
const device_t sis_5571_device = {
.name = "SiS 5571",
.internal_name = "sis_5571",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5571_init,
.close = sis_5571_close,
.reset = sis_5571_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5571_old.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,721 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.