text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185 values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C601/82C602 Buffer Devices.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/smram.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
typedef struct opti602_t {
uint8_t idx;
uint8_t regs[256];
uint8_t gpio[32];
uint16_t gpio_base;
uint16_t gpio_mask;
uint16_t gpio_size;
nvr_t *nvr;
} opti602_t;
#ifdef ENABLE_OPTI602_LOG
int opti602_do_log = ENABLE_OPTI602_LOG;
static void
opti602_log(const char *fmt, ...)
{
va_list ap;
if (opti602_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti602_log(fmt, ...)
#endif
static void
opti602_gpio_write(uint16_t addr, uint8_t val, void *priv)
{
opti602_t *dev = (opti602_t *) priv;
dev->gpio[addr - dev->gpio_base] = val;
}
static uint8_t
opti602_gpio_read(uint16_t addr, void *priv)
{
const opti602_t *dev = (opti602_t *) priv;
uint8_t ret = 0xff;
ret = dev->gpio[addr - dev->gpio_base];
return ret;
}
static void
opti602_gpio_recalc(opti602_t *dev)
{
if (dev->gpio_base != 0x0000)
io_removehandler(dev->gpio_base, dev->gpio_size, opti602_gpio_read, NULL, NULL, opti602_gpio_write, NULL, NULL, dev);
dev->gpio_base = dev->regs[0xf8];
dev->gpio_base |= (((uint16_t) dev->regs[0xf7]) << 8);
dev->gpio_size = 1 << ((dev->regs[0xf9] >> 2) & 0x07);
dev->gpio_mask = ~(dev->gpio_size - 1);
dev->gpio_base &= dev->gpio_mask;
dev->gpio_mask = ~dev->gpio_mask;
if (dev->gpio_base != 0x0000)
io_sethandler(dev->gpio_base, dev->gpio_size, opti602_gpio_read, NULL, NULL, opti602_gpio_write, NULL, NULL, dev);
}
static void
opti602_write(uint16_t addr, uint8_t val, void *priv)
{
opti602_t *dev = (opti602_t *) priv;
switch (addr) {
case 0x22:
dev->idx = val;
break;
case 0x24:
if ((dev->idx == 0xea) || ((dev->idx >= 0xf7) && (dev->idx <= 0xfa))) {
dev->regs[dev->idx] = val;
opti602_log("dev->regs[%04x] = %08x\n", dev->idx, val);
/* TODO: Registers 0x30-0x3F for OPTi 802GP and 898. */
switch (dev->idx) {
case 0xea:
/* GREEN Power Port */
break;
case 0xf7:
case 0xf8:
/* General Purpose Chip Select Registers */
opti602_gpio_recalc(dev);
break;
case 0xf9:
/* General Purpose Chip Select Register */
nvr_bank_set(0, !!(val & 0x20), dev->nvr);
opti602_gpio_recalc(dev);
break;
case 0xfa:
/* GPM Port */
break;
default:
break;
}
}
break;
default:
break;
}
}
static uint8_t
opti602_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
const opti602_t *dev = (opti602_t *) priv;
switch (addr) {
case 0x24:
if ((dev->idx == 0xea) || ((dev->idx >= 0xf7) && (dev->idx <= 0xfa))) {
ret = dev->regs[dev->idx];
if ((dev->idx == 0xfa) && (dev->regs[0xf9] & 0x40))
ret |= dev->regs[0xea];
}
break;
default:
break;
}
return ret;
}
static void
opti602_reset(void *priv)
{
opti602_t *dev = (opti602_t *) priv;
memset(dev->regs, 0x00, 256 * sizeof(uint8_t));
memset(dev->gpio, 0x00, 32 * sizeof(uint8_t));
dev->regs[0xfa] = 0x07;
dev->gpio[0x01] |= 0xfe;
nvr_bank_set(0, 0, dev->nvr);
opti602_gpio_recalc(dev);
}
static void
opti602_close(void *priv)
{
opti602_t *dev = (opti602_t *) priv;
free(dev);
}
static void *
opti602_init(UNUSED(const device_t *info))
{
opti602_t *dev = (opti602_t *) calloc(1, sizeof(opti602_t));
io_sethandler(0x0022, 0x0001, opti602_read, NULL, NULL, opti602_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti602_read, NULL, NULL, opti602_write, NULL, NULL, dev);
dev->nvr = device_add(&at_mb_nvr_device);
opti602_reset(dev);
return dev;
}
const device_t opti601_device = {
.name = "OPTi 82C601",
.internal_name = "opti601",
.flags = 0,
.local = 0,
.init = opti602_init,
.close = opti602_close,
.reset = opti602_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti602_device = {
.name = "OPTi 82C602",
.internal_name = "opti602",
.flags = 0,
.local = 0,
.init = opti602_init,
.close = opti602_close,
.reset = opti602_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti602.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,710 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the IMS 8848/8849 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
/*
IMS 884x Configuration Registers
Note: IMS 884x are rebadged ATMEL AT 40411/40412 chipsets
By: Tiseno100, Miran Grca(OBattler)
Register 00h:
Bit 3: F0000-FFFFF Shadow Enable
Bit 2: E0000-EFFFF Shadow Enable
Bit 0: ????
Register 04h:
Bit 3: Cache Write Hit Wait State
Bit 2: Cache Read Hit Wait State
Register 06h:
Bit 3: System BIOS Cacheable (1: Yes / 0: No)
Bit 1: Power Management Mode (1: IRQ / 0: SMI#)
Register 08h:
Bit 2: System BIOS Shadow Write (1: Enable / 0: Disable)
Bit 1: System BIOS Shadow Read?
Register 0Dh:
Bit 0: IO 100H-3FFH Idle Detect (1: Enable / 0: Disable)
Register 0Eh:
Bit 7: DMA & Local Bus Idle Detect (1: Enable / 0: Disable)
Bit 6: Floppy Disk Idle Detect (1: Enable / 0: Disable)
Bit 5: IDE Idle Detect (1: Enable / 0: Disable)
Bit 4: Serial Port Idle Detect (1: Enable / 0: Disable)
Bit 3: Parallel Port Idle Detect (1: Enable / 0: Disable)
Bit 2: Keyboard Idle Detect (1: Enable / 0: Disable)
Bit 1: Video Idle Detect (1: Enable / 0: Disable)
Register 12h:
Bits 3-2: Power Saving Timer (00 = 1 MIN, 01 = 3 MIN, 10 = 5 MIN, 11 = 8 MIN)
Bit 1: Base Memory (1: 512KB / 0: 640KB)
Register 1Ah:
Bit 3: Cache Write Hit W/S For PCI (1: Enabled / 0: Disable)
Bit 2: Cache Read Hit W/S For PCI (1: Enabled / 0: Disable)
Bit 1: VESA Clock Skew (1: 4ns/6ns, 0: No Delay/2ns)
Register 1Bh:
Bit 6: Enable SMRAM (always at 30000-4FFFF) in SMM
Bit 5: ????
Bit 4: Software SMI#
Bit 3: DC000-DFFFF Shadow Enable
Bit 2: D8000-DBFFF Shadow Enable
Bit 1: D4000-D7FFF Shadow Enable
Bit 0: D0000-D3FFF Shadow Enable
Register 1Ch:
Bits 7-4: INTA IRQ routing (0 = disabled, 1 to F = IRQ)
Bit 3: CC000-CFFFF Shadow Enable
Bit 2: C8000-CBFFF Shadow Enable
Bit 1: C4000-C7FFF Shadow Enable
Bit 0: C0000-C3FFF Shadow Enable
Register 1Dh:
Bits 7-4: INTB IRQ routing (0 = disabled, 1 to F = IRQ)
Register 1Eh:
Bits 7-4: INTC IRQ routing (0 = disabled, 1 to F = IRQ)
Bit 1: C4000-C7FFF Cacheable
Bit 0: C0000-C3FFF Cacheable
Register 21h:
Bits 7-4: INTD IRQ routing (0 = disabled, 1 to F = IRQ)
Register 22h:
Bit 5: Local Bus Master #2 select (0 = VESA, 1 = PCI)
Bit 4: Local Bus Master #1 select (0 = VESA, 1 = PCI)
Bits 1-0: Internal HADS# Delay Always (00 = No Delay, 01 = 1 Clk, 10 = 2 Clks)
Register 23h:
Bit 7: Seven Bits Tag (1: Enabled / 0: Disable)
Bit 3: Extend LBRDY#(VL Master) (1: Enabled / 0: Disable)
Bit 2: Sync LRDY#(VL Slave) (1: Enabled / 0: Disable)
Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable)
*/
typedef struct ims8848_t {
uint8_t idx;
uint8_t access_data;
uint8_t pci_slot;
uint8_t pad;
uint8_t regs[256];
uint8_t pci_conf[256];
smram_t *smram;
} ims8848_t;
#ifdef ENABLE_IMS8848_LOG
int ims8848_do_log = ENABLE_IMS8848_LOG;
static void
ims8848_log(const char *fmt, ...)
{
va_list ap;
if (ims8848_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ims8848_log(fmt, ...)
#endif
/* Shadow write always enabled, 1B and 1C control C000-DFFF read. */
static void
ims8848_recalc(ims8848_t *dev)
{
int state_on;
uint32_t base;
ims8848_log("SHADOW: 00 = %02X, 08 = %02X, 1B = %02X, 1C = %02X\n",
dev->regs[0x00], dev->regs[0x08], dev->regs[0x1b], dev->regs[0x1c]);
state_on = MEM_READ_INTERNAL;
state_on |= (dev->regs[0x08] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
for (uint8_t i = 0; i < 2; i++) {
base = 0xe0000 + (i << 16);
if (dev->regs[0x00] & (1 << (i + 2)))
mem_set_mem_state_both(base, 0x10000, state_on);
else
mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if (dev->regs[0x1c] & (1 << i))
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
base = 0xd0000 + (i << 14);
if (dev->regs[0x1b] & (1 << i))
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
flushmmucache_nopc();
}
static void
ims8848_base_memory(ims8848_t *dev)
{
/* We can use the proper mem_set_access to handle that. */
mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x12] & 2) ? (MEM_READ_DISABLED | MEM_WRITE_DISABLED) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
}
static void
ims8848_smram(ims8848_t *dev)
{
smram_disable_all();
smram_enable(dev->smram, 0x00030000, 0x00030000, 0x20000, dev->regs[0x1b] & 0x40, 1);
}
static void
ims8848_write(uint16_t addr, uint8_t val, void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
uint8_t old = dev->regs[dev->idx];
switch (addr) {
case 0x22:
ims8848_log("[W] IDX = %02X\n", val);
dev->idx = val;
break;
case 0x23:
ims8848_log("[W] IDX IN = %02X\n", val);
if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0)))
dev->access_data = 1;
break;
case 0x24:
ims8848_log("[W] [%i] REG %02X = %02X\n", dev->access_data, dev->idx, val);
if (dev->access_data) {
dev->regs[dev->idx] = val;
switch (dev->idx) {
case 0x00:
case 0x08:
case 0x1b:
case 0x1c:
/* Shadow RAM */
ims8848_recalc(dev);
if (dev->idx == 0x1b) {
ims8848_smram(dev);
if (!(old & 0x10) && (val & 0x10))
smi_raise();
} else if (dev->idx == 0x1c)
pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
break;
case 0x1d:
case 0x1e:
pci_set_irq_routing(PCI_INTB + (dev->idx - 0x1d), (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
break;
case 0x21:
pci_set_irq_routing(PCI_INTD, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
break;
case 0x12:
/* Base Memory */
ims8848_base_memory(dev);
break;
default:
break;
}
dev->access_data = 0;
}
break;
default:
break;
}
}
static uint8_t
ims8848_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
ims8848_t *dev = (ims8848_t *) priv;
#ifdef ENABLE_IMS8848_LOG
uint8_t old_ad = dev->access_data;
#endif
switch (addr) {
case 0x22:
ims8848_log("[R] IDX = %02X\n", ret);
ret = dev->idx;
break;
case 0x23:
ims8848_log("[R] IDX IN = %02X\n", ret);
ret = (dev->idx >> 4) | (dev->idx << 4);
break;
case 0x24:
if (dev->access_data) {
ret = dev->regs[dev->idx];
dev->access_data = 0;
}
ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret);
break;
default:
break;
}
return ret;
}
static void
ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
ims8848_log("IMS 884x-PCI: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80));
if (func == 0)
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val;
break;
case 0x05:
dev->pci_conf[addr] = val & 3;
break;
case 0x07:
dev->pci_conf[addr] &= val & 0xf7;
break;
case 0x0c ... 0x0d:
dev->pci_conf[addr] = val;
break;
case 0x52 ... 0x55:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
static uint8_t
ims8849_pci_read(int func, int addr, void *priv)
{
const ims8848_t *dev = (ims8848_t *) priv;
uint8_t ret = 0xff;
if (func == 0)
ret = dev->pci_conf[addr];
return ret;
}
static void
ims8848_reset(void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
memset(dev->regs, 0x00, sizeof(dev->regs));
memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
dev->pci_conf[0x00] = 0xe0; /* Integrated Micro Solutions (IMS) */
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x49; /* 8849 */
dev->pci_conf[0x03] = 0x88;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x0b] = 0x06;
ims8848_recalc(dev); /* Shadow RAM Setup */
ims8848_base_memory(dev); /* Base Memory Setup */
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
ims8848_smram(dev);
}
static void
ims8848_close(void *priv)
{
ims8848_t *dev = (ims8848_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
ims8848_init(UNUSED(const device_t *info))
{
ims8848_t *dev = (ims8848_t *) malloc(sizeof(ims8848_t));
memset(dev, 0, sizeof(ims8848_t));
device_add(&port_92_device);
/* IMS 8848:
22h Index
23h Data Unlock
24h Data
IMS 8849:
PCI Device 0: IMS 8849 Dummy for compatibility reasons
*/
io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev);
pci_add_card(PCI_ADD_NORTHBRIDGE, ims8849_pci_read, ims8849_pci_write, dev, &dev->pci_slot);
dev->smram = smram_add();
smram_set_separate_smram(1);
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
ims8848_reset(dev);
return dev;
}
const device_t ims8848_device = {
.name = "IMS 8848/8849",
.internal_name = "ims8848",
.flags = 0,
.local = 0,
.init = ims8848_init,
.close = ims8848_close,
.reset = ims8848_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ims8848.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,731 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C391/392 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI391_LOG
int opti391_do_log = ENABLE_OPTI391_LOG;
static void
opti391_log(const char *fmt, ...)
{
va_list ap;
if (opti391_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti391_log(fmt, ...)
#endif
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct opti391_t {
uint8_t type;
uint8_t reg_base;
uint8_t min_reg;
uint8_t max_reg;
uint16_t shadowed;
uint16_t old_start;
uint8_t index;
uint8_t regs[256];
} opti391_t;
static void
opti391_recalcremap(opti391_t *dev)
{
if (dev->type < 2) {
if ((mem_size > 8192) || (dev->shadowed & 0x0ff0) ||
!(dev->regs[0x01] & 0x0f) || !(dev->regs[0x01] & 0x10)) {
mem_remap_top_ex(0, dev->old_start);
dev->old_start = 1024;
} else {
mem_remap_top_ex(0, dev->old_start);
dev->old_start = (dev->regs[0x01] & 0x0f) * 1024;
mem_remap_top_ex(-256, dev->old_start);
}
}
}
static void
opti391_shadow_recalc(opti391_t *dev)
{
uint32_t base;
uint8_t sh_enable;
uint8_t sh_master;
uint8_t sh_wp;
uint8_t sh_write_internal;
shadowbios = shadowbios_write = 0;
/* F0000-FFFFF */
sh_enable = (dev->regs[0x02] & 0x80);
if (sh_enable)
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
else
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
dev->shadowed |= 0xf000;
sh_write_internal = (dev->regs[0x06] & 0x40);
/* D0000-EFFFF */
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if (base >= 0xe0000) {
sh_master = (dev->regs[0x02] & 0x20);
sh_wp = (dev->regs[0x02] & 0x08);
} else {
sh_master = (dev->regs[0x02] & 0x40);
sh_wp = (dev->regs[0x02] & 0x10);
}
sh_enable = dev->regs[0x03] & (1 << i);
if (sh_master) {
if (sh_enable) {
if (sh_wp)
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << (i + 4));
} else if (sh_write_internal) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << (i + 4));
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
dev->shadowed &= ~(1 << (i + 4));
}
} else if (sh_write_internal) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << (i + 4));
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
dev->shadowed &= ~(1 << (i + 4));
}
}
/* C0000-CFFFF */
sh_master = (dev->regs[0x06] & 0x10); /* OPTi 391 datasheet erratum! */
sh_wp = (dev->regs[0x06] & 0x20);
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
sh_enable = dev->regs[0x06] & (1 << i);
if (sh_master) {
if (sh_enable) {
if (sh_wp)
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << i);
} else if (sh_write_internal) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << i);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
dev->shadowed &= ~(1 << i);
}
} else if (sh_write_internal) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
dev->shadowed |= (1 << i);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
dev->shadowed &= ~(1 << i);
}
}
opti391_recalcremap(dev);
}
static void
opti391_write(uint16_t addr, uint8_t val, void *priv)
{
opti391_t *dev = (opti391_t *) priv;
opti391_log("[W] %04X = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x22:
dev->index = val;
break;
case 0x24:
opti391_log("OPTi 391: dev->regs[%02x] = %02x\n", dev->index, val);
if ((dev->index <= 0x01) && (dev->type < 2)) switch (dev->index) {
case 0x00:
if (!(dev->regs[0x10] & 0x20) && (val & 0x20)) {
softresetx86(); /* Pulse reset! */
cpu_set_edx();
flushmmucache();
}
dev->regs[dev->index + 0x10] = val;
break;
case 0x01:
dev->regs[dev->index + 0x10] = val;
reset_on_hlt = !!(val & 0x02);
break;
} else switch (dev->index - dev->reg_base) {
default:
break;
case 0x00:
if (dev->type == 2) {
reset_on_hlt = !!(val & 0x02);
if (!(dev->regs[dev->index - dev->reg_base] & 0x01) && (val & 0x01)) {
softresetx86(); /* Pulse reset! */
cpu_set_edx();
flushmmucache();
}
dev->regs[dev->index - dev->reg_base] =
(dev->regs[dev->index - dev->reg_base] & 0xc0) | (val & 0x3f);
}
break;
case 0x01:
dev->regs[dev->index - dev->reg_base] = val;
if (dev->type == 2) {
cpu_cache_ext_enabled = !!(dev->regs[0x01] & 0x10);
cpu_update_waitstates();
} else
opti391_recalcremap(dev);
break;
case 0x05:
if (dev->type == 2)
dev->regs[dev->index - dev->reg_base] = val & 0xf8;
else
dev->regs[dev->index - dev->reg_base] = val;
break;
case 0x04:
case 0x09:
case 0x0a:
case 0x0b:
dev->regs[dev->index - dev->reg_base] = val;
break;
case 0x07:
dev->regs[dev->index - dev->reg_base] = val;
if (dev->type < 2) {
mem_a20_alt = val & 0x08;
mem_a20_recalc();
}
break;
case 0x08:
if (dev->type == 2)
dev->regs[dev->index - dev->reg_base] = val & 0xe3;
else {
dev->regs[dev->index - dev->reg_base] = val;
cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x40);
cpu_update_waitstates();
}
break;
case 0x0c:
case 0x0d:
if (dev->type < 2)
dev->regs[dev->index - dev->reg_base] = val;
break;
case 0x02:
case 0x03:
case 0x06:
opti391_log("Write %02X: %02X\n", dev->index - dev->reg_base, val);
dev->regs[dev->index - dev->reg_base] = val;
opti391_shadow_recalc(dev);
break;
}
dev->index = 0xff;
break;
}
}
static uint8_t
opti391_read(uint16_t addr, void *priv)
{
opti391_t *dev = (opti391_t *) priv;
uint8_t ret = 0xff;
if (addr == 0x24) {
if ((dev->index <= 0x01) && (dev->type < 2))
ret = dev->regs[dev->index + 0x10];
else if ((dev->index >= dev->min_reg) && (dev->index <= dev->max_reg))
ret = dev->regs[dev->index - dev->reg_base];
dev->index = 0xff;
}
opti391_log("[R] %04X = %02X\n", addr, ret);
return ret;
}
static void
opti391_close(void *priv)
{
opti391_t *dev = (opti391_t *) priv;
free(dev);
}
static void *
opti391_init(const device_t *info)
{
opti391_t *dev = (opti391_t *) calloc(1, sizeof(opti391_t));
io_sethandler(0x0022, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti391_read, NULL, NULL, opti391_write, NULL, NULL, dev);
dev->type = info->local;
if (info->local == 2) {
dev->reg_base = 0x20;
dev->min_reg = 0x20;
dev->max_reg = 0x2b;
dev->regs[0x02] = 0x84;
dev->regs[0x04] = 0x07;
dev->regs[0x05] = 0xf0;
dev->regs[0x06] = 0x30;
dev->regs[0x07] = 0x91;
dev->regs[0x08] = 0x80;
dev->regs[0x09] = 0x10;
dev->regs[0x0a] = 0x80;
dev->regs[0x0b] = 0x10;
} else {
dev->reg_base = 0x0f;
dev->min_reg = 0x10;
dev->max_reg = 0x1c;
dev->regs[0x01] = 0x01;
dev->regs[0x02] = 0xe0;
if (info->local == 1)
/* Guess due to no OPTi 48x datasheet. */
dev->regs[0x04] = 0x07;
else
dev->regs[0x04] = 0x77;
dev->regs[0x05] = 0x60;
dev->regs[0x06] = 0x10;
dev->regs[0x07] = 0x50;
if (info->local == 1) {
/* Guess due to no OPTi 48x datasheet. */
dev->regs[0x09] = 0x80; /* Non-Cacheable Block 1 */
dev->regs[0x0b] = 0x80; /* Non-Cacheable Block 2 */
dev->regs[0x0d] = 0x91; /* Cacheable Area */
} else {
dev->regs[0x09] = 0xe0; /* Non-Cacheable Block 1 */
dev->regs[0x0b] = 0x10; /* Non-Cacheable Block 2 */
dev->regs[0x0d] = 0x80; /* Cacheable Area */
}
dev->regs[0x0a] = 0x10;
dev->regs[0x0c] = 0x10;
}
dev->old_start = 1024;
opti391_shadow_recalc(dev);
return dev;
}
const device_t opti381_device = {
.name = "OPTi 82C381",
.internal_name = "opti381",
.flags = 0,
.local = 0,
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti481_device = {
.name = "OPTi 82C481",
.internal_name = "opti481",
.flags = 0,
.local = 1,
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti391_device = {
.name = "OPTi 82C391",
.internal_name = "opti391",
.flags = 0,
.local = 2,
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti391.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,700 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC HB4 "Super Energy Star Green" PCI Chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
* Note 2: Additional information were also used from all
* around the web.
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
/*
UMC HB4 Configuration Registers
Sources & Notes:
Cache registers were found at Vogons: path_to_url
Basic Reverse engineering effort was done personally by me
Warning: Register documentation may be inaccurate!
UMC 8881x:
Register 50:
Bit 7: Enable L2 Cache
Bit 6: Cache Policy (0: Write Thru / 1: Write Back)
Bit 5-4 Cache Speed
0 0 Read 3-2-2-2 Write 3T
0 1 Read 3-1-1-1 Write 3T
1 0 Read 2-2-2-2 Write 2T
1 1 Read 2-1-1-1 Write 2T
Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
Bit 2-1-0 Cache Size
0 0 0 0KB
0 0 1 64KB
x-x-x Multiplications of 2(64*2 for 0 1 0) till 2MB
Register 51:
Bit 7-6 DRAM Read Speed
5-4 DRAM Write Speed
0 0 1 Waits
0 1 1 Waits
1 0 1 Wait
1 1 0 Waits
Bit 3 Resource Lock Enable
Bit 2 Graphics Adapter (0: VL Bus / 1: PCI Bus)
Bit 1 L1 WB Policy (0: WT / 1: WB)
Bit 0 L2 Cache Tag Lenght (0: 7 Bits / 1: 8 Bits)
Register 52:
Bit 7: Host-to-PCI Post Write (0: 1 Wait State / 1: 0 Wait States)
Register 54:
Bit 7: DC000-DFFFF Read Enable
Bit 6: D8000-DBFFF Read Enable
Bit 5: D4000-D7FFF Read Enable
Bit 4: D0000-D3FFF Read Enable
Bit 3: CC000-CFFFF Read Enable
Bit 2: C8000-CBFFF Read Enable
Bit 1: C0000-C7FFF Read Enable
Bit 0: E0000-EFFFF Read Enable
Register 55:
Bit 7: F0000-FFFF Read Enable
Bit 6: Shadow Write Status (1: Write Protect/0: Write)
Register 56h & 57h: DRAM Bank 0 Configuration
Register 58h & 59h: DRAM Bank 1 Configuration
Register 5A:
Bit 2: Detrubo
Register 5C:
Bits 7-0: SMRAM base A27-A20
Register 5D:
Bits 3-0: SMRAM base A31-A28
Register 60:
Bit 5: If set and SMRAM is enabled, data cycles go to PCI and code cycles go to DRAM
Bit 0: SMRAM Local Access Enable - if set, SMRAM is also enabled outside SMM
SMRAM appears to always be enabled in SMM, and always set to A0000-BFFFF.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_HB4_LOG
int hb4_do_log = ENABLE_HB4_LOG;
static void
hb4_log(const char *fmt, ...)
{
va_list ap;
if (hb4_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define hb4_log(fmt, ...)
#endif
typedef struct hb4_t {
uint8_t pci_slot;
uint8_t pci_conf[256]; /* PCI Registers */
int mem_state[9];
uint32_t smram_base;
smram_t *smram; /* SMRAM Handler */
} hb4_t;
static int shadow_bios[4] = { (MEM_READ_EXTANY | MEM_WRITE_INTERNAL), (MEM_READ_EXTANY | MEM_WRITE_EXTANY),
(MEM_READ_INTERNAL | MEM_WRITE_INTERNAL), (MEM_READ_INTERNAL | MEM_WRITE_EXTANY) };
static int shadow_read[2] = { MEM_READ_EXTANY, MEM_READ_INTERNAL };
static int shadow_write[2] = { MEM_WRITE_INTERNAL, MEM_WRITE_EXTANY };
int
hb4_shadow_bios_high(hb4_t *dev)
{
int state;
state = shadow_bios[dev->pci_conf[0x55] >> 6];
if (state != dev->mem_state[8]) {
mem_set_mem_state_both(0xf0000, 0x10000, state);
if ((dev->mem_state[8] & MEM_READ_INTERNAL) && !(state & MEM_READ_INTERNAL))
mem_invalidate_range(0xf0000, 0xfffff);
dev->mem_state[8] = state;
return 1;
}
return 0;
}
int
hb4_shadow_bios_low(hb4_t *dev)
{
int state;
/* Erratum in Vogons' datasheet: Register 55h bit 7 in fact controls E0000-FFFFF. */
state = shadow_bios[dev->pci_conf[0x55] >> 6];
if (state != dev->mem_state[7]) {
mem_set_mem_state_both(0xe0000, 0x10000, state);
dev->mem_state[7] = state;
return 1;
}
return 0;
}
int
hb4_shadow_main(hb4_t *dev)
{
int state;
int n = 0;
for (uint8_t i = 0; i < 6; i++) {
state = shadow_read[(dev->pci_conf[0x54] >> (i + 2)) & 0x01] |
shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
if (state != dev->mem_state[i + 1]) {
n++;
mem_set_mem_state_both(0xc8000 + (i << 14), 0x4000, state);
dev->mem_state[i + 1] = state;
}
}
return n;
}
int
hb4_shadow_video(hb4_t *dev)
{
int state;
state = shadow_read[(dev->pci_conf[0x54] >> 1) & 0x01] |
shadow_write[(dev->pci_conf[0x55] >> 6) & 0x01];
if (state != dev->mem_state[0]) {
mem_set_mem_state_both(0xc0000, 0x8000, state);
dev->mem_state[0] = state;
return 1;
}
return 0;
}
void
hb4_shadow(hb4_t *dev)
{
int n = 0;
hb4_log("SHADOW: %02X%02X\n", dev->pci_conf[0x55], dev->pci_conf[0x54]);
n = hb4_shadow_bios_high(dev);
n += hb4_shadow_bios_low(dev);
n += hb4_shadow_main(dev);
n += hb4_shadow_video(dev);
if (n > 0)
flushmmucache_nopc();
}
static void
hb4_smram(hb4_t *dev)
{
smram_disable_all();
if (dev->smram_base != 0x00000000)
umc_smram_recalc(dev->smram_base >> 12, 0);
dev->smram_base = ((uint32_t) dev->pci_conf[0x5c]) << 20;
dev->smram_base |= ((uint32_t) (dev->pci_conf[0x5d] & 0x0f)) << 28;
dev->smram_base |= 0x000a0000;
/* Bit 0, if set, enables SMRAM access outside SMM. SMRAM appears to be always enabled
in SMM, and is always set to A0000-BFFFF. */
smram_enable(dev->smram, dev->smram_base, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
/* Bit 5 seems to set data to go to PCI and code to DRAM. The Samsung SPC7700P-LW uses
this. */
if (dev->pci_conf[0x60] & 0x20) {
if (dev->pci_conf[0x60] & 0x01)
mem_set_mem_state_smram_ex(0, dev->smram_base, 0x20000, 0x02);
mem_set_mem_state_smram_ex(1, dev->smram_base, 0x20000, 0x02);
}
umc_smram_recalc(dev->smram_base >> 12, 1);
}
static void
hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *) priv;
hb4_log("UM8881: dev->regs[%02x] = %02x POST: %02x \n", addr, val, inb(0x80));
switch (addr) {
case 0x04:
case 0x05:
dev->pci_conf[addr] = val;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf9);
break;
case 0x0c:
case 0x0d:
dev->pci_conf[addr] = val;
break;
case 0x50:
dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/
cpu_update_waitstates();
break;
case 0x51 ... 0x53:
dev->pci_conf[addr] = val;
break;
case 0x54 ... 0x55:
dev->pci_conf[addr] = val;
hb4_shadow(dev);
break;
case 0x56 ... 0x5b:
case 0x5e ... 0x5f:
dev->pci_conf[addr] = val;
break;
case 0x5c ... 0x5d:
case 0x60:
dev->pci_conf[addr] = val;
hb4_smram(dev);
break;
case 0x61 ... 0x62:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
static uint8_t
hb4_read(int func, int addr, void *priv)
{
const hb4_t *dev = (hb4_t *) priv;
uint8_t ret = 0xff;
if (func == 0)
ret = dev->pci_conf[addr];
return ret;
}
static void
hb4_reset(void *priv)
{
hb4_t *dev = (hb4_t *) priv;
memset(dev->pci_conf, 0x00, sizeof(dev->pci_conf));
dev->pci_conf[0x00] = 0x60; /* UMC */
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x81; /* 8881x */
dev->pci_conf[0x03] = 0x88;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x04;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x50] = 0x00;
dev->pci_conf[0x51] = 0x00;
dev->pci_conf[0x52] = 0x01;
dev->pci_conf[0x53] = 0x00;
dev->pci_conf[0x54] = 0x00;
dev->pci_conf[0x55] = 0x00;
dev->pci_conf[0x56] = 0x00;
dev->pci_conf[0x57] = 0x00;
dev->pci_conf[0x58] = 0x00;
dev->pci_conf[0x59] = 0x00;
dev->pci_conf[0x5a] = 0x04;
dev->pci_conf[0x5c] = 0x00;
dev->pci_conf[0x5d] = 0x20;
dev->pci_conf[0x5f] = 0xff;
dev->pci_conf[0x60] = 0x00;
dev->pci_conf[0x61] = 0x00;
dev->pci_conf[0x62] = 0x00;
hb4_shadow(dev);
hb4_smram(dev);
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
memset(dev->mem_state, 0x00, sizeof(dev->mem_state));
}
static void
hb4_close(void *priv)
{
hb4_t *dev = (hb4_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
hb4_init(UNUSED(const device_t *info))
{
hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev, &dev->pci_slot); /* Device 10: UMC 8881x */
/* Port 92 */
device_add(&port_92_pci_device);
/* SMRAM */
dev->smram = smram_add();
dev->smram_base = 0x000a0000;
hb4_reset(dev);
return dev;
}
const device_t umc_hb4_device = {
.name = "UMC HB4(8881F)",
.internal_name = "umc_hb4",
.flags = DEVICE_PCI,
.local = 0x886a,
.init = hb4_init,
.close = hb4_close,
.reset = hb4_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/umc_hb4.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,599 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C493/82C495 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct opti495_t {
uint8_t type;
uint8_t max;
uint8_t idx;
uint8_t regs[256];
uint8_t scratch[2];
} opti495_t;
#ifdef ENABLE_OPTI495_LOG
int opti495_do_log = ENABLE_OPTI495_LOG;
static void
opti495_log(const char *fmt, ...)
{
va_list ap;
if (opti495_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti495_log(fmt, ...)
#endif
enum {
OPTI493 = 0,
OPTI495,
OPTI495SLC,
OPTI495SX,
OPTI495XLC,
TMAX
};
/* OPTi 82C493: According to The Last Byte, bit 1 of register 22h, while unused, must still be writable. */
static uint8_t masks[TMAX][0x1c] = { { 0x3f, 0xff, 0xff, 0xff, 0xf7, 0xfb, 0x7f, 0x9f, 0xe3, 0xff, 0xe3, 0xff },
{ 0x3a, 0x7f, 0xff, 0xff, 0xf0, 0xfb, 0x7f, 0xbf, 0xe3, 0xff, 0x00, 0x00 },
{ 0x3a, 0x7f, 0xfc, 0xff, 0xf0, 0xfb, 0xff, 0xbf, 0xe3, 0xff, 0x00, 0x00 },
{ 0x3a, 0xff, 0xfd, 0xff, 0xf0, 0xfb, 0x7f, 0xbf, 0xe3, 0xff, 0x00, 0x00 },
{ 0x3a, 0xff, 0xfc, 0xff, 0xf0, 0xfb, 0xff, 0xbf, 0xe3, 0xff, 0x00, 0x00 } };
static void
opti495_recalc(opti495_t *dev)
{
uint32_t base;
uint32_t shflags = 0;
shadowbios = 0;
shadowbios_write = 0;
if (dev->regs[0x22] & 0x80) {
shadowbios = 1;
shadowbios_write = 0;
shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
} else {
shadowbios = 0;
shadowbios_write = 1;
shflags = MEM_READ_INTERNAL | MEM_WRITE_DISABLED;
}
mem_set_mem_state_both(0xf0000, 0x10000, shflags);
for (uint8_t i = 0; i < 8; i++) {
base = 0xd0000 + (i << 14);
if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
if (dev->regs[0x26] & 0x40) {
shflags = MEM_READ_EXTANY;
shflags |= (dev->regs[0x22] & ((base >= 0xe0000) ? 0x08 : 0x10)) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
}
mem_set_mem_state_both(base, 0x4000, shflags);
}
for (uint8_t i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
shflags = MEM_READ_INTERNAL;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else {
if (dev->regs[0x26] & 0x40) {
shflags = MEM_READ_EXTANY;
shflags |= (dev->regs[0x26] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
} else
shflags = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
}
mem_set_mem_state_both(base, 0x4000, shflags);
}
flushmmucache();
}
static void
opti495_write(uint16_t addr, uint8_t val, void *priv)
{
opti495_t *dev = (opti495_t *) priv;
switch (addr) {
default:
break;
case 0x22:
opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val);
dev->idx = val;
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= dev->max)) {
opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val);
dev->regs[dev->idx] = val & masks[dev->type][dev->idx - 0x20];
if ((dev->type == OPTI493) && (dev->idx == 0x20))
val |= 0x40;
switch (dev->idx) {
default:
break;
case 0x21:
cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10);
cpu_update_waitstates();
break;
case 0x22:
case 0x23:
case 0x26:
opti495_recalc(dev);
break;
}
}
dev->idx = 0xff;
break;
case 0xe1:
case 0xe2:
dev->scratch[~addr & 0x01] = val;
break;
}
}
static uint8_t
opti495_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti495_t *dev = (opti495_t *) priv;
switch (addr) {
case 0x22:
opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret);
break;
case 0x24:
if ((dev->idx >= 0x20) && (dev->idx <= dev->max)) {
ret = dev->regs[dev->idx];
opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret);
}
dev->idx = 0xff;
break;
case 0xe1:
case 0xe2:
ret = dev->scratch[~addr & 0x01];
break;
default:
break;
}
return ret;
}
static void
opti495_close(void *priv)
{
opti495_t *dev = (opti495_t *) priv;
free(dev);
}
static void *
opti495_init(const device_t *info)
{
opti495_t *dev = (opti495_t *) malloc(sizeof(opti495_t));
memset(dev, 0, sizeof(opti495_t));
device_add(&port_92_device);
io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
dev->scratch[0] = dev->scratch[1] = 0xff;
dev->type = info->local;
if (info->local >= OPTI495) {
/* 85C495 */
dev->max = 0x29;
dev->regs[0x20] = 0x02;
dev->regs[0x21] = 0x20;
dev->regs[0x22] = 0xe4;
dev->regs[0x25] = 0xf0;
dev->regs[0x26] = 0x80;
dev->regs[0x27] = 0xb1;
dev->regs[0x28] = 0x80;
dev->regs[0x29] = 0x10;
} else {
/* 85C493 */
dev->max = 0x2b;
dev->regs[0x20] = 0x40;
dev->regs[0x22] = 0x84;
dev->regs[0x24] = 0x87;
dev->regs[0x25] = 0xf1; /* Note: 0xf0 is also valid default. */
dev->regs[0x27] = 0x91;
dev->regs[0x28] = 0x80;
dev->regs[0x29] = 0x10;
dev->regs[0x2a] = 0x80;
dev->regs[0x2b] = 0x10;
}
opti495_recalc(dev);
io_sethandler(0x00e1, 0x0002, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
return dev;
}
const device_t opti493_device = {
.name = "OPTi 82C493",
.internal_name = "opti493",
.flags = 0,
.local = OPTI493,
.init = opti495_init,
.close = opti495_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti495_device = {
.name = "OPTi 82C495",
.internal_name = "opti495",
.flags = 0,
.local = OPTI495XLC,
.init = opti495_init,
.close = opti495_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti495.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,702 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the Intel PIIX, PIIX3, PIIX4, PIIX4E, and SMSC
* SLC90E66 (Victory66) Xcelerators.
*
* PRD format :
* word 0 - base address
* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/keyboard.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/acpi.h>
#include <86box/ddma.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/plat.h>
#include <86box/port_92.h>
#include <86box/scsi_device.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/usb.h>
#include <86box/machine.h>
#include <86box/smbus.h>
#include <86box/chipset.h>
typedef struct piix_io_trap_t {
struct _piix_ *dev;
void *trap;
uint8_t dev_id;
uint32_t *sts_reg, *en_reg, sts_mask, en_mask;
} piix_io_trap_t;
typedef struct _piix_ {
uint8_t cur_readout_reg;
uint8_t rev;
uint8_t type;
uint8_t func_shift;
uint8_t max_func;
uint8_t pci_slot;
uint8_t no_mirq0;
uint8_t regs[4][256];
uint8_t readout_regs[256];
uint16_t func0_id;
uint16_t nvr_io_base;
uint16_t acpi_io_base;
double fast_off_period;
sff8038i_t *bm[2];
smbus_piix4_t *smbus;
apm_t *apm;
nvr_t *nvr;
ddma_t *ddma;
usb_t *usb;
acpi_t *acpi;
piix_io_trap_t io_traps[26];
port_92_t *port_92;
pc_timer_t fast_off_timer;
} piix_t;
#ifdef ENABLE_PIIX_LOG
int piix_do_log = ENABLE_PIIX_LOG;
static void
piix_log(const char *fmt, ...)
{
va_list ap;
if (piix_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define piix_log(fmt, ...)
#endif
static void
smsc_ide_irqs(piix_t *dev)
{
int irq_line = 3;
uint8_t irq_mode[2] = { IRQ_MODE_LEGACY, IRQ_MODE_LEGACY };
if (dev->regs[1][0x09] & 0x01)
irq_mode[0] = (dev->regs[0][0xe1] & 0x01) ? IRQ_MODE_PCI_IRQ_LINE : IRQ_MODE_PCI_IRQ_PIN;
if (dev->regs[1][0x09] & 0x04)
irq_mode[1] = (dev->regs[0][0xe1] & 0x01) ? IRQ_MODE_PCI_IRQ_LINE : IRQ_MODE_PCI_IRQ_PIN;
switch ((dev->regs[0][0xe1] >> 1) & 0x07) {
case 0x00:
irq_line = 3;
break;
case 0x01:
irq_line = 5;
break;
case 0x02:
irq_line = 7;
break;
case 0x03:
irq_line = 8;
break;
case 0x04:
irq_line = 11;
break;
case 0x05:
irq_line = 12;
break;
case 0x06:
irq_line = 14;
break;
case 0x07:
irq_line = 15;
break;
default:
break;
}
sff_set_irq_line(dev->bm[0], irq_line);
sff_set_irq_mode(dev->bm[0], irq_mode[0]);
sff_set_irq_line(dev->bm[1], irq_line);
sff_set_irq_mode(dev->bm[1], irq_mode[1]);
}
static void
piix_ide_handlers(piix_t *dev, int bus)
{
uint16_t main;
uint16_t side;
if (bus & 0x01) {
ide_pri_disable();
if (dev->type == 5) {
if (dev->regs[1][0x09] & 0x01) {
main = (dev->regs[1][0x11] << 8) | (dev->regs[1][0x10] & 0xf8);
side = ((dev->regs[1][0x15] << 8) | (dev->regs[1][0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
}
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x41] & 0x80))
ide_pri_enable();
}
if (bus & 0x02) {
ide_sec_disable();
if (dev->type == 5) {
if (dev->regs[1][0x09] & 0x04) {
main = (dev->regs[1][0x19] << 8) | (dev->regs[1][0x18] & 0xf8);
side = ((dev->regs[1][0x1d] << 8) | (dev->regs[1][0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
}
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x43] & 0x80))
ide_sec_enable();
}
}
static void
piix_ide_bm_handlers(piix_t *dev)
{
uint16_t base = (dev->regs[1][0x20] & 0xf0) | (dev->regs[1][0x21] << 8);
sff_bus_master_handler(dev->bm[0], (dev->regs[1][0x04] & 1), base);
sff_bus_master_handler(dev->bm[1], (dev->regs[1][0x04] & 1), base + 8);
}
static uint8_t
kbc_alias_reg_read(UNUSED(uint16_t addr), UNUSED(void *priv))
{
uint8_t ret = inb(0x61);
return ret;
}
static void
kbc_alias_reg_write(UNUSED(uint16_t addr), uint8_t val, UNUSED(void *priv))
{
outb(0x61, val);
}
static void
kbc_alias_update_io_mapping(piix_t *dev)
{
io_removehandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
io_removehandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
io_removehandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
if (dev->regs[0][0x4e] & 0x08) {
io_sethandler(0x0063, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
io_sethandler(0x0065, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
io_sethandler(0x0067, 1, kbc_alias_reg_read, NULL, NULL, kbc_alias_reg_write, NULL, NULL, dev);
}
}
static void
smbus_update_io_mapping(piix_t *dev)
{
smbus_piix4_remap(dev->smbus, ((uint16_t) (dev->regs[3][0x91] << 8)) | (dev->regs[3][0x90] & 0xf0), (dev->regs[3][PCI_REG_COMMAND] & PCI_COMMAND_IO) && (dev->regs[3][0xd2] & 0x01));
}
static void
nvr_update_io_mapping(piix_t *dev)
{
if (dev->nvr_io_base != 0x0000) {
piix_log("Removing NVR at %04X...\n", dev->nvr_io_base);
nvr_at_handler(0, dev->nvr_io_base, dev->nvr);
nvr_at_handler(0, dev->nvr_io_base + 0x0002, dev->nvr);
nvr_at_handler(0, dev->nvr_io_base + 0x0004, dev->nvr);
}
if (dev->type == 5)
dev->nvr_io_base = (dev->regs[0][0xd5] << 8) | (dev->regs[0][0xd4] & 0xf0);
else
dev->nvr_io_base = 0x70;
piix_log("New NVR I/O base: %04X\n", dev->nvr_io_base);
if (dev->regs[0][0xcb] & 0x01) {
piix_log("Adding low NVR at %04X...\n", dev->nvr_io_base);
if (dev->nvr_io_base != 0x0000) {
nvr_at_handler(1, dev->nvr_io_base, dev->nvr);
nvr_at_handler(1, dev->nvr_io_base + 0x0004, dev->nvr);
}
}
if (dev->regs[0][0xcb] & 0x04) {
piix_log("Adding high NVR at %04X...\n", dev->nvr_io_base + 0x0002);
if (dev->nvr_io_base != 0x0000)
nvr_at_handler(1, dev->nvr_io_base + 0x0002, dev->nvr);
}
}
static void
piix_trap_io(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
piix_io_trap_t *trap = (piix_io_trap_t *) priv;
if (*(trap->en_reg) & trap->en_mask) {
*(trap->sts_reg) |= trap->sts_mask;
acpi_raise_smi(trap->dev->acpi, 1);
}
}
static void
piix_trap_io_ide(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
const piix_io_trap_t *trap = (piix_io_trap_t *) priv;
/* IDE traps are per drive, not per channel. */
if (ide_drives[trap->dev_id]->selected)
piix_trap_io(size, addr, write, val, priv);
}
static void
piix_trap_update_devctl(piix_t *dev, uint8_t trap_id, uint8_t dev_id,
uint32_t devctl_mask, uint8_t enable,
uint16_t addr, uint16_t size)
{
piix_io_trap_t *trap = &dev->io_traps[trap_id];
enable = (dev->acpi->regs.devctl & devctl_mask) && enable;
/* Set up Device I/O traps dynamically. */
if (enable && !trap->trap) {
trap->dev = dev;
trap->trap = io_trap_add((dev_id <= 3) ? piix_trap_io_ide : piix_trap_io, trap);
trap->dev_id = dev_id;
trap->sts_reg = &dev->acpi->regs.devsts;
trap->sts_mask = 0x00010000 << dev_id;
trap->en_reg = &dev->acpi->regs.devctl;
trap->en_mask = devctl_mask;
}
#ifdef ENABLE_PIIX_LOG
if ((dev_id == 9) || (dev_id == 10) || (dev_id == 12) || (dev_id == 13))
piix_log("PIIX: Mapping trap device %d to %04X-%04X (enable %d)\n", dev_id, addr, addr + size - 1, enable);
#endif
/* Remap I/O trap. */
io_trap_remap(trap->trap, enable, addr, size);
}
static void
piix_trap_update(void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t trap_id = 0;
const uint8_t *fregs = dev->regs[3];
uint16_t temp;
piix_trap_update_devctl(dev, trap_id++, 0, 0x00000002, 1, 0x1f0, 8);
piix_trap_update_devctl(dev, trap_id++, 0, 0x00000002, 1, 0x3f6, 1);
piix_trap_update_devctl(dev, trap_id++, 1, 0x00000008, 1, 0x1f0, 8);
piix_trap_update_devctl(dev, trap_id++, 1, 0x00000008, 1, 0x3f6, 1);
piix_trap_update_devctl(dev, trap_id++, 2, 0x00000020, 1, 0x170, 8);
piix_trap_update_devctl(dev, trap_id++, 2, 0x00000020, 1, 0x376, 1);
piix_trap_update_devctl(dev, trap_id++, 3, 0x00000080, 1, 0x170, 8);
piix_trap_update_devctl(dev, trap_id++, 3, 0x00000080, 1, 0x376, 1);
piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x08, 0x220 + (0x20 * ((fregs[0x5c] >> 5) & 0x03)), 20);
piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x10, 0x200, 8);
piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x08, 0x388, 4);
switch (fregs[0x5d] & 0x03) {
case 0x00:
temp = 0x530;
break;
case 0x01:
temp = 0x604;
break;
case 0x02:
temp = 0xe80;
break;
default:
temp = 0xf40;
break;
}
piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x80, temp, 8);
piix_trap_update_devctl(dev, trap_id++, 4, 0x00000200, fregs[0x5c] & 0x01, 0x300 + (0x10 * ((fregs[0x5c] >> 1) & 0x03)), 4);
piix_trap_update_devctl(dev, trap_id++, 5, 0x00000800, fregs[0x51] & 0x10, 0x370 + (0x80 * !(fregs[0x63] & 0x10)), 6);
piix_trap_update_devctl(dev, trap_id++, 5, 0x00000800, fregs[0x51] & 0x10, 0x377 + (0x80 * !(fregs[0x63] & 0x10)), 1);
switch (fregs[0x67] & 0x07) {
case 0x00:
temp = 0x3f8;
break;
case 0x01:
temp = 0x2f8;
break;
case 0x02:
temp = 0x220;
break;
case 0x03:
temp = 0x228;
break;
case 0x04:
temp = 0x238;
break;
case 0x05:
temp = 0x2e8;
break;
case 0x06:
temp = 0x338;
break;
default:
temp = 0x3e8;
break;
}
piix_trap_update_devctl(dev, trap_id++, 6, 0x00002000, fregs[0x51] & 0x40, temp, 8);
switch (fregs[0x67] & 0x70) {
case 0x00:
temp = 0x3f8;
break;
case 0x10:
temp = 0x2f8;
break;
case 0x20:
temp = 0x220;
break;
case 0x30:
temp = 0x228;
break;
case 0x40:
temp = 0x238;
break;
case 0x50:
temp = 0x2e8;
break;
case 0x60:
temp = 0x338;
break;
default:
temp = 0x3e8;
break;
}
piix_trap_update_devctl(dev, trap_id++, 7, 0x00008000, fregs[0x52] & 0x01, temp, 8);
switch (fregs[0x63] & 0x06) {
case 0x00:
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x3bc, 4);
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x7bc, 3);
break;
case 0x02:
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x378, 8);
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x778, 3);
break;
case 0x04:
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x278, 8);
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0x678, 3);
break;
default:
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0);
piix_trap_update_devctl(dev, trap_id++, 8, 0x00020000, fregs[0x52] & 0x04, 0, 0);
break;
}
temp = fregs[0x62] & 0x0f;
piix_trap_update_devctl(dev, trap_id++, 9, 0x00080000, fregs[0x62] & 0x20, (fregs[0x60] | (fregs[0x61] << 8)) & ~temp, temp + 1);
temp = fregs[0x66] & 0x0f;
piix_trap_update_devctl(dev, trap_id++, 10, 0x00200000, fregs[0x66] & 0x20, (fregs[0x64] | (fregs[0x65] << 8)) & ~temp, temp + 1);
piix_trap_update_devctl(dev, trap_id++, 11, 0x00800000, fregs[0x5f] & 0x04, 0x3b0, 48);
piix_trap_update_devctl(dev, trap_id++, 11, 0x00800000, fregs[0x5f] & 0x10, 0x60, 1);
piix_trap_update_devctl(dev, trap_id++, 11, 0x00800000, fregs[0x5f] & 0x10, 0x64, 1);
/* [A0000:BFFFF] memory trap not implemented. */
temp = fregs[0x6a] & 0x0f;
piix_trap_update_devctl(dev, trap_id++, 12, 0x01000000, fregs[0x6a] & 0x10, (fregs[0x68] | (fregs[0x69] << 8)) & ~temp, temp + 1);
/* Programmable memory trap not implemented. */
temp = fregs[0x72] & 0x0f;
piix_trap_update_devctl(dev, trap_id++, 13, 0x02000000, fregs[0x72] & 0x10, (fregs[0x70] | (fregs[0x71] << 8)) & ~temp, temp + 1);
/* Programmable memory trap not implemented. */
}
static void
piix_write(int func, int addr, uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t *fregs;
uint16_t base;
/* Return on unsupported function. */
if (dev->max_func > 0) {
if (func > dev->max_func)
return;
} else {
if (func > 1)
return;
}
/* Ignore the new IDE BAR's on the Intel chips. */
if ((dev->type < 5) && (func == 1) && (addr >= 0x10) && (addr <= 0x1f))
return;
piix_log("PIIX function %i write: %02X to %02X\n", func, val, addr);
fregs = (uint8_t *) dev->regs[func];
if (func == 0)
switch (addr) {
case 0x04:
fregs[0x04] = (val & 0x08) | 0x07;
break;
case 0x05:
if (dev->type > 1)
fregs[0x05] = (val & 0x01);
break;
case 0x07:
if ((val & 0x40) && (dev->type > 1))
fregs[0x07] &= 0xbf;
if (val & 0x20)
fregs[0x07] &= 0xdf;
if (val & 0x10)
fregs[0x07] &= 0xef;
if (val & 0x08)
fregs[0x07] &= 0xf7;
if (val & 0x04)
fregs[0x07] &= 0xfb;
break;
case 0x4c:
fregs[0x4c] = val;
if (dev->type > 1)
dma_alias_remove();
else
dma_alias_remove_piix();
if (!(val & 0x80)) {
if (dev->type > 1)
dma_alias_set();
else
dma_alias_set_piix();
}
break;
case 0x4e:
fregs[0x4e] = val;
if (dev->type >= 4)
kbc_alias_update_io_mapping(dev);
break;
case 0x4f:
if (dev->type > 3)
fregs[0x4f] = val & 0x07;
else if (dev->type == 3)
fregs[0x4f] = val & 0x01;
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
piix_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
fregs[addr] = val & 0x8f;
if (val & 0x80)
pci_set_irq_routing(PCI_INTA + (addr & 0x03), PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA + (addr & 0x03), val & 0xf);
break;
case 0x64:
if (dev->type > 3)
fregs[0x64] = val;
break;
case 0x65:
if (dev->type > 4)
fregs[0x65] = val;
break;
case 0x66:
if (dev->type > 4)
fregs[0x66] = val & 0x81;
break;
case 0x69:
if (dev->type > 1)
fregs[0x69] = val & 0xfe;
else
fregs[0x69] = val & 0xfa;
break;
case 0x6a:
switch (dev->type) {
default:
case 1:
fregs[0x6a] = (fregs[0x6a] & 0xfb) | (val & 0x04);
fregs[0x0e] = (val & 0x04) ? 0x80 : 0x00;
piix_log("PIIX: Write %02X\n", val);
dev->max_func = 0 + !!(val & 0x04);
break;
case 3:
fregs[0x6a] = val & 0xd1;
piix_log("PIIX3: Write %02X\n", val);
dev->max_func = 1 + !!(val & 0x10);
break;
case 4:
fregs[0x6a] = val & 0x80;
break;
case 5:
/* This case is needed so it doesn't behave the PIIX way on the SMSC. */
break;
}
break;
case 0x6b:
if ((dev->type > 1) && (dev->type <= 4) && (val & 0x80))
fregs[0x6b] &= 0x7f;
return;
case 0x70:
case 0x71:
if ((dev->type > 1) && (addr == 0x71))
break;
if (dev->type < 4) {
piix_log("Set MIRQ routing: MIRQ%i -> %02X\n", addr & 0x01, val);
if (dev->type > 1)
fregs[addr] = val & 0xef;
else
fregs[addr] = val & 0xcf;
if (val & 0x80)
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ0 + (addr & 0x01), val & 0xf);
if (dev->type == 3) {
if (val & 0x20)
sff_set_irq_mode(dev->bm[1], IRQ_MODE_MIRQ_0);
else
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
}
piix_log("MIRQ%i is %s\n", addr & 0x01, (val & 0x20) ? "disabled" : "enabled");
}
break;
case 0x76:
case 0x77:
if (dev->type > 1)
fregs[addr] = val & 0x87;
else if (dev->type <= 4)
fregs[addr] = val & 0x8f;
break;
case 0x78:
case 0x79:
if (dev->type < 4)
fregs[addr] = val;
break;
case 0x80:
if (dev->type > 1)
fregs[addr] = val & 0x7f;
break;
case 0x81:
if (dev->type > 1)
fregs[addr] = val & 0x0f;
break;
case 0x82:
if (dev->type > 3)
fregs[addr] = val & 0x0f;
break;
case 0x90:
if (dev->type > 3)
fregs[addr] = val;
break;
case 0x91:
if (dev->type > 3)
fregs[addr] = val & 0xfc;
break;
case 0x92:
case 0x93:
case 0x94:
case 0x95:
if (dev->type > 3) {
if (addr & 0x01)
fregs[addr] = val & 0xff;
else
fregs[addr] = val & 0xc0;
base = fregs[addr | 0x01] << 8;
base |= fregs[addr & 0xfe];
for (uint8_t i = 0; i < 4; i++)
ddma_update_io_mapping(dev->ddma, (addr & 4) + i, fregs[addr & 0xfe] + (i << 4), fregs[addr | 0x01], (base != 0x0000));
}
break;
case 0xa0:
if (dev->type < 4) {
fregs[addr] = val & 0x1f;
apm_set_do_smi(dev->apm, !!(val & 0x01) && !!(fregs[0xa2] & 0x80));
switch ((val & 0x18) >> 3) {
case 0x00:
dev->fast_off_period = PCICLK * 32768.0 * 60000.0;
break;
case 0x01:
default:
dev->fast_off_period = 0.0;
break;
case 0x02:
dev->fast_off_period = PCICLK;
break;
case 0x03:
dev->fast_off_period = PCICLK * 32768.0;
break;
}
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
}
break;
case 0xa2:
if (dev->type < 4) {
fregs[addr] = val & 0xff;
apm_set_do_smi(dev->apm, !!(fregs[0xa0] & 0x01) && !!(val & 0x80));
}
break;
case 0xac:
case 0xae:
if (dev->type < 4)
fregs[addr] = val & 0xff;
break;
case 0xa3:
if (dev->type == 3)
fregs[addr] = val & 0x01;
break;
case 0xa4:
if (dev->type < 4) {
fregs[addr] = val & 0xfb;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffffff00) | fregs[addr];
}
break;
case 0xa5:
if (dev->type < 4) {
fregs[addr] = val & 0xff;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xffff00ff) | (fregs[addr] << 8);
}
break;
case 0xa6:
if (dev->type < 4) {
fregs[addr] = val & 0xff;
cpu_fast_off_flags = (cpu_fast_off_flags & 0xff00ffff) | (fregs[addr] << 16);
}
break;
case 0xa7:
if (dev->type == 3)
fregs[addr] = val & 0xef;
else if (dev->type < 3)
fregs[addr] = val;
if (dev->type < 4)
cpu_fast_off_flags = (cpu_fast_off_flags & 0x00ffffff) | (fregs[addr] << 24);
break;
case 0xa8:
if (dev->type < 3) {
fregs[addr] = val & 0xff;
cpu_fast_off_val = val;
cpu_fast_off_count = val + 1;
cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
}
break;
case 0xaa:
if (dev->type < 4)
fregs[addr] &= val;
break;
case 0xab:
if (dev->type == 3)
fregs[addr] &= (val & 0x01);
else if (dev->type < 3)
fregs[addr] = val;
break;
case 0xb0:
if (dev->type == 4)
fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73);
else if (dev->type == 5)
fregs[addr] = val & 0x7f;
if (dev->type >= 4)
alt_access = !!(val & 0x20);
break;
case 0xb1:
if (dev->type > 3)
fregs[addr] = val & 0xdf;
break;
case 0xb2:
if (dev->type > 3)
fregs[addr] = val;
break;
case 0xb3:
if (dev->type > 3)
fregs[addr] = val & 0xfb;
break;
case 0xcb:
if (dev->type > 3) {
fregs[addr] = val & 0x3d;
nvr_update_io_mapping(dev);
nvr_wp_set(!!(val & 0x08), 0, dev->nvr);
nvr_wp_set(!!(val & 0x10), 1, dev->nvr);
}
break;
case 0xd4:
if ((dev->type > 4) && !(fregs[addr] & 0x01)) {
fregs[addr] = val & 0xf1;
nvr_update_io_mapping(dev);
}
break;
case 0xd5:
if ((dev->type > 4) && !(fregs[0xd4] & 0x01)) {
fregs[addr] = val & 0xff;
nvr_update_io_mapping(dev);
}
break;
case 0xe0:
if (dev->type > 4)
fregs[addr] = val & 0xe7;
break;
case 0xe1:
case 0xe4:
case 0xe5:
case 0xe6:
case 0xe7:
case 0xe8:
case 0xe9:
case 0xea:
case 0xeb:
if (dev->type > 4) {
fregs[addr] = val;
if ((dev->type == 5) && (addr == 0xe1)) {
smsc_ide_irqs(dev);
port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x40));
}
}
break;
default:
break;
}
else if (func == 1)
switch (addr) { /* IDE */
case 0x04:
fregs[0x04] = (val & 5);
if (dev->type <= 3)
fregs[0x04] |= 0x02;
piix_ide_handlers(dev, 0x03);
piix_ide_bm_handlers(dev);
break;
case 0x07:
fregs[0x07] &= ~(val & 0x38);
break;
case 0x09:
if (dev->type == 5) {
fregs[0x09] = (fregs[0x09] & 0xfa) | (val & 0x05);
piix_ide_handlers(dev, 0x03);
smsc_ide_irqs(dev);
}
break;
case 0x0d:
fregs[0x0d] = val & 0xf0;
break;
case 0x10:
if (dev->type == 5) {
fregs[0x10] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x11:
if (dev->type == 5) {
fregs[0x11] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x14:
if (dev->type == 5) {
fregs[0x14] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x15:
if (dev->type == 5) {
fregs[0x15] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x18:
if (dev->type == 5) {
fregs[0x18] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x19:
if (dev->type == 5) {
fregs[0x19] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1c:
if (dev->type == 5) {
fregs[0x1c] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1d:
if (dev->type == 5) {
fregs[0x1d] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x20:
fregs[0x20] = (val & 0xf0) | 1;
piix_ide_bm_handlers(dev);
break;
case 0x21:
fregs[0x21] = val;
piix_ide_bm_handlers(dev);
break;
case 0x3c:
if (dev->type == 5)
fregs[0x3c] = val;
break;
case 0x3d:
if (dev->type == 5)
fregs[0x3d] = val;
break;
case 0x40:
case 0x42:
fregs[addr] = val;
break;
case 0x41:
case 0x43:
fregs[addr] = val & ((dev->type > 1) ? 0xf3 : 0xb3);
piix_ide_handlers(dev, 1 << !!(addr & 0x02));
break;
case 0x44:
if (dev->type > 1)
fregs[0x44] = val;
break;
case 0x45:
if (dev->type > 4)
fregs[0x45] = val;
break;
case 0x46:
if (dev->type > 4)
fregs[0x46] = val & 0x03;
break;
case 0x48:
if (dev->type > 3)
fregs[0x48] = val & 0x0f;
break;
case 0x4a:
case 0x4b:
if (dev->type > 3)
fregs[addr] = val & 0x33;
break;
case 0x5c:
case 0x5d:
if (dev->type > 4)
fregs[addr] = val;
break;
default:
break;
}
else if (func == 2)
switch (addr) { /* USB */
case 0x04:
if (dev->type > 4) {
fregs[0x04] = (val & 7);
ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM);
} else {
fregs[0x04] = (val & 5);
uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
}
break;
case 0x07:
if (dev->type > 4) {
if (val & 0x80)
fregs[0x07] &= 0x7f;
if (val & 0x40)
fregs[0x07] &= 0xbf;
}
if (val & 0x20)
fregs[0x07] &= 0xdf;
if (val & 0x10)
fregs[0x07] &= 0xef;
if (val & 0x08)
fregs[0x07] &= 0xf7;
break;
case 0x0c:
if (dev->type > 4)
fregs[0x0c] = val;
break;
case 0x0d:
if (dev->type < 5)
fregs[0x0d] = val & 0xf0;
break;
case 0x11:
if (dev->type > 4) {
fregs[addr] = val & 0xf0;
ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/);
}
break;
case 0x12:
case 0x13:
if (dev->type > 4) {
fregs[addr] = val;
ohci_update_mem_mapping(dev->usb, fregs[0x11], fregs[0x12], fregs[0x13], 1 /*fregs[PCI_REG_COMMAND] & PCI_COMMAND_MEM*/);
}
break;
case 0x20:
if (dev->type < 5) {
fregs[0x20] = (val & 0xe0) | 1;
uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
}
break;
case 0x21:
if (dev->type < 5) {
fregs[0x21] = val;
uhci_update_io_mapping(dev->usb, fregs[0x20] & ~0x1f, fregs[0x21], fregs[PCI_REG_COMMAND] & PCI_COMMAND_IO);
}
break;
case 0x3c:
fregs[0x3c] = val;
break;
case 0x3e:
case 0x3f:
case 0x40:
case 0x41:
case 0x43:
if (dev->type > 4)
fregs[addr] = val;
break;
case 0x42:
if (dev->type > 4)
fregs[addr] = val & 0x8f;
break;
case 0x44:
case 0x45:
if (dev->type > 4)
fregs[addr] = val & 0x01;
break;
case 0x6a:
if (dev->type <= 4)
fregs[0x6a] = val & 0x01;
break;
case 0xc0:
if (dev->type <= 4)
fregs[0xc0] = (fregs[0xc0] & 0x40) | (val & 0xbf);
break;
case 0xc1:
if (dev->type <= 4)
fregs[0xc1] = (fregs[0xc0] & ~(val & 0x8f)) | (val & 0x20);
break;
case 0xff:
if (dev->type == 4) {
fregs[addr] = val & 0x10;
nvr_read_addr_set(!!(val & 0x10), dev->nvr);
}
break;
default:
break;
}
else if (func == 3)
switch (addr) { /* Power Management */
case 0x04:
fregs[0x04] = (val & 0x01);
smbus_update_io_mapping(dev);
apm_set_do_smi(dev->acpi->apm, !!(fregs[0x5b] & 0x02) && !!(val & 0x01));
break;
case 0x07:
if (val & 0x08)
fregs[0x07] &= 0xf7;
break;
#if 0
case 0x3c:
fregs[0x3c] = val;
break;
#endif
case 0x40:
fregs[0x40] = (val & 0xc0) | 1;
dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0);
acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01));
break;
case 0x41:
fregs[0x41] = val;
dev->acpi_io_base = (dev->regs[3][0x41] << 8) | (dev->regs[3][0x40] & 0xc0);
acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01));
break;
case 0x44:
case 0x45:
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4c:
case 0x4d:
case 0x4e:
case 0x54:
case 0x55:
case 0x56:
case 0x57:
case 0x59:
case 0x5a:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f:
case 0x60:
case 0x61:
case 0x62:
case 0x64:
case 0x65:
case 0x67:
case 0x68:
case 0x69:
case 0x6c:
case 0x6e:
case 0x6f:
case 0x70:
case 0x71:
case 0x74:
case 0x77:
case 0x78:
case 0x79:
case 0x7c:
case 0x7d:
case 0xd3:
case 0xd4:
case 0xd5:
fregs[addr] = val;
if ((addr == 0x5c) || (addr == 0x60) || (addr == 0x61) || (addr == 0x62) || (addr == 0x64) || (addr == 0x65) || (addr == 0x68) || (addr == 0x69) || (addr == 0x70) || (addr == 0x71))
piix_trap_update(dev);
break;
case 0x4a:
fregs[addr] = val & 0x73;
break;
case 0x4b:
fregs[addr] = val & 0x01;
break;
case 0x4f:
case 0x80:
case 0xd2:
fregs[addr] = val & 0x0f;
if (addr == 0x80)
acpi_update_io_mapping(dev->acpi, dev->acpi_io_base, (dev->regs[3][0x80] & 0x01));
else if (addr == 0xd2)
smbus_update_io_mapping(dev);
break;
case 0x50:
fregs[addr] = val & 0x3f;
break;
case 0x51:
fregs[addr] = val & 0x58;
piix_trap_update(dev);
break;
case 0x52:
fregs[addr] = val & 0x7f;
piix_trap_update(dev);
break;
case 0x58:
fregs[addr] = val & 0x77;
break;
case 0x5b:
fregs[addr] = val & 0x03;
apm_set_do_smi(dev->acpi->apm, !!(val & 0x02) && !!(fregs[0x04] & 0x01));
break;
case 0x63:
fregs[addr] = val & 0xf7;
piix_trap_update(dev);
break;
case 0x66:
fregs[addr] = val & 0xef;
piix_trap_update(dev);
break;
case 0x6a:
case 0x72:
case 0x7a:
case 0x7e:
fregs[addr] = val & 0x1f;
if ((addr == 0x6a) || (addr == 0x72))
piix_trap_update(dev);
break;
case 0x6d:
case 0x75:
fregs[addr] = val & 0x80;
break;
case 0x90:
fregs[0x90] = (val & 0xf0) | 1;
smbus_update_io_mapping(dev);
break;
case 0x91:
fregs[0x91] = val;
smbus_update_io_mapping(dev);
break;
default:
break;
}
}
static uint8_t
piix_read(int func, int addr, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t ret = 0xff;
const uint8_t *fregs;
if ((dev->type == 3) && (func == 2) && (dev->max_func == 1) && (addr >= 0x40))
ret = 0x00;
/* Return on unsupported function. */
if ((func <= dev->max_func) || ((func == 1) && (dev->max_func == 0))) {
fregs = (uint8_t *) dev->regs[func];
ret = fregs[addr];
piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr);
}
return ret;
}
static void
board_write(uint16_t port, uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
if (port == 0x00e0)
dev->cur_readout_reg = val;
else if (port == 0x00e1)
dev->readout_regs[dev->cur_readout_reg] = val;
}
static uint8_t
board_read(uint16_t port, void *priv)
{
const piix_t *dev = (piix_t *) priv;
uint8_t ret = 0x64;
if (port == 0x00e0)
ret = dev->cur_readout_reg;
else if (port == 0x00e1)
ret = dev->readout_regs[dev->cur_readout_reg];
return ret;
}
static void
piix_reset_hard(piix_t *dev)
{
uint8_t *fregs;
sff_bus_master_reset(dev->bm[0]);
sff_bus_master_reset(dev->bm[1]);
if (dev->type >= 4) {
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_irq_pin(dev->bm[0], PCI_INTA);
sff_set_irq_line(dev->bm[0], 14);
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
sff_set_slot(dev->bm[1], dev->pci_slot);
sff_set_irq_pin(dev->bm[1], PCI_INTA);
sff_set_irq_line(dev->bm[1], 14);
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
}
#ifdef ENABLE_PIIX_LOG
piix_log("piix_reset_hard()\n");
#endif
ide_pri_disable();
ide_sec_disable();
if (dev->type > 3) {
nvr_at_handler(0, 0x0072, dev->nvr);
nvr_wp_set(0, 0, dev->nvr);
nvr_wp_set(0, 1, dev->nvr);
nvr_at_handler(1, 0x0074, dev->nvr);
dev->nvr_io_base = 0x0070;
}
/* Clear all 4 functions' arrays and set their vendor and device ID's. */
for (uint8_t i = 0; i < 4; i++) {
memset(dev->regs[i], 0, 256);
if (dev->type == 5) {
dev->regs[i][0x00] = 0x55;
dev->regs[i][0x01] = 0x10; /* SMSC/EFAR */
if (i == 1) { /* IDE controller is 9130, breaking convention */
dev->regs[i][0x02] = 0x30;
dev->regs[i][0x03] = 0x91;
} else {
dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift);
dev->regs[i][0x03] = (dev->func0_id >> 8);
}
} else {
dev->regs[i][0x00] = 0x86;
dev->regs[i][0x01] = 0x80; /* Intel */
dev->regs[i][0x02] = (dev->func0_id & 0xff) + (i << dev->func_shift);
dev->regs[i][0x03] = (dev->func0_id >> 8);
}
}
/* Function 0: PCI to ISA Bridge */
fregs = (uint8_t *) dev->regs[0];
piix_log("PIIX Function 0: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
fregs[0x04] = 0x07;
fregs[0x06] = 0x80;
fregs[0x07] = 0x02;
if (dev->type == 4)
fregs[0x08] = (dev->rev & 0x08) ? 0x02 : (dev->rev & 0x07);
else
fregs[0x08] = dev->rev;
fregs[0x09] = 0x00;
fregs[0x0a] = 0x01;
fregs[0x0b] = 0x06;
fregs[0x0e] = ((dev->type > 1) || (dev->rev != 2)) ? 0x80 : 0x00;
fregs[0x4c] = 0x4d;
fregs[0x4e] = 0x03;
fregs[0x60] = fregs[0x61] = fregs[0x62] = fregs[0x63] = 0x80;
fregs[0x64] = (dev->type > 3) ? 0x10 : 0x00;
fregs[0x69] = 0x02;
if ((dev->type == 1) && (dev->rev != 2))
fregs[0x6a] = 0x04;
else if (dev->type == 3)
fregs[0x6a] = 0x10;
fregs[0x70] = (dev->type < 4) ? 0x80 : 0x00;
fregs[0x71] = (dev->type < 3) ? 0x80 : 0x00;
if (dev->type <= 4) {
fregs[0x76] = fregs[0x77] = (dev->type > 1) ? 0x04 : 0x0c;
}
fregs[0x78] = (dev->type < 4) ? 0x02 : 0x00;
fregs[0xa0] = (dev->type < 4) ? 0x08 : 0x00;
fregs[0xa8] = (dev->type < 4) ? 0x0f : 0x00;
if (dev->type > 3)
fregs[0xb0] = is_pentium ? 0x00 : 0x04;
fregs[0xcb] = (dev->type > 3) ? 0x21 : 0x00;
if (dev->type > 4) {
fregs[0xd4] = 0x70;
fregs[0xe1] = 0x40;
fregs[0xe6] = 0x12;
fregs[0xe8] = 0x02;
fregs[0xea] = 0x12;
}
dev->max_func = 0;
/* Function 1: IDE */
fregs = (uint8_t *) dev->regs[1];
piix_log("PIIX Function 1: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
if (dev->type < 4)
fregs[0x04] = 0x02;
fregs[0x06] = 0x80;
fregs[0x07] = 0x02;
if (dev->type == 4)
fregs[0x08] = dev->rev & 0x07;
else
fregs[0x08] = dev->rev;
if (dev->type == 5)
fregs[0x09] = 0x8a;
else
fregs[0x09] = 0x80;
fregs[0x0a] = 0x01;
fregs[0x0b] = 0x01;
if (dev->type == 5) {
fregs[0x10] = 0xf1;
fregs[0x11] = 0x01;
fregs[0x14] = 0xf5;
fregs[0x15] = 0x03;
fregs[0x18] = 0x71;
fregs[0x19] = 0x01;
fregs[0x1c] = 0x75;
fregs[0x1d] = 0x03;
}
fregs[0x20] = 0x01;
if (dev->type == 5) {
fregs[0x3c] = 0x0e;
fregs[0x3d] = 0x01;
fregs[0x45] = 0x55;
fregs[0x46] = 0x01;
}
if ((dev->type == 1) && (dev->rev == 2))
dev->max_func = 0; /* It starts with IDE disabled, then enables it. */
else
dev->max_func = 1;
/* Function 2: USB */
if (dev->type > 1) {
fregs = (uint8_t *) dev->regs[2];
piix_log("PIIX Function 2: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
fregs[0x06] = 0x80;
fregs[0x07] = 0x02;
if (dev->type == 4)
fregs[0x08] = dev->rev & 0x07;
else if (dev->type < 4)
fregs[0x08] = 0x01;
else
fregs[0x08] = 0x02;
if (dev->type > 4)
fregs[0x09] = 0x10; /* SMSC has OHCI rather than UHCI */
fregs[0x0a] = 0x03;
fregs[0x0b] = 0x0c;
if (dev->type < 5)
fregs[0x20] = 0x01;
fregs[0x3d] = 0x04;
if (dev->type > 4)
fregs[0x60] = (dev->type > 3) ? 0x10 : 0x00;
if (dev->type < 5) {
fregs[0x6a] = (dev->type == 3) ? 0x01 : 0x00;
fregs[0xc1] = 0x20;
fregs[0xff] = (dev->type > 3) ? 0x10 : 0x00;
}
dev->max_func = 2; /* It starts with USB disabled, then enables it. */
}
/* Function 3: Power Management */
if (dev->type > 3) {
fregs = (uint8_t *) dev->regs[3];
piix_log("PIIX Function 3: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
fregs[0x06] = 0x80;
fregs[0x07] = 0x02;
if (dev->type > 4)
fregs[0x08] = 0x02;
else
fregs[0x08] = (dev->rev & 0x08) ? 0x02 : 0x01 /*(dev->rev & 0x07)*/;
fregs[0x0a] = 0x80;
fregs[0x0b] = 0x06;
/* NOTE: The Specification Update says this should default to 0x00 and be read-only. */
#ifdef WRONG_SPEC
if (dev->type == 4)
fregs[0x3d] = 0x01;
#endif
fregs[0x40] = 0x01;
fregs[0x90] = 0x01;
dev->max_func = 3;
}
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
if (dev->type < 4)
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
if (dev->type < 3)
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
if (dev->type >= 4)
acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f);
}
static void
piix_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
{
piix_t *dev = (piix_t *) priv;
if (dev->apm->do_smi) {
if (dev->type < 4)
dev->regs[0][0xaa] |= 0x80;
}
}
static void
piix_fast_off_count(void *priv)
{
piix_t *dev = (piix_t *) priv;
smi_raise();
dev->regs[0][0xaa] |= 0x20;
}
static void
piix_reset(void *priv)
{
const piix_t *dev = (piix_t *) priv;
if (dev->type > 3) {
piix_write(3, 0x04, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
} else {
piix_write(0, 0xa0, 0x08, priv);
piix_write(0, 0xa2, 0x00, priv);
piix_write(0, 0xa4, 0x00, priv);
piix_write(0, 0xa5, 0x00, priv);
piix_write(0, 0xa6, 0x00, priv);
piix_write(0, 0xa7, 0x00, priv);
piix_write(0, 0xa8, 0x0f, priv);
}
/* Disable the PIC mouse latch. */
piix_write(0, 0x4e, 0x03, priv);
if (dev->type == 5)
piix_write(0, 0xe1, 0x40, priv);
piix_write(1, 0x04, 0x00, priv);
if (dev->type == 5) {
piix_write(1, 0x09, 0x8a, priv);
piix_write(1, 0x10, 0xf1, priv);
piix_write(1, 0x11, 0x01, priv);
piix_write(1, 0x14, 0xf5, priv);
piix_write(1, 0x15, 0x03, priv);
piix_write(1, 0x18, 0x71, priv);
piix_write(1, 0x19, 0x01, priv);
piix_write(1, 0x1c, 0x75, priv);
piix_write(1, 0x1d, 0x03, priv);
} else
piix_write(1, 0x09, 0x80, priv);
piix_write(1, 0x20, 0x01, priv);
piix_write(1, 0x21, 0x00, priv);
piix_write(1, 0x41, 0x00, priv);
piix_write(1, 0x43, 0x00, priv);
ide_pri_disable();
ide_sec_disable();
if (dev->type >= 3) {
piix_write(2, 0x04, 0x00, priv);
if (dev->type == 5) {
piix_write(2, 0x10, 0x00, priv);
piix_write(2, 0x11, 0x00, priv);
piix_write(2, 0x12, 0x00, priv);
piix_write(2, 0x13, 0x00, priv);
} else {
piix_write(2, 0x20, 0x01, priv);
piix_write(2, 0x21, 0x00, priv);
piix_write(2, 0x22, 0x00, priv);
piix_write(2, 0x23, 0x00, priv);
}
}
if (dev->type >= 4) {
piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv);
piix_write(3, 0x40, 0x01, priv);
piix_write(3, 0x41, 0x00, priv);
piix_write(3, 0x5b, 0x00, priv);
piix_write(3, 0x80, 0x00, priv);
piix_write(3, 0x90, 0x01, priv);
piix_write(3, 0x91, 0x00, priv);
piix_write(3, 0xd2, 0x00, priv);
}
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
if (dev->no_mirq0 || (dev->type >= 4))
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
else
sff_set_irq_mode(dev->bm[1], IRQ_MODE_MIRQ_0);
}
static void
piix_close(void *priv)
{
piix_t *dev = (piix_t *) priv;
for (int i = 0; i < (sizeof(dev->io_traps) / sizeof(dev->io_traps[0])); i++)
io_trap_remove(dev->io_traps[i].trap);
free(dev);
}
static void
piix_speed_changed(void *priv)
{
piix_t *dev = (piix_t *) priv;
if (!dev)
return;
int to = timer_is_on(&dev->fast_off_timer);
timer_stop(&dev->fast_off_timer);
if (to)
timer_on_auto(&dev->fast_off_timer, ((double) cpu_fast_off_val + 1) * dev->fast_off_period);
}
static void *
piix_init(const device_t *info)
{
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));
dev->type = info->local & 0x0f;
/* If (dev->type == 4) and (dev->rev & 0x08), then this is PIIX4E. */
dev->rev = (info->local >> 4) & 0x0f;
dev->func_shift = (info->local >> 8) & 0x0f;
dev->no_mirq0 = (info->local >> 12) & 0x0f;
dev->func0_id = info->local >> 16;
pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev, &dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
if ((dev->type == 1) && (dev->rev == 2)) {
/* PIIX rev. 02 has faulty bus mastering on real hardware,
so set our devices IDE devices to force ATA-3 (no DMA). */
ide_board_set_force_ata3(0, 1);
ide_board_set_force_ata3(1, 1);
}
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
if (dev->no_mirq0 || (dev->type >= 4))
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
else
sff_set_irq_mode(dev->bm[1], IRQ_MODE_MIRQ_0);
if (dev->type >= 3)
dev->usb = device_add(&usb_device);
if (dev->type > 3) {
dev->nvr = device_add(&piix4_nvr_device);
dev->smbus = device_add(&piix4_smbus_device);
dev->acpi = device_add(&acpi_intel_device);
acpi_set_slot(dev->acpi, dev->pci_slot);
acpi_set_nvr(dev->acpi, dev->nvr);
/*
TriGem Richmond:
- Bit 5: Manufacturing jumper, must be set;
- Bit 4: CMOS clear jumper, must be clear;
- Bit 0: Password switch, must be clear.
*/
if (!strcmp(machine_get_internal_name(), "richmond"))
acpi_set_gpireg2_default(dev->acpi, 0xee);
else
acpi_set_gpireg2_default(dev->acpi, (dev->type > 4) ? 0xf1 : 0xdd);
acpi_set_trap_update(dev->acpi, piix_trap_update, dev);
dev->ddma = device_add(&ddma_device);
} else
timer_add(&dev->fast_off_timer, piix_fast_off_count, dev, 0);
piix_reset_hard(dev);
piix_log("Maximum function: %i\n", dev->max_func);
cpu_fast_off_flags = 0x00000000;
if (dev->type < 4) {
cpu_fast_off_val = dev->regs[0][0xa8];
cpu_fast_off_count = cpu_fast_off_val + 1;
cpu_register_fast_off_handler(&dev->fast_off_timer);
} else
cpu_fast_off_val = cpu_fast_off_count = 0;
/* On PIIX4, PIIX4E, and SMSC, APM is added by the ACPI device. */
if (dev->type < 4) {
dev->apm = device_add(&apm_pci_device);
/* APM intercept handler to update PIIX/PIIX3 and PIIX4/4E/SMSC ACPI SMI status on APM SMI. */
io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, piix_apm_out, NULL, NULL, dev);
}
dev->port_92 = device_add(&port_92_pci_device);
if (cpu_busspeed > 50000000)
cpu_set_isa_pci_div(4);
else
cpu_set_isa_pci_div(3);
dma_alias_set();
if (dev->type < 4)
pci_enable_mirq(0);
if (dev->type < 3)
pci_enable_mirq(1);
dev->readout_regs[0] = 0xff;
dev->readout_regs[1] = 0x40;
dev->readout_regs[2] = 0xff;
/* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined):
Bit 6: 1 = can boot, 0 = no;
Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5);
Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????):
Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz;
0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz;
1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz;
1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */
if (cpu_busspeed <= 40000000)
dev->readout_regs[1] |= 0x30;
else if ((cpu_busspeed > 40000000) && (cpu_busspeed <= 50000000))
dev->readout_regs[1] |= 0x00;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
dev->readout_regs[1] |= 0x20;
else if (cpu_busspeed > 60000000)
dev->readout_regs[1] |= 0x10;
if (cpu_dmulti <= 1.5)
dev->readout_regs[1] |= 0x82;
else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
dev->readout_regs[1] |= 0x02;
else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
dev->readout_regs[1] |= 0x00;
else if (cpu_dmulti > 2.5)
dev->readout_regs[1] |= 0x80;
io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
#if 0
device_add(&i8254_sec_device);
#endif
return dev;
}
const device_t piix_device = {
.name = "Intel 82371FB (PIIX)",
.internal_name = "piix",
.flags = DEVICE_PCI,
.local = 0x122e0101,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix_no_mirq_device = {
.name = "Intel 82371FB (PIIX) (No MIRQ)",
.internal_name = "piix_no_mirq",
.flags = DEVICE_PCI,
.local = 0x122e1101,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix_rev02_device = {
.name = "Intel 82371FB (PIIX) (Faulty BusMastering!!)",
.internal_name = "piix_rev02",
.flags = DEVICE_PCI,
.local = 0x122e0121,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix3_device = {
.name = "Intel 82371SB (PIIX3)",
.internal_name = "piix3",
.flags = DEVICE_PCI,
.local = 0x70000403,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix3_ioapic_device = {
.name = "Intel 82371SB (PIIX3) (Boards with I/O APIC)",
.internal_name = "piix3_ioapic",
.flags = DEVICE_PCI,
.local = 0x70001403,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix4_device = {
.name = "Intel 82371AB/EB (PIIX4/PIIX4E)",
.internal_name = "piix4",
.flags = DEVICE_PCI,
.local = 0x71100004,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t piix4e_device = {
.name = "Intel 82371EB (PIIX4E)",
.internal_name = "piix4e",
.flags = DEVICE_PCI,
.local = 0x71100094,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
const device_t slc90e66_device = {
.name = "SMSC SLC90E66 (Victory66)",
.internal_name = "slc90e66",
.flags = DEVICE_PCI,
.local = 0x94600005,
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_piix.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 19,285 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C546/82C547(Python) & 82C596/82C597(Cobra) chipsets.
* Authors: plant/nerd73,
* Miran Grca, <mgrca8@gmail.com>
* Tiseno100
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct opti5x7_t {
uint8_t idx;
uint8_t is_pci;
uint8_t regs[16];
} opti5x7_t;
#ifdef ENABLE_OPTI5X7_LOG
int opti5x7_do_log = ENABLE_OPTI5X7_LOG;
static void
opti5x7_log(const char *fmt, ...)
{
va_list ap;
if (opti5x7_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti5x7_log(fmt, ...)
#endif
static void
opti5x7_shadow_map(int cur_reg, opti5x7_t *dev)
{
/*
Register 4h: Cxxxx Segment
Register 5h: Dxxxx Segment
Bits 7-6: xC000-xFFFF
Bits 5-4: x8000-xBFFF
Bits 3-2: x4000-x7FFF
Bits 0-1: x0000-x3FFF
x-y
0 0 Read/Write AT bus
1 0 Read from AT - Write to DRAM
1 1 Read from DRAM - Write to DRAM
0 1 Read from DRAM (write protected)
*/
if (cur_reg == 0x06) {
if (dev->is_pci) {
mem_set_mem_state_cpu_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_cpu_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
} else {
mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
} else {
for (uint8_t i = 0; i < 4; i++) {
if (dev->is_pci)
mem_set_mem_state_cpu_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
else
mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
}
}
flushmmucache_nopc();
}
static void
opti5x7_write(uint16_t addr, uint8_t val, void *priv)
{
opti5x7_t *dev = (opti5x7_t *) priv;
switch (addr) {
case 0x22:
dev->idx = val;
break;
case 0x24:
switch (dev->idx) {
case 0x00: /* DRAM Configuration Register #1 */
dev->regs[dev->idx] = val & 0x7f;
break;
case 0x01: /* DRAM Control Register #1 */
dev->regs[dev->idx] = val;
break;
case 0x02: /* Cache Control Register #1 */
dev->regs[dev->idx] = val;
cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c);
cpu_update_waitstates();
break;
case 0x03: /* Cache Control Register #2 */
dev->regs[dev->idx] = val;
break;
case 0x04: /* Shadow RAM Control Register #1 */
case 0x05: /* Shadow RAM Control Register #2 */
case 0x06: /* Shadow RAM Control Register #3 */
dev->regs[dev->idx] = val;
opti5x7_shadow_map(dev->idx, dev);
break;
case 0x07: /* Tag Test Register */
case 0x08: /* CPU Cache Control Register #1 */
case 0x09: /* System Memory Function Register #1 */
case 0x0a: /* System Memory Address Decode Register #1 */
case 0x0b: /* System Memory Address Decode Register #2 */
dev->regs[dev->idx] = val;
break;
case 0x0c: /* Extended DMA Register */
dev->regs[dev->idx] = val & 0xcf;
break;
case 0x0d: /* ROMCS# Register */
case 0x0e: /* Local Master Preemption Register */
case 0x0f: /* Deturbo Control Register #1 */
case 0x10: /* Cache Write-Hit Control Register */
case 0x11: /* Master Cycle Control Register */
dev->regs[dev->idx] = val;
break;
default:
break;
}
opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]);
break;
default:
break;
}
}
static uint8_t
opti5x7_read(uint16_t addr, void *priv)
{
const opti5x7_t *dev = (opti5x7_t *) priv;
return (addr == 0x24) ? dev->regs[dev->idx] : 0xff;
}
static void
opti5x7_close(void *priv)
{
opti5x7_t *dev = (opti5x7_t *) priv;
free(dev);
}
static void *
opti5x7_init(const device_t *info)
{
opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t));
memset(dev, 0, sizeof(opti5x7_t));
dev->is_pci = info->local;
io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
device_add(&port_92_device);
return dev;
}
const device_t opti5x7_device = {
.name = "OPTi 82C5x6/82C5x7",
.internal_name = "opti5x7",
.flags = 0,
.local = 0,
.init = opti5x7_init,
.close = opti5x7_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti5x7_pci_device = {
.name = "OPTi 82C5x6/82C5x7 (PCI)",
.internal_name = "opti5x7_pci",
.flags = 0,
.local = 1,
.init = opti5x7_init,
.close = opti5x7_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/opti5x7.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,129 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5571/5572 Pentium PCI/ISA Chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#ifdef ENABLE_SIS_5571_LOG
int sis_5571_do_log = ENABLE_SIS_5571_LOG;
static void
sis_5571_log(const char *fmt, ...)
{
va_list ap;
if (sis_5571_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5571_log(fmt, ...)
#endif
typedef struct sis_5571_t {
uint8_t nb_slot;
uint8_t sb_slot;
void *h2p;
void *p2i;
void *ide;
void *usb;
sis_55xx_common_t *sis;
} sis_5571_t;
static void
sis_5571_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
sis_5571_log("SiS 5571: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
if (func == 0x00)
sis_5571_host_to_pci_write(addr, val, dev->h2p);
}
static uint8_t
sis_5571_read(int func, int addr, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = sis_5571_host_to_pci_read(addr, dev->h2p);
sis_5571_log("SiS 5571: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5572_write(int func, int addr, uint8_t val, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
sis_5571_log("SiS 5572: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (func) {
case 0x00:
sis_5513_pci_to_isa_write(addr, val, dev->p2i);
break;
case 0x01:
sis_5513_ide_write(addr, val, dev->ide);
break;
case 0x02:
sis_5572_usb_write(addr, val, dev->usb);
break;
}
}
static uint8_t
sis_5572_read(int func, int addr, void *priv)
{
const sis_5571_t *dev = (sis_5571_t *) priv;
uint8_t ret = 0xff;
switch (func) {
case 0x00:
ret = sis_5513_pci_to_isa_read(addr, dev->p2i);
break;
case 0x01:
ret = sis_5513_ide_read(addr, dev->ide);
break;
case 0x02:
ret = sis_5572_usb_read(addr, dev->usb);
break;
}
sis_5571_log("SiS 5572: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5571_close(void *priv)
{
sis_5571_t *dev = (sis_5571_t *) priv;
free(dev);
}
static void *
sis_5571_init(UNUSED(const device_t *info))
{
sis_5571_t *dev = (sis_5571_t *) calloc(1, sizeof(sis_5571_t));
/* Device 0: SiS 5571 */
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_5571_read, sis_5571_write, dev, &dev->nb_slot);
/* Device 1: SiS 5572 */
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_5572_read, sis_5572_write, dev, &dev->sb_slot);
dev->sis = device_add(&sis_55xx_common_device);
dev->h2p = device_add_linked(&sis_5571_h2p_device, dev->sis);
dev->p2i = device_add_linked(&sis_5572_p2i_device, dev->sis);
dev->ide = device_add_linked(&sis_5572_ide_device, dev->sis);
dev->usb = device_add_linked(&sis_5572_usb_device, dev->sis);
return dev;
}
const device_t sis_5571_device = {
.name = "SiS 5571",
.internal_name = "sis_5571",
.flags = DEVICE_PCI,
.local = 0,
.init = sis_5571_init,
.close = sis_5571_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5571.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,465 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1621/2 CPU-to-PCI Bridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1621_t {
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pad1;
uint8_t pci_conf[256];
smram_t *smram[2];
} ali1621_t;
#ifdef ENABLE_ALI1621_LOG
int ali1621_do_log = ENABLE_ALI1621_LOG;
static void
ali1621_log(const char *fmt, ...)
{
va_list ap;
if (ali1621_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1621_log(fmt, ...)
#endif
/* Table translated to a more sensible format:
Read cycles:
SMREN SMM Mode Code Data
0 X X PCI PCI
1 0 Close PCI PCI
1 0 Lock PCI PCI
1 0 Protect PCI PCI
1 0 Open DRAM DRAM
1 1 Open DRAM DRAM
1 1 Protect DRAM DRAM
1 1 Close DRAM PCI
1 1 Lock DRAM PCI
Write cycles:
SMWEN SMM Mode Data
0 X X PCI
1 0 Close PCI
1 0 Lock PCI
1 0 Protect PCI
1 0 Open DRAM
1 1 Open DRAM
1 1 Protect DRAM
1 1 Close PCI
1 1 Lock PCI
Explanation of the modes based above:
If SM*EN = 0, SMRAM is entirely disabled, otherwise:
If mode is Close or Lock, then SMRAM always goes to PCI outside SMM,
and data to PCI, code to DRAM in SMM;
If mode is Protect, then SMRAM always goes to PCI outside SMM and
DRAM in SMM;
If mode is Open, then SMRAM always goes to DRAM.
Read and write are enabled separately.
*/
static void
ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
{
uint16_t access_smm = 0x0000;
uint16_t access_normal = 0x0000;
smram_disable_all();
if (val & 0xc0) {
/* SMRAM 0: A0000-BFFFF */
if (val & 0x80) {
access_smm = ACCESS_SMRAM_X;
switch (val & 0x30) {
case 0x10: /* Open. */
access_normal = ACCESS_SMRAM_RX;
fallthrough;
case 0x30: /* Protect. */
access_smm |= ACCESS_SMRAM_R;
break;
default:
break;
}
}
if (val & 0x40)
switch (val & 0x30) {
case 0x10: /* Open. */
access_normal |= ACCESS_SMRAM_W;
fallthrough;
case 0x30: /* Protect. */
access_smm |= ACCESS_SMRAM_W;
break;
default:
break;
}
smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30));
mem_set_access(ACCESS_NORMAL, 3, 0xa0000, 0x20000, access_normal);
mem_set_access(ACCESS_SMM, 3, 0xa0000, 0x20000, access_smm);
}
if (val & 0x08)
smram_enable(dev->smram[1], 0x38000, 0xa8000, 0x08000, 0, 1);
flushmmucache_nopc();
}
static void
ali1621_shadow_recalc(UNUSED(int cur_reg), ali1621_t *dev)
{
int r_bit;
int w_bit;
int reg;
uint32_t base;
uint32_t flags = 0;
shadowbios = shadowbios_write = 0;
/* C0000-EFFFF */
for (uint8_t i = 0; i < 12; i++) {
base = 0x000c0000 + (i << 14);
r_bit = (i << 1) + 4;
reg = 0x84;
if (r_bit > 23) {
r_bit &= 7;
reg += 3;
} else if (r_bit > 15) {
r_bit &= 7;
reg += 2;
} else if (r_bit > 7) {
r_bit &= 7;
reg++;
}
w_bit = r_bit + 1;
flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[reg] & (1 << r_bit))
shadowbios |= 1;
if (dev->pci_conf[reg] & (1 << r_bit))
shadowbios_write |= 1;
}
ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
/* F0000-FFFFF */
base = 0x000f0000;
r_bit = 4;
w_bit = 5;
reg = 0x87;
flags = (dev->pci_conf[reg] & (1 << r_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[reg] & (1 << w_bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (dev->pci_conf[reg] & (1 << r_bit))
shadowbios |= 1;
if (dev->pci_conf[reg] & (1 << r_bit))
shadowbios_write |= 1;
ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x0000ffff,
(dev->pci_conf[reg] & (1 << r_bit)) ? 'I' : 'E', (dev->pci_conf[reg] & (1 << w_bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00010000, flags);
flushmmucache_nopc();
}
static void
ali1621_mask_bar(ali1621_t *dev)
{
uint32_t bar;
uint32_t mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
default:
case 0x00:
mask = 0x00000000;
break;
case 0x01:
mask = 0xfff00000;
break;
case 0x02:
mask = 0xffe00000;
break;
case 0x03:
mask = 0xffc00000;
break;
case 0x04:
mask = 0xff800000;
break;
case 0x06:
mask = 0xff000000;
break;
case 0x07:
mask = 0xfe000000;
break;
case 0x08:
mask = 0xfc000000;
break;
case 0x09:
mask = 0xf8000000;
break;
case 0x0a:
mask = 0xf0000000;
break;
}
bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask;
dev->pci_conf[0x12] = (bar >> 16) & 0xff;
dev->pci_conf[0x13] = (bar >> 24) & 0xff;
}
static void
ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf0);
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x12:
dev->pci_conf[0x12] = (val & 0xc0);
ali1621_mask_bar(dev);
break;
case 0x13:
dev->pci_conf[0x13] = val;
ali1621_mask_bar(dev);
break;
case 0x34:
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val;
break;
case 0x41:
dev->pci_conf[addr] = val;
break;
case 0x42:
dev->pci_conf[addr] = val;
break;
case 0x43:
dev->pci_conf[addr] = val;
break;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
case 0x46:
dev->pci_conf[addr] = val;
break;
case 0x47:
dev->pci_conf[addr] = val;
break;
case 0x48:
dev->pci_conf[addr] = val;
break;
case 0x49:
dev->pci_conf[addr] = val;
break;
case 0x4a:
dev->pci_conf[addr] = val;
break;
case 0x4b:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x4c:
dev->pci_conf[addr] = val;
break;
case 0x4d:
dev->pci_conf[addr] = val;
break;
case 0x4e:
dev->pci_conf[addr] = val;
break;
case 0x4f:
dev->pci_conf[addr] = val;
break;
case 0x50:
dev->pci_conf[addr] = val & 0xef;
break;
case 0x51:
dev->pci_conf[addr] = val;
break;
case 0x52:
dev->pci_conf[addr] = val & 0x9f;
break;
case 0x53:
dev->pci_conf[addr] = val;
break;
case 0x54:
dev->pci_conf[addr] = val & 0xb4;
break;
case 0x55:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x56:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x57:
dev->pci_conf[addr] = val & 0x08;
break;
case 0x58:
dev->pci_conf[addr] = val;
break;
case 0x59:
dev->pci_conf[addr] = val;
break;
case 0x5a:
dev->pci_conf[addr] = val;
break;
case 0x5c:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x60:
dev->pci_conf[addr] = val;
break;
case 0x61:
dev->pci_conf[addr] = val;
break;
case 0x62:
dev->pci_conf[addr] = val;
break;
case 0x63:
dev->pci_conf[addr] = val;
break;
case 0x64:
dev->pci_conf[addr] = val & 0xb7;
break;
case 0x65:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x66:
dev->pci_conf[addr] &= ~(val & 0x33);
break;
case 0x67:
dev->pci_conf[addr] = val;
break;
case 0x68:
dev->pci_conf[addr] = val;
break;
case 0x69:
dev->pci_conf[addr] = val;
break;
case 0x6c ... 0x7b:
/* Bits 22:20 = DRAM Row size:
- 000: 4 MB;
- 001: 8 MB;
- 010: 16 MB;
- 011: 32 MB;
- 100: 64 MB;
- 101: 128 MB;
- 110: 256 MB;
- 111: Reserved. */
dev->pci_conf[addr] = val;
spd_write_drbs_ali1621(dev->pci_conf, 0x6c, 0x7b);
break;
case 0x7c ... 0x7f:
dev->pci_conf[addr] = val;
break;
case 0x80:
dev->pci_conf[addr] = val;
break;
case 0x81:
dev->pci_conf[addr] = val & 0xdf;
break;
case 0x82:
dev->pci_conf[addr] = val & 0xf7;
break;
case 0x83:
dev->pci_conf[addr] = val & 0xfc;
ali1621_smram_recalc(val & 0xfc, dev);
break;
case 0x84 ... 0x87:
if (addr == 0x87)
dev->pci_conf[addr] = val & 0x3f;
else
dev->pci_conf[addr] = val;
ali1621_shadow_recalc(val, dev);
break;
case 0x88:
case 0x89:
dev->pci_conf[addr] = val;
break;
case 0x8a:
dev->pci_conf[addr] = val & 0xc5;
break;
case 0x8b:
dev->pci_conf[addr] = val & 0xbf;
break;
case 0x8c ... 0x8f:
dev->pci_conf[addr] = val;
break;
case 0x90:
dev->pci_conf[addr] = val;
break;
case 0x91:
dev->pci_conf[addr] = val & 0x07;
break;
case 0x94 ... 0x97:
dev->pci_conf[addr] = val;
break;
case 0x98 ... 0x9b:
dev->pci_conf[addr] = val;
break;
case 0x9c ... 0x9f:
dev->pci_conf[addr] = val;
break;
case 0xa0:
case 0xa1:
dev->pci_conf[addr] = val;
break;
case 0xbc:
dev->pci_conf[addr] = val & 0x0f;
ali1621_mask_bar(dev);
break;
case 0xbd:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0xbe:
case 0xbf:
dev->pci_conf[addr] = val;
break;
case 0xc0:
dev->pci_conf[addr] = val & 0xb1;
break;
case 0xc4 ... 0xc7:
dev->pci_conf[addr] = val;
break;
case 0xc8:
dev->pci_conf[addr] = val & 0x8c;
break;
case 0xc9:
dev->pci_conf[addr] = val;
break;
case 0xca:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0xcb:
dev->pci_conf[addr] = val & 0x87;
break;
case 0xcc ... 0xcf:
dev->pci_conf[addr] = val;
break;
case 0xd0:
dev->pci_conf[addr] = val & 0x80;
break;
case 0xd2:
dev->pci_conf[addr] = val & 0x40;
break;
case 0xd3:
dev->pci_conf[addr] = val & 0xb0;
break;
case 0xd4:
dev->pci_conf[addr] = val;
break;
case 0xd5:
dev->pci_conf[addr] = val & 0xef;
break;
case 0xd6:
case 0xd7:
dev->pci_conf[addr] = val;
break;
case 0xf0 ... 0xff:
dev->pci_conf[addr] = val;
break;
default:
break;
}
}
static uint8_t
ali1621_read(UNUSED(int func), int addr, void *priv)
{
const ali1621_t *dev = (ali1621_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
}
static void
ali1621_reset(void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x21;
dev->pci_conf[0x03] = 0x16;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0x01;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x10] = 0x08;
dev->pci_conf[0x34] = 0xb0;
dev->pci_conf[0x40] = 0x0c;
dev->pci_conf[0x41] = 0x0c;
dev->pci_conf[0x4c] = 0x04;
dev->pci_conf[0x4d] = 0x04;
dev->pci_conf[0x4e] = 0x7f;
dev->pci_conf[0x4f] = 0x7f;
dev->pci_conf[0x50] = 0x0c;
dev->pci_conf[0x53] = 0x02;
dev->pci_conf[0x5a] = 0x02;
dev->pci_conf[0x63] = 0x02;
dev->pci_conf[0x6c] = dev->pci_conf[0x70] = dev->pci_conf[0x74] = dev->pci_conf[0x78] = 0xff;
dev->pci_conf[0x6d] = dev->pci_conf[0x71] = dev->pci_conf[0x75] = dev->pci_conf[0x79] = 0xff;
dev->pci_conf[0x6e] = dev->pci_conf[0x72] = dev->pci_conf[0x76] = dev->pci_conf[0x7a] = 0x00;
dev->pci_conf[0x6f] = dev->pci_conf[0x73] = dev->pci_conf[0x77] = dev->pci_conf[0x7b] = 0xe0;
dev->pci_conf[0x6f] |= 0x06;
dev->pci_conf[0x7c] = 0x11;
dev->pci_conf[0x7d] = 0xc4;
dev->pci_conf[0x7e] = 0xc7;
dev->pci_conf[0x80] = 0x01;
dev->pci_conf[0x81] = 0xc0;
dev->pci_conf[0x8e] = 0x01;
dev->pci_conf[0xa0] = 0x20;
dev->pci_conf[0xb0] = 0x02;
dev->pci_conf[0xb2] = 0x10;
dev->pci_conf[0xb4] = 0x03;
dev->pci_conf[0xb5] = 0x02;
dev->pci_conf[0xb7] = 0x20;
dev->pci_conf[0xc0] = 0x80;
dev->pci_conf[0xc9] = 0x28;
dev->pci_conf[0xd4] = 0x10;
dev->pci_conf[0xd5] = 0x01;
dev->pci_conf[0xf0] = dev->pci_conf[0xf4] = dev->pci_conf[0xf8] = dev->pci_conf[0xfc] = 0x20;
dev->pci_conf[0xf1] = dev->pci_conf[0xf5] = dev->pci_conf[0xf9] = dev->pci_conf[0xfd] = 0x43;
dev->pci_conf[0xf2] = dev->pci_conf[0xf6] = dev->pci_conf[0xfa] = dev->pci_conf[0xfe] = 0x21;
dev->pci_conf[0xf3] = dev->pci_conf[0xf7] = dev->pci_conf[0xfb] = dev->pci_conf[0xff] = 0x43;
ali1621_write(0, 0x83, 0x08, dev);
for (uint8_t i = 0; i < 4; i++)
ali1621_write(0, 0x84 + i, 0x00, dev);
}
static void
ali1621_close(void *priv)
{
ali1621_t *dev = (ali1621_t *) priv;
smram_del(dev->smram[1]);
smram_del(dev->smram[0]);
free(dev);
}
static void *
ali1621_init(UNUSED(const device_t *info))
{
ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
memset(dev, 0, sizeof(ali1621_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev, &dev->pci_slot);
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();
ali1621_reset(dev);
device_add(&ali5247_agp_device);
return dev;
}
const device_t ali1621_device = {
.name = "ALi M1621 CPU-to-PCI Bridge",
.internal_name = "ali1621",
.flags = DEVICE_PCI,
.local = 0,
.init = ali1621_init,
.close = ali1621_close,
.reset = ali1621_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1621.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,847 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Western Digital WD76C10 chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/plat_fallthrough.h>
#include <86box/chipset.h>
/* Lock/Unlock Procedures */
#define LOCK dev->locked
#define UNLOCKED !dev->locked
#define WD76C10_ADDR_INVALID 0x80000000
#ifdef ENABLE_WD76C10_LOG
int wd76c10_do_log = ENABLE_WD76C10_LOG;
static void
wd76c10_log(const char *fmt, ...)
{
va_list ap;
if (wd76c10_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define wd76c10_log(fmt, ...)
#endif
typedef struct {
uint32_t enable;
uint32_t virt_addr, phys_addr;
uint32_t virt_size, phys_size;
} ram_bank_t;
typedef struct {
uint8_t enabled;
uint32_t virt, phys;
uint32_t size;
} ems_page_t;
typedef struct
{
uint8_t ep, p92;
uint8_t vbios_states[4];
uint8_t bios_states[8];
uint8_t high_bios_states[8];
uint8_t mem_pages[1024];
uint8_t ram_state[4192];
uint16_t toggle, cpuclk, fpu_ctl, mem_ctl,
split_sa, sh_wp, hmwpb, npmdmt,
ems_ctl, ems_pp, ser_par_cs, rtc_disk_cs,
prog_cs, pmc_in;
union
{
uint16_t bank_base_regs[2];
uint8_t bank_bases[4];
};
uint16_t ems_page_regs[40];
int locked;
uint32_t mem_top, hmwp_base;
ram_bank_t ram_banks[5];
ems_page_t ems_pages[40];
mem_mapping_t ram_mapping;
nvr_t *nvr;
fdc_t *fdc;
serial_t *uart[2];
} wd76c10_t;
static uint32_t bank_sizes[4] = { 0x00020000, /* 64 Kbit X 16 = 1024 Kbit = 128 kB, 8x 8 */
0x00080000, /* 256 Kbit X 16 = 4096 Kbit = 512 kB, 9x 9 */
0x00200000, /* 1 Mbit X 16 = 16 Mbit = 2 MB, 10x10 */
0x00800000 }; /* 4 Mbit X 16 = 64 Mbit = 8 MB, 11x11 */
static uint32_t
wd76c10_calc_addr(wd76c10_t *dev, uint32_t addr)
{
uint32_t ret;
uint8_t ems_page;
uint8_t ems_en = (uint8_t) ((dev->ems_ctl >> 10) & 0x03);
ems_page_t *ep;
uint8_t en_res = (uint8_t) ((dev->ems_ctl >> 7) & 0x01);
uint32_t low_boundary = (((uint32_t) (dev->ems_ctl & 0x007f)) << 17) + 131072;
ram_bank_t *rb = &(dev->ram_banks[4]);
addr &= 0x00ffffff;
ems_page = dev->mem_pages[addr >> 14];
ep = &dev->ems_pages[ems_page];
ret = addr;
/* First, do any address translation (EMS, low boundary filtering). */
if ((ems_page < 0x20) && (ems_en == 0x03))
/* Low EMS pages. */
ret = addr - ep->virt + ep->phys;
else if ((ems_page >= 0x20) && (ems_page < 0x2a) && (ems_en >= 0x02) && ep->enabled)
/* High EMS pages. */
ret = addr - ep->virt + ep->phys;
else if (en_res && (addr >= low_boundary))
/* EMS low boundary. */
ret = WD76C10_ADDR_INVALID;
/* Then, do the split. */
if (rb->enable && (ret >= rb->virt_addr) && (ret < (rb->virt_addr + rb->virt_size)))
ret = ret - rb->virt_addr + rb->phys_addr;
/* Then, disable the required amount of on-board memory between 128k and 640k if so requested. */
if ((ret >= dev->mem_top) && (ret < 0x000a0000))
ret = WD76C10_ADDR_INVALID;
/* Then, handle the physical memory banks. */
if (ret >= (mem_size << 10))
/* The physical memory address is too high or disabled, which is invalid. */
ret = WD76C10_ADDR_INVALID;
/* Otherwise, map it to the correct bank so the BIOS can auto-size it correctly. */
else for (uint8_t i = 0; i < 4; i++) {
rb = &(dev->ram_banks[i]);
if (rb->enable && (ret >= rb->virt_addr) && (ret < (rb->virt_addr + rb->virt_size))) {
if (rb->phys_size == 0x00000000)
ret = WD76C10_ADDR_INVALID;
else
ret = ((ret - rb->virt_addr) % rb->phys_size) + rb->phys_addr;
break;
}
}
return ret;
}
static uint8_t
wd76c10_read_ram(uint32_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *) priv;
uint8_t ret = 0xff;
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
ret = mem_read_ram(addr, priv);
return ret;
}
static uint16_t
wd76c10_read_ramw(uint32_t addr, void *priv)
{
wd76c10_t *dev = (wd76c10_t *) priv;
uint16_t ret = 0xffff;
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
ret = mem_read_ramw(addr, priv);
return ret;
}
static void
wd76c10_write_ram(uint32_t addr, uint8_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *) priv;
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
mem_write_ram(addr, val, priv);
}
static void
wd76c10_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *) priv;
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
mem_write_ramw(addr, val, priv);
}
static void
wd76c10_set_mem_state(wd76c10_t *dev, uint32_t base, uint32_t size, uint32_t access, uint8_t present)
{
mem_set_mem_state_both(base, size, access);
for (uint32_t i = base; i < (base + size); i += 4096)
dev->ram_state[i >> 12] = present;
}
static void
wd76c10_recalc_exec(wd76c10_t *dev, uint32_t base, uint32_t size)
{
uint32_t logical_addr = wd76c10_calc_addr(dev, base);
void *exec;
if (logical_addr != WD76C10_ADDR_INVALID)
exec = &(ram[logical_addr]);
else
exec = NULL;
for (uint32_t i = base; i < (base + size); i += 4096)
if (dev->ram_state[i >> 12])
_mem_exec[i >> 12] = exec;
if (cpu_use_exec)
flushmmucache_nopc();
}
static void
wd76c10_banks_recalc(wd76c10_t *dev)
{
for (uint8_t i = 0; i < 4; i++) {
ram_bank_t *rb = &(dev->ram_banks[i]);
uint8_t bit = i << 1;
rb->virt_size = bank_sizes[(dev->mem_ctl >> bit) & 0x03];
bit = i + 12;
rb->enable = (dev->split_sa >> bit) & 0x01;
rb->virt_addr = ((uint32_t) dev->bank_bases[i]) << 17;
if (cpu_use_exec)
wd76c10_recalc_exec(dev, rb->virt_addr, rb->virt_size);
}
}
static void
wd76c10_split_recalc(wd76c10_t *dev)
{
uint32_t sp_size = (dev->split_sa >> 8) & 0x03;
uint32_t split_size = ((sp_size - 1) * 65536);
ram_bank_t *rb = &(dev->ram_banks[4]);
if (rb->enable && (rb->virt_size != 0x00000000)) {
wd76c10_set_mem_state(dev, rb->virt_addr, rb->virt_size, MEM_READ_EXTANY | MEM_WRITE_EXTANY, 0);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, rb->virt_addr, rb->virt_size);
}
rb->virt_addr = ((uint32_t) ((dev->split_sa >> 2) & 0x3f)) << 19;
switch (sp_size) {
case 0x00:
rb->virt_size = 0x00000000;
break;
default:
rb->virt_size = 256 * 1024 + split_size;
break;
}
rb->enable = !!sp_size;
if (rb->enable && (rb->virt_size != 0x00000000)) {
wd76c10_set_mem_state(dev, rb->virt_addr, rb->virt_size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL, 1);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, rb->virt_addr, rb->virt_size);
}
}
static void
wd76c10_dis_mem_recalc(wd76c10_t *dev)
{
uint8_t dis_mem = (uint8_t) ((dev->sh_wp >> 14) & 0x03);
uint32_t mem_top;
switch (dis_mem) {
case 0x00:
default:
mem_top = 640 * 1024;
break;
case 0x01:
mem_top = 512 * 1024;
break;
case 0x02:
mem_top = 256 * 1024;
break;
case 0x03:
mem_top = 128 * 1024;
break;
}
dev->mem_top = mem_top;
if (cpu_use_exec)
wd76c10_recalc_exec(dev, 128 * 1024, (640 - 128) * 1024);
}
static void
wd76c10_shadow_ram_do_recalc(wd76c10_t *dev, uint8_t *new_st, uint8_t *old_st, uint8_t min, uint8_t max, uint32_t addr)
{
uint32_t base = 0x00000000;
int flags = 0;
for (uint8_t i = min; i < max; i++) {
if (new_st[i] != old_st[i]) {
old_st[i] = new_st[i];
base = addr + ((uint32_t) i) * 0x00004000;
flags = (new_st[i] & 0x01) ? MEM_READ_INTERNAL :
((new_st[i] & 0x04) ? MEM_READ_ROMCS : MEM_READ_EXTERNAL);
flags |= (new_st[i] & 0x02) ? MEM_WRITE_INTERNAL :
((new_st[i] & 0x04) ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL);
wd76c10_set_mem_state(dev, base, 0x00004000, flags, new_st[i] & 0x01);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, base, 0x000040000);
}
}
}
static void
wd76c10_shadow_ram_recalc(wd76c10_t *dev)
{
uint8_t vbios_states[4] = { 0 };
uint8_t bios_states[8] = { 0 };
uint8_t high_bios_states[8] = { 0 };
uint8_t wp = (uint8_t) ((dev->sh_wp >> 12) & 0x01);
uint8_t shd = (uint8_t) ((dev->sh_wp >> 8) & 0x03);
uint8_t x_mem = (uint8_t) ((dev->sh_wp >> 7) & 0x01);
uint8_t vb_siz = (uint8_t) ((dev->sh_wp >> 4) & 0x03);
uint8_t vb_top = vb_siz + 1;
uint8_t rom_typ = (uint8_t) ((dev->sh_wp >> 2) & 0x03);
switch (shd) {
case 0x03:
for (uint8_t i = 0; i < vb_top; i++) {
vbios_states[i] |= 0x01; /* Read. */
if (!wp)
vbios_states[i] |= 0x02; /* Write. */
}
if (x_mem) {
for (uint8_t i = 2; i < 4; i++)
bios_states[i] |= 0x03; /* Read/write. */
}
fallthrough;
case 0x01:
for (uint8_t i = 4; i < 8; i++) {
bios_states[i] |= 0x01; /* Read. */
if (!wp)
bios_states[i] |= 0x02; /* Write. */
}
break;
case 0x02:
for (uint8_t i = 0; i < 8; i++) {
bios_states[i] |= 0x01; /* Read. */
if (!wp)
bios_states[i] |= 0x02; /* Write. */
}
break;
}
switch (rom_typ) {
case 0x00:
for (uint8_t i = 0; i < 8; i++) {
bios_states[i] |= 0x04; /* CSPROM#. */
high_bios_states[i] |= 0x04; /* CSPROM#. */
}
break;
case 0x02:
for (uint8_t i = 0; i < vb_top; i++)
vbios_states[i] |= 0x04; /* CSPROM#. */
fallthrough;
case 0x01:
for (uint8_t i = 4; i < 8; i++) {
bios_states[i] |= 0x04; /* CSPROM#. */
high_bios_states[i] |= 0x04; /* CSPROM#. */
}
break;
}
wd76c10_shadow_ram_do_recalc(dev, vbios_states, dev->vbios_states, 0, 4, 0x000c0000);
wd76c10_shadow_ram_do_recalc(dev, bios_states, dev->bios_states, 0, 8, 0x000e0000);
/* This is not shadowed, but there is a CSPROM# (= ROMCS#) toggle. */
wd76c10_shadow_ram_do_recalc(dev, high_bios_states, dev->high_bios_states, 0, 8, 0x00fe0000);
flushmmucache_nopc();
}
static void
wd76c10_high_mem_wp_recalc(wd76c10_t *dev)
{
uint8_t hm_wp = (uint8_t) ((dev->sh_wp >> 13) & 0x01);
uint32_t base = ((uint32_t) (dev->hmwpb & 0x00f0)) << 17;
uint32_t size = 0x01000000 - dev->hmwp_base;
/* ACCESS_NORMAL means both ACCESS_BUS and ACCESS_CPU are set. */
mem_set_wp(dev->hmwp_base, size, ACCESS_NORMAL, 0);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, dev->hmwp_base, size);
size = 0x01000000 - base;
mem_set_wp(base, size, ACCESS_NORMAL, hm_wp);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, base, size);
dev->hmwp_base = base;
}
static void
wd76c10_pf_loc_reset(wd76c10_t *dev)
{
uint32_t base;
for (uint8_t i = 0x031; i <= 0x03b; i++) {
dev->mem_pages[i] = 0xff;
base = ((uint32_t) i) << 14;
wd76c10_set_mem_state(dev, base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY, 0);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, base, 0x00004000);
}
/* Re-apply any ROMCS#, etc. flags. */
wd76c10_shadow_ram_recalc(dev);
}
static void
wd76c10_pf_loc_recalc(wd76c10_t *dev)
{
uint8_t pf_loc = (uint8_t) ((dev->ems_ctl >> 13) & 0x03);
uint8_t ems_en = (uint8_t) ((dev->ems_ctl >> 10) & 0x03);
uint8_t ems_page;
uint32_t base;
for (uint8_t i = (0x031 + pf_loc); i <= (0x037 + pf_loc); i++) {
ems_page = (i - 0x10) & 0xf7;
dev->mem_pages[i] = ems_page;
base = ((uint32_t) i) << 14;
dev->ems_pages[ems_page].virt = base;
if ((ems_en >= 0x02) && dev->ems_pages[ems_page].enabled) {
wd76c10_set_mem_state(dev, dev->ems_pages[ems_page].virt,
0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL, 1);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, dev->ems_pages[ems_page].virt, 0x00004000);
}
}
}
static void
wd76c10_low_pages_recalc(wd76c10_t *dev)
{
uint8_t ems_page;
uint32_t base;
for (uint8_t i = 0x008; i <= 0x027; i++) {
ems_page = i & 0x1f;
dev->mem_pages[i] = ems_page;
base = ((uint32_t) i) << 14;
dev->ems_pages[ems_page].virt = base;
if (cpu_use_exec)
wd76c10_recalc_exec(dev, dev->ems_pages[ems_page].virt, 0x00004000);
}
}
static void
wd76c10_ser_par_cs_recalc(wd76c10_t *dev)
{
/* Serial B */
serial_remove(dev->uart[1]);
switch ((dev->ser_par_cs >> 1) & 0x07) {
case 0x01:
serial_setup(dev->uart[1], 0x3f8, 3);
break;
case 0x02:
serial_setup(dev->uart[1], 0x2f8, 3);
break;
case 0x03:
serial_setup(dev->uart[1], 0x3e8, 3);
break;
case 0x04:
serial_setup(dev->uart[1], 0x2e8, 3);
break;
}
/* Serial A */
serial_remove(dev->uart[0]);
switch ((dev->ser_par_cs >> 5) & 0x07) {
case 0x01:
serial_setup(dev->uart[0], 0x3f8, 4);
break;
case 0x02:
serial_setup(dev->uart[0], 0x2f8, 4);
break;
case 0x03:
serial_setup(dev->uart[0], 0x3e8, 4);
break;
case 0x04:
serial_setup(dev->uart[0], 0x2e8, 4);
break;
}
/* LPT */
lpt1_remove();
switch ((dev->ser_par_cs >> 9) & 0x03) {
case 1:
lpt1_init(0x3bc);
lpt1_irq(7);
break;
case 2:
lpt1_init(0x378);
lpt1_irq(7);
break;
case 3:
lpt1_init(0x278);
lpt1_irq(7);
break;
}
}
static void
wd76c10_disk_cs_recalc(wd76c10_t *dev)
{
ide_pri_disable();
ide_set_base(0, (dev->rtc_disk_cs & 0x0010) ? 0x0170 : 0x01f0);
ide_set_side(0, (dev->rtc_disk_cs & 0x0010) ? 0x0376 : 0x03f6);
if (!(dev->rtc_disk_cs & 0x0002))
ide_pri_enable();
fdc_remove(dev->fdc);
if (!(dev->rtc_disk_cs & 0x0001))
fdc_set_base(dev->fdc, (dev->rtc_disk_cs & 0x0010) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
static void
wd76c10_outb(uint16_t port, uint8_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
uint8_t lk_psw = (uint8_t) ((dev->rtc_disk_cs >> 2) & 0x01);
uint8_t valxor;
switch (port) {
case 0x0092:
if ((lk_psw && (val & 0x08)) || ((dev->p92 & 0x08) && !(val & 0x08)))
val = (val & 0xf7) | (dev->p92 & 0x08);
valxor = (dev->p92 ^ val) & 0x08;
dev->p92 = (val & 0x08) | 0xf7;
if (valxor)
nvr_lock_set(0x38, 0x08, (val & 0x08) ? 0x03 : 0x00, dev->nvr);
break;
}
}
static void
wd76c10_outw(uint16_t port, uint16_t val, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
uint8_t inc = (uint8_t) ((dev->ems_ctl >> 15) & 0x01);
uint8_t ems_en;
if (!dev->locked || (port < 0x1072) || (port > 0xf872) ||
(port == 0xe072) || (port == 0xe872) || (port == 0xf073)) switch (port) {
case 0x1072:
dev->cpuclk = val;
break;
case 0x1872:
dev->fpu_ctl = val;
break;
case 0x2072:
dev->ser_par_cs = val;
wd76c10_ser_par_cs_recalc(dev);
break;
case 0x2872:
dev->rtc_disk_cs = val;
wd76c10_disk_cs_recalc(dev);
break;
case 0x3072:
dev->prog_cs = val;
break;
/* TODO: Log this to determine how the BIOS does bank sizing. */
case 0x3872:
dev->mem_ctl = val;
wd76c10_banks_recalc(dev);
break;
case 0x4072:
dev->npmdmt = val;
break;
/* A17-A24 */
case 0x4872:
dev->bank_base_regs[0] = val;
wd76c10_banks_recalc(dev);
break;
/* A17-A24 */
case 0x5072:
dev->bank_base_regs[1] = val;
wd76c10_banks_recalc(dev);
break;
case 0x5872:
dev->split_sa = val;
wd76c10_banks_recalc(dev);
wd76c10_split_recalc(dev);
break;
case 0x6072:
dev->sh_wp = val;
wd76c10_dis_mem_recalc(dev);
wd76c10_pf_loc_reset(dev);
wd76c10_pf_loc_recalc(dev);
wd76c10_low_pages_recalc(dev);
wd76c10_high_mem_wp_recalc(dev);
break;
case 0x6872:
dev->ems_ctl = val;
wd76c10_pf_loc_reset(dev);
wd76c10_pf_loc_recalc(dev);
wd76c10_low_pages_recalc(dev);
break;
case 0x8872:
dev->pmc_in = val;
break;
case 0xc072:
dev->hmwpb = val;
wd76c10_high_mem_wp_recalc(dev);
break;
case 0xe072:
dev->ems_pp = val;
dev->ep = (val & 0x3f) % 40;
break;
case 0xe872:
ems_en = (uint8_t) ((dev->ems_ctl >> 10) & 0x03);
if (ems_en) {
dev->ems_page_regs[dev->ep] = val;
dev->ems_pages[dev->ep].phys = ((uint32_t) (val & 0x0fff)) << 14;
if (dev->ep >= 32) {
dev->ems_pages[dev->ep].enabled = !!(val & 0x8000);
if (ems_en >= 0x02) {
wd76c10_pf_loc_reset(dev);
wd76c10_pf_loc_recalc(dev);
}
} else {
dev->ems_pages[dev->ep].enabled = (ems_en == 0x03);
if (ems_en == 0x03)
wd76c10_low_pages_recalc(dev);
}
}
if (inc)
dev->ep = (dev->ep + 1) % 40;
break;
case 0xf073:
dev->locked = ((val & 0x00ff) != 0x00da);
break;
case 0xf872:
flushmmucache();
break;
}
}
static uint8_t
wd76c10_inb(uint16_t port, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
uint8_t ret = 0xff;
switch (port) {
case 0x0092:
ret = (dev->p92 & 0x08) | 0xf7;
break;
}
return ret;
}
static uint16_t
wd76c10_inw(uint16_t port, void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
uint8_t inc = (uint8_t) ((dev->ems_ctl >> 15) & 0x01);
uint16_t ret = 0xffff;
wd76c10_log("WD76C10: R dev->regs[%04x]\n", port);
if (!dev->locked || (port < 0x1072) || (port > 0xf872) ||
(port == 0xe072) || (port == 0xe872) || (port == 0xf073)) switch (port) {
case 0x1072:
ret = dev->cpuclk;
break;
case 0x1872:
ret = dev->fpu_ctl;
break;
case 0x2072:
ret = dev->ser_par_cs;
break;
case 0x2872:
ret = dev->rtc_disk_cs;
break;
case 0x3072:
ret = dev->prog_cs;
break;
case 0x3872:
ret = dev->mem_ctl;
break;
case 0x4072:
ret = dev->npmdmt;
break;
case 0x4872:
ret = dev->bank_base_regs[0];
break;
case 0x5072:
ret = dev->bank_base_regs[1];
break;
case 0x5872:
ret = dev->split_sa;
break;
case 0x6072:
ret = dev->sh_wp;
break;
case 0x6872:
ret = dev->ems_ctl;
break;
case 0x8872:
ret = dev->pmc_in;
break;
case 0xb872:
ret = dma[0].mode;
ret |= (((uint16_t) dma[1].mode) << 8);
break;
case 0xc072:
ret = dev->hmwpb;
break;
case 0xd072:
ret = (serial_read(0x0002, dev->uart[0]) & 0xc0) << 8;
ret |= (serial_read(0x0002, dev->uart[1]) & 0xc0) << 6;
ret |= (lpt_read_port(0, 0x0002) & 0x0f) << 8;
ret |= lpt_read_port(0, 0x0000);
break;
case 0xe072:
ret = (dev->ems_pp & 0xffc0) | dev->ep;
break;
case 0xe872:
ret = dev->ems_page_regs[dev->ep];
if (inc)
dev->ep = (dev->ep + 1) % 40;
break;
case 0xfc72:
ret = ((lpt_read_status(0) & 0x20) >> 2);
ret |= (((uint16_t) dma_m) << 4);
ret |= dev->toggle;
dev->toggle ^= 0x8000;
break;
}
return ret;
}
static void
wd76c10_close(void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
free(dev);
}
static void
wd76c10_reset(void *priv)
{
wd76c10_t *dev = (wd76c10_t *)priv;
dev->locked = 1;
dev->toggle = 0;
dev->p92 = 0xf7;
dev->cpuclk = 0x1000;
dev->fpu_ctl = 0x00ca;
dev->mem_ctl = 0x0000;
dev->bank_base_regs[0] = 0x0000;
dev->bank_base_regs[1] = 0x0000;
dev->split_sa = 0x0000;
dev->sh_wp = 0x0000;
dev->hmwpb = 0x0000;
dev->npmdmt = 0x0000;
dev->ems_ctl = 0x0000;
dev->ems_pp = 0x0000;
dev->ser_par_cs = 0x0000;
dev->rtc_disk_cs = 0x0000;
for (uint8_t i = 0; i < 40; i++) {
dev->ems_page_regs[i] = 0x0000;
dev->ems_pages[i].enabled = 0;
dev->ems_pages[i].phys = 0x00000000;
}
nvr_lock_set(0x38, 0x08, 0x00, dev->nvr);
wd76c10_banks_recalc(dev);
wd76c10_split_recalc(dev);
wd76c10_dis_mem_recalc(dev);
wd76c10_high_mem_wp_recalc(dev);
wd76c10_pf_loc_reset(dev);
wd76c10_pf_loc_recalc(dev);
wd76c10_low_pages_recalc(dev);
wd76c10_ser_par_cs_recalc(dev);
wd76c10_disk_cs_recalc(dev);
}
static void *
wd76c10_init(const device_t *info)
{
wd76c10_t *dev = (wd76c10_t *) calloc(1, sizeof(wd76c10_t));
uint32_t total_mem = mem_size << 10;
uint32_t accum_mem = 0x00000000;
ram_bank_t *rb;
/* Calculate the physical RAM banks. */
for (uint8_t i = 0; i < 4; i++) {
rb = &(dev->ram_banks[i]);
uint32_t size = 0x00000000;
for (int8_t j = 3; j >= 0; j--) {
uint32_t *bs = &(bank_sizes[j]);
if (*bs <= total_mem) {
size = *bs;
break;
}
}
if (size != 0x00000000) {
rb->phys_addr = accum_mem;
rb->phys_size = size;
total_mem -= size;
accum_mem += size;
}
}
rb = &(dev->ram_banks[4]);
rb->phys_addr = 0x000a0000;
rb->phys_size = 0x00060000;
memset(dev->mem_pages, 0xff, sizeof(dev->mem_pages));
for (uint8_t i = 0x008; i < 0x01f; i++)
dev->mem_pages[i] = i;
for (uint8_t i = 0x020; i < 0x027; i++)
dev->mem_pages[i] = i - 0x20;
device_add(&port_92_inv_device);
dev->nvr = device_add(&amstrad_megapc_nvr_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
dev->fdc = device_add(&fdc_at_device);
device_add(&ide_isa_device);
wd76c10_reset(dev);
/* Password Lock */
io_sethandler(0x0092, 1, wd76c10_inb, NULL, NULL, wd76c10_outb, NULL, NULL, dev);
/* Clock Control */
io_sethandler(0x1072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* FPU Bus Timing & Power Down Control */
io_sethandler(0x1872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Refresh Control, Serial and Parallel Chip Selects */
io_sethandler(0x2072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* RTC, PVGA, 80287 Timing, and Disk Chip Selects */
io_sethandler(0x2872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Programmable Chip Select Address */
io_sethandler(0x3072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Memory Control */
io_sethandler(0x3872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Non-page Mode DRAM Memory Timing */
io_sethandler(0x4072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Bank 1 & 0 Start Address */
io_sethandler(0x4872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Bank 3 & 2 Start Address */
io_sethandler(0x5072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Split Address */
io_sethandler(0x5872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* RAM Shadow And Write Protect */
io_sethandler(0x6072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* EMS Control And Lower EMS Boundary */
io_sethandler(0x6872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* PMC Inputs */
io_sethandler(0x8872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* DMA Mode Shadow Register */
io_sethandler(0xb872, 1, NULL, wd76c10_inw, NULL, NULL, NULL, NULL, dev);
/* High Memory Write Protect Boundry */
io_sethandler(0xc072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Shadow Register */
io_sethandler(0xd072, 1, NULL, wd76c10_inw, NULL, NULL, NULL, NULL, dev);
/* EMS Page Register Pointer */
io_sethandler(0xe072, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* EMS Page Register */
io_sethandler(0xe872, 1, NULL, wd76c10_inw, NULL, NULL, wd76c10_outw, NULL, dev);
/* Lock/Unlock Configuration */
io_sethandler(0xf073, 1, NULL, NULL, NULL, NULL, wd76c10_outw, NULL, dev);
/* Cache Flush */
io_sethandler(0xf872, 1, NULL, NULL, NULL, NULL, wd76c10_outw, NULL, dev);
/* Lock Status */
io_sethandler(0xfc72, 1, NULL, wd76c10_inw, NULL, NULL, NULL, NULL, dev);
dma_ext_mode_init();
mem_mapping_add(&dev->ram_mapping,
0x00000000,
(mem_size + 384) << 10,
wd76c10_read_ram,
wd76c10_read_ramw,
NULL,
wd76c10_write_ram,
wd76c10_write_ramw,
NULL,
ram,
MEM_MAPPING_INTERNAL,
dev);
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
mem_mapping_enable(&dev->ram_mapping);
memset(dev->ram_state, 0x00, sizeof(dev->ram_state));
return dev;
}
const device_t wd76c10_device = {
.name = "Western Digital WD76C10",
.internal_name = "wd76c10",
.flags = 0,
.local = 0,
.init = wd76c10_init,
.close = wd76c10_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/wd76c10.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,395 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VLSI VL82c480 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct vl82c480_t {
uint8_t idx;
uint8_t regs[256];
} vl82c480_t;
static int
vl82c480_shflags(uint8_t access)
{
int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
switch (access) {
default:
case 0x00:
ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
break;
case 0x01:
ret = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
break;
case 0x02:
ret = MEM_READ_INTERNAL | MEM_WRITE_EXTANY;
break;
case 0x03:
ret = MEM_READ_INTERNAL | MEM_WRITE_INTERNAL;
break;
}
return ret;
}
static void
vl82c480_recalc(vl82c480_t *dev)
{
uint32_t base;
uint8_t access;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t i = 0; i < 6; i++) {
for (uint8_t j = 0; j < 8; j += 2) {
base = 0x000a0000 + (i << 16) + (j << 13);
access = (dev->regs[0x0d + i] >> j) & 3;
mem_set_mem_state(base, 0x4000, vl82c480_shflags(access));
shadowbios |= ((base >= 0xe0000) && (access & 0x02));
shadowbios_write |= ((base >= 0xe0000) && (access & 0x01));
}
}
flushmmucache();
}
static void
vl82c480_write(uint16_t addr, uint8_t val, void *priv)
{
vl82c480_t *dev = (vl82c480_t *) priv;
switch (addr) {
case 0xec:
dev->idx = val;
break;
case 0xed:
if (dev->idx >= 0x01 && dev->idx <= 0x24) {
switch (dev->idx) {
default:
dev->regs[dev->idx] = val;
break;
case 0x04:
if (dev->regs[0x00] == 0x98)
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7);
else
dev->regs[dev->idx] = val;
break;
case 0x05:
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x10) | (val & 0xef);
break;
case 0x07:
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf);
break;
case 0x0d:
case 0x0e:
case 0x0f:
case 0x10:
case 0x11:
case 0x12:
dev->regs[dev->idx] = val;
vl82c480_recalc(dev);
break;
}
}
break;
/* TODO: This is actually Fast A20 disable. */
#if 0
case 0xee:
if (mem_a20_alt)
outb(0x92, inb(0x92) & ~2);
break;
#endif
default:
break;
}
}
static uint8_t
vl82c480_read(uint16_t addr, void *priv)
{
const vl82c480_t *dev = (vl82c480_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0xec:
ret = dev->idx;
break;
case 0xed:
ret = dev->regs[dev->idx];
break;
/* TODO: This is actually Fast A20 enable. */
#if 0
case 0xee:
if (!mem_a20_alt)
outb(0x92, inb(0x92) | 2);
break;
#endif
case 0xef:
softresetx86();
cpu_set_edx();
break;
default:
break;
}
return ret;
}
static void
vl82c480_close(void *priv)
{
vl82c480_t *dev = (vl82c480_t *) priv;
free(dev);
}
static void *
vl82c480_init(const device_t *info)
{
vl82c480_t *dev = (vl82c480_t *) malloc(sizeof(vl82c480_t));
memset(dev, 0, sizeof(vl82c480_t));
dev->regs[0x00] = info->local;
dev->regs[0x01] = 0xff;
dev->regs[0x02] = 0x8a;
dev->regs[0x03] = 0x88;
dev->regs[0x06] = 0x1b;
if (info->local == 0x98)
dev->regs[0x07] = 0x21;
dev->regs[0x08] = 0x38;
io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev);
device_add(&port_92_device);
return dev;
}
const device_t vl82c480_device = {
.name = "VLSI VL82c480",
.internal_name = "vl82c480",
.flags = 0,
.local = 0x90,
.init = vl82c480_init,
.close = vl82c480_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t vl82c486_device = {
.name = "VLSI VL82c486",
.internal_name = "vl82c486",
.flags = 0,
.local = 0x98,
.init = vl82c480_init,
.close = vl82c480_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/vl82c480.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,660 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of VLSI 82C311 ("SCAMP") chipset.
*
* Note: The datasheet mentions that the chipset supports up to 8MB
* of DRAM. This is intepreted as 'being able to refresh up to
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#define CFG_ID 0x00
#define CFG_SLTPTR 0x02
#define CFG_RAMMAP 0x03
#define CFG_EMSEN1 0x0b
#define CFG_EMSEN2 0x0c
#define CFG_ABAXS 0x0e
#define CFG_CAXS 0x0f
#define CFG_DAXS 0x10
#define CFG_FEAXS 0x11
#define ID_VL82C311 0xd6
#define RAMMAP_REMP386 (1 << 4)
#define EMSEN1_EMSMAP (1 << 4)
#define EMSEN1_EMSENAB (1 << 7)
#define NR_ELEMS(x) (sizeof(x) / sizeof(x[0]))
/*Commodore SL386SX requires proper memory slot decoding to detect memory size.
Therefore we emulate the SCAMP memory address decoding, and therefore are
limited to the DRAM combinations supported by the actual chip*/
enum {
BANK_NONE,
BANK_256K,
BANK_256K_INTERLEAVED,
BANK_1M,
BANK_1M_INTERLEAVED,
BANK_4M,
BANK_4M_INTERLEAVED
};
typedef struct ram_struct_t {
void *parent;
int bank;
} ram_struct_t;
typedef struct ems_struct_t {
void *parent;
int segment;
} ems_struct_t;
typedef struct scamp_t {
int cfg_index;
uint8_t cfg_regs[256];
int cfg_enable;
int ram_config;
int ems_index;
int ems_autoinc;
uint16_t ems[0x24];
mem_mapping_t ems_mappings[20]; /*a0000-effff*/
uint32_t mappings[20];
mem_mapping_t ram_mapping[2];
ram_struct_t ram_struct[2];
ems_struct_t ems_struct[20];
uint32_t ram_virt_base[2];
uint32_t ram_phys_base[2];
uint32_t ram_mask[2];
int row_virt_shift[2];
int row_phys_shift[2];
int ram_interleaved[2];
int ibank_shift[2];
port_92_t *port_92;
} scamp_t;
static const struct {
int size_kb;
int rammap;
int bank[2];
} ram_configs[] = {
{ 512, 0x0, { BANK_256K, BANK_NONE } },
{ 1024, 0x1, { BANK_256K_INTERLEAVED, BANK_NONE } },
{ 1536, 0x2, { BANK_256K_INTERLEAVED, BANK_256K } },
{ 2048, 0x3, { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }},
{ 3072, 0xc, { BANK_256K_INTERLEAVED, BANK_1M } },
{ 4096, 0x5, { BANK_1M_INTERLEAVED, BANK_NONE } },
{ 5120, 0xd, { BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED } },
{ 6144, 0x6, { BANK_1M_INTERLEAVED, BANK_1M } },
{ 8192, 0x7, { BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED } },
{ 12288, 0xe, { BANK_1M_INTERLEAVED, BANK_4M } },
{ 16384, 0x9, { BANK_4M_INTERLEAVED, BANK_NONE } },
};
static const struct {
int bank[2];
int remapped;
} rammap[16] = {
{ { BANK_256K, BANK_NONE }, 0},
{ { BANK_256K_INTERLEAVED, BANK_NONE }, 0},
{ { BANK_256K_INTERLEAVED, BANK_256K }, 0},
{ { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }, 0},
{ { BANK_1M, BANK_NONE }, 0},
{ { BANK_1M_INTERLEAVED, BANK_NONE }, 0},
{ { BANK_1M_INTERLEAVED, BANK_1M }, 0},
{ { BANK_1M_INTERLEAVED, BANK_1M_INTERLEAVED }, 0},
{ { BANK_4M, BANK_NONE }, 0},
{ { BANK_4M_INTERLEAVED, BANK_NONE }, 0},
{ { BANK_NONE, BANK_4M }, 1}, /*Bank 2 remapped to 0*/
{ { BANK_NONE, BANK_4M_INTERLEAVED }, 1}, /*Banks 2/3 remapped to 0/1*/
{ { BANK_256K_INTERLEAVED, BANK_1M }, 0},
{ { BANK_256K_INTERLEAVED, BANK_1M_INTERLEAVED }, 0},
{ { BANK_1M_INTERLEAVED, BANK_4M }, 0},
{ { BANK_1M_INTERLEAVED, BANK_4M_INTERLEAVED }, 0}, /*Undocumented - probably wrong!*/
};
/* The column bits masked when using 256kbit DRAMs in 4Mbit mode aren't contiguous,
so we use separate routines for that special case */
static uint8_t
ram_mirrored_256k_in_4mi_read(uint32_t addr, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
if (!dev->ram_interleaved[bank]) {
if (addr & 0x400)
return 0xff;
addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1);
column = (addr >> 1) & dev->ram_mask[bank];
row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9);
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
} else {
column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1);
row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9);
addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1));
}
return ram[addr + dev->ram_phys_base[bank]];
}
static void
ram_mirrored_256k_in_4mi_write(uint32_t addr, uint8_t val, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
if (!dev->ram_interleaved[bank]) {
if (addr & 0x400)
return;
addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1);
column = (addr >> 1) & dev->ram_mask[bank];
row = ((addr & 0xff000) >> 13) | (((addr & 0x200000) >> 22) << 9);
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
} else {
column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1);
row = ((addr & 0x1fe000) >> 13) | (((addr & 0x400000) >> 22) << 9);
addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1));
}
ram[addr + dev->ram_phys_base[bank]] = val;
}
/*Read/write handlers for interleaved memory banks. We must keep CPU and ram array
mapping linear, otherwise we won't be able to execute code from interleaved banks*/
static uint8_t
ram_mirrored_interleaved_read(uint32_t addr, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
if (!dev->ram_interleaved[bank]) {
if (addr & 0x400)
return 0xff;
addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1);
column = (addr >> 1) & dev->ram_mask[bank];
row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
} else {
column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1);
row = (addr >> (dev->row_virt_shift[bank] + 1)) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1));
}
return ram[addr + dev->ram_phys_base[bank]];
}
static void
ram_mirrored_interleaved_write(uint32_t addr, uint8_t val, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
if (!dev->ram_interleaved[bank]) {
if (addr & 0x400)
return;
addr = (addr & 0x3ff) | ((addr & ~0x7ff) >> 1);
column = (addr >> 1) & dev->ram_mask[bank];
row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
} else {
column = (addr >> 1) & ((dev->ram_mask[bank] << 1) | 1);
row = (addr >> (dev->row_virt_shift[bank] + 1)) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << (dev->row_phys_shift[bank] + 1));
}
ram[addr + dev->ram_phys_base[bank]] = val;
}
static uint8_t
ram_mirrored_read(uint32_t addr, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
column = (addr >> 1) & dev->ram_mask[bank];
row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
return ram[addr + dev->ram_phys_base[bank]];
}
static void
ram_mirrored_write(uint32_t addr, uint8_t val, void *priv)
{
const ram_struct_t *rs = (ram_struct_t *) priv;
const scamp_t *dev = rs->parent;
int bank = rs->bank;
int byte;
int row;
int column;
addr -= dev->ram_virt_base[bank];
byte = addr & 1;
column = (addr >> 1) & dev->ram_mask[bank];
row = (addr >> dev->row_virt_shift[bank]) & dev->ram_mask[bank];
addr = byte | (column << 1) | (row << dev->row_phys_shift[bank]);
ram[addr + dev->ram_phys_base[bank]] = val;
}
static void
recalc_mappings(void *priv)
{
scamp_t *dev = (scamp_t *) priv;
uint32_t virt_base = 0;
uint32_t old_virt_base;
uint8_t cur_rammap = dev->cfg_regs[CFG_RAMMAP] & 0xf;
int bank_nr = 0;
int phys_bank;
mem_set_mem_state_both((1 << 20), (16256 - 1024) * 1024, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
for (uint8_t c = 0; c < 2; c++)
mem_mapping_disable(&dev->ram_mapping[c]);
/* Once the BIOS programs the correct DRAM configuration, switch to regular
linear memory mapping */
if (cur_rammap == ram_configs[dev->ram_config].rammap) {
mem_mapping_set_handler(&ram_low_mapping,
mem_read_ram, mem_read_ramw, mem_read_raml,
mem_write_ram, mem_write_ramw, mem_write_raml);
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
if (mem_size > 1024)
mem_set_mem_state_both((1 << 20), (mem_size - 1024) << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_enable(&ram_high_mapping);
return;
} else {
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_read, NULL, NULL,
ram_mirrored_write, NULL, NULL);
mem_mapping_disable(&ram_low_mapping);
}
if (rammap[cur_rammap].bank[0] == BANK_NONE)
bank_nr = 1;
for (; bank_nr < 2; bank_nr++) {
old_virt_base = virt_base;
phys_bank = ram_configs[dev->ram_config].bank[bank_nr];
dev->ram_virt_base[bank_nr] = virt_base;
if (virt_base == 0) {
switch (rammap[cur_rammap].bank[bank_nr]) {
case BANK_NONE:
fatal(" Bank %i is empty!\n }\n}\n", bank_nr);
break;
case BANK_256K:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0x80000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
}
virt_base += (1 << 19);
dev->row_virt_shift[bank_nr] = 10;
break;
case BANK_256K_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
}
virt_base += (1 << 20);
dev->row_virt_shift[bank_nr] = 10;
break;
case BANK_1M:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x100000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]);
mem_set_mem_state_both((1 << 20), (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 21);
dev->row_virt_shift[bank_nr] = 11;
break;
case BANK_1M_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x300000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]);
mem_set_mem_state_both((1 << 20), (3 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 22);
dev->row_virt_shift[bank_nr] = 11;
break;
case BANK_4M:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0x700000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]);
mem_set_mem_state_both((1 << 20), (7 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 23);
dev->row_virt_shift[bank_nr] = 12;
break;
case BANK_4M_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&ram_low_mapping, 0, 0xa0000);
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[bank_nr]);
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], 0x100000, 0xf00000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr] + 0x100000]);
mem_set_mem_state_both((1 << 20), (15 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
} else {
switch (rammap[cur_rammap].bank[bank_nr]) {
case BANK_NONE:
break;
case BANK_256K:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x80000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 19), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 19);
dev->row_virt_shift[bank_nr] = 10;
break;
case BANK_256K_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x100000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 20);
dev->row_virt_shift[bank_nr] = 10;
break;
case BANK_1M:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x200000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 21), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 21);
dev->row_virt_shift[bank_nr] = 11;
break;
case BANK_1M_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x400000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 22), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 22);
dev->row_virt_shift[bank_nr] = 11;
break;
case BANK_4M:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x800000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 23), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 23);
dev->row_virt_shift[bank_nr] = 12;
break;
case BANK_4M_INTERLEAVED:
if (phys_bank != BANK_NONE) {
mem_mapping_set_addr(&dev->ram_mapping[bank_nr], virt_base, 0x1000000);
mem_mapping_set_exec(&dev->ram_mapping[bank_nr], &ram[dev->ram_phys_base[bank_nr]]);
mem_set_mem_state_both(virt_base, (1 << 24), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
virt_base += (1 << 24);
dev->row_virt_shift[bank_nr] = 12;
break;
default:
break;
}
}
switch (rammap[cur_rammap].bank[bank_nr]) {
case BANK_256K:
case BANK_1M:
case BANK_4M:
mem_mapping_set_handler(&dev->ram_mapping[bank_nr],
ram_mirrored_read, NULL, NULL,
ram_mirrored_write, NULL, NULL);
if (!old_virt_base)
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_read, NULL, NULL,
ram_mirrored_write, NULL, NULL);
break;
case BANK_256K_INTERLEAVED:
case BANK_1M_INTERLEAVED:
mem_mapping_set_handler(&dev->ram_mapping[bank_nr],
ram_mirrored_interleaved_read, NULL, NULL,
ram_mirrored_interleaved_write, NULL, NULL);
if (!old_virt_base)
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_interleaved_read, NULL, NULL,
ram_mirrored_interleaved_write, NULL, NULL);
break;
case BANK_4M_INTERLEAVED:
if (phys_bank == BANK_256K || phys_bank == BANK_256K_INTERLEAVED) {
mem_mapping_set_handler(&dev->ram_mapping[bank_nr],
ram_mirrored_256k_in_4mi_read, NULL, NULL,
ram_mirrored_256k_in_4mi_write, NULL, NULL);
if (!old_virt_base)
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_256k_in_4mi_read, NULL, NULL,
ram_mirrored_256k_in_4mi_write, NULL, NULL);
} else {
mem_mapping_set_handler(&dev->ram_mapping[bank_nr],
ram_mirrored_interleaved_read, NULL, NULL,
ram_mirrored_interleaved_write, NULL, NULL);
if (!old_virt_base)
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_interleaved_read, NULL, NULL,
ram_mirrored_interleaved_write, NULL, NULL);
}
break;
default:
break;
}
}
}
static void
recalc_sltptr(scamp_t *dev)
{
uint32_t sltptr = dev->cfg_regs[CFG_SLTPTR] << 16;
if (sltptr >= 0xa0000 && sltptr < 0x100000)
sltptr = 0x100000;
if (sltptr > 0xfe0000)
sltptr = 0xfe0000;
if (sltptr >= 0xa0000) {
mem_set_mem_state(0, 0xa0000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0x100000, sltptr - 0x100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(sltptr, 0x1000000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
} else {
mem_set_mem_state(0, sltptr, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(sltptr, 0xa0000 - sltptr, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state(0x100000, 0xf00000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
static uint8_t
scamp_ems_read(uint32_t addr, void *priv)
{
const ems_struct_t *ems = (ems_struct_t *) priv;
const scamp_t *dev = ems->parent;
int segment = ems->segment;
addr = (addr & 0x3fff) | dev->mappings[segment];
return ram[addr];
}
static void
scamp_ems_write(uint32_t addr, uint8_t val, void *priv)
{
const ems_struct_t *ems = (ems_struct_t *) priv;
const scamp_t *dev = ems->parent;
int segment = ems->segment;
addr = (addr & 0x3fff) | dev->mappings[segment];
ram[addr] = val;
}
static void
recalc_ems(scamp_t *dev)
{
const uint32_t ems_base[12] = {
0xc0000, 0xc4000, 0xc8000, 0xcc000,
0xd0000, 0xd4000, 0xd8000, 0xdc000,
0xe0000, 0xe4000, 0xe8000, 0xec000
};
uint32_t new_mappings[20];
uint16_t ems_enable;
for (int segment = 0; segment < 20; segment++)
new_mappings[segment] = 0xa0000 + segment * 0x4000;
if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB)
ems_enable = dev->cfg_regs[CFG_EMSEN2] | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 8);
else
ems_enable = 0;
for (int segment = 0; segment < 12; segment++) {
if (ems_enable & (1 << segment)) {
uint32_t phys_addr = dev->ems[segment] << 14;
/*If physical address is in remapped memory then adjust down to a0000-fffff range*/
if ((dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) && phys_addr >= (mem_size * 1024)
&& phys_addr < ((mem_size + 384) * 1024))
phys_addr = (phys_addr - mem_size * 1024) + 0xa0000;
new_mappings[(ems_base[segment] - 0xa0000) >> 14] = phys_addr;
}
}
for (int segment = 0; segment < 20; segment++) {
if (new_mappings[segment] != dev->mappings[segment]) {
dev->mappings[segment] = new_mappings[segment];
if (new_mappings[segment] < (mem_size * 1024)) {
mem_mapping_set_exec(&dev->ems_mappings[segment], ram + dev->mappings[segment]);
mem_mapping_enable(&dev->ems_mappings[segment]);
} else
mem_mapping_disable(&dev->ems_mappings[segment]);
}
}
}
static void
shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable)
{
if (ems_enable)
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
switch (state) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
default:
break;
}
flushmmucache_nopc();
}
static void
shadow_recalc(scamp_t *dev)
{
uint8_t abaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_ABAXS];
uint8_t caxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_CAXS];
uint8_t daxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_DAXS];
uint8_t feaxs = (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386) ? 0 : dev->cfg_regs[CFG_FEAXS];
uint32_t ems_enable;
if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB) {
if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSMAP) /*Axxx/Bxxx/Dxxx*/
ems_enable = (dev->cfg_regs[CFG_EMSEN2] & 0xf) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 4) | ((dev->cfg_regs[CFG_EMSEN2] & 0xf0) << 8);
else /*Cxxx/Dxxx/Exxx*/
ems_enable = (dev->cfg_regs[CFG_EMSEN2] << 8) | ((dev->cfg_regs[CFG_EMSEN1] & 0xf) << 16);
} else
ems_enable = 0;
/*Enabling remapping will disable all shadowing*/
if (dev->cfg_regs[CFG_RAMMAP] & RAMMAP_REMP386)
mem_remap_top(384);
shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00001);
shadow_control(0xa0000, 0x4000, abaxs & 3, ems_enable & 0x00002);
shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00004);
shadow_control(0xa8000, 0x4000, (abaxs >> 2) & 3, ems_enable & 0x00008);
shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00010);
shadow_control(0xb0000, 0x4000, (abaxs >> 4) & 3, ems_enable & 0x00020);
shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00040);
shadow_control(0xb8000, 0x4000, (abaxs >> 6) & 3, ems_enable & 0x00080);
shadow_control(0xc0000, 0x4000, caxs & 3, ems_enable & 0x00100);
shadow_control(0xc4000, 0x4000, (caxs >> 2) & 3, ems_enable & 0x00200);
shadow_control(0xc8000, 0x4000, (caxs >> 4) & 3, ems_enable & 0x00400);
shadow_control(0xcc000, 0x4000, (caxs >> 6) & 3, ems_enable & 0x00800);
shadow_control(0xd0000, 0x4000, daxs & 3, ems_enable & 0x01000);
shadow_control(0xd4000, 0x4000, (daxs >> 2) & 3, ems_enable & 0x02000);
shadow_control(0xd8000, 0x4000, (daxs >> 4) & 3, ems_enable & 0x04000);
shadow_control(0xdc000, 0x4000, (daxs >> 6) & 3, ems_enable & 0x08000);
shadow_control(0xe0000, 0x4000, feaxs & 3, ems_enable & 0x10000);
shadow_control(0xe4000, 0x4000, feaxs & 3, ems_enable & 0x20000);
shadow_control(0xe8000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x40000);
shadow_control(0xec000, 0x4000, (feaxs >> 2) & 3, ems_enable & 0x80000);
shadow_control(0xf0000, 0x8000, (feaxs >> 4) & 3, 0);
shadow_control(0xf8000, 0x8000, (feaxs >> 6) & 3, 0);
}
static void
scamp_write(uint16_t addr, uint8_t val, void *priv)
{
scamp_t *dev = (scamp_t *) priv;
switch (addr) {
case 0xe8:
dev->ems_index = val & 0x1f;
dev->ems_autoinc = val & 0x40;
break;
case 0xea:
if (dev->ems_index < 0x24) {
dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x300) | val;
recalc_ems(dev);
}
break;
case 0xeb:
if (dev->ems_index < 0x24) {
dev->ems[dev->ems_index] = (dev->ems[dev->ems_index] & 0x0ff) | ((val & 3) << 8);
recalc_ems(dev);
}
if (dev->ems_autoinc)
dev->ems_index = (dev->ems_index + 1) & 0x3f;
break;
case 0xec:
if (dev->cfg_enable)
dev->cfg_index = val;
break;
case 0xed:
if (dev->cfg_enable && (dev->cfg_index >= 0x02) && (dev->cfg_index <= 0x16)) {
dev->cfg_regs[dev->cfg_index] = val;
switch (dev->cfg_index) {
case CFG_SLTPTR:
recalc_sltptr(dev);
break;
case CFG_RAMMAP:
recalc_mappings(dev);
mem_mapping_disable(&ram_remapped_mapping);
shadow_recalc(dev);
break;
case CFG_EMSEN1:
case CFG_EMSEN2:
shadow_recalc(dev);
recalc_ems(dev);
break;
case CFG_ABAXS:
case CFG_CAXS:
case CFG_DAXS:
case CFG_FEAXS:
shadow_recalc(dev);
break;
default:
break;
}
}
break;
case 0xee:
if (dev->cfg_enable && mem_a20_alt) {
dev->port_92->reg &= 0xfd;
mem_a20_alt = 0;
mem_a20_recalc();
}
break;
default:
break;
}
}
static uint8_t
scamp_read(uint16_t addr, void *priv)
{
scamp_t *dev = (scamp_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0xe8:
ret = dev->ems_index | dev->ems_autoinc;
break;
case 0xea:
if (dev->ems_index < 0x24)
ret = dev->ems[dev->ems_index] & 0xff;
break;
case 0xeb:
if (dev->ems_index < 0x24)
ret = (dev->ems[dev->ems_index] >> 8) | 0xfc;
if (dev->ems_autoinc)
dev->ems_index = (dev->ems_index + 1) & 0x3f;
break;
case 0xed:
if (dev->cfg_enable && (dev->cfg_index >= 0x00) && (dev->cfg_index <= 0x16))
ret = (dev->cfg_regs[dev->cfg_index]);
break;
case 0xee:
if (!mem_a20_alt) {
dev->port_92->reg |= 0x02;
mem_a20_alt = 1;
mem_a20_recalc();
}
break;
case 0xef:
softresetx86();
cpu_set_edx();
break;
default:
break;
}
return ret;
}
static void
scamp_close(void *priv)
{
scamp_t *dev = (scamp_t *) priv;
free(dev);
}
static void *
scamp_init(UNUSED(const device_t *info))
{
uint32_t addr;
scamp_t *dev = (scamp_t *) malloc(sizeof(scamp_t));
memset(dev, 0x00, sizeof(scamp_t));
dev->cfg_regs[CFG_ID] = ID_VL82C311;
dev->cfg_enable = 1;
io_sethandler(0x00e8, 0x0001,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
io_sethandler(0x00ea, 0x0006,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
io_sethandler(0x00f4, 0x0002,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
io_sethandler(0x00f9, 0x0001,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
io_sethandler(0x00fb, 0x0001,
scamp_read, NULL, NULL, scamp_write, NULL, NULL, dev);
dev->ram_config = 0;
/* Find best fit configuration for the requested memory size */
for (uint8_t c = 0; c < NR_ELEMS(ram_configs); c++) {
if (mem_size < ram_configs[c].size_kb)
break;
dev->ram_config = c;
}
mem_mapping_set_p(&ram_low_mapping, (void *) &dev->ram_struct[0]);
mem_mapping_set_handler(&ram_low_mapping,
ram_mirrored_read, NULL, NULL,
ram_mirrored_write, NULL, NULL);
mem_mapping_disable(&ram_high_mapping);
mem_mapping_set_addr(&ram_mid_mapping, 0xf0000, 0x10000);
mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000);
addr = 0;
for (uint8_t c = 0; c < 2; c++) {
dev->ram_struct[c].parent = dev;
dev->ram_struct[c].bank = c;
mem_mapping_add(&dev->ram_mapping[c], 0, 0,
ram_mirrored_read, NULL, NULL,
ram_mirrored_write, NULL, NULL,
&ram[addr], MEM_MAPPING_INTERNAL, (void *) &dev->ram_struct[c]);
mem_mapping_disable(&dev->ram_mapping[c]);
dev->ram_phys_base[c] = addr;
switch (ram_configs[dev->ram_config].bank[c]) {
case BANK_NONE:
dev->ram_mask[c] = 0;
dev->ram_interleaved[c] = 0;
break;
case BANK_256K:
addr += (1 << 19);
dev->ram_mask[c] = 0x1ff;
dev->row_phys_shift[c] = 10;
dev->ram_interleaved[c] = 0;
break;
case BANK_256K_INTERLEAVED:
addr += (1 << 20);
dev->ram_mask[c] = 0x1ff;
dev->row_phys_shift[c] = 10;
dev->ibank_shift[c] = 19;
dev->ram_interleaved[c] = 1;
break;
case BANK_1M:
addr += (1 << 21);
dev->ram_mask[c] = 0x3ff;
dev->row_phys_shift[c] = 11;
dev->ram_interleaved[c] = 0;
break;
case BANK_1M_INTERLEAVED:
addr += (1 << 22);
dev->ram_mask[c] = 0x3ff;
dev->row_phys_shift[c] = 11;
dev->ibank_shift[c] = 21;
dev->ram_interleaved[c] = 1;
break;
case BANK_4M:
addr += (1 << 23);
dev->ram_mask[c] = 0x7ff;
dev->row_phys_shift[c] = 12;
dev->ram_interleaved[c] = 0;
break;
case BANK_4M_INTERLEAVED:
addr += (1 << 24);
dev->ram_mask[c] = 0x7ff;
dev->row_phys_shift[c] = 12;
dev->ibank_shift[c] = 23;
dev->ram_interleaved[c] = 1;
break;
default:
break;
}
}
mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
for (uint8_t c = 0; c < 20; c++) {
dev->ems_struct[c].parent = dev;
dev->ems_struct[c].segment = c;
mem_mapping_add(&dev->ems_mappings[c],
0xa0000 + c * 0x4000, 0x4000,
scamp_ems_read, NULL, NULL,
scamp_ems_write, NULL, NULL,
ram + 0xa0000 + c * 0x4000, MEM_MAPPING_INTERNAL, (void *) &dev->ems_struct[c]);
dev->mappings[c] = 0xa0000 + c * 0x4000;
}
dev->port_92 = device_add(&port_92_device);
return dev;
}
const device_t vlsi_scamp_device = {
.name = "VLSI SCAMP",
.internal_name = "vlsi_scamp",
.flags = 0,
.local = 0,
.init = scamp_init,
.close = scamp_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/scamp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,377 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SiS 5581 Host to PCI bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/apm.h>
#include <86box/ddma.h>
#include <86box/acpi.h>
#include <86box/smbus.h>
#include <86box/sis_55xx.h>
#include <86box/chipset.h>
#include <86box/usb.h>
#ifdef ENABLE_SIS_5581_HOST_TO_PCI_LOG
int sis_5581_host_to_pci_do_log = ENABLE_SIS_5581_HOST_TO_PCI_LOG;
static void
sis_5581_host_to_pci_log(const char *fmt, ...)
{
va_list ap;
if (sis_5581_host_to_pci_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sis_5581_host_to_pci_log(fmt, ...)
#endif
typedef struct {
uint8_t installed;
uint8_t code;
uint32_t phys_size;
} ram_bank_t;
typedef struct sis_5581_io_trap_t {
void *priv;
void *trap;
uint8_t flags, mask;
uint8_t *sts_reg, sts_mask;
uint16_t addr;
} sis_5581_io_trap_t;
typedef struct sis_5581_host_to_pci_t {
uint8_t pci_conf[256];
uint8_t states[7];
ram_bank_t ram_banks[3];
sis_5581_io_trap_t io_traps[10];
sis_55xx_common_t *sis;
smram_t *smram;
} sis_5581_host_to_pci_t;
static uint8_t bank_codes[7] = { 0x00, 0x20, 0x24, 0x22, 0x26, 0x2a, 0x2b };
static uint32_t bank_sizes[7] = { 0x00800000, /* 8 MB */
0x01000000, /* 16 MB */
0x02000000, /* 32 MB */
0x04000000, /* 64 MB */
0x08000000, /* 128 MB */
0x10000000, /* 256 MB */
0x20000000 }; /* 512 MB */
static void
sis_5581_shadow_recalc(sis_5581_host_to_pci_t *dev)
{
int state;
uint32_t base;
for (uint8_t i = 0x70; i <= 0x76; i++) {
if (i == 0x76) {
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(0xf0000, 0x10000, state);
sis_5581_host_to_pci_log("000F0000-000FFFFF\n");
}
} else {
base = ((i & 0x07) << 15) + 0xc0000;
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0xa0) {
state = (dev->pci_conf[i] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x4000, state);
sis_5581_host_to_pci_log("%08X-%08X\n", base, base + 0x3fff);
}
if ((dev->states[i & 0x0f] ^ dev->pci_conf[i]) & 0x0a) {
state = (dev->pci_conf[i] & 0x08) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
state |= (dev->pci_conf[i] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state_both(base + 0x4000, 0x4000, state);
sis_5581_host_to_pci_log("%08X-%08X\n", base + 0x4000, base + 0x7fff);
}
}
dev->states[i & 0x0f] = dev->pci_conf[i];
}
flushmmucache_nopc();
}
static void
sis_5581_trap_io(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val),
void *priv)
{
sis_5581_io_trap_t *trap = (sis_5581_io_trap_t *) priv;
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) trap->priv;
trap->sts_reg[0x04] |= trap->sts_mask;
if (trap->sts_reg[0x00] & trap->sts_mask)
acpi_sis5582_pmu_event(dev->sis->acpi);
}
static void
sis_5581_trap_io_mask(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
sis_5581_io_trap_t *trap = (sis_5581_io_trap_t *) priv;
if ((addr & trap->mask) == (trap->addr & trap->mask))
sis_5581_trap_io(size, addr, write, val, priv);
}
static void
sis_5581_trap_update_devctl(sis_5581_host_to_pci_t *dev, uint8_t trap_id, uint8_t enable,
uint8_t flags, uint8_t mask, uint8_t *sts_reg, uint8_t sts_mask,
uint16_t addr, uint16_t size)
{
sis_5581_io_trap_t *trap = &dev->io_traps[trap_id];
/* Set up Device I/O traps dynamically. */
if (enable && !trap->trap) {
trap->priv = (void *) dev;
trap->flags = flags;
trap->mask = mask;
trap->addr = addr;
if (flags & 0x08)
trap->trap = io_trap_add(sis_5581_trap_io_mask, trap);
else
trap->trap = io_trap_add(sis_5581_trap_io, trap);
trap->sts_reg = sts_reg;
trap->sts_mask = sts_mask;
}
/* Remap I/O trap. */
io_trap_remap(trap->trap, enable, addr, size);
}
static void
sis_5581_trap_update(void *priv)
{
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) priv;
uint8_t trap_id = 0;
uint8_t *fregs = dev->pci_conf;
uint16_t temp;
uint8_t mask;
uint8_t on;
on = fregs[0x9a];
temp = ((fregs[0x96] & 0x02) | (fregs[0x97] << 2)) & 0x03ff;
mask = ~((1 << ((fregs[0x96] >> 3) & 0x07)) - 1);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x40, 0x08, mask, &(fregs[0x9c]), 0x40, temp, 0x80);
temp = fregs[0x98] | (fregs[0x99] << 8);
mask = 0xff;
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x20, 0x08, mask, &(fregs[0x9c]), 0x20, temp, 0x80);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x00, 0xff, &(fregs[0x9c]), 0x10, 0x378, 0x08);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x10, 0x00, 0xff, &(fregs[0x9c]), 0x10, 0x278, 0x08);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x08, 0x00, 0xff, &(fregs[0x9c]), 0x08, 0x3f8, 0x08);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x04, 0x00, 0xff, &(fregs[0x9c]), 0x04, 0x2f8, 0x08);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x02, 0x00, 0xff, &(fregs[0x9c]), 0x02, 0x1f0, 0x08);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x01, 0x00, 0xff, &(fregs[0x9c]), 0x01, 0x170, 0x08);
on = fregs[0x9b];
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x08, 0x00, 0xff, &(fregs[0x9d]), 0x08, 0x064, 0x01);
sis_5581_trap_update_devctl(dev, trap_id++,
on & 0x08, 0x00, 0xff, &(fregs[0x9d]), 0x08, 0x060, 0x01);
}
static void
sis_5581_smram_recalc(sis_5581_host_to_pci_t *dev)
{
smram_disable_all();
switch (dev->pci_conf[0xa3] >> 6) {
case 0:
smram_enable(dev->smram, 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 1:
smram_enable(dev->smram, 0x000e0000, 0x000a0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 2:
smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0xa3] & 0x10, 1);
break;
case 3:
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0xa3] & 0x10, 1);
break;
default:
break;
}
flushmmucache();
}
void
sis_5581_host_to_pci_write(int addr, uint8_t val, void *priv)
{
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) priv;
sis_5581_host_to_pci_log("SiS 5581 H2P: [W] dev->pci_conf[%02X] = %02X\n", addr, val);
switch (addr) {
default:
break;
case 0x04: /* Command - Low Byte */
dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xfc) | (val & 0x03);
break;
case 0x05: /* Command - High Byte */
dev->pci_conf[addr] = val & 0x02;
break;
case 0x07: /* Status - High Byte */
dev->pci_conf[addr] &= ~(val & 0xb8);
break;
case 0x0d: /* Master latency timer */
case 0x50:
case 0x54:
case 0x56 ... 0x57:
case 0x59:
dev->pci_conf[addr] = val;
break;
case 0x51:
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates();
break;
case 0x52:
dev->pci_conf[addr] = val & 0xeb;
break;
case 0x53:
case 0x55:
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x58:
dev->pci_conf[addr] = val & 0xfc;
break;
case 0x5a:
dev->pci_conf[addr] = val & 0x03;
break;
case 0x60 ... 0x62:
dev->pci_conf[addr] = dev->ram_banks[addr & 0x0f].code | 0xc0;
break;
case 0x63:
dev->pci_conf[addr] = dev->ram_banks[0].installed |
(dev->ram_banks[1].installed << 1) |
(dev->ram_banks[2].installed << 2);
break;
case 0x70 ... 0x75:
dev->pci_conf[addr] = val & 0xee;
sis_5581_shadow_recalc(dev);
break;
case 0x76:
dev->pci_conf[addr] = val & 0xe8;
sis_5581_shadow_recalc(dev);
break;
case 0x77: /* Characteristics of non-cacheable area */
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x78: /* Allocation of Non-Cacheable area #1 */
case 0x79: /* NCA1REG2 */
case 0x7a: /* Allocation of Non-Cacheable area #2 */
case 0x7b: /* NCA2REG2 */
dev->pci_conf[addr] = val;
break;
case 0x80: /* PCI master characteristics */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x81:
dev->pci_conf[addr] = val & 0xde;
break;
case 0x82:
dev->pci_conf[addr] = val;
break;
case 0x83: /* CPU to PCI characteristics */
dev->pci_conf[addr] = val;
/* TODO: Implement Fast A20 and Fast reset stuff on the KBC already! */
break;
case 0x84 ... 0x86:
case 0x88 ... 0x8b:
dev->pci_conf[addr] = val;
break;
case 0x87: /* Miscellanea */
dev->pci_conf[addr] = val & 0xfe;
break;
case 0x8c ... 0x92:
case 0x9e ... 0xa2:
dev->pci_conf[addr] = val;
break;
case 0x93:
dev->pci_conf[addr] = val;
if (val & 0x02) {
dev->pci_conf[0x9d] |= 0x01;
if (dev->pci_conf[0x9b] & 0x01)
acpi_sis5582_pmu_event(dev->sis->acpi);
}
break;
case 0x94:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x95:
dev->pci_conf[addr] = val & 0xfb;
break;
case 0x96:
dev->pci_conf[addr] = val & 0xfb;
sis_5581_trap_update(dev);
break;
case 0x97 ... 0x9b:
dev->pci_conf[addr] = val;
sis_5581_trap_update(dev);
break;
case 0x9c ... 0x9d:
dev->pci_conf[addr] &= ~val;
break;
case 0xa3:
dev->pci_conf[addr] = val;
sis_5581_smram_recalc(dev);
break;
}
}
uint8_t
sis_5581_host_to_pci_read(int addr, void *priv)
{
const sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
sis_5581_host_to_pci_log("SiS 5581 H2P: [R] dev->pci_conf[%02X] = %02X\n", addr, ret);
return ret;
}
static void
sis_5581_host_to_pci_reset(void *priv)
{
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) priv;
dev->pci_conf[0x00] = 0x39;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x97;
dev->pci_conf[0x03] = 0x55;
dev->pci_conf[0x04] = 0x05;
dev->pci_conf[0x05] = dev->pci_conf[0x06] = 0x00;
dev->pci_conf[0x07] = 0x02;
dev->pci_conf[0x08] = 0x02;
dev->pci_conf[0x09] = dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0xff;
dev->pci_conf[0x0e] = dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x50] = dev->pci_conf[0x51] = 0x00;
dev->pci_conf[0x52] = 0x00;
dev->pci_conf[0x53] = 0x38;
dev->pci_conf[0x54] = 0x54;
dev->pci_conf[0x55] = 0x00;
dev->pci_conf[0x56] = 0x80;
dev->pci_conf[0x57] = dev->pci_conf[0x58] = 0x00;
dev->pci_conf[0x59] = dev->pci_conf[0x5a] = 0x00;
dev->pci_conf[0x60] = dev->pci_conf[0x61] = 0x00;
dev->pci_conf[0x62] = 0x00;
dev->pci_conf[0x63] = 0xff;
dev->pci_conf[0x70] = dev->pci_conf[0x71] = 0x00;
dev->pci_conf[0x72] = dev->pci_conf[0x73] = 0x00;
dev->pci_conf[0x74] = dev->pci_conf[0x75] = 0x00;
dev->pci_conf[0x76] = dev->pci_conf[0x77] = 0x00;
dev->pci_conf[0x78] = dev->pci_conf[0x79] = 0x00;
dev->pci_conf[0x7a] = dev->pci_conf[0x7b] = 0x00;
dev->pci_conf[0x80] = dev->pci_conf[0x81] = 0x00;
dev->pci_conf[0x82] = dev->pci_conf[0x83] = 0x00;
dev->pci_conf[0x84] = dev->pci_conf[0x85] = 0x00;
dev->pci_conf[0x86] = dev->pci_conf[0x87] = 0x00;
dev->pci_conf[0x88] = dev->pci_conf[0x89] = 0x00;
dev->pci_conf[0x8a] = dev->pci_conf[0x8b] = 0x00;
dev->pci_conf[0x90] = dev->pci_conf[0x91] = 0x00;
dev->pci_conf[0x92] = dev->pci_conf[0x93] = 0x00;
dev->pci_conf[0x94] = dev->pci_conf[0x95] = 0x00;
dev->pci_conf[0x96] = dev->pci_conf[0x97] = 0x00;
dev->pci_conf[0x98] = dev->pci_conf[0x99] = 0x00;
dev->pci_conf[0x9a] = dev->pci_conf[0x9b] = 0x00;
dev->pci_conf[0x9c] = dev->pci_conf[0x9d] = 0x00;
dev->pci_conf[0x9e] = dev->pci_conf[0x9f] = 0xff;
dev->pci_conf[0xa0] = 0xff;
dev->pci_conf[0xa1] = 0x00;
dev->pci_conf[0xa2] = 0xff;
dev->pci_conf[0xa3] = 0x00;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
sis_5581_shadow_recalc(dev);
sis_5581_trap_update(dev);
sis_5581_smram_recalc(dev);
}
static void
sis_5581_host_to_pci_close(void *priv)
{
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
sis_5581_host_to_pci_init(UNUSED(const device_t *info))
{
sis_5581_host_to_pci_t *dev = (sis_5581_host_to_pci_t *) calloc(1, sizeof(sis_5581_host_to_pci_t));
uint32_t total_mem = mem_size << 10;
ram_bank_t *rb;
dev->sis = device_get_common_priv();
/* Calculate the physical RAM banks. */
for (uint8_t i = 0; i < 3; i++) {
rb = &(dev->ram_banks[i]);
uint32_t size = 0x00000000;
uint8_t index = 0;
for (int8_t j = 6; j >= 0; j--) {
uint32_t *bs = &(bank_sizes[j]);
if (*bs <= total_mem) {
size = *bs;
index = j;
break;
}
}
if (size != 0x00000000) {
rb->installed = 1;
rb->code = bank_codes[index];
rb->phys_size = size;
total_mem -= size;
} else
rb->installed = 0;
}
/* SMRAM */
dev->smram = smram_add();
sis_5581_host_to_pci_reset(dev);
return dev;
}
const device_t sis_5581_h2p_device = {
.name = "SiS 5581 Host to PCI bridge",
.internal_name = "sis_5581_host_to_pci",
.flags = DEVICE_PCI,
.local = 0x00,
.init = sis_5581_host_to_pci_init,
.close = sis_5581_host_to_pci_close,
.reset = sis_5581_host_to_pci_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/sis_5581_h2p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,808 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 8886xx PCI to ISA Bridge .
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
/*
UMC 8886xx Configuration Registers
Note: PMU functionality is quite basic. There may be Enable/Disable bits, IRQ/SMI picks and it also
required for 386_common.c to get patched in order to function properly.
Warning: Register documentation may be inaccurate!
UMC 8886xx:
(F: Has No Internal IDE / AF or BF: Has Internal IDE)
Function 0 Register 43:
Bits 7-4 PCI IRQ for INTB
Bits 3-0 PCI IRQ for INTA
Function 0 Register 44:
Bits 7-4 PCI IRQ for INTD
Bits 3-0 PCI IRQ for INTC
Function 0 Register 46 (corrected by Miran Grca):
Bit 7: IRQ SMI Request (1: IRQ 15, 0: IRQ 10)
Bit 6: PMU Trigger(1: By IRQ/0: By SMI)
Function 0 Register 56:
Bit 1-0 ISA Bus Speed
0 0 PCICLK/3
0 1 PCICLK/4
1 0 PCICLK/2
Function 0 Register A2 - non-software SMI# status register
(documented by Miran Grca):
Bit 4: I set, graphics card goes into sleep mode
This register is most likely R/WC
Function 0 Register A3 (added more details by Miran Grca):
Bit 7: Unlock SMM
Bit 6: Software SMI trigger (also doubles as software SMI# status register,
cleared by writing a 0 to it - see the handler used by Phoenix BIOS'es):
If Function 0 Register 46 Bit 6 is set, it raises the specified IRQ (15
or 10) instead.
Function 0 Register A4:
Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
Function 1 Register 4: (UMC 8886AF/8886BF Only!)
Bit 0: Enable Internal IDE
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC_8886_LOG
int umc_8886_do_log = ENABLE_UMC_8886_LOG;
static void
umc_8886_log(const char *fmt, ...)
{
va_list ap;
if (umc_8886_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define umc_8886_log(fmt, ...)
#endif
typedef struct umc_8886_t {
uint8_t max_func; /* Last function number */
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
uint16_t ide_id; /* IDE Revision */
int has_ide; /* Check if Southbridge Revision is F, AF, or BF */
} umc_8886_t;
static void
umc_8886_ide_handler(umc_8886_t *dev)
{
ide_pri_disable();
ide_sec_disable();
if (dev->pci_conf_sb[1][0x04] & 0x01) {
if (dev->pci_conf_sb[1][0x40] & 0x80)
ide_pri_enable();
if (dev->pci_conf_sb[1][0x40] & 0x40)
ide_sec_enable();
}
}
static void
umc_8886_bus_recalc(umc_8886_t *dev)
{
switch (dev->pci_conf_sb[0x00][0xa4] & 0x03) {
case 0x00:
cpu_set_pci_speed(cpu_busspeed / 2);
break;
case 0x01:
cpu_set_pci_speed(cpu_busspeed);
break;
case 0x02:
cpu_set_pci_speed((cpu_busspeed * 2) / 3);
break;
}
switch (dev->pci_conf_sb[0x00][0x56] & 0x03) {
default:
break;
case 0x00:
cpu_set_isa_pci_div(3);
break;
case 0x01:
cpu_set_isa_pci_div(4);
break;
case 0x02:
cpu_set_isa_pci_div(2);
break;
}
}
static void
umc_8886_write(int func, int addr, uint8_t val, void *priv)
{
umc_8886_t *dev = (umc_8886_t *) priv;
int irq_routing;
if (func <= dev->max_func)
switch (func) {
case 0: /* PCI to ISA Bridge */
umc_8886_log("UM8886: dev->regs[%02x] = %02x POST %02x\n", addr, val, inb(0x80));
switch (addr) {
case 0x04 ... 0x05:
case 0x0c ... 0x0d:
case 0x40 ... 0x42:
case 0x45:
case 0x50 ... 0x55:
case 0x57:
case 0x70 ... 0x76:
case 0x80 ... 0x82:
case 0x90 ... 0x92:
case 0xa0 ... 0xa1:
case 0xa5 ... 0xa8:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x07:
dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
break;
case 0x43:
dev->pci_conf_sb[func][addr] = val;
irq_routing = (dev->pci_conf_sb[func][0x46] & 0x01) ? (val >> 8) :
PCI_IRQ_DISABLED;
pci_set_irq_routing(PCI_INTA, irq_routing);
irq_routing = (dev->pci_conf_sb[func][0x46] & 0x02) ? (val & 0x0f) :
PCI_IRQ_DISABLED;
pci_set_irq_routing(PCI_INTB, irq_routing);
break;
case 0x44:
dev->pci_conf_sb[func][addr] = val;
irq_routing = (dev->pci_conf_sb[func][0x46] & 0x04) ? (val >> 8) :
PCI_IRQ_DISABLED;
pci_set_irq_routing(PCI_INTC, irq_routing);
irq_routing = (dev->pci_conf_sb[func][0x46] & 0x08) ? (val & 0x0f) :
PCI_IRQ_DISABLED;
pci_set_irq_routing(PCI_INTD, irq_routing);
break;
case 0x46: /* Bits 3-0 = 0 = IRQ disabled, 1 = IRQ enabled. */
case 0x47: /* Bits 3-0 = 0 = IRQ edge-triggered, 1 = IRQ level-triggered. */
/* Bit 6 seems to be the IRQ/SMI# toggle, 1 = IRQ, 0 = SMI#. */
dev->pci_conf_sb[func][addr] = val;
break;
case 0x56:
dev->pci_conf_sb[func][addr] = val;
umc_8886_bus_recalc(dev);
break;
case 0xa2:
dev->pci_conf_sb[func][addr] &= ~val;
break;
case 0xa3:
/* SMI Provocation (Bit 7 Enable SMM + Bit 6 Software SMI) */
if (((val & 0xc0) == 0xc0) && !(dev->pci_conf_sb[0][0xa3] & 0x40)) {
if (dev->pci_conf_sb[0][0x46] & 0x40)
picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10));
else
smi_raise();
}
dev->pci_conf_sb[func][addr] = val;
break;
case 0xa4:
dev->pci_conf_sb[func][addr] = val;
umc_8886_bus_recalc(dev);
break;
default:
break;
}
break;
case 1: /* IDE Controller */
umc_8886_log("UM8886-IDE: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80));
switch (addr) {
case 0x04:
dev->pci_conf_sb[func][addr] = val;
if (dev->ide_id == 0x673a)
umc_8886_ide_handler(dev);
break;
case 0x07:
dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
break;
case 0x3c:
case 0x41 ... 0x4b:
case 0x54 ... 0x59:
if (dev->ide_id == 0x673a)
dev->pci_conf_sb[func][addr] = val;
break;
case 0x40:
if (dev->ide_id == 0x673a) {
dev->pci_conf_sb[func][addr] = val;
umc_8886_ide_handler(dev);
}
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
umc_8886_read(int func, int addr, void *priv)
{
const umc_8886_t *dev = (umc_8886_t *) priv;
uint8_t ret = 0xff;
if (func <= dev->max_func)
ret = dev->pci_conf_sb[func][addr];
return ret;
}
static void
umc_8886_reset(void *priv)
{
umc_8886_t *dev = (umc_8886_t *) priv;
memset(dev->pci_conf_sb[0], 0x00, sizeof(dev->pci_conf_sb[0]));
memset(dev->pci_conf_sb[1], 0x00, sizeof(dev->pci_conf_sb[1]));
dev->pci_conf_sb[0][0x00] = 0x60; /* UMC */
dev->pci_conf_sb[0][0x01] = 0x10;
dev->pci_conf_sb[0][0x02] = (dev->sb_id & 0xff); /* 8886xx */
dev->pci_conf_sb[0][0x03] = ((dev->sb_id >> 8) & 0xff);
dev->pci_conf_sb[0][0x04] = 0x0f;
dev->pci_conf_sb[0][0x07] = 0x02;
dev->pci_conf_sb[0][0x08] = 0x0e;
dev->pci_conf_sb[0][0x09] = 0x00;
dev->pci_conf_sb[0][0x0a] = 0x01;
dev->pci_conf_sb[0][0x0b] = 0x06;
dev->pci_conf_sb[0][0x40] = 0x01;
dev->pci_conf_sb[0][0x41] = 0x06;
dev->pci_conf_sb[0][0x42] = 0x08;
dev->pci_conf_sb[0][0x43] = 0x00;
dev->pci_conf_sb[0][0x44] = 0x00;
dev->pci_conf_sb[0][0x45] = 0x04;
dev->pci_conf_sb[0][0x46] = 0x00;
dev->pci_conf_sb[0][0x47] = 0x40;
dev->pci_conf_sb[0][0x50] = 0x01;
dev->pci_conf_sb[0][0x51] = 0x03;
dev->pci_conf_sb[0][0x56] = dev->pci_conf_sb[0][0x57] = 0x00;
dev->pci_conf_sb[0][0x70] = dev->pci_conf_sb[0][0x71] = 0x00;
dev->pci_conf_sb[0][0x72] = dev->pci_conf_sb[0][0x73] = 0x00;
dev->pci_conf_sb[0][0x74] = dev->pci_conf_sb[0][0x76] = 0x00;
dev->pci_conf_sb[0][0x82] = 0x00;
dev->pci_conf_sb[0][0x90] = dev->pci_conf_sb[0][0x91] = 0x00;
dev->pci_conf_sb[0][0xa0] = dev->pci_conf_sb[0][0xa2] = 0x00;
dev->pci_conf_sb[0][0xa4] = 0x00;
dev->pci_conf_sb[0][0xa8] = 0x20;
if (dev->has_ide) {
dev->pci_conf_sb[1][0x00] = 0x60; /* UMC */
dev->pci_conf_sb[1][0x01] = 0x10;
dev->pci_conf_sb[1][0x02] = (dev->ide_id & 0xff); /* 8886xx IDE */
dev->pci_conf_sb[1][0x03] = ((dev->ide_id >> 8) & 0xff);
dev->pci_conf_sb[1][0x04] = 0x05; /* Start with Internal IDE Enabled */
dev->pci_conf_sb[1][0x08] = 0x10;
dev->pci_conf_sb[1][0x09] = 0x8f;
dev->pci_conf_sb[1][0x0a] = dev->pci_conf_sb[1][0x0b] = 0x01;
dev->pci_conf_sb[1][0x10] = 0xf1;
dev->pci_conf_sb[1][0x11] = 0x01;
dev->pci_conf_sb[1][0x14] = 0xf5;
dev->pci_conf_sb[1][0x15] = 0x03;
dev->pci_conf_sb[1][0x18] = 0x71;
dev->pci_conf_sb[1][0x19] = 0x01;
dev->pci_conf_sb[1][0x1c] = 0x75;
dev->pci_conf_sb[1][0x1d] = 0x03;
dev->pci_conf_sb[1][0x20] = 0x01;
dev->pci_conf_sb[1][0x21] = 0x10;
if (dev->ide_id == 0x673a) {
dev->pci_conf_sb[1][0x40] = 0xc0;
dev->pci_conf_sb[1][0x41] = 0x00;
dev->pci_conf_sb[1][0x42] = dev->pci_conf_sb[1][0x43] = 0x00;
dev->pci_conf_sb[1][0x44] = dev->pci_conf_sb[1][0x45] = 0x00;
dev->pci_conf_sb[1][0x46] = dev->pci_conf_sb[1][0x47] = 0x00;
dev->pci_conf_sb[1][0x48] = dev->pci_conf_sb[1][0x49] = 0x00;
dev->pci_conf_sb[1][0x4a] = dev->pci_conf_sb[1][0x4b] = 0x00;
dev->pci_conf_sb[1][0x54] = dev->pci_conf_sb[1][0x55] = 0x00;
dev->pci_conf_sb[1][0x56] = dev->pci_conf_sb[1][0x57] = 0x00;
dev->pci_conf_sb[1][0x58] = dev->pci_conf_sb[1][0x59] = 0x00;
umc_8886_ide_handler(dev);
picintc(1 << 14);
picintc(1 << 15);
}
}
for (uint8_t i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
umc_8886_bus_recalc(dev);
}
static void
umc_8886_close(void *priv)
{
umc_8886_t *dev = (umc_8886_t *) priv;
free(dev);
}
static void *
umc_8886_init(const device_t *info)
{
umc_8886_t *dev = (umc_8886_t *) malloc(sizeof(umc_8886_t));
memset(dev, 0, sizeof(umc_8886_t));
/* Device 12: UMC 8886xx */
pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev, &dev->pci_slot);
/* Get the Southbridge Revision */
dev->sb_id = info->local & 0xffff;
/* IDE Revision */
dev->ide_id = info->local >> 16;
dev->has_ide = (dev->ide_id != 0x0000);
dev->max_func = 0;
/* Add IDE if this is the UM8886AF or UM8886BF. */
if (dev->ide_id == 0x673a) {
/* UM8886BF */
device_add(&ide_pci_2ch_device);
dev->max_func = 1;
} else if (dev->ide_id == 0x1001) {
/* UM8886AF */
device_add(&ide_um8673f_device);
}
umc_8886_reset(dev);
return dev;
}
const device_t umc_8886f_device = {
.name = "UMC 8886F",
.internal_name = "umc_8886f",
.flags = DEVICE_PCI,
.local = 0x00008886,
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t umc_8886af_device = {
.name = "UMC 8886AF",
.internal_name = "umc_8886af",
.flags = DEVICE_PCI,
.local = 0x1001886a,
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t umc_8886bf_device = {
.name = "UMC 8886BF",
.internal_name = "umc_8886bf",
.flags = DEVICE_PCI,
.local = 0x673a888a,
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/umc_8886.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,779 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1489 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#define DEFINE_SHADOW_PROCEDURE (((dev->regs[0x14] & 0x10) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | \
((dev->regs[0x14] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
#define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
#ifdef ENABLE_ALI1489_LOG
int ali1489_do_log = ENABLE_ALI1489_LOG;
static void
ali1489_log(const char *fmt, ...)
{
va_list ap;
if (ali1489_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali1489_log(fmt, ...)
#endif
typedef struct ali1489_t {
uint8_t index;
uint8_t pci_slot;
uint8_t regs[256];
uint8_t pci_conf[256];
port_92_t *port_92;
smram_t *smram;
} ali1489_t;
static void
ali1489_shadow_recalc(ali1489_t *dev)
{
shadowbios = shadowbios_write = 0;
for (uint8_t i = 0; i < 8; i++) {
if (dev->regs[0x13] & (1 << i)) {
ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
0xc0000 + (i << 14), 0xc3fff + (i << 14),
!!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DEFINE_SHADOW_PROCEDURE);
} else {
ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xc0000 + (i << 14), 0xc3fff + (i << 14));
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, DISABLED_SHADOW);
}
}
for (uint8_t i = 0; i < 4; i++) {
if (dev->regs[0x14] & (1 << i)) {
ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
0xe0000 + (i << 15), 0xe7fff + (i << 15),
!!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DEFINE_SHADOW_PROCEDURE);
shadowbios |= !!(dev->regs[0x14] & 0x10);
shadowbios_write |= !!(dev->regs[0x14] & 0x20);
} else {
ali1489_log("%06Xh-%06Xh region shadow disabled\n", 0xe0000 + (i << 15), 0xe7fff + (i << 15));
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, DISABLED_SHADOW);
}
}
flushmmucache_nopc();
}
static void
ali1489_smram_recalc(ali1489_t *dev)
{
/* The datasheet documents SMM behavior quite terribly.
Everything were done according to the M1489 programming guide. */
smram_disable(dev->smram);
switch (dev->regs[0x19] & 0x30) {
case 0x10:
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, (dev->regs[0x19] & 0x08), 1);
break;
case 0x20:
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, (dev->regs[0x19] & 0x08), 1);
break;
case 0x30:
if ((dev->regs[0x35] & 0xc0) == 0x80)
smram_enable(dev->smram, 0x68000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
else
smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
break;
default:
break;
}
if ((dev->regs[0x19] & 0x31) == 0x11) {
/* If SMRAM is enabled and bit 0 is set, code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
}
}
static void
ali1489_defaults(ali1489_t *dev)
{
memset(dev->pci_conf, 0x00, 256);
memset(dev->regs, 0x00, 256);
/* PCI registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x89;
dev->pci_conf[0x03] = 0x14;
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x0b] = 0x06;
/* ISA registers */
dev->regs[0x01] = 0x0f;
dev->regs[0x02] = 0x0f;
dev->regs[0x10] = 0xf1;
dev->regs[0x11] = 0xff;
dev->regs[0x15] = 0x20;
dev->regs[0x16] = 0x30;
dev->regs[0x19] = 0x04;
dev->regs[0x21] = 0x72;
dev->regs[0x28] = 0x02;
dev->regs[0x2b] = 0xdb;
dev->regs[0x3c] = 0x03;
dev->regs[0x3d] = 0x01;
dev->regs[0x40] = 0x03;
ali1489_shadow_recalc(dev);
cpu_cache_int_enabled = 0;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
ali1489_smram_recalc(dev);
port_92_remove(dev->port_92);
picintc(1 << 10);
picintc(1 << 15);
nmi = 0;
smi_line = 0;
in_smm = 0;
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
}
static void
ali1489_write(uint16_t addr, uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
uint8_t old;
uint8_t irq;
const uint8_t irq_array[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 };
switch (addr) {
case 0x22:
dev->index = val;
break;
case 0x23:
/* Check if the configuration registers are unlocked */
if (dev->regs[0x03] == 0xc5) {
switch (dev->index) {
case 0x03: /* Lock Register */
case 0x10: /* DRAM Configuration Register I */
case 0x11: /* DRAM Configuration Register II */
case 0x12: /* ROM Function Register */
dev->regs[dev->index] = val;
break;
case 0x13: /* Shadow Region Register */
case 0x14: /* Shadow Control Register */
if (dev->index == 0x14)
dev->regs[dev->index] = (val & 0xbf);
else
dev->regs[dev->index] = val;
ali1489_shadow_recalc(dev);
ali1489_smram_recalc(dev);
break;
case 0x15: /* Cycle Check Point Control Register */
dev->regs[dev->index] = (val & 0xf1);
break;
case 0x16: /* Cache Control Register I */
dev->regs[dev->index] = val;
cpu_cache_int_enabled = (val & 0x01);
cpu_cache_ext_enabled = (val & 0x02);
cpu_update_waitstates();
break;
case 0x17: /* Cache Control Register II */
dev->regs[dev->index] = val;
break;
case 0x19: /* SMM Control Register */
dev->regs[dev->index] = val;
ali1489_smram_recalc(dev);
break;
case 0x1a: /* EDO DRAM Configuration Register */
case 0x1b: /* DRAM Timing Control Register */
dev->regs[dev->index] = val;
break;
case 0x1c: /* Memory Data Buffer Direction Control Register */
dev->regs[dev->index] = val & 0x1f;
break;
case 0x1e: /* Linear Wrapped Burst Order Mode Control Register */
dev->regs[dev->index] = (val & 0x40);
break;
case 0x20: /* CPU to PCI Buffer Control Register */
dev->regs[dev->index] = val;
break;
case 0x21: /* DEVSELJ Check Point Setting Register */
dev->regs[dev->index] = (val & 0xbb) | 0x04;
break;
case 0x22: /* PCI to CPU W/R Buffer Configuration Register */
dev->regs[dev->index] = (val & 0xfd);
break;
case 0x25: /* GP/MEM Address Definition Register I */
case 0x26: /* GP/MEM Address Definition Register II */
case 0x27: /* GP/MEM Address Definition Register III */
dev->regs[dev->index] = val;
break;
case 0x28: /* PCI Arbiter Control Register */
dev->regs[dev->index] = val & 0x3f;
break;
case 0x29: /* System Clock Register */
dev->regs[dev->index] = val;
port_92_remove(dev->port_92);
if (val & 0x10)
port_92_add(dev->port_92);
break;
case 0x2a: /* I/O Recovery Register */
dev->regs[dev->index] = val;
break;
case 0x2b: /* Turbo Function Register */
dev->regs[dev->index] = (val & 0xbf) | 0x40;
break;
case 0x30: /* Power Management Unit Control Register */
old = dev->regs[dev->index];
dev->regs[dev->index] = val;
if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) {
switch (dev->regs[0x35] & 0x30) {
case 0x00:
smi_raise();
break;
case 0x10:
nmi_raise();
break;
case 0x20:
picint(1 << 15);
break;
case 0x30:
picint(1 << 10);
break;
default:
break;
}
dev->regs[0x35] |= 0x0e;
} else if (!(val & 0x10))
dev->regs[0x35] &= ~0x0f;
break;
case 0x31: /* Mode Timer Monitoring Events Selection Register I */
case 0x32: /* Mode Timer Monitoring Events Selection Register II */
case 0x33: /* SMI Triggered Events Selection Register I */
case 0x34: /* SMI Triggered Events Selection Register II */
dev->regs[dev->index] = val;
break;
case 0x35: /* SMI Status Register */
dev->regs[dev->index] = (dev->regs[dev->index] & 0x0f) | (val & 0xf0);
break;
case 0x36: /* IRQ Channel Group Selected Control Register I */
dev->regs[dev->index] = (val & 0xe5);
break;
case 0x37: /* IRQ Channel Group Selected Control Register II */
dev->regs[dev->index] = (val & 0xef);
break;
case 0x38: /* DRQ Channel Selected Control Register */
case 0x39: /* Mode Timer Setting Register */
case 0x3a: /* Input_device Timer Setting Register */
case 0x3b: /* GP/MEM Timer Setting Register */
case 0x3c: /* LED Flash Control Register */
dev->regs[dev->index] = val;
break;
case 0x3d: /* Miscellaneous Register I */
dev->regs[dev->index] = (val & 0x07);
break;
case 0x40: /* Clock Generator Control Feature Register */
dev->regs[dev->index] = (val & 0x3f);
break;
case 0x41: /* Power Control Output Register */
dev->regs[dev->index] = val;
break;
case 0x42: /* PCI INTx Routing Table Mapping Register I */
irq = irq_array[val & 0x0f];
pci_set_irq_routing(PCI_INTA, (irq != 0) ? irq : PCI_IRQ_DISABLED);
irq = irq_array[(val & 0xf0) >> 4];
pci_set_irq_routing(PCI_INTB, (irq != 0) ? irq : PCI_IRQ_DISABLED);
break;
case 0x43: /* PCI INTx Routing Table Mapping Register II */
irq = irq_array[val & 0x0f];
pci_set_irq_routing(PCI_INTC, (irq != 0) ? irq : PCI_IRQ_DISABLED);
irq = irq_array[(val & 0xf0) >> 4];
pci_set_irq_routing(PCI_INTD, (irq != 0) ? irq : PCI_IRQ_DISABLED);
break;
case 0x44: /* PCI INTx Sensitivity Register */
/* TODO: When doing the IRQ and PCI IRQ rewrite,
bits 0 to 3 toggle edge/level output. */
dev->regs[dev->index] = val;
break;
default:
break;
}
if (dev->index != 0x03) {
ali1489_log("M1489: dev->regs[%02x] = %02x\n", dev->index, val);
}
} else if (dev->index == 0x03)
dev->regs[dev->index] = val;
break;
default:
break;
}
}
static uint8_t
ali1489_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
const ali1489_t *dev = (ali1489_t *) priv;
switch (addr) {
case 0x23:
/* Avoid conflict with Cyrix CPU registers */
if (((dev->index == 0x20) || (dev->index >= 0xc0)) && cpu_iscyrix)
ret = 0xff;
else if (dev->index == 0x3f)
ret = inb(0x70);
else
ret = dev->regs[dev->index];
break;
default:
break;
}
ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret);
return ret;
}
static void
ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
ali1489_log("M1489-PCI: dev->pci_conf[%02x] = %02x\n", addr, val);
switch (addr) {
/* Dummy PCI Config */
case 0x04:
dev->pci_conf[0x04] = val & 0x7f;
break;
/* Dummy PCI Status */
case 0x07:
dev->pci_conf[0x07] &= ~(val & 0xb8);
break;
default:
break;
}
}
static uint8_t
ali1489_pci_read(UNUSED(int func), int addr, void *priv)
{
const ali1489_t *dev = (ali1489_t *) priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
ali1489_log("M1489-PCI: dev->pci_conf[%02x] (%02x)\n", addr, ret);
return ret;
}
static void
ali1489_reset(void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
ali1489_defaults(dev);
}
static void
ali1489_close(void *priv)
{
ali1489_t *dev = (ali1489_t *) priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1489_init(UNUSED(const device_t *info))
{
ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t));
memset(dev, 0, sizeof(ali1489_t));
/* M1487/M1489
22h Index Port
23h Data Port */
io_sethandler(0x0022, 0x0002, ali1489_read, NULL, NULL, ali1489_write, NULL, NULL, dev);
/* Dummy M1489 PCI device */
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1489_pci_read, ali1489_pci_write, dev, &dev->pci_slot);
device_add(&ide_ali1489_device);
dev->port_92 = device_add(&port_92_pci_device);
dev->smram = smram_add();
ali1489_defaults(dev);
return dev;
}
const device_t ali1489_device = {
.name = "ALi M1489",
.internal_name = "ali1489",
.flags = 0,
.local = 0,
.init = ali1489_init,
.close = ali1489_close,
.reset = ali1489_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/ali1489.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,731 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel PCISet chips from 420TX to 440GX.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#include <86box/machine.h>
#include <86box/agpgart.h>
enum {
INTEL_420TX,
INTEL_420ZX,
INTEL_430LX,
INTEL_430NX,
INTEL_430FX,
INTEL_430HX,
INTEL_430VX,
INTEL_430TX,
INTEL_440FX,
INTEL_440LX,
INTEL_440EX,
INTEL_440BX,
INTEL_440GX,
INTEL_440ZX
};
typedef struct i4x0_t {
uint8_t pm2_cntrl;
uint8_t smram_locked;
uint8_t max_drb;
uint8_t drb_unit;
uint8_t drb_default;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t regs[256];
uint8_t regs_locked[256];
uint8_t mem_state[256];
int type;
smram_t *smram_low;
smram_t *smram_high;
agpgart_t *agpgart;
void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
} i4x0_t;
#ifdef ENABLE_I4X0_LOG
int i4x0_do_log = ENABLE_I4X0_LOG;
static void
i4x0_log(const char *fmt, ...)
{
va_list ap;
if (i4x0_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i4x0_log(fmt, ...)
#endif
static void
i4x0_map(i4x0_t *dev, uint32_t addr, uint32_t size, int state)
{
uint32_t base = addr >> 12;
int states[4] = { MEM_READ_EXTANY | MEM_WRITE_EXTANY, MEM_READ_INTERNAL | MEM_WRITE_EXTANY,
MEM_READ_EXTANY | MEM_WRITE_INTERNAL, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL };
state &= 3;
if (dev->mem_state[base] != state) {
mem_set_mem_state_both(addr, size, states[state]);
dev->mem_state[base] = state;
flushmmucache_nopc();
}
}
static void
i4x0_smram_handler_phase0(i4x0_t *dev)
{
uint32_t tom = (mem_size << 10);
if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && smram_enabled(dev->smram_high)) {
tom -= (1 << 20);
mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
/* Disable any active mappings. */
smram_disable_all();
}
static void
i4x0_smram_handler_phase1(i4x0_t *dev)
{
const uint8_t *regs = (uint8_t *) dev->regs;
uint32_t tom = (mem_size << 10);
const uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]);
const uint8_t *ext_reg = (dev->type >= INTEL_440BX) ? &(regs[0x73]) : &(regs[0x71]);
uint32_t s;
uint32_t base[2] = { 0x000a0000, 0x00000000 };
uint32_t size[2] = { 0x00010000, 0x00000000 };
if ((dev->type <= INTEL_420ZX) || (dev->type >= INTEL_430FX)) {
/* Set temporary bases and sizes. */
if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && (*ext_reg & 0x80)) {
base[0] = 0x100a0000;
size[0] = 0x00060000;
} else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) {
base[0] = 0x000c0000;
size[0] = 0x00010000;
} else {
base[0] = 0x000a0000;
size[0] = 0x00020000;
}
if (*reg & 0x08)
smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0],
((*reg & 0x78) == 0x48), (*reg & 0x08));
if ((*reg & 0x28) == 0x28) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
}
/* TSEG mapping. */
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
if ((*reg & 0x08) && (*ext_reg & 0x01)) {
size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03)));
tom -= size[1];
base[1] = tom;
} else
base[1] = size[1] = 0x00000000;
if (size[1] != 0x00000000) {
smram_enable(dev->smram_high, base[1] + (1 << 28), base[1], size[1],
0, 1);
mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
} else {
size[0] = 0x00010000;
switch (*reg & 0x03) {
default:
case 0:
base[0] = (mem_size << 10) - size[0];
s = 1;
break;
case 1:
base[0] = size[0] = 0x00000000;
s = 1;
break;
case 2:
base[0] = 0x000a0000;
s = 0;
break;
case 3:
base[0] = 0x000b0000;
s = 0;
break;
}
if (size[0] != 0x00000000) {
smram_enable(dev->smram_low, base[0], base[0], size[0],
(((*reg & 0x38) == 0x20) || s), 1);
if (*reg & 0x10) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
}
}
}
flushmmucache();
}
static void
i4x0_mask_bar(uint8_t *regs, void *agpgart)
{
uint32_t bar;
/* Make sure the aperture's base is aligned to its size. */
bar = (regs[0x13] << 24) | (regs[0x12] << 16);
bar &= (((uint32_t) regs[0xb4] << 22) | 0xf0000000);
regs[0x12] = (bar >> 16) & 0xff;
regs[0x13] = (bar >> 24) & 0xff;
if (!agpgart)
return;
/* Map aperture and GART. */
agpgart_set_aperture(agpgart,
bar,
((uint32_t) (uint8_t) (~regs[0xb4] & 0x3f) + 1) << 22,
!!(regs[0x51] & 0x02));
agpgart_set_gart(agpgart, (regs[0xb9] << 8) | (regs[0xba] << 16) | (regs[0xbb] << 24));
}
static uint8_t
pm2_cntrl_read(UNUSED(uint16_t addr), void *priv)
{
const i4x0_t *dev = (i4x0_t *) priv;
return dev->pm2_cntrl & 0x01;
}
static void
pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
dev->pm2_cntrl = val & 0x01;
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t *regs = (uint8_t *) dev->regs;
uint8_t *regs_l = (uint8_t *) dev->regs_locked;
if (func > 0)
return;
if (func == 0)
switch (addr) {
case 0x04: /*Command register*/
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_440BX:
case INTEL_440GX:
case INTEL_440ZX:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break;
case INTEL_430FX:
case INTEL_430HX:
case INTEL_430VX:
case INTEL_430TX:
case INTEL_440FX:
regs[0x04] = (regs[0x04] & ~0x02) | (val & 0x02);
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x04] = val & 0x40;
break;
}
break;
case 0x05:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440BX:
case INTEL_440GX:
case INTEL_440ZX:
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x05] = val & 0x01;
break;
default:
break;
}
break;
case 0x07:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_430HX:
regs[0x07] &= ~(val & 0x70);
break;
case INTEL_430FX:
case INTEL_430VX:
case INTEL_430TX:
regs[0x07] &= ~(val & 0x30);
break;
case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9);
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x07] &= ~(val & 0xf1);
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x07] &= ~(val & 0xf0);
break;
}
break;
case 0x0d:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[0x0d] = (val & 0xf0);
break;
default:
regs[0x0d] = (val & 0xf8);
break;
}
break;
case 0x0f:
switch (dev->type) {
case INTEL_430FX:
case INTEL_430HX:
case INTEL_430VX:
case INTEL_430TX:
regs[0x0f] = (val & 0x40);
break;
default:
break;
}
break;
case 0x12:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x13:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x13] = val;
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
if (!regs_l[addr]) {
regs[addr] = val;
regs_l[addr] = 1;
}
break;
default:
break;
}
break;
case 0x4f:
switch (dev->type) {
case INTEL_430HX:
regs[0x4f] = (val & 0x84);
break;
case INTEL_430VX:
regs[0x4f] = (val & 0x94);
break;
case INTEL_430TX:
regs[0x4f] = (val & 0x80);
break;
default:
break;
}
break;
case 0x50:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
regs[0x50] = (val & 0xe5);
break;
case INTEL_430NX:
regs[0x50] = (val & 0xe7);
break;
case INTEL_430FX:
regs[0x50] = (val & 0xef);
break;
case INTEL_430HX:
regs[0x50] = (val & 0xf7);
break;
case INTEL_430VX:
case INTEL_430TX:
regs[0x50] = (val & 0x08);
break;
case INTEL_440FX:
regs[0x50] = (val & 0xf4);
break;
case INTEL_440LX:
regs[0x50] = (val & 0x70);
break;
case INTEL_440EX:
regs[0x50] = (val & 0x20);
break;
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
case INTEL_440GX:
regs[0x50] = (regs[0x50] & 0x04) | (val & 0xe8);
break;
case INTEL_440ZX:
regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
break;
}
break;
case 0x51:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[0x51] = (val & 0xc0);
break;
case INTEL_440FX:
regs[0x51] = (val & 0xc3);
break;
case INTEL_440LX:
regs[0x51] = (regs[0x51] & 0x40) | (val & 0x87);
i4x0_mask_bar(regs, dev->agpgart);
break;
case INTEL_440EX:
regs[0x51] = (val & 0x86);
i4x0_mask_bar(regs, dev->agpgart);
break;
case INTEL_440BX:
case INTEL_440ZX:
regs[0x51] = (regs[0x51] & 0x70) | (val & 0x8f);
i4x0_mask_bar(regs, dev->agpgart);
break;
case INTEL_440GX:
regs[0x51] = (regs[0x51] & 0xb0) | (val & 0x4f);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0x52: /* Cache Control Register */
switch (dev->type) {
default:
/*
420TX/ZX:
Bit 7-6: 0, 0 = 64 kB,
0, 1 = 128 kB,
1, 0 = 256 kB,
1, 1 = 512 kB.
Bit 5: 1 = L2 cache present, 0 = L2 cache absent.
Bit 1: 1 = Write back cache, 0 = write through cache.
Bit 0: 1 = L2 cache enable, 0 = L2 cache disable.
*/
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430NX:
regs[0x52] = (regs[0x52] & 0xe0) | (val & 0x1f);
cpu_cache_ext_enabled = val & 0x01;
cpu_update_waitstates();
break;
case INTEL_430LX:
regs[0x52] = (regs[0x52] & 0xe0) | (val & 0x1b);
cpu_cache_ext_enabled = val & 0x01;
cpu_update_waitstates();
break;
case INTEL_430FX:
case INTEL_430VX:
case INTEL_430TX:
regs[0x52] = (regs[0x52] & 0x04) | (val & 0xfb);
cpu_cache_ext_enabled = ((val & 0x03) == 0x01);
cpu_update_waitstates();
break;
case INTEL_430HX:
regs[0x52] = val;
cpu_cache_ext_enabled = ((val & 0x03) == 0x01);
cpu_update_waitstates();
break;
case INTEL_440FX:
regs[0x52] = val;
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x52] = val & 0x07;
break;
}
break;
case 0x53:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
regs[0x53] = val & 0x0b;
break;
case INTEL_430NX:
regs[0x53] = val & 0x0a;
break;
case INTEL_430VX:
case INTEL_430TX:
regs[0x53] = val & 0x3f;
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x53] = val & 0x60;
break;
case INTEL_440BX:
case INTEL_440GX:
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
default:
break;
}
break;
case 0x54:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[0x54] = val & 0x07;
break;
case INTEL_430VX:
regs[0x54] = val & 0xd8;
break;
case INTEL_430TX:
regs[0x54] = val & 0xfa;
break;
case INTEL_440FX:
regs[0x54] = val & 0x82;
break;
default:
break;
}
break;
case 0x55:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
/* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has
this register. The mask is unknown, so write all bits. */
regs[0x55] = val;
break;
case INTEL_430VX:
case INTEL_430TX:
regs[0x55] = val & 0x01;
break;
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
regs[0x55] = val;
break;
default:
break;
}
break;
case 0x56:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
/* According to the FreeBSD 3.x source code, the 420TX/ZX chipset has
this register. The mask is unknown, so write all bits. */
regs[0x56] = val;
break;
case INTEL_430HX:
regs[0x56] = val & 0x1f;
break;
case INTEL_430VX:
regs[0x56] = val & 0x77;
break;
case INTEL_430TX:
regs[0x56] = val & 0x76;
break;
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
regs[0x56] = val;
break;
default:
break;
}
break;
case 0x57:
switch (dev->type) {
/* On the 420TX and 420ZX, this is the SMRAM space register. */
case INTEL_420TX:
case INTEL_420ZX:
i4x0_smram_handler_phase0(dev);
if (dev->smram_locked)
regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20);
else {
regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x57] &= 0xbf;
}
i4x0_smram_handler_phase1(dev);
break;
case INTEL_430LX:
default:
regs[0x57] = val & 0x3f;
break;
case INTEL_430NX:
regs[0x57] = val;
break;
case INTEL_430FX:
case INTEL_430HX:
case INTEL_430VX:
regs[0x57] = val & 0xcf;
break;
case INTEL_430TX:
regs[0x57] = val & 0xdf;
break;
case INTEL_440FX:
regs[0x57] = val & 0x77;
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x57] = val & 0x37;
break;
case INTEL_440BX:
case INTEL_440GX:
regs[0x57] = val & 0x3f;
break;
case INTEL_440ZX:
regs[0x57] = val & 0x2f;
break;
}
break;
case 0x58:
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
regs[0x58] = val & 0x01;
break;
case INTEL_430NX:
case INTEL_440BX:
case INTEL_440ZX:
regs[0x58] = val & 0x03;
break;
case INTEL_430FX:
case INTEL_440FX:
regs[0x58] = val & 0x7f;
break;
case INTEL_430HX:
case INTEL_430VX:
case INTEL_440LX:
case INTEL_440EX:
regs[0x58] = val;
break;
case INTEL_430TX:
regs[0x58] = val & 0x7b;
break;
}
break;
case 0x59: /* PAM0 */
if (dev->type <= INTEL_430NX) {
if ((regs[0x59] ^ val) & 0x0f)
i4x0_map(dev, 0x80000, 0x20000, val & 0x0f);
}
if ((regs[0x59] ^ val) & 0xf0) {
i4x0_map(dev, 0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
if (dev->type > INTEL_430NX)
regs[0x59] = val & 0x70;
else
regs[0x59] = val & 0x77;
break;
case 0x5a: /* PAM1 */
if ((regs[0x5a] ^ val) & 0x0f)
i4x0_map(dev, 0xc0000, 0x04000, val & 0xf);
if ((regs[0x5a] ^ val) & 0xf0)
i4x0_map(dev, 0xc4000, 0x04000, val >> 4);
regs[0x5a] = val & 0x77;
break;
case 0x5b: /*PAM2 */
if ((regs[0x5b] ^ val) & 0x0f)
i4x0_map(dev, 0xc8000, 0x04000, val & 0xf);
if ((regs[0x5b] ^ val) & 0xf0)
i4x0_map(dev, 0xcc000, 0x04000, val >> 4);
regs[0x5b] = val & 0x77;
break;
case 0x5c: /*PAM3 */
if ((regs[0x5c] ^ val) & 0x0f)
i4x0_map(dev, 0xd0000, 0x04000, val & 0xf);
if ((regs[0x5c] ^ val) & 0xf0)
i4x0_map(dev, 0xd4000, 0x04000, val >> 4);
regs[0x5c] = val & 0x77;
break;
case 0x5d: /* PAM4 */
if ((regs[0x5d] ^ val) & 0x0f)
i4x0_map(dev, 0xd8000, 0x04000, val & 0xf);
if ((regs[0x5d] ^ val) & 0xf0)
i4x0_map(dev, 0xdc000, 0x04000, val >> 4);
regs[0x5d] = val & 0x77;
break;
case 0x5e: /* PAM5 */
if ((regs[0x5e] ^ val) & 0x0f)
i4x0_map(dev, 0xe0000, 0x04000, val & 0xf);
if ((regs[0x5e] ^ val) & 0xf0)
i4x0_map(dev, 0xe4000, 0x04000, val >> 4);
regs[0x5e] = val & 0x77;
break;
case 0x5f: /* PAM6 */
if ((regs[0x5f] ^ val) & 0x0f)
i4x0_map(dev, 0xe8000, 0x04000, val & 0xf);
if ((regs[0x5f] ^ val) & 0xf0)
i4x0_map(dev, 0xec000, 0x04000, val >> 4);
regs[0x5f] = val & 0x77;
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
case 0x64:
if ((addr & 0x7) <= dev->max_drb) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
default:
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = val;
break;
case INTEL_430FX:
case INTEL_430VX:
regs[addr] = val & 0x3f;
break;
case INTEL_430TX:
regs[addr] = val & 0x7f;
break;
}
break;
case 0x65:
if ((addr & 0x7) <= dev->max_drb) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440GX:
case INTEL_440BX:
case INTEL_440ZX:
regs[addr] = val;
break;
case INTEL_430VX:
regs[addr] = val & 0x3f;
break;
case INTEL_430TX:
regs[addr] = val & 0x7f;
break;
default:
break;
}
break;
case 0x66:
if ((addr & 0x7) <= dev->max_drb) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440GX:
case INTEL_440BX:
case INTEL_440ZX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0x67:
if ((addr & 0x7) <= dev->max_drb) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_430NX:
case INTEL_430HX:
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440GX:
case INTEL_440ZX:
regs[addr] = val;
break;
case INTEL_430VX:
regs[addr] = val & 0x11;
break;
case INTEL_430TX:
regs[addr] = val & 0xb7;
break;
default:
break;
}
break;
case 0x68:
if (dev->type == INTEL_430NX) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_430HX:
case INTEL_430VX:
case INTEL_430TX:
regs[0x68] = val;
break;
case INTEL_430FX:
regs[0x68] = val & 0x1f;
break;
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440GX:
regs[0x68] = val & 0xc0;
break;
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
case INTEL_440ZX:
regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
break;
default:
break;
}
break;
case 0x69:
if (dev->type == INTEL_430NX) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_440BX:
case INTEL_440GX:
regs[0x69] = val;
break;
case INTEL_430VX:
regs[0x69] = val & 0x07;
break;
case INTEL_440ZX:
regs[0x69] = val & 0x3f;
break;
default:
break;
}
break;
case 0x6a:
case 0x6b:
if (dev->type == INTEL_430NX) {
dev->write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
case INTEL_440BX:
case INTEL_440GX:
regs[addr] = val;
break;
case INTEL_440LX:
case INTEL_440EX:
if (addr == 0x6a)
regs[addr] = val & 0xef;
break;
case INTEL_440ZX:
if (addr == 0x6a)
regs[addr] = val & 0xfc;
else
regs[addr] = val & 0x33;
break;
default:
break;
}
break;
case 0x6c:
case 0x6d:
case 0x6e:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440GX:
if (addr != 0x6e)
regs[addr] = val;
break;
case INTEL_440ZX:
if (addr == 0x6c)
regs[addr] = val & 0x03;
else if (addr == 0x6d)
regs[addr] = val & 0xcf;
break;
default:
break;
}
break;
case 0x6f:
switch (dev->type) {
case INTEL_440LX:
regs[addr] = val;
break;
case INTEL_440EX:
regs[addr] = val & 0xcf;
break;
default:
break;
}
break;
case 0x70:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
regs[addr] = val & 0xc7;
break;
case INTEL_430NX:
regs[addr] = val;
break;
case INTEL_430VX:
case INTEL_430TX:
regs[addr] = val & 0xfc;
break;
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440EX:
regs[addr] = val & 0xf8;
break;
default:
break;
}
break;
case 0x71:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
regs[addr] = val & 0x4d;
break;
case INTEL_430TX:
if (!dev->smram_locked) {
i4x0_smram_handler_phase0(dev);
regs[0x71] = (regs[0x71] & 0x20) | (val & 0xdf);
i4x0_smram_handler_phase1(dev);
}
break;
case INTEL_440EX:
regs[addr] = val;
break;
case INTEL_440FX:
case INTEL_440LX:
regs[addr] = val & 0x1f;
break;
default:
break;
}
break;
case 0x72: /* SMRAM */
if (dev->type <= INTEL_420ZX)
break;
i4x0_smram_handler_phase0(dev);
if (dev->type >= INTEL_430FX) {
if (dev->smram_locked)
regs[0x72] = (regs[0x72] & 0xdf) | (val & 0x20);
else {
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX) || (dev->type == INTEL_440GX))
regs[0x72] = (val & 0x7f);
else
regs[0x72] = (regs[0x72] & 0x87) | (val & 0x78);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x72] &= 0xbf;
}
} else {
if (dev->smram_locked)
regs[0x72] = (regs[0x72] & 0xef) | (val & 0x10);
else {
regs[0x72] = (regs[0x72] & 0xc0) | (val & 0x3f);
dev->smram_locked = (val & 0x08);
if (dev->smram_locked)
regs[0x72] &= 0xdf;
}
}
i4x0_smram_handler_phase1(dev);
break;
case 0x73:
switch (dev->type) {
case INTEL_430VX:
regs[0x73] = val & 0x03;
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
if (!dev->smram_locked) {
i4x0_smram_handler_phase0(dev);
regs[0x73] = (regs[0x73] & 0x38) | (val & 0xc7);
i4x0_smram_handler_phase1(dev);
}
break;
default:
break;
}
break;
case 0x74:
switch (dev->type) {
case INTEL_430VX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x74] = val;
break;
default:
break;
}
break;
case 0x75:
case 0x76:
case 0x7b:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0x77:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
regs[0x77] = val & 0x03;
break;
default:
break;
}
break;
case 0x78:
switch (dev->type) {
case INTEL_430VX:
regs[0x78] = val & 0xcf;
break;
case INTEL_440BX:
case INTEL_440ZX:
regs[0x78] = val & 0x0f;
break;
case INTEL_440GX:
regs[0x78] = val & 0x1f;
break;
default:
break;
}
break;
case 0x79:
switch (dev->type) {
case INTEL_430TX:
regs[0x79] = val & 0x74;
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x79] = val;
break;
default:
break;
}
break;
case 0x7a:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
break;
default:
break;
}
break;
case 0x7c:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[0x7c] = val & 0x8f;
break;
case INTEL_440BX:
case INTEL_440GX:
case INTEL_440ZX:
regs[0x7c] = val & 0x1f;
break;
default:
break;
}
break;
case 0x7d:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[0x7d] = val & 0x32;
break;
default:
break;
}
break;
case 0x7e:
case 0x7f:
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
case INTEL_430LX:
case INTEL_430NX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0x80:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x80] &= ~(val & 0x03);
break;
default:
break;
}
break;
case 0x90:
switch (dev->type) {
case INTEL_430HX:
regs[0x90] = val & 0x87;
break;
case INTEL_440FX:
regs[0x90] = val & 0x1b;
break;
case INTEL_440LX:
regs[0x90] = val & 0xfb;
break;
case INTEL_440EX:
regs[0x90] = val & 0xf8;
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x90] = val;
break;
default:
break;
}
break;
case 0x91:
switch (dev->type) {
case INTEL_430HX:
case INTEL_440BX:
case INTEL_440FX:
case INTEL_440LX:
case INTEL_440GX:
/* Not applicable on 82443EX and 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
default:
break;
}
break;
case 0x92:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
regs[0x92] &= ~(val & 0x07);
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0x92] &= ~(val & 0x1f);
break;
default:
break;
}
break;
case 0x93:
switch (dev->type) {
case INTEL_440FX:
regs[0x93] = (val & 0x0f);
pci_write(0x0cf9, val & 0x06, NULL);
break;
case INTEL_440LX:
case INTEL_440EX:
regs[0x93] = (val & 0x0e);
pci_write(0x0cf9, val & 0x06, NULL);
break;
default:
break;
}
break;
case 0xa7:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
regs[0xa7] = val & 0x1f;
break;
default:
break;
}
break;
case 0xa8:
case 0xa9:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = (val & 0x03);
break;
default:
break;
}
break;
case 0xb0:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xb0] = (val & 0x80);
break;
default:
break;
}
break;
case 0xb1:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
regs[0xb1] = (val & 0x22);
break;
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xb1] = (val & 0xa0);
break;
default:
break;
}
break;
case 0xb4:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0xb9:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xb9] = (val & 0xf0);
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0xba:
case 0xbb:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = val;
i4x0_mask_bar(regs, dev->agpgart);
break;
default:
break;
}
break;
case 0xbc:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
default:
break;
}
break;
case 0xbd:
switch (dev->type) {
case INTEL_440LX:
case INTEL_440EX:
regs[addr] = (val & 0xf8);
break;
default:
break;
}
break;
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
case 0xd4:
case 0xd5:
case 0xd6:
case 0xd7:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[addr] = val;
break;
default:
break;
}
break;
case 0xca:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440GX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xe7;
break;
default:
break;
}
break;
case 0xcb:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440GX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xa7;
break;
default:
break;
}
break;
case 0xcc:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440GX:
regs[0xcc] = (val & 0x7f);
break;
case INTEL_440ZX:
regs[0xcc] = (val & 0x58);
break;
default:
break;
}
break;
case 0xe0:
case 0xe1:
case 0xe2:
case 0xe3:
case 0xe4:
case 0xe8:
case 0xe9:
case 0xea:
case 0xeb:
case 0xec:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
if (!regs_l[addr])
regs[addr] = val;
break;
default:
break;
}
break;
case 0xe5:
case 0xed:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
if (!regs_l[addr])
regs[addr] = (val & 0x3f);
break;
default:
break;
}
break;
case 0xe7:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xe7] = 0x80;
for (uint8_t i = 0; i < 16; i++)
regs_l[0xe0 + i] = !!(val & 0x80);
if (!regs_l[0xe7]) {
regs[0xe7] |= (val & 0x7f);
}
break;
default:
break;
}
break;
case 0xf0:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xf0] = (val & 0xc0);
break;
default:
break;
}
break;
case 0xf1:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440ZX:
case INTEL_440GX:
regs[0xf1] = (val & 0x03);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
const uint8_t *regs = (uint8_t *) dev->regs;
if (func == 0) {
ret = regs[addr];
/* Special behavior for 440FX register 0x93 which is basically TRC in PCI space
with the addition of bits 3 and 0. */
if ((func == 0) && (addr == 0x93) && ((dev->type == INTEL_440FX) || (dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)))
ret = (ret & 0xf9) | (pci_read(0x0cf9, NULL) & 0x06);
else if ((func == 0) && (addr == 0x52) && (dev->type == INTEL_430TX) && !strcmp(machine_get_internal_name(), "tomahawk"))
ret = 0xb2;
}
return ret;
}
static void
i4x0_reset(void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x59, 0x00, priv);
else
i4x0_write(0, 0x59, 0x0f, priv);
for (uint8_t i = 0; i < 6; i++)
i4x0_write(0, 0x5a + i, 0x00, priv);
for (uint8_t i = 0; i <= dev->max_drb; i++)
dev->regs[0x60 + i] = dev->drb_default;
if (dev->type >= INTEL_430NX) {
for (uint8_t i = 0; i < 4; i++)
dev->regs[0x68 + i] = 0x00;
}
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
} else if (dev->type >= INTEL_430LX) {
dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x00, priv);
} else {
dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x57, 0x02, priv);
}
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
}
}
static void
i4x0_close(void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
smram_del(dev->smram_high);
smram_del(dev->smram_low);
free(dev);
}
static void *
i4x0_init(const device_t *info)
{
i4x0_t *dev = (i4x0_t *) malloc(sizeof(i4x0_t));
uint8_t *regs;
memset(dev, 0, sizeof(i4x0_t));
dev->smram_low = smram_add();
dev->smram_high = smram_add();
dev->type = info->local & 0xff;
regs = (uint8_t *) dev->regs;
regs[0x00] = 0x86;
regs[0x01] = 0x80; /*Intel*/
dev->write_drbs = spd_write_drbs;
switch (dev->type) {
case INTEL_420TX:
case INTEL_420ZX:
regs[0x02] = 0x83;
regs[0x03] = 0x04; /* 82424TX/ZX */
regs[0x06] = 0x40;
regs[0x08] = (dev->type == INTEL_420ZX) ? 0x01 : 0x00;
regs[0x0d] = 0x20;
/* According to information from FreeBSD 3.x source code:
0x00 = 486DX, 0x20 = 486SX, 0x40 = 486DX2 or 486DX4, 0x80 = Pentium OverDrive. */
if (!hasfpu && (cpu_multi == 1))
regs[0x50] = 0x20;
else if (!hasfpu && (cpu_multi == 2))
regs[0x50] = 0x60; /* Guess based on the SX, DX, and DX2 values. */
else if (hasfpu && (cpu_multi == 1))
regs[0x50] = 0x00;
else if (hasfpu && (cpu_multi >= 2) && !(cpu_s->cpu_type == CPU_P24T))
regs[0x50] = 0x40;
else
regs[0x50] = 0x80; /* Pentium OverDrive. */
/* According to information from FreeBSD 3.x source code:
00 = 25 MHz, 01 = 33 MHz. */
if (cpu_busspeed > 25000000)
regs[0x50] |= 0x01;
regs[0x51] = 0x80;
/* According to information from FreeBSD 3.x source code:
0x00 = None, 0x01 = 64 kB, 0x41 = 128 kB, 0x81 = 256 kB, 0xc1 = 512 kB,
If bit 0 is set, then if bit 2 is also set, the cache is write back,
otherwise it's write through. */
regs[0x52] = 0xe0; /* 512 kB writeback cache */
regs[0x57] = 0x31;
regs[0x59] = 0x0f;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02;
dev->max_drb = 3;
dev->drb_unit = 1;
dev->drb_default = 0x02;
break;
case INTEL_430LX:
regs[0x02] = 0xa3;
regs[0x03] = 0x04; /* 82434LX/NX */
regs[0x06] = 0x40;
regs[0x08] = 0x03;
regs[0x0d] = 0x20;
regs[0x50] = 0x82;
if (cpu_busspeed <= 60000000)
regs[0x50] |= 0x00;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x50] |= 0x01;
regs[0x51] = 0x80;
regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */
regs[0x59] = 0x0f;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02;
dev->max_drb = 5;
dev->drb_unit = 1;
dev->drb_default = 0x02;
break;
case INTEL_430NX:
regs[0x02] = 0xa3;
regs[0x03] = 0x04; /* 82434LX/NX */
regs[0x06] = 0x40;
regs[0x08] = 0x11;
regs[0x0d] = 0x20;
regs[0x50] = 0x80;
if (cpu_busspeed <= 50000000)
regs[0x50] |= 0x01;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
regs[0x50] |= 0x02;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x50] |= 0x03;
regs[0x51] = 0x80;
regs[0x52] = 0xea; /* 512 kB burst cache, set to 0xaa for 256 kB */
regs[0x57] = 0x31;
regs[0x59] = 0x0f;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02;
dev->max_drb = 7;
dev->drb_unit = 1;
dev->drb_default = 0x02;
dev->write_drbs = spd_write_drbs_with_ext;
break;
case INTEL_430FX:
regs[0x02] = 0x2d;
regs[0x03] = 0x12; /* SB82437FX-66 */
regs[0x08] = (info->local >> 8) & 0xff;
regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */
if (cpu_busspeed <= 50000000)
regs[0x57] |= 0x01;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
regs[0x57] |= 0x02;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x57] |= 0x03;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02;
regs[0x72] = 0x02;
dev->max_drb = 4;
dev->drb_unit = 4;
dev->drb_default = 0x02;
break;
case INTEL_430HX:
regs[0x02] = 0x50;
regs[0x03] = 0x12; /* 82439HX */
regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */
if (cpu_busspeed <= 50000000)
regs[0x57] |= 0x01;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
regs[0x57] |= 0x02;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x57] |= 0x03;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02;
regs[0x72] = 0x02;
dev->max_drb = 7;
dev->drb_unit = 4;
dev->drb_default = 0x02;
break;
case INTEL_430VX:
regs[0x02] = 0x30;
regs[0x03] = 0x70; /* 82437VX */
regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */
regs[0x53] = 0x14;
regs[0x56] = 0x52;
if (cpu_busspeed <= 50000000)
regs[0x57] |= 0x01;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
regs[0x57] |= 0x02;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x57] |= 0x03;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = 0x02;
regs[0x67] = 0x11;
regs[0x69] = 0x03;
regs[0x70] = 0x20;
regs[0x72] = 0x02;
regs[0x74] = 0x0e;
regs[0x78] = 0x23;
dev->max_drb = 4;
dev->drb_unit = 4;
dev->drb_default = 0x02;
break;
case INTEL_430TX:
regs[0x02] = 0x00;
regs[0x03] = 0x71; /* 82439TX */
regs[0x08] = 0x01;
regs[0x52] = 0xb2; /* 512 kB PLB cache, set to 0x42 for 256 kB */
regs[0x53] = 0x14;
regs[0x56] = 0x52;
regs[0x57] = 0x01;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = 0x02;
if (cpu_busspeed <= 60000000)
regs[0x67] |= 0x00;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x67] |= 0x80;
regs[0x70] = 0x20;
regs[0x72] = 0x02;
dev->max_drb = 5;
dev->drb_unit = 4;
dev->drb_default = 0x02;
break;
case INTEL_440FX:
regs[0x02] = 0x37;
regs[0x03] = 0x12; /* 82441FX */
regs[0x08] = 0x02;
if (cpu_busspeed <= 60000000)
regs[0x51] |= 0x01;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x51] |= 0x02;
regs[0x53] = 0x80;
regs[0x57] = 0x01;
regs[0x58] = 0x10;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x02;
regs[0x71] = 0x10;
regs[0x72] = 0x02;
dev->max_drb = 7;
dev->drb_unit = 8;
dev->drb_default = 0x02;
break;
case INTEL_440LX:
regs[0x02] = 0x80;
regs[0x03] = 0x71; /* 82443LX */
regs[0x08] = 0x03;
regs[0x06] = 0x90;
regs[0x10] = 0x08;
regs[0x34] = 0xa0;
if (cpu_busspeed <= 60000000)
regs[0x51] |= 0x40;
else if ((cpu_busspeed > 60000000) && (cpu_busspeed <= 66666667))
regs[0x51] |= 0x00;
regs[0x53] = 0x83;
regs[0x57] = 0x01;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55;
regs[0x72] = 0x02;
regs[0xa0] = 0x02;
regs[0xa2] = 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
dev->max_drb = 7;
dev->drb_unit = 8;
dev->drb_default = 0x01;
break;
case INTEL_440EX:
regs[0x02] = 0x80;
regs[0x03] = 0x71; /* 82443EX. Same Vendor ID as 440LX */
regs[0x08] = 0x03;
regs[0x06] = 0x90;
regs[0x10] = 0x08;
regs[0x34] = 0xa0;
regs[0x51] = 0x80;
regs[0x53] = 0x83;
regs[0x57] = 0x01;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x6c] = regs[0x6d] = regs[0x6e] = regs[0x6f] = 0x55;
regs[0x72] = 0x02;
regs[0xa0] = 0x02;
regs[0xa2] = 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
dev->max_drb = 7;
dev->drb_unit = 8;
dev->drb_default = 0x01;
break;
case INTEL_440BX:
case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90;
regs[0x03] = 0x71; /* 82443BX */
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x08] = (regs[0x7a] & 0x02) ? 0x03 : 0x02;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
if (cpu_busspeed <= 66666667)
regs[0x51] |= 0x20;
else if ((cpu_busspeed > 66666667) && (cpu_busspeed <= 100000000))
regs[0x51] |= 0x00;
regs[0x57] = 0x28; /* 4 DIMMs, SDRAM */
regs[0x58] = 0x03;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x72] = 0x02;
regs[0x73] = 0x38;
regs[0x7b] = 0x38;
regs[0x90] = 0x80;
regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02;
regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
dev->max_drb = 7;
dev->drb_unit = 8;
dev->drb_default = 0x01;
break;
case INTEL_440GX:
regs[0x7a] = (info->local >> 8) & 0xff;
regs[0x02] = (regs[0x7a] & 0x02) ? 0xa2 : 0xa0;
regs[0x03] = 0x71; /* 82443GX */
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
regs[0x57] = 0x28;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] =
regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
regs[0x72] = 0x02;
regs[0x73] = 0x38;
regs[0x7b] = 0x38;
regs[0x90] = 0x80;
regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02;
regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0xa4] = 0x03;
regs[0xa5] = 0x02;
regs[0xa7] = 0x1f;
dev->max_drb = 7;
dev->drb_unit = 8;
dev->drb_default = 0x01;
break;
default:
break;
}
regs[0x04] = 0x06;
regs[0x07] = 0x02;
regs[0x0b] = 0x06;
if (dev->type >= INTEL_440FX) {
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
}
/* Out-of-spec PCI and AGP clocks with overclocked bus. */
if ((dev->type <= INTEL_440FX) && (cpu_busspeed >= 66666666))
cpu_set_pci_speed(cpu_busspeed / 2);
if ((dev->type >= INTEL_440BX) && (cpu_busspeed >= 100000000))
cpu_set_agp_speed(cpu_busspeed / 1.5);
else if (dev->type >= INTEL_440LX)
cpu_set_agp_speed(cpu_busspeed);
i4x0_write(regs[0x59], 0x59, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 0x00, dev);
i4x0_write(regs[0x5c], 0x5c, 0x00, dev);
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, dev);
else if (dev->type >= INTEL_430LX)
i4x0_write(0, 0x72, 0x00, dev);
else
i4x0_write(0, 0x57, 0x02, dev);
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev, &dev->pci_slot);
if ((dev->type >= INTEL_440BX) && !(regs[0x7a] & 0x02)) {
device_add((dev->type == INTEL_440GX) ? &i440gx_agp_device : &i440bx_agp_device);
dev->agpgart = device_add(&agpgart_device);
} else if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) {
device_add(&i440lx_agp_device);
dev->agpgart = device_add(&agpgart_device);
}
return dev;
}
const device_t i420tx_device = {
.name = "Intel 82424TX",
.internal_name = "i420tx",
.flags = DEVICE_PCI,
.local = INTEL_420TX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i420zx_device = {
.name = "Intel 82424ZX",
.internal_name = "i420zx",
.flags = DEVICE_PCI,
.local = INTEL_420ZX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430lx_device = {
.name = "Intel 82434LX",
.internal_name = "i430lx",
.flags = DEVICE_PCI,
.local = INTEL_430LX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430nx_device = {
.name = "Intel 82434NX",
.internal_name = "i430nx",
.flags = DEVICE_PCI,
.local = INTEL_430NX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430fx_device = {
.name = "Intel SB82437FX-66",
.internal_name = "i430fx",
.flags = DEVICE_PCI,
.local = INTEL_430FX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430fx_rev02_device = {
.name = "Intel SB82437FX-66 (Rev. 02)",
.internal_name = "i430fx_rev02",
.flags = DEVICE_PCI,
.local = 0x0200 | INTEL_430FX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430hx_device = {
.name = "Intel 82439HX",
.internal_name = "i430hx",
.flags = DEVICE_PCI,
.local = INTEL_430HX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430vx_device = {
.name = "Intel 82437VX",
.internal_name = "i430vx",
.flags = DEVICE_PCI,
.local = INTEL_430VX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i430tx_device = {
.name = "Intel 82439TX",
.internal_name = "i430tx",
.flags = DEVICE_PCI,
.local = INTEL_430TX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440fx_device = {
.name = "Intel 82441FX",
.internal_name = "i440fx",
.flags = DEVICE_PCI,
.local = INTEL_440FX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440lx_device = {
.name = "Intel 82443LX",
.internal_name = "i440lx",
.flags = DEVICE_PCI,
.local = INTEL_440LX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440ex_device = {
.name = "Intel 82443EX",
.internal_name = "i440ex",
.flags = DEVICE_PCI,
.local = INTEL_440EX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440bx_device = {
.name = "Intel 82443BX",
.internal_name = "i440bx",
.flags = DEVICE_PCI,
.local = 0x8000 | INTEL_440BX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440bx_no_agp_device = {
.name = "Intel 82443BX (No AGP)",
.internal_name = "i440bx_no_agp",
.flags = DEVICE_PCI,
.local = 0x8200 | INTEL_440BX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440gx_device = {
.name = "Intel 82443GX",
.internal_name = "i440gx",
.flags = DEVICE_PCI,
.local = 0x8000 | INTEL_440GX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t i440zx_device = {
.name = "Intel 82443ZX",
.internal_name = "i440zx",
.flags = DEVICE_PCI,
.local = 0x8000 | INTEL_440ZX,
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/chipset/intel_4x0.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 21,007 |
```c
// minitrace
// path_to_url
// Released under the MIT license.
// See minitrace.h for basic documentation.
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#ifdef _WIN32
#pragma warning (disable:4996)
#define WIN32_LEAN_AND_MEAN
#include <windows.h>
#ifndef __MINGW32__
#define __thread __declspec(thread)
#endif
#define pthread_cond_t CONDITION_VARIABLE
#define pthread_cond_init(a) InitializeConditionVariable(a)
#define pthread_cond_wait(a, b) SleepConditionVariableCS(a, b, INFINITE)
#define pthread_cond_signal(a) WakeConditionVariable(a)
#define pthread_mutex_t CRITICAL_SECTION
#define pthread_mutex_init(a, b) InitializeCriticalSection(a)
#define pthread_mutex_lock(a) EnterCriticalSection(a)
#define pthread_mutex_unlock(a) LeaveCriticalSection(a)
#define pthread_mutex_destroy(a) DeleteCriticalSection(a)
#else
#include <signal.h>
#include <pthread.h>
#include <sys/time.h>
#include <unistd.h>
#endif
#include <stdatomic.h>
#include <minitrace/minitrace.h>
#ifdef __GNUC__
#define ATTR_NORETURN __attribute__((noreturn))
#else
#define ATTR_NORETURN
#endif
#define ARRAY_SIZE(x) sizeof(x)/sizeof(x[0])
#define TRUE 1
#define FALSE 0
// Ugh, this struct is already pretty heavy.
// Will probably need to move arguments to a second buffer to support more than one.
typedef struct raw_event {
const char *name;
const char *cat;
void *id;
int64_t ts;
uint32_t pid;
uint32_t tid;
char ph;
mtr_arg_type arg_type;
const char *arg_name;
union {
const char *a_str;
int a_int;
double a_double;
};
} raw_event_t;
static raw_event_t *event_buffer;
static raw_event_t *flush_buffer;
static volatile int event_count;
static __attribute__ ((aligned (32))) atomic_long is_tracing = FALSE;
static __attribute__ ((aligned (32))) atomic_long stop_flushing_requested = FALSE;
static int is_flushing = FALSE;
static int events_in_progress = 0;
static int64_t time_offset;
static int first_line = 1;
static FILE *fp;
static __thread int cur_thread_id; // Thread local storage
static int cur_process_id;
static pthread_mutex_t mutex;
static pthread_mutex_t event_mutex;
static pthread_cond_t buffer_not_full_cond;
static pthread_cond_t buffer_full_cond;
#define STRING_POOL_SIZE 100
static char *str_pool[100];
// forward declaration
void mtr_flush_with_state(int);
// Tiny portability layer.
// Exposes:
// get_cur_thread_id()
// get_cur_process_id()
// mtr_time_s()
// pthread basics
#ifdef _WIN32
static int get_cur_thread_id(void) {
return (int)GetCurrentThreadId();
}
static int get_cur_process_id(void) {
return (int)GetCurrentProcessId();
}
static uint64_t _frequency = 0;
static uint64_t _starttime = 0;
double mtr_time_s(void) {
if (_frequency == 0) {
QueryPerformanceFrequency((LARGE_INTEGER*)&_frequency);
QueryPerformanceCounter((LARGE_INTEGER*)&_starttime);
}
__int64 time;
QueryPerformanceCounter((LARGE_INTEGER*)&time);
return ((double) (time - _starttime) / (double) _frequency);
}
// Ctrl+C handling for Windows console apps
static BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) {
if (atomic_load(&is_tracing) && fdwCtrlType == CTRL_C_EVENT) {
printf("Ctrl-C detected! Flushing trace and shutting down.\n\n");
mtr_flush();
mtr_shutdown();
}
ExitProcess(1);
}
void mtr_register_sigint_handler(void) {
// For console apps:
SetConsoleCtrlHandler(&CtrlHandler, TRUE);
}
HANDLE thread_handle;
static DWORD WINAPI thread_flush_proc(void* param) {
while(TRUE) {
mtr_flush_with_state(FALSE);
if(atomic_load(&stop_flushing_requested)) {
break;
}
}
return 0;
}
static void init_flushing_thread(void) {
pthread_mutex_lock(&mutex);
is_flushing = FALSE;
pthread_mutex_unlock(&mutex);
thread_handle = CreateThread(NULL, 0, thread_flush_proc, (void*)0, 0, NULL);
}
static void join_flushing_thread(void) {
WaitForSingleObject(thread_handle, INFINITE);
}
#else
static inline int get_cur_thread_id(void) {
return (int)(intptr_t)pthread_self();
}
static inline int get_cur_process_id(void) {
return (int)getpid();
}
static pthread_t thread_handle = 0;
static void* thread_flush_proc(void* param) {
while(1) {
mtr_flush_with_state(0);
if(atomic_load(&stop_flushing_requested)) {
break;
}
}
return 0;
}
static void init_flushing_thread(void) {
pthread_mutex_lock(&mutex);
is_flushing = FALSE;
pthread_mutex_unlock(&mutex);
if (pthread_create(&thread_handle, NULL, thread_flush_proc, NULL) != 0)
{
thread_handle = 0;
}
}
static void join_flushing_thread(void) {
if (thread_handle) pthread_join(thread_handle, NULL);
thread_handle = 0;
}
#if defined(BLACKBERRY)
double mtr_time_s() {
struct timespec time;
clock_gettime(CLOCK_MONOTONIC, &time); // Linux must use CLOCK_MONOTONIC_RAW due to time warps
return time.tv_sec + time.tv_nsec / 1.0e9;
}
#else
double mtr_time_s(void) {
static time_t start;
struct timeval tv;
gettimeofday(&tv, NULL);
if (start == 0) {
start = tv.tv_sec;
}
tv.tv_sec -= start;
return (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
}
#endif // !BLACKBERRY
static void termination_handler(int signum) ATTR_NORETURN;
static void termination_handler(int signum) {
(void) signum;
if (is_tracing) {
printf("Ctrl-C detected! Flushing trace and shutting down.\n\n");
mtr_flush();
fwrite("\n]}\n", 1, 4, f);
fclose(f);
}
exit(1);
}
void mtr_register_sigint_handler(void) {
#ifndef MTR_ENABLED
return;
#endif
// Avoid altering set-to-be-ignored handlers while registering.
if (signal(SIGINT, &termination_handler) == SIG_IGN)
signal(SIGINT, SIG_IGN);
}
#endif
void mtr_init_from_stream(void *stream) {
#ifndef MTR_ENABLED
return;
#endif
event_buffer = (raw_event_t *)malloc(INTERNAL_MINITRACE_BUFFER_SIZE * sizeof(raw_event_t));
flush_buffer = (raw_event_t *)malloc(INTERNAL_MINITRACE_BUFFER_SIZE * sizeof(raw_event_t));
event_count = 0;
fp = (FILE *) stream;
const char *header = "{\"traceEvents\":[\n";
fwrite(header, 1, strlen(header), fp);
time_offset = (uint64_t)(mtr_time_s() * 1000000);
first_line = 1;
pthread_mutex_init(&mutex, 0);
pthread_mutex_init(&event_mutex, 0);
}
void mtr_init(const char *json_file) {
#ifndef MTR_ENABLED
return;
#endif
mtr_init_from_stream(fopen(json_file, "wb"));
}
void mtr_shutdown(void) {
#ifndef MTR_ENABLED
return;
#endif
mtr_flush_with_state(TRUE);
fwrite("\n]}\n", 1, 4, fp);
fclose(fp);
pthread_mutex_destroy(&mutex);
pthread_mutex_destroy(&event_mutex);
fp = 0;
free(event_buffer);
event_buffer = 0;
for (uint8_t i = 0; i < STRING_POOL_SIZE; i++) {
if (str_pool[i]) {
free(str_pool[i]);
str_pool[i] = 0;
}
}
}
const char *mtr_pool_string(const char *str) {
for (uint8_t i = 0; i < STRING_POOL_SIZE; i++) {
if (!str_pool[i]) {
str_pool[i] = (char*)malloc(strlen(str) + 1);
strcpy(str_pool[i], str);
return str_pool[i];
} else {
if (!strcmp(str, str_pool[i]))
return str_pool[i];
}
}
return "string pool full";
}
void mtr_start(void) {
#ifndef MTR_ENABLED
return;
#endif
#ifdef _WIN32
pthread_cond_init(&buffer_not_full_cond);
pthread_cond_init(&buffer_full_cond);
#else
pthread_cond_init(&buffer_not_full_cond, NULL);
pthread_cond_init(&buffer_full_cond, NULL);
#endif
atomic_store(&is_tracing, TRUE);
init_flushing_thread();
}
void mtr_stop(void) {
#ifndef MTR_ENABLED
return;
#endif
atomic_store(&is_tracing, FALSE);
atomic_store(&stop_flushing_requested, TRUE);
pthread_cond_signal(&buffer_not_full_cond);
pthread_cond_signal(&buffer_full_cond);
join_flushing_thread();
atomic_store(&stop_flushing_requested, FALSE);
}
// TODO: fwrite more than one line at a time.
// Flushing is thread safe and process async
// using double-buffering mechanism.
// Aware: only one flushing process may be
// running at any point of time
void mtr_flush_with_state(int is_last) {
#ifndef MTR_ENABLED
return;
#endif
int i = 0;
char linebuf[1024];
char arg_buf[1024];
char id_buf[256];
int event_count_copy = 0;
int events_in_progress_copy = 1;
raw_event_t *event_buffer_tmp = NULL;
// small critical section to swap buffers
// - no any new events can be spawn while
// swapping since they tied to the same mutex
// - checks for any flushing in process
pthread_mutex_lock(&mutex);
// if not flushing already
if (is_flushing) {
pthread_mutex_unlock(&mutex);
return;
}
is_flushing = TRUE;
if(!is_last) {
while(event_count < INTERNAL_MINITRACE_BUFFER_SIZE && atomic_load(&is_tracing)) {
pthread_cond_wait(&buffer_full_cond, &mutex);
}
}
event_count_copy = event_count;
event_buffer_tmp = flush_buffer;
flush_buffer = event_buffer;
event_buffer = event_buffer_tmp;
event_count = 0;
// waiting for any unfinished events before swap
while (events_in_progress_copy != 0) {
pthread_mutex_lock(&event_mutex);
events_in_progress_copy = events_in_progress;
pthread_mutex_unlock(&event_mutex);
}
pthread_mutex_unlock(&mutex);
pthread_cond_signal(&buffer_not_full_cond);
for (i = 0; i < event_count_copy; i++) {
raw_event_t *raw = &flush_buffer[i];
int len;
switch (raw->arg_type) {
case MTR_ARG_TYPE_INT:
snprintf(arg_buf, ARRAY_SIZE(arg_buf), "\"%s\":%i", raw->arg_name, raw->a_int);
break;
case MTR_ARG_TYPE_STRING_CONST:
snprintf(arg_buf, ARRAY_SIZE(arg_buf), "\"%s\":\"%s\"", raw->arg_name, raw->a_str);
break;
case MTR_ARG_TYPE_STRING_COPY:
if (strlen(raw->a_str) > 700) {
snprintf(arg_buf, ARRAY_SIZE(arg_buf), "\"%s\":\"%.*s\"", raw->arg_name, 700, raw->a_str);
} else {
snprintf(arg_buf, ARRAY_SIZE(arg_buf), "\"%s\":\"%s\"", raw->arg_name, raw->a_str);
}
break;
case MTR_ARG_TYPE_NONE:
arg_buf[0] = '\0';
break;
}
if (raw->id) {
switch (raw->ph) {
case 'S':
case 'T':
case 'F':
// TODO: Support full 64-bit pointers
snprintf(id_buf, ARRAY_SIZE(id_buf), ",\"id\":\"0x%08x\"", (uint32_t)(uintptr_t)raw->id);
break;
case 'X':
snprintf(id_buf, ARRAY_SIZE(id_buf), ",\"dur\":%i", (int)raw->a_double);
break;
default:
break;
}
} else {
id_buf[0] = 0;
}
const char *cat = raw->cat;
#ifdef _WIN32
// On Windows, we often end up with backslashes in category.
char temp[256];
{
int len = (int)strlen(cat);
int i;
if (len > 255) len = 255;
for (i = 0; i < len; i++) {
temp[i] = cat[i] == '\\' ? '/' : cat[i];
}
temp[len] = 0;
cat = temp;
}
#endif
len = snprintf(linebuf, ARRAY_SIZE(linebuf), "%s{\"cat\":\"%s\",\"pid\":%i,\"tid\":%i,\"ts\":%" PRId64 ",\"ph\":\"%c\",\"name\":\"%s\",\"args\":{%s}%s}",
first_line ? "" : ",\n",
cat, raw->pid, raw->tid, raw->ts - time_offset, raw->ph, raw->name, arg_buf, id_buf);
fwrite(linebuf, 1, len, f);
first_line = 0;
if (raw->arg_type == MTR_ARG_TYPE_STRING_COPY) {
free((void*)raw->a_str);
}
#ifdef MTR_COPY_EVENT_CATEGORY_AND_NAME
free(raw->name);
free(raw->cat);
#endif
}
pthread_mutex_lock(&mutex);
is_flushing = is_last;
pthread_mutex_unlock(&mutex);
}
void mtr_flush(void) {
mtr_flush_with_state(FALSE);
}
void internal_mtr_raw_event(const char *category, const char *name, char ph, void *id) {
#ifndef MTR_ENABLED
return;
#endif
if (!atomic_load(&is_tracing)) {
return;
}
pthread_mutex_lock(&mutex);
while(event_count >= INTERNAL_MINITRACE_BUFFER_SIZE && atomic_load(&is_tracing)) {
pthread_cond_wait(&buffer_not_full_cond, &mutex);
}
raw_event_t *ev = &event_buffer[event_count];
++event_count;
pthread_mutex_lock(&event_mutex);
++events_in_progress;
pthread_mutex_unlock(&event_mutex);
int local_event_count = event_count;
pthread_mutex_unlock(&mutex);
if(local_event_count >= INTERNAL_MINITRACE_BUFFER_SIZE) {
pthread_cond_signal(&buffer_full_cond);
}
double ts = mtr_time_s();
if (!cur_thread_id) {
cur_thread_id = get_cur_thread_id();
}
if (!cur_process_id) {
cur_process_id = get_cur_process_id();
}
#ifdef MTR_COPY_EVENT_CATEGORY_AND_NAME
const size_t category_len = strlen(category);
ev->cat = malloc(category_len + 1);
strcpy(ev->cat, category);
const size_t name_len = strlen(name);
ev->name = malloc(name_len + 1);
strcpy(ev->name, name);
#else
ev->cat = category;
ev->name = name;
#endif
ev->id = id;
ev->ph = ph;
if (ev->ph == 'X') {
double x;
memcpy(&x, id, sizeof(double));
ev->ts = (int64_t)(x * 1000000);
ev->a_double = (ts - x) * 1000000;
} else {
ev->ts = (int64_t)(ts * 1000000);
}
ev->tid = cur_thread_id;
ev->pid = cur_process_id;
ev->arg_type = MTR_ARG_TYPE_NONE;
pthread_mutex_lock(&event_mutex);
--events_in_progress;
pthread_mutex_unlock(&event_mutex);
}
void internal_mtr_raw_event_arg(const char *category, const char *name, char ph, void *id, mtr_arg_type arg_type, const char *arg_name, void *arg_value) {
#ifndef MTR_ENABLED
return;
#endif
if (!atomic_load(&is_tracing)) {
return;
}
pthread_mutex_lock(&mutex);
while(event_count >= INTERNAL_MINITRACE_BUFFER_SIZE && atomic_load(&is_tracing)) {
pthread_cond_wait(&buffer_not_full_cond, &mutex);
}
raw_event_t *ev = &event_buffer[event_count];
++event_count;
pthread_mutex_lock(&event_mutex);
++events_in_progress;
pthread_mutex_unlock(&event_mutex);
int local_event_count = event_count;
pthread_mutex_unlock(&mutex);
if(local_event_count >= INTERNAL_MINITRACE_BUFFER_SIZE) {
pthread_cond_signal(&buffer_full_cond);
}
if (!cur_thread_id) {
cur_thread_id = get_cur_thread_id();
}
if (!cur_process_id) {
cur_process_id = get_cur_process_id();
}
double ts = mtr_time_s();
#ifdef MTR_COPY_EVENT_CATEGORY_AND_NAME
const size_t category_len = strlen(category);
ev->cat = malloc(category_len + 1);
strcpy(ev->cat, category);
const size_t name_len = strlen(name);
ev->name = malloc(name_len + 1);
strcpy(ev->name, name);
#else
ev->cat = category;
ev->name = name;
#endif
ev->id = id;
ev->ts = (int64_t)(ts * 1000000);
ev->ph = ph;
ev->tid = cur_thread_id;
ev->pid = cur_process_id;
ev->arg_type = arg_type;
ev->arg_name = arg_name;
switch (arg_type) {
case MTR_ARG_TYPE_INT: ev->a_int = (int)(uintptr_t)arg_value; break;
case MTR_ARG_TYPE_STRING_CONST: ev->a_str = (const char*)arg_value; break;
case MTR_ARG_TYPE_STRING_COPY: ev->a_str = strdup((const char*)arg_value); break;
case MTR_ARG_TYPE_NONE: break;
}
pthread_mutex_lock(&event_mutex);
--events_in_progress;
pthread_mutex_unlock(&event_mutex);
}
``` | /content/code_sandbox/src/minitrace/minitrace.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,073 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the CMD PCI-0640B controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/cdrom.h>
#include <86box/scsi_device.h>
#include <86box/scsi_cdrom.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/mo.h>
typedef struct cmd640_t {
uint8_t vlb_idx;
uint8_t id;
uint8_t in_cfg;
uint8_t channels;
uint8_t pci;
uint8_t irq_state;
uint8_t pci_slot;
uint8_t pad0;
uint8_t regs[256];
uint32_t local;
int irq_mode[2];
int irq_pin;
int irq_line;
} cmd640_t;
static int next_id = 0;
#ifdef ENABLE_CMD640_LOG
int cmd640_do_log = ENABLE_CMD640_LOG;
static void
cmd640_log(const char *fmt, ...)
{
va_list ap;
if (cmd640_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cmd640_log(fmt, ...)
#endif
void
cmd640_set_irq_0(uint8_t status, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
int irq = !!(status & 0x04);
if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
if (!(dev->channels & 1))
return;
if (irq) {
if (dev->irq_mode[0] == 1)
pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picint(1 << 14);
} else {
if (dev->irq_mode[0] == 1)
pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picintc(1 << 14);
}
}
void
cmd640_set_irq_1(uint8_t status, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
int irq = !!(status & 0x04);
if (!(dev->regs[0x57] & 0x10) || (status & 0x04))
dev->regs[0x57] = (dev->regs[0x57] & ~0x10) | (status << 2);
if (!(dev->channels & 2))
return;
if (irq) {
if (dev->irq_mode[1] == 1)
pci_set_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picint(1 << 15);
} else {
if (dev->irq_mode[1] == 1)
pci_clear_irq(dev->pci_slot, dev->irq_pin, &dev->irq_state);
else
picintc(1 << 15);
}
}
static void
cmd640_ide_handlers(cmd640_t *dev)
{
uint16_t main;
uint16_t side;
if (dev->channels & 0x01) {
ide_pri_disable();
if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
if (dev->regs[0x04] & 0x01)
ide_pri_enable();
}
if (dev->channels & 0x02) {
ide_sec_disable();
if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
ide_sec_enable();
}
}
static void
cmd640_common_write(int addr, uint8_t val, cmd640_t *dev)
{
switch (addr) {
case 0x51:
dev->regs[addr] = val;
cmd640_ide_handlers(dev);
break;
case 0x52:
case 0x54:
case 0x56:
case 0x58:
case 0x59:
dev->regs[addr] = val;
break;
case 0x53:
case 0x55:
dev->regs[addr] = val & 0xc0;
break;
case 0x57:
dev->regs[addr] = val & 0xdc;
break;
case 0x5b: /* Undocumented register that Linux attempts to use! */
dev->regs[addr] = val;
break;
default:
break;
}
}
static void
cmd640_vlb_write(uint16_t addr, uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
addr &= 0x00ff;
switch (addr) {
case 0x0078:
if (dev->in_cfg)
dev->vlb_idx = val;
else if ((dev->regs[0x50] & 0x80) && (val == dev->id))
dev->in_cfg = 1;
break;
case 0x007c:
cmd640_common_write(dev->vlb_idx, val, dev);
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
default:
break;
}
}
static void
cmd640_vlb_writew(uint16_t addr, uint16_t val, void *priv)
{
cmd640_vlb_write(addr, val & 0xff, priv);
cmd640_vlb_write(addr + 1, val >> 8, priv);
}
static void
cmd640_vlb_writel(uint16_t addr, uint32_t val, void *priv)
{
cmd640_vlb_writew(addr, val & 0xffff, priv);
cmd640_vlb_writew(addr + 2, val >> 16, priv);
}
static uint8_t
cmd640_vlb_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
cmd640_t *dev = (cmd640_t *) priv;
addr &= 0x00ff;
switch (addr) {
case 0x0078:
if (dev->in_cfg)
ret = dev->vlb_idx;
break;
case 0x007c:
ret = dev->regs[dev->vlb_idx];
if (dev->vlb_idx == 0x50)
dev->regs[0x50] &= ~0x04;
else if (dev->vlb_idx == 0x57)
dev->regs[0x57] &= ~0x10;
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
default:
break;
}
return ret;
}
static uint16_t
cmd640_vlb_readw(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = cmd640_vlb_read(addr, priv);
ret |= (cmd640_vlb_read(addr + 1, priv) << 8);
return ret;
}
static uint32_t
cmd640_vlb_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = cmd640_vlb_readw(addr, priv);
ret |= (cmd640_vlb_readw(addr + 2, priv) << 16);
return ret;
}
static void
cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
cmd640_log("cmd640_pci_write(%i, %02X, %02X)\n", func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
dev->regs[addr] = (val & 0x41);
cmd640_ide_handlers(dev);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0x80);
break;
case 0x09:
if ((dev->regs[addr] & 0x0a) == 0x0a) {
dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
dev->irq_mode[0] = !!(val & 0x01);
dev->irq_mode[1] = !!(val & 0x04);
cmd640_ide_handlers(dev);
}
break;
case 0x10:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x10] = (val & 0xf8) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x11:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x11] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x14:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x14] = (val & 0xfc) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x15:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x15] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x18:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x18] = (val & 0xf8) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x19:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x19] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x1c:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1c] = (val & 0xfc) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x1d:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1d] = val;
cmd640_ide_handlers(dev);
}
break;
default:
cmd640_common_write(addr, val, dev);
break;
}
}
static uint8_t
cmd640_pci_read(int func, int addr, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) {
ret = dev->regs[addr];
if (addr == 0x50)
dev->regs[0x50] &= ~0x04;
else if (addr == 0x57)
dev->regs[0x57] &= ~0x10;
}
cmd640_log("cmd640_pci_read(%i, %02X, %02X)\n", func, addr, ret);
return ret;
}
static void
cmd640_reset(void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
int i = 0;
int min_channel;
int max_channel;
switch (dev->channels) {
default:
case 0x00:
min_channel = max_channel = 0;
break;
case 0x01:
min_channel = 0;
max_channel = 1;
break;
case 0x02:
min_channel = 2;
max_channel = 3;
break;
case 0x03:
min_channel = 0;
max_channel = 3;
break;
}
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel >= min_channel) &&
(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
(mo_drives[i].ide_channel <= max_channel) && mo_drives[i].priv)
mo_reset((scsi_common_t *) mo_drives[i].priv);
}
if (dev->channels & 0x01)
cmd640_set_irq_0(0x00, priv);
if (dev->channels & 0x02)
cmd640_set_irq_1(0x00, priv);
memset(dev->regs, 0x00, sizeof(dev->regs));
dev->regs[0x50] = 0x02; /* Revision 02 */
dev->regs[0x50] |= (dev->id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
dev->regs[0x59] = 0x40;
if (dev->pci) {
cmd640_log("dev->local = %08X\n", dev->local);
if ((dev->local & 0xffff) == 0x0a) {
dev->regs[0x50] |= 0x40; /* Enable Base address register R/W;
If 0, they return 0 and are read-only 8 */
}
dev->regs[0x00] = 0x95; /* CMD */
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x40; /* PCI-0640B */
dev->regs[0x03] = 0x06;
dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x08] = 0x02; /* Revision 02 */
dev->regs[0x09] = dev->local; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
dev->regs[0x0b] = 0x01; /* Mass storage controller */
/* Base addresses (1F0, 3F4, 170, 374) */
if (dev->regs[0x50] & 0x40) {
dev->regs[0x10] = 0xf1;
dev->regs[0x11] = 0x01;
dev->regs[0x14] = 0xf5;
dev->regs[0x15] = 0x03;
dev->regs[0x18] = 0x71;
dev->regs[0x19] = 0x01;
dev->regs[0x1c] = 0x75;
dev->regs[0x1d] = 0x03;
}
dev->regs[0x3c] = 0x14; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
dev->irq_mode[0] = dev->irq_mode[1] = 0;
dev->irq_pin = PCI_INTA;
dev->irq_line = 14;
} else {
dev->regs[0x04] = 0x01; /* To make sure the two channels get enabled. */
if ((dev->local & 0xffff) == 0x0078)
dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
/* If bit 7 is 1, then device ID has to be written on port x78h before
accessing the configuration registers */
dev->in_cfg = 1; /* Configuration registers are accessible */
}
cmd640_ide_handlers(dev);
}
static void
cmd640_close(void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
free(dev);
next_id = 0;
}
static void *
cmd640_init(const device_t *info)
{
cmd640_t *dev = (cmd640_t *) malloc(sizeof(cmd640_t));
memset(dev, 0x00, sizeof(cmd640_t));
dev->id = next_id | 0x60;
dev->pci = !!(info->flags & DEVICE_PCI);
dev->local = info->local;
dev->channels = ((info->local & 0x60000) >> 17) & 0x03;
if (info->flags & DEVICE_PCI) {
device_add(&ide_pci_2ch_device);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev, &dev->pci_slot);
if (dev->channels & 0x01)
ide_set_bus_master(0, NULL, cmd640_set_irq_0, dev);
if (dev->channels & 0x02)
ide_set_bus_master(1, NULL, cmd640_set_irq_1, dev);
/* The CMD PCI-0640B IDE controller has no DMA capability,
so set our devices IDE devices to force ATA-3 (no DMA). */
if (dev->channels & 0x01)
ide_board_set_force_ata3(0, 1);
if (dev->channels & 0x02)
ide_board_set_force_ata3(1, 1);
#if 0
ide_pri_disable();
#endif
} else if (info->flags & DEVICE_VLB) {
device_add(&ide_vlb_2ch_device);
io_sethandler(info->local & 0xffff, 0x0008,
cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl,
cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel,
dev);
}
next_id++;
cmd640_reset(dev);
return dev;
}
const device_t ide_cmd640_vlb_device = {
.name = "CMD PCI-0640B VLB",
.internal_name = "ide_cmd640_vlb",
.flags = DEVICE_VLB,
.local = 0x60078,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_vlb_178_device = {
.name = "CMD PCI-0640B VLB (Port 178h)",
.internal_name = "ide_cmd640_vlb_178",
.flags = DEVICE_VLB,
.local = 0x60178,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_vlb_pri_device = {
.name = "CMD PCI-0640B VLB",
.internal_name = "ide_cmd640_vlb",
.flags = DEVICE_VLB,
.local = 0x20078,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_vlb_pri_178_device = {
.name = "CMD PCI-0640B VLB (Port 178h)",
.internal_name = "ide_cmd640_vlb_178",
.flags = DEVICE_VLB,
.local = 0x20178,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_vlb_sec_device = {
.name = "CMD PCI-0640B VLB",
.internal_name = "ide_cmd640_vlb",
.flags = DEVICE_VLB,
.local = 0x40078,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_vlb_sec_178_device = {
.name = "CMD PCI-0640B VLB (Port 178h)",
.internal_name = "ide_cmd640_vlb_178",
.flags = DEVICE_VLB,
.local = 0x40178,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_pci_device = {
.name = "CMD PCI-0640B PCI",
.internal_name = "ide_cmd640_pci",
.flags = DEVICE_PCI,
.local = 0x6000a,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_pci_legacy_only_device = {
.name = "CMD PCI-0640B PCI (Legacy Mode Only)",
.internal_name = "ide_cmd640_pci_legacy_only",
.flags = DEVICE_PCI,
.local = 0x60000,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_pci_single_channel_device = {
.name = "CMD PCI-0640B PCI",
.internal_name = "ide_cmd640_pci_single_channel",
.flags = DEVICE_PCI,
.local = 0x2000a,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd640_pci_single_channel_sec_device = {
.name = "CMD PCI-0640B PCI",
.internal_name = "ide_cmd640_pci_single_channel_sec",
.flags = DEVICE_PCI,
.local = 0x4000a,
.init = cmd640_init,
.close = cmd640_close,
.reset = cmd640_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_cmd640.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,004 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the IDE emulation for hard disks and ATAPI
* CD-ROM devices.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdarg.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/hdd.h>
unsigned int hdd_table[128][3] = {
// clang-format off
{ 306, 4, 17 }, /* 0 - 7 */
{ 615, 2, 17 },
{ 306, 4, 26 },
{ 1024, 2, 17 },
{ 697, 3, 17 },
{ 306, 8, 17 },
{ 614, 4, 17 },
{ 615, 4, 17 },
{ 670, 4, 17 }, /* 8 - 15 */
{ 697, 4, 17 },
{ 987, 3, 17 },
{ 820, 4, 17 },
{ 670, 5, 17 },
{ 697, 5, 17 },
{ 733, 5, 17 },
{ 615, 6, 17 },
{ 462, 8, 17 }, /* 016-023 */
{ 306, 8, 26 },
{ 615, 4, 26 },
{ 1024, 4, 17 },
{ 855, 5, 17 },
{ 925, 5, 17 },
{ 932, 5, 17 },
{ 1024, 2, 40 },
{ 809, 6, 17 }, /* 024-031 */
{ 976, 5, 17 },
{ 977, 5, 17 },
{ 698, 7, 17 },
{ 699, 7, 17 },
{ 981, 5, 17 },
{ 615, 8, 17 },
{ 989, 5, 17 },
{ 820, 4, 26 }, /* 032-039 */
{ 1024, 5, 17 },
{ 733, 7, 17 },
{ 754, 7, 17 },
{ 733, 5, 26 },
{ 940, 6, 17 },
{ 615, 6, 26 },
{ 462, 8, 26 },
{ 830, 7, 17 }, /* 040-047 */
{ 855, 7, 17 },
{ 751, 8, 17 },
{ 1024, 4, 26 },
{ 918, 7, 17 },
{ 925, 7, 17 },
{ 855, 5, 26 },
{ 977, 7, 17 },
{ 987, 7, 17 }, /* 048-055 */
{ 1024, 7, 17 },
{ 823, 4, 38 },
{ 925, 8, 17 },
{ 809, 6, 26 },
{ 976, 5, 26 },
{ 977, 5, 26 },
{ 698, 7, 26 },
{ 699, 7, 26 }, /* 056-063 */
{ 940, 8, 17 },
{ 615, 8, 26 },
{ 1024, 5, 26 },
{ 733, 7, 26 },
{ 1024, 8, 17 },
{ 823, 10, 17 },
{ 754, 11, 17 },
{ 830, 10, 17 }, /* 064-071 */
{ 925, 9, 17 },
{ 1224, 7, 17 },
{ 940, 6, 26 },
{ 855, 7, 26 },
{ 751, 8, 26 },
{ 1024, 9, 17 },
{ 965, 10, 17 },
{ 969, 5, 34 }, /* 072-079 */
{ 980, 10, 17 },
{ 960, 5, 35 },
{ 918, 11, 17 },
{ 1024, 10, 17 },
{ 977, 7, 26 },
{ 1024, 7, 26 },
{ 1024, 11, 17 },
{ 940, 8, 26 }, /* 080-087 */
{ 776, 8, 33 },
{ 755, 16, 17 },
{ 1024, 12, 17 },
{ 1024, 8, 26 },
{ 823, 10, 26 },
{ 830, 10, 26 },
{ 925, 9, 26 },
{ 960, 9, 26 }, /* 088-095 */
{ 1024, 13, 17 },
{ 1224, 11, 17 },
{ 900, 15, 17 },
{ 969, 7, 34 },
{ 917, 15, 17 },
{ 918, 15, 17 },
{ 1524, 4, 39 },
{ 1024, 9, 26 }, /* 096-103 */
{ 1024, 14, 17 },
{ 965, 10, 26 },
{ 980, 10, 26 },
{ 1020, 15, 17 },
{ 1023, 15, 17 },
{ 1024, 15, 17 },
{ 1024, 16, 17 },
{ 1224, 15, 17 }, /* 104-111 */
{ 755, 16, 26 },
{ 903, 8, 46 },
{ 984, 10, 34 },
{ 900, 15, 26 },
{ 917, 15, 26 },
{ 1023, 15, 26 },
{ 684, 16, 38 },
{ 1930, 4, 62 }, /* 112-119 */
{ 967, 16, 31 },
{ 1013, 10, 63 },
{ 1218, 15, 36 },
{ 654, 16, 63 },
{ 659, 16, 63 },
{ 702, 16, 63 },
{ 1002, 13, 63 },
{ 854, 16, 63 }, /* 119-127 */
{ 987, 16, 63 },
{ 995, 16, 63 },
{ 1024, 16, 63 },
{ 1036, 16, 63 },
{ 1120, 16, 59 },
{ 1054, 16, 63 },
{ 0, 0, 0 }
// clang-format on
};
``` | /content/code_sandbox/src/disk/hdd_table.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,912 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a generic Magneto-Optical Disk drive
* commands, for both ATAPI and SCSI usage.
*
*
*
* Authors: Natalia Portillo <claunia@claunia.com>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/config.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/scsi.h>
#include <86box/scsi_device.h>
#include <86box/nvr.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/mo.h>
#include <86box/version.h>
#ifdef _WIN32
# include <windows.h>
# include <io.h>
#else
# include <unistd.h>
#endif
#define IDE_ATAPI_IS_EARLY id->sc->pad0
mo_drive_t mo_drives[MO_NUM];
/* Table of all SCSI commands and their flags, needed for the new disc change / not ready handler. */
const uint8_t mo_command_flags[0x100] = {
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x00 */
IMPLEMENTED | ALLOW_UA | NONDATA | SCSI_ONLY, /* 0x01 */
0,
IMPLEMENTED | ALLOW_UA, /* 0x03 */
IMPLEMENTED | CHECK_READY | ALLOW_UA | NONDATA | SCSI_ONLY, /* 0x04 */
0, 0, 0,
IMPLEMENTED | CHECK_READY, /* 0x08 */
0,
IMPLEMENTED | CHECK_READY, /* 0x0A */
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x0B */
0, 0, 0, 0, 0, 0,
IMPLEMENTED | ALLOW_UA, /* 0x12 */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0x13 */
0,
IMPLEMENTED, /* 0x15 */
IMPLEMENTED | SCSI_ONLY, /* 0x16 */
IMPLEMENTED | SCSI_ONLY, /* 0x17 */
0, 0,
IMPLEMENTED, /* 0x1A */
IMPLEMENTED | CHECK_READY, /* 0x1B */
0,
IMPLEMENTED, /* 0x1D */
IMPLEMENTED | CHECK_READY, /* 0x1E */
0, 0, 0, 0, 0, 0,
IMPLEMENTED | CHECK_READY, /* 0x25 */
0, 0,
IMPLEMENTED | CHECK_READY, /* 0x28 */
0,
IMPLEMENTED | CHECK_READY, /* 0x2A */
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x2B */
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x2C */
0,
IMPLEMENTED | CHECK_READY, /* 0x2E */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0x2F */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0,
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
IMPLEMENTED, /* 0x55 */
0, 0, 0, 0,
IMPLEMENTED, /* 0x5A */
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
IMPLEMENTED | CHECK_READY, /* 0xA8 */
0,
IMPLEMENTED | CHECK_READY, /* 0xAA */
0,
IMPLEMENTED | CHECK_READY | NONDATA, /* 0xAC */
0,
IMPLEMENTED | CHECK_READY, /* 0xAE */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0xAF */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0,
0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
static uint64_t mo_mode_sense_page_flags = GPMODEP_ALL_PAGES;
static const mode_sense_pages_t mo_mode_sense_pages_default =
// clang-format off
{ {
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 }
} };
// clang-format on
static const mode_sense_pages_t mo_mode_sense_pages_default_scsi =
// clang-format off
{ {
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 }
} };
// clang-format on
static const mode_sense_pages_t mo_mode_sense_pages_changeable =
// clang-format off
{ {
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 }
} };
// clang-format on
static void mo_command_complete(mo_t *dev);
static void mo_init(mo_t *dev);
#ifdef ENABLE_MO_LOG
int mo_do_log = ENABLE_MO_LOG;
static void
mo_log(const char *fmt, ...)
{
va_list ap;
if (mo_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mo_log(fmt, ...)
#endif
int
find_mo_for_channel(uint8_t channel)
{
for (uint8_t i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel == channel))
return i;
}
return 0xff;
}
static int
mo_load_abort(mo_t *dev)
{
if (dev->drv->fp)
fclose(dev->drv->fp);
dev->drv->fp = NULL;
dev->drv->medium_size = 0;
dev->drv->sector_size = 0;
mo_eject(dev->id); /* Make sure the host OS knows we've rejected (and ejected) the image. */
return 0;
}
int
image_is_mdi(const char *s)
{
if (!strcasecmp(path_get_extension((char *) s), "MDI"))
return 1;
else
return 0;
}
int
mo_load(mo_t *dev, char *fn)
{
int is_mdi;
uint32_t size = 0;
unsigned int found = 0;
if (!dev->drv) {
mo_eject(dev->id);
return 0;
}
is_mdi = image_is_mdi(fn);
dev->drv->fp = plat_fopen(fn, dev->drv->read_only ? "rb" : "rb+");
if (!dev->drv->fp) {
if (!dev->drv->read_only) {
dev->drv->fp = plat_fopen(fn, "rb");
if (dev->drv->fp)
dev->drv->read_only = 1;
else
return mo_load_abort(dev);
} else
return mo_load_abort(dev);
}
fseek(dev->drv->fp, 0, SEEK_END);
size = (uint32_t) ftell(dev->drv->fp);
if (is_mdi) {
/* This is a MDI image. */
size -= 0x1000LL;
dev->drv->base = 0x1000;
}
for (uint8_t i = 0; i < KNOWN_MO_TYPES; i++) {
if (size == (mo_types[i].sectors * mo_types[i].bytes_per_sector)) {
found = 1;
dev->drv->medium_size = mo_types[i].sectors;
dev->drv->sector_size = mo_types[i].bytes_per_sector;
break;
}
}
if (!found)
return mo_load_abort(dev);
if (fseek(dev->drv->fp, dev->drv->base, SEEK_SET) == -1)
fatal("mo_load(): Error seeking to the beginning of the file\n");
strncpy(dev->drv->image_path, fn, sizeof(dev->drv->image_path) - 1);
return 1;
}
void
mo_disk_reload(mo_t *dev)
{
int ret = 0;
if (strlen(dev->drv->prev_image_path) == 0)
return;
else
ret = mo_load(dev, dev->drv->prev_image_path);
if (ret)
dev->unit_attention = 1;
}
void
mo_disk_unload(mo_t *dev)
{
if (dev->drv && dev->drv->fp) {
fclose(dev->drv->fp);
dev->drv->fp = NULL;
}
}
void
mo_disk_close(mo_t *dev)
{
if (dev->drv && dev->drv->fp) {
mo_disk_unload(dev);
memcpy(dev->drv->prev_image_path, dev->drv->image_path, sizeof(dev->drv->prev_image_path));
memset(dev->drv->image_path, 0, sizeof(dev->drv->image_path));
dev->drv->medium_size = 0;
}
}
static void
mo_set_callback(mo_t *dev)
{
if (dev->drv->bus_type != MO_BUS_SCSI)
ide_set_callback(ide_drives[dev->drv->ide_channel], dev->callback);
}
static void
mo_init(mo_t *dev)
{
if (dev->id >= MO_NUM)
return;
dev->requested_blocks = 1;
dev->sense[0] = 0xf0;
dev->sense[7] = 10;
dev->drv->bus_mode = 0;
if (dev->drv->bus_type >= MO_BUS_ATAPI)
dev->drv->bus_mode |= 2;
if (dev->drv->bus_type < MO_BUS_SCSI)
dev->drv->bus_mode |= 1;
mo_log("MO %i: Bus type %i, bus mode %i\n", dev->id, dev->drv->bus_type, dev->drv->bus_mode);
if (dev->drv->bus_type < MO_BUS_SCSI) {
dev->tf->phase = 1;
dev->tf->request_length = 0xEB14;
}
dev->tf->status = READY_STAT | DSC_STAT;
dev->tf->pos = 0;
dev->packet_status = PHASE_NONE;
mo_sense_key = mo_asc = mo_ascq = dev->unit_attention = 0;
}
static int
mo_supports_pio(mo_t *dev)
{
return (dev->drv->bus_mode & 1);
}
static int
mo_supports_dma(mo_t *dev)
{
return (dev->drv->bus_mode & 2);
}
/* Returns: 0 for none, 1 for PIO, 2 for DMA. */
static int
mo_current_mode(mo_t *dev)
{
if (!mo_supports_pio(dev) && !mo_supports_dma(dev))
return 0;
if (mo_supports_pio(dev) && !mo_supports_dma(dev)) {
mo_log("MO %i: Drive does not support DMA, setting to PIO\n", dev->id);
return 1;
}
if (!mo_supports_pio(dev) && mo_supports_dma(dev))
return 2;
if (mo_supports_pio(dev) && mo_supports_dma(dev)) {
mo_log("MO %i: Drive supports both, setting to %s\n", dev->id,
(dev->tf->features & 1) ? "DMA" : "PIO");
return (dev->tf->features & 1) ? 2 : 1;
}
return 0;
}
static void
mo_mode_sense_load(mo_t *dev)
{
FILE *fp;
char fn[512];
memset(&dev->ms_pages_saved, 0, sizeof(mode_sense_pages_t));
if (mo_drives[dev->id].bus_type == MO_BUS_SCSI)
memcpy(&dev->ms_pages_saved, &mo_mode_sense_pages_default_scsi, sizeof(mode_sense_pages_t));
else
memcpy(&dev->ms_pages_saved, &mo_mode_sense_pages_default, sizeof(mode_sense_pages_t));
memset(fn, 0, 512);
if (dev->drv->bus_type == MO_BUS_SCSI)
sprintf(fn, "scsi_mo_%02i_mode_sense_bin", dev->id);
else
sprintf(fn, "mo_%02i_mode_sense_bin", dev->id);
fp = plat_fopen(nvr_path(fn), "rb");
if (fp) {
/* Nothing to read, not used by MO. */
fclose(fp);
}
}
static void
mo_mode_sense_save(mo_t *dev)
{
FILE *fp;
char fn[512];
memset(fn, 0, 512);
if (dev->drv->bus_type == MO_BUS_SCSI)
sprintf(fn, "scsi_mo_%02i_mode_sense_bin", dev->id);
else
sprintf(fn, "mo_%02i_mode_sense_bin", dev->id);
fp = plat_fopen(nvr_path(fn), "wb");
if (fp) {
/* Nothing to write, not used by MO. */
fclose(fp);
}
}
/*SCSI Mode Sense 6/10*/
static uint8_t
mo_mode_sense_read(mo_t *dev, uint8_t page_control, uint8_t page, uint8_t pos)
{
switch (page_control) {
case 0:
case 3:
return dev->ms_pages_saved.pages[page][pos];
case 1:
return mo_mode_sense_pages_changeable.pages[page][pos];
case 2:
if (dev->drv->bus_type == MO_BUS_SCSI)
return mo_mode_sense_pages_default_scsi.pages[page][pos];
else
return mo_mode_sense_pages_default.pages[page][pos];
default:
break;
}
return 0;
}
static uint32_t
mo_mode_sense(mo_t *dev, uint8_t *buf, uint32_t pos, uint8_t page, uint8_t block_descriptor_len)
{
uint64_t pf;
uint8_t page_control = (page >> 6) & 3;
pf = mo_mode_sense_page_flags;
uint8_t msplen;
page &= 0x3f;
if (block_descriptor_len) {
buf[pos++] = ((dev->drv->medium_size >> 24) & 0xff);
buf[pos++] = ((dev->drv->medium_size >> 16) & 0xff);
buf[pos++] = ((dev->drv->medium_size >> 8) & 0xff);
buf[pos++] = (dev->drv->medium_size & 0xff);
buf[pos++] = 0; /* Reserved. */
buf[pos++] = 0;
buf[pos++] = ((dev->drv->sector_size >> 8) & 0xff);
buf[pos++] = (dev->drv->sector_size & 0xff);
}
for (uint8_t i = 0; i < 0x40; i++) {
if ((page == GPMODE_ALL_PAGES) || (page == i)) {
if (pf & (1LL << ((uint64_t) page))) {
buf[pos++] = mo_mode_sense_read(dev, page_control, i, 0);
msplen = mo_mode_sense_read(dev, page_control, i, 1);
buf[pos++] = msplen;
mo_log("MO %i: MODE SENSE: Page [%02X] length %i\n", dev->id, i, msplen);
for (uint8_t j = 0; j < msplen; j++)
buf[pos++] = mo_mode_sense_read(dev, page_control, i, 2 + j);
}
}
}
return pos;
}
static void
mo_update_request_length(mo_t *dev, int len, int block_len)
{
int bt;
int min_len = 0;
dev->max_transfer_len = dev->tf->request_length;
/* For media access commands, make sure the requested DRQ length matches the block length. */
switch (dev->current_cdb[0]) {
case 0x08:
case 0x0a:
case 0x28:
case 0x2a:
case 0xa8:
case 0xaa:
/* Round it to the nearest 2048 bytes. */
dev->max_transfer_len = (dev->max_transfer_len >> 9) << 9;
/* Make sure total length is not bigger than sum of the lengths of
all the requested blocks. */
bt = (dev->requested_blocks * block_len);
if (len > bt)
len = bt;
min_len = block_len;
if (len <= block_len) {
/* Total length is less or equal to block length. */
if (dev->max_transfer_len < block_len) {
/* Transfer a minimum of (block size) bytes. */
dev->max_transfer_len = block_len;
dev->packet_len = block_len;
break;
}
}
fallthrough;
default:
dev->packet_len = len;
break;
}
/* If the DRQ length is odd, and the total remaining length is bigger, make sure it's even. */
if ((dev->max_transfer_len & 1) && (dev->max_transfer_len < len))
dev->max_transfer_len &= 0xfffe;
/* If the DRQ length is smaller or equal in size to the total remaining length, set it to that. */
if (!dev->max_transfer_len)
dev->max_transfer_len = 65534;
if ((len <= dev->max_transfer_len) && (len >= min_len))
dev->tf->request_length = dev->max_transfer_len = len;
else if (len > dev->max_transfer_len)
dev->tf->request_length = dev->max_transfer_len;
return;
}
static double
mo_bus_speed(mo_t *dev)
{
double ret = -1.0;
if (dev && dev->drv && (dev->drv->bus_type == MO_BUS_SCSI)) {
dev->callback = -1.0; /* Speed depends on SCSI controller */
return 0.0;
} else {
if (dev && dev->drv)
ret = ide_atapi_get_period(dev->drv->ide_channel);
if (ret == -1.0) {
if (dev)
dev->callback = -1.0;
return 0.0;
} else
return ret * 1000000.0;
}
}
static void
mo_command_common(mo_t *dev)
{
double bytes_per_second;
double period;
dev->tf->status = BUSY_STAT;
dev->tf->phase = 1;
dev->tf->pos = 0;
if (dev->packet_status == PHASE_COMPLETE)
dev->callback = 0.0;
else {
if (dev->drv->bus_type == MO_BUS_SCSI) {
dev->callback = -1.0; /* Speed depends on SCSI controller */
return;
} else
bytes_per_second = mo_bus_speed(dev);
period = 1000000.0 / bytes_per_second;
dev->callback = period * (double) (dev->packet_len);
}
mo_set_callback(dev);
}
static void
mo_command_complete(mo_t *dev)
{
dev->packet_status = PHASE_COMPLETE;
mo_command_common(dev);
}
static void
mo_command_read(mo_t *dev)
{
dev->packet_status = PHASE_DATA_IN;
mo_command_common(dev);
}
static void
mo_command_read_dma(mo_t *dev)
{
dev->packet_status = PHASE_DATA_IN_DMA;
mo_command_common(dev);
}
static void
mo_command_write(mo_t *dev)
{
dev->packet_status = PHASE_DATA_OUT;
mo_command_common(dev);
}
static void
mo_command_write_dma(mo_t *dev)
{
dev->packet_status = PHASE_DATA_OUT_DMA;
mo_command_common(dev);
}
/* id = Current MO device ID;
len = Total transfer length;
block_len = Length of a single block (why does it matter?!);
alloc_len = Allocated transfer length;
direction = Transfer direction (0 = read from host, 1 = write to host). */
static void
mo_data_command_finish(mo_t *dev, int len, int block_len, int alloc_len, int direction)
{
mo_log("MO %i: Finishing command (%02X): %i, %i, %i, %i, %i\n",
dev->id, dev->current_cdb[0], len, block_len, alloc_len, direction, dev->tf->request_length);
dev->tf->pos = 0;
if (alloc_len >= 0) {
if (alloc_len < len)
len = alloc_len;
}
if ((len == 0) || (mo_current_mode(dev) == 0)) {
if (dev->drv->bus_type != MO_BUS_SCSI)
dev->packet_len = 0;
mo_command_complete(dev);
} else {
if (mo_current_mode(dev) == 2) {
if (dev->drv->bus_type != MO_BUS_SCSI)
dev->packet_len = alloc_len;
if (direction == 0)
mo_command_read_dma(dev);
else
mo_command_write_dma(dev);
} else {
mo_update_request_length(dev, len, block_len);
if (direction == 0)
mo_command_read(dev);
else
mo_command_write(dev);
}
}
mo_log("MO %i: Status: %i, cylinder %i, packet length: %i, position: %i, phase: %i\n",
dev->id, dev->packet_status, dev->tf->request_length, dev->packet_len, dev->tf->pos,
dev->tf->phase);
}
static void
mo_sense_clear(mo_t *dev, UNUSED(int command))
{
mo_sense_key = mo_asc = mo_ascq = 0;
}
static void
mo_set_phase(mo_t *dev, uint8_t phase)
{
uint8_t scsi_bus = (dev->drv->scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_device_id & 0x0f;
if (dev->drv->bus_type != MO_BUS_SCSI)
return;
scsi_devices[scsi_bus][scsi_id].phase = phase;
}
static void
mo_cmd_error(mo_t *dev)
{
mo_set_phase(dev, SCSI_PHASE_STATUS);
dev->tf->error = ((mo_sense_key & 0xf) << 4) | ABRT_ERR;
if (dev->unit_attention)
dev->tf->error |= MCR_ERR;
dev->tf->status = READY_STAT | ERR_STAT;
dev->tf->phase = 3;
dev->tf->pos = 0;
dev->packet_status = PHASE_ERROR;
dev->callback = 50.0 * MO_TIME;
mo_set_callback(dev);
ui_sb_update_icon(SB_MO | dev->id, 0);
mo_log("MO %i: [%02X] ERROR: %02X/%02X/%02X\n", dev->id, dev->current_cdb[0], mo_sense_key, mo_asc, mo_ascq);
}
static void
mo_unit_attention(mo_t *dev)
{
mo_set_phase(dev, SCSI_PHASE_STATUS);
dev->tf->error = (SENSE_UNIT_ATTENTION << 4) | ABRT_ERR;
if (dev->unit_attention)
dev->tf->error |= MCR_ERR;
dev->tf->status = READY_STAT | ERR_STAT;
dev->tf->phase = 3;
dev->tf->pos = 0;
dev->packet_status = PHASE_ERROR;
dev->callback = 50.0 * MO_TIME;
mo_set_callback(dev);
ui_sb_update_icon(SB_MO | dev->id, 0);
mo_log("MO %i: UNIT ATTENTION\n", dev->id);
}
static void
mo_buf_alloc(mo_t *dev, uint32_t len)
{
mo_log("MO %i: Allocated buffer length: %i\n", dev->id, len);
if (!dev->buffer)
dev->buffer = (uint8_t *) malloc(len);
}
static void
mo_buf_free(mo_t *dev)
{
if (dev->buffer) {
mo_log("MO %i: Freeing buffer...\n", dev->id);
free(dev->buffer);
dev->buffer = NULL;
}
}
static void
mo_bus_master_error(scsi_common_t *sc)
{
mo_t *dev = (mo_t *) sc;
mo_buf_free(dev);
mo_sense_key = mo_asc = mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_not_ready(mo_t *dev)
{
mo_sense_key = SENSE_NOT_READY;
mo_asc = ASC_MEDIUM_NOT_PRESENT;
mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_write_protected(mo_t *dev)
{
mo_sense_key = SENSE_UNIT_ATTENTION;
mo_asc = ASC_WRITE_PROTECTED;
mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_invalid_lun(mo_t *dev)
{
mo_sense_key = SENSE_ILLEGAL_REQUEST;
mo_asc = ASC_INV_LUN;
mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_illegal_opcode(mo_t *dev)
{
mo_sense_key = SENSE_ILLEGAL_REQUEST;
mo_asc = ASC_ILLEGAL_OPCODE;
mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_lba_out_of_range(mo_t *dev)
{
mo_sense_key = SENSE_ILLEGAL_REQUEST;
mo_asc = ASC_LBA_OUT_OF_RANGE;
mo_ascq = 0;
mo_cmd_error(dev);
}
static void
mo_invalid_field(mo_t *dev)
{
mo_sense_key = SENSE_ILLEGAL_REQUEST;
mo_asc = ASC_INV_FIELD_IN_CMD_PACKET;
mo_ascq = 0;
mo_cmd_error(dev);
dev->tf->status = 0x53;
}
static void
mo_invalid_field_pl(mo_t *dev)
{
mo_sense_key = SENSE_ILLEGAL_REQUEST;
mo_asc = ASC_INV_FIELD_IN_PARAMETER_LIST;
mo_ascq = 0;
mo_cmd_error(dev);
dev->tf->status = 0x53;
}
static int
mo_blocks(mo_t *dev, int32_t *len, UNUSED(int first_batch), int out)
{
*len = 0;
if (!dev->sector_len) {
mo_command_complete(dev);
return -1;
}
mo_log("%sing %i blocks starting from %i...\n", out ? "Writ" : "Read", dev->requested_blocks, dev->sector_pos);
if (dev->sector_pos >= dev->drv->medium_size) {
mo_log("MO %i: Trying to %s beyond the end of disk\n", dev->id, out ? "write" : "read");
mo_lba_out_of_range(dev);
return 0;
}
*len = dev->requested_blocks * dev->drv->sector_size;
for (int i = 0; i < dev->requested_blocks; i++) {
if (fseek(dev->drv->fp, dev->drv->base + (dev->sector_pos * dev->drv->sector_size) + (i * dev->drv->sector_size), SEEK_SET) == 1)
break;
if (feof(dev->drv->fp))
break;
if (out) {
if (fwrite(dev->buffer + (i * dev->drv->sector_size), 1, dev->drv->sector_size, dev->drv->fp) != dev->drv->sector_size)
fatal("mo_blocks(): Error writing data\n");
} else {
if (fread(dev->buffer + (i * dev->drv->sector_size), 1, dev->drv->sector_size, dev->drv->fp) != dev->drv->sector_size)
fatal("mo_blocks(): Error reading data\n");
}
}
mo_log("%s %i bytes of blocks...\n", out ? "Written" : "Read", *len);
dev->sector_pos += dev->requested_blocks;
dev->sector_len -= dev->requested_blocks;
return 1;
}
void
mo_insert(mo_t *dev)
{
dev->unit_attention = 1;
}
void
mo_format(mo_t *dev)
{
long size;
int ret;
int fd;
mo_log("MO %i: Formatting media...\n", dev->id);
fseek(dev->drv->fp, 0, SEEK_END);
size = ftell(dev->drv->fp);
#ifdef _WIN32
HANDLE fh;
LARGE_INTEGER liSize;
fd = _fileno(dev->drv->fp);
fh = (HANDLE) _get_osfhandle(fd);
liSize.QuadPart = 0;
ret = (int) SetFilePointerEx(fh, liSize, NULL, FILE_BEGIN);
if (!ret) {
mo_log("MO %i: Failed seek to start of image file\n", dev->id);
return;
}
ret = (int) SetEndOfFile(fh);
if (!ret) {
mo_log("MO %i: Failed to truncate image file to 0\n", dev->id);
return;
}
liSize.QuadPart = size;
ret = (int) SetFilePointerEx(fh, liSize, NULL, FILE_BEGIN);
if (!ret) {
mo_log("MO %i: Failed seek to end of image file\n", dev->id);
return;
}
ret = (int) SetEndOfFile(fh);
if (!ret) {
mo_log("MO %i: Failed to truncate image file to %llu\n", dev->id, size);
return;
}
#else
fd = fileno(dev->drv->fp);
ret = ftruncate(fd, 0);
if (ret) {
mo_log("MO %i: Failed to truncate image file to 0\n", dev->id);
return;
}
ret = ftruncate(fd, size);
if (ret) {
mo_log("MO %i: Failed to truncate image file to %llu", dev->id, size);
return;
}
#endif
}
static int
mo_erase(mo_t *dev)
{
int i;
if (!dev->sector_len) {
mo_command_complete(dev);
return -1;
}
mo_log("MO %i: Erasing %i blocks starting from %i...\n", dev->id, dev->sector_len, dev->sector_pos);
if (dev->sector_pos >= dev->drv->medium_size) {
mo_log("MO %i: Trying to erase beyond the end of disk\n", dev->id);
mo_lba_out_of_range(dev);
return 0;
}
mo_buf_alloc(dev, dev->drv->sector_size);
memset(dev->buffer, 0, dev->drv->sector_size);
fseek(dev->drv->fp, dev->drv->base + (dev->sector_pos * dev->drv->sector_size), SEEK_SET);
for (i = 0; i < dev->requested_blocks; i++) {
if (feof(dev->drv->fp))
break;
fwrite(dev->buffer, 1, dev->drv->sector_size, dev->drv->fp);
}
mo_log("MO %i: Erased %i bytes of blocks...\n", dev->id, i * dev->drv->sector_size);
dev->sector_pos += i;
dev->sector_len -= i;
return 1;
}
/*SCSI Sense Initialization*/
void
mo_sense_code_ok(mo_t *dev)
{
mo_sense_key = SENSE_NONE;
mo_asc = 0;
mo_ascq = 0;
}
static int
mo_pre_execution_check(mo_t *dev, uint8_t *cdb)
{
int ready = 0;
if ((cdb[0] != GPCMD_REQUEST_SENSE) && (dev->cur_lun == SCSI_LUN_USE_CDB) && (cdb[1] & 0xe0)) {
mo_log("MO %i: Attempting to execute a unknown command targeted at SCSI LUN %i\n", dev->id,
((dev->tf->request_length >> 5) & 7));
mo_invalid_lun(dev);
return 0;
}
if (!(mo_command_flags[cdb[0]] & IMPLEMENTED)) {
mo_log("MO %i: Attempting to execute unknown command %02X over %s\n", dev->id, cdb[0],
(dev->drv->bus_type == MO_BUS_SCSI) ? "SCSI" : "ATAPI");
mo_illegal_opcode(dev);
return 0;
}
if ((dev->drv->bus_type < MO_BUS_SCSI) && (mo_command_flags[cdb[0]] & SCSI_ONLY)) {
mo_log("MO %i: Attempting to execute SCSI-only command %02X over ATAPI\n", dev->id, cdb[0]);
mo_illegal_opcode(dev);
return 0;
}
if ((dev->drv->bus_type == MO_BUS_SCSI) && (mo_command_flags[cdb[0]] & ATAPI_ONLY)) {
mo_log("MO %i: Attempting to execute ATAPI-only command %02X over SCSI\n", dev->id, cdb[0]);
mo_illegal_opcode(dev);
return 0;
}
ready = (dev->drv->fp != NULL);
/* If the drive is not ready, there is no reason to keep the
UNIT ATTENTION condition present, as we only use it to mark
disc changes. */
if (!ready && dev->unit_attention)
dev->unit_attention = 0;
/* If the UNIT ATTENTION condition is set and the command does not allow
execution under it, error out and report the condition. */
if (dev->unit_attention == 1) {
/* Only increment the unit attention phase if the command can not pass through it. */
if (!(mo_command_flags[cdb[0]] & ALLOW_UA)) {
/* mo_log("MO %i: Unit attention now 2\n", dev->id); */
dev->unit_attention = 2;
mo_log("MO %i: UNIT ATTENTION: Command %02X not allowed to pass through\n", dev->id, cdb[0]);
mo_unit_attention(dev);
return 0;
}
} else if (dev->unit_attention == 2) {
if (cdb[0] != GPCMD_REQUEST_SENSE) {
/* mo_log("MO %i: Unit attention now 0\n", dev->id); */
dev->unit_attention = 0;
}
}
/* Unless the command is REQUEST SENSE, clear the sense. This will *NOT*
the UNIT ATTENTION condition if it's set. */
if (cdb[0] != GPCMD_REQUEST_SENSE)
mo_sense_clear(dev, cdb[0]);
/* Next it's time for NOT READY. */
if ((mo_command_flags[cdb[0]] & CHECK_READY) && !ready) {
mo_log("MO %i: Not ready (%02X)\n", dev->id, cdb[0]);
mo_not_ready(dev);
return 0;
}
mo_log("MO %i: Continuing with command %02X\n", dev->id, cdb[0]);
return 1;
}
static void
mo_seek(mo_t *dev, uint32_t pos)
{
#if 0
mo_log("MO %i: Seek %08X\n", dev->id, pos);
#endif
dev->sector_pos = pos;
}
static void
mo_rezero(mo_t *dev)
{
dev->sector_pos = dev->sector_len = 0;
mo_seek(dev, 0);
}
void
mo_reset(scsi_common_t *sc)
{
mo_t *dev = (mo_t *) sc;
mo_rezero(dev);
dev->tf->status = 0;
dev->callback = 0.0;
mo_set_callback(dev);
dev->tf->phase = 1;
dev->tf->request_length = 0xEB14;
dev->packet_status = PHASE_NONE;
dev->unit_attention = 0;
dev->cur_lun = SCSI_LUN_USE_CDB;
}
static void
mo_request_sense(mo_t *dev, uint8_t *buffer, uint8_t alloc_length, int desc)
{
/*Will return 18 bytes of 0*/
if (alloc_length != 0) {
memset(buffer, 0, alloc_length);
if (!desc)
memcpy(buffer, dev->sense, alloc_length);
else {
buffer[1] = mo_sense_key;
buffer[2] = mo_asc;
buffer[3] = mo_ascq;
}
}
buffer[0] = desc ? 0x72 : 0x70;
if (dev->unit_attention && (mo_sense_key == 0)) {
buffer[desc ? 1 : 2] = SENSE_UNIT_ATTENTION;
buffer[desc ? 2 : 12] = ASC_MEDIUM_MAY_HAVE_CHANGED;
buffer[desc ? 3 : 13] = 0;
}
mo_log("MO %i: Reporting sense: %02X %02X %02X\n", dev->id, buffer[2], buffer[12], buffer[13]);
if (buffer[desc ? 1 : 2] == SENSE_UNIT_ATTENTION) {
/* If the last remaining sense is unit attention, clear
that condition. */
dev->unit_attention = 0;
}
/* Clear the sense stuff as per the spec. */
mo_sense_clear(dev, GPCMD_REQUEST_SENSE);
}
static void
mo_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t alloc_length)
{
mo_t *dev = (mo_t *) sc;
int ready = 0;
ready = (dev->drv->fp != NULL);
if (!ready && dev->unit_attention) {
/* If the drive is not ready, there is no reason to keep the
UNIT ATTENTION condition present, as we only use it to mark
disc changes. */
dev->unit_attention = 0;
}
/* Do *NOT* advance the unit attention phase. */
mo_request_sense(dev, buffer, alloc_length, 0);
}
static void
mo_set_buf_len(mo_t *dev, int32_t *BufLen, int32_t *src_len)
{
if (dev->drv->bus_type == MO_BUS_SCSI) {
if (*BufLen == -1)
*BufLen = *src_len;
else {
*BufLen = MIN(*src_len, *BufLen);
*src_len = *BufLen;
}
mo_log("MO %i: Actual transfer length: %i\n", dev->id, *BufLen);
}
}
static void
mo_command(scsi_common_t *sc, uint8_t *cdb)
{
mo_t *dev = (mo_t *) sc;
int pos = 0;
int block_desc = 0;
int ret;
int32_t len;
int32_t max_len;
int32_t alloc_length;
int size_idx;
int idx = 0;
unsigned preamble_len;
char device_identify[9] = { '8', '6', 'B', '_', 'M', 'O', '0', '0', 0 };
int32_t blen = 0;
int32_t *BufLen;
uint32_t previous_pos = 0;
uint8_t scsi_bus = (dev->drv->scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_device_id & 0x0f;
if (dev->drv->bus_type == MO_BUS_SCSI) {
BufLen = &scsi_devices[scsi_bus][scsi_id].buffer_length;
dev->tf->status &= ~ERR_STAT;
} else {
BufLen = &blen;
dev->tf->error = 0;
}
dev->packet_len = 0;
dev->request_pos = 0;
device_identify[7] = dev->id + 0x30;
memcpy(dev->current_cdb, cdb, 12);
if (cdb[0] != 0) {
mo_log("MO %i: Command 0x%02X, Sense Key %02X, Asc %02X, Ascq %02X, Unit attention: %i\n",
dev->id, cdb[0], mo_sense_key, mo_asc, mo_ascq, dev->unit_attention);
mo_log("MO %i: Request length: %04X\n", dev->id, dev->tf->request_length);
mo_log("MO %i: CDB: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", dev->id,
cdb[0], cdb[1], cdb[2], cdb[3], cdb[4], cdb[5], cdb[6], cdb[7],
cdb[8], cdb[9], cdb[10], cdb[11]);
}
dev->sector_len = 0;
mo_set_phase(dev, SCSI_PHASE_STATUS);
/* This handles the Not Ready/Unit Attention check if it has to be handled at this point. */
if (mo_pre_execution_check(dev, cdb) == 0)
return;
switch (cdb[0]) {
case GPCMD_SEND_DIAGNOSTIC:
if (!(cdb[1] & (1 << 2))) {
mo_invalid_field(dev);
return;
}
fallthrough;
case GPCMD_SCSI_RESERVE:
case GPCMD_SCSI_RELEASE:
case GPCMD_TEST_UNIT_READY:
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
case GPCMD_FORMAT_UNIT:
if (dev->drv->read_only) {
mo_write_protected(dev);
return;
}
mo_format(dev);
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
case GPCMD_REZERO_UNIT:
dev->sector_pos = dev->sector_len = 0;
mo_seek(dev, 0);
mo_set_phase(dev, SCSI_PHASE_STATUS);
break;
case GPCMD_REQUEST_SENSE:
/* If there's a unit attention condition and there's a buffered not ready, a standalone REQUEST SENSE
should forget about the not ready, and report unit attention straight away. */
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[4];
if (!max_len) {
mo_set_phase(dev, SCSI_PHASE_STATUS);
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * MO_TIME;
mo_set_callback(dev);
break;
}
mo_buf_alloc(dev, 256);
mo_set_buf_len(dev, BufLen, &max_len);
len = (cdb[1] & 1) ? 8 : 18;
mo_request_sense(dev, dev->buffer, max_len, cdb[1] & 1);
mo_data_command_finish(dev, len, len, cdb[4], 0);
break;
case GPCMD_MECHANISM_STATUS:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
len = (cdb[8] << 8) | cdb[9];
mo_buf_alloc(dev, 8);
mo_set_buf_len(dev, BufLen, &len);
memset(dev->buffer, 0, 8);
dev->buffer[5] = 1;
mo_data_command_finish(dev, 8, 8, len, 0);
break;
case GPCMD_READ_6:
case GPCMD_READ_10:
case GPCMD_READ_12:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
alloc_length = dev->drv->sector_size;
switch (cdb[0]) {
case GPCMD_READ_6:
dev->sector_len = cdb[4];
dev->sector_pos = ((((uint32_t) cdb[1]) & 0x1f) << 16) | (((uint32_t) cdb[2]) << 8) | ((uint32_t) cdb[3]);
if (dev->sector_len == 0)
dev->sector_len = 256;
mo_log("MO %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_READ_10:
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
mo_log("MO %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_READ_12:
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) | (((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) | (((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
mo_log("MO %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
default:
break;
}
if (!dev->sector_len) {
mo_set_phase(dev, SCSI_PHASE_STATUS);
/* mo_log("MO %i: All done - callback set\n", dev->id); */
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * MO_TIME;
mo_set_callback(dev);
break;
}
max_len = dev->sector_len;
dev->requested_blocks = max_len; /* If we're reading all blocks in one go for DMA, why not also for PIO, it should NOT
matter anyway, this step should be identical and only the way the read dat is
transferred to the host should be different. */
dev->packet_len = max_len * alloc_length;
mo_buf_alloc(dev, dev->packet_len);
ret = mo_blocks(dev, &alloc_length, 1, 0);
if (ret <= 0) {
mo_set_phase(dev, SCSI_PHASE_STATUS);
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * MO_TIME;
mo_set_callback(dev);
mo_buf_free(dev);
return;
}
dev->requested_blocks = max_len;
dev->packet_len = alloc_length;
mo_set_buf_len(dev, BufLen, (int32_t *) &dev->packet_len);
mo_data_command_finish(dev, alloc_length, dev->drv->sector_size, alloc_length, 0);
if (dev->packet_status != PHASE_COMPLETE)
ui_sb_update_icon(SB_MO | dev->id, 1);
else
ui_sb_update_icon(SB_MO | dev->id, 0);
return;
case GPCMD_VERIFY_6:
case GPCMD_VERIFY_10:
case GPCMD_VERIFY_12:
/* Data and blank verification cannot be set at the same time */
if ((cdb[1] & 2) && (cdb[1] & 4)) {
mo_invalid_field(dev);
return;
}
if (!(cdb[1] & 2) || (cdb[1] & 4)) {
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
}
/*TODO: Implement*/
mo_invalid_field(dev);
return;
case GPCMD_WRITE_6:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
mo_set_phase(dev, SCSI_PHASE_DATA_OUT);
alloc_length = dev->drv->sector_size;
if (dev->drv->read_only) {
mo_write_protected(dev);
return;
}
switch (cdb[0]) {
case GPCMD_VERIFY_6:
case GPCMD_WRITE_6:
dev->sector_len = cdb[4];
if (dev->sector_len == 0)
dev->sector_len = 256; /* For READ (6) and WRITE (6), a length of 0 indicates a transfer of 256 sector. */
dev->sector_pos = ((((uint32_t) cdb[1]) & 0x1f) << 16) | (((uint32_t) cdb[2]) << 8) | ((uint32_t) cdb[3]);
break;
case GPCMD_VERIFY_10:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
mo_log("MO %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_VERIFY_12:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) | (((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) | (((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
if ((dev->sector_pos >= dev->drv->medium_size) /* ||
((dev->sector_pos + dev->sector_len - 1) >= dev->drv->medium_size)*/
) {
mo_lba_out_of_range(dev);
return;
}
if (!dev->sector_len) {
mo_set_phase(dev, SCSI_PHASE_STATUS);
/* mo_log("MO %i: All done - callback set\n", dev->id); */
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * MO_TIME;
mo_set_callback(dev);
break;
}
max_len = dev->sector_len;
dev->requested_blocks = max_len; /* If we're writing all blocks in one go for DMA, why not also for PIO, it should NOT
matter anyway, this step should be identical and only the way the read dat is
transferred to the host should be different. */
dev->packet_len = max_len * alloc_length;
mo_buf_alloc(dev, dev->packet_len);
dev->requested_blocks = max_len;
dev->packet_len = max_len << 9;
mo_set_buf_len(dev, BufLen, (int32_t *) &dev->packet_len);
mo_data_command_finish(dev, dev->packet_len, dev->drv->sector_size, dev->packet_len, 1);
if (dev->packet_status != PHASE_COMPLETE)
ui_sb_update_icon(SB_MO | dev->id, 1);
else
ui_sb_update_icon(SB_MO | dev->id, 0);
return;
case GPCMD_MODE_SENSE_6:
case GPCMD_MODE_SENSE_10:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
if (dev->drv->bus_type == MO_BUS_SCSI)
block_desc = ((cdb[1] >> 3) & 1) ? 0 : 1;
else
block_desc = 0;
if (cdb[0] == GPCMD_MODE_SENSE_6) {
len = cdb[4];
mo_buf_alloc(dev, 256);
} else {
len = (cdb[8] | (cdb[7] << 8));
mo_buf_alloc(dev, 65536);
}
if (!(mo_mode_sense_page_flags & (1LL << (uint64_t) (cdb[2] & 0x3f)))) {
mo_invalid_field(dev);
mo_buf_free(dev);
return;
}
memset(dev->buffer, 0, len);
alloc_length = len;
if (cdb[0] == GPCMD_MODE_SENSE_6) {
len = mo_mode_sense(dev, dev->buffer, 4, cdb[2], block_desc);
len = MIN(len, alloc_length);
dev->buffer[0] = len - 1;
dev->buffer[1] = 0;
if (block_desc)
dev->buffer[3] = 8;
} else {
len = mo_mode_sense(dev, dev->buffer, 8, cdb[2], block_desc);
len = MIN(len, alloc_length);
dev->buffer[0] = (len - 2) >> 8;
dev->buffer[1] = (len - 2) & 255;
dev->buffer[2] = 0;
if (block_desc) {
dev->buffer[6] = 0;
dev->buffer[7] = 8;
}
}
mo_set_buf_len(dev, BufLen, &len);
mo_log("MO %i: Reading mode page: %02X...\n", dev->id, cdb[2]);
mo_data_command_finish(dev, len, len, alloc_length, 0);
return;
case GPCMD_MODE_SELECT_6:
case GPCMD_MODE_SELECT_10:
mo_set_phase(dev, SCSI_PHASE_DATA_OUT);
if (cdb[0] == GPCMD_MODE_SELECT_6) {
len = cdb[4];
mo_buf_alloc(dev, 256);
} else {
len = (cdb[7] << 8) | cdb[8];
mo_buf_alloc(dev, 65536);
}
mo_set_buf_len(dev, BufLen, &len);
dev->total_length = len;
dev->do_page_save = cdb[1] & 1;
mo_data_command_finish(dev, len, len, len, 1);
return;
case GPCMD_START_STOP_UNIT:
mo_set_phase(dev, SCSI_PHASE_STATUS);
switch (cdb[4] & 3) {
case 0: /* Stop the disk. */
break;
case 1: /* Start the disk and read the TOC. */
break;
case 2: /* Eject the disk if possible. */
mo_eject(dev->id);
break;
case 3: /* Load the disk (close tray). */
mo_reload(dev->id);
break;
default:
break;
}
mo_command_complete(dev);
break;
case GPCMD_INQUIRY:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[3];
max_len <<= 8;
max_len |= cdb[4];
mo_buf_alloc(dev, 65536);
if (cdb[1] & 1) {
preamble_len = 4;
size_idx = 3;
dev->buffer[idx++] = 7; /*Optical disk*/
dev->buffer[idx++] = cdb[2];
dev->buffer[idx++] = 0;
idx++;
switch (cdb[2]) {
case 0x00:
dev->buffer[idx++] = 0x00;
dev->buffer[idx++] = 0x80;
break;
case 0x80: /*Unit serial number page*/
dev->buffer[idx++] = strlen("VCM!10") + 1;
ide_padstr8(dev->buffer + idx, 20, "VCM!10"); /* Serial */
idx += strlen("VCM!10");
break;
default:
mo_log("INQUIRY: Invalid page: %02X\n", cdb[2]);
mo_invalid_field(dev);
mo_buf_free(dev);
return;
}
} else {
preamble_len = 5;
size_idx = 4;
memset(dev->buffer, 0, 8);
if ((cdb[1] & 0xe0) || ((dev->cur_lun > 0x00) && (dev->cur_lun < 0xff)))
dev->buffer[0] = 0x7f; /*No physical device on this LUN*/
else
dev->buffer[0] = 0x07; /*Optical disk*/
dev->buffer[1] = 0x80; /*Removable*/
dev->buffer[2] = (dev->drv->bus_type == MO_BUS_SCSI) ? 0x02 : 0x00; /*SCSI-2 compliant*/
dev->buffer[3] = (dev->drv->bus_type == MO_BUS_SCSI) ? 0x02 : 0x21;
#if 0
dev->buffer[4] = 31;
#endif
dev->buffer[4] = 0;
if (dev->drv->bus_type == MO_BUS_SCSI) {
dev->buffer[6] = 1; /* 16-bit transfers supported */
dev->buffer[7] = 0x20; /* Wide bus supported */
}
dev->buffer[7] |= 0x02;
if (dev->drv->type > 0) {
ide_padstr8(dev->buffer + 8, 8, mo_drive_types[dev->drv->type].vendor); /* Vendor */
ide_padstr8(dev->buffer + 16, 16, mo_drive_types[dev->drv->type].model); /* Product */
ide_padstr8(dev->buffer + 32, 4, mo_drive_types[dev->drv->type].revision); /* Revision */
} else {
ide_padstr8(dev->buffer + 8, 8, EMU_NAME); /* Vendor */
ide_padstr8(dev->buffer + 16, 16, device_identify); /* Product */
ide_padstr8(dev->buffer + 32, 4, EMU_VERSION_EX); /* Revision */
}
idx = 36;
if (max_len == 96) {
dev->buffer[4] = 91;
idx = 96;
} else if (max_len == 128) {
dev->buffer[4] = 0x75;
idx = 128;
}
}
dev->buffer[size_idx] = idx - preamble_len;
len = idx;
len = MIN(len, max_len);
mo_set_buf_len(dev, BufLen, &len);
mo_data_command_finish(dev, len, len, max_len, 0);
break;
case GPCMD_PREVENT_REMOVAL:
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
case GPCMD_SEEK_6:
case GPCMD_SEEK_10:
mo_set_phase(dev, SCSI_PHASE_STATUS);
switch (cdb[0]) {
case GPCMD_SEEK_6:
pos = (cdb[2] << 8) | cdb[3];
break;
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
default:
break;
}
mo_seek(dev, pos);
mo_command_complete(dev);
break;
case GPCMD_READ_CDROM_CAPACITY:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
mo_buf_alloc(dev, 8);
max_len = dev->drv->medium_size - 1; /* IMPORTANT: What's returned is the last LBA block. */
memset(dev->buffer, 0, 8);
dev->buffer[0] = (max_len >> 24) & 0xff;
dev->buffer[1] = (max_len >> 16) & 0xff;
dev->buffer[2] = (max_len >> 8) & 0xff;
dev->buffer[3] = max_len & 0xff;
dev->buffer[6] = (dev->drv->sector_size >> 8) & 0xff;
dev->buffer[7] = dev->drv->sector_size & 0xff;
len = 8;
mo_set_buf_len(dev, BufLen, &len);
mo_data_command_finish(dev, len, len, len, 0);
break;
case GPCMD_ERASE_10:
case GPCMD_ERASE_12:
/*Relative address*/
if (cdb[1] & 1)
previous_pos = dev->sector_pos;
switch (cdb[0]) {
case GPCMD_ERASE_10:
dev->sector_len = (cdb[7] << 8) | cdb[8];
break;
case GPCMD_ERASE_12:
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) | (((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
break;
default:
break;
}
/*Erase all remaining sectors*/
if (cdb[1] & 4) {
/* Cannot have a sector number when erase all*/
if (dev->sector_len) {
mo_invalid_field(dev);
return;
}
mo_format(dev);
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
}
switch (cdb[0]) {
case GPCMD_ERASE_10:
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
case GPCMD_ERASE_12:
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) | (((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
dev->sector_pos += previous_pos;
mo_erase(dev);
mo_set_phase(dev, SCSI_PHASE_STATUS);
mo_command_complete(dev);
break;
/*Never seen media that supports generations but it's interesting to know if any implementation calls this commmand*/
case GPCMD_READ_GENERATION:
mo_set_phase(dev, SCSI_PHASE_DATA_IN);
mo_buf_alloc(dev, 4);
len = 4;
dev->buffer[0] = 0;
dev->buffer[1] = 0;
dev->buffer[2] = 0;
dev->buffer[3] = 0;
mo_set_buf_len(dev, BufLen, &len);
mo_data_command_finish(dev, len, len, len, 0);
break;
default:
mo_illegal_opcode(dev);
break;
}
#if 0
mo_log("MO %i: Phase: %02X, request length: %i\n", dev->id, dev->tf->phase, dev->tf->request_length);
#endif
if ((dev->packet_status == PHASE_COMPLETE) || (dev->packet_status == PHASE_ERROR))
mo_buf_free(dev);
}
static void
mo_command_stop(scsi_common_t *sc)
{
mo_t *dev = (mo_t *) sc;
mo_command_complete(dev);
mo_buf_free(dev);
}
/* The command second phase function, needed for Mode Select. */
static uint8_t
mo_phase_data_out(scsi_common_t *sc)
{
mo_t *dev = (mo_t *) sc;
uint16_t block_desc_len;
uint16_t pos;
uint16_t param_list_len;
uint8_t error = 0;
uint8_t page;
uint8_t page_len;
uint8_t hdr_len;
uint8_t val;
uint8_t old_val;
uint8_t ch;
int len = 0;
switch (dev->current_cdb[0]) {
case GPCMD_VERIFY_6:
case GPCMD_VERIFY_10:
case GPCMD_VERIFY_12:
break;
case GPCMD_WRITE_6:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
if (dev->requested_blocks > 0)
mo_blocks(dev, &len, 1, 1);
break;
case GPCMD_MODE_SELECT_6:
case GPCMD_MODE_SELECT_10:
if (dev->current_cdb[0] == GPCMD_MODE_SELECT_10) {
hdr_len = 8;
param_list_len = dev->current_cdb[7];
param_list_len <<= 8;
param_list_len |= dev->current_cdb[8];
} else {
hdr_len = 4;
param_list_len = dev->current_cdb[4];
}
if (dev->drv->bus_type == MO_BUS_SCSI) {
if (dev->current_cdb[0] == GPCMD_MODE_SELECT_6) {
block_desc_len = dev->buffer[2];
block_desc_len <<= 8;
block_desc_len |= dev->buffer[3];
} else {
block_desc_len = dev->buffer[6];
block_desc_len <<= 8;
block_desc_len |= dev->buffer[7];
}
} else
block_desc_len = 0;
pos = hdr_len + block_desc_len;
while (1) {
if (pos >= param_list_len) {
mo_log("MO %i: Buffer has only block descriptor\n", dev->id);
break;
}
page = dev->buffer[pos] & 0x3F;
page_len = dev->buffer[pos + 1];
pos += 2;
if (!(mo_mode_sense_page_flags & (1LL << ((uint64_t) page))))
error |= 1;
else {
for (uint8_t i = 0; i < page_len; i++) {
ch = mo_mode_sense_pages_changeable.pages[page][i + 2];
val = dev->buffer[pos + i];
old_val = dev->ms_pages_saved.pages[page][i + 2];
if (val != old_val) {
if (ch)
dev->ms_pages_saved.pages[page][i + 2] = val;
else
error |= 1;
}
}
}
pos += page_len;
if (dev->drv->bus_type == MO_BUS_SCSI)
val = mo_mode_sense_pages_default_scsi.pages[page][0] & 0x80;
else
val = mo_mode_sense_pages_default.pages[page][0] & 0x80;
if (dev->do_page_save && val)
mo_mode_sense_save(dev);
if (pos >= dev->total_length)
break;
}
if (error) {
mo_buf_free(dev);
mo_invalid_field_pl(dev);
return 0;
}
break;
default:
break;
}
mo_command_stop((scsi_common_t *) dev);
return 1;
}
/* Peform a master init on the entire module. */
void
mo_global_init(void)
{
/* Clear the global data. */
memset(mo_drives, 0x00, sizeof(mo_drives));
}
static int
mo_get_max(int ide_has_dma, int type)
{
int ret;
switch (type) {
case TYPE_PIO:
ret = ide_has_dma ? 3 : 0;
break;
case TYPE_SDMA:
default:
ret = -1;
break;
case TYPE_MDMA:
ret = ide_has_dma ? 1 : -1;
break;
case TYPE_UDMA:
ret = ide_has_dma ? 5 : -1;
break;
}
return ret;
}
static int
mo_get_timings(int ide_has_dma, int type)
{
int ret;
switch (type) {
case TIMINGS_DMA:
ret = ide_has_dma ? 0x96 : 0;
break;
case TIMINGS_PIO:
ret = ide_has_dma ? 0xb4 : 0;
break;
case TIMINGS_PIO_FC:
ret = ide_has_dma ? 0xb4 : 0;
break;
default:
ret = 0;
break;
}
return ret;
}
static void
mo_do_identify(ide_t *ide, int ide_has_dma)
{
char model[40];
const mo_t *mo = (mo_t *) ide->sc;
memset(model, 0, 40);
if (mo_drives[mo->id].type > 0) {
snprintf(model, 40, "%s %s", mo_drive_types[mo_drives[mo->id].type].vendor, mo_drive_types[mo_drives[mo->id].type].model);
ide_padstr((char *) (ide->buffer + 23), mo_drive_types[mo_drives[mo->id].type].revision, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), model, 40); /* Model */
} else {
snprintf(model, 40, "%s %s%02i", EMU_NAME, "86B_MO", mo->id);
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), model, 40); /* Model */
}
if (ide_has_dma) {
ide->buffer[80] = 0x70; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-6*/
ide->buffer[81] = 0x19; /*Maximum ATA revision supported : ATA/ATAPI-6 T13 1410D revision 3a*/
}
}
static void
mo_identify(ide_t *ide, int ide_has_dma)
{
ide->buffer[0] = 0x8000 | (0 << 8) | 0x80 | (1 << 5); /* ATAPI device, direct-access device, removable media, interrupt DRQ */
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
ide->buffer[49] = 0x200; /* LBA supported */
ide->buffer[126] = 0xfffe; /* Interpret zero byte count limit as maximum length */
mo_do_identify(ide, ide_has_dma);
}
static void
mo_drive_reset(int c)
{
mo_t *dev;
scsi_device_t *sd;
ide_t *id;
uint8_t scsi_bus = (mo_drives[c].scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = mo_drives[c].scsi_device_id & 0x0f;
if (!mo_drives[c].priv) {
mo_drives[c].priv = (mo_t *) malloc(sizeof(mo_t));
memset(mo_drives[c].priv, 0, sizeof(mo_t));
}
dev = (mo_t *) mo_drives[c].priv;
dev->id = c;
dev->cur_lun = SCSI_LUN_USE_CDB;
if (mo_drives[c].bus_type == MO_BUS_SCSI) {
if (!dev->tf)
dev->tf = (ide_tf_t *) calloc(1, sizeof(ide_tf_t));
/* SCSI MO, attach to the SCSI bus. */
sd = &scsi_devices[scsi_bus][scsi_id];
sd->sc = (scsi_common_t *) dev;
sd->command = mo_command;
sd->request_sense = mo_request_sense_for_scsi;
sd->reset = mo_reset;
sd->phase_data_out = mo_phase_data_out;
sd->command_stop = mo_command_stop;
sd->type = SCSI_REMOVABLE_DISK;
} else if (mo_drives[c].bus_type == MO_BUS_ATAPI) {
/* ATAPI MO, attach to the IDE bus. */
id = ide_get_drive(mo_drives[c].ide_channel);
/* If the IDE channel is initialized, we attach to it,
otherwise, we do nothing - it's going to be a drive
that's not attached to anything. */
if (id) {
id->sc = (scsi_common_t *) dev;
dev->tf = id->tf;
IDE_ATAPI_IS_EARLY = 0;
id->get_max = mo_get_max;
id->get_timings = mo_get_timings;
id->identify = mo_identify;
id->stop = NULL;
id->packet_command = mo_command;
id->device_reset = mo_reset;
id->phase_data_out = mo_phase_data_out;
id->command_stop = mo_command_stop;
id->bus_master_error = mo_bus_master_error;
id->interrupt_drq = 1;
ide_atapi_attach(id);
}
}
}
void
mo_hard_reset(void)
{
mo_t *dev;
uint8_t scsi_id;
uint8_t scsi_bus;
for (uint8_t c = 0; c < MO_NUM; c++) {
if ((mo_drives[c].bus_type == MO_BUS_ATAPI) || (mo_drives[c].bus_type == MO_BUS_SCSI)) {
mo_log("MO hard_reset drive=%d\n", c);
if (mo_drives[c].bus_type == MO_BUS_SCSI) {
scsi_bus = (mo_drives[c].scsi_device_id >> 4) & 0x0f;
scsi_id = mo_drives[c].scsi_device_id & 0x0f;
/* Make sure to ignore any SCSI MO drive that has an out of range SCSI Bus. */
if (scsi_bus >= SCSI_BUS_MAX)
continue;
/* Make sure to ignore any SCSI MO drive that has an out of range ID. */
if (scsi_id >= SCSI_ID_MAX)
continue;
}
/* Make sure to ignore any ATAPI MO drive that has an out of range IDE channel. */
if ((mo_drives[c].bus_type == MO_BUS_ATAPI) && (mo_drives[c].ide_channel > 7))
continue;
mo_drive_reset(c);
dev = (mo_t *) mo_drives[c].priv;
if (dev->tf == NULL)
continue;
dev->id = c;
dev->drv = &mo_drives[c];
mo_init(dev);
if (strlen(mo_drives[c].image_path))
mo_load(dev, mo_drives[c].image_path);
mo_mode_sense_load(dev);
if (mo_drives[c].bus_type == MO_BUS_SCSI)
mo_log("SCSI MO drive %i attached to SCSI ID %i\n", c, mo_drives[c].scsi_device_id);
else if (mo_drives[c].bus_type == MO_BUS_ATAPI)
mo_log("ATAPI MO drive %i attached to IDE channel %i\n", c, mo_drives[c].ide_channel);
}
}
}
void
mo_close(void)
{
mo_t *dev;
uint8_t scsi_id;
uint8_t scsi_bus;
for (uint8_t c = 0; c < MO_NUM; c++) {
if (mo_drives[c].bus_type == MO_BUS_SCSI) {
scsi_bus = (mo_drives[c].scsi_device_id >> 4) & 0x0f;
scsi_id = mo_drives[c].scsi_device_id & 0x0f;
memset(&scsi_devices[scsi_bus][scsi_id], 0x00, sizeof(scsi_device_t));
}
dev = (mo_t *) mo_drives[c].priv;
if (dev) {
mo_disk_unload(dev);
if (dev->tf)
free(dev->tf);
free(dev);
mo_drives[c].priv = NULL;
}
}
}
``` | /content/code_sandbox/src/disk/mo.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 19,379 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the SFF-8038i IDE Bus Master.
*
* PRD format :
* word 0 - base address
* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/cdrom.h>
#include <86box/hdd.h>
#include <86box/scsi_device.h>
#include <86box/scsi_disk.h>
#include <86box/scsi_cdrom.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/mo.h>
#include <86box/plat_unused.h>
static int next_id = 0;
uint8_t sff_bus_master_read(uint16_t port, void *priv);
static uint16_t sff_bus_master_readw(uint16_t port, void *priv);
static uint32_t sff_bus_master_readl(uint16_t port, void *priv);
void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
static void sff_bus_master_writew(uint16_t port, uint16_t val, void *priv);
static void sff_bus_master_writel(uint16_t port, uint32_t val, void *priv);
#ifdef ENABLE_SFF_LOG
int sff_do_log = ENABLE_SFF_LOG;
static void
sff_log(const char *fmt, ...)
{
va_list ap;
if (sff_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define sff_log(fmt, ...)
#endif
void
sff_bus_master_handler(sff8038i_t *dev, int enabled, uint16_t base)
{
if (dev->enabled && (dev->base != 0x0000)) {
io_removehandler(dev->base, 0x08,
sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
dev);
}
if (enabled && (base != 0x0000)) {
io_sethandler(base, 0x08,
sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
dev);
}
dev->enabled = enabled;
dev->base = base;
}
static void
sff_bus_master_next_addr(sff8038i_t *dev)
{
dma_bm_read(dev->ptr_cur, (uint8_t *) &(dev->addr), 4, 4);
dma_bm_read(dev->ptr_cur + 4, (uint8_t *) &(dev->count), 4, 4);
sff_log("SFF-8038i Bus master DWORDs: %08X %08X\n", dev->addr, dev->count);
dev->eot = dev->count >> 31;
dev->count &= 0xfffe;
if (!dev->count)
dev->count = 65536;
dev->addr &= 0xfffffffe;
dev->ptr_cur += 8;
}
void
sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
#ifdef ENABLE_SFF_LOG
int channel = (port & 8) ? 1 : 0;
#endif
sff_log("SFF-8038i Bus master BYTE write: %04X %02X\n", port, val);
switch (port & 7) {
case 0:
sff_log("sff Cmd : val = %02X, old = %02X\n", val, dev->command);
if ((val & 1) && !(dev->command & 1)) { /*Start*/
sff_log("sff Bus Master start on channel %i\n", channel);
dev->ptr_cur = dev->ptr;
sff_bus_master_next_addr(dev);
dev->status |= 1;
}
if (!(val & 1) && (dev->command & 1)) { /*Stop*/
sff_log("sff Bus Master stop on channel %i\n", channel);
dev->status &= ~1;
}
dev->command = val;
break;
case 1:
dev->dma_mode = val & 0x03;
break;
case 2:
sff_log("sff Status: val = %02X, old = %02X\n", val, dev->status);
dev->status &= 0x07;
dev->status |= (val & 0x60);
if (val & 0x04)
dev->status &= ~0x04;
if (val & 0x02)
dev->status &= ~0x02;
break;
case 4:
dev->ptr = (dev->ptr & 0xffffff00) | (val & 0xfc);
dev->ptr %= (mem_size * 1024);
dev->ptr0 = val;
break;
case 5:
dev->ptr = (dev->ptr & 0xffff00fc) | (val << 8);
dev->ptr %= (mem_size * 1024);
break;
case 6:
dev->ptr = (dev->ptr & 0xff00fffc) | (val << 16);
dev->ptr %= (mem_size * 1024);
break;
case 7:
dev->ptr = (dev->ptr & 0x00fffffc) | (val << 24);
dev->ptr %= (mem_size * 1024);
break;
default:
break;
}
}
static void
sff_bus_master_writew(uint16_t port, uint16_t val, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
sff_log("SFF-8038i Bus master WORD write: %04X %04X\n", port, val);
switch (port & 7) {
case 0:
case 1:
case 2:
sff_bus_master_write(port, val & 0xff, priv);
break;
case 4:
dev->ptr = (dev->ptr & 0xffff0000) | (val & 0xfffc);
dev->ptr %= (mem_size * 1024);
dev->ptr0 = val & 0xff;
break;
case 6:
dev->ptr = (dev->ptr & 0x0000fffc) | (val << 16);
dev->ptr %= (mem_size * 1024);
break;
default:
break;
}
}
static void
sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
sff_log("SFF-8038i Bus master DWORD write: %04X %08X\n", port, val);
switch (port & 7) {
case 0:
case 1:
case 2:
sff_bus_master_write(port, val & 0xff, priv);
break;
case 4:
dev->ptr = (val & 0xfffffffc);
dev->ptr %= (mem_size * 1024);
dev->ptr0 = val & 0xff;
break;
default:
break;
}
}
uint8_t
sff_bus_master_read(uint16_t port, void *priv)
{
const sff8038i_t *dev = (sff8038i_t *) priv;
uint8_t ret = 0xff;
switch (port & 7) {
case 0:
ret = dev->command;
break;
case 1:
ret = dev->dma_mode & 0x03;
break;
case 2:
ret = dev->status & 0x67;
break;
case 4:
ret = dev->ptr0;
break;
case 5:
ret = dev->ptr >> 8;
break;
case 6:
ret = dev->ptr >> 16;
break;
case 7:
ret = dev->ptr >> 24;
break;
default:
break;
}
sff_log("SFF-8038i Bus master BYTE read : %04X %02X\n", port, ret);
return ret;
}
static uint16_t
sff_bus_master_readw(uint16_t port, void *priv)
{
const sff8038i_t *dev = (sff8038i_t *) priv;
uint16_t ret = 0xffff;
switch (port & 7) {
case 0:
case 1:
case 2:
ret = (uint16_t) sff_bus_master_read(port, priv);
break;
case 4:
ret = dev->ptr0 | (dev->ptr & 0xff00);
break;
case 6:
ret = dev->ptr >> 16;
break;
default:
break;
}
sff_log("SFF-8038i Bus master WORD read : %04X %04X\n", port, ret);
return ret;
}
static uint32_t
sff_bus_master_readl(uint16_t port, void *priv)
{
const sff8038i_t *dev = (sff8038i_t *) priv;
uint32_t ret = 0xffffffff;
switch (port & 7) {
case 0:
case 1:
case 2:
ret = (uint32_t) sff_bus_master_read(port, priv);
break;
case 4:
ret = dev->ptr0 | (dev->ptr & 0xffffff00);
break;
default:
break;
}
sff_log("sff Bus master DWORD read : %04X %08X\n", port, ret);
return ret;
}
int
sff_bus_master_dma(uint8_t *data, int transfer_length, int out, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
#ifdef ENABLE_SFF_LOG
char *sop;
#endif
int force_end = 0;
int buffer_pos = 0;
#ifdef ENABLE_SFF_LOG
sop = out ? "Read" : "Writ";
#endif
if (!(dev->status & 1)) {
sff_log("DMA disabled\n");
return 2; /*DMA disabled*/
}
sff_log("SFF-8038i Bus master %s: %i bytes\n", out ? "write" : "read", transfer_length);
while (1) {
if (dev->count <= transfer_length) {
sff_log("%sing %i bytes to %08X\n", sop, dev->count, dev->addr);
if (out)
dma_bm_read(dev->addr, (uint8_t *) (data + buffer_pos), dev->count, 4);
else
dma_bm_write(dev->addr, (uint8_t *) (data + buffer_pos), dev->count, 4);
transfer_length -= dev->count;
buffer_pos += dev->count;
} else {
sff_log("%sing %i bytes to %08X\n", sop, transfer_length, dev->addr);
if (out)
dma_bm_read(dev->addr, (uint8_t *) (data + buffer_pos), transfer_length, 4);
else
dma_bm_write(dev->addr, (uint8_t *) (data + buffer_pos), transfer_length, 4);
/* Increase addr and decrease count so that resumed transfers do not mess up. */
dev->addr += transfer_length;
dev->count -= transfer_length;
transfer_length = 0;
force_end = 1;
}
if (force_end) {
sff_log("Total transfer length smaller than sum of all blocks, partial block\n");
dev->status &= ~2;
return 1; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
} else {
if (!transfer_length && !dev->eot) {
sff_log("Total transfer length smaller than sum of all blocks, full block\n");
dev->status &= ~2;
return 1; /* We have exhausted the data to transfer but there's more blocks left, break. */
} else if (transfer_length && dev->eot) {
sff_log("Total transfer length greater than sum of all blocks\n");
dev->status |= 2;
return 0; /* There is data left to transfer but we have reached EOT - return with error. */
} else if (dev->eot) {
sff_log("Regular EOT\n");
dev->status &= ~3;
return 1; /* We have regularly reached EOT - clear status and break. */
} else {
/* We have more to transfer and there are blocks left, get next block. */
sff_bus_master_next_addr(dev);
}
}
}
return 1;
}
void
sff_bus_master_set_irq(uint8_t status, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
uint8_t irq = !!(status & 0x04);
if (!(dev->status & 0x04) || (status & 0x04))
dev->status = (dev->status & ~0x04) | status;
switch (dev->irq_mode) {
default:
case IRQ_MODE_LEGACY:
/* Legacy IRQ mode. */
if (irq)
picint(1 << dev->irq_line);
else
picintc(1 << dev->irq_line);
break;
case IRQ_MODE_PCI_IRQ_PIN:
/* Native PCI IRQ mode with interrupt pin. */
if (irq)
pci_set_irq(dev->slot, dev->irq_pin, &dev->irq_state);
else
pci_clear_irq(dev->slot, dev->irq_pin, &dev->irq_state);
break;
case IRQ_MODE_MIRQ_0 ... IRQ_MODE_MIRQ_3:
/* MIRQ 0, 1, 2, or 3. */
if (irq)
pci_set_mirq(dev->irq_mode & 3, 0, &dev->irq_state);
else
pci_clear_mirq(dev->irq_mode & 3, 0, &dev->irq_state);
break;
/* TODO: Redo this as a MIRQ. */
case IRQ_MODE_PCI_IRQ_LINE:
/* Native PCI IRQ mode with specified interrupt line. */
if (irq)
pci_set_dirq(dev->pci_irq_line, &dev->irq_state);
else
pci_clear_dirq(dev->pci_irq_line, &dev->irq_state);
break;
case IRQ_MODE_ALI_ALADDIN:
/* ALi Aladdin Native PCI INTAJ mode. */
if (irq)
pci_set_mirq((dev->channel + 2), pci_get_mirq_level(dev->channel + 2), &dev->irq_state);
else
pci_clear_mirq((dev->channel + 2), pci_get_mirq_level(dev->channel + 2), &dev->irq_state);
break;
case IRQ_MODE_SIS_551X:
/* SiS 551x mode. */
if (irq)
pci_set_mirq(dev->mirq, 1, &dev->irq_state);
else
pci_clear_mirq(dev->mirq, 1, &dev->irq_state);
break;
}
}
void
sff_bus_master_reset(sff8038i_t *dev)
{
if (dev->enabled && (dev->base != 0x0000)) {
io_removehandler(dev->base, 0x08,
sff_bus_master_read, sff_bus_master_readw, sff_bus_master_readl,
sff_bus_master_write, sff_bus_master_writew, sff_bus_master_writel,
dev);
dev->enabled = 0;
}
dev->command = 0x00;
dev->status = 0x00;
dev->ptr = dev->ptr_cur = 0x00000000;
dev->addr = 0x00000000;
dev->ptr0 = 0x00;
dev->count = dev->eot = 0x00000000;
dev->irq_state = 0;
ide_pri_disable();
ide_sec_disable();
}
static void
sff_reset(void *priv)
{
#ifdef ENABLE_SFF_LOG
sff_log("SFF8038i: Reset\n");
#endif
for (uint8_t i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus == HDD_BUS_ATAPI) && (hdd[i].ide_channel < 4) && hdd[i].priv)
scsi_disk_reset((scsi_common_t *) hdd[i].priv);
}
for (uint8_t i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (uint8_t i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
for (uint8_t i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) && mo_drives[i].priv)
mo_reset((scsi_common_t *) mo_drives[i].priv);
}
sff_bus_master_set_irq(0x00, priv);
sff_bus_master_set_irq(0x01, priv);
}
void
sff_set_slot(sff8038i_t *dev, int slot)
{
dev->slot = slot;
}
void
sff_set_irq_line(sff8038i_t *dev, int pci_irq_line)
{
dev->pci_irq_line = pci_irq_line;
}
/* TODO: Why does this always set the level to 0, regardless of the parameter?! */
void
sff_set_irq_level(sff8038i_t *dev, UNUSED(int irq_level))
{
dev->irq_level = 0;
}
void
sff_set_irq_mode(sff8038i_t *dev, int irq_mode)
{
dev->irq_mode = irq_mode;
switch (dev->irq_mode) {
default:
case IRQ_MODE_LEGACY:
/* Legacy IRQ mode. */
sff_log("[%08X] Setting IRQ mode to legacy IRQ %i\n", dev, dev->irq_line);
break;
case IRQ_MODE_PCI_IRQ_PIN:
/* Native PCI IRQ mode with interrupt pin. */
sff_log("[%08X] Setting IRQ mode to native PCI INT%c\n", dev, 0x40 + dev->irq_pin);
break;
case IRQ_MODE_MIRQ_0 ... IRQ_MODE_MIRQ_3:
/* MIRQ 0, 1, 2, or 3. */
sff_log("[%08X] Setting IRQ mode to PCI MIRQ%i\n", dev, dev->irq_mode & 3);
break;
case IRQ_MODE_PCI_IRQ_LINE:
/* Native PCI IRQ mode with specified interrupt line. */
sff_log("[%08X] Setting IRQ mode to native PCI IRQ %i\n", dev, dev->pci_irq_line);
break;
case IRQ_MODE_ALI_ALADDIN:
/* ALi Aladdin Native PCI INTAJ mode. */
sff_log("[%08X] Setting IRQ mode to INT%cJ\n", dev, 'A' + dev->channel);
break;
case IRQ_MODE_SIS_551X:
/* SiS 551x mode. */
sff_log("[%08X] Setting IRQ mode to PCI MIRQ2\n", dev);
break;
}
}
void
sff_set_irq_pin(sff8038i_t *dev, int irq_pin)
{
dev->irq_pin = irq_pin;
}
void
sff_set_mirq(sff8038i_t *dev, uint8_t mirq)
{
dev->mirq = mirq;
}
static void
sff_close(void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
free(dev);
next_id--;
if (next_id < 0)
next_id = 0;
}
static void *
sff_init(UNUSED(const device_t *info))
{
sff8038i_t *dev = (sff8038i_t *) malloc(sizeof(sff8038i_t));
memset(dev, 0, sizeof(sff8038i_t));
/* Make sure to only add IDE once. */
if (next_id == 0)
device_add(&ide_pci_2ch_device);
ide_set_bus_master(next_id, sff_bus_master_dma, sff_bus_master_set_irq, dev);
dev->slot = 7;
/* Channel 0 goes to IRQ 14, channel 1 goes to MIRQ0. */
dev->irq_mode = next_id ? IRQ_MODE_MIRQ_0 : IRQ_MODE_LEGACY;
dev->irq_pin = PCI_INTA;
dev->irq_line = 14 + next_id;
dev->pci_irq_line = 14;
dev->irq_level = 0;
dev->irq_state = 0;
dev->mirq = 2;
dev->channel = next_id;
next_id++;
return dev;
}
const device_t sff8038i_device = {
.name = "SFF-8038i IDE Bus Master",
.internal_name = "sff8038i",
.flags = DEVICE_PCI,
.local = 0,
.init = sff_init,
.close = sff_close,
.reset = sff_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_sff8038i.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,231 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C611/611A VLB IDE controller.
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/plat_unused.h>
typedef struct opti611_t {
uint8_t is_sec;
uint8_t tries;
uint8_t in_cfg;
uint8_t cfg_locked;
uint8_t regs[19];
} opti611_t;
static void opti611_ide_handler(opti611_t *dev);
static void
opti611_cfg_write(uint16_t addr, uint8_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
addr &= 0x0007;
switch (addr) {
case 0x0000:
case 0x0001:
dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr] = val;
break;
case 0x0002:
dev->regs[0x12] = (val & 0xc1) | 0x02;
if (val & 0xc0) {
if (val & 0x40)
dev->cfg_locked = 1;
dev->in_cfg = 0;
opti611_ide_handler(dev);
}
break;
case 0x0003:
dev->regs[0x03] = (val & 0xdf);
break;
case 0x0005:
dev->regs[0x05] = (dev->regs[0x05] & 0x78) | (val & 0x87);
break;
case 0x0006:
dev->regs[0x06] = val;
break;
default:
break;
}
}
static void
opti611_cfg_writew(uint16_t addr, uint16_t val, void *priv)
{
opti611_cfg_write(addr, val & 0xff, priv);
opti611_cfg_write(addr + 1, val >> 8, priv);
}
static void
opti611_cfg_writel(uint16_t addr, uint32_t val, void *priv)
{
opti611_cfg_writew(addr, val & 0xffff, priv);
opti611_cfg_writew(addr + 2, val >> 16, priv);
}
static uint8_t
opti611_cfg_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
const opti611_t *dev = (opti611_t *) priv;
addr &= 0x0007;
switch (addr) {
case 0x0000:
case 0x0001:
ret = dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr];
break;
case 0x0002:
ret = ((!!in_smm) << 7);
if (ret & 0x80)
ret |= (dev->regs[addr] & 0x7f);
break;
case 0x0003:
case 0x0004:
case 0x0005:
case 0x0006:
ret = dev->regs[addr];
break;
default:
break;
}
return ret;
}
static uint16_t
opti611_cfg_readw(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = opti611_cfg_read(addr, priv);
ret |= (opti611_cfg_read(addr + 1, priv) << 8);
return ret;
}
static uint32_t
opti611_cfg_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = opti611_cfg_readw(addr, priv);
ret |= (opti611_cfg_readw(addr + 2, priv) << 16);
return ret;
}
static void
opti611_ide_write(uint16_t addr, uint8_t val, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0003);
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = val;
}
}
static void
opti611_ide_writew(uint16_t addr, UNUSED(uint16_t val), void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0002) | 0x0001;
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
}
static void
opti611_ide_writel(uint16_t addr, UNUSED(uint32_t val), void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | 0x0003;
dev->regs[0x04] = 0x00;
}
}
static uint8_t
opti611_ide_read(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0003);
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
return 0xff;
}
static uint16_t
opti611_ide_readw(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
uint8_t smibe = (addr & 0x0002) | 0x0001;
if ((addr & 0x0007) == 0x0001) {
dev->tries = (dev->tries + 1) & 0x01;
if ((dev->tries == 0x00) && !dev->cfg_locked) {
dev->in_cfg = 1;
opti611_ide_handler(dev);
}
}
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | smibe;
dev->regs[0x04] = 0x00;
}
return 0xffff;
}
static uint32_t
opti611_ide_readl(uint16_t addr, void *priv)
{
opti611_t *dev = (opti611_t *) priv;
uint8_t smia9 = (!!(addr & 0x0200)) << 5;
uint8_t smia2 = (!!(addr & 0x0004)) << 4;
if (dev->regs[0x03] & 0x02) {
smi_raise();
dev->regs[0x02] = smia9 | smia2 | 0x0003;
dev->regs[0x04] = 0x00;
}
return 0xffffffff;
}
static void
opti611_ide_handler(opti611_t *dev)
{
if (dev->is_sec) {
ide_sec_disable();
io_removehandler(0x0170, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
io_removehandler(0x0170, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
if (dev->in_cfg && !dev->cfg_locked) {
io_sethandler(0x0170, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
} else {
if (dev->regs[0x03] & 0x01)
ide_sec_enable();
io_sethandler(0x0170, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
}
} else {
ide_pri_disable();
io_removehandler(0x01f0, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
io_removehandler(0x01f0, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
if (dev->in_cfg && !dev->cfg_locked) {
io_sethandler(0x01f0, 0x0007,
opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl,
opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel,
dev);
} else {
if (dev->regs[0x03] & 0x01)
ide_pri_enable();
io_sethandler(0x01f0, 0x0007,
opti611_ide_read, opti611_ide_readw, opti611_ide_readl,
opti611_ide_write, opti611_ide_writew, opti611_ide_writel,
dev);
}
}
}
static void
opti611_close(void *priv)
{
opti611_t *dev = (opti611_t *) priv;
free(dev);
}
static void *
opti611_init(UNUSED(const device_t *info))
{
opti611_t *dev = (opti611_t *) malloc(sizeof(opti611_t));
memset(dev, 0, sizeof(opti611_t));
dev->is_sec = info->local;
dev->regs[0x12] = 0x80;
dev->regs[0x03] = 0x01;
dev->regs[0x05] = 0x20;
device_add(&ide_vlb_device);
opti611_ide_handler(dev);
return dev;
}
const device_t ide_opti611_vlb_device = {
.name = "OPTi 82C611/82C611A VLB",
.internal_name = "ide_opti611_vlb",
.flags = DEVICE_VLB,
.local = 0,
.init = opti611_init,
.close = opti611_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_opti611_vlb_sec_device = {
.name = "OPTi 82C611/82C611A VLB (Secondary)",
.internal_name = "ide_opti611_vlb",
.flags = DEVICE_VLB,
.local = 1,
.init = opti611_init,
.close = opti611_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_opti611.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,170 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of hard disk image files.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#define _GNU_SOURCE
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <wchar.h>
#include <errno.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/random.h>
#include <86box/hdd.h>
#include "minivhd/minivhd.h"
#include "minivhd/internal.h"
#define HDD_IMAGE_RAW 0
#define HDD_IMAGE_HDI 1
#define HDD_IMAGE_HDX 2
#define HDD_IMAGE_VHD 3
typedef struct hdd_image_t {
FILE *file; /* Used for HDD_IMAGE_RAW, HDD_IMAGE_HDI, and HDD_IMAGE_HDX. */
MVHDMeta *vhd; /* Used for HDD_IMAGE_VHD. */
uint32_t base;
uint32_t pos;
uint32_t last_sector;
uint8_t type; /* HDD_IMAGE_RAW, HDD_IMAGE_HDI, HDD_IMAGE_HDX, or HDD_IMAGE_VHD */
uint8_t loaded;
} hdd_image_t;
hdd_image_t hdd_images[HDD_NUM];
static char empty_sector[512];
static char *empty_sector_1mb;
#ifdef ENABLE_HDD_IMAGE_LOG
int hdd_image_do_log = ENABLE_HDD_IMAGE_LOG;
static void
hdd_image_log(const char *fmt, ...)
{
va_list ap;
if (hdd_image_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define hdd_image_log(fmt, ...)
#endif
int
image_is_hdi(const char *s)
{
if (!strcasecmp(path_get_extension((char *) s), "HDI"))
return 1;
else
return 0;
}
int
image_is_hdx(const char *s, int check_signature)
{
FILE *fp;
uint64_t filelen;
uint64_t signature;
if (!strcasecmp(path_get_extension((char *) s), "HDX")) {
if (check_signature) {
fp = plat_fopen(s, "rb");
if (!fp)
return 0;
if (fseeko64(fp, 0, SEEK_END))
fatal("image_is_hdx(): Error while seeking");
filelen = ftello64(fp);
if (fseeko64(fp, 0, SEEK_SET))
fatal("image_is_hdx(): Error while seeking");
if (filelen < 44) {
if (fp != NULL)
fclose(fp);
return 0;
}
if (fread(&signature, 1, 8, fp) != 8)
fatal("image_is_hdx(): Error reading signature\n");
fclose(fp);
if (signature == 0xD778A82044445459LL)
return 1;
else
return 0;
} else
return 1;
} else
return 0;
}
int
image_is_vhd(const char *s, int check_signature)
{
FILE *fp;
if (!strcasecmp(path_get_extension((char *) s), "VHD")) {
if (check_signature) {
fp = plat_fopen(s, "rb");
if (!fp)
return 0;
bool is_vhd = mvhd_file_is_vhd(fp);
fclose(fp);
return is_vhd ? 1 : 0;
} else
return 1;
} else
return 0;
}
void
hdd_image_calc_chs(uint32_t *c, uint32_t *h, uint32_t *s, uint32_t size)
{
/* Calculate the geometry from size (in MB), using the algorithm provided in
"Virtual Hard Disk Image Format Specification, Appendix: CHS Calculation" */
uint64_t ts = ((uint64_t) size) << 11LL;
uint32_t spt;
uint32_t heads;
uint32_t cyl;
uint32_t cth;
if (ts > 65535 * 16 * 255)
ts = 65535 * 16 * 255;
if (ts >= 65535 * 16 * 63) {
spt = 255;
heads = 16;
cth = (uint32_t) (ts / spt);
} else {
spt = 17;
cth = (uint32_t) (ts / spt);
heads = (cth + 1023) / 1024;
if (heads < 4)
heads = 4;
if ((cth >= (heads * 1024)) || (heads > 16)) {
spt = 31;
heads = 16;
cth = (uint32_t) (ts / spt);
}
if (cth >= (heads * 1024)) {
spt = 63;
heads = 16;
cth = (uint32_t) (ts / spt);
}
}
cyl = cth / heads;
*c = cyl;
*h = heads;
*s = spt;
}
static int
prepare_new_hard_disk(uint8_t id, uint64_t full_size)
{
uint64_t target_size = (full_size + hdd_images[id].base) - ftello64(hdd_images[id].file);
uint32_t size;
uint32_t t;
t = (uint32_t) (target_size >> 20); /* Amount of 1 MB blocks. */
size = (uint32_t) (target_size & 0xfffff); /* 1 MB mask. */
empty_sector_1mb = (char *) malloc(1048576);
memset(empty_sector_1mb, 0, 1048576);
/* Temporarily switch off suppression of seen messages so that the
progress gets displayed. */
pclog_toggle_suppr();
pclog("Writing image sectors: [");
/* First, write all the 1 MB blocks. */
if (t > 0) {
for (uint32_t i = 0; i < t; i++) {
fseek(hdd_images[id].file, 0, SEEK_END);
fwrite(empty_sector_1mb, 1, 1048576, hdd_images[id].file);
pclog("#");
}
}
/* Then, write the remainder. */
if (size > 0) {
fseek(hdd_images[id].file, 0, SEEK_END);
fwrite(empty_sector_1mb, 1, size, hdd_images[id].file);
pclog("#");
}
pclog("]\n");
/* Switch the suppression of seen messages back on. */
pclog_toggle_suppr();
free(empty_sector_1mb);
hdd_images[id].last_sector = (uint32_t) (full_size >> 9) - 1;
hdd_images[id].loaded = 1;
return 1;
}
void
hdd_image_init(void)
{
for (uint8_t i = 0; i < HDD_NUM; i++)
memset(&hdd_images[i], 0, sizeof(hdd_image_t));
}
int
hdd_image_load(int id)
{
uint32_t sector_size = 512;
uint32_t zero = 0;
uint64_t signature = 0xD778A82044445459LL;
uint64_t full_size = 0;
uint64_t spt = 0;
uint64_t hpc = 0;
uint64_t tracks = 0;
int ret;
uint64_t s = 0;
char *fn = hdd[id].fn;
int is_hdx[2] = { 0, 0 };
int is_vhd[2] = { 0, 0 };
int vhd_error = 0;
memset(empty_sector, 0, sizeof(empty_sector));
if (fn) {
path_normalize(fn);
}
hdd_images[id].base = 0;
if (hdd_images[id].loaded) {
if (hdd_images[id].file) {
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
} else if (hdd_images[id].vhd) {
mvhd_close(hdd_images[id].vhd);
hdd_images[id].vhd = NULL;
}
hdd_images[id].loaded = 0;
}
is_hdx[0] = image_is_hdx(fn, 0);
is_hdx[1] = image_is_hdx(fn, 1);
is_vhd[0] = image_is_vhd(fn, 0);
is_vhd[1] = image_is_vhd(fn, 1);
hdd_images[id].pos = 0;
/* Try to open existing hard disk image */
if (fn[0] == '.') {
hdd_image_log("File name starts with .\n");
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
return 0;
}
hdd_images[id].file = plat_fopen(fn, "rb+");
if (hdd_images[id].file == NULL) {
/* Failed to open existing hard disk image */
if (errno == ENOENT) {
/* Failed because it does not exist,
so try to create new file */
if (hdd[id].wp) {
hdd_image_log("A write-protected image must exist\n");
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
return 0;
}
hdd_images[id].file = plat_fopen(fn, "wb+");
if (hdd_images[id].file == NULL) {
hdd_image_log("Unable to open image\n");
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
return 0;
} else {
if (image_is_hdi(fn)) {
full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
hdd_images[id].base = 0x1000;
fwrite(&zero, 1, 4, hdd_images[id].file);
fwrite(&zero, 1, 4, hdd_images[id].file);
fwrite(&(hdd_images[id].base), 1, 4, hdd_images[id].file);
fwrite(&full_size, 1, 4, hdd_images[id].file);
fwrite(§or_size, 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].spt), 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].hpc), 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].tracks), 1, 4, hdd_images[id].file);
for (uint16_t c = 0; c < 0x3f8; c++)
fwrite(&zero, 1, 4, hdd_images[id].file);
hdd_images[id].type = HDD_IMAGE_HDI;
} else if (is_hdx[0]) {
full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
hdd_images[id].base = 0x28;
fwrite(&signature, 1, 8, hdd_images[id].file);
fwrite(&full_size, 1, 8, hdd_images[id].file);
fwrite(§or_size, 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].spt), 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].hpc), 1, 4, hdd_images[id].file);
fwrite(&(hdd[id].tracks), 1, 4, hdd_images[id].file);
fwrite(&zero, 1, 4, hdd_images[id].file);
fwrite(&zero, 1, 4, hdd_images[id].file);
hdd_images[id].type = HDD_IMAGE_HDX;
} else if (is_vhd[0]) {
fclose(hdd_images[id].file);
MVHDGeom geometry = { 0 };
geometry.cyl = hdd[id].tracks;
geometry.heads = hdd[id].hpc;
geometry.spt = hdd[id].spt;
full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
hdd_images[id].last_sector = (full_size >> 9LL) - 1;
if (hdd[id].vhd_blocksize || hdd[id].vhd_parent[0]) {
MVHDCreationOptions options = { 0 };
retry_vhd:
options.block_size_in_sectors = hdd[id].vhd_blocksize;
options.path = fn;
options.size_in_bytes = 0;
options.geometry = geometry;
if (hdd[id].vhd_parent[0]) {
options.type = MVHD_TYPE_DIFF;
options.parent_path = hdd[id].vhd_parent;
} else {
options.type = MVHD_TYPE_DYNAMIC;
options.parent_path = NULL;
}
hdd_images[id].vhd = mvhd_create_ex(options, &vhd_error);
} else {
hdd_images[id].vhd = mvhd_create_fixed(fn, geometry, &vhd_error, NULL);
}
if (hdd_images[id].vhd == NULL) {
/* Don't lock out if the parent of a differential VHD doesn't exist. */
if (hdd[id].vhd_parent[0]) {
hdd[id].vhd_parent[0] = '\0';
goto retry_vhd;
}
fatal("hdd_image_load(): VHD: Could not create VHD : %s\n", mvhd_strerr(vhd_error));
}
hdd_images[id].type = HDD_IMAGE_VHD;
return 1;
} else {
hdd_images[id].type = HDD_IMAGE_RAW;
}
hdd_images[id].last_sector = 0;
}
s = full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
ret = prepare_new_hard_disk(id, full_size);
return ret;
} else {
/* Failed for another reason */
hdd_image_log("Failed for another reason\n");
return 0;
}
} else {
if (image_is_hdi(fn)) {
if (fseeko64(hdd_images[id].file, 0x8, SEEK_SET) == -1)
fatal("hdd_image_load(): HDI: Error seeking to offset 0x8\n");
if (fread(&(hdd_images[id].base), 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading base offset\n");
if (fseeko64(hdd_images[id].file, 0xC, SEEK_SET) == -1)
fatal("hdd_image_load(): HDI: Error seeking to offest 0xC\n");
full_size = 0LL;
if (fread(&full_size, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading full size\n");
if (fseeko64(hdd_images[id].file, 0x10, SEEK_SET) == -1)
fatal("hdd_image_load(): HDI: Error seeking to offset 0x10\n");
if (fread(§or_size, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading sector size\n");
if (sector_size != 512) {
/* Sector size is not 512 */
hdd_image_log("HDI: Sector size is not 512\n");
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
return 0;
}
if (fread(&spt, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading sectors per track\n");
if (fread(&hpc, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading heads per cylinder\n");
if (fread(&tracks, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading number of tracks\n");
hdd[id].spt = spt;
hdd[id].hpc = hpc;
hdd[id].tracks = tracks;
hdd_images[id].type = HDD_IMAGE_HDI;
} else if (is_hdx[1]) {
hdd_images[id].base = 0x28;
if (fseeko64(hdd_images[id].file, 8, SEEK_SET) == -1)
fatal("hdd_image_load(): HDX: Error seeking to offset 0x8\n");
if (fread(&full_size, 1, 8, hdd_images[id].file) != 8)
fatal("hdd_image_load(): HDX: Error reading full size\n");
if (fseeko64(hdd_images[id].file, 0x10, SEEK_SET) == -1)
fatal("hdd_image_load(): HDX: Error seeking to offset 0x10\n");
if (fread(§or_size, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDX: Error reading sector size\n");
if (sector_size != 512) {
/* Sector size is not 512 */
hdd_image_log("HDX: Sector size is not 512\n");
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
return 0;
}
if (fread(&spt, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading sectors per track\n");
if (fread(&hpc, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDI: Error reading heads per cylinder\n");
if (fread(&tracks, 1, 4, hdd_images[id].file) != 4)
fatal("hdd_image_load(): HDX: Error reading number of tracks\n");
hdd[id].spt = spt;
hdd[id].hpc = hpc;
hdd[id].tracks = tracks;
hdd_images[id].type = HDD_IMAGE_HDX;
} else if (is_vhd[1]) {
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
hdd_images[id].vhd = mvhd_open(fn, (bool) 0, &vhd_error);
if (hdd_images[id].vhd == NULL) {
if (vhd_error == MVHD_ERR_FILE)
fatal("hdd_image_load(): VHD: Error opening VHD file '%s': %s\n", fn, strerror(mvhd_errno));
else
fatal("hdd_image_load(): VHD: Error opening VHD file '%s': %s\n", fn, mvhd_strerr(vhd_error));
} else if (vhd_error == MVHD_ERR_TIMESTAMP) {
pclog("hdd_image_load(): VHD: Parent/child timestamp mismatch for VHD file '%s'\n", fn);
}
hdd[id].tracks = hdd_images[id].vhd->footer.geom.cyl;
hdd[id].hpc = hdd_images[id].vhd->footer.geom.heads;
hdd[id].spt = hdd_images[id].vhd->footer.geom.spt;
hdd[id].vhd_blocksize = (hdd_images[id].vhd->footer.disk_type == MVHD_TYPE_FIXED) ? 0 : (hdd_images[id].vhd->sparse.block_sz / MVHD_SECTOR_SIZE);
if (hdd_images[id].vhd->parent && hdd_images[id].vhd->parent->filename[0])
strncpy(hdd[id].vhd_parent, hdd_images[id].vhd->parent->filename, sizeof(hdd[id].vhd_parent) - 1);
full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
hdd_images[id].type = HDD_IMAGE_VHD;
/* If we're here, this means there is a valid VHD footer in the
image, which means that by definition, all valid sectors
are there. */
hdd_images[id].last_sector = (uint32_t) (full_size >> 9) - 1;
hdd_images[id].loaded = 1;
return 1;
} else {
full_size = ((uint64_t) hdd[id].spt) * ((uint64_t) hdd[id].hpc) * ((uint64_t) hdd[id].tracks) << 9LL;
hdd_images[id].type = HDD_IMAGE_RAW;
}
}
if (fseeko64(hdd_images[id].file, 0, SEEK_END) == -1)
fatal("hdd_image_load(): Error seeking to the end of file\n");
s = ftello64(hdd_images[id].file);
if (s < (full_size + hdd_images[id].base))
ret = prepare_new_hard_disk(id, full_size);
else {
hdd_images[id].last_sector = (uint32_t) (full_size >> 9) - 1;
hdd_images[id].loaded = 1;
ret = 1;
}
return ret;
}
void
hdd_image_seek(uint8_t id, uint32_t sector)
{
off64_t addr = sector;
addr = (uint64_t) sector << 9LL;
hdd_images[id].pos = sector;
if (hdd_images[id].type != HDD_IMAGE_VHD) {
if (fseeko64(hdd_images[id].file, addr + hdd_images[id].base, SEEK_SET) == -1)
fatal("hdd_image_seek(): Error seeking\n");
}
}
void
hdd_image_read(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
int non_transferred_sectors;
size_t num_read;
if (hdd_images[id].type == HDD_IMAGE_VHD) {
non_transferred_sectors = mvhd_read_sectors(hdd_images[id].vhd, sector, count, buffer);
hdd_images[id].pos = sector + count - non_transferred_sectors - 1;
} else {
if (fseeko64(hdd_images[id].file, ((uint64_t) (sector) << 9LL) + hdd_images[id].base, SEEK_SET) == -1) {
fatal("Hard disk image %i: Read error during seek\n", id);
return;
}
num_read = fread(buffer, 512, count, hdd_images[id].file);
hdd_images[id].pos = sector + num_read;
}
}
uint32_t
hdd_image_get_last_sector(uint8_t id)
{
return hdd_images[id].last_sector;
}
uint32_t
hdd_sectors(uint8_t id)
{
return hdd_image_get_last_sector(id) - 1;
}
int
hdd_image_read_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
transfer_sectors = sectors - sector;
hdd_image_read(id, sector, transfer_sectors, buffer);
if (count != transfer_sectors)
return 1;
return 0;
}
void
hdd_image_write(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
int non_transferred_sectors;
size_t num_write;
if (hdd_images[id].type == HDD_IMAGE_VHD) {
non_transferred_sectors = mvhd_write_sectors(hdd_images[id].vhd, sector, count, buffer);
hdd_images[id].pos = sector + count - non_transferred_sectors - 1;
} else {
if (fseeko64(hdd_images[id].file, ((uint64_t) (sector) << 9LL) + hdd_images[id].base, SEEK_SET) == -1) {
fatal("Hard disk image %i: Write error during seek\n", id);
return;
}
num_write = fwrite(buffer, 512, count, hdd_images[id].file);
hdd_images[id].pos = sector + num_write;
}
}
int
hdd_image_write_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
transfer_sectors = sectors - sector;
hdd_image_write(id, sector, transfer_sectors, buffer);
if (count != transfer_sectors)
return 1;
return 0;
}
void
hdd_image_zero(uint8_t id, uint32_t sector, uint32_t count)
{
if (hdd_images[id].type == HDD_IMAGE_VHD) {
int non_transferred_sectors = mvhd_format_sectors(hdd_images[id].vhd, sector, count);
hdd_images[id].pos = sector + count - non_transferred_sectors - 1;
} else {
memset(empty_sector, 0, 512);
if (fseeko64(hdd_images[id].file, ((uint64_t) (sector) << 9LL) + hdd_images[id].base, SEEK_SET) == -1) {
fatal("Hard disk image %i: Zero error during seek\n", id);
return;
}
for (uint32_t i = 0; i < count; i++) {
if (feof(hdd_images[id].file))
break;
hdd_images[id].pos = sector + i;
fwrite(empty_sector, 512, 1, hdd_images[id].file);
}
}
}
int
hdd_image_zero_ex(uint8_t id, uint32_t sector, uint32_t count)
{
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
transfer_sectors = sectors - sector;
hdd_image_zero(id, sector, transfer_sectors);
if (count != transfer_sectors)
return 1;
return 0;
}
uint32_t
hdd_image_get_pos(uint8_t id)
{
return hdd_images[id].pos;
}
uint8_t
hdd_image_get_type(uint8_t id)
{
return hdd_images[id].type;
}
void
hdd_image_unload(uint8_t id, UNUSED(int fn_preserve))
{
if (strlen(hdd[id].fn) == 0)
return;
if (hdd_images[id].loaded) {
if (hdd_images[id].file != NULL) {
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
} else if (hdd_images[id].vhd != NULL) {
mvhd_close(hdd_images[id].vhd);
hdd_images[id].vhd = NULL;
}
hdd_images[id].loaded = 0;
}
hdd_images[id].last_sector = -1;
memset(hdd[id].fn, 0, sizeof(hdd[id].fn));
}
void
hdd_image_close(uint8_t id)
{
hdd_image_log("hdd_image_close(%i)\n", id);
if (!hdd_images[id].loaded)
return;
if (hdd_images[id].file != NULL) {
fclose(hdd_images[id].file);
hdd_images[id].file = NULL;
} else if (hdd_images[id].vhd != NULL) {
mvhd_close(hdd_images[id].vhd);
hdd_images[id].vhd = NULL;
}
memset(&hdd_images[id], 0, sizeof(hdd_image_t));
hdd_images[id].loaded = 0;
}
``` | /content/code_sandbox/src/disk/hdd_image.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,667 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* XT-IDE controller emulation.
*
* The XT-IDE project is intended to allow 8-bit ("XT") systems
* to use regular IDE drives. IDE is a standard based on the
* 16b PC/AT design, and so a special board (with its own BIOS)
* had to be created for this.
*
* XT-IDE is *NOT* the same as XTA, or X-IDE, which is an older
* standard where the actual MFM/RLL controller for the PC/XT
* was placed on the hard drive (hard drives where its drive
* type would end in "X" or "XT", such as the 8425XT.) This was
* more or less the original IDE, but since those systems were
* already on their way out, the newer IDE standard based on the
* PC/AT controller and 16b design became the IDE we now know.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/plat_unused.h>
#define ROM_PATH_XT "roms/hdd/xtide/ide_xt.bin"
#define ROM_PATH_XTP "roms/hdd/xtide/ide_xtp.bin"
#define ROM_PATH_AT "roms/hdd/xtide/ide_at.bin"
#define ROM_PATH_AT_386 "roms/hdd/xtide/ide_386.bin"
#define ROM_PATH_PS2 "roms/hdd/xtide/SIDE1V12.BIN"
#define ROM_PATH_PS2AT "roms/hdd/xtide/ide_at_1_1_5.bin"
typedef struct xtide_t {
void *ide_board;
uint8_t data_high;
rom_t bios_rom;
} xtide_t;
static void
xtide_write(uint16_t port, uint8_t val, void *priv)
{
xtide_t *xtide = (xtide_t *) priv;
switch (port & 0xf) {
case 0x0:
ide_writew(0x0, val | (xtide->data_high << 8), xtide->ide_board);
return;
case 0x1:
case 0x2:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
ide_writeb((port & 0xf), val, xtide->ide_board);
return;
case 0x8:
xtide->data_high = val;
return;
case 0xe:
ide_write_devctl(0x0, val, xtide->ide_board);
return;
default:
break;
}
}
static uint8_t
xtide_read(uint16_t port, void *priv)
{
xtide_t *xtide = (xtide_t *) priv;
uint16_t tempw = 0xffff;
switch (port & 0xf) {
case 0x0:
tempw = ide_readw(0x0, xtide->ide_board);
xtide->data_high = tempw >> 8;
break;
case 0x1:
case 0x2:
case 0x3:
case 0x4:
case 0x5:
case 0x6:
case 0x7:
tempw = ide_readb((port & 0xf), xtide->ide_board);
break;
case 0x8:
tempw = xtide->data_high;
break;
case 0xe:
tempw = ide_read_alt_status(0x0, xtide->ide_board);
break;
default:
break;
}
return (tempw & 0xff);
}
static void *
xtide_init(const device_t *info)
{
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0x00, sizeof(xtide_t));
rom_init(&xtide->bios_rom,
device_get_bios_file(info, device_get_config_bios("bios"), 0),
0xc8000, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
xtide->ide_board = ide_xtide_init();
io_sethandler(0x0300, 16,
xtide_read, NULL, NULL,
xtide_write, NULL, NULL, xtide);
return xtide;
}
static void *
xtide_at_init(const device_t *info)
{
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0x00, sizeof(xtide_t));
rom_init(&xtide->bios_rom,
device_get_bios_file(info, device_get_config_bios("bios"), 0),
0xc8000, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
device_add(&ide_isa_2ch_device);
return xtide;
}
static void *
xtide_acculogic_init(UNUSED(const device_t *info))
{
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0x00, sizeof(xtide_t));
rom_init(&xtide->bios_rom, ROM_PATH_PS2,
0xc8000, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
xtide->ide_board = ide_xtide_init();
io_sethandler(0x0360, 16,
xtide_read, NULL, NULL,
xtide_write, NULL, NULL, xtide);
return xtide;
}
static int
xtide_acculogic_available(void)
{
return (rom_present(ROM_PATH_PS2));
}
static void
xtide_close(void *priv)
{
xtide_t *xtide = (xtide_t *) priv;
free(xtide);
ide_xtide_close();
}
static void *
xtide_at_ps2_init(UNUSED(const device_t *info))
{
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0x00, sizeof(xtide_t));
rom_init(&xtide->bios_rom, ROM_PATH_PS2AT,
0xc8000, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
device_add(&ide_isa_2ch_device);
return xtide;
}
static int
xtide_at_ps2_available(void)
{
return (rom_present(ROM_PATH_PS2AT));
}
static void
xtide_at_close(void *priv)
{
xtide_t *xtide = (xtide_t *) priv;
free(xtide);
}
static const device_config_t xtide_config[] = {
// clang-format off
{
.name = "bios",
.description = "BIOS",
.type = CONFIG_BIOS,
.default_string = "xt",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "Regular XT", .internal_name = "xt", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { ROM_PATH_XT, "" } },
{ .name = "XT+ (V20/V30/8018x)", .internal_name = "xt_plus", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { ROM_PATH_XTP, "" } },
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_config_t xtide_at_config[] = {
// clang-format off
{
.name = "bios",
.description = "BIOS",
.type = CONFIG_BIOS,
.default_string = "at",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "Regular AT", .internal_name = "at", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { ROM_PATH_AT, "" } },
{ .name = "386", .internal_name = "at_386", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { ROM_PATH_AT_386, "" } },
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t xtide_device = {
.name = "PC/XT XTIDE",
.internal_name = "xtide",
.flags = DEVICE_ISA,
.local = 0,
.init = xtide_init,
.close = xtide_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = xtide_config
};
const device_t xtide_at_device = {
.name = "PC/AT XTIDE",
.internal_name = "xtide_at",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = xtide_at_init,
.close = xtide_at_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = xtide_at_config
};
const device_t xtide_acculogic_device = {
.name = "Acculogic XT IDE",
.internal_name = "xtide_acculogic",
.flags = DEVICE_ISA,
.local = 0,
.init = xtide_acculogic_init,
.close = xtide_close,
.reset = NULL,
{ .available = xtide_acculogic_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t xtide_at_ps2_device = {
.name = "PS/2 AT XTIDE (1.1.5)",
.internal_name = "xtide_at_ps2",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = xtide_at_ps2_init,
.close = xtide_at_close,
.reset = NULL,
{ .available = xtide_at_ps2_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_xtide.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,607 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1489 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_ALI5213_LOG
int ali5213_do_log = ENABLE_ALI5213_LOG;
static void
ali5213_log(const char *fmt, ...)
{
va_list ap;
if (ali5213_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ali5213_log(fmt, ...)
#endif
typedef struct ali5213_t {
uint8_t index;
uint8_t chip_id;
uint8_t regs[256];
} ali5213_t;
static void
ali5213_ide_handler(ali5213_t *dev)
{
ide_pri_disable();
ide_sec_disable();
if (dev->regs[0x01] & 0x01) {
ide_pri_enable();
if (!(dev->regs[0x35] & 0x40))
ide_sec_enable();
}
}
static void
ali5213_write(uint16_t addr, uint8_t val, void *priv)
{
ali5213_t *dev = (ali5213_t *) priv;
ali5213_log("[%04X:%08X] [W] %02X = %02X\n", CS, cpu_state.pc, addr, val);
switch (addr) {
case 0xf4: /* Usually it writes 30h here */
dev->chip_id = val;
break;
case 0xf8:
dev->index = val;
break;
case 0xfc:
if (dev->chip_id != 0x30)
break;
switch (dev->index) {
case 0x01: /* IDE Configuration Register */
dev->regs[dev->index] = val & 0x8f;
ali5213_ide_handler(dev);
break;
case 0x02: /* DBA Data Byte Cative Count for IDE-1 */
case 0x03: /* D0RA Disk 0 Read Active Count for IDE-1 */
case 0x04: /* D0WA Disk 0 Write Active Count for IDE-1 */
case 0x05: /* D1RA Disk 1 Read Active Count for IDE-1 */
case 0x06: /* D1WA Disk 1 Write Active Count for IDE-1 */
case 0x25: /* DBR Data Byte Recovery Count for IDE-1 */
case 0x26: /* D0RR Disk 0 Read Byte Recovery Count for IDE-1 */
case 0x27: /* D0WR Disk 0 Write Byte Recovery Count for IDE-1 */
case 0x28: /* D1RR Disk 1 Read Byte Recovery Count for IDE-1 */
case 0x29: /* D1WR Disk 1 Write Byte Recovery Count for IDE-1 */
case 0x2a: /* DBA Data Byte Cative Count for IDE-2 */
case 0x2b: /* D0RA Disk 0 Read Active Count for IDE-2 */
case 0x2c: /* D0WA Disk 0 Write Active Count for IDE-2 */
case 0x2d: /* D1RA Disk 1 Read Active Count for IDE-2 */
case 0x2e: /* D1WA Disk 1 Write Active Count for IDE-2 */
case 0x2f: /* DBR Data Byte Recovery Count for IDE-2 */
case 0x30: /* D0RR Disk 0 Read Byte Recovery Count for IDE-2 */
case 0x31: /* D0WR Disk 0 Write Byte Recovery Count for IDE-2 */
case 0x32: /* D1RR Disk 1 Read Byte Recovery Count for IDE-2 */
case 0x33: /* D1WR Disk 1 Write Byte Recovery Count for IDE-2 */
dev->regs[dev->index] = val & 0x1f;
break;
case 0x07: /* Buffer Mode Register 1 */
dev->regs[dev->index] = val;
break;
case 0x09: /* IDEPE1 IDE Port Enable Register 1 */
dev->regs[dev->index] = val & 0xc3;
break;
case 0x0a: /* Buffer Mode Register 2 */
dev->regs[dev->index] = val & 0x4f;
break;
case 0x0b: /* IDE Channel 1 Disk 0 Sector Byte Count Register 1 */
case 0x0d: /* IDE Channel 1 Disk 1 Sector Byte Count Register 1 */
case 0x0f: /* IDE Channel 2 Disk 0 Sector Byte Count Register 1 */
case 0x11: /* IDE Channel 2 Disk 1 Sector Byte Count Register 1 */
dev->regs[dev->index] = val & 0x03;
break;
case 0x0c: /* IDE Channel 1 Disk 0 Sector Byte Count Register 2 */
case 0x0e: /* IDE Channel 1 Disk 1 Sector Byte Count Register 2 */
case 0x10: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */
case 0x12: /* IDE Channel 2 Disk 1 Sector Byte Count Register 2 */
dev->regs[dev->index] = val & 0x1f;
break;
case 0x35: /* IDEPE3 IDE Port Enable Register 3 */
dev->regs[dev->index] = val;
ali5213_ide_handler(dev);
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
ali5213_read(uint16_t addr, void *priv)
{
const ali5213_t *dev = (ali5213_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0xf4:
ret = dev->chip_id;
break;
case 0xfc:
ret = dev->regs[dev->index];
break;
default:
break;
}
ali5213_log("[%04X:%08X] [R] %02X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static void
ali5213_reset(void *priv)
{
ali5213_t *dev = (ali5213_t *) priv;
memset(dev->regs, 0x00, 256);
ide_pri_disable();
ide_sec_disable();
/* IDE registers */
dev->regs[0x00] = 0x57;
dev->regs[0x01] = 0x02;
dev->regs[0x08] = 0xff;
dev->regs[0x09] = 0x41;
dev->regs[0x0c] = 0x02;
dev->regs[0x0e] = 0x02;
dev->regs[0x10] = 0x02;
dev->regs[0x12] = 0x02;
dev->regs[0x34] = 0xff;
dev->regs[0x35] = 0x01;
ali5213_ide_handler(dev);
}
static void
ali5213_close(void *priv)
{
ali5213_t *dev = (ali5213_t *) priv;
free(dev);
}
static void *
ali5213_init(UNUSED(const device_t *info))
{
ali5213_t *dev = (ali5213_t *) calloc(1, sizeof(ali5213_t));
/* M5213/M1489 IDE controller
F4h Chip ID we write always 30h onto it
F8h Index Port
FCh Data Port
*/
io_sethandler(0x0f4, 0x0001, ali5213_read, NULL, NULL, ali5213_write, NULL, NULL, dev);
io_sethandler(0x0f8, 0x0001, ali5213_read, NULL, NULL, ali5213_write, NULL, NULL, dev);
io_sethandler(0x0fc, 0x0001, ali5213_read, NULL, NULL, ali5213_write, NULL, NULL, dev);
device_add(info->local ? &ide_pci_2ch_device : &ide_vlb_2ch_device);
ali5213_reset(dev);
return dev;
}
const device_t ide_ali1489_device = {
.name = "ALi M1489 IDE",
.internal_name = "ali1489_ide",
.flags = 0,
.local = 1,
.init = ali5213_init,
.close = ali5213_close,
.reset = ali5213_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_ali5213_device = {
.name = "ALi M5213",
.internal_name = "ali5213",
.flags = 0,
.local = 0,
.init = ali5213_init,
.close = ali5213_close,
.reset = ali5213_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_ali5213.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,353 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Common code to handle all sorts of hard disk images.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <inttypes.h>
#include <string.h>
#include <stdlib.h>
#include <stdbool.h>
#include <math.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdd.h>
#include <86box/cdrom.h>
#include <86box/video.h>
#include "cpu.h"
#define HDD_OVERHEAD_TIME 50.0
hard_disk_t hdd[HDD_NUM];
int
hdd_init(void)
{
/* Clear all global data. */
memset(hdd, 0x00, sizeof(hdd));
return 0;
}
int
hdd_string_to_bus(char *str, int cdrom)
{
if (!strcmp(str, "none"))
return HDD_BUS_DISABLED;
if (!strcmp(str, "mfm")) {
if (cdrom) {
no_cdrom:
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_INVALID_CONFIG), plat_get_string(STRING_NO_ST506_ESDI_CDROM));
return 0;
}
return HDD_BUS_MFM;
}
if (!strcmp(str, "esdi")) {
if (cdrom)
goto no_cdrom;
return HDD_BUS_ESDI;
}
if (!strcmp(str, "ide"))
return HDD_BUS_IDE;
if (!strcmp(str, "atapi"))
return HDD_BUS_ATAPI;
if (!strcmp(str, "xta"))
return HDD_BUS_XTA;
if (!strcmp(str, "scsi"))
return HDD_BUS_SCSI;
return 0;
}
char *
hdd_bus_to_string(int bus, UNUSED(int cdrom))
{
char *s = "none";
switch (bus) {
default:
case HDD_BUS_DISABLED:
break;
case HDD_BUS_MFM:
s = "mfm";
break;
case HDD_BUS_XTA:
s = "xta";
break;
case HDD_BUS_ESDI:
s = "esdi";
break;
case HDD_BUS_IDE:
s = "ide";
break;
case HDD_BUS_ATAPI:
s = "atapi";
break;
case HDD_BUS_SCSI:
s = "scsi";
break;
}
return s;
}
int
hdd_is_valid(int c)
{
if (hdd[c].bus == HDD_BUS_DISABLED)
return 0;
if (strlen(hdd[c].fn) == 0)
return 0;
if ((hdd[c].tracks == 0) || (hdd[c].hpc == 0) || (hdd[c].spt == 0))
return 0;
return 1;
}
double
hdd_seek_get_time(hard_disk_t *hdd, uint32_t dst_addr, uint8_t operation, uint8_t continuous, double max_seek_time)
{
if (!hdd->speed_preset)
return HDD_OVERHEAD_TIME;
const hdd_zone_t *zone = NULL;
if (hdd->num_zones <= 0) {
fatal("hdd_seek_get_time(): hdd->num_zones < 0)\n");
return 0.0;
}
for (uint32_t i = 0; i < hdd->num_zones; i++) {
zone = &hdd->zones[i];
if (zone->end_sector >= dst_addr)
break;
}
double continuous_times[2][2] = {
{hdd->head_switch_usec, hdd->cyl_switch_usec },
{ zone->sector_time_usec, zone->sector_time_usec}
};
double times[2] = { HDD_OVERHEAD_TIME, hdd->avg_rotation_lat_usec };
uint32_t new_track = zone->start_track + ((dst_addr - zone->start_sector) / zone->sectors_per_track);
uint32_t new_cylinder = new_track / hdd->phy_heads;
uint32_t cylinder_diff = abs((int) hdd->cur_cylinder - (int) new_cylinder);
bool sequential = dst_addr == hdd->cur_addr + 1;
continuous = continuous && sequential;
double seek_time = 0.0;
if (continuous)
seek_time = continuous_times[new_track == hdd->cur_track][!!cylinder_diff];
else {
if (!cylinder_diff)
seek_time = times[operation != HDD_OP_SEEK];
else {
seek_time = hdd->cyl_switch_usec + (hdd->full_stroke_usec * (double) cylinder_diff / (double) hdd->phy_cyl) + ((operation != HDD_OP_SEEK) * hdd->avg_rotation_lat_usec);
}
}
if (!max_seek_time || seek_time <= max_seek_time) {
hdd->cur_addr = dst_addr;
hdd->cur_track = new_track;
hdd->cur_cylinder = new_cylinder;
}
return seek_time;
}
static void
hdd_readahead_update(hard_disk_t *hdd)
{
uint64_t elapsed_cycles;
double elapsed_us;
double seek_time;
int32_t max_read_ahead;
uint32_t space_needed;
hdd_cache_t *cache = &hdd->cache;
if (cache->ra_ongoing) {
hdd_cache_seg_t *segment = &cache->segments[cache->ra_segment];
elapsed_cycles = tsc - cache->ra_start_time;
elapsed_us = (double) elapsed_cycles / cpuclock * 1000000.0;
/* Do not overwrite data not yet read by host */
max_read_ahead = (segment->host_addr + cache->segment_size) - segment->ra_addr;
seek_time = 0.0;
for (int32_t i = 0; i < max_read_ahead; i++) {
seek_time += hdd_seek_get_time(hdd, segment->ra_addr, HDD_OP_READ, 1, elapsed_us - seek_time);
if (seek_time > elapsed_us)
break;
segment->ra_addr++;
}
if (segment->ra_addr > segment->lba_addr + cache->segment_size) {
space_needed = segment->ra_addr - (segment->lba_addr + cache->segment_size);
segment->lba_addr += space_needed;
}
}
}
static double
hdd_writecache_flush(hard_disk_t *hdd)
{
double seek_time = 0.0;
while (hdd->cache.write_pending) {
seek_time += hdd_seek_get_time(hdd, hdd->cache.write_addr, HDD_OP_WRITE, 1, 0);
hdd->cache.write_addr++;
hdd->cache.write_pending--;
}
return seek_time;
}
static void
hdd_writecache_update(hard_disk_t *hdd)
{
uint64_t elapsed_cycles;
double elapsed_us;
double seek_time;
if (hdd->cache.write_pending) {
elapsed_cycles = tsc - hdd->cache.write_start_time;
elapsed_us = (double) elapsed_cycles / cpuclock * 1000000.0;
seek_time = 0.0;
while (hdd->cache.write_pending) {
seek_time += hdd_seek_get_time(hdd, hdd->cache.write_addr, HDD_OP_WRITE, 1, elapsed_us - seek_time);
if (seek_time > elapsed_us)
break;
hdd->cache.write_addr++;
hdd->cache.write_pending--;
}
}
}
double
hdd_timing_write(hard_disk_t *hdd, uint32_t addr, uint32_t len)
{
double seek_time = 0.0;
uint32_t flush_needed;
if (!hdd->speed_preset)
return HDD_OVERHEAD_TIME;
hdd_readahead_update(hdd);
hdd_writecache_update(hdd);
hdd->cache.ra_ongoing = 0;
if (hdd->cache.write_pending && (addr != (hdd->cache.write_addr + hdd->cache.write_pending))) {
/* New request is not sequential to existing cache, need to flush it */
seek_time += hdd_writecache_flush(hdd);
}
if (!hdd->cache.write_pending) {
/* Cache is empty */
hdd->cache.write_addr = addr;
}
hdd->cache.write_pending += len;
if (hdd->cache.write_pending > hdd->cache.write_size) {
/* If request is bigger than free cache, flush some data first */
flush_needed = hdd->cache.write_pending - hdd->cache.write_size;
for (uint32_t i = 0; i < flush_needed; i++) {
seek_time += hdd_seek_get_time(hdd, hdd->cache.write_addr, HDD_OP_WRITE, 1, 0);
hdd->cache.write_addr++;
}
}
hdd->cache.write_start_time = tsc + (uint32_t) (seek_time * cpuclock / 1000000.0);
return seek_time;
}
double
hdd_timing_read(hard_disk_t *hdd, uint32_t addr, uint32_t len)
{
double seek_time = 0.0;
if (!hdd->speed_preset)
return HDD_OVERHEAD_TIME;
hdd_readahead_update(hdd);
hdd_writecache_update(hdd);
seek_time += hdd_writecache_flush(hdd);
hdd_cache_t *cache = &hdd->cache;
hdd_cache_seg_t *active_seg = &cache->segments[0];
for (uint32_t i = 0; i < cache->num_segments; i++) {
hdd_cache_seg_t *segment = &cache->segments[i];
if (!segment->valid) {
active_seg = segment;
continue;
}
if (segment->lba_addr <= addr && (segment->lba_addr + cache->segment_size) >= addr) {
/* Cache HIT */
segment->host_addr = addr;
active_seg = segment;
if (addr + len > segment->ra_addr) {
uint32_t need_read = (addr + len) - segment->ra_addr;
for (uint32_t j = 0; j < need_read; j++) {
seek_time += hdd_seek_get_time(hdd, segment->ra_addr, HDD_OP_READ, 1, 0.0);
segment->ra_addr++;
}
}
if (addr + len > segment->lba_addr + cache->segment_size) {
/* Need to erase some previously cached data */
uint32_t space_needed = (addr + len) - (segment->lba_addr + cache->segment_size);
segment->lba_addr += space_needed;
}
goto update_lru;
} else {
if (segment->lru > active_seg->lru)
active_seg = segment;
}
}
/* Cache MISS */
active_seg->lba_addr = addr;
active_seg->valid = 1;
active_seg->host_addr = addr;
active_seg->ra_addr = addr;
for (uint32_t i = 0; i < len; i++) {
seek_time += hdd_seek_get_time(hdd, active_seg->ra_addr, HDD_OP_READ, i != 0, 0.0);
active_seg->ra_addr++;
}
update_lru:
for (uint32_t i = 0; i < cache->num_segments; i++)
cache->segments[i].lru++;
active_seg->lru = 0;
cache->ra_ongoing = 1;
cache->ra_segment = active_seg->id;
cache->ra_start_time = tsc + (uint32_t) (seek_time * cpuclock / 1000000.0);
return seek_time;
}
static void
hdd_cache_init(hard_disk_t *hdd)
{
hdd_cache_t *cache = &hdd->cache;
cache->ra_segment = 0;
cache->ra_ongoing = 0;
cache->ra_start_time = 0;
for (uint32_t i = 0; i < cache->num_segments; i++) {
cache->segments[i].valid = 0;
cache->segments[i].lru = 0;
cache->segments[i].id = i;
cache->segments[i].ra_addr = 0;
cache->segments[i].host_addr = 0;
}
}
static void
hdd_zones_init(hard_disk_t *hdd)
{
uint32_t lba = 0;
uint32_t track = 0;
uint32_t tracks;
double revolution_usec = 60.0 / (double) hdd->rpm * 1000000.0;
hdd_zone_t *zone;
for (uint32_t i = 0; i < hdd->num_zones; i++) {
zone = &hdd->zones[i];
zone->start_sector = lba;
zone->start_track = track;
zone->sector_time_usec = revolution_usec / (double) zone->sectors_per_track;
tracks = zone->cylinders * hdd->phy_heads;
lba += tracks * zone->sectors_per_track;
zone->end_sector = lba - 1;
track += tracks - 1;
}
}
static hdd_preset_t hdd_speed_presets[] = {
// clang-format off
{ .name = "RAM Disk (max. speed)", .internal_name = "ramdisk", .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 32 },
{ .name = "[1989] 3500 RPM", .internal_name = "1989_3500rpm", .zones = 1, .avg_spt = 35, .heads = 2, .rpm = 3500, .full_stroke_ms = 40, .track_seek_ms = 8, .rcache_num_seg = 1, .rcache_seg_size = 16, .max_multiple = 8 },
{ .name = "[1992] 3600 RPM", .internal_name = "1992_3600rpm", .zones = 1, .avg_spt = 45, .heads = 2, .rpm = 3600, .full_stroke_ms = 30, .track_seek_ms = 6, .rcache_num_seg = 4, .rcache_seg_size = 16, .max_multiple = 8 },
{ .name = "[1994] 4500 RPM", .internal_name = "1994_4500rpm", .zones = 8, .avg_spt = 80, .heads = 4, .rpm = 4500, .full_stroke_ms = 26, .track_seek_ms = 5, .rcache_num_seg = 4, .rcache_seg_size = 32, .max_multiple = 16 },
{ .name = "[1996] 5400 RPM", .internal_name = "1996_5400rpm", .zones = 16, .avg_spt = 135, .heads = 4, .rpm = 5400, .full_stroke_ms = 24, .track_seek_ms = 3, .rcache_num_seg = 4, .rcache_seg_size = 64, .max_multiple = 16 },
{ .name = "[1997] 5400 RPM", .internal_name = "1997_5400rpm", .zones = 16, .avg_spt = 185, .heads = 6, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2.5, .rcache_num_seg = 8, .rcache_seg_size = 64, .max_multiple = 32 },
{ .name = "[1998] 5400 RPM", .internal_name = "1998_5400rpm", .zones = 16, .avg_spt = 300, .heads = 8, .rpm = 5400, .full_stroke_ms = 20, .track_seek_ms = 2, .rcache_num_seg = 8, .rcache_seg_size = 128, .max_multiple = 32 },
{ .name = "[2000] 7200 RPM", .internal_name = "2000_7200rpm", .zones = 16, .avg_spt = 350, .heads = 6, .rpm = 7200, .full_stroke_ms = 15, .track_seek_ms = 2, .rcache_num_seg = 16, .rcache_seg_size = 128, .max_multiple = 32 },
// clang-format on
};
int
hdd_preset_get_num(void)
{
return sizeof(hdd_speed_presets) / sizeof(hdd_preset_t);
}
const char *
hdd_preset_getname(int preset)
{
return hdd_speed_presets[preset].name;
}
const char *
hdd_preset_get_internal_name(int preset)
{
return hdd_speed_presets[preset].internal_name;
}
int
hdd_preset_get_from_internal_name(char *s)
{
int c = 0;
for (int i = 0; i < (sizeof(hdd_speed_presets) / sizeof(hdd_preset_t)); i++) {
if (!strcmp(hdd_speed_presets[c].internal_name, s))
return c;
c++;
}
return 0;
}
void
hdd_preset_apply(int hdd_id)
{
hard_disk_t *hd = &hdd[hdd_id];
double revolution_usec;
double zone_percent;
uint32_t disk_sectors;
uint32_t sectors_per_surface;
uint32_t cylinders;
uint32_t cylinders_per_zone;
uint32_t total_sectors = 0;
uint32_t spt;
uint32_t zone_sectors;
if (hd->speed_preset >= hdd_preset_get_num())
hd->speed_preset = 0;
const hdd_preset_t *preset = &hdd_speed_presets[hd->speed_preset];
hd->cache.num_segments = preset->rcache_num_seg;
hd->cache.segment_size = preset->rcache_seg_size;
hd->max_multiple_block = preset->max_multiple;
if (!hd->speed_preset)
return;
hd->phy_heads = preset->heads;
hd->rpm = preset->rpm;
revolution_usec = 60.0 / (double) hd->rpm * 1000000.0;
hd->avg_rotation_lat_usec = revolution_usec / 2;
hd->full_stroke_usec = preset->full_stroke_ms * 1000;
hd->head_switch_usec = preset->track_seek_ms * 1000;
hd->cyl_switch_usec = preset->track_seek_ms * 1000;
hd->cache.write_size = 64;
hd->num_zones = preset->zones;
disk_sectors = hd->tracks * hd->hpc * hd->spt;
sectors_per_surface = (uint32_t) ceil((double) disk_sectors / (double) hd->phy_heads);
cylinders = (uint32_t) ceil((double) sectors_per_surface / (double) preset->avg_spt);
hd->phy_cyl = cylinders;
cylinders_per_zone = cylinders / preset->zones;
for (uint32_t i = 0; i < preset->zones; i++) {
zone_percent = i * 100 / (double) preset->zones;
if (i < preset->zones - 1) {
/* Function for realistic zone sector density */
double spt_percent = -0.00341684 * pow(zone_percent, 2) - 0.175811 * zone_percent + 118.48;
spt = (uint32_t) ceil((double) preset->avg_spt * spt_percent / 100);
} else
spt = (uint32_t) ceil((double) (disk_sectors - total_sectors) / (double) (cylinders_per_zone * preset->heads));
zone_sectors = spt * cylinders_per_zone * preset->heads;
total_sectors += zone_sectors;
hd->zones[i].cylinders = cylinders_per_zone;
hd->zones[i].sectors_per_track = spt;
}
hdd_zones_init(hd);
hdd_cache_init(hd);
}
``` | /content/code_sandbox/src/disk/hdd.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,680 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Driver for the IBM PC-XT Fixed Disk controller.
*
* The original controller shipped by IBM was made by Xebec, and
* several variations had been made:
*
* #1 Original, single drive (ST412), 10MB, 2 heads.
* #2 Update, single drive (ST412) but with option for a
* switch block that can be used to 'set' the actual
* drive type. Four switches are defined, where switches
* 1 and 2 define drive0, and switches 3 and 4 drive1.
*
* 0 ON ON 306 2 0
* 1 ON OFF 375 8 0
* 2 OFF ON 306 6 256
* 3 OFF OFF 306 4 0
*
* The latter option is the default, in use on boards
* without the switch block option.
*
* #3 Another updated board, mostly to accomodate the new
* 20MB disk now being shipped. The controller can have
* up to 2 drives, the type of which is set using the
* switch block:
*
* SW1 SW2 CYLS HD SPT WPC
* 0 ON ON 306 4 17 0
* 1 ON OFF 612 4 17 0 (type 16)
* 2 OFF ON 615 4 17 300 (Seagate ST-225, 2)
* 3 OFF OFF 306 8 17 128 (IBM WD25, 13)
*
* Examples of #3 are IBM/Xebec, WD10004A-WX1 and ST11R.
*
* Since all controllers (including the ones made by DTC) use
* (mostly) the same API, we keep them all in this module.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/ui.h>
#include <86box/plat.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#define ST506_XT_TYPE_XEBEC 0
#define ST506_XT_TYPE_WDXT_GEN 1
#define ST506_XT_TYPE_DTC_5150X 2
#define ST506_XT_TYPE_ST11M 11
#define ST506_XT_TYPE_ST11R 12
#define ST506_XT_TYPE_WD1002A_WX1 21
#define ST506_XT_TYPE_WD1002A_WX1_NOBIOS 22
#define ST506_XT_TYPE_WD1002A_27X 23
#define ST506_XT_TYPE_WD1004A_WX1 24
#define ST506_XT_TYPE_WD1004_27X 25
#define ST506_XT_TYPE_WD1004A_27X 26
#define ST506_XT_TYPE_VICTOR_V86P 27
#define ST506_XT_TYPE_TOSHIBA_T1200 28
#define XEBEC_BIOS_FILE "roms/hdd/st506/ibm_xebec_62x0822_1985.bin"
#define WDXT_GEN_BIOS_FILE "roms/hdd/st506/wdxt-gen/62-000128-000.bin"
#define DTC_BIOS_FILE "roms/hdd/st506/dtc_cxd21a.bin"
#define ST11_BIOS_FILE_OLD "roms/hdd/st506/st11_bios_vers_1.7.bin"
#define ST11_BIOS_FILE_NEW "roms/hdd/st506/st11_bios_vers_2.0.bin"
#define WD1002A_WX1_BIOS_FILE "roms/hdd/st506/wd1002a_wx1-62-000094-032.bin"
#define WD1004A_WX1_BIOS_FILE "roms/hdd/st506/western_digital_WD1004A-27X.bin"
/* SuperBIOS was for both the WX1 and 27X, users jumpers readout to determine
if to use 26 sectors per track, 26 -> 17 sectors per track translation, or
17 sectors per track. */
#define WD1002A_27X_BIOS_FILE "roms/hdd/st506/wd1002a_27x-62-000094-032.bin"
#define WD1004_27X_BIOS_FILE "roms/hdd/st506/western_digital_WD1004A-27X.bin"
#define WD1004A_27X_BIOS_FILE "roms/hdd/st506/western_digital_WD1004A-27X.bin"
#define VICTOR_V86P_BIOS_FILE "roms/machines/v86p/2793VG.10010688.rom"
#define ST506_TIME (250 * TIMER_USEC)
#define ST506_TIME_MS (1000 * TIMER_USEC)
/* MFM and RLL use different sectors/track. */
#define SECTOR_SIZE 512
#define MFM_SECTORS 17
#define RLL_SECTORS 26
/* Status register. */
#define STAT_REQ 0x01 /* controller ready */
#define STAT_IO 0x02 /* input, data to host */
#define STAT_CD 0x04 /* command mode (else data) */
#define STAT_BSY 0x08 /* controller is busy */
#define STAT_DRQ 0x10 /* controller needs DMA */
#define STAT_IRQ 0x20 /* interrupt, we have info */
/* DMA/IRQ enable register. */
#define DMA_ENA 0x01 /* DMA operation enabled */
#define IRQ_ENA 0x02 /* IRQ operation enabled */
/* Error codes in sense report. */
#define ERR_BV 0x80
#define ERR_TYPE_MASK 0x30
#define ERR_TYPE_SHIFT 4
#define ERR_TYPE_DRIVE 0x00
#define ERR_TYPE_CONTROLLER 0x01
#define ERR_TYPE_COMMAND 0x02
#define ERR_TYPE_MISC 0x03
/* No, um, errors.. */
#define ERR_NONE 0x00
/* Group 0: drive errors. */
#define ERR_NO_SEEK 0x02 /* no seek_complete */
#define ERR_WR_FAULT 0x03 /* write fault */
#define ERR_NOT_READY 0x04 /* drive not ready */
#define ERR_NO_TRACK0 0x06 /* track 0 not found */
#define ERR_STILL_SEEKING 0x08 /* drive is still seeking */
#define ERR_NOT_AVAILABLE 0x09 /* drive not available */
/* Group 1: controller errors. */
#define ERR_ID_FAULT 0x10 /* could not read ID field */
#define ERR_UNC_ERR 0x11 /* uncorrectable data */
#define ERR_SECTOR_ADDR 0x12 /* sector address */
#define ERR_DATA_ADDR 0x13 /* data mark not found */
#define ERR_TARGET_SECTOR 0x14 /* target sector not found */
#define ERR_SEEK_ERROR 0x15 /* seek error- cyl not found */
#define ERR_CORR_ERR 0x18 /* correctable data */
#define ERR_BAD_TRACK 0x19 /* track is flagged as bad */
#define ERR_ALT_TRACK_FLAGGED 0x1c /* alt trk not flagged as alt */
#define ERR_ALT_TRACK_ACCESS 0x1e /* illegal access to alt trk */
#define ERR_NO_RECOVERY 0x1f /* recovery mode not avail */
/* Group 2: command errors. */
#define ERR_BAD_COMMAND 0x20 /* invalid command */
#define ERR_ILLEGAL_ADDR 0x21 /* address beyond disk size */
#define ERR_BAD_PARAMETER 0x22 /* invalid command parameter */
/* Group 3: misc errors. */
#define ERR_BAD_RAM 0x30 /* controller has bad RAM */
#define ERR_BAD_ROM 0x31 /* ROM failed checksum test */
#define ERR_CRC_FAIL 0x32 /* CRC circuit failed test */
/* Controller commands. */
#define CMD_TEST_DRIVE_READY 0x00
#define CMD_RECALIBRATE 0x01
/* reserved 0x02 */
#define CMD_STATUS 0x03
#define CMD_FORMAT_DRIVE 0x04
#define CMD_VERIFY 0x05
#define CMD_FORMAT_TRACK 0x06
#define CMD_FORMAT_BAD_TRACK 0x07
#define CMD_READ 0x08
#define CMD_REASSIGN 0x09
#define CMD_WRITE 0x0a
#define CMD_SEEK 0x0b
#define CMD_SPECIFY 0x0c
#define CMD_READ_ECC_BURST_LEN 0x0d
#define CMD_READ_BUFFER 0x0e
#define CMD_WRITE_BUFFER 0x0f
#define CMD_ALT_TRACK 0x11
#define CMD_INQUIRY_ST11 0x12 /* ST-11 BIOS */
#define CMD_V86P_POWEROFF 0x1a /* Victor V86P */
#define CMD_RAM_DIAGNOSTIC 0xe0
/* reserved 0xe1 */
/* reserved 0xe2 */
#define CMD_DRIVE_DIAGNOSTIC 0xe3
#define CMD_CTRLR_DIAGNOSTIC 0xe4
#define CMD_READ_LONG 0xe5
#define CMD_WRITE_LONG 0xe6
#define CMD_FORMAT_ST11 0xf6 /* ST-11 BIOS */
#define CMD_GET_GEOMETRY_ST11 0xf8 /* ST-11 BIOS */
#define CMD_SET_GEOMETRY_ST11 0xfa /* ST-11 BIOS */
#define CMD_WRITE_GEOMETRY_ST11 0xfc /* ST-11 BIOS 2.0 */
#define CMD_GET_DRIVE_PARAMS_DTC 0xfb /* DTC */
#define CMD_SET_STEP_RATE_DTC 0xfc /* DTC */
#define CMD_SET_GEOMETRY_DTC 0xfe /* DTC */
#define CMD_GET_GEOMETRY_DTC 0xff /* DTC */
enum {
STATE_IDLE,
STATE_RECEIVE_COMMAND,
STATE_START_COMMAND,
STATE_RECEIVE_DATA,
STATE_RECEIVED_DATA,
STATE_SEND_DATA,
STATE_SENT_DATA,
STATE_COMPLETION_BYTE,
STATE_DONE
};
typedef struct drive_t {
int8_t present;
uint8_t hdd_num;
uint8_t interleave; /* default interleave */
char pad;
uint16_t cylinder; /* current cylinder */
uint8_t spt; /* physical parameters */
uint8_t hpc;
uint16_t tracks;
uint8_t cfg_spt; /* configured parameters */
uint8_t cfg_hpc;
uint16_t cfg_cyl;
} drive_t;
typedef struct hdc_t {
uint8_t type; /* controller type */
uint8_t spt; /* sectors-per-track for controller */
uint16_t base; /* controller configuration */
int8_t irq;
int8_t dma;
uint8_t switches;
uint8_t misc;
uint8_t nr_err;
uint8_t err_bv;
uint8_t cur_sec;
uint8_t pad;
uint32_t bios_addr;
uint32_t bios_size;
uint32_t bios_ram;
rom_t bios_rom;
int state; /* operational data */
uint8_t irq_dma;
uint8_t error;
uint8_t status;
int8_t cyl_off; /* for ST-11, cylinder0 offset */
pc_timer_t timer;
uint8_t command[6]; /* current command request */
int drive_sel;
int sector;
int head;
int cylinder;
int count;
uint8_t compl ; /* current request completion code */
int buff_pos; /* pointers to the RAM buffer */
int buff_cnt;
drive_t drives[MFM_NUM]; /* the attached drives */
uint8_t scratch[64]; /* ST-11 scratchpad RAM */
uint8_t buff[SECTOR_SIZE + 4]; /* sector buffer RAM (+ ECC bytes) */
} hdc_t;
/* Supported drives table for the Xebec controller. */
typedef struct hd_type_t {
uint16_t tracks;
uint8_t hpc;
uint8_t spt;
} hd_type_t;
hd_type_t hd_types[4] = {
// clang-format off
{ 306, 4, MFM_SECTORS}, /* type 0 */
{ 612, 4, MFM_SECTORS}, /* type 16 */
{ 615, 4, MFM_SECTORS}, /* type 2 */
{ 306, 8, MFM_SECTORS} /* type 13 */
// clang-format on
};
hd_type_t hd_types_olivetti[16] = {
// clang-format off
{ 697, 5, MFM_SECTORS},
{ 612, 4, MFM_SECTORS}, /* type 16 */
{ 612, 4, MFM_SECTORS}, /* type 16 */
{ 306, 4, MFM_SECTORS}, /* type 0 */
{ 612, 8, MFM_SECTORS},
{ 820, 6, MFM_SECTORS},
{ 820, 6, MFM_SECTORS},
{ 823, 10, MFM_SECTORS},
{ 981, 5, MFM_SECTORS},
{ 981, 5, MFM_SECTORS},
{1024, 8, MFM_SECTORS},
{1024, 9, MFM_SECTORS},
{ 872, 5, MFM_SECTORS},
{ 612, 4, MFM_SECTORS}, /* type 16 */
{ 612, 4, MFM_SECTORS}, /* type 16 */
{ 306, 4, MFM_SECTORS} /* "not present" with the second hard disk */
// clang-format on
};
#ifdef ENABLE_ST506_XT_LOG
int st506_xt_do_log = ENABLE_ST506_XT_LOG;
static void
st506_xt_log(const char *fmt, ...)
{
va_list ap;
if (st506_xt_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define st506_xt_log(fmt, ...)
#endif
static void
st506_complete(hdc_t *dev)
{
dev->status = STAT_REQ | STAT_CD | STAT_IO | STAT_BSY;
dev->state = STATE_COMPLETION_BYTE;
if (dev->irq_dma & DMA_ENA)
dma_set_drq(dev->dma, 0);
if (dev->irq_dma & IRQ_ENA) {
dev->status |= STAT_IRQ;
picint(1 << dev->irq);
}
}
static void
st506_error(hdc_t *dev, uint8_t err)
{
dev->compl |= 0x02;
dev->error = err;
}
static int
get_sector(hdc_t *dev, drive_t *drive, off64_t *addr)
{
if (!drive->present) {
/* No need to log this. */
dev->error = dev->nr_err;
return 0;
}
#if 0
if (drive->cylinder != dev->cylinder) {
# ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: get_sector: wrong cylinder\n");
# endif
dev->error = ERR_ILLEGAL_ADDR;
return(0);
}
#endif
if (dev->head >= drive->cfg_hpc) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: get_sector: past end of configured heads\n");
#endif
dev->error = ERR_ILLEGAL_ADDR;
return 0;
}
if (dev->sector >= drive->cfg_spt) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: get_sector: past end of configured sectors\n");
#endif
dev->error = ERR_ILLEGAL_ADDR;
return 0;
}
*addr = ((((off64_t) dev->cylinder * drive->cfg_hpc) + dev->head) * drive->cfg_spt) + dev->sector;
return 1;
}
static void
next_sector(hdc_t *dev, drive_t *drive)
{
if (++dev->sector >= drive->cfg_spt) {
dev->sector = 0;
if (++dev->head >= drive->cfg_hpc) {
dev->head = 0;
if (++drive->cylinder >= drive->cfg_cyl) {
/*
* This really is an error, we cannot move
* past the end of the drive, which should
* result in an ERR_ILLEGAL_ADDR. --FvK
*/
drive->cylinder = drive->cfg_cyl - 1;
} else
dev->cylinder++;
}
}
}
/* Extract the CHS info from a command block. */
static int
get_chs(hdc_t *dev, drive_t *drive)
{
dev->err_bv = 0x80;
dev->head = dev->command[1] & 0x1f;
/* 6 bits are used for the sector number even on the IBM PC controller. */
dev->sector = dev->command[2] & 0x3f;
dev->count = dev->command[4];
if (((dev->type == ST506_XT_TYPE_ST11M) || (dev->type == ST506_XT_TYPE_ST11R)) && (dev->command[0] >= 0xf0))
dev->cylinder = 0;
else {
dev->cylinder = dev->command[3] | ((dev->command[2] & 0xc0) << 2);
dev->cylinder += dev->cyl_off; /* for ST-11 */
}
if (dev->cylinder >= drive->cfg_cyl) {
/*
* This really is an error, we cannot move
* past the end of the drive, which should
* result in an ERR_ILLEGAL_ADDR. --FvK
*/
drive->cylinder = drive->cfg_cyl - 1;
return 0;
}
drive->cylinder = dev->cylinder;
return 1;
}
static int
get_chs_format(hdc_t *dev, drive_t *drive)
{
dev->err_bv = 0x80;
dev->head = dev->command[1] & 0x1f;
/* 6 bits are used for the sector number even on the IBM PC controller. */
dev->sector = 1;
dev->count = dev->command[4];
if (((dev->type == ST506_XT_TYPE_ST11M) || (dev->type == ST506_XT_TYPE_ST11R)) && (dev->command[0] >= 0xf0))
dev->cylinder = 0;
else {
dev->cylinder = dev->command[3] | ((dev->command[2] & 0xc0) << 2);
dev->cylinder += dev->cyl_off; /* for ST-11 */
}
if (dev->cylinder >= drive->cfg_cyl) {
/*
* This really is an error, we cannot move
* past the end of the drive, which should
* result in an ERR_ILLEGAL_ADDR. --FvK
*/
drive->cylinder = drive->cfg_cyl - 1;
return 0;
}
drive->cylinder = dev->cylinder;
return 1;
}
static void
st506_callback(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
drive_t *drive;
off64_t addr;
uint32_t capac;
int val;
/* Get the drive info. Note that the API supports up to 8 drives! */
dev->drive_sel = (dev->command[1] >> 5) & 0x07;
drive = &dev->drives[dev->drive_sel];
/* Preset the completion byte to "No error" and the selected drive. */
dev->compl = (dev->drive_sel << 5) | ERR_NONE;
if (dev->command[0] != 3)
dev->err_bv = 0x00;
switch (dev->command[0]) {
case CMD_TEST_DRIVE_READY:
st506_xt_log("ST506: TEST_READY(%i) = %i\n",
dev->drive_sel, drive->present);
if (!drive->present)
st506_error(dev, dev->nr_err);
st506_complete(dev);
break;
case CMD_RECALIBRATE:
switch (dev->state) {
case STATE_START_COMMAND:
st506_xt_log("ST506: RECALIBRATE(%i) [%i]\n",
dev->drive_sel, drive->present);
if (!drive->present) {
st506_error(dev, dev->nr_err);
st506_complete(dev);
break;
}
/* Wait 20msec. */
timer_advance_u64(&dev->timer, ST506_TIME_MS * 20);
dev->cylinder = dev->cyl_off;
drive->cylinder = dev->cylinder;
dev->state = STATE_DONE;
break;
case STATE_DONE:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_STATUS:
switch (dev->state) {
case STATE_START_COMMAND:
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: STATUS\n");
#endif
dev->buff_pos = 0;
dev->buff_cnt = 4;
dev->buff[0] = dev->err_bv | dev->error;
dev->error = 0;
/* Give address of last operation. */
dev->buff[1] = (dev->drive_sel ? 0x20 : 0) | dev->head;
dev->buff[2] = ((dev->cylinder & 0x0300) >> 2) | dev->sector;
dev->buff[3] = (dev->cylinder & 0xff);
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
dev->state = STATE_SEND_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_FORMAT_DRIVE:
switch (dev->state) {
case STATE_START_COMMAND:
(void) get_chs(dev, drive);
st506_xt_log("ST506: FORMAT_DRIVE(%i) interleave=%i\n",
dev->drive_sel, dev->command[4]);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_SEND_DATA;
break;
case STATE_SEND_DATA: /* wrong, but works */
if (!get_sector(dev, drive, &addr)) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
/* FIXME: should be drive->capac, not ->spt */
capac = (drive->tracks - 1) * drive->hpc * drive->spt;
hdd_image_zero(drive->hdd_num, addr, capac);
/* Wait 20msec per cylinder. */
timer_advance_u64(&dev->timer, ST506_TIME_MS * 20);
dev->state = STATE_SENT_DATA;
break;
case STATE_SENT_DATA:
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_VERIFY:
switch (dev->state) {
case STATE_START_COMMAND:
(void) get_chs(dev, drive);
st506_xt_log("ST506: VERIFY(%i, %i/%i/%i, %i)\n",
dev->drive_sel, dev->cylinder,
dev->head, dev->sector, dev->count);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_SEND_DATA;
break;
case STATE_SEND_DATA:
if (dev->count-- == 0) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
}
if (!get_sector(dev, drive, &addr)) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
next_sector(dev, drive);
timer_advance_u64(&dev->timer, ST506_TIME);
break;
default:
break;
}
break;
case CMD_FORMAT_ST11: /* This is really "Format cylinder 0" */
if ((dev->type < ST506_XT_TYPE_ST11M) || (dev->type > ST506_XT_TYPE_ST11R)) {
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
break;
}
fallthrough;
case CMD_FORMAT_TRACK:
case CMD_FORMAT_BAD_TRACK:
switch (dev->state) {
case STATE_START_COMMAND:
(void) get_chs_format(dev, drive);
st506_xt_log("ST506: FORMAT_%sTRACK(%i, %i/%i)\n",
(dev->command[0] == CMD_FORMAT_BAD_TRACK) ? "BAD_" : "",
dev->drive_sel, dev->cylinder, dev->head);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_SEND_DATA;
break;
case STATE_SEND_DATA: /* wrong, but works */
if (!get_sector(dev, drive, &addr)) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
hdd_image_zero(drive->hdd_num,
addr, drive->cfg_spt);
/* Wait 20 msec per cylinder. */
timer_advance_u64(&dev->timer, ST506_TIME_MS * 20);
dev->state = STATE_SENT_DATA;
break;
case STATE_SENT_DATA:
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_GET_GEOMETRY_ST11: /* "Get geometry" is really "Read cylinder 0" */
if ((dev->type < ST506_XT_TYPE_ST11M) || (dev->type > ST506_XT_TYPE_ST11R)) {
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
break;
}
fallthrough;
case CMD_READ:
#if 0
case CMD_READ_LONG:
#endif
switch (dev->state) {
case STATE_START_COMMAND:
(void) get_chs(dev, drive);
st506_xt_log("ST506: READ%s(%i, %i/%i/%i, %i)\n",
(dev->command[0] == CMD_READ_LONG) ? "_LONG" : "",
dev->drive_sel, dev->cylinder,
dev->head, dev->sector, dev->count);
if (!get_sector(dev, drive, &addr)) {
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
/* Read data from the image. */
hdd_image_read(drive->hdd_num, addr, 1,
(uint8_t *) dev->buff);
/* Set up the data transfer. */
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
if (dev->command[0] == CMD_READ_LONG)
dev->buff_cnt += 4;
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_SEND_DATA;
break;
case STATE_SEND_DATA:
for (; dev->buff_pos < dev->buff_cnt; dev->buff_pos++) {
val = dma_channel_write(dev->dma, dev->buff[dev->buff_pos]);
if (val == DMA_NODATA) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: CMD_READ out of data!\n");
#endif
st506_error(dev, ERR_NO_RECOVERY);
st506_complete(dev);
return;
}
}
dma_set_drq(dev->dma, 0);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_SENT_DATA;
break;
case STATE_SENT_DATA:
if (--dev->count == 0) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
break;
}
next_sector(dev, drive);
if (!get_sector(dev, drive, &addr)) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
/* Read data from the image. */
hdd_image_read(drive->hdd_num, addr, 1,
(uint8_t *) dev->buff);
/* Set up the data transfer. */
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_SEND_DATA;
break;
default:
break;
}
break;
case CMD_SET_GEOMETRY_ST11: /* "Set geometry" is really "Write cylinder 0" */
if (dev->type == ST506_XT_TYPE_DTC_5150X) {
/* DTC sends this... */
st506_complete(dev);
break;
} else if ((dev->type < ST506_XT_TYPE_ST11M) || (dev->type > ST506_XT_TYPE_ST11R)) {
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
break;
}
fallthrough;
case CMD_WRITE:
#if 0
case CMD_WRITE_LONG:
#endif
switch (dev->state) {
case STATE_START_COMMAND:
(void) get_chs(dev, drive);
st506_xt_log("ST506: WRITE%s(%i, %i/%i/%i, %i)\n",
(dev->command[0] == CMD_WRITE_LONG) ? "_LONG" : "",
dev->drive_sel, dev->cylinder,
dev->head, dev->sector, dev->count);
if (!get_sector(dev, drive, &addr)) {
st506_error(dev, ERR_BAD_PARAMETER);
st506_complete(dev);
return;
}
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
/* Set up the data transfer. */
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
if (dev->command[0] == CMD_WRITE_LONG)
dev->buff_cnt += 4;
dev->status = STAT_BSY | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_RECEIVE_DATA;
break;
case STATE_RECEIVE_DATA:
for (; dev->buff_pos < dev->buff_cnt; dev->buff_pos++) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: CMD_WRITE out of data!\n");
#endif
st506_error(dev, ERR_NO_RECOVERY);
st506_complete(dev);
return;
}
dev->buff[dev->buff_pos] = val & 0xff;
}
dma_set_drq(dev->dma, 0);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_RECEIVED_DATA;
break;
case STATE_RECEIVED_DATA:
if (!get_sector(dev, drive, &addr)) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_error(dev, dev->error);
st506_complete(dev);
return;
}
/* Write data to image. */
hdd_image_write(drive->hdd_num, addr, 1,
(uint8_t *) dev->buff);
if (--dev->count == 0) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
break;
}
next_sector(dev, drive);
/* Set up the data transfer. */
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
dev->status = STAT_BSY | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_RECEIVE_DATA;
break;
default:
break;
}
break;
case CMD_SEEK:
if (drive->present) {
val = get_chs(dev, drive);
st506_xt_log("ST506: SEEK(%i, %i) [%i]\n",
dev->drive_sel, drive->cylinder, val);
if (!val)
st506_error(dev, ERR_SEEK_ERROR);
} else
st506_error(dev, dev->nr_err);
st506_complete(dev);
break;
case CMD_SPECIFY:
switch (dev->state) {
case STATE_START_COMMAND:
dev->buff_pos = 0;
dev->buff_cnt = 8;
dev->status = STAT_BSY | STAT_REQ;
dev->state = STATE_RECEIVE_DATA;
break;
case STATE_RECEIVED_DATA:
drive->cfg_cyl = dev->buff[1] | (dev->buff[0] << 8);
drive->cfg_hpc = dev->buff[2];
/* For a 615/4/26 we get 666/2/31 geometry. */
st506_xt_log("ST506: drive%i: cyls=%i, heads=%i\n",
dev->drive_sel, drive->cfg_cyl, drive->cfg_hpc);
if ((dev->type >= ST506_XT_TYPE_VICTOR_V86P) && (drive->cfg_hpc == 2)) {
/*
* On Victor V86P, there's a disagreement between
* the physical geometry, what the controller
* pretends it to be, and what the BIOS uses.
*
* The disk physically has 2/34 heads/sectors per
* track, but it is treated as 4/17 in order to
* look like a regular type 3 drive (see [1],
* line 1859). The controller accepts the 4/17
* geometry, so this should not really matter.
*
* However, the BIOS issues SPECIFY (see [1],
* line 2089) with head count of two. Let's
* hardwire the correct number instead, just like
* the real hardware seems to.
*
* [1] path_to_url
*/
drive->cfg_hpc = 4;
st506_xt_log("ST506: drive%i: corrected to heads=%i\n",
dev->drive_sel, drive->cfg_hpc);
}
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_READ_ECC_BURST_LEN:
switch (dev->state) {
case STATE_START_COMMAND:
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: READ_ECC_BURST_LEN\n");
#endif
dev->buff_pos = 0;
dev->buff_cnt = 1;
dev->buff[0] = 0; /* 0 bits */
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
dev->state = STATE_SEND_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_READ_BUFFER:
switch (dev->state) {
case STATE_START_COMMAND:
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
st506_xt_log("ST506: READ_BUFFER (%i)\n",
dev->buff_cnt);
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_SEND_DATA;
break;
case STATE_SEND_DATA:
for (; dev->buff_pos < dev->buff_cnt; dev->buff_pos++) {
val = dma_channel_write(dev->dma, dev->buff[dev->buff_pos]);
if (val == DMA_NODATA) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: CMD_READ_BUFFER out of data!\n");
#endif
st506_error(dev, ERR_NO_RECOVERY);
st506_complete(dev);
return;
}
}
dma_set_drq(dev->dma, 0);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_SENT_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_WRITE_BUFFER:
switch (dev->state) {
case STATE_START_COMMAND:
dev->buff_pos = 0;
dev->buff_cnt = SECTOR_SIZE;
st506_xt_log("ST506: WRITE_BUFFER (%i)\n",
dev->buff_cnt);
dev->status = STAT_BSY | STAT_REQ;
if (dev->irq_dma & DMA_ENA) {
timer_advance_u64(&dev->timer, ST506_TIME);
dma_set_drq(dev->dma, 1);
}
dev->state = STATE_RECEIVE_DATA;
break;
case STATE_RECEIVE_DATA:
for (; dev->buff_pos < dev->buff_cnt; dev->buff_pos++) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: CMD_WRITE_BUFFER out of data!\n");
#endif
st506_error(dev, ERR_NO_RECOVERY);
st506_complete(dev);
return;
}
dev->buff[dev->buff_pos] = val & 0xff;
}
dma_set_drq(dev->dma, 0);
timer_advance_u64(&dev->timer, ST506_TIME);
dev->state = STATE_RECEIVED_DATA;
break;
case STATE_RECEIVED_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_INQUIRY_ST11:
if (dev->type == ST506_XT_TYPE_ST11M || dev->type == ST506_XT_TYPE_ST11R)
switch (dev->state) {
case STATE_START_COMMAND:
st506_xt_log("ST506: INQUIRY (type=%i)\n", dev->type);
dev->buff_pos = 0;
dev->buff_cnt = 2;
dev->buff[0] = 0x80; /* "ST-11" */
if (dev->spt == 17)
dev->buff[0] |= 0x40; /* MFM */
dev->buff[1] = dev->misc; /* revision */
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
dev->state = STATE_SEND_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
else {
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
}
break;
case CMD_V86P_POWEROFF:
if (dev->type >= ST506_XT_TYPE_VICTOR_V86P) {
/*
* Main BIOS (not the option ROM on disk) issues this.
* Not much we can do, since we don't have a physical disk
* to spin down, but handle this anyways so that we log
* something more reasonable than "unknown command".
*
* Entirely undocumented, but this is what's been observed:
* BIOS setting | Command sent
* 1 minutes | 1a 00 00 0c 02 00
* 2 minutes | 1a 00 00 18 02 00
* 3 minutes | 1a 00 00 24 02 00
* 4 minutes | 1a 00 00 30 02 00
* 5 minutes | 1a 00 00 3c 02 00
* off | 1a 00 00 00 02 00
*/
if (dev->command[3])
st506_xt_log("ST506: Auto power-off in %d seconds (type=%i)\n",
dev->command[3] * 5, dev->type);
else
st506_xt_log("ST506: Auto power-off disabled (type=%i)\n", dev->type);
} else {
st506_error(dev, ERR_BAD_COMMAND);
}
st506_complete(dev);
break;
case CMD_RAM_DIAGNOSTIC:
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: RAM_DIAG\n");
#endif
st506_complete(dev);
break;
case CMD_CTRLR_DIAGNOSTIC:
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: CTRLR_DIAG\n");
#endif
st506_complete(dev);
break;
case CMD_SET_STEP_RATE_DTC:
if (dev->type == ST506_XT_TYPE_DTC_5150X) {
/* For DTC, we are done. */
st506_complete(dev);
} else if (dev->type == ST506_XT_TYPE_ST11M || dev->type == ST506_XT_TYPE_ST11R) {
/*
* For Seagate ST-11, this is WriteGeometry.
*
* This writes the contents of the buffer to track 0.
*
* By the time this command is sent, it will have
* formatted the first track, so it should be good,
* and our sector buffer contains the magic data
* (see above) we need to write to it.
*/
(void) get_chs(dev, drive);
st506_xt_log("ST506: WRITE BUFFER (%i, %i/%i/%i, %i)\n",
dev->drive_sel, dev->cylinder,
dev->head, dev->sector, dev->count);
if (!get_sector(dev, drive, &addr)) {
st506_error(dev, ERR_BAD_PARAMETER);
st506_complete(dev);
return;
}
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
/* Write data to image. */
hdd_image_write(drive->hdd_num, addr, 1,
(uint8_t *) dev->buff);
if (--dev->count == 0) {
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
st506_complete(dev);
break;
}
next_sector(dev, drive);
timer_advance_u64(&dev->timer, ST506_TIME);
break;
} else {
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
}
break;
case CMD_GET_DRIVE_PARAMS_DTC:
switch (dev->state) {
case STATE_START_COMMAND:
dev->buff_pos = 0;
dev->buff_cnt = 4;
memset(dev->buff, 0x00, dev->buff_cnt);
dev->buff[0] = drive->tracks & 0xff;
dev->buff[1] = ((drive->tracks >> 2) & 0xc0) | dev->spt;
dev->buff[2] = drive->hpc - 1;
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
dev->state = STATE_SEND_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_SET_GEOMETRY_DTC:
switch (dev->state) {
case STATE_START_COMMAND:
val = dev->command[1] & 0x01;
st506_xt_log("ST506: DTC_GET_GEOMETRY(%i) %i\n",
dev->drive_sel, val);
dev->buff_pos = 0;
dev->buff_cnt = 16;
dev->status = STAT_BSY | STAT_REQ;
dev->state = STATE_RECEIVE_DATA;
break;
case STATE_RECEIVED_DATA:
/* FIXME: ignore the results. */
st506_complete(dev);
break;
default:
break;
}
break;
case CMD_GET_GEOMETRY_DTC:
switch (dev->state) {
case STATE_START_COMMAND:
val = dev->command[1] & 0x01;
st506_xt_log("ST506: DTC_GET_GEOMETRY(%i) %i\n",
dev->drive_sel, val);
dev->buff_pos = 0;
dev->buff_cnt = 16;
memset(dev->buff, 0x00, dev->buff_cnt);
dev->buff[4] = drive->tracks & 0xff;
dev->buff[5] = (drive->tracks >> 8) & 0xff;
dev->buff[10] = drive->hpc;
dev->status = STAT_BSY | STAT_IO | STAT_REQ;
dev->state = STATE_SEND_DATA;
break;
case STATE_SENT_DATA:
st506_complete(dev);
break;
default:
break;
}
break;
default:
if (dev->command[0] == CMD_WRITE_GEOMETRY_ST11)
fatal("CMD_WRITE_GEOMETRY_ST11\n");
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: unknown command:\n");
#endif
st506_xt_log("ST506: %02x %02x %02x %02x %02x %02x\n",
dev->command[0], dev->command[1], dev->command[2],
dev->command[3], dev->command[4], dev->command[5]);
st506_error(dev, ERR_BAD_COMMAND);
st506_complete(dev);
}
}
/* Read from one of the registers. */
static uint8_t
st506_read(uint16_t port, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
uint8_t ret = 0xff;
switch (port & 3) {
case 0: /* read data */
dev->status &= ~STAT_IRQ;
switch (dev->state) {
case STATE_COMPLETION_BYTE:
ret = dev->compl ;
dev->status = 0x00;
dev->state = STATE_IDLE;
break;
case STATE_SEND_DATA:
ret = dev->buff[dev->buff_pos++];
if (dev->buff_pos == dev->buff_cnt) {
dev->buff_pos = 0;
dev->buff_cnt = 0;
dev->status = STAT_BSY;
dev->state = STATE_SENT_DATA;
timer_set_delay_u64(&dev->timer, ST506_TIME);
}
break;
default:
break;
}
break;
case 1: /* read status */
ret = dev->status;
if ((dev->irq_dma & DMA_ENA) && dma_get_drq(dev->dma))
ret |= STAT_DRQ;
break;
case 2: /* read option jumpers */
ret = dev->switches;
break;
default:
break;
}
st506_xt_log("ST506: read(%04x) = %02x\n", port, ret);
return ret;
}
/* Write to one of the registers. */
static void
st506_write(uint16_t port, uint8_t val, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
st506_xt_log("ST506: write(%04x, %02x)\n", port, val);
switch (port & 3) {
case 0: /* write data */
switch (dev->state) {
case STATE_RECEIVE_COMMAND: /* command data */
/* Write directly to the command buffer to avoid overwriting
the data buffer. */
dev->command[dev->buff_pos++] = val;
if (dev->buff_pos == dev->buff_cnt) {
/* We have a new command. */
dev->buff_pos = 0;
dev->buff_cnt = 0;
dev->status = STAT_BSY;
dev->state = STATE_START_COMMAND;
timer_set_delay_u64(&dev->timer, ST506_TIME);
}
break;
case STATE_RECEIVE_DATA: /* data */
dev->buff[dev->buff_pos++] = val;
if (dev->buff_pos == dev->buff_cnt) {
dev->buff_pos = 0;
dev->buff_cnt = 0;
dev->status = STAT_BSY;
dev->state = STATE_RECEIVED_DATA;
timer_set_delay_u64(&dev->timer, ST506_TIME);
}
break;
default:
break;
}
break;
case 1: /* controller reset */
dev->status = 0x00;
break;
case 2: /* generate controller-select-pulse */
dev->status = STAT_BSY | STAT_CD | STAT_REQ;
dev->buff_pos = 0;
dev->buff_cnt = sizeof(dev->command);
dev->state = STATE_RECEIVE_COMMAND;
break;
case 3: /* DMA/IRQ enable register */
dev->irq_dma = val;
if (!(dev->irq_dma & DMA_ENA))
dma_set_drq(dev->dma, 0);
if (!(dev->irq_dma & IRQ_ENA)) {
dev->status &= ~STAT_IRQ;
picintc(1 << dev->irq);
}
break;
default:
break;
}
}
/* Write to ROM (or scratchpad RAM.) */
static void
mem_write(uint32_t addr, uint8_t val, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
uint32_t ptr;
uint32_t mask = 0;
/* Ignore accesses to anything below the configured address,
needed because of the emulator's 4k mapping granularity. */
if (addr < dev->bios_addr)
return;
addr -= dev->bios_addr;
switch (dev->type) {
case ST506_XT_TYPE_ST11M: /* ST-11M */
case ST506_XT_TYPE_ST11R: /* ST-11R */
mask = 0x1fff; /* ST-11 decodes RAM on each 8K block */
break;
default:
break;
}
addr &= dev->bios_rom.mask;
ptr = (dev->bios_rom.mask & mask) - dev->bios_ram;
if (mask && ((addr & mask) > ptr) && ((addr & mask) <= (ptr + dev->bios_ram)))
dev->scratch[addr & (dev->bios_ram - 1)] = val;
}
static uint8_t
mem_read(uint32_t addr, void *priv)
{
const hdc_t *dev = (hdc_t *) priv;
uint32_t ptr;
uint32_t mask = 0;
uint8_t ret = 0xff;
/* Ignore accesses to anything below the configured address,
needed because of the emulator's 4k mapping granularity. */
if (addr < dev->bios_addr)
return 0xff;
addr -= dev->bios_addr;
switch (dev->type) {
case ST506_XT_TYPE_XEBEC: /* Xebec */
if (addr >= 0x001000) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: Xebec ROM access(0x%06lx)\n", addr);
#endif
return 0xff;
}
break;
case ST506_XT_TYPE_WDXT_GEN: /* WDXT-GEN */
if (addr >= 0x002000) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: WDXT-GEN ROM access(0x%06lx)\n", addr);
#endif
return 0xff;
}
break;
case ST506_XT_TYPE_DTC_5150X: /* DTC */
default:
if (addr >= 0x002000) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: DTC-5150X ROM access(0x%06lx)\n", addr);
#endif
return 0xff;
}
break;
case ST506_XT_TYPE_ST11M: /* ST-11M */
case ST506_XT_TYPE_ST11R: /* ST-11R */
mask = 0x1fff; /* ST-11 decodes RAM on each 8K block */
break;
#if 0
default:
break;
#endif
}
addr = addr & dev->bios_rom.mask;
ptr = (dev->bios_rom.mask & mask) - dev->bios_ram;
if (mask && ((addr & mask) > ptr) && ((addr & mask) <= (ptr + dev->bios_ram)))
ret = dev->scratch[addr & (dev->bios_ram - 1)];
else
ret = dev->bios_rom.rom[addr];
return ret;
}
/*
* Set up and load the ROM BIOS for this controller.
*
* This is straightforward for most, but some (like the ST-11x)
* map part of the area as scratchpad RAM, so we cannot use the
* standard 'rom_init' function here.
*/
static void
loadrom(hdc_t *dev, const char *fn)
{
uint32_t size;
FILE *fp;
if (fn == NULL) {
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: NULL BIOS ROM file pointer!\n");
#endif
return;
}
if ((fp = rom_fopen((char *) fn, "rb")) == NULL) {
st506_xt_log("ST506: BIOS ROM '%s' not found!\n", fn);
return;
}
/* Initialize the ROM entry. */
memset(&dev->bios_rom, 0x00, sizeof(rom_t));
/* Manually load and process the ROM image. */
(void) fseek(fp, 0L, SEEK_END);
size = ftell(fp);
(void) fseek(fp, 0L, SEEK_SET);
/* Load the ROM data. */
dev->bios_rom.rom = (uint8_t *) malloc(size);
memset(dev->bios_rom.rom, 0xff, size);
if (fread(dev->bios_rom.rom, 1, size, fp) != size)
fatal("ST-506 XT loadrom(): Error reading data\n");
(void) fclose(fp);
/* Set up an address mask for this memory. */
dev->bios_size = size;
dev->bios_rom.mask = (size - 1);
/* Map this system into the memory map. */
mem_mapping_add(&dev->bios_rom.mapping, dev->bios_addr, size,
mem_read, NULL, NULL, mem_write, NULL, NULL,
dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, dev);
}
static void
loadhd(hdc_t *dev, int c, int d, UNUSED(const char *fn))
{
drive_t *drive = &dev->drives[c];
if (!hdd_image_load(d)) {
drive->present = 0;
return;
}
/* Make sure we can do this. */
/* Allow 31 sectors per track on RLL controllers, for the
ST225R, which is 667/2/31. */
if ((hdd[d].spt != dev->spt) && (hdd[d].spt != 31) && (dev->spt != 26)) {
/*
* Uh-oh, MFM/RLL mismatch.
*
* Although this would be no issue in the code itself,
* most of the BIOSes were hardwired to whatever their
* native SPT setting was, so, do not allow this here.
*/
st506_xt_log("ST506: drive%i: MFM/RLL mismatch (%i/%i)\n",
c, hdd[d].spt, dev->spt);
hdd_image_close(d);
drive->present = 0;
return;
}
drive->spt = (uint8_t) hdd[d].spt;
drive->hpc = (uint8_t) hdd[d].hpc;
drive->tracks = (uint16_t) hdd[d].tracks;
drive->hdd_num = d;
drive->present = 1;
}
/* Set the "drive type" switches for the IBM Xebec controller. */
static void
set_switches(hdc_t *dev, hd_type_t *hdt, int num)
{
const drive_t *drive;
int c;
int e;
dev->switches = 0x00;
for (uint8_t d = 0; d < MFM_NUM; d++) {
drive = &dev->drives[d];
if (!drive->present) {
if (dev->type == ST506_XT_TYPE_WD1002A_WX1_NOBIOS)
dev->switches |= (0x33 << (d ? 0 : 2));
continue;
}
for (c = 0; c < num; c++) {
/* Does the Xebec also support more than 4 types? */
if ((drive->spt == hdt[c].spt) && (drive->hpc == hdt[c].hpc) && (drive->tracks == hdt[c].tracks)) {
/* Olivetti M24/M240: Move the upper 2 bites up by 2 bits, as the
layout is as follows: D0_3 D0_2 D1_3 D1_2 D0_1 D0_0 D1_1 D1_0. */
if (dev->type == ST506_XT_TYPE_WD1002A_WX1_NOBIOS)
e = (c & 0x03) | ((c >> 2) << 4);
else
e = c;
dev->switches |= (e << (d ? 0 : 2));
break;
}
}
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: ");
if (c == num)
st506_xt_log("*WARNING* drive%i unsupported", d);
else
st506_xt_log("drive%i is type %i", d, c);
st506_xt_log(" (%i/%i/%i)\n", drive->tracks, drive->hpc, drive->spt);
#endif
}
}
static void *
st506_init(const device_t *info)
{
const char *fn = NULL;
hdc_t *dev;
int i;
int c;
dev = (hdc_t *) malloc(sizeof(hdc_t));
memset(dev, 0x00, sizeof(hdc_t));
dev->type = info->local & 255;
/* Set defaults for the controller. */
dev->spt = MFM_SECTORS;
dev->base = 0x0320;
dev->irq = 5;
dev->dma = 3;
dev->bios_addr = 0xc8000;
dev->nr_err = ERR_NOT_READY;
switch (dev->type) {
case ST506_XT_TYPE_XEBEC: /* Xebec (MFM) */
fn = XEBEC_BIOS_FILE;
break;
case ST506_XT_TYPE_WDXT_GEN: /* WDXT-GEN (MFM) */
fn = WDXT_GEN_BIOS_FILE;
break;
case ST506_XT_TYPE_DTC_5150X: /* DTC5150 (MFM) */
fn = DTC_BIOS_FILE;
dev->switches = 0xff;
break;
case ST506_XT_TYPE_ST11R: /* Seagate ST-11R (RLL) */
dev->spt = RLL_SECTORS;
fallthrough;
case ST506_XT_TYPE_ST11M: /* Seagate ST-11M (MFM) */
dev->nr_err = ERR_NOT_AVAILABLE;
dev->switches = 0x01; /* fixed */
dev->misc = device_get_config_int("revision");
switch (dev->misc) {
case 5: /* v1.7 */
fn = ST11_BIOS_FILE_OLD;
break;
case 19: /* v2.0 */
fn = ST11_BIOS_FILE_NEW;
break;
default:
break;
}
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
dev->bios_addr = device_get_config_hex20("bios_addr");
dev->bios_ram = 64; /* scratch RAM size */
/*
* Industrial Madness Alert.
*
* With the ST-11 controller, Seagate decided to act
* like they owned the industry, and reserved the
* first cylinder of a drive for the controller. So,
* when the host accessed cylinder 0, that would be
* the actual cylinder 1 on the drive, and so on.
*/
dev->cyl_off = 1;
break;
case ST506_XT_TYPE_WD1002A_WX1: /* Western Digital WD1002A-WX1 (MFM) */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = WD1002A_WX1_BIOS_FILE;
/* The switches are read in reverse: 0 = closed, 1 = open.
Both open means MFM, 17 sectors per track. */
dev->switches = 0x30; /* autobios */
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
if (dev->irq == 2)
dev->switches |= 0x40;
dev->bios_addr = device_get_config_hex20("bios_addr");
break;
case ST506_XT_TYPE_WD1002A_WX1_NOBIOS: /* Western Digital WD1002A-WX1 (MFM, No BIOS) */
/* Supported base addresses: 320h, 324h, 328h, 32Ch. */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = NULL;
break;
case ST506_XT_TYPE_WD1004A_WX1: /* Western Digital WD1004A-WX1 (MFM) */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = WD1004A_WX1_BIOS_FILE;
/* The switches are read in reverse: 0 = closed, 1 = open.
Both open means MFM, 17 sectors per track. */
dev->switches = 0x30; /* autobios */
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
if (dev->irq == 2)
dev->switches |= 0x40;
dev->bios_addr = device_get_config_hex20("bios_addr");
break;
case ST506_XT_TYPE_WD1002A_27X: /* Western Digital WD1002A-27X (RLL) */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = WD1002A_27X_BIOS_FILE;
/* The switches are read in reverse: 0 = closed, 1 = open.
Both closed means translate 26 sectors per track to 17,
SW6 closed, SW5 open means 26 sectors per track. */
dev->switches = device_get_config_int("translate") ? 0x00 : 0x10; /* autobios */
dev->spt = RLL_SECTORS;
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
if (dev->irq == 2)
dev->switches |= 0x40;
dev->bios_addr = device_get_config_hex20("bios_addr");
break;
case ST506_XT_TYPE_WD1004_27X: /* Western Digital WD1004-27X (RLL) */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = WD1004_27X_BIOS_FILE;
/* The switches are read in reverse: 0 = closed, 1 = open.
Both closed means translate 26 sectors per track to 17,
SW6 closed, SW5 open means 26 sectors per track. */
dev->switches = device_get_config_int("translate") ? 0x00 : 0x10; /* autobios */
dev->spt = RLL_SECTORS;
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
if (dev->irq == 2)
dev->switches |= 0x40;
dev->bios_addr = device_get_config_hex20("bios_addr");
break;
case ST506_XT_TYPE_WD1004A_27X: /* Western Digital WD1004A-27X (RLL) */
dev->nr_err = ERR_NOT_AVAILABLE;
fn = WD1004A_27X_BIOS_FILE;
/* The switches are read in reverse: 0 = closed, 1 = open.
Both closed means translate 26 sectors per track to 17,
SW6 closed, SW5 open means 26 sectors per track. */
dev->switches = device_get_config_int("translate") ? 0x00 : 0x10; /* autobios */
dev->spt = RLL_SECTORS;
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
if (dev->irq == 2)
dev->switches |= 0x40;
dev->bios_addr = device_get_config_hex20("bios_addr");
break;
case ST506_XT_TYPE_VICTOR_V86P: /* Victor V86P (RLL) */
fn = VICTOR_V86P_BIOS_FILE;
break;
case ST506_XT_TYPE_TOSHIBA_T1200: /* Toshiba T1200 */
fn = NULL;
dev->base = 0x01f0;
dev->switches = 0x0c;
break;
default:
break;
}
/* Load the ROM BIOS. */
loadrom(dev, fn);
/* Set up the I/O region. */
io_sethandler(dev->base, 4,
st506_read, NULL, NULL, st506_write, NULL, NULL, dev);
/* Add the timer. */
timer_add(&dev->timer, st506_callback, dev, 0);
st506_xt_log("ST506: %s (I/O=%03X, IRQ=%i, DMA=%i, BIOS @0x%06lX, size %lu)\n",
info->name, dev->base, dev->irq, dev->dma, dev->bios_addr, dev->bios_size);
/* Load any drives configured for us. */
#ifdef ENABLE_ST506_XT_LOG
st506_xt_log("ST506: looking for disks...\n");
#endif
for (c = 0, i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus == HDD_BUS_MFM) && (hdd[i].mfm_channel < MFM_NUM)) {
st506_xt_log("ST506: disk '%s' on channel %i\n",
hdd[i].fn, hdd[i].mfm_channel);
loadhd(dev, hdd[i].mfm_channel, i, hdd[i].fn);
if (++c > MFM_NUM)
break;
}
}
st506_xt_log("ST506: %i disks loaded.\n", c);
/* For the Xebec, set the switches now. */
if (dev->type == ST506_XT_TYPE_XEBEC)
set_switches(dev, (hd_type_t *) hd_types, 4);
else if (dev->type == ST506_XT_TYPE_WD1002A_WX1_NOBIOS)
set_switches(dev, (hd_type_t *) hd_types_olivetti, 16);
/* Initial "active" drive parameters. */
for (c = 0; c < MFM_NUM; c++) {
dev->drives[c].cfg_cyl = dev->drives[c].tracks;
dev->drives[c].cfg_hpc = dev->drives[c].hpc;
dev->drives[c].cfg_spt = dev->drives[c].spt;
}
return dev;
}
static void
st506_close(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
const drive_t *drive;
for (uint8_t d = 0; d < MFM_NUM; d++) {
drive = &dev->drives[d];
hdd_image_close(drive->hdd_num);
}
if (dev->bios_rom.rom != NULL) {
free(dev->bios_rom.rom);
dev->bios_rom.rom = NULL;
}
free(dev);
}
static int
xebec_available(void)
{
return (rom_present(XEBEC_BIOS_FILE));
}
static int
wdxt_available(void)
{
return (rom_present(WDXT_GEN_BIOS_FILE));
}
static int
dtc5150x_available(void)
{
return (rom_present(DTC_BIOS_FILE));
}
static int
st11_m_available(void)
{
return (rom_present(ST11_BIOS_FILE_OLD) && rom_present(ST11_BIOS_FILE_NEW));
}
static int
st11_r_available(void)
{
return (rom_present(ST11_BIOS_FILE_OLD) && rom_present(ST11_BIOS_FILE_NEW));
}
static int
wd1002a_wx1_available(void)
{
return (rom_present(WD1002A_WX1_BIOS_FILE));
}
static int
wd1002a_27x_available(void)
{
return (rom_present(WD1002A_27X_BIOS_FILE));
}
static int
wd1004a_wx1_available(void)
{
return (rom_present(WD1004A_WX1_BIOS_FILE));
}
static int
wd1004_27x_available(void)
{
return (rom_present(WD1004_27X_BIOS_FILE));
}
static int
wd1004a_27x_available(void)
{
return (rom_present(WD1004A_27X_BIOS_FILE));
}
static int
victor_v86p_available(void)
{
return (rom_present(VICTOR_V86P_BIOS_FILE));
}
// clang-format off
static const device_config_t dtc_config[] = {
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "CA00H", .value = 0xca000 },
{ .description = "D800H", .value = 0xd8000 },
{ .description = "F400H", .value = 0xf4000 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t st11_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "328H", .value = 0x0328 },
{ .description = "32CH", .value = 0x032c },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "D000H", .value = 0xd0000 },
{ .description = "D800H", .value = 0xd8000 },
{ .description = "E000H", .value = 0xe0000 },
{ .description = "" }
}
},
{
.name = "revision",
.description = "Board Revision",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 19,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Rev. 05 (v1.7)", .value = 5 },
{ .description = "Rev. 19 (v2.0)", .value = 19 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd_config[] = {
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "" }
}
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd_nobios_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd_rll_config[] = {
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "" }
}
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{
.name = "translate",
.description = "Translate 26 -> 17",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Off", .value = 0 },
{ .description = "On", .value = 1 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd1004a_config[] = {
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "" }
}
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd1004_rll_config[] = {
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C800H", .value = 0xc8000 },
{ .description = "CA00H", .value = 0xca000 },
{ .description = "CC00H", .value = 0xcc000 },
{ .description = "CE00H", .value = 0xce000 },
{ .description = "" }
}
},
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "328H", .value = 0x0328 },
{ .description = "32CH", .value = 0x032c },
{ .description = "" }
}
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "" }
}
},
{
.name = "translate",
.description = "Translate 26 -> 17",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Off", .value = 0 },
{ .description = "On", .value = 1 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t st506_xt_xebec_device = {
.name = "IBM PC Fixed Disk Adapter (MFM)",
.internal_name = "st506_xt",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_XEBEC,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = xebec_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t st506_xt_wdxt_gen_device = {
.name = "Western Digital WDXT-GEN (MFM)",
.internal_name = "st506_xt_gen",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WDXT_GEN,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wdxt_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t st506_xt_dtc5150x_device = {
.name = "DTC 5150X MFM Fixed Disk Adapter",
.internal_name = "st506_xt_dtc5150x",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_DTC_5150X,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = dtc5150x_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = dtc_config
};
const device_t st506_xt_st11_m_device = {
.name = "ST-11M MFM Fixed Disk Adapter",
.internal_name = "st506_xt_st11_m",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_ST11M,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = st11_m_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = st11_config
};
const device_t st506_xt_st11_r_device = {
.name = "ST-11R RLL Fixed Disk Adapter",
.internal_name = "st506_xt_st11_r",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_ST11R,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = st11_r_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = st11_config
};
const device_t st506_xt_wd1002a_wx1_device = {
.name = "WD1002A-WX1 MFM Fixed Disk Adapter",
.internal_name = "st506_xt_wd1002a_wx1",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1002A_WX1,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1002a_wx1_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd_config
};
const device_t st506_xt_wd1002a_wx1_nobios_device = {
.name = "WD1002A-WX1 MFM Fixed Disk Adapter (No BIOS)",
.internal_name = "st506_xt_wd1002a_wx1",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1002A_WX1_NOBIOS,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1002a_wx1_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd_nobios_config
};
const device_t st506_xt_wd1002a_27x_device = {
.name = "WD1002A-27X RLL Fixed Disk Adapter",
.internal_name = "st506_xt_wd1002a_27x",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1002A_27X,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1002a_27x_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd_rll_config
};
const device_t st506_xt_wd1004a_wx1_device = {
.name = "WD1004A-WX1 MFM Fixed Disk Adapter",
.internal_name = "st506_xt_wd1004a_wx1",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1004A_WX1,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1004a_wx1_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd1004a_config
};
const device_t st506_xt_wd1004_27x_device = {
.name = "WD1004-27X RLL Fixed Disk Adapter",
.internal_name = "st506_xt_wd1004_27x",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1004_27X,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1004_27x_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd1004_rll_config
};
const device_t st506_xt_wd1004a_27x_device = {
.name = "WD1004a-27X RLL Fixed Disk Adapter",
.internal_name = "st506_xt_wd1004a_27x",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_WD1004A_27X,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = wd1004a_27x_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd_rll_config
};
const device_t st506_xt_victor_v86p_device = {
.name = "Victor V86P RLL Fixed Disk Adapter",
.internal_name = "st506_xt_victor_v86p",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_VICTOR_V86P,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = victor_v86p_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t st506_xt_toshiba_t1200_device = {
.name = "Toshiba T1200 RLL Fixed Disk Adapter",
.internal_name = "st506_xt_toshiba_t1200",
.flags = DEVICE_ISA,
.local = (HDD_BUS_MFM << 8) | ST506_XT_TYPE_TOSHIBA_T1200,
.init = st506_init,
.close = st506_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_st506_xt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 21,028 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Vision Systems LBA Enhancer emulation.
*
*
*
* Authors: Cacodemon345
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/plat_unused.h>
typedef struct lba_enhancer_t
{
rom_t rom;
} lba_enhancer_t;
#define BIOS_LBA_ENHANCER "roms/hdd/misc/lbaenhancer.bin"
void
lba_enhancer_close(void* priv)
{
free(priv);
return;
}
void *
lba_enhancer_init(const device_t *info)
{
lba_enhancer_t *dev = (lba_enhancer_t *) calloc(1, sizeof(lba_enhancer_t));
rom_init(&dev->rom, BIOS_LBA_ENHANCER,
device_get_config_hex20("bios_addr"), 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
return dev;
}
static int
lba_enhancer_available(void)
{
return rom_present(BIOS_LBA_ENHANCER);
}
// clang-format off
static const device_config_t lba_enhancer_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C800H", .value = 0xc8000 },
{ .description = "CC00H", .value = 0xcc000 },
{ .description = "D000H", .value = 0xd0000 },
{ .description = "D400H", .value = 0xd4000 },
{ .description = "D800H", .value = 0xd8000 },
{ .description = "DC00H", .value = 0xdc000 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t lba_enhancer_device = {
.name = "Vision Systems LBA Enhancer",
.internal_name = "lba_enhancer",
.flags = DEVICE_AT,
.local = 0,
.init = lba_enhancer_init,
.close = lba_enhancer_close,
.reset = NULL,
{ .available = lba_enhancer_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = lba_enhancer_config
};
``` | /content/code_sandbox/src/disk/lba_enhancer.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 718 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the CMD PCI-0646 controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/cdrom.h>
#include <86box/scsi_device.h>
#include <86box/scsi_cdrom.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/mo.h>
typedef struct cmd646_t {
uint8_t vlb_idx;
uint8_t single_channel;
uint8_t in_cfg;
uint8_t pci_slot;
uint8_t regs[256];
uint32_t local;
int irq_pin;
int irq_mode[2];
sff8038i_t *bm[2];
} cmd646_t;
#ifdef ENABLE_CMD646_LOG
int cmd646_do_log = ENABLE_CMD646_LOG;
static void
cmd646_log(const char *fmt, ...)
{
va_list ap;
if (cmd646_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cmd646_log(fmt, ...)
#endif
static void
cmd646_set_irq_0(uint8_t status, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
sff_bus_master_set_irq(status, dev->bm[0]);
}
static void
cmd646_set_irq_1(uint8_t status, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
if (!(dev->regs[0x57] & 0x10) || (status & 0x04))
dev->regs[0x57] = (dev->regs[0x57] & ~0x10) | (status << 2);
sff_bus_master_set_irq(status, dev->bm[1]);
}
static int
cmd646_bus_master_dma_0(uint8_t *data, int transfer_length, int out, void *priv)
{
const cmd646_t *dev = (cmd646_t *) priv;
return sff_bus_master_dma(data, transfer_length, out, dev->bm[0]);
}
static int
cmd646_bus_master_dma_1(uint8_t *data, int transfer_length, int out, void *priv)
{
const cmd646_t *dev = (cmd646_t *) priv;
return sff_bus_master_dma(data, transfer_length, out, dev->bm[1]);
}
static void
cmd646_ide_handlers(cmd646_t *dev)
{
uint16_t main;
uint16_t side;
int irq_mode[2] = { IRQ_MODE_LEGACY, IRQ_MODE_LEGACY };
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
ide_pri_disable();
if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
if (dev->regs[0x09] & 0x01)
irq_mode[0] = IRQ_MODE_PCI_IRQ_PIN;
sff_set_irq_mode(dev->bm[0], irq_mode[0]);
if (dev->regs[0x04] & 0x01)
ide_pri_enable();
if (dev->single_channel)
return;
ide_sec_disable();
if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
if (dev->regs[0x09] & 0x04)
irq_mode[1] = 1;
sff_set_irq_mode(dev->bm[1], irq_mode[1]);
if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
ide_sec_enable();
}
static void
cmd646_ide_bm_handlers(cmd646_t *dev)
{
uint16_t base = (dev->regs[0x20] & 0xf0) | (dev->regs[0x21] << 8);
sff_bus_master_handler(dev->bm[0], (dev->regs[0x04] & 1), base);
sff_bus_master_handler(dev->bm[1], (dev->regs[0x04] & 1), base + 8);
}
static void
cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
cmd646_log("[%04X:%08X] (%08X) cmd646_pci_write(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
dev->regs[addr] = (val & 0x45);
cmd646_ide_handlers(dev);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0xb1);
break;
case 0x09:
if ((dev->regs[addr] & 0x0a) == 0x0a) {
dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
dev->irq_mode[0] = !!(val & 0x01);
dev->irq_mode[1] = !!(val & 0x04);
cmd646_ide_handlers(dev);
}
break;
case 0x10:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x10] = (val & 0xf8) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x11:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x11] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x14:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x14] = (val & 0xfc) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x15:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x15] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x18:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x18] = (val & 0xf8) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x19:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x19] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x1c:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1c] = (val & 0xfc) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x1d:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1d] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x20:
dev->regs[0x20] = (val & 0xf0) | 1;
cmd646_ide_bm_handlers(dev);
break;
case 0x21:
dev->regs[0x21] = val;
cmd646_ide_bm_handlers(dev);
break;
case 0x51:
dev->regs[addr] = val & 0xc8;
cmd646_ide_handlers(dev);
break;
case 0x52:
case 0x54:
case 0x56:
case 0x58:
case 0x59:
case 0x5b:
dev->regs[addr] = val;
break;
case 0x53:
case 0x55:
dev->regs[addr] = val & 0xc0;
break;
case 0x57:
dev->regs[addr] = (dev->regs[addr] & 0x10) | (val & 0xcc);
break;
case 0x70 ... 0x77:
sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
break;
case 0x78 ... 0x7f:
sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
break;
default:
break;
}
}
static uint8_t
cmd646_pci_read(int func, int addr, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) {
ret = dev->regs[addr];
if (addr == 0x50)
dev->regs[0x50] &= ~0x04;
else if (addr == 0x57)
dev->regs[0x57] &= ~0x10;
else if ((addr >= 0x70) && (addr <= 0x77))
ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
else if ((addr >= 0x78) && (addr <= 0x7f))
ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
}
cmd646_log("[%04X:%08X] (%08X) cmd646_pci_read(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, ret);
return ret;
}
static void
cmd646_reset(void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
int i = 0;
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) && mo_drives[i].priv)
mo_reset((scsi_common_t *) mo_drives[i].priv);
}
cmd646_set_irq_0(0x00, priv);
cmd646_set_irq_1(0x00, priv);
memset(dev->regs, 0x00, sizeof(dev->regs));
dev->regs[0x00] = 0x95; /* CMD */
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x46; /* PCI-0646 */
dev->regs[0x03] = 0x06;
dev->regs[0x04] = 0x00;
dev->regs[0x06] = 0x80;
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x09] = dev->local; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
dev->regs[0x0b] = 0x01; /* Mass storage controller */
if ((dev->local & 0xffff) == 0x8a) {
dev->regs[0x50] = 0x40; /* Enable Base address register R/W;
If 0, they return 0 and are read-only 8 */
/* Base addresses (1F0, 3F4, 170, 374) */
dev->regs[0x10] = 0xf1;
dev->regs[0x11] = 0x01;
dev->regs[0x14] = 0xf5;
dev->regs[0x15] = 0x03;
dev->regs[0x18] = 0x71;
dev->regs[0x19] = 0x01;
dev->regs[0x1c] = 0x75;
dev->regs[0x1d] = 0x03;
}
dev->regs[0x20] = 0x01;
dev->regs[0x3c] = 0x0e; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
dev->regs[0x3e] = 0x02; /* Min_Gnt */
dev->regs[0x3f] = 0x04; /* Max_Iat */
if (!dev->single_channel)
dev->regs[0x51] = 0x08;
dev->regs[0x57] = 0x0c;
dev->regs[0x59] = 0x40;
dev->irq_mode[0] = dev->irq_mode[1] = 0;
dev->irq_pin = PCI_INTA;
cmd646_ide_handlers(dev);
cmd646_ide_bm_handlers(dev);
}
static void
cmd646_close(void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
free(dev);
}
static void *
cmd646_init(const device_t *info)
{
cmd646_t *dev = (cmd646_t *) malloc(sizeof(cmd646_t));
memset(dev, 0x00, sizeof(cmd646_t));
dev->local = info->local;
device_add(&ide_pci_2ch_device);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
dev->single_channel = !!(info->local & 0x20000);
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
if (!dev->single_channel)
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
ide_set_bus_master(0, cmd646_bus_master_dma_0, cmd646_set_irq_0, dev);
if (!dev->single_channel)
ide_set_bus_master(1, cmd646_bus_master_dma_1, cmd646_set_irq_1, dev);
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
if (!dev->single_channel)
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
cmd646_reset(dev);
return dev;
}
const device_t ide_cmd646_device = {
.name = "CMD PCI-0646",
.internal_name = "ide_cmd646",
.flags = DEVICE_PCI,
.local = 0x8a,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd646_legacy_only_device = {
.name = "CMD PCI-0646 (Legacy Mode Only)",
.internal_name = "ide_cmd646_legacy_only",
.flags = DEVICE_PCI,
.local = 0x80,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd646_single_channel_device = {
.name = "CMD PCI-0646",
.internal_name = "ide_cmd646_single_channel",
.flags = DEVICE_PCI,
.local = 0x2008a,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_cmd646.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,291 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of a generic IDE-XTA disk controller.
*
* XTA is the acronym for 'XT-Attached', which was basically
* the XT-counterpart to what we know now as IDE (which is
* also named ATA - AT Attachment.) The basic ideas was to
* put the actual drive controller electronics onto the drive
* itself, and have the host machine just talk to that using
* a simpe, standardized I/O path- hence the name IDE, for
* Integrated Drive Electronics.
*
* In the ATA version of IDE, the programming interface of
* the IBM PC/AT (which used the Western Digitial 1002/1003
* controllers) was kept, and, so, ATA-IDE assumes a 16bit
* data path: it reads and writes 16bit words of data. The
* disk drives for this bus commonly have an 'A' suffix to
* identify them as 'ATBUS'.
*
* In XTA-IDE, which is slightly older, the programming
* interface of the IBM PC/XT (which used the MFM controller
* from Xebec) was kept, and, so, it uses an 8bit data path.
* Disk drives for this bus commonly have the 'X' suffix to
* mark them as being for this XTBUS variant.
*
* So, XTA and ATA try to do the same thing, but they use
* different ways to achive their goal.
*
* Also, XTA is **not** the same as XTIDE. XTIDE is a modern
* variant of ATA-IDE, but retro-fitted for use on 8bit XT
* systems: an extra register is used to deal with the extra
* data byte per transfer. XTIDE uses regular IDE drives,
* and uses the regular ATA/IDE programming interface, just
* with the extra register.
*
* NOTE: This driver implements both the 'standard' XTA interface,
* sold by Western Digital as the WDXT-140 (no BIOS) and the
* WDXT-150 (with BIOS), as well as some variants customized
* for specific machines.
*
* NOTE: The XTA interface is 0-based for sector numbers !!
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Based on my earlier HD20 driver for the EuroPC.
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#define HDC_TIME (250 * TIMER_USEC)
#define WD_REV_1_BIOS_FILE "roms/hdd/xta/idexywd2.bin"
#define WD_REV_2_BIOS_FILE "roms/hdd/xta/infowdbios.rom"
enum {
STATE_IDLE = 0,
STATE_RECV,
STATE_RDATA,
STATE_RDONE,
STATE_SEND,
STATE_SDATA,
STATE_SDONE,
STATE_COMPL
};
/* Command values. */
#define CMD_TEST_READY 0x00
#define CMD_RECALIBRATE 0x01
/* unused 0x02 */
#define CMD_READ_SENSE 0x03
#define CMD_FORMAT_DRIVE 0x04
#define CMD_READ_VERIFY 0x05
#define CMD_FORMAT_TRACK 0x06
#define CMD_FORMAT_BAD_TRACK 0x07
#define CMD_READ_SECTORS 0x08
/* unused 0x09 */
#define CMD_WRITE_SECTORS 0x0a
#define CMD_SEEK 0x0b
#define CMD_SET_DRIVE_PARAMS 0x0c
#define CMD_READ_ECC_BURST 0x0d
#define CMD_READ_SECTOR_BUFFER 0x0e
#define CMD_WRITE_SECTOR_BUFFER 0x0f
#define CMD_RAM_DIAGS 0xe0
/* unused 0xe1 */
/* unused 0xe2 */
#define CMD_DRIVE_DIAGS 0xe3
#define CMD_CTRL_DIAGS 0xe4
#define CMD_READ_LONG 0xe5
#define CMD_WRITE_LONG 0xe6
/* Status register (reg 1) values. */
#define STAT_REQ 0x01 /* controller needs data transfer */
#define STAT_IO 0x02 /* direction of transfer (TO bus) */
#define STAT_CD 0x04 /* transfer of Command or Data */
#define STAT_BSY 0x08 /* controller is busy */
#define STAT_DRQ 0x10 /* DMA requested */
#define STAT_IRQ 0x20 /* interrupt requested */
#define STAT_DCB 0x80 /* not seen by driver */
/* Sense Error codes. */
#define ERR_NOERROR 0x00 /* no error detected */
#define ERR_NOINDEX 0x01 /* drive did not detect IDX pulse */
#define ERR_NOSEEK 0x02 /* drive did not complete SEEK */
#define ERR_WRFAULT 0x03 /* write fault during last cmd */
#define ERR_NOTRDY 0x04 /* drive did not go READY after cmd */
#define ERR_NOTRK000 0x06 /* drive did not see TRK0 signal */
#define ERR_LONGSEEK 0x08 /* long seek in progress */
#define ERR_IDREAD 0x10 /* ECC error during ID field */
#define ERR_DATA 0x11 /* uncorrectable ECC err in data */
#define ERR_NOMARK 0x12 /* no address mark detected */
#define ERR_NOSECT 0x14 /* sector not found */
#define ERR_SEEK 0x15 /* seek error */
#define ERR_ECCDATA 0x18 /* ECC corrected data */
#define ERR_BADTRK 0x19 /* bad track detected */
#define ERR_ILLCMD 0x20 /* invalid command received */
#define ERR_ILLADDR 0x21 /* invalid disk address received */
#define ERR_BADRAM 0x30 /* bad RAM in sector data buffer */
#define ERR_BADROM 0x31 /* bad checksum in ROM test */
#define ERR_BADECC 0x32 /* ECC polynomial generator bad */
/* Completion Byte fields. */
#define COMP_DRIVE 0x20
#define COMP_ERR 0x02
#define IRQ_ENA 0x02
#define DMA_ENA 0x01
/* The device control block (6 bytes) */
#pragma pack(push, 1)
typedef struct dcb_t {
uint8_t cmd; /* [7:5] class, [4:0] opcode */
uint8_t head : 5; /* [4:0] head number */
uint8_t drvsel : 1; /* [5] drive select */
uint8_t mbz : 2; /* [7:6] 00 */
uint8_t sector : 6; /* [5:0] sector number 0-63 */
uint8_t cyl_high : 2; /* [7:6] cylinder [9:8] bits */
uint8_t cyl_low; /* [7:0] cylinder [7:0] bits */
uint8_t count; /* [7:0] blk count / interleave */
uint8_t ctrl; /* [7:0] control field */
} dcb_t;
#pragma pack(pop)
/* The (configured) Drive Parameters. */
#pragma pack(push, 1)
typedef struct dprm_t {
uint8_t cyl_high; /* (MSB) number of cylinders */
uint8_t cyl_low; /* (LSB) number of cylinders */
uint8_t heads; /* number of heads per cylinder */
uint8_t rwc_high; /* (MSB) reduced write current cylinder */
uint8_t rwc_low; /* (LSB) reduced write current cylinder */
uint8_t wp_high; /* (MSB) write precompensation cylinder */
uint8_t wp_low; /* (LSB) write precompensation cylinder */
uint8_t maxecc; /* max ECC data burst length */
} dprm_t;
#pragma pack(pop)
/* Define an attached drive. */
typedef struct drive_t {
int8_t id; /* drive ID on bus */
int8_t present; /* drive is present */
int8_t hdd_num; /* index to global disk table */
int8_t type; /* drive type ID */
uint16_t cur_cyl; /* last known position of heads */
uint8_t spt; /* active drive parameters */
uint8_t hpc;
uint16_t tracks;
uint8_t cfg_spt; /* configured drive parameters */
uint8_t cfg_hpc;
uint16_t cfg_tracks;
} drive_t;
typedef struct hdc_t {
const char *name; /* controller name */
uint16_t base; /* controller base I/O address */
int8_t irq; /* controller IRQ channel */
int8_t dma; /* controller DMA channel */
int8_t type; /* controller type ID */
uint32_t rom_addr; /* address where ROM is */
rom_t bios_rom; /* descriptor for the BIOS */
/* Controller state. */
int8_t state; /* controller state */
uint8_t sense; /* current SENSE ERROR value */
uint8_t status; /* current operational status */
uint8_t intr;
pc_timer_t timer;
/* Data transfer. */
int16_t buf_idx; /* buffer index and pointer */
int16_t buf_len;
uint8_t *buf_ptr;
/* Current operation parameters. */
dcb_t dcb; /* device control block */
uint16_t track; /* requested track# */
uint8_t head; /* requested head# */
uint8_t sector; /* requested sector# */
uint8_t comp; /* operation completion byte */
int count; /* requested sector count */
drive_t drives[XTA_NUM]; /* the attached drive(s) */
uint8_t data[512]; /* data buffer */
uint8_t sector_buf[512]; /* sector buffer */
} hdc_t;
#ifdef ENABLE_XTA_LOG
int xta_do_log = ENABLE_XTA_LOG;
static void
xta_log(const char *fmt, ...)
{
va_list ap;
if (xta_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define xta_log(fmt, ...)
#endif
static void
set_intr(hdc_t *dev)
{
dev->status = STAT_REQ | STAT_CD | STAT_IO | STAT_BSY;
dev->state = STATE_COMPL;
if (dev->intr & IRQ_ENA) {
dev->status |= STAT_IRQ;
picint(1 << dev->irq);
}
}
/* Get the logical (block) address of a CHS triplet. */
static int
get_sector(hdc_t *dev, drive_t *drive, off64_t *addr)
{
if (drive->cur_cyl != dev->track) {
xta_log("%s: get_sector: wrong cylinder %d/%d\n",
dev->name, drive->cur_cyl, dev->track);
dev->sense = ERR_ILLADDR;
return 1;
}
if (dev->head >= drive->hpc) {
xta_log("%s: get_sector: past end of heads\n", dev->name);
dev->sense = ERR_ILLADDR;
return 1;
}
if (dev->sector >= drive->spt) {
xta_log("%s: get_sector: past end of sectors\n", dev->name);
dev->sense = ERR_ILLADDR;
return 1;
}
/* Calculate logical address (block number) of desired sector. */
*addr = ((((off64_t) dev->track * drive->hpc) + dev->head) * drive->spt) + dev->sector;
return 0;
}
static void
next_sector(hdc_t *dev, drive_t *drive)
{
if (++dev->sector >= drive->spt) {
dev->sector = 0;
if (++dev->head >= drive->hpc) {
dev->head = 0;
dev->track++;
if (++drive->cur_cyl >= drive->tracks)
drive->cur_cyl = (drive->tracks - 1);
}
}
}
/* Perform the seek operation. */
static void
do_seek(hdc_t *dev, drive_t *drive, int cyl)
{
dev->track = cyl;
if (dev->track >= drive->tracks)
drive->cur_cyl = (drive->tracks - 1);
else
drive->cur_cyl = dev->track;
}
/* Format a track or an entire drive. */
static void
do_format(hdc_t *dev, drive_t *drive, dcb_t *dcb)
{
int start_cyl;
int end_cyl;
int start_hd;
int end_hd;
off64_t addr;
/* Get the parameters from the DCB. */
if (dcb->cmd == CMD_FORMAT_DRIVE) {
start_cyl = 0;
start_hd = 0;
end_cyl = drive->tracks;
end_hd = drive->hpc;
} else {
start_cyl = (dcb->cyl_low | (dcb->cyl_high << 8));
start_hd = dcb->head;
end_cyl = start_cyl + 1;
end_hd = start_hd + 1;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder. */
do_seek(dev, drive, start_cyl);
dev->head = dcb->head;
dev->sector = 0;
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
do_fmt:
/*
* For now, we don't use the interleave factor (in
* dcb->count), although we should one day use an
* image format that can handle it..
*
* That said, we have been given a sector_buf of
* data to fill the sectors with, so we will use
* that at least.
*/
for (int h = start_hd; h < end_hd; h++) {
for (uint8_t s = 0; s < drive->spt; s++) {
/* Set the sector we need to write. */
dev->head = h;
dev->sector = s;
/* Get address of sector to write. */
if (get_sector(dev, drive, &addr))
break;
/* Write the block to the image. */
hdd_image_write(drive->hdd_num, addr, 1,
(uint8_t *) dev->sector_buf);
}
}
/* One more track done. */
if (++start_cyl == end_cyl)
break;
/* This saves us a LOT of code. */
goto do_fmt;
default:
break;
}
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
}
/* Execute the DCB we just received. */
static void
hdc_callback(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
dcb_t *dcb = &dev->dcb;
drive_t *drive;
const dprm_t *params;
off64_t addr;
int no_data = 0;
int val;
drive = &dev->drives[dcb->drvsel];
dev->comp = (dcb->drvsel) ? COMP_DRIVE : 0x00;
dev->status |= STAT_DCB;
switch (dcb->cmd) {
case CMD_TEST_READY:
if (!drive->present) {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
}
set_intr(dev);
break;
case CMD_RECALIBRATE:
if (!drive->present) {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
} else {
dev->track = drive->cur_cyl = 0;
}
set_intr(dev);
break;
case CMD_READ_SENSE:
switch (dev->state) {
case STATE_IDLE:
dev->buf_idx = 0;
dev->buf_len = 4;
dev->buf_ptr = dev->data;
dev->buf_ptr[0] = dev->sense;
dev->buf_ptr[1] = dcb->drvsel ? 0x20 : 0x00;
dev->buf_ptr[2] = (drive->cur_cyl >> 2) | (dev->sector & 0x3f);
dev->buf_ptr[3] = (drive->cur_cyl & 0xff);
dev->sense = ERR_NOERROR;
dev->status |= (STAT_IO | STAT_REQ);
dev->state = STATE_SDATA;
break;
case STATE_SDONE:
set_intr(dev);
break;
default:
break;
}
break;
case CMD_READ_VERIFY:
no_data = 1;
fallthrough;
case CMD_READ_SECTORS:
if (!drive->present) {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
set_intr(dev);
break;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder. */
do_seek(dev, drive,
(dcb->cyl_low | (dcb->cyl_high << 8)));
dev->head = dcb->head;
dev->sector = dcb->sector;
/* Get sector count; count=0 means 256. */
dev->count = (int) dcb->count;
if (dev->count == 0)
dev->count = 256;
dev->buf_len = 512;
dev->state = STATE_SEND;
fallthrough;
case STATE_SEND:
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
do_send:
/* Get address of sector to load. */
if (get_sector(dev, drive, &addr)) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
dev->comp |= COMP_ERR;
set_intr(dev);
return;
}
/* Read the block from the image. */
hdd_image_read(drive->hdd_num, addr, 1,
(uint8_t *) dev->sector_buf);
/* Ready to transfer the data out. */
dev->state = STATE_SDATA;
dev->buf_idx = 0;
if (no_data) {
/* Delay a bit, no actual transfer. */
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
if (dev->intr & DMA_ENA) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
/* Copy from sector to data. */
memcpy(dev->data,
dev->sector_buf,
dev->buf_len);
dev->buf_ptr = dev->data;
dev->status |= (STAT_IO | STAT_REQ);
}
}
break;
case STATE_SDATA:
if (!no_data) {
/* Perform DMA. */
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_write(dev->dma,
*dev->buf_ptr);
if (val == DMA_NODATA) {
xta_log("%s: CMD_READ_SECTORS out of data (idx=%d, len=%d)!\n", dev->name, dev->buf_idx, dev->buf_len);
dev->status |= (STAT_CD | STAT_IO | STAT_REQ);
timer_advance_u64(&dev->timer, HDC_TIME);
return;
}
dev->buf_ptr++;
dev->buf_idx++;
}
}
timer_advance_u64(&dev->timer, HDC_TIME);
dev->state = STATE_SDONE;
break;
case STATE_SDONE:
dev->buf_idx = 0;
if (--dev->count == 0) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
set_intr(dev);
return;
}
/* Addvance to next sector. */
next_sector(dev, drive);
/* This saves us a LOT of code. */
dev->state = STATE_SEND;
goto do_send;
default:
break;
}
break;
case CMD_WRITE_SECTORS:
if (!drive->present) {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
set_intr(dev);
break;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder. */
do_seek(dev, drive,
(dcb->cyl_low | (dcb->cyl_high << 8)));
dev->head = dcb->head;
dev->sector = dcb->sector;
/* Get sector count; count=0 means 256. */
dev->count = (int) dev->dcb.count;
if (dev->count == 0)
dev->count = 256;
dev->buf_len = 512;
dev->state = STATE_RECV;
fallthrough;
case STATE_RECV:
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
do_recv:
/* Ready to transfer the data in. */
dev->state = STATE_RDATA;
dev->buf_idx = 0;
if (dev->intr & DMA_ENA) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
/* No DMA, do PIO. */
dev->buf_ptr = dev->data;
dev->status |= STAT_REQ;
}
break;
case STATE_RDATA:
if (!no_data) {
/* Perform DMA. */
dev->status = STAT_BSY;
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
xta_log("%s: CMD_WRITE_SECTORS out of data (idx=%d, len=%d)!\n", dev->name, dev->buf_idx, dev->buf_len);
xta_log("%s: CMD_WRITE_SECTORS out of data!\n", dev->name);
dev->status |= (STAT_CD | STAT_IO | STAT_REQ);
timer_advance_u64(&dev->timer, HDC_TIME);
return;
}
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
dev->buf_idx++;
}
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, HDC_TIME);
}
break;
case STATE_RDONE:
/* Copy from data to sector if PIO. */
if (!(dev->intr & DMA_ENA))
memcpy(dev->sector_buf, dev->data,
dev->buf_len);
/* Get address of sector to write. */
if (get_sector(dev, drive, &addr)) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
dev->comp |= COMP_ERR;
set_intr(dev);
return;
}
/* Write the block to the image. */
hdd_image_write(drive->hdd_num, addr, 1,
(uint8_t *) dev->sector_buf);
dev->buf_idx = 0;
if (--dev->count == 0) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
set_intr(dev);
return;
}
/* Advance to next sector. */
next_sector(dev, drive);
/* This saves us a LOT of code. */
dev->state = STATE_RECV;
goto do_recv;
default:
break;
}
break;
case CMD_FORMAT_DRIVE:
case CMD_FORMAT_TRACK:
if (drive->present) {
do_format(dev, drive, dcb);
} else {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
}
set_intr(dev);
break;
case CMD_SEEK:
/* Seek to cylinder. */
val = (dcb->cyl_low | (dcb->cyl_high << 8));
if (drive->present) {
do_seek(dev, drive, val);
if (val != drive->cur_cyl) {
dev->comp |= COMP_ERR;
dev->sense = ERR_SEEK;
}
} else {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
}
set_intr(dev);
break;
case CMD_SET_DRIVE_PARAMS:
switch (dev->state) {
case STATE_IDLE:
dev->state = STATE_RDATA;
dev->buf_idx = 0;
dev->buf_len = sizeof(dprm_t);
dev->buf_ptr = (uint8_t *) dev->data;
dev->status |= STAT_REQ;
break;
case STATE_RDONE:
params = (dprm_t *) dev->data;
drive->tracks = (params->cyl_high << 8) | params->cyl_low;
drive->hpc = params->heads;
drive->spt = 17 /*hardcoded*/;
dev->status &= ~STAT_REQ;
set_intr(dev);
break;
default:
break;
}
break;
case CMD_WRITE_SECTOR_BUFFER:
switch (dev->state) {
case STATE_IDLE:
dev->buf_idx = 0;
dev->buf_len = 512;
dev->state = STATE_RDATA;
if (dev->intr & DMA_ENA) {
dev->buf_ptr = dev->sector_buf;
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
dev->buf_ptr = dev->data;
dev->status |= STAT_REQ;
}
break;
case STATE_RDATA:
if (dev->intr & DMA_ENA) {
/* Perform DMA. */
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
xta_log("%s: CMD_WRITE_BUFFER out of data!\n", dev->name);
dev->status |= (STAT_CD | STAT_IO | STAT_REQ);
timer_advance_u64(&dev->timer, HDC_TIME);
return;
}
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
dev->buf_idx++;
}
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, HDC_TIME);
}
break;
case STATE_RDONE:
if (!(dev->intr & DMA_ENA))
memcpy(dev->sector_buf,
dev->data, dev->buf_len);
set_intr(dev);
break;
default:
break;
}
break;
case CMD_RAM_DIAGS:
switch (dev->state) {
case STATE_IDLE:
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, 5 * HDC_TIME);
break;
case STATE_RDONE:
set_intr(dev);
break;
default:
break;
}
break;
case CMD_DRIVE_DIAGS:
switch (dev->state) {
case STATE_IDLE:
if (drive->present) {
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, 5 * HDC_TIME);
} else {
dev->comp |= COMP_ERR;
dev->sense = ERR_NOTRDY;
set_intr(dev);
}
break;
case STATE_RDONE:
set_intr(dev);
break;
default:
break;
}
break;
case CMD_CTRL_DIAGS:
switch (dev->state) {
case STATE_IDLE:
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, 10 * HDC_TIME);
break;
case STATE_RDONE:
set_intr(dev);
break;
default:
break;
}
break;
default:
xta_log("%s: unknown command - %02x\n", dev->name, dcb->cmd);
dev->comp |= COMP_ERR;
dev->sense = ERR_ILLCMD;
set_intr(dev);
}
}
/* Read one of the controller registers. */
static uint8_t
hdc_read(uint16_t port, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
uint8_t ret = 0xff;
switch (port & 7) {
case 0: /* DATA register */
dev->status &= ~STAT_IRQ;
if (dev->state == STATE_SDATA) {
if (dev->buf_idx > dev->buf_len) {
xta_log("%s: read with empty buffer!\n",
dev->name);
dev->comp |= COMP_ERR;
dev->sense = ERR_ILLCMD;
break;
}
ret = dev->buf_ptr[dev->buf_idx];
if (++dev->buf_idx == dev->buf_len) {
/* All data sent. */
dev->status &= ~STAT_REQ;
dev->state = STATE_SDONE;
timer_set_delay_u64(&dev->timer, HDC_TIME);
}
} else if (dev->state == STATE_COMPL) {
xta_log("DCB=%02X status=%02X comp=%02X\n", dev->dcb.cmd, dev->status, dev->comp);
ret = dev->comp;
dev->status = 0x00;
dev->state = STATE_IDLE;
}
break;
case 1: /* STATUS register */
ret = (dev->status & ~STAT_DCB);
break;
case 2: /* "read option jumpers" */
ret = 0xff; /* all switches off */
break;
default:
break;
}
return ret;
}
/* Write to one of the controller registers. */
static void
hdc_write(uint16_t port, uint8_t val, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
switch (port & 7) {
case 0: /* DATA register */
if (dev->state == STATE_RDATA) {
if (!(dev->status & STAT_REQ)) {
xta_log("%s: not ready for command/data!\n", dev->name);
dev->comp |= COMP_ERR;
dev->sense = ERR_ILLCMD;
break;
}
if (dev->buf_idx >= dev->buf_len) {
xta_log("%s: write with full buffer!\n", dev->name);
dev->comp |= COMP_ERR;
dev->sense = ERR_ILLCMD;
break;
}
/* Store the data into the buffer. */
dev->buf_ptr[dev->buf_idx] = val;
if (++dev->buf_idx == dev->buf_len) {
/* We got all the data we need. */
dev->status &= ~STAT_REQ;
if (dev->status & STAT_DCB)
dev->state = STATE_RDONE;
else
dev->state = STATE_IDLE;
dev->status &= ~STAT_CD;
timer_set_delay_u64(&dev->timer, HDC_TIME);
}
}
break;
case 1: /* RESET register */
dev->sense = 0x00;
dev->state = STATE_IDLE;
break;
case 2: /* "controller-select" */
/* Reset the DCB buffer. */
dev->buf_idx = 0;
dev->buf_len = sizeof(dcb_t);
dev->buf_ptr = (uint8_t *) &dev->dcb;
dev->state = STATE_RDATA;
dev->status = (STAT_BSY | STAT_CD | STAT_REQ);
break;
case 3: /* DMA/IRQ intr register */
#if 0
xta_log("%s: WriteMASK(%02X)\n", dev->name, val);
#endif
dev->intr = val;
break;
default:
break;
}
}
static void *
xta_init(const device_t *info)
{
drive_t *drive;
const char *bios_rev = NULL;
const char *fn = NULL;
hdc_t *dev;
int c;
int max = XTA_NUM;
/* Allocate and initialize device block. */
dev = malloc(sizeof(hdc_t));
memset(dev, 0x00, sizeof(hdc_t));
dev->type = info->local;
/* Do per-controller-type setup. */
switch (dev->type) {
case 0: /* WDXT-150, with BIOS */
dev->name = "WDXT-150";
dev->base = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
dev->rom_addr = device_get_config_hex20("bios_addr");
dev->dma = 3;
bios_rev = (char *) device_get_config_bios("bios_rev");
fn = (char *) device_get_bios_file(info, bios_rev, 0);
max = 1;
break;
case 1: /* EuroPC */
dev->name = "HD20";
dev->base = 0x0320;
dev->irq = 5;
dev->dma = 3;
break;
default:
break;
}
xta_log("%s: initializing (I/O=%04X, IRQ=%d, DMA=%d",
dev->name, dev->base, dev->irq, dev->dma);
if (dev->rom_addr != 0x000000)
xta_log(", BIOS=%06X", dev->rom_addr);
xta_log(")\n");
/* Load any disks for this device class. */
c = 0;
for (uint8_t i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus == HDD_BUS_XTA) && (hdd[i].xta_channel < max)) {
drive = &dev->drives[hdd[i].xta_channel];
if (!hdd_image_load(i)) {
drive->present = 0;
continue;
}
drive->id = c;
drive->hdd_num = i;
drive->present = 1;
/* These are the "hardware" parameters (from the image.) */
drive->cfg_spt = (uint8_t) (hdd[i].spt & 0xff);
drive->cfg_hpc = (uint8_t) (hdd[i].hpc & 0xff);
drive->cfg_tracks = (uint16_t) hdd[i].tracks;
/* Use them as "configured" parameters until overwritten. */
drive->spt = drive->cfg_spt;
drive->hpc = drive->cfg_hpc;
drive->tracks = drive->cfg_tracks;
xta_log("%s: drive%d (cyl=%d,hd=%d,spt=%d), disk %d\n",
dev->name, hdd[i].xta_channel, drive->tracks,
drive->hpc, drive->spt, i);
if (++c > max)
break;
}
}
/* Enable the I/O block. */
io_sethandler(dev->base, 4,
hdc_read, NULL, NULL, hdc_write, NULL, NULL, dev);
/* Load BIOS if it has one. */
if (dev->rom_addr != 0x000000) {
rom_init(&dev->bios_rom, fn,
dev->rom_addr, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
}
/* Create a timer for command delays. */
timer_add(&dev->timer, hdc_callback, dev, 0);
return dev;
}
static void
xta_close(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
const drive_t *drive;
/* Remove the I/O handler. */
io_removehandler(dev->base, 4,
hdc_read, NULL, NULL, hdc_write, NULL, NULL, dev);
/* Close all disks and their images. */
for (uint8_t d = 0; d < XTA_NUM; d++) {
drive = &dev->drives[d];
hdd_image_close(drive->hdd_num);
}
/* Release the device. */
free(dev);
}
static const device_config_t wdxt150_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0320,
.file_filter = "",
.spinner = { 0 }, /*W2*/
.selection = {
{ .description = "320H", .value = 0x0320 },
{ .description = "324H", .value = 0x0324 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 }, /*W3*/
.selection = {
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "" }
},
},
{
.name = "bios_addr",
.description = "BIOS Address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xc8000,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.selection = {
{ .description = "C800H", .value = 0xc8000 },
{ .description = "CA00H", .value = 0xca000 },
{ .description = "" }
},
},
{
.name = "bios_rev",
.description = "BIOS Revision",
.type = CONFIG_BIOS,
.default_string = "rev_1",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "Revision 1.0", .internal_name = "rev_1", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { WD_REV_1_BIOS_FILE, "" } },
{ .name = "Revision 2.0", .internal_name = "rev_2", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 8192, .files = { WD_REV_2_BIOS_FILE, "" } },
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format off
};
const device_t xta_wdxt150_device = {
.name = "WDXT-150 XTA Fixed Disk Controller",
.internal_name = "xta_wdxt150",
.flags = DEVICE_ISA,
.local = 0,
.init = xta_init,
.close = xta_close,
.reset = NULL,
{ .available = NULL /*xta_available*/ },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wdxt150_config
};
const device_t xta_hd20_device = {
.name = "EuroPC HD20 Fixed Disk Controller",
.internal_name = "xta_hd20",
.flags = DEVICE_ISA,
.local = 1,
.init = xta_init,
.close = xta_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_xta.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,510 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the IDE emulation for hard disks and ATAPI
* CD-ROM devices.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/pic.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/scsi_device.h>
#include <86box/isapnp.h>
#include <86box/cdrom.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdd.h>
#include <86box/zip.h>
#include <86box/version.h>
/* Bits of 'atastat' */
#define ERR_STAT 0x01 /* Error */
#define IDX_STAT 0x02 /* Index */
#define CORR_STAT 0x04 /* Corrected data */
#define DRQ_STAT 0x08 /* Data request */
#define DSC_STAT 0x10 /* Drive seek complete */
#define SERVICE_STAT 0x10 /* ATAPI service */
#define DWF_STAT 0x20 /* Drive write fault */
#define DRDY_STAT 0x40 /* Ready */
#define BSY_STAT 0x80 /* Busy */
/* Bits of 'error' */
#define AMNF_ERR 0x01 /* Address mark not found */
#define TK0NF_ERR 0x02 /* Track 0 not found */
#define ABRT_ERR 0x04 /* Command aborted */
#define MCR_ERR 0x08 /* Media change request */
#define IDNF_ERR 0x10 /* Sector ID not found */
#define MC_ERR 0x20 /* Media change */
#define UNC_ERR 0x40 /* Uncorrectable data error */
#define BBK_ERR 0x80 /* Bad block mark detected */
/* ATA Commands */
#define WIN_NOP 0x00
#define WIN_SRST 0x08 /* ATAPI Device Reset */
#define WIN_RECAL 0x10
#define WIN_READ 0x20 /* 28-Bit Read */
#define WIN_READ_NORETRY 0x21 /* 28-Bit Read - no retry */
#define WIN_WRITE 0x30 /* 28-Bit Write */
#define WIN_WRITE_NORETRY 0x31 /* 28-Bit Write - no retry */
#define WIN_VERIFY 0x40 /* 28-Bit Verify */
#define WIN_VERIFY_ONCE 0x41 /* Added by OBattler - deprected older ATA command, according to the specification I found, it is identical to 0x40 */
#define WIN_FORMAT 0x50
#define WIN_SEEK 0x70
#define WIN_DRIVE_DIAGNOSTICS 0x90 /* Execute Drive Diagnostics */
#define WIN_SPECIFY 0x91 /* Initialize Drive Parameters */
#define WIN_PACKETCMD 0xa0 /* Send a packet command. */
#define WIN_PIDENTIFY 0xa1 /* Identify ATAPI device */
#define WIN_READ_MULTIPLE 0xc4
#define WIN_WRITE_MULTIPLE 0xc5
#define WIN_SET_MULTIPLE_MODE 0xc6
#define WIN_READ_DMA 0xc8
#define WIN_READ_DMA_ALT 0xc9
#define WIN_WRITE_DMA 0xca
#define WIN_WRITE_DMA_ALT 0xcb
#define WIN_STANDBYNOW1 0xe0
#define WIN_IDLENOW1 0xe1
#define WIN_SETIDLE1 0xe3
#define WIN_CHECKPOWERMODE1 0xe5
#define WIN_SLEEP1 0xe6
#define WIN_IDENTIFY 0xec /* Ask drive to identify itself */
#define WIN_SET_FEATURES 0xef
#define WIN_READ_NATIVE_MAX 0xf8
#define FEATURE_SET_TRANSFER_MODE 0x03
#define FEATURE_ENABLE_IRQ_OVERLAPPED 0x5d
#define FEATURE_ENABLE_IRQ_SERVICE 0x5e
#define FEATURE_DISABLE_REVERT 0x66
#define FEATURE_ENABLE_REVERT 0xcc
#define FEATURE_DISABLE_IRQ_OVERLAPPED 0xdd
#define FEATURE_DISABLE_IRQ_SERVICE 0xde
#define IDE_TIME 10.0
#define IDE_ATAPI_IS_EARLY ide->sc->pad0
#define ROM_PATH_MCIDE "roms/hdd/xtide/ide_ps2 R1.1.bin"
typedef struct ide_bm_t {
int (*dma)(uint8_t *data, int transfer_length, int out, void *priv);
void (*set_irq)(uint8_t status, void *priv);
void *priv;
} ide_bm_t;
typedef struct ide_board_t {
uint8_t devctl;
uint8_t pad;
uint16_t base[2];
int bit32;
int cur_dev;
int irq;
int inited;
int diag;
int force_ata3;
pc_timer_t timer;
ide_t *ide[2];
ide_bm_t *bm;
} ide_board_t;
typedef struct mcide_t {
uint8_t pos_regs[8];
uint32_t bios_addr;
rom_t bios_rom;
} mcide_t;
ide_board_t *ide_boards[IDE_BUS_MAX];
static uint8_t ide_ter_pnp_rom[] = {
/* BOX0001, serial 0, dummy checksum (filled in by isapnp_add_card) */
0x09, 0xf8, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
/* PnP version 1.0, vendor version 1.0 */
0x0a, 0x10, 0x10,
/* ANSI identifier */
0x82, 0x0e, 0x00, 'I', 'D', 'E', ' ', 'C', 'o', 'n', 't', 'r', 'o',
'l', 'l', 'e', 'r',
/* Logical device BOX0001 */
0x15, 0x09, 0xf8, 0x00, 0x01, 0x00,
/* Compatible device PNP0600 */
0x1c, 0x41, 0xd0, 0x06, 0x00,
/* Start dependent functions, preferred */
0x31, 0x00,
/* IRQ 11 */
0x22, 0x00, 0x08,
/* I/O 0x1E8, decodes 16-bit, 1-byte alignment, 8 addresses */
0x47, 0x01, 0xe8, 0x01, 0xe8, 0x01, 0x01, 0x08,
/* I/O 0x3EE, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0xee, 0x03, 0xee, 0x03, 0x01, 0x01,
/* Start dependent functions, acceptable */
0x30,
/* IRQ 3/4/5/7/9/10/11/12 */
0x22, 0xb8, 0x1e,
/* I/O 0x1E8, decodes 16-bit, 1-byte alignment, 8 addresses */
0x47, 0x01, 0xe8, 0x01, 0xe8, 0x01, 0x01, 0x08,
/* I/O 0x3EE, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0xee, 0x03, 0xee, 0x03, 0x01, 0x01,
/* Start dependent functions, acceptable */
0x30,
/* IRQ 3/4/5/7/9/10/11/12 */
0x22, 0xb8, 0x1e,
/* I/O 0x100-0xFFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xf8, 0xff, 0x08, 0x08,
/* I/O 0x100-0xFFFF, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0x00, 0x01, 0xff, 0xff, 0x01, 0x01,
/* End dependent functions */
0x38,
/* End tag, dummy checksum (filled in by isapnp_add_card) */
0x79, 0x00
};
static uint8_t ide_qua_pnp_rom[] = {
/* BOX0001, serial 1, dummy checksum (filled in by isapnp_add_card) */
0x09, 0xf8, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
/* PnP version 1.0, vendor version 1.0 */
0x0a, 0x10, 0x10,
/* ANSI identifier */
0x82, 0x0e, 0x00, 'I', 'D', 'E', ' ', 'C', 'o', 'n', 't', 'r', 'o',
'l', 'l', 'e', 'r',
/* Logical device BOX0001 */
0x15, 0x09, 0xf8, 0x00, 0x01, 0x00,
/* Compatible device PNP0600 */
0x1c, 0x41, 0xd0, 0x06, 0x00,
/* Start dependent functions, preferred */
0x31, 0x00,
/* IRQ 10 */
0x22, 0x00, 0x04,
/* I/O 0x168, decodes 16-bit, 1-byte alignment, 8 addresses */
0x47, 0x01, 0x68, 0x01, 0x68, 0x01, 0x01, 0x08,
/* I/O 0x36E, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0x6e, 0x03, 0x6e, 0x03, 0x01, 0x01,
/* Start dependent functions, acceptable */
0x30,
/* IRQ 3/4/5/7/9/10/11/12 */
0x22, 0xb8, 0x1e,
/* I/O 0x168, decodes 16-bit, 1-byte alignment, 8 addresses */
0x47, 0x01, 0x68, 0x01, 0x68, 0x01, 0x01, 0x08,
/* I/O 0x36E, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0x6e, 0x03, 0x6e, 0x03, 0x01, 0x01,
/* Start dependent functions, acceptable */
0x30,
/* IRQ 3/4/5/7/9/10/11/12 */
0x22, 0xb8, 0x1e,
/* I/O 0x100-0xFFF8, decodes 16-bit, 8-byte alignment, 8 addresses */
0x47, 0x01, 0x00, 0x01, 0xf8, 0xff, 0x08, 0x08,
/* I/O 0x100-0xFFFF, decodes 16-bit, 1-byte alignment, 1 address */
0x47, 0x01, 0x00, 0x01, 0xff, 0xff, 0x01, 0x01,
/* End dependent functions */
0x38,
/* End tag, dummy checksum (filled in by isapnp_add_card) */
0x79, 0x00
};
ide_t *ide_drives[IDE_NUM];
int ide_ter_enabled = 0;
int ide_qua_enabled = 0;
static void ide_atapi_callback(ide_t *ide);
static void ide_callback(void *priv);
#ifdef ENABLE_IDE_LOG
int ide_do_log = ENABLE_IDE_LOG;
static void
ide_log(const char *fmt, ...)
{
va_list ap;
if (ide_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ide_log(fmt, ...)
#endif
uint8_t
getstat(ide_t *ide)
{
return ide->tf->atastat;
}
ide_t *
ide_get_drive(int ch)
{
if (ch >= 8)
return NULL;
return ide_drives[ch];
}
double
ide_get_xfer_time(ide_t *ide, int size)
{
double period = (10.0 / 3.0);
/* We assume that 1 MB = 1000000 B in this case, so we have as
many B/us as there are MB/s because 1 s = 1000000 us. */
switch (ide->mdma_mode & 0x300) {
case 0x000: /* PIO */
switch (ide->mdma_mode & 0xff) {
case 0x01:
period = (10.0 / 3.0);
break;
case 0x02:
period = (20.0 / 3.83);
break;
case 0x04:
period = (25.0 / 3.0);
break;
case 0x08:
period = (100.0 / 9.0);
break;
case 0x10:
period = (50.0 / 3.0);
break;
default:
break;
}
break;
case 0x100: /* Single Word DMA */
switch (ide->mdma_mode & 0xff) {
case 0x01:
period = (25.0 / 12.0);
break;
case 0x02:
period = (25.0 / 6.0);
break;
case 0x04:
period = (25.0 / 3.0);
break;
default:
break;
}
break;
case 0x200: /* Multiword DMA */
switch (ide->mdma_mode & 0xff) {
case 0x01:
period = (25.0 / 6.0);
break;
case 0x02:
period = (40.0 / 3.0);
break;
case 0x04:
period = (50.0 / 3.0);
break;
default:
break;
}
break;
case 0x300: /* Ultra DMA */
switch (ide->mdma_mode & 0xff) {
case 0x01:
period = (50.0 / 3.0);
break;
case 0x02:
period = 25.0;
break;
case 0x04:
period = (100.0 / 3.0);
break;
case 0x08:
period = (400.0 / 9.0);
break;
case 0x10:
period = (200.0 / 3.0);
break;
case 0x20:
period = 100.0;
break;
default:
break;
}
break;
default:
break;
}
period = (1.0 / period); /* get us for 1 byte */
return period * ((double) size); /* multiply by bytes to get period for the entire transfer */
}
double
ide_atapi_get_period(uint8_t channel)
{
ide_t *ide = ide_drives[channel];
ide_log("ide_atapi_get_period(%i)\n", channel);
if (ide == NULL) {
ide_log("Get period failed\n");
return -1.0;
}
return ide_get_xfer_time(ide, 1);
}
static void
ide_irq_update(ide_board_t *dev, int log)
{
ide_t *ide;
uint8_t set;
if (dev == NULL)
return;
#ifdef ENABLE_IDE_LOG
if (log)
ide_log("IDE %i: IRQ update (%i)\n", dev->cur_dev >> 1, dev->irq);
#endif
ide = ide_drives[dev->cur_dev];
set = !(ide_boards[ide->board]->devctl & 2) && ide->irqstat;
if (!dev->force_ata3 && dev->bm && dev->bm->set_irq)
dev->bm->set_irq(set << 2, dev->bm->priv);
else if (ide_boards[ide->board]->irq != -1)
picint_common(1 << dev->irq, PIC_IRQ_EDGE, set, NULL);
}
void
ide_irq(ide_t *ide, int set, int log)
{
if (ide_boards[ide->board] == NULL)
return;
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("IDE %i: IRQ %s\n", ide->channel, set ? "raise" : "lower");
#endif
ide->irqstat = set;
if (set)
ide->service = 1;
if (ide->selected)
ide_irq_update(ide_boards[ide->board], log);
}
/**
* Copy a string into a buffer, padding with spaces, and placing characters as
* if they were packed into 16-bit values, stored little-endian.
*
* @param str Destination buffer
* @param src Source string
* @param len Length of destination buffer to fill in. Strings shorter than
* this length will be padded with spaces.
*/
void
ide_padstr(char *str, const char *src, const int len)
{
int v;
for (int i = 0; i < len; i++) {
if (*src != '\0')
v = *src++;
else
v = ' ';
str[i ^ 1] = v;
}
}
/**
* Copy a string into a buffer, padding with spaces. Does not add string
* terminator.
*
* @param buf Destination buffer
* @param buf_size Size of destination buffer to fill in. Strings shorter than
* this length will be padded with spaces.
* @param src Source string
*/
void
ide_padstr8(uint8_t *buf, int buf_size, const char *src)
{
for (int i = 0; i < buf_size; i++) {
if (*src != '\0')
buf[i] = *src++;
else
buf[i] = ' ';
}
}
static int
ide_is_ata4(const ide_board_t *board)
{
const ide_bm_t *bm = board->bm;
return (!board->force_ata3 && (bm != NULL));
}
static int
ide_get_max(const ide_t *ide, const int type)
{
const int ata_4 = ide_is_ata4(ide_boards[ide->board]);
const int max[2][4] = { { 0, -1, -1, -1 }, { 4, 2, 2, 5 } };
int ret;
if (ide->type == IDE_ATAPI)
ret = ide->get_max(!IDE_ATAPI_IS_EARLY && ata_4, type);
else
ret = max[ata_4][type];
return ret;
}
static int
ide_get_timings(const ide_t *ide, const int type)
{
const int ata_4 = ide_is_ata4(ide_boards[ide->board]);
const int timings[2][3] = { { 0, 0, 0 }, { 120, 120, 0 } };
int ret;
if (ide->type == IDE_ATAPI)
ret = ide->get_timings(!IDE_ATAPI_IS_EARLY && ata_4, type);
else
ret = timings[ata_4][type];
return ret;
}
/**
* Fill in ide->buffer with the output of the "IDENTIFY DEVICE" command
*/
static void
ide_hd_identify(const ide_t *ide)
{
char device_identify[9] = { '8', '6', 'B', '_', 'H', 'D', '0', '0', 0 };
const ide_bm_t *bm = ide_boards[ide->board]->bm;
uint64_t full_size = (((uint64_t) hdd[ide->hdd_num].tracks) *
hdd[ide->hdd_num].hpc * hdd[ide->hdd_num].spt);
device_identify[6] = (ide->hdd_num / 10) + 0x30;
device_identify[7] = (ide->hdd_num % 10) + 0x30;
ide_log("IDE Identify: %s\n", device_identify);
uint32_t d_hpc = ide->hpc;
uint32_t d_spt = ide->spt;
uint32_t d_tracks;
if ((ide->hpc <= 16) && (ide->spt <= 63)) {
/* HPC <= 16, report as needed. */
d_tracks = ide->tracks;
} else {
/* HPC > 16, convert to 16 HPC. */
if (ide->hpc > 16)
d_hpc = 16;
if (ide->spt > 63)
d_spt = 63;
d_tracks = (ide->tracks * ide->hpc * ide->spt) / (16 * 63);
if (d_tracks > 16383)
d_tracks = 16383;
}
/* Specify default CHS translation */
if (full_size <= 16514064) {
ide->buffer[1] = d_tracks; /* Tracks in default CHS translation. */
ide->buffer[3] = d_hpc; /* Heads in default CHS translation. */
ide->buffer[6] = d_spt; /* Heads in default CHS translation. */
} else {
ide->buffer[1] = 16383; /* Tracks in default CHS translation. */
ide->buffer[3] = 16; /* Heads in default CHS translation. */
ide->buffer[6] = 63; /* Heads in default CHS translation. */
}
ide_log("Default CHS translation: %i, %i, %i\n", ide->buffer[1], ide->buffer[3], ide->buffer[6]);
/* Serial Number */
ide_padstr((char *) (ide->buffer + 10), "", 20);
/* Firmware */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8);
/* Model */
ide_padstr((char *) (ide->buffer + 27), device_identify, 40);
/* Fixed drive */
ide->buffer[0] = (1 << 6);
/* Buffer type */
ide->buffer[20] = 3;
/* Buffer size */
ide->buffer[21] = hdd[ide->hdd_num].cache.num_segments * hdd[ide->hdd_num].cache.segment_size;
/* Capabilities */
ide->buffer[50] = 0x4000;
ide->buffer[59] = ide->blocksize ? (ide->blocksize | 0x100) : 0;
if ((ide->tracks >= 1024) || (ide->hpc > 16) || (ide->spt > 63)) {
ide->buffer[49] = (1 << 9);
ide_log("LBA supported\n");
ide->buffer[60] = full_size & 0xFFFF; /* Total addressable sectors (LBA) */
ide->buffer[61] = (full_size >> 16) & 0x0FFF;
ide_log("Full size: %" PRIu64 "\n", full_size);
/*
Bit 0 = The fields reported in words 54-58 are valid;
Bit 1 = The fields reported in words 64-70 are valid;
Bit 2 = The fields reported in word 88 are valid.
*/
ide->buffer[53] = 1;
if (ide->params_specified) {
ide->buffer[54] = (full_size / ide->cfg_hpc) / ide->cfg_spt;
ide->buffer[55] = ide->cfg_hpc;
ide->buffer[56] = ide->cfg_spt;
} else {
if (full_size <= 16514064) {
ide->buffer[54] = d_tracks;
ide->buffer[55] = d_hpc;
ide->buffer[56] = d_spt;
} else {
ide->buffer[54] = 16383;
ide->buffer[55] = 16;
ide->buffer[56] = 63;
}
}
full_size = ((uint64_t) ide->buffer[54]) * ((uint64_t) ide->buffer[55]) *
((uint64_t) ide->buffer[56]);
/* Total addressable sectors (LBA) */
ide->buffer[57] = full_size & 0xFFFF;
ide->buffer[58] = (full_size >> 16) & 0x0FFF;
ide_log("Current CHS translation: %i, %i, %i\n", ide->buffer[54], ide->buffer[55], ide->buffer[56]);
}
/* Max sectors on multiple transfer command */
ide->buffer[47] = hdd[ide->hdd_num].max_multiple_block | 0x8000;
if (!ide_boards[ide->board]->force_ata3 && (bm != NULL)) {
ide->buffer[80] = 0x7e; /*ATA-1 to ATA-6 supported*/
ide->buffer[81] = 0x19; /*ATA-6 revision 3a supported*/
} else {
ide->buffer[80] = 0x0e; /*ATA-1 to ATA-3 supported*/
}
}
static void
ide_identify(ide_t *ide)
{
int d;
int i;
int max_pio;
int max_sdma;
int max_mdma;
int max_udma;
const ide_t *ide_other = ide_drives[ide->channel ^ 1];
ide_bm_t *bm = ide_boards[ide->board]->bm;
ide_log("IDE IDENTIFY or IDENTIFY PACKET DEVICE on board %i (channel %i)\n", ide->board, ide->channel);
memset(ide->buffer, 0, 512);
if (ide->type == IDE_ATAPI)
ide->identify(ide, !IDE_ATAPI_IS_EARLY && !ide_boards[ide->board]->force_ata3 && (bm != NULL));
else if (ide->type == IDE_HDD)
ide_hd_identify(ide);
else {
fatal("IDE IDENTIFY or IDENTIFY PACKET DEVICE on non-attached IDE device\n");
return;
}
max_pio = ide_get_max(ide, TYPE_PIO);
max_sdma = ide_get_max(ide, TYPE_SDMA);
max_mdma = ide_get_max(ide, TYPE_MDMA);
max_udma = ide_get_max(ide, TYPE_UDMA);
ide_log("IDE %i: max_pio = %i, max_sdma = %i, max_mdma = %i, max_udma = %i\n",
ide->channel, max_pio, max_sdma, max_mdma, max_udma);
if (ide_boards[ide->board]->bit32)
ide->buffer[48] |= 1; /*Dword transfers supported*/
ide->buffer[51] = ide_get_timings(ide, TIMINGS_PIO);
ide->buffer[53] &= 0xfff9;
ide->buffer[52] = ide->buffer[62] = ide->buffer[63] = ide->buffer[64] = 0x0000;
ide->buffer[65] = ide->buffer[66] = ide_get_timings(ide, TIMINGS_DMA);
ide->buffer[67] = ide->buffer[68] = 0x0000;
ide->buffer[88] = 0x0000;
if (max_pio >= 3) {
ide->buffer[53] |= 0x0002;
ide->buffer[67] = ide_get_timings(ide, TIMINGS_PIO);
ide->buffer[68] = ide_get_timings(ide, TIMINGS_PIO_FC);
for (i = 3; i <= max_pio; i++)
ide->buffer[64] |= (1 << (i - 3));
}
if (max_sdma != -1) {
for (i = 0; i <= max_sdma; i++)
ide->buffer[62] |= (1 << i);
}
if (max_mdma != -1) {
for (i = 0; i <= max_mdma; i++)
ide->buffer[63] |= (1 << i);
}
if (max_udma != -1) {
ide->buffer[53] |= 0x0004;
for (i = 0; i <= max_udma; i++)
ide->buffer[88] |= (1 << i);
if (max_udma >= 4)
ide->buffer[93] = 0x6000; /* Drive reports 80-conductor cable */
if (ide->channel & 1)
ide->buffer[93] |= 0x0b00;
else {
ide->buffer[93] |= 0x000b;
/* PDIAG- is assered by device 1, so the bit should be 1 if there's a device 1,
so it should be |= 0x001b if device 1 is present. */
if (ide_other != NULL)
ide->buffer[93] |= 0x0010;
}
}
if ((max_sdma != -1) || (max_mdma != -1) || (max_udma != -1)) {
/* DMA supported */
ide->buffer[49] |= 0x100;
ide->buffer[52] = ide_get_timings(ide, TIMINGS_DMA);
}
if ((max_mdma != -1) || (max_udma != -1)) {
ide->buffer[65] = ide_get_timings(ide, TIMINGS_DMA);
ide->buffer[66] = ide_get_timings(ide, TIMINGS_DMA);
}
if (ide->mdma_mode != -1) {
d = (ide->mdma_mode & 0xff);
d <<= 8;
if ((ide->mdma_mode & 0x300) == 0x000) {
if ((ide->mdma_mode & 0xff) >= 3)
ide->buffer[64] |= d;
} else if ((ide->mdma_mode & 0x300) == 0x100)
ide->buffer[62] |= d;
else if ((ide->mdma_mode & 0x300) == 0x200)
ide->buffer[63] |= d;
else if ((ide->mdma_mode & 0x300) == 0x300)
ide->buffer[88] |= d;
ide_log("PIDENTIFY DMA Mode: %04X, %04X\n", ide->buffer[62], ide->buffer[63]);
}
}
/*
* Return the sector offset for the current register values
*/
static off64_t
ide_get_sector(ide_t *ide)
{
uint32_t heads;
uint32_t sectors;
if (ide->tf->lba)
return (off64_t) ide->lba_addr;
else {
heads = ide->cfg_hpc;
sectors = ide->cfg_spt;
uint8_t sector = ide->tf->sector ? (ide->tf->sector - 1) : 0;
return ((((off64_t) ide->tf->cylinder * heads) + (off64_t) ide->tf->head) * sectors) +
(off64_t) sector;
}
}
static off64_t
ide_get_sector_format(ide_t *ide)
{
uint32_t heads;
uint32_t sectors;
if (ide->tf->lba)
return (off64_t) ide->lba_addr;
else {
heads = ide->cfg_hpc;
sectors = ide->cfg_spt;
return ((((off64_t) ide->tf->cylinder * heads) + (off64_t) ide->tf->head) * sectors);
}
}
/**
* Move to the next sector using CHS addressing
*/
static void
ide_next_sector(ide_t *ide)
{
uint32_t sector = ide->tf->sector;
uint32_t head = ide->tf->head;
if (ide->tf->lba)
ide->lba_addr++;
else {
sector++;
if ((sector == 0) || (sector == (ide->cfg_spt + 1))) {
sector = 1;
head++;
if (head == ide->cfg_hpc) {
head = 0;
ide->tf->cylinder++;
}
}
}
ide->tf->sector = sector & 0xff;
ide->tf->head = head & 0x0f;
}
static void
loadhd(ide_t *ide, int d, UNUSED(const char *fn))
{
if (!hdd_image_load(d)) {
ide->type = IDE_NONE;
return;
}
hdd_preset_apply(d);
ide->spt = ide->cfg_spt = hdd[d].spt;
ide->hpc = ide->cfg_hpc = hdd[d].hpc;
ide->tracks = hdd[d].tracks;
ide->type = IDE_HDD;
ide->hdd_num = d;
}
void
ide_set_signature(ide_t *ide)
{
uint16_t ide_signatures[4] = { 0x7f7f, 0x0000, 0xeb14, 0x7f7f };
ide->tf->sector = 1;
ide->tf->head = 0;
ide->tf->secount = 1;
ide->tf->cylinder = ide_signatures[ide->type & ~IDE_SHADOW];
if (ide->type == IDE_HDD)
ide->drive = 0;
}
static int
ide_set_features(ide_t *ide)
{
uint8_t features;
uint8_t features_data;
int mode;
int submode;
int max;
features = ide->tf->cylprecomp;
features_data = ide->tf->secount;
ide_log("IDE %02X: Set features: %02X, %02X\n", ide->channel, features, features_data);
switch (features) {
case FEATURE_SET_TRANSFER_MODE: /* Set transfer mode. */
ide_log("Transfer mode %02X\n", features_data >> 3);
mode = (features_data >> 3);
submode = features_data & 7;
switch (mode) {
case 0x00: /* PIO default */
if (submode != 0)
return 0;
max = ide_get_max(ide, TYPE_PIO);
ide->mdma_mode = (1 << max);
ide_log("IDE %02X: Setting DPIO mode: %02X, %08X\n", ide->channel,
submode, ide->mdma_mode);
break;
case 0x01: /* PIO mode */
max = ide_get_max(ide, TYPE_PIO);
if (submode > max)
return 0;
ide->mdma_mode = (1 << submode);
ide_log("IDE %02X: Setting PIO mode: %02X, %08X\n", ide->channel,
submode, ide->mdma_mode);
break;
case 0x02: /* Singleword DMA mode */
max = ide_get_max(ide, TYPE_SDMA);
if (submode > max)
return 0;
ide->mdma_mode = (1 << submode) | 0x100;
ide_log("IDE %02X: Setting SDMA mode: %02X, %08X\n", ide->channel,
submode, ide->mdma_mode);
break;
case 0x04: /* Multiword DMA mode */
max = ide_get_max(ide, TYPE_MDMA);
if (submode > max)
return 0;
ide->mdma_mode = (1 << submode) | 0x200;
ide_log("IDE %02X: Setting MDMA mode: %02X, %08X\n", ide->channel,
submode, ide->mdma_mode);
break;
case 0x08: /* Ultra DMA mode */
max = ide_get_max(ide, TYPE_UDMA);
if (submode > max)
return 0;
ide->mdma_mode = (1 << submode) | 0x300;
ide_log("IDE %02X: Setting UDMA mode: %02X, %08X\n", ide->channel,
submode, ide->mdma_mode);
break;
default:
return 0;
}
break;
case FEATURE_ENABLE_IRQ_OVERLAPPED:
case FEATURE_ENABLE_IRQ_SERVICE:
case FEATURE_DISABLE_IRQ_OVERLAPPED:
case FEATURE_DISABLE_IRQ_SERVICE:
max = ide_get_max(ide, TYPE_MDMA);
if (max == -1)
return 0;
else
return 1;
case FEATURE_DISABLE_REVERT: /* Disable reverting to power on defaults. */
case FEATURE_ENABLE_REVERT: /* Enable reverting to power on defaults. */
return 1;
default:
return 0;
}
return 1;
}
void
ide_set_sector(ide_t *ide, int64_t sector_num)
{
unsigned int cyl;
unsigned int r;
if (ide->tf->lba) {
ide->tf->head = (sector_num >> 24) & 0xff;
ide->tf->cylinder = (sector_num >> 8) & 0xffff;
ide->tf->sector = sector_num & 0xff;
} else {
cyl = sector_num / (hdd[ide->hdd_num].hpc * hdd[ide->hdd_num].spt);
r = sector_num % (hdd[ide->hdd_num].hpc * hdd[ide->hdd_num].spt);
ide->tf->cylinder = cyl & 0xffff;
ide->tf->head = ((r / hdd[ide->hdd_num].spt) & 0x0f) & 0xff;
ide->tf->sector = ((r % hdd[ide->hdd_num].spt) + 1) & 0xff;
}
}
static void
ide_zero(int d)
{
ide_t *dev;
if (ide_drives[d] == NULL)
ide_drives[d] = (ide_t *) calloc(1, sizeof(ide_t));
dev = ide_drives[d];
dev->tf = (ide_tf_t *) calloc(1, sizeof(ide_tf_t));
dev->channel = d;
dev->type = IDE_NONE;
dev->hdd_num = -1;
dev->tf->atastat = DRDY_STAT | DSC_STAT;
dev->service = 0;
dev->board = d >> 1;
dev->selected = !(d & 1);
ide_boards[dev->board]->ide[d & 1] = dev;
timer_add(&dev->timer, ide_callback, dev, 0);
}
void
ide_allocate_buffer(ide_t *dev)
{
if (dev->buffer == NULL)
dev->buffer = (uint16_t *) calloc(1, 65536 * sizeof(uint16_t));
}
void
ide_atapi_attach(ide_t *ide)
{
ide_bm_t *bm = ide_boards[ide->board]->bm;
if (ide->type != IDE_NONE)
return;
ide->type = IDE_ATAPI;
ide_allocate_buffer(ide);
ide_set_signature(ide);
ide->mdma_mode = (1 << ide->get_max(!IDE_ATAPI_IS_EARLY &&
!ide_boards[ide->board]->force_ata3 && (bm != NULL), TYPE_PIO));
ide->tf->error = 1;
ide->cfg_spt = ide->cfg_hpc = 0;
if (!IDE_ATAPI_IS_EARLY)
ide->tf->atastat = 0;
}
void
ide_set_callback(ide_t *ide, double callback)
{
if (ide == NULL) {
ide_log("ide_set_callback(NULL): Set callback failed\n");
return;
}
ide_log("ide_set_callback(%i)\n", ide->channel);
if (callback == 0.0)
timer_stop(&ide->timer);
else
timer_on_auto(&ide->timer, callback);
}
void
ide_set_board_callback(uint8_t board, double callback)
{
ide_board_t *dev = ide_boards[board];
ide_log("ide_set_board_callback(%i)\n", board);
if (dev == NULL) {
ide_log("Set board callback failed\n");
return;
}
if (callback == 0.0)
timer_stop(&dev->timer);
else
timer_on_auto(&dev->timer, callback);
}
static void
ide_atapi_command_bus(ide_t *ide)
{
ide->tf->atastat = BUSY_STAT;
ide->tf->phase = 1;
ide->tf->pos = 0;
ide->sc->callback = 1.0 * IDE_TIME;
ide_set_callback(ide, ide->sc->callback);
}
static void
ide_atapi_callback(ide_t *ide)
{
int out;
int ret = 0;
ide_bm_t *bm = ide_boards[ide->board]->bm;
#ifdef ENABLE_IDE_LOG
char *phases[7] = { "Idle", "Command", "Data in", "Data out", "Data in DMA", "Data out DMA",
"Complete" };
char *phase;
switch (ide->sc->packet_status) {
default:
phase = "Unknown";
break;
case PHASE_IDLE ... PHASE_COMPLETE:
phase = phases[ide->sc->packet_status];
break;
case PHASE_ERROR:
phase = "Error";
break;
case PHASE_NONE:
phase = "None";
break;
}
ide_log("Phase: %02X (%s)\n", ide->sc->packet_status, phase);
#endif
switch (ide->sc->packet_status) {
default:
break;
case PHASE_IDLE:
ide->tf->pos = 0;
ide->tf->phase = 1;
ide->tf->atastat = READY_STAT | DRQ_STAT | (ide->tf->atastat & ERR_STAT);
break;
case PHASE_COMMAND:
ide->tf->atastat = BUSY_STAT | (ide->tf->atastat & ERR_STAT);
if (ide->packet_command) {
ide->packet_command(ide->sc, ide->sc->atapi_cdb);
if ((ide->sc->packet_status == PHASE_COMPLETE) && (ide->sc->callback == 0.0))
ide_atapi_callback(ide);
}
break;
case PHASE_COMPLETE:
case PHASE_ERROR:
ide->tf->atastat = READY_STAT;
if (ide->sc->packet_status == PHASE_ERROR)
ide->tf->atastat |= ERR_STAT;
ide->tf->phase = 3;
ide->sc->packet_status = PHASE_NONE;
ide_irq_raise(ide);
break;
case PHASE_DATA_IN:
case PHASE_DATA_OUT:
ide->tf->atastat = READY_STAT | DRQ_STAT | (ide->tf->atastat & ERR_STAT);
ide->tf->phase = !(ide->sc->packet_status & 0x01) << 1;
ide_irq_raise(ide);
break;
case PHASE_DATA_IN_DMA:
case PHASE_DATA_OUT_DMA:
out = (ide->sc->packet_status & 0x01);
if (!IDE_ATAPI_IS_EARLY && !ide_boards[ide->board]->force_ata3 &&
(bm != NULL) && bm->dma) {
ret = bm->dma(ide->sc->temp_buffer, ide->sc->packet_len, out, bm->priv);
}
/* Else, DMA command without a bus master, ret = 0 (default). */
switch (ret) {
default:
break;
case 0:
if (ide->bus_master_error)
ide->bus_master_error(ide->sc);
break;
case 1:
if (out && ide->phase_data_out)
(void) ide->phase_data_out(ide->sc);
else if (!out && ide->command_stop)
ide->command_stop(ide->sc);
if ((ide->sc->packet_status == PHASE_COMPLETE) && (ide->sc->callback == 0.0))
ide_atapi_callback(ide);
break;
case 2:
ide_atapi_command_bus(ide);
break;
}
break;
}
}
/* This is the general ATAPI PIO request function. */
static void
ide_atapi_pio_request(ide_t *ide, uint8_t out)
{
scsi_common_t *dev = ide->sc;
ide_irq_lower(ide);
ide->tf->atastat = BSY_STAT;
if (ide->tf->pos >= dev->packet_len) {
ide_log("%i bytes %s, command done\n", ide->tf->pos, out ? "written" : "read");
ide->tf->pos = dev->request_pos = 0;
if (out && ide->phase_data_out)
ide->phase_data_out(dev);
else if (!out && ide->command_stop)
ide->command_stop(dev);
if ((ide->sc->packet_status == PHASE_COMPLETE) && (ide->sc->callback == 0.0))
ide_atapi_callback(ide);
} else {
ide_log("%i bytes %s, %i bytes are still left\n", ide->tf->pos,
out ? "written" : "read", dev->packet_len - ide->tf->pos);
/* If less than (packet length) bytes are remaining, update packet length
accordingly. */
if ((dev->packet_len - ide->tf->pos) < (dev->max_transfer_len)) {
dev->max_transfer_len = dev->packet_len - ide->tf->pos;
/* Also update the request length so the host knows how many bytes to transfer. */
ide->tf->request_length = dev->max_transfer_len;
}
ide_log("CD-ROM %i: Packet length %i, request length %i\n", dev->id, dev->packet_len,
dev->max_transfer_len);
dev->packet_status = PHASE_DATA_IN | out;
ide->tf->atastat = BSY_STAT;
ide->tf->phase = 1;
ide_atapi_callback(ide);
ide_set_callback(ide, 0.0);
dev->request_pos = 0;
}
}
static uint16_t
ide_atapi_packet_read(ide_t *ide)
{
scsi_common_t *dev = ide->sc;
const uint16_t *bufferw;
uint16_t ret = 0;
if (dev && dev->temp_buffer && (dev->packet_status == PHASE_DATA_IN)) {
ide_log("PHASE_DATA_IN read: %i, %i, %i, %i\n",
dev->request_pos, dev->max_transfer_len, ide->tf->pos, dev->packet_len);
bufferw = (uint16_t *) dev->temp_buffer;
/* Make sure we return a 0 and don't attempt to read from the buffer if
we're transferring bytes beyond it, which can happen when issuing media
access commands with an allocated length below minimum request length
(which is 1 sector = 2048 bytes). */
ret = (ide->tf->pos < dev->packet_len) ? bufferw[ide->tf->pos >> 1] : 0;
ide->tf->pos += 2;
dev->request_pos += 2;
if ((dev->request_pos >= dev->max_transfer_len) || (ide->tf->pos >= dev->packet_len)) {
/* Time for a DRQ. */
ide_atapi_pio_request(ide, 0);
}
}
return ret;
}
static void
ide_atapi_packet_write(ide_t *ide, const uint16_t val)
{
scsi_common_t *dev = ide->sc;
uint8_t *bufferb = NULL;
uint16_t *bufferw = NULL;
if (dev) {
if (dev->packet_status == PHASE_IDLE)
bufferb = dev->atapi_cdb;
else if (dev->temp_buffer)
bufferb = dev->temp_buffer;
bufferw = (uint16_t *) bufferb;
}
if ((bufferb != NULL) && (dev->packet_status != PHASE_DATA_IN)) {
bufferw[ide->tf->pos >> 1] = val & 0xffff;
ide->tf->pos += 2;
dev->request_pos += 2;
if (dev->packet_status == PHASE_DATA_OUT) {
if ((dev->request_pos >= dev->max_transfer_len) || (ide->tf->pos >= dev->packet_len)) {
/* Time for a DRQ. */
ide_atapi_pio_request(ide, 1);
}
} else if (dev->packet_status == PHASE_IDLE) {
if (ide->tf->pos >= 12) {
ide->tf->pos = 0;
ide->tf->atastat = BSY_STAT;
dev->packet_status = PHASE_COMMAND;
ide_atapi_callback(ide);
}
}
}
}
static void
ide_write_data(ide_t *ide, const uint16_t val)
{
uint16_t *idebufferw = ide->buffer;
if ((ide->type != IDE_NONE) && !(ide->type & IDE_SHADOW) && ide->buffer) {
if (ide->command == WIN_PACKETCMD) {
if (ide->type == IDE_ATAPI)
ide_atapi_packet_write(ide, val);
else
ide->tf->pos = 0;
} else {
idebufferw[ide->tf->pos >> 1] = val & 0xffff;
ide->tf->pos += 2;
if (ide->tf->pos >= 512) {
ide->tf->pos = 0;
ide->tf->atastat = BSY_STAT;
const double seek_time = hdd_timing_write(&hdd[ide->hdd_num], ide_get_sector(ide), 1);
const double xfer_time = ide_get_xfer_time(ide, 512);
const double wait_time = seek_time + xfer_time;
if (ide->command == WIN_WRITE_MULTIPLE) {
if ((ide->blockcount + 1) >= ide->blocksize || ide->tf->secount == 1) {
ide_set_callback(ide, seek_time + xfer_time + ide->pending_delay);
ide->pending_delay = 0;
} else {
ide->pending_delay += wait_time;
ide_callback(ide);
}
} else
ide_set_callback(ide, wait_time);
}
}
}
}
void
ide_writew(uint16_t addr, uint16_t val, void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
ide_t *ide;
int ch;
ch = dev->cur_dev;
ide = ide_drives[ch];
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("ide_writew(%04X, %04X, %08X)\n", addr, val, priv);
#endif
addr &= 0x7;
if ((ide->type == IDE_NONE) && ((addr == 0x0) || (addr == 0x7)))
return;
switch (addr) {
case 0x0: /* Data */
ide_write_data(ide, val);
break;
case 0x7:
ide_writeb(addr, val & 0xff, priv);
break;
default:
ide_writeb(addr, val & 0xff, priv);
ide_writeb(addr + 1, (val >> 8) & 0xff, priv);
break;
}
}
static void
ide_writel(uint16_t addr, uint32_t val, void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
ide_t *ide;
int ch;
ch = dev->cur_dev;
ide = ide_drives[ch];
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("ide_writel(%04X, %08X, %08X)\n", addr, val, priv);
#endif
addr &= 0x7;
if ((ide->type == IDE_NONE) && ((addr == 0x0) || (addr == 0x7)))
return;
switch (addr) {
case 0x0: /* Data */
ide_write_data(ide, val & 0xffff);
if (dev->bit32)
ide_write_data(ide, val >> 16);
else
ide_writew(addr + 2, (val >> 16) & 0xffff, priv);
break;
case 0x6:
case 0x7:
ide_writew(addr, val & 0xffff, priv);
break;
default:
ide_writew(addr, val & 0xffff, priv);
ide_writew(addr + 2, (val >> 16) & 0xffff, priv);
break;
}
}
static void
dev_reset(ide_t *ide)
{
ide_set_signature(ide);
if ((ide->type == IDE_ATAPI) && ide->stop)
ide->stop(ide->sc);
}
void
ide_write_devctl(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
ide_board_t *dev = (ide_board_t *) priv;
ide_t *ide;
ide_t *ide_other;
int ch;
uint8_t old;
ch = dev->cur_dev;
ide = ide_drives[ch];
ide_other = ide_drives[ch ^ 1];
ide_log("ide_write_devctl(%04X, %02X, %08X)\n", addr, val, priv);
if ((ide->type == IDE_NONE) && (ide_other->type == IDE_NONE))
return;
dev->diag = 0;
if ((val & 4) && !(dev->devctl & 4)) {
/* Reset toggled from 0 to 1, initiate reset procedure. */
if (ide->type == IDE_ATAPI)
ide->sc->callback = 0.0;
ide_set_callback(ide, 0.0);
ide_set_callback(ide_other, 0.0);
/* We must set set the status to busy in reset mode or
some 286 and 386 machines error out. */
if (!(ch & 1)) {
if (ide->type != IDE_NONE) {
ide->tf->atastat = BSY_STAT;
ide->tf->error = 1;
}
if (ide_other->type != IDE_NONE) {
ide_other->tf->atastat = BSY_STAT;
ide_other->tf->error = 1;
}
}
} else if (!(val & 4) && (dev->devctl & 4)) {
/* Reset toggled from 1 to 0. */
if (!(ch & 1)) {
/* Currently active device is 0, use the device 0 reset protocol. */
/* Device 0. */
dev_reset(ide);
ide->tf->atastat = BSY_STAT;
ide->tf->error = 1;
/* Device 1. */
dev_reset(ide_other);
ide_other->tf->atastat = BSY_STAT;
ide_other->tf->error = 1;
/* Fire the timer. */
dev->diag = 0;
ide->reset = 1;
ide_set_callback(ide, 0.0);
ide_set_callback(ide_other, 0.0);
ide_set_board_callback(ide->board, 1000.4); /* 1 ms + 400 ns, per the specification */
} else {
/* Currently active device is 1, simply reset the status and the active device. */
dev_reset(ide);
if (ide->type == IDE_ATAPI) {
/* Non-early ATAPI devices have DRDY clear after SRST. */
ide->tf->atastat = 0;
if (IDE_ATAPI_IS_EARLY)
ide->tf->atastat |= DRDY_STAT;
} else
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide->tf->error = 1;
ide_other->tf->error = 1; /* Assert PDIAG-. */
dev->cur_dev &= ~1;
ch = dev->cur_dev;
ide = ide_drives[ch];
ide->selected = 1;
ide_other = ide_drives[ch ^ 1];
ide_other->selected = 0;
}
}
old = dev->devctl;
dev->devctl = val;
if (!(val & 0x02) && (old & 0x02))
ide_irq_update(ide_boards[ide->board], 1);
}
static void
ide_reset_registers(ide_t *ide)
{
uint16_t ide_signatures[4] = { 0x7f7f, 0x0000, 0xeb14, 0x7f7f };
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide->tf->error = 1;
ide->tf->secount = 1;
ide->tf->cylinder = ide_signatures[ide->type & ~IDE_SHADOW];
ide->tf->sector = 1;
ide->tf->head = 0;
ide->reset = 0;
if (ide->type == IDE_ATAPI)
ide->sc->callback = 0.0;
ide_set_callback(ide, 0.0);
}
void
ide_writeb(uint16_t addr, uint8_t val, void *priv)
{
ide_board_t *dev = (ide_board_t *) priv;
ide_t *ide;
ide_t *ide_other;
int ch;
int bad = 0;
int reset = 0;
ch = dev->cur_dev;
ide = ide_drives[ch];
ide_other = ide_drives[ch ^ 1];
ide_log("ide_writeb(%04X, %02X, %08X)\n", addr, val, priv);
addr &= 0x7;
if ((ide->type != IDE_NONE) || ((addr != 0x0) && (addr != 0x7))) switch (addr) {
case 0x0: /* Data */
ide_write_data(ide, val | (val << 8));
break;
/* Note to self: for ATAPI, bit 0 of this is DMA if set, PIO if clear. */
case 0x1: /* Features */
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->cylprecomp = val;
if (ide->type == IDE_ATAPI)
ide_log("ATAPI transfer mode: %s\n", (val & 1) ? "DMA" : "PIO");
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT)))
ide_other->tf->cylprecomp = val;
break;
case 0x2: /* Sector count */
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT)))
ide->tf->secount = val;
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT)))
ide_other->tf->secount = val;
break;
case 0x3: /* Sector */
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->sector = val;
ide->lba_addr = (ide->lba_addr & 0xfffff00) | val;
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->sector = val;
ide_other->lba_addr = (ide_other->lba_addr & 0xfffff00) | val;
}
break;
case 0x4: /* Cylinder low */
if (ide->type & IDE_SHADOW)
break;
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->cylinder = (ide->tf->cylinder & 0xff00) | val;
ide->lba_addr = (ide->lba_addr & 0xfff00ff) | (val << 8);
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->cylinder = (ide_other->tf->cylinder & 0xff00) | val;
ide_other->lba_addr = (ide_other->lba_addr & 0xfff00ff) | (val << 8);
}
break;
case 0x5: /* Cylinder high */
if (ide->type & IDE_SHADOW)
break;
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->cylinder = (ide->tf->cylinder & 0xff) | (val << 8);
ide->lba_addr = (ide->lba_addr & 0xf00ffff) | (val << 16);
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->cylinder = (ide_other->tf->cylinder & 0xff) | (val << 8);
ide_other->lba_addr = (ide_other->lba_addr & 0xf00ffff) | (val << 16);
}
break;
case 0x6: /* Drive/Head */
if (ch != ((val >> 4) & 1) + (ide->board << 1)) {
if (!ide->reset && !ide_other->reset && ide->irqstat) {
ide_irq_lower(ide);
ide->irqstat = 1;
}
ide_boards[ide->board]->cur_dev = ((val >> 4) & 1) + (ide->board << 1);
ch = ide_boards[ide->board]->cur_dev;
ide = ide_drives[ch];
ide->selected = 1;
ide_other = ide_drives[ch ^ 1];
ide_other->selected = 0;
if (ide->reset || ide_other->reset) {
ide_reset_registers(ide);
ide_reset_registers(ide_other);
ide_set_board_callback(ide->board, 0.0);
reset = 1;
} else
ide_irq_update(ide_boards[ide->board], 1);
}
if (!reset) {
if (!(ide->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide->tf->drvsel = val & 0xef;
ide->lba_addr = (ide->lba_addr & 0x0ffffff) |
(ide->tf->head << 24);
}
if (!(ide_other->tf->atastat & (BSY_STAT | DRQ_STAT))) {
ide_other->tf->drvsel = val & 0xef;
ide_other->lba_addr = (ide_other->lba_addr & 0x0ffffff) |
(ide->tf->head << 24);
}
}
break;
case 0x7: /* Command register */
if (ide->tf->atastat & (BSY_STAT | DRQ_STAT))
break;
if ((ide->type == IDE_NONE) || ((ide->type & IDE_SHADOW) && (val != WIN_DRIVE_DIAGNOSTICS)))
break;
ide_irq_lower(ide);
ide->command = val;
ide->tf->error = 0;
switch (val) {
case WIN_RECAL ... 0x1f:
case WIN_SEEK ... 0x7f:
if (ide->type == IDE_ATAPI)
ide->tf->atastat = DRDY_STAT;
else
ide->tf->atastat = READY_STAT | BSY_STAT;
if (ide->type == IDE_ATAPI) {
ide->sc->callback = 100.0 * IDE_TIME;
ide_set_callback(ide, 100.0 * IDE_TIME);
} else {
double seek_time = hdd_seek_get_time(&hdd[ide->hdd_num], (val & 0x60) ?
ide_get_sector(ide) : 0, HDD_OP_SEEK, 0, 0.0);
ide_set_callback(ide, seek_time);
}
break;
case WIN_SRST: /* ATAPI Device Reset */
if (ide->type == IDE_ATAPI) {
ide->tf->atastat = BSY_STAT;
ide->sc->callback = 100.0 * IDE_TIME;
} else
ide->tf->atastat = DRDY_STAT;
ide_set_callback(ide, 100.0 * IDE_TIME);
break;
case WIN_READ_MULTIPLE:
/* Fatal removed in accordance with the official ATAPI reference:
If the Read Multiple command is attempted before the Set Multiple Mode
command has been executed or when Read Multiple commands are
disabled, the Read Multiple operation is rejected with an Aborted Com-
mand error. */
ide->blockcount = 0;
fallthrough;
case WIN_READ:
case WIN_READ_NORETRY:
case WIN_READ_DMA:
case WIN_READ_DMA_ALT:
ide->tf->atastat = BSY_STAT;
if (ide->type == IDE_ATAPI)
ide->sc->callback = 200.0 * IDE_TIME;
if (ide->type == IDE_HDD) {
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
uint32_t sec_count;
double wait_time;
if ((val == WIN_READ_DMA) || (val == WIN_READ_DMA_ALT)) {
/* TODO: Make DMA timing more accurate. */
sec_count = ide->tf->secount ? ide->tf->secount : 256;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), sec_count);
double xfer_time = ide_get_xfer_time(ide, 512 * sec_count);
wait_time = seek_time > xfer_time ? seek_time : xfer_time;
} else if ((val == WIN_READ_MULTIPLE) && (ide->blocksize > 0)) {
sec_count = ide->tf->secount ? ide->tf->secount : 256;
if (sec_count > ide->blocksize)
sec_count = ide->blocksize;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), sec_count);
double xfer_time = ide_get_xfer_time(ide, 512 * sec_count);
wait_time = seek_time + xfer_time;
} else if ((val == WIN_READ_MULTIPLE) && (ide->blocksize == 0))
wait_time = 200.0;
else {
sec_count = 1;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), sec_count);
double xfer_time = ide_get_xfer_time(ide, 512 * sec_count);
wait_time = seek_time + xfer_time;
}
ide_set_callback(ide, wait_time);
} else
ide_set_callback(ide, 200.0 * IDE_TIME);
ide->do_initial_read = 1;
break;
case WIN_WRITE_MULTIPLE:
/* Fatal removed for the same reason as for WIN_READ_MULTIPLE. */
ide->blockcount = 0;
/* Turn on the activity indicator *here* so that it gets turned on
less times. */
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
fallthrough;
case WIN_WRITE:
case WIN_WRITE_NORETRY:
ide->tf->atastat = DRQ_STAT | DSC_STAT | DRDY_STAT;
ide->tf->pos = 0;
break;
case WIN_WRITE_DMA:
case WIN_WRITE_DMA_ALT:
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
case WIN_IDENTIFY: /* Identify Device */
case WIN_SET_FEATURES: /* Set Features */
case WIN_READ_NATIVE_MAX:
ide->tf->atastat = BSY_STAT;
if (ide->type == IDE_ATAPI)
ide->sc->callback = 200.0 * IDE_TIME;
if ((ide->type == IDE_HDD) && ((val == WIN_WRITE_DMA) || (val == WIN_WRITE_DMA_ALT))) {
uint32_t sec_count = ide->tf->secount ? ide->tf->secount : 256;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), sec_count);
double xfer_time = ide_get_xfer_time(ide, 512 * sec_count);
double wait_time = seek_time > xfer_time ? seek_time : xfer_time;
ide_set_callback(ide, wait_time);
} else if ((ide->type == IDE_HDD) && ((val == WIN_VERIFY) ||
(val == WIN_VERIFY_ONCE))) {
uint32_t sec_count = ide->tf->secount ? ide->tf->secount : 256;
double seek_time = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), sec_count);
ide_set_callback(ide, seek_time + ide_get_xfer_time(ide, 2));
} else if ((val == WIN_IDENTIFY) || (val == WIN_SET_FEATURES))
ide_callback(ide);
else
ide_set_callback(ide, 200.0 * IDE_TIME);
break;
case WIN_FORMAT:
if (ide->type == IDE_ATAPI)
bad = 1;
else {
ide->tf->atastat = DRQ_STAT;
ide->tf->pos = 0;
}
break;
case WIN_SPECIFY: /* Initialize Drive Parameters */
ide->tf->atastat = BSY_STAT;
if (ide->type == IDE_ATAPI)
ide->sc->callback = 30.0 * IDE_TIME;
ide_set_callback(ide, 30.0 * IDE_TIME);
break;
case WIN_DRIVE_DIAGNOSTICS: /* Execute Drive Diagnostics */
dev->cur_dev &= ~1;
ide = ide_drives[ch & ~1];
ide->selected = 1;
ide_other = ide_drives[ch | 1];
ide_other->selected = 0;
/* Device 0. */
dev_reset(ide);
ide->tf->atastat = BSY_STAT;
ide->tf->error = 1;
/* Device 1. */
dev_reset(ide_other);
ide_other->tf->atastat = BSY_STAT;
ide_other->tf->error = 1;
/* Fire the timer. */
dev->diag = 1;
ide->reset = 1;
ide_set_callback(ide, 0.0);
ide_set_callback(ide_other, 0.0);
ide_set_board_callback(ide->board, 200.0 * IDE_TIME);
break;
case WIN_PIDENTIFY: /* Identify Packet Device */
case WIN_SET_MULTIPLE_MODE: /* Set Multiple Mode */
case WIN_NOP:
case WIN_STANDBYNOW1:
case WIN_IDLENOW1:
case WIN_SETIDLE1: /* Idle */
case WIN_CHECKPOWERMODE1:
case WIN_SLEEP1:
ide->tf->atastat = BSY_STAT;
ide_callback(ide);
break;
case WIN_PACKETCMD: /* ATAPI Packet */
/* Skip the command callback wait, and process immediately. */
ide->tf->pos = 0;
if (ide->type == IDE_ATAPI) {
ide->sc->packet_status = PHASE_IDLE;
ide->tf->secount = 1;
ide->tf->atastat = DRDY_STAT | DRQ_STAT;
if (ide->interrupt_drq)
ide_irq_raise(ide); /* Interrupt DRQ, requires IRQ on any DRQ. */
} else {
ide->tf->atastat = BSY_STAT;
ide_set_callback(ide, 200.0 * IDE_TIME);
}
break;
case 0xf0:
default:
bad = 1;
break;
}
if (bad) {
ide->tf->atastat = DRDY_STAT | ERR_STAT | DSC_STAT;
ide->tf->error = ABRT_ERR;
ide_irq_raise(ide);
}
break;
default:
break;
}
}
static uint16_t
ide_read_data(ide_t *ide)
{
const uint16_t *idebufferw = ide->buffer;
uint16_t ret = 0x0000;
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("ide_read_data(): ch = %i, board = %i, type = %i\n", ide->channel,
ide->board, ide->type);
#endif
if ((ide->type == IDE_NONE) || (ide->type & IDE_SHADOW) || (ide->buffer == NULL))
ret = 0xff7f;
else if (ide->command == WIN_PACKETCMD) {
if (ide->type == IDE_ATAPI)
ret = ide_atapi_packet_read(ide);
else {
ide_log("Drive not ATAPI (position: %i)\n", ide->tf->pos);
ide->tf->pos = 0;
}
} else {
ret = idebufferw[ide->tf->pos >> 1];
ide->tf->pos += 2;
if (ide->tf->pos >= 512) {
ide->tf->pos = 0;
ide->tf->atastat = DRDY_STAT | DSC_STAT;
if (ide->type == IDE_ATAPI)
ide->sc->packet_status = PHASE_IDLE;
if ((ide->command == WIN_READ) ||
(ide->command == WIN_READ_NORETRY) ||
(ide->command == WIN_READ_MULTIPLE)) {
ide->tf->secount--;
if (ide->tf->secount) {
ide_next_sector(ide);
ide->tf->atastat = BSY_STAT | READY_STAT | DSC_STAT;
if (ide->command == WIN_READ_MULTIPLE) {
if (!ide->blockcount) {
uint32_t cnt = ide->tf->secount ?
ide->tf->secount : 256;
if (cnt > ide->blocksize)
cnt = ide->blocksize;
const double seek_us = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), cnt);
const double xfer_us = ide_get_xfer_time(ide, 512 * cnt);
ide_set_callback(ide, seek_us + xfer_us);
} else
ide_callback(ide);
} else {
const double seek_us = hdd_timing_read(&hdd[ide->hdd_num],
ide_get_sector(ide), 1);
const double xfer_us = ide_get_xfer_time(ide, 512);
ide_set_callback(ide, seek_us + xfer_us);
}
} else
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 0);
}
}
}
return ret;
}
static uint8_t
ide_status(ide_t *ide, ide_t *ide_other, int ch)
{
uint8_t ret;
/* Absent and is master or both are absent. */
if (ide->type == IDE_NONE) {
/* Bit 7 pulled down, all other bits pulled up, per the spec. */
ret = 0x7f;
/* Absent and is slave and master is present. */
} else if (ide->type & IDE_SHADOW) {
/* On real hardware, a slave with a present master always
returns a status of 0x00.
Confirmed by the ATA-3 and ATA-4 specifications. */
// ret = 0x00;
ret = 0x01;
} else {
ret = ide->tf->atastat;
if (ide->type == IDE_ATAPI)
ret = (ret & ~DSC_STAT) | (ide->service << 4);
}
return ret;
}
uint8_t
ide_readb(uint16_t addr, void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
int ch;
ide_t *ide;
uint8_t ret = 0xff;
ch = dev->cur_dev;
ide = ide_drives[ch];
switch (addr & 0x7) {
case 0x0: /* Data */
ret = ide_read_data(ide) & 0xff;
break;
/* For ATAPI: Bits 7-4 = sense key, bit 3 = MCR (media change requested),
Bit 2 = ABRT (aborted command), Bit 1 = EOM (end of media),
and Bit 0 = ILI (illegal length indication). */
case 0x1: /* Error */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = ide->tf->error;
break;
/* For ATAPI:
Bit 0: Command or Data:
Data if clear, Command if set;
Bit 1: I/OB
Direction:
To device if set;
From device if clear.
IO DRQ CoD
0 1 1 Ready to accept command packet
1 1 1 Message - ready to send message to host
1 1 0 Data to host
0 1 0 Data from host
1 0 1 Status. */
case 0x2: /* Sector count */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = ide->tf->secount;
break;
case 0x3: /* Sector */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = (uint8_t) ide->tf->sector;
break;
case 0x4: /* Cylinder low */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = ide->tf->cylinder & 0xff;
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("Cylinder low @ board %i, channel %i: ide->type = %i, "
"ret = %02X\n", ide->board, ide->channel, ide->type, ret);
#endif
break;
case 0x5: /* Cylinder high */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = ide->tf->cylinder >> 8;
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("Cylinder high @ board %i, channel %i: ide->type = %i, "
"ret = %02X\n", ide->board, ide->channel, ide->type, ret);
#endif
break;
case 0x6: /* Drive/Head */
if (ide->type == IDE_NONE)
ret = 0x7f;
else
ret = ide->tf->drvsel | ((ch & 1) ? 0xb0 : 0xa0);
break;
/* For ATAPI: Bit 5 is DMA ready, but without overlapped or interlaved DMA, it is
DF (drive fault). */
case 0x7: /* Status */
ide_irq(ide, 0, 0);
ret = ide_status(ide, ide_drives[ch ^ 1], ch);
break;
default:
break;
}
ide_log("ide_readb(%04X, %08X) = %02X\n", addr, priv, ret);
return ret;
}
uint8_t
ide_read_alt_status(UNUSED(const uint16_t addr), void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
const int ch = dev->cur_dev;
ide_t * ide = ide_drives[ch];
/* Per the Seagate ATA-3 specification:
Reading the alternate status does *NOT* clear the IRQ. */
const uint8_t ret = ide_status(ide, ide_drives[ch ^ 1], ch);
ide_log("ide_read_alt_status(%04X, %08X) = %02X\n", addr, priv, ret);
return ret;
}
uint16_t
ide_readw(uint16_t addr, void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
const int ch = dev->cur_dev;
ide_t * ide = ide_drives[ch];
uint16_t ret;
switch (addr & 0x7) {
default:
ret = ide_readb(addr, priv) | (ide_readb(addr + 1, priv) << 8);
break;
case 0x0: /* Data */
ret = ide_read_data(ide);
break;
case 0x7:
ret = ide_readb(addr, priv) | 0xff00;
break;
}
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("ide_readw(%04X, %08X) = %04X\n", addr, priv, ret);
#endif
return ret;
}
static uint32_t
ide_readl(uint16_t addr, void *priv)
{
const ide_board_t *dev = (ide_board_t *) priv;
const int ch = dev->cur_dev;
ide_t * ide = ide_drives[ch];
uint32_t ret;
switch (addr & 0x7) {
case 0x0: /* Data */
ret = ide_read_data(ide);
if (dev->bit32)
ret |= (ide_read_data(ide) << 16);
else
ret |= (ide_readw(addr + 2, priv) << 16);
break;
case 0x6:
case 0x7:
ret = ide_readw(addr, priv) | 0xffff0000;
break;
default:
ret = ide_readw(addr, priv) | (ide_readw(addr + 2, priv) << 16);
break;
}
#if defined(ENABLE_IDE_LOG) && (ENABLE_IDE_LOG == 2)
ide_log("ide_readl(%04X, %08X) = %04X\n", addr, priv, ret);
#endif
return ret;
}
static void
ide_board_callback(void *priv)
{
ide_board_t *dev = (ide_board_t *) priv;
ide_t *ide;
ide_log("ide_board_callback(%i)\n", dev->cur_dev >> 1);
dev->cur_dev &= ~1;
/* Reset the devices in reverse so if there's a slave without a master,
its copy of the master's task file gets reset first. */
for (int8_t i = 1; i >= 0; i--) {
ide = dev->ide[i];
if (ide->type == IDE_ATAPI) {
ide->tf->atastat = 0;
if (IDE_ATAPI_IS_EARLY)
ide->tf->atastat |= DRDY_STAT | DSC_STAT;
} else
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide->reset = 0;
}
ide = dev->ide[0];
if (dev->diag) {
dev->diag = 0;
if ((ide->type != IDE_ATAPI) || IDE_ATAPI_IS_EARLY)
ide_irq_raise(ide);
}
}
static void
atapi_error_no_ready(ide_t *ide)
{
ide->command = 0;
ide->tf->atastat = ERR_STAT | DSC_STAT;
ide->tf->error = ABRT_ERR;
ide->tf->pos = 0;
ide_irq_raise(ide);
}
static void
ide_callback(void *priv)
{
ide_t * ide = (ide_t *) priv;
const ide_bm_t *bm = ide_boards[ide->board]->bm;
int chk_chs;
int ret;
uint8_t err = 0x00;
ide_log("ide_callback(%i): %02X\n", ide->channel, ide->command);
switch (ide->command) {
case WIN_SEEK ... 0x7f:
chk_chs = !ide->tf->lba;
if (ide->type == IDE_ATAPI)
atapi_error_no_ready(ide);
else {
/* The J-Bond PCI400C-A Phoenix BIOS implies that this command is supposed to
ignore the sector number. */
if (chk_chs && ((ide->tf->cylinder >= ide->tracks) || (ide->tf->head >= ide->hpc)))
err = IDNF_ERR;
else {
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
}
}
break;
case WIN_RECAL ... 0x1f:
if (ide->type == IDE_ATAPI)
atapi_error_no_ready(ide);
else {
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
}
break;
/* Initialize the Task File Registers as follows:
Status = 00h, Error = 01h, Sector Count = 01h, Sector Number = 01h,
Cylinder Low = 14h, Cylinder High = EBh and Drive/Head = 00h. */
case WIN_SRST: /*ATAPI Device Reset */
ide->tf->error = 1; /*Device passed*/
ide->tf->secount = 1;
ide->tf->sector = 1;
ide_set_signature(ide);
ide->tf->atastat = DRDY_STAT | DSC_STAT;
if (ide->type == IDE_ATAPI) {
if (ide->device_reset)
ide->device_reset(ide->sc);
if (!IDE_ATAPI_IS_EARLY)
ide->tf->atastat = 0;
}
ide_irq_raise(ide);
if ((ide->type == IDE_ATAPI) && !IDE_ATAPI_IS_EARLY)
ide->service = 0;
break;
case WIN_NOP:
case WIN_STANDBYNOW1:
case WIN_IDLENOW1:
case WIN_SETIDLE1:
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
break;
case WIN_CHECKPOWERMODE1:
case WIN_SLEEP1:
ide->tf->secount = 0xff;
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
break;
case WIN_READ:
case WIN_READ_NORETRY:
if (ide->type == IDE_ATAPI) {
ide_set_signature(ide);
err = ABRT_ERR;
} else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
if (ide->do_initial_read) {
ide->do_initial_read = 0;
ide->sector_pos = 0;
hdd_image_read(ide->hdd_num, ide_get_sector(ide),
ide->tf->secount ? ide->tf->secount : 256, ide->sector_buffer);
}
memcpy(ide->buffer, &ide->sector_buffer[ide->sector_pos * 512], 512);
ide->sector_pos++;
ide->tf->pos = 0;
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
}
break;
case WIN_READ_DMA:
case WIN_READ_DMA_ALT:
if ((ide->type == IDE_ATAPI) || ide_boards[ide->board]->force_ata3 || (bm == NULL)) {
ide_log("IDE %i: DMA read aborted (bad device or board)\n", ide->channel);
err = ABRT_ERR;
} else if (!ide->tf->lba && (ide->cfg_spt == 0)) {
ide_log("IDE %i: DMA read aborted (SPECIFY failed)\n", ide->channel);
err = IDNF_ERR;
} else {
ide->sector_pos = 0;
if (ide->tf->secount)
ide->sector_pos = ide->tf->secount;
else
ide->sector_pos = 256;
hdd_image_read(ide->hdd_num, ide_get_sector(ide), ide->sector_pos, ide->sector_buffer);
ide->tf->pos = 0;
if (!ide_boards[ide->board]->force_ata3 && bm->dma) {
/* We should not abort - we should simply wait for the host to start DMA. */
ret = bm->dma(ide->sector_buffer, ide->sector_pos * 512, 0, bm->priv);
if (ret == 2) {
/* Bus master DMA disabled, simply wait for the host to enable DMA. */
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide_set_callback(ide, 6.0 * IDE_TIME);
return;
} else if (ret == 1) {
/* DMA successful */
ide_log("IDE %i: DMA read successful\n", ide->channel);
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 0);
} else {
/* Bus master DMAS error, abort the command. */
ide_log("IDE %i: DMA read aborted (failed)\n", ide->channel);
err = ABRT_ERR;
}
} else {
ide_log("IDE %i: DMA read aborted (no bus master)\n", ide->channel);
err = ABRT_ERR;
}
}
break;
case WIN_READ_MULTIPLE:
/* According to the official ATA reference:
If the Read Multiple command is attempted before the Set Multiple Mode
command has been executed or when Read Multiple commands are
disabled, the Read Multiple operation is rejected with an Aborted Com-
mand error. */
if ((ide->type == IDE_ATAPI) || !ide->blocksize)
err = ABRT_ERR;
else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
if (ide->do_initial_read) {
ide->do_initial_read = 0;
ide->sector_pos = 0;
hdd_image_read(ide->hdd_num, ide_get_sector(ide),
ide->tf->secount ? ide->tf->secount : 256, ide->sector_buffer);
}
memcpy(ide->buffer, &ide->sector_buffer[ide->sector_pos * 512], 512);
ide->sector_pos++;
ide->tf->pos = 0;
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
if (!ide->blockcount)
ide_irq_raise(ide);
ide->blockcount++;
if (ide->blockcount >= ide->blocksize)
ide->blockcount = 0;
}
break;
case WIN_WRITE:
case WIN_WRITE_NORETRY:
#ifdef ENABLE_IDE_LOG
off64_t sector = ide_get_sector(ide);
#endif
if (ide->type == IDE_ATAPI)
err = ABRT_ERR;
else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
hdd_image_write(ide->hdd_num, ide_get_sector(ide), 1, (uint8_t *) ide->buffer);
ide_irq_raise(ide);
ide->tf->secount--;
if (ide->tf->secount) {
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide->tf->pos = 0;
ide_next_sector(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
} else {
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 0);
}
}
ide_log("Write: %02X, %i, %08X, %" PRIi64 "\n", err, ide->hdd_num, ide->lba_addr, sector);
break;
case WIN_WRITE_DMA:
case WIN_WRITE_DMA_ALT:
if ((ide->type == IDE_ATAPI) || ide_boards[ide->board]->force_ata3 || (bm == NULL)) {
ide_log("IDE %i: DMA write aborted (bad device type or board)\n", ide->channel);
err = ABRT_ERR;
} else if (!ide->tf->lba && (ide->cfg_spt == 0)) {
ide_log("IDE %i: DMA write aborted (SPECIFY failed)\n", ide->channel);
err = IDNF_ERR;
} else {
if (!ide_boards[ide->board]->force_ata3 && bm->dma) {
if (ide->tf->secount)
ide->sector_pos = ide->tf->secount;
else
ide->sector_pos = 256;
ret = bm->dma(ide->sector_buffer, ide->sector_pos * 512, 1, bm->priv);
if (ret == 2) {
/* Bus master DMA disabled, simply wait for the host to enable DMA. */
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide_set_callback(ide, 6.0 * IDE_TIME);
return;
} else if (ret == 1) {
/* DMA successful */
ide_log("IDE %i: DMA write successful\n", ide->channel);
hdd_image_write(ide->hdd_num, ide_get_sector(ide),
ide->sector_pos, ide->sector_buffer);
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 0);
} else {
/* Bus master DMA error, abort the command. */
ide_log("IDE %i: DMA read aborted (failed)\n", ide->channel);
err = ABRT_ERR;
}
} else {
ide_log("IDE %i: DMA write aborted (no bus master)\n", ide->channel);
err = ABRT_ERR;
}
}
break;
case WIN_WRITE_MULTIPLE:
/* According to the official ATA reference:
If the Read Multiple command is attempted before the Set Multiple Mode
command has been executed or when Read Multiple commands are
disabled, the Read Multiple operation is rejected with an Aborted Com-
mand error. */
if ((ide->type == IDE_ATAPI) || !ide->blocksize)
err = ABRT_ERR;
else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
hdd_image_write(ide->hdd_num, ide_get_sector(ide), 1, (uint8_t *) ide->buffer);
ide->blockcount++;
if (ide->blockcount >= ide->blocksize || ide->tf->secount == 1) {
ide->blockcount = 0;
ide_irq_raise(ide);
}
ide->tf->secount--;
if (ide->tf->secount) {
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide->tf->pos = 0;
ide_next_sector(ide);
} else {
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 0);
}
}
break;
case WIN_VERIFY:
case WIN_VERIFY_ONCE:
if (ide->type == IDE_ATAPI)
err = ABRT_ERR;
else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
ide->tf->pos = 0;
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
}
break;
case WIN_FORMAT:
if (ide->type == IDE_ATAPI)
err = ABRT_ERR;
else if (!ide->tf->lba && (ide->cfg_spt == 0))
err = IDNF_ERR;
else {
hdd_image_zero(ide->hdd_num, ide_get_sector_format(ide), ide->tf->secount);
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
ui_sb_update_icon(SB_HDD | hdd[ide->hdd_num].bus, 1);
}
break;
case WIN_SPECIFY: /* Initialize Drive Parameters */
if (ide->type == IDE_ATAPI)
err = ABRT_ERR;
else {
/* Only accept after RESET or DIAG. */
if (ide->params_specified) {
ide->cfg_spt = ide->tf->secount;
ide->cfg_hpc = ide->tf->head + 1;
ide->params_specified = 1;
}
ide->command = 0x00;
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide->tf->error = 1;
ide_irq_raise(ide);
}
break;
case WIN_PIDENTIFY: /* Identify Packet Device */
if (ide->type == IDE_ATAPI) {
ide_identify(ide);
ide->tf->pos = 0;
ide->tf->phase = 2;
ide->tf->error = 0;
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
} else
err = ABRT_ERR;
break;
case WIN_SET_MULTIPLE_MODE:
if ((ide->type == IDE_ATAPI) || (ide->tf->secount < 2) ||
(ide->tf->secount > hdd[ide->hdd_num].max_multiple_block))
err = ABRT_ERR;
else {
ide->blocksize = ide->tf->secount;
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
}
break;
case WIN_SET_FEATURES:
if ((ide->type == IDE_NONE) || !ide_set_features(ide))
err = ABRT_ERR;
else {
ide->tf->atastat = DRDY_STAT | DSC_STAT;
if (ide->type == IDE_ATAPI)
ide->tf->pos = 0;
ide_irq_raise(ide);
}
break;
case WIN_READ_NATIVE_MAX:
if (ide->type == IDE_HDD) {
int snum = hdd[ide->hdd_num].spt;
snum *= hdd[ide->hdd_num].hpc;
snum *= hdd[ide->hdd_num].tracks;
ide_set_sector(ide, snum - 1);
ide->tf->atastat = DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
} else
err = ABRT_ERR;
break;
case WIN_IDENTIFY: /* Identify Device */
if (ide->type == IDE_HDD) {
ide_identify(ide);
ide->tf->pos = 0;
ide->tf->atastat = DRQ_STAT | DRDY_STAT | DSC_STAT;
ide_irq_raise(ide);
} else {
ide_set_signature(ide);
err = ABRT_ERR;
}
break;
case WIN_PACKETCMD: /* ATAPI Packet */
if (ide->type == IDE_ATAPI)
ide_atapi_callback(ide);
else
err = ABRT_ERR;
break;
default:
case 0xff:
err = ABRT_ERR;
break;
}
if (err != 0x00) {
ide->tf->atastat = DRDY_STAT | ERR_STAT | DSC_STAT;
ide->tf->error = err;
ide->tf->pos = 0;
ide_irq_raise(ide);
}
}
uint8_t
ide_read_ali_75(void)
{
const ide_t *ide0;
const ide_t *ide1;
int ch0;
int ch1;
uint8_t ret = 0x00;
ch0 = ide_boards[0]->cur_dev;
ch1 = ide_boards[1]->cur_dev;
ide0 = ide_drives[ch0];
ide1 = ide_drives[ch1];
if (ch1)
ret |= 0x08;
if (ch0)
ret |= 0x04;
if (ide1->irqstat)
ret |= 0x02;
if (ide0->irqstat)
ret |= 0x01;
return ret;
}
uint8_t
ide_read_ali_76(void)
{
const ide_t *ide0;
const ide_t *ide1;
int ch0;
int ch1;
uint8_t ret = 0x00;
ch0 = ide_boards[0]->cur_dev;
ch1 = ide_boards[1]->cur_dev;
ide0 = ide_drives[ch0];
ide1 = ide_drives[ch1];
if (ide1->tf->atastat & BSY_STAT)
ret |= 0x40;
if (ide1->tf->atastat & DRQ_STAT)
ret |= 0x20;
if (ide1->tf->atastat & ERR_STAT)
ret |= 0x10;
if (ide0->tf->atastat & BSY_STAT)
ret |= 0x04;
if (ide0->tf->atastat & DRQ_STAT)
ret |= 0x02;
if (ide0->tf->atastat & ERR_STAT)
ret |= 0x01;
return ret;
}
void
ide_handlers(uint8_t board, int set)
{
if (ide_boards[board] != NULL) {
if (ide_boards[board]->base[0]) {
io_handler(set, ide_boards[board]->base[0], 8,
ide_readb, ide_readw, ide_readl,
ide_writeb, ide_writew, ide_writel,
ide_boards[board]);
}
if (ide_boards[board]->base[1]) {
io_handler(set, ide_boards[board]->base[1], 1,
ide_read_alt_status, NULL, NULL,
ide_write_devctl, NULL, NULL,
ide_boards[board]);
}
}
}
void
ide_set_base_addr(int board, int base, uint16_t port)
{
ide_log("ide_set_base_addr(%i, %i, %04X)\n", board, base, port);
if (ide_boards[board] != NULL)
ide_boards[board]->base[base] = port;
}
void
ide_set_irq(int board, int irq)
{
ide_log("ide_set_irq(%i, %i)\n", board, irq);
if (ide_boards[board] != NULL)
ide_boards[board]->irq = irq;
}
static void
ide_clear_bus_master(int board)
{
ide_bm_t *bm = ide_boards[board]->bm;
if (bm != NULL) {
free(bm);
ide_boards[board]->bm = NULL;
}
}
/*
This so drives can be forced to ATA-3 (no DMA) for machines that hide the
on-board PCI IDE controller (eg. Packard Bell PB640 and ASUS P/I-P54TP4XE),
breaking DMA drivers unless this is done.
*/
extern void
ide_board_set_force_ata3(int board, int force_ata3)
{
ide_log("ide_board_set_force_ata3(%i, %i)\n", board, force_ata3);
if ((ide_boards[board] != NULL) && ide_boards[board]->inited)
ide_boards[board]->force_ata3 = force_ata3;
}
static void
ide_board_close(int board)
{
ide_t *dev;
int c;
ide_log("ide_board_close(%i)\n", board);
if ((ide_boards[board] == NULL) || !ide_boards[board]->inited)
return;
ide_log("IDE: Closing board %i...\n", board);
timer_stop(&ide_boards[board]->timer);
ide_clear_bus_master(board);
/* Close hard disk image files (if previously open) */
for (uint8_t d = 0; d < 2; d++) {
c = (board << 1) + d;
ide_boards[board]->ide[d] = NULL;
dev = ide_drives[c];
if (dev != NULL) {
if ((dev->type == IDE_HDD) && (dev->hdd_num != -1))
hdd_image_close(dev->hdd_num);
if (dev->type == IDE_ATAPI)
dev->tf->atastat = DRDY_STAT | DSC_STAT;
else if (!(dev->type & IDE_SHADOW) && (dev->tf != NULL)) {
free(dev->tf);
dev->tf = NULL;
}
if (dev->buffer) {
free(dev->buffer);
dev->buffer = NULL;
}
if (dev->sector_buffer) {
free(dev->sector_buffer);
dev->buffer = NULL;
}
free(dev);
ide_drives[c] = NULL;
}
}
free(ide_boards[board]);
ide_boards[board] = NULL;
}
static void
ide_board_setup(const int board)
{
const int min_ch = (board << 1);
const int max_ch = min_ch + 1;
int c;
int d;
ide_log("IDE: board %i: loading disks...\n", board);
for (d = 0; d < 2; d++) {
c = (board << 1) + d;
ide_zero(c);
}
c = 0;
for (d = 0; d < HDD_NUM; d++) {
const int is_ide = (hdd[d].bus == HDD_BUS_IDE);
const int ch = hdd[d].ide_channel;
const int valid_ch = ((ch >= min_ch) && (ch <= max_ch));
if (is_ide && valid_ch) {
ide_log("Found IDE hard disk on channel %i\n", ch);
loadhd(ide_drives[ch], d, hdd[d].fn);
if (ide_drives[ch]->sector_buffer == NULL)
ide_drives[ch]->sector_buffer = (uint8_t *) calloc(1, 256 * 512);
if (++c >= 2)
break;
}
}
ide_log("IDE: board %i: done, loaded %d disks.\n", board, c);
for (d = 0; d < 2; d++) {
c = (board << 1) + d;
ide_t *dev = ide_drives[c];
if (dev->type == IDE_NONE)
continue;
ide_allocate_buffer(dev);
ide_set_signature(dev);
dev->mdma_mode = (1 << ide_get_max(dev, TYPE_PIO));
dev->tf->error = 1;
if (dev->type != IDE_HDD)
dev->cfg_spt = dev->cfg_hpc = 0;
if (dev->type == IDE_HDD) {
dev->blocksize = hdd[dev->hdd_num].max_multiple_block;
/* Calculate the default heads and sectors. */
uint32_t d_hpc = dev->hpc;
uint32_t d_spt = dev->spt;
if ((dev->hpc > 16) || (dev->spt > 63)) {
/* HPC > 16, convert to 16 HPC. */
if (dev->hpc > 16)
d_hpc = 16;
if (dev->spt > 63)
d_spt = 63;
}
dev->cfg_spt = d_spt;
dev->cfg_hpc = d_hpc;
}
dev->params_specified = 0;
}
}
static void
ide_board_init(int board, int irq, int base_main, int side_main, int type, int bus)
{
ide_log("ide_board_init(%i, %i, %04X, %04X, %i, %i)\n", board, irq, base_main, side_main, type, bus);
if ((ide_boards[board] != NULL) && ide_boards[board]->inited)
return;
ide_log("IDE: Initializing board %i...\n", board);
if (ide_boards[board] == NULL)
ide_boards[board] = (ide_board_t *) calloc(1, sizeof(ide_board_t));
ide_boards[board]->irq = irq;
ide_boards[board]->cur_dev = board << 1;
if (type & 6)
ide_boards[board]->bit32 = 1;
ide_boards[board]->base[0] = base_main;
ide_boards[board]->base[1] = side_main;
if (!(bus & DEVICE_MCA))
ide_set_handlers(board);
timer_add(&ide_boards[board]->timer, ide_board_callback, ide_boards[board], 0);
ide_board_setup(board);
ide_boards[board]->inited = 1;
}
/* Needed for ESS ES1688/968 PnP. */
void
ide_pnp_config_changed_1addr(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
intptr_t board = (intptr_t) priv;
if (ld)
return;
if (ide_boards[board]->base[0] || ide_boards[board]->base[1]) {
ide_remove_handlers(board);
ide_boards[board]->base[0] = ide_boards[board]->base[1] = 0;
}
ide_boards[board]->irq = -1;
if (config->activate) {
ide_boards[board]->base[0] = (config->io[0].base != ISAPNP_IO_DISABLED) ?
config->io[0].base : 0x0000;
ide_boards[board]->base[1] = (config->io[0].base != ISAPNP_IO_DISABLED) ?
(config->io[0].base + 0x0206) : 0x0000;
if (ide_boards[board]->base[0] && ide_boards[board]->base[1])
ide_set_handlers(board);
if (config->irq[0].irq != ISAPNP_IRQ_DISABLED)
ide_boards[board]->irq = config->irq[0].irq;
}
}
void
ide_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
intptr_t board = (intptr_t) priv;
if (ld)
return;
if (ide_boards[board]->base[0] || ide_boards[board]->base[1]) {
ide_remove_handlers(board);
ide_boards[board]->base[0] = ide_boards[board]->base[1] = 0;
}
ide_boards[board]->irq = -1;
if (config->activate) {
ide_boards[board]->base[0] = (config->io[0].base != ISAPNP_IO_DISABLED) ?
config->io[0].base : 0x0000;
ide_boards[board]->base[1] = (config->io[1].base != ISAPNP_IO_DISABLED) ?
config->io[1].base : 0x0000;
if (ide_boards[board]->base[0] && ide_boards[board]->base[1])
ide_set_handlers(board);
if (config->irq[0].irq != ISAPNP_IRQ_DISABLED)
ide_boards[board]->irq = config->irq[0].irq;
}
}
static void *
ide_ter_init(const device_t *info)
{
/* Don't claim this channel again if it was already claimed. */
if (ide_boards[2])
return (NULL);
int irq;
if (info->local)
irq = -2;
else
irq = device_get_config_int("irq");
if (irq < 0) {
ide_board_init(2, -1, 0, 0, 0, 0);
if (irq == -1)
isapnp_add_card(ide_ter_pnp_rom, sizeof(ide_ter_pnp_rom),
ide_pnp_config_changed, NULL, NULL, NULL, (void *) 2);
} else {
ide_board_init(2, irq, HDC_TERTIARY_BASE, HDC_TERTIARY_SIDE, 0, 0);
}
return (ide_boards[2]);
}
/* Close a standalone IDE unit. */
static void
ide_ter_close(UNUSED(void *priv))
{
ide_board_close(2);
}
static void *
ide_qua_init(const device_t *info)
{
/* Don't claim this channel again if it was already claimed. */
if (ide_boards[3])
return (NULL);
int irq;
if (info->local)
irq = -2;
else
irq = device_get_config_int("irq");
if (irq < 0) {
ide_board_init(3, -1, 0, 0, 0, 0);
if (irq == -1)
isapnp_add_card(ide_qua_pnp_rom, sizeof(ide_qua_pnp_rom),
ide_pnp_config_changed, NULL, NULL, NULL, (void *) 3);
} else
ide_board_init(3, irq, HDC_QUATERNARY_BASE, HDC_QUATERNARY_SIDE, 0, 0);
return (ide_boards[3]);
}
/* Close a standalone IDE unit. */
static void
ide_qua_close(UNUSED(void *priv))
{
ide_board_close(3);
}
void *
ide_xtide_init(void)
{
ide_board_init(0, -1, 0, 0, 0, 0);
return ide_boards[0];
}
void
ide_xtide_close(void)
{
ide_board_close(0);
}
void
ide_set_bus_master(int board,
int (*dma)(uint8_t *data, int transfer_length, int out, void *priv),
void (*set_irq)(uint8_t status, void *priv), void *priv)
{
ide_bm_t *bm;
if (ide_boards[board]->bm == NULL) {
bm = (ide_bm_t *) calloc(1, sizeof(ide_bm_t));
ide_boards[board]->bm = bm;
} else
bm = ide_boards[board]->bm;
bm->dma = dma;
bm->set_irq = set_irq;
bm->priv = priv;
}
static void *
ide_init(const device_t *info)
{
ide_log("Initializing IDE...\n");
switch (info->local) {
case 0 ... 5:
ide_board_init(0, 14, 0x1f0, 0x3f6, info->local, info->flags);
if (info->local & 1)
ide_board_init(1, 15, 0x170, 0x376, info->local, info->flags);
break;
default:
break;
}
return (void *) (intptr_t) -1;
}
static void
ide_drive_reset(int d)
{
ide_log("Resetting IDE drive %i...\n", d);
if ((d & 1) && (ide_drives[d]->type == IDE_NONE) && (ide_drives[d ^ 1]->type != IDE_NONE)) {
ide_drives[d]->type = ide_drives[d ^ 1]->type | IDE_SHADOW;
free(ide_drives[d]->tf);
ide_drives[d]->tf = ide_drives[d ^ 1]->tf;
} else
ide_drives[d]->tf->atastat = DRDY_STAT | DSC_STAT;
ide_drives[d]->channel = d;
ide_drives[d]->service = 0;
ide_drives[d]->board = d >> 1;
ide_drives[d]->selected = !(d & 1);
timer_stop(&ide_drives[d]->timer);
if (ide_boards[d >> 1]) {
ide_boards[d >> 1]->cur_dev = d & ~1;
timer_stop(&ide_boards[d >> 1]->timer);
}
ide_set_signature(ide_drives[d]);
if (ide_drives[d]->sector_buffer)
memset(ide_drives[d]->sector_buffer, 0, 256 * 512);
if (ide_drives[d]->buffer)
memset(ide_drives[d]->buffer, 0, 65536 * sizeof(uint16_t));
}
static void
ide_board_reset(int board)
{
int min;
int max;
ide_log("Resetting IDE board %i...\n", board);
timer_stop(&ide_boards[board]->timer);
min = (board << 1);
max = min + 2;
for (int d = min; d < max; d++)
ide_drive_reset(d);
}
void
ide_drives_set_shadow(void)
{
for (uint8_t d = 0; d < IDE_NUM; d++) {
if (ide_drives[d] == NULL)
continue;
if ((d & 1) && (ide_drives[d]->type == IDE_NONE) && (ide_drives[d ^ 1]->type != IDE_NONE)) {
ide_drives[d]->type = ide_drives[d ^ 1]->type | IDE_SHADOW;
if (ide_drives[d]->tf != NULL)
free(ide_drives[d]->tf);
ide_drives[d]->tf = ide_drives[d ^ 1]->tf;
}
}
}
/* Reset a standalone IDE unit. */
static void
ide_reset(UNUSED(void *priv))
{
ide_log("Resetting IDE...\n");
for (uint8_t i = 0; i < 2; i++) {
if (ide_boards[i] != NULL)
ide_board_reset(i);
}
}
/* Close a standalone IDE unit. */
static void
ide_close(UNUSED(void *priv))
{
ide_log("Closing IDE...\n");
for (uint8_t i = 0; i < 2; i++) {
if (ide_boards[i] != NULL) {
ide_board_close(i);
ide_boards[i] = NULL;
}
}
}
static uint8_t
mcide_mca_read(const int port, void *priv)
{
const mcide_t *dev = (mcide_t *) priv;
ide_log("IDE: mcard(%04x)\n", port);
return (dev->pos_regs[port & 7]);
}
static void
mcide_mca_write(const int port, const uint8_t val, void *priv)
{
mcide_t *dev = (mcide_t *) priv;
uint16_t bases[4] = { 0x01f0, 0x0170, 0x01e8, 0x0168 };
int irqs[4] = { 10, 11, 14, 15 };
if ((port >= 0x102) && (dev->pos_regs[port & 7] != val)) {
ide_log("IDE: mcawr(%04x, %02x) pos[2]=%02x pos[3]=%02x\n",
port, val, dev->pos_regs[2], dev->pos_regs[3]);
/* Save the new value. */
dev->pos_regs[port & 7] = val;
mem_mapping_disable(&dev->bios_rom.mapping);
dev->bios_addr = 0x00000000;
ide_remove_handlers(0);
ide_boards[0]->base[0] = ide_boards[0]->base[1] = 0x0000;
ide_boards[0]->irq = -1;
ide_remove_handlers(1);
ide_boards[1]->base[0] = ide_boards[1]->base[1] = 0x0000;
ide_boards[1]->irq = -1;
if (dev->pos_regs[2] & 1) {
if (dev->pos_regs[2] & 0x80)
dev->bios_addr = 0x000c0000 + (0x00004000 * (uint32_t) ((dev->pos_regs[2] >> 4) & 0x07));
if (dev->pos_regs[3] & 0x08) {
ide_boards[0]->base[0] = bases[dev->pos_regs[3] & 0x03];
ide_boards[0]->base[1] = bases[dev->pos_regs[3] & 0x03] + 0x0206;
}
if (dev->pos_regs[3] & 0x80)
ide_boards[0]->irq = irqs[(dev->pos_regs[3] >> 4) & 0x03];
if (dev->pos_regs[4] & 0x08) {
ide_boards[1]->base[0] = bases[dev->pos_regs[4] & 0x03];
ide_boards[1]->base[1] = bases[dev->pos_regs[4] & 0x03] + 0x0206;
}
if (dev->pos_regs[4] & 0x80)
ide_boards[1]->irq = irqs[(dev->pos_regs[4] >> 4) & 0x03];
ide_set_handlers(0);
ide_set_handlers(1);
if (dev->bios_addr)
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->bios_addr, 0x00004000);
/* Say hello. */
ide_log("McIDE: Primary Master I/O=%03X, Primary IRQ=%02i, "
"Secondary Master I/O=%03X, Secondary IRQ=%02i, "
"BIOS @%05X\n",
ide_boards[0]->base[0], ide_boards[0]->irq,
ide_boards[1]->base[0], ide_boards[1]->irq,
dev->bios_addr);
}
}
}
static uint8_t
mcide_mca_feedb(void *priv)
{
const mcide_t *dev = (mcide_t *) priv;
return (dev->pos_regs[2] & 1);
}
static void
mcide_mca_reset(void *priv)
{
mcide_t *dev = (mcide_t *) priv;
for (uint8_t i = 0; i < 2; i++) {
if (ide_boards[i] != NULL)
ide_board_reset(i);
}
ide_log("McIDE: MCA Reset.\n");
mem_mapping_disable(&dev->bios_rom.mapping);
mcide_mca_write(0x102, 0, dev);
}
static void
mcide_reset(void *priv)
{
for (uint8_t i = 0; i < 2; i++) {
if (ide_boards[i] != NULL)
ide_board_reset(i);
}
ide_log("McIDE: Reset.\n");
}
static void *
mcide_init(const device_t *info)
{
ide_log("Initializing McIDE...\n");
mcide_t *dev = (mcide_t *) calloc(1, sizeof(mcide_t));
ide_board_init(0, -1, 0, 0, info->local, info->flags);
ide_board_init(1, -1, 0, 0, info->local, info->flags);
rom_init(&dev->bios_rom, ROM_PATH_MCIDE,
0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&dev->bios_rom.mapping);
/* Set the MCA ID for this controller, 0xF171. */
dev->pos_regs[0] = 0xf1;
dev->pos_regs[1] = 0x71;
/* Enable the device. */
mca_add(mcide_mca_read, mcide_mca_write, mcide_mca_feedb, mcide_mca_reset, dev);
return dev;
}
static int
mcide_available(void)
{
return (rom_present(ROM_PATH_MCIDE));
}
static void
mcide_close(void *priv)
{
mcide_t *dev = (mcide_t *) priv;
for (uint8_t i = 0; i < 2; i++) {
if (ide_boards[i] != NULL) {
ide_board_close(i);
ide_boards[i] = NULL;
}
}
free(dev);
}
const device_t ide_isa_device = {
.name = "ISA PC/AT IDE Controller",
.internal_name = "ide_isa",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_isa_2ch_device = {
.name = "ISA PC/AT IDE Controller (Dual-Channel)",
.internal_name = "ide_isa_2ch",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 1,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_vlb_device = {
.name = "VLB IDE Controller",
.internal_name = "ide_vlb",
.flags = DEVICE_VLB | DEVICE_AT,
.local = 2,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_vlb_2ch_device = {
.name = "VLB IDE Controller (Dual-Channel)",
.internal_name = "ide_vlb_2ch",
.flags = DEVICE_VLB | DEVICE_AT,
.local = 3,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_pci_device = {
.name = "PCI IDE Controller",
.internal_name = "ide_pci",
.flags = DEVICE_PCI | DEVICE_AT,
.local = 4,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_pci_2ch_device = {
.name = "PCI IDE Controller (Dual-Channel)",
.internal_name = "ide_pci_2ch",
.flags = DEVICE_PCI | DEVICE_AT,
.local = 5,
.init = ide_init,
.close = ide_close,
.reset = ide_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t mcide_device = {
.name = "MCA McIDE Controller",
.internal_name = "ide_mcide",
.flags = DEVICE_MCA,
.local = 3,
.init = mcide_init,
.close = mcide_close,
.reset = mcide_reset,
{ .available = mcide_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
// clang-format off
static const device_config_t ide_ter_config[] = {
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = HDC_TERTIARY_IRQ,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Plug and Play", .value = -1 },
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 12", .value = 12 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t ide_qua_config[] = {
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = HDC_QUATERNARY_IRQ,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Plug and Play", .value = -1 },
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 12", .value = 12 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t ide_ter_device = {
.name = "Tertiary IDE Controller",
.internal_name = "ide_ter",
.flags = DEVICE_AT,
.local = 0,
.init = ide_ter_init,
.close = ide_ter_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ide_ter_config
};
const device_t ide_ter_pnp_device = {
.name = "Tertiary IDE Controller (Plug and Play only)",
.internal_name = "ide_ter_pnp",
.flags = DEVICE_AT,
.local = 1,
.init = ide_ter_init,
.close = ide_ter_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_qua_device = {
.name = "Quaternary IDE Controller",
.internal_name = "ide_qua",
.flags = DEVICE_AT,
.local = 0,
.init = ide_qua_init,
.close = ide_qua_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ide_qua_config
};
const device_t ide_qua_pnp_device = {
.name = "Quaternary IDE Controller (Plug and Play only)",
.internal_name = "ide_qua_pnp",
.flags = DEVICE_AT,
.local = 1,
.init = ide_qua_init,
.close = ide_qua_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 30,820 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Common code to handle all sorts of disk controllers.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdd.h>
int hdc_current[HDC_MAX] = { 0, 0 };
#ifdef ENABLE_HDC_LOG
int hdc_do_log = ENABLE_HDC_LOG;
static void
hdc_log(const char *fmt, ...)
{
va_list ap;
if (hdc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define hdc_log(fmt, ...)
#endif
static const struct {
const device_t *device;
} controllers[] = {
// clang-format off
{ &device_none },
{ &device_internal },
{ &st506_xt_xebec_device },
{ &st506_xt_wdxt_gen_device },
{ &st506_xt_dtc5150x_device },
{ &st506_xt_st11_m_device },
{ &st506_xt_wd1002a_wx1_device },
{ &st506_xt_wd1004a_wx1_device },
{ &st506_at_wd1003_device },
{ &st506_xt_st11_r_device },
{ &st506_xt_wd1002a_27x_device },
{ &st506_xt_wd1004_27x_device },
{ &st506_xt_wd1004a_27x_device },
{ &st506_xt_victor_v86p_device },
{ &esdi_at_wd1007vse1_device },
{ &ide_isa_device },
{ &ide_isa_2ch_device },
{ &xtide_at_device },
{ &xtide_at_ps2_device },
{ &xta_wdxt150_device },
{ &xtide_acculogic_device },
{ &xtide_device },
{ &esdi_ps2_device },
{ &ide_pci_device },
{ &ide_pci_2ch_device },
{ &ide_vlb_device },
{ &ide_vlb_2ch_device },
{ &mcide_device },
{ NULL }
// clang-format on
};
/* Initialize the 'hdc_current' value based on configured HDC name. */
void
hdc_init(void)
{
hdc_log("HDC: initializing..\n");
/* Zero all the hard disk image arrays. */
hdd_image_init();
}
/* Reset the HDC, whichever one that is. */
void
hdc_reset(void)
{
hdc_log("HDC: reset(current=%d, internal=%d)\n",
hdc_current[0], (machines[machine].flags & MACHINE_HDC) ? 1 : 0);
/* If we have a valid controller, add its device. */
if (hdc_current[0] > HDC_INTERNAL)
device_add(controllers[hdc_current[0]].device);
/* Now, add the tertiary and/or quaternary IDE controllers. */
if (ide_ter_enabled)
device_add(&ide_ter_device);
if (ide_qua_enabled)
device_add(&ide_qua_device);
}
const char *
hdc_get_internal_name(int hdc)
{
return device_get_internal_name(controllers[hdc].device);
}
int
hdc_get_from_internal_name(char *s)
{
int c = 0;
while (controllers[c].device != NULL) {
if (!strcmp(controllers[c].device->internal_name, s))
return c;
c++;
}
return 0;
}
const device_t *
hdc_get_device(int hdc)
{
return (controllers[hdc].device);
}
int
hdc_has_config(int hdc)
{
const device_t *dev = hdc_get_device(hdc);
if (dev == NULL)
return 0;
if (!device_has_config(dev))
return 0;
return 1;
}
int
hdc_get_flags(int hdc)
{
return (controllers[hdc].device->flags);
}
int
hdc_available(int hdc)
{
return (device_available(controllers[hdc].device));
}
``` | /content/code_sandbox/src/disk/hdc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,075 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Iomega ZIP drive with SCSI(-like)
* commands, for both ATAPI and SCSI usage.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/config.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/scsi.h>
#include <86box/scsi_device.h>
#include <86box/nvr.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/zip.h>
#define IDE_ATAPI_IS_EARLY id->sc->pad0
zip_drive_t zip_drives[ZIP_NUM];
/* Table of all SCSI commands and their flags, needed for the new disc change / not ready handler. */
const uint8_t zip_command_flags[0x100] = {
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x00 */
IMPLEMENTED | ALLOW_UA | NONDATA | SCSI_ONLY, /* 0x01 */
0,
IMPLEMENTED | ALLOW_UA, /* 0x03 */
IMPLEMENTED | CHECK_READY | ALLOW_UA | NONDATA | SCSI_ONLY, /* 0x04 */
0,
IMPLEMENTED, /* 0x06 */
0,
IMPLEMENTED | CHECK_READY, /* 0x08 */
0,
IMPLEMENTED | CHECK_READY, /* 0x0A */
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x0B */
IMPLEMENTED, /* 0x0C */
IMPLEMENTED | ATAPI_ONLY, /* 0x0D */
0, 0, 0, 0,
IMPLEMENTED | ALLOW_UA, /* 0x12 */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0x13 */
0,
IMPLEMENTED, /* 0x15 */
IMPLEMENTED | SCSI_ONLY, /* 0x16 */
IMPLEMENTED | SCSI_ONLY, /* 0x17 */
0, 0,
IMPLEMENTED, /* 0x1A */
IMPLEMENTED | CHECK_READY, /* 0x1B */
0,
IMPLEMENTED, /* 0x1D */
IMPLEMENTED | CHECK_READY, /* 0x1E */
0, 0, 0, 0,
IMPLEMENTED | ATAPI_ONLY, /* 0x23 */
0,
IMPLEMENTED | CHECK_READY, /* 0x25 */
0, 0,
IMPLEMENTED | CHECK_READY, /* 0x28 */
0,
IMPLEMENTED | CHECK_READY, /* 0x2A */
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x2B */
0, 0,
IMPLEMENTED | CHECK_READY, /* 0x2E */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0x2F */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0,
IMPLEMENTED | CHECK_READY, /* 0x41 */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
IMPLEMENTED, /* 0x55 */
0, 0, 0, 0,
IMPLEMENTED, /* 0x5A */
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
IMPLEMENTED | CHECK_READY, /* 0xA8 */
0,
IMPLEMENTED | CHECK_READY, /* 0xAA */
0, 0, 0,
IMPLEMENTED | CHECK_READY, /* 0xAE */
IMPLEMENTED | CHECK_READY | NONDATA | SCSI_ONLY, /* 0xAF */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IMPLEMENTED, /* 0xBD */
0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
static uint64_t zip_mode_sense_page_flags = (GPMODEP_R_W_ERROR_PAGE | GPMODEP_DISCONNECT_PAGE | GPMODEP_IOMEGA_PAGE | GPMODEP_ALL_PAGES);
static uint64_t zip_250_mode_sense_page_flags = (GPMODEP_R_W_ERROR_PAGE | GPMODEP_FLEXIBLE_DISK_PAGE | GPMODEP_CACHING_PAGE | GPMODEP_IOMEGA_PAGE | GPMODEP_ALL_PAGES);
static const mode_sense_pages_t zip_mode_sense_pages_default =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x0a, 0xc8, 22, 0, 0, 0, 0, 90, 0, 0x50, 0x20 },
{ GPMODE_DISCONNECT_PAGE, 0x0e, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0x5c, 0x0f, 0xff, 0x0f }
} };
// clang-format on
static const mode_sense_pages_t zip_250_mode_sense_pages_default =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x06, 0xc8, 0x64, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{GPMODE_FLEXIBLE_DISK_PAGE, 0x1e, 0x80, 0, 0x40, 0x20, 2, 0, 0, 0xef, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0b, 0x7d, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CACHING_PAGE, 0x0a, 4, 0, 0xff, 0xff, 0, 0, 0xff, 0xff, 0xff, 0xff },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0x5c, 0x0f, 0x3c, 0x0f }
} };
// clang-format on
static const mode_sense_pages_t zip_mode_sense_pages_default_scsi =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x0a, 0xc8, 22, 0, 0, 0, 0, 90, 0, 0x50, 0x20 },
{ GPMODE_DISCONNECT_PAGE, 0x0e, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0x5c, 0x0f, 0xff, 0x0f }
} };
// clang-format on
static const mode_sense_pages_t zip_250_mode_sense_pages_default_scsi =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x06, 0xc8, 0x64, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{GPMODE_FLEXIBLE_DISK_PAGE, 0x1e, 0x80, 0, 0x40, 0x20, 2, 0, 0, 0xef, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0b, 0x7d, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CACHING_PAGE, 0x0a, 4, 0, 0xff, 0xff, 0, 0, 0xff, 0xff, 0xff, 0xff },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0x5c, 0x0f, 0x3c, 0x0f }
} };
// clang-format on
static const mode_sense_pages_t zip_mode_sense_pages_changeable =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x0a, 0xFF, 0xFF, 0, 0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF },
{ GPMODE_DISCONNECT_PAGE, 0x0e, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0xff, 0xff, 0xff, 0xff }
} };
// clang-format on
static const mode_sense_pages_t zip_250_mode_sense_pages_changeable =
// clang-format off
{ {
{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 0x06, 0xFF, 0xFF, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{GPMODE_FLEXIBLE_DISK_PAGE, 0x1e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CACHING_PAGE, 0x0a, 4, 0, 0xff, 0xff, 0, 0, 0xff, 0xff, 0xff, 0xff },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_IOMEGA_PAGE, 0x04, 0xff, 0xff, 0xff, 0xff }
} };
// clang-format on
static void zip_command_complete(zip_t *dev);
static void zip_init(zip_t *dev);
#ifdef ENABLE_ZIP_LOG
int zip_do_log = ENABLE_ZIP_LOG;
static void
zip_log(const char *fmt, ...)
{
va_list ap;
if (zip_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define zip_log(fmt, ...)
#endif
int
find_zip_for_channel(uint8_t channel)
{
for (uint8_t i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel == channel))
return i;
}
return 0xff;
}
static int
zip_load_abort(zip_t *dev)
{
if (dev->drv->fp)
fclose(dev->drv->fp);
dev->drv->fp = NULL;
dev->drv->medium_size = 0;
zip_eject(dev->id); /* Make sure the host OS knows we've rejected (and ejected) the image. */
return 0;
}
int
zip_load(zip_t *dev, char *fn)
{
int size = 0;
if (!dev->drv) {
zip_eject(dev->id);
return 0;
}
dev->drv->fp = plat_fopen(fn, dev->drv->read_only ? "rb" : "rb+");
if (!dev->drv->fp) {
if (!dev->drv->read_only) {
dev->drv->fp = plat_fopen(fn, "rb");
if (dev->drv->fp)
dev->drv->read_only = 1;
else
return zip_load_abort(dev);
} else
return zip_load_abort(dev);
}
fseek(dev->drv->fp, 0, SEEK_END);
size = ftell(dev->drv->fp);
if ((size == ((ZIP_250_SECTORS << 9) + 0x1000)) || (size == ((ZIP_SECTORS << 9) + 0x1000))) {
/* This is a ZDI image. */
size -= 0x1000;
dev->drv->base = 0x1000;
} else
dev->drv->base = 0;
if (dev->drv->is_250) {
if ((size != (ZIP_250_SECTORS << 9)) && (size != (ZIP_SECTORS << 9))) {
zip_log("File is incorrect size for a ZIP image\nMust be exactly %i or %i bytes\n",
ZIP_250_SECTORS << 9, ZIP_SECTORS << 9);
return zip_load_abort(dev);
}
} else {
if (size != (ZIP_SECTORS << 9)) {
zip_log("File is incorrect size for a ZIP image\nMust be exactly %i bytes\n",
ZIP_SECTORS << 9);
return zip_load_abort(dev);
}
}
dev->drv->medium_size = size >> 9;
if (fseek(dev->drv->fp, dev->drv->base, SEEK_SET) == -1)
fatal("zip_load(): Error seeking to the beginning of the file\n");
strncpy(dev->drv->image_path, fn, sizeof(dev->drv->image_path) - 1);
// After using strncpy, dev->drv->image_path needs to be explicitly null terminated to make gcc happy.
// In the event strlen(dev->drv->image_path) == sizeof(dev->drv->image_path) (no null terminator)
// it is placed at the very end. Otherwise, it is placed right after the string.
const size_t term = strlen(dev->drv->image_path) == sizeof(dev->drv->image_path) ? sizeof(dev->drv->image_path) - 1 : strlen(dev->drv->image_path);
dev->drv->image_path[term] = '\0';
return 1;
}
void
zip_disk_reload(zip_t *dev)
{
int ret = 0;
if (strlen(dev->drv->prev_image_path) == 0)
return;
else
ret = zip_load(dev, dev->drv->prev_image_path);
if (ret)
dev->unit_attention = 1;
}
void
zip_disk_unload(zip_t *dev)
{
if (dev->drv && dev->drv->fp) {
fclose(dev->drv->fp);
dev->drv->fp = NULL;
}
}
void
zip_disk_close(zip_t *dev)
{
if (dev->drv && dev->drv->fp) {
zip_disk_unload(dev);
memcpy(dev->drv->prev_image_path, dev->drv->image_path, sizeof(dev->drv->prev_image_path));
memset(dev->drv->image_path, 0, sizeof(dev->drv->image_path));
dev->drv->medium_size = 0;
}
}
static void
zip_set_callback(zip_t *dev)
{
if (dev->drv->bus_type != ZIP_BUS_SCSI)
ide_set_callback(ide_drives[dev->drv->ide_channel], dev->callback);
}
static void
zip_init(zip_t *dev)
{
if (dev->id >= ZIP_NUM)
return;
dev->requested_blocks = 1;
dev->sense[0] = 0xf0;
dev->sense[7] = 10;
dev->drv->bus_mode = 0;
if (dev->drv->bus_type >= ZIP_BUS_ATAPI)
dev->drv->bus_mode |= 2;
if (dev->drv->bus_type < ZIP_BUS_SCSI)
dev->drv->bus_mode |= 1;
zip_log("ZIP %i: Bus type %i, bus mode %i\n", dev->id, dev->drv->bus_type, dev->drv->bus_mode);
if (dev->drv->bus_type < ZIP_BUS_SCSI) {
dev->tf->phase = 1;
dev->tf->request_length = 0xEB14;
}
dev->tf->status = READY_STAT | DSC_STAT;
dev->tf->pos = 0;
dev->packet_status = PHASE_NONE;
zip_sense_key = zip_asc = zip_ascq = dev->unit_attention = 0;
}
static int
zip_supports_pio(zip_t *dev)
{
return (dev->drv->bus_mode & 1);
}
static int
zip_supports_dma(zip_t *dev)
{
return (dev->drv->bus_mode & 2);
}
/* Returns: 0 for none, 1 for PIO, 2 for DMA. */
static int
zip_current_mode(zip_t *dev)
{
if (!zip_supports_pio(dev) && !zip_supports_dma(dev))
return 0;
if (zip_supports_pio(dev) && !zip_supports_dma(dev)) {
zip_log("ZIP %i: Drive does not support DMA, setting to PIO\n", dev->id);
return 1;
}
if (!zip_supports_pio(dev) && zip_supports_dma(dev))
return 2;
if (zip_supports_pio(dev) && zip_supports_dma(dev)) {
zip_log("ZIP %i: Drive supports both, setting to %s\n", dev->id,
(dev->tf->features & 1) ? "DMA" : "PIO");
return (dev->tf->features & 1) ? 2 : 1;
}
return 0;
}
static void
zip_mode_sense_load(zip_t *dev)
{
FILE *fp;
char fn[512];
memset(&dev->ms_pages_saved, 0, sizeof(mode_sense_pages_t));
if (dev->drv->is_250) {
if (zip_drives[dev->id].bus_type == ZIP_BUS_SCSI)
memcpy(&dev->ms_pages_saved, &zip_250_mode_sense_pages_default_scsi, sizeof(mode_sense_pages_t));
else
memcpy(&dev->ms_pages_saved, &zip_250_mode_sense_pages_default, sizeof(mode_sense_pages_t));
} else {
if (zip_drives[dev->id].bus_type == ZIP_BUS_SCSI)
memcpy(&dev->ms_pages_saved, &zip_mode_sense_pages_default_scsi, sizeof(mode_sense_pages_t));
else
memcpy(&dev->ms_pages_saved, &zip_mode_sense_pages_default, sizeof(mode_sense_pages_t));
}
memset(fn, 0, 512);
if (dev->drv->bus_type == ZIP_BUS_SCSI)
sprintf(fn, "scsi_zip_%02i_mode_sense_bin", dev->id);
else
sprintf(fn, "zip_%02i_mode_sense_bin", dev->id);
fp = plat_fopen(nvr_path(fn), "rb");
if (fp) {
/* Nothing to read, not used by ZIP. */
fclose(fp);
}
}
static void
zip_mode_sense_save(zip_t *dev)
{
FILE *fp;
char fn[512];
memset(fn, 0, 512);
if (dev->drv->bus_type == ZIP_BUS_SCSI)
sprintf(fn, "scsi_zip_%02i_mode_sense_bin", dev->id);
else
sprintf(fn, "zip_%02i_mode_sense_bin", dev->id);
fp = plat_fopen(nvr_path(fn), "wb");
if (fp) {
/* Nothing to write, not used by ZIP. */
fclose(fp);
}
}
/*SCSI Mode Sense 6/10*/
static uint8_t
zip_mode_sense_read(zip_t *dev, uint8_t page_control, uint8_t page, uint8_t pos)
{
switch (page_control) {
case 0:
case 3:
if (dev->drv->is_250 && (page == 5) && (pos == 9) && (dev->drv->medium_size == ZIP_SECTORS))
return 0x60;
return dev->ms_pages_saved.pages[page][pos];
case 1:
if (dev->drv->is_250)
return zip_250_mode_sense_pages_changeable.pages[page][pos];
else
return zip_mode_sense_pages_changeable.pages[page][pos];
case 2:
if (dev->drv->is_250) {
if ((page == 5) && (pos == 9) && (dev->drv->medium_size == ZIP_SECTORS))
return 0x60;
if (dev->drv->bus_type == ZIP_BUS_SCSI)
return zip_250_mode_sense_pages_default_scsi.pages[page][pos];
else
return zip_250_mode_sense_pages_default.pages[page][pos];
} else {
if (dev->drv->bus_type == ZIP_BUS_SCSI)
return zip_mode_sense_pages_default_scsi.pages[page][pos];
else
return zip_mode_sense_pages_default.pages[page][pos];
}
default:
break;
}
return 0;
}
static uint32_t
zip_mode_sense(zip_t *dev, uint8_t *buf, uint32_t pos, uint8_t page, uint8_t block_descriptor_len)
{
uint64_t pf;
uint8_t page_control = (page >> 6) & 3;
if (dev->drv->is_250)
pf = zip_250_mode_sense_page_flags;
else
pf = zip_mode_sense_page_flags;
uint8_t msplen;
page &= 0x3f;
if (block_descriptor_len) {
buf[pos++] = ((dev->drv->medium_size >> 24) & 0xff);
buf[pos++] = ((dev->drv->medium_size >> 16) & 0xff);
buf[pos++] = ((dev->drv->medium_size >> 8) & 0xff);
buf[pos++] = (dev->drv->medium_size & 0xff);
buf[pos++] = 0; /* Reserved. */
buf[pos++] = 0; /* Block length (0x200 = 512 bytes). */
buf[pos++] = 2;
buf[pos++] = 0;
}
for (uint8_t i = 0; i < 0x40; i++) {
if ((page == GPMODE_ALL_PAGES) || (page == i)) {
if (pf & (1LL << ((uint64_t) page))) {
buf[pos++] = zip_mode_sense_read(dev, page_control, i, 0);
msplen = zip_mode_sense_read(dev, page_control, i, 1);
buf[pos++] = msplen;
zip_log("ZIP %i: MODE SENSE: Page [%02X] length %i\n", dev->id, i, msplen);
for (uint8_t j = 0; j < msplen; j++)
buf[pos++] = zip_mode_sense_read(dev, page_control, i, 2 + j);
}
}
}
return pos;
}
static void
zip_update_request_length(zip_t *dev, int len, int block_len)
{
int bt;
int min_len = 0;
dev->max_transfer_len = dev->tf->request_length;
/* For media access commands, make sure the requested DRQ length matches the block length. */
switch (dev->current_cdb[0]) {
case 0x08:
case 0x0a:
case 0x28:
case 0x2a:
case 0xa8:
case 0xaa:
/* Round it to the nearest 2048 bytes. */
dev->max_transfer_len = (dev->max_transfer_len >> 9) << 9;
/* Make sure total length is not bigger than sum of the lengths of
all the requested blocks. */
bt = (dev->requested_blocks * block_len);
if (len > bt)
len = bt;
min_len = block_len;
if (len <= block_len) {
/* Total length is less or equal to block length. */
if (dev->max_transfer_len < block_len) {
/* Transfer a minimum of (block size) bytes. */
dev->max_transfer_len = block_len;
dev->packet_len = block_len;
break;
}
}
fallthrough;
default:
dev->packet_len = len;
break;
}
/* If the DRQ length is odd, and the total remaining length is bigger, make sure it's even. */
if ((dev->max_transfer_len & 1) && (dev->max_transfer_len < len))
dev->max_transfer_len &= 0xfffe;
/* If the DRQ length is smaller or equal in size to the total remaining length, set it to that. */
if (!dev->max_transfer_len)
dev->max_transfer_len = 65534;
if ((len <= dev->max_transfer_len) && (len >= min_len))
dev->tf->request_length = dev->max_transfer_len = len;
else if (len > dev->max_transfer_len)
dev->tf->request_length = dev->max_transfer_len;
return;
}
static double
zip_bus_speed(zip_t *dev)
{
double ret = -1.0;
if (dev && dev->drv && (dev->drv->bus_type == ZIP_BUS_SCSI)) {
dev->callback = -1.0; /* Speed depends on SCSI controller */
return 0.0;
} else {
if (dev && dev->drv)
ret = ide_atapi_get_period(dev->drv->ide_channel);
if (ret == -1.0) {
if (dev)
dev->callback = -1.0;
return 0.0;
} else
return ret * 1000000.0;
}
}
static void
zip_command_common(zip_t *dev)
{
double bytes_per_second;
double period;
dev->tf->status = BUSY_STAT;
dev->tf->phase = 1;
dev->tf->pos = 0;
if (dev->packet_status == PHASE_COMPLETE)
dev->callback = 0.0;
else {
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
dev->callback = -1.0; /* Speed depends on SCSI controller */
return;
} else
bytes_per_second = zip_bus_speed(dev);
period = 1000000.0 / bytes_per_second;
dev->callback = period * (double) (dev->packet_len);
}
zip_set_callback(dev);
}
static void
zip_command_complete(zip_t *dev)
{
dev->packet_status = PHASE_COMPLETE;
zip_command_common(dev);
}
static void
zip_command_read(zip_t *dev)
{
dev->packet_status = PHASE_DATA_IN;
zip_command_common(dev);
}
static void
zip_command_read_dma(zip_t *dev)
{
dev->packet_status = PHASE_DATA_IN_DMA;
zip_command_common(dev);
}
static void
zip_command_write(zip_t *dev)
{
dev->packet_status = PHASE_DATA_OUT;
zip_command_common(dev);
}
static void
zip_command_write_dma(zip_t *dev)
{
dev->packet_status = PHASE_DATA_OUT_DMA;
zip_command_common(dev);
}
/* id = Current ZIP device ID;
len = Total transfer length;
block_len = Length of a single block (why does it matter?!);
alloc_len = Allocated transfer length;
direction = Transfer direction (0 = read from host, 1 = write to host). */
static void
zip_data_command_finish(zip_t *dev, int len, int block_len, int alloc_len, int direction)
{
zip_log("ZIP %i: Finishing command (%02X): %i, %i, %i, %i, %i\n",
dev->id, dev->current_cdb[0], len, block_len, alloc_len, direction, dev->tf->request_length);
dev->tf->pos = 0;
if (alloc_len >= 0) {
if (alloc_len < len)
len = alloc_len;
}
if ((len == 0) || (zip_current_mode(dev) == 0)) {
if (dev->drv->bus_type != ZIP_BUS_SCSI)
dev->packet_len = 0;
zip_command_complete(dev);
} else {
if (zip_current_mode(dev) == 2) {
if (dev->drv->bus_type != ZIP_BUS_SCSI)
dev->packet_len = alloc_len;
if (direction == 0)
zip_command_read_dma(dev);
else
zip_command_write_dma(dev);
} else {
zip_update_request_length(dev, len, block_len);
if (direction == 0)
zip_command_read(dev);
else
zip_command_write(dev);
}
}
zip_log("ZIP %i: Status: %i, cylinder %i, packet length: %i, position: %i, phase: %i\n",
dev->id, dev->packet_status, dev->tf->request_length, dev->packet_len, dev->tf->pos,
dev->tf->phase);
}
static void
zip_sense_clear(zip_t *dev, UNUSED(int command))
{
zip_sense_key = zip_asc = zip_ascq = 0;
}
static void
zip_set_phase(zip_t *dev, uint8_t phase)
{
uint8_t scsi_bus = (dev->drv->scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_device_id & 0x0f;
if (dev->drv->bus_type != ZIP_BUS_SCSI)
return;
scsi_devices[scsi_bus][scsi_id].phase = phase;
}
static void
zip_cmd_error(zip_t *dev)
{
zip_set_phase(dev, SCSI_PHASE_STATUS);
dev->tf->error = ((zip_sense_key & 0xf) << 4) | ABRT_ERR;
if (dev->unit_attention)
dev->tf->error |= MCR_ERR;
dev->tf->status = READY_STAT | ERR_STAT;
dev->tf->phase = 3;
dev->tf->pos = 0;
dev->packet_status = PHASE_ERROR;
dev->callback = 50.0 * ZIP_TIME;
zip_set_callback(dev);
ui_sb_update_icon(SB_ZIP | dev->id, 0);
zip_log("ZIP %i: [%02X] ERROR: %02X/%02X/%02X\n", dev->id, dev->current_cdb[0], zip_sense_key, zip_asc, zip_ascq);
}
static void
zip_unit_attention(zip_t *dev)
{
zip_set_phase(dev, SCSI_PHASE_STATUS);
dev->tf->error = (SENSE_UNIT_ATTENTION << 4) | ABRT_ERR;
if (dev->unit_attention)
dev->tf->error |= MCR_ERR;
dev->tf->status = READY_STAT | ERR_STAT;
dev->tf->phase = 3;
dev->tf->pos = 0;
dev->packet_status = PHASE_ERROR;
dev->callback = 50.0 * ZIP_TIME;
zip_set_callback(dev);
ui_sb_update_icon(SB_ZIP | dev->id, 0);
zip_log("ZIP %i: UNIT ATTENTION\n", dev->id);
}
static void
zip_buf_alloc(zip_t *dev, uint32_t len)
{
zip_log("ZIP %i: Allocated buffer length: %i\n", dev->id, len);
if (!dev->buffer)
dev->buffer = (uint8_t *) malloc(len);
}
static void
zip_buf_free(zip_t *dev)
{
if (dev->buffer) {
zip_log("ZIP %i: Freeing buffer...\n", dev->id);
free(dev->buffer);
dev->buffer = NULL;
}
}
static void
zip_bus_master_error(scsi_common_t *sc)
{
zip_t *dev = (zip_t *) sc;
zip_buf_free(dev);
zip_sense_key = zip_asc = zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_not_ready(zip_t *dev)
{
zip_sense_key = SENSE_NOT_READY;
zip_asc = ASC_MEDIUM_NOT_PRESENT;
zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_write_protected(zip_t *dev)
{
zip_sense_key = SENSE_UNIT_ATTENTION;
zip_asc = ASC_WRITE_PROTECTED;
zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_invalid_lun(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_INV_LUN;
zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_illegal_opcode(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_ILLEGAL_OPCODE;
zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_lba_out_of_range(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_LBA_OUT_OF_RANGE;
zip_ascq = 0;
zip_cmd_error(dev);
}
static void
zip_invalid_field(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_INV_FIELD_IN_CMD_PACKET;
zip_ascq = 0;
zip_cmd_error(dev);
dev->tf->status = 0x53;
}
static void
zip_invalid_field_pl(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_INV_FIELD_IN_PARAMETER_LIST;
zip_ascq = 0;
zip_cmd_error(dev);
dev->tf->status = 0x53;
}
static void
zip_data_phase_error(zip_t *dev)
{
zip_sense_key = SENSE_ILLEGAL_REQUEST;
zip_asc = ASC_DATA_PHASE_ERROR;
zip_ascq = 0;
zip_cmd_error(dev);
}
static int
zip_blocks(zip_t *dev, int32_t *len, UNUSED(int first_batch), int out)
{
*len = 0;
if (!dev->sector_len) {
zip_command_complete(dev);
return -1;
}
zip_log("%sing %i blocks starting from %i...\n", out ? "Writ" : "Read", dev->requested_blocks, dev->sector_pos);
if (dev->sector_pos >= dev->drv->medium_size) {
zip_log("ZIP %i: Trying to %s beyond the end of disk\n", dev->id, out ? "write" : "read");
zip_lba_out_of_range(dev);
return 0;
}
*len = dev->requested_blocks << 9;
for (int i = 0; i < dev->requested_blocks; i++) {
if (fseek(dev->drv->fp, dev->drv->base + (dev->sector_pos << 9) + (i << 9), SEEK_SET) == 1)
break;
if (feof(dev->drv->fp))
break;
if (out) {
if (fwrite(dev->buffer + (i << 9), 1, 512, dev->drv->fp) != 512)
fatal("zip_blocks(): Error writing data\n");
} else {
if (fread(dev->buffer + (i << 9), 1, 512, dev->drv->fp) != 512)
fatal("zip_blocks(): Error reading data\n");
}
}
zip_log("%s %i bytes of blocks...\n", out ? "Written" : "Read", *len);
dev->sector_pos += dev->requested_blocks;
dev->sector_len -= dev->requested_blocks;
return 1;
}
void
zip_insert(zip_t *dev)
{
dev->unit_attention = 1;
}
/*SCSI Sense Initialization*/
void
zip_sense_code_ok(zip_t *dev)
{
zip_sense_key = SENSE_NONE;
zip_asc = 0;
zip_ascq = 0;
}
static int
zip_pre_execution_check(zip_t *dev, uint8_t *cdb)
{
int ready = 0;
if ((cdb[0] != GPCMD_REQUEST_SENSE) && (dev->cur_lun == SCSI_LUN_USE_CDB) && (cdb[1] & 0xe0)) {
zip_log("ZIP %i: Attempting to execute a unknown command targeted at SCSI LUN %i\n", dev->id,
((dev->tf->request_length >> 5) & 7));
zip_invalid_lun(dev);
return 0;
}
if (!(zip_command_flags[cdb[0]] & IMPLEMENTED)) {
zip_log("ZIP %i: Attempting to execute unknown command %02X over %s\n", dev->id, cdb[0],
(dev->drv->bus_type == ZIP_BUS_SCSI) ? "SCSI" : "ATAPI");
zip_illegal_opcode(dev);
return 0;
}
if ((dev->drv->bus_type < ZIP_BUS_SCSI) && (zip_command_flags[cdb[0]] & SCSI_ONLY)) {
zip_log("ZIP %i: Attempting to execute SCSI-only command %02X over ATAPI\n", dev->id, cdb[0]);
zip_illegal_opcode(dev);
return 0;
}
if ((dev->drv->bus_type == ZIP_BUS_SCSI) && (zip_command_flags[cdb[0]] & ATAPI_ONLY)) {
zip_log("ZIP %i: Attempting to execute ATAPI-only command %02X over SCSI\n", dev->id, cdb[0]);
zip_illegal_opcode(dev);
return 0;
}
ready = (dev->drv->fp != NULL);
/* If the drive is not ready, there is no reason to keep the
UNIT ATTENTION condition present, as we only use it to mark
disc changes. */
if (!ready && dev->unit_attention)
dev->unit_attention = 0;
/* If the UNIT ATTENTION condition is set and the command does not allow
execution under it, error out and report the condition. */
if (dev->unit_attention == 1) {
/* Only increment the unit attention phase if the command can not pass through it. */
if (!(zip_command_flags[cdb[0]] & ALLOW_UA)) {
/* zip_log("ZIP %i: Unit attention now 2\n", dev->id); */
dev->unit_attention = 2;
zip_log("ZIP %i: UNIT ATTENTION: Command %02X not allowed to pass through\n", dev->id, cdb[0]);
zip_unit_attention(dev);
return 0;
}
} else if (dev->unit_attention == 2) {
if (cdb[0] != GPCMD_REQUEST_SENSE) {
/* zip_log("ZIP %i: Unit attention now 0\n", dev->id); */
dev->unit_attention = 0;
}
}
/* Unless the command is REQUEST SENSE, clear the sense. This will *NOT*
the UNIT ATTENTION condition if it's set. */
if (cdb[0] != GPCMD_REQUEST_SENSE)
zip_sense_clear(dev, cdb[0]);
/* Next it's time for NOT READY. */
if ((zip_command_flags[cdb[0]] & CHECK_READY) && !ready) {
zip_log("ZIP %i: Not ready (%02X)\n", dev->id, cdb[0]);
zip_not_ready(dev);
return 0;
}
zip_log("ZIP %i: Continuing with command %02X\n", dev->id, cdb[0]);
return 1;
}
static void
zip_seek(zip_t *dev, uint32_t pos)
{
#if 0
zip_log("ZIP %i: Seek %08X\n", dev->id, pos);
#endif
dev->sector_pos = pos;
}
static void
zip_rezero(zip_t *dev)
{
dev->sector_pos = dev->sector_len = 0;
zip_seek(dev, 0);
}
void
zip_reset(scsi_common_t *sc)
{
zip_t *dev = (zip_t *) sc;
zip_rezero(dev);
dev->tf->status = 0;
dev->callback = 0.0;
zip_set_callback(dev);
dev->tf->phase = 1;
dev->tf->request_length = 0xEB14;
dev->packet_status = PHASE_NONE;
dev->unit_attention = 0;
dev->cur_lun = SCSI_LUN_USE_CDB;
}
static void
zip_request_sense(zip_t *dev, uint8_t *buffer, uint8_t alloc_length, int desc)
{
/*Will return 18 bytes of 0*/
if (alloc_length != 0) {
memset(buffer, 0, alloc_length);
if (!desc)
memcpy(buffer, dev->sense, alloc_length);
else {
buffer[1] = zip_sense_key;
buffer[2] = zip_asc;
buffer[3] = zip_ascq;
}
}
buffer[0] = desc ? 0x72 : 0x70;
if (dev->unit_attention && (zip_sense_key == 0)) {
buffer[desc ? 1 : 2] = SENSE_UNIT_ATTENTION;
buffer[desc ? 2 : 12] = ASC_MEDIUM_MAY_HAVE_CHANGED;
buffer[desc ? 3 : 13] = 0;
}
zip_log("ZIP %i: Reporting sense: %02X %02X %02X\n", dev->id, buffer[2], buffer[12], buffer[13]);
if (buffer[desc ? 1 : 2] == SENSE_UNIT_ATTENTION) {
/* If the last remaining sense is unit attention, clear
that condition. */
dev->unit_attention = 0;
}
/* Clear the sense stuff as per the spec. */
zip_sense_clear(dev, GPCMD_REQUEST_SENSE);
}
static void
zip_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t alloc_length)
{
zip_t *dev = (zip_t *) sc;
int ready = 0;
ready = (dev->drv->fp != NULL);
if (!ready && dev->unit_attention) {
/* If the drive is not ready, there is no reason to keep the
UNIT ATTENTION condition present, as we only use it to mark
disc changes. */
dev->unit_attention = 0;
}
/* Do *NOT* advance the unit attention phase. */
zip_request_sense(dev, buffer, alloc_length, 0);
}
static void
zip_set_buf_len(zip_t *dev, int32_t *BufLen, int32_t *src_len)
{
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
if (*BufLen == -1)
*BufLen = *src_len;
else {
*BufLen = MIN(*src_len, *BufLen);
*src_len = *BufLen;
}
zip_log("ZIP %i: Actual transfer length: %i\n", dev->id, *BufLen);
}
}
static void
zip_command(scsi_common_t *sc, uint8_t *cdb)
{
zip_t *dev = (zip_t *) sc;
int pos = 0;
int block_desc = 0;
int ret;
int32_t len;
int32_t max_len;
int32_t alloc_length;
uint32_t i = 0;
int size_idx;
int idx = 0;
unsigned preamble_len;
int32_t blen = 0;
int32_t *BufLen;
uint8_t scsi_bus = (dev->drv->scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_device_id & 0x0f;
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
BufLen = &scsi_devices[scsi_bus][scsi_id].buffer_length;
dev->tf->status &= ~ERR_STAT;
} else {
BufLen = &blen;
dev->tf->error = 0;
}
dev->packet_len = 0;
dev->request_pos = 0;
memcpy(dev->current_cdb, cdb, 12);
if (cdb[0] != 0) {
zip_log("ZIP %i: Command 0x%02X, Sense Key %02X, Asc %02X, Ascq %02X, Unit attention: %i\n",
dev->id, cdb[0], zip_sense_key, zip_asc, zip_ascq, dev->unit_attention);
zip_log("ZIP %i: Request length: %04X\n", dev->id, dev->tf->request_length);
zip_log("ZIP %i: CDB: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", dev->id,
cdb[0], cdb[1], cdb[2], cdb[3], cdb[4], cdb[5], cdb[6], cdb[7],
cdb[8], cdb[9], cdb[10], cdb[11]);
}
dev->sector_len = 0;
zip_set_phase(dev, SCSI_PHASE_STATUS);
/* This handles the Not Ready/Unit Attention check if it has to be handled at this point. */
if (zip_pre_execution_check(dev, cdb) == 0)
return;
switch (cdb[0]) {
case GPCMD_SEND_DIAGNOSTIC:
if (!(cdb[1] & (1 << 2))) {
zip_invalid_field(dev);
return;
}
fallthrough;
case GPCMD_SCSI_RESERVE:
case GPCMD_SCSI_RELEASE:
case GPCMD_TEST_UNIT_READY:
zip_set_phase(dev, SCSI_PHASE_STATUS);
zip_command_complete(dev);
break;
case GPCMD_FORMAT_UNIT:
if (dev->drv->read_only) {
zip_write_protected(dev);
return;
}
zip_set_phase(dev, SCSI_PHASE_STATUS);
zip_command_complete(dev);
break;
case GPCMD_IOMEGA_SENSE:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[4];
zip_buf_alloc(dev, 256);
zip_set_buf_len(dev, BufLen, &max_len);
memset(dev->buffer, 0, 256);
if (cdb[2] == 1) {
/* This page is related to disk health status - setting
this page to 0 makes disk health read as "marginal". */
dev->buffer[0] = 0x58;
dev->buffer[1] = 0x00;
for (i = 0x00; i < 0x58; i++)
dev->buffer[i + 0x02] = 0xff;
} else if (cdb[2] == 2) {
dev->buffer[0] = 0x3d;
dev->buffer[1] = 0x00;
for (i = 0x00; i < 0x13; i++)
dev->buffer[i + 0x02] = 0x00;
dev->buffer[0x15] = 0x00;
if (dev->drv->read_only)
dev->buffer[0x15] |= 0x02;
for (i = 0x00; i < 0x27; i++)
dev->buffer[i + 0x16] = 0x00;
} else {
zip_invalid_field(dev);
zip_buf_free(dev);
return;
}
zip_data_command_finish(dev, 18, 18, cdb[4], 0);
break;
case GPCMD_REZERO_UNIT:
dev->sector_pos = dev->sector_len = 0;
zip_seek(dev, 0);
zip_set_phase(dev, SCSI_PHASE_STATUS);
break;
case GPCMD_REQUEST_SENSE:
/* If there's a unit attention condition and there's a buffered not
ready, a standalone REQUEST SENSE should forget about the not
ready, and report unit attention straight away. */
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[4];
if (!max_len) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * ZIP_TIME;
zip_set_callback(dev);
break;
}
zip_buf_alloc(dev, 256);
zip_set_buf_len(dev, BufLen, &max_len);
len = (cdb[1] & 1) ? 8 : 18;
zip_request_sense(dev, dev->buffer, max_len, cdb[1] & 1);
zip_data_command_finish(dev, len, len, cdb[4], 0);
break;
case GPCMD_MECHANISM_STATUS:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
len = (cdb[8] << 8) | cdb[9];
zip_buf_alloc(dev, 8);
zip_set_buf_len(dev, BufLen, &len);
memset(dev->buffer, 0, 8);
dev->buffer[5] = 1;
zip_data_command_finish(dev, 8, 8, len, 0);
break;
case GPCMD_READ_6:
case GPCMD_READ_10:
case GPCMD_READ_12:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
alloc_length = 512;
switch (cdb[0]) {
case GPCMD_READ_6:
dev->sector_len = cdb[4];
/*
For READ (6) and WRITE (6), a length of 0 indicates a
transfer of 256 sectors.
*/
if (dev->sector_len == 0)
dev->sector_len = 256;
dev->sector_pos = ((((uint32_t) cdb[1]) & 0x1f) << 16) |
(((uint32_t) cdb[2]) << 8) | ((uint32_t) cdb[3]);
zip_log("ZIP %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_READ_10:
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
zip_log("ZIP %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_READ_12:
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) |
(((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) |
(((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
if (dev->sector_pos >= dev->drv->medium_size) {
zip_lba_out_of_range(dev);
return;
}
if (!dev->sector_len) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
/* zip_log("ZIP %i: All done - callback set\n", dev->id); */
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * ZIP_TIME;
zip_set_callback(dev);
break;
}
max_len = dev->sector_len;
/*
If we're reading all blocks in one go for DMA, why not also for
PIO, it should NOT matter anyway, this step should be identical
and only the way the read dat is transferred to the host should
be different.
*/
dev->requested_blocks = max_len;
dev->packet_len = max_len * alloc_length;
zip_buf_alloc(dev, dev->packet_len);
ret = zip_blocks(dev, &alloc_length, 1, 0);
if (ret <= 0) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * ZIP_TIME;
zip_set_callback(dev);
zip_buf_free(dev);
return;
}
dev->requested_blocks = max_len;
dev->packet_len = alloc_length;
zip_set_buf_len(dev, BufLen, (int32_t *) &dev->packet_len);
zip_data_command_finish(dev, alloc_length, 512, alloc_length, 0);
ui_sb_update_icon(SB_ZIP | dev->id, dev->packet_status != PHASE_COMPLETE);
return;
case GPCMD_VERIFY_6:
case GPCMD_VERIFY_10:
case GPCMD_VERIFY_12:
if (!(cdb[1] & 2)) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
zip_command_complete(dev);
break;
}
fallthrough;
case GPCMD_WRITE_6:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
zip_set_phase(dev, SCSI_PHASE_DATA_OUT);
alloc_length = 512;
if (dev->drv->read_only) {
zip_write_protected(dev);
return;
}
switch (cdb[0]) {
case GPCMD_VERIFY_6:
case GPCMD_WRITE_6:
dev->sector_len = cdb[4];
/*
For READ (6) and WRITE (6), a length of 0 indicates a
transfer of 256 sectors.
*/
if (dev->sector_len == 0)
dev->sector_len = 256;
dev->sector_pos = ((((uint32_t) cdb[1]) & 0x1f) << 16) |
(((uint32_t) cdb[2]) << 8) | ((uint32_t) cdb[3]);
break;
case GPCMD_VERIFY_10:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
zip_log("ZIP %i: Length: %i, LBA: %i\n", dev->id, dev->sector_len, dev->sector_pos);
break;
case GPCMD_VERIFY_12:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) |
(((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) |
(((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
if (dev->sector_pos >= dev->drv->medium_size) {
zip_lba_out_of_range(dev);
return;
}
if (!dev->sector_len) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
/* zip_log("ZIP %i: All done - callback set\n", dev->id); */
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * ZIP_TIME;
zip_set_callback(dev);
break;
}
max_len = dev->sector_len;
/*
If we're writing all blocks in one go for DMA, why not also for
PIO, it should NOT matter anyway, this step should be identical
and only the way the read dat is transferred to the host should
be different.
*/
dev->requested_blocks = max_len;
dev->packet_len = max_len * alloc_length;
zip_buf_alloc(dev, dev->packet_len);
dev->requested_blocks = max_len;
dev->packet_len = max_len << 9;
zip_set_buf_len(dev, BufLen, (int32_t *) &dev->packet_len);
zip_data_command_finish(dev, dev->packet_len, 512, dev->packet_len, 1);
ui_sb_update_icon(SB_ZIP | dev->id, dev->packet_status != PHASE_COMPLETE);
return;
case GPCMD_WRITE_SAME_10:
alloc_length = 512;
if ((cdb[1] & 6) == 6) {
zip_invalid_field(dev);
return;
}
if (dev->drv->read_only) {
zip_write_protected(dev);
return;
}
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
if (dev->sector_pos >= dev->drv->medium_size) {
zip_lba_out_of_range(dev);
return;
}
if (!dev->sector_len) {
zip_set_phase(dev, SCSI_PHASE_STATUS);
/* zip_log("ZIP %i: All done - callback set\n", dev->id); */
dev->packet_status = PHASE_COMPLETE;
dev->callback = 20.0 * ZIP_TIME;
zip_set_callback(dev);
break;
}
zip_buf_alloc(dev, alloc_length);
zip_set_buf_len(dev, BufLen, (int32_t *) &dev->packet_len);
max_len = 1;
dev->requested_blocks = 1;
dev->packet_len = alloc_length;
zip_set_phase(dev, SCSI_PHASE_DATA_OUT);
zip_data_command_finish(dev, 512, 512, alloc_length, 1);
ui_sb_update_icon(SB_ZIP | dev->id, dev->packet_status != PHASE_COMPLETE);
return;
case GPCMD_MODE_SENSE_6:
case GPCMD_MODE_SENSE_10:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
if (dev->drv->bus_type == ZIP_BUS_SCSI)
block_desc = ((cdb[1] >> 3) & 1) ? 0 : 1;
else
block_desc = 0;
if (cdb[0] == GPCMD_MODE_SENSE_6) {
len = cdb[4];
zip_buf_alloc(dev, 256);
} else {
len = (cdb[8] | (cdb[7] << 8));
zip_buf_alloc(dev, 65536);
}
if (!(zip_mode_sense_page_flags & (1LL << (uint64_t) (cdb[2] & 0x3f)))) {
zip_invalid_field(dev);
zip_buf_free(dev);
return;
}
memset(dev->buffer, 0, len);
alloc_length = len;
if (cdb[0] == GPCMD_MODE_SENSE_6) {
len = zip_mode_sense(dev, dev->buffer, 4, cdb[2], block_desc);
len = MIN(len, alloc_length);
dev->buffer[0] = len - 1;
dev->buffer[1] = 0;
if (block_desc)
dev->buffer[3] = 8;
} else {
len = zip_mode_sense(dev, dev->buffer, 8, cdb[2], block_desc);
len = MIN(len, alloc_length);
dev->buffer[0] = (len - 2) >> 8;
dev->buffer[1] = (len - 2) & 255;
dev->buffer[2] = 0;
if (block_desc) {
dev->buffer[6] = 0;
dev->buffer[7] = 8;
}
}
zip_set_buf_len(dev, BufLen, &len);
zip_log("ZIP %i: Reading mode page: %02X...\n", dev->id, cdb[2]);
zip_data_command_finish(dev, len, len, alloc_length, 0);
return;
case GPCMD_MODE_SELECT_6:
case GPCMD_MODE_SELECT_10:
zip_set_phase(dev, SCSI_PHASE_DATA_OUT);
if (cdb[0] == GPCMD_MODE_SELECT_6) {
len = cdb[4];
zip_buf_alloc(dev, 256);
} else {
len = (cdb[7] << 8) | cdb[8];
zip_buf_alloc(dev, 65536);
}
zip_set_buf_len(dev, BufLen, &len);
dev->total_length = len;
dev->do_page_save = cdb[1] & 1;
zip_data_command_finish(dev, len, len, len, 1);
return;
case GPCMD_START_STOP_UNIT:
zip_set_phase(dev, SCSI_PHASE_STATUS);
switch (cdb[4] & 3) {
case 0: /* Stop the disc. */
zip_eject(dev->id); /* The Iomega Windows 9x drivers require this. */
break;
case 1: /* Start the disc and read the TOC. */
break;
case 2: /* Eject the disc if possible. */
#if 0
zip_eject(dev->id);
#endif
break;
case 3: /* Load the disc (close tray). */
zip_reload(dev->id);
break;
default:
break;
}
zip_command_complete(dev);
break;
case GPCMD_INQUIRY:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
max_len = cdb[3];
max_len <<= 8;
max_len |= cdb[4];
zip_buf_alloc(dev, 65536);
if (cdb[1] & 1) {
preamble_len = 4;
size_idx = 3;
dev->buffer[idx++] = 0;
dev->buffer[idx++] = cdb[2];
dev->buffer[idx++] = 0;
idx++;
switch (cdb[2]) {
case 0x00:
dev->buffer[idx++] = 0x00;
dev->buffer[idx++] = 0x83;
break;
case 0x83:
if (idx + 24 > max_len) {
zip_data_phase_error(dev);
zip_buf_free(dev);
return;
}
dev->buffer[idx++] = 0x02;
dev->buffer[idx++] = 0x00;
dev->buffer[idx++] = 0x00;
dev->buffer[idx++] = 20;
ide_padstr8(dev->buffer + idx, 20, "53R141"); /* Serial */
idx += 20;
if (idx + 72 > cdb[4])
goto atapi_out;
dev->buffer[idx++] = 0x02;
dev->buffer[idx++] = 0x01;
dev->buffer[idx++] = 0x00;
dev->buffer[idx++] = 68;
ide_padstr8(dev->buffer + idx, 8, "IOMEGA "); /* Vendor */
idx += 8;
if (dev->drv->is_250)
ide_padstr8(dev->buffer + idx, 40, "ZIP 250 "); /* Product */
else
ide_padstr8(dev->buffer + idx, 40, "ZIP 100 "); /* Product */
idx += 40;
ide_padstr8(dev->buffer + idx, 20, "53R141"); /* Product */
idx += 20;
break;
default:
zip_log("INQUIRY: Invalid page: %02X\n", cdb[2]);
zip_invalid_field(dev);
zip_buf_free(dev);
return;
}
} else {
preamble_len = 5;
size_idx = 4;
memset(dev->buffer, 0, 8);
if ((cdb[1] & 0xe0) || ((dev->cur_lun > 0x00) && (dev->cur_lun < 0xff)))
dev->buffer[0] = 0x7f; /*No physical device on this LUN*/
else
dev->buffer[0] = 0x00; /*Hard disk*/
dev->buffer[1] = 0x80; /*Removable*/
dev->buffer[2] = (dev->drv->bus_type == ZIP_BUS_SCSI) ? 0x02 : 0x00; /*SCSI-2 compliant*/
dev->buffer[3] = (dev->drv->bus_type == ZIP_BUS_SCSI) ? 0x02 : 0x21;
#if 0
dev->buffer[4] = 31;
#endif
dev->buffer[4] = 0;
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
dev->buffer[6] = 1; /* 16-bit transfers supported */
dev->buffer[7] = 0x20; /* Wide bus supported */
}
dev->buffer[7] |= 0x02;
ide_padstr8(dev->buffer + 8, 8, "IOMEGA "); /* Vendor */
if (dev->drv->is_250) {
ide_padstr8(dev->buffer + 16, 16, "ZIP 250 "); /* Product */
ide_padstr8(dev->buffer + 32, 4, "42.S"); /* Revision */
if (max_len >= 44)
ide_padstr8(dev->buffer + 36, 8, "08/08/01"); /* Date? */
if (max_len >= 122)
} else {
ide_padstr8(dev->buffer + 16, 16, "ZIP 100 "); /* Product */
ide_padstr8(dev->buffer + 32, 4, "E.08"); /* Revision */
}
idx = 36;
if (max_len == 96) {
dev->buffer[4] = 91;
idx = 96;
} else if (max_len == 128) {
dev->buffer[4] = 0x75;
idx = 128;
}
}
atapi_out:
dev->buffer[size_idx] = idx - preamble_len;
len = idx;
len = MIN(len, max_len);
zip_set_buf_len(dev, BufLen, &len);
zip_data_command_finish(dev, len, len, max_len, 0);
break;
case GPCMD_PREVENT_REMOVAL:
zip_set_phase(dev, SCSI_PHASE_STATUS);
zip_command_complete(dev);
break;
case GPCMD_SEEK_6:
case GPCMD_SEEK_10:
zip_set_phase(dev, SCSI_PHASE_STATUS);
switch (cdb[0]) {
case GPCMD_SEEK_6:
pos = (cdb[2] << 8) | cdb[3];
break;
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
default:
break;
}
zip_seek(dev, pos);
zip_command_complete(dev);
break;
case GPCMD_READ_CDROM_CAPACITY:
zip_set_phase(dev, SCSI_PHASE_DATA_IN);
zip_buf_alloc(dev, 8);
max_len = dev->drv->medium_size - 1; /* IMPORTANT: What's returned is the last LBA block. */
memset(dev->buffer, 0, 8);
dev->buffer[0] = (max_len >> 24) & 0xff;
dev->buffer[1] = (max_len >> 16) & 0xff;
dev->buffer[2] = (max_len >> 8) & 0xff;
dev->buffer[3] = max_len & 0xff;
dev->buffer[6] = 2; /* 512 = 0x0200 */
len = 8;
zip_set_buf_len(dev, BufLen, &len);
zip_data_command_finish(dev, len, len, len, 0);
break;
case GPCMD_IOMEGA_EJECT:
zip_set_phase(dev, SCSI_PHASE_STATUS);
zip_eject(dev->id);
zip_command_complete(dev);
break;
case GPCMD_READ_FORMAT_CAPACITIES:
len = (cdb[7] << 8) | cdb[8];
zip_buf_alloc(dev, len);
memset(dev->buffer, 0, len);
pos = 0;
/* List header */
dev->buffer[pos++] = 0;
dev->buffer[pos++] = 0;
dev->buffer[pos++] = 0;
if (dev->drv->fp != NULL)
dev->buffer[pos++] = 16;
else
dev->buffer[pos++] = 8;
/* Current/Maximum capacity header */
if (dev->drv->is_250) {
/* ZIP 250 also supports ZIP 100 media, so if the medium is inserted,
we return the inserted medium's size, otherwise, the ZIP 250 size. */
if (dev->drv->fp != NULL) {
dev->buffer[pos++] = (dev->drv->medium_size >> 24) & 0xff;
dev->buffer[pos++] = (dev->drv->medium_size >> 16) & 0xff;
dev->buffer[pos++] = (dev->drv->medium_size >> 8) & 0xff;
dev->buffer[pos++] = dev->drv->medium_size & 0xff;
dev->buffer[pos++] = 2; /* Current medium capacity */
} else {
dev->buffer[pos++] = (ZIP_250_SECTORS >> 24) & 0xff;
dev->buffer[pos++] = (ZIP_250_SECTORS >> 16) & 0xff;
dev->buffer[pos++] = (ZIP_250_SECTORS >> 8) & 0xff;
dev->buffer[pos++] = ZIP_250_SECTORS & 0xff;
dev->buffer[pos++] = 3; /* Maximum medium capacity */
}
} else {
/* ZIP 100 only supports ZIP 100 media as well, so we always return
the ZIP 100 size. */
dev->buffer[pos++] = (ZIP_SECTORS >> 24) & 0xff;
dev->buffer[pos++] = (ZIP_SECTORS >> 16) & 0xff;
dev->buffer[pos++] = (ZIP_SECTORS >> 8) & 0xff;
dev->buffer[pos++] = ZIP_SECTORS & 0xff;
if (dev->drv->fp != NULL)
dev->buffer[pos++] = 2;
else
dev->buffer[pos++] = 3;
}
dev->buffer[pos++] = 512 >> 16;
dev->buffer[pos++] = 512 >> 8;
dev->buffer[pos++] = 512 & 0xff;
if (dev->drv->fp != NULL) {
/* Formattable capacity descriptor */
dev->buffer[pos++] = (dev->drv->medium_size >> 24) & 0xff;
dev->buffer[pos++] = (dev->drv->medium_size >> 16) & 0xff;
dev->buffer[pos++] = (dev->drv->medium_size >> 8) & 0xff;
dev->buffer[pos++] = dev->drv->medium_size & 0xff;
dev->buffer[pos++] = 0;
dev->buffer[pos++] = 512 >> 16;
dev->buffer[pos++] = 512 >> 8;
dev->buffer[pos++] = 512 & 0xff;
}
zip_set_buf_len(dev, BufLen, &len);
zip_data_command_finish(dev, len, len, len, 0);
break;
default:
zip_illegal_opcode(dev);
break;
}
#if 0
zip_log("ZIP %i: Phase: %02X, request length: %i\n", dev->id, dev->tf->phase, dev->tf->request_length);
#endif
if ((dev->packet_status == PHASE_COMPLETE) || (dev->packet_status == PHASE_ERROR))
zip_buf_free(dev);
}
static void
zip_command_stop(scsi_common_t *sc)
{
zip_t *dev = (zip_t *) sc;
zip_command_complete(dev);
zip_buf_free(dev);
}
/* The command second phase function, needed for Mode Select. */
static uint8_t
zip_phase_data_out(scsi_common_t *sc)
{
zip_t *dev = (zip_t *) sc;
uint16_t block_desc_len;
uint16_t pos;
uint16_t param_list_len;
uint8_t error = 0;
uint8_t page;
uint8_t page_len;
uint32_t i = 0;
uint8_t hdr_len;
uint8_t val;
uint8_t old_val;
uint8_t ch;
uint32_t last_to_write = 0;
uint32_t c;
uint32_t h;
uint32_t s;
int len = 0;
switch (dev->current_cdb[0]) {
case GPCMD_VERIFY_6:
case GPCMD_VERIFY_10:
case GPCMD_VERIFY_12:
break;
case GPCMD_WRITE_6:
case GPCMD_WRITE_10:
case GPCMD_WRITE_AND_VERIFY_10:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
if (dev->requested_blocks > 0)
zip_blocks(dev, &len, 1, 1);
break;
case GPCMD_WRITE_SAME_10:
if (!dev->current_cdb[7] && !dev->current_cdb[8]) {
last_to_write = (dev->drv->medium_size - 1);
} else
last_to_write = dev->sector_pos + dev->sector_len - 1;
for (i = dev->sector_pos; i <= last_to_write; i++) {
if (dev->current_cdb[1] & 2) {
dev->buffer[0] = (i >> 24) & 0xff;
dev->buffer[1] = (i >> 16) & 0xff;
dev->buffer[2] = (i >> 8) & 0xff;
dev->buffer[3] = i & 0xff;
} else if (dev->current_cdb[1] & 4) {
/* CHS are 96, 1, 2048 (ZIP 100) and 239, 1, 2048 (ZIP 250) */
s = (i % 2048);
h = ((i - s) / 2048) % 1;
c = ((i - s) / 2048) / 1;
dev->buffer[0] = (c >> 16) & 0xff;
dev->buffer[1] = (c >> 8) & 0xff;
dev->buffer[2] = c & 0xff;
dev->buffer[3] = h & 0xff;
dev->buffer[4] = (s >> 24) & 0xff;
dev->buffer[5] = (s >> 16) & 0xff;
dev->buffer[6] = (s >> 8) & 0xff;
dev->buffer[7] = s & 0xff;
}
if (fseek(dev->drv->fp, dev->drv->base + (i << 9), SEEK_SET) == -1)
fatal("zip_phase_data_out(): Error seeking\n");
if (fwrite(dev->buffer, 1, 512, dev->drv->fp) != 512)
fatal("zip_phase_data_out(): Error writing data\n");
}
break;
case GPCMD_MODE_SELECT_6:
case GPCMD_MODE_SELECT_10:
if (dev->current_cdb[0] == GPCMD_MODE_SELECT_10) {
hdr_len = 8;
param_list_len = dev->current_cdb[7];
param_list_len <<= 8;
param_list_len |= dev->current_cdb[8];
} else {
hdr_len = 4;
param_list_len = dev->current_cdb[4];
}
if (dev->drv->bus_type == ZIP_BUS_SCSI) {
if (dev->current_cdb[0] == GPCMD_MODE_SELECT_6) {
block_desc_len = dev->buffer[2];
block_desc_len <<= 8;
block_desc_len |= dev->buffer[3];
} else {
block_desc_len = dev->buffer[6];
block_desc_len <<= 8;
block_desc_len |= dev->buffer[7];
}
} else
block_desc_len = 0;
pos = hdr_len + block_desc_len;
while (1) {
if (pos >= param_list_len) {
zip_log("ZIP %i: Buffer has only block descriptor\n", dev->id);
break;
}
page = dev->buffer[pos] & 0x3F;
page_len = dev->buffer[pos + 1];
pos += 2;
if (!(zip_mode_sense_page_flags & (1LL << ((uint64_t) page))))
error |= 1;
else {
for (i = 0; i < page_len; i++) {
ch = zip_mode_sense_pages_changeable.pages[page][i + 2];
val = dev->buffer[pos + i];
old_val = dev->ms_pages_saved.pages[page][i + 2];
if (val != old_val) {
if (ch)
dev->ms_pages_saved.pages[page][i + 2] = val;
else
error |= 1;
}
}
}
pos += page_len;
if (dev->drv->bus_type == ZIP_BUS_SCSI)
val = zip_mode_sense_pages_default_scsi.pages[page][0] & 0x80;
else
val = zip_mode_sense_pages_default.pages[page][0] & 0x80;
if (dev->do_page_save && val)
zip_mode_sense_save(dev);
if (pos >= dev->total_length)
break;
}
if (error) {
zip_buf_free(dev);
zip_invalid_field_pl(dev);
return 0;
}
break;
default:
break;
}
zip_command_stop((scsi_common_t *) dev);
return 1;
}
/* Peform a master init on the entire module. */
void
zip_global_init(void)
{
/* Clear the global data. */
memset(zip_drives, 0x00, sizeof(zip_drives));
}
static int
zip_get_max(int ide_has_dma, int type)
{
int ret;
switch (type) {
case TYPE_PIO:
ret = ide_has_dma ? 3 : 0;
break;
case TYPE_SDMA:
default:
ret = -1;
break;
case TYPE_MDMA:
ret = ide_has_dma ? 1 : -1;
break;
case TYPE_UDMA:
ret = ide_has_dma ? 5 : -1;
break;
}
return ret;
}
static int
zip_get_timings(int ide_has_dma, int type)
{
int ret;
switch (type) {
case TIMINGS_DMA:
ret = ide_has_dma ? 0x96 : 0;
break;
case TIMINGS_PIO:
ret = ide_has_dma ? 0xb4 : 0;
break;
case TIMINGS_PIO_FC:
ret = ide_has_dma ? 0xb4 : 0;
break;
default:
ret = 0;
break;
}
return ret;
}
static void
zip_100_identify(ide_t *ide)
{
ide_padstr((char *) (ide->buffer + 23), "E.08", 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), "IOMEGA ZIP 100 ATAPI", 40); /* Model */
}
static void
zip_250_identify(ide_t *ide, int ide_has_dma)
{
ide_padstr((char *) (ide->buffer + 23), "42.S", 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), "IOMEGA ZIP 250 ATAPI", 40); /* Model */
if (ide_has_dma) {
ide->buffer[80] = 0x70; /*Supported ATA versions : ATA/ATAPI-4 ATA/ATAPI-6*/
ide->buffer[81] = 0x19; /*Maximum ATA revision supported : ATA/ATAPI-6 T13 1410D revision 3a*/
}
}
static void
zip_identify(ide_t *ide, int ide_has_dma)
{
const zip_t *zip;
zip = (zip_t *) ide->sc;
/* ATAPI device, direct-access device, removable media, interrupt DRQ:
Using (2 << 5) below makes the ASUS P/I-P54TP4XE misdentify the ZIP drive
as a LS-120. */
ide->buffer[0] = 0x8000 | (0 << 8) | 0x80 | (1 << 5);
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
ide->buffer[49] = 0x200; /* LBA supported */
ide->buffer[126] = 0xfffe; /* Interpret zero byte count limit as maximum length */
if (zip_drives[zip->id].is_250)
zip_250_identify(ide, ide_has_dma);
else
zip_100_identify(ide);
}
static void
zip_drive_reset(int c)
{
zip_t *dev;
scsi_device_t *sd;
ide_t *id;
uint8_t scsi_bus = (zip_drives[c].scsi_device_id >> 4) & 0x0f;
uint8_t scsi_id = zip_drives[c].scsi_device_id & 0x0f;
if (!zip_drives[c].priv) {
zip_drives[c].priv = (zip_t *) malloc(sizeof(zip_t));
memset(zip_drives[c].priv, 0, sizeof(zip_t));
}
dev = (zip_t *) zip_drives[c].priv;
dev->id = c;
dev->cur_lun = SCSI_LUN_USE_CDB;
if (zip_drives[c].bus_type == ZIP_BUS_SCSI) {
if (!dev->tf)
dev->tf = (ide_tf_t *) calloc(1, sizeof(ide_tf_t));
/* SCSI ZIP, attach to the SCSI bus. */
sd = &scsi_devices[scsi_bus][scsi_id];
sd->sc = (scsi_common_t *) dev;
sd->command = zip_command;
sd->request_sense = zip_request_sense_for_scsi;
sd->reset = zip_reset;
sd->phase_data_out = zip_phase_data_out;
sd->command_stop = zip_command_stop;
sd->type = SCSI_REMOVABLE_DISK;
} else if (zip_drives[c].bus_type == ZIP_BUS_ATAPI) {
/* ATAPI CD-ROM, attach to the IDE bus. */
id = ide_get_drive(zip_drives[c].ide_channel);
/* If the IDE channel is initialized, we attach to it,
otherwise, we do nothing - it's going to be a drive
that's not attached to anything. */
if (id) {
id->sc = (scsi_common_t *) dev;
dev->tf = id->tf;
IDE_ATAPI_IS_EARLY = 0;
id->get_max = zip_get_max;
id->get_timings = zip_get_timings;
id->identify = zip_identify;
id->stop = NULL;
id->packet_command = zip_command;
id->device_reset = zip_reset;
id->phase_data_out = zip_phase_data_out;
id->command_stop = zip_command_stop;
id->bus_master_error = zip_bus_master_error;
id->interrupt_drq = 1;
ide_atapi_attach(id);
}
}
}
void
zip_hard_reset(void)
{
zip_t *dev;
uint8_t scsi_id;
uint8_t scsi_bus;
for (uint8_t c = 0; c < ZIP_NUM; c++) {
if ((zip_drives[c].bus_type == ZIP_BUS_ATAPI) || (zip_drives[c].bus_type == ZIP_BUS_SCSI)) {
zip_log("ZIP hard_reset drive=%d\n", c);
if (zip_drives[c].bus_type == ZIP_BUS_SCSI) {
scsi_bus = (zip_drives[c].scsi_device_id >> 4) & 0x0f;
scsi_id = zip_drives[c].scsi_device_id & 0x0f;
/* Make sure to ignore any SCSI ZIP drive that has an out of range SCSI bus. */
if (scsi_bus >= SCSI_BUS_MAX)
continue;
/* Make sure to ignore any SCSI ZIP drive that has an out of range ID. */
if (scsi_id >= SCSI_ID_MAX)
continue;
}
/* Make sure to ignore any ATAPI ZIP drive that has an out of range IDE channel. */
if ((zip_drives[c].bus_type == ZIP_BUS_ATAPI) && (zip_drives[c].ide_channel > 7))
continue;
zip_drive_reset(c);
dev = (zip_t *) zip_drives[c].priv;
if (dev->tf == NULL)
continue;
dev->id = c;
dev->drv = &zip_drives[c];
zip_init(dev);
if (strlen(zip_drives[c].image_path))
zip_load(dev, zip_drives[c].image_path);
zip_mode_sense_load(dev);
if (zip_drives[c].bus_type == ZIP_BUS_SCSI)
zip_log("SCSI ZIP drive %i attached to SCSI ID %i\n", c, zip_drives[c].scsi_device_id);
else if (zip_drives[c].bus_type == ZIP_BUS_ATAPI)
zip_log("ATAPI ZIP drive %i attached to IDE channel %i\n", c, zip_drives[c].ide_channel);
}
}
}
void
zip_close(void)
{
zip_t *dev;
uint8_t scsi_bus;
uint8_t scsi_id;
for (uint8_t c = 0; c < ZIP_NUM; c++) {
if (zip_drives[c].bus_type == ZIP_BUS_SCSI) {
scsi_bus = (zip_drives[c].scsi_device_id >> 4) & 0x0f;
scsi_id = zip_drives[c].scsi_device_id & 0x0f;
memset(&scsi_devices[scsi_bus][scsi_id], 0x00, sizeof(scsi_device_t));
}
dev = (zip_t *) zip_drives[c].priv;
if (dev) {
zip_disk_unload(dev);
if (dev->tf)
free(dev->tf);
free(dev);
zip_drives[c].priv = NULL;
}
}
}
``` | /content/code_sandbox/src/disk/zip.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 23,210 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Driver for the IBM PC-AT MFM/RLL Fixed Disk controller.
*
* This controller was a 16bit ISA card, and it used a WD1003
* based design. Most cards were WD1003-WA2 or -WAH, where the
* -WA2 cards had a floppy controller as well (to save space.)
*
*
*
* Authors: Sarah Walker, <path_to_url
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/pic.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#define MFM_TIME (TIMER_USEC * 10)
/*Rough estimate - MFM drives spin at 3600 RPM, with 17 sectors per track,
meaning (3600/60)*17 = 1020 sectors per second, or 980us per sector.
This is required for OS/2 on slow 286 systems, as the hard drive formatter
will crash with 'internal processing error' if write sector interrupts are too
close in time*/
#define SECTOR_TIME (TIMER_USEC * 980)
#define STAT_ERR 0x01
#define STAT_INDEX 0x02
#define STAT_ECC 0x04
#define STAT_DRQ 0x08 /* data request */
#define STAT_DSC 0x10
#define STAT_WRFLT 0x20
#define STAT_READY 0x40
#define STAT_BUSY 0x80
#define ERR_DAM_NOT_FOUND 0x01 /* Data Address Mark not found */
#define ERR_TR000 0x02 /* track 0 not found */
#define ERR_ABRT 0x04 /* command aborted */
#define ERR_ID_NOT_FOUND 0x10 /* ID not found */
#define ERR_DATA_CRC 0x40 /* data CRC error */
#define ERR_BAD_BLOCK 0x80 /* bad block detected */
#define CMD_RESTORE 0x10
#define CMD_READ 0x20
#define CMD_WRITE 0x30
#define CMD_VERIFY 0x40
#define CMD_FORMAT 0x50
#define CMD_SEEK 0x70
#define CMD_DIAGNOSE 0x90
#define CMD_SET_PARAMETERS 0x91
typedef struct drive_t {
int8_t present; /* drive is present */
int8_t hdd_num; /* drive number in system */
int8_t steprate; /* current servo step rate */
int8_t spt; /* physical #sectors per track */
int8_t hpc; /* physical #heads per cylinder */
int8_t pad;
int16_t tracks; /* physical #tracks per cylinder */
int8_t cfg_spt; /* configured #sectors per track */
int8_t cfg_hpc; /* configured #heads per track */
int16_t curcyl; /* current track number */
} drive_t;
typedef struct mfm_t {
uint8_t precomp; /* 1: precomp/error register */
uint8_t error;
uint8_t secount; /* 2: sector count register */
uint8_t sector; /* 3: sector number */
uint8_t head; /* 6: head number + drive select */
uint8_t command; /* 7: command/status */
uint8_t status;
uint8_t fdisk; /* 8: control register */
uint16_t cylinder; /* 4/5: cylinder LOW and HIGH */
int8_t reset; /* controller in reset */
int8_t irqstat; /* current IRQ status */
int8_t drvsel; /* current selected drive */
int8_t pad;
int pos; /* offset within data buffer */
pc_timer_t callback_timer; /* callback delay timer */
uint16_t buffer[256]; /* data buffer (16b wide) */
drive_t drives[MFM_NUM]; /* attached drives */
} mfm_t;
static uint8_t mfm_read(uint16_t port, void *priv);
static void mfm_write(uint16_t port, uint8_t val, void *priv);
#ifdef ENABLE_ST506_AT_LOG
int st506_at_do_log = ENABLE_ST506_AT_LOG;
static void
st506_at_log(const char *fmt, ...)
{
va_list ap;
if (st506_at_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define st506_at_log(fmt, ...)
#endif
static __inline void
irq_raise(mfm_t *mfm)
{
mfm->irqstat = 1;
if (!(mfm->fdisk & 2))
picint_common(1 << 14, PIC_IRQ_EDGE, 1, NULL);
}
static __inline void
irq_lower(mfm_t *mfm)
{
mfm->irqstat = 0;
if (!(mfm->fdisk & 2))
picint_common(1 << 14, PIC_IRQ_EDGE, 0, NULL);
}
static __inline void
irq_update(mfm_t *mfm)
{
uint8_t set = !(mfm->fdisk & 2) && mfm->irqstat;
picint_common(1 << 14, PIC_IRQ_EDGE, set, NULL);
}
/*
* Return the sector offset for the current register values.
*
* According to the WD1002/WD1003 technical reference manual,
* this is not done entirely correct. It specifies that the
* parameters set with the SET_DRIVE_PARAMETERS command are
* to be used only for multi-sector operations, and that any
* such operation can only be executed AFTER these parameters
* have been set. This would imply that for regular single
* transfers, the controller uses (or, can use) the actual
* geometry information...
*/
static int
get_sector(mfm_t *mfm, off64_t *addr)
{
const drive_t *drive = &mfm->drives[mfm->drvsel];
/* FIXME: See if this is even needed - if the code is present, IBM AT
diagnostics v2.07 will error with: ERROR 152 - SYSTEM BOARD. */
if (drive->curcyl != mfm->cylinder) {
st506_at_log("WD1003(%d) sector: wrong cylinder\n");
return 1;
}
if (mfm->head > drive->cfg_hpc) {
st506_at_log("WD1003(%d) get_sector: past end of configured heads\n",
mfm->drvsel);
return 1;
}
if (mfm->sector >= (drive->cfg_spt + 1)) {
st506_at_log("WD1003(%d) get_sector: past end of configured sectors\n",
mfm->drvsel);
return 1;
}
/* We should check this in the SET_DRIVE_PARAMETERS command! --FvK */
if (mfm->head > drive->hpc) {
st506_at_log("WD1003(%d) get_sector: past end of heads\n", mfm->drvsel);
return 1;
}
if (mfm->sector >= (drive->spt + 1)) {
st506_at_log("WD1003(%d) get_sector: past end of sectors\n", mfm->drvsel);
return 1;
}
*addr = ((((off64_t) mfm->cylinder * drive->cfg_hpc) + mfm->head) * drive->cfg_spt) + (mfm->sector - 1);
return 0;
}
static int
get_sector_format(mfm_t *mfm, off64_t *addr)
{
const drive_t *drive = &mfm->drives[mfm->drvsel];
/* FIXME: See if this is even needed - if the code is present, IBM AT
diagnostics v2.07 will error with: ERROR 152 - SYSTEM BOARD. */
if (drive->curcyl != mfm->cylinder) {
st506_at_log("WD1003(%d) sector: wrong cylinder\n");
return 1;
}
if (mfm->head > drive->cfg_hpc) {
st506_at_log("WD1003(%d) get_sector: past end of configured heads\n",
mfm->drvsel);
return 1;
}
/* We should check this in the SET_DRIVE_PARAMETERS command! --FvK */
if (mfm->head > drive->hpc) {
st506_at_log("WD1003(%d) get_sector: past end of heads\n", mfm->drvsel);
return 1;
}
*addr = ((((off64_t) mfm->cylinder * drive->cfg_hpc) + mfm->head) * drive->cfg_spt);
return 0;
}
/* Move to the next sector using CHS addressing. */
static void
next_sector(mfm_t *mfm)
{
drive_t *drive = &mfm->drives[mfm->drvsel];
if (++mfm->sector == (drive->cfg_spt + 1)) {
mfm->sector = 1;
if (++mfm->head == drive->cfg_hpc) {
mfm->head = 0;
mfm->cylinder++;
if (drive->curcyl < drive->tracks)
drive->curcyl++;
}
}
}
static void
mfm_cmd(mfm_t *mfm, uint8_t val)
{
drive_t *drive = &mfm->drives[mfm->drvsel];
if (!drive->present) {
/* This happens if sofware polls all drives. */
st506_at_log("WD1003(%d) command %02x on non-present drive\n",
mfm->drvsel, val);
mfm->command = 0xff;
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
return;
}
irq_lower(mfm);
mfm->command = val;
mfm->error = 0;
switch (val & 0xf0) {
case CMD_RESTORE:
drive->steprate = (val & 0x0f);
mfm->command &= 0xf0;
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
case CMD_SEEK:
drive->steprate = (val & 0x0f);
mfm->command &= 0xf0;
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
default:
mfm->command = val;
switch (val) {
case CMD_READ:
case CMD_READ + 1:
case CMD_READ + 2:
case CMD_READ + 3:
st506_at_log("WD1003(%d) read, opt=%d\n",
mfm->drvsel, val & 0x03);
mfm->command &= 0xfc;
if (val & 2)
fatal("WD1003: READ with ECC\n");
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
case CMD_WRITE:
case CMD_WRITE + 1:
case CMD_WRITE + 2:
case CMD_WRITE + 3:
st506_at_log("WD1003(%d) write, opt=%d\n",
mfm->drvsel, val & 0x03);
mfm->command &= 0xfc;
if (val & 2)
fatal("WD1003: WRITE with ECC\n");
mfm->status = STAT_READY | STAT_DRQ | STAT_DSC;
mfm->pos = 0;
break;
case CMD_VERIFY:
case CMD_VERIFY + 1:
mfm->command &= 0xfe;
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
case CMD_FORMAT:
mfm->status = STAT_DRQ | STAT_BUSY;
mfm->pos = 0;
break;
case CMD_DIAGNOSE:
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
case CMD_SET_PARAMETERS:
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
default:
st506_at_log("WD1003: bad command %02X\n", val);
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, 200 * MFM_TIME);
break;
}
}
}
static void
mfm_writew(uint16_t port, uint16_t val, void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
if (port > 0x01f0) {
mfm_write(port, val & 0xff, priv);
if (port != 0x01f7)
mfm_write(port + 1, (val >> 8) & 0xff, priv);
} else {
mfm->buffer[mfm->pos >> 1] = val;
mfm->pos += 2;
if (mfm->pos >= 512) {
mfm->pos = 0;
mfm->status = STAT_BUSY;
timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME);
}
}
}
static void
mfm_write(uint16_t port, uint8_t val, void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
uint8_t old;
st506_at_log("WD1003 write(%04x, %02x)\n", port, val);
switch (port) {
case 0x01f0: /* data */
mfm_writew(port, val | (val << 8), priv);
return;
case 0x01f1: /* write precompenstation */
mfm->precomp = val;
return;
case 0x01f2: /* sector count */
mfm->secount = val;
return;
case 0x01f3: /* sector */
mfm->sector = val;
return;
case 0x01f4: /* cylinder low */
mfm->cylinder = (mfm->cylinder & 0xff00) | val;
return;
case 0x01f5: /* cylinder high */
mfm->cylinder = (mfm->cylinder & 0xff) | (val << 8);
return;
case 0x01f6: /* drive/head */
mfm->head = val & 0xF;
mfm->drvsel = !!(val & 0x10);
if (mfm->drives[mfm->drvsel].present)
mfm->status = STAT_READY | STAT_DSC;
else
mfm->status = 0;
return;
case 0x01f7: /* command register */
mfm_cmd(mfm, val);
break;
case 0x03f6: /* device control */
val &= 0x0f;
if ((mfm->fdisk & 0x04) && !(val & 0x04)) {
timer_set_delay_u64(&mfm->callback_timer, 500 * MFM_TIME);
mfm->reset = 1;
mfm->status = STAT_BUSY;
} else if (!(mfm->fdisk & 0x04) && (val & 0x04)) {
/* Drive held in reset. */
timer_disable(&mfm->callback_timer);
mfm->status = STAT_BUSY;
}
old = mfm->fdisk;
mfm->fdisk = val;
if (!(val & 0x02) && (old & 0x02))
irq_update(mfm);
break;
default:
break;
}
}
static uint16_t
mfm_readw(uint16_t port, void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
uint16_t ret;
if (port > 0x01f0) {
ret = mfm_read(port, priv);
if (port == 0x01f7)
ret |= 0xff00;
else
ret |= (mfm_read(port + 1, priv) << 8);
} else {
ret = mfm->buffer[mfm->pos >> 1];
mfm->pos += 2;
if (mfm->pos >= 512) {
mfm->pos = 0;
mfm->status = STAT_READY | STAT_DSC;
if (mfm->command == CMD_READ) {
mfm->secount = (mfm->secount - 1) & 0xff;
if (mfm->secount) {
next_sector(mfm);
mfm->status = STAT_BUSY | STAT_READY | STAT_DSC;
timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME);
} else
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
}
}
}
return ret;
}
static uint8_t
mfm_read(uint16_t port, void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x01f0: /* data */
ret = mfm_readw(port, mfm) & 0xff;
break;
case 0x01f1: /* error */
ret = mfm->error;
break;
case 0x01f2: /* sector count */
ret = mfm->secount;
break;
case 0x01f3: /* sector */
ret = mfm->sector;
break;
case 0x01f4: /* CYlinder low */
ret = (uint8_t) (mfm->cylinder & 0xff);
break;
case 0x01f5: /* Cylinder high */
ret = (uint8_t) (mfm->cylinder >> 8);
break;
case 0x01f6: /* drive/head */
ret = (uint8_t) (0xa0 | mfm->head | (mfm->drvsel ? 0x10 : 0));
break;
case 0x01f7: /* Status */
irq_lower(mfm);
ret = mfm->status;
break;
default:
break;
}
st506_at_log("WD1003 read(%04x) = %02x\n", port, ret);
return ret;
}
static void
do_seek(mfm_t *mfm)
{
drive_t *drive = &mfm->drives[mfm->drvsel];
st506_at_log("WD1003(%d) seek(%d) max=%d\n",
mfm->drvsel, mfm->cylinder, drive->tracks);
if (mfm->cylinder < drive->tracks)
drive->curcyl = mfm->cylinder;
else
drive->curcyl = drive->tracks - 1;
}
static void
do_callback(void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
drive_t *drive = &mfm->drives[mfm->drvsel];
off64_t addr;
if (mfm->reset) {
st506_at_log("WD1003(%d) reset\n", mfm->drvsel);
mfm->status = STAT_READY | STAT_DSC;
mfm->error = 1;
mfm->secount = 1;
mfm->sector = 1;
mfm->head = 0;
mfm->cylinder = 0;
drive->steprate = 0x0f; /* default steprate */
drive->cfg_spt = 0; /* need new parameters */
mfm->reset = 0;
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
return;
}
switch (mfm->command) {
case CMD_RESTORE:
st506_at_log("WD1003(%d) restore, step=%d\n",
mfm->drvsel, drive->steprate);
drive->curcyl = 0;
mfm->cylinder = 0;
mfm->status = STAT_READY | STAT_DSC;
irq_raise(mfm);
break;
case CMD_SEEK:
st506_at_log("WD1003(%d) seek, step=%d\n",
mfm->drvsel, drive->steprate);
do_seek(mfm);
mfm->status = STAT_READY | STAT_DSC;
irq_raise(mfm);
break;
case CMD_READ:
st506_at_log("WD1003(%d) read(%d,%d,%d)\n",
mfm->drvsel, mfm->cylinder, mfm->head, mfm->sector);
do_seek(mfm);
if (get_sector(mfm, &addr)) {
mfm->error = ERR_ID_NOT_FOUND;
mfm->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(mfm);
break;
}
hdd_image_read(drive->hdd_num, addr, 1, (uint8_t *) mfm->buffer);
mfm->pos = 0;
mfm->status = STAT_DRQ | STAT_READY | STAT_DSC;
irq_raise(mfm);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
break;
case CMD_WRITE:
st506_at_log("WD1003(%d) write(%d,%d,%d)\n",
mfm->drvsel, mfm->cylinder, mfm->head, mfm->sector);
do_seek(mfm);
if (get_sector(mfm, &addr)) {
mfm->error = ERR_ID_NOT_FOUND;
mfm->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(mfm);
break;
}
hdd_image_write(drive->hdd_num, addr, 1, (uint8_t *) mfm->buffer);
irq_raise(mfm);
mfm->secount = (mfm->secount - 1) & 0xff;
mfm->status = STAT_READY | STAT_DSC;
if (mfm->secount) {
/* More sectors to do.. */
mfm->status |= STAT_DRQ;
mfm->pos = 0;
next_sector(mfm);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
} else
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
break;
case CMD_VERIFY:
st506_at_log("WD1003(%d) verify(%d,%d,%d)\n",
mfm->drvsel, mfm->cylinder, mfm->head, mfm->sector);
do_seek(mfm);
mfm->pos = 0;
mfm->status = STAT_READY | STAT_DSC;
irq_raise(mfm);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
break;
case CMD_FORMAT:
st506_at_log("WD1003(%d) format(%d,%d)\n",
mfm->drvsel, mfm->cylinder, mfm->head);
do_seek(mfm);
if (get_sector_format(mfm, &addr)) {
mfm->error = ERR_ID_NOT_FOUND;
mfm->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(mfm);
break;
}
hdd_image_zero(drive->hdd_num, addr, mfm->secount);
mfm->status = STAT_READY | STAT_DSC;
irq_raise(mfm);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 1);
break;
case CMD_DIAGNOSE:
st506_at_log("WD1003(%d) diag\n", mfm->drvsel);
/* This is basically controller diagnostics - it resets drive select to 0,
and resets error and status to ready, DSC, and no error detected. */
mfm->drvsel = 0;
drive = &mfm->drives[mfm->drvsel];
drive->steprate = 0x0f;
mfm->error = 1;
mfm->status = STAT_READY | STAT_DSC;
irq_raise(mfm);
break;
case CMD_SET_PARAMETERS:
/*
* NOTE:
*
* We currently just set these parameters, and
* never bother to check if they "fit within"
* the actual parameters, as determined by the
* image loader.
*
* The difference in parameters is OK, and
* occurs when the BIOS or operating system
* decides to use a different translation
* scheme, but either way, it SHOULD always
* fit within the actual parameters!
*
* We SHOULD check that here!! --FvK
*/
if (drive->cfg_spt == 0) {
/* Only accept after RESET or DIAG. */
drive->cfg_spt = mfm->secount;
drive->cfg_hpc = mfm->head + 1;
st506_at_log("WD1003(%d) parameters: tracks=%d, spt=%i, hpc=%i\n",
mfm->drvsel, drive->tracks,
drive->cfg_spt, drive->cfg_hpc);
} else {
st506_at_log("WD1003(%d) parameters: tracks=%d,spt=%i,hpc=%i (IGNORED)\n",
mfm->drvsel, drive->tracks,
drive->cfg_spt, drive->cfg_hpc);
}
mfm->command = 0x00;
mfm->status = STAT_READY | STAT_DSC;
mfm->error = 1;
irq_raise(mfm);
break;
default:
st506_at_log("WD1003(%d) callback on unknown command %02x\n",
mfm->drvsel, mfm->command);
mfm->status = STAT_READY | STAT_ERR | STAT_DSC;
mfm->error = ERR_ABRT;
irq_raise(mfm);
break;
}
}
static void
loadhd(mfm_t *mfm, int c, int d, UNUSED(const char *fn))
{
drive_t *drive = &mfm->drives[c];
if (!hdd_image_load(d)) {
drive->present = 0;
return;
}
drive->spt = hdd[d].spt;
drive->hpc = hdd[d].hpc;
drive->tracks = hdd[d].tracks;
drive->hdd_num = d;
drive->present = 1;
}
static void *
mfm_init(UNUSED(const device_t *info))
{
mfm_t *mfm;
int c;
st506_at_log("WD1003: ISA MFM/RLL Fixed Disk Adapter initializing ...\n");
mfm = malloc(sizeof(mfm_t));
memset(mfm, 0x00, sizeof(mfm_t));
c = 0;
for (uint8_t d = 0; d < HDD_NUM; d++) {
if ((hdd[d].bus == HDD_BUS_MFM) && (hdd[d].mfm_channel < MFM_NUM)) {
loadhd(mfm, hdd[d].mfm_channel, d, hdd[d].fn);
st506_at_log("WD1003(%d): (%s) geometry %d/%d/%d\n", c, hdd[d].fn,
(int) hdd[d].tracks, (int) hdd[d].hpc, (int) hdd[d].spt);
if (++c >= MFM_NUM)
break;
}
}
mfm->status = STAT_READY | STAT_DSC; /* drive is ready */
mfm->error = 1; /* no errors */
io_sethandler(0x01f0, 1,
mfm_read, mfm_readw, NULL, mfm_write, mfm_writew, NULL, mfm);
io_sethandler(0x01f1, 7,
mfm_read, mfm_readw, NULL, mfm_write, mfm_writew, NULL, mfm);
io_sethandler(0x03f6, 1,
NULL, NULL, NULL, mfm_write, NULL, NULL, mfm);
timer_add(&mfm->callback_timer, do_callback, mfm, 0);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
return mfm;
}
static void
mfm_close(void *priv)
{
mfm_t *mfm = (mfm_t *) priv;
for (uint8_t d = 0; d < 2; d++) {
const drive_t *drive = &mfm->drives[d];
hdd_image_close(drive->hdd_num);
}
free(mfm);
ui_sb_update_icon(SB_HDD | HDD_BUS_MFM, 0);
}
const device_t st506_at_wd1003_device = {
.name = "WD1003 AT MFM/RLL Controller",
.internal_name = "st506_at",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = mfm_init,
.close = mfm_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_st506_at.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,894 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Driver for IBM PS/2 ESDI disk controller (MCA)
*
* AdapterID: 0xDDFF
* AdapterName: "ESDI Fixed Disk Controller"
* NumBytes 2
* I/O base: 0x3510-0x3517
* IRQ: 14
*
* Primary Board pos[0]=XXxx xx0X 0x3510
* Secondary Board pos[0]=XXxx xx1X 0x3518
*
* DMA 5 pos[0]=XX01 01XX
* DMA 6 pos[0]=XX01 10XX
* DMA 7 pos[0]=XX01 11XX
* DMA 0 pos[0]=XX00 00XX
* DMA 1 pos[0]=XX00 01XX
* DMA 3 pos[0]=XX00 11XX
* DMA 4 pos[0]=XX01 00XX
*
* MCA Fairness ON pos[0]=X1XX XXXX
* MCA Fairness OFF pos[0]=X0XX XXXX
*
* ROM C000 pos[1]=XXXX 0000
* ROM C400 pos[1]=XXXX 0001
* ROM C800 pos[1]=XXXX 0010
* ROM CC00 pos[1]=XXXX 0011
* ROM D000 pos[1]=XXXX 0100
* ROM D400 pos[1]=XXXX 0101
* ROM D800 pos[1]=XXXX 0110
* ROM DC00 pos[1]=XXXX 0111
* ROM Disabled pos[1]=XXXX 1XXX
*
* DMA Burst 8 pos[1]=XX01 XXXX
* DMA Burst 16 pos[1]=XX10 XXXX
* DMA Burst 24 pos[1]=XX11 XXXX
* DMA Disabled pos[1]=XX00 XXXX
*
* Although this is an MCA device, meaning that the system
* software will take care of device configuration, the ESDI
* controller is a somewhat weird one.. it's I/O base address
* and IRQ channel are locked to 0x3510 and IRQ14, possibly
* to enforce compatibility with the IBM MFM disk controller
* that was also in use on these systems. All other settings,
* however, are auto-configured by the system software as
* shown above.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <inttypes.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/pic.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#include <86box/plat_unused.h>
/* These are hardwired. */
#define ESDI_IOADDR_PRI 0x3510
#define ESDI_IOADDR_SEC 0x3518
#define ESDI_IRQCHAN 14
#define BIOS_FILE_L "roms/hdd/esdi/90x8969.bin"
#define BIOS_FILE_H "roms/hdd/esdi/90x8970.bin"
#define ESDI_TIME 500.0
#define CMD_ADAPTER 0
typedef struct esdi_drive_t {
int spt;
int hpc;
int tracks;
int sectors;
int present;
int hdd_num;
} drive_t;
typedef struct esdi_t {
int8_t dma;
uint32_t bios;
rom_t bios_rom;
uint8_t basic_ctrl;
uint8_t status;
uint8_t irq_status;
int irq_ena_disable;
int irq_in_progress;
int cmd_req_in_progress;
int cmd_pos;
uint16_t cmd_data[4];
int cmd_dev;
int status_pos;
int status_len;
uint16_t status_data[256];
int data_pos;
uint16_t data[256];
uint16_t sector_buffer[256][256];
int sector_pos;
int sector_count;
int command;
int cmd_state;
int in_reset;
pc_timer_t timer;
uint32_t rba;
struct cmds {
int req_in_progress;
} cmds[3];
drive_t drives[2];
uint8_t pos_regs[8];
} esdi_t;
#define STATUS_DMA_ENA (1 << 7)
#define STATUS_IRQ_PENDING (1 << 6)
#define STATUS_CMD_IN_PROGRESS (1 << 5)
#define STATUS_BUSY (1 << 4)
#define STATUS_STATUS_OUT_FULL (1 << 3)
#define STATUS_CMD_IR_FULL (1 << 2)
#define STATUS_TRANSFER_REQ (1 << 1)
#define STATUS_IRQ (1 << 0)
#define CTRL_RESET (1 << 7)
#define CTRL_DMA_ENA (1 << 1)
#define CTRL_IRQ_ENA (1 << 0)
#define IRQ_HOST_ADAPTER (7 << 5)
#define IRQ_DEVICE_0 (0 << 5)
#define IRQ_CMD_COMPLETE_SUCCESS 0x1
#define IRQ_RESET_COMPLETE 0xa
#define IRQ_DATA_TRANSFER_READY 0xb
#define IRQ_CMD_COMPLETE_FAILURE 0xc
#define ATTN_DEVICE_SEL (7 << 5)
#define ATTN_HOST_ADAPTER (7 << 5)
#define ATTN_DEVICE_0 (0 << 5)
#define ATTN_DEVICE_1 (1 << 5)
#define ATTN_REQ_MASK 0x0f
#define ATTN_CMD_REQ 1
#define ATTN_EOI 2
#define ATTN_RESET 4
#define CMD_SIZE_4 (1 << 14)
#define CMD_DEVICE_SEL (7 << 5)
#define CMD_MASK 0x1f
#define CMD_READ 0x01
#define CMD_WRITE 0x02
#define CMD_READ_VERIFY 0x03
#define CMD_WRITE_VERIFY 0x04
#define CMD_SEEK 0x05
#define CMD_GET_DEV_STATUS 0x08
#define CMD_GET_DEV_CONFIG 0x09
#define CMD_GET_POS_INFO 0x0a
#define CMD_FORMAT_UNIT 0x16
#define CMD_FORMAT_PREPARE 0x17
#define STATUS_LEN(x) ((x) << 8)
#define STATUS_DEVICE(x) ((x) << 5)
#define STATUS_DEVICE_HOST_ADAPTER (7 << 5)
#ifdef ENABLE_ESDI_MCA_LOG
int esdi_mca_do_log = ENABLE_ESDI_MCA_LOG;
static void
esdi_mca_log(const char *fmt, ...)
{
va_list ap;
if (esdi_mca_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define esdi_mca_log(fmt, ...)
#endif
static __inline void
set_irq(esdi_t *dev)
{
dev->irq_ena_disable = 1;
esdi_mca_log("Set IRQ 14: bit=%x, cmd=%02x.\n", dev->basic_ctrl & CTRL_IRQ_ENA, dev->command);
if (dev->basic_ctrl & CTRL_IRQ_ENA)
picint_common(1 << ESDI_IRQCHAN, PIC_IRQ_EDGE, 1, NULL);
}
static __inline void
clear_irq(esdi_t *dev)
{
dev->irq_ena_disable = 0;
esdi_mca_log("Clear IRQ 14: bit=%x, cmd=%02x.\n", dev->basic_ctrl & CTRL_IRQ_ENA, dev->command);
if (dev->basic_ctrl & CTRL_IRQ_ENA)
picint_common(1 << ESDI_IRQCHAN, PIC_IRQ_EDGE, 0, NULL);
}
static __inline void
update_irq(esdi_t *dev)
{
uint8_t set = (dev->basic_ctrl & CTRL_IRQ_ENA) && dev->irq_ena_disable;
picint_common(1 << ESDI_IRQCHAN, PIC_IRQ_EDGE, set, NULL);
}
static void
esdi_mca_set_callback(esdi_t *dev, double callback)
{
if (!dev) {
return;
}
if (callback == 0.0) {
esdi_mca_log("Callback Stopped.\n");
timer_stop(&dev->timer);
} else {
timer_on_auto(&dev->timer, callback);
}
}
static double
esdi_mca_get_xfer_time(UNUSED(esdi_t *esdi), int size)
{
/* 390.625 us per sector at 10 Mbit/s = 1280 kB/s. */
return (3125.0 / 8.0) * (double) size;
}
static void
cmd_unsupported(esdi_t *dev)
{
dev->status_len = 9;
dev->status_data[0] = dev->command | STATUS_LEN(9) | dev->cmd_dev;
dev->status_data[1] = 0x0f03; /*Attention error, command not supported*/
dev->status_data[2] = 0x0002; /*Interface fault*/
dev->status_data[3] = 0;
dev->status_data[4] = 0;
dev->status_data[5] = 0;
dev->status_data[6] = 0;
dev->status_data[7] = 0;
dev->status_data[8] = 0;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_FAILURE;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
static void
device_not_present(esdi_t *dev)
{
dev->status_len = 9;
dev->status_data[0] = dev->command | STATUS_LEN(9) | dev->cmd_dev;
dev->status_data[1] = 0x0c11; /*Command failed, internal hardware error*/
dev->status_data[2] = 0x000b; /*Selection error*/
dev->status_data[3] = 0;
dev->status_data[4] = 0;
dev->status_data[5] = 0;
dev->status_data[6] = 0;
dev->status_data[7] = 0;
dev->status_data[8] = 0;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_FAILURE;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
static void
rba_out_of_range(esdi_t *dev)
{
dev->status_len = 9;
dev->status_data[0] = dev->command | STATUS_LEN(9) | dev->cmd_dev;
dev->status_data[1] = 0x0e01; /*Command block error, invalid parameter*/
dev->status_data[2] = 0x0007; /*RBA out of range*/
dev->status_data[3] = 0;
dev->status_data[4] = 0;
dev->status_data[5] = 0;
dev->status_data[6] = 0;
dev->status_data[7] = 0;
dev->status_data[8] = 0;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_FAILURE;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
static void
complete_command_status(esdi_t *dev)
{
dev->status_len = 7;
if (dev->cmd_dev == ATTN_DEVICE_0)
dev->status_data[0] = dev->command | STATUS_LEN(7) | STATUS_DEVICE(0);
else
dev->status_data[0] = dev->command | STATUS_LEN(7) | STATUS_DEVICE(1);
dev->status_data[1] = 0x0000; /*Error bits*/
dev->status_data[2] = 0x1900; /*Device status*/
dev->status_data[3] = 0; /*Number of blocks left to do*/
dev->status_data[4] = (dev->rba - 1) & 0xffff; /*Last RBA processed*/
dev->status_data[5] = (dev->rba - 1) >> 8;
dev->status_data[6] = 0; /*Number of blocks requiring error recovery*/
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
#define ESDI_ADAPTER_ONLY() \
if (dev->cmd_dev != ATTN_HOST_ADAPTER) { \
cmd_unsupported(dev); \
return; \
}
#define ESDI_DRIVE_ONLY() \
if (dev->cmd_dev != ATTN_DEVICE_0 && dev->cmd_dev != ATTN_DEVICE_1) { \
cmd_unsupported(dev); \
return; \
} \
if (dev->cmd_dev == ATTN_DEVICE_0) \
drive = &dev->drives[0]; \
else \
drive = &dev->drives[1];
static void
esdi_callback(void *priv)
{
esdi_t *dev = (esdi_t *) priv;
const drive_t *drive;
int val;
double cmd_time = 0.0;
/* If we are returning from a RESET, handle this first. */
if (dev->in_reset) {
esdi_mca_log("ESDI reset.\n");
dev->in_reset = 0;
dev->status = STATUS_IRQ;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_RESET_COMPLETE;
return;
}
esdi_mca_log("Command=%02x.\n", dev->command);
switch (dev->command) {
case CMD_READ:
case 0x15:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
switch (dev->cmd_state) {
case 0:
if (dev->command == CMD_READ)
dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
dev->sector_pos = 0;
dev->sector_count = dev->cmd_data[1];
if ((dev->rba + dev->sector_count) > hdd_image_get_last_sector(drive->hdd_num)) {
rba_out_of_range(dev);
return;
}
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
dev->irq_status = dev->cmd_dev | IRQ_DATA_TRANSFER_READY;
dev->irq_in_progress = 1;
set_irq(dev);
dev->cmd_state = 1;
esdi_mca_set_callback(dev, ESDI_TIME);
dev->data_pos = 0;
break;
case 1:
if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
while (dev->sector_pos < dev->sector_count) {
if (!dev->data_pos) {
if (dev->rba >= drive->sectors)
fatal("Read past end of drive\n");
hdd_image_read(drive->hdd_num, dev->rba, 1, (uint8_t *) dev->data);
cmd_time += hdd_timing_read(&hdd[drive->hdd_num], dev->rba, 1);
cmd_time += esdi_mca_get_xfer_time(dev, 1);
}
while (dev->data_pos < 256) {
val = dma_channel_write(dev->dma, dev->data[dev->data_pos]);
if (val == DMA_NODATA) {
esdi_mca_set_callback(dev, ESDI_TIME + cmd_time);
return;
}
dev->data_pos++;
}
dev->data_pos = 0;
dev->sector_pos++;
dev->rba++;
}
dev->status = STATUS_CMD_IN_PROGRESS;
dev->cmd_state = 2;
esdi_mca_set_callback(dev, cmd_time);
break;
case 2:
complete_command_status(dev);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
case CMD_WRITE:
case CMD_WRITE_VERIFY:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
switch (dev->cmd_state) {
case 0:
dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
dev->sector_pos = 0;
dev->sector_count = dev->cmd_data[1];
if ((dev->rba + dev->sector_count) > hdd_image_get_last_sector(drive->hdd_num)) {
rba_out_of_range(dev);
return;
}
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
dev->irq_status = dev->cmd_dev | IRQ_DATA_TRANSFER_READY;
dev->irq_in_progress = 1;
set_irq(dev);
dev->cmd_state = 1;
esdi_mca_set_callback(dev, ESDI_TIME);
dev->data_pos = 0;
break;
case 1:
if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
while (dev->sector_pos < dev->sector_count) {
while (dev->data_pos < 256) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
esdi_mca_set_callback(dev, ESDI_TIME + cmd_time);
return;
}
dev->data[dev->data_pos++] = val & 0xffff;
}
if (dev->rba >= drive->sectors)
fatal("Write past end of drive\n");
hdd_image_write(drive->hdd_num, dev->rba, 1, (uint8_t *) dev->data);
cmd_time += hdd_timing_write(&hdd[drive->hdd_num], dev->rba, 1);
cmd_time += esdi_mca_get_xfer_time(dev, 1);
dev->rba++;
dev->sector_pos++;
dev->data_pos = 0;
}
dev->status = STATUS_CMD_IN_PROGRESS;
dev->cmd_state = 2;
esdi_mca_set_callback(dev, cmd_time);
break;
case 2:
complete_command_status(dev);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
case CMD_READ_VERIFY:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
switch (dev->cmd_state) {
case 0:
dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
dev->sector_count = dev->cmd_data[1];
if ((dev->rba + dev->sector_count) > hdd_image_get_last_sector(drive->hdd_num)) {
rba_out_of_range(dev);
return;
}
cmd_time = hdd_timing_read(&hdd[drive->hdd_num], dev->rba, dev->sector_count);
esdi_mca_set_callback(dev, ESDI_TIME + cmd_time);
dev->cmd_state = 1;
break;
case 1:
complete_command_status(dev);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
case CMD_SEEK:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
if ((dev->rba + dev->sector_count) > hdd_image_get_last_sector(drive->hdd_num)) {
rba_out_of_range(dev);
return;
}
switch (dev->cmd_state) {
case 0:
dev->rba = (dev->cmd_data[2] | (dev->cmd_data[3] << 16)) & 0x0fffffff;
cmd_time = hdd_seek_get_time(&hdd[drive->hdd_num], dev->rba, HDD_OP_SEEK, 0, 0.0);
esdi_mca_set_callback(dev, ESDI_TIME + cmd_time);
dev->cmd_state = 1;
break;
case 1:
complete_command_status(dev);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
case CMD_GET_DEV_STATUS:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
dev->status_len = 9;
dev->status_data[0] = CMD_GET_DEV_STATUS | STATUS_LEN(9) | STATUS_DEVICE_HOST_ADAPTER;
dev->status_data[1] = 0x0000; /*Error bits*/
dev->status_data[2] = 0x1900; /*Device status*/
dev->status_data[3] = 0; /*ESDI Standard Status*/
dev->status_data[4] = 0; /*ESDI Vendor Unique Status*/
dev->status_data[5] = 0;
dev->status_data[6] = 0;
dev->status_data[7] = 0;
dev->status_data[8] = 0;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_GET_DEV_CONFIG:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
dev->status_len = 6;
dev->status_data[0] = CMD_GET_DEV_CONFIG | STATUS_LEN(6) | STATUS_DEVICE_HOST_ADAPTER;
dev->status_data[1] = 0x10; /*Zero defect*/
dev->status_data[2] = drive->sectors & 0xffff;
dev->status_data[3] = drive->sectors >> 16;
dev->status_data[4] = drive->tracks;
dev->status_data[5] = drive->hpc | (drive->spt << 16);
esdi_mca_log("CMD_GET_DEV_CONFIG %i %04x %04x %04x %04x %04x %04x\n",
drive->sectors,
dev->status_data[0], dev->status_data[1],
dev->status_data[2], dev->status_data[3],
dev->status_data[4], dev->status_data[5]);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_GET_POS_INFO:
ESDI_ADAPTER_ONLY();
if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
dev->status_len = 5;
dev->status_data[0] = CMD_GET_POS_INFO | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER;
dev->status_data[1] = 0xffdd; /*MCA ID*/
dev->status_data[2] = dev->pos_regs[3] | (dev->pos_regs[2] << 8);
dev->status_data[3] = 0xff;
dev->status_data[4] = 0xff;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case 0x10:
ESDI_ADAPTER_ONLY();
switch (dev->cmd_state) {
case 0:
dev->sector_pos = 0;
dev->sector_count = dev->cmd_data[1];
if (dev->sector_count > 256)
fatal("Write sector buffer count %04x\n", dev->cmd_data[1]);
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY;
dev->irq_in_progress = 1;
set_irq(dev);
dev->cmd_state = 1;
esdi_mca_set_callback(dev, ESDI_TIME);
dev->data_pos = 0;
break;
case 1:
if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
while (dev->sector_pos < dev->sector_count) {
while (dev->data_pos < 256) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
dev->data[dev->data_pos++] = val & 0xffff;
}
memcpy(dev->sector_buffer[dev->sector_pos++], dev->data, 512);
dev->data_pos = 0;
}
dev->status = STATUS_CMD_IN_PROGRESS;
dev->cmd_state = 2;
esdi_mca_set_callback(dev, ESDI_TIME);
break;
case 2:
dev->status = STATUS_IRQ;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
default:
break;
}
break;
case 0x11:
ESDI_ADAPTER_ONLY();
switch (dev->cmd_state) {
case 0:
dev->sector_pos = 0;
dev->sector_count = dev->cmd_data[1];
if (dev->sector_count > 256)
fatal("Read sector buffer count %04x\n", dev->cmd_data[1]);
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_DATA_TRANSFER_READY;
dev->irq_in_progress = 1;
set_irq(dev);
dev->cmd_state = 1;
esdi_mca_set_callback(dev, ESDI_TIME);
dev->data_pos = 0;
break;
case 1:
if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
while (dev->sector_pos < dev->sector_count) {
if (!dev->data_pos)
memcpy(dev->data, dev->sector_buffer[dev->sector_pos++], 512);
while (dev->data_pos < 256) {
val = dma_channel_write(dev->dma, dev->data[dev->data_pos]);
if (val == DMA_NODATA) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
dev->data_pos++;
}
dev->data_pos = 0;
}
dev->status = STATUS_CMD_IN_PROGRESS;
dev->cmd_state = 2;
esdi_mca_set_callback(dev, ESDI_TIME);
break;
case 2:
dev->status = STATUS_IRQ;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
default:
break;
}
break;
case 0x12:
ESDI_ADAPTER_ONLY();
if ((dev->status & STATUS_IRQ) || dev->irq_in_progress)
fatal("IRQ in progress %02x %i\n", dev->status, dev->irq_in_progress);
dev->status_len = 2;
dev->status_data[0] = 0x12 | STATUS_LEN(5) | STATUS_DEVICE_HOST_ADAPTER;
dev->status_data[1] = 0;
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = IRQ_HOST_ADAPTER | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_FORMAT_UNIT:
case CMD_FORMAT_PREPARE:
ESDI_DRIVE_ONLY();
if (!drive->present) {
device_not_present(dev);
return;
}
switch (dev->cmd_state) {
case 0:
dev->rba = hdd_image_get_last_sector(drive->hdd_num);
if (dev->command == CMD_FORMAT_UNIT)
dev->sector_count = dev->cmd_data[1];
else
dev->sector_count = 0;
dev->status = STATUS_IRQ | STATUS_CMD_IN_PROGRESS | STATUS_TRANSFER_REQ;
dev->irq_status = dev->cmd_dev | IRQ_DATA_TRANSFER_READY;
dev->irq_in_progress = 1;
set_irq(dev);
dev->cmd_state = 1;
esdi_mca_set_callback(dev, ESDI_TIME);
break;
case 1:
if (!(dev->basic_ctrl & CTRL_DMA_ENA)) {
esdi_mca_set_callback(dev, ESDI_TIME);
return;
}
if (dev->command == CMD_FORMAT_UNIT)
hdd_image_zero(drive->hdd_num, 0, hdd_image_get_last_sector(drive->hdd_num) + 1);
dev->status = STATUS_CMD_IN_PROGRESS;
dev->cmd_state = 2;
esdi_mca_set_callback(dev, ESDI_TIME);
break;
case 2:
complete_command_status(dev);
dev->status = STATUS_IRQ | STATUS_STATUS_OUT_FULL;
dev->irq_status = dev->cmd_dev | IRQ_CMD_COMPLETE_SUCCESS;
dev->irq_in_progress = 1;
set_irq(dev);
break;
default:
break;
}
break;
default:
fatal("BAD COMMAND %02x %i\n", dev->command, dev->cmd_dev);
}
}
static uint8_t
esdi_read(uint16_t port, void *priv)
{
esdi_t *dev = (esdi_t *) priv;
uint8_t ret = 0x00;
switch (port & 7) {
case 2: /*Basic status register*/
ret = dev->status;
break;
case 3: /*IRQ status*/
dev->status &= ~STATUS_IRQ;
ret = dev->irq_status;
break;
default:
esdi_mca_log("esdi_read port=%04x\n", port);
break;
}
esdi_mca_log("ESDI: rr(%04x, %02x)\n", port & 7, ret);
return ret;
}
static void
esdi_write(uint16_t port, uint8_t val, void *priv)
{
esdi_t *dev = (esdi_t *) priv;
uint8_t old;
esdi_mca_log("ESDI: wr(%04x, %02x)\n", port & 7, val);
switch (port & 7) {
case 2: /*Basic control register*/
if ((dev->basic_ctrl & CTRL_RESET) && !(val & CTRL_RESET)) {
dev->in_reset = 1;
esdi_mca_set_callback(dev, ESDI_TIME * 50);
dev->status = STATUS_BUSY;
} else if (!(dev->basic_ctrl & CTRL_RESET) && (val & CTRL_RESET)) {
esdi_mca_set_callback(dev, 0.0);
dev->status = STATUS_BUSY;
}
old = dev->basic_ctrl;
dev->basic_ctrl = val;
if ((val & CTRL_IRQ_ENA) && !(old & CTRL_IRQ_ENA))
update_irq(dev);
break;
case 3: /*Attention register*/
switch (val & ATTN_DEVICE_SEL) {
case ATTN_HOST_ADAPTER:
switch (val & ATTN_REQ_MASK) {
case ATTN_CMD_REQ:
if (dev->cmd_req_in_progress)
fatal("Try to start command on in_progress adapter\n");
dev->cmd_req_in_progress = 1;
dev->cmd_dev = ATTN_HOST_ADAPTER;
dev->status |= STATUS_BUSY;
dev->cmd_pos = 0;
dev->status_pos = 0;
break;
case ATTN_EOI:
dev->irq_in_progress = 0;
dev->status &= ~STATUS_IRQ;
clear_irq(dev);
break;
case ATTN_RESET:
dev->in_reset = 1;
esdi_mca_set_callback(dev, ESDI_TIME * 50);
dev->status = STATUS_BUSY;
break;
default:
fatal("Bad attention request %02x\n", val);
}
break;
case ATTN_DEVICE_0:
esdi_mca_log("ATTN Device 0.\n");
switch (val & ATTN_REQ_MASK) {
case ATTN_CMD_REQ:
if (dev->cmd_req_in_progress)
fatal("Try to start command on in_progress device0\n");
dev->cmd_req_in_progress = 1;
dev->cmd_dev = ATTN_DEVICE_0;
dev->status |= STATUS_BUSY;
dev->cmd_pos = 0;
dev->status_pos = 0;
break;
case ATTN_EOI:
esdi_mca_log("EOI.\n");
dev->irq_in_progress = 0;
dev->status &= ~STATUS_IRQ;
clear_irq(dev);
break;
default:
fatal("Bad attention request %02x\n", val);
}
break;
case ATTN_DEVICE_1:
switch (val & ATTN_REQ_MASK) {
case ATTN_CMD_REQ:
if (dev->cmd_req_in_progress)
fatal("Try to start command on in_progress device0\n");
dev->cmd_req_in_progress = 1;
dev->cmd_dev = ATTN_DEVICE_1;
dev->status |= STATUS_BUSY;
dev->cmd_pos = 0;
dev->status_pos = 0;
break;
case ATTN_EOI:
dev->irq_in_progress = 0;
dev->status &= ~STATUS_IRQ;
clear_irq(dev);
break;
default:
fatal("Bad attention request %02x\n", val);
}
break;
default:
fatal("Attention to unknown device %02x\n", val);
}
break;
default:
fatal("esdi_write port=%04x val=%02x\n", port, val);
}
}
static uint16_t
esdi_readw(uint16_t port, void *priv)
{
esdi_t *dev = (esdi_t *) priv;
uint16_t ret = 0xffff;
switch (port & 7) {
case 0: /*Status Interface Register*/
if (dev->status_pos >= dev->status_len)
return 0;
ret = dev->status_data[dev->status_pos++];
if (dev->status_pos >= dev->status_len) {
dev->status &= ~STATUS_STATUS_OUT_FULL;
dev->status_pos = dev->status_len = 0;
}
break;
default:
fatal("esdi_readw port=%04x\n", port);
}
return ret;
}
static void
esdi_writew(uint16_t port, uint16_t val, void *priv)
{
esdi_t *dev = (esdi_t *) priv;
esdi_mca_log("ESDI: wrw(%04x, %04x)\n", port & 7, val);
switch (port & 7) {
case 0: /*Command Interface Register*/
if (dev->cmd_pos >= 4)
fatal("CIR pos 4\n");
dev->cmd_data[dev->cmd_pos++] = val;
if (((dev->cmd_data[0] & CMD_SIZE_4) && dev->cmd_pos == 4) || (!(dev->cmd_data[0] & CMD_SIZE_4) && dev->cmd_pos == 2)) {
dev->cmd_pos = 0;
dev->cmd_req_in_progress = 0;
dev->cmd_state = 0;
if ((dev->cmd_data[0] & CMD_DEVICE_SEL) != dev->cmd_dev)
fatal("Command device mismatch with attn\n");
dev->command = dev->cmd_data[0] & CMD_MASK;
esdi_mca_set_callback(dev, ESDI_TIME);
dev->status = STATUS_BUSY;
dev->data_pos = 0;
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
}
break;
default:
fatal("esdi_writew port=%04x val=%04x\n", port, val);
}
}
static uint8_t
esdi_mca_read(int port, void *priv)
{
const esdi_t *dev = (esdi_t *) priv;
esdi_mca_log("ESDI: mcard(%04x)\n", port);
return (dev->pos_regs[port & 7]);
}
static void
esdi_mca_write(int port, uint8_t val, void *priv)
{
esdi_t *dev = (esdi_t *) priv;
esdi_mca_log("ESDI: mcawr(%04x, %02x) pos[2]=%02x pos[3]=%02x\n",
port, val, dev->pos_regs[2], dev->pos_regs[3]);
if (port < 0x102)
return;
/* Save the new value. */
dev->pos_regs[port & 7] = val;
io_removehandler(ESDI_IOADDR_PRI, 8,
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, dev);
mem_mapping_disable(&dev->bios_rom.mapping);
switch (dev->pos_regs[2] & 0x3c) {
case 0x14:
dev->dma = 5;
break;
case 0x18:
dev->dma = 6;
break;
case 0x1c:
dev->dma = 7;
break;
case 0x00:
dev->dma = 0;
break;
case 0x04:
dev->dma = 1;
break;
case 0x0c:
dev->dma = 3;
break;
case 0x10:
dev->dma = 4;
break;
default:
break;
}
if (!(dev->pos_regs[3] & 8)) {
switch (dev->pos_regs[3] & 7) {
case 2:
dev->bios = 0xc8000;
break;
case 3:
dev->bios = 0xcc000;
break;
case 4:
dev->bios = 0xd0000;
break;
case 5:
dev->bios = 0xd4000;
break;
case 6:
dev->bios = 0xd8000;
break;
case 7:
dev->bios = 0xdc000;
break;
default:
break;
}
} else
dev->bios = 0;
if (dev->pos_regs[2] & 1) {
io_sethandler(ESDI_IOADDR_PRI, 8,
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, dev);
if (dev->bios) {
mem_mapping_enable(&dev->bios_rom.mapping);
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->bios, 0x4000);
}
/* Say hello. */
esdi_mca_log("ESDI: I/O=3510, IRQ=14, DMA=%d, BIOS @%05X\n",
dev->dma, dev->bios);
}
}
static uint8_t
esdi_mca_feedb(void *priv)
{
const esdi_t *dev = (esdi_t *) priv;
return (dev->pos_regs[2] & 1);
}
static void *
esdi_init(UNUSED(const device_t *info))
{
drive_t *drive;
esdi_t *dev;
uint8_t c;
uint8_t i;
dev = malloc(sizeof(esdi_t));
if (dev == NULL)
return (NULL);
memset(dev, 0x00, sizeof(esdi_t));
/* Mark as unconfigured. */
dev->irq_status = 0xff;
rom_init_interleaved(&dev->bios_rom,
BIOS_FILE_H, BIOS_FILE_L,
0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&dev->bios_rom.mapping);
dev->drives[0].present = dev->drives[1].present = 0;
for (c = 0, i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus == HDD_BUS_ESDI) && (hdd[i].esdi_channel < ESDI_NUM)) {
/* This is an ESDI drive. */
drive = &dev->drives[hdd[i].esdi_channel];
/* Try to load an image for the drive. */
if (!hdd_image_load(i)) {
/* Nope. */
drive->present = 0;
continue;
}
hdd_preset_apply(i);
/* OK, so fill in geometry info. */
drive->spt = hdd[i].spt;
drive->hpc = hdd[i].hpc;
drive->tracks = hdd[i].tracks;
drive->sectors = hdd_image_get_last_sector(i) + 1;
drive->hdd_num = i;
/* Mark drive as present. */
drive->present = 1;
}
if (++c >= ESDI_NUM)
break;
}
/* Set the MCA ID for this controller, 0xFFDD. */
dev->pos_regs[0] = 0xff;
dev->pos_regs[1] = 0xdd;
/* Enable the device. */
mca_add(esdi_mca_read, esdi_mca_write, esdi_mca_feedb, NULL, dev);
/* Mark for a reset. */
dev->in_reset = 1;
esdi_mca_set_callback(dev, ESDI_TIME * 50);
dev->status = STATUS_BUSY;
/* Set the reply timer. */
timer_add(&dev->timer, esdi_callback, dev, 0);
return dev;
}
static void
esdi_close(void *priv)
{
esdi_t *dev = (esdi_t *) priv;
const drive_t *drive;
dev->drives[0].present = dev->drives[1].present = 0;
for (uint8_t d = 0; d < 2; d++) {
drive = &dev->drives[d];
hdd_image_close(drive->hdd_num);
}
free(dev);
}
static int
esdi_available(void)
{
return (rom_present(BIOS_FILE_L) && rom_present(BIOS_FILE_H));
}
const device_t esdi_ps2_device = {
.name = "IBM PS/2 ESDI Fixed Disk Adapter (MCA)",
.internal_name = "esdi_mca",
.flags = DEVICE_MCA,
.local = 0,
.init = esdi_init,
.close = esdi_close,
.reset = NULL,
{ .available = esdi_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_esdi_mca.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,423 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Winbond W83769F controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/cdrom.h>
#include <86box/scsi_device.h>
#include <86box/scsi_cdrom.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/mo.h>
typedef struct w83769f_t {
uint8_t vlb_idx;
uint8_t id;
uint8_t in_cfg;
uint8_t channels;
uint8_t pci;
uint8_t pci_slot;
uint8_t pad;
uint8_t pad0;
uint8_t regs[256];
} w83769f_t;
static int next_id = 0;
#ifdef ENABLE_W83769F_LOG
int w83769f_do_log = ENABLE_W83769F_LOG;
static void
w83769f_log(const char *fmt, ...)
{
va_list ap;
if (w83769f_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define w83769f_log(fmt, ...)
#endif
void
w83769f_set_irq_0(uint8_t status, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
int irq = !!(status & 0x04);
if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
if (!(dev->channels & 1))
return;
if (irq)
picint(1 << 14);
else
picintc(1 << 14);
}
void
w83769f_set_irq_1(uint8_t status, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
int irq = !!(status & 0x04);
if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
if (!(dev->channels & 2))
return;
if (irq)
picint(1 << 15);
else
picintc(1 << 15);
}
static void
w83769f_ide_handlers(w83769f_t *dev)
{
if (dev->channels & 0x01) {
ide_pri_disable();
if (!dev->pci || (dev->regs[0x04] & 0x01))
ide_pri_enable();
}
if (dev->channels & 0x02) {
ide_sec_disable();
if ((!dev->pci || (dev->regs[0x04] & 0x01)) && (dev->regs[0x57] & 0x01))
ide_sec_enable();
}
}
static void
w83769f_common_write(int addr, uint8_t val, w83769f_t *dev)
{
switch (addr) {
case 0x50:
case 0x57:
dev->regs[0x57] = val & 0x01;
w83769f_ide_handlers(dev);
break;
case 0x51:
dev->regs[addr] = val & 0x7f;
break;
case 0x52:
case 0x54:
case 0x56:
case 0x58 ... 0x59:
dev->regs[addr] = val;
break;
case 0x53:
case 0x55:
dev->regs[addr] = val & 0xcf;
break;
default:
break;
}
}
static void
w83769f_vlb_write(uint16_t addr, uint8_t val, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
switch (addr) {
case 0x0034:
case 0x00b4:
dev->vlb_idx = val;
break;
case 0x0038:
case 0x00b8:
w83769f_common_write(dev->vlb_idx, val, dev);
break;
default:
break;
}
}
static void
w83769f_vlb_writew(uint16_t addr, uint16_t val, void *priv)
{
w83769f_vlb_write(addr, val & 0xff, priv);
w83769f_vlb_write(addr + 1, val >> 8, priv);
}
static void
w83769f_vlb_writel(uint16_t addr, uint32_t val, void *priv)
{
w83769f_vlb_writew(addr, val & 0xffff, priv);
w83769f_vlb_writew(addr + 2, val >> 16, priv);
}
static uint8_t
w83769f_vlb_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
w83769f_t *dev = (w83769f_t *) priv;
switch (addr) {
case 0x0034:
case 0x00b4:
ret = dev->vlb_idx;
break;
case 0x0038:
case 0x00b8:
ret = dev->regs[dev->vlb_idx];
if (dev->vlb_idx == 0x50)
dev->regs[0x50] &= ~0x04;
break;
default:
break;
}
return ret;
}
static uint16_t
w83769f_vlb_readw(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = w83769f_vlb_read(addr, priv);
ret |= (w83769f_vlb_read(addr + 1, priv) << 8);
return ret;
}
static uint32_t
w83769f_vlb_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = w83769f_vlb_readw(addr, priv);
ret |= (w83769f_vlb_readw(addr + 2, priv) << 16);
return ret;
}
static void
w83769f_pci_write(int func, int addr, uint8_t val, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
w83769f_log("w83769f_pci_write(%i, %02X, %02X)\n", func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
dev->regs[addr] = (dev->regs[addr] & 0xbf) | (val & 0x40);
w83769f_ide_handlers(dev);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0x80);
break;
}
}
static uint8_t
w83769f_pci_read(int func, int addr, void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
ret = dev->regs[addr];
w83769f_log("w83769f_pci_read(%i, %02X, %02X)\n", func, addr, ret);
return ret;
}
static void
w83769f_reset(void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
int i = 0;
int min_channel;
int max_channel;
switch (dev->channels) {
default:
case 0x00:
min_channel = max_channel = 0;
break;
case 0x01:
min_channel = 0;
max_channel = 1;
break;
case 0x02:
min_channel = 2;
max_channel = 3;
break;
case 0x03:
min_channel = 0;
max_channel = 3;
break;
}
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel >= min_channel) &&
(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
(mo_drives[i].ide_channel <= max_channel) && mo_drives[i].priv)
mo_reset((scsi_common_t *) mo_drives[i].priv);
}
if (dev->channels & 0x01)
w83769f_set_irq_0(0x00, priv);
if (dev->channels & 0x02)
w83769f_set_irq_1(0x00, priv);
memset(dev->regs, 0x00, sizeof(dev->regs));
dev->regs[0x50] = (dev->id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
dev->regs[0x51] = 0x40;
dev->regs[0x57] = 0x01; /* Required by the MSI MS-5109 */
dev->regs[0x59] = 0x40;
if (dev->pci) {
dev->regs[0x00] = 0xad; /* Winbond */
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x01; /* W83769 */
dev->regs[0x03] = 0x00;
dev->regs[0x04] = 0x01;
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x08] = 0x02; /* 00h for Rev BB, 02h for Rev A3C */
dev->regs[0x09] = 0x00; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
dev->regs[0x0b] = 0x01; /* Mass storage controller */
dev->regs[0x3c] = 0x0e; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
} else
dev->regs[0x04] = 0x01; /* To make sure the two channels get enabled. */
w83769f_ide_handlers(dev);
}
static void
w83769f_close(void *priv)
{
w83769f_t *dev = (w83769f_t *) priv;
free(dev);
next_id = 0;
}
static void *
w83769f_init(const device_t *info)
{
w83769f_t *dev = (w83769f_t *) malloc(sizeof(w83769f_t));
memset(dev, 0x00, sizeof(w83769f_t));
dev->id = next_id | 0x60;
dev->pci = !!(info->flags & DEVICE_PCI);
dev->channels = ((info->local & 0x60000) >> 17) & 0x03;
if (info->flags & DEVICE_PCI) {
device_add(&ide_pci_2ch_device);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, w83769f_pci_read, w83769f_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_IDE, w83769f_pci_read, w83769f_pci_write, dev, &dev->pci_slot);
} else if (info->flags & DEVICE_VLB)
device_add(&ide_vlb_2ch_device);
if (dev->channels & 0x01)
ide_set_bus_master(0, NULL, w83769f_set_irq_0, dev);
if (dev->channels & 0x02)
ide_set_bus_master(1, NULL, w83769f_set_irq_1, dev);
/* The CMD PCI-0640B IDE controller has no DMA capability,
so set our devices IDE devices to force ATA-3 (no DMA). */
if (dev->channels & 0x01)
ide_board_set_force_ata3(0, 1);
if (dev->channels & 0x02)
ide_board_set_force_ata3(1, 1);
io_sethandler(info->local & 0xffff, 0x0001,
w83769f_vlb_read, w83769f_vlb_readw, w83769f_vlb_readl,
w83769f_vlb_write, w83769f_vlb_writew, w83769f_vlb_writel,
dev);
io_sethandler((info->local & 0xffff) + 0x0004, 0x0001,
w83769f_vlb_read, w83769f_vlb_readw, w83769f_vlb_readl,
w83769f_vlb_write, w83769f_vlb_writew, w83769f_vlb_writel,
dev);
next_id++;
w83769f_reset(dev);
return dev;
}
const device_t ide_w83769f_vlb_device = {
.name = "Winbond W83769F VLB",
.internal_name = "ide_w83769f_vlb",
.flags = DEVICE_VLB,
.local = 0x600b4,
.init = w83769f_init,
.close = w83769f_close,
.reset = w83769f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_w83769f_vlb_34_device = {
.name = "Winbond W83769F VLB (Port 34h)",
.internal_name = "ide_w83769f_vlb_34",
.flags = DEVICE_VLB,
.local = 0x60034,
.init = w83769f_init,
.close = w83769f_close,
.reset = w83769f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_w83769f_pci_device = {
.name = "Winbond W83769F PCI",
.internal_name = "ide_w83769f_pci",
.flags = DEVICE_PCI,
.local = 0x600b4,
.init = w83769f_init,
.close = w83769f_close,
.reset = w83769f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_w83769f_pci_34_device = {
.name = "Winbond W83769F PCI (Port 34h)",
.internal_name = "ide_w83769f_pci_34",
.flags = DEVICE_PCI,
.local = 0x60034,
.init = w83769f_init,
.close = w83769f_close,
.reset = w83769f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_w83769f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,946 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC UMF8673F IDE controller.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/hdc_ide.h>
#include <86box/hdc.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_UM8673F_LOG
int um8673f_do_log = ENABLE_UM8673F_LOG;
static void
um8673f_log(const char *fmt, ...)
{
va_list ap;
if (um8673f_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define um8673f_log(fmt, ...)
#endif
typedef struct um8673f_t {
uint8_t index;
uint8_t tries;
uint8_t unlocked;
uint8_t regs[256];
} um8673f_t;
static void
um8673f_ide_handler(um8673f_t *dev)
{
ide_pri_disable();
ide_sec_disable();
if (dev->regs[0xb0] & 0x80)
ide_pri_enable();
if (dev->regs[0xb0] & 0x40)
ide_sec_enable();
}
static void
um8673f_write(uint16_t addr, uint8_t val, void *priv)
{
um8673f_t *dev = (um8673f_t *) priv;
um8673f_log("[%04X:%08X] [W] %02X = %02X (%i)\n", CS, cpu_state.pc, addr, val, dev->tries);
switch (addr) {
case 0x108:
if (dev->unlocked) {
if (dev->index == 0x34) {
dev->unlocked = 0;
dev->tries = 0;
} else
dev->index = val;
} else if (((dev->tries == 0) && (val == 0x4a)) ||
((dev->tries == 1) && (val == 0x6c))) {
dev->tries++;
if (dev->tries == 2)
dev->unlocked = 1;
} else
dev->tries = 0;
break;
case 0x109:
switch (dev->index) {
case 0xb0:
dev->regs[dev->index] = val;
um8673f_ide_handler(dev);
break;
case 0xb1 ... 0xb8:
dev->regs[dev->index] = val;
break;
default:
break;
}
break;
default:
break;
}
}
static uint8_t
um8673f_read(uint16_t addr, void *priv)
{
um8673f_t *dev = (um8673f_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x108:
if (dev->unlocked)
ret = dev->index;
else
dev->tries = 0;
break;
case 0x109:
if ((dev->index >= 0xb0) && (dev->index <= 0xb8))
ret = dev->regs[dev->index];
break;
default:
break;
}
um8673f_log("[%04X:%08X] [R] %02X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static void
um8673f_reset(void *priv)
{
um8673f_t *dev = (um8673f_t *) priv;
memset(dev->regs, 0x00, 256);
ide_pri_disable();
ide_sec_disable();
/* IDE registers */
dev->regs[0xb0] = 0xc0;
um8673f_ide_handler(dev);
}
static void
um8673f_close(void *priv)
{
um8673f_t *dev = (um8673f_t *) priv;
free(dev);
}
static void *
um8673f_init(UNUSED(const device_t *info))
{
um8673f_t *dev = (um8673f_t *) calloc(1, sizeof(um8673f_t));
io_sethandler(0x0108, 0x0002, um8673f_read, NULL, NULL, um8673f_write, NULL, NULL, dev);
device_add(info->local ? &ide_pci_2ch_device : &ide_vlb_2ch_device);
um8673f_reset(dev);
return dev;
}
const device_t ide_um8886af_device = {
.name = "UMC UM8886F IDE",
.internal_name = "um8886af_ide",
.flags = 0,
.local = 1,
.init = um8673f_init,
.close = um8673f_close,
.reset = um8673f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_um8673f_device = {
.name = "UMC UM8673F",
.internal_name = "um8673f",
.flags = 0,
.local = 0,
.init = um8673f_init,
.close = um8673f_close,
.reset = um8673f_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_ide_um8673f.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,452 |
```objective-c
/*
* MiniVHD Minimalist VHD implementation in C.
* MiniVHD is a minimalist implementation of read/write/creation
* of VHD files. It is designed to read and write to VHD files
* at a sector level. It does not enable file access, or provide
* mounting options. Those features are left to more advanced
* libraries and/or the operating system.
*
* This file is part of the MiniVHD Project.
*
* Definitions for the MiniVHD library.
*
* Version: @(#)minivhd.h 1.0.3 2021/04/16
*
* Authors: Sherman Perry, <shermperry@gmail.com>
* Fred N. van Kempen, <waltje@varcem.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MINIVHD_H
# define MINIVHD_H
typedef enum MVHDError {
MVHD_ERR_MEM = -128,
MVHD_ERR_FILE,
MVHD_ERR_NOT_VHD,
MVHD_ERR_TYPE,
MVHD_ERR_FOOTER_CHECKSUM,
MVHD_ERR_SPARSE_CHECKSUM,
MVHD_ERR_UTF_TRANSCODING_FAILED,
MVHD_ERR_UTF_SIZE,
MVHD_ERR_PATH_REL,
MVHD_ERR_PATH_LEN,
MVHD_ERR_PAR_NOT_FOUND,
MVHD_ERR_INVALID_PAR_UUID,
MVHD_ERR_INVALID_GEOM,
MVHD_ERR_INVALID_SIZE,
MVHD_ERR_INVALID_BLOCK_SIZE,
MVHD_ERR_INVALID_PARAMS,
MVHD_ERR_CONV_SIZE,
MVHD_ERR_TIMESTAMP
} MVHDError;
typedef enum MVHDType {
MVHD_TYPE_FIXED = 2,
MVHD_TYPE_DYNAMIC = 3,
MVHD_TYPE_DIFF = 4
} MVHDType;
typedef enum MVHDBlockSize {
MVHD_BLOCK_DEFAULT = 0, /**< 2 MB blocks */
MVHD_BLOCK_SMALL = 1024, /**< 512 KB blocks */
MVHD_BLOCK_LARGE = 4096 /**< 2 MB blocks */
} MVHDBlockSize;
typedef struct MVHDGeom {
uint16_t cyl;
uint8_t heads;
uint8_t spt;
} MVHDGeom;
#ifdef __cplusplus
extern "C" {
#endif
typedef void (*mvhd_progress_callback)(uint32_t current_sector, uint32_t total_sectors);
typedef struct MVHDCreationOptions {
int type; /** MVHD_TYPE_FIXED, MVHD_TYPE_DYNAMIC, or MVHD_TYPE_DIFF */
char* path; /** Absolute path of the new VHD file */
char* parent_path; /** For MVHD_TYPE_DIFF, this is the absolute path of the VHD's parent. For non-diff VHDs, this should be NULL. */
uint64_t size_in_bytes; /** Total size of the VHD's virtual disk in bytes. Must be a multiple of 512. If 0, the size is auto-calculated from the geometry field. Ignored for MVHD_TYPE_DIFF. */
MVHDGeom geometry; /** The geometry of the VHD. If set to 0, the geometry is auto-calculated from the size_in_bytes field. */
uint32_t block_size_in_sectors; /** MVHD_BLOCK_LARGE or MVHD_BLOCK_SMALL, or 0 for the default value. The number of sectors per block. */
mvhd_progress_callback progress_callback; /** Optional; if not NULL, gets called to indicate progress on the creation operation. Only applies to MVHD_TYPE_FIXED. */
} MVHDCreationOptions;
typedef struct MVHDMeta MVHDMeta;
extern int mvhd_errno;
/* Shared-library madness. */
//#if defined(_WIN32)
//# ifdef STATIC
# define MVHDAPI /*nothing*/
//# else
//# ifdef BUILDING_LIBRARY
//# define MVHDAPI __declspec(dllexport)
//# else
//# define MVHDAPI __declspec(dllimport)
//# endif
//# endif
//#elif defined(__GNUC__)
//# ifdef BUILDING_LIBRARY
//# define MVHDAPI __attribute__((visibility("default")))
//# else
//# define MVHDAPI /*nothing*/
//# endif
//#else
//# define MVHDAPI /*nothing*/
//#endif
/**
* \brief Return the library version as a string
*/
MVHDAPI const char *mvhd_version(void);
/**
* \brief Return the library version as a number
*/
MVHDAPI uint32_t mvhd_version_id(void);
/**
* \brief Output a string from a MiniVHD error number
*
* \param [in] err is the error number to return string from
*
* \return Error string
*/
MVHDAPI const char* mvhd_strerr(MVHDError err);
/**
* \brief A simple test to see if a given file is a VHD
*
* \param [in] f file to test
*
* \retval 1 if f is a VHD
* \retval 0 if f is not a VHD
*/
MVHDAPI int mvhd_file_is_vhd(FILE* f);
/**
* \brief Return the file type of the given file
*
* \param [in] vhdm VHD to check.
*
* \retval one of the defined MVHDType values
*/
MVHDAPI MVHDType mvhd_get_type(MVHDMeta* vhdm);
/**
* \brief Open a VHD image for reading and/or writing
*
* The returned pointer contains all required values and structures (and files) to
* read and write to a VHD file.
*
* Remember to call mvhd_close() when you are finished.
*
* \param [in] Absolute path to VHD file. Relative path will cause issues when opening
* a differencing VHD file
* \param [in] readonly set this to 1 to open the VHD in a read only manner
* \param [out] err will be set if the VHD fails to open. Value could be one of
* MVHD_ERR_MEM, MVHD_ERR_FILE, MVHD_ERR_NOT_VHD, MVHD_ERR_FOOTER_CHECKSUM, MVHD_ERR_SPARSE_CHECKSUM,
* MVHD_ERR_TYPE, MVHD_ERR_TIMESTAMP
* If MVHD_ERR_FILE is set, mvhd_errno will be set to the appropriate system errno value
*
* \return MVHDMeta pointer. If NULL, check err. err may also be set to MVHD_ERR_TIMESTAMP if
* opening a differencing VHD.
*/
MVHDAPI MVHDMeta* mvhd_open(const char* path, int readonly, int* err);
/**
* \brief Update the parent modified timestamp in the VHD file
*
* Differencing VHD's use a parent last modified timestamp to try and detect if the
* parent has been modified after the child has been created. However, this is rather
* fragile and can be broken by moving/copying the parent. Also, MS DiskPart does not
* set this timestamp in the child :(
*
* Be careful when using this function that you don't update the timestamp after the
* parent actually has been modified.
*
* \param [in] vhdm Differencing VHD to update.
* \param [out] err will be set if the timestamp could not be updated
*
* \return non-zero on error, 0 on success
*/
MVHDAPI int mvhd_diff_update_par_timestamp(MVHDMeta* vhdm, int* err);
/**
* \brief Create a fixed VHD image
*
* \param [in] path is the absolute path to the image to create
* \param [in] geom is the HDD geometry of the image to create. Determines final image size
* \param [out] err indicates what error occurred, if any
* \param [out] progress_callback optional; if not NULL, gets called to indicate progress on the creation operation
*
* \retval NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_create_fixed(const char* path, MVHDGeom geom, int* err, mvhd_progress_callback progress_callback);
/**
* \brief Create sparse (dynamic) VHD image.
*
* \param [in] path is the absolute path to the VHD file to create
* \param [in] geom is the HDD geometry of the image to create. Determines final image size
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_create_sparse(const char* path, MVHDGeom geom, int* err);
/**
* \brief Create differencing VHD imagee.
*
* \param [in] path is the absolute path to the VHD file to create
* \param [in] par_path is the absolute path to a parent image. If NULL, a sparse image is created, otherwise create a differencing image
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_create_diff(const char* path, const char* par_path, int* err);
/**
* \brief Create a VHD using the provided options
*
* Use mvhd_create_ex if you want more control over the VHD's options. For quick creation, you can use mvhd_create_fixed, mvhd_create_sparse, or mvhd_create_diff.
*
* \param [in] options the VHD creation options.
* \param [out] err indicates what error occurred, if any
*
* \retval NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_create_ex(MVHDCreationOptions options, int* err);
/**
* \brief Safely close a VHD image
*
* \param [in] vhdm MiniVHD data structure to close
*/
MVHDAPI void mvhd_close(MVHDMeta* vhdm);
/**
* \brief Calculate hard disk geometry from a provided size
*
* The VHD format uses Cylinder, Heads, Sectors per Track (CHS) when accessing the disk.
* The size of the disk can be determined from C * H * S * sector_size.
*
* Note, maximum geometry size (in bytes) is 65535 * 16 * 255 * 512, which is 127GB.
* However, the maximum VHD size is 2040GB. For VHDs larger than 127GB, the geometry size will be
* smaller than the actual VHD size.
*
* This function determines the appropriate CHS geometry from a provided size in bytes.
* The calculations used are those provided in "Appendix: CHS Calculation" from the document
* "Virtual Hard Disk Image Format Specification" provided by Microsoft.
*
* \param [in] size the desired VHD image size, in bytes
*
* \return MVHDGeom the calculated geometry. This can be used in the appropriate create functions.
*/
MVHDAPI MVHDGeom mvhd_calculate_geometry(uint64_t size);
/**
* \brief Get the CHS geometry from the image
*
* \param [in] vhdm MiniVHD data structure
*
* \return The CHS geometry as stored in the image
*/
MVHDAPI MVHDGeom mvhd_get_geometry(MVHDMeta* vhdm);
/**
* \brief Get the 'current_size' value from the image
*
* Note that the size returned may not match the size calculated from the
* CHS geometry. It is up to the caller to decide how best to handle this.
*
* \param [in] vhdm MiniVHD data structure
*
* \return The 'current_size' value in bytes, as stored in the image.
* Note, this may not match the CHS geometry.
*/
MVHDAPI uint64_t mvhd_get_current_size(MVHDMeta* vhdm);
/**
* \brief Calculate CHS geometry size in bytes
*
* \param [in] geom the CHS geometry to calculate
*
* \return the size in bytes
*/
MVHDAPI uint64_t mvhd_calc_size_bytes(MVHDGeom *geom);
/**
* \brief Calculate CHS geometry size in sectors
*
* \param [in] geom the CHS geometry to calculate
*
* \return the size in sectors
*/
MVHDAPI uint32_t mvhd_calc_size_sectors(MVHDGeom *geom);
/**
* \brief Convert a raw disk image to a fixed VHD image
*
* \param [in] utf8_raw_path is the path of the raw image to convert
* \param [in] utf8_vhd_path is the path of the VHD to create
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_convert_to_vhd_fixed(const char* utf8_raw_path, const char* utf8_vhd_path, int* err);
/**
* \brief Convert a raw disk image to a sparse VHD image
*
* \param [in] utf8_raw_path is the path of the raw image to convert
* \param [in] utf8_vhd_path is the path of the VHD to create
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
MVHDAPI MVHDMeta* mvhd_convert_to_vhd_sparse(const char* utf8_raw_path, const char* utf8_vhd_path, int* err);
/**
* \brief Convert a VHD image to a raw disk image
*
* \param [in] utf8_vhd_path is the path of the VHD to convert
* \param [in] utf8_raw_path is the path of the raw image to create
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns the raw disk image FILE pointer
*/
MVHDAPI FILE* mvhd_convert_to_raw(const char* utf8_vhd_path, const char* utf8_raw_path, int *err);
/**
* \brief Read sectors from VHD file
*
* Read num_sectors, beginning at offset from the VHD file into a buffer
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset the sector offset from which to start reading from
* \param [in] num_sectors the number of sectors to read
* \param [out] out_buff the buffer to write sector data to
*
* \return the number of sectors that were not read, or zero
*/
MVHDAPI int mvhd_read_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* out_buff);
/**
* \brief Write sectors to VHD file
*
* Write num_sectors, beginning at offset from a buffer VHD file into the VHD file
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset the sector offset from which to start writing to
* \param [in] num_sectors the number of sectors to write
* \param [in] in_buffer the buffer to write sector data to
*
* \return the number of sectors that were not written, or zero
*/
MVHDAPI int mvhd_write_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* in_buff);
/**
* \brief Write zeroed sectors to VHD file
*
* Write num_sectors, beginning at offset, of zero data into the VHD file.
* We reuse the existing write functions, with a preallocated zero buffer as
* our source buffer.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset the sector offset from which to start writing to
* \param [in] num_sectors the number of sectors to write
*
* \return the number of sectors that were not written, or zero
*/
MVHDAPI int mvhd_format_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors);
#ifdef __cplusplus
}
#endif
#endif /*MINIVHD_H*/
``` | /content/code_sandbox/src/disk/minivhd/minivhd.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,893 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Driver for the ESDI controller (WD1007-vse1) for PC/AT.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#define _GNU_SOURCE
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pic.h>
#include <86box/rom.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#define HDC_TIME 10.0
#define BIOS_FILE "roms/hdd/esdi_at/62-000279-061.bin"
#define STAT_ERR 0x01
#define STAT_INDEX 0x02
#define STAT_CORRECTED_DATA 0x04
#define STAT_DRQ 0x08 /* Data request */
#define STAT_DSC 0x10
#define STAT_SEEK_COMPLETE 0x20
#define STAT_READY 0x40
#define STAT_BUSY 0x80
#define ERR_DAM_NOT_FOUND 0x01 /* Data Address Mark not found */
#define ERR_TR000 0x02 /* track 0 not found */
#define ERR_ABRT 0x04 /* command aborted */
#define ERR_ID_NOT_FOUND 0x10 /* ID not found */
#define ERR_DATA_CRC 0x40 /* data CRC error */
#define ERR_BAD_BLOCK 0x80 /* bad block detected */
#define CMD_NOP 0x00
#define CMD_RESTORE 0x10
#define CMD_READ 0x20
#define CMD_WRITE 0x30
#define CMD_VERIFY 0x40
#define CMD_FORMAT 0x50
#define CMD_SEEK 0x70
#define CMD_DIAGNOSE 0x90
#define CMD_SET_PARAMETERS 0x91
#define CMD_READ_PARAMETERS 0xec
typedef struct drive_t {
int cfg_spt;
int cfg_hpc;
int current_cylinder;
int real_spt;
int real_hpc;
int real_tracks;
int present;
int hdd_num;
} drive_t;
typedef struct esdi_t {
uint8_t status;
uint8_t error;
int secount;
int sector;
int cylinder;
int head;
int cylprecomp;
uint8_t command;
uint8_t fdisk;
int pos;
int drive_sel;
int reset;
uint16_t buffer[256];
int irqstat;
pc_timer_t callback_timer;
drive_t drives[2];
rom_t bios_rom;
} esdi_t;
static uint8_t esdi_read(uint16_t port, void *priv);
static void esdi_write(uint16_t port, uint8_t val, void *priv);
#ifdef ENABLE_ESDI_AT_LOG
int esdi_at_do_log = ENABLE_ESDI_AT_LOG;
static void
esdi_at_log(const char *fmt, ...)
{
va_list ap;
if (esdi_at_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define esdi_at_log(fmt, ...)
#endif
static __inline void
irq_raise(esdi_t *esdi)
{
esdi->irqstat = 1;
if (!(esdi->fdisk & 2))
picint_common(1 << 14, PIC_IRQ_EDGE, 1, NULL);
}
static __inline void
irq_lower(esdi_t *esdi)
{
esdi->irqstat = 0;
if (!(esdi->fdisk & 2))
picint_common(1 << 14, PIC_IRQ_EDGE, 0, NULL);
}
static __inline void
irq_update(esdi_t *esdi)
{
uint8_t set = !(esdi->fdisk & 2) && esdi->irqstat;
picint_common(1 << 14, PIC_IRQ_EDGE, set, NULL);
}
static void
esdi_set_callback(esdi_t *esdi, double callback)
{
if (!esdi) {
esdi_at_log("esdi_set_callback(NULL): Set callback failed\n");
return;
}
if (callback == 0.0)
timer_stop(&esdi->callback_timer);
else
timer_on_auto(&esdi->callback_timer, callback);
}
double
esdi_get_xfer_time(UNUSED(esdi_t *esdi), int size)
{
/* 390.625 us per sector at 10 Mbit/s = 1280 kB/s. */
return (3125.0 / 8.0) * (double) size;
}
/* Return the sector offset for the current register values. */
static int
get_sector(esdi_t *esdi, off64_t *addr)
{
const drive_t *drive = &esdi->drives[esdi->drive_sel];
int heads = drive->cfg_hpc;
int sectors = drive->cfg_spt;
int c;
int h;
int s;
int sector;
if (esdi->head > heads) {
esdi_at_log("esdi_get_sector: past end of configured heads\n");
return 1;
}
if (esdi->sector >= sectors + 1) {
esdi_at_log("esdi_get_sector: past end of configured sectors\n");
return 1;
}
sector = esdi->sector ? esdi->sector : 1;
if (drive->cfg_spt == drive->real_spt && drive->cfg_hpc == drive->real_hpc) {
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) * sectors) + (sector - 1);
} else {
/*
* When performing translation, the firmware seems to leave 1
* sector per track inaccessible (spare sector)
*/
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) * sectors) + (sector - 1);
s = *addr % (drive->real_spt - 1);
h = (*addr / (drive->real_spt - 1)) % drive->real_hpc;
c = (*addr / (drive->real_spt - 1)) / drive->real_hpc;
*addr = ((((off64_t) c * drive->real_hpc) + h) * drive->real_spt) + s;
}
return 0;
}
static int
get_sector_format(esdi_t *esdi, off64_t *addr)
{
const drive_t *drive = &esdi->drives[esdi->drive_sel];
int heads = drive->cfg_hpc;
int sectors = drive->cfg_spt;
int c;
int h;
int s;
if (esdi->head > heads) {
esdi_at_log("esdi_get_sector: past end of configured heads\n");
return 1;
}
if (drive->cfg_spt == drive->real_spt && drive->cfg_hpc == drive->real_hpc) {
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) * sectors);
} else {
/*
* When performing translation, the firmware seems to leave 1
* sector per track inaccessible (spare sector)
*/
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) * sectors);
s = *addr % (drive->real_spt - 1);
h = (*addr / (drive->real_spt - 1)) % drive->real_hpc;
c = (*addr / (drive->real_spt - 1)) / drive->real_hpc;
*addr = ((((off64_t) c * drive->real_hpc) + h) * drive->real_spt) + s;
}
return 0;
}
/* Move to the next sector using CHS addressing. */
static void
next_sector(esdi_t *esdi)
{
drive_t *drive = &esdi->drives[esdi->drive_sel];
esdi->sector++;
if (esdi->sector == (drive->cfg_spt + 1)) {
esdi->sector = 1;
if (++esdi->head == drive->cfg_hpc) {
esdi->head = 0;
esdi->cylinder++;
if (drive->current_cylinder < drive->real_tracks)
drive->current_cylinder++;
}
}
}
static void
esdi_writew(uint16_t port, uint16_t val, void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
off64_t addr;
if (port > 0x01f0) {
esdi_write(port, val & 0xff, priv);
if (port != 0x01f7)
esdi_write(port + 1, (val >> 8) & 0xff, priv);
} else {
esdi->buffer[esdi->pos >> 1] = val;
esdi->pos += 2;
if (esdi->pos >= 512) {
esdi->pos = 0;
esdi->status = STAT_BUSY;
get_sector(esdi, &addr);
double seek_time = hdd_timing_write(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, 1);
double xfer_time = esdi_get_xfer_time(esdi, 1);
esdi_set_callback(esdi, seek_time + xfer_time);
}
}
}
static void
esdi_write(uint16_t port, uint8_t val, void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
double seek_time;
double xfer_time;
off64_t addr;
uint8_t old;
esdi_at_log("WD1007 write(%04x, %02x)\n", port, val);
switch (port) {
case 0x1f0: /* data */
esdi_writew(port, val | (val << 8), priv);
return;
case 0x1f1: /* write precompensation */
esdi->cylprecomp = val;
return;
case 0x1f2: /* sector count */
esdi->secount = val;
return;
case 0x1f3: /* sector */
esdi->sector = val;
return;
case 0x1f4: /* cylinder low */
esdi->cylinder = (esdi->cylinder & 0xFF00) | val;
return;
case 0x1f5: /* cylinder high */
esdi->cylinder = (esdi->cylinder & 0xFF) | (val << 8);
return;
case 0x1f6: /* drive/Head */
esdi->head = val & 0xF;
esdi->drive_sel = (val & 0x10) ? 1 : 0;
if (esdi->drives[esdi->drive_sel].present)
esdi->status = STAT_READY | STAT_DSC;
else
esdi->status = 0;
return;
case 0x1f7: /* command register */
irq_lower(esdi);
esdi->command = val;
esdi->error = 0;
esdi_at_log("WD1007: command %02x\n", val & 0xf0);
switch (val & 0xf0) {
case CMD_RESTORE:
esdi->command &= ~0x0f; /*mask off step rate*/
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 200 * HDC_TIME);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case CMD_SEEK:
esdi->command &= ~0x0f; /*mask off step rate*/
esdi->status = STAT_BUSY;
get_sector(esdi, &addr);
seek_time = hdd_seek_get_time(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, HDD_OP_SEEK, 0, 0.0);
esdi_set_callback(esdi, seek_time);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
default:
switch (val) {
case CMD_NOP:
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 200 * HDC_TIME);
break;
case CMD_READ:
case CMD_READ + 1:
case CMD_READ + 2:
case CMD_READ + 3:
esdi->command &= ~0x03;
if (val & 0x02)
fatal("Read with ECC\n");
fallthrough;
case 0xa0:
esdi->status = STAT_BUSY;
get_sector(esdi, &addr);
seek_time = hdd_timing_read(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, 1);
xfer_time = esdi_get_xfer_time(esdi, 1);
esdi_set_callback(esdi, seek_time + xfer_time);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case CMD_WRITE:
case CMD_WRITE + 1:
case CMD_WRITE + 2:
case CMD_WRITE + 3:
esdi->command &= ~0x03;
if (val & 0x02)
fatal("Write with ECC\n");
esdi->status = STAT_READY | STAT_DRQ | STAT_DSC;
esdi->pos = 0;
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case CMD_VERIFY:
case CMD_VERIFY + 1:
esdi->command &= ~0x01;
esdi->status = STAT_BUSY;
get_sector(esdi, &addr);
seek_time = hdd_timing_read(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, 1);
xfer_time = esdi_get_xfer_time(esdi, 1);
esdi_set_callback(esdi, seek_time + xfer_time);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case CMD_FORMAT:
esdi->status = STAT_DRQ;
esdi->pos = 0;
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case CMD_SET_PARAMETERS: /* Initialize Drive Parameters */
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 30 * HDC_TIME);
break;
case CMD_DIAGNOSE: /* Execute Drive Diagnostics */
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 200 * HDC_TIME);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
break;
case 0xe0: /*???*/
case CMD_READ_PARAMETERS:
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 200 * HDC_TIME);
break;
default:
esdi_at_log("WD1007: bad command %02X\n", val);
fallthrough;
case 0xe8: /*???*/
esdi->status = STAT_BUSY;
esdi_set_callback(esdi, 200 * HDC_TIME);
break;
}
}
break;
case 0x3f6: /* Device control */
if ((esdi->fdisk & 0x04) && !(val & 0x04)) {
esdi_set_callback(esdi, 500 * HDC_TIME);
esdi->reset = 1;
esdi->status = STAT_BUSY;
} else if (!(esdi->fdisk & 0x04) && (val & 0x04)) {
/* Drive held in reset. */
esdi_set_callback(esdi, 0);
esdi->status = STAT_BUSY;
}
old = esdi->fdisk;
esdi->fdisk = val;
if (!(val & 0x02) && (old & 0x02))
irq_update(esdi);
break;
default:
break;
}
}
static uint16_t
esdi_readw(uint16_t port, void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
uint16_t temp;
off64_t addr;
if (port > 0x01f0) {
temp = esdi_read(port, priv);
if (port == 0x01f7)
temp |= 0xff00;
else
temp |= (esdi_read(port + 1, priv) << 8);
} else {
temp = esdi->buffer[esdi->pos >> 1];
esdi->pos += 2;
if (esdi->pos >= 512) {
esdi->pos = 0;
esdi->status = STAT_READY | STAT_DSC;
if (esdi->command == CMD_READ || esdi->command == 0xa0) {
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount) {
next_sector(esdi);
esdi->status = STAT_BUSY;
get_sector(esdi, &addr);
double seek_time = hdd_timing_read(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, 1);
double xfer_time = esdi_get_xfer_time(esdi, 1);
/* 390.625 us per sector at 10 Mbit/s = 1280 kB/s. */
esdi_set_callback(esdi, seek_time + xfer_time);
} else
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
}
}
return temp;
}
static uint8_t
esdi_read(uint16_t port, void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
uint8_t temp = 0xff;
switch (port) {
case 0x1f0: /* data */
temp = esdi_readw(port, esdi) & 0xff;
break;
case 0x1f1: /* error */
temp = esdi->error;
break;
case 0x1f2: /* sector count */
temp = esdi->secount;
break;
case 0x1f3: /* sector */
temp = esdi->sector;
break;
case 0x1f4: /* cylinder low */
temp = (uint8_t) (esdi->cylinder & 0xff);
break;
case 0x1f5: /* cylinder high */
temp = (uint8_t) (esdi->cylinder >> 8);
break;
case 0x1f6: /* drive/Head */
temp = (uint8_t) (esdi->head | (esdi->drive_sel ? 0x10 : 0) | 0xa0);
break;
case 0x1f7: /* status */
irq_lower(esdi);
temp = esdi->status;
break;
default:
break;
}
esdi_at_log("WD1007 read(%04x) = %02x\n", port, temp);
return temp;
}
static void
esdi_callback(void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
drive_t *drive = &esdi->drives[esdi->drive_sel];
off64_t addr;
double seek_time;
if (esdi->reset) {
esdi->status = STAT_READY | STAT_DSC;
esdi->error = 1;
esdi->secount = 1;
esdi->sector = 1;
esdi->head = 0;
esdi->cylinder = 0;
esdi->reset = 0;
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
return;
}
esdi_at_log("WD1007: command %02x on drive %i\n", esdi->command, esdi->drive_sel);
switch (esdi->command) {
case CMD_RESTORE:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
} else {
drive->current_cylinder = 0;
esdi->status = STAT_READY | STAT_DSC;
}
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_SEEK:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
} else
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_READ:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
} else {
if (get_sector(esdi, &addr)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_read(drive->hdd_num, addr, 1, (uint8_t *) esdi->buffer);
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
irq_raise(esdi);
}
break;
case CMD_WRITE:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
} else {
if (get_sector(esdi, &addr)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
}
hdd_image_write(drive->hdd_num, addr, 1, (uint8_t *) esdi->buffer);
irq_raise(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount) {
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
esdi->pos = 0;
next_sector(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
} else {
esdi->status = STAT_READY | STAT_DSC;
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
}
break;
case CMD_VERIFY:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
} else {
if (get_sector(esdi, &addr)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
}
hdd_image_read(drive->hdd_num, addr, 1, (uint8_t *) esdi->buffer);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 1);
next_sector(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount) {
get_sector(esdi, &addr);
seek_time = hdd_timing_read(&hdd[esdi->drives[esdi->drive_sel].hdd_num], addr, 1);
esdi_set_callback(esdi, seek_time + HDC_TIME);
} else {
esdi->pos = 0;
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
}
break;
case CMD_FORMAT:
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
break;
} else {
if (get_sector_format(esdi, &addr)) {
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
irq_raise(esdi);
break;
}
hdd_image_zero(drive->hdd_num, addr, esdi->secount);
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
}
break;
case CMD_DIAGNOSE:
/* This is basically controller diagnostics - it resets drive select to 0,
and resets error and status to ready, DSC, and no error detected. */
esdi->drive_sel = 0;
drive = &esdi->drives[esdi->drive_sel];
esdi->error = 1; /*no error detected*/
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_SET_PARAMETERS: /* Initialize Drive Parameters */
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
} else {
drive->cfg_spt = esdi->secount;
drive->cfg_hpc = esdi->head + 1;
esdi_at_log("WD1007: parameters: spt=%i hpc=%i\n", drive->cfg_spt, drive->cfg_hpc);
if (!esdi->secount)
fatal("WD1007: secount=0\n");
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
}
break;
case CMD_NOP:
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case 0xe0:
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
break;
} else {
switch (esdi->cylinder >> 8) {
case 0x31:
esdi->cylinder = drive->real_tracks;
break;
case 0x33:
esdi->cylinder = drive->real_hpc;
break;
case 0x35:
esdi->cylinder = 0x200;
break;
case 0x36:
esdi->cylinder = drive->real_spt;
break;
default:
esdi_at_log("WD1007: bad read config %02x\n", esdi->cylinder >> 8);
}
esdi->status = STAT_READY | STAT_DSC;
irq_raise(esdi);
}
break;
case 0xa0:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
} else {
memset(esdi->buffer, 0x00, 512);
memset(&esdi->buffer[3], 0xff, 512 - 6);
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
}
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
case CMD_READ_PARAMETERS:
if (!drive->present) {
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
} else {
memset(esdi->buffer, 0x00, 512);
esdi->buffer[0] = 0x44; /* general configuration */
esdi->buffer[1] = drive->real_tracks; /* number of non-removable cylinders */
esdi->buffer[2] = 0; /* number of removable cylinders */
esdi->buffer[3] = drive->real_hpc; /* number of heads */
esdi->buffer[4] = 600; /* number of unformatted bytes/sector */
esdi->buffer[5] = esdi->buffer[4] * drive->real_spt; /* number of unformatted bytes/track */
esdi->buffer[6] = drive->real_spt; /* number of sectors */
esdi->buffer[7] = 0; /*minimum bytes in inter-sector gap*/
esdi->buffer[8] = 0; /* minimum bytes in postamble */
esdi->buffer[9] = 0; /* number of words of vendor status */
/* controller info */
esdi->buffer[20] = 2; /* controller type */
esdi->buffer[21] = 1; /* sector buffer size, in sectors */
esdi->buffer[22] = 0; /* ecc bytes appended */
esdi->buffer[27] = 'W' | ('D' << 8);
esdi->buffer[28] = '1' | ('0' << 8);
esdi->buffer[29] = '0' | ('7' << 8);
esdi->buffer[30] = 'V' | ('-' << 8);
esdi->buffer[31] = 'S' | ('E' << 8);
esdi->buffer[32] = '1';
esdi->buffer[47] = 0; /* sectors per interrupt */
esdi->buffer[48] = 0; /* can use double word read/write? */
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
irq_raise(esdi);
}
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
default:
esdi_at_log("WD1007: callback on unknown command %02x\n", esdi->command);
fallthrough;
case 0xe8:
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
irq_raise(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
break;
}
}
static void
loadhd(esdi_t *esdi, int hdd_num, int d, UNUSED(const char *fn))
{
drive_t *drive = &esdi->drives[hdd_num];
if (!hdd_image_load(d)) {
esdi_at_log("WD1007: drive %d not present!\n", d);
drive->present = 0;
return;
}
hdd_preset_apply(d);
drive->cfg_spt = drive->real_spt = hdd[d].spt;
drive->cfg_hpc = drive->real_hpc = hdd[d].hpc;
drive->real_tracks = hdd[d].tracks;
drive->hdd_num = d;
drive->present = 1;
}
static void
esdi_rom_write(uint32_t addr, uint8_t val, void *priv)
{
rom_t *rom = (rom_t *) priv;
addr &= rom->mask;
if (addr >= 0x1f00 && addr < 0x2000)
rom->rom[addr] = val;
}
static void *
wd1007vse1_init(UNUSED(const device_t *info))
{
int c;
esdi_t *esdi = malloc(sizeof(esdi_t));
memset(esdi, 0x00, sizeof(esdi_t));
c = 0;
for (uint8_t d = 0; d < HDD_NUM; d++) {
if ((hdd[d].bus == HDD_BUS_ESDI) && (hdd[d].esdi_channel < ESDI_NUM)) {
loadhd(esdi, hdd[d].esdi_channel, d, hdd[d].fn);
if (++c >= ESDI_NUM)
break;
}
}
esdi->status = STAT_READY | STAT_DSC;
esdi->error = 1;
rom_init(&esdi->bios_rom,
BIOS_FILE, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_set_handler(&esdi->bios_rom.mapping,
rom_read, rom_readw, rom_readl,
esdi_rom_write, NULL, NULL);
io_sethandler(0x01f0, 1,
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, esdi);
io_sethandler(0x01f1, 7,
esdi_read, esdi_readw, NULL,
esdi_write, esdi_writew, NULL, esdi);
io_sethandler(0x03f6, 1, NULL, NULL, NULL,
esdi_write, NULL, NULL, esdi);
timer_add(&esdi->callback_timer, esdi_callback, esdi, 0);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
return esdi;
}
static void
wd1007vse1_close(void *priv)
{
esdi_t *esdi = (esdi_t *) priv;
const drive_t *drive;
for (uint8_t d = 0; d < 2; d++) {
drive = &esdi->drives[d];
hdd_image_close(drive->hdd_num);
}
free(esdi);
ui_sb_update_icon(SB_HDD | HDD_BUS_ESDI, 0);
}
static int
wd1007vse1_available(void)
{
return (rom_present(BIOS_FILE));
}
const device_t esdi_at_wd1007vse1_device = {
.name = "Western Digital WD1007V-SE1 (ESDI)",
.internal_name = "esdi_at",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = wd1007vse1_init,
.close = wd1007vse1_close,
.reset = NULL,
{ .available = wd1007vse1_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/disk/hdc_esdi_at.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,177 |
```objective-c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Version: @(#)xml2_encoding.h 1.0.1 2021/03/15
*
* Author: Sherman Perry, <shermperry@gmail.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef XML2_ENCODING_H
# define XML2_ENCODING_H
typedef uint16_t mvhd_utf16;
#ifdef __cplusplus
extern "C" {
#endif
void xmlEncodingInit(void);
int UTF16LEToUTF8(uint8_t *out, int *outlen, const uint8_t *inb,
int *inlenb);
int UTF8ToUTF16LE(uint8_t *outb, int *outlen, const uint8_t *in,
int *inlen);
int UTF16BEToUTF8(uint8_t *out, int *outlen, const uint8_t *inb,
int *inlenb);
int UTF8ToUTF16BE(uint8_t *outb, int *outlen, const uint8_t *in,
int *inlen);
#ifdef __cplusplus
}
#endif
#endif /*XML2_ENCODING_H*/
``` | /content/code_sandbox/src/disk/minivhd/xml2_encoding.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 532 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* VHD management functions (open, close, read write etc)
*
* Version: @(#)manage.c 1.0.4 2021/04/16
*
* Authors: Sherman Perry, <shermperry@gmail.com>
* Fred N. van Kempen, <waltje@varcem.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
#include "minivhd.h"
#include "internal.h"
#include "version.h"
#include "cwalk.h"
#include "xml2_encoding.h"
struct MVHDPaths {
char dir_path[MVHD_MAX_PATH_BYTES];
char file_name[MVHD_MAX_PATH_BYTES];
char w2ku_path[MVHD_MAX_PATH_BYTES];
char w2ru_path[MVHD_MAX_PATH_BYTES];
char joined_path[MVHD_MAX_PATH_BYTES];
uint16_t tmp_src_path[MVHD_MAX_PATH_CHARS];
};
int mvhd_errno = 0;
static char tmp_open_path[MVHD_MAX_PATH_BYTES] = {0};
/**
* \brief Populate data stuctures with content from a VHD footer
*
* \param [in] vhdm MiniVHD data structure
*/
static void
read_footer(MVHDMeta* vhdm)
{
uint8_t buffer[MVHD_FOOTER_SIZE];
mvhd_fseeko64(vhdm->f, -MVHD_FOOTER_SIZE, SEEK_END);
(void) !fread(buffer, sizeof buffer, 1, vhdm->f);
mvhd_buffer_to_footer(&vhdm->footer, buffer);
}
/**
* \brief Populate data stuctures with content from a VHD sparse header
*
* \param [in] vhdm MiniVHD data structure
*/
static void
read_sparse_header(MVHDMeta* vhdm)
{
uint8_t buffer[MVHD_SPARSE_SIZE] = { 0 };
mvhd_fseeko64(vhdm->f, vhdm->footer.data_offset, SEEK_SET);
(void) !fread(buffer, sizeof buffer, 1, vhdm->f);
mvhd_buffer_to_header(&vhdm->sparse, buffer);
}
/**
* \brief Validate VHD footer checksum
*
* This works by generating a checksum from the footer, and comparing it against the stored checksum.
*
* \param [in] vhdm MiniVHD data structure
*/
static bool
footer_checksum_valid(MVHDMeta* vhdm)
{
return vhdm->footer.checksum == mvhd_gen_footer_checksum(&vhdm->footer);
}
/**
* \brief Validate VHD sparse header checksum
*
* This works by generating a checksum from the sparse header, and comparing it against the stored checksum.
*
* \param [in] vhdm MiniVHD data structure
*/
static bool
sparse_checksum_valid(MVHDMeta* vhdm)
{
return vhdm->sparse.checksum == mvhd_gen_sparse_checksum(&vhdm->sparse);
}
/**
* \brief Read BAT into MiniVHD data structure
*
* The Block Allocation Table (BAT) is the structure in a sparse and differencing VHD which stores
* the 4-byte sector offsets for each data block. This function allocates enough memory to contain
* the entire BAT, and then reads the contents of the BAT into the buffer.
*
* \param [in] vhdm MiniVHD data structure
* \param [out] err this is populated with MVHD_ERR_MEM if the calloc fails
*
* \retval -1 if an error occurrs. Check value of err in this case
* \retval 0 if the function call succeeds
*/
static int
read_bat(MVHDMeta *vhdm, MVHDError* err)
{
vhdm->block_offset = calloc(vhdm->sparse.max_bat_ent, sizeof *vhdm->block_offset);
if (vhdm->block_offset == NULL) {
*err = MVHD_ERR_MEM;
return -1;
}
mvhd_fseeko64(vhdm->f, vhdm->sparse.bat_offset, SEEK_SET);
for (uint32_t i = 0; i < vhdm->sparse.max_bat_ent; i++) {
(void) !fread(&vhdm->block_offset[i], sizeof *vhdm->block_offset, 1, vhdm->f);
vhdm->block_offset[i] = mvhd_from_be32(vhdm->block_offset[i]);
}
return 0;
}
/**
* \brief Perform a one-time calculation of some sparse VHD values
*
* \param [in] vhdm MiniVHD data structure
*/
static void
calc_sparse_values(MVHDMeta* vhdm)
{
vhdm->sect_per_block = vhdm->sparse.block_sz / MVHD_SECTOR_SIZE;
int bm_bytes = vhdm->sect_per_block / 8;
vhdm->bitmap.sector_count = bm_bytes / MVHD_SECTOR_SIZE;
if (bm_bytes % MVHD_SECTOR_SIZE > 0) {
vhdm->bitmap.sector_count++;
}
}
/**
* \brief Allocate memory for a sector bitmap.
*
* Each data block is preceded by a sector bitmap. Each bit indicates whether the corresponding sector
* is considered 'clean' or 'dirty' (for sparse VHD images), or whether to read from the parent or current
* image (for differencing images).
*
* \param [in] vhdm MiniVHD data structure
* \param [out] err this is populated with MVHD_ERR_MEM if the calloc fails
*
* \retval -1 if an error occurrs. Check value of err in this case
* \retval 0 if the function call succeeds
*/
static int
init_sector_bitmap(MVHDMeta* vhdm, MVHDError* err)
{
vhdm->bitmap.curr_bitmap = calloc(vhdm->bitmap.sector_count, MVHD_SECTOR_SIZE);
if (vhdm->bitmap.curr_bitmap == NULL) {
*err = MVHD_ERR_MEM;
return -1;
}
vhdm->bitmap.curr_block = -1;
return 0;
}
/**
* \brief Check if the path for a given platform code exists
*
* From the available paths, both relative and absolute, construct a full path
* and attempt to open a file at that path.
*
* Note, this function makes no attempt to verify that the path is the correct
* VHD image, or even a VHD image at all.
*
* \param [in] paths a struct containing all available paths to work with
* \param [in] the platform code to try and obtain a path for. Setting this to zero
* will try using the directory of the child image
*
* \retval true if a file is found
* \retval false if a file is not found
*/
static bool
mvhd_parent_path_exists(struct MVHDPaths* paths, uint32_t plat_code)
{
FILE* f;
int ferr;
size_t cwk_ret;
enum cwk_path_style style;
memset(paths->joined_path, 0, sizeof paths->joined_path);
style = cwk_path_guess_style((const char*)paths->dir_path);
cwk_path_set_style(style);
cwk_ret = 1;
if (plat_code == MVHD_DIF_LOC_W2RU && *paths->w2ru_path) {
cwk_ret = cwk_path_join((const char*)paths->dir_path, (const char*)paths->w2ru_path, paths->joined_path, sizeof paths->joined_path);
} else if (plat_code == MVHD_DIF_LOC_W2KU && *paths->w2ku_path) {
memcpy(paths->joined_path, paths->w2ku_path, (sizeof paths->joined_path) - 1);
cwk_ret = 0;
} else if (plat_code == 0) {
cwk_ret = cwk_path_join((const char*)paths->dir_path, (const char*)paths->file_name, paths->joined_path, sizeof paths->joined_path);
}
if (cwk_ret > MVHD_MAX_PATH_BYTES) {
return false;
}
f = mvhd_fopen((const char*)paths->joined_path, "rb", &ferr);
if (f != NULL) {
/* We found a file at the requested path! */
memcpy(tmp_open_path, paths->joined_path, (sizeof paths->joined_path) - 1);
tmp_open_path[sizeof tmp_open_path - 1] = '\0';
fclose(f);
return true;
}
return false;
}
/**
* \brief attempt to obtain a file path to a file that may be a valid VHD image
*
* Differential VHD images store both a UTF-16BE file name (or path), and up to
* eight "parent locator" entries. Using this information, this function tries to
* find a parent image.
*
* This function does not verify if the path returned is a valid parent image.
*
* \param [in] vhdm current MiniVHD data structure
* \param [out] err any errors that may occurr. Check this if NULL is returned
*
* \return a pointer to the global string `tmp_open_path`, or NULL if a path could
* not be found, or some error occurred
*/
static char*
get_diff_parent_path(MVHDMeta* vhdm, int* err)
{
int utf_outlen, utf_inlen, utf_ret;
char *par_fp = NULL;
struct MVHDPaths *paths;
size_t dirlen;
/* We can't resolve relative paths if we don't have an absolute
path to work with */
if (!cwk_path_is_absolute((const char*)vhdm->filename)) {
*err = MVHD_ERR_PATH_REL;
goto end;
}
paths = calloc(1, sizeof *paths);
if (paths == NULL) {
*err = MVHD_ERR_MEM;
goto end;
}
cwk_path_get_dirname((const char*)vhdm->filename, &dirlen);
if (dirlen >= sizeof paths->dir_path) {
*err = MVHD_ERR_PATH_LEN;
goto paths_cleanup;
}
memcpy(paths->dir_path, vhdm->filename, dirlen);
/* Get the filename field from the sparse header. */
utf_outlen = (int)sizeof paths->file_name;
utf_inlen = (int)sizeof vhdm->sparse.par_utf16_name;
utf_ret = UTF16BEToUTF8((unsigned char*)paths->file_name, &utf_outlen, (const unsigned char*)vhdm->sparse.par_utf16_name, &utf_inlen);
if (utf_ret < 0) {
mvhd_set_encoding_err(utf_ret, err);
goto paths_cleanup;
}
/* Now read the parent locator entries, both relative and absolute, if they exist */
unsigned char* loc_path;
for (int i = 0; i < 8; i++) {
utf_outlen = MVHD_MAX_PATH_BYTES - 1;
if (vhdm->sparse.par_loc_entry[i].plat_code == MVHD_DIF_LOC_W2RU) {
loc_path = (unsigned char*)paths->w2ru_path;
} else if (vhdm->sparse.par_loc_entry[i].plat_code == MVHD_DIF_LOC_W2KU) {
loc_path = (unsigned char*)paths->w2ku_path;
} else {
continue;
}
utf_inlen = vhdm->sparse.par_loc_entry[i].plat_data_len;
if (utf_inlen > MVHD_MAX_PATH_BYTES) {
*err = MVHD_ERR_PATH_LEN;
goto paths_cleanup;
}
mvhd_fseeko64(vhdm->f, vhdm->sparse.par_loc_entry[i].plat_data_offset, SEEK_SET);
(void) !fread(paths->tmp_src_path, sizeof (uint8_t), utf_inlen, vhdm->f);
/* Note, the W2*u parent locators are UTF-16LE, unlike the filename field previously obtained,
which is UTF-16BE */
utf_ret = UTF16LEToUTF8(loc_path, &utf_outlen, (const unsigned char*)paths->tmp_src_path, &utf_inlen);
if (utf_ret < 0) {
mvhd_set_encoding_err(utf_ret, err);
goto paths_cleanup;
}
}
/* We have paths in UTF-8. We should have enough info to try and find the parent VHD */
/* Does the relative path exist? */
if (mvhd_parent_path_exists(paths, MVHD_DIF_LOC_W2RU)) {
par_fp = tmp_open_path;
goto paths_cleanup;
}
/* What about trying the child directory? */
if (mvhd_parent_path_exists(paths, 0)) {
par_fp = tmp_open_path;
goto paths_cleanup;
}
/* Well, all else fails, try the stored absolute path, if it exists */
if (mvhd_parent_path_exists(paths, MVHD_DIF_LOC_W2KU)) {
par_fp = tmp_open_path;
goto paths_cleanup;
}
/* If we reach this point, we could not find a path with a valid file */
par_fp = NULL;
*err = MVHD_ERR_PAR_NOT_FOUND;
paths_cleanup:
free(paths);
paths = NULL;
end:
return par_fp;
}
/**
* \brief Attach the read/write function pointers to read/write functions
*
* Depending on the VHD type, different sector reading and writing functions are used.
* The functions are called via function pointers stored in the vhdm struct.
*
* \param [in] vhdm MiniVHD data structure
*/
static void
assign_io_funcs(MVHDMeta* vhdm)
{
switch (vhdm->footer.disk_type) {
case MVHD_TYPE_FIXED:
vhdm->read_sectors = mvhd_fixed_read;
vhdm->write_sectors = mvhd_fixed_write;
break;
case MVHD_TYPE_DYNAMIC:
vhdm->read_sectors = mvhd_sparse_read;
vhdm->write_sectors = mvhd_sparse_diff_write;
break;
case MVHD_TYPE_DIFF:
vhdm->read_sectors = mvhd_diff_read;
vhdm->write_sectors = mvhd_sparse_diff_write;
break;
}
if (vhdm->readonly)
vhdm->write_sectors = mvhd_noop_write;
}
/**
* \brief Return the library version as a string
*/
MVHDAPI const char *
mvhd_version(void)
{
return LIB_VERSION_4;
}
/**
* \brief Return the library version as a number
*/
MVHDAPI uint32_t
mvhd_version_id(void)
{
return (LIB_VER_MAJOR << 24) | (LIB_VER_MINOR << 16) |
(LIB_VER_REV << 16) | LIB_VER_PATCH;
}
/**
* \brief A simple test to see if a given file is a VHD
*
* \param [in] f file to test
*
* \retval 1 if f is a VHD
* \retval 0 if f is not a VHD
*/
MVHDAPI int
mvhd_file_is_vhd(FILE* f)
{
uint8_t con_str[8] = { 0 };
if (f == NULL)
return 0;
mvhd_fseeko64(f, -MVHD_FOOTER_SIZE, SEEK_END);
(void) !fread(con_str, sizeof con_str, 1, f);
if (mvhd_is_conectix_str(con_str))
return 1;
return 0;
}
MVHDAPI MVHDGeom
mvhd_calculate_geometry(uint64_t size)
{
MVHDGeom chs = { 0 };
uint32_t ts = (uint32_t)(size / MVHD_SECTOR_SIZE);
uint32_t spt, heads, cyl, cth;
if (ts > 65535 * 16 * 255)
ts = 65535 * 16 * 255;
if (ts >= 65535 * 16 * 63) {
spt = 255;
heads = 16;
cth = ts / spt;
} else {
spt = 17;
cth = ts / spt;
heads = (cth + 1023) / 1024;
if (heads < 4)
heads = 4;
if (cth >= (heads * 1024) || heads > 16) {
spt = 31;
heads = 16;
cth = ts / spt;
}
if (cth >= (heads * 1024)) {
spt = 63;
heads = 16;
cth = ts / spt;
}
}
cyl = cth / heads;
chs.heads = heads;
chs.spt = spt;
chs.cyl = cyl;
return chs;
}
MVHDAPI MVHDMeta*
mvhd_open(const char* path, int readonly, int* err)
{
MVHDError open_err = { 0 };
MVHDMeta *vhdm = calloc(sizeof *vhdm, 1);
if (vhdm == NULL) {
*err = MVHD_ERR_MEM;
goto end;
}
if (strlen(path) >= sizeof vhdm->filename) {
*err = MVHD_ERR_PATH_LEN;
goto cleanup_vhdm;
}
//This is safe, as we've just checked for potential overflow above
strcpy(vhdm->filename, path);
if (readonly)
vhdm->f = mvhd_fopen((const char*)vhdm->filename, "rb", err);
else
vhdm->f = mvhd_fopen((const char*)vhdm->filename, "rb+", err);
if (vhdm->f == NULL) {
/* note, mvhd_fopen sets err for us */
goto cleanup_vhdm;
}
vhdm->readonly = readonly;
if (!mvhd_file_is_vhd(vhdm->f)) {
*err = MVHD_ERR_NOT_VHD;
goto cleanup_file;
}
read_footer(vhdm);
if (!footer_checksum_valid(vhdm)) {
*err = MVHD_ERR_FOOTER_CHECKSUM;
goto cleanup_file;
}
if (vhdm->footer.disk_type == MVHD_TYPE_DIFF || vhdm->footer.disk_type == MVHD_TYPE_DYNAMIC) {
read_sparse_header(vhdm);
if (!sparse_checksum_valid(vhdm)) {
*err = MVHD_ERR_SPARSE_CHECKSUM;
goto cleanup_file;
}
if (read_bat(vhdm, &open_err) == -1) {
*err = open_err;
goto cleanup_file;
}
calc_sparse_values(vhdm);
if (init_sector_bitmap(vhdm, &open_err) == -1) {
*err = open_err;
goto cleanup_bat;
}
} else if (vhdm->footer.disk_type != MVHD_TYPE_FIXED) {
*err = MVHD_ERR_TYPE;
goto cleanup_bitmap;
}
assign_io_funcs(vhdm);
vhdm->format_buffer.zero_data = calloc(64, MVHD_SECTOR_SIZE);
if (vhdm->format_buffer.zero_data == NULL) {
*err = MVHD_ERR_MEM;
goto cleanup_bitmap;
}
vhdm->format_buffer.sector_count = 64;
if (vhdm->footer.disk_type == MVHD_TYPE_DIFF) {
char* par_path = get_diff_parent_path(vhdm, err);
if (par_path == NULL)
goto cleanup_format_buff;
uint32_t par_mod_ts = mvhd_file_mod_timestamp(par_path, err);
if (*err != 0)
goto cleanup_format_buff;
if (vhdm->sparse.par_timestamp != par_mod_ts) {
/* The last-modified timestamp is to fragile to make this a fatal error.
Instead, we inform the caller of the potential problem. */
*err = MVHD_ERR_TIMESTAMP;
}
vhdm->parent = mvhd_open(par_path, true, err);
if (vhdm->parent == NULL)
goto cleanup_format_buff;
if (memcmp(vhdm->sparse.par_uuid, vhdm->parent->footer.uuid, sizeof vhdm->sparse.par_uuid) != 0) {
*err = MVHD_ERR_INVALID_PAR_UUID;
goto cleanup_format_buff;
}
}
/*
* If we've reached this point, we are good to go,
* so skip the cleanup steps.
*/
goto end;
cleanup_format_buff:
free(vhdm->format_buffer.zero_data);
vhdm->format_buffer.zero_data = NULL;
cleanup_bitmap:
free(vhdm->bitmap.curr_bitmap);
vhdm->bitmap.curr_bitmap = NULL;
cleanup_bat:
free(vhdm->block_offset);
vhdm->block_offset = NULL;
cleanup_file:
fclose(vhdm->f);
vhdm->f = NULL;
cleanup_vhdm:
free(vhdm);
vhdm = NULL;
end:
return vhdm;
}
MVHDAPI void
mvhd_close(MVHDMeta* vhdm)
{
if (vhdm == NULL)
return;
if (vhdm->parent != NULL)
mvhd_close(vhdm->parent);
fclose(vhdm->f);
if (vhdm->block_offset != NULL) {
free(vhdm->block_offset);
vhdm->block_offset = NULL;
}
if (vhdm->bitmap.curr_bitmap != NULL) {
free(vhdm->bitmap.curr_bitmap);
vhdm->bitmap.curr_bitmap = NULL;
}
if (vhdm->format_buffer.zero_data != NULL) {
free(vhdm->format_buffer.zero_data);
vhdm->format_buffer.zero_data = NULL;
}
free(vhdm);
}
MVHDAPI int
mvhd_diff_update_par_timestamp(MVHDMeta* vhdm, int* err)
{
uint8_t sparse_buff[1024] = { 0 };
if (vhdm == NULL || err == NULL) {
*err = MVHD_ERR_INVALID_PARAMS;
return -1;
}
if (vhdm->footer.disk_type != MVHD_TYPE_DIFF) {
*err = MVHD_ERR_TYPE;
return -1;
}
char* par_path = get_diff_parent_path(vhdm, err);
if (par_path == NULL) {
return -1;
}
uint32_t par_mod_ts = mvhd_file_mod_timestamp(par_path, err);
if (*err != 0) {
return -1;
}
/* Update the timestamp and sparse header checksum */
vhdm->sparse.par_timestamp = par_mod_ts;
vhdm->sparse.checksum = mvhd_gen_sparse_checksum(&vhdm->sparse);
/* Generate and write the updated sparse header */
mvhd_header_to_buffer(&vhdm->sparse, sparse_buff);
mvhd_fseeko64(vhdm->f, (int64_t)vhdm->footer.data_offset, SEEK_SET);
fwrite(sparse_buff, sizeof sparse_buff, 1, vhdm->f);
return 0;
}
MVHDAPI int
mvhd_read_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* out_buff)
{
return vhdm->read_sectors(vhdm, offset, num_sectors, out_buff);
}
MVHDAPI int
mvhd_write_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* in_buff)
{
return vhdm->write_sectors(vhdm, offset, num_sectors, in_buff);
}
MVHDAPI int
mvhd_format_sectors(MVHDMeta* vhdm, uint32_t offset, int num_sectors)
{
int num_full = num_sectors / vhdm->format_buffer.sector_count;
int remain = num_sectors % vhdm->format_buffer.sector_count;
for (int i = 0; i < num_full; i++) {
vhdm->write_sectors(vhdm, offset, vhdm->format_buffer.sector_count, vhdm->format_buffer.zero_data);
offset += vhdm->format_buffer.sector_count;
}
vhdm->write_sectors(vhdm, offset, remain, vhdm->format_buffer.zero_data);
return 0;
}
MVHDAPI MVHDType
mvhd_get_type(MVHDMeta* vhdm)
{
return vhdm->footer.disk_type;
}
``` | /content/code_sandbox/src/disk/minivhd/manage.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,710 |
```c
/*
* encoding.c : implements the encoding conversion functions needed for XML
*
* Related specs:
* rfc2044 (UTF-8 and UTF-16) F. Yergeau Alis Technologies
* rfc2781 UTF-16, an encoding of ISO 10646, P. Hoffman, F. Yergeau
* [ISO-10646] UTF-8 and UTF-16 in Annexes
* [ISO-8859-1] ISO Latin-1 characters codes.
* [UNICODE] The Unicode Consortium, "The Unicode Standard --
* Worldwide Character Encoding -- Version 1.0", Addison-
* Wesley, Volume 1, 1991, Volume 2, 1992. UTF-8 is
* described in Unicode Technical Report #4.
* [US-ASCII] Coded Character Set--7-bit American Standard Code for
* Information Interchange, ANSI X3.4-1986.
*
*
* daniel@veillard.com
*
* Original code for IsoLatin1 and UTF-16 by "Martin J. Duerst" <duerst@w3.org>
*
* Adapted and abridged for MiniVHD by Sherman Perry
*/
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
#include <time.h>
#define BUILDING_LIBRARY
#include "minivhd.h"
#include "internal.h"
#include "xml2_encoding.h"
static int xmlLittleEndian = 1;
/* Note: extracted from original 'void xmlInitCharEncodingHandlers(void)' function */
void xmlEncodingInit(void)
{
unsigned short int tst = 0x1234;
unsigned char *ptr = (unsigned char *) &tst;
if (*ptr == 0x12) xmlLittleEndian = 0;
else if (*ptr == 0x34) xmlLittleEndian = 1;
}
/**
* UTF16LEToUTF8:
* @out: a pointer to an array of bytes to store the result
* @outlen: the length of @out
* @inb: a pointer to an array of UTF-16LE passwd as a byte array
* @inlenb: the length of @in in UTF-16LE chars
*
* Take a block of UTF-16LE ushorts in and try to convert it to an UTF-8
* block of chars out. This function assumes the endian property
* is the same between the native type of this machine and the
* inputed one.
*
* Returns the number of bytes written, or -1 if lack of space, or -2
* if the transcoding fails (if *in is not a valid utf16 string)
* The value of *inlen after return is the number of octets consumed
* if the return value is positive, else unpredictable.
*/
int UTF16LEToUTF8(unsigned char* out, int *outlen,
const unsigned char* inb, int *inlenb)
{
unsigned char* outstart = out;
const unsigned char* processed = inb;
unsigned char* outend = out + *outlen;
unsigned short* in = (unsigned short*) inb;
unsigned short* inend;
unsigned int c, d, inlen;
unsigned char *tmp;
int bits;
if ((*inlenb % 2) == 1)
(*inlenb)--;
inlen = *inlenb / 2;
inend = in + inlen;
while ((in < inend) && (out - outstart + 5 < *outlen)) {
if (xmlLittleEndian) {
c= *in++;
} else {
tmp = (unsigned char *) in;
c = *tmp++;
c = c | (((unsigned int)*tmp) << 8);
in++;
}
if ((c & 0xFC00) == 0xD800) { /* surrogates */
if (in >= inend) { /* (in > inend) shouldn't happens */
break;
}
if (xmlLittleEndian) {
d = *in++;
} else {
tmp = (unsigned char *) in;
d = *tmp++;
d = d | (((unsigned int)*tmp) << 8);
in++;
}
if ((d & 0xFC00) == 0xDC00) {
c &= 0x03FF;
c <<= 10;
c |= d & 0x03FF;
c += 0x10000;
}
else {
*outlen = (int)(out - outstart);
*inlenb = (int)(processed - inb);
return(-2);
}
}
/* assertion: c is a single UTF-4 value */
if (out >= outend)
break;
if (c < 0x80) { *out++= c; bits= -6; }
else if (c < 0x800) { *out++= ((c >> 6) & 0x1F) | 0xC0; bits= 0; }
else if (c < 0x10000) { *out++= ((c >> 12) & 0x0F) | 0xE0; bits= 6; }
else { *out++= ((c >> 18) & 0x07) | 0xF0; bits= 12; }
for ( ; bits >= 0; bits-= 6) {
if (out >= outend)
break;
*out++= ((c >> bits) & 0x3F) | 0x80;
}
processed = (const unsigned char*) in;
}
*outlen = (int)(out - outstart);
*inlenb = (int)(processed - inb);
return(*outlen);
}
/**
* UTF8ToUTF16LE:
* @outb: a pointer to an array of bytes to store the result
* @outlen: the length of @outb
* @in: a pointer to an array of UTF-8 chars
* @inlen: the length of @in
*
* Take a block of UTF-8 chars in and try to convert it to an UTF-16LE
* block of chars out.
*
* Returns the number of bytes written, or -1 if lack of space, or -2
* if the transcoding failed.
*/
int UTF8ToUTF16LE(unsigned char* outb, int *outlen,
const unsigned char* in, int *inlen)
{
unsigned short* out = (unsigned short*) outb;
const unsigned char* processed = in;
const unsigned char *const instart = in;
unsigned short* outstart= out;
unsigned short* outend;
const unsigned char* inend;
unsigned int c, d;
int trailing;
unsigned char *tmp;
unsigned short tmp1, tmp2;
/* UTF16LE encoding has no BOM */
if ((out == NULL) || (outlen == NULL) || (inlen == NULL)) return(-1);
if (in == NULL) {
*outlen = 0;
*inlen = 0;
return(0);
}
inend= in + *inlen;
outend = out + (*outlen / 2);
while (in < inend) {
d= *in++;
if (d < 0x80) { c= d; trailing= 0; }
else if (d < 0xC0) {
/* trailing byte in leading position */
*outlen = (int)((out - outstart) * 2);
*inlen = (int)(processed - instart);
return(-2);
} else if (d < 0xE0) { c= d & 0x1F; trailing= 1; }
else if (d < 0xF0) { c= d & 0x0F; trailing= 2; }
else if (d < 0xF8) { c= d & 0x07; trailing= 3; }
else {
/* no chance for this in UTF-16 */
*outlen = (int)((out - outstart) * 2);
*inlen = (int)(processed - instart);
return(-2);
}
if (inend - in < trailing) {
break;
}
for ( ; trailing; trailing--) {
if ((in >= inend) || (((d= *in++) & 0xC0) != 0x80))
break;
c <<= 6;
c |= d & 0x3F;
}
/* assertion: c is a single UTF-4 value */
if (c < 0x10000) {
if (out >= outend)
break;
if (xmlLittleEndian) {
*out++ = c;
} else {
tmp = (unsigned char *) out;
*tmp = c ;
*(tmp + 1) = c >> 8 ;
out++;
}
}
else if (c < 0x110000) {
if (out+1 >= outend)
break;
c -= 0x10000;
if (xmlLittleEndian) {
*out++ = 0xD800 | (c >> 10);
*out++ = 0xDC00 | (c & 0x03FF);
} else {
tmp1 = 0xD800 | (c >> 10);
tmp = (unsigned char *) out;
*tmp = (unsigned char) tmp1;
*(tmp + 1) = tmp1 >> 8;
out++;
tmp2 = 0xDC00 | (c & 0x03FF);
tmp = (unsigned char *) out;
*tmp = (unsigned char) tmp2;
*(tmp + 1) = tmp2 >> 8;
out++;
}
}
else
break;
processed = in;
}
*outlen = (int)((out - outstart) * 2);
*inlen = (int)(processed - instart);
return(*outlen);
}
/**
* UTF16BEToUTF8:
* @out: a pointer to an array of bytes to store the result
* @outlen: the length of @out
* @inb: a pointer to an array of UTF-16 passed as a byte array
* @inlenb: the length of @in in UTF-16 chars
*
* Take a block of UTF-16 ushorts in and try to convert it to an UTF-8
* block of chars out. This function assumes the endian property
* is the same between the native type of this machine and the
* inputed one.
*
* Returns the number of bytes written, or -1 if lack of space, or -2
* if the transcoding fails (if *in is not a valid utf16 string)
* The value of *inlen after return is the number of octets consumed
* if the return value is positive, else unpredictable.
*/
int UTF16BEToUTF8(unsigned char* out, int *outlen,
const unsigned char* inb, int *inlenb)
{
unsigned char* outstart = out;
const unsigned char* processed = inb;
unsigned char* outend = out + *outlen;
unsigned short* in = (unsigned short*) inb;
unsigned short* inend;
unsigned int c, d, inlen;
unsigned char *tmp;
int bits;
if ((*inlenb % 2) == 1)
(*inlenb)--;
inlen = *inlenb / 2;
inend= in + inlen;
while (in < inend) {
if (xmlLittleEndian) {
tmp = (unsigned char *) in;
c = *tmp++;
c = c << 8;
c = c | (unsigned int) *tmp;
in++;
} else {
c= *in++;
}
if ((c & 0xFC00) == 0xD800) { /* surrogates */
if (in >= inend) { /* (in > inend) shouldn't happens */
*outlen = (int)(out - outstart);
*inlenb = (int)(processed - inb);
return(-2);
}
if (xmlLittleEndian) {
tmp = (unsigned char *) in;
d = *tmp++;
d = d << 8;
d = d | (unsigned int) *tmp;
in++;
} else {
d= *in++;
}
if ((d & 0xFC00) == 0xDC00) {
c &= 0x03FF;
c <<= 10;
c |= d & 0x03FF;
c += 0x10000;
}
else {
*outlen = (int)(out - outstart);
*inlenb = (int)(processed - inb);
return(-2);
}
}
/* assertion: c is a single UTF-4 value */
if (out >= outend)
break;
if (c < 0x80) { *out++= c; bits= -6; }
else if (c < 0x800) { *out++= ((c >> 6) & 0x1F) | 0xC0; bits= 0; }
else if (c < 0x10000) { *out++= ((c >> 12) & 0x0F) | 0xE0; bits= 6; }
else { *out++= ((c >> 18) & 0x07) | 0xF0; bits= 12; }
for ( ; bits >= 0; bits-= 6) {
if (out >= outend)
break;
*out++= ((c >> bits) & 0x3F) | 0x80;
}
processed = (const unsigned char*) in;
}
*outlen = (int)(out - outstart);
*inlenb = (int)(processed - inb);
return(*outlen);
}
/**
* UTF8ToUTF16BE:
* @outb: a pointer to an array of bytes to store the result
* @outlen: the length of @outb
* @in: a pointer to an array of UTF-8 chars
* @inlen: the length of @in
*
* Take a block of UTF-8 chars in and try to convert it to an UTF-16BE
* block of chars out.
*
* Returns the number of byte written, or -1 by lack of space, or -2
* if the transcoding failed.
*/
int UTF8ToUTF16BE(unsigned char* outb, int *outlen,
const unsigned char* in, int *inlen)
{
unsigned short* out = (unsigned short*) outb;
const unsigned char* processed = in;
const unsigned char *const instart = in;
unsigned short* outstart= out;
unsigned short* outend;
const unsigned char* inend;
unsigned int c, d;
int trailing;
unsigned char *tmp;
unsigned short tmp1, tmp2;
/* UTF-16BE has no BOM */
if ((outb == NULL) || (outlen == NULL) || (inlen == NULL)) return(-1);
if (in == NULL) {
*outlen = 0;
*inlen = 0;
return(0);
}
inend= in + *inlen;
outend = out + (*outlen / 2);
while (in < inend) {
d= *in++;
if (d < 0x80) { c= d; trailing= 0; }
else if (d < 0xC0) {
/* trailing byte in leading position */
*outlen = (int)(out - outstart);
*inlen = (int)(processed - instart);
return(-2);
} else if (d < 0xE0) { c= d & 0x1F; trailing= 1; }
else if (d < 0xF0) { c= d & 0x0F; trailing= 2; }
else if (d < 0xF8) { c= d & 0x07; trailing= 3; }
else {
/* no chance for this in UTF-16 */
*outlen = (int)(out - outstart);
*inlen = (int)(processed - instart);
return(-2);
}
if (inend - in < trailing) {
break;
}
for ( ; trailing; trailing--) {
if ((in >= inend) || (((d= *in++) & 0xC0) != 0x80)) break;
c <<= 6;
c |= d & 0x3F;
}
/* assertion: c is a single UTF-4 value */
if (c < 0x10000) {
if (out >= outend) break;
if (xmlLittleEndian) {
tmp = (unsigned char *) out;
*tmp = c >> 8;
*(tmp + 1) = c;
out++;
} else {
*out++ = c;
}
}
else if (c < 0x110000) {
if (out+1 >= outend) break;
c -= 0x10000;
if (xmlLittleEndian) {
tmp1 = 0xD800 | (c >> 10);
tmp = (unsigned char *) out;
*tmp = tmp1 >> 8;
*(tmp + 1) = (unsigned char) tmp1;
out++;
tmp2 = 0xDC00 | (c & 0x03FF);
tmp = (unsigned char *) out;
*tmp = tmp2 >> 8;
*(tmp + 1) = (unsigned char) tmp2;
out++;
} else {
*out++ = 0xD800 | (c >> 10);
*out++ = 0xDC00 | (c & 0x03FF);
}
}
else
break;
processed = in;
}
*outlen = (int)((out - outstart) * 2);
*inlen = (int)(processed - instart);
return(*outlen);
}
/* This file is licenced under the MIT licence as follows:
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is fur-
nished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT-
NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE. */
``` | /content/code_sandbox/src/disk/minivhd/xml2_encoding.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,388 |
```objective-c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Define library version and build info.
*
* Version: @(#)version.h 1.034 2021/04/16
*
* Author: Fred N. van Kempen, <waltje@varcem.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MINIVHD_VERSION_H
# define MINIVHD_VERSION_H
/* Library name. */
#define LIB_NAME "MiniVHD"
/* Version info. */
#define LIB_VER_MAJOR 1
#define LIB_VER_MINOR 0
#define LIB_VER_REV 3
#define LIB_VER_PATCH 0
/* Standard C preprocessor macros. */
#define STR_STRING(x) #x
#define STR(x) STR_STRING(x)
#define STR_RC(a,e) a ## , ## e
/* These are used in the application. */
#define LIB_VER_NUM LIB_VER_MAJOR.LIB_VER_MINOR.LIB_VER_REV
#if defined(LIB_VER_PATCH) && LIB_VER_PATCH > 0
# define LIB_VER_NUM_4 LIB_VER_MAJOR.LIB_VER_MINOR.LIB_VER_REV.LIB_VER_PATCH
#else
# define LIB_VER_NUM_4 LIB_VER_MAJOR.LIB_VER_MINOR.LIB_VER_REV.0
#endif
#define LIB_VERSION STR(LIB_VER_NUM)
#define LIB_VERSION_4 STR(LIB_VER_NUM_4)
#endif /*MINIVHD_VERSION_H*/
``` | /content/code_sandbox/src/disk/minivhd/version.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 582 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Sector reading and writing implementations.
*
* Version: @(#)io.c 1.0.3 2021/04/16
*
* Author: Sherman Perry, <shermperry@gmail.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include "minivhd.h"
#include "internal.h"
/*
* The following bit array macros adapted from:
*
* path_to_url~cheung/Courses/255/Syllabus/1-C-intro/bit-array.html
*/
#define VHD_SETBIT(A,k) ( A[(k>>3)] |= (0x80 >> (k&7)) )
#define VHD_CLEARBIT(A,k) ( A[(k>>3)] &= ~(0x80 >> (k&7)) )
#define VHD_TESTBIT(A,k) ( A[(k>>3)] & (0x80 >> (k&7)) )
/**
* \brief Check that we will not be overflowing buffers
*
* \param [in] offset The offset from which we are beginning from
* \param [in] num_sectors The number of sectors which we desire to read/write
* \param [in] total_sectors The total number of sectors available
* \param [out] transfer_sect The number of sectors to actually write.
* This may be lower than num_sectors if offset + num_sectors >= total_sectors
* \param [out] trunc_sectors The number of sectors truncated if transfer_sectors < num_sectors
*/
static inline void
check_sectors(uint32_t offset, int num_sectors, uint32_t total_sectors, int *transfer_sect, int *trunc_sect)
{
*transfer_sect = num_sectors;
*trunc_sect = 0;
if ((total_sectors - offset) < ((uint32_t) *transfer_sect)) {
*transfer_sect = total_sectors - offset;
*trunc_sect = num_sectors - *transfer_sect;
}
}
void
mvhd_write_empty_sectors(FILE *f, int sector_count)
{
uint8_t zero_bytes[MVHD_SECTOR_SIZE] = {0};
for (int i = 0; i < sector_count; i++)
fwrite(zero_bytes, sizeof zero_bytes, 1, f);
}
/**
* \brief Read the sector bitmap for a block.
*
* If the block is sparse, the sector bitmap in memory will be
* zeroed. Otherwise, the sector bitmap is read from the VHD file.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] blk The block for which to read the sector bitmap from
*/
static void
read_sect_bitmap(MVHDMeta *vhdm, int blk)
{
if (vhdm->block_offset[blk] != MVHD_SPARSE_BLK) {
mvhd_fseeko64(vhdm->f, (uint64_t)vhdm->block_offset[blk] * MVHD_SECTOR_SIZE, SEEK_SET);
(void) !fread(vhdm->bitmap.curr_bitmap, vhdm->bitmap.sector_count * MVHD_SECTOR_SIZE, 1, vhdm->f);
} else
memset(vhdm->bitmap.curr_bitmap, 0, vhdm->bitmap.sector_count * MVHD_SECTOR_SIZE);
vhdm->bitmap.curr_block = blk;
}
/**
* \brief Write the current sector bitmap in memory to file
*
* \param [in] vhdm MiniVHD data structure
*/
static void
write_curr_sect_bitmap(MVHDMeta* vhdm)
{
if (vhdm->bitmap.curr_block >= 0) {
int64_t abs_offset = (int64_t)vhdm->block_offset[vhdm->bitmap.curr_block] * MVHD_SECTOR_SIZE;
mvhd_fseeko64(vhdm->f, abs_offset, SEEK_SET);
fwrite(vhdm->bitmap.curr_bitmap, MVHD_SECTOR_SIZE, vhdm->bitmap.sector_count, vhdm->f);
}
}
/**
* \brief Write block offset from memory into file
*
* \param [in] vhdm MiniVHD data structure
* \param [in] blk The block for which to write the offset for
*/
static void
write_bat_entry(MVHDMeta *vhdm, int blk)
{
uint64_t table_offset = vhdm->sparse.bat_offset + ((uint64_t)blk * sizeof *vhdm->block_offset);
uint32_t offset = mvhd_to_be32(vhdm->block_offset[blk]);
mvhd_fseeko64(vhdm->f, table_offset, SEEK_SET);
fwrite(&offset, sizeof offset, 1, vhdm->f);
}
/**
* \brief Create an empty block in a sparse or differencing VHD image
*
* VHD images store data in blocks, which are typically 4096 sectors in size
* (~2MB). These blocks may be stored on disk in any order. Blocks are created
* on demand when required.
*
* This function creates new, empty blocks, by replacing the footer at the end of the file
* and then re-inserting the footer at the new file end. The BAT table entry for the
* new block is updated with the new offset.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] blk The block number to create
*/
static void
create_block(MVHDMeta *vhdm, int blk)
{
uint8_t footer[MVHD_FOOTER_SIZE] = { 0 };
/* Seek to where the footer SHOULD be */
mvhd_fseeko64(vhdm->f, -MVHD_FOOTER_SIZE, SEEK_END);
(void) !fread(footer, sizeof footer, 1, vhdm->f);
mvhd_fseeko64(vhdm->f, -MVHD_FOOTER_SIZE, SEEK_END);
if (!mvhd_is_conectix_str(footer)) {
/* Oh dear. We use the header instead, since something has gone wrong at the footer */
mvhd_fseeko64(vhdm->f, 0, SEEK_SET);
(void) !fread(footer, sizeof footer, 1, vhdm->f);
mvhd_fseeko64(vhdm->f, 0, SEEK_END);
}
int64_t abs_offset = mvhd_ftello64(vhdm->f);
if ((abs_offset % MVHD_SECTOR_SIZE) != 0) {
/* Yikes! We're supposed to be on a sector boundary. Add some padding */
int64_t padding_amount = ((int64_t) MVHD_SECTOR_SIZE) - (abs_offset % MVHD_SECTOR_SIZE);
uint8_t zero_byte = 0;
for (int i = 0; i < padding_amount; i++)
fwrite(&zero_byte, sizeof zero_byte, 1, vhdm->f);
abs_offset += padding_amount;
}
uint32_t sect_offset = (uint32_t)(abs_offset / MVHD_SECTOR_SIZE);
int blk_size_sectors = vhdm->sparse.block_sz / MVHD_SECTOR_SIZE;
mvhd_write_empty_sectors(vhdm->f, vhdm->bitmap.sector_count + blk_size_sectors);
/* Add a bit of padding. That's what Windows appears to do, although it's not strictly necessary... */
mvhd_write_empty_sectors(vhdm->f, 5);
/* And we finish with the footer */
fwrite(footer, sizeof footer, 1, vhdm->f);
/* We no longer have a sparse block. Update that BAT! */
vhdm->block_offset[blk] = sect_offset;
write_bat_entry(vhdm, blk);
}
int
mvhd_fixed_read(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *out_buff) {
int64_t addr = 0ULL;
int transfer_sectors = 0;
int truncated_sectors = 0;
uint32_t total_sectors = (uint32_t)(vhdm->footer.curr_sz / MVHD_SECTOR_SIZE);
check_sectors(offset, num_sectors, total_sectors, &transfer_sectors, &truncated_sectors);
addr = ((int64_t) offset) * MVHD_SECTOR_SIZE;
mvhd_fseeko64(vhdm->f, addr, SEEK_SET);
(void) !fread(out_buff, transfer_sectors * MVHD_SECTOR_SIZE, 1, vhdm->f);
return truncated_sectors;
}
int
mvhd_sparse_read(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *out_buff)
{
int transfer_sectors = 0;
int truncated_sectors;
uint32_t total_sectors = (uint32_t)(vhdm->footer.curr_sz / MVHD_SECTOR_SIZE);
check_sectors(offset, num_sectors, total_sectors, &transfer_sectors, &truncated_sectors);
uint8_t* buff = (uint8_t*)out_buff;
int64_t addr = 0ULL;
uint32_t s = 0;
uint32_t ls = 0;
int blk = 0;
int prev_blk = -1;
int sib = 0;
ls = offset + transfer_sectors;
for (s = offset; s < ls; s++) {
blk = s / vhdm->sect_per_block;
sib = s % vhdm->sect_per_block;
if (blk != prev_blk) {
prev_blk = blk;
if (vhdm->bitmap.curr_block != blk) {
read_sect_bitmap(vhdm, blk);
mvhd_fseeko64(vhdm->f, (uint64_t)sib * MVHD_SECTOR_SIZE, SEEK_CUR);
} else {
addr = (((int64_t) vhdm->block_offset[blk]) + vhdm->bitmap.sector_count + sib) *
MVHD_SECTOR_SIZE;
mvhd_fseeko64(vhdm->f, addr, SEEK_SET);
}
}
if (VHD_TESTBIT(vhdm->bitmap.curr_bitmap, sib))
(void) !fread(buff, MVHD_SECTOR_SIZE, 1, vhdm->f);
else {
memset(buff, 0, MVHD_SECTOR_SIZE);
mvhd_fseeko64(vhdm->f, MVHD_SECTOR_SIZE, SEEK_CUR);
}
buff += MVHD_SECTOR_SIZE;
}
return truncated_sectors;
}
int
mvhd_diff_read(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *out_buff)
{
int transfer_sectors = 0;
int truncated_sectors = 0;
uint32_t total_sectors = (uint32_t)(vhdm->footer.curr_sz / MVHD_SECTOR_SIZE);
check_sectors(offset, num_sectors, total_sectors, &transfer_sectors, &truncated_sectors);
uint8_t *buff = (uint8_t*)out_buff;
MVHDMeta *curr_vhdm = vhdm;
uint32_t s = 0;
uint32_t ls = 0;
int blk = 0;
int sib = 0;
ls = offset + transfer_sectors;
for (s = offset; s < ls; s++) {
while (curr_vhdm->footer.disk_type == MVHD_TYPE_DIFF) {
blk = s / curr_vhdm->sect_per_block;
sib = s % curr_vhdm->sect_per_block;
if (curr_vhdm->bitmap.curr_block != blk) {
read_sect_bitmap(curr_vhdm, blk);
}
if (!VHD_TESTBIT(curr_vhdm->bitmap.curr_bitmap, sib)) {
curr_vhdm = curr_vhdm->parent;
} else { break; }
}
/* We handle actual sector reading using the fixed or sparse functions,
as a differencing VHD is also a sparse VHD */
if ((curr_vhdm->footer.disk_type == MVHD_TYPE_DIFF) ||
(curr_vhdm->footer.disk_type == MVHD_TYPE_DYNAMIC))
mvhd_sparse_read(curr_vhdm, s, 1, buff);
else
mvhd_fixed_read(curr_vhdm, s, 1, buff);
curr_vhdm = vhdm;
buff += MVHD_SECTOR_SIZE;
}
return truncated_sectors;
}
int
mvhd_fixed_write(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *in_buff)
{
int64_t addr = 0ULL;
int transfer_sectors = 0;
int truncated_sectors = 0;
uint32_t total_sectors = (uint32_t)(vhdm->footer.curr_sz / MVHD_SECTOR_SIZE);
check_sectors(offset, num_sectors, total_sectors, &transfer_sectors, &truncated_sectors);
addr = (int64_t)offset * MVHD_SECTOR_SIZE;
mvhd_fseeko64(vhdm->f, addr, SEEK_SET);
fwrite(in_buff, transfer_sectors * MVHD_SECTOR_SIZE, 1, vhdm->f);
return truncated_sectors;
}
int
mvhd_sparse_diff_write(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *in_buff)
{
int transfer_sectors = 0;
int truncated_sectors = 0;
uint32_t total_sectors = (uint32_t)(vhdm->footer.curr_sz / MVHD_SECTOR_SIZE);
check_sectors(offset, num_sectors, total_sectors, &transfer_sectors, &truncated_sectors);
uint8_t* buff = (uint8_t *) in_buff;
int64_t addr = 0ULL;
uint32_t s = 0;
uint32_t ls = 0;
int blk = 0;
int prev_blk = -1;
int sib = 0;
ls = offset + transfer_sectors;
for (s = offset; s < ls; s++) {
blk = s / vhdm->sect_per_block;
sib = s % vhdm->sect_per_block;
if (vhdm->bitmap.curr_block != blk && prev_blk >= 0) {
/* Write the sector bitmap for the previous block, before we replace it. */
write_curr_sect_bitmap(vhdm);
}
if (vhdm->block_offset[blk] == MVHD_SPARSE_BLK) {
/* "read" the sector bitmap first, before creating a new block, as the bitmap will be
zero either way */
read_sect_bitmap(vhdm, blk);
create_block(vhdm, blk);
}
if (blk != prev_blk) {
if (vhdm->bitmap.curr_block != blk) {
read_sect_bitmap(vhdm, blk);
mvhd_fseeko64(vhdm->f, (uint64_t)sib * MVHD_SECTOR_SIZE, SEEK_CUR);
} else {
addr = (((int64_t) vhdm->block_offset[blk]) + vhdm->bitmap.sector_count + sib) *
MVHD_SECTOR_SIZE;
mvhd_fseeko64(vhdm->f, addr, SEEK_SET);
}
prev_blk = blk;
}
fwrite(buff, MVHD_SECTOR_SIZE, 1, vhdm->f);
VHD_SETBIT(vhdm->bitmap.curr_bitmap, sib);
buff += MVHD_SECTOR_SIZE;
}
/* And write the sector bitmap for the last block we visited to disk */
write_curr_sect_bitmap(vhdm);
return truncated_sectors;
}
int
mvhd_noop_write(MVHDMeta *vhdm, uint32_t offset, int num_sectors, void *in_buff)
{
(void) vhdm;
(void) offset;
(void) num_sectors;
(void) in_buff;
return 0;
}
``` | /content/code_sandbox/src/disk/minivhd/minivhd_io.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,852 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Version: @(#)convert.c 1.0.2 2021/04/16
*
* Authors: Sherman Perry, <shermperry@gmail.com>
* Fred N. van Kempen, <waltje@varcem.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <stdbool.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include "minivhd.h"
#include "internal.h"
static FILE*
open_existing_raw_img(const char* utf8_raw_path, MVHDGeom* geom, int* err)
{
if (geom == NULL) {
*err = MVHD_ERR_INVALID_GEOM;
return NULL;
}
FILE *raw_img = mvhd_fopen(utf8_raw_path, "rb", err);
if (raw_img == NULL) {
*err = MVHD_ERR_FILE;
return NULL;
}
mvhd_fseeko64(raw_img, 0, SEEK_END);
uint64_t size_bytes = (uint64_t)mvhd_ftello64(raw_img);
MVHDGeom new_geom = mvhd_calculate_geometry(size_bytes);
if (mvhd_calc_size_bytes(&new_geom) != size_bytes) {
*err = MVHD_ERR_CONV_SIZE;
return NULL;
}
geom->cyl = new_geom.cyl;
geom->heads = new_geom.heads;
geom->spt = new_geom.spt;
mvhd_fseeko64(raw_img, 0, SEEK_SET);
return raw_img;
}
MVHDAPI MVHDMeta*
mvhd_convert_to_vhd_fixed(const char* utf8_raw_path, const char* utf8_vhd_path, int* err)
{
MVHDGeom geom;
FILE *raw_img = open_existing_raw_img(utf8_raw_path, &geom, err);
if (raw_img == NULL) {
return NULL;
}
uint64_t size_in_bytes = mvhd_calc_size_bytes(&geom);
MVHDMeta *vhdm = mvhd_create_fixed_raw(utf8_vhd_path, raw_img, size_in_bytes, &geom, err, NULL);
if (vhdm == NULL) {
return NULL;
}
return vhdm;
}
MVHDAPI MVHDMeta*
mvhd_convert_to_vhd_sparse(const char* utf8_raw_path, const char* utf8_vhd_path, int* err)
{
MVHDGeom geom;
MVHDMeta *vhdm = NULL;
FILE *raw_img = open_existing_raw_img(utf8_raw_path, &geom, err);
if (raw_img == NULL) {
return NULL;
}
vhdm = mvhd_create_sparse(utf8_vhd_path, geom, err);
if (vhdm == NULL) {
goto end;
}
uint8_t buff[4096] = {0}; // 8 sectors
uint8_t empty_buff[4096] = {0};
int total_sectors = mvhd_calc_size_sectors(&geom);
int copy_sect = 0;
for (int i = 0; i < total_sectors; i += 8) {
copy_sect = 8;
if ((i + 8) >= total_sectors) {
copy_sect = total_sectors - i;
memset(buff, 0, sizeof buff);
}
(void) !fread(buff, MVHD_SECTOR_SIZE, copy_sect, raw_img);
/* Only write data if there's data to write, to take advantage of the sparse VHD format */
if (memcmp(buff, empty_buff, sizeof buff) != 0) {
mvhd_write_sectors(vhdm, i, copy_sect, buff);
}
}
end:
fclose(raw_img);
return vhdm;
}
MVHDAPI FILE*
mvhd_convert_to_raw(const char* utf8_vhd_path, const char* utf8_raw_path, int *err)
{
FILE *raw_img = mvhd_fopen(utf8_raw_path, "wb", err);
if (raw_img == NULL) {
return NULL;
}
MVHDMeta *vhdm = mvhd_open(utf8_vhd_path, true, err);
if (vhdm == NULL) {
fclose(raw_img);
return NULL;
}
uint8_t buff[4096] = {0}; // 8 sectors
int total_sectors = mvhd_calc_size_sectors((MVHDGeom*)&vhdm->footer.geom);
int copy_sect = 0;
for (int i = 0; i < total_sectors; i += 8) {
copy_sect = 8;
if ((i + 8) >= total_sectors) {
copy_sect = total_sectors - i;
}
mvhd_read_sectors(vhdm, i, copy_sect, buff);
fwrite(buff, MVHD_SECTOR_SIZE, copy_sect, raw_img);
}
mvhd_close(vhdm);
mvhd_fseeko64(raw_img, 0, SEEK_SET);
return raw_img;
}
``` | /content/code_sandbox/src/disk/minivhd/convert.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,427 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Version: @(#)create.c 1.0.3 2021/04/16
*
* Authors: Sherman Perry, <shermperry@gmail.com>
* Fred N. van Kempen, <waltje@varcem.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <assert.h>
#include <stdbool.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <time.h>
#include "minivhd.h"
#include "internal.h"
#include "cwalk.h"
#include "xml2_encoding.h"
static const char MVHD_CONECTIX_COOKIE[] = "conectix";
static const char MVHD_CREATOR[] = "mVHD";
static const char MVHD_CREATOR_HOST_OS[] = "Wi2k";
static const char MVHD_CXSPARSE_COOKIE[] = "cxsparse";
/**
* \brief Populate a VHD footer
*
* \param [in] footer to populate
* \param [in] size_in_bytes is the total size of the virtual hard disk in bytes
* \param [in] geom to use
* \param [in] type of HVD that is being created
* \param [in] sparse_header_off, an absolute file offset to the sparse header. Not used for fixed VHD images
*/
static void
gen_footer(MVHDFooter* footer, uint64_t size_in_bytes, MVHDGeom* geom, MVHDType type, uint64_t sparse_header_off)
{
memcpy(footer->cookie, MVHD_CONECTIX_COOKIE, sizeof footer->cookie);
footer->features = 0x00000002;
footer->fi_fmt_vers = 0x00010000;
footer->data_offset = (type == MVHD_TYPE_DIFF || type == MVHD_TYPE_DYNAMIC) ? sparse_header_off : 0xffffffffffffffff;
footer->timestamp = vhd_calc_timestamp();
memcpy(footer->cr_app, MVHD_CREATOR, sizeof footer->cr_app);
footer->cr_vers = 0x000e0000;
memcpy(footer->cr_host_os, MVHD_CREATOR_HOST_OS, sizeof footer->cr_host_os);
footer->orig_sz = footer->curr_sz = size_in_bytes;
footer->geom.cyl = geom->cyl;
footer->geom.heads = geom->heads;
footer->geom.spt = geom->spt;
footer->disk_type = type;
mvhd_generate_uuid(footer->uuid);
footer->checksum = mvhd_gen_footer_checksum(footer);
}
/**
* \brief Populate a VHD sparse header
*
* \param [in] header for sparse and differencing images
* \param [in] num_blks is the number of data blocks that the image contains
* \param [in] bat_offset is the absolute file offset for start of the Block Allocation Table
* \param [in] block_size_in_sectors is the block size in sectors.
*/
static void
gen_sparse_header(MVHDSparseHeader* header, uint32_t num_blks, uint64_t bat_offset, uint32_t block_size_in_sectors)
{
memcpy(header->cookie, MVHD_CXSPARSE_COOKIE, sizeof header->cookie);
header->data_offset = 0xffffffffffffffff;
header->bat_offset = bat_offset;
header->head_vers = 0x00010000;
header->max_bat_ent = num_blks;
header->block_sz = block_size_in_sectors * (uint32_t)MVHD_SECTOR_SIZE;
header->checksum = mvhd_gen_sparse_checksum(header);
}
/**
* \brief Generate parent locators for differencing VHD images
*
* \param [in] header the sparse header to populate with parent locator entries
* \param [in] child_path is the full path to the VHD being created
* \param [in] par_path is the full path to the parent image
* \param [in] start_offset is the absolute file offset from where to start storing the entries themselves. Must be sector aligned.
* \param [out] w2ku_path_buff is a buffer containing the full path to the parent, encoded as UTF16-LE
* \param [out] w2ru_path_buff is a buffer containing the relative path to the parent, encoded as UTF16-LE
* \param [out] err indicates what error occurred, if any
*
* \retval 0 if success
* \retval < 0 if an error occurrs. Check value of *err for actual error
*/
static int
gen_par_loc(MVHDSparseHeader* header, const char* child_path,
const char* par_path, uint64_t start_offset,
mvhd_utf16* w2ku_path_buff, mvhd_utf16* w2ru_path_buff,
MVHDError* err)
{
/* Get our paths to store in the differencing VHD. We want both the absolute path to the parent,
as well as the relative path from the child VHD */
int rv = 0;
char* par_filename;
size_t par_fn_len;
char rel_path[MVHD_MAX_PATH_BYTES] = {0};
char child_dir[MVHD_MAX_PATH_BYTES] = {0};
size_t child_dir_len;
if (strlen(child_path) < sizeof child_dir) {
strcpy(child_dir, child_path);
} else {
*err = MVHD_ERR_PATH_LEN;
rv = -1;
goto end;
}
cwk_path_get_basename(par_path, (const char**)&par_filename, &par_fn_len);
cwk_path_get_dirname(child_dir, &child_dir_len);
child_dir[child_dir_len] = '\0';
size_t rel_len = cwk_path_get_relative(child_dir, par_path, rel_path, sizeof rel_path);
if (rel_len > sizeof rel_path) {
*err = MVHD_ERR_PATH_LEN;
rv = -1;
goto end;
}
/* We have our paths, now store the parent filename directly in the sparse header. */
int outlen = sizeof header->par_utf16_name;
int utf_ret;
utf_ret = UTF8ToUTF16BE((unsigned char*)header->par_utf16_name, &outlen, (const unsigned char*)par_filename, (int*)&par_fn_len);
if (utf_ret < 0) {
mvhd_set_encoding_err(utf_ret, (int*)err);
rv = -1;
goto end;
}
/* And encode the paths to UTF16-LE */
size_t par_path_len = strlen(par_path);
outlen = sizeof *w2ku_path_buff * MVHD_MAX_PATH_CHARS;
utf_ret = UTF8ToUTF16LE((unsigned char*)w2ku_path_buff, &outlen, (const unsigned char*)par_path, (int*)&par_path_len);
if (utf_ret < 0) {
mvhd_set_encoding_err(utf_ret, (int*)err);
rv = -1;
goto end;
}
int w2ku_len = utf_ret;
outlen = sizeof *w2ru_path_buff * MVHD_MAX_PATH_CHARS;
utf_ret = UTF8ToUTF16LE((unsigned char*)w2ru_path_buff, &outlen, (const unsigned char*)rel_path, (int*)&rel_len);
if (utf_ret < 0) {
mvhd_set_encoding_err(utf_ret, (int*)err);
rv = -1;
goto end;
}
int w2ru_len = utf_ret;
/**
* Finally populate the parent locaters in the sparse header.
* This is the information needed to find the paths saved elsewhere
* in the VHD image
*/
/* Note about the plat_data_space field: The VHD spec says this field stores the number of sectors needed to store the locator path.
* However, Hyper-V and VPC store the number of bytes, not the number of sectors, and will refuse to open VHDs which have the
* number of sectors in this field.
* See path_to_url
*/
header->par_loc_entry[0].plat_code = MVHD_DIF_LOC_W2KU;
header->par_loc_entry[0].plat_data_len = (uint32_t)w2ku_len;
header->par_loc_entry[0].plat_data_offset = (uint64_t)start_offset;
header->par_loc_entry[0].plat_data_space = ((header->par_loc_entry[0].plat_data_len / MVHD_SECTOR_SIZE) + 1) * MVHD_SECTOR_SIZE;
header->par_loc_entry[1].plat_code = MVHD_DIF_LOC_W2RU;
header->par_loc_entry[1].plat_data_len = (uint32_t)w2ru_len;
header->par_loc_entry[1].plat_data_offset = (uint64_t)start_offset + ((uint64_t)header->par_loc_entry[0].plat_data_space);
header->par_loc_entry[1].plat_data_space = ((header->par_loc_entry[1].plat_data_len / MVHD_SECTOR_SIZE) + 1) * MVHD_SECTOR_SIZE;
goto end;
end:
return rv;
}
MVHDAPI MVHDMeta*
mvhd_create_fixed(const char* path, MVHDGeom geom, int* err, mvhd_progress_callback progress_callback)
{
uint64_t size_in_bytes = mvhd_calc_size_bytes(&geom);
return mvhd_create_fixed_raw(path, NULL, size_in_bytes, &geom, err, progress_callback);
}
/**
* \brief internal function that implements public mvhd_create_fixed() functionality
*
* Contains one more parameter than the public function, to allow using an existing
* raw disk image as the data source for the new fixed VHD.
*
* \param [in] raw_image file handle to a raw disk image to populate VHD
*/
MVHDMeta*
mvhd_create_fixed_raw(const char* path, FILE* raw_img, uint64_t size_in_bytes, MVHDGeom* geom, int* err, mvhd_progress_callback progress_callback)
{
uint8_t img_data[MVHD_SECTOR_SIZE] = {0};
uint8_t footer_buff[MVHD_FOOTER_SIZE] = {0};
if (geom == NULL || (geom->cyl == 0 || geom->heads == 0 || geom->spt == 0)) {
*err = MVHD_ERR_INVALID_GEOM;
return NULL;
}
MVHDMeta* vhdm = calloc(1, sizeof *vhdm);
if (vhdm == NULL) {
*err = MVHD_ERR_MEM;
goto end;
}
FILE* fp = mvhd_fopen(path, "wb+", err);
if (fp == NULL) {
goto cleanup_vhdm;
}
mvhd_fseeko64(fp, 0, SEEK_SET);
uint32_t size_sectors = (uint32_t)(size_in_bytes / MVHD_SECTOR_SIZE);
uint32_t s;
if (progress_callback)
progress_callback(0, size_sectors);
if (raw_img != NULL) {
mvhd_fseeko64(raw_img, 0, SEEK_END);
uint64_t raw_size = (uint64_t)mvhd_ftello64(raw_img);
MVHDGeom raw_geom = mvhd_calculate_geometry(raw_size);
if (mvhd_calc_size_bytes(&raw_geom) != raw_size) {
*err = MVHD_ERR_CONV_SIZE;
goto cleanup_vhdm;
}
gen_footer(&vhdm->footer, raw_size, geom, MVHD_TYPE_FIXED, 0);
mvhd_fseeko64(raw_img, 0, SEEK_SET);
for (s = 0; s < size_sectors; s++) {
(void) !fread(img_data, sizeof img_data, 1, raw_img);
fwrite(img_data, sizeof img_data, 1, fp);
if (progress_callback)
progress_callback(s + 1, size_sectors);
}
} else {
gen_footer(&vhdm->footer, size_in_bytes, geom, MVHD_TYPE_FIXED, 0);
for (s = 0; s < size_sectors; s++) {
fwrite(img_data, sizeof img_data, 1, fp);
if (progress_callback)
progress_callback(s + 1, size_sectors);
}
}
mvhd_footer_to_buffer(&vhdm->footer, footer_buff);
fwrite(footer_buff, sizeof footer_buff, 1, fp);
fclose(fp);
fp = NULL;
free(vhdm);
vhdm = mvhd_open(path, false, err);
goto end;
cleanup_vhdm:
free(vhdm);
vhdm = NULL;
end:
return vhdm;
}
/**
* \brief Create sparse or differencing VHD image.
*
* \param [in] path is the absolute path to the VHD file to create
* \param [in] par_path is the absolute path to a parent image. If NULL, a sparse image is created, otherwise create a differencing image
* \param [in] size_in_bytes is the total size in bytes of the virtual hard disk image
* \param [in] geom is the HDD geometry of the image to create. Determines final image size
* \param [in] block_size_in_sectors is the block size in sectors
* \param [out] err indicates what error occurred, if any
*
* \return NULL if an error occurrs. Check value of *err for actual error. Otherwise returns pointer to a MVHDMeta struct
*/
static MVHDMeta*
create_sparse_diff(const char* path, const char* par_path, uint64_t size_in_bytes, MVHDGeom* geom, uint32_t block_size_in_sectors, int* err)
{
uint8_t footer_buff[MVHD_FOOTER_SIZE] = {0};
uint8_t sparse_buff[MVHD_SPARSE_SIZE] = {0};
uint8_t bat_sect[MVHD_SECTOR_SIZE] = {0};
MVHDGeom par_geom = {0};
memset(bat_sect, 0xffffffff, sizeof bat_sect);
MVHDMeta* vhdm = NULL;
MVHDMeta* par_vhdm = NULL;
mvhd_utf16* w2ku_path_buff = NULL;
mvhd_utf16* w2ru_path_buff = NULL;
uint32_t par_mod_timestamp = 0;
if (par_path != NULL) {
par_mod_timestamp = mvhd_file_mod_timestamp(par_path, err);
if (*err != 0) {
goto end;
}
par_vhdm = mvhd_open(par_path, true, err);
if (par_vhdm == NULL) {
goto end;
}
}
vhdm = calloc(1, sizeof *vhdm);
if (vhdm == NULL) {
*err = MVHD_ERR_MEM;
goto cleanup_par_vhdm;
}
if (par_vhdm != NULL) {
/* We use the geometry from the parent VHD, not what was passed in */
par_geom.cyl = par_vhdm->footer.geom.cyl;
par_geom.heads = par_vhdm->footer.geom.heads;
par_geom.spt = par_vhdm->footer.geom.spt;
geom = &par_geom;
size_in_bytes = par_vhdm->footer.curr_sz;
} else if (geom == NULL || (geom->cyl == 0 || geom->heads == 0 || geom->spt == 0)) {
*err = MVHD_ERR_INVALID_GEOM;
goto cleanup_vhdm;
}
FILE* fp = mvhd_fopen(path, "wb+", err);
if (fp == NULL) {
goto cleanup_vhdm;
}
mvhd_fseeko64(fp, 0, SEEK_SET);
/* Note, the sparse header follows the footer copy at the beginning of the file */
if (par_path == NULL) {
gen_footer(&vhdm->footer, size_in_bytes, geom, MVHD_TYPE_DYNAMIC, MVHD_FOOTER_SIZE);
} else {
gen_footer(&vhdm->footer, size_in_bytes, geom, MVHD_TYPE_DIFF, MVHD_FOOTER_SIZE);
}
mvhd_footer_to_buffer(&vhdm->footer, footer_buff);
/* As mentioned, start with a copy of the footer */
fwrite(footer_buff, sizeof footer_buff, 1, fp);
/**
* Calculate the number of (2MB or 512KB) data blocks required to store the entire
* contents of the disk image, followed by the number of sectors the
* BAT occupies in the image. Note, the BAT is sector aligned, and is padded
* to the next sector boundary
* */
uint32_t size_in_sectors = (uint32_t)(size_in_bytes / MVHD_SECTOR_SIZE);
uint32_t num_blks = size_in_sectors / block_size_in_sectors;
if (size_in_sectors % block_size_in_sectors != 0) {
num_blks += 1;
}
uint32_t num_bat_sect = num_blks / MVHD_BAT_ENT_PER_SECT;
if (num_blks % MVHD_BAT_ENT_PER_SECT != 0) {
num_bat_sect += 1;
}
/* Storing the BAT directly following the footer and header */
uint64_t bat_offset = MVHD_FOOTER_SIZE + MVHD_SPARSE_SIZE;
uint64_t par_loc_offset = 0;
/**
* If creating a differencing VHD, populate the sparse header with additional
* data about the parent image, and where to find it, and it's last modified timestamp
* */
if (par_vhdm != NULL) {
/**
* Create output buffers to encode paths into.
* The paths are not stored directly in the sparse header, hence the need to
* store them in buffers to be written to the VHD image later
*/
w2ku_path_buff = calloc(MVHD_MAX_PATH_CHARS, sizeof * w2ku_path_buff);
if (w2ku_path_buff == NULL) {
*err = MVHD_ERR_MEM;
goto end;
}
w2ru_path_buff = calloc(MVHD_MAX_PATH_CHARS, sizeof * w2ru_path_buff);
if (w2ru_path_buff == NULL) {
*err = MVHD_ERR_MEM;
goto end;
}
memcpy(vhdm->sparse.par_uuid, par_vhdm->footer.uuid, sizeof vhdm->sparse.par_uuid);
par_loc_offset = bat_offset + ((uint64_t)num_bat_sect * MVHD_SECTOR_SIZE) + (5 * MVHD_SECTOR_SIZE);
if (gen_par_loc(&vhdm->sparse, path, par_path, par_loc_offset, w2ku_path_buff, w2ru_path_buff, (MVHDError*)err) < 0) {
goto cleanup_vhdm;
}
vhdm->sparse.par_timestamp = par_mod_timestamp;
}
gen_sparse_header(&vhdm->sparse, num_blks, bat_offset, block_size_in_sectors);
mvhd_header_to_buffer(&vhdm->sparse, sparse_buff);
fwrite(sparse_buff, sizeof sparse_buff, 1, fp);
/* The BAT sectors need to be filled with 0xffffffff */
for (uint32_t k = 0; k < num_bat_sect; k++) {
fwrite(bat_sect, sizeof bat_sect, 1, fp);
}
mvhd_write_empty_sectors(fp, 5);
/**
* If creating a differencing VHD, the paths to the parent image need to be written
* tp the file. Both absolute and relative paths are written
* */
if (par_vhdm != NULL) {
uint64_t curr_pos = (uint64_t)mvhd_ftello64(fp);
/* Double check my sums... */
assert(curr_pos == par_loc_offset);
/* Fill the space required for location data with zero */
uint8_t empty_sect[MVHD_SECTOR_SIZE] = {0};
for (int i = 0; i < 2; i++) {
for (uint32_t j = 0; j < (vhdm->sparse.par_loc_entry[i].plat_data_space / MVHD_SECTOR_SIZE); j++) {
fwrite(empty_sect, sizeof empty_sect, 1, fp);
}
}
/* Now write the location entries */
mvhd_fseeko64(fp, vhdm->sparse.par_loc_entry[0].plat_data_offset, SEEK_SET);
fwrite(w2ku_path_buff, vhdm->sparse.par_loc_entry[0].plat_data_len, 1, fp);
mvhd_fseeko64(fp, vhdm->sparse.par_loc_entry[1].plat_data_offset, SEEK_SET);
fwrite(w2ru_path_buff, vhdm->sparse.par_loc_entry[1].plat_data_len, 1, fp);
/* and reset the file position to continue */
mvhd_fseeko64(fp, vhdm->sparse.par_loc_entry[1].plat_data_offset + vhdm->sparse.par_loc_entry[1].plat_data_space, SEEK_SET);
mvhd_write_empty_sectors(fp, 5);
}
/* And finish with the footer */
fwrite(footer_buff, sizeof footer_buff, 1, fp);
fclose(fp);
fp = NULL;
free(vhdm);
vhdm = mvhd_open(path, false, err);
goto end;
cleanup_vhdm:
free(vhdm);
vhdm = NULL;
cleanup_par_vhdm:
if (par_vhdm != NULL) {
mvhd_close(par_vhdm);
}
end:
free(w2ku_path_buff);
free(w2ru_path_buff);
return vhdm;
}
MVHDAPI MVHDMeta*
mvhd_create_sparse(const char* path, MVHDGeom geom, int* err)
{
uint64_t size_in_bytes = mvhd_calc_size_bytes(&geom);
return create_sparse_diff(path, NULL, size_in_bytes, &geom, MVHD_BLOCK_LARGE, err);
}
MVHDAPI MVHDMeta*
mvhd_create_diff(const char* path, const char* par_path, int* err)
{
return create_sparse_diff(path, par_path, 0, NULL, MVHD_BLOCK_LARGE, err);
}
MVHDAPI MVHDMeta*
mvhd_create_ex(MVHDCreationOptions options, int* err)
{
uint32_t geom_sector_size;
switch (options.type) {
case MVHD_TYPE_FIXED:
case MVHD_TYPE_DYNAMIC:
geom_sector_size = mvhd_calc_size_sectors(&(options.geometry));
if ((options.size_in_bytes > 0 && (options.size_in_bytes % MVHD_SECTOR_SIZE) > 0)
|| (options.size_in_bytes > MVHD_MAX_SIZE_IN_BYTES)
|| (options.size_in_bytes == 0 && geom_sector_size == 0)) {
*err = MVHD_ERR_INVALID_SIZE;
return NULL;
}
if (options.size_in_bytes > 0 && ((uint64_t)geom_sector_size * MVHD_SECTOR_SIZE) > options.size_in_bytes) {
*err = MVHD_ERR_INVALID_GEOM;
return NULL;
}
if (options.size_in_bytes == 0)
options.size_in_bytes = (uint64_t)geom_sector_size * MVHD_SECTOR_SIZE;
if (geom_sector_size == 0)
options.geometry = mvhd_calculate_geometry(options.size_in_bytes);
break;
case MVHD_TYPE_DIFF:
if (options.parent_path == NULL) {
*err = MVHD_ERR_FILE;
return NULL;
}
break;
default:
*err = MVHD_ERR_TYPE;
return NULL;
}
if (options.path == NULL) {
*err = MVHD_ERR_FILE;
return NULL;
}
if (options.type != MVHD_TYPE_FIXED) {
if (options.block_size_in_sectors == MVHD_BLOCK_DEFAULT)
options.block_size_in_sectors = MVHD_BLOCK_LARGE;
if (options.block_size_in_sectors != MVHD_BLOCK_LARGE && options.block_size_in_sectors != MVHD_BLOCK_SMALL) {
*err = MVHD_ERR_INVALID_BLOCK_SIZE;
return NULL;
}
}
switch (options.type) {
case MVHD_TYPE_FIXED:
return mvhd_create_fixed_raw(options.path, NULL, options.size_in_bytes, &(options.geometry), err, options.progress_callback);
case MVHD_TYPE_DYNAMIC:
return create_sparse_diff(options.path, NULL, options.size_in_bytes, &(options.geometry), options.block_size_in_sectors, err);
case MVHD_TYPE_DIFF:
return create_sparse_diff(options.path, options.parent_path, 0, NULL, options.block_size_in_sectors, err);
}
return NULL; /* Make the compiler happy */
}
bool
mvhd_is_conectix_str(const void* buffer)
{
if (strncmp(buffer, MVHD_CONECTIX_COOKIE, strlen(MVHD_CONECTIX_COOKIE)) == 0) {
return true;
}
return false;
}
``` | /content/code_sandbox/src/disk/minivhd/create.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,792 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Utility functions.
*
* Version: @(#)util.c 1.0.4 2021/04/16
*
* Author: Sherman Perry, <shermperry@gmail.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <errno.h>
#include <stdlib.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "minivhd.h"
#include "internal.h"
#include "xml2_encoding.h"
uint16_t
mvhd_from_be16(uint16_t val)
{
uint8_t *tmp = (uint8_t*)&val;
uint16_t ret = 0;
ret |= (uint16_t)tmp[0] << 8;
ret |= (uint16_t)tmp[1] << 0;
return ret;
}
uint32_t
mvhd_from_be32(uint32_t val)
{
uint8_t *tmp = (uint8_t*)&val;
uint32_t ret = 0;
ret = (uint32_t)tmp[0] << 24;
ret |= (uint32_t)tmp[1] << 16;
ret |= (uint32_t)tmp[2] << 8;
ret |= (uint32_t)tmp[3] << 0;
return ret;
}
uint64_t
mvhd_from_be64(uint64_t val)
{
uint8_t *tmp = (uint8_t*)&val;
uint64_t ret = 0;
ret = (uint64_t)tmp[0] << 56;
ret |= (uint64_t)tmp[1] << 48;
ret |= (uint64_t)tmp[2] << 40;
ret |= (uint64_t)tmp[3] << 32;
ret |= (uint64_t)tmp[4] << 24;
ret |= (uint64_t)tmp[5] << 16;
ret |= (uint64_t)tmp[6] << 8;
ret |= (uint64_t)tmp[7] << 0;
return ret;
}
uint16_t
mvhd_to_be16(uint16_t val)
{
uint16_t ret = 0;
uint8_t *tmp = (uint8_t*)&ret;
tmp[0] = (val & 0xff00) >> 8;
tmp[1] = (val & 0x00ff) >> 0;
return ret;
}
uint32_t
mvhd_to_be32(uint32_t val)
{
uint32_t ret = 0;
uint8_t *tmp = (uint8_t*)&ret;
tmp[0] = (val & 0xff000000) >> 24;
tmp[1] = (val & 0x00ff0000) >> 16;
tmp[2] = (val & 0x0000ff00) >> 8;
tmp[3] = (val & 0x000000ff) >> 0;
return ret;
}
uint64_t
mvhd_to_be64(uint64_t val)
{
uint64_t ret = 0;
uint8_t *tmp = (uint8_t*)&ret;
tmp[0] = (uint8_t)((val & 0xff00000000000000) >> 56);
tmp[1] = (uint8_t)((val & 0x00ff000000000000) >> 48);
tmp[2] = (uint8_t)((val & 0x0000ff0000000000) >> 40);
tmp[3] = (uint8_t)((val & 0x000000ff00000000) >> 32);
tmp[4] = (uint8_t)((val & 0x00000000ff000000) >> 24);
tmp[5] = (uint8_t)((val & 0x0000000000ff0000) >> 16);
tmp[6] = (uint8_t)((val & 0x000000000000ff00) >> 8);
tmp[7] = (uint8_t)((val & 0x00000000000000ff) >> 0);
return ret;
}
void
mvhd_generate_uuid(uint8_t* uuid)
{
/* We aren't doing crypto here, so using system time as seed should be good enough */
srand((unsigned int)time(0));
for (int n = 0; n < 16; n++) {
uuid[n] = rand();
}
uuid[6] &= 0x0F;
uuid[6] |= 0x40; /* Type 4 */
uuid[8] &= 0x3F;
uuid[8] |= 0x80; /* Variant 1 */
}
uint32_t
vhd_calc_timestamp(void)
{
time_t start_time;
time_t curr_time;
double vhd_time;
start_time = MVHD_START_TS; /* 1 Jan 2000 00:00 */
curr_time = time(NULL);
vhd_time = difftime(curr_time, start_time);
return (uint32_t)vhd_time;
}
uint32_t
mvhd_epoch_to_vhd_ts(time_t ts)
{
time_t start_time = MVHD_START_TS;
double vhd_time;
if (ts < start_time)
return (uint32_t)start_time;
vhd_time = difftime(ts, start_time);
return (uint32_t)vhd_time;
}
time_t
vhd_get_created_time(MVHDMeta *vhdm)
{
time_t vhd_time = (time_t)vhdm->footer.timestamp;
time_t vhd_time_unix = MVHD_START_TS + vhd_time;
return vhd_time_unix;
}
FILE*
mvhd_fopen(const char* path, const char* mode, int* err)
{
FILE* f = NULL;
#ifdef _WIN32
size_t path_len = strlen(path);
size_t mode_len = strlen(mode);
mvhd_utf16 new_path[260] = {0};
int new_path_len = (sizeof new_path) - 2;
mvhd_utf16 mode_str[5] = {0};
int new_mode_len = (sizeof mode_str) - 2;
int path_res = UTF8ToUTF16LE((unsigned char*)new_path, &new_path_len, (const unsigned char*)path, (int*)&path_len);
int mode_res = UTF8ToUTF16LE((unsigned char*)mode_str, &new_mode_len, (const unsigned char*)mode, (int*)&mode_len);
if (path_res > 0 && mode_res > 0) {
f = _wfopen(new_path, mode_str);
if (f == NULL) {
mvhd_errno = errno;
*err = MVHD_ERR_FILE;
}
} else {
if (path_res == -1 || mode_res == -1) {
*err = MVHD_ERR_UTF_SIZE;
} else if (path_res == -2 || mode_res == -2) {
*err = MVHD_ERR_UTF_TRANSCODING_FAILED;
}
}
#else
f = fopen(path, mode);
if (f == NULL) {
mvhd_errno = errno;
*err = MVHD_ERR_FILE;
}
#endif
return f;
}
void
mvhd_set_encoding_err(int encoding_retval, int* err)
{
if (encoding_retval == -1) {
*err = MVHD_ERR_UTF_SIZE;
} else if (encoding_retval == -2) {
*err = MVHD_ERR_UTF_TRANSCODING_FAILED;
}
}
uint64_t
mvhd_calc_size_bytes(MVHDGeom *geom)
{
uint64_t img_size = (uint64_t)geom->cyl * (uint64_t)geom->heads * (uint64_t)geom->spt * (uint64_t)MVHD_SECTOR_SIZE;
return img_size;
}
uint32_t
mvhd_calc_size_sectors(MVHDGeom *geom)
{
uint32_t sector_size = (uint32_t)geom->cyl * (uint32_t)geom->heads * (uint32_t)geom->spt;
return sector_size;
}
MVHDAPI MVHDGeom
mvhd_get_geometry(MVHDMeta* vhdm)
{
MVHDGeom geometry = {
.cyl = vhdm->footer.geom.cyl,
.heads = vhdm->footer.geom.heads,
.spt = vhdm->footer.geom.spt
};
return geometry;
}
MVHDAPI uint64_t
mvhd_get_current_size(MVHDMeta* vhdm)
{
return vhdm->footer.curr_sz;
}
uint32_t
mvhd_gen_footer_checksum(MVHDFooter* footer)
{
uint32_t new_chk = 0;
uint32_t orig_chk = footer->checksum;
footer->checksum = 0;
uint8_t* footer_bytes = (uint8_t*)footer;
for (size_t i = 0; i < sizeof *footer; i++)
new_chk += footer_bytes[i];
footer->checksum = orig_chk;
return ~new_chk;
}
uint32_t
mvhd_gen_sparse_checksum(MVHDSparseHeader* header)
{
uint32_t new_chk = 0;
uint32_t orig_chk = header->checksum;
header->checksum = 0;
uint8_t* sparse_bytes = (uint8_t*)header;
for (size_t i = 0; i < sizeof *header; i++) {
new_chk += sparse_bytes[i];
}
header->checksum = orig_chk;
return ~new_chk;
}
MVHDAPI const char*
mvhd_strerr(MVHDError err)
{
const char *s = "unknown error";
switch (err) {
case MVHD_ERR_MEM:
s = "memory allocation error";
break;
case MVHD_ERR_FILE:
s = "file error";
break;
case MVHD_ERR_NOT_VHD:
s = "file is not a VHD image";
break;
case MVHD_ERR_TYPE:
s = "unsupported VHD image type";
break;
case MVHD_ERR_FOOTER_CHECKSUM:
s = "invalid VHD footer checksum";
break;
case MVHD_ERR_SPARSE_CHECKSUM:
s = "invalid VHD sparse header checksum";
break;
case MVHD_ERR_UTF_TRANSCODING_FAILED:
s = "error converting path encoding";
break;
case MVHD_ERR_UTF_SIZE:
s = "buffer size mismatch when converting path encoding";
break;
case MVHD_ERR_PATH_REL:
s = "relative path detected where absolute path expected";
break;
case MVHD_ERR_PATH_LEN:
s = "path length exceeds MVHD_MAX_PATH";
break;
case MVHD_ERR_PAR_NOT_FOUND:
s = "parent VHD image not found";
break;
case MVHD_ERR_INVALID_PAR_UUID:
s = "UUID mismatch between child and parent VHD";
break;
case MVHD_ERR_INVALID_GEOM:
s = "invalid geometry detected";
break;
case MVHD_ERR_INVALID_SIZE:
s = "invalid size";
break;
case MVHD_ERR_INVALID_BLOCK_SIZE:
s = "invalid block size";
break;
case MVHD_ERR_INVALID_PARAMS:
s = "invalid parameters passed to function";
break;
case MVHD_ERR_CONV_SIZE:
s = "error converting image. Size mismatch detected";
break;
default:
break;
}
return s;
}
int64_t
mvhd_ftello64(FILE* stream)
{
#ifdef _MSC_VER
return _ftelli64(stream);
#elif defined(__MINGW32__)
return ftello64(stream);
#else /* This should work with linux (with _FILE_OFFSET_BITS), and hopefully OS X and BSD */
return ftello(stream);
#endif
}
int
mvhd_fseeko64(FILE* stream, int64_t offset, int origin)
{
#ifdef _MSC_VER
return _fseeki64(stream, offset, origin);
#elif defined(__MINGW32__)
return fseeko64(stream, offset, origin);
#else /* This should work with linux (with _FILE_OFFSET_BITS), and hopefully OS X and BSD */
return fseeko(stream, offset, origin);
#endif
}
uint32_t
mvhd_crc32_for_byte(uint32_t r)
{
for (int j = 0; j < 8; ++j)
r = (r & 1 ? 0 : (uint32_t)0xEDB88320L) ^ r >> 1;
return r ^ (uint32_t)0xFF000000L;
}
uint32_t
mvhd_crc32(const void* data, size_t n_bytes)
{
static uint32_t table[0x100];
if (!*table)
for (size_t i = 0; i < 0x100; ++i)
table[i] = mvhd_crc32_for_byte((uint32_t)i);
uint32_t crc = 0;
for (size_t i = 0; i < n_bytes; ++i)
crc = table[(uint8_t)crc ^ ((uint8_t*)data)[i]] ^ crc >> 8;
return crc;
}
uint32_t
mvhd_file_mod_timestamp(const char* path, int *err)
{
*err = 0;
#ifdef _WIN32
struct _stat file_stat = { 0 };
size_t path_len = strlen(path);
mvhd_utf16 new_path[260] = {0};
int new_path_len = (sizeof new_path) - 2;
int path_res = UTF8ToUTF16LE((unsigned char*)new_path, &new_path_len, (const unsigned char*)path, (int*)&path_len);
if (path_res > 0) {
int stat_res = _wstat(new_path, &file_stat);
if (stat_res != 0) {
mvhd_errno = errno;
*err = MVHD_ERR_FILE;
return 0;
}
return mvhd_epoch_to_vhd_ts(file_stat.st_mtime);
} else {
if (path_res == -1) {
*err = MVHD_ERR_UTF_SIZE;
} else if (path_res == -2) {
*err = MVHD_ERR_UTF_TRANSCODING_FAILED;
}
return 0;
}
#else
struct stat file_stat = { 0 };
int stat_res = stat(path, &file_stat);
if (stat_res != 0) {
mvhd_errno = errno;
*err = MVHD_ERR_FILE;
return 0;
}
return mvhd_epoch_to_vhd_ts(file_stat.st_mtime);
#endif
}
``` | /content/code_sandbox/src/disk/minivhd/minivhd_util.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,562 |
```c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Header and footer serialize/deserialize functions.
*
* Read data from footer into the struct members, swapping
* endian where necessary.
*
* NOTE: Order matters here!
* We must read each field in the order the struct is in.
* Doing this may be less elegant than performing a memcpy
* to a packed struct, but it avoids potential data alignment
* issues, and the endian swapping allows us to use the fields
* directly.
*
* Version: @(#)struct_rw.c 1.0.2 2021/04/16
*
* Author: Sherman Perry, <shermperry@gmail.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _FILE_OFFSET_BITS
# define _FILE_OFFSET_BITS 64
#endif
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <time.h>
#include "minivhd.h"
#include "internal.h"
/**
* \brief Get the next field from a buffer and store it in a struct member, converting endian if necessary
*
* \param [out] struct_memb struct member to save the field to
* \param [in] memb_size the size of struct_memb, in bytes
* \param [in] req_endian is the field a value that requires endian conversion (eg: uint16, uint32)
* \param [in] buffer the buffer from which fields are read from. Will be advanced at the end of the function call
*/
static void
next_buffer_to_struct(void* struct_memb, size_t memb_size, bool req_endian, uint8_t** buffer)
{
memcpy(struct_memb, *buffer, memb_size);
if (req_endian) switch (memb_size) {
case 2:
*(uint16_t*)(struct_memb) = mvhd_from_be16(*(uint16_t*)(struct_memb));
break;
case 4:
*(uint32_t*)(struct_memb) = mvhd_from_be32(*(uint32_t*)(struct_memb));
break;
case 8:
*(uint64_t*)(struct_memb) = mvhd_from_be64(*(uint64_t*)(struct_memb));
break;
}
*buffer += memb_size;
}
/**
* \brief Save a struct member into a buffer, converting endian if necessary
*
* \param [in] struct_memb struct member read from
* \param [in] memb_size the size of struct_memb, in bytes
* \param [in] req_endian is the field a value that requires endian conversion (eg: uint16, uint32)
* \param [out] buffer the buffer from which struct member is saved to. Will be advanced at the end of the function call
*/
static void
next_struct_to_buffer(void* struct_memb, size_t memb_size, bool req_endian, uint8_t** buffer)
{
uint8_t *buf_ptr = *buffer;
memcpy(buf_ptr, struct_memb, memb_size);
if (req_endian) switch (memb_size) {
case 2:
*((uint16_t*)buf_ptr) = mvhd_to_be16(*(uint16_t*)(struct_memb));
break;
case 4:
*((uint32_t*)buf_ptr) = mvhd_to_be32(*(uint32_t*)(struct_memb));
break;
case 8:
*((uint64_t*)buf_ptr) = mvhd_to_be64(*(uint64_t*)(struct_memb));
break;
}
buf_ptr += memb_size;
*buffer = buf_ptr;
}
void
mvhd_buffer_to_footer(MVHDFooter* footer, uint8_t* buffer)
{
uint8_t* buff_ptr = buffer;
next_buffer_to_struct(&footer->cookie, sizeof footer->cookie, false, &buff_ptr);
next_buffer_to_struct(&footer->features, sizeof footer->features, true, &buff_ptr);
next_buffer_to_struct(&footer->fi_fmt_vers, sizeof footer->fi_fmt_vers, true, &buff_ptr);
next_buffer_to_struct(&footer->data_offset, sizeof footer->data_offset, true, &buff_ptr);
next_buffer_to_struct(&footer->timestamp, sizeof footer->timestamp, true, &buff_ptr);
next_buffer_to_struct(&footer->cr_app, sizeof footer->cr_app, false, &buff_ptr);
next_buffer_to_struct(&footer->cr_vers, sizeof footer->cr_vers, true, &buff_ptr);
next_buffer_to_struct(&footer->cr_host_os, sizeof footer->cr_host_os, false, &buff_ptr);
next_buffer_to_struct(&footer->orig_sz, sizeof footer->orig_sz, true, &buff_ptr);
next_buffer_to_struct(&footer->curr_sz, sizeof footer->curr_sz, true, &buff_ptr);
next_buffer_to_struct(&footer->geom.cyl, sizeof footer->geom.cyl, true, &buff_ptr);
next_buffer_to_struct(&footer->geom.heads, sizeof footer->geom.heads, false, &buff_ptr);
next_buffer_to_struct(&footer->geom.spt, sizeof footer->geom.spt, false, &buff_ptr);
next_buffer_to_struct(&footer->disk_type, sizeof footer->disk_type, true, &buff_ptr);
next_buffer_to_struct(&footer->checksum, sizeof footer->checksum, true, &buff_ptr);
next_buffer_to_struct(&footer->uuid, sizeof footer->uuid, false, &buff_ptr);
next_buffer_to_struct(&footer->saved_st, sizeof footer->saved_st, false, &buff_ptr);
next_buffer_to_struct(&footer->reserved, sizeof footer->reserved, false, &buff_ptr);
}
void
mvhd_footer_to_buffer(MVHDFooter* footer, uint8_t* buffer)
{
uint8_t* buff_ptr = buffer;
next_struct_to_buffer(&footer->cookie, sizeof footer->cookie, false, &buff_ptr);
next_struct_to_buffer(&footer->features, sizeof footer->features, true, &buff_ptr);
next_struct_to_buffer(&footer->fi_fmt_vers, sizeof footer->fi_fmt_vers, true, &buff_ptr);
next_struct_to_buffer(&footer->data_offset, sizeof footer->data_offset, true, &buff_ptr);
next_struct_to_buffer(&footer->timestamp, sizeof footer->timestamp, true, &buff_ptr);
next_struct_to_buffer(&footer->cr_app, sizeof footer->cr_app, false, &buff_ptr);
next_struct_to_buffer(&footer->cr_vers, sizeof footer->cr_vers, true, &buff_ptr);
next_struct_to_buffer(&footer->cr_host_os, sizeof footer->cr_host_os, false, &buff_ptr);
next_struct_to_buffer(&footer->orig_sz, sizeof footer->orig_sz, true, &buff_ptr);
next_struct_to_buffer(&footer->curr_sz, sizeof footer->curr_sz, true, &buff_ptr);
next_struct_to_buffer(&footer->geom.cyl, sizeof footer->geom.cyl, true, &buff_ptr);
next_struct_to_buffer(&footer->geom.heads, sizeof footer->geom.heads, false, &buff_ptr);
next_struct_to_buffer(&footer->geom.spt, sizeof footer->geom.spt, false, &buff_ptr);
next_struct_to_buffer(&footer->disk_type, sizeof footer->disk_type, true, &buff_ptr);
next_struct_to_buffer(&footer->checksum, sizeof footer->checksum, true, &buff_ptr);
next_struct_to_buffer(&footer->uuid, sizeof footer->uuid, false, &buff_ptr);
next_struct_to_buffer(&footer->saved_st, sizeof footer->saved_st, false, &buff_ptr);
next_struct_to_buffer(&footer->reserved, sizeof footer->reserved, false, &buff_ptr);
}
void
mvhd_buffer_to_header(MVHDSparseHeader* header, uint8_t* buffer)
{
uint8_t* buff_ptr = buffer;
next_buffer_to_struct(&header->cookie, sizeof header->cookie, false, &buff_ptr);
next_buffer_to_struct(&header->data_offset, sizeof header->data_offset, true, &buff_ptr);
next_buffer_to_struct(&header->bat_offset, sizeof header->bat_offset, true, &buff_ptr);
next_buffer_to_struct(&header->head_vers, sizeof header->head_vers, true, &buff_ptr);
next_buffer_to_struct(&header->max_bat_ent, sizeof header->max_bat_ent, true, &buff_ptr);
next_buffer_to_struct(&header->block_sz, sizeof header->block_sz, true, &buff_ptr);
next_buffer_to_struct(&header->checksum, sizeof header->checksum, true, &buff_ptr);
next_buffer_to_struct(&header->par_uuid, sizeof header->par_uuid, false, &buff_ptr);
next_buffer_to_struct(&header->par_timestamp, sizeof header->par_timestamp, true, &buff_ptr);
next_buffer_to_struct(&header->reserved_1, sizeof header->reserved_1, true, &buff_ptr);
next_buffer_to_struct(&header->par_utf16_name, sizeof header->par_utf16_name, false, &buff_ptr);
for (int i = 0; i < 8; i++) {
next_buffer_to_struct(&header->par_loc_entry[i].plat_code, sizeof header->par_loc_entry[i].plat_code, true, &buff_ptr);
next_buffer_to_struct(&header->par_loc_entry[i].plat_data_space, sizeof header->par_loc_entry[i].plat_data_space, true, &buff_ptr);
next_buffer_to_struct(&header->par_loc_entry[i].plat_data_len, sizeof header->par_loc_entry[i].plat_data_len, true, &buff_ptr);
next_buffer_to_struct(&header->par_loc_entry[i].reserved, sizeof header->par_loc_entry[i].reserved, true, &buff_ptr);
next_buffer_to_struct(&header->par_loc_entry[i].plat_data_offset, sizeof header->par_loc_entry[i].plat_data_offset, true, &buff_ptr);
}
next_buffer_to_struct(&header->reserved_2, sizeof header->reserved_2, false, &buff_ptr);
}
void
mvhd_header_to_buffer(MVHDSparseHeader* header, uint8_t* buffer)
{
uint8_t* buff_ptr = buffer;
next_struct_to_buffer(&header->cookie, sizeof header->cookie, false, &buff_ptr);
next_struct_to_buffer(&header->data_offset, sizeof header->data_offset, true, &buff_ptr);
next_struct_to_buffer(&header->bat_offset, sizeof header->bat_offset, true, &buff_ptr);
next_struct_to_buffer(&header->head_vers, sizeof header->head_vers, true, &buff_ptr);
next_struct_to_buffer(&header->max_bat_ent, sizeof header->max_bat_ent, true, &buff_ptr);
next_struct_to_buffer(&header->block_sz, sizeof header->block_sz, true, &buff_ptr);
next_struct_to_buffer(&header->checksum, sizeof header->checksum, true, &buff_ptr);
next_struct_to_buffer(&header->par_uuid, sizeof header->par_uuid, false, &buff_ptr);
next_struct_to_buffer(&header->par_timestamp, sizeof header->par_timestamp, true, &buff_ptr);
next_struct_to_buffer(&header->reserved_1, sizeof header->reserved_1, true, &buff_ptr);
next_struct_to_buffer(&header->par_utf16_name, sizeof header->par_utf16_name, false, &buff_ptr);
for (int i = 0; i < 8; i++) {
next_struct_to_buffer(&header->par_loc_entry[i].plat_code, sizeof header->par_loc_entry[i].plat_code, true, &buff_ptr);
next_struct_to_buffer(&header->par_loc_entry[i].plat_data_space, sizeof header->par_loc_entry[i].plat_data_space, true, &buff_ptr);
next_struct_to_buffer(&header->par_loc_entry[i].plat_data_len, sizeof header->par_loc_entry[i].plat_data_len, true, &buff_ptr);
next_struct_to_buffer(&header->par_loc_entry[i].reserved, sizeof header->par_loc_entry[i].reserved, true, &buff_ptr);
next_struct_to_buffer(&header->par_loc_entry[i].plat_data_offset, sizeof header->par_loc_entry[i].plat_data_offset, true, &buff_ptr);
}
next_struct_to_buffer(&header->reserved_2, sizeof header->reserved_2, false, &buff_ptr);
}
``` | /content/code_sandbox/src/disk/minivhd/struct_rw.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,985 |
```objective-c
/*
* MiniVHD Minimalist VHD implementation in C.
*
* This file is part of the MiniVHD Project.
*
* Internal definitions.
*
* Version: @(#)internal.h 1.0.1 2021/03/15
*
* Author: Sherman Perry, <shermperry@gmail.com>
*
*
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documenta-
* tion files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall
* be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF O R IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MINIVHD_INTERNAL_H
# define MINIVHD_INTERNAL_H
#define MVHD_FOOTER_SIZE 512
#define MVHD_SPARSE_SIZE 1024
#define MVHD_SECTOR_SIZE 512
#define MVHD_BAT_ENT_PER_SECT 128
#define MVHD_MAX_SIZE_IN_BYTES 0x1fe00000000
#define MVHD_SPARSE_BLK 0xffffffff
/* For simplicity, we don't handle paths longer than this
* Note, this is the max path in characters, as that is what
* Windows uses
*/
#define MVHD_MAX_PATH_CHARS 260
#define MVHD_MAX_PATH_BYTES 1040
#define MVHD_DIF_LOC_W2RU 0x57327275
#define MVHD_DIF_LOC_W2KU 0x57326B75
#define MVHD_START_TS 946684800
typedef struct MVHDSectorBitmap {
uint8_t* curr_bitmap;
int sector_count;
int curr_block;
} MVHDSectorBitmap;
typedef struct MVHDFooter {
uint8_t cookie[8];
uint32_t features;
uint32_t fi_fmt_vers;
uint64_t data_offset;
uint32_t timestamp;
uint8_t cr_app[4];
uint32_t cr_vers;
uint8_t cr_host_os[4];
uint64_t orig_sz;
uint64_t curr_sz;
struct {
uint16_t cyl;
uint8_t heads;
uint8_t spt;
} geom;
uint32_t disk_type;
uint32_t checksum;
uint8_t uuid[16];
uint8_t saved_st;
uint8_t reserved[427];
} MVHDFooter;
typedef struct MVHDSparseHeader {
uint8_t cookie[8];
uint64_t data_offset;
uint64_t bat_offset;
uint32_t head_vers;
uint32_t max_bat_ent;
uint32_t block_sz;
uint32_t checksum;
uint8_t par_uuid[16];
uint32_t par_timestamp;
uint32_t reserved_1;
uint8_t par_utf16_name[512];
struct {
uint32_t plat_code;
uint32_t plat_data_space;
uint32_t plat_data_len;
uint32_t reserved;
uint64_t plat_data_offset;
} par_loc_entry[8];
uint8_t reserved_2[256];
} MVHDSparseHeader;
struct MVHDMeta {
FILE* f;
bool readonly;
char filename[MVHD_MAX_PATH_BYTES];
struct MVHDMeta* parent;
MVHDFooter footer;
MVHDSparseHeader sparse;
uint32_t* block_offset;
int sect_per_block;
MVHDSectorBitmap bitmap;
int (*read_sectors)(struct MVHDMeta*, uint32_t, int, void*);
int (*write_sectors)(struct MVHDMeta*, uint32_t, int, void*);
struct {
uint8_t* zero_data;
int sector_count;
} format_buffer;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* Functions to deal with endian issues
*/
uint16_t mvhd_from_be16(uint16_t val);
uint32_t mvhd_from_be32(uint32_t val);
uint64_t mvhd_from_be64(uint64_t val);
uint16_t mvhd_to_be16(uint16_t val);
uint32_t mvhd_to_be32(uint32_t val);
uint64_t mvhd_to_be64(uint64_t val);
/**
* \brief Check if provided buffer begins with the string "conectix"
*
* \param [in] buffer The buffer to compare. Must be at least 8 bytes in length
*
* \return true if the buffer begins with "conectix"
* \return false if the buffer does not begin with "conectix"
*/
bool mvhd_is_conectix_str(const void* buffer);
/**
* \brief Generate a raw 16 byte UUID
*
* \param [out] uuid A 16 byte buffer in which the generated UUID will be stored to
*/
void mvhd_generate_uuid(uint8_t *uuid);
/**
* \brief Calculate a VHD formatted timestamp from the current time
*/
uint32_t vhd_calc_timestamp(void);
/**
* \brief Convert an epoch timestamp to a VHD timestamp
*
* \param [in] ts epoch timestamp to convert.
*
* \return The adjusted timestamp, or 0 if the input timestamp is
* earlier that 1 Janurary 2000
*/
uint32_t mvhd_epoch_to_vhd_ts(time_t ts);
/**
* \brief Return the created time from a VHD image
*
* \param [in] vhdm Pointer to the MiniVHD metadata structure
*
* \return The created time, as a Unix timestamp
*/
time_t vhd_get_created_time(struct MVHDMeta *vhdm);
/**
* \brief Cross platform, unicode filepath opening
*
* This function accounts for the fact that fopen() handles file paths differently compared to other
* operating systems. Windows version of fopen() will not handle multi byte encoded text like UTF-8.
*
* Unicode filepath support on Windows requires using the _wfopen() function, which expects UTF-16LE
* encoded path and modestring.
*
* \param [in] path The filepath to open as a UTF-8 string
* \param [in] mode The mode string to use (eg: "rb+"")
* \param [out] err The error value, if an error occurrs
*
* \return a FILE pointer if successful, NULL otherwise. If NULL, check the value of err
*/
FILE* mvhd_fopen(const char* path, const char* mode, int* err);
void mvhd_set_encoding_err(int encoding_retval, int* err);
/**
* \brief Generate VHD footer checksum
*
* \param [in] vhdm MiniVHD data structure
*/
uint32_t mvhd_gen_footer_checksum(MVHDFooter* footer);
/**
* \brief Generate VHD sparse header checksum
*
* \param [in] vhdm MiniVHD data structure
*/
uint32_t mvhd_gen_sparse_checksum(MVHDSparseHeader* header);
uint32_t mvhd_crc32_for_byte(uint32_t r);
/**
* \brief Get current position in file stream
*
* This is a portable version of the POSIX ftello64(). *
*/
int64_t mvhd_ftello64(FILE* stream);
/**
* \brief Reposition the file stream's position
*
* This is a portable version of the POSIX fseeko64(). *
*/
int mvhd_fseeko64(FILE* stream, int64_t offset, int origin);
/**
* \brief Calculate the CRC32 of a data buffer.
*
* This function can be used for verifying data integrity.
*
* \param [in] data The data buffer
* \param [in] n_bytes The size of the data buffer in bytes
*
* \return The CRC32 of the data buffer
*/
uint32_t mvhd_crc32(const void* data, size_t n_bytes);
/**
* \brief Calculate the file modification timestamp.
*
* This function is primarily to help protect differencing VHD's
*
* \param [in] path the UTF-8 file path
* \param [out] err The error value, if an error occurrs
*
* \return The file modified timestamp, in VHD compatible timestamp.
* 'err' will be set to non-zero on error
*/
uint32_t mvhd_file_mod_timestamp(const char* path, int *err);
struct MVHDMeta* mvhd_create_fixed_raw(const char* path, FILE* raw_img, uint64_t size_in_bytes, MVHDGeom* geom, int* err, mvhd_progress_callback progress_callback);
/**
* \brief Write zero filled sectors to file.
*
* Note, the caller should set the file position before calling this
* function for correct operation.
*
* \param [in] f File to write sectors to
* \param [in] sector_count The number of sectors to write
*/
void mvhd_write_empty_sectors(FILE* f, int sector_count);
/**
* \brief Read a fixed VHD image
*
* Fixed VHD images are essentially raw image files with a footer tacked on
* the end. They are therefore straightforward to write
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to read from
* \param [in] num_sectors The desired number of sectors to read
* \param [out] out_buff An output buffer to store read sectors. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were read from file
* \retval >0 < num_sectors were read from file
*/
int mvhd_fixed_read(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* out_buff);
/**
* \brief Read a sparse VHD image
*
* Sparse, or dynamic images are VHD images that grow as data is written to them.
*
* This function implements the logic to read sectors from the file, taking into
* account the fact that blocks may be stored on disk in any order, and that the
* read could cross block boundaries.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to read from
* \param [in] num_sectors The desired number of sectors to read
* \param [out] out_buff An output buffer to store read sectors. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were read from file
* \retval >0 < num_sectors were read from file
*/
int mvhd_sparse_read(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* out_buff);
/**
* \brief Read a differencing VHD image
*
* Differencing images are a variant of a sparse image. They contain the grow-on-demand
* properties of sparse images, but also reference a parent image. Data is read from the
* child image only if it is newer than the data stored in the parent image.
*
* This function implements the logic to read sectors from the child, or a parent image.
* Differencing images may have a differencing image as a parent, creating a chain of images.
* There is no theoretical chain length limit, although I do not consider long chains to be
* advisable. Verifying the parent-child relationship is not very robust.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to read from
* \param [in] num_sectors The desired number of sectors to read
* \param [out] out_buff An output buffer to store read sectors. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were read from file
* \retval >0 < num_sectors were read from file
*/
int mvhd_diff_read(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* out_buff);
/**
* \brief Write to a fixed VHD image
*
* Fixed VHD images are essentially raw image files with a footer tacked on
* the end. They are therefore straightforward to write
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to write to
* \param [in] num_sectors The desired number of sectors to write
* \param [in] in_buff A source buffer to write sectors from. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were written to file
* \retval >0 < num_sectors were written to file
*/
int mvhd_fixed_write(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* in_buff);
/**
* \brief Write to a sparse or differencing VHD image
*
* Sparse, or dynamic images are VHD images that grow as data is written to them.
*
* Differencing images are a variant of a sparse image. They contain the grow-on-demand
* properties of sparse images, but also reference a parent image. Data is always written
* to the child image. This makes writing to differencing images essentially identical to
* writing to sparse images, hence they use the same function.
*
* This function implements the logic to write sectors to the file, taking into
* account the fact that blocks may be stored on disk in any order, and that the
* write operation could cross block boundaries.
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to write to
* \param [in] num_sectors The desired number of sectors to write
* \param [in] in_buff A source buffer to write sectors from. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were written to file
* \retval >0 < num_sectors were written to file
*/
int mvhd_sparse_diff_write(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* in_buff);
/**
* \brief A no-op function to "write" to read-only VHD images
*
* \param [in] vhdm MiniVHD data structure
* \param [in] offset Sector offset to write to
* \param [in] num_sectors The desired number of sectors to write
* \param [in] in_buff A source buffer to write sectors from. Must be
* large enough to hold num_sectors worth of sectors.
*
* \retval 0 num_sectors were written to file
* \retval >0 < num_sectors were written to file
*/
int mvhd_noop_write(struct MVHDMeta* vhdm, uint32_t offset, int num_sectors, void* in_buff);
/**
* \brief Save the contents of a VHD footer from a buffer to a struct
*
* \param [out] footer save contents of buffer into footer
* \param [in] buffer VHD footer in raw bytes
*/
void mvhd_buffer_to_footer(MVHDFooter* footer, uint8_t* buffer);
/**
* \brief Save the contents of a VHD sparse header from a buffer to a struct
*
* \param [out] header save contents of buffer into header
* \param [in] buffer VHD header in raw bytes
*/
void mvhd_buffer_to_header(MVHDSparseHeader* header, uint8_t* buffer);
/**
* \brief Save the contents of a VHD footer struct to a buffer
*
* \param [in] footer save contents of struct into buffer
* \param [out] buffer VHD footer in raw bytes
*/
void mvhd_footer_to_buffer(MVHDFooter* footer, uint8_t* buffer);
/**
* \brief Save the contents of a VHD sparse header struct to a buffer
*
* \param [in] header save contents of struct into buffer
* \param [out] buffer VHD sparse header in raw bytes
*/
void mvhd_header_to_buffer(MVHDSparseHeader* header, uint8_t* buffer);
#ifdef __cplusplus
}
#endif
#endif /*MINIVHD_INTERNAL_H*/
``` | /content/code_sandbox/src/disk/minivhd/internal.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,734 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* CD-ROM passthrough support.
*
*
*
* Authors: TheCollector1995, <mariogplayer@gmail.com>,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/plat_cdrom.h>
#include <86box/scsi_device.h>
#include <86box/cdrom.h>
#ifdef ENABLE_CDROM_IOCTL_LOG
int cdrom_ioctl_do_log = ENABLE_CDROM_IOCTL_LOG;
void
cdrom_ioctl_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_ioctl_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_ioctl_log(fmt, ...)
#endif
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
static void
ioctl_get_tracks(UNUSED(cdrom_t *dev), int *first, int *last)
{
TMSF tmsf;
plat_cdrom_get_audio_tracks(first, last, &tmsf);
}
static void
ioctl_get_track_info(UNUSED(cdrom_t *dev), uint32_t track, int end, track_info_t *ti)
{
TMSF tmsf;
plat_cdrom_get_audio_track_info(end, track, &ti->number, &tmsf, &ti->attr);
ti->m = tmsf.min;
ti->s = tmsf.sec;
ti->f = tmsf.fr;
}
static void
ioctl_get_subchannel(UNUSED(cdrom_t *dev), uint32_t lba, subchannel_t *subc)
{
TMSF rel_pos;
TMSF abs_pos;
if ((dev->cd_status == CD_STATUS_PLAYING) || (dev->cd_status == CD_STATUS_PAUSED)) {
const uint32_t trk = plat_cdrom_get_track_start(lba, &subc->attr, &subc->track);
FRAMES_TO_MSF(lba + 150, &abs_pos.min, &abs_pos.sec, &abs_pos.fr);
/* Absolute position should be adjusted by 150, not the relative ones. */
FRAMES_TO_MSF(lba - trk, &rel_pos.min, &rel_pos.sec, &rel_pos.fr);
subc->index = 1;
} else
plat_cdrom_get_audio_sub(lba, &subc->attr, &subc->track, &subc->index,
&rel_pos, &abs_pos);
subc->abs_m = abs_pos.min;
subc->abs_s = abs_pos.sec;
subc->abs_f = abs_pos.fr;
subc->rel_m = rel_pos.min;
subc->rel_s = rel_pos.sec;
subc->rel_f = rel_pos.fr;
cdrom_ioctl_log("ioctl_get_subchannel(): %02X, %02X, %02i, %02i:%02i:%02i, %02i:%02i:%02i\n",
subc->attr, subc->track, subc->index, subc->abs_m, subc->abs_s, subc->abs_f, subc->rel_m, subc->rel_s, subc->rel_f);
}
static int
ioctl_get_capacity(UNUSED(cdrom_t *dev))
{
int ret;
ret = plat_cdrom_get_last_block();
cdrom_ioctl_log("GetCapacity=%x.\n", ret);
return ret;
}
static int
ioctl_is_track_audio(cdrom_t *dev, uint32_t pos, int ismsf)
{
int m;
int s;
int f;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
if (ismsf) {
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
pos = MSFtoLBA(m, s, f) - 150;
}
/* GetTrack requires LBA. */
return plat_cdrom_is_track_audio(pos);
}
static int
ioctl_is_track_pre(UNUSED(cdrom_t *dev), uint32_t lba)
{
return plat_cdrom_is_track_pre(lba);
}
static int
ioctl_sector_size(UNUSED(cdrom_t *dev), uint32_t lba)
{
cdrom_ioctl_log("LBA=%x.\n", lba);
return plat_cdrom_get_sector_size(lba);
}
static int
ioctl_read_sector(UNUSED(cdrom_t *dev), int type, uint8_t *b, uint32_t lba)
{
switch (type) {
case CD_READ_DATA:
cdrom_ioctl_log("cdrom_ioctl_read_sector(): Data.\n");
return plat_cdrom_read_sector(b, 0, lba);
case CD_READ_AUDIO:
cdrom_ioctl_log("cdrom_ioctl_read_sector(): Audio.\n");
return plat_cdrom_read_sector(b, 1, lba);
case CD_READ_RAW:
cdrom_ioctl_log("cdrom_ioctl_read_sector(): Raw.\n");
return plat_cdrom_read_sector(b, 1, lba);
default:
cdrom_ioctl_log("cdrom_ioctl_read_sector(): Unknown CD read type.\n");
break;
}
return 0;
}
static int
ioctl_track_type(cdrom_t *dev, uint32_t lba)
{
int ret = 0;
if (ioctl_is_track_audio(dev, lba, 0))
ret = CD_TRACK_AUDIO;
cdrom_ioctl_log("cdrom_ioctl_track_type(): %i\n", ret);
return ret;
}
static int
ioctl_ext_medium_changed(cdrom_t *dev)
{
int ret;
if ((dev->cd_status == CD_STATUS_PLAYING) || (dev->cd_status == CD_STATUS_PAUSED))
ret = 0;
else
ret = plat_cdrom_ext_medium_changed();
if (ret == 1) {
dev->cd_status = CD_STATUS_STOPPED;
dev->cdrom_capacity = ioctl_get_capacity(dev);
} else if (ret == -1)
dev->cd_status = CD_STATUS_EMPTY;
return ret;
}
static void
ioctl_exit(cdrom_t *dev)
{
cdrom_ioctl_log("CDROM: ioctl_exit(%s)\n", dev->image_path);
dev->cd_status = CD_STATUS_EMPTY;
plat_cdrom_close();
dev->ops = NULL;
}
static const cdrom_ops_t cdrom_ioctl_ops = {
ioctl_get_tracks,
ioctl_get_track_info,
ioctl_get_subchannel,
ioctl_is_track_pre,
ioctl_sector_size,
ioctl_read_sector,
ioctl_track_type,
ioctl_ext_medium_changed,
ioctl_exit
};
static int
cdrom_ioctl_open_abort(cdrom_t *dev)
{
cdrom_ioctl_close(dev);
dev->ops = NULL;
dev->image_path[0] = 0;
return 1;
}
int
cdrom_ioctl_open(cdrom_t *dev, const char *drv)
{
const char *actual_drv = &(drv[8]);
/* Make sure to not STRCPY if the two are pointing
at the same place. */
if (drv != dev->image_path)
strcpy(dev->image_path, drv);
/* Open the image. */
if (strstr(drv, "ioctl://") != drv)
return cdrom_ioctl_open_abort(dev);
cdrom_ioctl_log("actual_drv = %s\n", actual_drv);
int i = plat_cdrom_set_drive(actual_drv);
if (!i)
return cdrom_ioctl_open_abort(dev);
/* All good, reset state. */
dev->cd_status = CD_STATUS_STOPPED;
dev->seek_pos = 0;
dev->cd_buflen = 0;
dev->cdrom_capacity = ioctl_get_capacity(dev);
cdrom_ioctl_log("CD-ROM capacity: %i sectors (%" PRIi64 " bytes)\n",
dev->cdrom_capacity, ((uint64_t) dev->cdrom_capacity) << 11ULL);
/* Attach this handler to the drive. */
dev->ops = &cdrom_ioctl_ops;
return 0;
}
void
cdrom_ioctl_close(cdrom_t *dev)
{
cdrom_ioctl_log("CDROM: ioctl_close(%s)\n", dev->image_path);
if (dev && dev->ops && dev->ops->exit)
dev->ops->exit(dev);
}
``` | /content/code_sandbox/src/cdrom/cdrom_ioctl.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,098 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* CD-ROM image file handling module, translated to C from
* cdrom_dosbox.cpp.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* The DOSBox Team, <unknown>
* Cacodemon345
*
*/
#define __STDC_FORMAT_MACROS
#include <ctype.h>
#include <inttypes.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h>
#ifdef _WIN32
# include <string.h>
# include <sys/types.h>
#else
# include <libgen.h>
#endif
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/cdrom_image_backend.h>
#include <sndfile.h>
#define CDROM_BCD(x) (((x) % 10) | (((x) / 10) << 4))
#define MAX_LINE_LENGTH 512
#define MAX_FILENAME_LENGTH 256
#define CROSS_LEN 512
static char temp_keyword[1024];
#ifdef ENABLE_CDROM_IMAGE_BACKEND_LOG
int cdrom_image_backend_do_log = ENABLE_CDROM_IMAGE_BACKEND_LOG;
void
cdrom_image_backend_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_image_backend_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_image_backend_log(fmt, ...)
#endif
typedef struct audio_file_t {
SNDFILE *file;
SF_INFO info;
} audio_file_t;
/* Audio file functions */
static int
audio_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count)
{
track_file_t *tf = (track_file_t *) priv;
audio_file_t *audio = (audio_file_t *) tf->priv;
uint64_t samples_seek = seek / 4;
uint64_t samples_count = count / 4;
if ((seek & 3) || (count & 3)) {
cdrom_image_backend_log("CD Audio file: Reading on non-4-aligned boundaries.\n");
}
sf_count_t res = sf_seek(audio->file, samples_seek, SEEK_SET);
if (res == -1)
return 0;
return !!sf_readf_short(audio->file, (short *) buffer, samples_count);
}
static uint64_t
audio_get_length(void *priv)
{
track_file_t *tf = (track_file_t *) priv;
audio_file_t *audio = (audio_file_t *) tf->priv;
/* Assume 16-bit audio, 2 channel. */
return audio->info.frames * 4ull;
}
static void
audio_close(void *priv)
{
track_file_t *tf = (track_file_t *) priv;
audio_file_t *audio = (audio_file_t *) tf->priv;
memset(tf->fn, 0x00, sizeof(tf->fn));
if (audio && audio->file)
sf_close(audio->file);
free(audio);
free(tf);
}
static track_file_t *
audio_init(const char *filename, int *error)
{
track_file_t *tf = (track_file_t *) calloc(sizeof(track_file_t), 1);
audio_file_t *audio = (audio_file_t *) calloc(sizeof(audio_file_t), 1);
#ifdef _WIN32
wchar_t filename_w[4096];
#endif
if (tf == NULL || audio == NULL) {
goto cleanup_error;
}
memset(tf->fn, 0x00, sizeof(tf->fn));
strncpy(tf->fn, filename, sizeof(tf->fn) - 1);
#ifdef _WIN32
mbstowcs(filename_w, filename, 4096);
audio->file = sf_wchar_open(filename_w, SFM_READ, &audio->info);
#else
audio->file = sf_open(filename, SFM_READ, &audio->info);
#endif
if (!audio->file) {
cdrom_image_backend_log("Audio file open error!");
goto cleanup_error;
}
if (audio->info.channels != 2 || audio->info.samplerate != 44100 || !audio->info.seekable) {
cdrom_image_backend_log("Audio file not seekable or in non-CD format!");
sf_close(audio->file);
goto cleanup_error;
}
*error = 0;
tf->priv = audio;
tf->fp = NULL;
tf->close = audio_close;
tf->get_length = audio_get_length;
tf->read = audio_read;
return tf;
cleanup_error:
free(tf);
free(audio);
*error = 1;
return NULL;
}
/* Binary file functions. */
static int
bin_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count)
{
track_file_t *tf = NULL;
if ((tf = (track_file_t *) priv)->fp == NULL)
return 0;
cdrom_image_backend_log("CDROM: binary_read(%08lx, pos=%" PRIu64 " count=%lu)\n",
tf->fp, seek, count);
if (fseeko64(tf->fp, seek, SEEK_SET) == -1) {
cdrom_image_backend_log("CDROM: binary_read failed during seek!\n");
return 0;
}
if (fread(buffer, count, 1, tf->fp) != 1) {
cdrom_image_backend_log("CDROM: binary_read failed during read!\n");
return 0;
}
if (UNLIKELY(tf->motorola)) {
for (uint64_t i = 0; i < count; i += 2) {
uint8_t buffer0 = buffer[i];
uint8_t buffer1 = buffer[i + 1];
buffer[i] = buffer1;
buffer[i + 1] = buffer0;
}
}
return 1;
}
static uint64_t
bin_get_length(void *priv)
{
track_file_t *tf = NULL;
if ((tf = (track_file_t *) priv)->fp == NULL)
return 0;
fseeko64(tf->fp, 0, SEEK_END);
const off64_t len = ftello64(tf->fp);
cdrom_image_backend_log("CDROM: binary_length(%08lx) = %" PRIu64 "\n", tf->fp, len);
return len;
}
static void
bin_close(void *priv)
{
track_file_t *tf = (track_file_t *) priv;
if (tf == NULL)
return;
if (tf->fp != NULL) {
fclose(tf->fp);
tf->fp = NULL;
}
memset(tf->fn, 0x00, sizeof(tf->fn));
free(priv);
}
static track_file_t *
bin_init(const char *filename, int *error)
{
track_file_t *tf = (track_file_t *) calloc(1, sizeof(track_file_t));
struct stat stats;
if (tf == NULL) {
*error = 1;
return NULL;
}
memset(tf->fn, 0x00, sizeof(tf->fn));
strncpy(tf->fn, filename, sizeof(tf->fn) - 1);
tf->fp = plat_fopen64(tf->fn, "rb");
cdrom_image_backend_log("CDROM: binary_open(%s) = %08lx\n", tf->fn, tf->fp);
if (stat(tf->fn, &stats) != 0) {
/* Use a blank structure if stat failed. */
memset(&stats, 0, sizeof(struct stat));
}
*error = ((tf->fp == NULL) || ((stats.st_mode & S_IFMT) == S_IFDIR));
/* Set the function pointers. */
if (!*error) {
tf->read = bin_read;
tf->get_length = bin_get_length;
tf->close = bin_close;
} else {
/* From the check above, error may still be non-zero if opening a directory.
* The error is set for viso to try and open the directory following this function.
* However, we need to make sure the descriptor is closed. */
if ((tf->fp != NULL) && ((stats.st_mode & S_IFMT) == S_IFDIR)) {
/* tf is freed by bin_close */
bin_close(tf);
} else {
free(tf);
}
tf = NULL;
}
return tf;
}
static track_file_t *
track_file_init(const char *filename, int *error)
{
/* Current we only support .BIN files, either combined or one per
track. In the future, more is planned. */
return bin_init(filename, error);
}
static void
track_file_close(track_t *trk)
{
if (trk == NULL)
return;
if (trk->file == NULL)
return;
if (trk->file->close == NULL)
return;
trk->file->close(trk->file);
trk->file = NULL;
}
/* Root functions. */
static void
cdi_clear_tracks(cd_img_t *cdi)
{
const track_file_t *last = NULL;
track_t *cur = NULL;
if ((cdi->tracks == NULL) || (cdi->tracks_num == 0))
return;
for (int i = 0; i < cdi->tracks_num; i++) {
cur = &cdi->tracks[i];
/* Make sure we do not attempt to close a NULL file. */
if (cur->file != last) {
last = cur->file;
track_file_close(cur);
} else
cur->file = NULL;
}
/* Now free the array. */
free(cdi->tracks);
cdi->tracks = NULL;
/* Mark that there's no tracks. */
cdi->tracks_num = 0;
}
void
cdi_close(cd_img_t *cdi)
{
cdi_clear_tracks(cdi);
free(cdi);
}
int
cdi_set_device(cd_img_t *cdi, const char *path)
{
int ret;
if ((ret = cdi_load_cue(cdi, path)))
return ret;
if ((ret = cdi_load_iso(cdi, path)))
return ret;
return 0;
}
void
cdi_get_audio_tracks(cd_img_t *cdi, int *st_track, int *end, TMSF *lead_out)
{
*st_track = 1;
*end = cdi->tracks_num - 1;
FRAMES_TO_MSF(cdi->tracks[*end].start + 150, &lead_out->min, &lead_out->sec, &lead_out->fr);
}
void
cdi_get_audio_tracks_lba(cd_img_t *cdi, int *st_track, int *end, uint32_t *lead_out)
{
*st_track = 1;
*end = cdi->tracks_num - 1;
*lead_out = cdi->tracks[*end].start;
}
int
cdi_get_audio_track_pre(cd_img_t *cdi, int track)
{
const track_t *trk = &cdi->tracks[track - 1];
if ((track < 1) || (track > cdi->tracks_num))
return 0;
return trk->pre;
}
/* This replaces both Info and EndInfo, they are specified by a variable. */
int
cdi_get_audio_track_info(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, TMSF *start, uint8_t *attr)
{
const track_t *trk = &cdi->tracks[track - 1];
const int pos = trk->start + 150;
if ((track < 1) || (track > cdi->tracks_num))
return 0;
FRAMES_TO_MSF(pos, &start->min, &start->sec, &start->fr);
*track_num = trk->track_number;
*attr = trk->attr;
return 1;
}
int
cdi_get_audio_track_info_lba(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, uint32_t *start, uint8_t *attr)
{
const track_t *trk = &cdi->tracks[track - 1];
if ((track < 1) || (track > cdi->tracks_num))
return 0;
*start = (uint32_t) trk->start;
*track_num = trk->track_number;
*attr = trk->attr;
return 1;
}
int
cdi_get_track(cd_img_t *cdi, uint32_t sector)
{
/* There must be at least two tracks - data and lead out. */
if (cdi->tracks_num < 2)
return -1;
/* This has a problem - the code skips the last track, which is
lead out - is that correct? */
for (int i = 0; i < (cdi->tracks_num - 1); i++) {
const track_t *cur = &cdi->tracks[i];
const track_t *next = &cdi->tracks[i + 1];
/* Take into account cue sheets that do not start on sector 0. */
if ((i == 0) && (sector < cur->start))
return cur->number;
if ((cur->start <= sector) && (sector < next->start))
return cur->number;
}
return -1;
}
/* TODO: See if track start is adjusted by 150 or not. */
int
cdi_get_audio_sub(cd_img_t *cdi, uint32_t sector, uint8_t *attr, uint8_t *track, uint8_t *index, TMSF *rel_pos, TMSF *abs_pos)
{
const int cur_track = cdi_get_track(cdi, sector);
if (cur_track < 1)
return 0;
*track = (uint8_t) cur_track;
const track_t *trk = &cdi->tracks[*track - 1];
*attr = trk->attr;
*index = 1;
FRAMES_TO_MSF(sector + 150, &abs_pos->min, &abs_pos->sec, &abs_pos->fr);
/* Absolute position should be adjusted by 150, not the relative ones. */
FRAMES_TO_MSF(sector - trk->start, &rel_pos->min, &rel_pos->sec, &rel_pos->fr);
return 1;
}
int
cdi_read_sector(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector)
{
const int track = cdi_get_track(cdi, sector) - 1;
const uint64_t sect = (uint64_t) sector;
int raw_size;
int cooked_size;
uint64_t offset;
int m = 0;
int s = 0;
int f = 0;
if (track < 0)
return 0;
const track_t *trk = &cdi->tracks[track];
const int track_is_raw = ((trk->sector_size == RAW_SECTOR_SIZE) || (trk->sector_size == 2448));
const uint64_t seek = trk->skip + ((sect - trk->start) * trk->sector_size);
if (track_is_raw)
raw_size = trk->sector_size;
else
raw_size = 2448;
if (trk->mode2 && (trk->form != 1)) {
if (trk->form == 2)
cooked_size = (track_is_raw ? 2328 : trk->sector_size); /* Both 2324 + ECC and 2328 variants are valid. */
else
cooked_size = 2336;
} else
cooked_size = COOKED_SECTOR_SIZE;
const size_t length = (raw ? raw_size : cooked_size);
if (trk->mode2 && (trk->form >= 1))
offset = 24ULL;
else
offset = 16ULL;
if (raw && !track_is_raw) {
memset(buffer, 0x00, 2448);
const int ret = trk->file->read(trk->file, buffer + offset, seek, length);
if (!ret)
return 0;
/* Construct the rest of the raw sector. */
memset(buffer + 1, 0xff, 10);
buffer += 12;
FRAMES_TO_MSF(sector + 150, &m, &s, &f);
/* These have to be BCD. */
buffer[0] = CDROM_BCD(m & 0xff);
buffer[1] = CDROM_BCD(s & 0xff);
buffer[2] = CDROM_BCD(f & 0xff);
/* Data, should reflect the actual sector type. */
buffer[3] = trk->mode2 ? 2 : 1;
return 1;
} else if (!raw && track_is_raw)
return trk->file->read(trk->file, buffer, seek + offset, length);
else
return trk->file->read(trk->file, buffer, seek, length);
}
int
cdi_read_sectors(cd_img_t *cdi, uint8_t *buffer, int raw, uint32_t sector, uint32_t num)
{
int success = 1;
/* TODO: This fails to account for Mode 2. Shouldn't we have a function
to get sector size? */
const int sector_size = raw ? RAW_SECTOR_SIZE : COOKED_SECTOR_SIZE;
const uint32_t buf_len = num * sector_size;
uint8_t *buf = (uint8_t *) calloc(1, buf_len * sizeof(uint8_t));
for (uint32_t i = 0; i < num; i++) {
success = cdi_read_sector(cdi, &buf[i * sector_size], raw, sector + i);
if (!success)
break;
/* Based on the DOSBox patch, but check all 8 bytes and makes sure it's not an
audio track. */
if (raw && (sector < cdi->tracks[0].length) && !cdi->tracks[0].mode2 && (cdi->tracks[0].attr != AUDIO_TRACK) && *(uint64_t *) &(buf[(i * sector_size) + 2068]))
return 0;
}
memcpy((void *) buffer, buf, buf_len);
free(buf);
buf = NULL;
return success;
}
/* TODO: Do CUE+BIN images with a sector size of 2448 even exist? */
int
cdi_read_sector_sub(cd_img_t *cdi, uint8_t *buffer, uint32_t sector)
{
const int track = cdi_get_track(cdi, sector) - 1;
if (track < 0)
return 0;
const track_t *trk = &cdi->tracks[track];
const uint64_t seek = trk->skip + (((uint64_t) sector - trk->start) * trk->sector_size);
if (trk->sector_size != 2448)
return 0;
return trk->file->read(trk->file, buffer, seek, 2448);
}
int
cdi_get_sector_size(cd_img_t *cdi, uint32_t sector)
{
const int track = cdi_get_track(cdi, sector) - 1;
if (track < 0)
return 0;
const track_t *trk = &cdi->tracks[track];
return trk->sector_size;
}
int
cdi_is_mode2(cd_img_t *cdi, uint32_t sector)
{
const int track = cdi_get_track(cdi, sector) - 1;
if (track < 0)
return 0;
const track_t *trk = &cdi->tracks[track];
return !!(trk->mode2);
}
int
cdi_get_mode2_form(cd_img_t *cdi, uint32_t sector)
{
const int track = cdi_get_track(cdi, sector) - 1;
if (track < 0)
return 0;
const track_t *trk = &cdi->tracks[track];
return trk->form;
}
static int
cdi_can_read_pvd(track_file_t *file, uint64_t sector_size, int mode2, int form)
{
uint8_t pvd[COOKED_SECTOR_SIZE];
uint64_t seek = 16ULL * sector_size; /* First VD is located at sector 16. */
if (sector_size == RAW_SECTOR_SIZE) {
if (mode2 && (form > 0))
seek += 24;
else
seek += 16;
} else if (form > 0)
seek += 8;
file->read(file, pvd, seek, COOKED_SECTOR_SIZE);
return ((pvd[0] == 1 && !strncmp((char *) (&pvd[1]), "CD001", 5) && pvd[6] == 1) || (pvd[8] == 1 && !strncmp((char *) (&pvd[9]), "CDROM", 5) && pvd[14] == 1));
}
/* This reallocates the array and returns the pointer to the last track. */
static void
cdi_track_push_back(cd_img_t *cdi, track_t *trk)
{
/* This has to be done so situations in which realloc would misbehave
can be detected and reported to the user. */
if ((cdi->tracks != NULL) && (cdi->tracks_num == 0))
fatal("CD-ROM Image: Non-null tracks array at 0 loaded tracks\n");
if ((cdi->tracks == NULL) && (cdi->tracks_num != 0))
fatal("CD-ROM Image: Null tracks array at non-zero loaded tracks\n");
cdi->tracks = realloc(cdi->tracks, (cdi->tracks_num + 1) * sizeof(track_t));
memcpy(&(cdi->tracks[cdi->tracks_num]), trk, sizeof(track_t));
cdi->tracks_num++;
}
int
cdi_get_iso_track(cd_img_t *cdi, track_t *trk, const char *filename)
{
int error = 0;
int ret = 2;
memset(trk, 0, sizeof(track_t));
/* Data track (shouldn't there be a lead in track?). */
trk->file = bin_init(filename, &error);
if (error) {
if ((trk->file != NULL) && (trk->file->close != NULL))
trk->file->close(trk->file);
ret = 3;
trk->file = viso_init(filename, &error);
if (error) {
if ((trk->file != NULL) && (trk->file->close != NULL))
trk->file->close(trk->file);
return 0;
}
}
trk->number = 1;
trk->track_number = 1;
trk->attr = DATA_TRACK;
/* Try to detect ISO type. */
trk->form = 0;
trk->mode2 = 0;
if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 0, 0))
trk->sector_size = RAW_SECTOR_SIZE;
else if (cdi_can_read_pvd(trk->file, 2336, 1, 0)) {
trk->sector_size = 2336;
trk->mode2 = 1;
} else if (cdi_can_read_pvd(trk->file, 2324, 1, 2)) {
trk->sector_size = 2324;
trk->mode2 = 1;
trk->form = 2;
trk->noskip = 1;
} else if (cdi_can_read_pvd(trk->file, 2328, 1, 2)) {
trk->sector_size = 2328;
trk->mode2 = 1;
trk->form = 2;
trk->noskip = 1;
} else if (cdi_can_read_pvd(trk->file, 2336, 1, 1)) {
trk->sector_size = 2336;
trk->mode2 = 1;
trk->form = 1;
trk->skip = 8;
} else if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 1, 0)) {
trk->sector_size = RAW_SECTOR_SIZE;
trk->mode2 = 1;
} else if (cdi_can_read_pvd(trk->file, RAW_SECTOR_SIZE, 1, 1)) {
trk->sector_size = RAW_SECTOR_SIZE;
trk->mode2 = 1;
trk->form = 1;
} else {
/* We use 2048 mode 1 as the default. */
trk->sector_size = COOKED_SECTOR_SIZE;
}
trk->length = trk->file->get_length(trk->file) / trk->sector_size;
cdrom_image_backend_log("ISO: Data track: length = %" PRIu64 ", sector_size = %i\n", trk->length, trk->sector_size);
return ret;
}
int
cdi_load_iso(cd_img_t *cdi, const char *filename)
{
int ret = 2;
track_t trk = { 0 };
cdi->tracks = NULL;
cdi->tracks_num = 0;
ret = cdi_get_iso_track(cdi, &trk, filename);
if (ret >= 1) {
cdi_track_push_back(cdi, &trk);
/* Lead out track. */
trk.number = 2;
trk.track_number = 0xAA;
trk.attr = 0x16; /* Was originally 0x00, but I believe 0x16 is appropriate. */
trk.start = trk.length;
trk.length = 0;
trk.file = NULL;
cdi_track_push_back(cdi, &trk);
}
return ret;
}
static int
cdi_cue_get_buffer(char *str, char **line, int up)
{
char *s = *line;
char *p = str;
int quote = 0;
int done = 0;
int space = 1;
/* Copy to local buffer until we have end of string or whitespace. */
while (!done) {
switch (*s) {
case '\0':
if (quote) {
/* Ouch, unterminated string.. */
return 0;
}
done = 1;
break;
case '\"':
quote ^= 1;
break;
case ' ':
case '\t':
if (space)
break;
if (!quote) {
done = 1;
break;
}
fallthrough;
default:
if (up && islower((int) *s))
*p++ = toupper((int) *s);
else
*p++ = *s;
space = 0;
break;
}
if (!done)
s++;
}
*p = '\0';
*line = s;
return 1;
}
static int
cdi_cue_get_keyword(char **dest, char **line)
{
int success;
success = cdi_cue_get_buffer(temp_keyword, line, 1);
if (success)
*dest = temp_keyword;
return success;
}
/* Get a string from the input line, handling quotes properly. */
static uint64_t
cdi_cue_get_number(char **line)
{
char temp[128];
uint64_t num;
if (!cdi_cue_get_buffer(temp, line, 0))
return 0;
if (sscanf(temp, "%" PRIu64, &num) != 1)
return 0;
return num;
}
static int
cdi_cue_get_frame(uint64_t *frames, char **line)
{
char temp[128];
int min = 0;
int sec = 0;
int fr = 0;
int success;
success = cdi_cue_get_buffer(temp, line, 0);
if (!success)
return 0;
success = sscanf(temp, "%d:%d:%d", &min, &sec, &fr) == 3;
if (!success)
return 0;
*frames = MSF_TO_FRAMES(min, sec, fr);
return 1;
}
static int
cdi_cue_get_flags(track_t *cur, char **line)
{
char temp[128];
char temp2[128];
int success;
success = cdi_cue_get_buffer(temp, line, 0);
if (!success)
return 0;
memset(temp2, 0x00, sizeof(temp2));
success = sscanf(temp, "%s", temp2) == 1;
if (!success)
return 0;
cur->pre = (strstr(temp2, "PRE") != NULL);
return 1;
}
static int
cdi_add_track(cd_img_t *cdi, track_t *cur, uint64_t *shift, uint64_t prestart, uint64_t *total_pregap, uint64_t cur_pregap)
{
/* Frames between index 0 (prestart) and 1 (current track start) must be skipped. */
track_t *prev = NULL;
/* Skip *MUST* be calculated even if prestart is 0. */
if (prestart > cur->start)
return 0;
const uint64_t skip = cur->start - prestart;
if ((cdi->tracks != NULL) && (cdi->tracks_num != 0))
prev = &cdi->tracks[cdi->tracks_num - 1];
else if ((cdi->tracks == NULL) && (cdi->tracks_num != 0)) {
fatal("NULL cdi->tracks with non-zero cdi->tracks_num\n");
return 0;
}
/* First track (track number must be 1). */
if ((prev == NULL) || (cdi->tracks_num == 0)) {
/* I guess this makes sure the structure is not filled with invalid data. */
if (cur->number != 1)
return 0;
cur->skip = skip * cur->sector_size;
if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0) && !cur->noskip)
cur->skip += 8;
cur->start += cur_pregap;
*total_pregap = cur_pregap;
cdi_track_push_back(cdi, cur);
return 1;
}
/* Current track consumes data from the same file as the previous. */
if (prev->file == cur->file) {
cur->start += *shift;
prev->length = cur->start + *total_pregap - prev->start - skip;
cur->skip += prev->skip + (prev->length * prev->sector_size) + (skip * cur->sector_size);
*total_pregap += cur_pregap;
cur->start += *total_pregap;
} else {
const uint64_t temp = prev->file->get_length(prev->file) - (prev->skip);
prev->length = temp / ((uint64_t) prev->sector_size);
if ((temp % prev->sector_size) != 0)
prev->length++;
/* Padding. */
cur->start += prev->start + prev->length + cur_pregap;
cur->skip = skip * cur->sector_size;
if ((cur->sector_size != RAW_SECTOR_SIZE) && (cur->form > 0) && !cur->noskip)
cur->skip += 8;
*shift += prev->start + prev->length;
*total_pregap = cur_pregap;
}
/* Error checks. */
if (cur->number <= 1)
return 0;
if ((prev->number + 1) != cur->number)
return 0;
if (cur->start < (prev->start + prev->length))
return 0;
cdi_track_push_back(cdi, cur);
return 1;
}
int
cdi_load_cue(cd_img_t *cdi, const char *cuefile)
{
track_t trk;
char pathname[MAX_FILENAME_LENGTH];
uint64_t shift = 0ULL;
uint64_t prestart = 0ULL;
uint64_t cur_pregap = 0ULL;
uint64_t total_pregap = 0ULL;
uint64_t frame = 0ULL;
uint64_t index;
int iso_file_used = 0;
int success;
int error;
int can_add_track = 0;
FILE *fp;
char buf[MAX_LINE_LENGTH];
char *line;
char *command;
char *type;
cdi->tracks = NULL;
cdi->tracks_num = 0;
memset(&trk, 0, sizeof(track_t));
/* Get a copy of the filename into pathname, we need it later. */
memset(pathname, 0, MAX_FILENAME_LENGTH * sizeof(char));
path_get_dirname(pathname, cuefile);
/* Open the file. */
fp = plat_fopen(cuefile, "r");
if (fp == NULL)
return 0;
success = 0;
for (;;) {
line = buf;
/* Read a line from the cuesheet file. */
if (feof(fp) || fgets(buf, sizeof(buf), fp) == NULL || ferror(fp))
break;
/* Do two iterations to make sure to nuke even if it's \r\n or \n\r,
but do checks to make sure we're not nuking other bytes. */
for (uint8_t i = 0; i < 2; i++) {
if (strlen(buf) > 0) {
if (buf[strlen(buf) - 1] == '\n')
buf[strlen(buf) - 1] = '\0';
/* nuke trailing newline */
else if (buf[strlen(buf) - 1] == '\r')
buf[strlen(buf) - 1] = '\0';
/* nuke trailing newline */
}
}
(void) cdi_cue_get_keyword(&command, &line);
if (!strcmp(command, "TRACK")) {
if (can_add_track)
success = cdi_add_track(cdi, &trk, &shift, prestart, &total_pregap, cur_pregap);
else
success = 1;
if (!success)
break;
if (iso_file_used) {
/* We don't alter anything of the detected track type with the one specified in the CUE file, except its numbers. */
cur_pregap = 0;
prestart = 0;
trk.number = cdi_cue_get_number(&line);
trk.track_number = trk.number;
success = cdi_cue_get_keyword(&type, &line);
if (!success)
break;
can_add_track = 1;
iso_file_used = 0;
} else {
trk.start = 0;
trk.skip = 0;
cur_pregap = 0;
prestart = 0;
trk.number = cdi_cue_get_number(&line);
trk.track_number = trk.number;
success = cdi_cue_get_keyword(&type, &line);
if (!success)
break;
trk.form = 0;
trk.mode2 = 0;
trk.pre = 0;
if (!strcmp(type, "AUDIO")) {
trk.sector_size = RAW_SECTOR_SIZE;
trk.attr = AUDIO_TRACK;
} else if (!strcmp(type, "MODE1/2048")) {
trk.sector_size = COOKED_SECTOR_SIZE;
trk.attr = DATA_TRACK;
} else if (!strcmp(type, "MODE1/2352")) {
trk.sector_size = RAW_SECTOR_SIZE;
trk.attr = DATA_TRACK;
} else if (!strcmp(type, "MODE1/2448")) {
trk.sector_size = 2448;
trk.attr = DATA_TRACK;
} else if (!strcmp(type, "MODE2/2048")) {
trk.form = 1;
trk.sector_size = COOKED_SECTOR_SIZE;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "MODE2/2324")) {
trk.form = 2;
trk.sector_size = 2324;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "MODE2/2328")) {
trk.form = 2;
trk.sector_size = 2328;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "MODE2/2336")) {
trk.form = 1;
trk.sector_size = 2336;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "MODE2/2352")) {
/* Assume this is XA Mode 2 Form 1. */
trk.form = 1;
trk.sector_size = RAW_SECTOR_SIZE;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "MODE2/2448")) {
/* Assume this is XA Mode 2 Form 1. */
trk.form = 1;
trk.sector_size = 2448;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "CDG/2448")) {
trk.sector_size = 2448;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "CDI/2336")) {
trk.sector_size = 2336;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else if (!strcmp(type, "CDI/2352")) {
trk.sector_size = RAW_SECTOR_SIZE;
trk.attr = DATA_TRACK;
trk.mode2 = 1;
} else
success = 0;
can_add_track = 1;
}
} else if (!strcmp(command, "INDEX")) {
index = cdi_cue_get_number(&line);
success = cdi_cue_get_frame(&frame, &line);
switch (index) {
case 0:
prestart = frame;
break;
case 1:
trk.start = frame;
break;
default:
/* Ignore other indices. */
break;
}
} else if (!strcmp(command, "FILE")) {
char filename[MAX_FILENAME_LENGTH];
char ansi[MAX_FILENAME_LENGTH];
if (can_add_track)
success = cdi_add_track(cdi, &trk, &shift, prestart, &total_pregap, cur_pregap);
else
success = 1;
if (!success)
break;
can_add_track = 0;
memset(ansi, 0, MAX_FILENAME_LENGTH * sizeof(char));
memset(filename, 0, MAX_FILENAME_LENGTH * sizeof(char));
success = cdi_cue_get_buffer(ansi, &line, 0);
if (!success)
break;
success = cdi_cue_get_keyword(&type, &line);
if (!success)
break;
trk.file = NULL;
error = 1;
if (!strcmp(type, "BINARY") || !strcmp(type, "MOTOROLA")) {
int fn_len = 0;
if (!path_abs(ansi)) {
path_append_filename(filename, pathname, ansi);
} else {
strcpy(filename, ansi);
}
fn_len = strlen(filename);
if ((tolower((int) filename[fn_len - 1]) == 'o'
&& tolower((int) filename[fn_len - 2]) == 's'
&& tolower((int) filename[fn_len - 3]) == 'i'
&& filename[fn_len - 4] == '.')
|| plat_dir_check(filename)) {
error = !cdi_get_iso_track(cdi, &trk, filename);
if (!error) {
iso_file_used = 1;
}
} else
trk.file = track_file_init(filename, &error);
if (trk.file) {
trk.file->motorola = !strcmp(type, "MOTOROLA");
}
} else if (!strcmp(type, "WAVE") || !strcmp(type, "AIFF") || !strcmp(type, "MP3")) {
if (!path_abs(ansi)) {
path_append_filename(filename, pathname, ansi);
} else {
strcpy(filename, ansi);
}
trk.file = audio_init(filename, &error);
}
if (error) {
cdrom_image_backend_log("CUE: cannot open file '%s' in cue sheet!\n",
filename);
if (trk.file != NULL) {
trk.file->close(trk.file);
trk.file = NULL;
}
success = 0;
}
} else if (!strcmp(command, "PREGAP"))
success = cdi_cue_get_frame(&cur_pregap, &line);
else if (!strcmp(command, "FLAGS"))
success = cdi_cue_get_flags(&trk, &line);
else if (!strcmp(command, "CATALOG") || !strcmp(command, "CDTEXTFILE") || !strcmp(command, "ISRC") || !strcmp(command, "PERFORMER") || !strcmp(command, "POSTGAP") || !strcmp(command, "REM") || !strcmp(command, "SONGWRITER") || !strcmp(command, "TITLE") || !strcmp(command, "")) {
/* Ignored commands. */
success = 1;
} else {
cdrom_image_backend_log("CUE: unsupported command '%s' in cue sheet!\n", command);
success = 0;
}
if (!success)
break;
}
fclose(fp);
if (!success)
return 0;
/* Add last track. */
if (!cdi_add_track(cdi, &trk, &shift, prestart, &total_pregap, cur_pregap))
return 0;
/* Add lead out track. */
trk.number++;
trk.track_number = 0xAA;
trk.attr = 0x16; /* Was 0x00 but I believe 0x16 is appropriate. */
trk.start = 0;
trk.length = 0;
trk.file = NULL;
if (!cdi_add_track(cdi, &trk, &shift, 0, &total_pregap, 0))
return 0;
return 1;
}
int
cdi_has_data_track(cd_img_t *cdi)
{
if ((cdi == NULL) || (cdi->tracks == NULL))
return 0;
/* Data track has attribute 0x14. */
for (int i = 0; i < cdi->tracks_num; i++) {
if (cdi->tracks[i].attr == DATA_TRACK)
return 1;
}
return 0;
}
int
cdi_has_audio_track(cd_img_t *cdi)
{
if ((cdi == NULL) || (cdi->tracks == NULL))
return 0;
/* Audio track has attribute 0x10. */
for (int i = 0; i < cdi->tracks_num; i++) {
if (cdi->tracks[i].attr == AUDIO_TRACK)
return 1;
}
return 0;
}
``` | /content/code_sandbox/src/cdrom/cdrom_image_backend.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,073 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Generic CD-ROM drive core.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/config.h>
#include <86box/cdrom.h>
#include <86box/cdrom_image.h>
#include <86box/cdrom_interface.h>
#include <86box/cdrom_mitsumi.h>
#include <86box/plat.h>
#include <86box/scsi.h>
#include <86box/scsi_device.h>
#include <86box/sound.h>
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#undef MSFtoLBA
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
#define RAW_SECTOR_SIZE 2352
#define COOKED_SECTOR_SIZE 2048
#define MIN_SEEK 2000
#define MAX_SEEK 333333
#pragma pack(push, 1)
typedef struct {
uint8_t user_data[2048],
ecc[288];
} m1_data_t;
typedef struct {
uint8_t sub_header[8],
user_data[2328];
} m2_data_t;
typedef union {
m1_data_t m1_data;
m2_data_t m2_data;
uint8_t raw_data[2336];
} sector_data_t;
typedef struct {
uint8_t sync[12];
uint8_t header[4];
sector_data_t data;
} sector_raw_data_t;
typedef union {
sector_raw_data_t sector_data;
uint8_t raw_data[2352];
} sector_t;
typedef struct {
sector_t sector;
uint8_t c2[296];
uint8_t subchannel_raw[96];
uint8_t subchannel_q[16];
uint8_t subchannel_rw[96];
} cdrom_sector_t;
typedef union {
cdrom_sector_t cdrom_sector;
uint8_t buffer[2856];
} sector_buffer_t;
#pragma pack(pop)
static int cdrom_sector_size;
static uint8_t raw_buffer[2856]; /* Needs to be the same size as sector_buffer_t in the structs. */
static uint8_t extra_buffer[296];
cdrom_t cdrom[CDROM_NUM];
int cdrom_interface_current;
#ifdef ENABLE_CDROM_LOG
int cdrom_do_log = ENABLE_CDROM_LOG;
void
cdrom_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_log(fmt, ...)
#endif
static const device_t cdrom_interface_none_device = {
.name = "None",
.internal_name = "none",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const struct {
const device_t *device;
} controllers[] = {
// clang-format off
{ &cdrom_interface_none_device },
{ NULL }
// clang-format on
};
/* Reset the CD-ROM Interface, whichever one that is. */
void
cdrom_interface_reset(void)
{
cdrom_log("CD-ROM Interface: reset(current=%d)\n",
cdrom_interface_current);
/* If we have a valid controller, add its device. */
if ((cdrom_interface_current > 0) && controllers[cdrom_interface_current].device)
device_add(controllers[cdrom_interface_current].device);
}
const char *
cdrom_interface_get_internal_name(int cdinterface)
{
return device_get_internal_name(controllers[cdinterface].device);
}
int
cdrom_interface_get_from_internal_name(char *s)
{
int c = 0;
while (controllers[c].device != NULL) {
if (!strcmp(controllers[c].device->internal_name, s))
return c;
c++;
}
return 0;
}
const device_t *
cdrom_interface_get_device(int cdinterface)
{
return (controllers[cdinterface].device);
}
int
cdrom_interface_has_config(int cdinterface)
{
const device_t *dev = cdrom_interface_get_device(cdinterface);
if (dev == NULL)
return 0;
if (!device_has_config(dev))
return 0;
return 1;
}
int
cdrom_interface_get_flags(int cdinterface)
{
return (controllers[cdinterface].device->flags);
}
int
cdrom_interface_available(int cdinterface)
{
return (device_available(controllers[cdinterface].device));
}
char *
cdrom_getname(int type)
{
return (char *) cdrom_drive_types[type].name;
}
char *
cdrom_get_internal_name(int type)
{
return (char *) cdrom_drive_types[type].internal_name;
}
int
cdrom_get_from_internal_name(char *s)
{
int c = 0;
while (strlen(cdrom_drive_types[c].internal_name)) {
if (!strcmp((char *) cdrom_drive_types[c].internal_name, s))
return c;
c++;
}
return 0;
}
void
cdrom_set_type(int model, int type)
{
cdrom[model].type = type;
}
int
cdrom_get_type(int model)
{
return cdrom[model].type;
}
static __inline int
bin2bcd(int x)
{
return (x % 10) | ((x / 10) << 4);
}
static __inline int
bcd2bin(int x)
{
return (x >> 4) * 10 + (x & 0x0f);
}
int
cdrom_lba_to_msf_accurate(int lba)
{
int pos;
int m;
int s;
int f;
pos = lba + 150;
f = pos % 75;
pos -= f;
pos /= 75;
s = pos % 60;
pos -= s;
pos /= 60;
m = pos;
return ((m << 16) | (s << 8) | f);
}
static double
cdrom_get_short_seek(cdrom_t *dev)
{
switch (dev->cur_speed) {
case 0:
fatal("CD-ROM %i: 0x speed\n", dev->id);
return 0.0;
case 1:
return 240.0;
case 2:
return 160.0;
case 3:
return 150.0;
case 4:
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
case 11:
return 112.0;
case 12:
case 13:
case 14:
case 15:
return 75.0;
case 16:
case 17:
case 18:
case 19:
return 58.0;
case 20:
case 21:
case 22:
case 23:
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
case 48:
return 50.0;
default:
/* 24-32, 52+ */
return 45.0;
}
}
static double
cdrom_get_long_seek(cdrom_t *dev)
{
switch (dev->cur_speed) {
case 0:
fatal("CD-ROM %i: 0x speed\n", dev->id);
return 0.0;
case 1:
return 1446.0;
case 2:
return 1000.0;
case 3:
return 900.0;
case 4:
case 5:
case 6:
case 7:
case 8:
case 9:
case 10:
case 11:
return 675.0;
case 12:
case 13:
case 14:
case 15:
return 400.0;
case 16:
case 17:
case 18:
case 19:
return 350.0;
case 20:
case 21:
case 22:
case 23:
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
case 48:
return 300.0;
default:
/* 24-32, 52+ */
return 270.0;
}
}
double
cdrom_seek_time(cdrom_t *dev)
{
uint32_t diff = dev->seek_diff;
double sd = (double) (MAX_SEEK - MIN_SEEK);
if (diff < MIN_SEEK)
return 0.0;
if (diff > MAX_SEEK)
diff = MAX_SEEK;
diff -= MIN_SEEK;
return cdrom_get_short_seek(dev) + ((cdrom_get_long_seek(dev) * ((double) diff)) / sd);
}
void
cdrom_stop(cdrom_t *dev)
{
if (dev->cd_status > CD_STATUS_DATA_ONLY)
dev->cd_status = CD_STATUS_STOPPED;
}
void
cdrom_seek(cdrom_t *dev, uint32_t pos, uint8_t vendor_type)
{
int m;
int s;
int f;
if (!dev)
return;
cdrom_log("CD-ROM %i: Seek to LBA %08X, vendor type = %02x.\n", dev->id, pos, vendor_type);
switch (vendor_type) {
case 0x40:
m = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
f = bcd2bin((pos >> 8) & 0xff);
pos = MSFtoLBA(m, s, f) - 150;
break;
case 0x80:
pos = bcd2bin((pos >> 24) & 0xff);
break;
default:
break;
}
dev->seek_pos = pos;
cdrom_stop(dev);
}
int
cdrom_is_pre(cdrom_t *dev, uint32_t lba)
{
if (dev->ops && dev->ops->is_track_pre)
return dev->ops->is_track_pre(dev, lba);
return 0;
}
int
cdrom_audio_callback(cdrom_t *dev, int16_t *output, int len)
{
int ret = 1;
if (!dev->sound_on || (dev->cd_status != CD_STATUS_PLAYING) || dev->audio_muted_soft) {
cdrom_log("CD-ROM %i: Audio callback while not playing\n", dev->id);
if (dev->cd_status == CD_STATUS_PLAYING)
dev->seek_pos += (len >> 11);
memset(output, 0, len * 2);
return 0;
}
while (dev->cd_buflen < len) {
if (dev->seek_pos < dev->cd_end) {
if (dev->ops->read_sector(dev, CD_READ_AUDIO, (uint8_t *) &(dev->cd_buffer[dev->cd_buflen]),
dev->seek_pos)) {
cdrom_log("CD-ROM %i: Read LBA %08X successful\n", dev->id, dev->seek_pos);
dev->seek_pos++;
dev->cd_buflen += (RAW_SECTOR_SIZE / 2);
ret = 1;
} else {
cdrom_log("CD-ROM %i: Read LBA %08X failed\n", dev->id, dev->seek_pos);
memset(&(dev->cd_buffer[dev->cd_buflen]), 0x00, (BUF_SIZE - dev->cd_buflen) * 2);
dev->cd_status = CD_STATUS_STOPPED;
dev->cd_buflen = len;
ret = 0;
}
} else {
cdrom_log("CD-ROM %i: Playing completed\n", dev->id);
memset(&dev->cd_buffer[dev->cd_buflen], 0x00, (BUF_SIZE - dev->cd_buflen) * 2);
dev->cd_status = CD_STATUS_PLAYING_COMPLETED;
dev->cd_buflen = len;
ret = 0;
}
}
memcpy(output, dev->cd_buffer, len * 2);
memmove(dev->cd_buffer, &dev->cd_buffer[len], (BUF_SIZE - len) * 2);
dev->cd_buflen -= len;
cdrom_log("CD-ROM %i: Audio callback returning %i\n", dev->id, ret);
return ret;
}
static void
msf_from_bcd(int *m, int *s, int *f)
{
*m = bcd2bin(*m);
*s = bcd2bin(*s);
*f = bcd2bin(*f);
}
static void
msf_to_bcd(int *m, int *s, int *f)
{
*m = bin2bcd(*m);
*s = bin2bcd(*s);
*f = bin2bcd(*f);
}
uint8_t
cdrom_audio_play(cdrom_t *dev, uint32_t pos, uint32_t len, int ismsf)
{
track_info_t ti;
int m = 0;
int s = 0;
int f = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
cdrom_log("CD-ROM %i: Play audio - %08X %08X %i\n", dev->id, pos, len, ismsf);
if (ismsf & 0x100) {
/* Track-relative audio play. */
dev->ops->get_track_info(dev, ismsf & 0xff, 0, &ti);
pos += MSFtoLBA(ti.m, ti.s, ti.f) - 150;
} else if ((ismsf == 2) || (ismsf == 3)) {
dev->ops->get_track_info(dev, pos, 0, &ti);
pos = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
if (ismsf == 2) {
/* We have to end at the *end* of the specified track,
not at the beginning. */
dev->ops->get_track_info(dev, len, 1, &ti);
len = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
}
} else if (ismsf == 1) {
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) /*NEC*/
msf_from_bcd(&m, &s, &f);
if (pos == 0xffffff) {
cdrom_log("CD-ROM %i: Playing from current position (MSF)\n", dev->id);
pos = dev->seek_pos;
} else
pos = MSFtoLBA(m, s, f) - 150;
m = (len >> 16) & 0xff;
s = (len >> 8) & 0xff;
f = len & 0xff;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) /*NEC*/
msf_from_bcd(&m, &s, &f);
len = MSFtoLBA(m, s, f) - 150;
cdrom_log("CD-ROM %i: MSF - pos = %08X len = %08X\n", dev->id, pos, len);
} else if (ismsf == 0) {
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: Playing from current position\n", dev->id);
pos = dev->seek_pos;
}
len += pos;
}
dev->audio_muted_soft = 0;
/* Do this at this point, since it's at this point that we know the
actual LBA position to start playing from. */
if (!(dev->ops->track_type(dev, pos) & CD_TRACK_AUDIO)) {
cdrom_log("CD-ROM %i: LBA %08X not on an audio track\n", dev->id, pos);
cdrom_stop(dev);
return 0;
}
dev->seek_pos = pos;
dev->cd_end = len;
dev->cd_status = CD_STATUS_PLAYING;
dev->cd_buflen = 0;
return 1;
}
uint8_t
cdrom_audio_track_search(cdrom_t *dev, uint32_t pos, int type, uint8_t playbit)
{
int m = 0;
int s = 0;
int f = 0;
uint32_t pos2 = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
cdrom_log("Audio Track Search: MSF = %06x, type = %02x, playbit = %02x\n", pos, type, playbit);
switch (type) {
case 0x00:
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: (type 0) Search from current position\n", dev->id);
pos = dev->seek_pos;
}
dev->seek_pos = pos;
break;
case 0x40:
m = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
f = bcd2bin((pos >> 8) & 0xff);
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: (type 1) Search from current position\n", dev->id);
pos = dev->seek_pos;
} else
pos = MSFtoLBA(m, s, f) - 150;
dev->seek_pos = pos;
break;
case 0x80:
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: (type 2) Search from current position\n", dev->id);
pos = dev->seek_pos;
}
dev->seek_pos = (pos >> 24) & 0xff;
break;
default:
break;
}
pos2 = pos - 1;
if (pos2 == 0xffffffff)
pos2 = pos + 1;
/* Do this at this point, since it's at this point that we know the
actual LBA position to start playing from. */
if (!(dev->ops->track_type(dev, pos2) & CD_TRACK_AUDIO)) {
cdrom_log("CD-ROM %i: Track Search: LBA %08X not on an audio track\n", dev->id, pos);
dev->audio_muted_soft = 1;
if (dev->ops->track_type(dev, pos) & CD_TRACK_AUDIO)
dev->audio_muted_soft = 0;
} else
dev->audio_muted_soft = 0;
cdrom_log("Track Search Toshiba: Muted?=%d, LBA=%08X.\n", dev->audio_muted_soft, pos);
dev->cd_buflen = 0;
dev->cd_status = playbit ? CD_STATUS_PLAYING : CD_STATUS_PAUSED;
return 1;
}
uint8_t
cdrom_audio_track_search_pioneer(cdrom_t *dev, uint32_t pos, uint8_t playbit)
{
int m = 0;
int s = 0;
int f = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
f = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
m = bcd2bin((pos >> 8) & 0xff);
if (pos == 0xffffffff) {
pos = dev->seek_pos;
} else
pos = MSFtoLBA(m, s, f) - 150;
dev->seek_pos = pos;
dev->audio_muted_soft = 0;
/* Do this at this point, since it's at this point that we know the
actual LBA position to start playing from. */
if (!(dev->ops->track_type(dev, pos) & CD_TRACK_AUDIO)) {
cdrom_log("CD-ROM %i: LBA %08X not on an audio track\n", dev->id, pos);
cdrom_stop(dev);
return 0;
}
dev->cd_buflen = 0;
dev->cd_status = playbit ? CD_STATUS_PLAYING : CD_STATUS_PAUSED;
return 1;
}
uint8_t
cdrom_audio_play_pioneer(cdrom_t *dev, uint32_t pos)
{
int m = 0;
int s = 0;
int f = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
f = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
m = bcd2bin((pos >> 8) & 0xff);
pos = MSFtoLBA(m, s, f) - 150;
dev->cd_end = pos;
dev->audio_muted_soft = 0;
dev->cd_buflen = 0;
dev->cd_status = CD_STATUS_PLAYING;
return 1;
}
uint8_t
cdrom_audio_play_toshiba(cdrom_t *dev, uint32_t pos, int type)
{
int m = 0;
int s = 0;
int f = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
/*Preliminary support, revert if too incomplete*/
switch (type) {
case 0x00:
dev->cd_end = pos;
break;
case 0x40:
m = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
f = bcd2bin((pos >> 8) & 0xff);
pos = MSFtoLBA(m, s, f) - 150;
dev->cd_end = pos;
break;
case 0x80:
dev->cd_end = (pos >> 24) & 0xff;
break;
case 0xc0:
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: Playing from current position\n", dev->id);
pos = dev->cd_end;
}
dev->cd_end = pos;
break;
default:
break;
}
cdrom_log("Toshiba Play Audio: Muted?=%d, LBA=%08X.\n", dev->audio_muted_soft, pos);
dev->cd_buflen = 0;
dev->cd_status = CD_STATUS_PLAYING;
return 1;
}
uint8_t
cdrom_audio_scan(cdrom_t *dev, uint32_t pos, int type)
{
int m = 0;
int s = 0;
int f = 0;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
cdrom_log("Audio Scan: MSF = %06x, type = %02x\n", pos, type);
switch (type) {
case 0x00:
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: (type 0) Search from current position\n", dev->id);
pos = dev->seek_pos;
}
dev->seek_pos = pos;
break;
case 0x40:
m = bcd2bin((pos >> 24) & 0xff);
s = bcd2bin((pos >> 16) & 0xff);
f = bcd2bin((pos >> 8) & 0xff);
if (pos == 0xffffffff) {
cdrom_log("CD-ROM %i: (type 1) Search from current position\n", dev->id);
pos = dev->seek_pos;
} else
pos = MSFtoLBA(m, s, f) - 150;
dev->seek_pos = pos;
break;
case 0x80:
dev->seek_pos = (pos >> 24) & 0xff;
break;
default:
break;
}
dev->audio_muted_soft = 0;
/* Do this at this point, since it's at this point that we know the
actual LBA position to start playing from. */
if (!(dev->ops->track_type(dev, pos) & CD_TRACK_AUDIO)) {
cdrom_log("CD-ROM %i: LBA %08X not on an audio track\n", dev->id, pos);
cdrom_stop(dev);
return 0;
}
dev->cd_buflen = 0;
return 1;
}
void
cdrom_audio_pause_resume(cdrom_t *dev, uint8_t resume)
{
if ((dev->cd_status == CD_STATUS_PLAYING) || (dev->cd_status == CD_STATUS_PAUSED))
dev->cd_status = (dev->cd_status & 0xfe) | (resume & 0x01);
}
uint8_t
cdrom_get_current_subchannel(cdrom_t *dev, uint8_t *b, int msf)
{
uint8_t ret;
subchannel_t subc;
int pos = 1;
int m;
int s;
int f;
uint32_t dat;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
if (dev->cd_status == CD_STATUS_DATA_ONLY)
ret = 0x15;
else {
if (dev->cd_status == CD_STATUS_PLAYING)
ret = 0x11;
else if (dev->cd_status == CD_STATUS_PAUSED)
ret = 0x12;
else
ret = 0x13;
}
cdrom_log("CD-ROM %i: Returned subchannel absolute at %02i:%02i.%02i, relative at %02i:%02i.%02i, ret = %02x, seek pos = %08x, cd_end = %08x.\n", dev->id, subc.abs_m, subc.abs_s, subc.abs_f, subc.rel_m, subc.rel_s, subc.rel_f, ret, dev->seek_pos, dev->cd_end);
if (b[pos] > 1) {
cdrom_log("B[%i] = %02x, ret = %02x.\n", pos, b[pos], ret);
return ret;
}
b[pos++] = subc.attr;
b[pos++] = subc.track;
b[pos++] = subc.index;
if (msf) {
b[pos] = 0;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) { /*NEC*/
m = subc.abs_m;
s = subc.abs_s;
f = subc.abs_f;
msf_to_bcd(&m, &s, &f);
b[pos + 1] = m;
b[pos + 2] = s;
b[pos + 3] = f;
} else {
b[pos + 1] = subc.abs_m;
b[pos + 2] = subc.abs_s;
b[pos + 3] = subc.abs_f;
}
pos += 4;
b[pos] = 0;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) { /*NEC*/
m = subc.rel_m;
s = subc.rel_s;
f = subc.rel_f;
msf_to_bcd(&m, &s, &f);
b[pos + 1] = m;
b[pos + 2] = s;
b[pos + 3] = f;
} else {
b[pos + 1] = subc.rel_m;
b[pos + 2] = subc.rel_s;
b[pos + 3] = subc.rel_f;
}
pos += 4;
} else {
dat = MSFtoLBA(subc.abs_m, subc.abs_s, subc.abs_f) - 150;
b[pos++] = (dat >> 24) & 0xff;
b[pos++] = (dat >> 16) & 0xff;
b[pos++] = (dat >> 8) & 0xff;
b[pos++] = dat & 0xff;
dat = MSFtoLBA(subc.rel_m, subc.rel_s, subc.rel_f);
b[pos++] = (dat >> 24) & 0xff;
b[pos++] = (dat >> 16) & 0xff;
b[pos++] = (dat >> 8) & 0xff;
b[pos++] = dat & 0xff;
}
return ret;
}
void
cdrom_get_current_subchannel_sony(cdrom_t *dev, uint8_t *b, int msf)
{
subchannel_t subc;
uint32_t dat;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
cdrom_log("CD-ROM %i: Returned subchannel at %02i:%02i.%02i, seek pos = %08x, cd_end = %08x, msf = %x.\n", dev->id, subc.abs_m, subc.abs_s, subc.abs_f, dev->seek_pos, dev->cd_end, msf);
b[0] = subc.attr;
b[1] = subc.track;
b[2] = subc.index;
if (msf) {
b[3] = subc.rel_m;
b[4] = subc.rel_s;
b[5] = subc.rel_f;
b[6] = subc.abs_m;
b[7] = subc.abs_s;
b[8] = subc.abs_f;
} else {
dat = MSFtoLBA(subc.rel_m, subc.rel_s, subc.rel_f);
b[3] = (dat >> 16) & 0xff;
b[4] = (dat >> 8) & 0xff;
b[5] = dat & 0xff;
dat = MSFtoLBA(subc.abs_m, subc.abs_s, subc.abs_f) - 150;
b[6] = (dat >> 16) & 0xff;
b[7] = (dat >> 8) & 0xff;
b[8] = dat & 0xff;
}
}
uint8_t
cdrom_get_audio_status_pioneer(cdrom_t *dev, uint8_t *b)
{
uint8_t ret;
subchannel_t subc;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
if (dev->cd_status == CD_STATUS_DATA_ONLY)
ret = 0x05;
else {
if (dev->cd_status == CD_STATUS_PLAYING)
ret = dev->sound_on ? 0x00 : 0x02;
else if (dev->cd_status == CD_STATUS_PAUSED)
ret = 0x01;
else
ret = 0x03;
}
b[0] = 0;
b[1] = bin2bcd(subc.abs_m);
b[2] = bin2bcd(subc.abs_s);
b[3] = bin2bcd(subc.abs_f);
return ret;
}
uint8_t
cdrom_get_audio_status_sony(cdrom_t *dev, uint8_t *b, int msf)
{
uint8_t ret;
subchannel_t subc;
uint32_t dat;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
if (dev->cd_status == CD_STATUS_DATA_ONLY)
ret = 0x05;
else {
if (dev->cd_status == CD_STATUS_PLAYING)
ret = dev->sound_on ? 0x00 : 0x02;
else if (dev->cd_status == CD_STATUS_PAUSED)
ret = 0x01;
else
ret = 0x03;
}
if (msf) {
b[0] = 0;
b[1] = subc.abs_m;
b[2] = subc.abs_s;
b[3] = subc.abs_f;
} else {
dat = MSFtoLBA(subc.abs_m, subc.abs_s, subc.abs_f) - 150;
b[0] = (dat >> 24) & 0xff;
b[1] = (dat >> 16) & 0xff;
b[2] = (dat >> 8) & 0xff;
b[3] = dat & 0xff;
}
return ret;
}
void
cdrom_get_current_subcodeq(cdrom_t *dev, uint8_t *b)
{
subchannel_t subc;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
b[0] = subc.attr;
b[1] = bin2bcd(subc.track);
b[2] = bin2bcd(subc.index);
b[3] = bin2bcd(subc.rel_m);
b[4] = bin2bcd(subc.rel_s);
b[5] = bin2bcd(subc.rel_f);
b[6] = bin2bcd(subc.abs_m);
b[7] = bin2bcd(subc.abs_s);
b[8] = bin2bcd(subc.abs_f);
}
uint8_t
cdrom_get_current_subcodeq_playstatus(cdrom_t *dev, uint8_t *b)
{
uint8_t ret;
subchannel_t subc;
dev->ops->get_subchannel(dev, dev->seek_pos, &subc);
if ((dev->cd_status == CD_STATUS_DATA_ONLY) ||
(dev->cd_status == CD_STATUS_PLAYING_COMPLETED) ||
(dev->cd_status == CD_STATUS_STOPPED))
ret = 0x03;
else
ret = (dev->cd_status == CD_STATUS_PLAYING) ? 0x00 : dev->audio_op;
/*If a valid audio track is detected with audio on, unmute it.*/
if (dev->ops->track_type(dev, dev->seek_pos) & CD_TRACK_AUDIO)
dev->audio_muted_soft = 0;
cdrom_log("SubCodeQ: Play Status: Seek LBA=%08x, CDEND=%08x, mute=%d.\n", dev->seek_pos, dev->cd_end, dev->audio_muted_soft);
b[0] = subc.attr;
b[1] = bin2bcd(subc.track);
b[2] = bin2bcd(subc.index);
b[3] = bin2bcd(subc.rel_m);
b[4] = bin2bcd(subc.rel_s);
b[5] = bin2bcd(subc.rel_f);
b[6] = bin2bcd(subc.abs_m);
b[7] = bin2bcd(subc.abs_s);
b[8] = bin2bcd(subc.abs_f);
return ret;
}
static int
read_toc_normal(cdrom_t *dev, unsigned char *b, unsigned char start_track, int msf)
{
track_info_t ti;
int i;
int len = 4;
int m;
int s;
int f;
int first_track;
int last_track;
uint32_t temp;
cdrom_log("read_toc_normal(%08X, %08X, %02X, %i)\n", dev, b, start_track, msf);
dev->ops->get_tracks(dev, &first_track, &last_track);
/* Byte 2 = Number of the first track */
dev->ops->get_track_info(dev, 1, 0, &ti);
b[2] = ti.number;
cdrom_log(" b[2] = %02X\n", b[2]);
/* Byte 3 = Number of the last track before the lead-out track */
dev->ops->get_track_info(dev, last_track, 0, &ti);
b[3] = ti.number;
cdrom_log(" b[3] = %02X\n", b[2]);
if (start_track == 0x00)
first_track = 0;
else {
first_track = -1;
for (i = 0; i <= last_track; i++) {
dev->ops->get_track_info(dev, i + 1, 0, &ti);
if (ti.number >= start_track) {
first_track = i;
break;
}
}
}
cdrom_log(" first_track = %i, last_track = %i\n", first_track, last_track);
/* No suitable starting track, return with error. */
if (first_track == -1) {
cdrom_log(" [ERROR] No suitable track found\n");
return -1;
}
for (i = first_track; i <= last_track; i++) {
cdrom_log(" tracks(%i) = %02X, %02X, %i:%02i.%02i\n", i, ti.attr, ti.number, ti.m, ti.s, ti.f);
dev->ops->get_track_info(dev, i + 1, 0, &ti);
b[len++] = 0; /* reserved */
b[len++] = ti.attr;
b[len++] = ti.number; /* track number */
b[len++] = 0; /* reserved */
if (msf) {
b[len++] = 0;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) { /*NEC*/
m = ti.m;
s = ti.s;
f = ti.f;
msf_to_bcd(&m, &s, &f);
b[len++] = m;
b[len++] = s;
b[len++] = f;
} else {
b[len++] = ti.m;
b[len++] = ti.s;
b[len++] = ti.f;
}
} else {
temp = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
b[len++] = temp >> 24;
b[len++] = temp >> 16;
b[len++] = temp >> 8;
b[len++] = temp;
}
}
return len;
}
static int
read_toc_session(cdrom_t *dev, unsigned char *b, int msf)
{
track_info_t ti;
int len = 4;
int m;
int s;
int f;
uint32_t temp;
cdrom_log("read_toc_session(%08X, %08X, %i)\n", dev, b, msf);
/* Bytes 2 and 3 = Number of first and last sessions */
b[2] = b[3] = 1;
dev->ops->get_track_info(dev, 1, 0, &ti);
cdrom_log(" tracks(0) = %02X, %02X, %i:%02i.%02i\n", ti.attr, ti.number, ti.m, ti.s, ti.f);
b[len++] = 0; /* reserved */
b[len++] = ti.attr;
b[len++] = ti.number; /* track number */
b[len++] = 0; /* reserved */
if (msf) {
b[len++] = 0;
/* NEC CDR-260 speaks BCD. */
if ((dev->type == CDROM_TYPE_NEC_260_100) || (dev->type == CDROM_TYPE_NEC_260_101)) { /*NEC*/
m = ti.m;
s = ti.s;
f = ti.f;
msf_to_bcd(&m, &s, &f);
b[len++] = m;
b[len++] = s;
b[len++] = f;
} else {
b[len++] = ti.m;
b[len++] = ti.s;
b[len++] = ti.f;
}
} else {
temp = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
b[len++] = temp >> 24;
b[len++] = temp >> 16;
b[len++] = temp >> 8;
b[len++] = temp;
}
return len;
}
static int
read_toc_raw(cdrom_t *dev, unsigned char *b)
{
track_info_t ti;
int len = 4;
int first_track;
int last_track;
cdrom_log("read_toc_raw(%08X, %08X)\n", dev, b);
dev->ops->get_tracks(dev, &first_track, &last_track);
/* Bytes 2 and 3 = Number of first and last sessions */
b[2] = b[3] = 1;
for (int i = 0; i <= last_track; i++) {
dev->ops->get_track_info(dev, i + 1, 0, &ti);
cdrom_log(" tracks(%i) = %02X, %02X, %i:%02i.%02i\n", i, ti.attr, ti.number, ti.m, ti.s, ti.f);
b[len++] = 1; /* Session number */
b[len++] = ti.attr; /* Track ADR and Control */
b[len++] = 0; /* TNO (always 0) */
b[len++] = ti.number; /* Point (for track points - track number) */
b[len++] = ti.m; /* M */
b[len++] = ti.s; /* S */
b[len++] = ti.f; /* F */
b[len++] = 0;
b[len++] = 0;
b[len++] = 0;
}
return len;
}
static int
read_toc_sony(cdrom_t *dev, unsigned char *b, unsigned char start_track, int msf)
{
track_info_t ti;
int i;
int len = 4;
int first_track;
int last_track;
uint32_t temp;
cdrom_log("read_toc_sony(%08X, %08X, %02X, %i)\n", dev, b, start_track, msf);
dev->ops->get_tracks(dev, &first_track, &last_track);
/* Byte 2 = Number of the first track */
dev->ops->get_track_info(dev, 1, 0, &ti);
b[2] = ti.number;
cdrom_log(" b[2] = %02X\n", b[2]);
/* Byte 3 = Number of the last track before the lead-out track */
dev->ops->get_track_info(dev, last_track, 0, &ti);
b[3] = ti.number;
cdrom_log(" b[3] = %02X\n", b[2]);
if (start_track == 0x00)
first_track = 0;
else {
first_track = -1;
for (i = 0; i <= last_track; i++) {
dev->ops->get_track_info(dev, i + 1, 0, &ti);
if (ti.number >= start_track) {
first_track = i;
break;
}
}
}
cdrom_log(" first_track = %i, last_track = %i\n", first_track, last_track);
/* No suitable starting track, return with error. */
if (first_track == -1) {
cdrom_log(" [ERROR] No suitable track found\n");
return -1;
}
for (i = first_track; i <= last_track; i++) {
cdrom_log(" tracks(%i) = %02X, %02X, %i:%02i.%02i\n", i, ti.attr, ti.number, ti.m, ti.s, ti.f);
dev->ops->get_track_info(dev, i + 1, 0, &ti);
b[len++] = ti.number; /* track number */
b[len++] = ti.attr;
if (msf) {
b[len++] = 0;
b[len++] = ti.m;
b[len++] = ti.s;
b[len++] = ti.f;
} else {
temp = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
b[len++] = temp >> 24;
b[len++] = temp >> 16;
b[len++] = temp >> 8;
b[len++] = temp;
}
}
return len;
}
int
cdrom_read_toc(cdrom_t *dev, unsigned char *b, int type, unsigned char start_track, int msf, int max_len)
{
int len;
switch (type) {
case CD_TOC_NORMAL:
len = read_toc_normal(dev, b, start_track, msf);
break;
case CD_TOC_SESSION:
len = read_toc_session(dev, b, msf);
break;
case CD_TOC_RAW:
len = read_toc_raw(dev, b);
break;
default:
cdrom_log("CD-ROM %i: Unknown TOC read type: %i\n", dev->id, type);
return 0;
}
len = MIN(len, max_len);
b[0] = (uint8_t) (((len - 2) >> 8) & 0xff);
b[1] = (uint8_t) ((len - 2) & 0xff);
return len;
}
int
cdrom_read_toc_sony(cdrom_t *dev, unsigned char *b, unsigned char start_track, int msf, int max_len)
{
int len;
len = read_toc_sony(dev, b, start_track, msf);
len = MIN(len, max_len);
b[0] = (uint8_t) (((len - 2) >> 8) & 0xff);
b[1] = (uint8_t) ((len - 2) & 0xff);
return len;
}
/* New API calls for Mitsumi CD-ROM. */
void
cdrom_get_track_buffer(cdrom_t *dev, uint8_t *buf)
{
track_info_t ti;
int first_track;
int last_track;
if (dev != NULL) {
dev->ops->get_tracks(dev, &first_track, &last_track);
buf[0] = 1;
buf[1] = last_track + 1;
dev->ops->get_track_info(dev, 1, 0, &ti);
buf[2] = ti.m;
buf[3] = ti.s;
buf[4] = ti.f;
dev->ops->get_track_info(dev, last_track + 1, 0, &ti);
buf[5] = ti.m;
buf[6] = ti.s;
buf[7] = ti.f;
buf[8] = 0x00;
} else
memset(buf, 0x00, 9);
}
void
cdrom_get_q(cdrom_t *dev, uint8_t *buf, int *curtoctrk, uint8_t mode)
{
track_info_t ti;
int first_track;
int last_track;
if (dev != NULL) {
dev->ops->get_tracks(dev, &first_track, &last_track);
dev->ops->get_track_info(dev, *curtoctrk, 0, &ti);
buf[0] = (ti.attr << 4) & 0xf0;
buf[1] = ti.number;
buf[2] = bin2bcd(*curtoctrk + 1);
buf[3] = ti.m;
buf[4] = ti.s;
buf[5] = ti.f;
buf[6] = 0x00;
dev->ops->get_track_info(dev, 1, 0, &ti);
buf[7] = ti.m;
buf[8] = ti.s;
buf[9] = ti.f;
if (*curtoctrk >= (last_track + 1))
*curtoctrk = 0;
else if (mode)
*curtoctrk = *curtoctrk + 1;
} else
memset(buf, 0x00, 10);
}
uint8_t
cdrom_mitsumi_audio_play(cdrom_t *dev, uint32_t pos, uint32_t len)
{
track_info_t ti;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
cdrom_log("CD-ROM 0: Play Mitsumi audio - %08X %08X\n", pos, len);
dev->ops->get_track_info(dev, pos, 0, &ti);
pos = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
dev->ops->get_track_info(dev, len, 1, &ti);
len = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
/* Do this at this point, since it's at this point that we know the
actual LBA position to start playing from. */
if (!(dev->ops->track_type(dev, pos) & CD_TRACK_AUDIO)) {
cdrom_log("CD-ROM %i: LBA %08X not on an audio track\n", dev->id, pos);
cdrom_stop(dev);
return 0;
}
dev->seek_pos = pos;
dev->cd_end = len;
dev->cd_status = CD_STATUS_PLAYING;
dev->cd_buflen = 0;
return 1;
}
uint8_t
cdrom_read_disc_info_toc(cdrom_t *dev, unsigned char *b, unsigned char track, int type)
{
track_info_t ti;
int first_track;
int last_track;
int m = 0;
int s = 0;
int f = 0;
uint32_t temp;
dev->ops->get_tracks(dev, &first_track, &last_track);
cdrom_log("Read DISC Info TOC Type = %d, track = %d, first_track = %d, last_track = %d.\n", type, track, first_track, last_track);
switch (type) {
case 0:
b[0] = bin2bcd(first_track);
b[1] = bin2bcd(last_track);
b[2] = 0;
b[3] = 0;
cdrom_log("CD-ROM %i: Returned Toshiba/NEC disc information (type 0) at %02i:%02i\n", dev->id, b[0], b[1]);
break;
case 1:
dev->ops->get_track_info(dev, 0xaa, 0, &ti);
m = ti.m;
s = ti.s;
f = ti.f;
msf_to_bcd(&m, &s, &f);
b[0] = m;
b[1] = s;
b[2] = f;
b[3] = 0;
cdrom_log("CD-ROM %i: Returned Toshiba/NEC disc information (type 1) at %02i:%02i.%02i, track=%d\n", dev->id, b[0], b[1], b[2], bcd2bin(track));
break;
case 2:
if (track > bin2bcd(last_track))
return 0;
dev->ops->get_track_info(dev, bcd2bin(track), 0, &ti);
m = ti.m;
s = ti.s;
f = ti.f;
msf_to_bcd(&m, &s, &f);
b[0] = m;
b[1] = s;
b[2] = f;
b[3] = ti.attr;
cdrom_log("CD-ROM %i: Returned Toshiba/NEC disc information (type 2) at %02i:%02i.%02i, track=%d, m=%02i,s=%02i,f=%02i, tno=%02x.\n", dev->id, b[0], b[1], b[2], bcd2bin(track), m, s, f, ti.attr);
break;
case 3: /* Undocumented on NEC CD-ROM's, from information based on sr_vendor.c from the Linux kernel */
switch (dev->type) {
case CDROM_TYPE_NEC_25_10a:
case CDROM_TYPE_NEC_38_103:
case CDROM_TYPE_NEC_75_103:
case CDROM_TYPE_NEC_77_106:
case CDROM_TYPE_NEC_211_100:
case CDROM_TYPE_NEC_464_105:
dev->ops->get_track_info(dev, 1, 0, &ti);
b[0x0e] = 0;
temp = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
b[0x0f] = temp >> 24;
b[0x10] = temp >> 16;
b[0x11] = temp >> 8;
b[0x12] = temp;
break;
default:
dev->ops->get_track_info(dev, 1, 0, &ti);
b[0] = 0;
temp = MSFtoLBA(ti.m, ti.s, ti.f) - 150;
b[1] = temp >> 24;
b[2] = temp >> 16;
b[3] = temp >> 8;
break;
}
break;
default:
break;
}
return 1;
}
static int
track_type_is_valid(UNUSED(uint8_t id), int type, int flags, int audio, int mode2)
{
if (!(flags & 0x70) && (flags & 0xf8)) { /* 0x08/0x80/0x88 are illegal modes */
cdrom_log("CD-ROM %i: [Any Mode] 0x08/0x80/0x88 are illegal modes\n", id);
return 0;
}
if ((type != 1) && !audio) {
if ((flags & 0x06) == 0x06) {
cdrom_log("CD-ROM %i: [Any Data Mode] Invalid error flags\n", id);
return 0;
}
if (((flags & 0x700) == 0x300) || ((flags & 0x700) > 0x400)) {
cdrom_log("CD-ROM %i: [Any Data Mode] Invalid subchannel data flags (%02X)\n", id, flags & 0x700);
return 0;
}
if ((flags & 0x18) == 0x08) { /* EDC/ECC without user data is an illegal mode */
cdrom_log("CD-ROM %i: [Any Data Mode] EDC/ECC without user data is an illegal mode\n", id);
return 0;
}
if (((flags & 0xf0) == 0x90) || ((flags & 0xf0) == 0xc0)) { /* 0x90/0x98/0xC0/0xC8 are illegal modes */
cdrom_log("CD-ROM %i: [Any Data Mode] 0x90/0x98/0xC0/0xC8 are illegal modes\n", id);
return 0;
}
if (((type > 3) && (type != 8)) || (mode2 && (mode2 & 0x03))) {
if ((flags & 0xf0) == 0x30) { /* 0x30/0x38 are illegal modes */
cdrom_log("CD-ROM %i: [Any XA Mode 2] 0x30/0x38 are illegal modes\n", id);
return 0;
}
if (((flags & 0xf0) == 0xb0) || ((flags & 0xf0) == 0xd0)) { /* 0xBx and 0xDx are illegal modes */
cdrom_log("CD-ROM %i: [Any XA Mode 2] 0xBx and 0xDx are illegal modes\n", id);
return 0;
}
}
}
return 1;
}
static void
read_sector_to_buffer(cdrom_t *dev, uint8_t *rbuf, uint32_t msf, uint32_t lba, int mode2, int len)
{
uint8_t *bb = rbuf;
const int offset = (!!(mode2 & 0x03)) ? 24 : 16;
dev->ops->read_sector(dev, CD_READ_DATA, rbuf + offset, lba);
/* Sync bytes */
bb[0] = 0;
memset(bb + 1, 0xff, 10);
bb[11] = 0;
bb += 12;
/* Sector header */
bb[0] = (msf >> 16) & 0xff;
bb[1] = (msf >> 8) & 0xff;
bb[2] = msf & 0xff;
bb[3] = 1; /* mode 1 data */
bb += mode2 ? 12 : 4;
bb += len;
if (mode2 && ((mode2 & 0x03) == 1))
memset(bb, 0, 280);
else if (!mode2)
memset(bb, 0, 288);
}
static void
read_audio(cdrom_t *dev, uint32_t lba, uint8_t *b)
{
dev->ops->read_sector(dev, CD_READ_RAW, raw_buffer, lba);
memcpy(b, raw_buffer, 2352);
cdrom_sector_size = 2352;
}
static void
read_mode1(cdrom_t *dev, int cdrom_sector_flags, uint32_t lba, uint32_t msf, int mode2, uint8_t *b)
{
if ((dev->cd_status == CD_STATUS_DATA_ONLY) || (dev->ops->sector_size(dev, lba) == 2048))
read_sector_to_buffer(dev, raw_buffer, msf, lba, mode2, 2048);
else
dev->ops->read_sector(dev, CD_READ_RAW, raw_buffer, lba);
cdrom_sector_size = 0;
if (cdrom_sector_flags & 0x80) {
/* Sync */
cdrom_log("CD-ROM %i: [Mode 1] Sync\n", dev->id);
memcpy(b, raw_buffer, 12);
cdrom_sector_size += 12;
b += 12;
}
if (cdrom_sector_flags & 0x20) {
/* Header */
cdrom_log("CD-ROM %i: [Mode 1] Header\n", dev->id);
memcpy(b, raw_buffer + 12, 4);
cdrom_sector_size += 4;
b += 4;
}
if (cdrom_sector_flags & 0x40) {
/* Sub-header */
if (!(cdrom_sector_flags & 0x10)) {
/* No user data */
cdrom_log("CD-ROM %i: [Mode 1] Sub-header\n", dev->id);
memcpy(b, raw_buffer + 16, 8);
cdrom_sector_size += 8;
b += 8;
}
}
if (cdrom_sector_flags & 0x10) {
/* User data */
cdrom_log("CD-ROM %i: [Mode 1] User data\n", dev->id);
memcpy(b, raw_buffer + 16, 2048);
cdrom_sector_size += 2048;
b += 2048;
}
if (cdrom_sector_flags & 0x08) {
/* EDC/ECC */
cdrom_log("CD-ROM %i: [Mode 1] EDC/ECC\n", dev->id);
memcpy(b, raw_buffer + 2064, 288);
cdrom_sector_size += 288;
b += 288;
}
}
static void
read_mode2_non_xa(cdrom_t *dev, int cdrom_sector_flags, uint32_t lba, uint32_t msf, int mode2, uint8_t *b)
{
if ((dev->cd_status == CD_STATUS_DATA_ONLY) || (dev->ops->sector_size(dev, lba) == 2336))
read_sector_to_buffer(dev, raw_buffer, msf, lba, mode2, 2336);
else
dev->ops->read_sector(dev, CD_READ_RAW, raw_buffer, lba);
cdrom_sector_size = 0;
if (cdrom_sector_flags & 0x80) {
/* Sync */
cdrom_log("CD-ROM %i: [Mode 2 Formless] Sync\n", dev->id);
memcpy(b, raw_buffer, 12);
cdrom_sector_size += 12;
b += 12;
}
if (cdrom_sector_flags & 0x20) {
/* Header */
cdrom_log("CD-ROM %i: [Mode 2 Formless] Header\n", dev->id);
memcpy(b, raw_buffer + 12, 4);
cdrom_sector_size += 4;
b += 4;
}
/* Mode 1 sector, expected type is 1 type. */
if (cdrom_sector_flags & 0x40) {
/* Sub-header */
cdrom_log("CD-ROM %i: [Mode 2 Formless] Sub-header\n", dev->id);
memcpy(b, raw_buffer + 16, 8);
cdrom_sector_size += 8;
b += 8;
}
if (cdrom_sector_flags & 0x10) {
/* User data */
cdrom_log("CD-ROM %i: [Mode 2 Formless] User data\n", dev->id);
memcpy(b, raw_buffer + 24, 2336);
cdrom_sector_size += 2336;
b += 2336;
}
}
static void
read_mode2_xa_form1(cdrom_t *dev, int cdrom_sector_flags, uint32_t lba, uint32_t msf, int mode2, uint8_t *b)
{
if ((dev->cd_status == CD_STATUS_DATA_ONLY) || (dev->ops->sector_size(dev, lba) == 2048))
read_sector_to_buffer(dev, raw_buffer, msf, lba, mode2, 2048);
else
dev->ops->read_sector(dev, CD_READ_RAW, raw_buffer, lba);
cdrom_sector_size = 0;
if (cdrom_sector_flags & 0x80) {
/* Sync */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] Sync\n", dev->id);
memcpy(b, raw_buffer, 12);
cdrom_sector_size += 12;
b += 12;
}
if (cdrom_sector_flags & 0x20) {
/* Header */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] Header\n", dev->id);
memcpy(b, raw_buffer + 12, 4);
cdrom_sector_size += 4;
b += 4;
}
if (cdrom_sector_flags & 0x40) {
/* Sub-header */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] Sub-header\n", dev->id);
memcpy(b, raw_buffer + 16, 8);
cdrom_sector_size += 8;
b += 8;
}
if (cdrom_sector_flags & 0x10) {
/* User data */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] User data\n", dev->id);
memcpy(b, raw_buffer + 24, 2048);
cdrom_sector_size += 2048;
b += 2048;
}
if (cdrom_sector_flags & 0x08) {
/* EDC/ECC */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] EDC/ECC\n", dev->id);
memcpy(b, raw_buffer + 2072, 280);
cdrom_sector_size += 280;
b += 280;
}
}
static void
read_mode2_xa_form2(cdrom_t *dev, int cdrom_sector_flags, uint32_t lba, uint32_t msf, int mode2, uint8_t *b)
{
if ((dev->cd_status == CD_STATUS_DATA_ONLY) || (dev->ops->sector_size(dev, lba) == 2324))
read_sector_to_buffer(dev, raw_buffer, msf, lba, mode2, 2324);
else
dev->ops->read_sector(dev, CD_READ_RAW, raw_buffer, lba);
cdrom_sector_size = 0;
if (cdrom_sector_flags & 0x80) {
/* Sync */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 2] Sync\n", dev->id);
memcpy(b, raw_buffer, 12);
cdrom_sector_size += 12;
b += 12;
}
if (cdrom_sector_flags & 0x20) {
/* Header */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 2] Header\n", dev->id);
memcpy(b, raw_buffer + 12, 4);
cdrom_sector_size += 4;
b += 4;
}
if (cdrom_sector_flags & 0x40) {
/* Sub-header */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 2] Sub-header\n", dev->id);
memcpy(b, raw_buffer + 16, 8);
cdrom_sector_size += 8;
b += 8;
}
if (cdrom_sector_flags & 0x10) {
/* User data */
cdrom_log("CD-ROM %i: [XA Mode 2 Form 2] User data\n", dev->id);
memcpy(b, raw_buffer + 24, 2328);
cdrom_sector_size += 2328;
b += 2328;
}
}
int
cdrom_readsector_raw(cdrom_t *dev, uint8_t *buffer, int sector, int ismsf, int cdrom_sector_type,
int cdrom_sector_flags, int *len, uint8_t vendor_type)
{
uint8_t *b;
uint8_t *temp_b;
uint32_t msf;
uint32_t lba;
int audio = 0;
int mode2 = 0;
int m;
int s;
int f;
if (dev->cd_status == CD_STATUS_EMPTY)
return 0;
b = temp_b = buffer;
*len = 0;
if (ismsf) {
m = (sector >> 16) & 0xff;
s = (sector >> 8) & 0xff;
f = sector & 0xff;
lba = MSFtoLBA(m, s, f) - 150;
msf = sector;
} else {
switch (vendor_type) {
case 0x00:
lba = sector;
msf = cdrom_lba_to_msf_accurate(sector);
break;
case 0x40:
m = bcd2bin((sector >> 24) & 0xff);
s = bcd2bin((sector >> 16) & 0xff);
f = bcd2bin((sector >> 8) & 0xff);
lba = MSFtoLBA(m, s, f) - 150;
msf = sector;
break;
case 0x80:
lba = bcd2bin((sector >> 24) & 0xff);
msf = sector;
break;
/* Never used values but the compiler complains. */
default:
lba = msf = 0;
}
}
if (dev->ops->track_type)
audio = dev->ops->track_type(dev, lba);
mode2 = audio & ~CD_TRACK_AUDIO;
audio &= CD_TRACK_AUDIO;
memset(raw_buffer, 0, 2448);
memset(extra_buffer, 0, 296);
if ((cdrom_sector_flags & 0xf8) == 0x08) {
/* 0x08 is an illegal mode */
cdrom_log("CD-ROM %i: [Mode 1] 0x08 is an illegal mode\n", dev->id);
return 0;
}
if (!track_type_is_valid(dev->id, cdrom_sector_type, cdrom_sector_flags, audio, mode2))
return 0;
if ((cdrom_sector_type > 5) && (cdrom_sector_type != 8)) {
cdrom_log("CD-ROM %i: Attempting to read an unrecognized sector type from an image\n", dev->id);
return 0;
} else if (cdrom_sector_type == 1) {
if (!audio || (dev->cd_status == CD_STATUS_DATA_ONLY)) {
cdrom_log("CD-ROM %i: [Audio] Attempting to read an audio sector from a data image\n", dev->id);
return 0;
}
read_audio(dev, lba, temp_b);
} else if (cdrom_sector_type == 2) {
if (audio || mode2) {
cdrom_log("CD-ROM %i: [Mode 1] Attempting to read a sector of another type\n", dev->id);
return 0;
}
read_mode1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
} else if (cdrom_sector_type == 3) {
if (audio || !mode2 || (mode2 & 0x03)) {
cdrom_log("CD-ROM %i: [Mode 2 Formless] Attempting to read a sector of another type\n", dev->id);
return 0;
}
read_mode2_non_xa(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
} else if (cdrom_sector_type == 4) {
if (audio || !mode2 || ((mode2 & 0x03) != 1)) {
cdrom_log("CD-ROM %i: [XA Mode 2 Form 1] Attempting to read a sector of another type\n", dev->id);
return 0;
}
read_mode2_xa_form1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
} else if (cdrom_sector_type == 5) {
if (audio || !mode2 || ((mode2 & 0x03) != 2)) {
cdrom_log("CD-ROM %i: [XA Mode 2 Form 2] Attempting to read a sector of another type\n", dev->id);
return 0;
}
read_mode2_xa_form2(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
} else if (cdrom_sector_type == 8) {
if (audio) {
cdrom_log("CD-ROM %i: [Any Data] Attempting to read a data sector from an audio track\n", dev->id);
return 0;
}
if (mode2 && ((mode2 & 0x03) == 1))
read_mode2_xa_form1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
else if (!mode2)
read_mode1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
else {
cdrom_log("CD-ROM %i: [Any Data] Attempting to read a data sector whose cooked size is not 2048 bytes\n", dev->id);
return 0;
}
} else {
if (mode2) {
if ((mode2 & 0x03) == 0x01)
read_mode2_xa_form1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
else if ((mode2 & 0x03) == 0x02)
read_mode2_xa_form2(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
else
read_mode2_non_xa(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
} else {
if (audio)
read_audio(dev, lba, temp_b);
else
read_mode1(dev, cdrom_sector_flags, lba, msf, mode2, temp_b);
}
}
if ((cdrom_sector_flags & 0x06) == 0x02) {
/* Add error flags. */
cdrom_log("CD-ROM %i: Error flags\n", dev->id);
memcpy(b + cdrom_sector_size, extra_buffer, 294);
cdrom_sector_size += 294;
} else if ((cdrom_sector_flags & 0x06) == 0x04) {
/* Add error flags. */
cdrom_log("CD-ROM %i: Full error flags\n", dev->id);
memcpy(b + cdrom_sector_size, extra_buffer, 296);
cdrom_sector_size += 296;
}
if ((cdrom_sector_flags & 0x700) == 0x100) {
cdrom_log("CD-ROM %i: Raw subchannel data\n", dev->id);
memcpy(b + cdrom_sector_size, raw_buffer + 2352, 96);
cdrom_sector_size += 96;
} else if ((cdrom_sector_flags & 0x700) == 0x200) {
cdrom_log("CD-ROM %i: Q subchannel data\n", dev->id);
memcpy(b + cdrom_sector_size, raw_buffer + 2352, 16);
cdrom_sector_size += 16;
} else if ((cdrom_sector_flags & 0x700) == 0x400) {
cdrom_log("CD-ROM %i: R/W subchannel data\n", dev->id);
memcpy(b + cdrom_sector_size, raw_buffer + 2352, 96);
cdrom_sector_size += 96;
}
*len = cdrom_sector_size;
return 1;
}
/* Peform a master init on the entire module. */
void
cdrom_global_init(void)
{
/* Clear the global data. */
memset(cdrom, 0x00, sizeof(cdrom));
}
static void
cdrom_drive_reset(cdrom_t *dev)
{
dev->priv = NULL;
dev->insert = NULL;
dev->close = NULL;
dev->get_volume = NULL;
dev->get_channel = NULL;
}
void
cdrom_hard_reset(void)
{
cdrom_t *dev;
for (uint8_t i = 0; i < CDROM_NUM; i++) {
dev = &cdrom[i];
if (dev->bus_type) {
cdrom_log("CD-ROM %i: Hard reset\n", i);
dev->id = i;
cdrom_drive_reset(dev);
switch (dev->bus_type) {
case CDROM_BUS_ATAPI:
case CDROM_BUS_SCSI:
scsi_cdrom_drive_reset(i);
break;
default:
break;
}
dev->cd_status = CD_STATUS_EMPTY;
if (strlen(dev->image_path) > 0) {
#ifdef _WIN32
if ((strlen(dev->image_path) >= 1) && (dev->image_path[strlen(dev->image_path) - 1] == '/'))
dev->image_path[strlen(dev->image_path) - 1] = '\\';
#else
if ((strlen(dev->image_path) >= 1) &&
(dev->image_path[strlen(dev->image_path) - 1] == '\\'))
dev->image_path[strlen(dev->image_path) - 1] = '/';
#endif
if ((strlen(dev->image_path) != 0) && (strstr(dev->image_path, "ioctl://") == dev->image_path))
cdrom_ioctl_open(dev, dev->image_path);
else
cdrom_image_open(dev, dev->image_path);
}
}
}
sound_cd_thread_reset();
}
void
cdrom_close(void)
{
cdrom_t *dev;
for (uint8_t i = 0; i < CDROM_NUM; i++) {
dev = &cdrom[i];
if (dev->bus_type == CDROM_BUS_SCSI)
memset(&scsi_devices[dev->scsi_device_id], 0x00, sizeof(scsi_device_t));
if (dev->close)
dev->close(dev->priv);
if (dev->ops && dev->ops->exit)
dev->ops->exit(dev);
dev->ops = NULL;
dev->priv = NULL;
cdrom_drive_reset(dev);
}
}
/* Signal disc change to the emulated machine. */
void
cdrom_insert(uint8_t id)
{
cdrom_t *dev = &cdrom[id];
if (dev->bus_type && dev->insert)
dev->insert(dev->priv);
}
/* The mechanics of ejecting a CD-ROM from a drive. */
void
cdrom_eject(uint8_t id)
{
cdrom_t *dev = &cdrom[id];
/* This entire block should be in cdrom.c/cdrom_eject(dev*) ... */
if (strlen(dev->image_path) == 0) {
/* Switch from empty to empty. Do nothing. */
return;
}
strcpy(dev->prev_image_path, dev->image_path);
dev->ops->exit(dev);
dev->ops = NULL;
memset(dev->image_path, 0, sizeof(dev->image_path));
cdrom_insert(id);
plat_cdrom_ui_update(id, 0);
config_save();
}
/* The mechanics of re-loading a CD-ROM drive. */
void
cdrom_reload(uint8_t id)
{
cdrom_t *dev = &cdrom[id];
if ((strcmp(dev->image_path, dev->prev_image_path) == 0) || (strlen(dev->prev_image_path) == 0) || (strlen(dev->image_path) > 0)) {
/* Switch from empty to empty. Do nothing. */
return;
}
if (dev->ops && dev->ops->exit)
dev->ops->exit(dev);
dev->ops = NULL;
memset(dev->image_path, 0, sizeof(dev->image_path));
if (strlen(dev->image_path) > 0) {
/* Reload a previous image. */
if (strlen(dev->prev_image_path) > 0)
strcpy(dev->image_path, dev->prev_image_path);
#ifdef _WIN32
if (strlen(dev->prev_image_path) > 0) {
if ((strlen(dev->image_path) >= 1) && (dev->image_path[strlen(dev->image_path) - 1] == '/'))
dev->image_path[strlen(dev->image_path) - 1] = '\\';
}
#else
if (strlen(dev->prev_image_path) > 0) {
if ((strlen(dev->image_path) >= 1) && (dev->image_path[strlen(dev->image_path) - 1] == '\\'))
dev->image_path[strlen(dev->image_path) - 1] = '/';
}
#endif
if ((strlen(dev->image_path) != 0) && (strstr(dev->image_path, "ioctl://") == dev->image_path))
cdrom_ioctl_open(dev, dev->image_path);
else
cdrom_image_open(dev, dev->image_path);
cdrom_insert(id);
}
plat_cdrom_ui_update(id, 1);
config_save();
}
``` | /content/code_sandbox/src/cdrom/cdrom.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 18,412 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* CD-ROM image support.
*
*
*
* Authors: RichardG867,
* Miran Grca, <mgrca8@gmail.com>
* bit,
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/scsi_device.h>
#include <86box/cdrom_image_backend.h>
#include <86box/cdrom.h>
#include <86box/cdrom_image.h>
#ifdef ENABLE_CDROM_IMAGE_LOG
int cdrom_image_do_log = ENABLE_CDROM_IMAGE_LOG;
void
cdrom_image_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_image_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_image_log(fmt, ...)
#endif
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
static void
image_get_tracks(cdrom_t *dev, int *first, int *last)
{
cd_img_t *img = (cd_img_t *) dev->image;
TMSF tmsf;
cdi_get_audio_tracks(img, first, last, &tmsf);
}
static void
image_get_track_info(cdrom_t *dev, uint32_t track, int end, track_info_t *ti)
{
cd_img_t *img = (cd_img_t *) dev->image;
TMSF tmsf;
cdi_get_audio_track_info(img, end, track, &ti->number, &tmsf, &ti->attr);
ti->m = tmsf.min;
ti->s = tmsf.sec;
ti->f = tmsf.fr;
}
static void
image_get_subchannel(cdrom_t *dev, uint32_t lba, subchannel_t *subc)
{
cd_img_t *img = (cd_img_t *) dev->image;
TMSF rel_pos;
TMSF abs_pos;
cdi_get_audio_sub(img, lba, &subc->attr, &subc->track, &subc->index,
&rel_pos, &abs_pos);
subc->abs_m = abs_pos.min;
subc->abs_s = abs_pos.sec;
subc->abs_f = abs_pos.fr;
subc->rel_m = rel_pos.min;
subc->rel_s = rel_pos.sec;
subc->rel_f = rel_pos.fr;
cdrom_image_log("image_get_subchannel(): %02X, %02X, %02i, %02i:%02i:%02i, %02i:%02i:%02i\n",
subc->attr, subc->track, subc->index, subc->abs_m, subc->abs_s, subc->abs_f, subc->rel_m, subc->rel_s, subc->rel_f);
}
static int
image_get_capacity(cdrom_t *dev)
{
cd_img_t *img = (cd_img_t *) dev->image;
int first_track;
int last_track;
int number;
unsigned char attr;
uint32_t address = 0;
uint32_t lb = 0;
if (!img)
return 0;
cdi_get_audio_tracks_lba(img, &first_track, &last_track, &lb);
for (int c = 0; c <= last_track; c++) {
cdi_get_audio_track_info_lba(img, 0, c + 1, &number, &address, &attr);
if (address > lb)
lb = address;
}
return lb;
}
static int
image_is_track_audio(cdrom_t *dev, uint32_t pos, int ismsf)
{
cd_img_t *img = (cd_img_t *) dev->image;
uint8_t attr;
TMSF tmsf;
int m;
int s;
int f;
int number;
int track;
if (!img || (dev->cd_status == CD_STATUS_DATA_ONLY))
return 0;
if (ismsf) {
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
pos = MSFtoLBA(m, s, f) - 150;
}
/* GetTrack requires LBA. */
track = cdi_get_track(img, pos);
if (track == -1)
return 0;
else {
cdi_get_audio_track_info(img, 0, track, &number, &tmsf, &attr);
return attr == AUDIO_TRACK;
}
}
static int
image_is_track_pre(cdrom_t *dev, uint32_t lba)
{
cd_img_t *img = (cd_img_t *) dev->image;
int track;
/* GetTrack requires LBA. */
track = cdi_get_track(img, lba);
if (track != -1)
return cdi_get_audio_track_pre(img, track);
return 0;
}
static int
image_sector_size(struct cdrom *dev, uint32_t lba)
{
cd_img_t *img = (cd_img_t *) dev->image;
return cdi_get_sector_size(img, lba);
}
static int
image_read_sector(struct cdrom *dev, int type, uint8_t *b, uint32_t lba)
{
cd_img_t *img = (cd_img_t *) dev->image;
switch (type) {
case CD_READ_DATA:
return cdi_read_sector(img, b, 0, lba);
case CD_READ_AUDIO:
return cdi_read_sector(img, b, 1, lba);
case CD_READ_RAW:
if (cdi_get_sector_size(img, lba) == 2352)
return cdi_read_sector(img, b, 1, lba);
else
return cdi_read_sector_sub(img, b, lba);
default:
cdrom_image_log("CD-ROM %i: Unknown CD read type\n", dev->id);
return 0;
}
}
static int
image_track_type(cdrom_t *dev, uint32_t lba)
{
cd_img_t *img = (cd_img_t *) dev->image;
if (img) {
if (image_is_track_audio(dev, lba, 0))
return CD_TRACK_AUDIO;
else {
if (cdi_is_mode2(img, lba))
return CD_TRACK_MODE2 | cdi_get_mode2_form(img, lba);
}
}
return 0;
}
static int
image_ext_medium_changed(cdrom_t *dev)
{
return 0;
}
static void
image_exit(cdrom_t *dev)
{
cd_img_t *img = (cd_img_t *) dev->image;
cdrom_image_log("CDROM: image_exit(%s)\n", dev->image_path);
dev->cd_status = CD_STATUS_EMPTY;
if (img) {
cdi_close(img);
dev->image = NULL;
}
dev->ops = NULL;
}
static const cdrom_ops_t cdrom_image_ops = {
image_get_tracks,
image_get_track_info,
image_get_subchannel,
image_is_track_pre,
image_sector_size,
image_read_sector,
image_track_type,
image_ext_medium_changed,
image_exit
};
static int
image_open_abort(cdrom_t *dev)
{
cdrom_image_close(dev);
dev->ops = NULL;
dev->image_path[0] = 0;
return 1;
}
int
cdrom_image_open(cdrom_t *dev, const char *fn)
{
cd_img_t *img;
/* Make sure to not STRCPY if the two are pointing
at the same place. */
if (fn != dev->image_path)
strcpy(dev->image_path, fn);
/* Create new instance of the CDROM_Image class. */
img = (cd_img_t *) malloc(sizeof(cd_img_t));
/* This guarantees that if ops is not NULL, then
neither is the image pointer. */
if (!img)
return image_open_abort(dev);
memset(img, 0, sizeof(cd_img_t));
dev->image = img;
/* Open the image. */
int i = cdi_set_device(img, fn);
if (!i)
return image_open_abort(dev);
/* All good, reset state. */
if (i >= 2)
dev->cd_status = CD_STATUS_DATA_ONLY;
else
dev->cd_status = CD_STATUS_STOPPED;
dev->seek_pos = 0;
dev->cd_buflen = 0;
dev->cdrom_capacity = image_get_capacity(dev);
cdrom_image_log("CD-ROM capacity: %i sectors (%" PRIi64 " bytes)\n", dev->cdrom_capacity, ((uint64_t) dev->cdrom_capacity) << 11ULL);
/* Attach this handler to the drive. */
dev->ops = &cdrom_image_ops;
return 0;
}
void
cdrom_image_close(cdrom_t *dev)
{
cdrom_image_log("CDROM: image_close(%s)\n", dev->image_path);
if (dev && dev->ops && dev->ops->exit)
dev->ops->exit(dev);
}
``` | /content/code_sandbox/src/cdrom/cdrom_image.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,294 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Mitsumi CD-ROM emulation for the ISA bus.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/dma.h>
#include <86box/cdrom.h>
#include <86box/cdrom_interface.h>
#include <86box/cdrom_mitsumi.h>
#include <86box/plat.h>
#include <86box/sound.h>
#define MCD_DEFAULT_IOPORT 0x310
#define MCD_DEFAULT_IRQ 5
#define MCD_DEFAULT_DMA 5
#define RAW_SECTOR_SIZE 2352
#define COOKED_SECTOR_SIZE 2048
enum {
STAT_CMD_CHECK = 0x01,
STAT_PLAY_CDDA = 0x02,
STAT_ERROR = 0x04,
STAT_DISK_CDDA = 0x08,
STAT_SPIN = 0x10,
STAT_CHANGE = 0x20,
STAT_READY = 0x40,
STAT_OPEN = 0x80
};
enum {
CMD_GET_INFO = 0x10,
CMD_GET_Q = 0x20,
CMD_GET_STAT = 0x40,
CMD_SET_MODE = 0x50,
CMD_SOFT_RESET = 0x60,
CMD_STOPCDDA = 0x70,
CMD_CONFIG = 0x90,
CMD_SET_VOL = 0xae,
CMD_READ1X = 0xc0,
CMD_READ2X = 0xc1,
CMD_GET_VER = 0xdc,
CMD_STOP = 0xf0,
CMD_EJECT = 0xf6,
CMD_LOCK = 0xfe
};
enum {
MODE_MUTE = 0x01,
MODE_GET_TOC = 0x04,
MODE_STOP = 0x08,
MODE_ECC = 0x20,
MODE_DATA = 0x40
};
enum {
DRV_MODE_STOP,
DRV_MODE_READ,
DRV_MODE_CDDA
};
enum {
FLAG_NODATA = 2,
FLAG_NOSTAT = 4,
FLAG_UNK = 8, //??
FLAG_OPEN = 16
};
enum {
IRQ_DATAREADY = 1,
IRQ_DATACOMP = 2,
IRQ_ERROR = 4
};
typedef struct mcd_t {
int dma;
int irq;
int change;
int data;
uint8_t stat;
uint8_t buf[RAW_SECTOR_SIZE];
int buf_count;
int buf_idx;
uint8_t cmdbuf[16];
int cmdbuf_count;
int cmdrd_count;
int cmdbuf_idx;
uint8_t mode;
uint8_t cmd;
uint8_t conf;
uint8_t enable_irq;
uint8_t enable_dma;
uint16_t dmalen;
uint32_t readmsf;
uint32_t readcount;
int locked;
int drvmode;
int cur_toc_track;
int pos;
int newstat;
} mcd_t;
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#ifdef MSFtoLBA
#undef MSFtoLBA
#endif
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
#define CD_BCD(x) (((x) % 10) | (((x) / 10) << 4))
#define CD_DCB(x) ((((x) &0xf0) >> 4) * 10 + ((x) &0x0f))
#ifdef ENABLE_MITSUMI_CDROM_LOG
int mitsumi_cdrom_do_log = ENABLE_MITSUMI_CDROM_LOG;
void
mitsumi_cdrom_log(const char *fmt, ...)
{
va_list ap;
if (mitsumi_cdrom_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mitsumi_cdrom_log(fmt, ...)
#endif
static int
mitsumi_cdrom_is_ready(const cdrom_t *dev)
{
return (dev->image_path[0] != 0x00);
}
static void
mitsumi_cdrom_reset(mcd_t *dev)
{
cdrom_t cdrom;
dev->stat = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | STAT_CHANGE) : 0;
dev->cmdrd_count = 0;
dev->cmdbuf_count = 0;
dev->buf_count = 0;
dev->cur_toc_track = 0;
dev->enable_dma = 0;
dev->enable_irq = 0;
dev->conf = 0;
dev->dmalen = COOKED_SECTOR_SIZE;
dev->locked = 0;
dev->change = 1;
dev->newstat = 1;
dev->data = 0;
}
static int
mitsumi_cdrom_read_sector(mcd_t *dev, int first)
{
cdrom_t cdrom;
uint8_t status;
int ret;
if (dev->drvmode == DRV_MODE_CDDA) {
status = cdrom_mitsumi_audio_play(&cdrom, dev->readmsf, dev->readcount);
if (status == 1)
return status;
else
dev->drvmode = DRV_MODE_READ;
}
if ((dev->enable_irq & IRQ_DATACOMP) && !first) {
picint(1 << dev->irq);
}
if (!dev->readcount) {
dev->data = 0;
return 0;
}
cdrom_stop(&cdrom);
ret = cdrom_readsector_raw(&cdrom, dev->buf, cdrom.seek_pos, 0, 2, 0x10, (int *) &dev->readcount, 0);
if (!ret)
return 0;
if (dev->mode & 0x40) {
dev->buf[12] = CD_BCD((dev->readmsf >> 16) & 0xff);
dev->buf[13] = CD_BCD((dev->readmsf >> 8) & 0xff);
}
dev->readmsf = cdrom_lba_to_msf_accurate(cdrom.seek_pos + 1);
dev->buf_count = dev->dmalen + 1;
dev->buf_idx = 0;
dev->data = 1;
if (dev->enable_dma) {
while (dev->pos < dev->readcount) {
dma_channel_write(dev->dma, dev->buf[dev->pos]);
dev->pos++;
}
dev->pos = 0;
}
dev->readcount--;
if ((dev->enable_irq & IRQ_DATAREADY) && first)
picint(1 << dev->irq);
return 1;
}
static uint8_t
mitsumi_cdrom_in(uint16_t port, void *priv)
{
mcd_t *dev = (mcd_t *) priv;
uint8_t ret;
pclog("Mitsumi CD-ROM IN=%03x\n", port);
switch (port & 1) {
case 0:
if (dev->cmdbuf_count) {
dev->cmdbuf_count--;
return dev->cmdbuf[dev->cmdbuf_idx++];
} else if (dev->buf_count) {
ret = (dev->buf_idx < RAW_SECTOR_SIZE) ? dev->buf[dev->buf_idx] : 0;
dev->buf_idx++;
dev->buf_count--;
if (!dev->buf_count)
mitsumi_cdrom_read_sector(dev, 0);
pclog("Read port 0: ret = %02x\n", ret);
return ret;
}
pclog("Read port 0: stat = %02x\n", dev->stat);
return dev->stat;
case 1:
ret = 0;
picintc(1 << dev->irq);
if (!dev->buf_count || !dev->data || dev->enable_dma)
ret |= FLAG_NODATA;
if (!dev->cmdbuf_count || !dev->newstat)
ret |= FLAG_NOSTAT;
pclog("Read port 1: ret = %02x\n", ret | FLAG_UNK);
return ret | FLAG_UNK;
case 2:
break;
default:
break;
}
return 0xff;
}
static void
mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
{
mcd_t *dev = (mcd_t *) priv;
cdrom_t cdrom;
pclog("Mitsumi CD-ROM OUT=%03x, val=%02x\n", port, val);
switch (port & 1) {
case 0:
if (dev->cmdrd_count) {
dev->cmdrd_count--;
switch (dev->cmd) {
case CMD_SET_MODE:
dev->mode = val;
dev->cmdbuf[1] = 0;
dev->cmdbuf_count = 2;
break;
case CMD_LOCK:
dev->locked = val & 1;
dev->cmdbuf[1] = 0;
dev->cmdbuf[2] = 0;
dev->cmdbuf_count = 3;
break;
case CMD_CONFIG:
switch (dev->cmdrd_count) {
case 0:
switch (dev->conf) {
case 0x01:
dev->dmalen |= val;
break;
case 0x02:
dev->enable_dma = val;
break;
case 0x10:
dev->enable_irq = val;
break;
default:
break;
}
dev->cmdbuf[1] = 0;
dev->cmdbuf_count = 2;
dev->conf = 0;
break;
case 1:
if (dev->conf == 1) {
dev->dmalen = val << 8;
break;
}
dev->conf = val;
if (dev->conf == 1)
dev->cmdrd_count++;
break;
default:
break;
}
break;
case CMD_READ1X:
case CMD_READ2X:
switch (dev->cmdrd_count) {
case 0:
dev->readcount |= val;
mitsumi_cdrom_read_sector(dev, 1);
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = STAT_SPIN | STAT_READY;
break;
case 1:
dev->readcount |= (val << 8);
break;
case 2:
dev->readcount = (val << 16);
break;
case 5:
dev->readmsf = 0;
fallthrough;
case 4:
case 3:
dev->readmsf |= CD_DCB(val) << ((dev->cmdrd_count - 3) << 3);
break;
default:
break;
}
break;
default:
break;
}
if (!dev->cmdrd_count)
dev->stat = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
return;
}
dev->cmd = val;
dev->cmdbuf_idx = 0;
dev->cmdrd_count = 0;
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
dev->data = 0;
switch (val) {
case CMD_GET_INFO:
if (mitsumi_cdrom_is_ready(&cdrom)) {
cdrom_get_track_buffer(&cdrom, &(dev->cmdbuf[1]));
dev->cmdbuf_count = 10;
dev->readcount = 0;
} else {
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = STAT_CMD_CHECK;
}
break;
case CMD_GET_Q:
if (mitsumi_cdrom_is_ready(&cdrom)) {
cdrom_get_q(&cdrom, &(dev->cmdbuf[1]), &dev->cur_toc_track, dev->mode & MODE_GET_TOC);
dev->cmdbuf_count = 11;
dev->readcount = 0;
} else {
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = STAT_CMD_CHECK;
}
break;
case CMD_GET_STAT:
dev->change = 0;
break;
case CMD_SET_MODE:
dev->cmdrd_count = 1;
break;
case CMD_STOPCDDA:
case CMD_STOP:
cdrom_stop(&cdrom);
dev->drvmode = DRV_MODE_STOP;
dev->cur_toc_track = 0;
break;
case CMD_CONFIG:
dev->cmdrd_count = 2;
break;
case CMD_READ1X:
case CMD_READ2X:
if (mitsumi_cdrom_is_ready(&cdrom)) {
dev->readcount = 0;
dev->drvmode = (val == CMD_READ1X) ? DRV_MODE_CDDA : DRV_MODE_READ;
dev->cmdrd_count = 6;
} else {
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = STAT_CMD_CHECK;
}
break;
case CMD_GET_VER:
dev->cmdbuf[0] = 1;
dev->cmdbuf[1] = 'D';
dev->cmdbuf[2] = 0;
dev->cmdbuf_count = 3;
break;
case CMD_EJECT:
cdrom_stop(&cdrom);
cdrom_eject(0);
dev->readcount = 0;
break;
case CMD_LOCK:
dev->cmdrd_count = 1;
break;
case CMD_SOFT_RESET:
pclog("Soft Reset\n");
mitsumi_cdrom_reset(dev);
break;
default:
dev->cmdbuf[0] = dev->stat | STAT_CMD_CHECK;
break;
}
break;
case 1:
mitsumi_cdrom_reset(dev);
break;
case 2:
break;
default:
break;
}
}
static void *
mitsumi_cdrom_init(UNUSED(const device_t *info))
{
mcd_t *dev;
dev = malloc(sizeof(mcd_t));
memset(dev, 0x00, sizeof(mcd_t));
dev->irq = MCD_DEFAULT_IRQ;
dev->dma = MCD_DEFAULT_DMA;
io_sethandler(MCD_DEFAULT_IOPORT, 3,
mitsumi_cdrom_in, NULL, NULL, mitsumi_cdrom_out, NULL, NULL, dev);
mitsumi_cdrom_reset(dev);
return dev;
}
static void
mitsumi_cdrom_close(void *priv)
{
mcd_t *dev = (mcd_t *) priv;
if (dev) {
free(dev);
dev = NULL;
}
}
const device_t mitsumi_cdrom_device = {
.name = "Mitsumi CD-ROM interface",
.internal_name = "mcd",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 1,
.init = mitsumi_cdrom_init,
.close = mitsumi_cdrom_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/cdrom/cdrom_mitsumi.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,782 |
```c
/*This is the chipset used in the LaserXT series model*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/plat_unused.h>
static int laserxt_emspage[4];
static int laserxt_emscontrol[4];
static mem_mapping_t laserxt_ems_mapping[4];
static int laserxt_ems_baseaddr_index = 0;
static int laserxt_is_lxt3 = 0;
static uint32_t
get_laserxt_ems_addr(uint32_t addr)
{
if (laserxt_emspage[(addr >> 14) & 3] & 0x80) {
addr = (!laserxt_is_lxt3 ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10)) + ((laserxt_emspage[(addr >> 14) & 3] & 0x0F) << 14) + ((laserxt_emspage[(addr >> 14) & 3] & 0x40) << 12) + (addr & 0x3FFF);
}
return addr;
}
static void
laserxt_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
uint32_t paddr;
uint32_t vaddr;
switch (port) {
case 0x0208:
case 0x4208:
case 0x8208:
case 0xC208:
laserxt_emspage[port >> 14] = val;
paddr = 0xC0000 + (port & 0xC000) + (((laserxt_ems_baseaddr_index + (4 - (port >> 14))) & 0x0C) << 14);
if (val & 0x80) {
mem_mapping_enable(&laserxt_ems_mapping[port >> 14]);
vaddr = get_laserxt_ems_addr(paddr);
mem_mapping_set_exec(&laserxt_ems_mapping[port >> 14], ram + vaddr);
} else {
mem_mapping_disable(&laserxt_ems_mapping[port >> 14]);
}
flushmmucache();
break;
case 0x0209:
case 0x4209:
case 0x8209:
case 0xC209:
laserxt_emscontrol[port >> 14] = val;
laserxt_ems_baseaddr_index = 0;
for (uint8_t i = 0; i < 4; i++) {
laserxt_ems_baseaddr_index |= (laserxt_emscontrol[i] & 0x80) >> (7 - i);
}
mem_mapping_set_addr(&laserxt_ems_mapping[0], 0xC0000 + (((laserxt_ems_baseaddr_index + 4) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[1], 0xC4000 + (((laserxt_ems_baseaddr_index + 3) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[2], 0xC8000 + (((laserxt_ems_baseaddr_index + 2) & 0x0C) << 14), 0x4000);
mem_mapping_set_addr(&laserxt_ems_mapping[3], 0xCC000 + (((laserxt_ems_baseaddr_index + 1) & 0x0C) << 14), 0x4000);
flushmmucache();
break;
default:
break;
}
}
static uint8_t
laserxt_read(uint16_t port, UNUSED(void *priv))
{
switch (port) {
case 0x0208:
case 0x4208:
case 0x8208:
case 0xC208:
return laserxt_emspage[port >> 14];
case 0x0209:
case 0x4209:
case 0x8209:
case 0xC209:
return laserxt_emscontrol[port >> 14];
default:
break;
}
return 0xff;
}
static void
mem_write_laserxtems(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
addr = get_laserxt_ems_addr(addr);
if (addr < (mem_size << 10))
ram[addr] = val;
}
static uint8_t
mem_read_laserxtems(uint32_t addr, UNUSED(void *priv))
{
uint8_t val = 0xFF;
addr = get_laserxt_ems_addr(addr);
if (addr < (mem_size << 10))
val = ram[addr];
return val;
}
static void
laserxt_init(int is_lxt3)
{
if (mem_size > 640) {
io_sethandler(0x0208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0x4208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0x8208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
io_sethandler(0xc208, 0x0002, laserxt_read, NULL, NULL, laserxt_write, NULL, NULL, NULL);
mem_mapping_set_addr(&ram_low_mapping, 0, !is_lxt3 ? 0x70000 + (((mem_size + 64) & 255) << 10) : 0x30000 + (((mem_size + 320) & 511) << 10));
}
for (uint8_t i = 0; i < 4; i++) {
laserxt_emspage[i] = 0x7F;
laserxt_emscontrol[i] = (i == 3) ? 0x00 : 0x80;
mem_mapping_add(&laserxt_ems_mapping[i], 0xE0000 + (i << 14), 0x4000, mem_read_laserxtems, NULL, NULL, mem_write_laserxtems, NULL, NULL, ram + 0xA0000 + (i << 14), 0, NULL);
mem_mapping_disable(&laserxt_ems_mapping[i]);
}
mem_set_mem_state(0x0c0000, 0x40000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
laserxt_is_lxt3 = is_lxt3;
}
static void
machine_xt_laserxt_common_init(const machine_t *model,int is_lxt3)
{
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
nmi_init();
standalone_gameport_type = &gameport_device;
laserxt_init(is_lxt3);
}
int
machine_xt_laserxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ltxt/27c64.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_laserxt_common_init(model, 0);
return ret;
}
int
machine_xt_lxt3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/lxt3/27c64d.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_lxt3_device);
machine_xt_laserxt_common_init(model, 1);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_laserxt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,929 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Slot 2 machines.
*
* Slot 2 is quite a rare type of Slot. Used mostly by Pentium II & III Xeons
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/spd.h>
#include <86box/video.h>
#include <86box/clock.h>
#include "cpu.h"
#include <86box/machine.h>
int
machine_at_6gxu_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/6gxu/6gxu.f1c",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); /* On-Board SCSI. Not emulated at the moment */
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440gx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 512);
device_add(&w83782d_device); /* fans: CPU, Power, System; temperatures: System, CPU, unused */
hwm_values.temperatures[2] = 0; /* unused */
hwm_values.voltages[1] = 1500; /* VGTL */
return ret;
}
int
machine_at_s2dge_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/s2dge/2gu7301.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
device_add(&i440gx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 512);
device_add(&w83781d_device); /* fans: CPU1, CPU2, Thermal Control; temperatures: unused, CPU1, CPU2? */
hwm_values.fans[1] = 0; /* no CPU2 fan */
hwm_values.temperatures[0] = 0; /* unused */
hwm_values.temperatures[2] = 0; /* CPU2? */
return ret;
}
int
machine_at_fw6400gx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/fw6400gx/FWGX1211.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
device_add(&i440gx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87309_15c_device);
device_add(ics9xxx_get(ICS9250_08));
device_add(&sst_flash_29ee020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 512);
device_add(&w83781d_device); /* fans: Chassis, Power, CPU; temperatures: System, CPU, unused */
hwm_values.temperatures[3] = 0; /* unused */
hwm_values.voltages[1] = 1500; /* Vtt */
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_slot2.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,750 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Epson Equity LT portable computer emulation.
*
* Authors: Lubomir Rintel, <lkundrak@v3.sk>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdint.h>
#include <stdio.h>
#include <time.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/io.h>
#include <86box/keyboard.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/nvr.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/hdc.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
static void
elt_vid_off_poll(void *priv)
{
cga_t *cga = priv;
uint8_t hdisp = cga->crtc[1];
/* Don't display anything.
* TODO: Do something less stupid to emulate backlight off. */
cga->crtc[1] = 0;
cga_poll(cga);
cga->crtc[1] = hdisp;
}
static void
sysstat_out(UNUSED(uint16_t port), uint8_t val, void *priv)
{
cga_t *cga = priv;
switch (val) {
case 0:
break;
case 1:
/* Backlight off. */
if (cga)
timer_set_callback(&cga->timer, elt_vid_off_poll);
break;
case 2:
/* Backlight on. */
if (cga)
timer_set_callback(&cga->timer, cga_poll);
break;
default:
pclog("Unknown sysstat command: 0x%02x\n", val);
}
}
static uint8_t
sysstat_in(UNUSED(uint16_t port), void *priv)
{
const cga_t *cga = priv;
uint8_t ret = 0x0a; /* No idea what these bits are */
/* External CRT. We don't emulate the LCD/CRT switching, let's just
* frivolously use this bit to indicate we're using the LCD if the
* user didn't override the video card for now. */
if (cga == NULL)
ret |= 0x40;
return ret;
}
static void
elt_vid_out(uint16_t addr, uint8_t val, void *priv)
{
cga_t *cga = priv;
/* The Equity LT chipset's CRTC contains more registers than the
* regular CGA. The BIOS writes one of them, register 36 (0x24).
* Nothing is known about the number or function of those registers,
* let's just ignore them so that we don't clobber the CGA register.
* Also, the BIOS writes that register via the 3D0h/3D1h alias
* instead of the usual 3D4h/3D5h, possibly to keep the wraparound
* behavior on the usual addresses (just an assumption, not
* verified). */
switch (addr) {
case 0x3d0:
cga->crtcreg = val;
return;
case 0x3d1:
if (cga->crtcreg >= 32)
return;
fallthrough;
default:
cga->crtcreg &= 31;
cga_out(addr, val, priv);
}
}
static uint8_t
elt_vid_in(uint16_t addr, void *priv)
{
cga_t *cga = priv;
/* Just make sure we don't ever let regular CGA code run with crtcreg
* pointing out of crtcregs[] bounds. */
cga->crtcreg &= 31;
return cga_in(addr, priv);
}
static void
load_font_rom(uint32_t font_data)
{
for (uint16_t c = 0; c < 256; c++)
for (uint8_t d = 0; d < 8; d++)
fontdat[c][d] = mem_readb_phys(font_data++);
}
int
machine_elt_init(const machine_t *model)
{
cga_t *cga = NULL;
int ret;
ret = bios_load_interleavedr("roms/machines/elt/HLO-B2.rom",
"roms/machines/elt/HLO-A2.rom",
0x000fc000, 65536, 0);
if (bios_only || !ret)
return ret;
/* The machine doesn't have any separate font ROM chip. The text mode
* font is likely a mask ROM in the chipset. video_reset() will try
* to load a MDA font, but let's have a reasonable fall back if it's
* not available. Read in the graphical mode font from the BIOS ROM
* image. */
load_font_rom(0xffa6e);
machine_common_init(model);
nmi_init();
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
if (gfxcard[0] == VID_INTERNAL) {
cga = device_add(&cga_device);
io_removehandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, cga);
io_sethandler(0x03d0, 0x0010, elt_vid_in, NULL, NULL, elt_vid_out, NULL, NULL, cga);
}
/* Keyboard goes after the video, because on XT compatibles it's dealt
* with by the same PPI as the config switches and we need them to
* indicate the correct display type */
device_add(&keyboard_xt_device);
device_add(&elt_nvr_device);
io_sethandler(0x11b8, 1, sysstat_in, NULL, NULL, sysstat_out, NULL, NULL, cga);
return ret;
}
``` | /content/code_sandbox/src/machine/m_elt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,603 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of MCA-based PS/2 machines.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/nvr.h>
#include <86box/nvr_ps2.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/mouse.h>
#include <86box/port_6x.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/video.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
static struct ps2_t {
uint8_t adapter_setup;
uint8_t option[4];
uint8_t pos_vga;
uint8_t setup;
uint8_t sys_ctrl_port_a;
uint8_t subaddr_lo;
uint8_t subaddr_hi;
uint8_t memory_bank[8];
uint8_t io_id;
uint16_t planar_id;
mem_mapping_t split_mapping;
mem_mapping_t expansion_mapping;
mem_mapping_t cache_mapping;
uint8_t (*planar_read)(uint16_t port);
void (*planar_write)(uint16_t port, uint8_t val);
uint8_t mem_regs[3];
uint32_t split_addr;
uint32_t split_size;
uint32_t split_phys;
uint8_t mem_pos_regs[8];
uint8_t mem_2mb_pos_regs[8];
int pending_cache_miss;
serial_t *uart;
} ps2;
/*The model 70 type 3/4 BIOS performs cache testing. Since 86Box doesn't have any
proper cache emulation, it's faked a bit here.
Port E2 is used for cache diagnostics. Bit 7 seems to be set on a cache miss,
toggling bit 2 seems to clear this. The BIOS performs at least the following
tests :
- Disable RAM, access low 64kb (386) / 8kb (486), execute code from cache to
access low memory and verify that there are no cache misses.
- Write to low memory using DMA, read low memory and verify that all accesses
cause cache misses.
- Read low memory, verify that first access is cache miss. Read again and
verify that second access is cache hit.
These tests are also performed on the 486 model 70, despite there being no
external cache on this system. Port E2 seems to control the internal cache on
these systems. Presumably this port is connected to KEN#/FLUSH# on the 486.
This behaviour is required to pass the timer interrupt test on the 486 version
- the BIOS uses a fixed length loop that will terminate too early on a 486/25
if it executes from internal cache.
To handle this, 86Box uses some basic heuristics :
- If cache is enabled but RAM is disabled, accesses to low memory go directly
to cache memory.
- Reads to cache addresses not 'valid' will set the cache miss flag, and mark
that line as valid.
- Cache flushes will clear the valid array.
- DMA via the undocumented PS/2 command 0xb will clear the valid array.
- Disabling the cache will clear the valid array.
- Disabling the cache will also mark shadowed ROM areas as using ROM timings.
This works around the timing loop mentioned above.
*/
static uint8_t ps2_cache[65536];
static int ps2_cache_valid[65536 / 8];
#ifdef ENABLE_PS2_MCA_LOG
int ps2_mca_do_log = ENABLE_PS2_MCA_LOG;
static void
ps2_mca_log(const char *fmt, ...)
{
va_list ap;
if (ps2_mca_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ps2_mca_log(fmt, ...)
#endif
static uint8_t
ps2_read_cache_ram(uint32_t addr, UNUSED(void *priv))
{
ps2_mca_log("ps2_read_cache_ram: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS, cpu_state.pc);
if (!ps2_cache_valid[addr >> 3]) {
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
} else
ps2.pending_cache_miss = 0;
return ps2_cache[addr];
}
static uint16_t
ps2_read_cache_ramw(uint32_t addr, UNUSED(void *priv))
{
ps2_mca_log("ps2_read_cache_ramw: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS, cpu_state.pc);
if (!ps2_cache_valid[addr >> 3]) {
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
} else
ps2.pending_cache_miss = 0;
return *(uint16_t *) &ps2_cache[addr];
}
static uint32_t
ps2_read_cache_raml(uint32_t addr, UNUSED(void *priv))
{
ps2_mca_log("ps2_read_cache_raml: addr=%08x %i %04x:%04x\n", addr, ps2_cache_valid[addr >> 3], CS, cpu_state.pc);
if (!ps2_cache_valid[addr >> 3]) {
ps2_cache_valid[addr >> 3] = 1;
ps2.mem_regs[2] |= 0x80;
} else
ps2.pending_cache_miss = 0;
return *(uint32_t *) &ps2_cache[addr];
}
static void
ps2_write_cache_ram(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
ps2_mca_log("ps2_write_cache_ram: addr=%08x val=%02x %04x:%04x %i\n", addr, val, CS, cpu_state.pc);
ps2_cache[addr] = val;
}
void
ps2_cache_clean(void)
{
memset(ps2_cache_valid, 0, sizeof(ps2_cache_valid));
}
static uint8_t
ps2_read_split_ram(uint32_t addr, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
return mem_read_ram(addr, priv);
}
static uint16_t
ps2_read_split_ramw(uint32_t addr, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
return mem_read_ramw(addr, priv);
}
static uint32_t
ps2_read_split_raml(uint32_t addr, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
return mem_read_raml(addr, priv);
}
static void
ps2_write_split_ram(uint32_t addr, uint8_t val, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
mem_write_ram(addr, val, priv);
}
static void
ps2_write_split_ramw(uint32_t addr, uint16_t val, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
mem_write_ramw(addr, val, priv);
}
static void
ps2_write_split_raml(uint32_t addr, uint32_t val, void *priv)
{
addr = (addr % (ps2.split_size << 10)) + ps2.split_phys;
mem_write_raml(addr, val, priv);
}
#define PS2_SETUP_IO 0x80
#define PS2_SETUP_VGA 0x20
#define PS2_ADAPTER_SETUP 0x08
static uint8_t
model_50_read(uint16_t port)
{
switch (port) {
case 0x100:
return ps2.planar_id & 0xff;
case 0x101:
return ps2.planar_id >> 8;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
default:
break;
}
return 0xff;
}
static uint8_t
model_55sx_read(uint16_t port)
{
switch (port) {
case 0x100:
return ps2.planar_id & 0xff;
case 0x101:
return ps2.planar_id >> 8;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.memory_bank[ps2.option[3] & 7];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
default:
break;
}
return 0xff;
}
static uint8_t
model_70_type3_read(uint16_t port)
{
switch (port) {
case 0x100:
return ps2.planar_id & 0xff;
case 0x101:
return ps2.planar_id >> 8;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
default:
break;
}
return 0xff;
}
static uint8_t
model_80_read(uint16_t port)
{
switch (port) {
case 0x100:
return ps2.planar_id & 0xff;
case 0x101:
return ps2.planar_id >> 8;
case 0x102:
return ps2.option[0];
case 0x103:
return ps2.option[1];
case 0x104:
return ps2.option[2];
case 0x105:
return ps2.option[3];
case 0x106:
return ps2.subaddr_lo;
case 0x107:
return ps2.subaddr_hi;
default:
break;
}
return 0xff;
}
static void
model_50_write(uint16_t port, uint8_t val)
{
switch (port) {
case 0x102:
lpt1_remove();
serial_remove(ps2.uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps2.uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps2.uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2.option[1] = val;
break;
case 0x104:
ps2.option[2] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
default:
break;
}
}
static void
model_55sx_mem_recalc(void)
{
int state;
#ifdef ENABLE_PS2_MCA_LOG
int enabled_mem = 0;
#endif
int base = 0;
int remap_size = (ps2.option[3] & 0x10) ? 384 : 256;
int bit_mask = 0x00;
int max_rows = 4;
int bank_to_rows[16] = { 4, 2, 1, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0 };
ps2_mca_log("%02X %02X\n", ps2.option[1], ps2.option[3]);
mem_remap_top(remap_size);
mem_set_mem_state(0x00000000, (mem_size + 384) * 1024, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0x000e0000, 0x00020000, MEM_READ_EXTANY | MEM_WRITE_DISABLED);
for (uint8_t i = 0; i < 2; i++) {
max_rows = bank_to_rows[(ps2.memory_bank[i] >> 4) & 0x0f];
if (max_rows == 0)
continue;
for (int j = 0; j < max_rows; j++) {
if (ps2.memory_bank[i] & (1 << j)) {
ps2_mca_log("Set memory at %06X-%06X to internal\n", (base * 1024), (base * 1024) + (((base > 0) ? 1024 : 640) * 1024) - 1);
mem_set_mem_state(base * 1024, ((base > 0) ? 1024 : 640) * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
#ifdef ENABLE_PS2_MCA_LOG
enabled_mem += 1024;
#endif
bit_mask |= (1 << (j + (i << 2)));
}
base += 1024;
}
}
#ifdef ENABLE_PS2_MCA_LOG
ps2_mca_log("Enabled memory: %i kB (%02X)\n", enabled_mem, bit_mask);
#endif
if (ps2.option[3] & 0x10) {
/* Enable ROM. */
ps2_mca_log("Enable ROM\n");
state = MEM_READ_EXTANY;
} else {
/* Disable ROM. */
if ((ps2.option[1] & 1) && !(ps2.option[3] & 0x20) && (bit_mask & 0x01)) {
/* Disable RAM between 640 kB and 1 MB. */
ps2_mca_log("Disable ROM, enable RAM\n");
state = MEM_READ_INTERNAL;
} else {
ps2_mca_log("Disable ROM, disable RAM\n");
state = MEM_READ_DISABLED;
}
}
/* Write always disabled. */
state |= MEM_WRITE_DISABLED;
mem_set_mem_state(0xe0000, 0x20000, state);
#if 0
if (!(ps2.option[3] & 0x08)) {
ps2_mca_log("Memory not yet configured\n");
return;
}
#endif
ps2_mca_log("Enable shadow mapping at %06X-%06X\n", (mem_size * 1024), (mem_size * 1024) + (remap_size * 1024) - 1);
if ((ps2.option[1] & 1) && !(ps2.option[3] & 0x20) && (bit_mask & 0x01)) {
ps2_mca_log("Set memory at %06X-%06X to internal\n", (mem_size * 1024), (mem_size * 1024) + (remap_size * 1024) - 1);
mem_set_mem_state(mem_size * 1024, remap_size * 1024, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
flushmmucache_nopc();
}
static void
model_55sx_write(uint16_t port, uint8_t val)
{
switch (port) {
case 0x102:
lpt1_remove();
serial_remove(ps2.uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps2.uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps2.uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2_mca_log("Write POS1: %02X\n", val);
ps2.option[1] = val;
model_55sx_mem_recalc();
break;
case 0x104:
ps2.memory_bank[ps2.option[3] & 7] &= ~0xf;
ps2.memory_bank[ps2.option[3] & 7] |= (val & 0xf);
ps2_mca_log("Write memory bank %i: %02X\n", ps2.option[3] & 7, val);
model_55sx_mem_recalc();
break;
case 0x105:
ps2_mca_log("Write POS3: %02X\n", val);
ps2.option[3] = val;
model_55sx_mem_recalc();
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
default:
break;
}
}
static void
model_70_type3_write(uint16_t port, uint8_t val)
{
switch (port) {
case 0x102:
lpt1_remove();
serial_remove(ps2.uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps2.uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps2.uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
if (ps2.planar_id == 0xfff9)
ps2.option[1] = (ps2.option[1] & 0x0f) | (val & 0xf0);
break;
case 0x104:
if (ps2.planar_id == 0xfff9)
ps2.option[2] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
default:
break;
}
}
static void
model_80_write(uint16_t port, uint8_t val)
{
switch (port) {
case 0x102:
lpt1_remove();
serial_remove(ps2.uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps2.uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps2.uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps2.option[0] = val;
break;
case 0x103:
ps2.option[1] = (ps2.option[1] & 0x0f) | (val & 0xf0);
break;
case 0x104:
ps2.option[2] = val;
break;
case 0x105:
ps2.option[3] = val;
break;
case 0x106:
ps2.subaddr_lo = val;
break;
case 0x107:
ps2.subaddr_hi = val;
break;
default:
break;
}
}
uint8_t
ps2_mca_read(uint16_t port, UNUSED(void *priv))
{
uint8_t temp;
switch (port) {
case 0x91:
#if 0
fatal("Read 91 setup=%02x adapter=%02x\n", ps2.setup, ps2.adapter_setup);
#endif
if (!(ps2.setup & PS2_SETUP_IO))
temp = 0x00;
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0x00;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = 0x00;
else
temp = !mca_feedb();
temp |= 0xfe;
break;
case 0x94:
temp = ps2.setup;
break;
case 0x96:
temp = ps2.adapter_setup | 0x70;
break;
case 0x100:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0xfd;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x101:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = 0xef;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x102:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if (!(ps2.setup & PS2_SETUP_VGA))
temp = ps2.pos_vga;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x103:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x104:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x105:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x106:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
case 0x107:
if (!(ps2.setup & PS2_SETUP_IO))
temp = ps2.planar_read(port);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
temp = mca_read(port);
else
temp = 0xff;
break;
default:
temp = 0xff;
break;
}
ps2_mca_log("ps2_read: port=%04x temp=%02x\n", port, temp);
return temp;
}
static void
ps2_mca_write(uint16_t port, uint8_t val, UNUSED(void *priv))
{
ps2_mca_log("ps2_write: port=%04x val=%02x %04x:%04x\n", port, val, CS, cpu_state.pc);
switch (port) {
case 0x94:
ps2.setup = val;
break;
case 0x96:
if ((val & 0x80) && !(ps2.adapter_setup & 0x80))
mca_reset();
ps2.adapter_setup = val;
mca_set_index(val & 7);
break;
case 0x100:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
mca_write(port, val);
break;
case 0x101:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if ((ps2.setup & PS2_SETUP_VGA) && (ps2.adapter_setup & PS2_ADAPTER_SETUP))
mca_write(port, val);
break;
case 0x102:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (!(ps2.setup & PS2_SETUP_VGA))
ps2.pos_vga = val;
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x103:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x104:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x105:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x106:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
case 0x107:
if (!(ps2.setup & PS2_SETUP_IO))
ps2.planar_write(port, val);
else if (ps2.adapter_setup & PS2_ADAPTER_SETUP)
mca_write(port, val);
break;
default:
break;
}
}
static void
ps2_mca_board_common_init(void)
{
io_sethandler(0x0091, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0096, 0x0001, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
io_sethandler(0x0100, 0x0008, ps2_mca_read, NULL, NULL, ps2_mca_write, NULL, NULL, NULL);
device_add(&port_6x_ps2_device);
device_add(&port_92_device);
ps2.setup = 0xff;
lpt1_init(LPT_MDA_ADDR);
}
static uint8_t
ps2_mem_expansion_read(int port, UNUSED(void *priv))
{
return ps2.mem_pos_regs[port & 7];
}
static void
ps2_mem_expansion_write(int port, uint8_t val, UNUSED(void *priv))
{
if (port < 0x102 || port == 0x104)
return;
ps2.mem_pos_regs[port & 7] = val;
if (ps2.mem_pos_regs[2] & 1)
mem_mapping_enable(&ps2.expansion_mapping);
else
mem_mapping_disable(&ps2.expansion_mapping);
}
static uint8_t
ps2_mem_expansion_feedb(UNUSED(void *priv))
{
return (ps2.mem_pos_regs[2] & 1);
}
static void
ps2_mca_mem_fffc_init(int start_mb)
{
uint32_t planar_size;
uint32_t expansion_start;
planar_size = (start_mb - 1) << 20;
expansion_start = start_mb << 20;
mem_mapping_set_addr(&ram_high_mapping, 0x100000, planar_size);
ps2.mem_pos_regs[0] = 0xff;
ps2.mem_pos_regs[1] = 0xfc;
switch ((mem_size / 1024) - start_mb) {
case 1:
ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
break;
case 2:
ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
break;
case 3:
ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
break;
case 4:
ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
break;
case 5:
ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
break;
case 6:
ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
break;
case 7:
ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
break;
case 8:
ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
break;
default:
break;
}
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, ps2_mem_expansion_feedb, NULL, NULL);
mem_mapping_add(&ps2.expansion_mapping,
expansion_start,
(mem_size - (start_mb << 10)) << 10,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[expansion_start],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
static void
ps2_mca_mem_d071_init(int start_mb)
{
uint32_t planar_size;
uint32_t expansion_start;
planar_size = (start_mb - 1) << 20;
expansion_start = start_mb << 20;
mem_mapping_set_addr(&ram_high_mapping, 0x100000, planar_size);
ps2.mem_pos_regs[0] = 0xd0;
ps2.mem_pos_regs[1] = 0x71;
ps2.mem_pos_regs[4] = (mem_size / 1024) - start_mb;
mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, ps2_mem_expansion_feedb, NULL, NULL);
mem_mapping_add(&ps2.expansion_mapping,
expansion_start,
(mem_size - (start_mb << 10)) << 10,
mem_read_ram,
mem_read_ramw,
mem_read_raml,
mem_write_ram,
mem_write_ramw,
mem_write_raml,
&ram[expansion_start],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.expansion_mapping);
}
static void
ps2_mca_board_model_50_init(void)
{
ps2_mca_board_common_init();
mem_remap_top(384);
mca_init(4);
device_add(&keyboard_ps2_mca_2_device);
ps2.planar_read = model_50_read;
ps2.planar_write = model_50_write;
if (mem_size > 2048) {
/* Only 2 MB supported on planar, create a memory expansion card for the rest */
ps2_mca_mem_fffc_init(2);
}
if (gfxcard[0] == VID_INTERNAL)
device_add(&ps1vga_mca_device);
}
static void
ps2_mca_board_model_60_init(void)
{
ps2_mca_board_common_init();
mem_remap_top(384);
mca_init(8);
device_add(&keyboard_ps2_mca_2_device);
ps2.planar_read = model_50_read;
ps2.planar_write = model_50_write;
if (mem_size > 2048) {
/* Only 2 MB supported on planar, create a memory expansion card for the rest */
ps2_mca_mem_fffc_init(2);
}
device_add(&ps2_nvr_55ls_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&ps1vga_mca_device);
}
static void
ps2_mca_board_model_55sx_init(int has_sec_nvram, int slots)
{
ps2_mca_board_common_init();
ps2.option[1] = 0x00;
ps2.option[2] = 0x00;
ps2.option[3] = 0x10;
memset(ps2.memory_bank, 0xf0, 8);
switch (mem_size / 1024) {
case 1:
ps2.memory_bank[0] = 0x61;
break;
case 2:
ps2.memory_bank[0] = 0x51;
break;
case 3:
ps2.memory_bank[0] = 0x51;
ps2.memory_bank[1] = 0x61;
break;
case 4:
ps2.memory_bank[0] = 0x51;
ps2.memory_bank[1] = 0x51;
break;
case 5:
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x61;
break;
case 6:
case 7: /*Not supported*/
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x51;
break;
case 8:
ps2.memory_bank[0] = 0x01;
ps2.memory_bank[1] = 0x01;
break;
default:
break;
}
mca_init(slots);
device_add(&keyboard_ps2_mca_1_device);
if (has_sec_nvram)
device_add(&ps2_nvr_55ls_device);
ps2.planar_read = model_55sx_read;
ps2.planar_write = model_55sx_write;
if (gfxcard[0] == VID_INTERNAL)
device_add(&ps1vga_mca_device);
model_55sx_mem_recalc();
}
static void
mem_encoding_update(void)
{
mem_mapping_disable(&ps2.split_mapping);
if (ps2.split_size > 0)
mem_set_mem_state(ps2.split_addr, ps2.split_size << 10, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (((mem_size << 10) - (1 << 20)) > 0)
mem_set_mem_state(1 << 20, (mem_size << 10) - (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
ps2.split_addr = ((uint32_t) (ps2.mem_regs[0] & 0xf)) << 20;
if (!ps2.split_addr)
ps2.split_addr = 1 << 20;
if (ps2.mem_regs[1] & 2) {
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
ps2_mca_log("PS/2 Model 80-111: ROM space enabled\n");
} else {
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
ps2_mca_log("PS/2 Model 80-111: ROM space disabled\n");
}
if (ps2.mem_regs[1] & 4) {
mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0x80000);
ps2_mca_log("PS/2 Model 80-111: 00080000- 0009FFFF disabled\n");
} else {
mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0xa0000);
ps2_mca_log("PS/2 Model 80-111: 00080000- 0009FFFF enabled\n");
}
if (!(ps2.mem_regs[1] & 8)) {
if (ps2.mem_regs[1] & 4) {
ps2.split_size = 384;
ps2.split_phys = 0x80000;
} else {
ps2.split_size = 256;
ps2.split_phys = 0xa0000;
}
mem_set_mem_state(ps2.split_addr, ps2.split_size << 10, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_set_exec(&ps2.split_mapping, &ram[ps2.split_phys]);
mem_mapping_set_addr(&ps2.split_mapping, ps2.split_addr, ps2.split_size << 10);
ps2_mca_log("PS/2 Model 80-111: Split memory block enabled at %08X\n", ps2.split_addr);
} else {
ps2.split_size = 0;
ps2_mca_log("PS/2 Model 80-111: Split memory block disabled\n");
}
flushmmucache_nopc();
}
static uint8_t
mem_encoding_read(uint16_t addr, UNUSED(void *priv))
{
switch (addr) {
case 0xe0:
return ps2.mem_regs[0];
case 0xe1:
return ps2.mem_regs[1];
default:
break;
}
return 0xff;
}
static void
mem_encoding_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
{
switch (addr) {
case 0xe0:
ps2.mem_regs[0] = val;
break;
case 0xe1:
ps2.mem_regs[1] = val;
break;
default:
break;
}
mem_encoding_update();
}
static uint8_t
mem_encoding_read_cached(uint16_t addr, UNUSED(void *priv))
{
switch (addr) {
case 0xe0:
return ps2.mem_regs[0];
case 0xe1:
return ps2.mem_regs[1];
case 0xe2:
return ps2.mem_regs[2];
default:
break;
}
return 0xff;
}
static void
mem_encoding_write_cached(uint16_t addr, uint8_t val, UNUSED(void *priv))
{
uint8_t old;
switch (addr) {
case 0xe0:
ps2.mem_regs[0] = val;
break;
case 0xe1:
ps2.mem_regs[1] = val;
break;
case 0xe2:
old = ps2.mem_regs[2];
ps2.mem_regs[2] = (ps2.mem_regs[2] & 0x80) | (val & ~0x88);
if (val & 2) {
ps2_mca_log("Clear latch - %i\n", ps2.pending_cache_miss);
if (ps2.pending_cache_miss)
ps2.mem_regs[2] |= 0x80;
else
ps2.mem_regs[2] &= ~0x80;
ps2.pending_cache_miss = 0;
}
if ((val & 0x21) == 0x20 && (old & 0x21) != 0x20)
ps2.pending_cache_miss = 1;
if ((val & 0x21) == 0x01 && (old & 0x21) != 0x01)
ps2_cache_clean();
#if 1
// FIXME: Look into this!!!
if (val & 0x01)
ram_mid_mapping.flags |= MEM_MAPPING_ROM_WS;
else
ram_mid_mapping.flags &= ~MEM_MAPPING_ROM_WS;
#endif
break;
default:
break;
}
ps2_mca_log("mem_encoding_write: addr=%02x val=%02x %04x:%04x %02x %02x\n", addr, val, CS, cpu_state.pc, ps2.mem_regs[1], ps2.mem_regs[2]);
mem_encoding_update();
if ((ps2.mem_regs[1] & 0x10) && (ps2.mem_regs[2] & 0x21) == 0x20) {
mem_mapping_disable(&ram_low_mapping);
mem_mapping_enable(&ps2.cache_mapping);
flushmmucache();
} else {
mem_mapping_disable(&ps2.cache_mapping);
mem_mapping_enable(&ram_low_mapping);
flushmmucache();
}
}
static void
ps2_mca_board_model_70_type34_init(int is_type4, int slots)
{
ps2_mca_board_common_init();
ps2.split_addr = mem_size * 1024;
mca_init(slots);
device_add(&keyboard_ps2_mca_1_device);
ps2.planar_read = model_70_type3_read;
ps2.planar_write = model_70_type3_write;
device_add(&ps2_nvr_device);
io_sethandler(0x00e0, 0x0003, mem_encoding_read_cached, NULL, NULL, mem_encoding_write_cached, NULL, NULL, NULL);
ps2.mem_regs[1] = 2;
switch (mem_size / 1024) {
case 2:
ps2.option[1] = 0xa6;
ps2.option[2] = 0x01;
break;
case 4:
ps2.option[1] = 0xaa;
ps2.option[2] = 0x01;
break;
case 6:
ps2.option[1] = 0xca;
ps2.option[2] = 0x01;
break;
case 8:
default:
ps2.option[1] = 0xca;
ps2.option[2] = 0x02;
break;
}
if (is_type4)
ps2.option[2] |= 0x04; /*486 CPU*/
mem_mapping_add(&ps2.split_mapping,
(mem_size + 256) * 1024,
256 * 1024,
ps2_read_split_ram,
ps2_read_split_ramw,
ps2_read_split_raml,
ps2_write_split_ram,
ps2_write_split_ramw,
ps2_write_split_raml,
&ram[0xa0000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.split_mapping);
mem_mapping_add(&ps2.cache_mapping,
0,
is_type4 ? (8 * 1024) : (64 * 1024),
ps2_read_cache_ram,
ps2_read_cache_ramw,
ps2_read_cache_raml,
ps2_write_cache_ram,
NULL,
NULL,
ps2_cache,
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.cache_mapping);
if (ps2.planar_id == 0xfff9) {
if (mem_size > 4096) {
/* Only 4 MB supported on planar, create a memory expansion card for the rest */
if (mem_size > 12288) {
ps2_mca_mem_d071_init(4);
} else {
ps2_mca_mem_fffc_init(4);
}
}
} else {
if (mem_size > 8192) {
/* Only 8 MB supported on planar, create a memory expansion card for the rest */
if (mem_size > 16384)
ps2_mca_mem_d071_init(8);
else {
ps2_mca_mem_fffc_init(8);
}
}
}
if (gfxcard[0] == VID_INTERNAL)
device_add(&ps1vga_mca_device);
}
static void
ps2_mca_board_model_80_type2_init(void)
{
ps2_mca_board_common_init();
ps2.split_addr = mem_size * 1024;
mca_init(8);
device_add(&keyboard_ps2_mca_1_device);
ps2.planar_read = model_80_read;
ps2.planar_write = model_80_write;
device_add(&ps2_nvr_device);
io_sethandler(0x00e0, 0x0002, mem_encoding_read, NULL, NULL, mem_encoding_write, NULL, NULL, NULL);
ps2.mem_regs[1] = 2;
/* Note by Kotori: I rewrote this because the original code was using
Model 80 Type 1-style 1 MB memory card settings, which are *NOT*
supported by Model 80 Type 2. */
switch (mem_size / 1024) {
case 1:
ps2.option[1] = 0x0e; /* 11 10 = 0 2 */
ps2.mem_regs[1] = 0xd2; /* 01 = 1 (first) */
ps2.mem_regs[0] = 0xf0; /* 11 = invalid */
break;
case 2:
ps2.option[1] = 0x0e; /* 11 10 = 0 2 */
ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
ps2.mem_regs[0] = 0xf0; /* 11 = invalid */
break;
case 3:
ps2.option[1] = 0x0a; /* 10 10 = 2 2 */
ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
ps2.mem_regs[0] = 0xd0; /* 01 = 1 (first) */
break;
case 4:
default:
ps2.option[1] = 0x0a; /* 10 10 = 2 2 */
ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
ps2.mem_regs[0] = 0xc0; /* 00 = 2 */
break;
}
ps2.mem_regs[0] |= ((mem_size / 1024) & 0x0f);
mem_mapping_add(&ps2.split_mapping,
(mem_size + 256) * 1024,
256 * 1024,
ps2_read_split_ram,
ps2_read_split_ramw,
ps2_read_split_raml,
ps2_write_split_ram,
ps2_write_split_ramw,
ps2_write_split_raml,
&ram[0xa0000],
MEM_MAPPING_INTERNAL,
NULL);
mem_mapping_disable(&ps2.split_mapping);
if (mem_size > 4096) {
/* Only 4 MB supported on planar, create a memory expansion card for the rest */
if (mem_size > 12288)
ps2_mca_mem_d071_init(4);
else {
ps2_mca_mem_fffc_init(4);
}
}
if (gfxcard[0] == VID_INTERNAL)
device_add(&ps1vga_mca_device);
ps2.split_size = 0;
}
static void
machine_ps2_common_init(const machine_t *model)
{
machine_common_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
dma16_init();
ps2_dma_init();
device_add(&ps_no_nmi_nvr_device);
pic2_init();
int pit_type = ((pit_mode == -1 && is486) || pit_mode == 1) ? PIT_8254_FAST : PIT_8254;
pit_ps2_init(pit_type);
nmi_mask = 0x80;
ps2.uart = device_add_inst(&ns16550_device, 1);
}
int
machine_ps2_model_50_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m50/90x7420.zm13",
"roms/machines/ibmps2_m50/90x7429.zm18",
0x000f0000, 131072, 0);
ret &= bios_load_aux_interleaved("roms/machines/ibmps2_m50/90x7423.zm14",
"roms/machines/ibmps2_m50/90x7426.zm16",
0x000e0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xfbff;
ps2_mca_board_model_50_init();
return ret;
}
int
machine_ps2_model_60_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m50/90x7420.zm13",
"roms/machines/ibmps2_m50/90x7429.zm18",
0x000f0000, 131072, 0);
ret &= bios_load_aux_interleaved("roms/machines/ibmps2_m50/90x7423.zm14",
"roms/machines/ibmps2_m50/90x7426.zm16",
0x000e0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xf7ff;
ps2_mca_board_model_60_init();
return ret;
}
int
machine_ps2_model_55sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m55sx/33f8146.zm41",
"roms/machines/ibmps2_m55sx/33f8145.zm40",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xfbff;
ps2_mca_board_model_55sx_init(0, 4);
return ret;
}
int
machine_ps2_model_65sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m65sx/64F3608.BIN",
"roms/machines/ibmps2_m65sx/64F3611.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xe3ff;
ps2_mca_board_model_55sx_init(1, 8);
return ret;
}
int
machine_ps2_model_70_type3_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m70_type3/70-a_even.bin",
"roms/machines/ibmps2_m70_type3/70-a_odd.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xf9ff;
ps2_mca_board_model_70_type34_init(0, 4);
return ret;
}
int
machine_ps2_model_80_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m80/15f6637.bin",
"roms/machines/ibmps2_m80/15f6639.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xfdff;
ps2_mca_board_model_80_type2_init();
return ret;
}
int
machine_ps2_model_80_axx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m80/64f4356.bin",
"roms/machines/ibmps2_m80/64f4355.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xfff9;
ps2_mca_board_model_70_type34_init(0, 8);
return ret;
}
int
machine_ps2_model_70_type4_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m70_type4/64F3126.BIN",
"roms/machines/ibmps2_m70_type4/64F3125.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xf9ff;
ps2_mca_board_model_70_type34_init(1, 4);
return ret;
}
``` | /content/code_sandbox/src/machine/m_ps2_mca.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 12,821 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Virtual ISO CD-ROM image back-end.
*
*
*
* Authors: RichardG <richardg867@gmail.com>
*
*/
#ifndef _LARGEFILE_SOURCE
# define _LARGEFILE_SOURCE
#endif
#ifndef _LARGEFILE64_SOURCE
# define _LARGEFILE64_SOURCE
#endif
#define __STDC_FORMAT_MACROS
#include <ctype.h>
#include <inttypes.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h>
#include <time.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/bswap.h>
#include <86box/cdrom_image_backend.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/plat_dir.h>
#include <86box/version.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#ifndef S_ISDIR
# define S_ISDIR(m) (((m) &S_IFMT) == S_IFDIR)
#endif
#ifdef _WIN32
# define stat _stat64
typedef struct __stat64 stat_t;
#else
typedef struct stat stat_t;
#endif
#define VISO_SKIP(p, n) \
{ \
memset((p), 0x00, (n)); \
(p) += (n); \
}
#define VISO_TIME_VALID(t) ((t) > 0)
/* ISO 9660 defines "both endian" data formats, which
are stored as little endian followed by big endian. */
#define VISO_LBE_16(p, x) \
{ \
*((uint16_t *) (p)) = cpu_to_le16((x)); \
(p) += 2; \
*((uint16_t *) (p)) = cpu_to_be16((x)); \
(p) += 2; \
}
#define VISO_LBE_32(p, x) \
{ \
*((uint32_t *) (p)) = cpu_to_le32((x)); \
(p) += 4; \
*((uint32_t *) (p)) = cpu_to_be32((x)); \
(p) += 4; \
}
#define VISO_SECTOR_SIZE COOKED_SECTOR_SIZE
#define VISO_OPEN_FILES 32
enum {
VISO_CHARSET_D = 0,
VISO_CHARSET_A,
VISO_CHARSET_FN,
VISO_CHARSET_ANY
};
enum {
VISO_DIR_CURRENT = 0,
VISO_DIR_CURRENT_ROOT,
VISO_DIR_PARENT,
VISO_DIR_REGULAR,
VISO_DIR_JOLIET
};
enum {
VISO_FORMAT_ISO = 1, /* ISO 9660 (High Sierra if not set) */
VISO_FORMAT_JOLIET = 2, /* Joliet extensions (Microsoft) */
VISO_FORMAT_RR = 4 /* Rock Ridge extensions (*nix) */
};
typedef struct _viso_entry_ {
union { /* save some memory */
uint64_t pt_offsets[4];
FILE *file;
};
union {
char name_short[13];
uint64_t dr_offsets[2];
uint64_t data_offset;
};
uint16_t pt_idx;
stat_t stats;
struct _viso_entry_ *parent, *next, *next_dir, *first_child;
char *basename, path[];
} viso_entry_t;
typedef struct {
uint64_t vol_size_offsets[2];
uint64_t pt_meta_offsets[2];
int format;
uint8_t use_version_suffix : 1;
size_t metadata_sectors, all_sectors, entry_map_size, sector_size, file_fifo_pos;
uint8_t *metadata;
track_file_t tf;
viso_entry_t *root_dir;
viso_entry_t **entry_map;
viso_entry_t *file_fifo[VISO_OPEN_FILES];
} viso_t;
static const char rr_eid[] = "RRIP_1991A"; /* identifiers used in ER field for Rock Ridge */
static const char rr_edesc[] = "THE ROCK RIDGE INTERCHANGE PROTOCOL PROVIDES SUPPORT FOR POSIX FILE SYSTEM SEMANTICS.";
static int8_t tz_offset = 0;
#ifdef ENABLE_CDROM_IMAGE_VISO_LOG
int cdrom_image_viso_do_log = ENABLE_CDROM_IMAGE_VISO_LOG;
void
cdrom_image_viso_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_image_viso_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_image_viso_log(fmt, ...)
#endif
static size_t
viso_pread(void *ptr, uint64_t offset, size_t size, size_t count, FILE *fp)
{
uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
if (fseeko64(fp, offset, SEEK_SET) != -1)
ret = fread(ptr, size, count, fp);
fseeko64(fp, cur_pos, SEEK_SET);
return ret;
}
static size_t
viso_pwrite(const void *ptr, uint64_t offset, size_t size, size_t count, FILE *fp)
{
uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
if (fseeko64(fp, offset, SEEK_SET) != -1)
ret = fwrite(ptr, size, count, fp);
fseeko64(fp, cur_pos, SEEK_SET);
return ret;
}
static size_t
viso_convert_utf8(wchar_t *dest, const char *src, ssize_t buf_size)
{
uint32_t c;
wchar_t *p = dest;
size_t next;
while (buf_size-- > 0) {
/* Interpret source codepoint. */
c = *src;
if (!c) {
/* Terminator. */
*p = 0;
break;
} else if (c & 0x80) {
/* Convert UTF-8 sequence into a codepoint. */
next = 0;
while (c & 0x40) {
next++;
c <<= 1;
}
c = *src++ & (0x3f >> next);
while ((next-- > 0) && ((*src & 0xc0) == 0x80))
c = (c << 6) | (*src++ & 0x3f);
/* Convert codepoints >= U+10000 to UTF-16 surrogate pairs.
This has to be done here because wchar_t on some platforms
(Windows) is not wide enough to store such high codepoints. */
if (c >= 0x10000) {
if ((c <= 0x10ffff) && (buf_size-- > 0)) {
/* Encode surrogate pair. */
c -= 0x10000;
*p++ = 0xd800 | (c >> 10);
c = 0xdc00 | (c & 0x3ff);
} else {
/* Codepoint overflow or no room for a pair. */
c = '?';
}
}
} else {
/* Pass through sub-UTF-8 codepoints. */
src++;
}
/* Write destination codepoint. */
*p++ = c;
}
return p - dest;
}
#define VISO_WRITE_STR_FUNC(func, dst_type, src_type, converter, bounds_chk) \
static void \
func(dst_type *dest, const src_type *src, ssize_t buf_size, int charset) \
{ \
src_type c; \
while (buf_size-- > 0) { \
/* Interpret source codepoint. */ \
c = *src++; \
switch (c) { \
case 0x00: \
/* Terminator, apply space padding. */ \
while (buf_size-- >= 0) \
*dest++ = converter(' '); \
return; \
\
case 'A' ... 'Z': \
case '0' ... '9': \
case '_': \
/* Valid on all sets. */ \
break; \
\
case 'a' ... 'z': \
/* Convert to uppercase on D and A. */ \
if (charset <= VISO_CHARSET_A) \
c -= 'a' - 'A'; \
break; \
\
case '!': \
case '#': \
case '$': \
case '%': \
case '&': \
case '\'': \
case '(': \
case ')': \
case '-': \
case '@': \
case '^': \
case '`': \
case '{': \
case '}': \
case '~': \
/* Valid on all sets (non-complying DOS characters). */ \
break; \
\
case ' ': \
case '"': \
case '+': \
case ',': \
case '.': \
case '<': \
case '=': \
case '>': \
/* Valid for A and filenames but not for D. */ \
if (charset < VISO_CHARSET_A) \
c = '_'; \
break; \
\
case '*': \
case '/': \
case ':': \
case ';': \
case '?': \
/* Valid for A but not for filenames or D. */ \
if ((charset < VISO_CHARSET_A) || (charset == VISO_CHARSET_FN)) \
c = '_'; \
break; \
\
case 0x01 ... 0x1f: \
case '\\': \
/* Not valid for D, A or filenames. */ \
if (charset <= VISO_CHARSET_FN) \
c = '_'; \
break; \
\
default: \
/* Not valid for D or A, but valid for filenames. */ \
if ((charset < VISO_CHARSET_FN) || (bounds_chk)) \
c = '_'; \
break; \
} \
\
/* Write destination codepoint with conversion function applied. */ \
*dest++ = converter(c); \
} \
}
VISO_WRITE_STR_FUNC(viso_write_string, uint8_t, char, , 0)
VISO_WRITE_STR_FUNC(viso_write_wstring, uint16_t, wchar_t, cpu_to_be16, c > 0xffff)
static int
viso_fill_fn_short(char *data, const viso_entry_t *entry, viso_entry_t **entries)
{
/* Get name and extension length. */
const char *ext_pos = strrchr(entry->basename, '.');
int name_len;
int ext_len;
if (ext_pos) {
name_len = ext_pos - entry->basename;
ext_len = strlen(ext_pos);
} else {
name_len = strlen(entry->basename);
ext_len = 0;
}
/* Copy name. */
int name_copy_len = MIN(8, name_len);
viso_write_string((uint8_t *) data, entry->basename, name_copy_len, VISO_CHARSET_D);
data[name_copy_len] = '\0';
/* Copy extension to temporary buffer. */
char ext[5] = { 0 };
int force_tail = (name_len > 8) || (ext_len == 1);
if (ext_len > 1) {
ext[0] = '.';
if (ext_len > 4) {
ext_len = 4;
force_tail = 1;
}
viso_write_string((uint8_t *) &ext[1], &ext_pos[1], ext_len - 1, VISO_CHARSET_D);
}
/* Check if this filename is unique, and add a tail if required, while also adding the extension. */
char tail[16];
for (int i = force_tail; i <= 999999; i++) {
/* Add tail to the filename if this is not the first run. */
int tail_len = -1;
if (i) {
tail_len = sprintf(tail, "~%d", i);
strcpy(&data[MIN(name_copy_len, 8 - tail_len)], tail);
}
/* Add extension to the filename if present. */
if (ext[0])
strcat(data, ext);
/* Go through files in this directory to make sure this filename is unique. */
for (size_t j = 0; entries[j] != entry; j++) {
/* Flag and stop if this filename was seen. */
if (!strcmp(data, entries[j]->name_short)) {
tail_len = 0;
break;
}
}
/* Stop if this is an unique name. */
if (tail_len)
return 0;
}
return 1;
}
static size_t
viso_fill_fn_rr(uint8_t *data, const viso_entry_t *entry, size_t max_len)
{
/* Trim filename to max_len if needed. */
size_t len = strlen(entry->basename);
if (len > max_len) {
viso_write_string(data, entry->basename, max_len, VISO_CHARSET_FN);
/* Relocate extension if the original name exceeds the maximum length. */
if (!S_ISDIR(entry->stats.st_mode)) { /* do this on files only */
const char *ext = strrchr(entry->basename, '.');
if (ext > entry->basename) {
len = strlen(ext);
if (len >= max_len)
len = max_len - 1; /* don't create a dotfile where there isn't one */
viso_write_string(data + (max_len - len), ext, len, VISO_CHARSET_FN);
}
}
return max_len;
} else {
viso_write_string(data, entry->basename, len, VISO_CHARSET_FN);
return len;
}
}
static size_t
viso_fill_fn_joliet(uint8_t *data, const viso_entry_t *entry, size_t max_len) /* note: receives and returns byte sizes */
{
/* Decode filename as UTF-8. */
size_t len = strlen(entry->basename);
wchar_t utf8dec[len + 1];
len = viso_convert_utf8(utf8dec, entry->basename, len + 1);
/* Trim decoded filename to max_len if needed. */
max_len /= 2;
if (len > max_len) {
viso_write_wstring((uint16_t *) data, utf8dec, max_len, VISO_CHARSET_FN);
/* Relocate extension if the original name exceeds the maximum length. */
if (!S_ISDIR(entry->stats.st_mode)) { /* do this on files only */
const wchar_t *ext = wcsrchr(utf8dec, L'.');
if (ext > utf8dec) {
len = wcslen(ext);
if (len > max_len)
len = max_len;
else if ((len < max_len) && ((((uint16_t *) data)[max_len - len] & be16_to_cpu(0xfc00)) == be16_to_cpu(0xdc00)))
max_len--; /* don't break an UTF-16 pair */
viso_write_wstring(((uint16_t *) data) + (max_len - len), ext, len, VISO_CHARSET_FN);
}
}
return max_len * 2;
} else {
viso_write_wstring((uint16_t *) data, utf8dec, len, VISO_CHARSET_FN);
return len * 2;
}
}
static int
viso_fill_time(uint8_t *data, time_t time, int format, int longform)
{
uint8_t *p = data;
struct tm *time_s = localtime(&time);
if (!time_s) {
/* localtime will return NULL if the time_t is negative (Windows)
or way too far into 64-bit space (Linux). Fall back to epoch. */
time_t epoch = 0;
time_s = localtime(&epoch);
if (UNLIKELY(!time_s))
fatal("VISO: localtime(0) = NULL\n");
/* Force year clamping if the timestamp is known to be outside the supported ranges. */
if (time < (longform ? -62135596800LL : -2208988800LL)) /* 0001-01-01 00:00:00 : 1900-01-01 00:00:00 */
time_s->tm_year = -1901;
else if (time > (longform ? 253402300799LL : 5869583999LL)) /* 9999-12-31 23:59:59 : 2155-12-31 23:59:59 */
time_s->tm_year = 8100;
}
/* Clamp year to the supported ranges, and assume the
OS returns valid numbers in the other struct fields. */
if (time_s->tm_year < (longform ? -1900 : 0)) {
time_s->tm_year = longform ? -1900 : 0;
time_s->tm_mon = time_s->tm_hour = time_s->tm_min = time_s->tm_sec = 0;
time_s->tm_mday = 1;
} else if (time_s->tm_year > (longform ? 8099 : 255)) {
time_s->tm_year = longform ? 8099 : 255;
time_s->tm_mon = 11;
time_s->tm_mday = 31;
time_s->tm_hour = 23;
time_s->tm_min = time_s->tm_sec = 59;
}
/* Convert timestamp. */
if (longform) {
p += sprintf((char *) p, "%04u%02u%02u%02u%02u%02u00",
1900 + time_s->tm_year, 1 + time_s->tm_mon, time_s->tm_mday,
time_s->tm_hour, time_s->tm_min, time_s->tm_sec);
} else {
*p++ = time_s->tm_year; /* year since 1900 */
*p++ = 1 + time_s->tm_mon; /* month */
*p++ = time_s->tm_mday; /* day */
*p++ = time_s->tm_hour; /* hour */
*p++ = time_s->tm_min; /* minute */
*p++ = time_s->tm_sec; /* second */
}
if (format & VISO_FORMAT_ISO)
*p++ = tz_offset; /* timezone (ISO only) */
return p - data;
}
static int
viso_fill_dir_record(uint8_t *data, viso_entry_t *entry, viso_t *viso, int type)
{
uint8_t *p = data;
uint8_t *q;
uint8_t *r;
*p++ = 0; /* size (filled in later) */
*p++ = 0; /* extended attribute length */
VISO_SKIP(p, 8); /* sector offset */
VISO_LBE_32(p, entry->stats.st_size); /* size (filled in later if this is a directory) */
p += viso_fill_time(p, entry->stats.st_mtime, viso->format, 0); /* time */
*p++ = S_ISDIR(entry->stats.st_mode) ? 0x02 : 0x00; /* flags */
VISO_SKIP(p, 2 + !(viso->format & VISO_FORMAT_ISO)); /* file unit size (reserved on HSF), interleave gap size (HSF/ISO) and skip factor (HSF only) */
VISO_LBE_16(p, 1); /* volume sequence number */
switch (type) {
case VISO_DIR_CURRENT:
case VISO_DIR_CURRENT_ROOT:
case VISO_DIR_PARENT:
*p++ = 1; /* file ID length */
*p++ = (type == VISO_DIR_PARENT) ? 1 : 0; /* magic value corresponding to . or .. */
/* Fill Rock Ridge Extension Record for the root directory's . entry. */
if ((type == VISO_DIR_CURRENT_ROOT) && (viso->format & VISO_FORMAT_RR)) {
*p++ = 'E';
*p++ = 'R';
*p++ = 8 + (sizeof(rr_eid) - 1) + (sizeof(rr_edesc) - 1); /* length */
*p++ = 1; /* version */
*p++ = sizeof(rr_eid) - 1; /* ID length */
*p++ = sizeof(rr_edesc) - 1; /* description length */
*p++ = 0; /* source length (source is recommended but won't fit here) */
*p++ = 1; /* extension version */
memcpy(p, rr_eid, sizeof(rr_eid) - 1); /* ID */
p += sizeof(rr_eid) - 1;
memcpy(p, rr_edesc, sizeof(rr_edesc) - 1); /* description */
p += sizeof(rr_edesc) - 1;
goto pad_susp;
}
break;
case VISO_DIR_REGULAR:
q = p++; /* save file ID length location for later */
*q = strlen(entry->name_short);
memcpy(p, entry->name_short, *q); /* file ID */
p += *q;
if (viso->use_version_suffix && !S_ISDIR(entry->stats.st_mode)) {
*p++ = ';'; /* version suffix for files (ISO only, except for Windows NT SETUPLDR.BIN El Torito hack) */
*p++ = '1';
*q += 2;
}
if (!(*q & 1)) /* padding for even file ID lengths */
*p++ = 0;
/* Fill Rock Ridge data. */
if (viso->format & VISO_FORMAT_RR) {
*p++ = 'R'; /* RR = present Rock Ridge entries (only documented by RRIP revision 1.09!) */
*p++ = 'R';
*p++ = 5; /* length */
*p++ = 1; /* version */
q = p++; /* save Rock Ridge flags location for later */
#ifndef _WIN32 /* attributes reported by MinGW don't really make sense because it's Windows */
*q |= 0x01; /* PX = POSIX attributes */
*p++ = 'P';
*p++ = 'X';
*p++ = 36; /* length */
*p++ = 1; /* version */
VISO_LBE_32(p, entry->stats.st_mode); /* mode */
VISO_LBE_32(p, entry->stats.st_nlink); /* number of links */
VISO_LBE_32(p, entry->stats.st_uid); /* owner UID */
VISO_LBE_32(p, entry->stats.st_gid); /* owner GID */
# ifndef S_ISCHR
# define S_ISCHR(x) 0
# endif
# ifndef S_ISBLK
# define S_ISBLK(x) 0
# endif
if (S_ISCHR(entry->stats.st_mode) || S_ISBLK(entry->stats.st_mode)) {
*q |= 0x02; /* PN = POSIX device */
*p++ = 'P';
*p++ = 'N';
*p++ = 20; /* length */
*p++ = 1; /* version */
uint64_t dev = entry->stats.st_rdev; /* avoid warning if <= 32 bits */
VISO_LBE_32(p, dev >> 32); /* device number (high 32 bits) */
VISO_LBE_32(p, dev); /* device number (low 32 bits) */
}
#endif
int times =
#ifdef st_birthtime
(VISO_TIME_VALID(entry->stats.st_birthtime) << 0) | /* creation (hack: assume the platform remaps st_birthtime at header level) */
#endif
(VISO_TIME_VALID(entry->stats.st_mtime) << 1) | /* modify */
(VISO_TIME_VALID(entry->stats.st_atime) << 2) | /* access */
(VISO_TIME_VALID(entry->stats.st_ctime) << 3); /* attributes */
if (times) {
*q |= 0x80; /* TF = timestamps */
*p++ = 'T';
*p++ = 'F';
r = p; /* save length location for later */
*p++ = 2; /* length (added to later) */
*p++ = 1; /* version */
*p++ = times; /* flags */
#ifdef st_birthtime
if (times & (1 << 0))
p += viso_fill_time(p, entry->stats.st_birthtime, viso->format, 0); /* creation */
#endif
if (times & (1 << 1))
p += viso_fill_time(p, entry->stats.st_mtime, viso->format, 0); /* modify */
if (times & (1 << 2))
p += viso_fill_time(p, entry->stats.st_atime, viso->format, 0); /* access */
if (times & (1 << 3))
p += viso_fill_time(p, entry->stats.st_ctime, viso->format, 0); /* attributes */
*r += p - r; /* add to length */
}
*q |= 0x08; /* NM = alternate name */
*p++ = 'N';
*p++ = 'M';
r = p; /* save length location for later */
*p++ = 2; /* length (added to later) */
*p++ = 1; /* version */
*p++ = 0; /* flags */
p += viso_fill_fn_rr(p, entry, 254 - (p - data)); /* name */
*r += p - r; /* add to length */
pad_susp:
if ((p - data) & 1) /* padding for odd SUSP section lengths */
*p++ = 0;
}
break;
case VISO_DIR_JOLIET:
q = p++; /* save file ID length location for later */
*q = viso_fill_fn_joliet(p, entry, 254 - (p - data));
p += *q;
if (!(*q & 1)) /* padding for even file ID lengths */
*p++ = 0;
break;
default:
break;
}
if (UNLIKELY((p - data) > 255))
fatal("VISO: Directory record overflow (%" PRIuPTR ") on entry %08" PRIXPTR "\n", (uintptr_t) (p - data), (uintptr_t) entry);
data[0] = p - data; /* length */
return data[0];
}
static int
viso_compare_entries(const void *a, const void *b)
{
return strcmp((*((viso_entry_t **) a))->name_short, (*((viso_entry_t **) b))->name_short);
}
int
viso_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count)
{
track_file_t *tf = (track_file_t *) priv;
viso_t *viso = (viso_t *) tf->priv;
/* Handle reads in a sector by sector basis. */
while (count > 0) {
/* Determine the current sector, offset and remainder. */
size_t sector = seek / viso->sector_size;
size_t sector_offset = seek % viso->sector_size;
size_t sector_remain = MIN(count, viso->sector_size - sector_offset);
/* Handle sector. */
if (sector < viso->metadata_sectors) {
/* Copy metadata. */
memcpy(buffer, viso->metadata + seek, sector_remain);
} else {
size_t read = 0;
/* Get the file entry corresponding to this sector. */
viso_entry_t *entry = viso->entry_map[sector - viso->metadata_sectors];
if (entry) {
/* Open file if it's not already open. */
if (!entry->file) {
/* Close any existing FIFO entry's file. */
viso_entry_t *other_entry = viso->file_fifo[viso->file_fifo_pos];
if (other_entry && other_entry->file) {
cdrom_image_viso_log("VISO: Closing [%s]", other_entry->path);
fclose(other_entry->file);
other_entry->file = NULL;
cdrom_image_viso_log("\n");
}
/* Open file. */
cdrom_image_viso_log("VISO: Opening [%s]", entry->path);
if ((entry->file = fopen(entry->path, "rb"))) {
cdrom_image_viso_log("\n");
/* Add this entry to the FIFO. */
viso->file_fifo[viso->file_fifo_pos++] = entry;
viso->file_fifo_pos &= (sizeof(viso->file_fifo) / sizeof(viso->file_fifo[0])) - 1;
} else {
cdrom_image_viso_log(" => failed\n");
/* Clear any existing FIFO entry. */
viso->file_fifo[viso->file_fifo_pos] = NULL;
}
}
/* Read data. */
if (entry->file && (fseeko64(entry->file, seek - entry->data_offset, SEEK_SET) != -1))
read = fread(buffer, 1, sector_remain, entry->file);
}
/* Fill remainder with 00 bytes if needed. */
if (read < sector_remain)
memset(buffer + read, 0x00, sector_remain - read);
}
/* Move on to the next sector. */
buffer += sector_remain;
seek += sector_remain;
count -= sector_remain;
}
return 1;
}
uint64_t
viso_get_length(void *priv)
{
track_file_t *tf = (track_file_t *) priv;
const viso_t *viso = (viso_t *) tf->priv;
return ((uint64_t) viso->all_sectors) * viso->sector_size;
}
void
viso_close(void *priv)
{
track_file_t *tf = (track_file_t *) priv;
viso_t *viso = (viso_t *) tf->priv;
if (viso == NULL)
return;
cdrom_image_viso_log("VISO: close()\n");
/* De-allocate everything. */
if (tf->fp)
fclose(tf->fp);
#ifndef ENABLE_CDROM_IMAGE_VISO_LOG
remove(nvr_path(viso->tf.fn));
#endif
viso_entry_t *entry = viso->root_dir;
viso_entry_t *next_entry;
while (entry) {
if (entry->file)
fclose(entry->file);
next_entry = entry->next;
free(entry);
entry = next_entry;
}
if (viso->metadata)
free(viso->metadata);
if (viso->entry_map)
free(viso->entry_map);
free(viso);
}
track_file_t *
viso_init(const char *dirname, int *error)
{
cdrom_image_viso_log("VISO: init()\n");
/* Initialize our data structure. */
viso_t *viso = (viso_t *) calloc(1, sizeof(viso_t));
uint8_t *data = NULL;
uint8_t *p;
*error = 1;
if (viso == NULL)
goto end;
viso->sector_size = VISO_SECTOR_SIZE;
viso->format = VISO_FORMAT_ISO | VISO_FORMAT_JOLIET | VISO_FORMAT_RR;
viso->use_version_suffix = (viso->format & VISO_FORMAT_ISO); /* cleared later if required */
/* Prepare temporary data buffers. */
data = calloc(2, viso->sector_size);
if (!data)
goto end;
/* Open temporary file. */
#ifdef ENABLE_CDROM_IMAGE_VISO_LOG
strcpy(viso->tf.fn, "viso-debug.iso");
#else
plat_tempfile(viso->tf.fn, "viso", ".tmp");
#endif
viso->tf.fp = plat_fopen64(nvr_path(viso->tf.fn), "w+b");
if (!viso->tf.fp)
goto end;
/* Set up directory traversal. */
cdrom_image_viso_log("VISO: Traversing directories:\n");
viso_entry_t *entry;
viso_entry_t *last_entry;
viso_entry_t *dir;
viso_entry_t *last_dir;
const viso_entry_t *eltorito_dir = NULL;
const viso_entry_t *eltorito_entry = NULL;
struct dirent *readdir_entry;
int len;
int eltorito_others_present = 0;
size_t dir_path_len;
uint64_t eltorito_offset = 0;
uint8_t eltorito_type = 0;
/* Fill root directory entry. */
dir_path_len = strlen(dirname);
last_entry = dir = last_dir = viso->root_dir = (viso_entry_t *) calloc(1, sizeof(viso_entry_t) + dir_path_len + 1);
if (!dir)
goto end;
strcpy(dir->path, dirname);
if (stat(dirname, &dir->stats) != 0) {
/* Use a blank structure if stat failed. */
memset(&dir->stats, 0x00, sizeof(stat_t));
}
if (!S_ISDIR(dir->stats.st_mode)) /* root is not a directory */
goto end;
dir->parent = dir; /* for the root's path table and .. entries */
cdrom_image_viso_log("[%08X] %s => [root]\n", dir, dir->path);
/* Traverse directories, starting with the root. */
viso_entry_t **dir_entries = NULL;
size_t dir_entries_len = 0;
while (dir) {
/* Open directory for listing. */
DIR *dirp = opendir(dir->path);
/* Iterate through this directory's children to determine the entry array size. */
size_t children_count = 3; /* include terminator, . and .. */
if (dirp) { /* create empty directory if opendir failed */
while ((readdir_entry = readdir(dirp))) {
/* Ignore . and .. pseudo-directories. */
if ((readdir_entry->d_name[0] == '.') && ((readdir_entry->d_name[1] == '\0') || (*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
continue;
children_count++;
}
}
/* Grow array if needed. */
if (children_count > dir_entries_len) {
viso_entry_t **new_dir_entries = (viso_entry_t **) realloc(dir_entries, children_count * sizeof(viso_entry_t *));
if (new_dir_entries) {
dir_entries = new_dir_entries;
dir_entries_len = children_count;
} else {
goto next_dir;
}
}
/* Add . and .. pseudo-directories. */
dir_path_len = strlen(dir->path);
for (children_count = 0; children_count < 2; children_count++) {
entry = dir_entries[children_count] = (viso_entry_t *) calloc(1, sizeof(viso_entry_t) + 1);
if (!entry)
goto next_dir;
entry->parent = dir;
if (!children_count)
dir->first_child = entry;
/* Stat the current directory or parent directory. */
if (stat(children_count ? dir->parent->path : dir->path, &entry->stats) != 0) {
/* Use a blank structure if stat failed. */
memset(&entry->stats, 0x00, sizeof(stat_t));
}
/* Set basename. */
strcpy(entry->name_short, children_count ? ".." : ".");
cdrom_image_viso_log("[%08X] %s => %s\n", entry, dir->path, entry->name_short);
}
/* Iterate through this directory's children again, making the entries. */
if (dirp) {
rewinddir(dirp);
while ((readdir_entry = readdir(dirp))) {
/* Ignore . and .. pseudo-directories. */
if ((readdir_entry->d_name[0] == '.') && ((readdir_entry->d_name[1] == '\0') || (*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
continue;
/* Add and fill entry. */
entry = dir_entries[children_count++] = (viso_entry_t *) calloc(1, sizeof(viso_entry_t) + dir_path_len + strlen(readdir_entry->d_name) + 2);
if (!entry)
break;
entry->parent = dir;
strcpy(entry->path, dir->path);
path_slash(&entry->path[dir_path_len]);
entry->basename = &entry->path[dir_path_len + 1];
strcpy(entry->basename, readdir_entry->d_name);
/* Stat this child. */
if (stat(entry->path, &entry->stats) != 0) {
/* Use a blank structure if stat failed. */
memset(&entry->stats, 0x00, sizeof(stat_t));
}
/* Handle file size and El Torito boot code. */
if (!S_ISDIR(entry->stats.st_mode)) {
/* Clamp file size to 4 GB - 1 byte. */
if (entry->stats.st_size > ((uint32_t) -1))
entry->stats.st_size = (uint32_t) -1;
/* Increase entry map size. */
viso->entry_map_size += entry->stats.st_size / viso->sector_size;
if (entry->stats.st_size % viso->sector_size)
viso->entry_map_size++; /* round up to the next sector */
/* Detect El Torito boot code file and set it accordingly. */
if (dir == eltorito_dir) {
if (!stricmp(readdir_entry->d_name, "Boot-NoEmul.img")) {
eltorito_type = 0x00;
have_eltorito_entry:
if (eltorito_entry)
eltorito_others_present = 1; /* flag that the boot code directory contains other files */
eltorito_entry = entry;
} else if (!stricmp(readdir_entry->d_name, "Boot-1.2M.img")) {
eltorito_type = 0x01;
goto have_eltorito_entry;
} else if (!stricmp(readdir_entry->d_name, "Boot-1.44M.img")) {
eltorito_type = 0x02;
goto have_eltorito_entry;
} else if (!stricmp(readdir_entry->d_name, "Boot-2.88M.img")) {
eltorito_type = 0x03;
goto have_eltorito_entry;
} else if (!stricmp(readdir_entry->d_name, "Boot-HardDisk.img")) {
eltorito_type = 0x04;
goto have_eltorito_entry;
} else {
eltorito_others_present = 1; /* flag that the boot code directory contains other files */
}
} else {
/* Disable version suffixes if this structure appears to contain the Windows NT
El Torito boot code, which is known not to tolerate suffixed file names. */
if (eltorito_dir && /* El Torito directory present? */
(eltorito_type == 0x00) && /* El Torito directory not checked yet, or confirmed to contain non-emulation boot code? */
(dir->parent == viso->root_dir) && /* one subdirectory deep? (I386 for instance) */
!stricmp(readdir_entry->d_name, "SETUPLDR.BIN")) /* SETUPLDR.BIN present? */
viso->use_version_suffix = 0;
}
} else if ((dir == viso->root_dir) && !stricmp(readdir_entry->d_name, "[BOOT]")) {
/* Set this as the directory containing El Torito boot code. */
eltorito_dir = entry;
eltorito_others_present = 0;
}
/* Set short filename. */
if (viso_fill_fn_short(entry->name_short, entry, dir_entries)) {
free(entry);
children_count--;
continue;
}
cdrom_image_viso_log("[%08X] %s => [%-12s] %s\n", entry, dir->path, entry->name_short, entry->basename);
}
} else {
cdrom_image_viso_log("VISO: Failed to enumerate [%s], will be empty\n", dir->path);
}
/* Add terminator. */
dir_entries[children_count] = NULL;
/* Sort directory entries and create the linked list. */
qsort(&dir_entries[2], children_count - 2, sizeof(viso_entry_t *), viso_compare_entries);
for (size_t i = 0; dir_entries[i]; i++) {
/* Add link. */
last_entry->next = dir_entries[i];
last_entry = dir_entries[i];
/* If this is a directory, add it to the traversal list. */
if ((i >= 2) && S_ISDIR(dir_entries[i]->stats.st_mode)) {
last_dir->next_dir = dir_entries[i];
last_dir = dir_entries[i];
}
}
next_dir:
/* Move on to the next directory. */
if (dirp)
closedir(dirp);
dir = dir->next_dir;
}
if (dir_entries)
free(dir_entries);
/* Write 16 blank sectors. */
for (int i = 0; i < 16; i++)
fwrite(data, viso->sector_size, 1, viso->tf.fp);
/* Get current time for the volume descriptors, and calculate
the timezone offset for descriptors and file times to use. */
tzset();
time_t now = time(NULL);
if (viso->format & VISO_FORMAT_ISO) /* timezones are ISO only */
tz_offset = (now - mktime(gmtime(&now))) / (3600 / 4);
/* Get root directory basename for the volume ID. */
const char *basename = path_get_filename(viso->root_dir->path);
if (!basename || (basename[0] == '\0'))
basename = EMU_NAME;
/* Determine whether or not we're working with 2 volume descriptors
(as well as 2 directory trees and 4 path tables) for Joliet. */
int max_vd = (viso->format & VISO_FORMAT_JOLIET) ? 1 : 0;
/* Write volume descriptors. */
for (int i = 0; i <= max_vd; i++) {
/* Fill volume descriptor. */
p = data;
if (!(viso->format & VISO_FORMAT_ISO))
VISO_LBE_32(p, ftello64(viso->tf.fp) / viso->sector_size); /* sector offset (HSF only) */
*p++ = 1 + i; /* type */
memcpy(p, (viso->format & VISO_FORMAT_ISO) ? "CD001" : "CDROM", 5); /* standard ID */
p += 5;
*p++ = 1; /* version */
*p++ = 0; /* unused */
if (i) {
viso_write_wstring((uint16_t *) p, EMU_NAME_W, 16, VISO_CHARSET_A); /* system ID */
p += 32;
wchar_t wtemp[16];
viso_convert_utf8(wtemp, basename, 16);
viso_write_wstring((uint16_t *) p, wtemp, 16, VISO_CHARSET_D); /* volume ID */
p += 32;
} else {
viso_write_string(p, EMU_NAME, 32, VISO_CHARSET_A); /* system ID */
p += 32;
viso_write_string(p, basename, 32, VISO_CHARSET_D); /* volume ID */
p += 32;
}
VISO_SKIP(p, 8); /* unused */
viso->vol_size_offsets[i] = ftello64(viso->tf.fp) + (p - data);
VISO_LBE_32(p, 0); /* volume space size (filled in later) */
if (i) {
*p++ = 0x25; /* escape sequence (indicates our Joliet names are UCS-2 Level 3) */
*p++ = 0x2f;
*p++ = 0x45;
VISO_SKIP(p, 32 - 3); /* unused */
} else {
VISO_SKIP(p, 32); /* unused */
}
VISO_LBE_16(p, 1); /* volume set size */
VISO_LBE_16(p, 1); /* volume sequence number */
VISO_LBE_16(p, viso->sector_size); /* logical block size */
/* Path table metadata is filled in later. */
viso->pt_meta_offsets[i] = ftello64(viso->tf.fp) + (p - data);
VISO_SKIP(p, 24 + (16 * !(viso->format & VISO_FORMAT_ISO))); /* PT size, LE PT offset, optional LE PT offset (three on HSF), BE PT offset, optional BE PT offset (three on HSF) */
viso->root_dir->dr_offsets[i] = ftello64(viso->tf.fp) + (p - data);
p += viso_fill_dir_record(p, viso->root_dir, viso, VISO_DIR_CURRENT); /* root directory */
int copyright_abstract_len = (viso->format & VISO_FORMAT_ISO) ? 37 : 32;
if (i) {
viso_write_wstring((uint16_t *) p, L"", 64, VISO_CHARSET_D); /* volume set ID */
p += 128;
viso_write_wstring((uint16_t *) p, L"", 64, VISO_CHARSET_A); /* publisher ID */
p += 128;
viso_write_wstring((uint16_t *) p, L"", 64, VISO_CHARSET_A); /* data preparer ID */
p += 128;
viso_write_wstring((uint16_t *) p, EMU_NAME_W L" " EMU_VERSION_W L" VIRTUAL ISO", 64, VISO_CHARSET_A); /* application ID */
p += 128;
viso_write_wstring((uint16_t *) p, L"", copyright_abstract_len >> 1, VISO_CHARSET_D); /* copyright file ID */
p += copyright_abstract_len;
viso_write_wstring((uint16_t *) p, L"", copyright_abstract_len >> 1, VISO_CHARSET_D); /* abstract file ID */
p += copyright_abstract_len;
if (viso->format & VISO_FORMAT_ISO) {
viso_write_wstring((uint16_t *) p, L"", 18, VISO_CHARSET_D); /* bibliography file ID (ISO only) */
p += 37;
}
} else {
viso_write_string(p, "", 128, VISO_CHARSET_D); /* volume set ID */
p += 128;
viso_write_string(p, "", 128, VISO_CHARSET_A); /* publisher ID */
p += 128;
viso_write_string(p, "", 128, VISO_CHARSET_A); /* data preparer ID */
p += 128;
viso_write_string(p, EMU_NAME " " EMU_VERSION " VIRTUAL ISO", 128, VISO_CHARSET_A); /* application ID */
p += 128;
viso_write_string(p, "", copyright_abstract_len, VISO_CHARSET_D); /* copyright file ID */
p += copyright_abstract_len;
viso_write_string(p, "", copyright_abstract_len, VISO_CHARSET_D); /* abstract file ID */
p += copyright_abstract_len;
if (viso->format & VISO_FORMAT_ISO) {
viso_write_string(p, "", 37, VISO_CHARSET_D); /* bibliography file ID (ISO only) */
p += 37;
}
}
len = viso_fill_time(p, now, viso->format, 1); /* volume created */
memcpy(p + len, p, len); /* volume modified */
p += len * 2;
VISO_SKIP(p, len * 2); /* volume expires/effective */
*p++ = 1; /* file structure version */
*p++ = 0; /* unused */
/* Blank the rest of the working sector. */
memset(p, 0x00, viso->sector_size - (p - data));
/* Write volume descriptor. */
fwrite(data, viso->sector_size, 1, viso->tf.fp);
/* Write El Torito boot descriptor. This is an awkward spot for
that, but the spec requires it to be the second descriptor. */
if (!i && eltorito_entry) {
cdrom_image_viso_log("VISO: Writing El Torito boot descriptor for entry [%08X]\n", eltorito_entry);
p = data;
if (!(viso->format & VISO_FORMAT_ISO))
VISO_LBE_32(p, ftello64(viso->tf.fp) / viso->sector_size); /* sector offset (HSF only) */
*p++ = 0; /* type */
memcpy(p, (viso->format & VISO_FORMAT_ISO) ? "CD001" : "CDROM", 5); /* standard ID */
p += 5;
*p++ = 1; /* version */
memcpy(p, "EL TORITO SPECIFICATION", 24); /* identifier */
p += 24;
VISO_SKIP(p, 40);
/* Save the boot catalog pointer's offset for later. */
eltorito_offset = ftello64(viso->tf.fp) + (p - data);
/* Blank the rest of the working sector. */
memset(p, 0x00, viso->sector_size - (p - data));
/* Write boot descriptor. */
fwrite(data, viso->sector_size, 1, viso->tf.fp);
}
}
/* Fill terminator. */
p = data;
if (!(viso->format & VISO_FORMAT_ISO))
VISO_LBE_32(p, ftello64(viso->tf.fp) / viso->sector_size); /* sector offset (HSF only) */
*p++ = 0xff; /* type */
memcpy(p, (viso->format & VISO_FORMAT_ISO) ? "CD001" : "CDROM", 5); /* standard ID */
p += 5;
*p++ = 1; /* version */
/* Blank the rest of the working sector. */
memset(p, 0x00, viso->sector_size - (p - data));
/* Write terminator. */
fwrite(data, viso->sector_size, 1, viso->tf.fp);
/* We start seeing a pattern of padding to even sectors here.
mkisofs does this, presumably for a very good reason... */
int write = ftello64(viso->tf.fp) % (viso->sector_size * 2);
if (write) {
write = (viso->sector_size * 2) - write;
memset(data, 0x00, write);
fwrite(data, write, 1, viso->tf.fp);
}
/* Handle El Torito boot catalog. */
if (eltorito_entry) {
/* Write a pointer to this boot catalog to the boot descriptor. */
*((uint32_t *) data) = cpu_to_le32(ftello64(viso->tf.fp) / viso->sector_size);
viso_pwrite(data, eltorito_offset, 4, 1, viso->tf.fp);
/* Fill boot catalog validation entry. */
p = data;
*p++ = 0x01; /* header ID */
*p++ = 0x00; /* platform */
*p++ = 0x00; /* reserved */
*p++ = 0x00;
VISO_SKIP(p, 24);
strncpy((char *) (p - 24), EMU_NAME, 24); /* ID string */
*p++ = 0x00; /* checksum */
*p++ = 0x00;
*p++ = 0x55; /* key bytes */
*p++ = 0xaa;
/* Calculate checksum. */
uint16_t eltorito_checksum = 0;
for (int i = 0; i < (p - data); i += 2)
eltorito_checksum -= le16_to_cpu(*((uint16_t *) &data[i]));
*((uint16_t *) &data[28]) = cpu_to_le16(eltorito_checksum);
/* Now fill the default boot entry. */
*p++ = 0x88; /* bootable flag */
*p++ = eltorito_type; /* boot media type */
*p++ = 0x00; /* load segment */
*p++ = 0x00;
*p++ = 0x00; /* system type (is this even relevant?) */
*p++ = 0x00; /* reserved */
/* Save offsets to the boot catalog entry's offset and size fields for later. */
eltorito_offset = ftello64(viso->tf.fp) + (p - data);
/* Blank the rest of the working sector. This includes the sector count,
ISO sector offset and 20-byte selection criteria fields at the end. */
memset(p, 0x00, viso->sector_size - (p - data));
/* Write boot catalog. */
fwrite(data, viso->sector_size, 1, viso->tf.fp);
/* Pad to the next even sector. */
write = ftello64(viso->tf.fp) % (viso->sector_size * 2);
if (write) {
write = (viso->sector_size * 2) - write;
memset(data, 0x00, write);
fwrite(data, write, 1, viso->tf.fp);
}
/* Flag that we shouldn't hide the boot code directory if it contains other files. */
if (eltorito_others_present)
eltorito_dir = NULL;
}
/* Write each path table. */
for (int i = 0; i <= ((max_vd << 1) | 1); i++) {
cdrom_image_viso_log("VISO: Generating path table #%d:\n", i);
/* Save this path table's start offset. */
uint64_t pt_start = ftello64(viso->tf.fp);
/* Write this table's sector offset to the corresponding volume descriptor. */
uint32_t pt_temp = pt_start / viso->sector_size;
*((uint32_t *) data) = (i & 1) ? cpu_to_be32(pt_temp) : cpu_to_le32(pt_temp);
viso_pwrite(data, viso->pt_meta_offsets[i >> 1] + 8 + (8 * (i & 1)), 4, 1, viso->tf.fp);
/* Go through directories. */
dir = viso->root_dir;
uint16_t pt_idx = 1;
while (dir) {
/* Ignore . and .. pseudo-directories, and hide the El Torito
boot code directory if no other files are present in it. */
if ((dir->name_short[0] == '.' && (dir->name_short[1] == '\0' || (dir->name_short[1] == '.' && dir->name_short[2] == '\0'))) || (dir == eltorito_dir)) {
dir = dir->next_dir;
continue;
}
cdrom_image_viso_log("[%08X] %s => %s\n", dir, dir->path, ((i & 2) || (dir == viso->root_dir)) ? dir->basename : dir->name_short);
/* Save this directory's path table index and offset. */
dir->pt_idx = pt_idx;
dir->pt_offsets[i] = ftello64(viso->tf.fp);
/* Fill path table entry. */
p = data;
if (!(viso->format & VISO_FORMAT_ISO)) {
*((uint32_t *) p) = 0; /* extent location (filled in later) */
p += 4;
*p++ = 0; /* extended attribute length */
p++; /* skip ID length for now */
} else {
p++; /* skip ID length for now */
*p++ = 0; /* extended attribute length */
dir->pt_offsets[i] += p - data;
*((uint32_t *) p) = 0; /* extent location (filled in later) */
p += 4;
}
*((uint16_t *) p) = (i & 1) ? cpu_to_be16(dir->parent->pt_idx) : cpu_to_le16(dir->parent->pt_idx); /* parent directory number */
p += 2;
pt_temp = 5 * !(viso->format & VISO_FORMAT_ISO); /* directory ID length at offset 0 for ISO, 5 for HSF */
if (dir == viso->root_dir) { /* directory ID length then ID for root... */
data[pt_temp] = 1;
*p = 0x00;
} else if (i & 2) { /* ...or Joliet... */
data[pt_temp] = viso_fill_fn_joliet(p, dir, 255);
} else { /* ...or short name */
data[pt_temp] = strlen(dir->name_short);
memcpy(p, dir->name_short, data[pt_temp]);
}
p += data[pt_temp];
if ((p - data) & 1) /* padding for odd directory ID lengths */
*p++ = 0x00;
/* Write path table entry. */
fwrite(data, p - data, 1, viso->tf.fp);
/* Increment path table index and stop if it overflows. */
if (++pt_idx == 0)
break;
/* Move on to the next directory. */
dir = dir->next_dir;
}
/* Write this table's size to the corresponding volume descriptor. */
pt_temp = ftello64(viso->tf.fp) - pt_start;
p = data;
VISO_LBE_32(p, pt_temp);
viso_pwrite(data, viso->pt_meta_offsets[i >> 1], 8, 1, viso->tf.fp);
/* Pad to the next even sector. */
write = ftello64(viso->tf.fp) % (viso->sector_size * 2);
if (write) {
write = (viso->sector_size * 2) - write;
memset(data, 0x00, write);
fwrite(data, write, 1, viso->tf.fp);
}
}
/* Write directory records for each type. */
int dir_type = VISO_DIR_CURRENT_ROOT;
for (int i = 0; i <= max_vd; i++) {
cdrom_image_viso_log("VISO: Generating directory record set #%d:\n", i);
/* Go through directories. */
dir = viso->root_dir;
while (dir) {
/* Hide the El Torito boot code directory if no other files are present in it. */
if (dir == eltorito_dir) {
dir = dir->next_dir;
continue;
}
/* Pad to the next sector if required. */
write = ftello64(viso->tf.fp) % viso->sector_size;
if (write) {
write = viso->sector_size - write;
memset(data, 0x00, write);
fwrite(data, write, 1, viso->tf.fp);
}
/* Save this directory's child record array's start offset. */
uint64_t dir_start = ftello64(viso->tf.fp);
/* Write this directory's child record array's sector offset to its record... */
uint32_t dir_temp = dir_start / viso->sector_size;
p = data;
VISO_LBE_32(p, dir_temp);
viso_pwrite(data, dir->dr_offsets[i] + 2, 8, 1, viso->tf.fp);
/* ...and to its path table entries. */
viso_pwrite(data, dir->pt_offsets[i << 1], 4, 1, viso->tf.fp); /* little endian */
viso_pwrite(data + 4, dir->pt_offsets[(i << 1) | 1], 4, 1, viso->tf.fp); /* big endian */
if (i == max_vd) /* overwrite pt_offsets in the union if we no longer need them */
dir->file = NULL;
/* Go through entries in this directory. */
entry = dir->first_child;
while (entry) {
/* Skip the El Torito boot code entry if present, or hide the
boot code directory if no other files are present in it. */
if ((entry == eltorito_entry) || (entry == eltorito_dir))
goto next_entry;
cdrom_image_viso_log("[%08X] %s => %s\n", entry, dir->path,
((dir_type == VISO_DIR_PARENT) ? ".." : ((dir_type < VISO_DIR_PARENT) ? "." : (i ? entry->basename : entry->name_short))));
/* Fill directory record. */
viso_fill_dir_record(data, entry, viso, dir_type);
/* Entries cannot cross sector boundaries, so pad to the next sector if needed. */
write = viso->sector_size - (ftello64(viso->tf.fp) % viso->sector_size);
if (write < data[0]) {
p = data + (viso->sector_size * 2) - write;
memset(p, 0x00, write);
fwrite(p, write, 1, viso->tf.fp);
}
/* Save this entry's record's offset. This overwrites name_short in the union. */
entry->dr_offsets[i] = ftello64(viso->tf.fp);
/* Write data related to the . and .. pseudo-subdirectories,
while advancing the current directory type. */
if (dir_type < VISO_DIR_PARENT) {
/* Write a self-referential pointer to this entry. */
p = data + 2;
VISO_LBE_32(p, dir_temp);
dir_type = VISO_DIR_PARENT;
} else if (dir_type == VISO_DIR_PARENT) {
/* Copy the parent directory's offset and size. The root directory's
parent size is a special, self-referential case handled later. */
viso_pread(data + 2, dir->parent->dr_offsets[i] + 2, 16, 1, viso->tf.fp);
dir_type = i ? VISO_DIR_JOLIET : VISO_DIR_REGULAR;
}
/* Write entry. */
fwrite(data, data[0], 1, viso->tf.fp);
next_entry:
/* Move on to the next entry, and stop if the end of this directory was reached. */
entry = entry->next;
if (entry && (entry->parent != dir))
break;
}
/* Write this directory's child record array's size to its parent and . records. */
dir_temp = ftello64(viso->tf.fp) - dir_start;
p = data;
VISO_LBE_32(p, dir_temp);
viso_pwrite(data, dir->dr_offsets[i] + 10, 8, 1, viso->tf.fp);
viso_pwrite(data, dir->first_child->dr_offsets[i] + 10, 8, 1, viso->tf.fp);
if (dir->parent == dir) /* write size to .. on root directory as well */
viso_pwrite(data, dir->first_child->next->dr_offsets[i] + 10, 8, 1, viso->tf.fp);
/* Move on to the next directory. */
dir_type = VISO_DIR_CURRENT;
dir = dir->next_dir;
}
/* Pad to the next even sector. */
write = ftello64(viso->tf.fp) % (viso->sector_size * 2);
if (write) {
write = (viso->sector_size * 2) - write;
memset(data, 0x00, write);
fwrite(data, write, 1, viso->tf.fp);
}
}
/* Allocate entry map for sector->file lookups. */
size_t orig_sector_size = viso->sector_size;
while (1) {
cdrom_image_viso_log("VISO: Allocating entry map for %zu %zu-byte sectors\n", viso->entry_map_size, viso->sector_size);
viso->entry_map = (viso_entry_t **) calloc(viso->entry_map_size, sizeof(viso_entry_t *));
if (viso->entry_map) {
/* Successfully allocated. */
break;
} else {
/* Blank data buffer for padding if this is the first run. */
if (orig_sector_size == viso->sector_size)
memset(data, 0x00, orig_sector_size);
/* If we don't have enough memory, double the sector size. */
viso->sector_size *= 2;
if ((viso->sector_size < VISO_SECTOR_SIZE) || (viso->sector_size > (1 << 30))) /* give up if sectors become too large */
goto end;
/* Go through files, recalculating the entry map size. */
size_t orig_entry_map_size = viso->entry_map_size;
viso->entry_map_size = 0;
entry = viso->root_dir;
while (entry) {
if (!S_ISDIR(entry->stats.st_mode)) {
viso->entry_map_size += entry->stats.st_size / viso->sector_size;
if (entry->stats.st_size % viso->sector_size)
viso->entry_map_size++; /* round up to the next sector */
}
entry = entry->next;
}
if (viso->entry_map_size == orig_entry_map_size) /* give up if there was no change in map size */
goto end;
/* Pad metadata to the new size's next sector. */
while (ftello64(viso->tf.fp) % viso->sector_size)
fwrite(data, orig_sector_size, 1, viso->tf.fp);
}
}
/* Start sector counts. */
viso->metadata_sectors = ftello64(viso->tf.fp) / viso->sector_size;
viso->all_sectors = viso->metadata_sectors;
/* Go through files, assigning sectors to them. */
cdrom_image_viso_log("VISO: Assigning sectors to files:\n");
size_t base_factor = viso->sector_size / orig_sector_size;
viso_entry_t *prev_entry = viso->root_dir;
viso_entry_t **entry_map_p = viso->entry_map;
entry = prev_entry->next;
while (entry) {
/* Skip this entry if it corresponds to a directory. */
if (S_ISDIR(entry->stats.st_mode)) {
/* Deallocate directory entries to save some memory. */
prev_entry->next = entry->next;
free(entry);
entry = prev_entry->next;
continue;
}
/* Write this file's base sector offset to its directory
entries, unless this is the El Torito boot code entry,
in which case, write offset and size to the boot entry. */
if (entry == eltorito_entry) {
/* Load the entire file if not emulating, or just the first virtual
sector (which usually contains all the boot code) if emulating. */
if (eltorito_type == 0x00) { /* non-emulation */
uint32_t boot_size = entry->stats.st_size;
if (boot_size % 512) /* round up */
boot_size += 512 - (boot_size % 512);
*((uint16_t *) &data[0]) = cpu_to_le16(boot_size / 512);
} else { /* emulation */
*((uint16_t *) &data[0]) = cpu_to_le16(1);
}
*((uint32_t *) &data[2]) = cpu_to_le32(viso->all_sectors * base_factor);
viso_pwrite(data, eltorito_offset, 6, 1, viso->tf.fp);
} else {
p = data;
VISO_LBE_32(p, viso->all_sectors * base_factor);
for (int i = 0; i <= max_vd; i++)
viso_pwrite(data, entry->dr_offsets[i] + 2, 8, 1, viso->tf.fp);
}
/* Save this file's base offset. This overwrites dr_offsets in the union. */
entry->data_offset = ((uint64_t) viso->all_sectors) * viso->sector_size;
/* Determine how many sectors this file will take. */
size_t size = entry->stats.st_size / viso->sector_size;
if (entry->stats.st_size % viso->sector_size)
size++; /* round up to the next sector */
cdrom_image_viso_log("[%08X] %s => %zu + %zu sectors\n", entry, entry->path, viso->all_sectors, size);
/* Allocate sectors to this file. */
viso->all_sectors += size;
while (size-- > 0)
*entry_map_p++ = entry;
/* Move on to the next entry. */
prev_entry = entry;
entry = entry->next;
}
/* Write final volume size to all volume descriptors. */
p = data;
VISO_LBE_32(p, viso->all_sectors);
for (int i = 0; i < (sizeof(viso->vol_size_offsets) / sizeof(viso->vol_size_offsets[0])); i++)
viso_pwrite(data, viso->vol_size_offsets[i], 8, 1, viso->tf.fp);
/* Metadata processing is finished, read it back to memory. */
cdrom_image_viso_log("VISO: Reading back %zu %zu-byte sectors of metadata\n", viso->metadata_sectors, viso->sector_size);
viso->metadata = (uint8_t *) calloc(viso->metadata_sectors, viso->sector_size);
if (!viso->metadata)
goto end;
fseeko64(viso->tf.fp, 0, SEEK_SET);
size_t metadata_size = viso->metadata_sectors * viso->sector_size;
size_t metadata_remain = metadata_size;
while (metadata_remain > 0)
metadata_remain -= fread(viso->metadata + (metadata_size - metadata_remain), 1, MIN(metadata_remain, viso->sector_size), viso->tf.fp);
/* We no longer need the temporary file; close and delete it. */
fclose(viso->tf.fp);
viso->tf.fp = NULL;
#ifndef ENABLE_CDROM_IMAGE_VISO_LOG
remove(nvr_path(viso->tf.fn));
#endif
/* All good. */
*error = 0;
end:
/* Set the function pointers. */
viso->tf.priv = viso;
if (!*error) {
cdrom_image_viso_log("VISO: Initialized\n");
viso->tf.read = viso_read;
viso->tf.get_length = viso_get_length;
viso->tf.close = viso_close;
return &viso->tf;
} else {
cdrom_image_viso_log("VISO: Initialization failed\n");
if (data)
free(data);
viso_close(&viso->tf);
return NULL;
}
}
``` | /content/code_sandbox/src/cdrom/cdrom_image_viso.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 16,133 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Standard PC/AT implementation.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/nvr.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/machine.h>
void
machine_at_common_init_ex(const machine_t *model, int type)
{
machine_common_init(model);
refresh_at_enable = 1;
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_at);
pic2_init();
dma16_init();
if (!(type & 4))
device_add(&port_6x_device);
type &= 3;
if (type == 1)
device_add(&ibmat_nvr_device);
else if (type == 0)
device_add(&at_nvr_device);
standalone_gameport_type = &gameport_device;
}
void
machine_at_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 0);
}
void
machine_at_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_at_device);
}
static void
machine_at_ibm_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 1);
device_add(&keyboard_at_device);
mem_remap_top(384);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
}
void
machine_at_ps2_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_ps2_device);
}
void
machine_at_common_ide_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&ide_isa_device);
}
void
machine_at_ibm_common_ide_init(const machine_t *model)
{
machine_at_common_init_ex(model, 1);
device_add(&ide_isa_device);
}
void
machine_at_ide_init(const machine_t *model)
{
machine_at_init(model);
device_add(&ide_isa_device);
}
void
machine_at_ps2_ide_init(const machine_t *model)
{
machine_at_ps2_init(model);
device_add(&ide_isa_device);
}
int
machine_at_ibm_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmat/62x0820.u27",
"roms/machines/ibmat/62x0821.u47",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
/* IBM AT machines with custom BIOSes */
int
machine_at_ibmatquadtel_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmatquadtel/BIOS_30MAR90_U27_QUADTEL_ENH_286_BIOS_3.05.01_27256.BIN",
"roms/machines/ibmatquadtel/BIOS_30MAR90_U47_QUADTEL_ENH_286_BIOS_3.05.01_27256.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
int
machine_at_ibmatami_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmatami/BIOS_5170_30APR89_U27_AMI_27256.BIN",
"roms/machines/ibmatami/BIOS_5170_30APR89_U47_AMI_27256.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
int
machine_at_ibmatpx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmatpx/BIOS ROM - PhoenixBIOS A286 - Version 1.01 - Even.bin",
"roms/machines/ibmatpx/BIOS ROM - PhoenixBIOS A286 - Version 1.01 - Odd.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
int
machine_at_ibmxt286_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmxt286/bios_5162_21apr86_u34_78x7460_27256.bin",
"roms/machines/ibmxt286/bios_5162_21apr86_u35_78x7461_27256.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
int
machine_at_siemens_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/siemens/286BIOS.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 1);
device_add(&keyboard_at_siemens_device);
mem_remap_top(384);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_wellamerastar_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/wellamerastar/W_3.031_L.BIN",
"roms/machines/wellamerastar/W_3.031_H.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
#ifdef USE_OPEN_AT
int
machine_at_openat_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/openat/bios.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_init(model);
return ret;
}
#endif /* USE_OPEN_AT */
``` | /content/code_sandbox/src/machine/m_at.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,828 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the IBM PS/1 models 2011, 2121.
*
* Model 2011: The initial model, using a 10MHz 80286.
*
* Model 2121: This is similar to model 2011 but some of the functionality
* has moved to a chip at ports 0xe0 (index)/0xe1 (data). The
* only functions I have identified are enables for the first
* 512K and next 128K of RAM, in bits 0 of registers 0 and 1
* respectively.
*
* Port 0x105 has bit 7 forced high. Without this 128K of
* memory will be missed by the BIOS on cold boots.
*
* The reserved 384K is remapped to the top of extended memory.
* If this is not done then you get an error on startup.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/sio.h>
#include <86box/nvr.h>
#include <86box/gameport.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/keyboard.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_6x.h>
#include <86box/video.h>
#include <86box/machine.h>
#include <86box/sound.h>
#include <86box/plat_unused.h>
typedef struct {
int model;
rom_t mid_rom, high_rom;
uint8_t ps1_91,
ps1_92,
ps1_94,
ps1_102,
ps1_103,
ps1_104,
ps1_105,
ps1_190;
int ps1_e0_addr;
uint8_t ps1_e0_regs[256];
serial_t *uart;
} ps1_t;
static void
recalc_memory(ps1_t *ps)
{
/* Enable first 512K */
mem_set_mem_state(0x00000, 0x80000,
(ps->ps1_e0_regs[0] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
/* Enable 512-640K */
mem_set_mem_state(0x80000, 0x20000,
(ps->ps1_e0_regs[1] & 0x01) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
}
static void
ps1_write(uint16_t port, uint8_t val, void *priv)
{
ps1_t *ps = (ps1_t *) priv;
switch (port) {
case 0x0092:
if (ps->model != 2011) {
if (val & 1) {
softresetx86();
cpu_set_edx();
}
ps->ps1_92 = val & ~1;
} else {
ps->ps1_92 = val;
}
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x0094:
ps->ps1_94 = val;
break;
case 0x00e0:
if (ps->model != 2011) {
ps->ps1_e0_addr = val;
}
break;
case 0x00e1:
if (ps->model != 2011) {
ps->ps1_e0_regs[ps->ps1_e0_addr] = val;
recalc_memory(ps);
}
break;
case 0x0102:
if (!(ps->ps1_94 & 0x80)) {
lpt1_remove();
serial_remove(ps->uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps->uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps->uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps->ps1_102 = val;
}
break;
case 0x0103:
ps->ps1_103 = val;
break;
case 0x0104:
ps->ps1_104 = val;
break;
case 0x0105:
ps->ps1_105 = val;
break;
case 0x0190:
ps->ps1_190 = val;
break;
default:
break;
}
}
static uint8_t
ps1_read(uint16_t port, void *priv)
{
ps1_t *ps = (ps1_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x0091:
ret = ps->ps1_91;
ps->ps1_91 = 0;
break;
case 0x0092:
ret = ps->ps1_92;
break;
case 0x0094:
ret = ps->ps1_94;
break;
case 0x00e1:
if (ps->model != 2011) {
ret = ps->ps1_e0_regs[ps->ps1_e0_addr];
}
break;
case 0x0102:
if (ps->model == 2011)
ret = ps->ps1_102 | 0x08;
else
ret = ps->ps1_102;
break;
case 0x0103:
ret = ps->ps1_103;
break;
case 0x0104:
ret = ps->ps1_104;
break;
case 0x0105:
if (ps->model == 2011)
ret = ps->ps1_105;
else
ret = ps->ps1_105 | 0x80;
break;
case 0x0190:
ret = ps->ps1_190;
break;
default:
break;
}
return ret;
}
static const device_config_t ps1_2011_config[] = {
// clang-format off
{
.name = "bios_language",
.description = "BIOS Language",
.type = CONFIG_BIOS,
.default_string = "english_us",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "English (US)", .internal_name = "english_us", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/FC0000_US.BIN", "" } },
{ .name = "English (UK)", .internal_name = "english_uk", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_UK.BIN", "roms/machines/ibmps1es/FC0000_UK.BIN", "" } },
{ .name = "English (Canada)", .internal_name = "english_ca", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_CA.BIN", "roms/machines/ibmps1es/FC0000_CA.BIN", "" } },
{ .name = "Portuguese", .internal_name = "portuguese", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_PT.BIN", "roms/machines/ibmps1es/FC0000_PT.BIN", "" } },
{ .name = "German", .internal_name = "german", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_DE.BIN", "roms/machines/ibmps1es/FC0000_DE.BIN", "" } },
{ .name = "Swedish", .internal_name = "swedish", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_SE.BIN", "roms/machines/ibmps1es/FC0000_SE.BIN", "" } },
{ .name = "French", .internal_name = "french", .bios_type = BIOS_NORMAL,
.files_no = 2, .local = 0, .size = 262144, .files = { "roms/machines/ibmps1es/F80000_FR.BIN", "roms/machines/ibmps1es/FC0000_FR.BIN", "" } },
{ .name = "Italian", .internal_name = "italian", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 524288, .files = { "roms/machines/ibmps1es/f80000.bin", "" } },
{ .name = "Spanish", .internal_name = "spanish", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 524288, .files = { "roms/machines/ibmps1es/F80000_ES.bin", "" } },
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t ps1_2011_device = {
.name = "PS/1 2011",
.internal_name = "ps/1_2011",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = &ps1_2011_config[0]
};
static void
ps1_setup(int model)
{
ps1_t *ps;
void *priv;
ps = (ps1_t *) malloc(sizeof(ps1_t));
memset(ps, 0x00, sizeof(ps1_t));
ps->model = model;
io_sethandler(0x0091, 1,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
io_sethandler(0x0092, 1,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
io_sethandler(0x0094, 1,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
io_sethandler(0x0102, 4,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
io_sethandler(0x0190, 1,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
ps->uart = device_add_inst(&ns16450_device, 1);
lpt1_remove();
lpt1_init(LPT_MDA_ADDR);
mem_remap_top(384);
device_add(&ps_nvr_device);
if (model == 2011) {
if (!strcmp("english_us", device_get_config_bios("bios_language"))) {
/* US English */
rom_init(&ps->high_rom,
device_get_bios_file(device_context_get_device(), device_get_config_bios("bios_language"), 0),
0xfc0000, 0x40000, 0x3ffff, 0, MEM_MAPPING_EXTERNAL);
} else if ((device_get_bios_file(device_context_get_device(), device_get_config_bios("bios_language"), 1)) == NULL) {
/* Combined ROM. */
rom_init(&ps->high_rom,
device_get_bios_file(device_context_get_device(), device_get_config_bios("bios_language"), 0),
0xf80000, 0x80000, 0x7ffff, 0, MEM_MAPPING_EXTERNAL);
} else {
/* Split ROM. */
rom_init(&ps->mid_rom,
device_get_bios_file(device_context_get_device(), device_get_config_bios("bios_language"), 0),
0xf80000, 0x40000, 0x3ffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ps->high_rom,
device_get_bios_file(device_context_get_device(), device_get_config_bios("bios_language"), 1),
0xfc0000, 0x40000, 0x3ffff, 0, MEM_MAPPING_EXTERNAL);
}
lpt2_remove();
device_add(&ps1snd_device);
device_add(&fdc_at_ps1_device);
/* Enable the builtin HDC. */
if (hdc_current[0] == HDC_INTERNAL) {
priv = device_add(&ps1_hdc_device);
ps1_hdc_inform(priv, &ps->ps1_91);
}
/* Enable the PS/1 VGA controller. */
device_add(&ps1vga_device);
} else if (model == 2121) {
io_sethandler(0x00e0, 2,
ps1_read, NULL, NULL, ps1_write, NULL, NULL, ps);
if (rom_present("roms/machines/ibmps1_2121/F80000.BIN")) {
rom_init(&ps->mid_rom,
"roms/machines/ibmps1_2121/F80000.BIN",
0xf80000, 0x40000, 0x3ffff, 0, MEM_MAPPING_EXTERNAL);
}
rom_init(&ps->high_rom,
"roms/machines/ibmps1_2121/FC0000.BIN",
0xfc0000, 0x40000, 0x3ffff, 0, MEM_MAPPING_EXTERNAL);
/* Initialize the video controller. */
if (gfxcard[0] == VID_INTERNAL)
device_add(&ibm_ps1_2121_device);
device_add(&fdc_at_ps1_2121_device);
device_add(&ide_isa_device);
device_add(&ps1snd_device);
}
}
static void
ps1_common_init(const machine_t *model)
{
machine_common_init(model);
refresh_at_enable = 1;
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_at);
dma16_init();
pic2_init();
device_add(&keyboard_ps2_ps1_device);
device_add(&port_6x_device);
/* Audio uses ports 200h and 202-207h, so only initialize gameport on 201h. */
standalone_gameport_type = &gameport_201_device;
}
int
machine_ps1_m2011_init(const machine_t *model)
{
int ret;
const char* fn;
uint32_t offset;
if (!device_available(model->device)) {
/* No ROMs available. */
return 0;
}
device_context(model->device);
if ((fn = device_get_bios_file(model->device, device_get_config_bios("bios_language"), 1)) == NULL) {
/* Combined ROM or US English. */
fn = device_get_bios_file(model->device, device_get_config_bios("bios_language"), 0);
offset = (!strcmp("english_us", device_get_config_bios("bios_language"))) ? 0x20000 : 0x60000;
} else {
/* Separated ROM. */
offset = 0x20000;
}
if (!fn) {
fn = device_get_bios_file(model->device, "us_english", 0);
offset = 0x20000;
}
ret = bios_load_linear(fn, 0x000e0000, 131072, offset);
device_context_restore();
if (bios_only || !ret) {
return ret;
}
ps1_common_init(model);
device_context(model->device);
ps1_setup(2011);
device_context_restore();
return ret;
}
int
machine_ps1_m2121_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ibmps1_2121/FC0000.BIN",
0x000e0000, 131072, 0x20000);
if (bios_only || !ret)
return ret;
ps1_common_init(model);
ps1_setup(2121);
return ret;
}
``` | /content/code_sandbox/src/machine/m_ps1.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,095 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Schneider EuroPC system.
*
* NOTES: BIOS info (taken from MAME, thanks guys!!)
*
* f000:e107 bios checksum test
* memory test
* f000:e145 irq vector init
* f000:e156
* f000:e169-d774 test of special registers 254/354
* f000:e16c-e817
* f000:e16f
* f000:ec08 test of special registers 800a rtc time
* or date error, rtc corrected
* f000:ef66 0xf
* f000:db3e 0x8..0xc
* f000:d7f8
* f000:db5f
* f000:e172
* f000:ecc5 801a video setup error
* f000:d6c9 copyright output
* f000:e1b7
* f000:e1be DI bits set mean output text!!! (801a)
* f000: 0x8000 output
* 1 rtc error
* 2 rtc time or date error
* 4 checksum error in setup
* 8 rtc status corrected
* 10 video setup error
* 20 video ram bad
* 40 monitor type not recogniced
* 80 mouse port enabled
* 100 joystick port enabled
* f000:e1e2-dc0c CPU speed is 4.77 mhz
* f000:e1e5-f9c0 keyboard processor error
* f000:e1eb-c617 external lpt1 at 0x3bc
* f000:e1ee-e8ee external coms at
*
* Routines:
* f000:c92d output text at bp
* f000:db3e RTC read reg cl
* f000:e8ee piep
* f000:e95e RTC write reg cl
* polls until JIM 0xa is zero,
* output cl at jim 0xa
* write ah hinibble as lownibble into jim 0xa
* write ah lownibble into jim 0xa
* f000:ef66 RTC read reg cl
* polls until jim 0xa is zero,
* output cl at jim 0xa
* read low 4 nibble at jim 0xa
* read low 4 nibble at jim 0xa
* return first nibble<<4|second nibble in ah
* f000:f046 seldom compares ret
* f000:fe87 0 -> ds
*
* Memory:
* 0000:0469 bit 0: b0000 memory available
* bit 1: b8000 memory available
* 0000:046a: 00 jim 250 01 jim 350
*
* WARNING THIS IS A WORK-IN-PROGRESS MODULE. USE AT OWN RISK.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Inspired by the "jim.c" file originally present, but a
* fully re-written module, based on the information from
* Schneider's schematics and technical manuals, and the
* input from people with real EuroPC hardware.
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/nmi.h>
#include <86box/mem.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/mouse.h>
#include <86box/gameport.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/hdc.h>
#include <86box/video.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
#define EUROPC_DEBUG 0 /* current debugging level */
/* M3002 RTC chip registers. */
#define MRTC_SECONDS 0x00 /* BCD, 00-59 */
#define MRTC_MINUTES 0x01 /* BCD, 00-59 */
#define MRTC_HOURS 0x02 /* BCD, 00-23 */
#define MRTC_DAYS 0x03 /* BCD, 01-31 */
#define MRTC_MONTHS 0x04 /* BCD, 01-12 */
#define MRTC_YEARS 0x05 /* BCD, 00-99 (year only) */
#define MRTC_WEEKDAY 0x06 /* BCD, 01-07 */
#define MRTC_WEEKNO 0x07 /* BCD, 01-52 */
#define MRTC_CONF_A 0x08 /* EuroPC config, binary */
#define MRTC_CONF_B 0x09 /* EuroPC config, binary */
#define MRTC_CONF_C 0x0a /* EuroPC config, binary */
#define MRTC_CONF_D 0x0b /* EuroPC config, binary */
#define MRTC_CONF_E 0x0c /* EuroPC config, binary */
#define MRTC_CHECK_LO 0x0d /* Checksum, low byte */
#define MRTC_CHECK_HI 0x0e /* Checksum, high byte */
#define MRTC_CTRLSTAT 0x0f /* RTC control/status, binary */
typedef struct europc_t {
uint16_t jim; /* JIM base address */
uint8_t regs[16]; /* JIM internal regs (8) */
nvr_t nvr; /* NVR */
uint8_t nvr_stat;
uint8_t nvr_addr;
void *mouse;
} europc_t;
static europc_t europc;
#ifdef ENABLE_EUROPC_LOG
int europc_do_log = ENABLE_EUROPC_LOG;
static void
europc_log(const char *fmt, ...)
{
va_list ap;
if (europc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define europc_log(fmt, ...)
#endif
/*
* This is called every second through the NVR/RTC hook.
*
* We fake a 'running' RTC by updating its registers on
* each passing second. Not exactly accurate, but good
* enough.
*
* Note that this code looks nasty because of all the
* BCD to decimal vv going on.
*
* FIXME: should we mark NVR as dirty?
*/
static void
europc_rtc_tick(nvr_t *nvr)
{
uint8_t *regs;
int mon;
int yr;
/* Only if RTC is running.. */
regs = nvr->regs;
if (!(regs[MRTC_CTRLSTAT] & 0x01))
return;
regs[MRTC_SECONDS] = RTC_BCDINC(nvr->regs[MRTC_SECONDS], 1);
if (regs[MRTC_SECONDS] >= RTC_BCD(60)) {
regs[MRTC_SECONDS] = RTC_BCD(0);
regs[MRTC_MINUTES] = RTC_BCDINC(regs[MRTC_MINUTES], 1);
if (regs[MRTC_MINUTES] >= RTC_BCD(60)) {
regs[MRTC_MINUTES] = RTC_BCD(0);
regs[MRTC_HOURS] = RTC_BCDINC(regs[MRTC_HOURS], 1);
if (regs[MRTC_HOURS] >= RTC_BCD(24)) {
regs[MRTC_HOURS] = RTC_BCD(0);
regs[MRTC_DAYS] = RTC_BCDINC(regs[MRTC_DAYS], 1);
mon = RTC_DCB(regs[MRTC_MONTHS]);
yr = RTC_DCB(regs[MRTC_YEARS]) + 1900;
if (RTC_DCB(regs[MRTC_DAYS]) > nvr_get_days(mon, yr)) {
regs[MRTC_DAYS] = RTC_BCD(1);
regs[MRTC_MONTHS] = RTC_BCDINC(regs[MRTC_MONTHS], 1);
if (regs[MRTC_MONTHS] > RTC_BCD(12)) {
regs[MRTC_MONTHS] = RTC_BCD(1);
regs[MRTC_YEARS] = RTC_BCDINC(regs[MRTC_YEARS], 1) & 0xff;
}
}
}
}
}
}
/* Get the current NVR time. */
static void
rtc_time_get(uint8_t *regs, struct tm *tm)
{
/* NVR is in BCD data mode. */
tm->tm_sec = RTC_DCB(regs[MRTC_SECONDS]);
tm->tm_min = RTC_DCB(regs[MRTC_MINUTES]);
tm->tm_hour = RTC_DCB(regs[MRTC_HOURS]);
tm->tm_wday = (RTC_DCB(regs[MRTC_WEEKDAY]) - 1);
tm->tm_mday = RTC_DCB(regs[MRTC_DAYS]);
tm->tm_mon = (RTC_DCB(regs[MRTC_MONTHS]) - 1);
tm->tm_year = RTC_DCB(regs[MRTC_YEARS]);
#if USE_Y2K
tm->tm_year += (RTC_DCB(regs[MRTC_CENTURY]) * 100) - 1900;
#endif
}
/* Set the current NVR time. */
static void
rtc_time_set(uint8_t *regs, struct tm *tm)
{
/* NVR is in BCD data mode. */
regs[MRTC_SECONDS] = RTC_BCD(tm->tm_sec);
regs[MRTC_MINUTES] = RTC_BCD(tm->tm_min);
regs[MRTC_HOURS] = RTC_BCD(tm->tm_hour);
regs[MRTC_WEEKDAY] = RTC_BCD(tm->tm_wday + 1);
regs[MRTC_DAYS] = RTC_BCD(tm->tm_mday);
regs[MRTC_MONTHS] = RTC_BCD(tm->tm_mon + 1);
regs[MRTC_YEARS] = RTC_BCD(tm->tm_year % 100);
#if USE_Y2K
regs[MRTC_CENTURY] = RTC_BCD((tm->tm_year + 1900) / 100);
#endif
}
static void
rtc_start(nvr_t *nvr)
{
struct tm tm;
/* Initialize the internal and chip times. */
if (time_sync & TIME_SYNC_ENABLED) {
/* Use the internal clock's time. */
nvr_time_get(&tm);
rtc_time_set(nvr->regs, &tm);
} else {
/* Set the internal clock from the chip time. */
rtc_time_get(nvr->regs, &tm);
nvr_time_set(&tm);
}
#if 0
/* Start the RTC - BIOS will do this. */
nvr->regs[MRTC_CTRLSTAT] = 0x01;
#endif
}
/* Create a valid checksum for the current NVR data. */
static uint8_t
rtc_checksum(uint8_t *ptr)
{
uint8_t sum;
/* Calculate all bytes with XOR. */
sum = 0x00;
for (uint8_t i = MRTC_CONF_A; i <= MRTC_CONF_E; i++)
sum += ptr[i];
return sum;
}
/* Reset the machine's NVR to a sane state. */
static void
rtc_reset(nvr_t *nvr)
{
/* Initialize the RTC to a known state. */
nvr->regs[MRTC_SECONDS] = RTC_BCD(0); /* seconds */
nvr->regs[MRTC_MINUTES] = RTC_BCD(0); /* minutes */
nvr->regs[MRTC_HOURS] = RTC_BCD(0); /* hours */
nvr->regs[MRTC_DAYS] = RTC_BCD(1); /* days */
nvr->regs[MRTC_MONTHS] = RTC_BCD(1); /* months */
nvr->regs[MRTC_YEARS] = RTC_BCD(80); /* years */
nvr->regs[MRTC_WEEKDAY] = RTC_BCD(1); /* weekday */
nvr->regs[MRTC_WEEKNO] = RTC_BCD(1); /* weekno */
/*
* EuroPC System Configuration:
*
* [A] unknown
*
* [B] 7 1 bootdrive extern
* 0 bootdrive intern
* 6:5 11 invalid hard disk type
* 10 hard disk installed, type 2
* 01 hard disk installed, type 1
* 00 hard disk not installed
* 4:3 11 invalid external drive type
* 10 external drive 720K
* 01 external drive 360K
* 00 external drive disabled
* 2 unknown
* 1:0 11 invalid internal drive type
* 10 internal drive 360K
* 01 internal drive 720K
* 00 internal drive disabled
*
* [C] 7:6 unknown
* 5 monitor detection OFF
* 4 unknown
* 3:2 11 illegal memory size
* 10 512K
* 01 256K
* 00 640K
* 1:0 11 illegal game port
* 10 gameport as mouse port
* 01 gameport as joysticks
* 00 gameport disabled
*
* [D] 7:6 10 9MHz CPU speed
* 01 7MHz CPU speed
* 00 4.77 MHz CPU
* 5 unknown
* 4 external: color, internal: mono
* 3 unknown
* 2 internal video ON
* 1:0 11 mono
* 10 color80
* 01 color40
* 00 special (EGA,VGA etc)
*
* [E] 7:4 unknown
* 3:0 country (00=Deutschland, 0A=ASCII)
*/
nvr->regs[MRTC_CONF_A] = 0x00; /* CONFIG A */
nvr->regs[MRTC_CONF_B] = 0x0A; /* CONFIG B */
nvr->regs[MRTC_CONF_C] = 0x28; /* CONFIG C */
nvr->regs[MRTC_CONF_D] = 0x12; /* CONFIG D */
nvr->regs[MRTC_CONF_E] = 0x0A; /* CONFIG E */
nvr->regs[MRTC_CHECK_LO] = 0x00; /* checksum (LO) */
nvr->regs[MRTC_CHECK_HI] = 0x00; /* checksum (HI) */
nvr->regs[MRTC_CTRLSTAT] = 0x01; /* status/control */
/* Generate a valid checksum. */
nvr->regs[MRTC_CHECK_LO] = rtc_checksum(nvr->regs);
}
/* Execute a JIM control command. */
static void
jim_set(europc_t *sys, uint8_t reg, uint8_t val)
{
switch (reg) {
case 0: /* MISC control (WO) */
// bit0: enable MOUSE
// bit1: enable joystick
break;
case 2: /* AGA control */
if (!(val & 0x80)) {
/* Reset AGA. */
break;
}
switch (val) {
case 0x1f: /* 0001 1111 */
case 0x0b: /* 0000 1011 */
#if 0
europc_jim.mode=AGA_MONO;
#endif
europc_log("EuroPC: AGA Monochrome mode!\n");
break;
case 0x18: /* 0001 1000 */
case 0x1a: /* 0001 1010 */
#if 0
europc_jim.mode=AGA_COLOR;
#endif
break;
case 0x0e: /* 0000 1100 */
/*80 columns? */
europc_log("EuroPC: AGA 80-column mode!\n");
break;
case 0x0d: /* 0000 1011 */
/*40 columns? */
europc_log("EuroPC: AGA 40-column mode!\n");
break;
default:
#if 0
europc_jim.mode=AGA_OFF;
#endif
break;
}
break;
case 4: /* CPU Speed control */
switch (val & 0xc0) {
case 0x00: /* 4.77 MHz */
#if 0
cpu_set_clockscale(0, 1.0/2);
#endif
break;
case 0x40: /* 7.16 MHz */
#if 0
cpu_set_clockscale(0, 3.0/4);
#endif
break;
default: /* 9.54 MHz */
#if 0
cpu_set_clockscale(0, 1);break;
#endif
break;
}
break;
default:
break;
}
sys->regs[reg] = val;
}
/* Write to one of the JIM registers. */
static void
jim_write(uint16_t addr, uint8_t val, void *priv)
{
europc_t *sys = (europc_t *) priv;
uint8_t b;
#if EUROPC_DEBUG > 1
europc_log("EuroPC: jim_wr(%04x, %02x)\n", addr, val);
#endif
switch (addr & 0x000f) {
case 0x00: /* JIM internal registers (WRONLY) */
case 0x01:
case 0x02:
case 0x03:
case 0x04: /* JIM internal registers (R/W) */
case 0x05:
case 0x06:
case 0x07:
jim_set(sys, (addr & 0x07), val);
break;
case 0x0a: /* M3002 RTC INDEX/DATA register */
switch (sys->nvr_stat) {
case 0: /* save index */
sys->nvr_addr = val & 0x0f;
sys->nvr_stat++;
break;
case 1: /* save data HI nibble */
b = sys->nvr.regs[sys->nvr_addr] & 0x0f;
b |= (val << 4);
sys->nvr.regs[sys->nvr_addr] = b;
sys->nvr_stat++;
nvr_dosave++;
break;
case 2: /* save data LO nibble */
b = sys->nvr.regs[sys->nvr_addr] & 0xf0;
b |= (val & 0x0f);
sys->nvr.regs[sys->nvr_addr] = b;
sys->nvr_stat = 0;
nvr_dosave++;
break;
default:
break;
}
break;
default:
europc_log("EuroPC: invalid JIM write %02x, val %02x\n", addr, val);
break;
}
}
/* Read from one of the JIM registers. */
static uint8_t
jim_read(uint16_t addr, void *priv)
{
europc_t *sys = (europc_t *) priv;
uint8_t r = 0xff;
switch (addr & 0x000f) {
case 0x00: /* JIM internal registers (WRONLY) */
case 0x01:
case 0x02:
case 0x03:
r = 0x00;
break;
case 0x04: /* JIM internal registers (R/W) */
case 0x05:
case 0x06:
case 0x07:
r = sys->regs[addr & 0x07];
break;
case 0x0a: /* M3002 RTC INDEX/DATA register */
switch (sys->nvr_stat) {
case 0:
r = 0x00;
break;
case 1: /* read data HI nibble */
r = (sys->nvr.regs[sys->nvr_addr] >> 4);
sys->nvr_stat++;
break;
case 2: /* read data LO nibble */
r = (sys->nvr.regs[sys->nvr_addr] & 0x0f);
sys->nvr_stat = 0;
break;
default:
break;
}
break;
default:
europc_log("EuroPC: invalid JIM read %02x\n", addr);
break;
}
#if EUROPC_DEBUG > 1
europc_log("EuroPC: jim_rd(%04x): %02x\n", addr, r);
#endif
return r;
}
/* Initialize the mainboard 'device' of the machine. */
static void *
europc_boot(UNUSED(const device_t *info))
{
europc_t *sys = &europc;
uint8_t b;
#if EUROPC_DEBUG
europc_log("EuroPC: booting mainboard..\n");
#endif
europc_log("EuroPC: NVR=[ %02x %02x %02x %02x %02x ] %sVALID\n",
sys->nvr.regs[MRTC_CONF_A], sys->nvr.regs[MRTC_CONF_B],
sys->nvr.regs[MRTC_CONF_C], sys->nvr.regs[MRTC_CONF_D],
sys->nvr.regs[MRTC_CONF_E],
(sys->nvr.regs[MRTC_CHECK_LO] != rtc_checksum(sys->nvr.regs)) ? "IN" : "");
/*
* Now that we have initialized the NVR (either from file,
* or by setting it to defaults) we can start overriding it
* with values set by the user.
*/
b = (sys->nvr.regs[MRTC_CONF_D] & ~0x17);
video_reset(gfxcard[0]);
if (video_is_cga())
b |= 0x12; /* external video, CGA80 */
else if (video_is_mda())
b |= 0x03; /* external video, mono */
else
b |= 0x10; /* external video, special */
sys->nvr.regs[MRTC_CONF_D] = b;
/* Update the memory size. */
b = (sys->nvr.regs[MRTC_CONF_C] & 0xf3);
switch (mem_size) {
case 256:
b |= 0x04;
break;
case 512:
b |= 0x08;
break;
case 640:
b |= 0x00;
break;
default:
break;
}
sys->nvr.regs[MRTC_CONF_C] = b;
/* Update CPU speed. */
b = (sys->nvr.regs[MRTC_CONF_D] & 0x3f);
switch (cpu) {
case 0: /* 8088, 4.77 MHz */
b |= 0x00;
break;
case 1: /* 8088, 7.15 MHz */
b |= 0x40;
break;
case 2: /* 8088, 9.56 MHz */
b |= 0x80;
break;
default:
break;
}
sys->nvr.regs[MRTC_CONF_D] = b;
/* Set up game port. */
b = (sys->nvr.regs[MRTC_CONF_C] & 0xfc);
if (mouse_type == MOUSE_TYPE_INTERNAL) {
sys->mouse = device_add(&mouse_logibus_onboard_device);
mouse_bus_set_irq(sys->mouse, 2);
/* Configure the port for (Bus Mouse Compatible) Mouse. */
b |= 0x01;
} else if (joystick_type)
b |= 0x02; /* enable port as joysticks */
sys->nvr.regs[MRTC_CONF_C] = b;
#if 0
/* Set up floppy types. */
sys->nvr.regs[MRTC_CONF_B] = 0x2a;
#endif
/* Validate the NVR checksum and save. */
sys->nvr.regs[MRTC_CHECK_LO] = rtc_checksum(sys->nvr.regs);
nvr_dosave++;
/*
* Allocate the system's I/O handlers.
*
* The first one is for the JIM. Note that although JIM usually
* resides at 0x0250, a special solder jumper on the mainboard
* (JS9) can be used to "move" it to 0x0350, to get it out of
* the way of other cards that need this range.
*/
io_sethandler(sys->jim, 16,
jim_read, NULL, NULL, jim_write, NULL, NULL, sys);
/* Only after JIM has been initialized. */
(void) device_add(&keyboard_xt_device);
/* Enable and set up the FDC. */
(void) device_add(&fdc_xt_device);
/*
* Set up and enable the HD20 disk controller.
*
* We only do this if we have not configured another one.
*/
if (hdc_current[0] == HDC_INTERNAL)
(void) device_add(&xta_hd20_device);
return sys;
}
static void
europc_close(UNUSED(void *priv))
{
nvr_t *nvr = &europc.nvr;
if (nvr->fn != NULL)
free(nvr->fn);
}
static const device_config_t europc_config[] = {
// clang-format off
{
.name = "js9",
.description = "JS9 Jumper (JIM)",
.type = CONFIG_INT,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled (250h)", .value = 0 },
{ .description = "Enabled (350h)", .value = 1 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t europc_device = {
.name = "EuroPC System Board",
.internal_name = "europc",
.flags = 0,
.local = 0,
.init = europc_boot,
.close = europc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = europc_config
};
/*
* This function sets up the Scheider EuroPC machine.
*
* Its task is to allocate a clean machine data block,
* and then simply enable the mainboard "device" which
* allows it to reset (dev init) and configured by the
* user.
*/
int
machine_europc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/europc/50145",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
nmi_init();
/* Clear the machine state. */
memset(&europc, 0x00, sizeof(europc_t));
europc.jim = 0x0250;
/* This is machine specific. */
europc.nvr.size = model->nvrmask + 1;
europc.nvr.irq = -1;
/* Set up any local handlers here. */
europc.nvr.reset = rtc_reset;
europc.nvr.start = rtc_start;
europc.nvr.tick = europc_rtc_tick;
/* Initialize the actual NVR. */
nvr_init(&europc.nvr);
/* Enable and set up the mainboard device. */
device_add(&europc_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_europc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,460 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Toshiba T3100e.
*
* The Toshiba 3100e is a 286-based portable.
*
* To bring up the BIOS setup screen hold down the 'Fn' key
* on booting.
*
* Memory management
* ~~~~~~~~~~~~~~~~~
*
* Motherboard memory is divided into:
* - Conventional memory: Either 512k or 640k
* - Upper memory: Either 512k or 384k, depending on
* amount of conventional memory.
* Upper memory can be used as EMS or XMS.
* - High memory: 0-4Mb, depending on RAM installed.
* The BIOS setup screen allows some or
* all of this to be used as EMS; the
* remainder is XMS.
*
* Additional memory (either EMS or XMS) can also be provided
* by ISA expansion cards.
*
* Under test in PCem, the BIOS will boot with up to 65368Kb
* of memory in total (16Mb less 16k). However it will give
* an error with RAM sizes above 8Mb, if any of the high
* memory is allocated as EMS, because the builtin EMS page
* registers can only access up to 8Mb.
*
* Memory is controlled by writes to I/O port 8084h:
* Bit 7: Always 0 }
* Bit 6: Always 1 } These bits select which motherboard
* Bit 5: Always 0 } function to access.
* Bit 4: Set to treat upper RAM as XMS
* Bit 3: Enable external RAM boards?
* Bit 2: Set for 640k conventional memory, clear for 512k
* Bit 1: Enable RAM beyond 1Mb.
* Bit 0: Enable EMS.
*
* The last value written to this port is saved at 0040:0093h,
* and in CMOS memory at offset 0x37. If the top bit of the
* CMOS byte is set, then high memory is being provided by
* an add-on card rather than the mainboard; accordingly,
* the BIOS will not allow high memory to be used as EMS.
*
* EMS is controlled by 16 page registers:
*
* Page mapped at 0xD000 0xD400 0xD800 0xDC00
* ------------------------------------------------------
* Pages 0x00-0x7F 0x208 0x4208 0x8208 0xc208
* Pages 0x80-0xFF 0x218 0x4218 0x8218 0xc218
* Pages 0x100-0x17F 0x258 0x4258 0x8258 0xc258
* Pages 0x180-0x1FF 0x268 0x4268 0x8268 0xc268
*
* The value written has bit 7 set to enable EMS, reset to
* disable it.
*
* So:
* OUT 0x208, 0x80 will page in the first 16k page at 0xD0000.
* OUT 0x208, 0x00 will page out EMS, leaving nothing at 0xD0000.
* OUT 0x4208, 0x80 will page in the first 16k page at 0xD4000.
* OUT 0x218, 0x80 will page in the 129th 16k page at 0xD0000.
* etc.
*
* To use EMS from DOS, you will need the Toshiba EMS driver
* (TOSHEMM.ZIP). This supports the above system, plus further
* ranges of ports at 0x_2A8, 0x_2B8, 0x_2C8.
*
* Features not implemented:
* > Four video fonts.
* > BIOS-controlled mapping of serial ports to IRQs.
* > Custom keyboard controller. This has a number of extra
* commands in the 0xB0-0xBC range, for such things as turbo
* on/off, and switching the keyboard between AT and PS/2
* modes. Currently I have only implemented command 0xBB,
* so that self-test completes successfully. Commands include:
*
* 0xB0: Turbo on
* 0xB1: Turbo off
* 0xB2: Internal display on?
* 0xB3: Internal display off?
* 0xB5: Get settings byte (bottom bit is color/mono setting)
* 0xB6: Set settings byte
* 0xB7: Behave as 101-key PS/2 keyboard
* 0xB8: Behave as 84-key AT keyboard
* 0xBB: Return a byte, bit 2 is Fn key state, other bits unknown.
*
* The other main I/O port needed to POST is:
* 0x8084: System control.
* Top 3 bits give command, bottom 5 bits give parameters.
* 000 => set serial port IRQ / addresses
* bit 4: IRQ5 serial port base: 1 => 0x338, 0 => 0x3E8
* bits 3, 2, 0 specify serial IRQs for COM1, COM2, COM3:
* 00 0 => 4, 3, 5
* 00 1 => 4, 5, 3
* 01 0 => 3, 4, 5
* 01 1 => 3, 5, 4
* 10 0 => 4, -, 3
* 10 1 => 3, -, 4
* 010 => set memory mappings
* bit 4 set if upper RAM is XMS
* bit 3 enable add-on memory boards beyond 5Mb?
* bit 2 set for 640k sysram, clear for 512k sysram
* bit 1 enable mainboard XMS
* bit 0 enable mainboard EMS
* 100 => set parallel mode / LCD settings
* bit 4 set for bidirectional parallel port
* bit 3 set to disable internal CGA
* bit 2 set for single-pixel LCD font
* bits 0,1 for display font
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/mouse.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/rom.h>
#include "cpu.h"
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/machine.h>
#include <86box/m_at_t3100e.h>
#include <86box/plat_unused.h>
extern uint8_t *ram; /* Physical RAM */
void at_init(void);
/* The T3100e motherboard can (and does) dynamically reassign RAM between
* conventional, XMS and EMS. This translates to monkeying with the mappings.
*/
extern mem_mapping_t base_mapping;
extern mem_mapping_t ram_low_mapping; /* This is to switch conventional RAM
* between 512k and 640k */
extern mem_mapping_t ram_mid_mapping; /* This will not be used */
extern mem_mapping_t ram_high_mapping; /* This is RAM beyond 1Mb if any */
extern uint8_t *ram;
static unsigned t3100e_ems_page_reg[] = {
0x208,
0x4208,
0x8208,
0xc208, /* The first four map the first 2Mb */
/* of RAM into the page frame */
0x218,
0x4218,
0x8218,
0xc218, /* The next four map the next 2Mb */
/* of RAM */
0x258,
0x4258,
0x8258,
0xc258, /* and so on. */
0x268,
0x4268,
0x8268,
0xc268,
};
struct t3100e_ems_regs {
uint8_t page[16];
mem_mapping_t mapping[4];
uint32_t page_exec[4]; /* Physical location of memory pages */
uint32_t upper_base; /* Start of upper RAM */
uint8_t upper_pages; /* Pages of EMS available from upper RAM */
uint8_t upper_is_ems; /* Upper RAM is EMS? */
mem_mapping_t upper_mapping;
uint8_t notify; /* Notification from keyboard controller */
uint8_t turbo; /* 0 for 6MHz, else full speed */
uint8_t mono; /* Emulates PC/AT 'mono' motherboard switch */
/* Bit 0 is 0 for colour, 1 for mono */
} t3100e_ems;
void t3100e_ems_out(uint16_t addr, uint8_t val, void *priv);
#ifdef ENABLE_T3100E_LOG
int t3100e_do_log = ENABLE_T3100E_LOG;
static void
t3100e_log(const char *fmt, ...)
{
va_list ap;
if (t3100e_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define t3100e_log(fmt, ...)
#endif
/* Given a memory address (which ought to be in the page frame at 0xD0000),
* which page does it relate to? */
static int
addr_to_page(uint32_t addr)
{
if ((addr & 0xF0000) == 0xD0000) {
return ((addr >> 14) & 3);
}
return -1;
}
/* And vice versa: Given a page slot, which memory address does it
* correspond to? */
static uint32_t
page_to_addr(int pg)
{
return 0xD0000 + ((pg & 3) * 16384);
}
/* Given an EMS page ID, return its physical address in RAM. */
uint32_t
t3100e_ems_execaddr(struct t3100e_ems_regs *regs,
int pg, uint16_t val)
{
uint32_t addr;
if (!(val & 0x80))
return 0; /* Bit 7 reset => not mapped */
val &= 0x7F;
val += (0x80 * (pg >> 2)); /* The high bits of the register bank */
/* are used to extend val to allow up */
/* to 8Mb of EMS to be accessed */
/* Is it in the upper memory range? */
if (regs->upper_is_ems) {
if (val < regs->upper_pages) {
addr = regs->upper_base + 0x4000 * val;
return addr;
}
val -= regs->upper_pages;
}
/* Otherwise work down from the top of high RAM (so, the more EMS,
* the less XMS) */
if ((val * 0x4000) + 0x100000 >= (mem_size * 1024)) {
return 0; /* Not enough high RAM for this page */
}
/* High RAM found */
addr = (mem_size * 1024) - 0x4000 * (val + 1);
return addr;
}
/* The registers governing the EMS ports are in rather a nonintuitive order */
static int
port_to_page(uint16_t addr)
{
switch (addr) {
case 0x208:
return 0;
case 0x4208:
return 1;
case 0x8208:
return 2;
case 0xC208:
return 3;
case 0x218:
return 4;
case 0x4218:
return 5;
case 0x8218:
return 6;
case 0xC218:
return 7;
case 0x258:
return 8;
case 0x4258:
return 9;
case 0x8258:
return 10;
case 0xC258:
return 11;
case 0x268:
return 12;
case 0x4268:
return 13;
case 0x8268:
return 14;
case 0xC268:
return 15;
default:
break;
}
return -1;
}
/* Used to dump the memory mapping table, for debugging */
#if 0
void dump_mappings(void)
{
mem_mapping_t *mm = base_mapping.next;
if (!t3100e_log) return;
while (mm)
{
const char *name = "";
uint32_t offset = (uint32_t)(mm->exec - ram);
if (mm == &ram_low_mapping ) name = "LOW ";
if (mm == &ram_mid_mapping ) name = "MID ";
if (mm == &ram_high_mapping) name = "HIGH";
if (mm == &t3100e_ems.upper_mapping) name = "UPPR";
if (mm == &t3100e_ems.mapping[0])
{
name = "EMS0";
offset = t3100e_ems.page_exec[0];
}
if (mm == &t3100e_ems.mapping[1])
{
name = "EMS1";
offset = t3100e_ems.page_exec[1];
}
if (mm == &t3100e_ems.mapping[2])
{
name = "EMS2";
offset = t3100e_ems.page_exec[2];
}
if (mm == &t3100e_ems.mapping[3])
{
name = "EMS3";
offset = t3100e_ems.page_exec[3];
}
t3100e_log(" %p | base=%05x size=%05x %c @ %06x %s\n", mm,
mm->base, mm->size, mm->enable ? 'Y' : 'N',
offset, name);
mm = mm->next;
}
}
#endif
void
t3100e_map_ram(uint8_t val)
{
int32_t upper_len;
#ifdef ENABLE_T3100E_LOG
t3100e_log("OUT 0x8084, %02x [ set memory mapping :", val | 0x40);
if (val & 1)
t3100e_log("ENABLE_EMS ");
if (val & 2)
t3100e_log("ENABLE_XMS ");
if (val & 4)
t3100e_log("640K ");
if (val & 8)
t3100e_log("X8X ");
if (val & 16)
t3100e_log("UPPER_IS_XMS ");
t3100e_log("\n");
#endif
/* Bit 2 controls size of conventional memory */
if (val & 4) {
t3100e_ems.upper_base = 0xA0000;
t3100e_ems.upper_pages = 24;
} else {
t3100e_ems.upper_base = 0x80000;
t3100e_ems.upper_pages = 32;
}
upper_len = t3100e_ems.upper_pages * 16384;
mem_mapping_set_addr(&ram_low_mapping, 0, t3100e_ems.upper_base);
/* Bit 0 set if upper RAM is EMS */
t3100e_ems.upper_is_ems = (val & 1);
/* Bit 1 set if high RAM is enabled */
if (val & 2) {
mem_mapping_enable(&ram_high_mapping);
} else {
mem_mapping_disable(&ram_high_mapping);
}
/* Bit 4 set if upper RAM is mapped to high memory
* (and bit 1 set if XMS enabled) */
if ((val & 0x12) == 0x12) {
mem_mapping_set_addr(&t3100e_ems.upper_mapping,
mem_size * 1024,
upper_len);
mem_mapping_enable(&t3100e_ems.upper_mapping);
mem_mapping_set_exec(&t3100e_ems.upper_mapping, ram + t3100e_ems.upper_base);
} else {
mem_mapping_disable(&t3100e_ems.upper_mapping);
}
/* Recalculate EMS mappings */
for (uint8_t n = 0; n < 4; n++) {
t3100e_ems_out(t3100e_ems_page_reg[n], t3100e_ems.page[n],
&t3100e_ems);
}
#if 0
dump_mappings();
#endif
}
void
t3100e_notify_set(uint8_t value)
{
t3100e_ems.notify = value;
}
void
t3100e_mono_set(uint8_t value)
{
t3100e_ems.mono = value;
}
uint8_t
t3100e_mono_get(void)
{
return t3100e_ems.mono;
}
void
t3100e_turbo_set(uint8_t value)
{
t3100e_ems.turbo = value;
if (!value) {
cpu_dynamic_switch(0); /* 286/6 */
} else {
cpu_dynamic_switch(cpu);
}
}
uint8_t
t3100e_sys_in(UNUSED(uint16_t addr), void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
/* The low 4 bits always seem to be 0x0C. The high 4 are a
* notification sent by the keyboard controller when it detects
* an [Fn] key combination */
t3100e_log("IN 0x8084\n");
return 0x0C | (regs->notify << 4);
}
/* Handle writes to the T3100e system control port at 0x8084 */
void
t3100e_sys_out(UNUSED(uint16_t addr), uint8_t val, UNUSED(void *priv))
{
#if 0
struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
#endif
switch (val & 0xE0) {
case 0x00: /* Set serial port IRQs. Not implemented */
t3100e_log("OUT 0x8084, %02x [ set serial port IRQs]\n", val);
break;
case 0x40: /* Set RAM mappings. */
t3100e_map_ram(val & 0x1F);
break;
case 0x80: /* Set video options. */
t3100e_video_options_set(val & 0x1F);
break;
/* Other options not implemented. */
default:
t3100e_log("OUT 0x8084, %02x\n", val);
break;
}
}
uint8_t
t3100e_config_get(void)
{
/* The byte returned:
Bit 7: Set if internal plasma display enabled
Bit 6: Set if running at 6MHz, clear at full speed
Bit 5: Always 1?
Bit 4: Set if the FD2MB jumper is present (internal floppy is ?tri-mode)
Bit 3: Clear if the FD2 jumper is present (two internal floppies)
Bit 2: Set if the internal drive is A:, clear if B:
Bit 1: Set if the parallel port is configured as a floppy connector
for the second drive.
Bit 0: Set if the F2HD jumper is present (internal floppy is 720k)
*/
uint8_t value = 0x28; /* Start with bits 5 and 3 set. */
int type_a = fdd_get_type(0);
int type_b = fdd_get_type(1);
int prt_switch; /* External drive type: 0=> none, 1=>A, 2=>B */
/* Get display setting */
if (t3100e_display_get())
value |= 0x80;
if (!t3100e_ems.turbo)
value |= 0x40;
/* Try to determine the floppy types.*/
prt_switch = (type_b ? 2 : 0);
switch (type_a) {
/* Since a T3100e cannot have an internal 5.25" drive, mark 5.25" A: drive as
* being external, and set the internal type based on type_b. */
case 1: /* 360k */
case 2: /* 1.2Mb */
case 3: /* 1.2Mb RPMx2*/
prt_switch = 1; /* External drive is A: */
switch (type_b) {
case 1: /* 360k */
case 4:
value |= 1;
break; /* 720k */
case 6:
value |= 0x10;
break; /* Tri-mode */
/* All others will be treated as 1.4M */
default:
break;
}
break;
case 4:
value |= 0x01; /* 720k */
if (type_a == type_b) {
value &= (~8); /* Two internal drives */
prt_switch = 0; /* No external drive */
}
break;
case 5: /* 1.4M */
case 7: /* 2.8M */
if (type_a == type_b) {
value &= (~8); /* Two internal drives */
prt_switch = 0; /* No external drive */
}
break;
case 6: /* 3-mode */
value |= 0x10;
if (type_a == type_b) {
value &= (~8); /* Two internal drives */
prt_switch = 0; /* No external drive */
}
break;
default:
break;
} /* End switch */
switch (prt_switch) {
case 0:
value |= 4;
break; /* No external floppy */
case 1:
value |= 2;
break; /* External floppy is A: */
case 2:
value |= 6;
break; /* External floppy is B: */
default:
break;
}
return value;
}
/* Read EMS page register */
uint8_t
t3100e_ems_in(uint16_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int page = port_to_page(addr);
if (page >= 0)
return regs->page[page];
else {
fatal("t3100e_ems_in(): invalid address");
return 0xff;
}
}
/* Write EMS page register */
void
t3100e_ems_out(uint16_t addr, uint8_t val, void *priv)
{
struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = port_to_page(addr);
if (pg == -1)
return;
regs->page_exec[pg & 3] = t3100e_ems_execaddr(regs, pg, val);
t3100e_log("EMS: page %d %02x -> %02x [%06x]\n",
pg, regs->page[pg], val, regs->page_exec[pg & 3]);
regs->page[pg] = val;
pg &= 3;
/* Bit 7 set if page is enabled, reset if page is disabled */
if (regs->page_exec[pg]) {
t3100e_log("Enabling EMS RAM at %05x\n",
page_to_addr(pg));
mem_mapping_enable(®s->mapping[pg]);
mem_mapping_set_exec(®s->mapping[pg], ram + regs->page_exec[pg]);
} else {
t3100e_log("Disabling EMS RAM at %05x\n",
page_to_addr(pg));
mem_mapping_disable(®s->mapping[pg]);
}
}
/* Read RAM in the EMS page frame */
static uint8_t
ems_read_ram(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xFF;
addr = regs->page_exec[pg] + (addr & 0x3FFF);
return ram[addr];
}
static uint16_t
ems_read_ramw(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xFFFF;
#if 0
t3100e_log("ems_read_ramw addr=%05x ", addr);
#endif
addr = regs->page_exec[pg] + (addr & 0x3FFF);
#if 0
// t3100e_log("-> %06x val=%04x\n", addr, *(uint16_t *) &ram[addr]);
#endif
return *(uint16_t *) &ram[addr];
}
static uint32_t
ems_read_raml(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xFFFFFFFF;
addr = regs->page_exec[pg] + (addr & 0x3FFF);
return *(uint32_t *) &ram[addr];
}
/* Write RAM in the EMS page frame */
static void
ems_write_ram(uint32_t addr, uint8_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
addr = regs->page_exec[pg] + (addr & 0x3FFF);
ram[addr] = val;
}
static void
ems_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
#if 0
t3100e_log("ems_write_ramw addr=%05x ", addr);
#endif
addr = regs->page_exec[pg] + (addr & 0x3FFF);
#if 0
t3100e_log("-> %06x val=%04x\n", addr, val);
#endif
*(uint16_t *) &ram[addr] = val;
}
static void
ems_write_raml(uint32_t addr, uint32_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
addr = regs->page_exec[pg] + (addr & 0x3FFF);
*(uint32_t *) &ram[addr] = val;
}
/* Read RAM in the upper area. This is basically what the 'remapped'
* mapping in mem.c does, except that the upper area can move around */
static uint8_t
upper_read_ram(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
return ram[addr];
}
static uint16_t
upper_read_ramw(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
return *(uint16_t *) &ram[addr];
}
static uint32_t
upper_read_raml(uint32_t addr, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
return *(uint32_t *) &ram[addr];
}
static void
upper_write_ram(uint32_t addr, uint8_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
ram[addr] = val;
}
static void
upper_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
*(uint16_t *) &ram[addr] = val;
}
static void
upper_write_raml(uint32_t addr, uint32_t val, void *priv)
{
const struct t3100e_ems_regs *regs = (struct t3100e_ems_regs *) priv;
addr = (addr - (1024 * mem_size)) + regs->upper_base;
*(uint32_t *) &ram[addr] = val;
}
int
machine_at_t3100e_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/t3100e/t3100e.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
int pg;
memset(&t3100e_ems, 0, sizeof(t3100e_ems));
machine_at_common_ide_init(model);
device_add(&keyboard_at_toshiba_device);
if (fdc_current[0] == FDC_INTERNAL) {
device_add(&fdc_at_device);
}
/* Hook up system control port */
io_sethandler(0x8084, 0x0001,
t3100e_sys_in, NULL, NULL,
t3100e_sys_out, NULL, NULL, &t3100e_ems);
/* Start monitoring all 16 EMS registers */
for (pg = 0; pg < 16; pg++) {
io_sethandler(t3100e_ems_page_reg[pg], 0x0001,
t3100e_ems_in, NULL, NULL,
t3100e_ems_out, NULL, NULL, &t3100e_ems);
}
/* Map the EMS page frame */
for (pg = 0; pg < 4; pg++) {
t3100e_log("Adding memory map at %x for page %d\n", page_to_addr(pg), pg);
mem_mapping_add(&t3100e_ems.mapping[pg],
page_to_addr(pg), 16384,
ems_read_ram, ems_read_ramw, ems_read_raml,
ems_write_ram, ems_write_ramw, ems_write_raml,
NULL, MEM_MAPPING_EXTERNAL,
&t3100e_ems);
/* Start them all off disabled */
mem_mapping_disable(&t3100e_ems.mapping[pg]);
}
/* Mapping for upper RAM when in use as XMS*/
mem_mapping_add(&t3100e_ems.upper_mapping, mem_size * 1024, 384 * 1024,
upper_read_ram, upper_read_ramw, upper_read_raml,
upper_write_ram, upper_write_ramw, upper_write_raml,
NULL, MEM_MAPPING_INTERNAL, &t3100e_ems);
mem_mapping_disable(&t3100e_ems.upper_mapping);
device_add(&t3100e_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_t3100e.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,527 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Victor V86P portable computer emulation.
*
* Authors: Lubomir Rintel, <lkundrak@v3.sk>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
#include <86box/sio.h>
#include <86box/video.h>
int
machine_v86p_init(const machine_t *model)
{
int ret;
int rom_id = 0;
ret = bios_load_interleavedr("roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_122089_Odd.rom",
0x000f8000, 65536, 0);
if (!ret) {
/* Try an older version of the BIOS. */
rom_id = 1;
ret = bios_load_interleavedr("roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Even.rom",
"roms/machines/v86p/INTEL8086AWD_BIOS_S3.1_V86P_090489_Odd.rom",
0x000f8000, 65536, 0);
}
if (!ret) {
/* Try JVERNET's BIOS. */
rom_id = 2;
ret = bios_load_linear("roms/machines/v86p/V86P.ROM",
0x000f0000, 65536, 0);
}
if (bios_only || !ret)
return ret;
if (rom_id == 2)
loadfont("roms/machines/v86p/V86P.FON", 8);
else
loadfont("roms/machines/v86p/v86pfont.rom", 8);
machine_common_init(model);
device_add(&ct_82c100_device);
device_add(&f82c606_device);
device_add(&keyboard_xt_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&f82c425_video_device);
if (hdc_current[0] <= HDC_INTERNAL)
device_add(&st506_xt_victor_v86p_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_v86p.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 831 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of 286 and 386SX machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* EngiNerd <webmaster.crrc@yahoo.it>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/nvr.h>
#include <86box/port_6x.h>
#include <86box/sio.h>
#include <86box/serial.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/flash.h>
#include <86box/machine.h>
int
machine_at_mr286_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/mr286/V000B200-1",
"roms/machines/mr286/V000B200-2",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_headland_common_init(int type)
{
device_add(&keyboard_at_ami_device);
if ((type != 2) && (fdc_current[0] == FDC_INTERNAL))
device_add(&fdc_at_device);
if (type == 2)
device_add(&headland_ht18b_device);
else if (type == 1)
device_add(&headland_gc113_device);
else
device_add(&headland_gc10x_device);
}
int
machine_at_tg286m_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tg286m/ami.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
return ret;
}
int
machine_at_ama932j_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ama932j/ami.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
if (gfxcard[0] == VID_INTERNAL)
device_add(&oti067_ama932j_device);
machine_at_headland_common_init(2);
device_add(&ali5105_device);
return ret;
}
int
machine_at_quadt286_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/quadt286/QUADT89L.ROM",
"roms/machines/quadt286/QUADT89H.ROM",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&headland_gc10x_device);
return ret;
}
int
machine_at_quadt386sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/quadt386sx/QTC-SXM-EVEN-U3-05-07.BIN",
"roms/machines/quadt386sx/QTC-SXM-ODD-U3-05-07.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&headland_gc10x_device);
return ret;
}
int
machine_at_neat_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dtk386/3cto001.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
device_add(&neat_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_neat_ami_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ami286/AMIC206.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&neat_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_px286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/px286/KENITEC.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&neat_device);
return ret;
}
int
machine_at_micronics386_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/micronics386/386-Micronics-09-00021-EVEN.BIN",
"roms/machines/micronics386/386-Micronics-09-00021-ODD.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_scat_init(const machine_t *model, int is_v4, int is_ami)
{
machine_at_common_init(model);
if (machines[machine].bus_flags & MACHINE_BUS_PS2) {
if (is_ami)
device_add(&keyboard_ps2_ami_device);
else
device_add(&keyboard_ps2_device);
} else {
if (is_ami)
device_add(&keyboard_at_ami_device);
else
device_add(&keyboard_at_device);
}
if (is_v4)
device_add(&scat_4_device);
else
device_add(&scat_device);
}
static void
machine_at_scatsx_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&scat_sx_device);
}
int
machine_at_award286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/award286/award.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_gdc212m_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/gdc212m/gdc212m_72h.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_gw286ct_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/gw286ct/2ctc001.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
device_add(&f82c710_device);
machine_at_scat_init(model, 1, 0);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_senor_scat286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/senor286/AMI-DSC2-1115-061390-K8.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_super286c_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/super286c/hyundai_award286.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&neat_device);
return ret;
}
int
machine_at_super286tr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/super286tr/hyundai_award286.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_spc4200p_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/spc4200p/u8.01",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_spc4216p_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/spc4216p/7101.U8",
"roms/machines/spc4216p/AC64.U10",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 1, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_spc4620p_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/spc4620p/31005h.u8",
"roms/machines/spc4620p/31005h.u10",
0x000f0000, 131072, 0x8000);
if (bios_only || !ret)
return ret;
if (gfxcard[0] == VID_INTERNAL)
device_add(&ati28800k_spc4620p_device);
machine_at_scat_init(model, 1, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_kmxc02_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/kmxc02/3ctm005.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scatsx_init(model);
return ret;
}
int
machine_at_deskmaster286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/deskmaster286/SAMSUNG-DESKMASTER-28612-ROM.BIN",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_scat_init(model, 0, 1);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ide_isa_device);
return ret;
}
int
machine_at_shuttle386sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/shuttle386sx/386-Shuttle386SX-Even.BIN",
"roms/machines/shuttle386sx/386-Shuttle386SX-Odd.BIN",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&intel_82335_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_adi386sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/adi386sx/3iip001l.bin",
"roms/machines/adi386sx/3iip001h.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&amstrad_megapc_nvr_device); /* NVR that is initialized to all 0x00's. */
device_add(&intel_82335_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_wd76c10_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/megapc/41651-bios lo.u18",
"roms/machines/megapc/211253-bios hi.u19",
0x000f0000, 65536, 0x08000);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
if (gfxcard[0] == VID_INTERNAL)
device_add(¶dise_wd90c11_megapc_device);
device_add(&keyboard_ps2_quadtel_device);
device_add(&wd76c10_device);
return ret;
}
int
machine_at_cmdsl386sx16_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/cmdsl386sx16/cbm-sl386sx-bios-lo-v1.04-390914-04.bin",
"roms/machines/cmdsl386sx16/cbm-sl386sx-bios-hi-v1.04-390915-04.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&neat_device);
/* Two serial ports - on the real hardware SL386SX-16, they are on the single UMC UM82C452. */
device_add_inst(&ns16450_device, 1);
device_add_inst(&ns16450_device, 2);
return ret;
}
static void
machine_at_scamp_common_init(const machine_t *model, int is_ps2)
{
machine_at_common_ide_init(model);
if (is_ps2)
device_add(&keyboard_ps2_ami_device);
else
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&vlsi_scamp_device);
}
int
machine_at_cmdsl386sx25_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cmdsl386sx25/f000.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5402_onboard_device);
machine_at_common_ide_init(model);
device_add(&ali5105_device); /* The FDC is part of the ALi M5105. */
device_add(&vl82c113_device); /* The keyboard controller is part of the VL82c113. */
device_add(&vlsi_scamp_device);
return ret;
}
int
machine_at_dataexpert386sx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dataexpert386sx/5e9f20e5ef967717086346.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_scamp_common_init(model, 0);
return ret;
}
int
machine_at_spc6033p_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/spc6033p/phoenix.BIN",
0x000f0000, 65536, 0x10000);
if (bios_only || !ret)
return ret;
if (gfxcard[0] == VID_INTERNAL)
device_add(&ati28800k_spc6033p_device);
machine_at_scamp_common_init(model, 1);
return ret;
}
int
machine_at_awardsx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/awardsx/Unknown 386SX OPTi291 - Award (original).BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
device_add(&opti291_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_acer100t_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acer100t/acer386.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ps2_ide_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&ali1409_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&oti077_acer100t_device);
device_add(&ali5105_device);
return ret;
}
int
machine_at_arb1374_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/arb1374/1374s.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1217_device);
device_add(&w83787f_ide_en_device);
device_add(&keyboard_ps2_ami_device);
return ret;
}
int
machine_at_sbc350a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sbc350a/350a.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1217_device);
device_add(&fdc37c665_ide_device);
device_add(&keyboard_ps2_ami_device);
return ret;
}
int
machine_at_flytech386_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/flytech386/FLYTECH.BIO",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1217_device);
device_add(&w83787f_ide_en_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&tvga8900d_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_325ax_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/325ax/M27C512.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1217_device);
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_mr1217_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mr1217/mrbios.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1217_device);
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_pja511m_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pja511m/2006915102435734.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add_inst(&fdc37c669_device, 1);
device_add_inst(&fdc37c669_device, 2);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ali6117d_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_prox1332_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/prox1332/D30B3AC1.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&fdc37c669_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ali6117d_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
/*
* Current bugs:
* - ctrl-alt-del produces an 8042 error
*/
int
machine_at_pc8_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/pc8/ncr_35117_u127_vers.4-2.bin",
"roms/machines/pc8/ncr_35116_u113_vers.4-2.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_ncr_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_3302_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/3302/f000-flex_drive_test.bin",
0x000f0000, 65536, 0);
if (ret) {
ret &= bios_load_aux_linear("roms/machines/3302/f800-setup_ncr3.5-013190.bin",
0x000f8000, 32768, 0);
}
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&neat_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(¶dise_pvga1a_ncr3302_device);
device_add(&keyboard_at_ncr_device);
return ret;
}
/*
* Current bugs:
* - soft-reboot after saving CMOS settings/pressing ctrl-alt-del produces an 8042 error
*/
int
machine_at_pc916sx_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/pc916sx/ncr_386sx_u46-17_7.3.bin",
"roms/machines/pc916sx/ncr_386sx_u12-19_7.3.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_ncr_device);
mem_remap_top(384);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
#ifdef USE_OLIVETTI
int
machine_at_m290_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m290/m290_pep3_1.25.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 4);
device_add(&keyboard_at_olivetti_device);
device_add(&port_6x_olivetti_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&olivetti_eva_device);
return ret;
}
#endif /* USE_OLIVETTI */
``` | /content/code_sandbox/src/machine/m_at_286_386sx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,137 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of the PS/1 Model 2011 disk controller.
*
* XTA is the acronym for 'XT-Attached', which was basically
* the XT-counterpart to what we know now as IDE (which is
* also named ATA - AT Attachment.) The basic ideas was to
* put the actual drive controller electronics onto the drive
* itself, and have the host machine just talk to that using
* a simpe, standardized I/O path- hence the name IDE, for
* Integrated Drive Electronics.
*
* In the ATA version of IDE, the programming interface of
* the IBM PC/AT (which used the Western Digitial 1002/1003
* controllers) was kept, and, so, ATA-IDE assumes a 16bit
* data path: it reads and writes 16bit words of data. The
* disk drives for this bus commonly have an 'A' suffix to
* identify them as 'ATBUS'.
*
* In XTA-IDE, which is slightly older, the programming
* interface of the IBM PC/XT (which used the MFM controller
* from Xebec) was kept, and, so, it uses an 8bit data path.
* Disk drives for this bus commonly have the 'X' suffix to
* mark them as being for this XTBUS variant.
*
* So, XTA and ATA try to do the same thing, but they use
* different ways to achive their goal.
*
* Also, XTA is **not** the same as XTIDE. XTIDE is a modern
* variant of ATA-IDE, but retro-fitted for use on 8bit XT
* systems: an extra register is used to deal with the extra
* data byte per transfer. XTIDE uses regular IDE drives,
* and uses the regular ATA/IDE programming interface, just
* with the extra register.
*
* NOTE: We should probably find a nicer way to integrate our Disk
* Type table with the main code, so the user can only select
* items from that list...
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Based on my earlier HD20 driver for the EuroPC.
* Thanks to Marco Bortolin for the help and feedback !!
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/device.h>
#include <86box/hdc.h>
#include <86box/hdd.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/machine.h>
#define HDC_TIME (250 * TIMER_USEC)
#define HDC_TYPE_USER 47 /* user drive type */
enum {
STATE_IDLE = 0,
STATE_RECV,
STATE_RDATA,
STATE_RDONE,
STATE_SEND,
STATE_SDATA,
STATE_SDONE,
STATE_FINIT,
STATE_FDONE
};
/* Command values. These deviate from the XTA ones. */
#define CMD_READ_SECTORS 0x01 /* regular read-date */
#define CMD_READ_VERIFY 0x02 /* read for verify, no data */
#define CMD_READ_EXT 0x03 /* read extended (ecc) */
#define CMD_READ_ID 0x05 /* read ID mark on cyl */
#define CMD_RECALIBRATE 0x08 /* recalibrate to track0 */
#define CMD_WRITE_SECTORS 0x09 /* regular write-data */
#define CMD_WRITE_VERIFY 0x0a /* write-data with verify */
#define CMD_WRITE_EXT 0x0b /* write extended (ecc) */
#define CMD_FORMAT_DRIVE 0x0d /* format entire disk */
#define CMD_SEEK 0x0e /* seek */
#define CMD_FORMAT_TRACK 0x0f /* format one track */
/* Attachment Status register (reg 2R) values (IBM PS/1 2011.) */
#define ASR_TX_EN 0x01 /* transfer enable */
#define ASR_INT_REQ 0x02 /* interrupt request */
#define ASR_BUSY 0x04 /* busy */
#define ASR_DIR 0x08 /* direction */
#define ASR_DATA_REQ 0x10 /* data request */
/* Attachment Control register (2W) values (IBM PS/1 2011.) */
#define ACR_DMA_EN 0x01 /* DMA enable */
#define ACR_INT_EN 0x02 /* interrupt enable */
#define ACR_RESET 0x80 /* reset */
/* Interrupt Status register (4R) values (IBM PS/1 2011.) */
#define ISR_EQUIP_CHECK 0x01 /* internal hardware error */
#define ISR_ERP_INVOKED 0x02 /* error recovery invoked */
#define ISR_CMD_REJECT 0x20 /* command reject */
#define ISR_INVALID_CMD 0x40 /* invalid command */
#define ISR_TERMINATION 0x80 /* termination error */
/* Attention register (4W) values (IBM PS/1 2011.) */
#define ATT_DATA 0x10 /* data request */
#define ATT_SSB 0x20 /* sense summary block */
#define ATT_CSB 0x40 /* command specify block */
#define ATT_CCB 0x80 /* command control block */
/*
* Define the Sense Summary Block.
*
* The sense summary block contains the current status of the
* drive. The information in the summary block is updated after
* each command is completed, after an error, or before the
* block is transferred.
*/
#pragma pack(push, 1)
typedef struct ssb_t {
/* Status byte 0. */
uint8_t track_0 : 1; /* T0 */
uint8_t mbz1 : 1; /* 0 */
uint8_t mbz2 : 1; /* 0 */
uint8_t cylinder_err : 1; /* CE */
uint8_t write_fault : 1; /* WF */
uint8_t mbz3 : 1; /* 0 */
uint8_t seek_end : 1; /* SE */
uint8_t not_ready : 1; /* NR */
/* Status byte 1. */
uint8_t id_not_found : 1; /* ID */
uint8_t mbz4 : 1; /* 0 */
uint8_t mbz5 : 1; /* 0 */
uint8_t wrong_cyl : 1; /* WC */
uint8_t all_bit_set : 1; /* BT */
uint8_t mark_not_found : 1; /* AM */
uint8_t ecc_crc_err : 1; /* ET */
uint8_t ecc_crc_field : 1; /* EF */
/* Status byte 2. */
uint8_t headsel_state : 4; /* headsel state[4] */
uint8_t defective_sector : 1; /* DS */
uint8_t retried_ok : 1; /* RG */
uint8_t need_reset : 1; /* RR */
#if 1
uint8_t valid : 1; /* 0 (abused as VALID) */
#else
uint8_t mbz6 : 1; /* 0 */
#endif
/* Most recent ID field seen. */
uint8_t last_cyl_low; /* Cyl_Low[8] */
uint8_t last_head : 4; /* HD[4] */
uint8_t mbz7 : 1; /* 0 */
uint8_t last_cyl_high : 2; /* Cyl_high[2] */
uint8_t last_def_sect : 1; /* DS */
uint8_t last_sect; /* Sect[8] */
uint8_t sect_size; /* Size[8] = 02 */
/* Current position. */
uint8_t curr_cyl_high : 2; /* Cyl_High_[2] */
uint8_t mbz8 : 1; /* 0 */
uint8_t mbz9 : 1; /* 0 */
uint8_t curr_head : 4; /* HD_2[4] */
uint8_t curr_cyl_low; /* Cyl_Low_2[8] */
uint8_t sect_corr; /* sectors corrected */
uint8_t retries; /* retries */
/*
* This byte shows the progress of the controller through the
* last command. It allows the system to monitor the controller
* and determine if a reset is needed. When the transfer of the
* control block is started, the value is set to hex 00. The
* progress indicated by this byte is:
*
* 1. Set to hex 01 after the control block is successfully
* transferred.
*
* 2. Set to hex 02 when the command is valid and the drive
* is ready.
*
* 3. Set to hex 03 when the head is in the correct track.
* The most-significant four bits (high nibble) are then
* used to indicate the successful stages of the data
* transfer:
*
* Bit 7 A sector was transferred between the system
* and the sector buffer.
*
* Bit 6 A sector was transferred between the controller
* and the sector buffer.
*
* Bit 5 An error was detected and error recovery
* procedures have been started.
*
* Bit 4 The controller has completed the operation
* and is now not busy.
*
* 4. When the transfer is complete, the low nibble equals hex 4
* and the high nibble is unchanged.
*/
uint8_t cmd_syndrome; /* command syndrome */
uint8_t drive_type; /* drive type */
uint8_t rsvd; /* reserved byte */
} ssb_t;
#pragma pack(pop)
/*
* Define the Format Control Block.
*
* The format control block (FCB) specifies the ID data used
* in formatting the track. It is used by the Format Track
* and Format Disk commands and contains five bytes for each
* sector formatted on that track.
*
* When the Format Disk command is used, the control block
* contains the sector information of all sectors for head 0,
* cylinder 0. The drive will use the same block to format
* the rest of the disk and automatically increment the head
* number and cylinder number for the remaining tracks. The
* sector numbers, sector size, and the fill byte will be
* the same for each track.
*
* The drive formats the sector IDs on the disk in the same
* order as they are specified in the control block.
* Therefore, sector interleaving is accomplished by filling
* in the control block with the desired interleave.
*
* For example, when formatting 17 sectors per track with an
* interleave of 2, the control block has the first 5 bytes
* with a sector number of 1, the second with a sector number
* of 10, the third with a sector number of 2, and continuing
* until all 17 sectors for that track are defined.
*
* The format for the format control block is described in
* the following. The five bytes are repeated for each
* sector on the track. The control block must contain an
* even number of bytes. If an odd number of sectors are
* being formatted, an additional byte is sent with all
* bits 0.
*/
#pragma pack(push, 1)
typedef struct fcb_t {
uint8_t cyl_high : 2; /* cylinder [9:8] bits */
uint8_t defective_sector : 1; /* DS */
uint8_t mbz1 : 1; /* 0 */
uint8_t head : 4; /* head number */
uint8_t cyl_low; /* cylinder [7:0] bits */
uint8_t sector; /* sector number */
uint8_t mbz2 : 1; /* 0 */
uint8_t mbo : 1; /* 1 */
uint8_t mbz3 : 6; /* 000000 */
uint8_t fill; /* filler byte */
} fcb_t;
#pragma pack(pop)
/*
* Define the Command Control Block.
*
* The system specifies the operation by sending the 6-byte
* command control block to the controller. It can be sent
* through a DMA or PIO operation.
*/
#pragma pack(push, 1)
typedef struct ccb_t{
uint8_t ec_p : 1; /* EC/P (ecc/park) */
uint8_t mbz1 : 1; /* 0 */
uint8_t auto_seek : 1; /* AS (auto-seek) */
uint8_t no_data : 1; /* ND (no data) */
uint8_t cmd : 4; /* command code[4] */
uint8_t cyl_high : 2; /* cylinder [9:8] bits */
uint8_t mbz2 : 2; /* 00 */
uint8_t head : 4; /* head number */
uint8_t cyl_low; /* cylinder [7:0] bits */
uint8_t sector; /* sector number */
uint8_t mbz3 : 1; /* 0 */
uint8_t mbo1 : 1; /* 1 */
uint8_t mbz4 : 6; /* 000000 */
uint8_t count; /* blk count/interleave */
} ccb_t;
#pragma pack(pop)
/* Define the hard drive geometry table. */
typedef struct geom_t {
uint16_t cyl;
uint8_t hpc;
uint8_t spt;
int16_t wpc;
int16_t lz;
} geom_t;
/* Define an attached drive. */
typedef struct drive_t {
int8_t id; /* drive ID on bus */
int8_t present; /* drive is present */
int8_t hdd_num; /* index to global disk table */
int8_t type; /* drive type ID */
uint16_t cur_cyl; /* last known position of heads */
uint8_t spt; /* active drive parameters */
uint8_t hpc;
uint16_t tracks;
uint8_t cfg_spt; /* configured drive parameters */
uint8_t cfg_hpc;
uint16_t cfg_tracks;
} drive_t;
typedef struct hdc_t {
uint16_t base; /* controller base I/O address */
int8_t irq; /* controller IRQ channel */
int8_t dma; /* controller DMA channel */
/* Registers. */
uint8_t attn; /* ATTENTION register */
uint8_t ctrl; /* Control register (ACR) */
uint8_t status; /* Status register (ASR) */
uint8_t intstat; /* Interrupt Status register (ISR) */
uint8_t *reg_91; /* handle to system board's register 0x91 */
/* Controller state. */
pc_timer_t timer;
int8_t state; /* controller state */
int8_t reset; /* reset state counter */
/* Data transfer. */
int16_t buf_idx; /* buffer index and pointer */
int16_t buf_len;
uint8_t *buf_ptr;
/* Current operation parameters. */
ssb_t ssb; /* sense block */
ccb_t ccb; /* command control block */
uint16_t track; /* requested track# */
uint8_t head; /* requested head# */
uint8_t sector; /* requested sector# */
int count; /* requested sector count */
drive_t drives[XTA_NUM]; /* the attached drive(s) */
uint8_t data[512]; /* data buffer */
uint8_t sector_buf[512]; /* sector buffer */
} hdc_t;
/*
* IBM hard drive types 1-44.
*
* We need these to translate the selected disk's
* geometry back to a valid type through the SSB.
*
* Cyl. Head Sect. Write Land
* p-comp Zone
*/
static const geom_t ibm_type_table[] = {
// clang-format off
{ 0, 0, 0, 0, 0 }, /* 0 (none) */
{ 306, 4, 17, 128, 305 }, /* 1 10 MB */
{ 615, 4, 17, 300, 615 }, /* 2 20 MB */
{ 615, 6, 17, 300, 615 }, /* 3 31 MB */
{ 940, 8, 17, 512, 940 }, /* 4 62 MB */
{ 940, 6, 17, 512, 940 }, /* 5 47 MB */
{ 615, 4, 17, -1, 615 }, /* 6 20 MB */
{ 462, 8, 17, 256, 511 }, /* 7 31 MB */
{ 733, 5, 17, -1, 733 }, /* 8 30 MB */
{ 900, 15, 17, -1, 901 }, /* 9 112 MB */
{ 820, 3, 17, -1, 820 }, /* 10 20 MB */
{ 855, 5, 17, -1, 855 }, /* 11 35 MB */
{ 855, 7, 17, -1, 855 }, /* 12 50 MB */
{ 306, 8, 17, 128, 319 }, /* 13 20 MB */
{ 733, 7, 17, -1, 733 }, /* 14 43 MB */
{ 0, 0, 0, 0, 0 }, /* 15 (rsvd) */
{ 612, 4, 17, 0, 663 }, /* 16 20 MB */
{ 977, 5, 17, 300, 977 }, /* 17 41 MB */
{ 977, 7, 17, -1, 977 }, /* 18 57 MB */
{ 1024, 7, 17, 512, 1023 }, /* 19 59 MB */
{ 733, 5, 17, 300, 732 }, /* 20 30 MB */
{ 733, 7, 17, 300, 732 }, /* 21 43 MB */
{ 733, 5, 17, 300, 733 }, /* 22 30 MB */
{ 306, 4, 17, 0, 336 }, /* 23 10 MB */
{ 612, 4, 17, 305, 663 }, /* 24 20 MB */
{ 306, 4, 17, -1, 340 }, /* 25 10 MB */
{ 612, 4, 17, -1, 670 }, /* 26 20 MB */
{ 698, 7, 17, 300, 732 }, /* 27 41 MB */
{ 976, 5, 17, 488, 977 }, /* 28 40 MB */
{ 306, 4, 17, 0, 340 }, /* 29 10 MB */
{ 611, 4, 17, 306, 663 }, /* 30 20 MB */
{ 732, 7, 17, 300, 732 }, /* 31 43 MB */
{ 1023, 5, 17, -1, 1023 }, /* 32 42 MB */
{ 614, 4, 25, -1, 663 }, /* 33 30 MB */
{ 775, 2, 27, -1, 900 }, /* 34 20 MB */
{ 921, 2, 33, -1, 1000 }, /* 35 30 MB * */
{ 402, 4, 26, -1, 460 }, /* 36 20 MB */
{ 580, 6, 26, -1, 640 }, /* 37 44 MB */
{ 845, 2, 36, -1, 1023 }, /* 38 30 MB * */
{ 769, 3, 36, -1, 1023 }, /* 39 41 MB * */
{ 531, 4, 39, -1, 532 }, /* 40 40 MB */
{ 577, 2, 36, -1, 1023 }, /* 41 20 MB */
{ 654, 2, 32, -1, 674 }, /* 42 20 MB */
{ 923, 5, 36, -1, 1023 }, /* 43 81 MB */
{ 531, 8, 39, -1, 532 } /* 44 81 MB */
// clang-format on
};
#define ENABLE_PS1_HDC_LOG 1
#ifdef ENABLE_PS1_HDC_LOG
int ps1_hdc_do_log = ENABLE_PS1_HDC_LOG;
static void
ps1_hdc_log(const char *fmt, ...)
{
va_list ap;
if (ps1_hdc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ps1_hdc_log(fmt, ...)
#endif
/* FIXME: we should use the disk/hdd_table.c code with custom tables! */
static int
ibm_drive_type(drive_t *drive)
{
const geom_t *ptr;
for (uint16_t i = 0; i < (sizeof(ibm_type_table) / sizeof(geom_t)); i++) {
ptr = &ibm_type_table[i];
if ((drive->tracks == ptr->cyl) && (drive->hpc == ptr->hpc) && (drive->spt == ptr->spt))
return i;
}
return HDC_TYPE_USER;
}
static void
set_intr(hdc_t *dev, int raise)
{
if (raise) {
dev->status |= ASR_INT_REQ;
if (dev->ctrl & ACR_INT_EN)
picint(1 << dev->irq);
} else {
dev->status &= ~ASR_INT_REQ;
picintc(1 << dev->irq);
}
}
/* Get the logical (block) address of a CHS triplet. */
static int
get_sector(hdc_t *dev, drive_t *drive, off64_t *addr)
{
if (drive->cur_cyl != dev->track) {
ps1_hdc_log("HDC: get_sector: wrong cylinder %d/%d\n",
drive->cur_cyl, dev->track);
dev->ssb.wrong_cyl = 1;
return 1;
}
if (dev->head >= drive->hpc) {
ps1_hdc_log("HDC: get_sector: past end of heads\n");
dev->ssb.cylinder_err = 1;
return 1;
}
if (dev->sector > drive->spt) {
ps1_hdc_log("HDC: get_sector: past end of sectors\n");
dev->ssb.mark_not_found = 1;
return 1;
}
/* Calculate logical address (block number) of desired sector. */
*addr = ((((off64_t) dev->track * drive->hpc) + dev->head) * drive->spt) + dev->sector - 1;
return 0;
}
static void
next_sector(hdc_t *dev, drive_t *drive)
{
if (++dev->sector > drive->spt) {
dev->sector = 1;
if (++dev->head >= drive->hpc) {
dev->head = 0;
dev->track++;
if (++drive->cur_cyl >= drive->tracks) {
drive->cur_cyl = drive->tracks - 1;
dev->ssb.cylinder_err = 1;
}
}
}
}
/* Finish up. Repeated all over, so a function it is now. */
static void
do_finish(hdc_t *dev)
{
dev->state = STATE_IDLE;
dev->attn &= ~(ATT_CCB | ATT_DATA);
dev->status = 0x00;
set_intr(dev, 1);
}
/* Seek to a cylinder. */
static int
do_seek(hdc_t *dev, drive_t *drive, uint16_t cyl)
{
if (cyl >= drive->tracks) {
dev->ssb.cylinder_err = 1;
return 1;
}
dev->track = cyl;
drive->cur_cyl = dev->track;
return 0;
}
/* Format a track or an entire drive. */
static void
do_format(hdc_t *dev, drive_t *drive, ccb_t *ccb)
{
int start_cyl;
int end_cyl;
int intr = 0;
int val;
off64_t addr;
#if 0
fcb_t *fcb;
#endif
/* Get the parameters from the CCB. */
if (ccb->cmd == CMD_FORMAT_DRIVE) {
start_cyl = 0;
end_cyl = drive->tracks;
} else {
start_cyl = (ccb->cyl_low | (ccb->cyl_high << 8));
end_cyl = start_cyl + 1;
}
switch (dev->state) {
case STATE_IDLE:
/* Ready to transfer the FCB data in. */
dev->state = STATE_RDATA;
dev->buf_idx = 0;
dev->buf_ptr = dev->data;
dev->buf_len = ccb->count * sizeof(fcb_t);
if (dev->buf_len & 1)
dev->buf_len++; /* must be even */
/* Enable for PIO or DMA, as needed. */
#if NOT_USED
if (dev->ctrl & ACR_DMA_EN)
timer_advance_u64(&dev->timer, HDC_TIME);
else
#endif
dev->status |= ASR_DATA_REQ;
break;
case STATE_RDATA:
/* Perform DMA. */
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
dev->intstat |= ISR_EQUIP_CHECK;
dev->ssb.need_reset = 1;
intr = 1;
break;
}
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
dev->buf_idx++;
}
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, HDC_TIME);
break;
case STATE_RDONE:
if (!(dev->ctrl & ACR_DMA_EN))
dev->status &= ~ASR_DATA_REQ;
/* Point to the FCB we got. */
#if 0
fcb = (fcb_t *)dev->data;
#endif
dev->state = STATE_FINIT;
fallthrough;
case STATE_FINIT:
do_fmt:
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
/* Seek to cylinder. */
if (do_seek(dev, drive, start_cyl)) {
intr = 1;
break;
}
dev->head = ccb->head;
dev->sector = 1;
/* Get address of sector to write. */
if (get_sector(dev, drive, &addr)) {
intr = 1;
break;
}
/*
* For now, we don't use the info from
* the FCB, although we should at least
* use it's "filler byte" value...
*/
#if 0
hdd_image_zero_ex(drive->hdd_num, addr, fcb->fill, drive->spt);
#else
hdd_image_zero(drive->hdd_num, addr, drive->spt);
#endif
/* Done with this track. */
dev->state = STATE_FDONE;
fallthrough;
case STATE_FDONE:
/* One more track done. */
if (++start_cyl == end_cyl) {
intr = 1;
break;
}
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
/* This saves us a LOT of code. */
dev->state = STATE_FINIT;
goto do_fmt;
default:
break;
}
/* If we errored out, go back idle. */
if (intr) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
do_finish(dev);
}
}
/* Execute the CCB we just received. */
static void
hdc_callback(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
ccb_t *ccb = &dev->ccb;
drive_t *drive;
off64_t addr;
int no_data = 0;
int val;
uint8_t cmd = ccb->cmd & 0x0f;
/* Clear the SSB error bits. */
dev->ssb.track_0 = 0;
dev->ssb.cylinder_err = 0;
dev->ssb.write_fault = 0;
dev->ssb.seek_end = 0;
dev->ssb.not_ready = 0;
dev->ssb.id_not_found = 0;
dev->ssb.wrong_cyl = 0;
dev->ssb.all_bit_set = 0;
dev->ssb.mark_not_found = 0;
dev->ssb.ecc_crc_err = 0;
dev->ssb.ecc_crc_field = 0;
dev->ssb.valid = 1;
/* We really only support one drive, but ohwell. */
drive = &dev->drives[0];
ps1_hdc_log("hdc_callback(): %02X\n", cmd);
switch (ccb->cmd) {
case CMD_READ_VERIFY:
no_data = 1;
fallthrough;
case CMD_READ_SECTORS:
if (!drive->present) {
dev->ssb.not_ready = 1;
do_finish(dev);
return;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder if requested. */
if (ccb->auto_seek) {
if (do_seek(dev, drive,
(ccb->cyl_low | (ccb->cyl_high << 8)))) {
do_finish(dev);
return;
}
}
dev->head = ccb->head;
dev->sector = ccb->sector;
/* Get sector count and size. */
dev->count = (int) ccb->count;
dev->buf_len = (128 << dev->ssb.sect_size);
dev->state = STATE_SEND;
fallthrough;
case STATE_SEND:
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
do_send:
/* Get address of sector to load. */
if (get_sector(dev, drive, &addr)) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
do_finish(dev);
return;
}
/* Read the block from the image. */
hdd_image_read(drive->hdd_num, addr, 1,
(uint8_t *) dev->sector_buf);
/* Ready to transfer the data out. */
dev->state = STATE_SDATA;
dev->buf_idx = 0;
if (no_data) {
/* Delay a bit, no actual transfer. */
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
if (dev->ctrl & ACR_DMA_EN) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
/* No DMA, do PIO. */
dev->status |= (ASR_DATA_REQ | ASR_DIR);
/* Copy from sector to data. */
memcpy(dev->data,
dev->sector_buf,
dev->buf_len);
dev->buf_ptr = dev->data;
}
}
break;
case STATE_SDATA:
if (!no_data) {
/* Perform DMA. */
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_write(dev->dma,
*dev->buf_ptr++);
if (val == DMA_NODATA) {
ps1_hdc_log("HDC: CMD_READ_SECTORS out of data (idx=%d, len=%d)!\n", dev->buf_idx, dev->buf_len);
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
dev->intstat |= ISR_EQUIP_CHECK;
dev->ssb.need_reset = 1;
do_finish(dev);
return;
}
dev->buf_idx++;
}
}
dev->state = STATE_SDONE;
timer_advance_u64(&dev->timer, HDC_TIME);
break;
case STATE_SDONE:
dev->buf_idx = 0;
if (--dev->count == 0) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
if (!(dev->ctrl & ACR_DMA_EN))
dev->status &= ~(ASR_DATA_REQ | ASR_DIR);
dev->ssb.cmd_syndrome = 0xD4;
do_finish(dev);
return;
}
/* Addvance to next sector. */
next_sector(dev, drive);
/* This saves us a LOT of code. */
dev->state = STATE_SEND;
goto do_send;
default:
break;
}
break;
case CMD_READ_ID: /* READ_ID */
if (!drive->present) {
dev->ssb.not_ready = 1;
do_finish(dev);
return;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder if requested. */
if (ccb->auto_seek) {
if (do_seek(dev, drive,
(ccb->cyl_low | (ccb->cyl_high << 8)))) {
do_finish(dev);
return;
}
}
dev->head = ccb->head;
/* Get sector count and size. */
dev->count = (int) ccb->count;
dev->buf_len = (128 << dev->ssb.sect_size);
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
/* Ready to transfer the data out. */
dev->state = STATE_SDONE;
dev->buf_idx = 0;
/* Delay a bit, no actual transfer. */
timer_advance_u64(&dev->timer, HDC_TIME);
break;
case STATE_SDONE:
dev->buf_idx = 0;
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
if (!(dev->ctrl & ACR_DMA_EN))
dev->status &= ~(ASR_DATA_REQ | ASR_DIR);
dev->ssb.cmd_syndrome = 0x14;
do_finish(dev);
break;
default:
break;
}
break;
case CMD_READ_EXT: /* READ_EXT */
if (!drive->present) {
dev->ssb.not_ready = 1;
do_finish(dev);
return;
}
dev->intstat |= ISR_INVALID_CMD;
do_finish(dev);
break;
case CMD_RECALIBRATE: /* RECALIBRATE */
if (drive->present) {
dev->track = drive->cur_cyl = 0;
} else {
dev->ssb.not_ready = 1;
dev->intstat |= ISR_TERMINATION;
}
do_finish(dev);
break;
case CMD_WRITE_VERIFY:
no_data = 1;
fallthrough;
case CMD_WRITE_SECTORS:
if (!drive->present) {
dev->ssb.not_ready = 1;
do_finish(dev);
return;
}
switch (dev->state) {
case STATE_IDLE:
/* Seek to cylinder if requested. */
if (ccb->auto_seek) {
if (do_seek(dev, drive,
(ccb->cyl_low | (ccb->cyl_high << 8)))) {
do_finish(dev);
return;
}
}
dev->head = ccb->head;
dev->sector = ccb->sector;
/* Get sector count and size. */
dev->count = (int) ccb->count;
dev->buf_len = (128 << dev->ssb.sect_size);
dev->state = STATE_RECV;
fallthrough;
case STATE_RECV:
/* Activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 1);
do_recv:
/* Ready to transfer the data in. */
dev->state = STATE_RDATA;
dev->buf_idx = 0;
if (no_data) {
/* Delay a bit, no actual transfer. */
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
if (dev->ctrl & ACR_DMA_EN) {
/* DMA enabled. */
dev->buf_ptr = dev->sector_buf;
timer_advance_u64(&dev->timer, HDC_TIME);
} else {
/* No DMA, do PIO. */
dev->buf_ptr = dev->data;
dev->status |= ASR_DATA_REQ;
}
}
break;
case STATE_RDATA:
if (!no_data) {
/* Perform DMA. */
while (dev->buf_idx < dev->buf_len) {
val = dma_channel_read(dev->dma);
if (val == DMA_NODATA) {
ps1_hdc_log("HDC: CMD_WRITE_SECTORS out of data (idx=%d, len=%d)!\n", dev->buf_idx, dev->buf_len);
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
dev->intstat |= ISR_EQUIP_CHECK;
dev->ssb.need_reset = 1;
do_finish(dev);
return;
}
dev->buf_ptr[dev->buf_idx] = (val & 0xff);
dev->buf_idx++;
}
}
dev->state = STATE_RDONE;
timer_advance_u64(&dev->timer, HDC_TIME);
break;
case STATE_RDONE:
/* Copy from data to sector if PIO. */
if (!(dev->ctrl & ACR_DMA_EN))
memcpy(dev->sector_buf,
dev->data,
dev->buf_len);
/* Get address of sector to write. */
if (get_sector(dev, drive, &addr)) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
do_finish(dev);
return;
}
/* Write the block to the image. */
hdd_image_write(drive->hdd_num, addr, 1,
(uint8_t *) dev->sector_buf);
dev->buf_idx = 0;
if (--dev->count == 0) {
/* De-activate the status icon. */
ui_sb_update_icon(SB_HDD | HDD_BUS_XTA, 0);
if (!(dev->ctrl & ACR_DMA_EN))
dev->status &= ~ASR_DATA_REQ;
dev->ssb.cmd_syndrome = 0xD4;
do_finish(dev);
return;
}
/* Advance to next sector. */
next_sector(dev, drive);
/* This saves us a LOT of code. */
dev->state = STATE_RECV;
goto do_recv;
default:
break;
}
break;
case CMD_FORMAT_DRIVE:
case CMD_FORMAT_TRACK:
do_format(dev, drive, ccb);
break;
case CMD_SEEK:
if (!drive->present) {
dev->ssb.not_ready = 1;
do_finish(dev);
return;
}
if (ccb->ec_p == 1) {
/* Park the heads. */
val = do_seek(dev, drive, drive->tracks - 1);
} else {
/* Seek to cylinder. */
val = do_seek(dev, drive,
(ccb->cyl_low | (ccb->cyl_high << 8)));
}
if (!val)
dev->ssb.seek_end = 1;
do_finish(dev);
break;
default:
dev->intstat |= ISR_INVALID_CMD;
do_finish(dev);
}
}
/* Prepare to send the SSB block. */
static void
hdc_send_ssb(hdc_t *dev)
{
const drive_t *drive;
/* We only support one drive, really, but ohwell. */
drive = &dev->drives[0];
if (!dev->ssb.valid) {
/* Create a valid SSB. */
memset(&dev->ssb, 0x00, sizeof(dev->ssb));
dev->ssb.sect_size = 0x02; /* 512 bytes */
dev->ssb.drive_type = drive->type;
}
/* Update position fields. */
dev->ssb.track_0 = !!(dev->track == 0);
dev->ssb.last_cyl_low = dev->ssb.curr_cyl_low;
dev->ssb.last_cyl_high = dev->ssb.curr_cyl_high;
dev->ssb.last_head = dev->ssb.curr_head;
dev->ssb.curr_cyl_high = ((dev->track >> 8) & 0x03);
dev->ssb.curr_cyl_low = (dev->track & 0xff);
dev->ssb.curr_head = (dev->head & 0x0f);
dev->ssb.headsel_state = dev->ssb.curr_head;
dev->ssb.last_sect = dev->sector;
/* We abuse an unused MBZ bit, so clear it. */
dev->ssb.valid = 0;
/* Set up the transfer buffer for the SSB. */
dev->buf_idx = 0;
dev->buf_len = sizeof(dev->ssb);
dev->buf_ptr = (uint8_t *) &dev->ssb;
/* Done with the SSB. */
dev->attn &= ~ATT_SSB;
}
/* Read one of the controller registers. */
static uint8_t
hdc_read(uint16_t port, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
uint8_t ret = 0xff;
/* TRM: tell system board we are alive. */
*dev->reg_91 |= 0x01;
switch (port & 7) {
case 0: /* DATA register */
if (dev->state == STATE_SDATA) {
if (dev->buf_idx > dev->buf_len) {
ps1_hdc_log("HDC: read with empty buffer!\n");
dev->state = STATE_IDLE;
dev->intstat |= ISR_INVALID_CMD;
dev->status &= (ASR_TX_EN | ASR_DATA_REQ | ASR_DIR);
set_intr(dev, 1);
break;
}
ret = dev->buf_ptr[dev->buf_idx];
if (++dev->buf_idx == dev->buf_len) {
/* Data block sent OK. */
dev->status &= ~(ASR_TX_EN | ASR_DATA_REQ | ASR_DIR);
dev->state = STATE_IDLE;
}
}
break;
case 2: /* ASR */
ret = dev->status;
break;
case 4: /* ISR */
ret = dev->intstat;
dev->intstat = 0x00;
break;
default:
break;
}
ps1_hdc_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, port, ret);
return ret;
}
static void
hdc_write(uint16_t port, uint8_t val, void *priv)
{
hdc_t *dev = (hdc_t *) priv;
ps1_hdc_log("[%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, port, val);
/* TRM: tell system board we are alive. */
*dev->reg_91 |= 0x01;
switch (port & 7) {
case 0: /* DATA register */
if (dev->state == STATE_RDATA) {
if (dev->buf_idx >= dev->buf_len) {
ps1_hdc_log("HDC: write with full buffer!\n");
dev->intstat |= ISR_INVALID_CMD;
dev->status &= ~ASR_DATA_REQ;
set_intr(dev, 1);
break;
}
/* Store the data into the buffer. */
dev->buf_ptr[dev->buf_idx] = val;
ps1_hdc_log("dev->buf_ptr[%02X] = %02X\n", dev->buf_idx, val);
if (++dev->buf_idx == dev->buf_len) {
/* We got all the data we need. */
dev->status &= ~ASR_DATA_REQ;
dev->state = STATE_IDLE;
/* If we were receiving a CCB, execute it. */
if (dev->attn & ATT_CCB) {
/*
* If we were already busy with
* a CCB, then it must have had
* some new data using PIO.
*/
if (dev->status & ASR_BUSY)
dev->state = STATE_RDONE;
else
dev->status |= ASR_BUSY;
/* Schedule command execution. */
timer_set_delay_u64(&dev->timer, HDC_TIME);
}
}
}
break;
case 2: /* ACR */
dev->ctrl = val;
if (val & ACR_INT_EN)
set_intr(dev, 0); /* clear IRQ */
if (dev->reset != 0) {
if (++dev->reset == 3) {
dev->reset = 0;
set_intr(dev, 1);
}
break;
}
if (val & ACR_RESET)
dev->reset = 1;
break;
case 4: /* ATTN */
dev->status &= ~ASR_INT_REQ;
if (val & ATT_DATA) {
/* Dunno. Start PIO/DMA now? */
}
if (val & ATT_SSB) {
if (dev->attn & ATT_CCB) {
/* Hey now, we're still busy for you! */
dev->intstat |= ISR_INVALID_CMD;
set_intr(dev, 1);
break;
}
/* OK, prepare for sending an SSB. */
dev->attn |= ATT_SSB;
/* Grab or initialize an SSB to send. */
hdc_send_ssb(dev);
dev->state = STATE_SDATA;
dev->status |= (ASR_TX_EN | ASR_DATA_REQ | ASR_DIR);
set_intr(dev, 1);
}
if (val & ATT_CCB) {
dev->attn |= ATT_CCB;
/* Set up the transfer buffer for a CCB. */
dev->buf_idx = 0;
dev->buf_len = sizeof(dev->ccb);
dev->buf_ptr = (uint8_t *) &dev->ccb;
dev->state = STATE_RDATA;
dev->status |= ASR_DATA_REQ;
set_intr(dev, 1);
}
break;
default:
break;
}
}
static void *
ps1_hdc_init(UNUSED(const device_t *info))
{
drive_t *drive;
hdc_t *dev;
int c;
/* Allocate and initialize device block. */
dev = malloc(sizeof(hdc_t));
memset(dev, 0x00, sizeof(hdc_t));
/* Set up controller parameters for PS/1 2011. */
dev->base = 0x0320;
dev->irq = 14;
dev->dma = 3;
ps1_hdc_log("HDC: initializing (I/O=%04X, IRQ=%d, DMA=%d)\n",
dev->base, dev->irq, dev->dma);
/* Load any disks for this device class. */
c = 0;
for (uint8_t i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus == HDD_BUS_XTA) && (hdd[i].xta_channel < 1)) {
drive = &dev->drives[hdd[i].xta_channel];
if (!hdd_image_load(i)) {
drive->present = 0;
continue;
}
drive->id = c;
/* These are the "hardware" parameters (from the image.) */
drive->cfg_spt = (uint8_t) (hdd[i].spt & 0xff);
drive->cfg_hpc = (uint8_t) (hdd[i].hpc & 0xff);
drive->cfg_tracks = (uint16_t) hdd[i].tracks;
/* Use them as "active" parameters until overwritten. */
drive->spt = drive->cfg_spt;
drive->hpc = drive->cfg_hpc;
drive->tracks = drive->cfg_tracks;
drive->type = ibm_drive_type(drive);
drive->hdd_num = i;
drive->present = 1;
ps1_hdc_log("HDC: drive%d (type %d: cyl=%d,hd=%d,spt=%d), disk %d\n",
hdd[i].xta_channel, drive->type,
drive->tracks, drive->hpc, drive->spt, i);
if (++c > 1)
break;
}
}
/* Sectors are 1-based. */
dev->sector = 1;
/* Enable the I/O block. */
io_sethandler(dev->base, 5,
hdc_read, NULL, NULL, hdc_write, NULL, NULL, dev);
/* Create a timer for command delays. */
timer_add(&dev->timer, hdc_callback, dev, 0);
return dev;
}
static void
ps1_hdc_close(void *priv)
{
hdc_t *dev = (hdc_t *) priv;
const drive_t *drive;
/* Remove the I/O handler. */
io_removehandler(dev->base, 5,
hdc_read, NULL, NULL, hdc_write, NULL, NULL, dev);
/* Close all disks and their images. */
for (uint8_t d = 0; d < XTA_NUM; d++) {
drive = &dev->drives[d];
if (drive->present)
hdd_image_close(drive->hdd_num);
}
/* Release the device. */
free(dev);
}
const device_t ps1_hdc_device = {
.name = "PS/1 2011 Fixed Disk Controller",
.internal_name = "ps1_hdc",
.flags = DEVICE_ISA | DEVICE_PS2,
.local = 0,
.init = ps1_hdc_init,
.close = ps1_hdc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/*
* Very nasty.
*
* The PS/1 systems employ a feedback system where external
* cards let the system know they were 'addressed' by setting
* their Card Selected Flag (CSF) in register 0x0091. Driver
* software can test this register to see if they are talking
* to hardware or not.
*
* This means, that we must somehow do the same, and yes, I
* agree that the current solution is nasty.
*/
void
ps1_hdc_inform(void *priv, uint8_t *reg_91)
{
hdc_t *dev = (hdc_t *) priv;
dev->reg_91 = reg_91;
}
``` | /content/code_sandbox/src/machine/m_ps1_hdc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 12,659 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Commodore PC3 system.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/fdc_ext.h>
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/serial.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
static serial_t *cmd_uart;
static void
cbm_io_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
{
lpt1_remove();
lpt2_remove();
switch (val & 3) {
case 1:
lpt1_init(LPT_MDA_ADDR);
break;
case 2:
lpt1_init(LPT1_ADDR);
break;
case 3:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
switch (val & 0xc) {
case 0x4:
serial_setup(cmd_uart, COM2_ADDR, COM2_IRQ);
break;
case 0x8:
serial_setup(cmd_uart, COM1_ADDR, COM1_IRQ);
break;
default:
break;
}
}
static void
cbm_io_init(void)
{
io_sethandler(0x0230, 0x0001, NULL, NULL, NULL, cbm_io_write, NULL, NULL, NULL);
}
int
machine_at_cmdpc_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/cmdpc30/commodore pc 30 iii even.bin",
"roms/machines/cmdpc30/commodore pc 30 iii odd.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_at_init(model);
mem_remap_top(384);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
cmd_uart = device_add(&ns8250_device);
cbm_io_init();
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_commodore.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 762 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the IBM PCjr.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/cassette.h>
#include <86box/io.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/gameport.h>
#include <86box/serial.h>
#include <86box/keyboard.h>
#include <86box/rom.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/snd_sn76489.h>
#include <86box/video.h>
#include <86box/vid_cga_comp.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
#define PCJR_RGB 0
#define PCJR_COMPOSITE 1
#define STAT_PARITY 0x80
#define STAT_RTIMEOUT 0x40
#define STAT_TTIMEOUT 0x20
#define STAT_LOCK 0x10
#define STAT_CD 0x08
#define STAT_SYSFLAG 0x04
#define STAT_IFULL 0x02
#define STAT_OFULL 0x01
typedef struct pcjr_t {
/* Video Controller stuff. */
mem_mapping_t mapping;
uint8_t crtc[32];
int crtcreg;
int array_index;
uint8_t array[32];
int array_ff;
int memctrl;
uint8_t stat;
int addr_mode;
uint8_t *vram;
uint8_t *b8000;
int linepos;
int displine;
int sc;
int vc;
int dispon;
int con;
int coff;
int cursoron;
int blink;
int vsynctime;
int fullchange;
int vadj;
uint16_t ma;
uint16_t maback;
uint64_t dispontime;
uint64_t dispofftime;
pc_timer_t timer;
int firstline;
int lastline;
int composite;
/* Keyboard Controller stuff. */
int latched;
int data;
int serial_data[44];
int serial_pos;
uint8_t pa;
uint8_t pb;
pc_timer_t send_delay_timer;
} pcjr_t;
static video_timings_t timing_dram = { VIDEO_BUS, 0, 0, 0, 0, 0, 0 }; /*No additional waitstates*/
static uint8_t crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f,
0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static uint8_t key_queue[16];
static int key_queue_start = 0;
static int key_queue_end = 0;
static void
recalc_address(pcjr_t *pcjr)
{
uint8_t masked_memctrl = pcjr->memctrl;
/* According to the Technical Reference, bits 2 and 5 are
ignored if there is only 64k of RAM and there are only
4 pages. */
if (mem_size < 128)
masked_memctrl &= ~0x24;
if ((pcjr->memctrl & 0xc0) == 0xc0) {
pcjr->vram = &ram[(masked_memctrl & 0x06) << 14];
pcjr->b8000 = &ram[(masked_memctrl & 0x30) << 11];
} else {
pcjr->vram = &ram[(masked_memctrl & 0x07) << 14];
pcjr->b8000 = &ram[(masked_memctrl & 0x38) << 11];
}
}
static void
recalc_timings(pcjr_t *pcjr)
{
double _dispontime;
double _dispofftime;
double disptime;
if (pcjr->array[0] & 1) {
disptime = pcjr->crtc[0] + 1;
_dispontime = pcjr->crtc[1];
} else {
disptime = (pcjr->crtc[0] + 1) << 1;
_dispontime = pcjr->crtc[1] << 1;
}
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
pcjr->dispontime = (uint64_t) (_dispontime);
pcjr->dispofftime = (uint64_t) (_dispofftime);
}
static int
vid_get_h_overscan_size(pcjr_t *pcjr)
{
int ret;
if (pcjr->array[0] & 1)
ret = 128;
else
ret = 256;
return ret;
}
static void
vid_out(uint16_t addr, uint8_t val, void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
uint8_t old;
switch (addr) {
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
pcjr->crtcreg = val & 0x1f;
return;
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
old = pcjr->crtc[pcjr->crtcreg];
pcjr->crtc[pcjr->crtcreg] = val & crtcmask[pcjr->crtcreg];
if (pcjr->crtcreg == 2)
overscan_x = vid_get_h_overscan_size(pcjr);
if (old != val) {
if (pcjr->crtcreg < 0xe || pcjr->crtcreg > 0x10) {
pcjr->fullchange = changeframecount;
recalc_timings(pcjr);
}
}
return;
case 0x3da:
if (!pcjr->array_ff)
pcjr->array_index = val & 0x1f;
else {
if (pcjr->array_index & 0x10)
val &= 0x0f;
pcjr->array[pcjr->array_index & 0x1f] = val;
if (!(pcjr->array_index & 0x1f))
update_cga16_color(val);
}
pcjr->array_ff = !pcjr->array_ff;
break;
case 0x3df:
pcjr->memctrl = val;
pcjr->pa = val; /* The PCjr BIOS expects the value written to 3DF to
then be readable from port 60, others it errors out
with only 64k RAM set (but somehow, still works with
128k or more RAM). */
pcjr->addr_mode = val >> 6;
recalc_address(pcjr);
break;
default:
break;
}
}
static uint8_t
vid_in(uint16_t addr, void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
ret = pcjr->crtcreg;
break;
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
ret = pcjr->crtc[pcjr->crtcreg];
break;
case 0x3da:
pcjr->array_ff = 0;
pcjr->stat ^= 0x10;
ret = pcjr->stat;
break;
default:
break;
}
return ret;
}
static void
vid_write(uint32_t addr, uint8_t val, void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
if (pcjr->memctrl == -1)
return;
pcjr->b8000[addr & 0x3fff] = val;
}
static uint8_t
vid_read(uint32_t addr, void *priv)
{
const pcjr_t *pcjr = (pcjr_t *) priv;
if (pcjr->memctrl == -1)
return 0xff;
return (pcjr->b8000[addr & 0x3fff]);
}
static int
vid_get_h_overscan_delta(pcjr_t *pcjr)
{
int def;
int coef;
int ret;
switch ((pcjr->array[0] & 0x13) | ((pcjr->array[3] & 0x08) << 5)) {
case 0x13: /*320x200x16*/
def = 0x56;
coef = 8;
break;
case 0x12: /*160x200x16*/
def = 0x2b;
coef = 16;
break;
case 0x03: /*640x200x4*/
def = 0x56;
coef = 8;
break;
case 0x01: /*80 column text*/
def = 0x5a;
coef = 8;
break;
case 0x00: /*40 column text*/
default:
def = 0x2c;
coef = 16;
break;
case 0x02: /*320x200x4*/
def = 0x2b;
coef = 16;
break;
case 0x102: /*640x200x2*/
def = 0x2b;
coef = 16;
break;
}
ret = pcjr->crtc[0x02] - def;
if (ret < -8)
ret = -8;
if (ret > 8)
ret = 8;
return ret * coef;
}
static void
vid_blit_h_overscan(pcjr_t *pcjr)
{
int cols;
int i;
int x;
int y = (pcjr->lastline << 1) + 16;
int ho_s = vid_get_h_overscan_size(pcjr);
if (pcjr->dispon)
cols = (pcjr->array[2] & 0xf) + 16;
else {
if (pcjr->array[3] & 4)
cols = (pcjr->array[2] & 0xf) + 16;
else
cols = pcjr->array[0 + 16] + 16;
}
if (pcjr->array[0] & 1)
x = (pcjr->crtc[1] << 3) + ho_s;
else
x = (pcjr->crtc[1] << 4) + ho_s;
for (i = 0; i < 16; i++) {
hline(buffer32, 0, i, x, cols);
hline(buffer32, 0, y + i, x, cols);
if (pcjr->composite) {
Composite_Process(pcjr->array[0], 0, x >> 2, buffer32->line[i]);
Composite_Process(pcjr->array[0], 0, x >> 2, buffer32->line[y + i]);
} else {
video_process_8(x, i);
video_process_8(x, y + i);
}
}
}
static void
vid_poll(void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
uint16_t ca = (pcjr->crtc[15] | (pcjr->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint16_t dat;
int cols[4];
int oldsc;
int l = (pcjr->displine << 1) + 16;
int ho_s = vid_get_h_overscan_size(pcjr);
int ho_d = vid_get_h_overscan_delta(pcjr) + (ho_s / 2);
if (!pcjr->linepos) {
timer_advance_u64(&pcjr->timer, pcjr->dispofftime);
pcjr->stat &= ~1;
pcjr->linepos = 1;
oldsc = pcjr->sc;
if ((pcjr->crtc[8] & 3) == 3)
pcjr->sc = (pcjr->sc << 1) & 7;
if (pcjr->dispon) {
uint16_t offset = 0;
uint16_t mask = 0x1fff;
if (pcjr->displine < pcjr->firstline) {
pcjr->firstline = pcjr->displine;
video_wait_for_buffer();
}
pcjr->lastline = pcjr->displine;
cols[0] = (pcjr->array[2] & 0xf) + 16;
if (pcjr->array[0] & 1) {
hline(buffer32, 0, l, (pcjr->crtc[1] << 3) + ho_s, cols[0]);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 3) + ho_s, cols[0]);
} else {
hline(buffer32, 0, l, (pcjr->crtc[1] << 4) + ho_s, cols[0]);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 4) + ho_s, cols[0]);
}
switch (pcjr->addr_mode) {
case 0: /*Alpha*/
offset = 0;
mask = 0x3fff;
break;
case 1: /*Low resolution graphics*/
offset = (pcjr->sc & 1) * 0x2000;
break;
case 3: /*High resolution graphics*/
offset = (pcjr->sc & 3) * 0x2000;
break;
default:
break;
}
switch ((pcjr->array[0] & 0x13) | ((pcjr->array[3] & 0x08) << 5)) {
case 0x13: /*320x200x16*/
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 3) + ho_d;
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
buffer32->line[l][ef_x] = buffer32->line[l][ef_x + 1] =
buffer32->line[l + 1][ef_x] = buffer32->line[l + 1][ef_x + 1] =
pcjr->array[((dat >> 12) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 2] = buffer32->line[l][ef_x + 3] =
buffer32->line[l + 1][ef_x + 2] = buffer32->line[l + 1][ef_x + 3] =
pcjr->array[((dat >> 8) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 4] = buffer32->line[l][ef_x + 5] =
buffer32->line[l + 1][ef_x + 4] = buffer32->line[l + 1][ef_x + 5] =
pcjr->array[((dat >> 4) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 6] = buffer32->line[l][ef_x + 7] =
buffer32->line[l + 1][ef_x + 6] = buffer32->line[l + 1][ef_x + 7] =
pcjr->array[(dat & pcjr->array[1] & 0x0f) + 16] + 16;
}
break;
case 0x12: /*160x200x16*/
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 4) + ho_d;
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
buffer32->line[l][ef_x] = buffer32->line[l][ef_x + 1] =
buffer32->line[l][ef_x + 2] = buffer32->line[l][ef_x + 3] =
buffer32->line[l + 1][ef_x] = buffer32->line[l + 1][ef_x + 1] =
buffer32->line[l + 1][ef_x + 2] = buffer32->line[l + 1][ef_x + 3] =
pcjr->array[((dat >> 12) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 4] = buffer32->line[l][ef_x + 5] =
buffer32->line[l][ef_x + 6] = buffer32->line[l][ef_x + 7] =
buffer32->line[l + 1][ef_x + 4] = buffer32->line[l + 1][ef_x + 5] =
buffer32->line[l + 1][ef_x + 6] = buffer32->line[l + 1][ef_x + 7] =
pcjr->array[((dat >> 8) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 8] = buffer32->line[l][ef_x + 9] =
buffer32->line[l][ef_x + 10] = buffer32->line[l][ef_x + 11] =
buffer32->line[l + 1][ef_x + 8] = buffer32->line[l + 1][ef_x + 9] =
buffer32->line[l + 1][ef_x + 10] = buffer32->line[l + 1][ef_x + 11] =
pcjr->array[((dat >> 4) & pcjr->array[1] & 0x0f) + 16] + 16;
buffer32->line[l][ef_x + 12] = buffer32->line[l][ef_x + 13] =
buffer32->line[l][ef_x + 14] = buffer32->line[l][ef_x + 15] =
buffer32->line[l + 1][ef_x + 12] = buffer32->line[l + 1][ef_x + 13] =
buffer32->line[l + 1][ef_x + 14] = buffer32->line[l + 1][ef_x + 15] =
pcjr->array[(dat & pcjr->array[1] & 0x0f) + 16] + 16;
}
break;
case 0x03: /*640x200x4*/
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 3) + ho_d;
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset];
pcjr->ma++;
for (uint8_t c = 0; c < 8; c++) {
chr = (dat >> 7) & 1;
chr |= ((dat >> 14) & 2);
buffer32->line[l][ef_x + c] = buffer32->line[l + 1][ef_x + c] =
pcjr->array[(chr & pcjr->array[1] & 0x0f) + 16] + 16;
dat <<= 1;
}
}
break;
case 0x01: /*80 column text*/
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 3) + ho_d;
chr = pcjr->vram[((pcjr->ma << 1) & mask) + offset];
attr = pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
drawcursor = ((pcjr->ma == ca) && pcjr->con && pcjr->cursoron);
if (pcjr->array[3] & 4) {
cols[1] = pcjr->array[((attr & 15) & pcjr->array[1] & 0x0f) + 16] + 16;
cols[0] = pcjr->array[(((attr >> 4) & 7) & pcjr->array[1] & 0x0f) + 16] + 16;
if ((pcjr->blink & 16) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = pcjr->array[((attr & 15) & pcjr->array[1] & 0x0f) + 16] + 16;
cols[0] = pcjr->array[((attr >> 4) & pcjr->array[1] & 0x0f) + 16] + 16;
}
if (pcjr->sc & 8)
for (uint8_t c = 0; c < 8; c++)
buffer32->line[l][ef_x + c] =
buffer32->line[l + 1][ef_x + c] = cols[0];
else
for (uint8_t c = 0; c < 8; c++)
buffer32->line[l][ef_x + c] =
buffer32->line[l + 1][ef_x + c] =
cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
if (drawcursor)
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[l][ef_x + c] ^= 15;
buffer32->line[l + 1][ef_x + c] ^= 15;
}
pcjr->ma++;
}
break;
case 0x00: /*40 column text*/
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 4) + ho_d;
chr = pcjr->vram[((pcjr->ma << 1) & mask) + offset];
attr = pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
drawcursor = ((pcjr->ma == ca) && pcjr->con && pcjr->cursoron);
if (pcjr->array[3] & 4) {
cols[1] = pcjr->array[((attr & 15) & pcjr->array[1] & 0x0f) + 16] + 16;
cols[0] = pcjr->array[(((attr >> 4) & 7) & pcjr->array[1] & 0x0f) + 16] + 16;
if ((pcjr->blink & 16) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = pcjr->array[((attr & 15) & pcjr->array[1] & 0x0f) + 16] + 16;
cols[0] = pcjr->array[((attr >> 4) & pcjr->array[1] & 0x0f) + 16] + 16;
}
pcjr->ma++;
if (pcjr->sc & 8)
for (uint8_t c = 0; c < 8; c++)
buffer32->line[l][ef_x + (c << 1)] =
buffer32->line[l][ef_x + (c << 1) + 1] =
buffer32->line[l + 1][ef_x + (c << 1)] =
buffer32->line[l + 1][ef_x + (c << 1) + 1] = cols[0];
else
for (uint8_t c = 0; c < 8; c++)
buffer32->line[l][ef_x + (c << 1)] =
buffer32->line[l][ef_x + (c << 1) + 1] =
buffer32->line[l + 1][ef_x + (c << 1)] =
buffer32->line[l + 1][ef_x + (c << 1) + 1] =
cols[(fontdat[chr][pcjr->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
if (drawcursor)
for (uint8_t c = 0; c < 16; c++) {
buffer32->line[l][ef_x + c] ^= 15;
buffer32->line[l + 1][ef_x + c] ^= 15;
}
}
break;
case 0x02: /*320x200x4*/
cols[0] = pcjr->array[0 + 16] + 16;
cols[1] = pcjr->array[1 + 16] + 16;
cols[2] = pcjr->array[2 + 16] + 16;
cols[3] = pcjr->array[3 + 16] + 16;
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 4) + ho_d;
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[l][ef_x + (c << 1)] =
buffer32->line[l][ef_x + (c << 1) + 1] =
buffer32->line[l + 1][ef_x + (c << 1)] =
buffer32->line[l + 1][ef_x + (c << 1) + 1] = cols[dat >> 14];
dat <<= 2;
}
}
break;
case 0x102: /*640x200x2*/
cols[0] = pcjr->array[0 + 16] + 16;
cols[1] = pcjr->array[1 + 16] + 16;
for (x = 0; x < pcjr->crtc[1]; x++) {
int ef_x = (x << 4) + ho_d;
dat = (pcjr->vram[((pcjr->ma << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->ma << 1) & mask) + offset + 1];
pcjr->ma++;
for (uint8_t c = 0; c < 16; c++) {
buffer32->line[l][ef_x + c] = buffer32->line[l + 1][ef_x + c] =
cols[dat >> 15];
dat <<= 1;
}
}
break;
default:
break;
}
} else {
if (pcjr->array[3] & 4) {
if (pcjr->array[0] & 1) {
hline(buffer32, 0, l, (pcjr->crtc[1] << 3) + ho_s, (pcjr->array[2] & 0xf) + 16);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 3) + ho_s, (pcjr->array[2] & 0xf) + 16);
} else {
hline(buffer32, 0, l, (pcjr->crtc[1] << 4) + ho_s, (pcjr->array[2] & 0xf) + 16);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 4) + ho_s, (pcjr->array[2] & 0xf) + 16);
}
} else {
cols[0] = pcjr->array[0 + 16] + 16;
if (pcjr->array[0] & 1) {
hline(buffer32, 0, l, (pcjr->crtc[1] << 3) + ho_s, cols[0]);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 3) + ho_s, cols[0]);
} else {
hline(buffer32, 0, l, (pcjr->crtc[1] << 4) + ho_s, cols[0]);
hline(buffer32, 0, l + 1, (pcjr->crtc[1] << 4) + ho_s, cols[0]);
}
}
}
if (pcjr->array[0] & 1)
x = (pcjr->crtc[1] << 3) + ho_s;
else
x = (pcjr->crtc[1] << 4) + ho_s;
if (pcjr->composite) {
Composite_Process(pcjr->array[0], 0, x >> 2, buffer32->line[l]);
Composite_Process(pcjr->array[0], 0, x >> 2, buffer32->line[l + 1]);
} else {
video_process_8(x, l);
video_process_8(x, l + 1);
}
pcjr->sc = oldsc;
if (pcjr->vc == pcjr->crtc[7] && !pcjr->sc) {
pcjr->stat |= 8;
}
pcjr->displine++;
if (pcjr->displine >= 360)
pcjr->displine = 0;
} else {
timer_advance_u64(&pcjr->timer, pcjr->dispontime);
if (pcjr->dispon)
pcjr->stat |= 1;
pcjr->linepos = 0;
if (pcjr->vsynctime) {
pcjr->vsynctime--;
if (!pcjr->vsynctime) {
pcjr->stat &= ~8;
}
}
if (pcjr->sc == (pcjr->crtc[11] & 31) || ((pcjr->crtc[8] & 3) == 3 && pcjr->sc == ((pcjr->crtc[11] & 31) >> 1))) {
pcjr->con = 0;
pcjr->coff = 1;
}
if (pcjr->vadj) {
pcjr->sc++;
pcjr->sc &= 31;
pcjr->ma = pcjr->maback;
pcjr->vadj--;
if (!pcjr->vadj) {
pcjr->dispon = 1;
pcjr->ma = pcjr->maback = (pcjr->crtc[13] | (pcjr->crtc[12] << 8)) & 0x3fff;
pcjr->sc = 0;
}
} else if (pcjr->sc == pcjr->crtc[9] || ((pcjr->crtc[8] & 3) == 3 && pcjr->sc == (pcjr->crtc[9] >> 1))) {
pcjr->maback = pcjr->ma;
pcjr->sc = 0;
oldvc = pcjr->vc;
pcjr->vc++;
pcjr->vc &= 127;
if (pcjr->vc == pcjr->crtc[6])
pcjr->dispon = 0;
if (oldvc == pcjr->crtc[4]) {
pcjr->vc = 0;
pcjr->vadj = pcjr->crtc[5];
if (!pcjr->vadj)
pcjr->dispon = 1;
if (!pcjr->vadj)
pcjr->ma = pcjr->maback = (pcjr->crtc[13] | (pcjr->crtc[12] << 8)) & 0x3fff;
if ((pcjr->crtc[10] & 0x60) == 0x20)
pcjr->cursoron = 0;
else
pcjr->cursoron = pcjr->blink & 16;
}
if (pcjr->vc == pcjr->crtc[7]) {
pcjr->dispon = 0;
pcjr->displine = 0;
pcjr->vsynctime = 16;
picint(1 << 5);
if (pcjr->crtc[7]) {
if (pcjr->array[0] & 1)
x = (pcjr->crtc[1] << 3) + ho_s;
else
x = (pcjr->crtc[1] << 4) + ho_s;
pcjr->lastline++;
xs_temp = x;
ys_temp = (pcjr->lastline - pcjr->firstline) << 1;
if ((xs_temp > 0) && (ys_temp > 0)) {
int actual_ys = ys_temp;
if (xs_temp < 64)
xs_temp = 656;
if (ys_temp < 32)
ys_temp = 400;
if (!enable_overscan)
xs_temp -= ho_s;
if ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get()) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 32 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
vid_blit_h_overscan(pcjr);
if (enable_overscan) {
video_blit_memtoscreen(0, pcjr->firstline << 1,
xsize, actual_ys + 32);
} else {
video_blit_memtoscreen(ho_s / 2, (pcjr->firstline << 1) + 16,
xsize, actual_ys);
}
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
}
pcjr->firstline = 1000;
pcjr->lastline = 0;
pcjr->blink++;
}
} else {
pcjr->sc++;
pcjr->sc &= 31;
pcjr->ma = pcjr->maback;
}
if (pcjr->sc == (pcjr->crtc[10] & 31) || ((pcjr->crtc[8] & 3) == 3 && pcjr->sc == ((pcjr->crtc[10] & 31) >> 1)))
pcjr->con = 1;
}
}
static void
kbd_write(uint16_t port, uint8_t val, void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
if ((port >= 0xa0) && (port <= 0xa7))
port = 0xa0;
switch (port) {
case 0x60:
pcjr->pa = val;
break;
case 0x61:
pcjr->pb = val;
if (cassette != NULL)
pc_cas_set_motor(cassette, (pcjr->pb & 0x08) == 0);
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
if (speaker_enable)
was_speaker_enable = 1;
pit_devs[0].set_gate(pit_devs[0].data, 2, val & 1);
sn76489_mute = speaker_mute = 1;
switch (val & 0x60) {
case 0x00:
speaker_mute = 0;
break;
case 0x60:
sn76489_mute = 0;
break;
default:
break;
}
break;
case 0xa0:
nmi_mask = val & 0x80;
pit_devs[0].set_using_timer(pit_devs[0].data, 1, !(val & 0x20));
break;
default:
break;
}
}
static uint8_t
kbd_read(uint16_t port, void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
uint8_t ret = 0xff;
if ((port >= 0xa0) && (port <= 0xa7))
port = 0xa0;
switch (port) {
case 0x60:
ret = pcjr->pa;
break;
case 0x61:
ret = pcjr->pb;
break;
case 0x62:
ret = (pcjr->latched ? 1 : 0);
ret |= 0x02; /* Modem card not installed */
if (mem_size < 128)
ret |= 0x08; /* 64k expansion card not installed */
if ((pcjr->pb & 0x08) || (cassette == NULL))
ret |= (ppispeakon ? 0x10 : 0);
else
ret |= (pc_cas_get_inp(cassette) ? 0x10 : 0);
ret |= (ppispeakon ? 0x10 : 0);
ret |= (ppispeakon ? 0x20 : 0);
ret |= (pcjr->data ? 0x40 : 0);
if (pcjr->data)
ret |= 0x40;
break;
case 0xa0:
pcjr->latched = 0;
ret = 0;
break;
default:
break;
}
return ret;
}
static void
kbd_poll(void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
int c;
int p = 0;
int key;
timer_advance_u64(&pcjr->send_delay_timer, 220 * TIMER_USEC);
if (key_queue_start != key_queue_end && !pcjr->serial_pos && !pcjr->latched) {
key = key_queue[key_queue_start];
key_queue_start = (key_queue_start + 1) & 0xf;
pcjr->latched = 1;
pcjr->serial_data[0] = 1; /*Start bit*/
pcjr->serial_data[1] = 0;
for (c = 0; c < 8; c++) {
if (key & (1 << c)) {
pcjr->serial_data[(c + 1) * 2] = 1;
pcjr->serial_data[(c + 1) * 2 + 1] = 0;
p++;
} else {
pcjr->serial_data[(c + 1) * 2] = 0;
pcjr->serial_data[(c + 1) * 2 + 1] = 1;
}
}
if (p & 1) { /*Parity*/
pcjr->serial_data[9 * 2] = 1;
pcjr->serial_data[9 * 2 + 1] = 0;
} else {
pcjr->serial_data[9 * 2] = 0;
pcjr->serial_data[9 * 2 + 1] = 1;
}
for (c = 0; c < 11; c++) { /*11 stop bits*/
pcjr->serial_data[(c + 10) * 2] = 0;
pcjr->serial_data[(c + 10) * 2 + 1] = 0;
}
pcjr->serial_pos++;
}
if (pcjr->serial_pos) {
pcjr->data = pcjr->serial_data[pcjr->serial_pos - 1];
nmi = pcjr->data;
pcjr->serial_pos++;
if (pcjr->serial_pos == 42 + 1)
pcjr->serial_pos = 0;
}
}
static void
kbd_adddata(uint16_t val)
{
key_queue[key_queue_end] = val;
key_queue_end = (key_queue_end + 1) & 0xf;
}
static void
kbd_adddata_ex(uint16_t val)
{
kbd_adddata_process(val, kbd_adddata);
}
static void
speed_changed(void *priv)
{
pcjr_t *pcjr = (pcjr_t *) priv;
recalc_timings(pcjr);
}
void
pit_irq0_timer_pcjr(int new_out, int old_out, UNUSED(void *priv))
{
if (new_out && !old_out) {
picint(1);
pit_devs[0].ctr_clock(pit_devs[0].data, 1);
}
if (!new_out)
picintc(1);
}
static const device_config_t pcjr_config[] = {
// clang-format off
{
.name = "display_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = PCJR_RGB,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "RGB", .value = PCJR_RGB },
{ .description = "Composite", .value = PCJR_COMPOSITE },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t pcjr_device = {
.name = "IBM PCjr",
.internal_name = "pcjr",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = speed_changed,
.force_redraw = NULL,
.config = pcjr_config
};
int
machine_pcjr_init(UNUSED(const machine_t *model))
{
int display_type;
pcjr_t *pcjr;
int ret;
ret = bios_load_linear("roms/machines/ibmpcjr/bios.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
pcjr = malloc(sizeof(pcjr_t));
memset(pcjr, 0x00, sizeof(pcjr_t));
pcjr->memctrl = -1;
if (mem_size < 128)
pcjr->memctrl &= ~0x24;
display_type = machine_get_config_int("display_type");
pcjr->composite = (display_type != PCJR_RGB);
overscan_x = 256;
overscan_y = 32;
pic_init_pcjr();
pit_common_init(0, pit_irq0_timer_pcjr, NULL);
cpu_set();
/* Initialize the video controller. */
video_reset(gfxcard[0]);
loadfont("roms/video/mda/mda.rom", 0);
mem_mapping_add(&pcjr->mapping, 0xb8000, 0x08000,
vid_read, NULL, NULL,
vid_write, NULL, NULL, NULL, 0, pcjr);
io_sethandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, pcjr);
timer_add(&pcjr->timer, vid_poll, pcjr, 1);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_dram);
device_add_ex(&pcjr_device, pcjr);
cga_palette = 0;
cgapal_rebuild();
/* Initialize the keyboard. */
keyboard_scan = 1;
key_queue_start = key_queue_end = 0;
io_sethandler(0x0060, 4,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
io_sethandler(0x00a0, 8,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, pcjr);
timer_add(&pcjr->send_delay_timer, kbd_poll, pcjr, 1);
keyboard_set_table(scancode_xt);
keyboard_send = kbd_adddata_ex;
/* Technically it's the SN76496N, but the SN76489 is identical to the SN76496N. */
device_add(&sn76489_device);
nmi_mask = 0x80;
device_add(&fdc_pcjr_device);
device_add(&ns8250_pcjr_device);
serial_set_next_inst(SERIAL_MAX); /* So that serial_standalone_init() won't do anything. */
/* "All the inputs are 'read' with one 'IN' from address hex 201." - PCjr Technical Reference (Nov. 83), p.2-119
Note by Miran Grca: Meanwhile, the same Technical Reference clearly says that
the gameport is on ports 201-207. */
standalone_gameport_type = &gameport_201_device;
return ret;
}
``` | /content/code_sandbox/src/machine/m_pcjr.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,982 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 8 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/sio.h>
#include <86box/sound.h>
#include <86box/hwm.h>
#include <86box/spd.h>
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
int
machine_at_ap61_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap61/ap61r120.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x19, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORTHBRIDGE_SEC, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_IDE, 0xFE, 0xFF, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i450kx_device);
device_add(&sio_zb_device);
device_add(&ide_cmd646_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&fdc37c665_device);
device_add(&sst_flash_29ee010_device);
// device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p6rp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6rp4/OR6I0106.SMC",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&p6rp4_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x19, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORTHBRIDGE_SEC, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x04, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i450kx_device);
device_add(&sio_zb_device);
device_add(&ide_cmd646_device);
/* Input port bit 2 must be 1 or CMOS Setup is disabled. */
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_686nx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/686nx/6nx.140",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device); // Uses the AMIKEY keyboard controller
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_mb600n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mb600n/60915cs.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_acerv60n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv60n/V60NE5.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model,2 );
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&fdc37c935_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_lgibmx61_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/lgibmx61/bios.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
// device_add(&keyboard_ps2_ami_pci_device);
device_add(&keyboard_ps2_ami_device);
// device_add(&w83787f_device);
device_add(&w83877f_president_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_vs440fx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/vs440fx/1018CS1_.BIO",
"roms/machines/vs440fx/1018CS1_.BI1",
"roms/machines/vs440fx/1018CS1_.BI2",
"roms/machines/vs440fx/1018CS1_.BI3",
"roms/machines/vs440fx/1018CS1_.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&pc87307_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_gw2kvenus_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/gw2kvenus/1011CS1T.BIO",
"roms/machines/gw2kvenus/1011CS1T.BI1",
"roms/machines/gw2kvenus/1011CS1T.BI2",
"roms/machines/gw2kvenus/1011CS1T.BI3",
"roms/machines/gw2kvenus/1011CS1T.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&pc87307_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ap440fx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/ap440fx/1011CT1_.BIO",
"roms/machines/ap440fx/1011CT1_.BI1",
"roms/machines/ap440fx/1011CT1_.BI2",
"roms/machines/ap440fx/1011CT1_.BI3",
"roms/machines/ap440fx/1011CT1_.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87307_device);
device_add(&intel_flash_bxt_ami_device);
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cs4236b_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&s3_virge_375_onboard_pci_device);
return ret;
}
int
machine_at_8600ttc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/8600ttc/TTC0715B.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_m6mi_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m6mi/M6MI05.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&fdc37c935_device);
device_add(&intel_flash_bxt_device);
return ret;
}
void
machine_at_p65up5_common_init(const machine_t *model, const device_t *northbridge)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(northbridge);
device_add(&piix3_ioapic_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
device_add(&ioapic_device);
}
int
machine_at_p65up5_cp6nd_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p65up5/ND6I0218.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_p65up5_common_init(model, &i440fx_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket8.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,543 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of various Zenith PC compatible machines.
* Currently only the Zenith Data Systems Supersport is emulated.
*
*
*
* Authors: Tux,
* Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, <mariogplayer@gmail.com>
* EngiNerd <webmaster.crrc@yahoo.it>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/vid_cga.h>
#include <86box/plat_unused.h>
typedef struct {
mem_mapping_t scratchpad_mapping;
uint8_t *scratchpad_ram;
} zenith_t;
static uint8_t
zenith_scratchpad_read(uint32_t addr, void *priv)
{
const zenith_t *dev = (zenith_t *) priv;
return dev->scratchpad_ram[addr & 0x3fff];
}
static void
zenith_scratchpad_write(uint32_t addr, uint8_t val, void *priv)
{
zenith_t *dev = (zenith_t *) priv;
dev->scratchpad_ram[addr & 0x3fff] = val;
}
static void *
zenith_scratchpad_init(UNUSED(const device_t *info))
{
zenith_t *dev;
dev = (zenith_t *) malloc(sizeof(zenith_t));
memset(dev, 0x00, sizeof(zenith_t));
dev->scratchpad_ram = malloc(0x4000);
mem_mapping_add(&dev->scratchpad_mapping, 0xf0000, 0x4000,
zenith_scratchpad_read, NULL, NULL,
zenith_scratchpad_write, NULL, NULL,
dev->scratchpad_ram, MEM_MAPPING_EXTERNAL, dev);
return dev;
}
static void
zenith_scratchpad_close(void *priv)
{
zenith_t *dev = (zenith_t *) priv;
free(dev->scratchpad_ram);
free(dev);
}
static const device_t zenith_scratchpad_device = {
.name = "Zenith scratchpad RAM",
.internal_name = "zenith_scratchpad",
.flags = 0,
.local = 0,
.init = zenith_scratchpad_init,
.close = zenith_scratchpad_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
void
machine_zenith_init(const machine_t *model)
{
machine_common_init(model);
device_add(&zenith_scratchpad_device);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_zenith_device);
nmi_init();
}
/*
* Current bugs and limitations:
* - missing NVRAM implementation
*/
int
machine_xt_z184_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/zdsupers/z184m v3.1d.10d",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_zenith_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
lpt1_remove(); /* only one parallel port */
lpt2_remove();
lpt1_init(0x278);
device_add(&ns8250_device);
serial_set_next_inst(SERIAL_MAX); /* So that serial_standalone_init() won't do anything. */
device_add(&cga_device);
return ret;
}
int
machine_xt_z151_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/zdsz151/444-229-18.bin",
0x000fc000, 32768, 0);
if (ret) {
bios_load_aux_linear("roms/machines/zdsz151/444-260-18.bin",
0x000f8000, 16384, 0);
}
if (bios_only || !ret)
return ret;
machine_zenith_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_tandy_device);
return ret;
}
/*
* Current bugs and limitations:
* - Memory board support for EMS currently missing
*/
int
machine_xt_z159_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/zdsz159/z159m v2.9e.10d",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_zenith_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_tandy_device);
/* parallel port is on the memory board */
lpt1_remove(); /* only one parallel port */
lpt2_remove();
lpt1_init(0x278);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_zenith.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,353 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of the emulated machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/cassette.h>
#include <86box/cartridge.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/gameport.h>
#include "cpu.h"
#include <86box/video.h>
#include <86box/machine.h>
#include <86box/isamem.h>
#include <86box/pci.h>
#include <86box/plat_unused.h>
int bios_only = 0;
int machine;
// int AT, PCI;
#ifdef ENABLE_MACHINE_LOG
int machine_do_log = ENABLE_MACHINE_LOG;
static void
machine_log(const char *fmt, ...)
{
va_list ap;
if (machine_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define machine_log(fmt, ...)
#endif
static int
machine_init_ex(int m)
{
int ret = 0;
if (!bios_only) {
machine_log("Initializing as \"%s\"\n", machine_getname());
machine_init_p1();
machine_init_gpio();
machine_init_gpio_acpi();
machine_snd = NULL;
is_vpc = 0;
standalone_gameport_type = NULL;
gameport_instance_id = 0;
/* Set up the architecture flags. */
#if 0
AT = IS_AT(machine);
PCI = IS_ARCH(machine, MACHINE_BUS_PCI);
#endif
cpu_set();
pc_speed_changed();
/* Reset the memory state. */
mem_reset();
smbase = is_am486dxl ? 0x00060000 : 0x00030000;
lpt_init();
if (cassette_enable)
device_add(&cassette_device);
cart_reset();
/* Prepare some video-related things if we're using internal
or no video. */
video_pre_reset(gfxcard[0]);
/* Reset any ISA memory cards. */
isamem_reset();
/* Reset the fast off stuff. */
cpu_fast_off_reset();
pci_flags = 0x00000000;
}
/* All good, boot the machine! */
if (machines[m].init)
ret = machines[m].init(&machines[m]);
if (bios_only || !ret)
return ret;
video_post_reset();
return ret;
}
void
machine_init(void)
{
bios_only = 0;
(void) machine_init_ex(machine);
}
int
machine_available(int m)
{
int ret;
const device_t *dev = machine_get_device(m);
bios_only = 1;
ret = device_available(dev);
/* Do not check via machine_init_ex() if the device is not NULL and
it has a CONFIG_BIOS field. */
if ((dev == NULL) || (ret != -1))
ret = machine_init_ex(m);
bios_only = 0;
return !!ret;
}
void
pit_irq0_timer(int new_out, int old_out, UNUSED(void *priv))
{
if (new_out && !old_out)
picint(1);
if (!new_out)
picintc(1);
}
void
machine_common_init(UNUSED(const machine_t *model))
{
uint8_t cpu_requires_fast_pit = is486 || (!is286 && is8086 && (cpu_s->rspeed >= 8000000));
cpu_requires_fast_pit = cpu_requires_fast_pit && !cpu_16bitbus;
/* System devices first. */
pic_init();
dma_init();
int pit_type = IS_AT(machine) ? PIT_8254 : PIT_8253;
/* Select fast PIT if needed */
if (((pit_mode == -1) && cpu_requires_fast_pit) || (pit_mode == 1))
pit_type += 2;
pit_common_init(pit_type, pit_irq0_timer, NULL);
}
``` | /content/code_sandbox/src/machine/machine.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,042 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 5 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/sio.h>
#include <86box/video.h>
#include <86box/machine.h>
int
machine_at_plato_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/plato/1016ax1_.bio",
"roms/machines/plato/1016ax1_.bi1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, PCI_CAN_SWITCH_TYPE);
device_add(&i430nx_device);
return ret;
}
int
machine_at_dellplato_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/dellplato/1016AX1J.BIO",
"roms/machines/dellplato/1016AX1J.BI1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, PCI_CAN_SWITCH_TYPE);
device_add(&i430nx_device);
return ret;
}
int
machine_at_ambradp90_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ambradp90/1002AX1P.BIO",
"roms/machines/ambradp90/1002AX1P.BI1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, PCI_CAN_SWITCH_TYPE);
device_add(&i430nx_device);
return ret;
}
int
machine_at_586ip_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/586ip/IP.20",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&i430nx_device);
return ret;
}
int
machine_at_tek932_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tek932/B932_019.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2 | PCI_CAN_SWITCH_TYPE);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430nx_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_ide_device);
device_add(&ide_vlb_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_acerv30_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv30/V30R01N9.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&fdc37c665_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_apollo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/apollo/S728P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1995_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87332_398_device);
device_add(&intel_flash_bxt_device);
return ret;
}
static void
machine_at_zappa_gpio_init(void)
{
uint32_t gpio = 0xffffe6ff;
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: No Connect. */
/* Bit 1: No Connect. */
/* Bit 0: 2x multiplier, 1 = 1.5x multiplier (Switch 6). */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff00ff;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff08ff;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff10ff;
if (cpu_dmulti <= 1.5)
gpio |= 0xffff01ff;
else
gpio |= 0xffff00ff;
machine_set_gpio_default(gpio);
}
int
machine_at_zappa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/zappa/1006bs0_.bio",
"roms/machines/zappa/1006bs0_.bi1",
0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_zappa_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_powermatev_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/powermatev/BIOS.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_hawk_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hawk/HAWK.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_tg_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_pt2000_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficpt2000/PT2000_v1.01.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Should be VIA, but we do not emulate that yet. */
device_add(&keyboard_ps2_holtek_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87332_398_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_pat54pv_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pat54pv/PAT54PV.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti5x7_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_hot543_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot543/543_R21.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&opti5x7_pci_device);
device_add(&opti822_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ncselp90_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ncselp90/elegancep90.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&opti5x7_pci_device);
device_add(&opti822_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_opti611_vlb_device);
device_add(&fdc37c665_ide_sec_device);
device_add(&ide_vlb_2ch_device);
return ret;
}
int
machine_at_p54sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54sp4/SI5I0204.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
int
machine_at_sq588_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sq588/sq588b03.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Correct: 0D (01), 0F (02), 11 (03), 13 (04) */
pci_register_slot(0x02, PCI_CARD_IDE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_single_channel_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_ide_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_p54sps_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54sps/35s106.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_pci_2ch_device);
device_add(&keyboard_at_ami_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ms5109_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5109/A778.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 3, 2, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_550x_85c503_device);
device_add(&ide_w83769f_pci_device);
device_add(&keyboard_ps2_ami_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_torino_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/torino/PER113.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&sis_550x_85c503_device);
device_add(&ide_um8673f_device);
device_add(&keyboard_ps2_tg_ami_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_hot539_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot539/539_R17.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x15, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x16, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&umc_8890_device);
device_add(&umc_8886af_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8663af_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket5.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,764 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of 386DX and 486 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/dma.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/sio.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/port_92.h>
#include <86box/video.h>
#include <86box/flash.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/hwm.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
int
machine_at_acc386_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acc386/acc386.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&acc2168_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_asus386_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/asus386/ASUS_ISA-386C_BIOS.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&rabbit_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_tandy4000_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tandy4000/BIOS Tandy 4000 v1.03.01.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_sis401_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&sis_85c401_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
}
int
machine_at_sis401_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sis401/SIS401-2.AMI",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis401_common_init(model);
return ret;
}
int
machine_at_isa486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/isa486/ISA-486.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis401_common_init(model);
return ret;
}
int
machine_at_av4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/av4/amibios_486dx_isa_bios_aa4025963.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c460_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2 mouse
{
int ret;
ret = bios_load_linear("roms/machines/valuepoint433/$IMAGEP.FLH",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&sis_85c461_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&et4000w32_onboard_device);
device_add(&keyboard_ps2_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ecs386_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ecs386/AMI BIOS for ECS-386_32 motherboard - L chip.bin",
"roms/machines/ecs386/AMI BIOS for ECS-386_32 motherboard - H chip.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&cs8230_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_spc6000a_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/spc6000a/3c80.u27",
"roms/machines/spc6000a/9f80.u26",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 1);
device_add(&cs8230_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_ecs386v_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ecs386v/PANDA_386V.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1429_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_rycleopardlx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/rycleopardlx/486-RYC-Leopard-LX.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti283_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_486vchd_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486vchd/486-4386-VC-HD.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&via_vt82c49x_device);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_cs4031_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cs4031/CHIPS_1.AMI",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&cs4031_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_pb410a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pb410a/pb410a.080337.4abf.u25.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_ibm_common_ide_init(model);
device_add(&keyboard_ps2_device);
device_add(&acc3221_device);
device_add(&acc2168_device);
device_add(&phoenix_486_jumper_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&ht216_32_pb410a_device);
return ret;
}
int
machine_at_vect486vl_init(const machine_t *model) // has HDC problems
{
int ret;
ret = bios_load_linear("roms/machines/vect486vl/aa0500.ami",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&vl82c480_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&vl82c113_device);
device_add(&fdc37c651_ide_device);
return ret;
}
int
machine_at_d824_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/d824/fts-biosupdated824noflashbiosepromv320-320334-160.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&vl82c480_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&keyboard_ps2_device);
device_add(&ide_isa_device);
device_add(&fdc37c651_device);
return ret;
}
int
machine_at_acera1g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acera1g/4alo001.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1429g_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&ali5105_device);
device_add(&ide_ali5213_device);
return ret;
}
int
machine_at_acerv10_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv10/ALL.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c461_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&ide_isa_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_decpclpv_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/decpclpv/bios.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c461_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&s3_86c805_onboard_vlb_device);
/* TODO: Phoenix MultiKey KBC */
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_isa_2ch_device);
device_add(&fdc37c663_ide_device);
return ret;
}
static void
machine_at_ali1429_common_init(const machine_t *model, int is_green)
{
machine_at_common_init(model);
if (is_green)
device_add(&ali1429g_device);
else
device_add(&ali1429_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
}
int
machine_at_ali1429_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ali1429/ami486.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ali1429_common_init(model, 0);
return ret;
}
int
machine_at_winbios1429_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/win486/ali1429g.amw",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_ali1429_common_init(model, 1);
return ret;
}
int
machine_at_opti495_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/award495/opt495s.awa",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti495_device);
device_add(&keyboard_at_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_opti495_ami_common_init(const machine_t *model)
{
machine_at_common_init(model);
device_add(&opti495_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
}
int
machine_at_opti495_ami_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ami495/opt495sx.ami",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_opti495_ami_common_init(model);
return ret;
}
int
machine_at_opti495_mr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mr495/opt495sx.mr",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_opti495_ami_common_init(model);
return ret;
}
int
machine_at_exp4349_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/exp4349/biosdump.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1429g_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
static void
machine_at_403tg_common_init(const machine_t *model, int nvr_hack)
{
if (nvr_hack) {
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
} else
machine_at_common_init(model);
device_add(&opti895_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
}
int
machine_at_403tg_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/403tg/403TG.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 0);
return ret;
}
int
machine_at_403tg_d_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/403tg_d/J403TGRevD.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 1);
return ret;
}
int
machine_at_403tg_d_mr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/403tg_d/MRBiosOPT895.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_403tg_common_init(model, 0);
return ret;
}
int
machine_at_pb450_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pb450/OPTI802.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ide_vlb_2ch_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 5, 6, 7, 8);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&opti895_device);
device_add(&opti602_device);
device_add(&opti822_device);
device_add(&keyboard_ps2_phoenix_device);
device_add(&fdc37c665_ide_device);
device_add(&ide_opti611_vlb_sec_device);
device_add(&intel_flash_bxt_device);
device_add(&phoenix_486_jumper_pci_device);
return ret;
}
static void
machine_at_pc330_6573_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 2);
device_add(&ide_vlb_2ch_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 5, 6, 7, 8);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 9, 10, 11, 12);
/* This is a guess because the BIOS always gives it a video BIOS
and never gives it an IRQ, so it is impossible to known for
certain until we obtain PCI readouts from the real machine. */
pci_register_slot(0x0E, PCI_CARD_VIDEO, 13, 14, 15, 16);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&opti602_device);
device_add(&opti802g_device);
device_add(&opti822_device);
device_add(&keyboard_ps2_ami_device);
device_add(&fdc37c665_ide_device);
device_add(&ide_opti611_vlb_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_aptiva510_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/aptiva510/$IMAGES.USF",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_pc330_6573_common_init(model);
return ret;
}
int
machine_at_pc330_6573_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pc330_6573/$IMAGES.USF",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_pc330_6573_common_init(model);
return ret;
}
int
machine_at_mvi486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mvi486/MVI627.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti895_device);
device_add(&keyboard_at_device);
device_add(&pc87311_ide_device);
return ret;
}
static void
machine_at_sis_85c471_common_init(const machine_t *model)
{
machine_at_common_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&sis_85c471_device);
}
int
machine_at_ami471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ami471/SIS471BE.AMI",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_vli486sv2g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vli486sv2g/0402.001",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_dtk486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dtk486/4siw005.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_device);
return ret;
}
int
machine_at_px471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/px471/SIS471A1.PHO",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&ide_vlb_device);
device_add(&keyboard_at_device);
return ret;
}
int
machine_at_win471_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/win471/486-SiS_AC0360136.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_pci400ca_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pci400ca/486-AA008851.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SCSI, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_device);
device_add(&sio_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420tx_device);
device_add(&ncr53c810_onboard_pci_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_vi15g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vi15g/vi15gr23.rom",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_sis_85c471_common_init(model);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_greenb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/greenb/4gpv31-ami-1993-8273517.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&contaq_82c597_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_4gpv5_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/4gpv5/4GPV5.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&contaq_82c596a_device);
device_add(&keyboard_at_device);
return ret;
}
static void
machine_at_sis_85c496_common_init(UNUSED(const machine_t *model))
{
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
}
int
machine_at_r418_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/r418/r418i.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_pci_device);
return ret;
}
int
machine_at_m4li_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m4li/M4LI.04S",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_pci_device);
return ret;
}
int
machine_at_ls486e_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ls486e/LS486E RevC.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_ls486e_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
return ret;
}
int
machine_at_4dps_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/4dps/4DPS172G.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&w83787f_device);
device_add(&keyboard_ps2_ami_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_ms4144_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms4144/ms-4144-1.4.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_ls486e_device);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&w83787f_device);
device_add(&keyboard_at_ami_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_486sp3c_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486sp3c/SI4I0306.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_4saw2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/4saw2/4saw0911.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_sis_85c496_common_init(model);
device_add(&sis_85c496_device);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&w83787f_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_alfredo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/alfredo/1010AQ0_.BIO",
"roms/machines/alfredo/1010AQ0_.BI1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_device);
device_add(&fdc37c663_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420tx_device);
return ret;
}
int
machine_at_ninja_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ninja/1008AY0_.BIO",
"roms/machines/ninja/1008AY0_.BI1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 2, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 1, 2, 1);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420ex_device);
device_add(&i82091aa_device);
return ret;
}
int
machine_at_bat4ip3e_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/bat4ip3e/404C.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0xfe, 0xff, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 1, 2, 1);
pci_register_slot(0x0a, PCI_CARD_NORMAL, 1, 2, 1, 2);
device_add(&phoenix_486_jumper_pci_device);
device_add(&keyboard_ps2_pci_device);
device_add(&i420ex_device);
device_add(&ide_cmd640_pci_device);
device_add(&fdc37c665_device);
return ret;
}
int
machine_at_486pi_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486pi/486pi.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 2, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 1, 2);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&i420ex_device);
return ret;
}
int
machine_at_sb486p_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sb486p/amiboot.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 2, 1);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i82091aa_device);
device_add(&i420ex_device);
return ret;
}
int
machine_at_486sp3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486sp3/awsi2737.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_isa_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SCSI, 1, 2, 3, 4); /* 01 = SCSI */
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 03 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 05 = Slot 3 */
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device); /* Uses the AMIKEY KBC */
device_add(&sio_device);
device_add(&fdc37c663_ide_device);
device_add(&sst_flash_29ee010_device);
device_add(&i420tx_device);
device_add(&ncr53c810_onboard_pci_device);
return ret;
}
int
machine_at_amis76_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/s76p/S76P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
// pci_register_slot(0x01, PCI_CARD_IDE, 1, 2, 3 ,4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i420tx_device);
// device_add(&ide_cmd640_pci_device); /* is this actually cmd640? is it single channel? */
device_add(&ide_pci_device);
return ret;
}
int
machine_at_pci400cb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pci400cb/032295.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 3, 2, 1); /* 0F = Slot 1 */
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 0E = Slot 2 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 0D = Slot 3 */
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 0C = Slot 4 */
device_add(&keyboard_ps2_ami_pci_device); /* Assume AMI Megakey 1993 standalone ('P')
because of the Tekram machine below. */
device_add(&ims8848_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_g486ip_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/g486ip/G486IP.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1992_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 03 = Slot 1 */
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 05 = Slot 3 */
device_add(&keyboard_ps2_ami_pci_device); /* AMI Megakey 1993 stanalone ('P') */
device_add(&ims8848_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_486sp3g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486sp3g/PCI-I-486SP3G_0306.001 (Beta).bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_isa_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SCSI, 1, 2, 3, 4); /* 01 = SCSI */
pci_register_slot(0x06, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 06 = Slot 1 */
pci_register_slot(0x05, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 05 = Slot 2 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 04 = Slot 3 */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device); /* Uses the AMIKEY KBC */
device_add(&sio_zb_device);
device_add(&pc87332_398_ide_device);
device_add(&sst_flash_29ee010_device);
device_add(&i420zx_device);
device_add(&ncr53c810_onboard_pci_device);
return ret;
}
int
machine_at_486ap4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486ap4/0205.002",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
/* Excluded: 5, 6, 7, 8 */
pci_register_slot(0x05, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 09 = Slot 1 */
pci_register_slot(0x0a, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 0a = Slot 2 */
pci_register_slot(0x0b, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 0b = Slot 3 */
pci_register_slot(0x0c, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 0c = Slot 4 */
device_add(&keyboard_ps2_ami_pci_device); /* Uses the AMIKEY KBC */
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&i420ex_device);
return ret;
}
int
machine_at_g486vpa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/g486vpa/3.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&via_vt82c49x_pci_ide_device);
device_add(&via_vt82c505_device);
device_add(&pc87332_398_ide_sec_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_486vipio2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/486vipio2/1175G701.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&via_vt82c49x_pci_ide_device);
device_add(&via_vt82c505_device);
device_add(&w83787f_ide_sec_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_abpb4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/abpb4/486-AB-PB4.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CAN_SWITCH_TYPE);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1489_device);
device_add(&w83787f_device);
device_add(&keyboard_at_device);
#if 0
device_add(&intel_flash_bxt_device);
#endif
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_win486pci_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/win486pci/v1hj3.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1489_device);
device_add(&prime3b_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_ms4145_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms4145/AG56S.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&ali1489_device);
device_add(&w83787f_device);
device_add(&keyboard_at_ami_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_sbc490_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sbc490/07159589.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_VIDEO, 4, 1, 2, 3);
device_add(&ali1489_device);
device_add(&fdc37c665_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&tgui9440_onboard_pci_device);
device_add(&keyboard_ps2_ami_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_tf486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tf486/tf486v10.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1489_device);
device_add(&w83977ef_device);
device_add(&keyboard_at_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_arb1476_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/arb1476/w1476b.v21",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
device_add(&ali1489_device);
device_add(&fdc37c669_device);
device_add(&keyboard_ps2_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_itoxstar_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/itoxstar/STARA.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_client_device);
device_add(&sst_flash_29ee020_device);
device_add(&w83781d_device); /* fans: Chassis, CPU, unused; temperatures: Chassis, CPU, unused */
hwm_values.fans[2] = 0; /* unused */
hwm_values.temperatures[2] = 0; /* unused */
hwm_values.voltages[0] = 0; /* Vcore unused */
return ret;
}
int
machine_at_arb1423c_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/arb1423c/A1423C.v12",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 0, 0, 0);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_consumer2_device);
device_add(&winbond_flash_w29c020_device);
return ret;
}
int
machine_at_arb1479_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/arb1479/1479A.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 0, 0, 0);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_consumer2_device);
device_add(&winbond_flash_w29c020_device);
return ret;
}
int
machine_at_iach488_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/iach488/FH48800B.980",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&w83977f_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_consumer2_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pcm9340_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pcm9340/9340v110.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x1D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x1E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x1F, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add_inst(&w83977f_device, 1);
device_add_inst(&w83977f_device, 2);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_elite_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pcm5330_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pcm5330/5330_13b.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x0B, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_SOUTHBRIDGE_IDE, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&stpc_serial_device);
device_add(&w83977f_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&stpc_atlas_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_ecs486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ecs486/8810AIO.32J",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886f_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_ps2_ami_device);
return ret;
}
int
machine_at_hot433a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot433/433AUS33.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&umc_hb4_device);
device_add(&umc_8886bf_device);
device_add(&um8669f_device);
device_add(&winbond_flash_w29c010_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_atc1415_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc1415/1415V330.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886bf_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_actionpc2600_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/actionpc2600/action2600.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 3);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_VIDEO, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&umc_hb4_device);
device_add(&umc_8886bf_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_ps2_tg_ami_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&tgui9440_onboard_pci_device);
return ret;
}
int
machine_at_actiontower8400_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/actiontower8400/V31C.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x15, PCI_CARD_VIDEO, 0, 0, 0, 0);
pci_register_slot(0x16, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&umc_hb4_device);
device_add(&umc_8886f_device);
device_add(&fdc37c665_device);
device_add(&ide_cmd640_pci_device);
device_add(&intel_flash_bxt_device); // The ActionPC 2600 has this so I'm gonna assume this does too.
device_add(&keyboard_ps2_ami_pci_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5430_onboard_pci_device);
return ret;
}
int
machine_at_m919_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m919/9190914s.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device); /* AF is correct - the BIOS does IDE writes to ports 108h and 109h. */
device_add(&um8663bf_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_spc7700plw_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/spc7700plw/77LW13FH.P24",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_ps2_ami_device);
return ret;
}
int
machine_at_ms4134_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms4134/4alm001.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&ali1429g_device);
device_add(&fdc37c665_ide_pri_device);
pci_init(FLAG_MECHANISM_1 | FLAG_MECHANISM_2 | PCI_ALWAYS_EXPOSE_DEV0);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_SCSI, 4, 1, 2, 3);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1435_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_ps2_ami_device);
return ret;
}
int
machine_at_tg486gp_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tg486gp/tg486gp.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_ide_init(model);
device_add(&ali1429g_device);
device_add(&fdc37c665_ide_pri_device);
pci_init(FLAG_MECHANISM_1 | FLAG_MECHANISM_2 | PCI_ALWAYS_EXPOSE_DEV0);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1435_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_ps2_tg_ami_device);
return ret;
}
int
machine_at_tg486g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tg486g/tg486g.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c471_device);
device_add(&ide_isa_device);
device_add(&fdc37c651_ide_device);
device_add(&keyboard_ps2_tg_ami_pci_device);
if (gfxcard[0] != VID_INTERNAL) {
for (uint16_t i = 0; i < 32768; i++)
rom[i] = mem_readb_phys(0x000c0000 + i);
}
mem_mapping_set_addr(&bios_mapping, 0x0c0000, 0x40000);
mem_mapping_set_exec(&bios_mapping, rom);
return ret;
}
int
machine_at_dvent4xx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dvent4xx/Venturis466_BIOS.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&sis_85c471_device);
device_add(&ide_cmd640_vlb_pri_device);
device_add(&fdc37c665_ide_device);
device_add(&keyboard_ps2_phoenix_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
return ret;
}
int
machine_at_ecsal486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ecsal486/ECS_AL486.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1429g_device);
device_add(&keyboard_ps2_ami_pci_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ap4100aa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap4100aa/M27C512DIP28.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
device_add(&ali1429g_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_vlb_device);
device_add(&um8663bf_device);
return ret;
}
int
machine_at_atc1762_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc1762/atc1762.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ali1429g_device);
device_add(&keyboard_ps2_ami_pci_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_dataexpert386wb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dataexpert386wb/st0386-wb-ver2-0-618f078c738cb397184464.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti391_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_genoa486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/genoa486/AMI486.BIO",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&compaq_genoa_device);
device_add(&port_92_key_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_ga486l_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ga486l/ga-486l_bios.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti381_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_cougar_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cougar/COUGRMRB.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_vlb_device);
device_add(&opti499_device);
device_add(&fdc37c665_ide_pri_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_386dx_486.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 19,174 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Amstrad series of PC's: PC1512, PC1640 and
* PC200, including their keyboard, mouse and video devices, as
* well as the PC2086 and PC3086 systems.
*
* PC1512: The PC1512 extends CGA with a bit-planar 640x200x16 mode.
* Most CRTC registers are fixed.
*
* The Technical Reference Manual lists the video waitstate
* time as between 12 and 46 cycles. We currently always use
* the lower number.
*
* PC1640: Mostly standard EGA, but with CGA & Hercules emulation.
*
* PC200: CGA with some NMI stuff. But we don't need that as it's only
* used for TV and LCD displays, and we're emulating a CRT.
*
* PPC512/640: Portable with both CGA-compatible and MDA-compatible monitors.
*
* TODO: This module is not complete yet:
*
* All models: The internal mouse controller does not work correctly with
* version 7.04 of the mouse driver.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* John Elliott, <jce@seasip.info>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/ppi.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/mouse.h>
#include <86box/gameport.h>
#include <86box/lpt.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_ega.h>
#include <86box/vid_mda.h>
#include <86box/machine.h>
#include <86box/m_amstrad.h>
#include <86box/plat_unused.h>
#define STAT_PARITY 0x80
#define STAT_RTIMEOUT 0x40
#define STAT_TTIMEOUT 0x20
#define STAT_LOCK 0x10
#define STAT_CD 0x08
#define STAT_SYSFLAG 0x04
#define STAT_IFULL 0x02
#define STAT_OFULL 0x01
typedef struct amsvid_t {
rom_t bios_rom; /* 1640 */
cga_t cga; /* 1640/200 */
mda_t mda; /* 1512/200/PPC512/640*/
ega_t ega; /* 1640 */
uint8_t emulation; /* Which display are we emulating? */
uint8_t dipswitches; /* DIP switches 1-3 */
uint8_t crtc_index; /* CRTC index readback
* Bit 7: CGA control port written
* Bit 6: Operation control port written
* Bit 5: CRTC register written
* Bits 0-4: Last CRTC register selected */
uint8_t operation_ctrl;
uint8_t reg_3df;
uint8_t type;
uint8_t crtc[32];
int crtcreg;
int cga_enabled; /* 1640 */
uint8_t cgacol;
uint8_t cgamode;
uint8_t stat;
uint8_t plane_write; /* 1512/200 */
uint8_t plane_read; /* 1512/200 */
uint8_t border; /* 1512/200 */
uint8_t invert; /* 512/640 */
int fontbase; /* 1512/200 */
int linepos;
int displine;
int sc;
int vc;
int cgadispon;
int con;
int coff;
int cursoron;
int cgablink;
int vsynctime;
int fullchange;
int vadj;
uint16_t ma;
uint16_t maback;
int dispon;
int blink;
uint64_t dispontime; /* 1512/1640 */
uint64_t dispofftime; /* 1512/1640 */
pc_timer_t timer; /* 1512/1640 */
int firstline;
int lastline;
uint8_t *vram;
void *ams;
} amsvid_t;
typedef struct amstrad_t {
/* Machine stuff. */
uint8_t dead;
uint8_t stat1;
uint8_t stat2;
uint8_t type;
uint8_t language;
/* Keyboard stuff. */
int8_t wantirq;
uint8_t key_waiting;
uint8_t pa;
uint8_t pb;
pc_timer_t send_delay_timer;
/* Mouse stuff. */
int oldb;
/* Video stuff. */
amsvid_t *vid;
fdc_t *fdc;
} amstrad_t;
uint32_t amstrad_latch;
static uint8_t key_queue[16];
static int key_queue_start = 0;
static int key_queue_end = 0;
static uint8_t crtc_mask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f,
0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static video_timings_t timing_pc1512 = { VIDEO_BUS, 0, 0, 0, 0, 0, 0 }; /*PC1512 video code handles waitstates itself*/
static video_timings_t timing_pc1640 = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
static video_timings_t timing_pc200 = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
enum {
AMS_PC1512,
AMS_PC1640,
AMS_PC200,
AMS_PPC512,
AMS_PC2086,
AMS_PC3086
};
#ifdef ENABLE_AMSTRAD_LOG
int amstrad_do_log = ENABLE_AMSTRAD_LOG;
static void
amstrad_log(const char *fmt, ...)
{
va_list ap;
if (amstrad_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define amstrad_log(fmt, ...)
#endif
static void
recalc_timings_1512(amsvid_t *vid)
{
double _dispontime;
double _dispofftime;
double disptime;
disptime = /*128*/ 114; /*Fixed on PC1512*/
_dispontime = 80;
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
vid->dispontime = (uint64_t) _dispontime;
vid->dispofftime = (uint64_t) _dispofftime;
}
static void
vid_out_1512(uint16_t addr, uint8_t val, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
uint8_t old;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x03d4:
vid->crtcreg = val & 31;
return;
case 0x03d5:
old = vid->crtc[vid->crtcreg];
vid->crtc[vid->crtcreg] = val & crtc_mask[vid->crtcreg];
if (old != val) {
if (vid->crtcreg < 0xe || vid->crtcreg > 0x10) {
vid->fullchange = changeframecount;
recalc_timings_1512(vid);
}
}
return;
case 0x03d8:
if ((val & 0x12) == 0x12 && (vid->cgamode & 0x12) != 0x12) {
vid->plane_write = 0xf;
vid->plane_read = 0;
}
vid->cgamode = val;
return;
case 0x03d9:
vid->cgacol = val;
return;
case 0x03dd:
vid->plane_write = val;
return;
case 0x03de:
vid->plane_read = val & 3;
return;
case 0x03df:
vid->border = val;
return;
default:
return;
}
}
static uint8_t
vid_in_1512(uint16_t addr, void *priv)
{
const amsvid_t *vid = (amsvid_t *) priv;
uint8_t ret = 0xff;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x03d4:
ret = vid->crtcreg;
break;
case 0x03d5:
ret = vid->crtc[vid->crtcreg];
break;
case 0x03da:
ret = vid->stat;
break;
default:
break;
}
return ret;
}
static void
vid_write_1512(uint32_t addr, uint8_t val, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
cycles -= 12;
addr &= 0x3fff;
if ((vid->cgamode & 0x12) == 0x12) {
if (vid->plane_write & 1)
vid->vram[addr] = val;
if (vid->plane_write & 2)
vid->vram[addr | 0x4000] = val;
if (vid->plane_write & 4)
vid->vram[addr | 0x8000] = val;
if (vid->plane_write & 8)
vid->vram[addr | 0xc000] = val;
} else
vid->vram[addr] = val;
}
static uint8_t
vid_read_1512(uint32_t addr, void *priv)
{
const amsvid_t *vid = (amsvid_t *) priv;
cycles -= 12;
addr &= 0x3fff;
if ((vid->cgamode & 0x12) == 0x12)
return (vid->vram[addr | (vid->plane_read << 14)]);
return (vid->vram[addr]);
}
static void
vid_poll_1512(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
uint16_t ca = (vid->crtc[15] | (vid->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int xs_temp;
int ys_temp;
uint8_t chr;
uint8_t attr;
uint16_t dat;
uint16_t dat2;
uint16_t dat3;
uint16_t dat4;
int cols[4];
int col;
int oldsc;
if (!vid->linepos) {
timer_advance_u64(&vid->timer, vid->dispofftime);
vid->stat |= 1;
vid->linepos = 1;
oldsc = vid->sc;
if (vid->dispon) {
if (vid->displine < vid->firstline) {
vid->firstline = vid->displine;
video_wait_for_buffer();
}
vid->lastline = vid->displine;
for (c = 0; c < 8; c++) {
if ((vid->cgamode & 0x12) == 0x12) {
buffer32->line[vid->displine << 1][c] = buffer32->line[(vid->displine << 1) + 1][c] = (vid->border & 15) + 16;
if (vid->cgamode & 1) {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 3) + 8] = 0;
} else {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 4) + 8] = 0;
}
} else {
buffer32->line[vid->displine << 1][c] = buffer32->line[(vid->displine << 1) + 1][c] = (vid->cgacol & 15) + 16;
if (vid->cgamode & 1) {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 3) + 8] = (vid->cgacol & 15) + 16;
} else {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 4) + 8] = (vid->cgacol & 15) + 16;
}
}
}
if (vid->cgamode & 1) {
for (x = 0; x < 80; x++) {
chr = vid->vram[(vid->ma << 1) & 0x3fff];
attr = vid->vram[((vid->ma << 1) + 1) & 0x3fff];
drawcursor = ((vid->ma == ca) && vid->con && vid->cursoron);
if (vid->cgamode & 0x20) {
cols[1] = (attr & 15) + 16;
cols[0] = ((attr >> 4) & 7) + 16;
if ((vid->blink & 16) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = (attr & 15) + 16;
cols[0] = (attr >> 4) + 16;
}
if (drawcursor) {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] = cols[(fontdat[vid->fontbase + chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
}
} else {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] = cols[(fontdat[vid->fontbase + chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
vid->ma++;
}
} else if (!(vid->cgamode & 2)) {
for (x = 0; x < 40; x++) {
chr = vid->vram[(vid->ma << 1) & 0x3fff];
attr = vid->vram[((vid->ma << 1) + 1) & 0x3fff];
drawcursor = ((vid->ma == ca) && vid->con && vid->cursoron);
if (vid->cgamode & 0x20) {
cols[1] = (attr & 15) + 16;
cols[0] = ((attr >> 4) & 7) + 16;
if ((vid->blink & 16) && (attr & 0x80))
cols[1] = cols[0];
} else {
cols[1] = (attr & 15) + 16;
cols[0] = (attr >> 4) + 16;
}
vid->ma++;
if (drawcursor) {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[vid->fontbase + chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
}
} else {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[vid->fontbase + chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
}
} else if (!(vid->cgamode & 16)) {
cols[0] = (vid->cgacol & 15) | 16;
col = (vid->cgacol & 16) ? 24 : 16;
if (vid->cgamode & 4) {
cols[1] = col | 3;
cols[2] = col | 4;
cols[3] = col | 7;
} else if (vid->cgacol & 32) {
cols[1] = col | 3;
cols[2] = col | 5;
cols[3] = col | 7;
} else {
cols[1] = col | 2;
cols[2] = col | 4;
cols[3] = col | 6;
}
for (x = 0; x < 40; x++) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000) + 1];
vid->ma++;
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
dat <<= 2;
}
}
} else {
for (x = 0; x < 40; x++) {
ca = ((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000);
dat = (vid->vram[ca] << 8) | vid->vram[ca + 1];
dat2 = (vid->vram[ca + 0x4000] << 8) | vid->vram[ca + 0x4001];
dat3 = (vid->vram[ca + 0x8000] << 8) | vid->vram[ca + 0x8001];
dat4 = (vid->vram[ca + 0xc000] << 8) | vid->vram[ca + 0xc001];
vid->ma++;
for (c = 0; c < 16; c++) {
buffer32->line[vid->displine << 1][(x << 4) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + c + 8] = (((dat >> 15) | ((dat2 >> 15) << 1) | ((dat3 >> 15) << 2) | ((dat4 >> 15) << 3)) & (vid->cgacol & 15)) + 16;
dat <<= 1;
dat2 <<= 1;
dat3 <<= 1;
dat4 <<= 1;
}
}
}
} else {
cols[0] = ((vid->cgamode & 0x12) == 0x12) ? 0 : (vid->cgacol & 15) + 16;
if (vid->cgamode & 1) {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 3) + 16, cols[0]);
hline(buffer32, 0, (vid->displine << 1) + 1, (vid->crtc[1] << 3) + 16, cols[0]);
} else {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 4) + 16, cols[0]);
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 4) + 16, cols[0]);
}
}
if (vid->cgamode & 1)
x = (vid->crtc[1] << 3) + 16;
else
x = (vid->crtc[1] << 4) + 16;
video_process_8(x, vid->displine << 1);
video_process_8(x, (vid->displine << 1) + 1);
vid->sc = oldsc;
if (vid->vsynctime)
vid->stat |= 8;
vid->displine++;
if (vid->displine >= 360)
vid->displine = 0;
} else {
timer_advance_u64(&vid->timer, vid->dispontime);
if ((vid->lastline - vid->firstline) == 199)
vid->dispon = 0; /*Amstrad PC1512 always displays 200 lines, regardless of CRTC settings*/
if (vid->dispon)
vid->stat &= ~1;
vid->linepos = 0;
if (vid->vsynctime) {
vid->vsynctime--;
if (!vid->vsynctime)
vid->stat &= ~8;
}
if (vid->sc == (vid->crtc[11] & 31)) {
vid->con = 0;
vid->coff = 1;
}
if (vid->vadj) {
vid->sc++;
vid->sc &= 31;
vid->ma = vid->maback;
vid->vadj--;
if (!vid->vadj) {
vid->dispon = 1;
vid->ma = vid->maback = (vid->crtc[13] | (vid->crtc[12] << 8)) & 0x3fff;
vid->sc = 0;
}
} else if (vid->sc == vid->crtc[9]) {
vid->maback = vid->ma;
vid->sc = 0;
vid->vc++;
vid->vc &= 127;
if (vid->displine == 32) {
vid->vc = 0;
vid->vadj = 6;
if ((vid->crtc[10] & 0x60) == 0x20)
vid->cursoron = 0;
else
vid->cursoron = vid->blink & 16;
}
if (vid->displine >= 262) {
vid->dispon = 0;
vid->displine = 0;
vid->vsynctime = 46;
if (vid->cgamode & 1)
x = (vid->crtc[1] << 3) + 16;
else
x = (vid->crtc[1] << 4) + 16;
vid->lastline++;
xs_temp = x;
ys_temp = (vid->lastline - vid->firstline) << 1;
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xs_temp < 64)
xs_temp = 656;
if (ys_temp < 32)
ys_temp = 400;
if (!enable_overscan)
xs_temp -= 16;
if ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get()) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
if (enable_overscan) {
video_blit_memtoscreen(0, (vid->firstline - 4) << 1,
xsize, ((vid->lastline - vid->firstline) + 8) << 1);
} else {
video_blit_memtoscreen(8, vid->firstline << 1,
xsize, (vid->lastline - vid->firstline) << 1);
}
}
video_res_x = xsize;
video_res_y = ysize;
if (vid->cgamode & 1) {
video_res_x /= 8;
video_res_y /= vid->crtc[9] + 1;
video_bpp = 0;
} else if (!(vid->cgamode & 2)) {
video_res_x /= 16;
video_res_y /= vid->crtc[9] + 1;
video_bpp = 0;
} else if (!(vid->cgamode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else {
video_bpp = 4;
}
vid->firstline = 1000;
vid->lastline = 0;
vid->blink++;
}
} else {
vid->sc++;
vid->sc &= 31;
vid->ma = vid->maback;
}
if (vid->sc == (vid->crtc[10] & 31))
vid->con = 1;
}
}
static void
vid_init_1512(amstrad_t *ams)
{
amsvid_t *vid;
/* Allocate a video controller block. */
vid = (amsvid_t *) malloc(sizeof(amsvid_t));
memset(vid, 0x00, sizeof(amsvid_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_pc1512);
vid->vram = malloc(0x10000);
vid->cgacol = 7;
vid->cgamode = 0x12;
timer_add(&vid->timer, vid_poll_1512, vid, 1);
mem_mapping_add(&vid->cga.mapping, 0xb8000, 0x08000,
vid_read_1512, NULL, NULL, vid_write_1512, NULL, NULL,
NULL, 0, vid);
io_sethandler(0x03d0, 16,
vid_in_1512, NULL, NULL, vid_out_1512, NULL, NULL, vid);
overscan_x = overscan_y = 16;
vid->fontbase = (device_get_config_int("codepage") & 3) * 256;
cga_palette = (device_get_config_int("display_type") << 1);
cgapal_rebuild();
ams->vid = vid;
}
static void
vid_close_1512(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
free(vid->vram);
free(vid);
}
static void
vid_speed_change_1512(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
recalc_timings_1512(vid);
}
const device_config_t vid_1512_config[] = {
// clang-format off
{
.name = "display_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "PC-CM (Colour)", .value = 0 },
{ .description = "PC-MM (Monochrome)", .value = 3 },
{ .description = "" }
}
},
{
.name = "codepage",
.description = "Hardware font",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "US English", .value = 3 },
{ .description = "Danish", .value = 1 },
{ .description = "Greek", .value = 0 },
{ .description = "" }
}
},
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "German", .value = 6 },
{ .description = "French", .value = 5 },
{ .description = "Spanish", .value = 4 },
{ .description = "Danish", .value = 3 },
{ .description = "Swedish", .value = 2 },
{ .description = "Italian", .value = 1 },
{ .description = "Diagnostic mode", .value = 0 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_1512_device = {
.name = "Amstrad PC1512 (video)",
.internal_name = "vid_1512",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close_1512,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_change_1512,
.force_redraw = NULL,
.config = vid_1512_config
};
static void
recalc_timings_1640(amsvid_t *vid)
{
cga_recalctimings(&vid->cga);
ega_recalctimings(&vid->ega);
if (vid->cga_enabled) {
overscan_x = overscan_y = 16;
vid->dispontime = vid->cga.dispontime;
vid->dispofftime = vid->cga.dispofftime;
} else {
overscan_x = 16;
overscan_y = 28;
vid->dispontime = vid->ega.dispontime;
vid->dispofftime = vid->ega.dispofftime;
}
}
static void
vid_out_1640(uint16_t addr, uint8_t val, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
switch (addr) {
case 0x03db:
vid->cga_enabled = val & 0x40;
if (vid->cga_enabled) {
timer_disable(&vid->ega.timer);
timer_set_delay_u64(&vid->cga.timer, 0);
mem_mapping_enable(&vid->cga.mapping);
mem_mapping_disable(&vid->ega.mapping);
} else {
timer_disable(&vid->cga.timer);
timer_set_delay_u64(&vid->ega.timer, 0);
mem_mapping_disable(&vid->cga.mapping);
switch (vid->ega.gdcreg[6] & 0xc) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&vid->ega.mapping,
0xa0000, 0x20000);
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&vid->ega.mapping,
0xa0000, 0x10000);
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&vid->ega.mapping,
0xb0000, 0x08000);
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&vid->ega.mapping,
0xb8000, 0x08000);
break;
default:
break;
}
}
return;
default:
break;
}
if (vid->cga_enabled)
cga_out(addr, val, &vid->cga);
else
ega_out(addr, val, &vid->ega);
}
static uint8_t
vid_in_1640(uint16_t addr, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
if (vid->cga_enabled)
return (cga_in(addr, &vid->cga));
else
return (ega_in(addr, &vid->ega));
}
static void
vid_init_1640(amstrad_t *ams)
{
amsvid_t *vid;
/* Allocate a video controller block. */
vid = (amsvid_t *) malloc(sizeof(amsvid_t));
memset(vid, 0x00, sizeof(amsvid_t));
rom_init(&vid->bios_rom, "roms/machines/pc1640/40100",
0xc0000, 0x8000, 0x7fff, 0, 0);
ega_init(&vid->ega, 9, 0);
vid->cga.vram = vid->ega.vram;
vid->cga_enabled = 1;
cga_init(&vid->cga);
timer_disable(&vid->ega.timer);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_pc1640);
mem_mapping_add(&vid->cga.mapping, 0xb8000, 0x08000,
cga_read, NULL, NULL, cga_write, NULL, NULL, NULL, 0, &vid->cga);
mem_mapping_add(&vid->ega.mapping, 0, 0,
ega_read, NULL, NULL, ega_write, NULL, NULL, NULL, 0, &vid->ega);
io_sethandler(0x03a0, 64,
vid_in_1640, NULL, NULL, vid_out_1640, NULL, NULL, vid);
overscan_x = overscan_y = 16;
vid->fontbase = 768;
cga_palette = 0;
cgapal_rebuild();
ams->vid = vid;
}
static void
vid_close_1640(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
free(vid->ega.vram);
free(vid);
}
static void
vid_speed_changed_1640(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
recalc_timings_1640(vid);
}
const device_config_t vid_1640_config[] = {
// clang-format off
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "German", .value = 6 },
{ .description = "French", .value = 5 },
{ .description = "Spanish", .value = 4 },
{ .description = "Danish", .value = 3 },
{ .description = "Swedish", .value = 2 },
{ .description = "Italian", .value = 1 },
{ .description = "Diagnostic mode", .value = 0 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_1640_device = {
.name = "Amstrad PC1640 (video)",
.internal_name = "vid_1640",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close_1640,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed_1640,
.force_redraw = NULL,
.config = vid_1640_config
};
/* Display type */
#define PC200_CGA 0 /* CGA monitor */
#define PC200_MDA 1 /* MDA monitor */
#define PC200_TV 2 /* Television */
#define PC200_LCDC 3 /* PPC512 LCD as CGA*/
#define PC200_LCDM 4 /* PPC512 LCD as MDA*/
extern int nmi_mask;
static uint32_t blue;
static uint32_t green;
static uint32_t lcdcols[256][2][2];
static void
ams_inform(amsvid_t *vid)
{
switch (vid->emulation) {
case PC200_CGA:
case PC200_TV:
case PC200_LCDC:
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_pc200);
break;
case PC200_MDA:
case PC200_LCDM:
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_pc200);
break;
default:
break;
}
}
static void
vid_speed_changed_200(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
cga_recalctimings(&vid->cga);
mda_recalctimings(&vid->mda);
}
/* LCD colour mappings
*
* 0 => solid green
* 1 => blue on green
* 2 => green on blue
* 3 => solid blue
*/
static unsigned char mapping1[256] = {
// clang-format off
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/*00*/ 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
/*10*/ 2, 0, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1,
/*20*/ 2, 2, 0, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
/*30*/ 2, 2, 2, 0, 2, 2, 1, 1, 2, 2, 2, 1, 2, 2, 1, 1,
/*40*/ 2, 2, 1, 1, 0, 1, 1, 1, 2, 2, 1, 1, 1, 1, 1, 1,
/*50*/ 2, 2, 1, 1, 2, 0, 1, 1, 2, 2, 1, 1, 2, 1, 1, 1,
/*60*/ 2, 2, 2, 2, 2, 2, 0, 1, 2, 2, 2, 2, 2, 2, 1, 1,
/*70*/ 2, 2, 2, 2, 2, 2, 2, 0, 2, 2, 2, 2, 2, 2, 2, 1,
/*80*/ 2, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1,
/*90*/ 2, 2, 1, 1, 1, 1, 1, 1, 2, 0, 1, 1, 1, 1, 1, 1,
/*A0*/ 2, 2, 2, 1, 2, 2, 1, 1, 2, 2, 0, 1, 2, 2, 1, 1,
/*B0*/ 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, 2, 0, 2, 2, 1, 1,
/*C0*/ 2, 2, 1, 1, 2, 1, 1, 1, 2, 2, 1, 1, 0, 1, 1, 1,
/*D0*/ 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 0, 1, 1,
/*E0*/ 2, 2, 2, 2, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 0, 1,
/*F0*/ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0,
// clang-format on
};
static unsigned char mapping2[256] = {
// clang-format off
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/*00*/ 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
/*10*/ 1, 3, 2, 2, 2, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2,
/*20*/ 1, 1, 3, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2,
/*30*/ 1, 1, 1, 3, 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 2, 2,
/*40*/ 1, 1, 2, 2, 3, 2, 2, 2, 1, 1, 2, 2, 2, 2, 2, 2,
/*50*/ 1, 1, 2, 2, 1, 3, 2, 2, 1, 1, 2, 2, 1, 2, 2, 2,
/*60*/ 1, 1, 1, 1, 1, 1, 3, 2, 1, 1, 1, 1, 1, 1, 2, 2,
/*70*/ 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 2,
/*80*/ 2, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1,
/*90*/ 1, 1, 2, 2, 2, 2, 2, 2, 1, 3, 2, 2, 2, 2, 2, 2,
/*A0*/ 1, 1, 1, 2, 1, 1, 2, 2, 1, 1, 3, 2, 1, 1, 2, 2,
/*B0*/ 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 3, 1, 1, 2, 2,
/*C0*/ 1, 1, 2, 2, 1, 2, 2, 2, 1, 1, 2, 2, 3, 2, 2, 2,
/*D0*/ 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 3, 2, 2,
/*E0*/ 1, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 3, 2,
/*F0*/ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3,
// clang-format on
};
static void
set_lcd_cols(uint8_t mode_reg)
{
const unsigned char *mapping = (mode_reg & 0x80) ? mapping2 : mapping1;
for (uint16_t c = 0; c < 256; c++) {
switch (mapping[c]) {
case 0:
lcdcols[c][0][0] = lcdcols[c][1][0] = green;
lcdcols[c][0][1] = lcdcols[c][1][1] = green;
break;
case 1:
lcdcols[c][0][0] = lcdcols[c][1][0] = lcdcols[c][1][1] = green;
lcdcols[c][0][1] = blue;
break;
case 2:
lcdcols[c][0][0] = lcdcols[c][1][0] = lcdcols[c][1][1] = blue;
lcdcols[c][0][1] = green;
break;
case 3:
lcdcols[c][0][0] = lcdcols[c][1][0] = blue;
lcdcols[c][0][1] = lcdcols[c][1][1] = blue;
break;
default:
break;
}
}
}
static uint8_t
vid_in_200(uint16_t addr, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
cga_t *cga = &vid->cga;
mda_t *mda = &vid->mda;
uint8_t ret;
switch (addr) {
case 0x03b8:
return (mda->ctrl);
case 0x03d8:
return (cga->cgamode);
case 0x03dd:
ret = vid->crtc_index; /* Read NMI reason */
vid->crtc_index &= 0x1f; /* Reset NMI reason */
nmi = 0; /* And reset NMI flag */
return ret;
case 0x03de:
return ((vid->operation_ctrl & 0xc7) | vid->dipswitches); /*External CGA*/
case 0x03df:
return (vid->reg_3df);
default:
break;
}
if (addr >= 0x3D0 && addr <= 0x3DF)
return cga_in(addr, cga);
if (addr >= 0x3B0 && addr <= 0x3BB)
return mda_in(addr, mda);
return 0xFF;
}
static void
vid_out_200(uint16_t addr, uint8_t val, void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
cga_t *cga = &vid->cga;
mda_t *mda = &vid->mda;
uint8_t old;
switch (addr) {
/* MDA writes ============================================================== */
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
/* Writes banned to CRTC registers 0-11? */
if (!(vid->operation_ctrl & 0x40) && mda->crtcreg <= 11) {
vid->crtc_index = 0x20 | (mda->crtcreg & 0x1f);
if (vid->operation_ctrl & 0x80)
nmi_raise();
vid->reg_3df = val;
return;
}
old = mda->crtc[mda->crtcreg];
mda->crtc[mda->crtcreg] = val & crtc_mask[mda->crtcreg];
if (old != val) {
if (mda->crtcreg < 0xe || mda->crtcreg > 0x10) {
vid->fullchange = changeframecount;
mda_recalctimings(mda);
}
}
return;
case 0x3b8:
old = mda->ctrl;
mda->ctrl = val;
if ((mda->ctrl ^ old) & 3)
mda_recalctimings(mda);
vid->crtc_index &= 0x1F;
vid->crtc_index |= 0x80;
if (vid->operation_ctrl & 0x80)
nmi_raise();
return;
/* CGA writes ============================================================== */
case 0x03d1:
case 0x03d3:
case 0x03d5:
case 0x03d7:
if (!(vid->operation_ctrl & 0x40) && cga->crtcreg <= 11) {
vid->crtc_index = 0x20 | (cga->crtcreg & 0x1f);
if (vid->operation_ctrl & 0x80)
nmi_raise();
vid->reg_3df = val;
return;
}
old = cga->crtc[cga->crtcreg];
cga->crtc[cga->crtcreg] = val & crtc_mask[cga->crtcreg];
if (old != val) {
if (cga->crtcreg < 0xe || cga->crtcreg > 0x10) {
vid->fullchange = changeframecount;
cga_recalctimings(cga);
}
}
return;
case 0x03d8:
old = cga->cgamode;
cga->cgamode = val;
if ((cga->cgamode ^ old) & 3)
cga_recalctimings(cga);
vid->crtc_index &= 0x1f;
vid->crtc_index |= 0x80;
if (vid->operation_ctrl & 0x80)
nmi_raise();
else
set_lcd_cols(val);
return;
/* PC200 control port writes ============================================== */
case 0x03de:
vid->crtc_index = 0x1f;
/* NMI only seems to be triggered if the value being written has the high
* bit set (enable NMI). So it only protects writes to this port if you
* let it? */
if (val & 0x80) {
vid->operation_ctrl = val;
vid->crtc_index |= 0x40;
nmi_raise();
return;
}
timer_disable(&vid->cga.timer);
timer_disable(&vid->mda.timer);
timer_disable(&vid->timer);
vid->operation_ctrl = val;
/* Bits 0 and 1 control emulation and output mode */
amstrad_log("emulation and mode = %02X\n", val & 0x03);
if (val & 1) /* Monitor */
vid->emulation = (val & 2) ? PC200_MDA : PC200_CGA;
else if (vid->type == AMS_PPC512)
vid->emulation = (val & 2) ? PC200_LCDM : PC200_LCDC;
else
vid->emulation = PC200_TV;
if (vid->emulation == PC200_CGA || vid->emulation == PC200_TV)
timer_advance_u64(&vid->cga.timer, 1);
else if (vid->emulation == PC200_MDA)
timer_advance_u64(&vid->mda.timer, 1);
else
timer_advance_u64(&vid->timer, 1);
/* Bit 2 disables the IDA. We don't support dynamic enabling
* and disabling of the IDA (instead, PCEM disconnects the
* IDA from the bus altogether) so don't implement this */
/* Enable the appropriate memory ranges depending whether
* the IDA is configured as MDA or CGA */
if (vid->emulation == PC200_MDA || vid->emulation == PC200_LCDM) {
mem_mapping_disable(&vid->cga.mapping);
mem_mapping_enable(&vid->mda.mapping);
} else {
mem_mapping_disable(&vid->mda.mapping);
mem_mapping_enable(&vid->cga.mapping);
}
return;
default:
break;
}
if (addr >= 0x3D0 && addr <= 0x3DF)
cga_out(addr, val, cga);
if (addr >= 0x3B0 && addr <= 0x3BB)
mda_out(addr, val, mda);
}
static void
lcd_draw_char_80(amsvid_t *vid, uint32_t *buffer, uint8_t chr,
uint8_t attr, int drawcursor, int blink, int sc,
int mode160, uint8_t control)
{
int c;
uint8_t bits = fontdat[chr + vid->cga.fontbase][sc];
uint8_t bright = 0;
uint16_t mask;
if (attr & 8) { /* bright */
/* The brightness algorithm appears to be: replace any bit sequence 011
* with 001 (assuming an extra 0 to the left of the byte).
*/
bright = bits;
for (c = 0, mask = 0x100; c < 7; c++, mask >>= 1) {
if (((bits & mask) == 0) && ((bits & (mask >> 1)) != 0) && ((bits & (mask >> 2)) != 0))
bright &= ~(mask >> 1);
}
bits = bright;
}
if (drawcursor)
bits ^= 0xFF;
for (c = 0, mask = 0x80; c < 8; c++, mask >>= 1) {
if (mode160)
buffer[c] = (attr & mask) ? blue : green;
else if (control & 0x20) /* blinking */
buffer[c] = lcdcols[attr & 0x7F][blink][(bits & mask) ? 1 : 0];
else
buffer[c] = lcdcols[attr][blink][(bits & mask) ? 1 : 0];
}
}
static void
lcd_draw_char_40(amsvid_t *vid, uint32_t *buffer, uint8_t chr,
uint8_t attr, int drawcursor, int blink, int sc,
uint8_t control)
{
uint8_t bits = fontdat[chr + vid->cga.fontbase][sc];
uint8_t mask = 0x80;
if (attr & 8) /* bright */
bits = bits & (bits >> 1);
if (drawcursor)
bits ^= 0xFF;
for (uint8_t c = 0; c < 8; c++, mask >>= 1) {
if (control & 0x20) {
buffer[c * 2] = buffer[c * 2 + 1] = lcdcols[attr & 0x7F][blink][(bits & mask) ? 1 : 0];
} else {
buffer[c * 2] = buffer[c * 2 + 1] = lcdcols[attr][blink][(bits & mask) ? 1 : 0];
}
}
}
static void
lcdm_poll(amsvid_t *vid)
{
mda_t *mda = &vid->mda;
uint16_t ca = (mda->crtc[15] | (mda->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int oldvc;
uint8_t chr;
uint8_t attr;
int oldsc;
int blink;
if (!mda->linepos) {
timer_advance_u64(&vid->timer, mda->dispofftime);
mda->stat |= 1;
mda->linepos = 1;
oldsc = mda->sc;
if ((mda->crtc[8] & 3) == 3)
mda->sc = (mda->sc << 1) & 7;
if (mda->dispon) {
if (mda->displine < mda->firstline)
mda->firstline = mda->displine;
mda->lastline = mda->displine;
for (x = 0; x < mda->crtc[1]; x++) {
chr = mda->vram[(mda->ma << 1) & 0xfff];
attr = mda->vram[((mda->ma << 1) + 1) & 0xfff];
drawcursor = ((mda->ma == ca) && mda->con && mda->cursoron);
blink = ((mda->blink & 16) && (mda->ctrl & 0x20) && (attr & 0x80) && !drawcursor);
lcd_draw_char_80(vid, &(buffer32->line[mda->displine])[x * 8], chr, attr, drawcursor, blink, mda->sc, 0, mda->ctrl);
mda->ma++;
}
}
mda->sc = oldsc;
if (mda->vc == mda->crtc[7] && !mda->sc)
mda->stat |= 8;
mda->displine++;
if (mda->displine >= 500)
mda->displine = 0;
} else {
timer_advance_u64(&vid->timer, mda->dispontime);
if (mda->dispon)
mda->stat &= ~1;
mda->linepos = 0;
if (mda->vsynctime) {
mda->vsynctime--;
if (!mda->vsynctime)
mda->stat &= ~8;
}
if (mda->sc == (mda->crtc[11] & 31) || ((mda->crtc[8] & 3) == 3 && mda->sc == ((mda->crtc[11] & 31) >> 1))) {
mda->con = 0;
mda->coff = 1;
}
if (mda->vadj) {
mda->sc++;
mda->sc &= 31;
mda->ma = mda->maback;
mda->vadj--;
if (!mda->vadj) {
mda->dispon = 1;
mda->ma = mda->maback = (mda->crtc[13] | (mda->crtc[12] << 8)) & 0x3fff;
mda->sc = 0;
}
} else if (mda->sc == mda->crtc[9] || ((mda->crtc[8] & 3) == 3 && mda->sc == (mda->crtc[9] >> 1))) {
mda->maback = mda->ma;
mda->sc = 0;
oldvc = mda->vc;
mda->vc++;
mda->vc &= 127;
if (mda->vc == mda->crtc[6])
mda->dispon = 0;
if (oldvc == mda->crtc[4]) {
mda->vc = 0;
mda->vadj = mda->crtc[5];
if (!mda->vadj)
mda->dispon = 1;
if (!mda->vadj)
mda->ma = mda->maback = (mda->crtc[13] | (mda->crtc[12] << 8)) & 0x3fff;
if ((mda->crtc[10] & 0x60) == 0x20)
mda->cursoron = 0;
else
mda->cursoron = mda->blink & 16;
}
if (mda->vc == mda->crtc[7]) {
mda->dispon = 0;
mda->displine = 0;
mda->vsynctime = 16;
if (mda->crtc[7]) {
x = mda->crtc[1] * 8;
mda->lastline++;
if ((x != xsize) || ((mda->lastline - mda->firstline) != ysize) || video_force_resize_get()) {
xsize = x;
ysize = mda->lastline - mda->firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, mda->firstline, xsize, ysize);
frames++;
video_res_x = mda->crtc[1];
video_res_y = mda->crtc[6];
video_bpp = 0;
}
mda->firstline = 1000;
mda->lastline = 0;
mda->blink++;
}
} else {
mda->sc++;
mda->sc &= 31;
mda->ma = mda->maback;
}
if (mda->sc == (mda->crtc[10] & 31) || ((mda->crtc[8] & 3) == 3 && mda->sc == ((mda->crtc[10] & 31) >> 1)))
mda->con = 1;
}
}
static void
lcdc_poll(amsvid_t *vid)
{
cga_t *cga = &vid->cga;
int drawcursor;
int x;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint16_t dat;
int oldsc;
uint16_t ca;
int blink;
ca = (cga->crtc[15] | (cga->crtc[14] << 8)) & 0x3fff;
if (!cga->linepos) {
timer_advance_u64(&vid->timer, cga->dispofftime);
cga->cgastat |= 1;
cga->linepos = 1;
oldsc = cga->sc;
if ((cga->crtc[8] & 3) == 3)
cga->sc = ((cga->sc << 1) + cga->oddeven) & 7;
if (cga->cgadispon) {
if (cga->displine < cga->firstline) {
cga->firstline = cga->displine;
video_wait_for_buffer();
}
cga->lastline = cga->displine;
if (cga->cgamode & 1) {
for (x = 0; x < cga->crtc[1]; x++) {
chr = cga->charbuffer[x << 1];
attr = cga->charbuffer[(x << 1) + 1];
drawcursor = ((cga->ma == ca) && cga->con && cga->cursoron);
blink = ((cga->cgablink & 16) && (cga->cgamode & 0x20) && (attr & 0x80) && !drawcursor);
lcd_draw_char_80(vid, &(buffer32->line[cga->displine << 1])[x * 8], chr, attr, drawcursor, blink, cga->sc, cga->cgamode & 0x40, cga->cgamode);
lcd_draw_char_80(vid, &(buffer32->line[(cga->displine << 1) + 1])[x * 8], chr, attr, drawcursor, blink, cga->sc, cga->cgamode & 0x40, cga->cgamode);
cga->ma++;
}
} else if (!(cga->cgamode & 2)) {
for (x = 0; x < cga->crtc[1]; x++) {
chr = cga->vram[(cga->ma << 1) & 0x3fff];
attr = cga->vram[((cga->ma << 1) + 1) & 0x3fff];
drawcursor = ((cga->ma == ca) && cga->con && cga->cursoron);
blink = ((cga->cgablink & 16) && (cga->cgamode & 0x20) && (attr & 0x80) && !drawcursor);
lcd_draw_char_40(vid, &(buffer32->line[cga->displine << 1])[x * 16], chr, attr, drawcursor, blink, cga->sc, cga->cgamode);
lcd_draw_char_40(vid, &(buffer32->line[(cga->displine << 1) + 1])[x * 16], chr, attr, drawcursor, blink, cga->sc, cga->cgamode);
cga->ma++;
}
} else { /* Graphics mode */
for (x = 0; x < cga->crtc[1]; x++) {
dat = (cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000)] << 8) | cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000) + 1];
cga->ma++;
for (uint8_t c = 0; c < 16; c++) {
buffer32->line[cga->displine << 1][(x << 4) + c] = buffer32->line[(cga->displine << 1) + 1][(x << 4) + c] = (dat & 0x8000) ? blue : green;
dat <<= 1;
}
}
}
} else {
if (cga->cgamode & 1) {
hline(buffer32, 0, (cga->displine << 1), (cga->crtc[1] << 3), green);
hline(buffer32, 0, (cga->displine << 1) + 1, (cga->crtc[1] << 3), green);
} else {
hline(buffer32, 0, (cga->displine << 1), (cga->crtc[1] << 4), green);
hline(buffer32, 0, (cga->displine << 1) + 1, (cga->crtc[1] << 4), green);
}
}
if (cga->cgamode & 1)
x = (cga->crtc[1] << 3);
else
x = (cga->crtc[1] << 4);
cga->sc = oldsc;
if (cga->vc == cga->crtc[7] && !cga->sc)
cga->cgastat |= 8;
cga->displine++;
if (cga->displine >= 360)
cga->displine = 0;
} else {
timer_advance_u64(&vid->timer, cga->dispontime);
cga->linepos = 0;
if (cga->vsynctime) {
cga->vsynctime--;
if (!cga->vsynctime)
cga->cgastat &= ~8;
}
if (cga->sc == (cga->crtc[11] & 31) || ((cga->crtc[8] & 3) == 3 && cga->sc == ((cga->crtc[11] & 31) >> 1))) {
cga->con = 0;
cga->coff = 1;
}
if ((cga->crtc[8] & 3) == 3 && cga->sc == (cga->crtc[9] >> 1))
cga->maback = cga->ma;
if (cga->vadj) {
cga->sc++;
cga->sc &= 31;
cga->ma = cga->maback;
cga->vadj--;
if (!cga->vadj) {
cga->cgadispon = 1;
cga->ma = cga->maback = (cga->crtc[13] | (cga->crtc[12] << 8)) & 0x3fff;
cga->sc = 0;
}
} else if (cga->sc == cga->crtc[9]) {
cga->maback = cga->ma;
cga->sc = 0;
oldvc = cga->vc;
cga->vc++;
cga->vc &= 127;
if (cga->vc == cga->crtc[6])
cga->cgadispon = 0;
if (oldvc == cga->crtc[4]) {
cga->vc = 0;
cga->vadj = cga->crtc[5];
if (!cga->vadj)
cga->cgadispon = 1;
if (!cga->vadj)
cga->ma = cga->maback = (cga->crtc[13] | (cga->crtc[12] << 8)) & 0x3fff;
if ((cga->crtc[10] & 0x60) == 0x20)
cga->cursoron = 0;
else
cga->cursoron = cga->cgablink & 8;
}
if (cga->vc == cga->crtc[7]) {
cga->cgadispon = 0;
cga->displine = 0;
cga->vsynctime = 16;
if (cga->crtc[7]) {
if (cga->cgamode & 1)
x = (cga->crtc[1] << 3);
else
x = (cga->crtc[1] << 4);
cga->lastline++;
xs_temp = x;
ys_temp = (cga->lastline - cga->firstline) << 1;
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xs_temp < 64)
xs_temp = 640;
if (ys_temp < 32)
ys_temp = 400;
if ((cga->cgamode & 8) && ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get())) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, cga->firstline << 1,
xsize, (cga->lastline - cga->firstline) << 1);
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
if (cga->cgamode & 1) {
video_res_x /= 8;
video_res_y /= cga->crtc[9] + 1;
video_bpp = 0;
} else if (!(cga->cgamode & 2)) {
video_res_x /= 16;
video_res_y /= cga->crtc[9] + 1;
video_bpp = 0;
} else if (!(cga->cgamode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else
video_bpp = 1;
}
cga->firstline = 1000;
cga->lastline = 0;
cga->cgablink++;
cga->oddeven ^= 1;
}
} else {
cga->sc++;
cga->sc &= 31;
cga->ma = cga->maback;
}
if (cga->cgadispon)
cga->cgastat &= ~1;
if (cga->sc == (cga->crtc[10] & 31) || ((cga->crtc[8] & 3) == 3 && cga->sc == ((cga->crtc[10] & 31) >> 1)))
cga->con = 1;
if (cga->cgadispon && (cga->cgamode & 1)) {
for (x = 0; x < (cga->crtc[1] << 1); x++)
cga->charbuffer[x] = cga->vram[((cga->ma << 1) + x) & 0x3fff];
}
}
}
static void
vid_poll_200(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
switch (vid->emulation) {
case PC200_LCDM:
lcdm_poll(vid);
return;
case PC200_LCDC:
lcdc_poll(vid);
return;
default:
break;
}
}
static void
vid_init_200(amstrad_t *ams)
{
amsvid_t *vid;
cga_t *cga;
mda_t *mda;
/* Allocate a video controller block. */
vid = (amsvid_t *) malloc(sizeof(amsvid_t));
memset(vid, 0x00, sizeof(amsvid_t));
vid->emulation = device_get_config_int("video_emulation");
/* Default to CGA */
vid->dipswitches = 0x10;
vid->type = ams->type;
if (ams->type == AMS_PC200)
switch (vid->emulation) {
/* DIP switches for PC200. Switches 2,3 give video emulation.
* Switch 1 is 'swap floppy drives' (not implemented) */
case PC200_CGA:
vid->dipswitches = 0x10;
break;
case PC200_MDA:
vid->dipswitches = 0x30;
break;
case PC200_TV:
vid->dipswitches = 0x00;
break;
/* The other combination is 'IDA disabled' (0x20) - see
* m_amstrad.c */
default:
break;
}
else
switch (vid->emulation) {
/* DIP switches for PPC512. Switch 1 is CRT/LCD. Switch 2
* is MDA / CGA. Switch 3 disables IDA, not implemented. */
/* 1 = on, 0 = off
SW1: off = crt, on = lcd;
SW2: off = mda, on = cga;
SW3: off = disable built-in card, on = enable */
case PC200_CGA:
vid->dipswitches = 0x08;
break;
case PC200_MDA:
vid->dipswitches = 0x18;
break;
case PC200_LCDC:
vid->dipswitches = 0x00;
break;
case PC200_LCDM:
vid->dipswitches = 0x10;
break;
default:
break;
}
cga = &vid->cga;
mda = &vid->mda;
cga->vram = mda->vram = malloc(0x4000);
cga_init(cga);
mda_init(mda);
cga_palette = (device_get_config_int("display_type") << 1);
ams_inform(vid);
/* Attribute 8 is white on black (on a real MDA it's black on black) */
mda_setcol(0x08, 0, 1, 15);
mda_setcol(0x88, 0, 1, 15);
/* Attribute 64 is black on black (on a real MDA it's white on black) */
mda_setcol(0x40, 0, 1, 0);
mda_setcol(0xC0, 0, 1, 0);
cga->fontbase = (device_get_config_int("codepage") & 3) * 256;
mda->fontbase = cga->fontbase;
timer_add(&vid->timer, vid_poll_200, vid, 1);
mem_mapping_add(&vid->mda.mapping, 0xb0000, 0x08000,
mda_read, NULL, NULL, mda_write, NULL, NULL, NULL, 0, mda);
mem_mapping_add(&vid->cga.mapping, 0xb8000, 0x08000,
cga_read, NULL, NULL, cga_write, NULL, NULL, NULL, 0, cga);
io_sethandler(0x03d0, 16, vid_in_200, NULL, NULL, vid_out_200, NULL, NULL, vid);
io_sethandler(0x03b0, 0x000c, vid_in_200, NULL, NULL, vid_out_200, NULL, NULL, vid);
overscan_x = overscan_y = 16;
if (ams->type == AMS_PC200)
vid->invert = 0;
else
vid->invert = device_get_config_int("invert");
if (vid->invert) {
blue = makecol(0x1C, 0x71, 0x31);
green = makecol(0x0f, 0x21, 0x3f);
} else {
green = makecol(0x1C, 0x71, 0x31);
blue = makecol(0x0f, 0x21, 0x3f);
}
cgapal_rebuild();
set_lcd_cols(0);
timer_disable(&vid->cga.timer);
timer_disable(&vid->mda.timer);
timer_disable(&vid->timer);
if (vid->emulation == PC200_CGA || vid->emulation == PC200_TV)
timer_enable(&vid->cga.timer);
else if (vid->emulation == PC200_MDA)
timer_enable(&vid->mda.timer);
else
timer_enable(&vid->timer);
ams->vid = vid;
}
static void
vid_close_200(void *priv)
{
amsvid_t *vid = (amsvid_t *) priv;
if (vid->cga.vram != vid->mda.vram) {
free(vid->cga.vram);
free(vid->mda.vram);
} else
free(vid->cga.vram);
vid->cga.vram = vid->mda.vram = NULL;
free(vid);
}
const device_config_t vid_200_config[] = {
/* TODO: Should have options here for:
*
* > Display port (TTL or RF)
*/
// clang-format off
{
.name = "video_emulation",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = PC200_CGA,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "CGA monitor", .value = PC200_CGA },
{ .description = "MDA monitor", .value = PC200_MDA },
{ .description = "Television", .value = PC200_TV },
{ .description = "" }
}
},
{
.name = "display_type",
.description = "Monitor type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "RGB", .value = 0 },
{ .description = "RGB (no brown)", .value = 4 },
{ .description = "Green Monochrome", .value = 1 },
{ .description = "Amber Monochrome", .value = 2 },
{ .description = "White Monochrome", .value = 3 },
{ .description = "" }
}
},
{
.name = "codepage",
.description = "Hardware font",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "US English", .value = 3 },
{ .description = "Portugese", .value = 2 },
{ .description = "Norwegian", .value = 1 },
{ .description = "Greek", .value = 0 },
{ .description = "" }
}
},
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "German", .value = 6 },
{ .description = "French", .value = 5 },
{ .description = "Spanish", .value = 4 },
{ .description = "Danish", .value = 3 },
{ .description = "Swedish", .value = 2 },
{ .description = "Italian", .value = 1 },
{ .description = "Diagnostic mode", .value = 0 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_200_device = {
.name = "Amstrad PC200 (video)",
.internal_name = "vid_200",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close_200,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed_200,
.force_redraw = NULL,
.config = vid_200_config
};
const device_config_t vid_ppc512_config[] = {
/* TODO: Should have options here for:
*
* > Display port (TTL or RF)
*/
// clang-format off
{
.name = "video_emulation",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = PC200_LCDC,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "CGA monitor", .value = PC200_CGA },
{ .description = "MDA monitor", .value = PC200_MDA },
{ .description = "LCD (CGA mode)", .value = PC200_LCDC },
{ .description = "LCD (MDA mode)", .value = PC200_LCDM },
{ .description = "" }
},
},
{
.name = "display_type",
.description = "Monitor type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "RGB", .value = 0 },
{ .description = "RGB (no brown)", .value = 4 },
{ .description = "Green Monochrome", .value = 1 },
{ .description = "Amber Monochrome", .value = 2 },
{ .description = "White Monochrome", .value = 3 },
{ .description = "" }
},
},
{
.name = "codepage",
.description = "Hardware font",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "US English", .value = 3 },
{ .description = "Portugese", .value = 2 },
{ .description = "Norwegian", .value = 1 },
{ .description = "Greek", .value = 0 },
{ .description = "" }
},
},
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "German", .value = 6 },
{ .description = "French", .value = 5 },
{ .description = "Spanish", .value = 4 },
{ .description = "Danish", .value = 3 },
{ .description = "Swedish", .value = 2 },
{ .description = "Italian", .value = 1 },
{ .description = "Diagnostic mode", .value = 0 },
{ .description = "" }
}
},
{
.name = "invert",
.description = "Invert LCD colors",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 0
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_ppc512_device = {
.name = "Amstrad PPC512 (video)",
.internal_name = "vid_ppc512",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close_200,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed_200,
.force_redraw = NULL,
.config = vid_ppc512_config
};
const device_config_t vid_pc2086_config[] = {
// clang-format off
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "Diagnostic mode", .value = 0 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_pc2086_device = {
.name = "Amstrad PC2086",
.internal_name = "vid_pc2086",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = vid_pc2086_config
};
const device_config_t vid_pc3086_config[] = {
// clang-format off
{
.name = "language",
.description = "BIOS language",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "English", .value = 7 },
{ .description = "Diagnostic mode", .value = 3 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_pc3086_device = {
.name = "Amstrad PC3086",
.internal_name = "vid_pc3086",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = vid_pc3086_config
};
static void
ms_write(uint16_t addr, UNUSED(uint8_t val), UNUSED(void *priv))
{
if ((addr == 0x78) || (addr == 0x79))
mouse_clear_x();
else
mouse_clear_y();
}
static uint8_t
ms_read(uint16_t addr, UNUSED(void *priv))
{
uint8_t ret;
int delta = 0;
if ((addr == 0x78) || (addr == 0x79)) {
mouse_subtract_x(&delta, NULL, -128, 127, 0);
mouse_clear_x();
} else {
mouse_subtract_y(&delta, NULL, -128, 127, 1, 0);
mouse_clear_y();
}
ret = (uint8_t) (int8_t) delta;
return ret;
}
static int
ms_poll(void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
int b = mouse_get_buttons_ex();
if ((b & 1) && !(ams->oldb & 1))
keyboard_send(0x7e);
if (!(b & 1) && (ams->oldb & 1))
keyboard_send(0xfe);
if ((b & 2) && !(ams->oldb & 2))
keyboard_send(0x7d);
if (!(b & 2) && (ams->oldb & 2))
keyboard_send(0xfd);
ams->oldb = b;
return 0;
}
static void
kbd_adddata(uint16_t val)
{
key_queue[key_queue_end] = val;
key_queue_end = (key_queue_end + 1) & 0xf;
}
static void
kbd_adddata_ex(uint16_t val)
{
kbd_adddata_process(val, kbd_adddata);
}
static void
kbd_write(uint16_t port, uint8_t val, void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
amstrad_log("keyboard_amstrad : write %04X %02X %02X\n", port, val, ams->pb);
switch (port) {
case 0x61:
/*
* PortB - System Control.
*
* 7 Enable Status-1/Disable Keyboard Code on Port A.
* 6 Enable incoming Keyboard Clock.
* 5 Prevent external parity errors from causing NMI.
* 4 Disable parity checking of on-board system Ram.
* 3 Undefined (Not Connected).
* 2 Enable Port C LSB / Disable MSB. (See 1.8.3)
* 1 Speaker Drive.
* 0 8253 GATE 2 (Speaker Modulate).
*
* This register is controlled by BIOS and/or ROS.
*/
amstrad_log("AMSkb: write PB %02x (%02x)\n", val, ams->pb);
if (!(ams->pb & 0x40) && (val & 0x40)) { /*Reset keyboard*/
amstrad_log("AMSkb: reset keyboard\n");
kbd_adddata(0xaa);
}
ams->pb = val;
ppi.pb = val;
speaker_update();
speaker_gated = val & 0x01;
speaker_enable = val & 0x02;
if (speaker_enable)
was_speaker_enable = 1;
pit_devs[0].set_gate(pit_devs[0].data, 2, val & 0x01);
if (val & 0x80) {
/* Keyboard enabled, so enable PA reading. */
ams->pa = 0x00;
}
break;
case 0x63:
break;
case 0x64:
ams->stat1 = val;
break;
case 0x65:
ams->stat2 = val;
break;
case 0x66:
softresetx86();
break;
default:
amstrad_log("AMSkb: bad keyboard write %04X %02X\n", port, val);
}
}
static uint8_t
kbd_read(uint16_t port, void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x60:
if (ams->pb & 0x80) {
/*
* PortA - System Status 1
*
* 7 Always 0 (KBD7)
* 6 Second Floppy disk drive installed (KBD6)
* 5 DDM1 - Default Display Mode bit 1 (KBD5)
* 4 DDM0 - Default Display Mode bit 0 (KBD4)
* 3 Always 1 (KBD3)
* 2 Always 1 (KBD2)
* 1 8087 NDP installed (KBD1)
* 0 Always 1 (KBD0)
*
* DDM00
* 00 unknown, external color?
* 01 Color,alpha,40x25, bright white on black.
* 10 Color,alpha,80x25, bright white on black.
* 11 External Monochrome,80x25.
*
* Following a reset, the hardware selects VDU mode
* 2. The ROS then sets the initial VDU state based
* on the DDM value.
*/
ret = (ams->stat1 | 0x0d) & 0x7f;
} else {
ret = ams->pa;
if (key_queue_start == key_queue_end)
ams->wantirq = 0;
else {
ams->key_waiting = key_queue[key_queue_start];
key_queue_start = (key_queue_start + 1) & 0xf;
ams->wantirq = 1;
}
}
break;
case 0x61:
ret = ams->pb;
break;
case 0x62:
/*
* PortC - System Status 2.
*
* 7 On-board system RAM parity error.
* 6 External parity error (I/OCHCK from expansion bus).
* 5 8253 PIT OUT2 output.
* 4 Undefined (Not Connected).
*-------------------------------------------
* LSB MSB (depends on PB2)
*-------------------------------------------
* 3 RAM3 Undefined
* 2 RAM2 Undefined
* 1 RAM1 Undefined
* 0 RAM0 RAM4
*
* PC7 is forced to 0 when on-board system RAM parity
* checking is disabled by PB4.
*
* RAM4:0
* 01110 512K bytes on-board.
* 01111 544K bytes (32K external).
* 10000 576K bytes (64K external).
* 10001 608K bytes (96K external).
* 10010 640K bytes (128K external or fitted on-board).
*/
if (ams->pb & 0x04)
ret = ams->stat2 & 0x0f;
else
ret = ams->stat2 >> 4;
ret |= (ppispeakon ? 0x20 : 0);
if (nmi)
ret |= 0x40;
break;
default:
amstrad_log("AMDkb: bad keyboard read %04X\n", port);
}
return ret;
}
static void
kbd_poll(void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
timer_advance_u64(&ams->send_delay_timer, 1000 * TIMER_USEC);
if (ams->wantirq) {
ams->wantirq = 0;
ams->pa = ams->key_waiting;
picint(2);
}
if (key_queue_start != key_queue_end && !ams->pa) {
ams->key_waiting = key_queue[key_queue_start];
key_queue_start = (key_queue_start + 1) & 0x0f;
ams->wantirq = 1;
}
}
static void
ams_write(uint16_t port, uint8_t val, void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
switch (port) {
case 0x0378:
case 0x0379:
case 0x037a:
lpt_write(port, val, &lpt_ports[0]);
break;
case 0xdead:
ams->dead = val;
break;
default:
break;
}
}
static uint8_t
ams_read(uint16_t port, void *priv)
{
amstrad_t *ams = (amstrad_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x0378:
ret = lpt_read(port, &lpt_ports[0]);
break;
case 0x0379: /* printer control, also set LK1-3.
* per John Elliott's site, this is xor'ed with 0x07
* 7 English Language.
* 6 German Language.
* 5 French Language.
* 4 Spanish Language.
* 3 Danish Language.
* 2 Swedish Language.
* 1 Italian Language.
* 0 Diagnostic Mode.
*/
ret = (lpt_read(port, &lpt_ports[0]) & 0xf8) | ams->language;
break;
case 0x037a: /* printer status */
ret = lpt_read(port, &lpt_ports[0]) & 0x1f;
switch (ams->type) {
case AMS_PC1512:
ret |= 0x20;
break;
case AMS_PC200:
case AMS_PPC512:
if (video_is_cga())
ret |= 0x80;
else if (video_is_mda())
ret |= 0xc0;
if (fdc_read(0x037f, ams->fdc) & 0x80)
ret |= 0x20;
break;
case AMS_PC1640:
if (video_is_cga())
ret |= 0x80;
else if (video_is_mda())
ret |= 0xc0;
switch (amstrad_latch & 0x7fffffff) {
case AMSTRAD_NOLATCH:
ret &= ~0x20;
break;
case AMSTRAD_SW9:
ret &= ~0x20;
break;
case AMSTRAD_SW10:
ret |= 0x20;
break;
default:
break;
}
break;
default:
break;
}
break;
case 0x03de:
ret = 0x20;
break;
case 0xdead:
ret = ams->dead;
break;
default:
break;
}
return ret;
}
static const scancode scancode_pc200[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 012 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 022 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 053 */
{ .mk = { 0x54, 0 }, .brk = { 0xd4, 0 } }, /* 054 */
{ .mk = { 0x55, 0 }, .brk = { 0xd5, 0 } }, /* 055 */
{ .mk = { 0x56, 0 }, .brk = { 0xd6, 0 } }, /* 056 */
{ .mk = { 0x57, 0 }, .brk = { 0xd7, 0 } }, /* 057 */
{ .mk = { 0x58, 0 }, .brk = { 0xd8, 0 } }, /* 058 */
{ .mk = { 0x59, 0 }, .brk = { 0xd9, 0 } }, /* 059 */
{ .mk = { 0x5a, 0 }, .brk = { 0xda, 0 } }, /* 05a */
{ .mk = { 0x5b, 0 }, .brk = { 0xdb, 0 } }, /* 05b */
{ .mk = { 0x5c, 0 }, .brk = { 0xdc, 0 } }, /* 05c */
{ .mk = { 0x5d, 0 }, .brk = { 0xdd, 0 } }, /* 05d */
{ .mk = { 0x5e, 0 }, .brk = { 0xde, 0 } }, /* 05e */
{ .mk = { 0x5f, 0 }, .brk = { 0xdf, 0 } }, /* 05f */
{ .mk = { 0x60, 0 }, .brk = { 0xe0, 0 } }, /* 060 */
{ .mk = { 0x61, 0 }, .brk = { 0xe1, 0 } }, /* 061 */
{ .mk = { 0x62, 0 }, .brk = { 0xe2, 0 } }, /* 062 */
{ .mk = { 0x63, 0 }, .brk = { 0xe3, 0 } }, /* 063 */
{ .mk = { 0x64, 0 }, .brk = { 0xe4, 0 } }, /* 064 */
{ .mk = { 0x65, 0 }, .brk = { 0xe5, 0 } }, /* 065 */
{ .mk = { 0x66, 0 }, .brk = { 0xe6, 0 } }, /* 066 */
{ .mk = { 0x67, 0 }, .brk = { 0xe7, 0 } }, /* 067 */
{ .mk = { 0x68, 0 }, .brk = { 0xe8, 0 } }, /* 068 */
{ .mk = { 0x69, 0 }, .brk = { 0xe9, 0 } }, /* 069 */
{ .mk = { 0x6a, 0 }, .brk = { 0xea, 0 } }, /* 06a */
{ .mk = { 0x6b, 0 }, .brk = { 0xeb, 0 } }, /* 06b */
{ .mk = { 0x6c, 0 }, .brk = { 0xec, 0 } }, /* 06c */
{ .mk = { 0x6d, 0 }, .brk = { 0xed, 0 } }, /* 06d */
{ .mk = { 0x6e, 0 }, .brk = { 0xee, 0 } }, /* 06e */
{ .mk = { 0x6f, 0 }, .brk = { 0xef, 0 } }, /* 06f */
{ .mk = { 0x70, 0 }, .brk = { 0xf0, 0 } }, /* 070 */
{ .mk = { 0x71, 0 }, .brk = { 0xf1, 0 } }, /* 071 */
{ .mk = { 0x72, 0 }, .brk = { 0xf2, 0 } }, /* 072 */
{ .mk = { 0x73, 0 }, .brk = { 0xf3, 0 } }, /* 073 */
{ .mk = { 0x74, 0 }, .brk = { 0xf4, 0 } }, /* 074 */
{ .mk = { 0x75, 0 }, .brk = { 0xf5, 0 } }, /* 075 */
{ .mk = { 0x76, 0 }, .brk = { 0xf6, 0 } }, /* 076 */
{ .mk = { 0x77, 0 }, .brk = { 0xf7, 0 } }, /* 077 */
{ .mk = { 0x78, 0 }, .brk = { 0xf8, 0 } }, /* 078 */
{ .mk = { 0x79, 0 }, .brk = { 0xf9, 0 } }, /* 079 */
{ .mk = { 0x7a, 0 }, .brk = { 0xfa, 0 } }, /* 07a */
{ .mk = { 0x7b, 0 }, .brk = { 0xfb, 0 } }, /* 07b */
{ .mk = { 0x7c, 0 }, .brk = { 0xfc, 0 } }, /* 07c */
{ .mk = { 0x7d, 0 }, .brk = { 0xfd, 0 } }, /* 07d */
{ .mk = { 0x7e, 0 }, .brk = { 0xfe, 0 } }, /* 07e */
{ .mk = { 0x7f, 0 }, .brk = { 0xff, 0 } }, /* 07f */
{ .mk = { 0x80, 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0x81, 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0x82, 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0x85, 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0x86, 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0x87, 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0x88, 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0x89, 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0x8a, 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0x8b, 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0x8c, 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0x8d, 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0x8e, 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0x8f, 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0x90, 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0x91, 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0x92, 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0x93, 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0x94, 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0x95, 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0x96, 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0x97, 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0x98, 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0x99, 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0x9a, 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0x9b, 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0x9c, 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0x9d, 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0x9e, 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0x9f, 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0xa0, 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0xa1, 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0xa2, 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0xa3, 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0xa4, 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0xa5, 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0xa6, 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0xa7, 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0xa8, 0 }, .brk = { 0 } }, /* 0a8 */
{ .mk = { 0xa9, 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0xaa, 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0xab, 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0xac, 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0xad, 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0xae, 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0xaf, 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0xb0, 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0xb1, 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0xb2, 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0xb3, 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0xb4, 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0xb5, 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0xb6, 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0xb7, 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0xb8, 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0xb9, 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0xba, 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0xbb, 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0xbc, 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0xbd, 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0xbe, 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0xbf, 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0xc0, 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0xc1, 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0xc2, 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0xc3, 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0xc4, 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0xc5, 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0xc6, 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0xc7, 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0xc8, 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0xc9, 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0xca, 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0xcb, 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0xcc, 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0xcd, 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0xce, 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0xcf, 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0xd0, 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0xd1, 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0xd2, 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0xd3, 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0xd4, 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0xd5, 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0xd6, 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0xd7, 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0xd8, 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0xd9, 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0xda, 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0xdb, 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0xdc, 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0xdd, 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0xde, 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0xdf, 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0xe0, 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0xe1, 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0xe2, 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0xe3, 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0xe4, 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0xe5, 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0xe6, 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0xe7, 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0xe8, 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0xe9, 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0xea, 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0xeb, 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0xec, 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0xed, 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0xee, 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0xef, 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0xf1, 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0xf2, 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0xf3, 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0xf4, 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0xf5, 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0xf6, 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0xf7, 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0xf8, 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0xf9, 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0xfa, 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0xfb, 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0xfc, 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0xfd, 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0xfe, 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0xff, 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = {0xe1, 0x1d, 0 }, .brk = { 0xe1, 0x9d, 0 } }, /* 100 */
{ .mk = {0xe0, 0x01, 0 }, .brk = { 0xe0, 0x81, 0 } }, /* 101 */
{ .mk = {0xe0, 0x02, 0 }, .brk = { 0xe0, 0x82, 0 } }, /* 102 */
{ .mk = {0xe0, 0x03, 0 }, .brk = { 0xe0, 0x83, 0 } }, /* 103 */
{ .mk = {0xe0, 0x04, 0 }, .brk = { 0xe0, 0x84, 0 } }, /* 104 */
{ .mk = {0xe0, 0x05, 0 }, .brk = { 0xe0, 0x85, 0 } }, /* 105 */
{ .mk = {0xe0, 0x06, 0 }, .brk = { 0xe0, 0x86, 0 } }, /* 106 */
{ .mk = {0xe0, 0x07, 0 }, .brk = { 0xe0, 0x87, 0 } }, /* 107 */
{ .mk = {0xe0, 0x08, 0 }, .brk = { 0xe0, 0x88, 0 } }, /* 108 */
{ .mk = {0xe0, 0x09, 0 }, .brk = { 0xe0, 0x89, 0 } }, /* 109 */
{ .mk = {0xe0, 0x0a, 0 }, .brk = { 0xe0, 0x8a, 0 } }, /* 10a */
{ .mk = {0xe0, 0x0b, 0 }, .brk = { 0xe0, 0x8b, 0 } }, /* 10b */
{ .mk = {0xe0, 0x0c, 0 }, .brk = { 0xe0, 0x8c, 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = {0xe0, 0x0e, 0 }, .brk = { 0xe0, 0x8e, 0 } }, /* 10e */
{ .mk = {0xe0, 0x0f, 0 }, .brk = { 0xe0, 0x8f, 0 } }, /* 10f */
{ .mk = {0xe0, 0x10, 0 }, .brk = { 0xe0, 0x90, 0 } }, /* 110 */
{ .mk = {0xe0, 0x11, 0 }, .brk = { 0xe0, 0x91, 0 } }, /* 111 */
{ .mk = {0xe0, 0x12, 0 }, .brk = { 0xe0, 0x92, 0 } }, /* 112 */
{ .mk = {0xe0, 0x13, 0 }, .brk = { 0xe0, 0x93, 0 } }, /* 113 */
{ .mk = {0xe0, 0x14, 0 }, .brk = { 0xe0, 0x94, 0 } }, /* 114 */
{ .mk = {0xe0, 0x15, 0 }, .brk = { 0xe0, 0x95, 0 } }, /* 115 */
{ .mk = {0xe0, 0x16, 0 }, .brk = { 0xe0, 0x96, 0 } }, /* 116 */
{ .mk = {0xe0, 0x17, 0 }, .brk = { 0xe0, 0x97, 0 } }, /* 117 */
{ .mk = {0xe0, 0x18, 0 }, .brk = { 0xe0, 0x98, 0 } }, /* 118 */
{ .mk = {0xe0, 0x19, 0 }, .brk = { 0xe0, 0x99, 0 } }, /* 119 */
{ .mk = {0xe0, 0x1a, 0 }, .brk = { 0xe0, 0x9a, 0 } }, /* 11a */
{ .mk = {0xe0, 0x1b, 0 }, .brk = { 0xe0, 0x9b, 0 } }, /* 11b */
{ .mk = {0xe0, 0x1c, 0 }, .brk = { 0xe0, 0x9c, 0 } }, /* 11c */
{ .mk = {0xe0, 0x1d, 0 }, .brk = { 0xe0, 0x9d, 0 } }, /* 11d */
{ .mk = {0xe0, 0x1e, 0 }, .brk = { 0xe0, 0x9e, 0 } }, /* 11e */
{ .mk = {0xe0, 0x1f, 0 }, .brk = { 0xe0, 0x9f, 0 } }, /* 11f */
{ .mk = {0xe0, 0x20, 0 }, .brk = { 0xe0, 0xa0, 0 } }, /* 120 */
{ .mk = {0xe0, 0x21, 0 }, .brk = { 0xe0, 0xa1, 0 } }, /* 121 */
{ .mk = {0xe0, 0x22, 0 }, .brk = { 0xe0, 0xa2, 0 } }, /* 122 */
{ .mk = {0xe0, 0x23, 0 }, .brk = { 0xe0, 0xa3, 0 } }, /* 123 */
{ .mk = {0xe0, 0x24, 0 }, .brk = { 0xe0, 0xa4, 0 } }, /* 124 */
{ .mk = {0xe0, 0x25, 0 }, .brk = { 0xe0, 0xa5, 0 } }, /* 125 */
{ .mk = {0xe0, 0x26, 0 }, .brk = { 0xe0, 0xa6, 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = {0xe0, 0x2c, 0 }, .brk = { 0xe0, 0xac, 0 } }, /* 12c */
{ .mk = {0xe0, 0x2d, 0 }, .brk = { 0xe0, 0xad, 0 } }, /* 12d */
{ .mk = {0xe0, 0x2e, 0 }, .brk = { 0xe0, 0xae, 0 } }, /* 12e */
{ .mk = {0xe0, 0x2f, 0 }, .brk = { 0xe0, 0xaf, 0 } }, /* 12f */
{ .mk = {0xe0, 0x30, 0 }, .brk = { 0xe0, 0xb0, 0 } }, /* 130 */
{ .mk = {0xe0, 0x31, 0 }, .brk = { 0xe0, 0xb1, 0 } }, /* 131 */
{ .mk = {0xe0, 0x32, 0 }, .brk = { 0xe0, 0xb2, 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = {0xe0, 0x34, 0 }, .brk = { 0xe0, 0xb4, 0 } }, /* 134 */
{ .mk = {0xe0, 0x35, 0 }, .brk = { 0xe0, 0xb5, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = {0xe0, 0x37, 0 }, .brk = { 0xe0, 0xb7, 0 } }, /* 137 */
{ .mk = {0xe0, 0x38, 0 }, .brk = { 0xe0, 0xb8, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = {0xe0, 0x3a, 0 }, .brk = { 0xe0, 0xba, 0 } }, /* 13a */
{ .mk = {0xe0, 0x3b, 0 }, .brk = { 0xe0, 0xbb, 0 } }, /* 13b */
{ .mk = {0xe0, 0x3c, 0 }, .brk = { 0xe0, 0xbc, 0 } }, /* 13c */
{ .mk = {0xe0, 0x3d, 0 }, .brk = { 0xe0, 0xbd, 0 } }, /* 13d */
{ .mk = {0xe0, 0x3e, 0 }, .brk = { 0xe0, 0xbe, 0 } }, /* 13e */
{ .mk = {0xe0, 0x3f, 0 }, .brk = { 0xe0, 0xbf, 0 } }, /* 13f */
{ .mk = {0xe0, 0x40, 0 }, .brk = { 0xe0, 0xc0, 0 } }, /* 140 */
{ .mk = {0xe0, 0x41, 0 }, .brk = { 0xe0, 0xc1, 0 } }, /* 141 */
{ .mk = {0xe0, 0x42, 0 }, .brk = { 0xe0, 0xc2, 0 } }, /* 142 */
{ .mk = {0xe0, 0x43, 0 }, .brk = { 0xe0, 0xc3, 0 } }, /* 143 */
{ .mk = {0xe0, 0x44, 0 }, .brk = { 0xe0, 0xc4, 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = {0xe0, 0x46, 0 }, .brk = { 0xe0, 0xc6, 0 } }, /* 146 */
{ .mk = {0xe0, 0x47, 0 }, .brk = { 0xe0, 0xc7, 0 } }, /* 147 */
{ .mk = {0xe0, 0x48, 0 }, .brk = { 0xe0, 0xc8, 0 } }, /* 148 */
{ .mk = {0xe0, 0x49, 0 }, .brk = { 0xe0, 0xc9, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = {0xe0, 0x4b, 0 }, .brk = { 0xe0, 0xcb, 0 } }, /* 14b */
{ .mk = {0xe0, 0x4c, 0 }, .brk = { 0xe0, 0xcc, 0 } }, /* 14c */
{ .mk = {0xe0, 0x4d, 0 }, .brk = { 0xe0, 0xcd, 0 } }, /* 14d */
{ .mk = {0xe0, 0x4e, 0 }, .brk = { 0xe0, 0xce, 0 } }, /* 14e */
{ .mk = {0xe0, 0x4f, 0 }, .brk = { 0xe0, 0xcf, 0 } }, /* 14f */
{ .mk = {0xe0, 0x50, 0 }, .brk = { 0xe0, 0xd0, 0 } }, /* 150 */
{ .mk = {0xe0, 0x51, 0 }, .brk = { 0xe0, 0xd1, 0 } }, /* 151 */
{ .mk = {0xe0, 0x52, 0 }, .brk = { 0xe0, 0xd2, 0 } }, /* 152 */
{ .mk = {0xe0, 0x53, 0 }, .brk = { 0xe0, 0xd3, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = {0xe0, 0x55, 0 }, .brk = { 0xe0, 0xd5, 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = {0xe0, 0x57, 0 }, .brk = { 0xe0, 0xd7, 0 } }, /* 157 */
{ .mk = {0xe0, 0x58, 0 }, .brk = { 0xe0, 0xd8, 0 } }, /* 158 */
{ .mk = {0xe0, 0x59, 0 }, .brk = { 0xe0, 0xd9, 0 } }, /* 159 */
{ .mk = {0xe0, 0x5a, 0 }, .brk = { 0xe0, 0xaa, 0 } }, /* 15a */
{ .mk = {0xe0, 0x5b, 0 }, .brk = { 0xe0, 0xdb, 0 } }, /* 15b */
{ .mk = {0xe0, 0x5c, 0 }, .brk = { 0xe0, 0xdc, 0 } }, /* 15c */
{ .mk = {0xe0, 0x5d, 0 }, .brk = { 0xe0, 0xdd, 0 } }, /* 15d */
{ .mk = {0xe0, 0x5e, 0 }, .brk = { 0xe0, 0xee, 0 } }, /* 15e */
{ .mk = {0xe0, 0x5f, 0 }, .brk = { 0xe0, 0xdf, 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = {0xe0, 0x61, 0 }, .brk = { 0xe0, 0xe1, 0 } }, /* 161 */
{ .mk = {0xe0, 0x62, 0 }, .brk = { 0xe0, 0xe2, 0 } }, /* 162 */
{ .mk = {0xe0, 0x63, 0 }, .brk = { 0xe0, 0xe3, 0 } }, /* 163 */
{ .mk = {0xe0, 0x64, 0 }, .brk = { 0xe0, 0xe4, 0 } }, /* 164 */
{ .mk = {0xe0, 0x65, 0 }, .brk = { 0xe0, 0xe5, 0 } }, /* 165 */
{ .mk = {0xe0, 0x66, 0 }, .brk = { 0xe0, 0xe6, 0 } }, /* 166 */
{ .mk = {0xe0, 0x67, 0 }, .brk = { 0xe0, 0xe7, 0 } }, /* 167 */
{ .mk = {0xe0, 0x68, 0 }, .brk = { 0xe0, 0xe8, 0 } }, /* 168 */
{ .mk = {0xe0, 0x69, 0 }, .brk = { 0xe0, 0xe9, 0 } }, /* 169 */
{ .mk = {0xe0, 0x6a, 0 }, .brk = { 0xe0, 0xea, 0 } }, /* 16a */
{ .mk = {0xe0, 0x6b, 0 }, .brk = { 0xe0, 0xeb, 0 } }, /* 16b */
{ .mk = {0xe0, 0x6c, 0 }, .brk = { 0xe0, 0xec, 0 } }, /* 16c */
{ .mk = {0xe0, 0x6d, 0 }, .brk = { 0xe0, 0xed, 0 } }, /* 16d */
{ .mk = {0xe0, 0x6e, 0 }, .brk = { 0xe0, 0xee, 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = {0xe0, 0x70, 0 }, .brk = { 0xe0, 0xf0, 0 } }, /* 170 */
{ .mk = {0xe0, 0x71, 0 }, .brk = { 0xe0, 0xf1, 0 } }, /* 171 */
{ .mk = {0xe0, 0x72, 0 }, .brk = { 0xe0, 0xf2, 0 } }, /* 172 */
{ .mk = {0xe0, 0x73, 0 }, .brk = { 0xe0, 0xf3, 0 } }, /* 173 */
{ .mk = {0xe0, 0x74, 0 }, .brk = { 0xe0, 0xf4, 0 } }, /* 174 */
{ .mk = {0xe0, 0x75, 0 }, .brk = { 0xe0, 0xf5, 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = {0xe0, 0x77, 0 }, .brk = { 0xe0, 0xf7, 0 } }, /* 177 */
{ .mk = {0xe0, 0x78, 0 }, .brk = { 0xe0, 0xf8, 0 } }, /* 178 */
{ .mk = {0xe0, 0x79, 0 }, .brk = { 0xe0, 0xf9, 0 } }, /* 179 */
{ .mk = {0xe0, 0x7a, 0 }, .brk = { 0xe0, 0xfa, 0 } }, /* 17a */
{ .mk = {0xe0, 0x7b, 0 }, .brk = { 0xe0, 0xfb, 0 } }, /* 17b */
{ .mk = {0xe0, 0x7c, 0 }, .brk = { 0xe0, 0xfc, 0 } }, /* 17c */
{ .mk = {0xe0, 0x7d, 0 }, .brk = { 0xe0, 0xfd, 0 } }, /* 17d */
{ .mk = {0xe0, 0x7e, 0 }, .brk = { 0xe0, 0xfe, 0 } }, /* 17e */
{ .mk = {0xe0, 0x7f, 0 }, .brk = { 0xe0, 0xff, 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = {0xe0, 0xe1, 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = {0xe0, 0xee, 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = {0xe0, 0xf1, 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = {0xe0, 0xfe, 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = {0xe0, 0xff, 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
static void
machine_amstrad_init(const machine_t *model, int type)
{
amstrad_t *ams;
ams = (amstrad_t *) malloc(sizeof(amstrad_t));
memset(ams, 0x00, sizeof(amstrad_t));
ams->type = type;
amstrad_latch = 0x80000000;
switch (type) {
case AMS_PC200:
case AMS_PPC512:
device_add(&amstrad_no_nmi_nvr_device);
break;
default:
device_add(&amstrad_nvr_device);
break;
}
machine_common_init(model);
nmi_init();
lpt1_remove_ams();
lpt2_remove();
io_sethandler(0x0378, 3,
ams_read, NULL, NULL, ams_write, NULL, NULL, ams);
io_sethandler(0xdead, 1,
ams_read, NULL, NULL, ams_write, NULL, NULL, ams);
switch (type) {
case AMS_PC1512:
case AMS_PC1640:
case AMS_PC200:
case AMS_PPC512:
ams->fdc = device_add(&fdc_xt_device);
break;
case AMS_PC2086:
case AMS_PC3086:
ams->fdc = device_add(&fdc_at_actlow_device);
break;
default:
break;
}
ams->language = 7;
video_reset(gfxcard[0]);
if (gfxcard[0] == VID_INTERNAL)
switch (type) {
case AMS_PC1512:
loadfont("roms/machines/pc1512/40078", 8);
device_context(&vid_1512_device);
ams->language = device_get_config_int("language");
vid_init_1512(ams);
device_context_restore();
device_add_ex(&vid_1512_device, ams->vid);
break;
case AMS_PPC512:
loadfont("roms/machines/ppc512/40109", 1);
device_context(&vid_ppc512_device);
ams->language = device_get_config_int("language");
vid_init_200(ams);
device_context_restore();
device_add_ex(&vid_ppc512_device, ams->vid);
break;
case AMS_PC1640:
loadfont("roms/video/mda/mda.rom", 0);
device_context(&vid_1640_device);
ams->language = device_get_config_int("language");
vid_init_1640(ams);
device_context_restore();
device_add_ex(&vid_1640_device, ams->vid);
break;
case AMS_PC200:
loadfont("roms/machines/pc200/40109", 1);
device_context(&vid_200_device);
ams->language = device_get_config_int("language");
vid_init_200(ams);
device_context_restore();
device_add_ex(&vid_200_device, ams->vid);
break;
case AMS_PC2086:
device_context(&vid_pc2086_device);
ams->language = device_get_config_int("language");
device_context_restore();
device_add(¶dise_pvga1a_pc2086_device);
break;
case AMS_PC3086:
device_context(&vid_pc3086_device);
ams->language = device_get_config_int("language");
device_context_restore();
device_add(¶dise_pvga1a_pc3086_device);
break;
default:
break;
}
else if ((type == AMS_PC200) || (type == AMS_PPC512))
io_sethandler(0x03de, 1,
ams_read, NULL, NULL, ams_write, NULL, NULL, ams);
/* Initialize the (custom) keyboard/mouse interface. */
ams->wantirq = 0;
io_sethandler(0x0060, 7,
kbd_read, NULL, NULL, kbd_write, NULL, NULL, ams);
timer_add(&ams->send_delay_timer, kbd_poll, ams, 1);
if (type == AMS_PC1512)
keyboard_set_table(scancode_xt);
else
keyboard_set_table(scancode_pc200);
keyboard_send = kbd_adddata_ex;
keyboard_scan = 1;
keyboard_set_is_amstrad(((type == AMS_PC1512) || (type == AMS_PC1640)) ? 0 : 1);
io_sethandler(0x0078, 2,
ms_read, NULL, NULL, ms_write, NULL, NULL, ams);
io_sethandler(0x007a, 2,
ms_read, NULL, NULL, ms_write, NULL, NULL, ams);
if (mouse_type == MOUSE_TYPE_INTERNAL) {
/* Tell mouse driver about our internal mouse. */
mouse_reset();
mouse_set_buttons(2);
mouse_set_poll(ms_poll, ams);
}
standalone_gameport_type = &gameport_device;
}
int
machine_pc1512_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/pc1512/40044",
"roms/machines/pc1512/40043",
0x000fc000, 16384, 0);
ret &= rom_present("roms/machines/pc1512/40078");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PC1512);
return ret;
}
int
machine_pc1640_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/pc1640/40044.v3",
"roms/machines/pc1640/40043.v3",
0x000fc000, 16384, 0);
ret &= rom_present("roms/machines/pc1640/40100");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PC1640);
return ret;
}
int
machine_pc200_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/pc200/pc20v2.1",
"roms/machines/pc200/pc20v2.0",
0x000fc000, 16384, 0);
ret &= rom_present("roms/machines/pc200/40109");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PC200);
return ret;
}
int
machine_ppc512_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ppc512/40107.v2",
"roms/machines/ppc512/40108.v2",
0x000fc000, 16384, 0);
ret &= rom_present("roms/machines/ppc512/40109");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PPC512);
return ret;
}
int
machine_pc2086_init(const machine_t *model)
{
int ret;
ret = bios_load_interleavedr("roms/machines/pc2086/40179.ic129",
"roms/machines/pc2086/40180.ic132",
0x000fc000, 65536, 0);
ret &= rom_present("roms/machines/pc2086/40186.ic171");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PC2086);
return ret;
}
int
machine_pc3086_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/pc3086/fc00.bin",
0x000fc000, 65536, 0);
ret &= rom_present("roms/machines/pc3086/c000.bin");
if (bios_only || !ret)
return ret;
machine_amstrad_init(model, AMS_PC3086);
return ret;
}
``` | /content/code_sandbox/src/machine/m_amstrad.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 42,616 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Olivetti XT-compatible machines.
*
* - Supports MM58174 real-time clock emulation (M24)
* - Supports MM58274 real-time clock emulation (M240)
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* EngiNerd <webmaster.crrc@yahoo.it>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#include <stdarg.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/ppi.h>
#include <86box/nmi.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/mouse.h>
#include <86box/rom.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/serial.h>
#include <86box/sound.h>
#include <86box/snd_speaker.h>
#include <86box/video.h>
#include <86box/machine.h>
#include <86box/vid_cga.h>
#include <86box/vid_ogc.h>
#include <86box/vid_colorplus.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
#define STAT_PARITY 0x80
#define STAT_RTIMEOUT 0x40
#define STAT_TTIMEOUT 0x20
#define STAT_LOCK 0x10
#define STAT_CD 0x08
#define STAT_SYSFLAG 0x04
#define STAT_IFULL 0x02
#define STAT_OFULL 0x01
#define PLANTRONICS_MODE 1
#define OLIVETTI_OGC_MODE 0
#define CGA_RGB 0
#define CGA_COMPOSITE 1
enum MM58174_ADDR {
/* Registers */
MM58174_TEST, /* TEST register, write only */
MM58174_TENTHS, /* Tenths of second, read only */
MM58174_SECOND1, /* Units of seconds, read only */
MM58174_SECOND10, /* Tens of seconds, read only */
MM58174_MINUTE1,
MM58174_MINUTE10,
MM58174_HOUR1,
MM58174_HOUR10,
MM58174_DAY1,
MM58174_DAY10,
MM58174_WEEKDAY,
MM58174_MONTH1,
MM58174_MONTH10,
MM58174_LEAPYEAR, /* Leap year status, write only */
MM58174_RESET, /* RESET register, write only */
MM58174_IRQ /* Interrupt register, read / write */
};
enum MM58274_ADDR {
/* Registers */
MM58274_CONTROL, /* Control register */
MM58274_TENTHS, /* Tenths of second, read only */
MM58274_SECOND1,
MM58274_SECOND10,
MM58274_MINUTE1,
MM58274_MINUTE10,
MM58274_HOUR1,
MM58274_HOUR10,
MM58274_DAY1,
MM58274_DAY10,
MM58274_MONTH1,
MM58274_MONTH10,
MM58274_YEAR1,
MM58274_YEAR10,
MM58274_WEEKDAY,
MM58274_SETTINGS /* Settings register */
};
static struct tm intclk;
typedef struct m24_kbd_t {
/* Keyboard stuff. */
int wantirq;
uint8_t command;
uint8_t status;
uint8_t out;
uint8_t output_port;
uint8_t id;
int param;
int param_total;
uint8_t params[16];
uint8_t scan[7];
/* Mouse stuff. */
int mouse_input_mode;
int b;
pc_timer_t send_delay_timer;
} m24_kbd_t;
typedef struct m19_vid_t {
ogc_t ogc;
colorplus_t colorplus;
int mode;
} m19_vid_t;
static uint8_t key_queue[16];
static int key_queue_start = 0;
static int key_queue_end = 0;
video_timings_t timing_m19_vid = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
const device_t m19_vid_device;
#ifdef ENABLE_XT_OLIVETTI_LOG
int xt_olivetti_do_log = ENABLE_XT_OLIVETTI_LOG;
static void
xt_olivetti_log(const char *fmt, ...)
{
va_list ap;
if (xt_olivetti_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define xt_olivetti_log(fmt, ...)
#endif
/* Set the chip time. */
static void
mm58174_time_set(uint8_t *regs, struct tm *tm)
{
regs[MM58174_SECOND1] = (tm->tm_sec % 10);
regs[MM58174_SECOND10] = (tm->tm_sec / 10);
regs[MM58174_MINUTE1] = (tm->tm_min % 10);
regs[MM58174_MINUTE10] = (tm->tm_min / 10);
regs[MM58174_HOUR1] = (tm->tm_hour % 10);
regs[MM58174_HOUR10] = (tm->tm_hour / 10);
regs[MM58174_WEEKDAY] = (tm->tm_wday + 1);
regs[MM58174_DAY1] = (tm->tm_mday % 10);
regs[MM58174_DAY10] = (tm->tm_mday / 10);
regs[MM58174_MONTH1] = ((tm->tm_mon + 1) % 10);
regs[MM58174_MONTH10] = ((tm->tm_mon + 1) / 10);
/* MM58174 does not store the year, M24 uses the IRQ register to count 8 years from leap year */
regs[MM58174_IRQ] = ((tm->tm_year + 1900) % 8);
regs[MM58174_LEAPYEAR] = 8 >> ((regs[MM58174_IRQ] & 0x07) & 0x03);
}
/* Get the chip time. */
#define nibbles(a) (regs[(a##1)] + 10 * regs[(a##10)])
static void
mm58174_time_get(uint8_t *regs, struct tm *tm)
{
tm->tm_sec = nibbles(MM58174_SECOND);
tm->tm_min = nibbles(MM58174_MINUTE);
tm->tm_hour = nibbles(MM58174_HOUR);
tm->tm_wday = (regs[MM58174_WEEKDAY] - 1);
tm->tm_mday = nibbles(MM58174_DAY);
tm->tm_mon = (nibbles(MM58174_MONTH) - 1);
/* MM58174 does not store the year */
tm->tm_year = (1984 + (regs[MM58174_IRQ] & 0x07) - 1900);
}
/* One more second has passed, update the internal clock. */
static void
mm58x74_recalc(void)
{
/* Ping the internal clock. */
if (++intclk.tm_sec == 60) {
intclk.tm_sec = 0;
if (++intclk.tm_min == 60) {
intclk.tm_min = 0;
if (++intclk.tm_hour == 24) {
intclk.tm_hour = 0;
if (++intclk.tm_mday == (nvr_get_days(intclk.tm_mon, intclk.tm_year) + 1)) {
intclk.tm_mday = 1;
if (++intclk.tm_mon == 13) {
intclk.tm_mon = 1;
intclk.tm_year++;
}
}
}
}
}
}
/* This is called every second through the NVR/RTC hook. */
static void
mm58174_tick(nvr_t *nvr)
{
mm58x74_recalc();
mm58174_time_set(nvr->regs, &intclk);
}
static void
mm58174_start(nvr_t *nvr)
{
struct tm tm;
/* Initialize the internal and chip times. */
if (time_sync & TIME_SYNC_ENABLED) {
/* Use the internal clock's time. */
nvr_time_get(&tm);
mm58174_time_set(nvr->regs, &tm);
} else {
/* Set the internal clock from the chip time. */
mm58174_time_get(nvr->regs, &tm);
nvr_time_set(&tm);
}
mm58174_time_get(nvr->regs, &intclk);
}
/* Write to one of the chip registers. */
static void
mm58174_write(uint16_t addr, uint8_t val, void *priv)
{
nvr_t *nvr = (nvr_t *) priv;
addr &= 0x0f;
val &= 0x0f;
/* Update non-read-only changed values if not synchronizing time to host */
if ((addr != MM58174_TENTHS) && (addr != MM58174_SECOND1) && (addr != MM58174_SECOND10))
if ((nvr->regs[addr] != val) && !(time_sync & TIME_SYNC_ENABLED))
nvr_dosave = 1;
if ((addr == MM58174_RESET) && (val & 0x01)) {
/* When timer starts, MM58174 sets seconds and tenths of second to 0 */
nvr->regs[MM58174_TENTHS] = 0;
if (!(time_sync & TIME_SYNC_ENABLED)) {
/* Only set seconds to 0 if not synchronizing time to host clock */
nvr->regs[MM58174_SECOND1] = 0;
nvr->regs[MM58174_SECOND10] = 0;
}
}
/* Store the new value */
nvr->regs[addr] = val;
/* Update internal clock with MM58174 time */
mm58174_time_get(nvr->regs, &intclk);
}
/* Read from one of the chip registers. */
static uint8_t
mm58174_read(uint16_t addr, void *priv)
{
nvr_t *nvr = (nvr_t *) priv;
addr &= 0x0f;
/* Set IRQ control bit to 0 upon read */
if (addr == 0x0f)
nvr->regs[addr] &= 0x07;
/* Grab and return the desired value */
return (nvr->regs[addr]);
}
/* Reset the MM58174 to a default state. */
static void
mm58174_reset(nvr_t *nvr)
{
/* Clear the NVRAM. */
memset(nvr->regs, 0xff, nvr->size);
/* Reset the RTC registers. */
memset(nvr->regs, 0x00, 16);
nvr->regs[MM58174_WEEKDAY] = 0x01;
nvr->regs[MM58174_DAY1] = 0x01;
nvr->regs[MM58174_MONTH1] = 0x01;
}
static void
mm58174_init(nvr_t *nvr, int size)
{
/* This is machine specific. */
nvr->size = size;
nvr->irq = -1;
/* Set up any local handlers here. */
nvr->reset = mm58174_reset;
nvr->start = mm58174_start;
nvr->tick = mm58174_tick;
/* Initialize the actual NVR. */
nvr_init(nvr);
io_sethandler(0x0070, 16,
mm58174_read, NULL, NULL, mm58174_write, NULL, NULL, nvr);
}
/* Set the chip time. */
static void
mm58274_time_set(uint8_t *regs, struct tm *tm)
{
regs[MM58274_SECOND1] = (tm->tm_sec % 10);
regs[MM58274_SECOND10] = (tm->tm_sec / 10);
regs[MM58274_MINUTE1] = (tm->tm_min % 10);
regs[MM58274_MINUTE10] = (tm->tm_min / 10);
regs[MM58274_HOUR1] = (tm->tm_hour % 10);
regs[MM58274_HOUR10] = (tm->tm_hour / 10);
/* Store hour in 24-hour or 12-hour mode */
if (regs[MM58274_SETTINGS] & 0x01) {
regs[MM58274_HOUR1] = (tm->tm_hour % 10);
regs[MM58274_HOUR10] = (tm->tm_hour / 10);
} else {
regs[MM58274_HOUR1] = ((tm->tm_hour % 12) % 10);
regs[MM58274_HOUR10] = ((tm->tm_hour % 12) / 10);
if (tm->tm_hour >= 12)
regs[MM58274_SETTINGS] |= 0x04;
else
regs[MM58274_SETTINGS] &= 0x0B;
}
regs[MM58274_WEEKDAY] = (tm->tm_wday + 1);
regs[MM58274_DAY1] = (tm->tm_mday % 10);
regs[MM58274_DAY10] = (tm->tm_mday / 10);
regs[MM58274_MONTH1] = ((tm->tm_mon + 1) % 10);
regs[MM58274_MONTH10] = ((tm->tm_mon + 1) / 10);
/* MM58274 can store 00 to 99 years but M240 uses the YEAR1 register to count 8 years from leap year */
regs[MM58274_YEAR1] = ((tm->tm_year + 1900) % 8);
/* Keep bit 0 and 1 12-hour / 24-hour and AM / PM */
regs[MM58274_SETTINGS] &= 0x03;
/* Set leap counter bits 2 and 3 */
regs[MM58274_SETTINGS] += (4 * (regs[MM58274_YEAR1] & 0x03));
}
/* Get the chip time. */
static void
mm58274_time_get(uint8_t *regs, struct tm *tm)
{
tm->tm_sec = nibbles(MM58274_SECOND);
tm->tm_min = nibbles(MM58274_MINUTE);
/* Read hour in 24-hour or 12-hour mode */
if (regs[MM58274_SETTINGS] & 0x01)
tm->tm_hour = nibbles(MM58274_HOUR);
else
tm->tm_hour = ((nibbles(MM58274_HOUR) % 12) + (regs[MM58274_SETTINGS] & 0x04) ? 12 : 0);
tm->tm_wday = (regs[MM58274_WEEKDAY] - 1);
tm->tm_mday = nibbles(MM58274_DAY);
tm->tm_mon = (nibbles(MM58274_MONTH) - 1);
/* MM58274 can store 00 to 99 years but M240 uses the YEAR1 register to count 8 years from leap year */
tm->tm_year = (1984 + regs[MM58274_YEAR1] - 1900);
}
/* This is called every second through the NVR/RTC hook. */
static void
mm58274_tick(nvr_t *nvr)
{
mm58x74_recalc();
mm58274_time_set(nvr->regs, &intclk);
}
static void
mm58274_start(nvr_t *nvr)
{
struct tm tm;
/* Initialize the internal and chip times. */
if (time_sync & TIME_SYNC_ENABLED) {
/* Use the internal clock's time. */
nvr_time_get(&tm);
mm58274_time_set(nvr->regs, &tm);
} else {
/* Set the internal clock from the chip time. */
mm58274_time_get(nvr->regs, &tm);
nvr_time_set(&tm);
}
mm58274_time_get(nvr->regs, &intclk);
}
/* Write to one of the chip registers. */
static void
mm58274_write(uint16_t addr, uint8_t val, void *priv)
{
nvr_t *nvr = (nvr_t *) priv;
addr &= 0x0f;
val &= 0x0f;
/* Update non-read-only changed values if not synchronizing time to host */
if (addr != MM58274_TENTHS)
if ((nvr->regs[addr] != val) && !(time_sync & TIME_SYNC_ENABLED))
nvr_dosave = 1;
if ((addr == MM58274_CONTROL) && (val & 0x04)) {
/* When timer starts, MM58274 sets tenths of second to 0 */
nvr->regs[MM58274_TENTHS] = 0;
}
/* Store the new value */
nvr->regs[addr] = val;
/* Update internal clock with MM58274 time */
mm58274_time_get(nvr->regs, &intclk);
}
/* Read from one of the chip registers. */
static uint8_t
mm58274_read(uint16_t addr, void *priv)
{
const nvr_t *nvr = (nvr_t *) priv;
addr &= 0x0f;
/* Grab and return the desired value */
return (nvr->regs[addr]);
}
/* Reset the MM58274 to a default state. */
static void
mm58274_reset(nvr_t *nvr)
{
/* Clear the NVRAM. */
memset(nvr->regs, 0xff, nvr->size);
/* Reset the RTC registers. */
memset(nvr->regs, 0x00, 16);
nvr->regs[MM58274_WEEKDAY] = 0x01;
nvr->regs[MM58274_DAY1] = 0x01;
nvr->regs[MM58274_MONTH1] = 0x01;
nvr->regs[MM58274_SETTINGS] = 0x01;
}
static void
mm58274_init(nvr_t *nvr, int size)
{
/* This is machine specific. */
nvr->size = size;
nvr->irq = -1;
/* Set up any local handlers here. */
nvr->reset = mm58274_reset;
nvr->start = mm58274_start;
nvr->tick = mm58274_tick;
/* Initialize the actual NVR. */
nvr_init(nvr);
io_sethandler(0x0070, 16,
mm58274_read, NULL, NULL, mm58274_write, NULL, NULL, nvr);
}
static void
m24_kbd_poll(void *priv)
{
m24_kbd_t *m24_kbd = (m24_kbd_t *) priv;
timer_advance_u64(&m24_kbd->send_delay_timer, 1000 * TIMER_USEC);
if (m24_kbd->wantirq) {
m24_kbd->wantirq = 0;
picint(2);
xt_olivetti_log("M24: take IRQ\n");
}
if (!(m24_kbd->status & STAT_OFULL) && key_queue_start != key_queue_end) {
xt_olivetti_log("Reading %02X from the key queue at %i\n",
m24_kbd->out, key_queue_start);
m24_kbd->out = key_queue[key_queue_start];
key_queue_start = (key_queue_start + 1) & 0xf;
m24_kbd->status |= STAT_OFULL;
m24_kbd->status &= ~STAT_IFULL;
m24_kbd->wantirq = 1;
}
}
static void
m24_kbd_adddata(uint16_t val)
{
key_queue[key_queue_end] = val;
key_queue_end = (key_queue_end + 1) & 0xf;
}
static void
m24_kbd_adddata_ex(uint16_t val)
{
kbd_adddata_process(val, m24_kbd_adddata);
}
/*
From the Olivetti M21/M24 Theory of Operation:
Port Function
---- --------
60h Keyboard 8041 Data Transfer Read/Write
61h Control Port A Read/Write
62h Control Port B Read
63h Not Used
64h Keyboard 8041 Command/Status
65h Communications Port Read
66h System Configuration Read
67h System Configuration Read
*/
static void
m24_kbd_write(uint16_t port, uint8_t val, void *priv)
{
m24_kbd_t *m24_kbd = (m24_kbd_t *) priv;
uint8_t ret;
xt_olivetti_log("M24: write %04X %02X\n", port, val);
switch (port) {
case 0x60:
m24_kbd->status &= ~STAT_CD;
if (m24_kbd->param != m24_kbd->param_total) {
m24_kbd->params[m24_kbd->param++] = val;
if (m24_kbd->param == m24_kbd->param_total) {
switch (m24_kbd->command) {
case 0x11:
m24_kbd->mouse_input_mode = 0;
m24_kbd->scan[0] = m24_kbd->params[0];
m24_kbd->scan[1] = m24_kbd->params[1];
m24_kbd->scan[2] = m24_kbd->params[2];
m24_kbd->scan[3] = m24_kbd->params[3];
m24_kbd->scan[4] = m24_kbd->params[4];
m24_kbd->scan[5] = m24_kbd->params[5];
m24_kbd->scan[6] = m24_kbd->params[6];
break;
case 0x12:
m24_kbd->mouse_input_mode = 1;
m24_kbd->scan[0] = m24_kbd->params[0];
m24_kbd->scan[1] = m24_kbd->params[1];
m24_kbd->scan[2] = m24_kbd->params[2];
break;
default:
xt_olivetti_log("M24: bad keyboard command complete %02X\n", m24_kbd->command);
}
}
} else {
m24_kbd->command = val;
switch (val) {
/* 01: FD, 05: ANY ---> Customer test reports no keyboard.
01: AA, 05: 01 ---> Customer test reports 102 Deluxe keyboard.
01: AA, 05: 02 ---> Customer test reports 83-key keyboard.
01: AA, 05: 10 ---> Customer test reports M240 keyboard.
01: AA, 05: 20 ---> Customer test reports 101/102/key keyboard.
01: AA, 05: 40 or anything else ---> Customer test reports 101/102/key keyboard.
AA is the correct return for command 01, as confirmed by the M24 Customer Test. */
case 0x01: /*Self-test*/
m24_kbd_adddata(0xaa);
break;
case 0x02: /*Olivetti M240: Read SWB*/
/* SWB on mainboard (off=1)
* bit 7 - use BIOS HD on mainboard (on) / on controller (off)
* bit 6 - use OCG/CGA display adapter (on) / other display adapter (off)
*/
ret = (hdc_current[0] == HDC_INTERNAL) ? 0x00 : 0x80;
ret |= video_is_cga() ? 0x40 : 0x00;
m24_kbd_adddata(ret);
break;
case 0x05: /*Read ID*/
ret = m24_kbd->id;
m24_kbd_adddata(ret);
break;
case 0x11:
m24_kbd->param = 0;
m24_kbd->param_total = 9;
break;
case 0x12:
m24_kbd->param = 0;
m24_kbd->param_total = 4;
break;
case 0x13: /*Sent by Olivetti M240 Customer Diagnostics*/
break;
default:
xt_olivetti_log("M24: bad keyboard command %02X\n", val);
}
}
break;
case 0x61:
ppi.pb = val;
speaker_update();
speaker_gated = val & 1;
speaker_enable = val & 2;
if (speaker_enable)
was_speaker_enable = 1;
pit_devs[0].set_gate(pit_devs[0].data, 2, val & 1);
break;
case 0x64:
m24_kbd->status |= STAT_CD;
if (val == 0x02)
m24_kbd_adddata(0x00);
break;
default:
break;
}
}
extern uint8_t random_generate(void);
static uint8_t
m24_kbd_read(uint16_t port, void *priv)
{
m24_kbd_t *m24_kbd = (m24_kbd_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x60:
ret = m24_kbd->out;
if (key_queue_start == key_queue_end) {
m24_kbd->status &= ~STAT_OFULL;
m24_kbd->wantirq = 0;
} else {
m24_kbd->out = key_queue[key_queue_start];
key_queue_start = (key_queue_start + 1) & 0xf;
m24_kbd->status |= STAT_OFULL;
m24_kbd->status &= ~STAT_IFULL;
m24_kbd->wantirq = 1;
}
break;
case 0x61:
/* MS-DOS 5.00 and higher's KEYB.COM freezes due to port 61h not having the
AT refresh toggle, because for some reson it thinks the M24 is an AT.
A German-language site confirms this also happens on real hardware.
The M240 is not affected. */
ret = ppi.pb;
break;
case 0x64:
ret = m24_kbd->status & 0x0f;
m24_kbd->status &= ~(STAT_RTIMEOUT | STAT_TTIMEOUT);
break;
default:
xt_olivetti_log("\nBad M24 keyboard read %04X\n", port);
}
return ret;
}
static void
m24_kbd_close(void *priv)
{
m24_kbd_t *kbd = (m24_kbd_t *) priv;
/* Stop the timer. */
timer_disable(&kbd->send_delay_timer);
/* Disable scanning. */
keyboard_scan = 0;
keyboard_send = NULL;
io_removehandler(0x0060, 2,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
io_removehandler(0x0064, 1,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
free(kbd);
}
static void
m24_kbd_reset(void *priv)
{
m24_kbd_t *m24_kbd = (m24_kbd_t *) priv;
/* Initialize the keyboard. */
m24_kbd->status = STAT_LOCK | STAT_CD;
m24_kbd->wantirq = 0;
keyboard_scan = 1;
m24_kbd->param = m24_kbd->param_total = 0;
m24_kbd->mouse_input_mode = 0;
m24_kbd->scan[0] = 0x1c;
m24_kbd->scan[1] = 0x53;
m24_kbd->scan[2] = 0x01;
m24_kbd->scan[3] = 0x4b;
m24_kbd->scan[4] = 0x4d;
m24_kbd->scan[5] = 0x48;
m24_kbd->scan[6] = 0x50;
}
static int
ms_poll(void *priv)
{
m24_kbd_t *m24_kbd = (m24_kbd_t *) priv;
int delta_x;
int delta_y;
int o_x;
int o_y;
int b = mouse_get_buttons_ex();
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
if ((b & 1) && !(m24_kbd->b & 1))
m24_kbd_adddata(m24_kbd->scan[0]);
if (!(b & 1) && (m24_kbd->b & 1))
m24_kbd_adddata(m24_kbd->scan[0] | 0x80);
m24_kbd->b = (m24_kbd->b & ~1) | (b & 1);
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
if ((b & 2) && !(m24_kbd->b & 2))
m24_kbd_adddata(m24_kbd->scan[2]);
if (!(b & 2) && (m24_kbd->b & 2))
m24_kbd_adddata(m24_kbd->scan[2] | 0x80);
m24_kbd->b = (m24_kbd->b & ~2) | (b & 2);
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
if ((b & 4) && !(m24_kbd->b & 4))
m24_kbd_adddata(m24_kbd->scan[1]);
if (!(b & 4) && (m24_kbd->b & 4))
m24_kbd_adddata(m24_kbd->scan[1] | 0x80);
m24_kbd->b = (m24_kbd->b & ~4) | (b & 4);
if (m24_kbd->mouse_input_mode) {
if (((key_queue_end - key_queue_start) & 0xf) > 12)
return 0xff;
if (!mouse_moved())
return 0xff;
mouse_subtract_coords(&delta_x, &delta_y, &o_x, &o_y, -127, 127, 1, 0);
if ((delta_x == -127) && o_x)
delta_x = 0x80 | ((-delta_x) & 0x7f);
if ((delta_y == -127) && o_y)
delta_y = 0x80 | ((-delta_y) & 0x7f);
m24_kbd_adddata(0xfe);
m24_kbd_adddata(delta_x);
m24_kbd_adddata(delta_y);
} else {
mouse_subtract_coords(&delta_x, &delta_y, &o_x, &o_y, -127, 127, 1, 0);
while (delta_x < -4) {
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
delta_x += 4;
m24_kbd_adddata(m24_kbd->scan[3]);
}
while (delta_x > 4) {
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
delta_x -= 4;
m24_kbd_adddata(m24_kbd->scan[4]);
}
while (delta_y < -4) {
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
delta_y += 4;
m24_kbd_adddata(m24_kbd->scan[5]);
}
while (delta_y > 4) {
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return 0xff;
delta_y -= 4;
m24_kbd_adddata(m24_kbd->scan[6]);
}
}
return 0;
}
/* Remapping as follows:
- Left Windows (E0 5B) -> NUMPAD 00 (54);
- Print Screen (E0 37) -> SCR PRT (55);
- Menu (E0 5D) -> HELP (56);
- NumPad Enter (E0 1C) -> NUMPAD ENTER (57).
- Left (E0 4B) -> LEFT (58);
- Down (E0 50) -> DOWN (59);
- Right (E0 4D) -> RIGHT (5A);
- Up (E0 48) -> UP (5B);
- Page Up (E0 49) -> CLEAR (5C);
- Page Down (E0 51) -> BREAK (5D);
- CE Key (56) -> CE KEY (5E);
WARNING: The Olivetti CE Key is undocumented, but can be inferred from the fact
its position is missing in the shown layout, it being used by the Italian
keyboard layout, the keyboard is called 103-key, but only 102 keys are
shown.
- NumPad / (E0 35) -> NUMPAD / (5F);
- F11 (57) -> F11 (60);
- F12 (58) -> F12 (61);
- Insert (E0 52) -> F13 (62);
- Home (E0 47) -> F14 (63);
- Delete (E0 53) -> F15 (64);
- End (E0 4F) -> F16 (65);
- Right Alt (Gr)(E0 38) -> F16 (66);
- Right Windows (E0 5C) -> F18 (67).
*/
const scancode scancode_olivetti_m24_deluxe[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 013 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 022 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 053 */
{ .mk = { 0 }, .brk = { 0 } }, /* 054 */
{ .mk = { 0 }, .brk = { 0 } }, /* 055 */
{ .mk = { 0x5e, 0 }, .brk = { 0xde, 0 } }, /* 056 */
{ .mk = { 0x60, 0 }, .brk = { 0xe0, 0 } }, /* 057 */
{ .mk = { 0x61, 0 }, .brk = { 0xe1, 0 } }, /* 058 */
{ .mk = { 0 }, .brk = { 0 } }, /* 059 */
{ .mk = { 0 }, .brk = { 0 } }, /* 05a */
{ .mk = { 0 }, .brk = { 0 } }, /* 05b */
{ .mk = { 0 }, .brk = { 0 } }, /* 05c */
{ .mk = { 0 }, .brk = { 0 } }, /* 05d */
{ .mk = { 0 }, .brk = { 0 } }, /* 05e */
{ .mk = { 0 }, .brk = { 0 } }, /* 05f */
{ .mk = { 0 }, .brk = { 0 } }, /* 060 */
{ .mk = { 0 }, .brk = { 0 } }, /* 061 */
{ .mk = { 0 }, .brk = { 0 } }, /* 062 */
{ .mk = { 0 }, .brk = { 0 } }, /* 063 */
{ .mk = { 0 }, .brk = { 0 } }, /* 064 */
{ .mk = { 0 }, .brk = { 0 } }, /* 065 */
{ .mk = { 0 }, .brk = { 0 } }, /* 066 */
{ .mk = { 0 }, .brk = { 0 } }, /* 067 */
{ .mk = { 0 }, .brk = { 0 } }, /* 068 */
{ .mk = { 0 }, .brk = { 0 } }, /* 069 */
{ .mk = { 0 }, .brk = { 0 } }, /* 06a */
{ .mk = { 0 }, .brk = { 0 } }, /* 06b */
{ .mk = { 0 }, .brk = { 0 } }, /* 06c */
{ .mk = { 0 }, .brk = { 0 } }, /* 06d */
{ .mk = { 0 }, .brk = { 0 } }, /* 06e */
{ .mk = { 0 }, .brk = { 0 } }, /* 06f */
{ .mk = { 0 }, .brk = { 0 } }, /* 070 */
{ .mk = { 0 }, .brk = { 0 } }, /* 071 */
{ .mk = { 0 }, .brk = { 0 } }, /* 072 */
{ .mk = { 0 }, .brk = { 0 } }, /* 073 */
{ .mk = { 0 }, .brk = { 0 } }, /* 074 */
{ .mk = { 0 }, .brk = { 0 } }, /* 075 */
{ .mk = { 0 }, .brk = { 0 } }, /* 076 */
{ .mk = { 0 }, .brk = { 0 } }, /* 077 */
{ .mk = { 0 }, .brk = { 0 } }, /* 078 */
{ .mk = { 0 }, .brk = { 0 } }, /* 079 */
{ .mk = { 0 }, .brk = { 0 } }, /* 07a */
{ .mk = { 0 }, .brk = { 0 } }, /* 07b */
{ .mk = { 0 }, .brk = { 0 } }, /* 07c */
{ .mk = { 0 }, .brk = { 0 } }, /* 07d */
{ .mk = { 0 }, .brk = { 0 } }, /* 07e */
{ .mk = { 0 }, .brk = { 0 } }, /* 07f */
{ .mk = { 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = { 0 }, .brk = { 0 } }, /* 100 */
{ .mk = { 0 }, .brk = { 0 } }, /* 101 */
{ .mk = { 0 }, .brk = { 0 } }, /* 102 */
{ .mk = { 0 }, .brk = { 0 } }, /* 103 */
{ .mk = { 0 }, .brk = { 0 } }, /* 104 */
{ .mk = { 0 }, .brk = { 0 } }, /* 105 */
{ .mk = { 0 }, .brk = { 0 } }, /* 106 */
{ .mk = { 0 }, .brk = { 0 } }, /* 107 */
{ .mk = { 0 }, .brk = { 0 } }, /* 108 */
{ .mk = { 0 }, .brk = { 0 } }, /* 109 */
{ .mk = { 0 }, .brk = { 0 } }, /* 10a */
{ .mk = { 0 }, .brk = { 0 } }, /* 10b */
{ .mk = { 0 }, .brk = { 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = { 0 }, .brk = { 0 } }, /* 10e */
{ .mk = { 0 }, .brk = { 0 } }, /* 10f */
{ .mk = { 0 }, .brk = { 0 } }, /* 110 */
{ .mk = { 0 }, .brk = { 0 } }, /* 111 */
{ .mk = { 0 }, .brk = { 0 } }, /* 112 */
{ .mk = { 0 }, .brk = { 0 } }, /* 113 */
{ .mk = { 0 }, .brk = { 0 } }, /* 114 */
{ .mk = { 0 }, .brk = { 0 } }, /* 115 */
{ .mk = { 0 }, .brk = { 0 } }, /* 116 */
{ .mk = { 0 }, .brk = { 0 } }, /* 117 */
{ .mk = { 0 }, .brk = { 0 } }, /* 118 */
{ .mk = { 0 }, .brk = { 0 } }, /* 119 */
{ .mk = { 0 }, .brk = { 0 } }, /* 11a */
{ .mk = { 0 }, .brk = { 0 } }, /* 11b */
{ .mk = { 0x57, 0 }, .brk = { 0xd7, 0 } }, /* 11c */
{ .mk = { 0 }, .brk = { 0 } }, /* 11d */
{ .mk = { 0 }, .brk = { 0 } }, /* 11e */
{ .mk = { 0 }, .brk = { 0 } }, /* 11f */
{ .mk = { 0 }, .brk = { 0 } }, /* 120 */
{ .mk = { 0 }, .brk = { 0 } }, /* 121 */
{ .mk = { 0 }, .brk = { 0 } }, /* 122 */
{ .mk = { 0 }, .brk = { 0 } }, /* 123 */
{ .mk = { 0 }, .brk = { 0 } }, /* 124 */
{ .mk = { 0 }, .brk = { 0 } }, /* 125 */
{ .mk = { 0 }, .brk = { 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = { 0 }, .brk = { 0 } }, /* 12c */
{ .mk = { 0 }, .brk = { 0 } }, /* 12d */
{ .mk = { 0 }, .brk = { 0 } }, /* 12e */
{ .mk = { 0 }, .brk = { 0 } }, /* 12f */
{ .mk = { 0 }, .brk = { 0 } }, /* 130 */
{ .mk = { 0 }, .brk = { 0 } }, /* 131 */
{ .mk = { 0 }, .brk = { 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = { 0 }, .brk = { 0 } }, /* 134 */
{ .mk = { 0x5f, 0 }, .brk = { 0xdf, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 137 */
{ .mk = { 0x66, 0 }, .brk = { 0xe6, 0 } }, /* 138 */
{ .mk = { 0x55, 0 }, .brk = { 0xd5, 0 } }, /* 139 */
{ .mk = { 0 }, .brk = { 0 } }, /* 13a */
{ .mk = { 0 }, .brk = { 0 } }, /* 13b */
{ .mk = { 0 }, .brk = { 0 } }, /* 13c */
{ .mk = { 0 }, .brk = { 0 } }, /* 13d */
{ .mk = { 0 }, .brk = { 0 } }, /* 13e */
{ .mk = { 0 }, .brk = { 0 } }, /* 13f */
{ .mk = { 0 }, .brk = { 0 } }, /* 140 */
{ .mk = { 0 }, .brk = { 0 } }, /* 141 */
{ .mk = { 0 }, .brk = { 0 } }, /* 142 */
{ .mk = { 0 }, .brk = { 0 } }, /* 143 */
{ .mk = { 0 }, .brk = { 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 146 */
{ .mk = { 0x63, 0 }, .brk = { 0xe3, 0 } }, /* 147 */
{ .mk = { 0x5b, 0 }, .brk = { 0xdb, 0 } }, /* 148 */
{ .mk = { 0x5c, 0 }, .brk = { 0xdc, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = { 0x58, 0 }, .brk = { 0xd8, 0 } }, /* 14b */
{ .mk = { 0 }, .brk = { 0 } }, /* 14c */
{ .mk = { 0x5a, 0 }, .brk = { 0xda, 0 } }, /* 14d */
{ .mk = { 0 }, .brk = { 0 } }, /* 14e */
{ .mk = { 0x65, 0 }, .brk = { 0xe5, 0 } }, /* 14f */
{ .mk = { 0x59, 0 }, .brk = { 0xd9, 0 } }, /* 150 */
{ .mk = { 0x5d, 0 }, .brk = { 0xdd, 0 } }, /* 151 */
{ .mk = { 0x62, 0 }, .brk = { 0xe2, 0 } }, /* 152 */
{ .mk = { 0x64, 0 }, .brk = { 0xe4, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = { 0 }, .brk = { 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = { 0 }, .brk = { 0 } }, /* 157 */
{ .mk = { 0 }, .brk = { 0 } }, /* 158 */
{ .mk = { 0 }, .brk = { 0 } }, /* 159 */
{ .mk = { 0 }, .brk = { 0 } }, /* 15a */
{ .mk = { 0x54, 0 }, .brk = { 0xd4, 0 } }, /* 15b */
{ .mk = { 0x67, 0 }, .brk = { 0xe7, 0 } }, /* 15c */
{ .mk = { 0x56, 0 }, .brk = { 0xd6, 0 } }, /* 15d */
{ .mk = { 0 }, .brk = { 0 } }, /* 15e */
{ .mk = { 0 }, .brk = { 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = { 0 }, .brk = { 0 } }, /* 161 */
{ .mk = { 0 }, .brk = { 0 } }, /* 162 */
{ .mk = { 0 }, .brk = { 0 } }, /* 163 */
{ .mk = { 0 }, .brk = { 0 } }, /* 164 */
{ .mk = { 0 }, .brk = { 0 } }, /* 165 */
{ .mk = { 0 }, .brk = { 0 } }, /* 166 */
{ .mk = { 0 }, .brk = { 0 } }, /* 167 */
{ .mk = { 0 }, .brk = { 0 } }, /* 168 */
{ .mk = { 0 }, .brk = { 0 } }, /* 169 */
{ .mk = { 0 }, .brk = { 0 } }, /* 16a */
{ .mk = { 0 }, .brk = { 0 } }, /* 16b */
{ .mk = { 0 }, .brk = { 0 } }, /* 16c */
{ .mk = { 0 }, .brk = { 0 } }, /* 16d */
{ .mk = { 0 }, .brk = { 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = { 0 }, .brk = { 0 } }, /* 170 */
{ .mk = { 0 }, .brk = { 0 } }, /* 171 */
{ .mk = { 0 }, .brk = { 0 } }, /* 172 */
{ .mk = { 0 }, .brk = { 0 } }, /* 173 */
{ .mk = { 0 }, .brk = { 0 } }, /* 174 */
{ .mk = { 0 }, .brk = { 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = { 0 }, .brk = { 0 } }, /* 177 */
{ .mk = { 0 }, .brk = { 0 } }, /* 178 */
{ .mk = { 0 }, .brk = { 0 } }, /* 179 */
{ .mk = { 0 }, .brk = { 0 } }, /* 17a */
{ .mk = { 0 }, .brk = { 0 } }, /* 17b */
{ .mk = { 0 }, .brk = { 0 } }, /* 17c */
{ .mk = { 0 }, .brk = { 0 } }, /* 17d */
{ .mk = { 0 }, .brk = { 0 } }, /* 17e */
{ .mk = { 0 }, .brk = { 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = { 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
/* Remapping as follows:
- Left Windows (E0 5B) -> 54;
- Right Windows (E0 5C) -> 56;
- Menu (E0 5D) -> 5C.
*/
const scancode scancode_olivetti_m240[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 012 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 023 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 053 */
{ .mk = { 0 }, .brk = { 0 } }, /* 054 */
{ .mk = { 0 }, .brk = { 0 } }, /* 055 */
{ .mk = { 0 }, .brk = { 0 } }, /* 056 */
{ .mk = { 0 }, .brk = { 0 } }, /* 057 */
{ .mk = { 0 }, .brk = { 0 } }, /* 058 */
{ .mk = { 0 }, .brk = { 0 } }, /* 059 */
{ .mk = { 0 }, .brk = { 0 } }, /* 05a */
{ .mk = { 0 }, .brk = { 0 } }, /* 05b */
{ .mk = { 0 }, .brk = { 0 } }, /* 05c */
{ .mk = { 0 }, .brk = { 0 } }, /* 05d */
{ .mk = { 0 }, .brk = { 0 } }, /* 05e */
{ .mk = { 0 }, .brk = { 0 } }, /* 05f */
{ .mk = { 0 }, .brk = { 0 } }, /* 060 */
{ .mk = { 0 }, .brk = { 0 } }, /* 061 */
{ .mk = { 0 }, .brk = { 0 } }, /* 062 */
{ .mk = { 0 }, .brk = { 0 } }, /* 063 */
{ .mk = { 0 }, .brk = { 0 } }, /* 064 */
{ .mk = { 0 }, .brk = { 0 } }, /* 065 */
{ .mk = { 0 }, .brk = { 0 } }, /* 066 */
{ .mk = { 0 }, .brk = { 0 } }, /* 067 */
{ .mk = { 0 }, .brk = { 0 } }, /* 068 */
{ .mk = { 0 }, .brk = { 0 } }, /* 069 */
{ .mk = { 0 }, .brk = { 0 } }, /* 06a */
{ .mk = { 0 }, .brk = { 0 } }, /* 06b */
{ .mk = { 0 }, .brk = { 0 } }, /* 06c */
{ .mk = { 0 }, .brk = { 0 } }, /* 06d */
{ .mk = { 0 }, .brk = { 0 } }, /* 06e */
{ .mk = { 0 }, .brk = { 0 } }, /* 06f */
{ .mk = { 0 }, .brk = { 0 } }, /* 070 */
{ .mk = { 0 }, .brk = { 0 } }, /* 071 */
{ .mk = { 0 }, .brk = { 0 } }, /* 072 */
{ .mk = { 0 }, .brk = { 0 } }, /* 073 */
{ .mk = { 0 }, .brk = { 0 } }, /* 074 */
{ .mk = { 0 }, .brk = { 0 } }, /* 075 */
{ .mk = { 0 }, .brk = { 0 } }, /* 076 */
{ .mk = { 0 }, .brk = { 0 } }, /* 077 */
{ .mk = { 0 }, .brk = { 0 } }, /* 078 */
{ .mk = { 0 }, .brk = { 0 } }, /* 079 */
{ .mk = { 0 }, .brk = { 0 } }, /* 07a */
{ .mk = { 0 }, .brk = { 0 } }, /* 07b */
{ .mk = { 0 }, .brk = { 0 } }, /* 07c */
{ .mk = { 0 }, .brk = { 0 } }, /* 07d */
{ .mk = { 0 }, .brk = { 0 } }, /* 07e */
{ .mk = { 0 }, .brk = { 0 } }, /* 07f */
{ .mk = { 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = { 0 }, .brk = { 0 } }, /* 100 */
{ .mk = { 0 }, .brk = { 0 } }, /* 101 */
{ .mk = { 0 }, .brk = { 0 } }, /* 102 */
{ .mk = { 0 }, .brk = { 0 } }, /* 103 */
{ .mk = { 0 }, .brk = { 0 } }, /* 104 */
{ .mk = { 0 }, .brk = { 0 } }, /* 105 */
{ .mk = { 0 }, .brk = { 0 } }, /* 106 */
{ .mk = { 0 }, .brk = { 0 } }, /* 107 */
{ .mk = { 0 }, .brk = { 0 } }, /* 108 */
{ .mk = { 0 }, .brk = { 0 } }, /* 109 */
{ .mk = { 0 }, .brk = { 0 } }, /* 10a */
{ .mk = { 0 }, .brk = { 0 } }, /* 10b */
{ .mk = { 0 }, .brk = { 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = { 0 }, .brk = { 0 } }, /* 10e */
{ .mk = { 0 }, .brk = { 0 } }, /* 10f */
{ .mk = { 0 }, .brk = { 0 } }, /* 110 */
{ .mk = { 0 }, .brk = { 0 } }, /* 111 */
{ .mk = { 0 }, .brk = { 0 } }, /* 112 */
{ .mk = { 0 }, .brk = { 0 } }, /* 113 */
{ .mk = { 0 }, .brk = { 0 } }, /* 114 */
{ .mk = { 0 }, .brk = { 0 } }, /* 115 */
{ .mk = { 0 }, .brk = { 0 } }, /* 116 */
{ .mk = { 0 }, .brk = { 0 } }, /* 117 */
{ .mk = { 0 }, .brk = { 0 } }, /* 118 */
{ .mk = { 0 }, .brk = { 0 } }, /* 119 */
{ .mk = { 0 }, .brk = { 0 } }, /* 11a */
{ .mk = { 0 }, .brk = { 0 } }, /* 11b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 11c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 11d */
{ .mk = { 0 }, .brk = { 0 } }, /* 11e */
{ .mk = { 0 }, .brk = { 0 } }, /* 11f */
{ .mk = { 0 }, .brk = { 0 } }, /* 120 */
{ .mk = { 0 }, .brk = { 0 } }, /* 121 */
{ .mk = { 0 }, .brk = { 0 } }, /* 122 */
{ .mk = { 0 }, .brk = { 0 } }, /* 123 */
{ .mk = { 0 }, .brk = { 0 } }, /* 124 */
{ .mk = { 0 }, .brk = { 0 } }, /* 125 */
{ .mk = { 0 }, .brk = { 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = { 0 }, .brk = { 0 } }, /* 12c */
{ .mk = { 0 }, .brk = { 0 } }, /* 12d */
{ .mk = { 0 }, .brk = { 0 } }, /* 12e */
{ .mk = { 0 }, .brk = { 0 } }, /* 12f */
{ .mk = { 0 }, .brk = { 0 } }, /* 130 */
{ .mk = { 0 }, .brk = { 0 } }, /* 131 */
{ .mk = { 0 }, .brk = { 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = { 0 }, .brk = { 0 } }, /* 134 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 137 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = { 0 }, .brk = { 0 } }, /* 13a */
{ .mk = { 0 }, .brk = { 0 } }, /* 13b */
{ .mk = { 0 }, .brk = { 0 } }, /* 13c */
{ .mk = { 0 }, .brk = { 0 } }, /* 13d */
{ .mk = { 0 }, .brk = { 0 } }, /* 13e */
{ .mk = { 0 }, .brk = { 0 } }, /* 13f */
{ .mk = { 0 }, .brk = { 0 } }, /* 140 */
{ .mk = { 0 }, .brk = { 0 } }, /* 141 */
{ .mk = { 0 }, .brk = { 0 } }, /* 142 */
{ .mk = { 0 }, .brk = { 0 } }, /* 143 */
{ .mk = { 0 }, .brk = { 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 146 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 147 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 148 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 14b */
{ .mk = { 0 }, .brk = { 0 } }, /* 14c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 14d */
{ .mk = { 0 }, .brk = { 0 } }, /* 14e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 14f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 150 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 151 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 152 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = { 0 }, .brk = { 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = { 0 }, .brk = { 0 } }, /* 157 */
{ .mk = { 0 }, .brk = { 0 } }, /* 158 */
{ .mk = { 0 }, .brk = { 0 } }, /* 159 */
{ .mk = { 0 }, .brk = { 0 } }, /* 15a */
{ .mk = { 0 }, .brk = { 0 } }, /* 15b */
{ .mk = { 0 }, .brk = { 0 } }, /* 15c */
{ .mk = { 0x54, 0 }, .brk = { 0xd4, 0 } }, /* 15d */
{ .mk = { 0x56, 0 }, .brk = { 0xd6, 0 } }, /* 15e */
{ .mk = { 0x5c, 0 }, .brk = { 0xdc, 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = { 0 }, .brk = { 0 } }, /* 161 */
{ .mk = { 0 }, .brk = { 0 } }, /* 162 */
{ .mk = { 0 }, .brk = { 0 } }, /* 163 */
{ .mk = { 0 }, .brk = { 0 } }, /* 164 */
{ .mk = { 0 }, .brk = { 0 } }, /* 165 */
{ .mk = { 0 }, .brk = { 0 } }, /* 166 */
{ .mk = { 0 }, .brk = { 0 } }, /* 167 */
{ .mk = { 0 }, .brk = { 0 } }, /* 168 */
{ .mk = { 0 }, .brk = { 0 } }, /* 169 */
{ .mk = { 0 }, .brk = { 0 } }, /* 16a */
{ .mk = { 0 }, .brk = { 0 } }, /* 16b */
{ .mk = { 0 }, .brk = { 0 } }, /* 16c */
{ .mk = { 0 }, .brk = { 0 } }, /* 16d */
{ .mk = { 0 }, .brk = { 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = { 0 }, .brk = { 0 } }, /* 170 */
{ .mk = { 0 }, .brk = { 0 } }, /* 171 */
{ .mk = { 0 }, .brk = { 0 } }, /* 172 */
{ .mk = { 0 }, .brk = { 0 } }, /* 173 */
{ .mk = { 0 }, .brk = { 0 } }, /* 174 */
{ .mk = { 0 }, .brk = { 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = { 0 }, .brk = { 0 } }, /* 177 */
{ .mk = { 0 }, .brk = { 0 } }, /* 178 */
{ .mk = { 0 }, .brk = { 0 } }, /* 179 */
{ .mk = { 0 }, .brk = { 0 } }, /* 17a */
{ .mk = { 0 }, .brk = { 0 } }, /* 17b */
{ .mk = { 0 }, .brk = { 0 } }, /* 17c */
{ .mk = { 0 }, .brk = { 0 } }, /* 17d */
{ .mk = { 0 }, .brk = { 0 } }, /* 17e */
{ .mk = { 0 }, .brk = { 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = { 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
static void
m24_kbd_init(m24_kbd_t *kbd)
{
/* Initialize the keyboard. */
io_sethandler(0x0060, 2,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
io_sethandler(0x0064, 1,
m24_kbd_read, NULL, NULL, m24_kbd_write, NULL, NULL, kbd);
keyboard_send = m24_kbd_adddata_ex;
m24_kbd_reset(kbd);
timer_add(&kbd->send_delay_timer, m24_kbd_poll, kbd, 1);
if (mouse_type == MOUSE_TYPE_INTERNAL) {
/* Tell mouse driver about our internal mouse. */
mouse_reset();
mouse_set_buttons(2);
mouse_set_poll(ms_poll, kbd);
}
keyboard_set_table((kbd->id == 0x01) ? scancode_olivetti_m24_deluxe : scancode_olivetti_m240);
keyboard_set_is_amstrad(0);
}
static void
m19_vid_out(uint16_t addr, uint8_t val, void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
int oldmode = vid->mode;
/* activating plantronics mode */
if (addr == 0x3dd) {
/* already in graphics mode */
if ((val & 0x30) && (vid->ogc.cga.cgamode & 0x2))
vid->mode = PLANTRONICS_MODE;
else
vid->mode = OLIVETTI_OGC_MODE;
/* setting graphics mode */
} else if (addr == 0x3d8) {
if ((val & 0x2) && (vid->colorplus.control & 0x30))
vid->mode = PLANTRONICS_MODE;
else
vid->mode = OLIVETTI_OGC_MODE;
}
/* video mode changed */
if (oldmode != vid->mode) {
/* activate Plantronics emulation */
if (vid->mode == PLANTRONICS_MODE) {
timer_disable(&vid->ogc.cga.timer);
timer_set_delay_u64(&vid->colorplus.cga.timer, 0);
/* return to OGC mode */
} else {
timer_disable(&vid->colorplus.cga.timer);
timer_set_delay_u64(&vid->ogc.cga.timer, 0);
}
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
}
colorplus_out(addr, val, &vid->colorplus);
ogc_out(addr, val, &vid->ogc);
}
static uint8_t
m19_vid_in(uint16_t addr, void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
if (vid->mode == PLANTRONICS_MODE)
return colorplus_in(addr, &vid->colorplus);
else
return ogc_in(addr, &vid->ogc);
}
static uint8_t
m19_vid_read(uint32_t addr, void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
vid->colorplus.cga.mapping = vid->ogc.cga.mapping;
if (vid->mode == PLANTRONICS_MODE)
return colorplus_read(addr, &vid->colorplus);
else
return ogc_read(addr, &vid->ogc);
}
static void
m19_vid_write(uint32_t addr, uint8_t val, void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
colorplus_write(addr, val, &vid->colorplus);
ogc_write(addr, val, &vid->ogc);
}
static void
m19_vid_close(void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
free(vid->ogc.cga.vram);
free(vid->colorplus.cga.vram);
free(vid);
}
static void
m19_vid_speed_changed(void *priv)
{
m19_vid_t *vid = (m19_vid_t *) priv;
colorplus_recalctimings(&vid->colorplus);
ogc_recalctimings(&vid->ogc);
}
static void
m19_vid_init(m19_vid_t *vid)
{
device_context(&m19_vid_device);
#if 0
int display_type;
#endif
vid->mode = OLIVETTI_OGC_MODE;
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_m19_vid);
#if 0
display_type = device_get_config_int("display_type");
#endif
/* OGC emulation part begin */
loadfont("roms/machines/m19/MBM2764-30 8514 107 AB PCF3.BIN", 7);
/* composite is not working yet */
vid->ogc.cga.composite = 0; // (display_type != CGA_RGB);
vid->ogc.cga.revision = device_get_config_int("composite_type");
vid->ogc.cga.snow_enabled = device_get_config_int("snow_enabled");
vid->ogc.cga.vram = malloc(0x8000);
#if 0
cga_comp_init(vid->ogc.cga.revision);
#endif
vid->ogc.cga.rgb_type = device_get_config_int("rgb_type");
cga_palette = (vid->ogc.cga.rgb_type << 1);
cgapal_rebuild();
ogc_mdaattr_rebuild();
/* color display */
if (device_get_config_int("rgb_type") == 0 || device_get_config_int("rgb_type") == 4)
vid->ogc.mono_display = 0;
else
vid->ogc.mono_display = 1;
/* OGC emulation part end */
/* Plantronics emulation part begin*/
/* composite is not working yet */
vid->colorplus.cga.composite = 0; //(display_type != CGA_RGB);
#if 0
vid->colorplus.cga.snow_enabled = device_get_config_int("snow_enabled");
#endif
vid->colorplus.cga.vram = malloc(0x8000);
#if 0
vid->colorplus.cga.cgamode = 0x1;
#endif
/* Plantronics emulation part end*/
timer_add(&vid->ogc.cga.timer, ogc_poll, &vid->ogc, 1);
timer_add(&vid->colorplus.cga.timer, colorplus_poll, &vid->colorplus, 1);
timer_disable(&vid->colorplus.cga.timer);
mem_mapping_add(&vid->ogc.cga.mapping, 0xb8000, 0x08000, m19_vid_read, NULL, NULL, m19_vid_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, vid);
io_sethandler(0x03d0, 0x0010, m19_vid_in, NULL, NULL, m19_vid_out, NULL, NULL, vid);
vid->mode = OLIVETTI_OGC_MODE;
device_context_restore();
}
const device_t m24_kbd_device = {
.name = "Olivetti M24 keyboard and mouse",
.internal_name = "m24_kbd",
.flags = 0,
.local = 0,
.init = NULL,
.close = m24_kbd_close,
.reset = m24_kbd_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_config_t m19_vid_config[] = {
// clang-format off
{
/* Olivetti / ATT compatible displays */
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = CGA_RGB,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Color", .value = 0 },
{ .description = "Green Monochrome", .value = 1 },
{ .description = "Amber Monochrome", .value = 2 },
{ .description = "Gray Monochrome", .value = 3 },
{ .description = "" }
}
},
{
.name = "snow_enabled",
.description = "Snow emulation",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1,
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t m19_vid_device = {
.name = "Olivetti M19 graphics card",
.internal_name = "m19_vid",
.flags = 0,
.local = 0,
.init = NULL,
.close = m19_vid_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = m19_vid_speed_changed,
.force_redraw = NULL,
.config = m19_vid_config
};
static uint8_t
m24_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0x00;
int fdd_count = 0;
switch (port) {
case 0x62:
/* Control Port B Read */
ret = 0xff;
break;
case 0x65:
/* Communications Port Read */
ret = 0xff;
break;
/*
* port 66:
* DIPSW-0 on mainboard (off=present=1)
* bit 7 - 2764 (off) / 2732 (on) ROM (BIOS < 1.36)
* bit 7 - Use (off) / do not use (on) memory bank 1 (BIOS >= 1.36)
* bit 6 - n/a
* bit 5 - 8530 (off) / 8250 (on) SCC
* bit 4 - 8087 present
* bits 3-0 - installed memory
*/
case 0x66:
/* Switch 5 - 8087 present */
if (hasfpu)
ret |= 0x10;
/*
* Switches 1, 2, 3, 4 - installed memory
* Switch 8 - Use memory bank 1
*/
switch (mem_size) {
case 128:
ret |= 0x1;
break;
case 256:
ret |= 0x2;
break;
case 384:
ret |= 0x1 | 0x2 | 0x80;
break;
case 512:
ret |= 0x8;
break;
case 640:
ret |= 0x1 | 0x8 | 0x80;
break;
default:
break;
}
break;
/*
* port 67:
* DIPSW-1 on mainboard (off=present=1)
* bits 7-6 - number of drives
* bits 5-4 - display adapter
* bit 3 - video scroll CPU (on) / slow scroll (off)
* bit 2 - BIOS HD on mainboard (on) / on controller (off)
* bit 1 - FDD fast (off) / slow (on) start drive
* bit 0 - 96 TPI (720 KB 3.5") (off) / 48 TPI (360 KB 5.25") FDD drive
*
* Display adapter:
* off off 80x25 mono
* off on 40x25 color
* on off 80x25 color
* on on EGA/VGA (works only for BIOS ROM 1.43)
*/
case 0x67:
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
}
/* Switches 7, 8 - floppy drives. */
if (!fdd_count)
ret |= 0x00;
else
ret |= ((fdd_count - 1) << 6);
/* Switches 5, 6 - monitor type */
if (video_is_mda())
ret |= 0x30;
else if (video_is_cga())
ret |= 0x20; /* 0x10 would be 40x25 */
else
ret |= 0x0;
/* Switch 4 - The M21/M24 Theory of Operation says
"Reserved for HDU", same as for Switch 3 */
/* Switch 3 - Disable internal BIOS HD */
if (hdc_current[0] != HDC_INTERNAL)
ret |= 0x4;
/* Switch 2 - Set fast startup */
ret |= 0x2;
/* 1 = 720 kB (3.5"), 0 = 360 kB (5.25") */
ret |= (fdd_doublestep_40(0) || fdd_doublestep_40(1)) ? 0x1 : 0x0;
break;
default:
break;
}
return ret;
}
static uint8_t
m240_read(uint16_t port, UNUSED(void *priv))
{
uint8_t ret = 0x00;
int fdd_count = 0;
switch (port) {
case 0x62:
/* SWA on Olivetti M240 mainboard (off=1) */
ret = 0x00;
if (ppi.pb & 0x8) {
/* Switches 4, 5 - floppy drives (number) */
for (uint8_t i = 0; i < FDD_NUM; i++) {
if (fdd_get_flags(i))
fdd_count++;
}
if (!fdd_count)
ret |= 0x00;
else
ret |= ((fdd_count - 1) << 2);
/* Switches 6, 7 - monitor type */
if (video_is_mda())
ret |= 0x3;
else if (video_is_cga())
ret |= 0x2; /* 0x10 would be 40x25 */
else
ret |= 0x0;
} else {
/* bit 2 always on */
ret |= 0x4;
/* Switch 8 - 8087 FPU. */
if (hasfpu)
ret |= 0x02;
}
break;
case 0x63:
/* Olivetti M240 SWB:
- Bit 7: 1 = MFDD (= high-density) unit present (Customer Test will then always think Drive 2 is absent),
0 = MFD unit absent;
- Bit 6: 1 = Second drive is 3.5" (for low density drive, this means 80-track),
0 = Second drive is 5.25" (for low density drive, this means 40-track).
- Bit 5: 1 = First drive is 3.5" (for low density drive, this means 80-track),
0 = First drive is 5.25" (for low density drive, this means 40-track).
*/
ret = (fdd_is_hd(0) || fdd_is_hd(1)) ? 0x80 : 0x00;
ret |= fdd_doublestep_40(1) ? 0x40 : 0x00;
ret |= fdd_doublestep_40(0) ? 0x20 : 0x00;
break;
default:
break;
}
return ret;
}
/*
* Uses M21/M24/M240 keyboard controller and M24 102/103-key Deluxe keyboard.
*/
int
machine_xt_m24_init(const machine_t *model)
{
int ret;
m24_kbd_t *m24_kbd;
nvr_t *nvr;
ret = bios_load_interleaved("roms/machines/m24/olivetti_m24_bios_version_1.44_low_even.bin",
"roms/machines/m24/olivetti_m24_bios_version_1.44_high_odd.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
m24_kbd = (m24_kbd_t *) malloc(sizeof(m24_kbd_t));
memset(m24_kbd, 0x00, sizeof(m24_kbd_t));
machine_common_init(model);
/* On-board FDC can be disabled only on M24SP */
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
/* Address 66-67 = mainboard dip-switch settings */
io_sethandler(0x0065, 3, m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
standalone_gameport_type = &gameport_device;
nmi_init();
/* Allocate an NVR for this machine. */
nvr = (nvr_t *) malloc(sizeof(nvr_t));
if (nvr == NULL)
return 0;
memset(nvr, 0x00, sizeof(nvr_t));
mm58174_init(nvr, model->nvrmask + 1);
video_reset(gfxcard[0]);
if (gfxcard[0] == VID_INTERNAL)
device_add(&ogc_m24_device);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
io_sethandler(0x0062, 1, m24_read, NULL, NULL, NULL, NULL, NULL, NULL);
m24_kbd->id = 0x01;
m24_kbd_init(m24_kbd);
device_add_ex(&m24_kbd_device, m24_kbd);
if (hdc_current[0] == HDC_INTERNAL)
device_add(&st506_xt_wd1002a_wx1_nobios_device);
return ret;
}
/*
* Uses M21/M24/M240 keyboard controller and M240 keyboard.
*/
int
machine_xt_m240_init(const machine_t *model)
{
int ret;
m24_kbd_t *m24_kbd;
nvr_t *nvr;
ret = bios_load_interleaved("roms/machines/m240/olivetti_m240_pchj_2.11_low.bin",
"roms/machines/m240/olivetti_m240_pchk_2.11_high.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
m24_kbd = (m24_kbd_t *) malloc(sizeof(m24_kbd_t));
memset(m24_kbd, 0x00, sizeof(m24_kbd_t));
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
/* Address 66-67 = mainboard dip-switch settings */
io_sethandler(0x0062, 2, m240_read, NULL, NULL, NULL, NULL, NULL, NULL);
/*
* port 60: should return jumper settings only under unknown conditions
* SWB on mainboard (off=1)
* bit 7 - use BIOS HD on mainboard (on) / on controller (off)
* bit 6 - use OCG/CGA display adapter (on) / other display adapter (off)
*/
m24_kbd->id = 0x10;
m24_kbd_init(m24_kbd);
device_add_ex(&m24_kbd_device, m24_kbd);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device); /* io.c logs clearly show it using port 3F7 */
if (joystick_type)
device_add(&gameport_device);
nmi_init();
/* Allocate an NVR for this machine. */
nvr = (nvr_t *) malloc(sizeof(nvr_t));
if (nvr == NULL)
return 0;
memset(nvr, 0x00, sizeof(nvr_t));
mm58274_init(nvr, model->nvrmask + 1);
if (hdc_current[0] == HDC_INTERNAL)
device_add(&st506_xt_wd1002a_wx1_nobios_device);
return ret;
}
/*
* Current bugs:
* - 640x400x2 graphics mode not supported (bit 0 of register 0x3de cannot be set)
* - optional mouse emulation missing
* - setting CPU speed at 4.77MHz sometimes throws a timer error. If the machine is hard-resetted, the error disappears.
*/
int
machine_xt_m19_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m19/BIOS.BIN",
0x000fc000, 16384, 0);
ret &= rom_present("roms/machines/m19/MBM2764-30 8514 107 AB PCF3.BIN");
if (bios_only || !ret)
return ret;
m19_vid_t *vid;
/* Do not move memory allocation elsewhere. */
vid = (m19_vid_t *) malloc(sizeof(m19_vid_t));
memset(vid, 0x00, sizeof(m19_vid_t));
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
/* On-board FDC cannot be disabled */
device_add(&fdc_xt_device);
nmi_init();
video_reset(gfxcard[0]);
m19_vid_init(vid);
device_add_ex(&m19_vid_device, vid);
device_add(&keyboard_xt_olivetti_device);
pit_set_clock((uint32_t) 14318184.0);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_olivetti.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 40,572 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of various Compaq PC's.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, <mariogplayer@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/keyboard.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/machine.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
static video_timings_t timing_compaq_plasma = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
enum {
COMPAQ_PORTABLEII = 0,
COMPAQ_PORTABLEIII,
COMPAQ_PORTABLEIII386,
COMPAQ_DESKPRO386,
COMPAQ_DESKPRO386_05_1988
};
#define CGA_RGB 0
#define CGA_COMPOSITE 1
/*Very rough estimate*/
#define VID_CLOCK (double) (651 * 416 * 60)
static uint8_t cga_crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
/* Mapping of attributes to colours */
static uint32_t amber;
static uint32_t black;
static uint32_t blinkcols[256][2];
static uint32_t normcols[256][2];
/* Video options set by the motherboard; they will be picked up by the card
* on the next poll.
*
* Bit 3: Disable built-in video (for add-on card)
* Bit 2: Thin font
* Bits 0,1: Font set (not currently implemented)
*/
static int8_t cpq_st_display_internal = -1;
static uint8_t mdaattr[256][2][2];
static void
compaq_plasma_display_set(uint8_t internal)
{
cpq_st_display_internal = internal;
}
static uint8_t
compaq_plasma_display_get(void)
{
return cpq_st_display_internal;
}
typedef struct compaq_plasma_t {
cga_t cga;
uint8_t port_23c6;
uint8_t internal_monitor;
uint8_t attrmap;
} compaq_plasma_t;
static int compaq_machine_type = 0;
/* Compaq Deskpro 386 remaps RAM from 0xA0000-0xFFFFF to 0xFA0000-0xFFFFFF */
static mem_mapping_t ram_mapping;
static void compaq_plasma_recalcattrs(compaq_plasma_t *self);
static void
compaq_plasma_recalctimings(compaq_plasma_t *self)
{
double _dispontime;
double _dispofftime;
double disptime;
if (!self->internal_monitor && !(self->port_23c6 & 1)) {
cga_recalctimings(&self->cga);
return;
}
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
self->cga.dispontime = (uint64_t) (_dispontime * (cpuclock / VID_CLOCK) * (double) (1ULL << 32));
self->cga.dispofftime = (uint64_t) (_dispofftime * (cpuclock / VID_CLOCK) * (double) (1ULL << 32));
}
static void
compaq_plasma_waitstates(UNUSED(void *priv))
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
sub_cycles(ws);
}
static void
compaq_plasma_write(uint32_t addr, uint8_t val, void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
self->cga.vram[addr & 0x7fff] = val;
compaq_plasma_waitstates(&self->cga);
}
static uint8_t
compaq_plasma_read(uint32_t addr, void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
uint8_t ret;
compaq_plasma_waitstates(&self->cga);
ret = (self->cga.vram[addr & 0x7fff]);
return ret;
}
static void
compaq_plasma_out(uint16_t addr, uint8_t val, void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
uint8_t old;
switch (addr) {
/* Emulated CRTC, register select */
case 0x3d4:
cga_out(addr, val, &self->cga);
break;
/* Emulated CRTC, value */
case 0x3d5:
old = self->cga.crtc[self->cga.crtcreg];
self->cga.crtc[self->cga.crtcreg] = val & cga_crtcmask[self->cga.crtcreg];
/* Register 0x12 controls the attribute mappings for the
* plasma screen. */
if (self->cga.crtcreg == 0x12) {
self->attrmap = val;
compaq_plasma_recalcattrs(self);
break;
}
if (old != val) {
if (self->cga.crtcreg < 0xe || self->cga.crtcreg > 0x10) {
self->cga.fullchange = changeframecount;
compaq_plasma_recalctimings(self);
}
}
break;
case 0x3d8:
case 0x3d9:
cga_out(addr, val, &self->cga);
break;
case 0x13c6:
compaq_plasma_display_set((val & 8) ? 1 : 0);
break;
case 0x23c6:
self->port_23c6 = val;
if (val & 8) /* Disable internal CGA */
mem_mapping_disable(&self->cga.mapping);
else
mem_mapping_enable(&self->cga.mapping);
break;
default:
break;
}
}
static uint8_t
compaq_plasma_in(uint16_t addr, void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x3d4:
case 0x3da:
ret = cga_in(addr, &self->cga);
break;
case 0x3d5:
if (self->cga.crtcreg == 0x12) {
ret = self->attrmap & 0x0f;
if (self->internal_monitor)
ret |= 0x30; /* Plasma / CRT */
} else
ret = cga_in(addr, &self->cga);
break;
case 0x13c6:
ret = compaq_plasma_display_get() ? 8 : 0;
ret |= 4;
break;
case 0x1bc6:
ret = 0;
if (compaq_plasma_display_get()) {
if ((self->cga.cgamode & 0x12) == 0x12) {
if (self->port_23c6 & 8)
ret |= 0x40;
else
ret |= 0x20;
}
}
break;
case 0x23c6:
ret = 0;
break;
default:
break;
}
return ret;
}
static void
compaq_plasma_poll(void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
uint8_t chr;
uint8_t attr;
uint8_t sc;
uint16_t ma = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x7fff;
uint16_t ca = (self->cga.crtc[15] | (self->cga.crtc[14] << 8)) & 0x7fff;
uint16_t addr;
int drawcursor;
int cursorline;
int blink = 0;
int underline = 0;
uint32_t ink = 0;
uint32_t fg = (self->cga.cgacol & 0x0f) ? amber : black;
uint32_t bg = black;
uint32_t cols[2];
uint8_t dat;
uint8_t pattern;
uint32_t ink0 = 0;
uint32_t ink1 = 0;
/* Switch between internal plasma and external CRT display. */
if ((cpq_st_display_internal != -1) && (cpq_st_display_internal != self->internal_monitor)) {
self->internal_monitor = cpq_st_display_internal;
compaq_plasma_recalctimings(self);
}
/* graphic mode and not mode 40h */
if (!self->internal_monitor && !(self->port_23c6 & 1)) {
cga_poll(&self->cga);
return;
}
/* mode 40h or text mode */
if (!self->cga.linepos) {
timer_advance_u64(&self->cga.timer, self->cga.dispofftime);
self->cga.cgastat |= 1;
self->cga.linepos = 1;
if (self->cga.cgadispon) {
if (self->cga.displine == 0) {
video_wait_for_buffer();
}
if (self->cga.cgamode & 2) {
if (self->cga.cgamode & 0x10) {
/* 640x400 mode */
if (self->port_23c6 & 1) /* 640*400 */ {
addr = ((self->cga.displine) & 1) * 0x2000 + ((self->cga.displine >> 1) & 1) * 0x4000 + (self->cga.displine >> 2) * 80 + ((ma & ~1) << 1);
} else {
addr = ((self->cga.displine >> 1) & 1) * 0x2000 + (self->cga.displine >> 2) * 80 + ((ma & ~1) << 1);
}
for (uint8_t x = 0; x < 80; x++) {
dat = self->cga.vram[addr & 0x7FFF];
addr++;
for (uint8_t c = 0; c < 8; c++) {
ink = (dat & 0x80) ? fg : bg;
if (!(self->cga.cgamode & 8))
ink = black;
(buffer32->line[self->cga.displine])[x * 8 + c] = ink;
dat <<= 1;
}
}
} else {
addr = ((self->cga.displine >> 1) & 1) * 0x2000 + (self->cga.displine >> 2) * 80 + ((ma & ~1) << 1);
for (uint8_t x = 0; x < 80; x++) {
dat = self->cga.vram[addr & 0x7fff];
addr++;
for (uint8_t c = 0; c < 4; c++) {
pattern = (dat & 0xC0) >> 6;
if (!(self->cga.cgamode & 8))
pattern = 0;
switch (pattern & 3) {
case 0:
ink0 = ink1 = black;
break;
case 1:
if (self->cga.displine & 1) {
ink0 = black;
ink1 = black;
} else {
ink0 = amber;
ink1 = black;
}
break;
case 2:
if (self->cga.displine & 1) {
ink0 = black;
ink1 = amber;
} else {
ink0 = amber;
ink1 = black;
}
break;
case 3:
ink0 = ink1 = amber;
break;
default:
break;
}
buffer32->line[self->cga.displine][x * 8 + 2 * c] = ink0;
buffer32->line[self->cga.displine][x * 8 + 2 * c + 1] = ink1;
dat <<= 2;
}
}
}
} else if (self->cga.cgamode & 1) {
/* 80-col */
sc = self->cga.displine & 0x0f;
addr = ((ma & ~1) + (self->cga.displine >> 4) * 80) * 2;
ma += (self->cga.displine >> 4) * 80;
if ((self->cga.crtc[0x0a] & 0x60) == 0x20)
cursorline = 0;
else
cursorline = ((self->cga.crtc[0x0a] & 0x0f) * 2 <= sc) && ((self->cga.crtc[0x0b] & 0x0F) * 2 >= sc);
/* for each text column */
for (uint8_t x = 0; x < 80; x++) {
/* video output enabled */
chr = self->cga.vram[(addr + 2 * x) & 0x7FFF];
attr = self->cga.vram[(addr + 2 * x + 1) & 0x7FFF];
drawcursor = ((ma == ca) && cursorline && (self->cga.cgamode & 8) && (self->cga.cgablink & 16));
blink = ((self->cga.cgablink & 16) && (self->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
underline = ((self->port_23c6 & 0x40) && (attr & 0x1) && !(attr & 0x6));
/* blink active */
if (self->cga.cgamode & 0x20) {
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
/* attribute 7 active and not cursor */
if (blink) {
/* set blinking */
cols[1] = cols[0];
}
} else {
/* Set intensity bit */
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
/* character underline active and 7th row of pixels in character height being drawn */
if (underline && (sc == 7)) {
/* for each pixel in character width */
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c] = cols[(fontdatm2[chr + self->cga.fontbase][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black);
} else {
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c] = cols[(fontdatm2[chr + self->cga.fontbase][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
++ma;
}
} else { /* 40-col */
sc = self->cga.displine & 0x0f;
addr = ((ma & ~1) + (self->cga.displine >> 4) * 40) * 2;
ma += (self->cga.displine >> 4) * 40;
if ((self->cga.crtc[0x0a] & 0x60) == 0x20)
cursorline = 0;
else
cursorline = ((self->cga.crtc[0x0a] & 0x0f) * 2 <= sc) && ((self->cga.crtc[0x0b] & 0x0F) * 2 >= sc);
for (uint8_t x = 0; x < 40; x++) {
chr = self->cga.vram[(addr + 2 * x) & 0x7FFF];
attr = self->cga.vram[(addr + 2 * x + 1) & 0x7FFF];
drawcursor = ((ma == ca) && cursorline && (self->cga.cgamode & 8) && (self->cga.cgablink & 16));
blink = ((self->cga.cgablink & 16) && (self->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
underline = ((self->port_23c6 & 0x40) && (attr & 0x1) && !(attr & 0x6));
/* blink active */
if (self->cga.cgamode & 0x20) {
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
/* attribute 7 active and not cursor */
if (blink) {
/* set blinking */
cols[1] = cols[0];
}
} else {
/* Set intensity bit */
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
/* character underline active and 7th row of pixels in character height being drawn */
if (underline && (sc == 7)) {
/* for each pixel in character width */
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + (c * 2)] = buffer32->line[self->cga.displine][(x << 4) + (c * 2) + 1] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + c * 2] = buffer32->line[self->cga.displine][(x << 4) + c * 2 + 1] = cols[(fontdatm2[chr][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black);
} else {
for (uint8_t c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + c * 2] = buffer32->line[self->cga.displine][(x << 4) + c * 2 + 1] = cols[(fontdatm2[chr][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
++ma;
}
}
}
self->cga.displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (self->cga.displine == 400) { /* Start of VSYNC */
self->cga.cgastat |= 8;
self->cga.cgadispon = 0;
}
if (self->cga.displine == 416) { /* End of VSYNC */
self->cga.displine = 0;
self->cga.cgastat &= ~8;
self->cga.cgadispon = 1;
}
} else {
if (self->cga.cgadispon)
self->cga.cgastat &= ~1;
timer_advance_u64(&self->cga.timer, self->cga.dispontime);
self->cga.linepos = 0;
if (self->cga.displine == 400) {
/* Hardcode 640x400 window size */
if ((640 != xsize) || (400 != ysize) || video_force_resize_get()) {
xsize = 640;
ysize = 400;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 640x400 resolution */
video_res_x = 640;
video_res_y = 400;
if (self->cga.cgamode & 0x02) {
if (self->cga.cgamode & 0x10)
video_bpp = 1;
else
video_bpp = 2;
} else
video_bpp = 0;
self->cga.cgablink++;
}
}
}
static void
compaq_plasma_mdaattr_rebuild(void)
{
for (uint16_t c = 0; c < 256; c++) {
mdaattr[c][0][0] = mdaattr[c][1][0] = mdaattr[c][1][1] = 16;
if (c & 8)
mdaattr[c][0][1] = 15 + 16;
else
mdaattr[c][0][1] = 7 + 16;
}
mdaattr[0x70][0][1] = 16;
mdaattr[0x70][0][0] = mdaattr[0x70][1][0] = mdaattr[0x70][1][1] = 16 + 15;
mdaattr[0xF0][0][1] = 16;
mdaattr[0xF0][0][0] = mdaattr[0xF0][1][0] = mdaattr[0xF0][1][1] = 16 + 15;
mdaattr[0x78][0][1] = 16 + 7;
mdaattr[0x78][0][0] = mdaattr[0x78][1][0] = mdaattr[0x78][1][1] = 16 + 15;
mdaattr[0xF8][0][1] = 16 + 7;
mdaattr[0xF8][0][0] = mdaattr[0xF8][1][0] = mdaattr[0xF8][1][1] = 16 + 15;
mdaattr[0x00][0][1] = mdaattr[0x00][1][1] = 16;
mdaattr[0x08][0][1] = mdaattr[0x08][1][1] = 16;
mdaattr[0x80][0][1] = mdaattr[0x80][1][1] = 16;
mdaattr[0x88][0][1] = mdaattr[0x88][1][1] = 16;
}
static void
compaq_plasma_recalcattrs(compaq_plasma_t *self)
{
int n;
/* val behaves as follows:
* Bit 0: Attributes 01-06, 08-0E are inverse video
* Bit 1: Attributes 01-06, 08-0E are bold
* Bit 2: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are inverse video
* Bit 3: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are bold */
/* Set up colours */
amber = makecol(0xff, 0x7d, 0x00);
black = makecol(0x64, 0x0c, 0x00);
/* Initialize the attribute mapping. Start by defaulting everything
* to black on amber, and with bold set by bit 3 */
for (n = 0; n < 256; n++) {
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
}
/* Colours 0x11-0xFF are controlled by bits 2 and 3 of the
* passed value. Exclude x0 and x8, which are always black on
* amber. */
for (n = 0x11; n <= 0xFF; n++) {
if ((n & 7) == 0)
continue;
if (self->attrmap & 4) { /* Inverse */
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
} else { /* Normal */
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
}
}
/* Set up the 01-0E range, controlled by bits 0 and 1 of the
* passed value. When blinking is enabled this also affects 81-8E. */
for (n = 0x01; n <= 0x0E; n++) {
if (n == 7)
continue;
if (self->attrmap & 1) {
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
blinkcols[n + 128][0] = amber;
blinkcols[n + 128][1] = black;
} else {
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
blinkcols[n + 128][0] = black;
blinkcols[n + 128][1] = amber;
}
}
/* Colours 07 and 0F are always amber on black. If blinking is
* enabled so are 87 and 8F. */
for (n = 0x07; n <= 0x0F; n += 8) {
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
blinkcols[n + 128][0] = black;
blinkcols[n + 128][1] = amber;
}
/* When not blinking, colours 81-8F are always amber on black. */
for (n = 0x81; n <= 0x8F; n++) {
normcols[n][0] = black;
normcols[n][1] = amber;
}
/* Finally do the ones which are solid black. These differ between
* the normal and blinking mappings */
for (n = 0; n <= 0xFF; n += 0x11)
normcols[n][0] = normcols[n][1] = black;
/* In the blinking range, 00 11 22 .. 77 and 80 91 A2 .. F7 are black */
for (n = 0; n <= 0x77; n += 0x11) {
blinkcols[n][0] = blinkcols[n][1] = black;
blinkcols[n + 128][0] = blinkcols[n + 128][1] = black;
}
}
static void *
compaq_plasma_init(UNUSED(const device_t *info))
{
compaq_plasma_t *self = malloc(sizeof(compaq_plasma_t));
memset(self, 0, sizeof(compaq_plasma_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_compaq_plasma);
if (compaq_machine_type == COMPAQ_PORTABLEIII)
loadfont_ex("roms/machines/portableiii/K Combined.bin", 11, 0x4bb2);
else
loadfont_ex("roms/machines/portableiii/P.2 Combined.bin", 11, 0x4b49);
self->cga.composite = 0;
self->cga.revision = 0;
self->cga.vram = malloc(0x8000);
self->internal_monitor = 1;
cga_comp_init(self->cga.revision);
timer_add(&self->cga.timer, compaq_plasma_poll, self, 1);
mem_mapping_add(&self->cga.mapping, 0xb8000, 0x08000, compaq_plasma_read, NULL, NULL, compaq_plasma_write, NULL, NULL, NULL /*self->cga.vram*/, MEM_MAPPING_EXTERNAL, self);
io_sethandler(0x03d0, 0x0010, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self);
io_sethandler(0x13c6, 0x0001, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self);
io_sethandler(0x1bc6, 0x0001, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self);
io_sethandler(0x23c6, 0x0001, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self);
/* Default attribute mapping is 4 */
self->attrmap = 4;
compaq_plasma_recalcattrs(self);
self->cga.cgastat = 0xf4;
overscan_x = overscan_y = 16;
self->cga.rgb_type = device_get_config_int("rgb_type");
cga_palette = (self->cga.rgb_type << 1);
cgapal_rebuild();
compaq_plasma_mdaattr_rebuild();
return self;
}
static void
compaq_plasma_close(void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
free(self->cga.vram);
free(self);
}
static void
compaq_plasma_speed_changed(void *priv)
{
compaq_plasma_t *self = (compaq_plasma_t *) priv;
compaq_plasma_recalctimings(self);
}
const device_config_t compaq_plasma_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Color", .value = 0 },
{ .description = "Green Monochrome", .value = 1 },
{ .description = "Amber Monochrome", .value = 2 },
{ .description = "Gray Monochrome", .value = 3 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t compaq_plasma_device = {
.name = "Compaq Plasma",
.internal_name = "compaq_plasma",
.flags = 0,
.local = 0,
.init = compaq_plasma_init,
.close = compaq_plasma_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = compaq_plasma_speed_changed,
.force_redraw = NULL,
.config = compaq_plasma_config
};
static uint8_t
read_ram(uint32_t addr, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return (ram[addr]);
}
static uint16_t
read_ramw(uint32_t addr, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return (*(uint16_t *) &ram[addr]);
}
static uint32_t
read_raml(uint32_t addr, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addreadlookup(mem_logical_addr, addr);
return (*(uint32_t *) &ram[addr]);
}
static void
write_ram(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
}
static void
write_ramw(uint32_t addr, uint16_t val, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
}
static void
write_raml(uint32_t addr, uint32_t val, UNUSED(void *priv))
{
addr = (addr & 0x7ffff) + 0x80000;
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
}
static void
machine_at_compaq_init(const machine_t *model, int type)
{
compaq_machine_type = type;
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
if (type < COMPAQ_PORTABLEIII386) {
mem_remap_top(384);
mem_mapping_add(&ram_mapping, 0xfa0000, 0x60000,
read_ram, read_ramw, read_raml,
write_ram, write_ramw, write_raml,
0xa0000 + ram, MEM_MAPPING_INTERNAL, NULL);
}
video_reset(gfxcard[0]);
switch (type) {
case COMPAQ_PORTABLEII:
machine_at_init(model);
break;
case COMPAQ_PORTABLEIII:
if (hdc_current[0] == HDC_INTERNAL)
device_add(&ide_isa_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&compaq_plasma_device);
machine_at_init(model);
break;
case COMPAQ_PORTABLEIII386:
if (hdc_current[0] == HDC_INTERNAL)
device_add(&ide_isa_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&compaq_plasma_device);
device_add(&compaq_386_device);
machine_at_common_init(model);
device_add(&keyboard_at_compaq_device);
break;
case COMPAQ_DESKPRO386:
case COMPAQ_DESKPRO386_05_1988:
device_add(&compaq_386_device);
machine_at_common_init(model);
device_add(&keyboard_at_compaq_device);
break;
default:
break;
}
}
int
machine_at_portableii_init(const machine_t *model)
{
int ret;
ret = bios_load_interleavedr("roms/machines/portableii/109740-001.rom",
"roms/machines/portableii/109739-001.rom",
0x000f8000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEII);
return ret;
}
int
machine_at_portableiii_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/portableiii/K Combined.bin",
0x000f8000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEIII);
return ret;
}
int
machine_at_portableiii386_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/portableiii/P.2 Combined.bin",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_PORTABLEIII386);
return ret;
}
int
machine_at_deskpro386_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/deskpro386/1986-09-04-HI.json.bin",
0x000f8000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_DESKPRO386);
return ret;
}
int
machine_at_deskpro386_05_1988_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/deskpro386/1988-05-10.json.bin",
0x000f8000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_compaq_init(model, COMPAQ_DESKPRO386_05_1988);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_compaq.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,013 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of Tandy models 1000, 1000HX and 1000SL2.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/pit.h>
#include <86box/nmi.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/sound.h>
#include <86box/snd_sn76489.h>
#include <86box/video.h>
#include <86box/vid_cga_comp.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
enum {
TANDY_RGB = 0,
TANDY_COMPOSITE
};
enum {
TYPE_TANDY = 0,
TYPE_TANDY1000SX,
TYPE_TANDY1000HX,
TYPE_TANDY1000SL2
};
enum {
EEPROM_IDLE = 0,
EEPROM_GET_OPERATION,
EEPROM_READ,
EEPROM_WRITE
};
typedef struct t1kvid_t {
mem_mapping_t mapping;
mem_mapping_t vram_mapping;
uint8_t crtc[32];
int crtcreg;
int array_index;
uint8_t array[256];
int memctrl;
uint8_t mode;
uint8_t col;
uint8_t stat;
uint8_t *vram;
uint8_t *b8000;
uint32_t b8000_mask;
uint32_t b8000_limit;
uint8_t planar_ctrl;
int linepos;
int displine;
int sc;
int vc;
int dispon;
int con;
int coff;
int cursoron;
int blink;
int fullchange;
int vsynctime;
int vadj;
uint16_t ma;
uint16_t maback;
uint64_t dispontime;
uint64_t dispofftime;
pc_timer_t timer;
int firstline;
int lastline;
int composite;
} t1kvid_t;
typedef struct t1keep_t {
char *path;
int state;
int count;
int addr;
int clk;
uint16_t data;
uint16_t store[64];
} t1keep_t;
typedef struct tandy_t {
mem_mapping_t ram_mapping;
mem_mapping_t rom_mapping; /* SL2 */
uint8_t *rom; /* SL2 */
uint8_t ram_bank;
uint8_t rom_bank; /* SL2 */
int rom_offset; /* SL2 */
uint32_t base;
uint32_t mask;
int is_hx;
int is_sl2;
t1kvid_t *vid;
} tandy_t;
static video_timings_t timing_dram = { VIDEO_BUS, 0, 0, 0, 0, 0, 0 }; /*No additional waitstates*/
static const scancode scancode_tandy[512] = {
// clang-format off
{ .mk = { 0 }, .brk = { 0 } }, /* 000 */
{ .mk = { 0x01, 0 }, .brk = { 0x81, 0 } }, /* 001 */
{ .mk = { 0x02, 0 }, .brk = { 0x82, 0 } }, /* 002 */
{ .mk = { 0x03, 0 }, .brk = { 0x83, 0 } }, /* 003 */
{ .mk = { 0x04, 0 }, .brk = { 0x84, 0 } }, /* 004 */
{ .mk = { 0x05, 0 }, .brk = { 0x85, 0 } }, /* 005 */
{ .mk = { 0x06, 0 }, .brk = { 0x86, 0 } }, /* 006 */
{ .mk = { 0x07, 0 }, .brk = { 0x87, 0 } }, /* 007 */
{ .mk = { 0x08, 0 }, .brk = { 0x88, 0 } }, /* 008 */
{ .mk = { 0x09, 0 }, .brk = { 0x89, 0 } }, /* 009 */
{ .mk = { 0x0a, 0 }, .brk = { 0x8a, 0 } }, /* 00a */
{ .mk = { 0x0b, 0 }, .brk = { 0x8b, 0 } }, /* 00b */
{ .mk = { 0x0c, 0 }, .brk = { 0x8c, 0 } }, /* 00c */
{ .mk = { 0x0d, 0 }, .brk = { 0x8d, 0 } }, /* 00d */
{ .mk = { 0x0e, 0 }, .brk = { 0x8e, 0 } }, /* 00e */
{ .mk = { 0x0f, 0 }, .brk = { 0x8f, 0 } }, /* 00f */
{ .mk = { 0x10, 0 }, .brk = { 0x90, 0 } }, /* 010 */
{ .mk = { 0x11, 0 }, .brk = { 0x91, 0 } }, /* 011 */
{ .mk = { 0x12, 0 }, .brk = { 0x92, 0 } }, /* 013 */
{ .mk = { 0x13, 0 }, .brk = { 0x93, 0 } }, /* 013 */
{ .mk = { 0x14, 0 }, .brk = { 0x94, 0 } }, /* 014 */
{ .mk = { 0x15, 0 }, .brk = { 0x95, 0 } }, /* 015 */
{ .mk = { 0x16, 0 }, .brk = { 0x96, 0 } }, /* 016 */
{ .mk = { 0x17, 0 }, .brk = { 0x97, 0 } }, /* 017 */
{ .mk = { 0x18, 0 }, .brk = { 0x98, 0 } }, /* 018 */
{ .mk = { 0x19, 0 }, .brk = { 0x99, 0 } }, /* 019 */
{ .mk = { 0x1a, 0 }, .brk = { 0x9a, 0 } }, /* 01a */
{ .mk = { 0x1b, 0 }, .brk = { 0x9b, 0 } }, /* 01b */
{ .mk = { 0x1c, 0 }, .brk = { 0x9c, 0 } }, /* 01c */
{ .mk = { 0x1d, 0 }, .brk = { 0x9d, 0 } }, /* 01d */
{ .mk = { 0x1e, 0 }, .brk = { 0x9e, 0 } }, /* 01e */
{ .mk = { 0x1f, 0 }, .brk = { 0x9f, 0 } }, /* 01f */
{ .mk = { 0x20, 0 }, .brk = { 0xa0, 0 } }, /* 020 */
{ .mk = { 0x21, 0 }, .brk = { 0xa1, 0 } }, /* 021 */
{ .mk = { 0x22, 0 }, .brk = { 0xa2, 0 } }, /* 022 */
{ .mk = { 0x23, 0 }, .brk = { 0xa3, 0 } }, /* 023 */
{ .mk = { 0x24, 0 }, .brk = { 0xa4, 0 } }, /* 024 */
{ .mk = { 0x25, 0 }, .brk = { 0xa5, 0 } }, /* 025 */
{ .mk = { 0x26, 0 }, .brk = { 0xa6, 0 } }, /* 026 */
{ .mk = { 0x27, 0 }, .brk = { 0xa7, 0 } }, /* 027 */
{ .mk = { 0x28, 0 }, .brk = { 0xa8, 0 } }, /* 028 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 029 */
{ .mk = { 0x2a, 0 }, .brk = { 0xaa, 0 } }, /* 02a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 02b */
{ .mk = { 0x2c, 0 }, .brk = { 0xac, 0 } }, /* 02c */
{ .mk = { 0x2d, 0 }, .brk = { 0xad, 0 } }, /* 02d */
{ .mk = { 0x2e, 0 }, .brk = { 0xae, 0 } }, /* 02e */
{ .mk = { 0x2f, 0 }, .brk = { 0xaf, 0 } }, /* 02f */
{ .mk = { 0x30, 0 }, .brk = { 0xb0, 0 } }, /* 030 */
{ .mk = { 0x31, 0 }, .brk = { 0xb1, 0 } }, /* 031 */
{ .mk = { 0x32, 0 }, .brk = { 0xb2, 0 } }, /* 032 */
{ .mk = { 0x33, 0 }, .brk = { 0xb3, 0 } }, /* 033 */
{ .mk = { 0x34, 0 }, .brk = { 0xb4, 0 } }, /* 034 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 035 */
{ .mk = { 0x36, 0 }, .brk = { 0xb6, 0 } }, /* 036 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 037 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 038 */
{ .mk = { 0x39, 0 }, .brk = { 0xb9, 0 } }, /* 039 */
{ .mk = { 0x3a, 0 }, .brk = { 0xba, 0 } }, /* 03a */
{ .mk = { 0x3b, 0 }, .brk = { 0xbb, 0 } }, /* 03b */
{ .mk = { 0x3c, 0 }, .brk = { 0xbc, 0 } }, /* 03c */
{ .mk = { 0x3d, 0 }, .brk = { 0xbd, 0 } }, /* 03d */
{ .mk = { 0x3e, 0 }, .brk = { 0xbe, 0 } }, /* 03e */
{ .mk = { 0x3f, 0 }, .brk = { 0xbf, 0 } }, /* 03f */
{ .mk = { 0x40, 0 }, .brk = { 0xc0, 0 } }, /* 040 */
{ .mk = { 0x41, 0 }, .brk = { 0xc1, 0 } }, /* 041 */
{ .mk = { 0x42, 0 }, .brk = { 0xc2, 0 } }, /* 042 */
{ .mk = { 0x43, 0 }, .brk = { 0xc3, 0 } }, /* 043 */
{ .mk = { 0x44, 0 }, .brk = { 0xc4, 0 } }, /* 044 */
{ .mk = { 0x45, 0 }, .brk = { 0xc5, 0 } }, /* 045 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 046 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 047 */
{ .mk = { 0x48, 0 }, .brk = { 0xc8, 0 } }, /* 048 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 049 */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 04a */
{ .mk = { 0x4b, 0 }, .brk = { 0xcb, 0 } }, /* 04b */
{ .mk = { 0x4c, 0 }, .brk = { 0xcc, 0 } }, /* 04c */
{ .mk = { 0x4d, 0 }, .brk = { 0xcd, 0 } }, /* 04d */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 04e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 04f */
{ .mk = { 0x50, 0 }, .brk = { 0xd0, 0 } }, /* 050 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 051 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 052 */
{ .mk = { 0x56, 0 }, .brk = { 0xd6, 0 } }, /* 053 */
{ .mk = { 0 }, .brk = { 0 } }, /* 054 */
{ .mk = { 0 }, .brk = { 0 } }, /* 055 */
{ .mk = { 0 }, .brk = { 0 } }, /* 056 */
{ .mk = { 0 }, .brk = { 0 } }, /* 057 */
{ .mk = { 0 }, .brk = { 0 } }, /* 058 */
{ .mk = { 0 }, .brk = { 0 } }, /* 059 */
{ .mk = { 0 }, .brk = { 0 } }, /* 05a */
{ .mk = { 0 }, .brk = { 0 } }, /* 05b */
{ .mk = { 0 }, .brk = { 0 } }, /* 05c */
{ .mk = { 0 }, .brk = { 0 } }, /* 05d */
{ .mk = { 0 }, .brk = { 0 } }, /* 05e */
{ .mk = { 0 }, .brk = { 0 } }, /* 05f */
{ .mk = { 0 }, .brk = { 0 } }, /* 060 */
{ .mk = { 0 }, .brk = { 0 } }, /* 061 */
{ .mk = { 0 }, .brk = { 0 } }, /* 062 */
{ .mk = { 0 }, .brk = { 0 } }, /* 063 */
{ .mk = { 0 }, .brk = { 0 } }, /* 064 */
{ .mk = { 0 }, .brk = { 0 } }, /* 065 */
{ .mk = { 0 }, .brk = { 0 } }, /* 066 */
{ .mk = { 0 }, .brk = { 0 } }, /* 067 */
{ .mk = { 0 }, .brk = { 0 } }, /* 068 */
{ .mk = { 0 }, .brk = { 0 } }, /* 069 */
{ .mk = { 0 }, .brk = { 0 } }, /* 06a */
{ .mk = { 0 }, .brk = { 0 } }, /* 06b */
{ .mk = { 0 }, .brk = { 0 } }, /* 06c */
{ .mk = { 0 }, .brk = { 0 } }, /* 06d */
{ .mk = { 0 }, .brk = { 0 } }, /* 06e */
{ .mk = { 0 }, .brk = { 0 } }, /* 06f */
{ .mk = { 0 }, .brk = { 0 } }, /* 070 */
{ .mk = { 0 }, .brk = { 0 } }, /* 071 */
{ .mk = { 0 }, .brk = { 0 } }, /* 072 */
{ .mk = { 0 }, .brk = { 0 } }, /* 073 */
{ .mk = { 0 }, .brk = { 0 } }, /* 074 */
{ .mk = { 0 }, .brk = { 0 } }, /* 075 */
{ .mk = { 0 }, .brk = { 0 } }, /* 076 */
{ .mk = { 0 }, .brk = { 0 } }, /* 077 */
{ .mk = { 0 }, .brk = { 0 } }, /* 078 */
{ .mk = { 0 }, .brk = { 0 } }, /* 079 */
{ .mk = { 0 }, .brk = { 0 } }, /* 07a */
{ .mk = { 0 }, .brk = { 0 } }, /* 07b */
{ .mk = { 0 }, .brk = { 0 } }, /* 07c */
{ .mk = { 0 }, .brk = { 0 } }, /* 07d */
{ .mk = { 0 }, .brk = { 0 } }, /* 07e */
{ .mk = { 0 }, .brk = { 0 } }, /* 07f */
{ .mk = { 0 }, .brk = { 0 } }, /* 080 */
{ .mk = { 0 }, .brk = { 0 } }, /* 081 */
{ .mk = { 0 }, .brk = { 0 } }, /* 082 */
{ .mk = { 0 }, .brk = { 0 } }, /* 083 */
{ .mk = { 0 }, .brk = { 0 } }, /* 084 */
{ .mk = { 0 }, .brk = { 0 } }, /* 085 */
{ .mk = { 0 }, .brk = { 0 } }, /* 086 */
{ .mk = { 0 }, .brk = { 0 } }, /* 087 */
{ .mk = { 0 }, .brk = { 0 } }, /* 088 */
{ .mk = { 0 }, .brk = { 0 } }, /* 089 */
{ .mk = { 0 }, .brk = { 0 } }, /* 08a */
{ .mk = { 0 }, .brk = { 0 } }, /* 08b */
{ .mk = { 0 }, .brk = { 0 } }, /* 08c */
{ .mk = { 0 }, .brk = { 0 } }, /* 08d */
{ .mk = { 0 }, .brk = { 0 } }, /* 08e */
{ .mk = { 0 }, .brk = { 0 } }, /* 08f */
{ .mk = { 0 }, .brk = { 0 } }, /* 090 */
{ .mk = { 0 }, .brk = { 0 } }, /* 091 */
{ .mk = { 0 }, .brk = { 0 } }, /* 092 */
{ .mk = { 0 }, .brk = { 0 } }, /* 093 */
{ .mk = { 0 }, .brk = { 0 } }, /* 094 */
{ .mk = { 0 }, .brk = { 0 } }, /* 095 */
{ .mk = { 0 }, .brk = { 0 } }, /* 096 */
{ .mk = { 0 }, .brk = { 0 } }, /* 097 */
{ .mk = { 0 }, .brk = { 0 } }, /* 098 */
{ .mk = { 0 }, .brk = { 0 } }, /* 099 */
{ .mk = { 0 }, .brk = { 0 } }, /* 09a */
{ .mk = { 0 }, .brk = { 0 } }, /* 09b */
{ .mk = { 0 }, .brk = { 0 } }, /* 09c */
{ .mk = { 0 }, .brk = { 0 } }, /* 09d */
{ .mk = { 0 }, .brk = { 0 } }, /* 09e */
{ .mk = { 0 }, .brk = { 0 } }, /* 09f */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 0af */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0be */
{ .mk = { 0 }, .brk = { 0 } }, /* 0bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 0cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0da */
{ .mk = { 0 }, .brk = { 0 } }, /* 0db */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0de */
{ .mk = { 0 }, .brk = { 0 } }, /* 0df */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 0eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 0fe */
{ .mk = { 0 }, .brk = { 0 } }, /* 0ff */
{ .mk = { 0 }, .brk = { 0 } }, /* 100 */
{ .mk = { 0 }, .brk = { 0 } }, /* 101 */
{ .mk = { 0 }, .brk = { 0 } }, /* 102 */
{ .mk = { 0 }, .brk = { 0 } }, /* 103 */
{ .mk = { 0 }, .brk = { 0 } }, /* 104 */
{ .mk = { 0 }, .brk = { 0 } }, /* 105 */
{ .mk = { 0 }, .brk = { 0 } }, /* 106 */
{ .mk = { 0 }, .brk = { 0 } }, /* 107 */
{ .mk = { 0 }, .brk = { 0 } }, /* 108 */
{ .mk = { 0 }, .brk = { 0 } }, /* 109 */
{ .mk = { 0 }, .brk = { 0 } }, /* 10a */
{ .mk = { 0 }, .brk = { 0 } }, /* 10b */
{ .mk = { 0 }, .brk = { 0 } }, /* 10c */
{ .mk = { 0 }, .brk = { 0 } }, /* 10d */
{ .mk = { 0 }, .brk = { 0 } }, /* 10e */
{ .mk = { 0 }, .brk = { 0 } }, /* 10f */
{ .mk = { 0 }, .brk = { 0 } }, /* 110 */
{ .mk = { 0 }, .brk = { 0 } }, /* 111 */
{ .mk = { 0 }, .brk = { 0 } }, /* 112 */
{ .mk = { 0 }, .brk = { 0 } }, /* 113 */
{ .mk = { 0 }, .brk = { 0 } }, /* 114 */
{ .mk = { 0 }, .brk = { 0 } }, /* 115 */
{ .mk = { 0 }, .brk = { 0 } }, /* 116 */
{ .mk = { 0 }, .brk = { 0 } }, /* 117 */
{ .mk = { 0 }, .brk = { 0 } }, /* 118 */
{ .mk = { 0 }, .brk = { 0 } }, /* 119 */
{ .mk = { 0 }, .brk = { 0 } }, /* 11a */
{ .mk = { 0 }, .brk = { 0 } }, /* 11b */
{ .mk = { 0x57, 0 }, .brk = { 0xd7, 0 } }, /* 11c */
{ .mk = { 0 }, .brk = { 0 } }, /* 11d */
{ .mk = { 0 }, .brk = { 0 } }, /* 11e */
{ .mk = { 0 }, .brk = { 0 } }, /* 11f */
{ .mk = { 0 }, .brk = { 0 } }, /* 120 */
{ .mk = { 0 }, .brk = { 0 } }, /* 121 */
{ .mk = { 0 }, .brk = { 0 } }, /* 122 */
{ .mk = { 0 }, .brk = { 0 } }, /* 123 */
{ .mk = { 0 }, .brk = { 0 } }, /* 124 */
{ .mk = { 0 }, .brk = { 0 } }, /* 125 */
{ .mk = { 0 }, .brk = { 0 } }, /* 126 */
{ .mk = { 0 }, .brk = { 0 } }, /* 127 */
{ .mk = { 0 }, .brk = { 0 } }, /* 128 */
{ .mk = { 0 }, .brk = { 0 } }, /* 129 */
{ .mk = { 0 }, .brk = { 0 } }, /* 12a */
{ .mk = { 0 }, .brk = { 0 } }, /* 12b */
{ .mk = { 0 }, .brk = { 0 } }, /* 12c */
{ .mk = { 0 }, .brk = { 0 } }, /* 12d */
{ .mk = { 0 }, .brk = { 0 } }, /* 12e */
{ .mk = { 0 }, .brk = { 0 } }, /* 12f */
{ .mk = { 0 }, .brk = { 0 } }, /* 130 */
{ .mk = { 0 }, .brk = { 0 } }, /* 131 */
{ .mk = { 0 }, .brk = { 0 } }, /* 132 */
{ .mk = { 0 }, .brk = { 0 } }, /* 133 */
{ .mk = { 0 }, .brk = { 0 } }, /* 134 */
{ .mk = { 0x35, 0 }, .brk = { 0xb5, 0 } }, /* 135 */
{ .mk = { 0 }, .brk = { 0 } }, /* 136 */
{ .mk = { 0x37, 0 }, .brk = { 0xb7, 0 } }, /* 137 */
{ .mk = { 0x38, 0 }, .brk = { 0xb8, 0 } }, /* 138 */
{ .mk = { 0 }, .brk = { 0 } }, /* 139 */
{ .mk = { 0 }, .brk = { 0 } }, /* 13a */
{ .mk = { 0 }, .brk = { 0 } }, /* 13b */
{ .mk = { 0 }, .brk = { 0 } }, /* 13c */
{ .mk = { 0 }, .brk = { 0 } }, /* 13d */
{ .mk = { 0 }, .brk = { 0 } }, /* 13e */
{ .mk = { 0 }, .brk = { 0 } }, /* 13f */
{ .mk = { 0 }, .brk = { 0 } }, /* 140 */
{ .mk = { 0 }, .brk = { 0 } }, /* 141 */
{ .mk = { 0 }, .brk = { 0 } }, /* 142 */
{ .mk = { 0 }, .brk = { 0 } }, /* 143 */
{ .mk = { 0 }, .brk = { 0 } }, /* 144 */
{ .mk = { 0 }, .brk = { 0 } }, /* 145 */
{ .mk = { 0x46, 0 }, .brk = { 0xc6, 0 } }, /* 146 */
{ .mk = { 0x47, 0 }, .brk = { 0xc7, 0 } }, /* 147 */
{ .mk = { 0x29, 0 }, .brk = { 0xa9, 0 } }, /* 148 */
{ .mk = { 0x49, 0 }, .brk = { 0xc9, 0 } }, /* 149 */
{ .mk = { 0 }, .brk = { 0 } }, /* 14a */
{ .mk = { 0x2b, 0 }, .brk = { 0xab, 0 } }, /* 14b */
{ .mk = { 0 }, .brk = { 0 } }, /* 14c */
{ .mk = { 0x4e, 0 }, .brk = { 0xce, 0 } }, /* 14d */
{ .mk = { 0 }, .brk = { 0 } }, /* 14e */
{ .mk = { 0x4f, 0 }, .brk = { 0xcf, 0 } }, /* 14f */
{ .mk = { 0x4a, 0 }, .brk = { 0xca, 0 } }, /* 150 */
{ .mk = { 0x51, 0 }, .brk = { 0xd1, 0 } }, /* 151 */
{ .mk = { 0x52, 0 }, .brk = { 0xd2, 0 } }, /* 152 */
{ .mk = { 0x53, 0 }, .brk = { 0xd3, 0 } }, /* 153 */
{ .mk = { 0 }, .brk = { 0 } }, /* 154 */
{ .mk = { 0 }, .brk = { 0 } }, /* 155 */
{ .mk = { 0 }, .brk = { 0 } }, /* 156 */
{ .mk = { 0 }, .brk = { 0 } }, /* 157 */
{ .mk = { 0 }, .brk = { 0 } }, /* 158 */
{ .mk = { 0 }, .brk = { 0 } }, /* 159 */
{ .mk = { 0 }, .brk = { 0 } }, /* 15a */
{ .mk = { 0 }, .brk = { 0 } }, /* 15b */
{ .mk = { 0 }, .brk = { 0 } }, /* 15c */
{ .mk = { 0 }, .brk = { 0 } }, /* 15d */
{ .mk = { 0 }, .brk = { 0 } }, /* 15e */
{ .mk = { 0 }, .brk = { 0 } }, /* 15f */
{ .mk = { 0 }, .brk = { 0 } }, /* 160 */
{ .mk = { 0 }, .brk = { 0 } }, /* 161 */
{ .mk = { 0 }, .brk = { 0 } }, /* 162 */
{ .mk = { 0 }, .brk = { 0 } }, /* 163 */
{ .mk = { 0 }, .brk = { 0 } }, /* 164 */
{ .mk = { 0 }, .brk = { 0 } }, /* 165 */
{ .mk = { 0 }, .brk = { 0 } }, /* 166 */
{ .mk = { 0 }, .brk = { 0 } }, /* 167 */
{ .mk = { 0 }, .brk = { 0 } }, /* 168 */
{ .mk = { 0 }, .brk = { 0 } }, /* 169 */
{ .mk = { 0 }, .brk = { 0 } }, /* 16a */
{ .mk = { 0 }, .brk = { 0 } }, /* 16b */
{ .mk = { 0 }, .brk = { 0 } }, /* 16c */
{ .mk = { 0 }, .brk = { 0 } }, /* 16d */
{ .mk = { 0 }, .brk = { 0 } }, /* 16e */
{ .mk = { 0 }, .brk = { 0 } }, /* 16f */
{ .mk = { 0 }, .brk = { 0 } }, /* 170 */
{ .mk = { 0 }, .brk = { 0 } }, /* 171 */
{ .mk = { 0 }, .brk = { 0 } }, /* 172 */
{ .mk = { 0 }, .brk = { 0 } }, /* 173 */
{ .mk = { 0 }, .brk = { 0 } }, /* 174 */
{ .mk = { 0 }, .brk = { 0 } }, /* 175 */
{ .mk = { 0 }, .brk = { 0 } }, /* 176 */
{ .mk = { 0 }, .brk = { 0 } }, /* 177 */
{ .mk = { 0 }, .brk = { 0 } }, /* 178 */
{ .mk = { 0 }, .brk = { 0 } }, /* 179 */
{ .mk = { 0 }, .brk = { 0 } }, /* 17a */
{ .mk = { 0 }, .brk = { 0 } }, /* 17b */
{ .mk = { 0 }, .brk = { 0 } }, /* 17c */
{ .mk = { 0 }, .brk = { 0 } }, /* 17d */
{ .mk = { 0 }, .brk = { 0 } }, /* 17e */
{ .mk = { 0 }, .brk = { 0 } }, /* 17f */
{ .mk = { 0 }, .brk = { 0 } }, /* 180 */
{ .mk = { 0 }, .brk = { 0 } }, /* 181 */
{ .mk = { 0 }, .brk = { 0 } }, /* 182 */
{ .mk = { 0 }, .brk = { 0 } }, /* 183 */
{ .mk = { 0 }, .brk = { 0 } }, /* 184 */
{ .mk = { 0 }, .brk = { 0 } }, /* 185 */
{ .mk = { 0 }, .brk = { 0 } }, /* 186 */
{ .mk = { 0 }, .brk = { 0 } }, /* 187 */
{ .mk = { 0 }, .brk = { 0 } }, /* 188 */
{ .mk = { 0 }, .brk = { 0 } }, /* 189 */
{ .mk = { 0 }, .brk = { 0 } }, /* 18a */
{ .mk = { 0 }, .brk = { 0 } }, /* 18b */
{ .mk = { 0 }, .brk = { 0 } }, /* 18c */
{ .mk = { 0 }, .brk = { 0 } }, /* 18d */
{ .mk = { 0 }, .brk = { 0 } }, /* 18e */
{ .mk = { 0 }, .brk = { 0 } }, /* 18f */
{ .mk = { 0 }, .brk = { 0 } }, /* 190 */
{ .mk = { 0 }, .brk = { 0 } }, /* 191 */
{ .mk = { 0 }, .brk = { 0 } }, /* 192 */
{ .mk = { 0 }, .brk = { 0 } }, /* 193 */
{ .mk = { 0 }, .brk = { 0 } }, /* 194 */
{ .mk = { 0 }, .brk = { 0 } }, /* 195 */
{ .mk = { 0 }, .brk = { 0 } }, /* 196 */
{ .mk = { 0 }, .brk = { 0 } }, /* 197 */
{ .mk = { 0 }, .brk = { 0 } }, /* 198 */
{ .mk = { 0 }, .brk = { 0 } }, /* 199 */
{ .mk = { 0 }, .brk = { 0 } }, /* 19a */
{ .mk = { 0 }, .brk = { 0 } }, /* 19b */
{ .mk = { 0 }, .brk = { 0 } }, /* 19c */
{ .mk = { 0 }, .brk = { 0 } }, /* 19d */
{ .mk = { 0 }, .brk = { 0 } }, /* 19e */
{ .mk = { 0 }, .brk = { 0 } }, /* 19f */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1a9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1aa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ab */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ac */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ad */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ae */
{ .mk = { 0 }, .brk = { 0 } }, /* 1af */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1b9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ba */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1be */
{ .mk = { 0 }, .brk = { 0 } }, /* 1bf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1c9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ca */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ce */
{ .mk = { 0 }, .brk = { 0 } }, /* 1cf */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1d9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1da */
{ .mk = { 0 }, .brk = { 0 } }, /* 1db */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1dd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1de */
{ .mk = { 0 }, .brk = { 0 } }, /* 1df */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1e9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ea */
{ .mk = { 0 }, .brk = { 0 } }, /* 1eb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ec */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ed */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ee */
{ .mk = { 0 }, .brk = { 0 } }, /* 1ef */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f0 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f1 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f2 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f3 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f4 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f5 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f6 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f7 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f8 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1f9 */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fa */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fb */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fc */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fd */
{ .mk = { 0 }, .brk = { 0 } }, /* 1fe */
{ .mk = { 0 }, .brk = { 0 } } /* 1ff */
// clang-format on
};
static uint8_t crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f,
0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static uint8_t crtcmask_sl[32] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff,
0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static int eep_data_out;
static uint8_t vid_in(uint16_t addr, void *priv);
static void vid_out(uint16_t addr, uint8_t val, void *priv);
#ifdef ENABLE_TANDY_LOG
int tandy_do_log = ENABLE_TANDY_LOG;
static void
tandy_log(const char *fmt, ...)
{
va_list ap;
if (tandy_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define tandy_log(fmt, ...)
#endif
static void
recalc_mapping(tandy_t *dev)
{
t1kvid_t *vid = dev->vid;
mem_mapping_disable(&vid->mapping);
io_removehandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
if (vid->planar_ctrl & 4) {
mem_mapping_enable(&vid->mapping);
if (vid->array[5] & 1)
mem_mapping_set_addr(&vid->mapping, 0xa0000, 0x10000);
else
mem_mapping_set_addr(&vid->mapping, 0xb8000, 0x8000);
io_sethandler(0x03d0, 16, vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
}
}
static void
recalc_timings(tandy_t *dev)
{
t1kvid_t *vid = dev->vid;
double _dispontime;
double _dispofftime;
double disptime;
disptime = vid->crtc[0] + 1;
_dispontime = vid->crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
vid->dispontime = (uint64_t) (_dispontime);
vid->dispofftime = (uint64_t) (_dispofftime);
}
static void
recalc_address(tandy_t *dev)
{
t1kvid_t *vid = dev->vid;
if ((vid->memctrl & 0xc0) == 0xc0) {
vid->vram = &ram[((vid->memctrl & 0x06) << 14) + dev->base];
vid->b8000 = &ram[((vid->memctrl & 0x30) << 11) + dev->base];
vid->b8000_mask = 0x7fff;
} else {
vid->vram = &ram[((vid->memctrl & 0x07) << 14) + dev->base];
vid->b8000 = &ram[((vid->memctrl & 0x38) << 11) + dev->base];
vid->b8000_mask = 0x3fff;
}
}
static void
recalc_address_sl(tandy_t *dev)
{
t1kvid_t *vid = dev->vid;
vid->b8000_limit = 0x8000;
if (vid->array[5] & 1) {
vid->vram = &ram[((vid->memctrl & 0x04) << 14) + dev->base];
vid->b8000 = &ram[((vid->memctrl & 0x20) << 11) + dev->base];
} else if ((vid->memctrl & 0xc0) == 0xc0) {
vid->vram = &ram[((vid->memctrl & 0x06) << 14) + dev->base];
vid->b8000 = &ram[((vid->memctrl & 0x30) << 11) + dev->base];
} else {
vid->vram = &ram[((vid->memctrl & 0x07) << 14) + dev->base];
vid->b8000 = &ram[((vid->memctrl & 0x38) << 11) + dev->base];
if ((vid->memctrl & 0x38) == 0x38)
vid->b8000_limit = 0x4000;
}
}
static void
vid_out(uint16_t addr, uint8_t val, void *priv)
{
tandy_t *dev = (tandy_t *) priv;
t1kvid_t *vid = dev->vid;
uint8_t old;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x03d4:
vid->crtcreg = val & 0x1f;
break;
case 0x03d5:
old = vid->crtc[vid->crtcreg];
if (dev->is_sl2)
vid->crtc[vid->crtcreg] = val & crtcmask_sl[vid->crtcreg];
else
vid->crtc[vid->crtcreg] = val & crtcmask[vid->crtcreg];
if (old != val) {
if (vid->crtcreg < 0xe || vid->crtcreg > 0x10) {
vid->fullchange = changeframecount;
recalc_timings(dev);
}
}
break;
case 0x03d8:
vid->mode = val;
if (!dev->is_sl2)
update_cga16_color(vid->mode);
break;
case 0x03d9:
vid->col = val;
break;
case 0x03da:
vid->array_index = val & 0x1f;
break;
case 0x03de:
if (vid->array_index & 16)
val &= 0xf;
vid->array[vid->array_index & 0x1f] = val;
if (dev->is_sl2) {
if ((vid->array_index & 0x1f) == 5) {
recalc_mapping(dev);
recalc_address_sl(dev);
}
}
break;
case 0x03df:
vid->memctrl = val;
if (dev->is_sl2)
recalc_address_sl(dev);
else
recalc_address(dev);
break;
case 0x0065:
if (val == 8)
return; /*Hack*/
vid->planar_ctrl = val;
recalc_mapping(dev);
break;
default:
break;
}
}
static uint8_t
vid_in(uint16_t addr, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
const t1kvid_t *vid = dev->vid;
uint8_t ret = 0xff;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x03d4:
ret = vid->crtcreg;
break;
case 0x03d5:
ret = vid->crtc[vid->crtcreg];
break;
case 0x03da:
ret = vid->stat;
break;
default:
break;
}
return ret;
}
static void
vid_write(uint32_t addr, uint8_t val, void *priv)
{
tandy_t *dev = (tandy_t *) priv;
t1kvid_t *vid = dev->vid;
if (vid->memctrl == -1)
return;
if (dev->is_sl2) {
if (vid->array[5] & 1)
vid->b8000[addr & 0xffff] = val;
else {
if ((addr & 0x7fff) < vid->b8000_limit)
vid->b8000[addr & 0x7fff] = val;
}
} else {
vid->b8000[addr & vid->b8000_mask] = val;
}
}
static uint8_t
vid_read(uint32_t addr, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
const t1kvid_t *vid = dev->vid;
if (vid->memctrl == -1)
return 0xff;
if (dev->is_sl2) {
if (vid->array[5] & 1)
return (vid->b8000[addr & 0xffff]);
if ((addr & 0x7fff) < vid->b8000_limit)
return (vid->b8000[addr & 0x7fff]);
else
return 0xff;
} else {
return (vid->b8000[addr & vid->b8000_mask]);
}
}
static void
vid_poll(void *priv)
{
tandy_t *dev = (tandy_t *) priv;
t1kvid_t *vid = dev->vid;
uint16_t ca = (vid->crtc[15] | (vid->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint16_t dat;
int cols[4];
int col;
int oldsc;
if (!vid->linepos) {
timer_advance_u64(&vid->timer, vid->dispofftime);
vid->stat |= 1;
vid->linepos = 1;
oldsc = vid->sc;
if ((vid->crtc[8] & 3) == 3)
vid->sc = (vid->sc << 1) & 7;
if (vid->dispon) {
if (vid->displine < vid->firstline) {
vid->firstline = vid->displine;
video_wait_for_buffer();
}
vid->lastline = vid->displine;
cols[0] = (vid->array[2] & 0xf) + 16;
for (c = 0; c < 8; c++) {
if (vid->array[3] & 4) {
buffer32->line[vid->displine << 1][c] = buffer32->line[(vid->displine << 1) + 1][c] = cols[0];
if (vid->mode & 1) {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 3) + 8] = cols[0];
} else {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 4) + 8] = cols[0];
}
} else if ((vid->mode & 0x12) == 0x12) {
buffer32->line[vid->displine << 1][c] = buffer32->line[(vid->displine << 1) + 1][c] = 0;
if (vid->mode & 1) {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 3) + 8] = 0;
} else {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 4) + 8] = 0;
}
} else {
buffer32->line[vid->displine << 1][c] = buffer32->line[(vid->displine << 1) + 1][c] = (vid->col & 15) + 16;
if (vid->mode & 1) {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 3) + 8] = (vid->col & 15) + 16;
} else {
buffer32->line[vid->displine << 1][c + (vid->crtc[1] << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][c + (vid->crtc[1] << 4) + 8] = (vid->col & 15) + 16;
}
}
}
if (dev->is_sl2 && (vid->array[5] & 1)) { /*640x200x16*/
for (x = 0; x < vid->crtc[1] * 2; x++) {
dat = (vid->vram[(vid->ma << 1) & 0xffff] << 8) | vid->vram[((vid->ma << 1) + 1) & 0xffff];
vid->ma++;
buffer32->line[vid->displine << 1][(x << 2) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 2) + 8] = vid->array[((dat >> 12) & 0xf) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 2) + 9] = buffer32->line[(vid->displine << 1) + 1][(x << 2) + 9] = vid->array[((dat >> 8) & 0xf) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 2) + 10] = buffer32->line[(vid->displine << 1) + 1][(x << 2) + 10] = vid->array[((dat >> 4) & 0xf) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 2) + 11] = buffer32->line[(vid->displine << 1) + 1][(x << 2) + 11] = vid->array[(dat & 0xf) + 16] + 16;
}
} else if ((vid->array[3] & 0x10) && (vid->mode & 1)) { /*320x200x16*/
for (x = 0; x < vid->crtc[1]; x++) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000) + 1];
vid->ma++;
buffer32->line[vid->displine << 1][(x << 3) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 8] = buffer32->line[vid->displine << 1][(x << 3) + 9] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 9] = vid->array[((dat >> 12) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 3) + 10] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 10] = buffer32->line[vid->displine << 1][(x << 3) + 11] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 11] = vid->array[((dat >> 8) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 3) + 12] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 12] = buffer32->line[vid->displine << 1][(x << 3) + 13] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 13] = vid->array[((dat >> 4) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 3) + 14] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 14] = buffer32->line[vid->displine << 1][(x << 3) + 15] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 15] = vid->array[(dat & vid->array[1] & 0x0f) + 16] + 16;
}
} else if (vid->array[3] & 0x10) { /*160x200x16*/
for (x = 0; x < vid->crtc[1]; x++) {
if (dev->is_sl2) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000) + 1];
} else {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000) + 1];
}
vid->ma++;
buffer32->line[vid->displine << 1][(x << 4) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 8] = buffer32->line[vid->displine << 1][(x << 4) + 9] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 9] = buffer32->line[vid->displine << 1][(x << 4) + 10] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 10] = buffer32->line[vid->displine << 1][(x << 4) + 11] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 11] = vid->array[((dat >> 12) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 4) + 12] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 12] = buffer32->line[vid->displine << 1][(x << 4) + 13] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 13] = buffer32->line[vid->displine << 1][(x << 4) + 14] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 14] = buffer32->line[vid->displine << 1][(x << 4) + 15] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 15] = vid->array[((dat >> 8) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 4) + 16] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 16] = buffer32->line[vid->displine << 1][(x << 4) + 17] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 17] = buffer32->line[vid->displine << 1][(x << 4) + 18] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 18] = buffer32->line[vid->displine << 1][(x << 4) + 19] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 19] = vid->array[((dat >> 4) & vid->array[1] & 0x0f) + 16] + 16;
buffer32->line[vid->displine << 1][(x << 4) + 20] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 20] = buffer32->line[vid->displine << 1][(x << 4) + 21] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 21] = buffer32->line[vid->displine << 1][(x << 4) + 22] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 22] = buffer32->line[vid->displine << 1][(x << 4) + 23] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + 23] = vid->array[(dat & vid->array[1] & 0x0f) + 16] + 16;
}
} else if (vid->array[3] & 0x08) { /*640x200x4 - this implementation is a complete guess!*/
for (x = 0; x < vid->crtc[1]; x++) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 3) * 0x2000) + 1];
vid->ma++;
for (c = 0; c < 8; c++) {
chr = (dat >> 6) & 2;
chr |= ((dat >> 15) & 1);
buffer32->line[vid->displine << 1][(x << 3) + 8 + c] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + 8 + c] = vid->array[(chr & vid->array[1]) + 16] + 16;
dat <<= 1;
}
}
} else if (vid->mode & 1) {
for (x = 0; x < vid->crtc[1]; x++) {
chr = vid->vram[(vid->ma << 1) & 0x3fff];
attr = vid->vram[((vid->ma << 1) + 1) & 0x3fff];
drawcursor = ((vid->ma == ca) && vid->con && vid->cursoron);
if (vid->mode & 0x20) {
cols[1] = vid->array[((attr & 15) & vid->array[1]) + 16] + 16;
cols[0] = vid->array[(((attr >> 4) & 7) & vid->array[1]) + 16] + 16;
if ((vid->blink & 16) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = vid->array[((attr & 15) & vid->array[1]) + 16] + 16;
cols[0] = vid->array[((attr >> 4) & vid->array[1]) + 16] + 16;
}
if (vid->sc & 8) {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] = cols[0];
}
} else {
for (c = 0; c < 8; c++) {
if (vid->sc == 8) {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] = cols[(fontdat[chr][7] & (1 << (c ^ 7))) ? 1 : 0];
} else {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] = cols[(fontdat[chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
}
if (drawcursor) {
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 3) + c + 8] ^= 15;
buffer32->line[(vid->displine << 1) + 1][(x << 3) + c + 8] ^= 15;
}
}
vid->ma++;
}
} else if (!(vid->mode & 2)) {
for (x = 0; x < vid->crtc[1]; x++) {
chr = vid->vram[(vid->ma << 1) & 0x3fff];
attr = vid->vram[((vid->ma << 1) + 1) & 0x3fff];
drawcursor = ((vid->ma == ca) && vid->con && vid->cursoron);
if (vid->mode & 0x20) {
cols[1] = vid->array[((attr & 15) & vid->array[1]) + 16] + 16;
cols[0] = vid->array[(((attr >> 4) & 7) & vid->array[1]) + 16] + 16;
if ((vid->blink & 16) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = vid->array[((attr & 15) & vid->array[1]) + 16] + 16;
cols[0] = vid->array[((attr >> 4) & vid->array[1]) + 16] + 16;
}
vid->ma++;
if (vid->sc & 8) {
for (c = 0; c < 8; c++)
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = cols[0];
} else {
for (c = 0; c < 8; c++) {
if (vid->sc == 8) {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[chr][7] & (1 << (c ^ 7))) ? 1 : 0];
} else {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdat[chr][vid->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
}
if (drawcursor) {
for (c = 0; c < 16; c++) {
buffer32->line[vid->displine << 1][(x << 4) + c + 8] ^= 15;
buffer32->line[(vid->displine << 1) + 1][(x << 4) + c + 8] ^= 15;
}
}
}
} else if (!(vid->mode & 16)) {
cols[0] = (vid->col & 15);
col = (vid->col & 16) ? 8 : 0;
if (vid->mode & 4) {
cols[1] = col | 3;
cols[2] = col | 4;
cols[3] = col | 7;
} else if (vid->col & 32) {
cols[1] = col | 3;
cols[2] = col | 5;
cols[3] = col | 7;
} else {
cols[1] = col | 2;
cols[2] = col | 4;
cols[3] = col | 6;
}
cols[0] = vid->array[(cols[0] & vid->array[1]) + 16] + 16;
cols[1] = vid->array[(cols[1] & vid->array[1]) + 16] + 16;
cols[2] = vid->array[(cols[2] & vid->array[1]) + 16] + 16;
cols[3] = vid->array[(cols[3] & vid->array[1]) + 16] + 16;
for (x = 0; x < vid->crtc[1]; x++) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000) + 1];
vid->ma++;
for (c = 0; c < 8; c++) {
buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 8] = buffer32->line[vid->displine << 1][(x << 4) + (c << 1) + 1 + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + (c << 1) + 1 + 8] = cols[dat >> 14];
dat <<= 2;
}
}
} else {
cols[0] = 0;
cols[1] = vid->array[(vid->col & vid->array[1]) + 16] + 16;
for (x = 0; x < vid->crtc[1]; x++) {
dat = (vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000)] << 8) | vid->vram[((vid->ma << 1) & 0x1fff) + ((vid->sc & 1) * 0x2000) + 1];
vid->ma++;
for (c = 0; c < 16; c++) {
buffer32->line[vid->displine << 1][(x << 4) + c + 8] = buffer32->line[(vid->displine << 1) + 1][(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
}
}
} else {
if (vid->array[3] & 4) {
if (vid->mode & 1) {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 3) + 16, (vid->array[2] & 0xf) + 16);
hline(buffer32, 0, (vid->displine << 1) + 1, (vid->crtc[1] << 3) + 16, (vid->array[2] & 0xf) + 16);
} else {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 4) + 16, (vid->array[2] & 0xf) + 16);
hline(buffer32, 0, (vid->displine << 1) + 1, (vid->crtc[1] << 4) + 16, (vid->array[2] & 0xf) + 16);
}
} else {
cols[0] = ((vid->mode & 0x12) == 0x12) ? 0 : (vid->col & 0xf) + 16;
if (vid->mode & 1) {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 3) + 16, cols[0]);
hline(buffer32, 0, (vid->displine << 1) + 1, (vid->crtc[1] << 3) + 16, cols[0]);
} else {
hline(buffer32, 0, (vid->displine << 1), (vid->crtc[1] << 4) + 16, cols[0]);
hline(buffer32, 0, (vid->displine << 1) + 1, (vid->crtc[1] << 4) + 16, cols[0]);
}
}
}
if (vid->mode & 1)
x = (vid->crtc[1] << 3) + 16;
else
x = (vid->crtc[1] << 4) + 16;
if (!dev->is_sl2 && vid->composite) {
Composite_Process(vid->mode, 0, x >> 2, buffer32->line[vid->displine << 1]);
Composite_Process(vid->mode, 0, x >> 2, buffer32->line[(vid->displine << 1) + 1]);
} else {
video_process_8(x, vid->displine << 1);
video_process_8(x, (vid->displine << 1) + 1);
}
vid->sc = oldsc;
if (vid->vc == vid->crtc[7] && !vid->sc)
vid->stat |= 8;
vid->displine++;
if (vid->displine >= 360)
vid->displine = 0;
} else {
timer_advance_u64(&vid->timer, vid->dispontime);
if (vid->dispon)
vid->stat &= ~1;
vid->linepos = 0;
if (vid->vsynctime) {
vid->vsynctime--;
if (!vid->vsynctime)
vid->stat &= ~8;
}
if (vid->sc == (vid->crtc[11] & 31) || ((vid->crtc[8] & 3) == 3 && vid->sc == ((vid->crtc[11] & 31) >> 1))) {
vid->con = 0;
vid->coff = 1;
}
if (vid->vadj) {
vid->sc++;
vid->sc &= 31;
vid->ma = vid->maback;
vid->vadj--;
if (!vid->vadj) {
vid->dispon = 1;
if (dev->is_sl2 && (vid->array[5] & 1))
vid->ma = vid->maback = vid->crtc[13] | (vid->crtc[12] << 8);
else
vid->ma = vid->maback = (vid->crtc[13] | (vid->crtc[12] << 8)) & 0x3fff;
vid->sc = 0;
}
} else if (vid->sc == vid->crtc[9] || ((vid->crtc[8] & 3) == 3 && vid->sc == (vid->crtc[9] >> 1))) {
vid->maback = vid->ma;
vid->sc = 0;
oldvc = vid->vc;
vid->vc++;
if (dev->is_sl2)
vid->vc &= 255;
else
vid->vc &= 127;
if (vid->vc == vid->crtc[6])
vid->dispon = 0;
if (oldvc == vid->crtc[4]) {
vid->vc = 0;
vid->vadj = vid->crtc[5];
if (!vid->vadj)
vid->dispon = 1;
if (!vid->vadj) {
if (dev->is_sl2 && (vid->array[5] & 1))
vid->ma = vid->maback = vid->crtc[13] | (vid->crtc[12] << 8);
else
vid->ma = vid->maback = (vid->crtc[13] | (vid->crtc[12] << 8)) & 0x3fff;
}
if ((vid->crtc[10] & 0x60) == 0x20)
vid->cursoron = 0;
else
vid->cursoron = vid->blink & 16;
}
if (vid->vc == vid->crtc[7]) {
vid->dispon = 0;
vid->displine = 0;
vid->vsynctime = 16;
if (vid->crtc[7]) {
if (vid->mode & 1)
x = (vid->crtc[1] << 3) + 16;
else
x = (vid->crtc[1] << 4) + 16;
vid->lastline++;
xs_temp = x;
ys_temp = (vid->lastline - vid->firstline) << 1;
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xs_temp < 64)
xs_temp = 656;
if (ys_temp < 32)
ys_temp = 400;
if (!enable_overscan)
xs_temp -= 16;
if ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get()) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
if (enable_overscan) {
video_blit_memtoscreen(0, (vid->firstline - 4) << 1,
xsize, ((vid->lastline - vid->firstline) + 8) << 1);
} else {
video_blit_memtoscreen(8, vid->firstline << 1,
xsize, (vid->lastline - vid->firstline) << 1);
}
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
if ((vid->array[3] & 0x10) && (vid->mode & 1)) { /*320x200x16*/
video_res_x /= 2;
video_bpp = 4;
} else if (vid->array[3] & 0x10) { /*160x200x16*/
video_res_x /= 4;
video_bpp = 4;
} else if (vid->array[3] & 0x08) { /*640x200x4 - this implementation is a complete guess!*/
video_bpp = 2;
} else if (vid->mode & 1) {
video_res_x /= 8;
video_res_y /= vid->crtc[9] + 1;
video_bpp = 0;
} else if (!(vid->mode & 2)) {
video_res_x /= 16;
video_res_y /= vid->crtc[9] + 1;
video_bpp = 0;
} else if (!(vid->mode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else {
video_bpp = 1;
}
}
vid->firstline = 1000;
vid->lastline = 0;
vid->blink++;
}
} else {
vid->sc++;
vid->sc &= 31;
vid->ma = vid->maback;
}
if (vid->sc == (vid->crtc[10] & 31) || ((vid->crtc[8] & 3) == 3 && vid->sc == ((vid->crtc[10] & 31) >> 1)))
vid->con = 1;
}
}
static void
vid_speed_changed(void *priv)
{
tandy_t *dev = (tandy_t *) priv;
recalc_timings(dev);
}
static void
vid_close(void *priv)
{
tandy_t *dev = (tandy_t *) priv;
free(dev->vid);
dev->vid = NULL;
}
static void
vid_init(tandy_t *dev)
{
int display_type;
t1kvid_t *vid;
vid = malloc(sizeof(t1kvid_t));
memset(vid, 0x00, sizeof(t1kvid_t));
vid->memctrl = -1;
dev->vid = vid;
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_dram);
display_type = machine_get_config_int("display_type");
vid->composite = (display_type != TANDY_RGB);
cga_comp_init(1);
if (dev->is_sl2) {
vid->b8000_limit = 0x8000;
vid->planar_ctrl = 4;
overscan_x = overscan_y = 16;
io_sethandler(0x0065, 1, vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
} else
vid->b8000_mask = 0x3fff;
timer_add(&vid->timer, vid_poll, dev, 1);
mem_mapping_add(&vid->mapping, 0xb8000, 0x08000,
vid_read, NULL, NULL, vid_write, NULL, NULL, NULL, 0, dev);
io_sethandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
}
const device_config_t vid_config[] = {
// clang-format off
{
.name = "display_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = TANDY_RGB,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "RGB", .value = TANDY_RGB },
{ .description = "Composite", .value = TANDY_COMPOSITE },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t vid_device = {
.name = "Tandy 1000",
.internal_name = "tandy1000_video",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed,
.force_redraw = NULL,
.config = vid_config
};
const device_t vid_device_hx = {
.name = "Tandy 1000 HX",
.internal_name = "tandy1000_hx_video",
.flags = 0,
.local = 0,
.init = NULL,
.close = vid_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed,
.force_redraw = NULL,
.config = vid_config
};
const device_t vid_device_sl = {
.name = "Tandy 1000SL2",
.internal_name = "tandy1000_sl_video",
.flags = 0,
.local = 1,
.init = NULL,
.close = vid_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed,
.force_redraw = NULL,
.config = NULL
};
static void
eep_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
t1keep_t *eep = (t1keep_t *) priv;
if ((val & 4) && !eep->clk)
switch (eep->state) {
case EEPROM_IDLE:
switch (eep->count) {
case 0:
if (!(val & 3))
eep->count = 1;
else
eep->count = 0;
break;
case 1:
if ((val & 3) == 2)
eep->count = 2;
else
eep->count = 0;
break;
case 2:
if ((val & 3) == 3)
eep->state = EEPROM_GET_OPERATION;
eep->count = 0;
break;
default:
break;
}
break;
case EEPROM_GET_OPERATION:
eep->data = (eep->data << 1) | (val & 1);
eep->count++;
if (eep->count == 8) {
eep->count = 0;
eep->addr = eep->data & 0x3f;
switch (eep->data & 0xc0) {
case 0x40:
eep->state = EEPROM_WRITE;
break;
case 0x80:
eep->state = EEPROM_READ;
eep->data = eep->store[eep->addr];
break;
default:
eep->state = EEPROM_IDLE;
break;
}
}
break;
case EEPROM_READ:
eep_data_out = eep->data & 0x8000;
eep->data <<= 1;
eep->count++;
if (eep->count == 16) {
eep->count = 0;
eep->state = EEPROM_IDLE;
}
break;
case EEPROM_WRITE:
eep->data = (eep->data << 1) | (val & 1);
eep->count++;
if (eep->count == 16) {
eep->count = 0;
eep->state = EEPROM_IDLE;
eep->store[eep->addr] = eep->data;
}
break;
default:
break;
}
eep->clk = val & 4;
}
static void *
eep_init(const device_t *info)
{
t1keep_t *eep;
FILE *fp = NULL;
eep = (t1keep_t *) malloc(sizeof(t1keep_t));
memset(eep, 0x00, sizeof(t1keep_t));
switch (info->local) {
case TYPE_TANDY1000HX:
eep->path = "tandy1000hx.bin";
break;
case TYPE_TANDY1000SL2:
eep->path = "tandy1000sl2.bin";
break;
default:
break;
}
fp = nvr_fopen(eep->path, "rb");
if (fp != NULL) {
if (fread(eep->store, 1, 128, fp) != 128)
fatal("eep_init(): Error reading Tandy EEPROM\n");
(void) fclose(fp);
} else
memset(eep->store, 0x00, 128);
io_sethandler(0x037c, 1, NULL, NULL, NULL, eep_write, NULL, NULL, eep);
return eep;
}
static void
eep_close(void *priv)
{
t1keep_t *eep = (t1keep_t *) priv;
FILE *fp = NULL;
fp = nvr_fopen(eep->path, "wb");
if (fp != NULL) {
(void) fwrite(eep->store, 128, 1, fp);
(void) fclose(fp);
}
free(eep);
}
static const device_t eep_1000hx_device = {
.name = "Tandy 1000HX EEPROM",
.internal_name = "eep_1000hx",
.flags = 0,
.local = TYPE_TANDY1000HX,
.init = eep_init,
.close = eep_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static const device_t eep_1000sl2_device = {
.name = "Tandy 1000SL2 EEPROM",
.internal_name = "eep_1000sl2",
.flags = 0,
.local = TYPE_TANDY1000SL2,
.init = eep_init,
.close = eep_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
static void
tandy_write(uint16_t addr, uint8_t val, void *priv)
{
tandy_t *dev = (tandy_t *) priv;
switch (addr) {
case 0x00a0:
if (dev->is_hx && (val & 0x10)) {
dev->base = (mem_size - 256) * 1024;
dev->mask = 0x3ffff;
mem_mapping_set_addr(&ram_low_mapping, 0, dev->base);
mem_mapping_set_addr(&dev->ram_mapping,
(((val >> 1) & 7) - 1) * 128 * 1024, 0x40000);
} else {
dev->base = (mem_size - 128) * 1024;
dev->mask = 0x1ffff;
mem_mapping_set_addr(&ram_low_mapping, 0, dev->base);
mem_mapping_set_addr(&dev->ram_mapping,
((val >> 1) & 7) * 128 * 1024, 0x20000);
}
if (dev->is_hx) {
io_removehandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
if (val & 0x01)
mem_mapping_disable(&dev->vid->mapping);
else {
io_sethandler(0x03d0, 16,
vid_in, NULL, NULL, vid_out, NULL, NULL, dev);
mem_mapping_set_addr(&dev->vid->mapping, 0xb8000, 0x8000);
}
} else {
if (val & 0x01)
mem_mapping_set_addr(&dev->vid->mapping, 0xc0000, 0x10000);
else
mem_mapping_set_addr(&dev->vid->mapping, 0xb8000, 0x8000);
}
dev->ram_bank = val;
break;
case 0xffe8:
if ((val & 0xe) == 0xe)
mem_mapping_disable(&dev->ram_mapping);
else
mem_mapping_set_addr(&dev->ram_mapping,
((val >> 1) & 7) * 128 * 1024,
0x20000);
recalc_address_sl(dev);
dev->ram_bank = val;
break;
case 0xffea:
dev->rom_bank = val;
dev->rom_offset = ((val ^ 4) & 7) * 0x10000;
mem_mapping_set_exec(&dev->rom_mapping,
&dev->rom[dev->rom_offset]);
break;
default:
break;
}
}
static uint8_t
tandy_read(uint16_t addr, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x00a0:
ret = dev->ram_bank;
break;
case 0xffe8:
ret = dev->ram_bank;
break;
case 0xffea:
ret = (dev->rom_bank ^ 0x10);
break;
default:
break;
}
return ret;
}
static void
write_ram(uint32_t addr, uint8_t val, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
ram[dev->base + (addr & dev->mask)] = val;
}
static uint8_t
read_ram(uint32_t addr, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
return (ram[dev->base + (addr & dev->mask)]);
}
static uint8_t
read_rom(uint32_t addr, void *priv)
{
const tandy_t *dev = (tandy_t *) priv;
uint32_t addr2 = (addr & 0xffff) + dev->rom_offset;
return (dev->rom[addr2]);
}
static uint16_t
read_romw(uint32_t addr, void *priv)
{
tandy_t *dev = (tandy_t *) priv;
uint32_t addr2 = (addr & 0xffff) + dev->rom_offset;
return (*(uint16_t *) &dev->rom[addr2]);
}
static uint32_t
read_roml(uint32_t addr, void *priv)
{
tandy_t *dev = (tandy_t *) priv;
return (*(uint32_t *) &dev->rom[addr]);
}
static void
init_rom(tandy_t *dev)
{
dev->rom = (uint8_t *) malloc(0x80000);
#if 1
if (!rom_load_interleaved("roms/machines/tandy1000sl2/8079047.hu1",
"roms/machines/tandy1000sl2/8079048.hu2",
0x000000, 0x80000, 0, dev->rom)) {
tandy_log("TANDY: unable to load BIOS for 1000/SL2 !\n");
free(dev->rom);
dev->rom = NULL;
return;
}
#else
f = rom_fopen("roms/machines/tandy1000sl2/8079047.hu1", "rb");
ff = rom_fopen("roms/machines/tandy1000sl2/8079048.hu2", "rb");
for (c = 0x0000; c < 0x80000; c += 2) {
dev->rom[c] = getc(f);
dev->rom[c + 1] = getc(ff);
}
fclose(ff);
fclose(f);
#endif
mem_mapping_add(&dev->rom_mapping, 0xe0000, 0x10000,
read_rom, read_romw, read_roml, NULL, NULL, NULL,
dev->rom, MEM_MAPPING_EXTERNAL, dev);
}
static void
machine_tandy1k_init(const machine_t *model, int type)
{
tandy_t *dev;
dev = calloc(1, sizeof(tandy_t));
machine_common_init(model);
nmi_init();
/*
* Base 128K mapping is controlled via ports 0xA0 or
* 0xFFE8 (SL2), so we remove it from the main mapping.
*/
dev->base = (mem_size - 128) * 1024;
dev->mask = 0x1ffff;
mem_mapping_add(&dev->ram_mapping, 0x60000, 0x20000,
read_ram, NULL, NULL, write_ram, NULL, NULL, NULL,
MEM_MAPPING_INTERNAL, dev);
mem_mapping_set_addr(&ram_low_mapping, 0, dev->base);
device_add(&keyboard_tandy_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_tandy_device);
video_reset(gfxcard[0]);
switch (type) {
case TYPE_TANDY:
case TYPE_TANDY1000SX:
keyboard_set_table(scancode_tandy);
io_sethandler(0x00a0, 1,
tandy_read, NULL, NULL, tandy_write, NULL, NULL, dev);
vid_init(dev);
device_add_ex(&vid_device, dev);
device_add((type == TYPE_TANDY1000SX) ? &ncr8496_device : &sn76489_device);
break;
case TYPE_TANDY1000HX:
dev->is_hx = 1;
keyboard_set_table(scancode_tandy);
io_sethandler(0x00a0, 1,
tandy_read, NULL, NULL, tandy_write, NULL, NULL, dev);
vid_init(dev);
device_add_ex(&vid_device, dev);
device_add(&ncr8496_device);
device_add(&eep_1000hx_device);
break;
case TYPE_TANDY1000SL2:
dev->is_sl2 = 1;
init_rom(dev);
io_sethandler(0xffe8, 8,
tandy_read, NULL, NULL, tandy_write, NULL, NULL, dev);
vid_init(dev);
device_add_ex(&vid_device_sl, dev);
device_add(&pssj_device);
device_add(&eep_1000sl2_device);
break;
default:
break;
}
standalone_gameport_type = &gameport_device;
eep_data_out = 0x0000;
}
int
tandy1k_eeprom_read(void)
{
return eep_data_out;
}
int
machine_tandy1000sx_init(const machine_t *model)
{
int ret;
ret = bios_load_linearr("roms/machines/tandy/tandy1t1.020",
0x000f0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_tandy1k_init(model, TYPE_TANDY1000SX);
return ret;
}
int
machine_tandy1000hx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tandy1000hx/v020000.u12",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_tandy1k_init(model, TYPE_TANDY1000HX);
return ret;
}
int
machine_tandy1000sl2_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/tandy1000sl2/8079047.hu1",
"roms/machines/tandy1000sl2/8079048.hu2",
0x000f0000, 65536, 0x18000);
if (bios_only || !ret)
return ret;
machine_tandy1k_init(model, TYPE_TANDY1000SL2);
return ret;
}
``` | /content/code_sandbox/src/machine/m_tandy.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 29,129 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Toshiba 3100e plasma display.
* This display has a fixed 640x400 resolution.
*
* T3100e CRTC regs (from the ROM):
*
* Selecting a character height of 3 seems to be sufficient to
* convert the 640x200 graphics mode to 640x400 (and, by
* analogy, 320x200 to 320x400).
*
* Horiz-----> Vert------> I ch
* 38 28 2D 0A 1F 06 19 1C 02 07 06 07 CO40
* 71 50 5A 0A 1F 06 19 1C 02 07 06 07 CO80
* 38 28 2D 0A 7F 06 64 70 02 01 06 07 Graphics
* 61 50 52 0F 19 06 19 19 02 0D 0B 0C MONO
* 2D 28 22 0A 67 00 64 67 02 03 06 07 640x400
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include "cpu.h"
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/m_at_t3100e.h>
#include <86box/plat_unused.h>
#define T3100E_XSIZE 640
#define T3100E_YSIZE 400
/*Very rough estimate*/
#define VID_CLOCK (double) (651 * 416 * 60)
/* Mapping of attributes to colours */
static uint32_t amber;
static uint32_t black;
static uint8_t boldcols[256]; /* Which attributes use the bold font */
static uint32_t blinkcols[256][2];
static uint32_t normcols[256][2];
/* Video options set by the motherboard; they will be picked up by the card
* on the next poll.
*
* Bit 3: Disable built-in video (for add-on card)
* Bit 2: Thin font
* Bits 0,1: Font set (not currently implemented)
*/
static uint8_t st_video_options;
static int8_t st_display_internal = -1;
void
t3100e_video_options_set(uint8_t options)
{
st_video_options = options;
}
void
t3100e_display_set(uint8_t internal)
{
st_display_internal = internal;
}
uint8_t
t3100e_display_get(void)
{
return st_display_internal;
}
typedef struct t3100e_t {
mem_mapping_t mapping;
cga_t cga; /* The CGA is used for the external
* display; most of its registers are
* ignored by the plasma display. */
int font; /* Current font, 0-3 */
int enabled; /* Hardware enabled, 0 or 1 */
int internal; /* Using internal display? */
uint8_t attrmap; /* Attribute mapping register */
uint64_t dispontime, dispofftime;
int linepos, displine;
int vc;
int dispon;
int vsynctime;
uint8_t video_options;
uint8_t *vram;
} t3100e_t;
static video_timings_t timing_t3100e = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
void t3100e_recalctimings(t3100e_t *t3100e);
void t3100e_write(uint32_t addr, uint8_t val, void *priv);
uint8_t t3100e_read(uint32_t addr, void *priv);
void t3100e_recalcattrs(t3100e_t *t3100e);
void
t3100e_out(uint16_t addr, uint8_t val, void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
switch (addr) {
/* Emulated CRTC, register select */
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
cga_out(addr, val, &t3100e->cga);
break;
/* Emulated CRTC, value */
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
/* Register 0x12 controls the attribute mappings for the
* plasma screen. */
if (t3100e->cga.crtcreg == 0x12) {
t3100e->attrmap = val;
t3100e_recalcattrs(t3100e);
return;
}
cga_out(addr, val, &t3100e->cga);
t3100e_recalctimings(t3100e);
return;
case 0x3D8: /* CGA control register */
case 0x3D9: /* CGA colour register */
cga_out(addr, val, &t3100e->cga);
return;
default:
break;
}
}
uint8_t
t3100e_in(uint16_t addr, void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
uint8_t val;
switch (addr) {
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
if (t3100e->cga.crtcreg == 0x12) {
val = t3100e->attrmap & 0x0F;
if (t3100e->internal)
val |= 0x30; /* Plasma / CRT */
return val;
}
break;
default:
break;
}
return cga_in(addr, &t3100e->cga);
}
void
t3100e_write(uint32_t addr, uint8_t val, void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
t3100e->vram[addr & 0x7fff] = val;
cycles -= 4;
}
uint8_t
t3100e_read(uint32_t addr, void *priv)
{
const t3100e_t *t3100e = (t3100e_t *) priv;
cycles -= 4;
return t3100e->vram[addr & 0x7fff];
}
void
t3100e_recalctimings(t3100e_t *t3100e)
{
double disptime;
double _dispontime;
double _dispofftime;
if (!t3100e->internal) {
cga_recalctimings(&t3100e->cga);
return;
}
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
t3100e->dispontime = (uint64_t) (_dispontime * (cpuclock / VID_CLOCK) * (double) (1ULL << 32));
t3100e->dispofftime = (uint64_t) (_dispofftime * (cpuclock / VID_CLOCK) * (double) (1ULL << 32));
}
/* Draw a row of text in 80-column mode */
void
t3100e_text_row80(t3100e_t *t3100e)
{
uint32_t cols[2];
uint8_t chr;
uint8_t attr;
int drawcursor;
int cursorline;
int bold;
int blink;
uint16_t addr;
uint8_t sc;
uint16_t ma = (t3100e->cga.crtc[13] | (t3100e->cga.crtc[12] << 8)) & 0x7fff;
uint16_t ca = (t3100e->cga.crtc[15] | (t3100e->cga.crtc[14] << 8)) & 0x7fff;
sc = (t3100e->displine) & 15;
addr = ((ma & ~1) + (t3100e->displine >> 4) * 80) * 2;
ma += (t3100e->displine >> 4) * 80;
if ((t3100e->cga.crtc[10] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((t3100e->cga.crtc[10] & 0x0F) * 2 <= sc) && ((t3100e->cga.crtc[11] & 0x0F) * 2 >= sc);
}
for (uint8_t x = 0; x < 80; x++) {
chr = t3100e->vram[(addr + 2 * x) & 0x7FFF];
attr = t3100e->vram[(addr + 2 * x + 1) & 0x7FFF];
drawcursor = ((ma == ca) && cursorline && (t3100e->cga.cgamode & 8) && (t3100e->cga.cgablink & 16));
blink = ((t3100e->cga.cgablink & 16) && (t3100e->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
if (t3100e->video_options & 4)
bold = boldcols[attr] ? chr + 256 : chr;
else
bold = boldcols[attr] ? chr : chr + 256;
bold += 512 * (t3100e->video_options & 3);
if (t3100e->cga.cgamode & 0x20) /* Blink */
{
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
if (blink)
cols[1] = cols[0];
} else {
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
if (drawcursor) {
for (uint8_t c = 0; c < 8; c++) {
(buffer32->line[t3100e->displine])[(x << 3) + c] = cols[(fontdatm[bold][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black);
}
} else {
for (uint8_t c = 0; c < 8; c++)
(buffer32->line[t3100e->displine])[(x << 3) + c] = cols[(fontdatm[bold][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
++ma;
}
}
/* Draw a row of text in 40-column mode */
void
t3100e_text_row40(t3100e_t *t3100e)
{
uint32_t cols[2];
int c;
uint8_t chr;
uint8_t attr;
int drawcursor;
int cursorline;
int bold;
int blink;
uint16_t addr;
uint8_t sc;
uint16_t ma = (t3100e->cga.crtc[13] | (t3100e->cga.crtc[12] << 8)) & 0x7fff;
uint16_t ca = (t3100e->cga.crtc[15] | (t3100e->cga.crtc[14] << 8)) & 0x7fff;
sc = (t3100e->displine) & 15;
addr = ((ma & ~1) + (t3100e->displine >> 4) * 40) * 2;
ma += (t3100e->displine >> 4) * 40;
if ((t3100e->cga.crtc[10] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((t3100e->cga.crtc[10] & 0x0F) * 2 <= sc) && ((t3100e->cga.crtc[11] & 0x0F) * 2 >= sc);
}
for (uint8_t x = 0; x < 40; x++) {
chr = t3100e->vram[(addr + 2 * x) & 0x7FFF];
attr = t3100e->vram[(addr + 2 * x + 1) & 0x7FFF];
drawcursor = ((ma == ca) && cursorline && (t3100e->cga.cgamode & 8) && (t3100e->cga.cgablink & 16));
blink = ((t3100e->cga.cgablink & 16) && (t3100e->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
if (t3100e->video_options & 4)
bold = boldcols[attr] ? chr + 256 : chr;
else
bold = boldcols[attr] ? chr : chr + 256;
bold += 512 * (t3100e->video_options & 3);
if (t3100e->cga.cgamode & 0x20) /* Blink */
{
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
if (blink)
cols[1] = cols[0];
} else {
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
if (drawcursor) {
for (c = 0; c < 8; c++) {
(buffer32->line[t3100e->displine])[(x << 4) + c * 2] = (buffer32->line[t3100e->displine])[(x << 4) + c * 2 + 1] = cols[(fontdatm[bold][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black);
}
} else {
for (c = 0; c < 8; c++) {
(buffer32->line[t3100e->displine])[(x << 4) + c * 2] = (buffer32->line[t3100e->displine])[(x << 4) + c * 2 + 1] = cols[(fontdatm[bold][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
}
++ma;
}
}
/* Draw a line in CGA 640x200 or T3100e 640x400 mode */
void
t3100e_cgaline6(t3100e_t *t3100e)
{
uint8_t dat;
uint32_t ink = 0;
uint16_t addr;
uint32_t fg = (t3100e->cga.cgacol & 0x0F) ? amber : black;
uint32_t bg = black;
uint16_t ma = (t3100e->cga.crtc[13] | (t3100e->cga.crtc[12] << 8)) & 0x7fff;
if (t3100e->cga.crtc[9] == 3) /* 640*400 */
{
addr = ((t3100e->displine) & 1) * 0x2000 + ((t3100e->displine >> 1) & 1) * 0x4000 + (t3100e->displine >> 2) * 80 + ((ma & ~1) << 1);
} else {
addr = ((t3100e->displine >> 1) & 1) * 0x2000 + (t3100e->displine >> 2) * 80 + ((ma & ~1) << 1);
}
for (uint8_t x = 0; x < 80; x++) {
dat = t3100e->vram[addr & 0x7FFF];
addr++;
for (uint8_t c = 0; c < 8; c++) {
ink = (dat & 0x80) ? fg : bg;
if (!(t3100e->cga.cgamode & 8))
ink = black;
(buffer32->line[t3100e->displine])[x * 8 + c] = ink;
dat = dat << 1;
}
}
}
/* Draw a line in CGA 320x200 mode. Here the CGA colours are converted to
* dither patterns: colour 1 to 25% grey, colour 2 to 50% grey */
void
t3100e_cgaline4(t3100e_t *t3100e)
{
uint8_t dat;
uint8_t pattern;
uint32_t ink0 = 0;
uint32_t ink1 = 0;
uint16_t addr;
uint16_t ma = (t3100e->cga.crtc[13] | (t3100e->cga.crtc[12] << 8)) & 0x7fff;
if (t3100e->cga.crtc[9] == 3) /* 320*400 undocumented */
{
addr = ((t3100e->displine) & 1) * 0x2000 + ((t3100e->displine >> 1) & 1) * 0x4000 + (t3100e->displine >> 2) * 80 + ((ma & ~1) << 1);
} else /* 320*200 */
{
addr = ((t3100e->displine >> 1) & 1) * 0x2000 + (t3100e->displine >> 2) * 80 + ((ma & ~1) << 1);
}
for (uint8_t x = 0; x < 80; x++) {
dat = t3100e->vram[addr & 0x7FFF];
addr++;
for (uint8_t c = 0; c < 4; c++) {
pattern = (dat & 0xC0) >> 6;
if (!(t3100e->cga.cgamode & 8))
pattern = 0;
switch (pattern & 3) {
case 0:
ink0 = ink1 = black;
break;
case 1:
if (t3100e->displine & 1) {
ink0 = black;
ink1 = black;
} else {
ink0 = amber;
ink1 = black;
}
break;
case 2:
if (t3100e->displine & 1) {
ink0 = black;
ink1 = amber;
} else {
ink0 = amber;
ink1 = black;
}
break;
case 3:
ink0 = ink1 = amber;
break;
default:
break;
}
(buffer32->line[t3100e->displine])[x * 8 + 2 * c] = ink0;
(buffer32->line[t3100e->displine])[x * 8 + 2 * c + 1] = ink1;
dat = dat << 2;
}
}
}
void
t3100e_poll(void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
if (t3100e->video_options != st_video_options) {
t3100e->video_options = st_video_options;
if (t3100e->video_options & 8) /* Disable internal CGA */
mem_mapping_disable(&t3100e->mapping);
else
mem_mapping_enable(&t3100e->mapping);
/* Set the font used for the external display */
t3100e->cga.fontbase = (512 * (t3100e->video_options & 3))
+ ((t3100e->video_options & 4) ? 256 : 0);
}
/* Switch between internal plasma and external CRT display. */
if (st_display_internal != -1 && st_display_internal != t3100e->internal) {
t3100e->internal = st_display_internal;
t3100e_recalctimings(t3100e);
}
if (!t3100e->internal) {
cga_poll(&t3100e->cga);
return;
}
if (!t3100e->linepos) {
timer_advance_u64(&t3100e->cga.timer, t3100e->dispofftime);
t3100e->cga.cgastat |= 1;
t3100e->linepos = 1;
if (t3100e->dispon) {
if (t3100e->displine == 0) {
video_wait_for_buffer();
}
/* Graphics */
if (t3100e->cga.cgamode & 0x02) {
if (t3100e->cga.cgamode & 0x10)
t3100e_cgaline6(t3100e);
else
t3100e_cgaline4(t3100e);
} else if (t3100e->cga.cgamode & 0x01) /* High-res text */
{
t3100e_text_row80(t3100e);
} else {
t3100e_text_row40(t3100e);
}
}
t3100e->displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (t3100e->displine == 400) /* Start of VSYNC */
{
t3100e->cga.cgastat |= 8;
t3100e->dispon = 0;
}
if (t3100e->displine == 416) /* End of VSYNC */
{
t3100e->displine = 0;
t3100e->cga.cgastat &= ~8;
t3100e->dispon = 1;
}
} else {
if (t3100e->dispon) {
t3100e->cga.cgastat &= ~1;
}
timer_advance_u64(&t3100e->cga.timer, t3100e->dispontime);
t3100e->linepos = 0;
if (t3100e->displine == 400) {
/* Hardcode 640x400 window size */
if ((T3100E_XSIZE != xsize) || (T3100E_YSIZE != ysize) || video_force_resize_get()) {
xsize = T3100E_XSIZE;
ysize = T3100E_YSIZE;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 640x400 resolution */
video_res_x = T3100E_XSIZE;
video_res_y = T3100E_YSIZE;
if (t3100e->cga.cgamode & 0x02) {
if (t3100e->cga.cgamode & 0x10)
video_bpp = 1;
else
video_bpp = 2;
} else
video_bpp = 0;
t3100e->cga.cgablink++;
}
}
}
void
t3100e_recalcattrs(t3100e_t *t3100e)
{
int n;
/* val behaves as follows:
* Bit 0: Attributes 01-06, 08-0E are inverse video
* Bit 1: Attributes 01-06, 08-0E are bold
* Bit 2: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are inverse video
* Bit 3: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are bold */
/* Set up colours */
amber = makecol(0xf7, 0x7C, 0x34);
black = makecol(0x17, 0x0C, 0x00);
/* Initialise the attribute mapping. Start by defaulting everything
* to black on amber, and with bold set by bit 3 */
for (n = 0; n < 256; n++) {
boldcols[n] = (n & 8) != 0;
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
}
/* Colours 0x11-0xFF are controlled by bits 2 and 3 of the
* passed value. Exclude x0 and x8, which are always black on
* amber. */
for (n = 0x11; n <= 0xFF; n++) {
if ((n & 7) == 0)
continue;
if (t3100e->attrmap & 4) /* Inverse */
{
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
} else /* Normal */
{
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
}
if (t3100e->attrmap & 8)
boldcols[n] = 1; /* Bold */
}
/* Set up the 01-0E range, controlled by bits 0 and 1 of the
* passed value. When blinking is enabled this also affects 81-8E. */
for (n = 0x01; n <= 0x0E; n++) {
if (n == 7)
continue;
if (t3100e->attrmap & 1) {
blinkcols[n][0] = normcols[n][0] = amber;
blinkcols[n][1] = normcols[n][1] = black;
blinkcols[n + 128][0] = amber;
blinkcols[n + 128][1] = black;
} else {
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
blinkcols[n + 128][0] = black;
blinkcols[n + 128][1] = amber;
}
if (t3100e->attrmap & 2)
boldcols[n] = 1;
}
/* Colours 07 and 0F are always amber on black. If blinking is
* enabled so are 87 and 8F. */
for (n = 0x07; n <= 0x0F; n += 8) {
blinkcols[n][0] = normcols[n][0] = black;
blinkcols[n][1] = normcols[n][1] = amber;
blinkcols[n + 128][0] = black;
blinkcols[n + 128][1] = amber;
}
/* When not blinking, colours 81-8F are always amber on black. */
for (n = 0x81; n <= 0x8F; n++) {
normcols[n][0] = black;
normcols[n][1] = amber;
boldcols[n] = (n & 0x08) != 0;
}
/* Finally do the ones which are solid black. These differ between
* the normal and blinking mappings */
for (n = 0; n <= 0xFF; n += 0x11) {
normcols[n][0] = normcols[n][1] = black;
}
/* In the blinking range, 00 11 22 .. 77 and 80 91 A2 .. F7 are black */
for (n = 0; n <= 0x77; n += 0x11) {
blinkcols[n][0] = blinkcols[n][1] = black;
blinkcols[n + 128][0] = blinkcols[n + 128][1] = black;
}
}
void *
t3100e_init(UNUSED(const device_t *info))
{
t3100e_t *t3100e = malloc(sizeof(t3100e_t));
memset(t3100e, 0, sizeof(t3100e_t));
loadfont("roms/machines/t3100e/t3100e_font.bin", 5);
cga_init(&t3100e->cga);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_t3100e);
t3100e->internal = 1;
/* 32k video RAM */
t3100e->vram = malloc(0x8000);
timer_set_callback(&t3100e->cga.timer, t3100e_poll);
timer_set_p(&t3100e->cga.timer, t3100e);
/* Occupy memory between 0xB8000 and 0xBFFFF */
mem_mapping_add(&t3100e->mapping, 0xb8000, 0x8000, t3100e_read, NULL, NULL, t3100e_write, NULL, NULL, NULL, 0, t3100e);
/* Respond to CGA I/O ports */
io_sethandler(0x03d0, 0x000c, t3100e_in, NULL, NULL, t3100e_out, NULL, NULL, t3100e);
/* Default attribute mapping is 4 */
t3100e->attrmap = 4;
t3100e_recalcattrs(t3100e);
/* Start off in 80x25 text mode */
t3100e->cga.cgastat = 0xF4;
t3100e->cga.vram = t3100e->vram;
t3100e->enabled = 1;
t3100e->video_options = 0xFF;
return t3100e;
}
void
t3100e_close(void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
free(t3100e->vram);
free(t3100e);
}
void
t3100e_speed_changed(void *priv)
{
t3100e_t *t3100e = (t3100e_t *) priv;
t3100e_recalctimings(t3100e);
}
const device_t t3100e_device = {
.name = "Toshiba T3100e",
.internal_name = "t3100e",
.flags = 0,
.local = 0,
.init = t3100e_init,
.close = t3100e_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = t3100e_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/machine/m_at_t3100e_vid.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,571 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Super Socket 7 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/spd.h>
#include <86box/hwm.h>
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/sound.h>
#include <86box/snd_ac97.h>
#include <86box/clock.h>
int
machine_at_p5a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5a/1011.005",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1541_device);
device_add(&ali1543c_device); /* +0 */
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
device_add(&w83781d_p5a_device); /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
return ret;
}
int
machine_at_m579_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m579/MS6260S_Socket7_ALi_M1542_AMI.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1541_device);
device_add(&ali1543c_device); /* +0 */
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
int
machine_at_gwlucas_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/gwlucas/gw2kboot.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUND, 1, 2, 3, 4); // ES1373
pci_register_slot(0x14, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&ali1541_device);
device_add(&ali1543c_device); /* +0 */
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&cs4297_device);
}
return ret;
}
int
machine_at_5aa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5aa/GA-5AA.F7b",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1541_device);
device_add(&ali1543c_device); /* +0 */
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
int
machine_at_5ax_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5ax/5AX.F4",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1541_device);
device_add(&ali1543c_device); /* +0 */
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
int
machine_at_ax59pro_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ax59pro/AX59P236.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_mvp3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficva503p/je4333.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_39sf010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_ficva503a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficva503a/jn4116.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device);
device_add(&via_vt82c686a_device); /* fans: CPU1, Chassis; temperatures: CPU, System, unused */
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
hwm_values.temperatures[0] += 2; /* CPU offset */
hwm_values.temperatures[1] += 2; /* System offset */
hwm_values.temperatures[2] = 0; /* unused */
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&wm9701a_device); /* on daughtercard */
return ret;
}
int
machine_at_5emapro_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5emapro/5emo1aa2.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device); /* Rebranded as EQ82C6638 */
device_add(&via_vt82c686a_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&via_vt82c686_hwm_device); /* fans: CPU1, Chassis; temperatures: CPU, System, unused */
hwm_values.temperatures[0] += 2; /* CPU offset */
hwm_values.temperatures[1] += 2; /* System offset */
hwm_values.temperatures[2] = 0; /* unused */
return ret;
}
int
machine_at_5sg100_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5sg100/5sg.20g",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x02, PCI_CARD_AGPBRIDGE, 0, 0, 0, 0);
device_add(&sis_5591_1997_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_sockets7.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,467 |
```c
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/port_6x.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/video.h>
#include <86box/machine.h>
typedef struct {
int model;
int cpu_type;
uint8_t ps2_91,
ps2_92,
ps2_94,
ps2_102,
ps2_103,
ps2_104,
ps2_105,
ps2_190;
serial_t *uart;
} ps2_isa_t;
static void
ps2_write(uint16_t port, uint8_t val, void *priv)
{
ps2_isa_t *ps2 = (ps2_isa_t *) priv;
switch (port) {
case 0x0094:
ps2->ps2_94 = val;
break;
case 0x0102:
if (!(ps2->ps2_94 & 0x80)) {
lpt1_remove();
serial_remove(ps2->uart);
if (val & 0x04) {
if (val & 0x08)
serial_setup(ps2->uart, COM1_ADDR, COM1_IRQ);
else
serial_setup(ps2->uart, COM2_ADDR, COM2_IRQ);
}
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
lpt1_init(LPT_MDA_ADDR);
break;
case 1:
lpt1_init(LPT1_ADDR);
break;
case 2:
lpt1_init(LPT2_ADDR);
break;
default:
break;
}
}
ps2->ps2_102 = val;
}
break;
case 0x0103:
ps2->ps2_103 = val;
break;
case 0x0104:
ps2->ps2_104 = val;
break;
case 0x0105:
ps2->ps2_105 = val;
break;
case 0x0190:
ps2->ps2_190 = val;
break;
default:
break;
}
}
static uint8_t
ps2_read(uint16_t port, void *priv)
{
ps2_isa_t *ps2 = (ps2_isa_t *) priv;
uint8_t temp = 0xff;
switch (port) {
case 0x0091:
temp = ps2->ps2_91;
ps2->ps2_91 = 0;
break;
case 0x0094:
temp = ps2->ps2_94;
break;
case 0x0102:
temp = ps2->ps2_102 | 0x08;
break;
case 0x0103:
temp = ps2->ps2_103;
break;
case 0x0104:
temp = ps2->ps2_104;
break;
case 0x0105:
temp = ps2->ps2_105;
break;
case 0x0190:
temp = ps2->ps2_190;
break;
default:
break;
}
return temp;
}
static void
ps2_isa_setup(int model, int cpu_type)
{
ps2_isa_t *ps2;
void *priv;
ps2 = (ps2_isa_t *) malloc(sizeof(ps2_isa_t));
memset(ps2, 0x00, sizeof(ps2_isa_t));
ps2->model = model;
ps2->cpu_type = cpu_type;
io_sethandler(0x0091, 1,
ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2);
io_sethandler(0x0094, 1,
ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2);
io_sethandler(0x0102, 4,
ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2);
io_sethandler(0x0190, 1,
ps2_read, NULL, NULL, ps2_write, NULL, NULL, ps2);
ps2->uart = device_add_inst(&ns16450_device, 1);
lpt1_remove();
lpt1_init(LPT_MDA_ADDR);
device_add(&port_92_device);
mem_remap_top(384);
device_add(&ps_nvr_device);
device_add(&fdc_at_ps1_device);
/* Enable the builtin HDC. */
if (hdc_current[0] == HDC_INTERNAL) {
priv = device_add(&ps1_hdc_device);
ps1_hdc_inform(priv, &ps2->ps2_91);
}
device_add(&ps1vga_device);
}
static void
ps2_isa_common_init(const machine_t *model)
{
machine_common_init(model);
refresh_at_enable = 1;
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_at);
dma16_init();
pic2_init();
device_add(&keyboard_ps2_device);
device_add(&port_6x_ps2_device);
}
int
machine_ps2_m30_286_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ibmps2_m30_286/33f5381a.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
ps2_isa_common_init(model);
ps2_isa_setup(30, 286);
return ret;
}
``` | /content/code_sandbox/src/machine/m_ps2_isa.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,426 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Philips XT-compatible machines.
*
*
*
* Authors: EngiNerd <webmaster.crrc@yahoo.it>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/nmi.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/gameport.h>
#include <86box/ibm_5161.h>
#include <86box/keyboard.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/io.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
typedef struct philips_t {
uint8_t reg;
} philips_t;
#ifdef ENABLE_PHILIPS_LOG
int philips_do_log = ENABLE_PHILIPS_LOG;
static void
philips_log(const char *fmt, ...)
{
va_list ap;
if (philips_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define philips_log(fmt, ...)
#endif
static void
philips_write(uint16_t port, uint8_t val, void *priv)
{
philips_t *dev = (philips_t *) priv;
switch (port) {
/* port 0xc0
* bit 7: turbo
* bits 4-5: rtc read/set (I2C Bus SDA/SCL?)
* bit 2: parity disabled
*/
case 0xc0:
dev->reg = val;
if (val & 0x80)
cpu_dynamic_switch(cpu);
else
cpu_dynamic_switch(0);
break;
default:
break;
}
philips_log("Philips XT Mainboard: Write %02x at %02x\n", val, port);
}
static uint8_t
philips_read(uint16_t port, void *priv)
{
const philips_t *dev = (philips_t *) priv;
uint8_t ret = 0xff;
switch (port) {
/* port 0xc0
* bit 7: turbo
* bits 4-5: rtc read/set
* bit 2: parity disabled
*/
case 0xc0:
ret = dev->reg;
break;
default:
break;
}
philips_log("Philips XT Mainboard: Read %02x at %02x\n", ret, port);
return ret;
}
static void
philips_close(void *priv)
{
philips_t *dev = (philips_t *) priv;
free(dev);
}
static void *
philips_init(UNUSED(const device_t *info))
{
philips_t *dev = (philips_t *) malloc(sizeof(philips_t));
memset(dev, 0, sizeof(philips_t));
dev->reg = 0x40;
io_sethandler(0x0c0, 0x01, philips_read, NULL, NULL, philips_write, NULL, NULL, dev);
return dev;
}
const device_t philips_device = {
.name = "Philips XT Mainboard",
.internal_name = "philips",
.flags = 0,
.local = 0,
.init = philips_init,
.close = philips_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
void
machine_xt_philips_common_init(const machine_t *model)
{
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
nmi_init();
standalone_gameport_type = &gameport_device;
device_add(&keyboard_pc_device);
device_add(&philips_device);
device_add(&xta_hd20_device);
}
int
machine_xt_p3105_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p3105/philipsnms9100.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
machine_xt_philips_common_init(model);
/* On-board FDC cannot be disabled */
device_add(&fdc_xt_device);
return ret;
}
int
machine_xt_p3120_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p3120/philips_p3120.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
machine_xt_philips_common_init(model);
device_add(&gc100a_device);
device_add(&fdc_at_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_philips.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,230 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 7 (Dual Voltage) machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/sound.h>
#include <86box/hwm.h>
#include <86box/video.h>
#include <86box/spd.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/thread.h>
#include <86box/network.h>
int
machine_at_acerv35n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerv35n/v35nd1s1.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
/* Yes, it's called amstrad_mega_pc_nvr_device, but it's basically the
standard AT NVR, just initialized to 0x00's (perhaps that should be the
default behavior?). */
device_add(&amstrad_megapc_nvr_device);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ap5vm_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap5vm/AP5V270.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
/* It seems there were plans for an on-board NCR 53C810 according to some clues
left in the manual, but were latter scrapped. The BIOS still support that
PCI device, though, so why not. */
pci_register_slot(0x06, PCI_CARD_SCSI, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&ncr53c810_onboard_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2p4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p55t2p4/0207_j2.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_m7shi_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m7shi/m7shi2n.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c935_device);
device_add(&intel_flash_bxt_device);
return ret;
}
/* The Sony VAIO is an AG430HX, I'm assuming it has the same configuration bits
as the TC430HX, hence the #define. */
#define machine_at_ag430hx_gpio_init machine_at_tc430hx_gpio_init
/* The PB680 is a NV430VX, I'm assuming it has the same configuration bits as
the TC430HX, hence the #define. */
#define machine_at_nv430vx_gpio_init machine_at_tc430hx_gpio_init
static void
machine_at_tc430hx_gpio_init(void)
{
uint32_t gpio = 0xffffe1ff;
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
/* Bit 1: 0 = Soft-off capable power supply present, 1 = Soft-off capable power supply absent. */
/* Bit 0: 0 = Reserved. */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff10ff;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff18ff;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff00ff;
machine_set_gpio_default(gpio);
}
int
machine_at_tc430hx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/tc430hx/1007DH0_.BIO",
"roms/machines/tc430hx/1007DH0_.BI1",
"roms/machines/tc430hx/1007DH0_.BI2",
"roms/machines/tc430hx/1007DH0_.BI3",
"roms/machines/tc430hx/1007DH0_.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_tc430hx_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_infinia7200_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/infinia7200/1008DH08.BIO",
"roms/machines/infinia7200/1008DH08.BI1",
"roms/machines/infinia7200/1008DH08.BI2",
"roms/machines/infinia7200/1008DH08.BI3",
"roms/machines/infinia7200/1008DH08.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_tc430hx_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
static void
machine_at_cu430hx_gpio_init(void)
{
uint32_t gpio = 0xffffe1ff;
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
/* Bit 1: 0 = Soft-off capable power supply present, 1 = Soft-off capable power supply absent. */
/* Bit 0: 0 = Reserved. */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff10ff;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff18ff;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff00ff;
if ((sound_card_current[0] == SOUND_INTERNAL) && machine_get_snd_device(machine)->available())
gpio |= 0xffff04ff;
machine_set_gpio_default(gpio);
}
static void
machine_at_cu430hx_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 2);
machine_at_cu430hx_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0); // ATI VGA Graphics
pci_register_slot(0x0C, PCI_CARD_NETWORK, 4, 0, 0, 0); // Intel 82557 Ethernet Network
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 0, 0, 0); // riser
if ((sound_card_current[0] == SOUND_INTERNAL) && machine_get_snd_device(machine)->available())
machine_snd = device_add(machine_get_snd_device(machine));
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
int
machine_at_cu430hx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/cu430hx/1006DK0_.BIO",
"roms/machines/cu430hx/1006DK0_.BI1",
"roms/machines/cu430hx/1006DK0_.BI2",
"roms/machines/cu430hx/1006DK0_.BI3",
"roms/machines/cu430hx/1006DK0_.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_cu430hx_common_init(model);
return ret;
}
int
machine_at_equium5200_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/equium5200/1003DK08.BIO",
"roms/machines/equium5200/1003DK08.BI1",
"roms/machines/equium5200/1003DK08.BI2",
"roms/machines/equium5200/1003DK08.BI3",
"roms/machines/equium5200/1003DK08.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_cu430hx_common_init(model);
return ret;
}
int
machine_at_pcv90_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/pcv90/1010DD04.BIO",
"roms/machines/pcv90/1010DD04.BI1",
"roms/machines/pcv90/1010DD04.BI2",
"roms/machines/pcv90/1010DD04.BI3",
"roms/machines/pcv90/1010DD04.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_ag430hx_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p65up5_cp55t2d_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p65up5/TD5I0201.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_p65up5_common_init(model, &i430hx_device);
return ret;
}
int
machine_at_epc2102_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/epc2102/P5000HX.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add_params(&at_nvr_device, (void *) 0x20);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i82091aa_device);
device_add(&sst_flash_39sf010_device);
return ret;
}
int
machine_at_p55tvp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p55tvp4/0204_128.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device); // It uses the AMIKEY KBC
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_5ivg_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5ivg/5IVG.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&prime3c_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_8500tvxa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/8500tvxa/tvx0619b.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 3, 2, 1);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_presario2240_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/presario2240/B0184008.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_NO_BRIDGES);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
if (gfxcard[0] == VID_INTERNAL)
device_add(&s3_trio64v2_dx_onboard_pci_device);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c932qf_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_presario4500_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/presario4500/B013300I.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_NO_BRIDGES);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
if (gfxcard[0] == VID_INTERNAL)
device_add(&s3_trio64v2_dx_onboard_pci_device);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c931apm_compaq_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_dellhannibalp_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/dellhannibalp/1003DY0J.BIO",
"roms/machines/dellhannibalp/1003DY0J.BI1",
"roms/machines/dellhannibalp/1003DY0J.BI2",
"roms/machines/dellhannibalp/1003DY0J.BI3",
"roms/machines/dellhannibalp/1003DY0J.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p55va_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p55va/va021297.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_brio80xx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/brio80xx/Hf0705.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c935_370_device);
device_add(&sst_flash_29ee020_device);
return ret;
}
int
machine_at_pb680_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/pb680/1012DN0R.BIO",
"roms/machines/pb680/1012DN0R.BI1",
"roms/machines/pb680/1012DN0R.BI2",
"roms/machines/pb680/1012DN0R.BI3",
"roms/machines/pb680/1012DN0R.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_nv430vx_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_pb810_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pb810/G400125I.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x0b, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cs4237b_device);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c935_370_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_mb520n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mb520n/520n503s.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_i430vx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/430vx/55XWUQ0E.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_ma23c_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ma23c/BIOS.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_VIDEO, 3, 4, 1, 2);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&nec_mate_unk_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c67x_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_nupro592_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/nupro592/np590b10.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0B, PCI_CARD_VIDEO, 3, 4, 1, 2); /* C&T B69000 */
pci_register_slot(0x0C, PCI_CARD_NETWORK, 4, 1, 2, 3); /* Intel 82559 */
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4); /* PIIX4 */
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
device_add(&w83781d_device); /* fans: CPU1, unused, unused; temperatures: System, CPU1, unused */
hwm_values.temperatures[2] = 0; /* unused */
hwm_values.fans[1] = 0; /* unused */
hwm_values.fans[2] = 0; /* unused */
/* -5V is not reported by the BIOS, but leave it set */
return ret;
}
int
machine_at_tx97_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tx97/0112.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877tf_acorp_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
device_add(&w83781d_device); /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
hwm_values.temperatures[1] = 0; /* unused */
/* CPU offset */
if (hwm_values.temperatures[2] < 32) /* prevent underflow */
hwm_values.temperatures[2] = 0;
else
hwm_values.temperatures[2] -= 32;
return ret;
}
#ifdef USE_AN430TX
int
machine_at_an430tx_init(const machine_t *model)
{
int ret;
# if 1
ret = bios_load_linear_combined2("roms/machines/an430tx/P10-0095.BIO",
"roms/machines/an430tx/P10-0095.BI1",
"roms/machines/an430tx/P10-0095.BI2",
"roms/machines/an430tx/P10-0095.BI3",
"roms/machines/an430tx/P10-0095.RCV",
0x3a000, 160);
# else
ret = bios_load_linear_combined2("roms/machines/an430tx/P06-0062.BIO",
"roms/machines/an430tx/P06-0062.BI1",
"roms/machines/an430tx/P06-0062.BI2",
"roms/machines/an430tx/P06-0062.BI3",
"roms/machines/an430tx/P10-0095.RCV",
0x3a000, 160);
# endif
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
// pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87307_both_device);
device_add(&intel_flash_bxt_ami_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
#endif /* USE_AN430TX */
int
machine_at_ym430tx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ym430tx/YM430TX.003",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977tf_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_mb540n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mb540n/Tx0720ug.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&um8669f_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_56a5_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/56a5/54p5b6b.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_p5mms98_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5mms98/s981182.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
device_add(&lm78_device); /* fans: Thermal, CPU, Chassis; temperature: unused */
device_add(&lm75_1_4a_device); /* temperature: CPU */
return ret;
}
int
machine_at_richmond_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/richmond/RICHMOND.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&it8671f_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
device_add(&lm78_device); /* fans: Thermal, CPU, Chassis; temperature: unused */
device_add(&lm75_1_4a_device); /* temperature: CPU */
return ret;
}
int
machine_at_tomahawk_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/tomahawk/0AAGT046.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NETWORK, 4, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&fdc37c67x_device);
device_add(&amd_flash_29f020a_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
device_add(&lm78_device); /* fans: Thermal, CPU, Chassis; temperature: unused */
device_add(&lm75_1_4a_device); /* temperature: CPU */
if ((gfxcard[0] == VID_INTERNAL) && machine_get_vid_device(machine))
device_add(machine_get_vid_device(machine));
if ((sound_card_current[0] == SOUND_INTERNAL) && machine_get_snd_device(machine))
device_add(machine_get_snd_device(machine));
if ((net_cards_conf[0].device_num == NET_INTERNAL) && machine_get_net_device(machine))
device_add(machine_get_net_device(machine));
return ret;
}
int
machine_at_ficva502_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficva502/VA502bp.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&via_vpx_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c669_370_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_ficpa2012_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficpa2012/113jb16.awd",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_vp3_device);
device_add(&via_vt82c586b_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
int
machine_at_r534f_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/r534f/r534f008.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_5571_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ms5146_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5146/A546MS11.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_5571_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_cb52xsi_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cb52xsi/CD5205S.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_5571_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_370_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_sp97xv_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sp97xv/0109XVJ2.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x13, PCI_CARD_VIDEO, 1, 2, 3, 4); /* On-chip SiS graphics, absent here. */
device_add(&sis_5581_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_sq578_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sq578/578b03.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&sis_5581_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ms5172_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5172/A572MS15.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_AGPBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&sis_5591_1997_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_m560_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m560/5600410s.ami",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&ali1531_device);
device_add(&ali1543_device); /* -5 */
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_ms5164_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5164/W564MS43.005",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_SOUTHBRIDGE_IDE, 5, 6, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1531_device);
device_add(&ali1543_device); /* -5 */
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_thunderbolt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/thunderbolt/tbolt-01.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 1, 2, 3); /* PIIX4 */
pci_register_slot(0x11, PCI_CARD_NORMAL, 0, 1, 2, 3);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 0, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 0, 1, 2);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&fdc37c935_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket7.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 16,720 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Toshiba T1000 plasma display, which
* has a fixed resolution of 640x200 pixels.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include "cpu.h"
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/m_xt_t1000.h>
#include <86box/plat_unused.h>
#define T1000_XSIZE 640
#define T1000_YSIZE 200
/* Mapping of attributes to colours */
static uint32_t blue;
static uint32_t grey;
static uint8_t boldcols[256]; /* Which attributes use the bold font */
static uint32_t blinkcols[256][2];
static uint32_t normcols[256][2];
static uint8_t language;
static video_timings_t timing_t1000 = { VIDEO_ISA, 8, 16, 32, 8, 16, 32 };
/* Video options set by the motherboard; they will be picked up by the card
* on the next poll.
*
* Bit 1: Danish
* Bit 0: Thin font
*/
static uint8_t st_video_options;
static uint8_t st_enabled = 1;
static int8_t st_display_internal = -1;
void
t1000_video_options_set(uint8_t options)
{
st_video_options = options & 1;
st_video_options |= language;
}
void
t1000_video_enable(uint8_t enabled)
{
st_enabled = enabled;
}
void
t1000_display_set(uint8_t internal)
{
st_display_internal = (int8_t) internal;
}
uint8_t
t1000_display_get(void)
{
return (uint8_t) st_display_internal;
}
typedef struct t1000_t {
mem_mapping_t mapping;
cga_t cga; /* The CGA is used for the external
* display; most of its registers are
* ignored by the plasma display. */
int font; /* Current font, 0-3 */
int enabled; /* Hardware enabled, 0 or 1 */
int internal; /* Using internal display? */
uint8_t attrmap; /* Attribute mapping register */
uint64_t dispontime, dispofftime;
int linepos, displine;
int vc;
int dispon;
int vsynctime;
uint8_t video_options;
uint8_t backlight, invert;
uint8_t *vram;
} t1000_t;
static void t1000_recalctimings(t1000_t *t1000);
static void t1000_write(uint32_t addr, uint8_t val, void *priv);
static uint8_t t1000_read(uint32_t addr, void *priv);
static void t1000_recalcattrs(t1000_t *t1000);
static void
t1000_out(uint16_t addr, uint8_t val, void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
switch (addr) {
/* Emulated CRTC, register select */
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
cga_out(addr, val, &t1000->cga);
break;
/* Emulated CRTC, value */
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
/* Register 0x12 controls the attribute mappings for the
* LCD screen. */
if (t1000->cga.crtcreg == 0x12) {
t1000->attrmap = val;
t1000_recalcattrs(t1000);
return;
}
cga_out(addr, val, &t1000->cga);
t1000_recalctimings(t1000);
return;
case 0x3D8: /* CGA control register */
case 0x3D9: /* CGA colour register */
cga_out(addr, val, &t1000->cga);
return;
default:
break;
}
}
static uint8_t
t1000_in(uint16_t addr, void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
uint8_t val;
switch (addr) {
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
if (t1000->cga.crtcreg == 0x12) {
val = t1000->attrmap & 0x0F;
if (t1000->internal)
val |= 0x20; /* LCD / CRT */
return val;
}
break;
default:
break;
}
return cga_in(addr, &t1000->cga);
}
static void
t1000_write(uint32_t addr, uint8_t val, void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
t1000->vram[addr & 0x3fff] = val;
cycles -= 4;
}
static uint8_t
t1000_read(uint32_t addr, void *priv)
{
const t1000_t *t1000 = (t1000_t *) priv;
cycles -= 4;
return t1000->vram[addr & 0x3fff];
}
static void
t1000_recalctimings(t1000_t *t1000)
{
double disptime;
double _dispontime;
double _dispofftime;
if (!t1000->internal) {
cga_recalctimings(&t1000->cga);
return;
}
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
t1000->dispontime = (uint64_t) (_dispontime * xt_cpu_multi);
t1000->dispofftime = (uint64_t) (_dispofftime * xt_cpu_multi);
}
/* Draw a row of text in 80-column mode */
static void
t1000_text_row80(t1000_t *t1000)
{
uint32_t cols[2];
uint8_t chr;
uint8_t attr;
int drawcursor;
int cursorline;
int bold;
int blink;
uint16_t addr;
uint8_t sc;
uint16_t ma = (t1000->cga.crtc[13] | (t1000->cga.crtc[12] << 8)) & 0x3fff;
uint16_t ca = (t1000->cga.crtc[15] | (t1000->cga.crtc[14] << 8)) & 0x3fff;
sc = (t1000->displine) & 7;
addr = ((ma & ~1) + (t1000->displine >> 3) * 80) * 2;
ma += (t1000->displine >> 3) * 80;
if ((t1000->cga.crtc[10] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((t1000->cga.crtc[10] & 0x0F) <= sc) && ((t1000->cga.crtc[11] & 0x0F) >= sc);
}
for (uint8_t x = 0; x < 80; x++) {
chr = t1000->vram[(addr + 2 * x) & 0x3FFF];
attr = t1000->vram[(addr + 2 * x + 1) & 0x3FFF];
drawcursor = ((ma == ca) && cursorline && (t1000->cga.cgamode & 8) && (t1000->cga.cgablink & 16));
blink = ((t1000->cga.cgablink & 16) && (t1000->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
if (t1000->video_options & 1)
bold = boldcols[attr] ? chr : chr + 256;
else
bold = boldcols[attr] ? chr + 256 : chr;
if (t1000->video_options & 2)
bold += 512;
if (t1000->cga.cgamode & 0x20) /* Blink */
{
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
if (blink)
cols[1] = cols[0];
} else {
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
if (drawcursor) {
for (uint8_t c = 0; c < 8; c++) {
(buffer32->line[t1000->displine])[(x << 3) + c] = cols[(fontdat[bold][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (blue ^ grey);
}
} else {
for (uint8_t c = 0; c < 8; c++)
(buffer32->line[t1000->displine])[(x << 3) + c] = cols[(fontdat[bold][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
++ma;
}
}
/* Draw a row of text in 40-column mode */
static void
t1000_text_row40(t1000_t *t1000)
{
uint32_t cols[2];
uint8_t chr;
uint8_t attr;
int drawcursor;
int cursorline;
int bold;
int blink;
uint16_t addr;
uint8_t sc;
uint16_t ma = (t1000->cga.crtc[13] | (t1000->cga.crtc[12] << 8)) & 0x3fff;
uint16_t ca = (t1000->cga.crtc[15] | (t1000->cga.crtc[14] << 8)) & 0x3fff;
sc = (t1000->displine) & 7;
addr = ((ma & ~1) + (t1000->displine >> 3) * 40) * 2;
ma += (t1000->displine >> 3) * 40;
if ((t1000->cga.crtc[10] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((t1000->cga.crtc[10] & 0x0F) <= sc) && ((t1000->cga.crtc[11] & 0x0F) >= sc);
}
for (uint8_t x = 0; x < 40; x++) {
chr = t1000->vram[(addr + 2 * x) & 0x3FFF];
attr = t1000->vram[(addr + 2 * x + 1) & 0x3FFF];
drawcursor = ((ma == ca) && cursorline && (t1000->cga.cgamode & 8) && (t1000->cga.cgablink & 16));
blink = ((t1000->cga.cgablink & 16) && (t1000->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
if (t1000->video_options & 1)
bold = boldcols[attr] ? chr : chr + 256;
else
bold = boldcols[attr] ? chr + 256 : chr;
if (t1000->video_options & 2)
bold += 512;
if (t1000->cga.cgamode & 0x20) /* Blink */
{
cols[1] = blinkcols[attr][1];
cols[0] = blinkcols[attr][0];
if (blink)
cols[1] = cols[0];
} else {
cols[1] = normcols[attr][1];
cols[0] = normcols[attr][0];
}
if (drawcursor) {
for (uint8_t c = 0; c < 8; c++) {
(buffer32->line[t1000->displine])[(x << 4) + c * 2] = (buffer32->line[t1000->displine])[(x << 4) + c * 2 + 1] = cols[(fontdat[bold][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (blue ^ grey);
}
} else {
for (uint8_t c = 0; c < 8; c++) {
(buffer32->line[t1000->displine])[(x << 4) + c * 2] = (buffer32->line[t1000->displine])[(x << 4) + c * 2 + 1] = cols[(fontdat[bold][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
}
++ma;
}
}
/* Draw a line in CGA 640x200 mode */
static void
t1000_cgaline6(t1000_t *t1000)
{
uint8_t dat;
uint32_t ink = 0;
uint16_t addr;
uint32_t fg = (t1000->cga.cgacol & 0x0F) ? blue : grey;
uint32_t bg = grey;
uint16_t ma = (t1000->cga.crtc[13] | (t1000->cga.crtc[12] << 8)) & 0x3fff;
addr = ((t1000->displine) & 1) * 0x2000 + (t1000->displine >> 1) * 80 + ((ma & ~1) << 1);
for (uint8_t x = 0; x < 80; x++) {
dat = t1000->vram[addr & 0x3FFF];
addr++;
for (uint8_t c = 0; c < 8; c++) {
ink = (dat & 0x80) ? fg : bg;
if (!(t1000->cga.cgamode & 8))
ink = grey;
(buffer32->line[t1000->displine])[x * 8 + c] = ink;
dat = dat << 1;
}
}
}
/* Draw a line in CGA 320x200 mode. Here the CGA colours are converted to
* dither patterns: colour 1 to 25% grey, colour 2 to 50% grey */
static void
t1000_cgaline4(t1000_t *t1000)
{
uint8_t dat;
uint8_t pattern;
uint32_t ink0;
uint32_t ink1;
uint16_t addr;
uint16_t ma = (t1000->cga.crtc[13] | (t1000->cga.crtc[12] << 8)) & 0x3fff;
addr = ((t1000->displine) & 1) * 0x2000 + (t1000->displine >> 1) * 80 + ((ma & ~1) << 1);
for (uint8_t x = 0; x < 80; x++) {
dat = t1000->vram[addr & 0x3FFF];
addr++;
for (uint8_t c = 0; c < 4; c++) {
pattern = (dat & 0xC0) >> 6;
if (!(t1000->cga.cgamode & 8))
pattern = 0;
switch (pattern & 3) {
default:
case 0:
ink0 = ink1 = grey;
break;
case 1:
if (t1000->displine & 1) {
ink0 = grey;
ink1 = grey;
} else {
ink0 = blue;
ink1 = grey;
}
break;
case 2:
if (t1000->displine & 1) {
ink0 = grey;
ink1 = blue;
} else {
ink0 = blue;
ink1 = grey;
}
break;
case 3:
ink0 = ink1 = blue;
break;
}
(buffer32->line[t1000->displine])[x * 8 + 2 * c] = ink0;
(buffer32->line[t1000->displine])[x * 8 + 2 * c + 1] = ink1;
dat = dat << 2;
}
}
}
static void
t1000_poll(void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
if (t1000->video_options != st_video_options || t1000->enabled != st_enabled) {
t1000->video_options = st_video_options;
t1000->enabled = st_enabled;
/* Set the font used for the external display */
t1000->cga.fontbase = ((t1000->video_options & 3) * 256);
if (t1000->enabled) /* Disable internal chipset */
mem_mapping_enable(&t1000->mapping);
else
mem_mapping_disable(&t1000->mapping);
}
/* Switch between internal plasma and external CRT display. */
if (st_display_internal != -1 && st_display_internal != t1000->internal) {
t1000->internal = st_display_internal;
t1000_recalctimings(t1000);
}
if (!t1000->internal) {
cga_poll(&t1000->cga);
return;
}
if (!t1000->linepos) {
timer_advance_u64(&t1000->cga.timer, t1000->dispofftime);
t1000->cga.cgastat |= 1;
t1000->linepos = 1;
if (t1000->dispon) {
if (t1000->displine == 0) {
video_wait_for_buffer();
}
/* Graphics */
if (t1000->cga.cgamode & 0x02) {
if (t1000->cga.cgamode & 0x10)
t1000_cgaline6(t1000);
else
t1000_cgaline4(t1000);
} else if (t1000->cga.cgamode & 0x01) /* High-res text */
{
t1000_text_row80(t1000);
} else {
t1000_text_row40(t1000);
}
}
t1000->displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (t1000->displine == 200) /* Start of VSYNC */
{
t1000->cga.cgastat |= 8;
t1000->dispon = 0;
}
if (t1000->displine == 216) /* End of VSYNC */
{
t1000->displine = 0;
t1000->cga.cgastat &= ~8;
t1000->dispon = 1;
}
} else {
if (t1000->dispon) {
t1000->cga.cgastat &= ~1;
}
timer_advance_u64(&t1000->cga.timer, t1000->dispontime);
t1000->linepos = 0;
if (t1000->displine == 200) {
/* Hardcode 640x200 window size */
if ((T1000_XSIZE != xsize) || (T1000_YSIZE != ysize) || video_force_resize_get()) {
xsize = T1000_XSIZE;
ysize = T1000_YSIZE;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 640x200 resolution */
video_res_x = T1000_XSIZE;
video_res_y = T1000_YSIZE;
if (t1000->cga.cgamode & 0x02) {
if (t1000->cga.cgamode & 0x10)
video_bpp = 1;
else
video_bpp = 2;
} else
video_bpp = 0;
t1000->cga.cgablink++;
}
}
}
static void
t1000_recalcattrs(t1000_t *t1000)
{
int n;
/* val behaves as follows:
* Bit 0: Attributes 01-06, 08-0E are inverse video
* Bit 1: Attributes 01-06, 08-0E are bold
* Bit 2: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are inverse video
* Bit 3: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF
* are bold */
/* Set up colours */
if (t1000->invert) {
if (t1000->backlight) {
grey = makecol(0x2D, 0x39, 0x5A);
blue = makecol(0x85, 0xa0, 0xD6);
} else {
grey = makecol(0x0f, 0x21, 0x3f);
blue = makecol(0x1C, 0x71, 0x31);
}
} else {
if (t1000->backlight) {
blue = makecol(0x2D, 0x39, 0x5A);
grey = makecol(0x85, 0xa0, 0xD6);
} else {
blue = makecol(0x0f, 0x21, 0x3f);
grey = makecol(0x1C, 0x71, 0x31);
}
}
/* Initialise the attribute mapping. Start by defaulting everything
* to grey on blue, and with bold set by bit 3 */
for (n = 0; n < 256; n++) {
boldcols[n] = (n & 8) != 0;
blinkcols[n][0] = normcols[n][0] = blue;
blinkcols[n][1] = normcols[n][1] = grey;
}
/* Colours 0x11-0xFF are controlled by bits 2 and 3 of the
* passed value. Exclude x0 and x8, which are always grey on
* blue. */
for (n = 0x11; n <= 0xFF; n++) {
if ((n & 7) == 0)
continue;
if (t1000->attrmap & 4) /* Inverse */
{
blinkcols[n][0] = normcols[n][0] = blue;
blinkcols[n][1] = normcols[n][1] = grey;
} else /* Normal */
{
blinkcols[n][0] = normcols[n][0] = grey;
blinkcols[n][1] = normcols[n][1] = blue;
}
if (t1000->attrmap & 8)
boldcols[n] = 1; /* Bold */
}
/* Set up the 01-0E range, controlled by bits 0 and 1 of the
* passed value. When blinking is enabled this also affects 81-8E. */
for (n = 0x01; n <= 0x0E; n++) {
if (n == 7)
continue;
if (t1000->attrmap & 1) {
blinkcols[n][0] = normcols[n][0] = blue;
blinkcols[n][1] = normcols[n][1] = grey;
blinkcols[n + 128][0] = blue;
blinkcols[n + 128][1] = grey;
} else {
blinkcols[n][0] = normcols[n][0] = grey;
blinkcols[n][1] = normcols[n][1] = blue;
blinkcols[n + 128][0] = grey;
blinkcols[n + 128][1] = blue;
}
if (t1000->attrmap & 2)
boldcols[n] = 1;
}
/* Colours 07 and 0F are always blue on grey. If blinking is
* enabled so are 87 and 8F. */
for (n = 0x07; n <= 0x0F; n += 8) {
blinkcols[n][0] = normcols[n][0] = grey;
blinkcols[n][1] = normcols[n][1] = blue;
blinkcols[n + 128][0] = grey;
blinkcols[n + 128][1] = blue;
}
/* When not blinking, colours 81-8F are always blue on grey. */
for (n = 0x81; n <= 0x8F; n++) {
normcols[n][0] = grey;
normcols[n][1] = blue;
boldcols[n] = (n & 0x08) != 0;
}
/* Finally do the ones which are solid grey. These differ between
* the normal and blinking mappings */
for (n = 0; n <= 0xFF; n += 0x11) {
normcols[n][0] = normcols[n][1] = grey;
}
/* In the blinking range, 00 11 22 .. 77 and 80 91 A2 .. F7 are grey */
for (n = 0; n <= 0x77; n += 0x11) {
blinkcols[n][0] = blinkcols[n][1] = grey;
blinkcols[n + 128][0] = blinkcols[n + 128][1] = grey;
}
}
static void *
t1000_init(UNUSED(const device_t *info))
{
t1000_t *t1000 = malloc(sizeof(t1000_t));
memset(t1000, 0, sizeof(t1000_t));
loadfont("roms/machines/t1000/t1000font.bin", 8);
cga_init(&t1000->cga);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_t1000);
t1000->internal = 1;
t1000->backlight = device_get_config_int("backlight");
t1000->invert = device_get_config_int("invert");
/* 16k video RAM */
t1000->vram = malloc(0x4000);
timer_set_callback(&t1000->cga.timer, t1000_poll);
timer_set_p(&t1000->cga.timer, t1000);
/* Occupy memory between 0xB8000 and 0xBFFFF */
mem_mapping_add(&t1000->mapping, 0xb8000, 0x8000, t1000_read, NULL, NULL, t1000_write, NULL, NULL, NULL, 0, t1000);
/* Respond to CGA I/O ports */
io_sethandler(0x03d0, 0x000c, t1000_in, NULL, NULL, t1000_out, NULL, NULL, t1000);
/* Default attribute mapping is 4 */
t1000->attrmap = 4;
t1000_recalcattrs(t1000);
/* Start off in 80x25 text mode */
t1000->cga.cgastat = 0xF4;
t1000->cga.vram = t1000->vram;
t1000->enabled = 1;
t1000->video_options = 0x01;
language = device_get_config_int("display_language") ? 2 : 0;
return t1000;
}
static void
t1000_close(void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
free(t1000->vram);
free(t1000);
}
static void
t1000_speed_changed(void *priv)
{
t1000_t *t1000 = (t1000_t *) priv;
t1000_recalctimings(t1000);
}
static const device_config_t t1000_config[] = {
// clang-format off
{
.name = "display_language",
.description = "Language",
.type = CONFIG_SELECTION,
.selection = {
{ .description = "USA", .value = 0 },
{ .description = "Danish", .value = 1 }
},
.default_int = 0
},
{
.name = "backlight",
.description = "Enable backlight",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{
.name = "invert",
.description = "Invert colors",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 0
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t t1000_video_device = {
.name = "Toshiba T1000 Video",
.internal_name = "t1000_video",
.flags = 0,
.local = 0,
.init = t1000_init,
.close = t1000_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = t1000_speed_changed,
.force_redraw = NULL,
.config = t1000_config
};
const device_t t1200_video_device = {
.name = "Toshiba T1200 Video",
.internal_name = "t1200_video",
.flags = 0,
.local = 0,
.init = t1000_init,
.close = t1000_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = t1000_speed_changed,
.force_redraw = NULL,
.config = t1000_config
};
``` | /content/code_sandbox/src/machine/m_xt_t1000_vid.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,368 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 7 (Single Voltage) machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/video.h>
#include <86box/spd.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/nvr.h>
#include <86box/plat_unused.h>
#include <86box/sound.h>
static void
machine_at_thor_gpio_init(void)
{
uint32_t gpio = 0xffffe1cf;
/* Register 0x0078 (Undocumented): */
/* Bit 5: 0 = Multiplier. */
/* Bit 4: 0 = Multiplier. */
/* 1.5: 0, 0. */
/* 3.0: 0, 1. */
/* 2.0: 1, 0. */
/* 2.5: 1, 1. */
/* Bit 1: 0 = Error beep, 1 = No error. */
if (cpu_dmulti <= 1.5)
gpio |= 0xffff0000;
else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
gpio |= 0xffff0020;
else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
gpio |= 0xffff0030;
else if (cpu_dmulti > 2.5)
gpio |= 0xffff0010;
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
/* Bit 1: 0 = Soft-off capable power supply present, 1 = Soft-off capable power supply absent. */
/* Bit 0: 0 = Reserved. */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff0000;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff0800;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff1000;
machine_set_gpio_default(gpio);
}
static void
machine_at_thor_common_init(const machine_t *model, int has_video)
{
machine_at_common_init_ex(model, 2);
machine_at_thor_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (has_video && (gfxcard[0] == VID_INTERNAL))
device_add(machine_get_vid_device(machine));
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
static void
machine_at_p54tp4xe_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_p54tp4xe_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54tp4xe/t15i0302.awd",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_p54tp4xe_common_init(model);
return ret;
}
int
machine_at_p54tp4xe_mr_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p54tp4xe/TRITON.BIO",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_p54tp4xe_common_init(model);
return ret;
}
int
machine_at_exp8551_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/exp8551/AMI20.BIO",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_gw2katx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/gw2katx/1003CN0T.BIO",
"roms/machines/gw2katx/1003CN0T.BI1",
0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 0);
return ret;
}
int
machine_at_thor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/thor/1006cn0_.bio",
"roms/machines/thor/1006cn0_.bi1",
0x20000, 128);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 1);
return ret;
}
int
machine_at_mrthor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mrthor/mr_atx.bio",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_thor_common_init(model, 0);
return ret;
}
static void
machine_at_endeavor_gpio_init(void)
{
uint32_t gpio = 0xffffe0cf;
uint16_t addr;
/* Register 0x0078 (Undocumented): */
/* Bit 5,4: Vibra 16S base address: 0 = 220h, 1 = 260h, 2 = 240h, 3 = 280h. */
device_context(machine_get_snd_device(machine));
addr = device_get_config_hex16("base");
switch (addr) {
case 0x0220:
gpio |= 0xffff00cf;
break;
case 0x0240:
gpio |= 0xffff00ef;
break;
case 0x0260:
gpio |= 0xffff00df;
break;
case 0x0280:
gpio |= 0xffff00ff;
break;
}
device_context_restore();
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
/* Bit 1: 0 = Soft-off capable power supply present, 1 = Soft-off capable power supply absent. */
/* Bit 0: 0 = 2x multiplier, 1 = 1.5x multiplier (Switch 6). */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff0000;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff0800;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff1000;
if (sound_card_current[0] == SOUND_INTERNAL)
gpio |= 0xffff0400;
if (cpu_dmulti <= 1.5)
gpio |= 0xffff0100;
else
gpio |= 0xffff0000;
machine_set_gpio_default(gpio);
}
uint32_t
machine_at_endeavor_gpio_handler(uint8_t write, uint32_t val)
{
uint32_t ret = machine_get_gpio_default();
if (write) {
ret &= ((val & 0xffffffcf) | 0xffff0000);
ret |= (val & 0x00000030);
if (machine_snd != NULL) switch ((val >> 4) & 0x03) {
case 0x00:
sb_vibra16s_onboard_relocate_base(0x0220, machine_snd);
break;
case 0x01:
sb_vibra16s_onboard_relocate_base(0x0260, machine_snd);
break;
case 0x02:
sb_vibra16s_onboard_relocate_base(0x0240, machine_snd);
break;
case 0x03:
sb_vibra16s_onboard_relocate_base(0x0280, machine_snd);
break;
}
machine_set_gpio(ret);
} else
ret = machine_get_gpio();
return ret;
}
int
machine_at_endeavor_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/endeavor/1006cb0_.bio",
"roms/machines/endeavor/1006cb0_.bi1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_endeavor_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
if (sound_card_current[0] == SOUND_INTERNAL)
machine_snd = device_add(machine_get_snd_device(machine));
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ms5119_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5119/A37EB.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0f, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83787f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
static void
machine_at_pb640_gpio_init(void)
{
uint32_t gpio = 0xffffe6ff;
/* Register 0x0079: */
/* Bit 7: 0 = Clear password, 1 = Keep password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: No Connect. */
/* Bit 1: No Connect. */
/* Bit 0: 2x multiplier, 1 = 1.5x multiplier (Switch 6). */
/* NOTE: A bit is read as 1 if switch is off, and as 0 if switch is on. */
if (cpu_busspeed <= 50000000)
gpio |= 0xffff00ff;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
gpio |= 0xffff08ff;
else if (cpu_busspeed > 60000000)
gpio |= 0xffff10ff;
if (cpu_dmulti <= 1.5)
gpio |= 0xffff01ff;
else
gpio |= 0xffff00ff;
machine_set_gpio_default(gpio);
}
int
machine_at_pb640_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/pb640/1007CP0R.BIO",
"roms/machines/pb640/1007CP0R.BI1", 0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_pb640_gpio_init();
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430fx_rev02_device);
device_add(&piix_rev02_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5440_onboard_pci_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_mb500n_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mb500n/031396s.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_pci_device);
device_add(&i430fx_device);
device_add(&piix_no_mirq_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_fmb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/fmb/P5IV183.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 2, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 3, 2, 1);
device_add(&i430fx_device);
device_add(&piix_no_mirq_device);
device_add(&keyboard_at_ami_device);
device_add(&w83787f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_acerm3a_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/acerm3a/r01-b3.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x10, PCI_CARD_VIDEO, 4, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&fdc37c935_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ap53_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap53/ap53r2c0.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_VIDEO, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_8500tuc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/8500tuc/Tuc0221b.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2s_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p55t2s/s6y08t.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p5vxb_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5vxb/P5VXB10.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_gw2kte_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined2("roms/machines/gw2kte/1008CY1T.BIO",
"roms/machines/gw2kte/1008CY1T.BI1",
"roms/machines/gw2kte/1008CY1T.BI2",
"roms/machines/gw2kte/1008CY1T.BI3",
"roms/machines/gw2kte/1008CY1T.RCV",
0x3a000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ap5s_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap5s/AP5S150.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_5511_device);
device_add(&keyboard_ps2_ami_device);
device_add(&fdc37c665_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_ms5124_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms5124/AG77.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0xFE, 0xFF, 0, 0);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&sis_5511_device);
device_add(&keyboard_ps2_ami_device);
device_add(&w83787f_88h_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_amis727_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/amis727/S727p.rom",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0xFE, 0xFF, 0, 0);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_5511_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_vectra54_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vectra54/GT0724.22",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_VIDEO, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
if (gfxcard[0] == VID_INTERNAL)
device_add(&s3_phoenix_trio64_onboard_pci_device);
device_add(&i430fx_device);
device_add(&piix_device);
device_add(&fdc37c932_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_5sbm2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/5sbm2/5SBM0717.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x11, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&keyboard_at_ami_device);
device_add(&sis_550x_device);
device_add(&um8663af_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_pc140_6260_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pc140_6260/LYKT32A.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_VIDEO, 0, 0, 0, 0); /* Onboard video */
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5436_onboard_pci_device);
device_add(&sis_5511_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c669_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket7_3v.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,976 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 370(PGA370) machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/spd.h>
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/clock.h>
#include <86box/sound.h>
#include <86box/snd_ac97.h>
int
machine_at_s370slm_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/s370slm/3LM1202.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&w83781d_device); /* fans: CPU, Fan 2, Chassis; temperatures: unused, CPU, unused */
hwm_values.temperatures[0] = 0; /* unused */
hwm_values.temperatures[2] = 0; /* unused */
return ret;
}
int
machine_at_s1857_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/s1857/BX57200A.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUND, 1, 0, 0, 0);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&cs4297_device); /* no good pictures, but the marking looks like CS4297 from a distance */
}
return ret;
}
int
machine_at_p6bap_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6bap/bapa14a.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0a, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0b, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133a_device); /* Rebranded as ET82C693A */
device_add(&via_vt82c596b_device); /* Rebranded as ET82C696B */
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cmi8738_onboard_device);
return ret;
}
int
machine_at_p6bat_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6bat/bata+56.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0a, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0b, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133_device);
device_add(&via_vt82c596b_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cmi8738_onboard_device);
return ret;
}
int
machine_at_cubx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cubx/1008cu.004",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_IDE, 2, 3, 4, 1);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(ics9xxx_get(ICS9250_08));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
return ret;
}
int
machine_at_atc7020bxii_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc7020bxii/7020s102.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&slc90e66_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
return ret;
}
int
machine_at_m773_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m773/010504s.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_SOUND, 4, 3, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&slc90e66_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&it8671f_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
device_add(&gl520sm_2d_device); /* fans: CPU, Chassis; temperature: System */
hwm_values.temperatures[0] += 2; /* System offset */
hwm_values.temperatures[1] += 2; /* CPU offset */
hwm_values.voltages[0] = 3300; /* Vcore and 3.3V are swapped */
hwm_values.voltages[2] = hwm_get_vcore();
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cmi8738_onboard_device);
return ret;
}
int
machine_at_ambx133_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ambx133/mkbx2vg2.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&gl518sm_2d_device); /* fans: CPUFAN1, CPUFAN2; temperature: CPU */
hwm_values.fans[1] += 500;
hwm_values.temperatures[0] += 4; /* CPU offset */
hwm_values.voltages[1] = RESISTOR_DIVIDER(12000, 10, 2); /* different 12V divider in BIOS (10K/2K?) */
return ret;
}
int
machine_at_awo671r_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/awo671r/a08139c.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add_inst(&w83977ef_device, 1);
device_add_inst(&w83977ef_device, 2);
device_add(&keyboard_ps2_pci_device);
device_add(&sst_flash_39sf020_device);
if (gfxcard[0] == VID_INTERNAL) {
device_add(&chips_69000_onboard_device);
}
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_63a1_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/63a1/63a-q3.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); /* Integrated Sound? */
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440zx_device);
device_add(&piix4e_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
int
machine_at_apas3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/apas3/V0218SAG.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro_device);
device_add(&via_vt82c586b_device);
device_add(&fdc37c669_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_cuv4xls_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/cuv4xls/1005LS.001",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 4, 1, 2, 3);
pci_register_slot(0x05, PCI_CARD_SOUND, 3, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_NORMAL, 2, 3, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133a_device);
device_add(&via_vt82c686b_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9250_18));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 1024);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&cmi8738_onboard_device);
return ret;
}
int
machine_at_6via90ap_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/6via90ap/90ap10.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133a_device);
device_add(&via_vt82c686b_device); /* fans: CPU1, CPU2; temperatures: CPU, System, unused */
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9250_18));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 1024);
hwm_values.temperatures[0] += 2; /* CPU offset */
hwm_values.temperatures[1] += 2; /* System offset */
hwm_values.temperatures[2] = 0; /* unused */
if (sound_card_current[0] == SOUND_INTERNAL)
device_add(&alc100_device); /* ALC100P identified on similar Acorp boards (694TA, 6VIA90A1) */
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket370.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,100 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of various Compaq XT-class PC's.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, <mariogplayer@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/nmi.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/machine.h>
int
machine_xt_compaq_deskpro_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/deskpro/Compaq - BIOS - Revision J - 106265-002.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_compaq_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
nmi_init();
standalone_gameport_type = &gameport_device;
lpt1_remove();
lpt1_init(LPT_MDA_ADDR);
return ret;
}
int
machine_xt_compaq_portable_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/portable/compaq portable plus 100666-001 rev c u47.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_compaq_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_xt_device);
nmi_init();
if (joystick_type)
device_add(&gameport_device);
lpt1_remove();
lpt1_init(LPT_MDA_ADDR);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_compaq.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 637 |
```c
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/nmi.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/gameport.h>
#include <86box/ibm_5161.h>
#include <86box/keyboard.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/chipset.h>
#include <86box/port_6x.h>
extern const device_t vendex_xt_rtc_onboard_device;
static void
machine_xt_common_init(const machine_t *model, int fixed_floppy)
{
if ((fdc_current[0] == FDC_INTERNAL) || fixed_floppy)
device_add(&fdc_xt_device);
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
nmi_init();
standalone_gameport_type = &gameport_device;
}
int
machine_pc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ibmpc/BIOS_5150_24APR81_U33.BIN",
0x000fe000, 40960, 0);
if (ret) {
bios_load_aux_linear("roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U29 - 5700019.bin",
0x000f6000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U30 - 5700027.bin",
0x000f8000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U31 - 5700035.bin",
0x000fa000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc/IBM 5150 - Cassette BASIC version C1.00 - U32 - 5700043.bin",
0x000fc000, 8192, 0);
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_pc82_init(const machine_t *model)
{
int ret;
int ret2;
ret = bios_load_linear("roms/machines/ibmpc82/pc102782.bin",
0x000fe000, 40960, 0);
if (ret) {
ret2 = bios_load_aux_linear("roms/machines/ibmpc82/ibm-basic-1.10.rom",
0x000f6000, 32768, 0);
if (!ret2) {
bios_load_aux_linear("roms/machines/ibmpc82/basicc11.f6",
0x000f6000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc82/basicc11.f8",
0x000f8000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc82/basicc11.fa",
0x000fa000, 8192, 0);
bios_load_aux_linear("roms/machines/ibmpc82/basicc11.fc",
0x000fc000, 8192, 0);
}
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc82_device);
device_add(&ibm_5161_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ibmxt/xt.rom",
0x000f0000, 65536, 0);
if (!ret) {
ret = bios_load_linear("roms/machines/ibmxt/1501512.u18",
0x000fe000, 65536, 0x6000);
if (ret) {
bios_load_aux_linear("roms/machines/ibmxt/1501512.u18",
0x000f8000, 24576, 0);
bios_load_aux_linear("roms/machines/ibmxt/5000027.u19",
0x000f0000, 32768, 0);
}
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
device_add(&ibm_5161_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_genxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/genxt/pcxt.rom",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt86_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ibmxt86/BIOS_5160_09MAY86_U18_59X7268_62X0890_27256_F800.BIN",
0x000fe000, 65536, 0x6000);
if (ret) {
(void) bios_load_aux_linear("roms/machines/ibmxt86/BIOS_5160_09MAY86_U18_59X7268_62X0890_27256_F800.BIN",
0x000f8000, 24576, 0);
(void) bios_load_aux_linear("roms/machines/ibmxt86/BIOS_5160_09MAY86_U19_62X0819_68X4370_27256_F000.BIN",
0x000f0000, 32768, 0);
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt86_device);
device_add(&ibm_5161_device);
machine_xt_common_init(model, 0);
return ret;
}
static void
machine_xt_clone_init(const machine_t *model, int fixed_floppy)
{
device_add(&keyboard_xtclone_device);
machine_xt_common_init(model, fixed_floppy);
}
int
machine_xt_americxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/americxt/AMERICXT.ROM",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_amixt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/amixt/ami_8088_bios_31jan89.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_znic_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/znic/ibmzen.rom",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_dtk_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/dtk/dtk_erso_2.42_2764.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_jukopc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/jukopc/000o001.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_openxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/openxt/pcxt31.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_pcxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pcxt/u18.rom",
0x000f8000, 65536, 0);
if (ret) {
bios_load_aux_linear("roms/machines/pcxt/u19.rom",
0x000f0000, 32768, 0);
}
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_pxxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pxxt/000p001.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_iskra3104_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/iskra3104/198.bin",
"roms/machines/iskra3104/199.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_pravetz16_imko4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pravetz16/BIOS_IMKO4_FE00.bin",
0x000fe000, 65536, 0);
if (ret) {
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F400.BIN",
0x000f4000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F600.BIN",
0x000f6000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_FA00.BIN",
0x000fa000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F800.BIN",
0x000f8000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_FC00.BIN",
0x000fc000, 8192, 0);
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_pravetz_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_pravetz16s_cpu12p_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pravetz16s/PR16S.BIN",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_micoms_xl7turbo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mxl7t/XL7_TURBO.BIN",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_pc4i_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pc4i/NCR_PC4i_BIOSROM_1985.BIN",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_mpc1600_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mpc1600/mpc4.34_merged.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc82_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_pcspirit_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pcspirit/u1101.bin",
0x000fe000, 16384, 0);
if (ret) {
bios_load_aux_linear("roms/machines/pcspirit/u1103.bin",
0x000fc000, 8192, 0);
}
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc82_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_pc700_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pc700/multitech pc-700 3.1.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_pc500_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pc500/rom404.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_pc_device);
machine_xt_common_init(model, 0);
return ret;
}
int
machine_xt_vendex_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vendex/Vendex Turbo 888 XT - ROM BIOS - VER 2.03C.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
/* On-board FDC cannot be disabled */
machine_xt_clone_init(model, 1);
device_add(&vendex_xt_rtc_onboard_device);
return ret;
}
static void
machine_xt_hyundai_common_init(const machine_t *model, int fixed_floppy)
{
device_add(&keyboard_xt_hyundai_device);
machine_xt_common_init(model, fixed_floppy);
}
int
machine_xt_super16t_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/super16t/Hyundai SUPER-16T - System BIOS HEA v1.12Ta (16k)(MBM27128)(1986).BIN",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
/* On-board FDC cannot be disabled */
machine_xt_hyundai_common_init(model, 1);
return ret;
}
int
machine_xt_super16te_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/super16te/Hyundai SUPER-16TE - System BIOS v2.00Id (16k)(D27128A)(1989).BIN",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
/* On-board FDC cannot be disabled */
machine_xt_hyundai_common_init(model, 1);
return ret;
}
int
machine_xt_top88_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/top88/Hyosung Topstar 88T - BIOS version 3.0.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
/* On-board FDC cannot be disabled */
machine_xt_clone_init(model, 1);
return ret;
}
int
machine_xt_kaypropc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/kaypropc/Kaypro_v2.03K.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_sansx16_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sansx16/tmm27128ad.bin.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
/* On-board FDC cannot be disabled */
machine_xt_clone_init(model, 1);
return ret;
}
int
machine_xt_bw230_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/bw230/bondwell.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_v20xt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/v20xt/V20XTBios.bin",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_pb8810_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pb8810/pb8088-8810-633acc631aba0345517682.bin",
0x000fc000, 16384, 0);
if (bios_only || !ret)
return ret;
machine_xt_clone_init(model, 0);
return ret;
}
int
machine_xt_glabios_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/glabios/GLABIOS_0.2.6_8X_012324.ROM",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
device_add(&keyboard_xt_device);
machine_xt_common_init(model, 0);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,411 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Slot 1 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/spd.h>
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/sound.h>
#include <86box/clock.h>
#include <86box/snd_ac97.h>
int
machine_at_p65up5_cpknd_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p65up5/NDKN0218.AWD",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_p65up5_common_init(model, &i440fx_device);
return ret;
}
int
machine_at_kn97_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/kn97/0116I.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&i440fx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
device_add(&lm78_device); /* fans: Chassis, CPU, Power; temperature: MB */
for (uint8_t i = 0; i < 3; i++)
hwm_values.fans[i] *= 2; /* BIOS reports fans with the wrong divisor for some reason */
return ret;
}
int
machine_at_lx6_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/lx6/LX6C_PZ.B00",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
return ret;
}
int
machine_at_spitfire_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/spitfire/SPIHM.02",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_VIDEO, 1, 2, 0, 0);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&fdc37c935_no_nvr_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
device_add(&lm78_device); /* no reporting in BIOS */
return ret;
}
int
machine_at_ma30d_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ma30d/BIOS.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
#ifdef UNKNOWN_SLOT
pci_register_slot(0x0A, PCI_CARD_NETWORK, 2, 3, 4, 1); /* ???? device - GPIO? */
#endif
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 3, 0, 0, 0);
device_add(&i440lx_device);
device_add(&piix4e_device);
device_add(&nec_mate_unk_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c67x_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_p6i440e2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6i440e2/E2_v14sl.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440ex_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x03, 256);
device_add(&w83781d_device); /* fans: CPU, CHS, PS; temperatures: unused, CPU, System */
hwm_values.temperatures[0] = 0; /* unused */
hwm_values.voltages[1] = 1500; /* CPUVTT */
return ret;
}
int
machine_at_p2bls_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p2bls/1014ls.003",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x06, PCI_CARD_SCSI, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_NETWORK, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
#if 0
device_add(ics9xxx_get(ICS9150_08)); /* setting proper speeds requires some interaction with the AS97127F ASIC */
#endif
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
device_add(&w83781d_device); /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
hwm_values.temperatures[1] = 0; /* unused */
hwm_values.temperatures[2] -= 3; /* CPU offset */
return ret;
}
int
machine_at_lgibmx7g_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/lgibmx7g/ms6119.331",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&winbond_flash_w29c020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_p3bf_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p3bf/1008f.004",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977ef_device);
device_add(ics9xxx_get(ICS9250_08));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
hwm_values.voltages[4] = hwm_values.voltages[5]; /* +12V reading not in line with other boards; appears to be close to the -12V reading */
return ret;
}
int
machine_at_bf6_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/bf6/Beh_70.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 1, 4, 3);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 3, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_ax6bc_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ax6bc/AX6BC_R2.59.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&sst_flash_29ee020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&gl518sm_2d_device); /* fans: System, CPU; temperature: CPU; no reporting in BIOS */
return ret;
}
int
machine_at_atc6310bxii_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc6310bxii/6310s102.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&slc90e66_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_686bx_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/686bx/6BX.F2a",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&w83977tf_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
device_add(&w83781d_device); /* fans: CPU, unused, unused; temperatures: unused, CPU, unused */
hwm_values.temperatures[0] = 0; /* unused */
hwm_values.temperatures[1] += 4; /* CPU offset */
hwm_values.temperatures[2] = 0; /* unused */
hwm_values.fans[1] = 0; /* unused */
hwm_values.fans[2] = 0; /* unused */
return ret;
}
int
machine_at_p6sba_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6sba/SBAB21.ROM",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&w83781d_device); /* fans: CPU1, CPU2, Thermal Control; temperatures: unused, CPU1, CPU2? */
hwm_values.fans[1] = 0; /* no CPU2 fan */
hwm_values.temperatures[0] = 0; /* unused */
hwm_values.temperatures[2] = 0; /* CPU2? */
/* no CPU2 voltage */
return ret;
}
int
machine_at_s1846_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/s1846/bx46200f.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUND, 1, 0, 0, 0);
pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&pc87309_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&ct1297_device); /* no good pictures, but the marking looks like CT1297 from a distance */
}
return ret;
}
int
machine_at_ficka6130_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ficka6130/qa4163.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro_device);
device_add(&via_vt82c596a_device);
device_add(&w83877tf_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
return ret;
}
int
machine_at_p3v133_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p3v133/1003.002",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133_device);
device_add(&via_vt82c596b_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9248_39));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
device_add(&w83781d_device); /* fans: Chassis, CPU, Power; temperatures: MB, unused, CPU */
hwm_values.temperatures[1] = 0; /* unused */
hwm_values.temperatures[2] -= 3; /* CPU offset */
return ret;
}
int
machine_at_p3v4x_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p3v4x/1006.004",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133a_device);
device_add(&via_vt82c596b_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9250_18));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 512);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
return ret;
}
int
machine_at_gt694va_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/gt694va/21071100.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 3, 4);
pci_register_slot(0x0D, PCI_CARD_SOUND, 4, 1, 2, 3); /* assumed */
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_apro133a_device);
device_add(&via_vt82c596b_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 1024);
device_add(&w83782d_device); /* fans: CPU, unused, unused; temperatures: System, CPU1, unused */
hwm_values.voltages[1] = 1500; /* IN1 (unknown purpose, assumed Vtt) */
hwm_values.fans[0] = 4500; /* BIOS does not display <4411 RPM */
hwm_values.fans[1] = 0; /* unused */
hwm_values.fans[2] = 0; /* unused */
hwm_values.temperatures[2] = 0; /* unused */
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&cs4297_device); /* no good pictures, but the marking looks like CS4297 from a distance */
}
return ret;
}
int
machine_at_vei8_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vei8/QHW1001.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&fdc37m60x_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(ics9xxx_get(ICS9250_08));
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 512);
device_add(&as99127f_device); /* fans: Chassis, CPU, Power; temperatures: MB, JTPWR, CPU */
return ret;
}
static void
machine_at_ms6168_common_init(const machine_t *model)
{
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_SOUND, 3, 4, 1, 2);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440zx_device);
device_add(&piix4e_device);
device_add(&w83977ef_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&voodoo_3_2000_agp_onboard_8m_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&cs4297_device);
}
}
int
machine_at_borapro_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/borapro/MS6168V2.50",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_ms6168_common_init(model);
return ret;
}
int
machine_at_ms6168_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ms6168/w6168ims.130",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_ms6168_common_init(model);
return ret;
}
int
machine_at_m729_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m729/M729NEW.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE_IDE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE_PMU, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE_USB, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1621_device);
device_add(&ali1543c_device); /* +0 */
device_add(&winbond_flash_w29c010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
int
machine_at_p6f99_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p6f99/99-8.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_SOUND, 2, 3, 4, 1);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x02, PCI_CARD_AGPBRIDGE, 0, 0, 0, 0);
device_add(&sis_5600_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&it8661f_device);
device_add(&winbond_flash_w29c020_device);
if (sound_card_current[0] == SOUND_INTERNAL) {
device_add(machine_get_snd_device(machine));
device_add(&ct1297_device);
}
return ret;
}
int
machine_at_m747_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m747/990521.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x02, PCI_CARD_AGPBRIDGE, 0, 0, 0, 0);
device_add(&sis_5600_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&it8661f_device);
device_add(&winbond_flash_w29c020_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_slot1.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,229 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Toshiba T1000 and T1200 portables.
*
* The T1000 is the T3100e's little brother -- a real laptop
* with a rechargeable battery.
*
* Features: 80C88 at 4.77MHz
* - 512k system RAM
* - 640x200 monochrome LCD
* - 82-key keyboard
* - Real-time clock. Not the normal 146818, but a TC8521,
* which is a 4-bit chip.
* - A ROM drive (128k, 256k or 512k) which acts as a mini
* hard drive and contains a copy of DOS 2.11.
* - 160 bytes of non-volatile RAM for the CONFIG.SYS used
* when booting from the ROM drive. Possibly physically
* located in the keyboard controller RAM.
*
* An optional memory expansion board can be fitted. This adds
* 768k of RAM, which can be used for up to three purposes:
* > Conventional memory -- 128k between 512k and 640k
* > HardRAM -- a battery-backed RAM drive.
* > EMS
*
* This means that there are up to three different
* implementations of non-volatile RAM in the same computer
* (52 nibbles in the TC8521, 160 bytes of CONFIG.SYS, and
* up to 768k of HardRAM).
*
* The T1200 is a slightly upgraded version with a turbo mode
* (double CPU clock, 9.54MHz) and an optional hard drive.
* The interface for this is proprietary both at the physical
* and programming level.
*
* 01F2h: If hard drive is present, low 4 bits are 0Ch [20Mb]
* or 0Dh [10Mb].
*
* The hard drive is a 20MB (615/2/26) RLL 3.5" drive.
*
* The TC8521 is a 4-bit RTC, so each memory location can only
* hold a single BCD digit. Hence everything has 'ones' and
* 'tens' digits.
*
* NOTE: Still need to figure out a way to load/save ConfigSys and
* HardRAM stuff. Needs to be linked in to the NVR code.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/nmi.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/nvr.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/gameport.h>
#include <86box/hdc.h>
#include <86box/video.h>
#include <86box/plat.h>
#include <86box/machine.h>
#include <86box/m_xt_t1000.h>
#define T1000_ROMSIZE (512 * 1024UL) /* Maximum ROM drive size is 512k */
enum TC8521_ADDR {
/* Page 0 registers */
TC8521_SECOND1 = 0,
TC8521_SECOND10,
TC8521_MINUTE1,
TC8521_MINUTE10,
TC8521_HOUR1,
TC8521_HOUR10,
TC8521_WEEKDAY,
TC8521_DAY1,
TC8521_DAY10,
TC8521_MONTH1,
TC8521_MONTH10,
TC8521_YEAR1,
TC8521_YEAR10,
TC8521_PAGE, /* PAGE register */
TC8521_TEST, /* TEST register */
TC8521_RESET, /* RESET register */
/* Page 1 registers */
TC8521_24HR = 0x1A,
TC8521_LEAPYEAR = 0x1B
};
typedef struct t1000_t {
/* ROM drive */
uint8_t *romdrive;
uint8_t rom_ctl;
uint32_t rom_offset;
mem_mapping_t rom_mapping;
/* CONFIG.SYS drive. */
uint8_t t1000_nvram[160];
uint8_t t1200_nvram[2048];
/* System control registers */
uint8_t sys_ctl[16];
uint8_t syskeys;
uint8_t turbo;
/* NVRAM control */
uint8_t nvr_c0;
uint8_t nvr_tick;
int nvr_addr;
uint8_t nvr_active;
mem_mapping_t nvr_mapping; /* T1200 NVRAM mapping */
/* EMS data */
uint8_t ems_reg[4];
mem_mapping_t mapping[4];
uint32_t page_exec[4];
uint8_t ems_port_index;
uint16_t ems_port;
uint8_t is_640k;
uint32_t ems_base;
int32_t ems_pages;
fdc_t *fdc;
nvr_t nvr;
int is_t1200;
} t1000_t;
static t1000_t t1000;
#ifdef ENABLE_T1000_LOG
int t1000_do_log = ENABLE_T1000_LOG;
static void
t1000_log(const char *fmt, ...)
{
va_list ap;
if (t1000_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define t1000_log(fmt, ...)
#endif
/* Set the chip time. */
static void
tc8521_time_set(uint8_t *regs, struct tm *tm)
{
regs[TC8521_SECOND1] = (tm->tm_sec % 10);
regs[TC8521_SECOND10] = (tm->tm_sec / 10);
regs[TC8521_MINUTE1] = (tm->tm_min % 10);
regs[TC8521_MINUTE10] = (tm->tm_min / 10);
if (regs[TC8521_24HR] & 0x01) {
regs[TC8521_HOUR1] = (tm->tm_hour % 10);
regs[TC8521_HOUR10] = (tm->tm_hour / 10);
} else {
regs[TC8521_HOUR1] = ((tm->tm_hour % 12) % 10);
regs[TC8521_HOUR10] = (((tm->tm_hour % 12) / 10) | ((tm->tm_hour >= 12) ? 2 : 0));
}
regs[TC8521_WEEKDAY] = tm->tm_wday;
regs[TC8521_DAY1] = (tm->tm_mday % 10);
regs[TC8521_DAY10] = (tm->tm_mday / 10);
regs[TC8521_MONTH1] = ((tm->tm_mon + 1) % 10);
regs[TC8521_MONTH10] = ((tm->tm_mon + 1) / 10);
regs[TC8521_YEAR1] = ((tm->tm_year - 80) % 10);
regs[TC8521_YEAR10] = (((tm->tm_year - 80) % 100) / 10);
}
/* Get the chip time. */
#define nibbles(a) (regs[(a##1)] + 10 * regs[(a##10)])
static void
tc8521_time_get(uint8_t *regs, struct tm *tm)
{
tm->tm_sec = nibbles(TC8521_SECOND);
tm->tm_min = nibbles(TC8521_MINUTE);
if (regs[TC8521_24HR] & 0x01)
tm->tm_hour = nibbles(TC8521_HOUR);
else
tm->tm_hour = ((nibbles(TC8521_HOUR) % 12) + (regs[TC8521_HOUR10] & 0x02) ? 12 : 0);
tm->tm_wday = regs[TC8521_WEEKDAY];
tm->tm_mday = nibbles(TC8521_DAY);
tm->tm_mon = (nibbles(TC8521_MONTH) - 1);
tm->tm_year = (nibbles(TC8521_YEAR) + 1980);
}
/* This is called every second through the NVR/RTC hook. */
static void
tc8521_tick(UNUSED(nvr_t *nvr))
{
t1000_log("TC8521: ping\n");
}
static void
tc8521_start(nvr_t *nvr)
{
struct tm tm;
/* Initialize the internal and chip times. */
if (time_sync & TIME_SYNC_ENABLED) {
/* Use the internal clock's time. */
nvr_time_get(&tm);
tc8521_time_set(nvr->regs, &tm);
} else {
/* Set the internal clock from the chip time. */
tc8521_time_get(nvr->regs, &tm);
nvr_time_set(&tm);
}
#if 0
/* Start the RTC - BIOS will do this. */
nvr->regs[TC8521_PAGE] |= 0x80;
#endif
}
/* Write to one of the chip registers. */
static void
tc8521_write(uint16_t addr, uint8_t val, void *priv)
{
nvr_t *nvr = (nvr_t *) priv;
uint8_t page;
/* Get to the correct register page. */
addr &= 0x0f;
page = nvr->regs[0x0d] & 0x03;
if (addr < 0x0d)
addr += (16 * page);
if (addr >= 0x10 && nvr->regs[addr] != val)
nvr_dosave = 1;
/* Store the new value. */
nvr->regs[addr] = val;
}
/* Read from one of the chip registers. */
static uint8_t
tc8521_read(uint16_t addr, void *priv)
{
const nvr_t *nvr = (nvr_t *) priv;
uint8_t page;
/* Get to the correct register page. */
addr &= 0x0f;
page = nvr->regs[0x0d] & 0x03;
if (addr < 0x0d)
addr += (16 * page);
/* Grab and return the desired value. */
return (nvr->regs[addr]);
}
/* Reset the 8521 to a default state. */
static void
tc8521_reset(nvr_t *nvr)
{
/* Clear the NVRAM. */
memset(nvr->regs, 0xff, nvr->size);
/* Reset the RTC registers. */
memset(nvr->regs, 0x00, 16);
nvr->regs[TC8521_WEEKDAY] = 0x01;
nvr->regs[TC8521_DAY1] = 0x01;
nvr->regs[TC8521_MONTH1] = 0x01;
}
static void
tc8521_init(nvr_t *nvr, int size)
{
/* This is machine specific. */
nvr->size = size;
nvr->irq = -1;
/* Set up any local handlers here. */
nvr->reset = tc8521_reset;
nvr->start = tc8521_start;
nvr->tick = tc8521_tick;
/* Initialize the actual NVR. */
nvr_init(nvr);
io_sethandler(0x02c0, 16,
tc8521_read, NULL, NULL, tc8521_write, NULL, NULL, nvr);
}
/* Given an EMS page ID, return its physical address in RAM. */
static uint32_t
ems_execaddr(t1000_t *sys, UNUSED(int pg), uint16_t val)
{
if (!(val & 0x80))
return 0; /* Bit 7 reset => not mapped */
if (!sys->ems_pages)
return 0; /* No EMS available: all used by
* HardRAM or conventional RAM */
val &= 0x7f;
#if 0
t1000_log("Select EMS page: %d of %d\n", val, sys->ems_pages);
#endif
if (val < sys->ems_pages) {
/* EMS is any memory above 512k,
with ems_base giving the start address */
return ((512 * 1024) + (sys->ems_base * 0x10000) + (0x4000 * val));
}
return 0;
}
static uint8_t
ems_in(uint16_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
#if 0
t1000_log("ems_in(%04x)=%02x\n", addr, sys->ems_reg[(addr >> 14) & 3]);
#endif
return (sys->ems_reg[(addr >> 14) & 3]);
}
static void
ems_out(uint16_t addr, uint8_t val, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
int pg = (addr >> 14) & 3;
#if 0
t1000_log("ems_out(%04x, %02x) pg=%d\n", addr, val, pg);
#endif
sys->ems_reg[pg] = val;
sys->page_exec[pg] = ems_execaddr(sys, pg, val);
if (sys->page_exec[pg]) {
/* Page present */
mem_mapping_enable(&sys->mapping[pg]);
mem_mapping_set_exec(&sys->mapping[pg], ram + sys->page_exec[pg]);
} else {
mem_mapping_disable(&sys->mapping[pg]);
}
}
/* Hardram size is in 64k units */
static void
ems_set_hardram(t1000_t *sys, uint8_t val)
{
val &= 0x1f; /* Mask off pageframe address */
if (val && mem_size > 512)
sys->ems_base = val;
else
sys->ems_base = 0;
#if 0
t1000_log("EMS base set to %02x\n", val);
#endif
sys->ems_pages = ((mem_size - 512) / 16) - 4 * sys->ems_base;
if (sys->ems_pages < 0)
sys->ems_pages = 0;
/* Recalculate EMS mappings */
for (uint8_t n = 0; n < 4; n++)
ems_out(n << 14, sys->ems_reg[n], sys);
}
static void
ems_set_640k(t1000_t *sys, uint8_t val)
{
if (val && mem_size >= 640) {
mem_mapping_set_addr(&ram_low_mapping, 0, 640 * 1024);
sys->is_640k = 1;
} else {
mem_mapping_set_addr(&ram_low_mapping, 0, 512 * 1024);
sys->is_640k = 0;
}
}
static void
ems_set_port(t1000_t *sys, uint8_t val)
{
int n;
#if 0
t1000_log("ems_set_port(%d)", val & 0x0f);
#endif
if (sys->ems_port) {
for (n = 0; n <= 0xc000; n += 0x4000) {
io_removehandler(sys->ems_port + n, 1,
ems_in, NULL, NULL, ems_out, NULL, NULL, sys);
}
sys->ems_port = 0;
}
val &= 0x0f;
sys->ems_port_index = val;
if (val == 7) {
/* No EMS */
sys->ems_port = 0;
} else {
sys->ems_port = 0x208 | (val << 4);
for (n = 0; n <= 0xc000; n += 0x4000) {
io_sethandler(sys->ems_port + n, 1,
ems_in, NULL, NULL, ems_out, NULL, NULL, sys);
}
sys->ems_port = 0;
}
#if 0
t1000_log(" -> %04x\n", sys->ems_port);
#endif
}
static int
addr_to_page(uint32_t addr)
{
return ((addr - 0xd0000) / 0x4000);
}
/* Read RAM in the EMS page frame. */
static uint8_t
ems_read_ram(uint32_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xff;
addr = sys->page_exec[pg] + (addr & 0x3fff);
return (ram[addr]);
}
static uint16_t
ems_read_ramw(uint32_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xff;
#if 0
t1000_log("ems_read_ramw addr=%05x ", addr);
#endif
addr = sys->page_exec[pg] + (addr & 0x3FFF);
#if 0
t1000_log("-> %06x val=%04x\n", addr, *(uint16_t *)&ram[addr]);
#endif
return (*(uint16_t *) &ram[addr]);
}
static uint32_t
ems_read_raml(uint32_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return 0xff;
addr = sys->page_exec[pg] + (addr & 0x3fff);
return (*(uint32_t *) &ram[addr]);
}
/* Write RAM in the EMS page frame. */
static void
ems_write_ram(uint32_t addr, uint8_t val, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
addr = sys->page_exec[pg] + (addr & 0x3fff);
if (ram[addr] != val)
nvr_dosave = 1;
ram[addr] = val;
}
static void
ems_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
#if 0
t1000_log("ems_write_ramw addr=%05x ", addr);
#endif
addr = sys->page_exec[pg] + (addr & 0x3fff);
#if 0
t1000_log("-> %06x val=%04x\n", addr, val);
#endif
if (*(uint16_t *) &ram[addr] != val)
nvr_dosave = 1;
*(uint16_t *) &ram[addr] = val;
}
static void
ems_write_raml(uint32_t addr, uint32_t val, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
int pg = addr_to_page(addr);
if (pg < 0)
return;
addr = sys->page_exec[pg] + (addr & 0x3fff);
if (*(uint32_t *) &ram[addr] != val)
nvr_dosave = 1;
*(uint32_t *) &ram[addr] = val;
}
static uint8_t
read_ctl(uint16_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
uint8_t ret = 0xff;
switch (addr & 0x0f) {
case 1:
ret = sys->syskeys;
break;
case 0x0f: /* Detect EMS board */
switch (sys->sys_ctl[0x0e]) {
case 0x50:
if (mem_size > 512)
ret = (0x90 | sys->ems_port_index);
break;
case 0x51:
/* 0x60 is the page frame address:
(0xd000 - 0xc400) / 0x20 */
ret = (sys->ems_base | 0x60);
break;
case 0x52:
ret = (sys->is_640k ? 0x80 : 0);
break;
default:
break;
}
break;
default:
ret = (sys->sys_ctl[addr & 0x0f]);
}
return ret;
}
static void
t1200_turbo_set(uint8_t value)
{
if (value == t1000.turbo)
return;
t1000.turbo = value;
if (!value)
cpu_dynamic_switch(0);
else
cpu_dynamic_switch(cpu);
}
static void
write_ctl(uint16_t addr, uint8_t val, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
sys->sys_ctl[addr & 0x0f] = val;
switch (addr & 0x0f) {
case 4: /* Video control */
if (sys->sys_ctl[3] == 0x5A) {
t1000_video_options_set((val & 0x20) ? 1 : 0);
t1000_display_set((val & 0x40) ? 0 : 1);
if (sys->is_t1200)
t1200_turbo_set((val & 0x80) ? 1 : 0);
}
break;
/* It looks as if the T1200, like the T3100, can disable
* its builtin video chipset if it detects the presence of
* another video card. */
case 6:
if (sys->is_t1200) {
t1000_video_enable(val & 0x01 ? 0 : 1);
}
break;
case 0x0f: /* EMS control */
switch (sys->sys_ctl[0x0e]) {
case 0x50:
ems_set_port(sys, val);
break;
case 0x51:
ems_set_hardram(sys, val);
break;
case 0x52:
ems_set_640k(sys, val);
break;
default:
break;
}
break;
default:
break;
}
}
/* Ports 0xC0 to 0xC3 appear to have two purposes:
*
* > Access to the 160 bytes of non-volatile RAM containing CONFIG.SYS
* > Reading the floppy changeline. I don't know why the Toshiba doesn't
* use the normal port 0x3F7 for this, but it doesn't.
*
*/
static uint8_t
t1000_read_nvram(uint16_t addr, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
uint8_t tmp = 0xff;
switch (addr) {
case 0xc2: /* Read next byte from NVRAM */
if (sys->nvr_addr >= 0 && sys->nvr_addr < 160)
tmp = sys->t1000_nvram[sys->nvr_addr];
sys->nvr_addr++;
break;
case 0xc3: /* Read floppy changeline and NVRAM ready state */
tmp = fdc_read(0x03f7, t1000.fdc);
tmp = (tmp & 0x80) >> 3; /* Bit 4 is changeline */
tmp |= (sys->nvr_active & 0xc0); /* Bits 6, 7 are r/w mode */
tmp |= 0x2e; /* Bits 5, 3, 2, 1 always 1 */
tmp |= (sys->nvr_active & 0x40) >> 6; /* Ready state */
break;
default:
break;
}
return tmp;
}
static void
t1000_write_nvram(uint16_t addr, uint8_t val, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
/*
* On the real T1000, port 0xC1 is only usable as the high byte
* of a 16-bit write to port 0xC0, with 0x5A in the low byte.
*/
switch (addr) {
case 0xc0:
sys->nvr_c0 = val;
break;
case 0xc1: /* Write next byte to NVRAM */
if (sys->nvr_addr >= 0 && sys->nvr_addr < 160) {
if (sys->t1000_nvram[sys->nvr_addr] != val)
nvr_dosave = 1;
sys->t1000_nvram[sys->nvr_addr] = val;
}
sys->nvr_addr++;
break;
case 0xc2:
break;
case 0xc3:
/*
* At start of NVRAM read / write, 0x80 is written to
* port 0xC3. This seems to reset the NVRAM address
* counter. A single byte is then written (0xff for
* write, 0x00 for read) which appears to be ignored.
* Simulate that by starting the address counter off
* at -1.
*/
sys->nvr_active = val;
if (val == 0x80)
sys->nvr_addr = -1;
break;
default:
break;
}
}
static uint8_t
read_t1200_nvram(uint32_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
return sys->t1200_nvram[addr & 0x7FF];
}
static void
write_t1200_nvram(uint32_t addr, uint8_t value, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
if (sys->t1200_nvram[addr & 0x7FF] != value)
nvr_dosave = 1;
sys->t1200_nvram[addr & 0x7FF] = value;
}
/* Port 0xC8 controls the ROM drive */
static uint8_t
t1000_read_rom_ctl(UNUSED(uint16_t addr), void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
return (sys->rom_ctl);
}
static void
t1000_write_rom_ctl(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
sys->rom_ctl = val;
if (sys->romdrive && (val & 0x80)) {
/* Enable */
sys->rom_offset = ((val & 0x7f) * 0x10000) % T1000_ROMSIZE;
mem_mapping_set_addr(&sys->rom_mapping, 0xa0000, 0x10000);
mem_mapping_set_exec(&sys->rom_mapping, sys->romdrive + sys->rom_offset);
mem_mapping_enable(&sys->rom_mapping);
} else {
mem_mapping_disable(&sys->rom_mapping);
}
}
/* Read the ROM drive */
static uint8_t
t1000_read_rom(uint32_t addr, void *priv)
{
const t1000_t *sys = (t1000_t *) priv;
if (!sys->romdrive)
return 0xff;
return (sys->romdrive[sys->rom_offset + (addr & 0xffff)]);
}
static uint16_t
t1000_read_romw(uint32_t addr, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
if (!sys->romdrive)
return 0xffff;
return (*(uint16_t *) (&sys->romdrive[sys->rom_offset + (addr & 0xffff)]));
}
static uint32_t
t1000_read_roml(uint32_t addr, void *priv)
{
t1000_t *sys = (t1000_t *) priv;
if (!sys->romdrive)
return 0xffffffff;
return (*(uint32_t *) (&sys->romdrive[sys->rom_offset + (addr & 0xffff)]));
}
int
machine_xt_t1000_init(const machine_t *model)
{
FILE *fp;
int ret;
ret = bios_load_linear("roms/machines/t1000/t1000.rom",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
memset(&t1000, 0x00, sizeof(t1000));
t1000.is_t1200 = 0;
t1000.turbo = 0xff;
t1000.ems_port_index = 7; /* EMS disabled */
/* Load the T1000 CGA Font ROM. */
loadfont("roms/machines/t1000/t1000font.bin", 2);
/*
* The ROM drive is optional.
*
* If the file is missing, continue to boot; the BIOS will
* complain 'No ROM drive' but boot normally from floppy.
*/
fp = rom_fopen("roms/machines/t1000/t1000dos.rom", "rb");
if (fp != NULL) {
t1000.romdrive = malloc(T1000_ROMSIZE);
if (t1000.romdrive) {
memset(t1000.romdrive, 0xff, T1000_ROMSIZE);
if (fread(t1000.romdrive, 1, T1000_ROMSIZE, fp) != T1000_ROMSIZE)
fatal("machine_xt_t1000_init(): Error reading DOS ROM data\n");
}
fclose(fp);
}
mem_mapping_add(&t1000.rom_mapping, 0xa0000, 0x10000,
t1000_read_rom, t1000_read_romw, t1000_read_roml,
NULL, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, &t1000);
mem_mapping_disable(&t1000.rom_mapping);
/* Map the EMS page frame */
for (uint8_t pg = 0; pg < 4; pg++) {
mem_mapping_add(&t1000.mapping[pg], 0xd0000 + (0x4000 * pg), 16384,
ems_read_ram, ems_read_ramw, ems_read_raml,
ems_write_ram, ems_write_ramw, ems_write_raml,
NULL, MEM_MAPPING_EXTERNAL, &t1000);
/* Start them all off disabled */
mem_mapping_disable(&t1000.mapping[pg]);
}
/* Non-volatile RAM for CONFIG.SYS */
io_sethandler(0xc0, 4,
t1000_read_nvram, NULL, NULL,
t1000_write_nvram, NULL, NULL, &t1000);
/* ROM drive */
io_sethandler(0xc8, 1,
t1000_read_rom_ctl, NULL, NULL,
t1000_write_rom_ctl, NULL, NULL, &t1000);
/* System control functions, and add-on memory board */
io_sethandler(0xe0, 16,
read_ctl, NULL, NULL, write_ctl, NULL, NULL, &t1000);
machine_common_init(model);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_t1x00_device);
t1000.fdc = device_add(&fdc_xt_device);
nmi_init();
tc8521_init(&t1000.nvr, model->nvrmask + 1);
t1000_nvr_load();
nvr_set_ven_save(t1000_nvr_save);
if (gfxcard[0] == VID_INTERNAL)
device_add(&t1000_video_device);
return ret;
}
int
machine_xt_t1200_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/t1200/t1200_019e.ic15.bin",
0x000f8000, 32768, 0);
if (bios_only || !ret)
return ret;
memset(&t1000, 0x00, sizeof(t1000));
t1000.is_t1200 = 1;
t1000.ems_port_index = 7; /* EMS disabled */
/* Load the T1000 CGA Font ROM. */
loadfont("roms/machines/t1000/t1000font.bin", 2);
/* Map the EMS page frame */
for (uint8_t pg = 0; pg < 4; pg++) {
mem_mapping_add(&t1000.mapping[pg],
0xd0000 + (0x4000 * pg), 16384,
ems_read_ram, ems_read_ramw, ems_read_raml,
ems_write_ram, ems_write_ramw, ems_write_raml,
NULL, MEM_MAPPING_EXTERNAL, &t1000);
/* Start them all off disabled */
mem_mapping_disable(&t1000.mapping[pg]);
}
/* System control functions, and add-on memory board */
io_sethandler(0xe0, 16,
read_ctl, NULL, NULL, write_ctl, NULL, NULL, &t1000);
machine_common_init(model);
mem_mapping_add(&t1000.nvr_mapping,
0x000f0000, 2048,
read_t1200_nvram, NULL, NULL,
write_t1200_nvram, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, &t1000);
pit_devs[0].set_out_func(pit_devs[0].data, 1, pit_refresh_timer_xt);
device_add(&keyboard_xt_t1x00_device);
t1000.fdc = device_add(&fdc_xt_t1x00_device);
nmi_init();
tc8521_init(&t1000.nvr, model->nvrmask + 1);
t1200_nvr_load();
nvr_set_ven_save(t1200_nvr_save);
if (gfxcard[0] == VID_INTERNAL)
device_add(&t1200_video_device);
if (hdc_current[0] <= HDC_INTERNAL)
device_add(&st506_xt_toshiba_t1200_device);
return ret;
}
void
t1000_syskey(uint8_t andmask, uint8_t ormask, uint8_t xormask)
{
t1000.syskeys &= ~andmask;
t1000.syskeys |= ormask;
t1000.syskeys ^= xormask;
}
static void
t1000_configsys_load(void)
{
FILE *fp;
int size;
memset(t1000.t1000_nvram, 0x1a, sizeof(t1000.t1000_nvram));
fp = plat_fopen(nvr_path("t1000_config.nvr"), "rb");
if (fp != NULL) {
size = sizeof(t1000.t1000_nvram);
if (fread(t1000.t1000_nvram, 1, size, fp) != size)
fatal("t1000_configsys_load(): Error reading data\n");
fclose(fp);
}
}
static void
t1000_configsys_save(void)
{
FILE *fp;
int size;
fp = plat_fopen(nvr_path("t1000_config.nvr"), "wb");
if (fp != NULL) {
size = sizeof(t1000.t1000_nvram);
if (fwrite(t1000.t1000_nvram, 1, size, fp) != size)
fatal("t1000_configsys_save(): Error writing data\n");
fclose(fp);
}
}
static void
t1200_state_load(void)
{
FILE *fp;
int size;
memset(t1000.t1200_nvram, 0, sizeof(t1000.t1200_nvram));
fp = plat_fopen(nvr_path("t1200_state.nvr"), "rb");
if (fp != NULL) {
size = sizeof(t1000.t1200_nvram);
if (fread(t1000.t1200_nvram, 1, size, fp) != size)
fatal("t1200_state_load(): Error reading data\n");
fclose(fp);
}
}
static void
t1200_state_save(void)
{
FILE *fp;
int size;
fp = plat_fopen(nvr_path("t1200_state.nvr"), "wb");
if (fp != NULL) {
size = sizeof(t1000.t1200_nvram);
if (fwrite(t1000.t1200_nvram, 1, size, fp) != size)
fatal("t1200_state_save(): Error writing data\n");
fclose(fp);
}
}
/* All RAM beyond 512k is non-volatile */
static void
t1000_emsboard_load(void)
{
FILE *fp;
if (mem_size > 512) {
fp = plat_fopen(nvr_path("t1000_ems.nvr"), "rb");
if (fp != NULL) {
(void) !fread(&ram[512 * 1024], 1024, (mem_size - 512), fp);
fclose(fp);
}
}
}
static void
t1000_emsboard_save(void)
{
FILE *fp;
if (mem_size > 512) {
fp = plat_fopen(nvr_path("t1000_ems.nvr"), "wb");
if (fp != NULL) {
fwrite(&ram[512 * 1024], 1024, (mem_size - 512), fp);
fclose(fp);
}
}
}
void
t1000_nvr_load(void)
{
t1000_emsboard_load();
t1000_configsys_load();
}
void
t1000_nvr_save(void)
{
t1000_emsboard_save();
t1000_configsys_save();
}
void
t1200_nvr_load(void)
{
t1000_emsboard_load();
t1200_state_load();
}
void
t1200_nvr_save(void)
{
t1000_emsboard_save();
t1200_state_save();
}
``` | /content/code_sandbox/src/machine/m_xt_t1000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,008 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Miscellaneous, Fake, Hypervisor machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#include <86box/spd.h>
#include <86box/video.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/sound.h>
int
machine_at_vpc2007_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/vpc2007/13500.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
is_vpc = 1;
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_no_agp_device);
device_add(&piix4e_device);
device_add(&w83977f_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256); /* real VPC provides invalid SPD data */
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_misc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 716 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 4 machines.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/mem.h>
#include <86box/io.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/fdc_ext.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
#include <86box/sio.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/machine.h>
void
machine_at_premiere_common_init(const machine_t *model, int pci_switch)
{
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_2 | pci_switch);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
}
void
machine_at_sp4_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
/* Excluded: 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14 */
pci_register_slot(0x0D, PCI_CARD_IDE, 1, 2, 3, 4);
/* Excluded: 02, 03*, 04*, 05*, 06*, 07*, 08* */
/* Slots: 09 (04), 0A (03), 0B (02), 0C (07) */
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&sis_85c50x_device);
device_add(&ide_cmd640_pci_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_excaliburpci_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excaliburpci/S701P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&i430lx_device);
device_add(&sio_zb_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p5mp3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5mp3/0205.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 05 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x03, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 03 = Slot 3 */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&fdc_at_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_zb_device);
device_add(&catalyst_flash_device);
device_add(&i430lx_device);
return ret;
}
int
machine_at_dellxp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/dellxp60/XP60-A08.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
/* Not: 00, 02, 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F. */
/* Yes: 01, 10, 11, 12, 13, 14. */
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x04, PCI_CARD_NORMAL, 4, 4, 3, 3);
pci_register_slot(0x05, PCI_CARD_NORMAL, 1, 4, 3, 2);
pci_register_slot(0x06, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_opti560l_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/opti560l/560L_A06.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 4, 4, 3, 3);
pci_register_slot(0x07, PCI_CARD_NORMAL, 1, 4, 3, 2);
pci_register_slot(0x08, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&sio_zb_device);
device_add(&i82091aa_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_ambradp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/ambradp60/1004AF1P.BIO",
"roms/machines/ambradp60/1004AF1P.BI1",
0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, 0);
device_add(&i430lx_device);
return ret;
}
int
machine_at_valuepointp60_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/valuepointp60/1006AV0M.BIO",
"roms/machines/valuepointp60/1006AV0M.BI1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&ide_pci_2ch_device);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_VIDEO, 3, 3, 3, 3);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&keyboard_ps2_ps1_pci_device);
device_add(&sio_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_ami_device);
device_add(&i430lx_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&mach32_onboard_pci_device);
return ret;
}
int
machine_at_revenge_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/revenge/1013af2_.bio",
"roms/machines/revenge/1013af2_.bi1",
0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_premiere_common_init(model, 0);
device_add(&i430lx_device);
return ret;
}
void
machine_at_award_common_init(const machine_t *model)
{
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_NORMAL, 1, 2, 3, 4); /* 03 = Slot 1 */
pci_register_slot(0x04, PCI_CARD_NORMAL, 2, 3, 4, 1); /* 04 = Slot 2 */
pci_register_slot(0x05, PCI_CARD_NORMAL, 3, 4, 1, 2); /* 05 = Slot 3 */
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); /* 06 = Slot 4 */
pci_register_slot(0x07, PCI_CARD_SCSI, 1, 2, 3, 4); /* 07 = SCSI */
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sio_zb_device);
device_add(&intel_flash_bxt_device);
}
int
machine_at_586is_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/586is/IS.34",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_award_common_init(model);
device_add(&i430lx_device);
return ret;
}
int
machine_at_pb520r_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined("roms/machines/pb520r/1009bc0r.bio",
"roms/machines/pb520r/1009bc0r.bi1",
0x1d000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_VIDEO, 3, 3, 3, 3);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&ide_cmd640_pci_single_channel_device);
if (gfxcard[0] == VID_INTERNAL)
device_add(&gd5434_onboard_pci_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_zb_device);
device_add(&i82091aa_ide_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_excalibur_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excalibur/S75P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti5x7_device);
device_add(&ide_opti611_vlb_device);
device_add(&fdc37c661_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
return ret;
}
int
machine_at_p5vl_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5vl/SM507.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x12, PCI_CARD_NORMAL, 5, 6, 7, 8);
pci_register_slot(0x13, PCI_CARD_NORMAL, 9, 10, 11, 12);
pci_register_slot(0x14, PCI_CARD_NORMAL, 13, 14, 15, 16);
device_add(&opti5x7_pci_device);
device_add(&opti822_device);
device_add(&sst_flash_29ee010_device);
device_add(&keyboard_at_ami_device);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_excaliburpci2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excaliburpci2/S722P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
device_add(&ami_1994_nvr_device);
pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&sis_85c50x_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p5sp4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/p5sp4/0106.001",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_sp4_common_init(model);
return ret;
}
``` | /content/code_sandbox/src/machine/m_at_socket4.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,586 |
```c
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/nmi.h>
#include <86box/nvr.h>
#include <86box/gameport.h>
#include <86box/keyboard.h>
#include <86box/flash.h>
#include <86box/lpt.h>
#include <86box/rom.h>
#include <86box/hdc.h>
#include <86box/port_6x.h>
#include <86box/video.h>
#include <86box/machine.h>
#include "cpu.h"
#include <86box/plat_unused.h>
#include <86box/m_xt_xi8088.h>
typedef struct xi8088_t {
uint8_t turbo;
int turbo_setting;
int bios_128kb;
} xi8088_t;
static xi8088_t xi8088;
uint8_t
xi8088_turbo_get(void)
{
return xi8088.turbo;
}
void
xi8088_turbo_set(uint8_t value)
{
int c;
if (!xi8088.turbo_setting)
return;
xi8088.turbo = value;
if (!value) {
c = cpu;
cpu = 0; /* 8088/4.77 */
cpu_set();
cpu = c;
} else
cpu_set();
}
int
xi8088_bios_128kb(void)
{
return xi8088.bios_128kb;
}
static void *
xi8088_init(UNUSED(const device_t *info))
{
xi8088.turbo = 1;
xi8088.turbo_setting = device_get_config_int("turbo_setting");
xi8088.bios_128kb = device_get_config_int("bios_128kb");
mem_set_mem_state(0x0a0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
mem_set_mem_state(0x0c0000, 0x08000, device_get_config_int("umb_c0000h_c7fff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0c8000, 0x08000, device_get_config_int("umb_c8000h_cffff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0d0000, 0x08000, device_get_config_int("umb_d0000h_d7fff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0d8000, 0x08000, device_get_config_int("umb_d8000h_dffff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0e0000, 0x08000, device_get_config_int("umb_e0000h_e7fff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0e8000, 0x08000, device_get_config_int("umb_e8000h_effff") ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state(0x0f0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
return &xi8088;
}
static const device_config_t xi8088_config[] = {
// clang-format off
{
.name = "turbo_setting",
.description = "Turbo",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "Always at selected speed",
.value = 0
},
{
.description = "BIOS setting + Hotkeys (off during POST)",
.value = 1
}
},
.default_int = 0
},
{
.name = "bios_128kb",
.description = "BIOS size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "64KB starting from 0xF0000",
.value = 0
},
{
.description = "128KB starting from 0xE0000 (address MSB inverted, last 64KB first)",
.value = 1
}
},
.default_int = 1
},
{
.name = "umb_c0000h_c7fff",
.description = "Map 0xc0000-0xc7fff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "umb_c8000h_cffff",
.description = "Map 0xc8000-0xcffff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "umb_d0000h_d7fff",
.description = "Map 0xd0000-0xd7fff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "umb_d8000h_dffff",
.description = "Map 0xd8000-0xdffff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "umb_e0000h_e7fff",
.description = "Map 0xe0000-0xe7fff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "umb_e8000h_effff",
.description = "Map 0xe8000-0xeffff as UMB",
.type = CONFIG_BINARY,
.default_int = 0
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t xi8088_device = {
.name = "Xi8088",
.internal_name = "xi8088",
.flags = 0,
.local = 0,
.init = xi8088_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = xi8088_config
};
int
machine_xt_xi8088_init(const machine_t *model)
{
int ret;
if (bios_only) {
ret = bios_load_linear_inverted("roms/machines/xi8088/bios-xi8088-128k.bin",
0x000e0000, 131072, 0);
ret |= bios_load_linear("roms/machines/xi8088/bios-xi8088.bin",
0x000f0000, 65536, 0);
} else {
device_add(&xi8088_device);
if (xi8088_bios_128kb()) {
ret = bios_load_linear_inverted("roms/machines/xi8088/bios-xi8088-128k.bin",
0x000e0000, 131072, 0);
} else {
ret = bios_load_linear("roms/machines/xi8088/bios-xi8088.bin",
0x000f0000, 65536, 0);
}
}
if (bios_only || !ret)
return ret;
machine_common_init(model);
if (fdc_current[0] == FDC_INTERNAL)
device_add(&fdc_at_device);
device_add(&keyboard_ps2_xi8088_device);
device_add(&port_6x_xi8088_device);
nmi_init();
device_add(&ibmat_nvr_device);
pic2_init();
standalone_gameport_type = &gameport_device;
device_add(&sst_flash_39sf010_device);
return ret;
}
``` | /content/code_sandbox/src/machine/m_xt_xi8088.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,852 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of the emulated machines.
*
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/keyboard.h>
#include <86box/sound.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
// Temporarily here till we move everything out into the right files
extern const device_t pcjr_device;
extern const device_t m19_vid_device;
extern const device_t vid_device;
extern const device_t vid_device_hx;
extern const device_t t1000_video_device;
extern const device_t xi8088_device;
extern const device_t cga_device;
extern const device_t vid_1512_device;
extern const device_t vid_1640_device;
extern const device_t vid_pc2086_device;
extern const device_t vid_pc3086_device;
extern const device_t vid_200_device;
extern const device_t vid_ppc512_device;
extern const device_t vid_device_sl;
extern const device_t t1200_video_device;
extern const device_t compaq_plasma_device;
extern const device_t ps1_2011_device;
const machine_filter_t machine_types[] = {
{ "None", MACHINE_TYPE_NONE },
{ "[1979] 8088", MACHINE_TYPE_8088 },
{ "[1978] 8086", MACHINE_TYPE_8086 },
{ "[1982] 80286", MACHINE_TYPE_286 },
{ "[1988] i386SX", MACHINE_TYPE_386SX },
{ "[1992] 486SLC", MACHINE_TYPE_486SLC },
{ "[1985] i386DX", MACHINE_TYPE_386DX },
{ "[1989] i386DX/i486", MACHINE_TYPE_386DX_486 },
{ "[1992] i486 (Socket 168 and 1)", MACHINE_TYPE_486 },
{ "[1992] i486 (Socket 2)", MACHINE_TYPE_486_S2 },
{ "[1994] i486 (Socket 3)", MACHINE_TYPE_486_S3 },
{ "[1992] i486 (Miscellaneous)", MACHINE_TYPE_486_MISC },
{ "[1993] Socket 4", MACHINE_TYPE_SOCKET4 },
{ "[1994] Socket 5", MACHINE_TYPE_SOCKET5 },
{ "[1995] Socket 7 (Single Voltage)", MACHINE_TYPE_SOCKET7_3V },
{ "[1996] Socket 7 (Dual Voltage)", MACHINE_TYPE_SOCKET7 },
{ "[1998] Super Socket 7", MACHINE_TYPE_SOCKETS7 },
{ "[1995] Socket 8", MACHINE_TYPE_SOCKET8 },
{ "[1997] Slot 1", MACHINE_TYPE_SLOT1 },
{ "[1998] Slot 1/2", MACHINE_TYPE_SLOT1_2 },
{ "[1998] Slot 1/Socket 370", MACHINE_TYPE_SLOT1_370 },
{ "[1998] Slot 2", MACHINE_TYPE_SLOT2 },
{ "[1998] Socket 370", MACHINE_TYPE_SOCKET370 },
{ "Miscellaneous", MACHINE_TYPE_MISC }
};
const machine_filter_t machine_chipsets[] = {
{ "None", MACHINE_CHIPSET_NONE },
{ "Discrete", MACHINE_CHIPSET_DISCRETE },
{ "Proprietary", MACHINE_CHIPSET_PROPRIETARY },
{ "Headland GC100A", MACHINE_CHIPSET_GC100A },
{ "Headland GC103", MACHINE_CHIPSET_GC103 },
{ "Headland HT18", MACHINE_CHIPSET_HT18 },
{ "ACC 2168", MACHINE_CHIPSET_ACC_2168 },
{ "ALi M1217", MACHINE_CHIPSET_ALI_M1217 },
{ "ALi M6117", MACHINE_CHIPSET_ALI_M6117 },
{ "ALi M1409", MACHINE_CHIPSET_ALI_M1409 },
{ "ALi M1429", MACHINE_CHIPSET_ALI_M1429 },
{ "ALi M1429G", MACHINE_CHIPSET_ALI_M1429G },
{ "ALi M1489", MACHINE_CHIPSET_ALI_M1489 },
{ "ALi ALADDiN IV+", MACHINE_CHIPSET_ALI_ALADDIN_IV_PLUS },
{ "ALi ALADDiN V", MACHINE_CHIPSET_ALI_ALADDIN_V },
{ "ALi ALADDiN-PRO II", MACHINE_CHIPSET_ALI_ALADDIN_PRO_II },
{ "C&T 82C235 SCAT", MACHINE_CHIPSET_SCAT },
{ "C&T CS8121 NEAT", MACHINE_CHIPSET_NEAT },
{ "C&T 386", MACHINE_CHIPSET_CT_386 },
{ "C&T CS4031", MACHINE_CHIPSET_CT_CS4031 },
{ "Contaq 82C596", MACHINE_CHIPSET_CONTAQ_82C596 },
{ "Contaq 82C597", MACHINE_CHIPSET_CONTAQ_82C597 },
{ "IMS 8848", MACHINE_CHIPSET_IMS_8848 },
{ "Intel 82335", MACHINE_CHIPSET_INTEL_82335 },
{ "Intel 420TX", MACHINE_CHIPSET_INTEL_420TX },
{ "Intel 420ZX", MACHINE_CHIPSET_INTEL_420ZX },
{ "Intel 420EX", MACHINE_CHIPSET_INTEL_420EX },
{ "Intel 430LX", MACHINE_CHIPSET_INTEL_430LX },
{ "Intel 430NX", MACHINE_CHIPSET_INTEL_430NX },
{ "Intel 430FX", MACHINE_CHIPSET_INTEL_430FX },
{ "Intel 430HX", MACHINE_CHIPSET_INTEL_430HX },
{ "Intel 430VX", MACHINE_CHIPSET_INTEL_430VX },
{ "Intel 430TX", MACHINE_CHIPSET_INTEL_430TX },
{ "Intel 450KX", MACHINE_CHIPSET_INTEL_450KX },
{ "Intel 440FX", MACHINE_CHIPSET_INTEL_440FX },
{ "Intel 440LX", MACHINE_CHIPSET_INTEL_440LX },
{ "Intel 440EX", MACHINE_CHIPSET_INTEL_440EX },
{ "Intel 440BX", MACHINE_CHIPSET_INTEL_440BX },
{ "Intel 440ZX", MACHINE_CHIPSET_INTEL_440ZX },
{ "Intel 440GX", MACHINE_CHIPSET_INTEL_440GX },
{ "OPTi 283", MACHINE_CHIPSET_OPTI_283 },
{ "OPTi 291", MACHINE_CHIPSET_OPTI_291 },
{ "OPTi 381", MACHINE_CHIPSET_OPTI_381 },
{ "OPTi 391", MACHINE_CHIPSET_OPTI_391 },
{ "OPTi 481", MACHINE_CHIPSET_OPTI_481 },
{ "OPTi 493", MACHINE_CHIPSET_OPTI_493 },
{ "OPTi 495", MACHINE_CHIPSET_OPTI_495 },
{ "OPTi 499", MACHINE_CHIPSET_OPTI_499 },
{ "OPTi 895/802G", MACHINE_CHIPSET_OPTI_895_802G },
{ "OPTi 547/597", MACHINE_CHIPSET_OPTI_547_597 },
{ "SARC RC2016A", MACHINE_CHIPSET_SARC_RC2016A },
{ "SiS 310", MACHINE_CHIPSET_SIS_310 },
{ "SiS 401", MACHINE_CHIPSET_SIS_401 },
{ "SiS 460", MACHINE_CHIPSET_SIS_460 },
{ "SiS 461", MACHINE_CHIPSET_SIS_461 },
{ "SiS 471", MACHINE_CHIPSET_SIS_471 },
{ "SiS 496", MACHINE_CHIPSET_SIS_496 },
{ "SiS 501", MACHINE_CHIPSET_SIS_501 },
{ "SiS 5501", MACHINE_CHIPSET_SIS_5501 },
{ "SiS 5511", MACHINE_CHIPSET_SIS_5511 },
{ "SiS 5571", MACHINE_CHIPSET_SIS_5571 },
{ "SiS 5581", MACHINE_CHIPSET_SIS_5581 },
{ "SiS 5591", MACHINE_CHIPSET_SIS_5591 },
{ "SiS (5)600", MACHINE_CHIPSET_SIS_5600 },
{ "SMSC VictoryBX-66", MACHINE_CHIPSET_SMSC_VICTORYBX_66 },
{ "STPC Client", MACHINE_CHIPSET_STPC_CLIENT },
{ "STPC Consumer-II", MACHINE_CHIPSET_STPC_CONSUMER_II },
{ "STPC Elite", MACHINE_CHIPSET_STPC_ELITE },
{ "STPC Atlas", MACHINE_CHIPSET_STPC_ATLAS },
{ "Symphony SL82C460 Haydn II", MACHINE_CHIPSET_SYMPHONY_SL82C460 },
{ "UMC UM82C480", MACHINE_CHIPSET_UMC_UM82C480 },
{ "UMC UM82C491", MACHINE_CHIPSET_UMC_UM82C491 },
{ "UMC UM8881", MACHINE_CHIPSET_UMC_UM8881 },
{ "UMC UM8890BF", MACHINE_CHIPSET_UMC_UM8890BF },
{ "VIA VT82C495", MACHINE_CHIPSET_VIA_VT82C495 },
{ "VIA VT82C496G", MACHINE_CHIPSET_VIA_VT82C496G },
{ "VIA Apollo VPX", MACHINE_CHIPSET_VIA_APOLLO_VPX },
{ "VIA Apollo VP3", MACHINE_CHIPSET_VIA_APOLLO_VP3 },
{ "VIA Apollo MVP3", MACHINE_CHIPSET_VIA_APOLLO_MVP3 },
{ "VIA Apollo Pro", MACHINE_CHIPSET_VIA_APOLLO_PRO },
{ "VIA Apollo Pro 133", MACHINE_CHIPSET_VIA_APOLLO_PRO_133 },
{ "VIA Apollo Pro 133A", MACHINE_CHIPSET_VIA_APOLLO_PRO_133A },
{ "VLSI SCAMP", MACHINE_CHIPSET_VLSI_SCAMP },
{ "VLSI VL82C480", MACHINE_CHIPSET_VLSI_VL82C480 },
{ "VLSI VL82C481", MACHINE_CHIPSET_VLSI_VL82C481 },
{ "VLSI VL82C486", MACHINE_CHIPSET_VLSI_VL82C486 },
{ "WD76C10", MACHINE_CHIPSET_WD76C10 }
};
/* Machines to add before machine freeze:
- TMC Mycomp PCI54ST;
- Zeos Quadtel 486.
NOTE: The AMI MegaKey tests were done on a real Intel Advanced/ATX
(thanks, MrKsoft for running my AMIKEY.COM on it), but the
technical specifications of the other Intel machines confirm
that the other boards also have the MegaKey.
NOTE: The later (ie. not AMI Color) Intel AMI BIOS'es execute a
sequence of commands (B8, BA, BB) during one of the very first
phases of POST, in a way that is only valid on the AMIKey-3
KBC firmware, that includes the Classic PCI/ED (Ninja) BIOS
which otherwise does not execute any AMI KBC commands, which
indicates that the sequence is a leftover of whatever AMI
BIOS (likely a laptop one since the AMIKey-3 is a laptop KBC
firmware!) Intel forked.
NOTE: The VIA VT82C42N returns 0x46 ('F') in command 0xA1 (so it
emulates the AMI KF/AMIKey KBC firmware), and 0x42 ('B') in
command 0xAF.
The version on the VIA VT82C686B southbridge also returns
'F' in command 0xA1, but 0x45 ('E') in command 0xAF.
The version on the VIA VT82C586B southbridge also returns
'F' in command 0xA1, but 0x44 ('D') in command 0xAF.
The version on the VIA VT82C586A southbridge also returns
'F' in command 0xA1, but 0x43 ('C') in command 0xAF.
NOTE: The AMI MegaKey commands blanked in the technical reference
are CC and and C4, which are Set P14 High and Set P14 Low,
respectively. Also, AMI KBC command C1, mysteriously missing
from the technical references of AMI MegaKey and earlier, is
Write Input Port, same as on AMIKey-3.
*/
const machine_t machines[] = {
// clang-format off
/* 8088 Machines */
{
.name = "[8088] IBM PC (1981)",
.internal_name = "ibmpc",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_pc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC5150,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 16,
.max = 64,
.step = 16
},
.nvrmask = 0,
.kbc_device = &keyboard_pc_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] IBM PC (1982)",
.internal_name = "ibmpc82",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_pc82_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC5150,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 256,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pc82_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] IBM PCjr",
.internal_name = "ibmpcjr",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_pcjr_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 4772728,
.max_bus = 4772728,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCJR,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = NULL, /* TODO: No specific kbd_device yet */
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &pcjr_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] IBM XT (1982)",
.internal_name = "ibmxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 256,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] IBM XT (1986)",
.internal_name = "ibmxt86",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt86_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt86_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] American XT Computer",
.internal_name = "americxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_americxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] AMI XT clone",
.internal_name = "amixt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_amixt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Bondwell BW230",
.internal_name = "bw230",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_bw230_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Columbia Data Products MPC-1600",
.internal_name = "mpc1600",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_mpc1600_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 512,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pc82_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Compaq Portable",
.internal_name = "portable",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_compaq_portable_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_compaq_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] DTK PIM-TB10-Z",
.internal_name = "dtk",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_dtk_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Eagle PC Spirit",
.internal_name = "pcspirit",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pcspirit_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pc82_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Generic XT clone",
.internal_name = "genxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_genxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] GLaBIOS",
.internal_name = "glabios",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_glabios_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Hyosung Topstar 88T",
.internal_name = "top88",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_top88_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Hyundai SUPER-16T",
.internal_name = "super16t",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_super16t_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 4772728,
.max_bus = 8000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Hyundai SUPER-16TE",
.internal_name = "super16te",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_super16te_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Juko ST",
.internal_name = "jukopc",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_jukopc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Kaypro PC",
.internal_name = "kaypropc",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_kaypropc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Micoms XL-7 Turbo",
.internal_name = "mxl7t",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_micoms_xl7turbo_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Multitech PC-500",
.internal_name = "pc500",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pc500_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pc_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Multitech PC-700",
.internal_name = "pc700",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pc700_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pc_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] NCR PC4i",
.internal_name = "pc4i",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pc4i_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Olivetti M19",
.internal_name = "m19",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_m19_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 4772728,
.max_bus = 7159092,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_olivetti_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &m19_vid_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] OpenXT",
.internal_name = "openxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_openxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Packard Bell PB8810",
.internal_name = "pb8810",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pb8810_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Philips P3105/NMS9100",
.internal_name = "p3105",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_p3105_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_XTA,
.ram = {
.min = 256,
.max = 768,
.step = 256
},
.nvrmask = 0,
.kbc_device = &keyboard_pc_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Phoenix XT clone",
.internal_name = "pxxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pxxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Pravetz 16 / IMKO-4",
.internal_name = "pravetz16",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pravetz16_imko4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_pravetz_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Pravetz 16S / CPU12 Plus",
.internal_name = "pravetz16s",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pravetz16s_cpu12p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 4772728,
.max_bus = 12000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 1024,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Sanyo SX-16",
.internal_name = "sansx16",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_sansx16_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Schneider EuroPC",
.internal_name = "europc",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_europc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088_EUROPC,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_XTA | MACHINE_MOUSE,
.ram = {
.min = 512,
.max = 640,
.step = 128
},
.nvrmask = 15,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Super PC/Turbo XT",
.internal_name = "pcxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_pcxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Tandy 1000 SX",
.internal_name = "tandy",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_tandy1000sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 384,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_tandy_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Tandy 1000 HX",
.internal_name = "tandy1000hx",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_tandy1000hx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_tandy_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_device_hx,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Toshiba T1000",
.internal_name = "t1000",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_t1000_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO,
.ram = {
.min = 512,
.max = 1280,
.step = 768
},
.nvrmask = 63,
.kbc_device = &keyboard_xt_t1x00_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &t1000_video_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Vendex HeadStart Turbo 888-XT",
.internal_name = "vendex",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_vendex_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 768,
.step = 256
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#ifdef USE_LASERXT
{
.name = "[8088] VTech Laser Turbo XT",
.internal_name = "ltxt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_laserxt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 256
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#endif /* USE_LASERXT */
/* Has a standard PS/2 KBC (so, use IBM PS/2 Type 1). */
{
.name = "[8088] Xi8088",
.internal_name = "xi8088",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_xi8088_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 1024,
.step = 128
},
.nvrmask = 127,
.kbc_device = &keyboard_ps2_xi8088_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = &xi8088_device,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Z-NIX PC-1600",
.internal_name = "znic",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_znic_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Zenith Data Systems Z-151/152/161",
.internal_name = "zdsz151",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_z151_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_zenith_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Zenith Data Systems Z-159",
.internal_name = "zdsz159",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_z159_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_zenith_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Zenith Data Systems SupersPort (Z-184)",
.internal_name = "zdsupers",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_z184_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_zenith_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &cga_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[GC100A] Philips P3120",
.internal_name = "p3120",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_GC100A,
.init = machine_xt_p3120_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_XTA,
.ram = {
.min = 256,
.max = 768,
.step = 256
},
.nvrmask = 0,
.kbc_device = &keyboard_pc_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[V20] PC-XT",
.internal_name = "v20xt",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_v20xt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK(CPU_8088),
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 8086 Machines */
{
.name = "[8086] Amstrad PC1512",
.internal_name = "pc1512",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_pc1512_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 8000000,
.max_bus = 8000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED | MACHINE_MOUSE,
.ram = {
.min = 512,
.max = 640,
.step = 128
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_1512_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Amstrad PC1640",
.internal_name = "pc1640",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_pc1640_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MOUSE,
.ram = {
.min = 640,
.max = 640,
.step = 640
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_1640_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Amstrad PC2086",
.internal_name = "pc2086",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_pc2086_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED | MACHINE_MOUSE,
.ram = {
.min = 640,
.max = 640,
.step = 640
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_pc2086_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Amstrad PC3086",
.internal_name = "pc3086",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_pc3086_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED | MACHINE_MOUSE,
.ram = {
.min = 640,
.max = 640,
.step = 640
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_pc3086_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Amstrad PC20(0)",
.internal_name = "pc200",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_pc200_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MOUSE,
.ram = {
.min = 512,
.max = 640,
.step = 128
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_200_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Amstrad PPC512/640",
.internal_name = "ppc512",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ppc512_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MOUSE,
.ram = {
.min = 512,
.max = 640,
.step = 128
},
.nvrmask = 63,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_ppc512_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Compaq Deskpro",
.internal_name = "deskpro",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_compaq_deskpro_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_compaq_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Epson Equity LT",
.internal_name = "elt",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_elt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO,
.ram = {
.min = 640,
.max = 640,
.step = 640
},
.nvrmask = 0x3f,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Olivetti M21/24/24SP",
.internal_name = "m24",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_m24_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MOUSE | MACHINE_MFM,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 15,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &ogc_m24_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has Olivetti KBC firmware. */
{
.name = "[8086] Olivetti M240",
.internal_name = "m240",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_m240_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_MFM,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 15,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Schetmash Iskra-3104",
.internal_name = "iskra3104",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_iskra3104_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 128,
.max = 640,
.step = 128
},
.nvrmask = 0,
.kbc_device = &keyboard_xtclone_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Tandy 1000 SL/2",
.internal_name = "tandy1000sl2",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_tandy1000sl2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO_FIXED,
.ram = {
.min = 512,
.max = 768,
.step = 128
},
.nvrmask = 0,
.kbc_device = NULL /* TODO: No specific kbd_device yet */,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &vid_device_sl,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Toshiba T1200",
.internal_name = "t1200",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_xt_t1200_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MFM,
.ram = {
.min = 1024,
.max = 2048,
.step = 1024
},
.nvrmask = 63,
.kbc_device = &keyboard_xt_t1x00_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &t1200_video_device,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8086] Victor V86P",
.internal_name = "v86p",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_v86p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_VIDEO | MACHINE_MFM,
.ram = {
.min = 512,
.max = 1024,
.step = 128
},
.nvrmask = 127,
.kbc_device = &keyboard_xt_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#ifdef USE_LASERXT
{
.name = "[8086] VTech Laser XT3",
.internal_name = "lxt3",
.type = MACHINE_TYPE_8086,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_lxt3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_8086,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 256
},
.nvrmask = 0,
.kbc_device = &keyboard_xt_lxt3_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#endif /* USE_LASERXT */
/* 286 AT machines */
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] IBM AT",
.internal_name = "ibmat",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_ibm_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 8000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 512,
.step = 256
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[ISA] IBM PS/1 model 2011",
.internal_name = "ibmps1es",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps1_m2011_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 10000000,
.max_bus = 10000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_XTA | MACHINE_VIDEO_FIXED,
.ram = {
.min = 512,
.max = 15360,
.step = 512
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = &ps1_2011_device,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[ISA] IBM PS/2 model 30-286",
.internal_name = "ibmps2_m30_286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_m30_286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286 | CPU_PKG_486SLC_IBM,
.block = CPU_BLOCK_NONE,
.min_bus = 10000000,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_XTA | MACHINE_VIDEO_FIXED,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] IBM XT Model 286",
.internal_name = "ibmxt286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_ibmxt286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 6000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 640,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* AMI BIOS for a chipset-less machine, most likely has AMI 'F' KBC firmware. */
{
.name = "[ISA] AMI IBM AT",
.internal_name = "ibmatami",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_ibmatami_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 512,
.step = 256
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to the
IBM AT KBC firmware unless evidence emerges of any proprietary commands. */
{
.name = "[ISA] Commodore PC 30 III",
.internal_name = "cmdpc30",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_at_cmdpc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 12500000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 640,
.max = 14912,
.step = 64
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Compaq KBC firmware. */
{
.name = "[ISA] Compaq Portable II",
.internal_name = "portableii",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_at_portableii_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 16000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 640,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Compaq KBC firmware. */
{
.name = "[ISA] Compaq Portable III",
.internal_name = "portableiii",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_at_portableiii_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 16000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 640,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &compaq_plasma_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] MR BIOS 286 clone",
.internal_name = "mr286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_mr286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] NCR PC8/810/710/3390/3392",
.internal_name = "pc8",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_pc8_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Chips & Technologies KBC firmware. */
{
.name = "[ISA] Wells American A*Star",
.internal_name = "wellamerastar",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_wellamerastar_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 14000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 1024,
.step = 512
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#ifdef USE_OLIVETTI
/* Has Olivetti KBC firmware. */
{
.name = "[ISA] Olivetti M290",
.internal_name = "m290",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_at_m290_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 640,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#endif /* USE_OLIVETTI */
#ifdef USE_OPEN_AT
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] OpenAT",
.internal_name = "openat",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_openat_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 15872,
.step = 128
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#endif /* USE_OPEN_AT */
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] Phoenix IBM AT",
.internal_name = "ibmatpx",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_ibmatpx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 512,
.step = 256
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Quadtel KBC firmware. */
{
.name = "[ISA] Quadtel IBM AT",
.internal_name = "ibmatquadtel",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_ibmatquadtel_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 512,
.step = 256
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a Siemens proprietary KBC which is completely undocumented. */
{
.name = "[ISA] Siemens PCD-2L",
.internal_name = "siemens",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_siemens_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 6000000,
.max_bus = 12500000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 256,
.max = 15872,
.step = 128
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has Toshiba's proprietary KBC, which is already implemented. */
{
.name = "[ISA] Toshiba T3100e",
.internal_name = "t3100e",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_at_t3100e_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO_FIXED,
.ram = {
.min = 1024,
.max = 5120,
.step = 256
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Quadtel KBC firmware. */
{
.name = "[GC103] Quadtel 286 clone",
.internal_name = "quadt286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_GC103,
.init = machine_at_quadt286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_SOFTFLOAT_ONLY,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Most likely has AMI 'F' KBC firmware. */
{
.name = "[GC103] TriGem 286M",
.internal_name = "tg286m",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_GC103,
.init = machine_at_tg286m_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has "AMI KEYBOARD BIOS", most likely 'F'. */
{
.name = "[NEAT] DataExpert 286",
.internal_name = "ami286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_neat_ami_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* has an Award-branded KBC controller */
{
.name = "[NEAT] Hyundai Super-286C",
.internal_name = "super286c",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_super286c_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 1024,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[NEAT] NCR 3302",
.internal_name = "3302",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_3302_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[NEAT] Arche AMA-2010",
.internal_name = "px286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_px286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Chips & Technologies KBC firmware. */
{
.name = "[SCAT] GW-286CT GEAR",
.internal_name = "gw286ct",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_gw286ct_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 512,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[SCAT] Goldstar GDC-212M",
.internal_name = "gdc212m",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_gdc212m_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE,
.ram = {
.min = 512,
.max = 4096,
.step = 512
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[SCAT] Hyundai Solomon 286KP",
.internal_name = "award286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_award286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[SCAT] Hyundai Super-286TR",
.internal_name = "super286tr",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_super286tr_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[SCAT] Samsung SPC-4200P",
.internal_name = "spc4200p",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_spc4200p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE, /* Has internal video: C&T VGA 411 */
.ram = {
.min = 512,
.max = 2048,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[SCAT] Samsung SPC-4216P",
.internal_name = "spc4216p",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_spc4216p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 5120,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[SCAT] Samsung SPC-4620P",
.internal_name = "spc4620p",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_spc4620p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 5120,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[SCAT] Samsung Deskmaster 286",
.internal_name = "deskmaster286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_deskmaster286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE, /* Has internal video: C&T VGA 411 */
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[SCAT] Senor Science Co. SCAT-286-003",
.internal_name = "senorscat286",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_senor_scat286_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 4096,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 286 machines that utilize the MCA bus */
/* Has IBM PS/2 Type 2 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 50",
.internal_name = "ibmps2_m50",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_50_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286 | CPU_PKG_486SLC_IBM,
.block = CPU_BLOCK_NONE,
.min_bus = 10000000,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 10240,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 2 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 60",
.internal_name = "ibmps2_m60",
.type = MACHINE_TYPE_286,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_60_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_286 | CPU_PKG_486SLC_IBM,
.block = CPU_BLOCK_NONE,
.min_bus = 10000000,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 10240,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 386SX machines */
/* ISA slots available because an official IBM expansion for that existed. */
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[ISA] IBM PS/1 model 2121",
.internal_name = "ibmps1_2121",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps1_m2121_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 2048,
.max = 6144,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] NCR PC916SX",
.internal_name = "pc916sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_pc916sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Quadtel KBC firmware. */
{
.name = "[ISA] QTC-SXM KT X20T02/HI",
.internal_name = "quadt386sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_quadt386sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[ALi M1217] Acrosser AR-B1374",
.internal_name = "arb1374",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1217,
.init = machine_at_arb1374_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the AMIKey-2 KBC. */
{
.name = "[ALi M1217] AAEON SBC-350A",
.internal_name = "sbc350a",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1217,
.init = machine_at_sbc350a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[ALi M1217] Flytech A36",
.internal_name = "flytech386",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1217,
.init = machine_at_flytech386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &tvga8900d_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a JetKey KBC without version, shows up as a 'H'. */
{
.name = "[ALi M1217] Chaintech 325AX",
.internal_name = "325ax",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1217,
.init = machine_at_325ax_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a JetKey KBC without version, shows up as a 'H'. */
{
.name = "[ALi M1217] Chaintech 325AX (MR BIOS)",
.internal_name = "mr1217",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1217,
.init = machine_at_mr1217_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[ALI M1409] Acer 100T",
.internal_name = "acer100t",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M1409,
.init = machine_at_acer100t_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 16000000,
.max_bus = 25000000, /* Limited to 25 due a inaccurate cpu speed */
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0,
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO , /* Machine has internal OTI 077 Video card*/
.ram = {
.min = 2048,
.max = 16256,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &oti077_acer100t_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[ALi M6117] Acrosser PJ-A511M",
.internal_name = "pja511m",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M6117,
.init = machine_at_pja511m_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_M6117,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[ALi M6117] Protech ProX-1332",
.internal_name = "prox1332",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_ALI_M6117,
.init = machine_at_prox1332_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_M6117,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an AMI KBC firmware, the only photo of this is too low resolution
for me to read what's on the KBC chip, so I'm going to assume AMI 'F'
based on the other known HT18 AMI BIOS strings. */
{
.name = "[HT18] Arche AMA-932J",
.internal_name = "ama932j",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_HT18,
.init = machine_at_ama932j_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &oti067_ama932j_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has an unknown KBC firmware with commands B8 and BB in the style of
Phoenix MultiKey and AMIKey-3(!), but also commands E1 and EA with
unknown functions. */
{
.name = "[Intel 82335] ADI 386SX",
.internal_name = "adi386sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_INTEL_82335,
.init = machine_at_adi386sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an AMI Keyboard BIOS PLUS KBC firmware ('8'). */
{ .name = "[Intel 82335] Shuttle 386SX",
.internal_name = "shuttle386sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_INTEL_82335,
.init = machine_at_shuttle386sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to
the IBM PS/2 Type 1 KBC firmware unless evidence emerges of any
proprietary commands. */
{
.name = "[NEAT] Commodore SL386SX-16",
.internal_name = "cmdsl386sx16",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_cmdsl386sx16_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE,
.ram = {
.min = 1024,
.max = 8192,
.step = 512
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[NEAT] DTK PM-1630C",
.internal_name = "dtk386",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_NEAT,
.init = machine_at_neat_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[OPTi 291] DTK PPM-3333P",
.internal_name = "awardsx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_OPTI_291,
.init = machine_at_awardsx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Commodore (CBM) KBC firmware, to be implemented as identical to
the IBM PS/2 Type 1 KBC firmware unless evidence emerges of any
proprietary commands. */
{
.name = "[SCAMP] Commodore SL386SX-25",
.internal_name = "cmdsl386sx25",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_VLSI_SCAMP,
.init = machine_at_cmdsl386sx25_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 8192,
.step = 512
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5402_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* The closest BIOS string I find to this one's, differs only in one part,
and ends in -8, so I'm going to assume that this, too, has an AMI '8'
(AMI Keyboard BIOS Plus) KBC firmware. */
{
.name = "[SCAMP] DataExpert 386SX",
.internal_name = "dataexpert386sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_VLSI_SCAMP,
.init = machine_at_dataexpert386sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 10000000,
.max_bus = 25000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[SCAMP] Samsung SPC-6033P",
.internal_name = "spc6033p",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_VLSI_SCAMP,
.init = machine_at_spc6033p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 2048,
.max = 12288,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &ati28800k_spc6033p_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has an unknown AMI KBC firmware, I'm going to assume 'F' until a
photo or real hardware BIOS string is found. */
{
.name = "[SCAT] Kaimei KMX-C-02",
.internal_name = "kmxc02",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_SCAT,
.init = machine_at_kmxc02_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 512,
.max = 16384,
.step = 512
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Quadtel KBC firmware. */
{
.name = "[WD76C10] Amstrad MegaPC",
.internal_name = "megapc",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_WD76C10,
.init = machine_at_wd76c10_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 16000000,
.max_bus = 25000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 386SX machines which utilize the MCA bus */
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 55SX",
.internal_name = "ibmps2_m55sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_55sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 8192,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 65SX",
.internal_name = "ibmps2_m65sx",
.type = MACHINE_TYPE_386SX,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_65sx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386SX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 8192,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486SLC machines */
/* 486SLC machines with just the ISA slot */
/* Has AMIKey H KBC firmware. */
{
.name = "[OPTi 283] RYC Leopard LX",
.internal_name = "rycleopardlx",
.type = MACHINE_TYPE_486SLC,
.chipset = MACHINE_CHIPSET_OPTI_283,
.init = machine_at_rycleopardlx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_486SLC_IBM,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 386DX machines */
/* Has a Jetkey V3, which identifies as a 'B'. */
{
.name = "[ACC 2168] Juko AT046DX3",
.internal_name = "acc386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_ACC_2168,
.init = machine_at_acc386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an AMI Keyboard BIOS PLUS KBC firmware ('8'). */
{
.name = "[C&T 386] ECS 386/32",
.internal_name = "ecs386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_CT_386,
.init = machine_at_ecs386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[C&T 386] Samsung SPC-6000A",
.internal_name = "spc6000a",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_CT_386,
.init = machine_at_spc6000a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses Compaq KBC firmware. */
{
.name = "[ISA] Compaq Deskpro 386 (September 1986)",
.internal_name = "deskpro386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_deskpro386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX_DESKPRO386,
.block = CPU_BLOCK(CPU_486DLC, CPU_RAPIDCAD),
.min_bus = 16000000,
.max_bus = 25000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[ISA] Compaq Deskpro 386 (May 1988)",
.internal_name = "deskpro386_05_1988",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_deskpro386_05_1988_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX_DESKPRO386,
.block = CPU_BLOCK(CPU_486DLC, CPU_RAPIDCAD),
.min_bus = 16000000,
.max_bus = 25000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[ISA] Compaq Portable III (386)",
.internal_name = "portableiii386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_portableiii386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 20000000,
.max_bus = 20000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_IDE | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 14336,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &compaq_plasma_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] Micronics 09-00021",
.internal_name = "micronics386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_micronics386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 512,
.max = 8192,
.step = 128
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM AT KBC firmware. */
{
.name = "[ISA] Tandy 4000",
.internal_name = "tandy4000",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_at_tandy4000_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Lance LT38C41 with AMI Megakey P KBC firmware */
{
.name = "[ALi M1429] ECS Panda 386V",
.internal_name = "ecs386v",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_ALI_M1429,
.init = machine_at_ecs386v_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0,
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024,
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey 'F' KBC firmware. */
{
.name = "[OPTi 391] DataExpert 386WB",
.internal_name = "dataexpert386wb",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_OPTI_391,
.init = machine_at_dataexpert386wb_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX, /* Actual machine only supports 386DXes */
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The board has a "ASII KB-100" which I was not able to find any information about,
but the BIOS sends commands C9 without a parameter and D5, both of which are
Phoenix MultiKey commands. */
{
.name = "[OPTi 495] U-Board OPTi 495SLC",
.internal_name = "award495",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_OPTI_495,
.init = machine_at_opti495_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX, /* Actual machine only supports 386DXes */
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey F KBC firmware. */
{
.name = "[SiS 310] ASUS ISA-386C",
.internal_name = "asus386",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_SIS_310,
.init = machine_at_asus386_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 386DX machines which utilize the MCA bus */
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 80 (type 2)",
.internal_name = "ibmps2_m80",
.type = MACHINE_TYPE_386DX,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_80_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_486BL,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 386DX/486 machines */
/* Has AMIKey F KBC firmware. */
{
.name = "[OPTi 495] DataExpert SX495",
.internal_name = "ami495",
.type = MACHINE_TYPE_386DX_486,
.chipset = MACHINE_CHIPSET_OPTI_495,
.init = machine_at_opti495_ami_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 25000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey F KBC firmware (it's just the MR BIOS for the above machine). */
{
.name = "[OPTi 495] DataExpert SX495 (MR BIOS)",
.internal_name = "mr495",
.type = MACHINE_TYPE_386DX_486,
.chipset = MACHINE_CHIPSET_OPTI_495,
.init = machine_at_opti495_mr_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 25000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Winbond W83C42 with unknown firmware. */
{
.name = "[ALi M1429G] DataExpert EXP4349",
.internal_name = "exp4349",
.type = MACHINE_TYPE_386DX_486,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_exp4349_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 49152,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 70 (type 3)",
.internal_name = "ibmps2_m70_type3",
.type = MACHINE_TYPE_386DX_486,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_70_type3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 80 (type 3)",
.internal_name = "ibmps2_m80_type3",
.type = MACHINE_TYPE_386DX_486,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_80_axx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_386DX | CPU_PKG_486BL | CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines - Socket 1 */
/* Has AMI KF KBC firmware. */
{
.name = "[ZyMOS Poach] Genoa Unknown 486",
.internal_name = "genoa486",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_ZYMOS_POACH,
.init = machine_at_genoa486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI KF KBC firmware. */
{
.name = "[OPTi 381] Gigabyte GA-486L",
.internal_name = "ga486l",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_OPTI_381,
.init = machine_at_ga486l_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 16384,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has JetKey 5 KBC Firmware - but the BIOS string ends in a hardcoded -F, and
the BIOS also explicitly expects command A1 to return a 'F', so it looks like
the JetKey 5 is a clone of AMIKey type F. */
{
.name = "[CS4031] AMI 486 CS4031",
.internal_name = "cs4031",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_CT_CS4031,
.init = machine_at_cs4031_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses some variant of Phoenix MultiKey/42 as the Intel 8242 chip has a Phoenix
copyright. */
{
.name = "[OPTi 895] Mylex MVI486",
.internal_name = "mvi486",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_mvi486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI KF KBC firmware. */
{
.name = "[SiS 401] ASUS ISA-486",
.internal_name = "isa486",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_SIS_401,
.init = machine_at_isa486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware, per the screenshot in "How computers & MS-DOS work". */
{
.name = "[SiS 401] Chaintech 433SC",
.internal_name = "sis401",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_SIS_401,
.init = machine_at_sis401_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey F KBC firmware, per a photo of a monitor with the BIOS screen on
eBay. */
{
.name = "[SiS 460] ABIT AV4",
.internal_name = "av4",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_SIS_460,
.init = machine_at_av4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The chip is a Lance LT38C41, a clone of the Intel 8041, and the BIOS sends
commands BC, BD, and C9 which exist on both AMIKey and Phoenix MultiKey/42,
but it does not write a byte after C9, which is consistent with AMIKey, so
this must have some form of AMIKey. */
{
.name = "[VIA VT82C495] FIC 486-VC-HD",
.internal_name = "486vchd",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_VIA_VT82C495,
.init = machine_at_486vchd_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 64512,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VLSI VL82C113A SCAMP Combination I/O which holds the KBC. */
{
.name = "[VLSI 82C480] HP Vectra 486VL",
.internal_name = "vect486vl",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_VLSI_VL82C480,
.init = machine_at_vect486vl_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 2048,
.max = 32768,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL, /*Has SIO (sorta): VLSI VL82C113A SCAMP Combination I/O*/
.vid_device = &gd5428_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a standard IBM PS/2 KBC firmware or a clone thereof. */
{
.name = "[VLSI 82C481] Siemens Nixdorf D824",
.internal_name = "d824",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_VLSI_VL82C481,
.init = machine_at_d824_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 2048,
.max = 32768,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5428_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 70 (type 4)",
.internal_name = "ibmps2_m70_type4",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_70_type4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK(CPU_i486SX, CPU_i486SX_SLENH, CPU_Am486SX, CPU_Cx486S),
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO | MACHINE_SOFTFLOAT_ONLY,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines - Socket 2 */
/* 486 machines with just the ISA slot */
/* Uses some variant of Phoenix MultiKey/42 as the BIOS sends keyboard controller
command C7 (OR input byte with received data byte). */
{
.name = "[ACC 2168] Packard Bell PB410A",
.internal_name = "pb410a",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_ACC_2168,
.init = machine_at_pb410a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 4096,
.max = 36864,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses an ACER/NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware (V4.01H). */
{
.name = "[ALi M1429G] Acer A1G",
.internal_name = "acera1g",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_acera1g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 4096,
.max = 36864,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5428_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[ALi M1429G] Kaimei SA-486 VL-BUS M.B.",
.internal_name = "win486",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_winbios1429_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F.
It also has those Ex commands also seen on the VIA VT82C42N (the BIOS
supposedly sends command EF.
The board was also seen in 2003 with a -H string - perhaps someone swapped
the KBC? */
{
.name = "[ALi M1429] Olystar LIL1429",
.internal_name = "ali1429",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_ALI_M1429,
.init = machine_at_ali1429_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a standalone AMI Megakey 1993, which is type 'P'. */
{
.name = "[IMS 8848] Tekram G486IP",
.internal_name = "g486ip",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_IMS_8848,
.init = machine_at_g486ip_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey-2 'H' KBC firmware. */
{
.name = "[OPTi 499] Alaris COUGAR 486BL",
.internal_name = "cougar",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_OPTI_499,
.init = machine_at_cougar_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3 | CPU_PKG_486BL,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Uses an Intel KBC with Phoenix MultiKey KBC firmware. */
{
.name = "[SiS 461] DEC DECpc LPV",
.internal_name = "decpclpv",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_SIS_461,
.init = machine_at_decpclpv_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_86c805_onboard_vlb_device,
.snd_device = NULL,
.net_device = NULL
},
/* The BIOS does not send any non-standard keyboard controller commands and wants
a PS/2 mouse, so it's an IBM PS/2 KBC (Type 1) firmware. */
{
.name = "[SiS 461] IBM PS/ValuePoint 433DX/Si",
.internal_name = "valuepoint433",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_SIS_461,
.init = machine_at_valuepoint433_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI MegaKey KBC. */
{
.name = "[i420TX] J-Bond PCI400C-A",
.internal_name = "pci400ca",
.type = MACHINE_TYPE_486_S2,
.chipset = MACHINE_CHIPSET_INTEL_420TX,
.init = machine_at_pci400ca_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_SCSI,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = &keyboard_ps2_ami_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines - Socket 3 */
/* 486 machines with just the ISA slot */
/* Has a Fujitsu MBL8042H KBC. */
{
.name = "[Contaq 82C596A] A-Trend 4GPV5",
.internal_name = "4gpv5",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_CONTAQ_82C596,
.init = machine_at_4gpv5_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI MegaKey KBC firmware. */
{
.name = "[Contaq 82C597] Visionex Green-B",
.internal_name = "greenb",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_CONTAQ_82C597,
.init = machine_at_greenb_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Version 1.0 has an AMIKEY-2, version 2.0 has a VIA VT82C42N KBC. */
{
.name = "[OPTi 895] Jetway J-403TG",
.internal_name = "403tg",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_403tg_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{
.name = "[OPTi 895] Jetway J-403TG Rev D",
.internal_name = "403tg_d",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_403tg_d_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{
.name = "[OPTi 895] Jetway J-403TG Rev D (MR BIOS)",
.internal_name = "403tg_d_mr",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_403tg_d_mr_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* has a Phoenix PLCC Multikey copyrighted 1993, version unknown. */
{
.name = "[OPTi 895] Packard Bell PB450",
.internal_name = "pb450",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_pb450_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE_DUAL | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5428_vlb_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* Uses an NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware. */
{
.name = "[SiS 461] Acer V10",
.internal_name = "acerv10",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_461,
.init = machine_at_acerv10_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_VLB,
.flags = MACHINE_IDE | MACHINE_APM, /* Machine has internal SCSI: Adaptec AIC-6360 */
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The BIOS string ends in -U, unless command 0xA1 (AMIKey get version) returns an
'F', in which case, it ends in -F, so it has an AMIKey F KBC firmware.
The photo of the board shows an AMIKey KBC which is indeed F. */
{
.name = "[SiS 471] ABIT AB-AH4",
.internal_name = "win471",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_win471_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey-2 'H' keyboard BIOS. */
{
.name = "[SiS 471] AOpen Vi15G",
.internal_name = "vi15g",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_vi15g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 471] ASUS VL/I-486SV2G (GX4)",
.internal_name = "vli486sv2g",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_vli486sv2g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has JetKey 5 KBC Firmware which looks like it is a clone of AMIKey type F. */
{
.name = "[SiS 471] DTK PKM-0038S E-2",
.internal_name = "dtk486",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_dtk486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Lance LT38C41L with AMIKey F keyboard BIOS. */
{
.name = "[SiS 471] Epox GXA486SG",
.internal_name = "ami471",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_ami471_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has MR (!) KBC firmware, which is a clone of the standard IBM PS/2 KBC firmware. */
{
.name = "[SiS 471] SiS VL-BUS 471 REV. A1",
.internal_name = "px471",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_px471_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* TriGem AMIBIOS Pre-Color with TriGem AMI 'Z' keyboard controller */
{
.name = "[SiS 471] TriGem 486G",
.internal_name = "tg486g",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_tg486g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_VLB,
.flags = MACHINE_IDE | MACHINE_APM, /* Has internal video: Western Digital WD90C33-ZZ */
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Unknown revision phoenix 1993 multikey */
{
.name = "[SiS 471] DEC Venturis 4xx",
.internal_name = "dvent4xx",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_471,
.init = machine_at_dvent4xx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE_DUAL | MACHINE_SUPER_IO | MACHINE_APM | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_phoenix_trio32_onboard_vlb_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[ALi M1429G] ECS AL486",
.internal_name = "ecsal486",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_ecsal486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 98304,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This uses a VIA VT82C42N KBC, which is a clone of type 'F' with additional commands */
{
.name = "[ALi M1429G] Lanner Electronics AP-4100AA",
.internal_name = "ap4100aa",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_ap4100aa_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_AT,
.flags = MACHINE_SUPER_IO | MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* JETKey V5.0 */
{
.name = "[ALi M1429G] A-Trend ATC-1762",
.internal_name = "atc1762",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_atc1762_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 40960,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines which utilize the PCI bus */
/* Machine with ALi M1429G chipset and M1435 southbridge */
/* Has an AMIKEY-2 KBC. */
{
.name = "[ALi M1429G] MSI MS-4134",
.internal_name = "ms4134",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_ms4134_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* TriGem machine with M1429G and PhoenixBIOS */
{
.name = "[ALi M1429G] TriGem 486GP",
.internal_name = "tg486gp",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1429G,
.init = machine_at_tg486gp_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[ALi M1489] AAEON SBC-490",
.internal_name = "sbc490",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_sbc490_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = &tgui9440_onboard_pci_device,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC. */
{
.name = "[ALi M1489] ABIT AB-PB4",
.internal_name = "abpb4",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_abpb4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI, /* Machine has a PISA slot */
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC.
The BIOS string always ends in -U, but the BIOS will send AMIKey commands 0xCA
and 0xCB if command 0xA1 returns a letter in the 0x5x or 0x7x ranges, so I'm
going to give it an AMI 'U' KBC. */
{
.name = "[ALi M1489] AMI WinBIOS 486 PCI",
.internal_name = "win486pci",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_win486pci_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC.
The known BIOS string ends in -E, and the BIOS returns whatever command 0xA1
returns (but only if command 0xA1 is instant response), so said ALi keyboard
controller likely returns 'E'. */
{
.name = "[ALi M1489] MSI MS-4145",
.internal_name = "ms4145",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_ms4145_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an ALi M5042 keyboard controller with Phoenix MultiKey/42 v1.40 firmware. */
{
.name = "[ALi M1489] ESA TF-486",
.internal_name = "tf486",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_tf486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an ALi M5042 with phoenix firmware like the ESA TF-486. */
{
.name = "[ALi M1489] Acrosser AR-B1476",
.internal_name = "arb1476",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_ALI_M1489,
.init = machine_at_arb1476_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_SUPER_IO | MACHINE_IDE | MACHINE_APM, /* Has onboard video: C&T F65545 */
.ram = {
.min = 1024,
.max = 32768,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[OPTi 802G] IBM Aptiva 510/710/Vision",
.internal_name = "aptiva510",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_aptiva510_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3_PC330,
.block = CPU_BLOCK_NONE,
.min_bus = 25000000,
.max_bus = 33333333,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5430_onboard_vlb_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[OPTi 802G] IBM PC 330 (type 6573)",
.internal_name = "pc330_6573",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_OPTI_895_802G,
.init = machine_at_pc330_6573_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3_PC330,
.block = CPU_BLOCK_NONE,
.min_bus = 25000000,
.max_bus = 33333333,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5430_onboard_vlb_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i420EX] ASUS PVI-486AP4",
.internal_name = "486ap4",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420EX,
.init = machine_at_486ap4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i420EX] Intel Classic/PCI ED",
.internal_name = "ninja",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420EX,
.init = machine_at_ninja_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Phoenix Multikey/42 PS/2 KBC, but unknown version */
{
.name = "[i420EX] Anigma BAT4IP3e",
.internal_name = "bat4ip3e",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420EX,
.init = machine_at_bat4ip3e_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i420EX] Advanced Integration Research 486PI",
.internal_name = "486pi",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420EX,
.init = machine_at_486pi_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_SUPER_IO | MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* absolutely no KBC info */
{
.name = "[i420EX] ICS SB486P",
.internal_name = "sb486p",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420EX,
.init = machine_at_sb486p_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* I'm going to assume this as an AMIKey-2 like the other two 486SP3's. */
{
.name = "[i420TX] ASUS PCI/I-486SP3",
.internal_name = "486sp3",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420TX,
.init = machine_at_486sp3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE | MACHINE_SCSI | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i420TX] Intel Classic/PCI",
.internal_name = "alfredo",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420TX,
.init = machine_at_alfredo_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to another string seen on the UH19 website, this has AMI 'H' KBC. */
{
.name = "[i420TX] AMI Super Voyager PCI",
.internal_name = "amis76",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420TX,
.init = machine_at_amis76_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. Also has a
SST 29EE010 Flash chip. */
{
.name = "[i420ZX] ASUS PCI/I-486SP3G",
.internal_name = "486sp3g",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_INTEL_420ZX,
.init = machine_at_486sp3g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_SCSI | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This most likely has a standalone AMI Megakey 1993, which is type 'P', like the below Tekram board. */
{
.name = "[IMS 8848] J-Bond PCI400C-B",
.internal_name = "pci400cb",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_IMS_8848,
.init = machine_at_pci400cb_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 496] ASUS PVI-486SP3C",
.internal_name = "486sp3c",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_486sp3c_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 261120,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 496] Lucky Star LS-486E",
.internal_name = "ls486e",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_ls486e_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_BUS_PS2_LATCH | MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[SiS 496] Micronics M4Li",
.internal_name = "m4li",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_m4li_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Revision 1 has a Lance LT38C41L, revision 2 has a Holtek HT6542B. Another variant with a Bestkey KBC might exist as well. */
{
.name = "[SiS 496] Rise Computer R418",
.internal_name = "r418",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_r418_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_BUS_PS2_LATCH | MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 261120,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a Holtek HT6542B KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{
.name = "[SiS 496] Soyo 4SAW2",
.internal_name = "4saw2",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_4saw2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK(CPU_i486SX, CPU_i486DX, CPU_Am486SX, CPU_Am486DX),
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 2048,
.max = 261120,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to MrKsoft, his real 4DPS has an AMIKey-2, which is an updated version
of type 'H'. There are other variants of the board with Holtek HT6542B KBCs. */
{
.name = "[SiS 496] Zida Tomato 4DP",
.internal_name = "4dps",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_4dps_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 2048,
.max = 261120,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* AMIKEY-2 */
{
.name = "[SiS 496] MSI MS-4144",
.internal_name = "ms4144",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_SIS_496,
.init = machine_at_ms4144_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 5120, /* Hack: machine seems to break with less than 5 MBs of RAM */
.max = 131072,
.step = 1024
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the UMC 88xx on-chip KBC. */
{
.name = "[UMC 8881] A-Trend ATC-1415",
.internal_name = "atc1415",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_atc1415_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 65536,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[UMC 8881] ECS Elite UM8810P-AIO",
.internal_name = "ecs486",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_ecs486_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI | MACHINE_BUS_PS2_LATCH,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey Z(!) KBC firmware. */
{
.name = "[UMC 8881] Epson ActionPC 2600",
.internal_name = "actionpc2600",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_actionpc2600_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 262144,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the UMC 88xx on-chip KBC. All the copies of the BIOS string I can find, end in
in -H, so the UMC on-chip KBC likely emulates the AMI 'H' KBC firmware. */
{
.name = "[UMC 8881] Epson ActionTower 8400",
.internal_name = "actiontower8400",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_actiontower8400_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_SUPER_IO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_VIDEO,
.ram = {
.min = 1024,
.max = 262144,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the UMC 88xx on-chip KBC. All the copies of the BIOS string I can find, end in
in -H, so the UMC on-chip KBC likely emulates the AMI 'H' KBC firmware. */
{
.name = "[UMC 8881] PC Chips M919",
.internal_name = "m919",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_m919_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. Uses a mysterious I/O port C05. */
{
.name = "[UMC 8881] Samsung SPC7700P-LW",
.internal_name = "spc7700plw",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_spc7700plw_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a Holtek KBC. */
{
.name = "[UMC 8881] Shuttle HOT-433A",
.internal_name = "hot433a",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_UMC_UM8881,
.init = machine_at_hot433a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 262144,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C406 KBC+RTC that likely has identical commands to the VT82C42N. */
{
.name = "[VIA VT82C496G] DFI G486VPA",
.internal_name = "g486vpa",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_VIA_VT82C496G,
.init = machine_at_g486vpa_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[VIA VT82C496G] FIC VIP-IO2",
.internal_name = "486vipio2",
.type = MACHINE_TYPE_486_S3,
.chipset = MACHINE_CHIPSET_VIA_VT82C496G,
.init = machine_at_486vipio2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET3,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 1024,
.max = 131072,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines - Miscellaneous */
/* 486 machines which utilize the PCI bus */
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Client] ITOX STAR",
.internal_name = "itoxstar",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_CLIENT,
.init = machine_at_itoxstar_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 75000000,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 1.0,
.max_multi = 1.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Consumer-II] Acrosser AR-B1423C",
.internal_name = "arb1423c",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_CONSUMER_II,
.init = machine_at_arb1423c_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM, /* Machine has internal video: ST STPC Atlas */
.ram = {
.min = 32768,
.max = 163840,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Consumer-II] Acrosser AR-B1479",
.internal_name = "arb1479",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_CONSUMER_II,
.init = machine_at_arb1479_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, /* Machine has internal video: ST STPC Atlas */
.ram = {
.min = 32768,
.max = 163840,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Consumer-II] Lanner Electronics IAC-H488",
.internal_name = "iach488",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_CONSUMER_II,
.init = machine_at_iach488_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2,
.flags = MACHINE_IDE | MACHINE_APM, /* Machine has internal video: ST STPC Atlas and NIC: Realtek RTL8139C+ */
.ram = {
.min = 32768,
.max = 131072,
.step = 32768
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Elite] Advantech PCM-9340",
.internal_name = "pcm9340",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_ELITE,
.init = machine_at_pcm9340_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 32768,
.max = 98304,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[STPC Atlas] AAEON PCM-5330",
.internal_name = "pcm5330",
.type = MACHINE_TYPE_486_MISC,
.chipset = MACHINE_CHIPSET_STPC_ATLAS,
.init = machine_at_pcm5330_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_STPC,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 2.0,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 32768,
.max = 131072,
.step = 32768
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Socket 4 machines */
/* 430LX */
/* Has AMIKey H KBC firmware (AMIKey-2), per POST screen with BIOS string
shown in the manual. Has PS/2 mouse support with serial-style (DB9)
connector.
The boot block for BIOS recovery requires an unknown bit on port 805h
to be clear. */
{
.name = "[i430LX] AMI Excalibur PCI Pentium",
.internal_name = "excaliburpci",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_excaliburpci_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_APM, /* Machine has internal SCSI */
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey F KBC firmware (AMIKey). */
{
.name = "[i430LX] ASUS P/I-P5MP3",
.internal_name = "p5mp3",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_p5mp3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_BUS_PS2_LATCH | MACHINE_PCI,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 196608,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[i430LX] Dell Dimension XPS P60",
.internal_name = "dellxp60",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_dellxp60_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[i430LX] Dell OptiPlex 560/L",
.internal_name = "opti560l",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_opti560l_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware.
This is basically an Intel Batman (*NOT* Batman's Revenge) with a fancier
POST screen */
{
.name = "[i430LX] AMBRA DP60 PCI",
.internal_name = "ambradp60",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_ambradp60_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[i430LX] IBM PS/ValuePoint P60",
.internal_name = "valuepointp60",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_valuepointp60_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_VIDEO_8514A | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &mach32_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i430LX] Intel Premiere/PCI",
.internal_name = "revenge",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_revenge_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI MegaKey 'H' KBC firmware. */
{
.name = "[i430LX] Gigabyte GA-586IS",
.internal_name = "586is",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_586is_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i430LX] Packard Bell PB520R",
.internal_name = "pb520r",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_INTEL_430LX,
.init = machine_at_pb520r_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 8192,
.max = 139264,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5434_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* OPTi 596/597 */
/* This uses an AMI KBC firmware in PS/2 mode (it sends command A5 with the
PS/2 "Load Security" meaning), most likely MegaKey as it sends command AF
(Set Extended Controller RAM) just like the later Intel AMI BIOS'es. */
{
.name = "[OPTi 597] AMI Excalibur VLB",
.internal_name = "excalibur",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_OPTI_547_597,
.init = machine_at_excalibur_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 60000000,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_VLB,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* OPTi 596/597/822 */
/* This has AMIKey 'F' KBC firmware. */
{
.name = "[OPTi 597] Supermicro P5VL-PCI",
.internal_name = "p5vl",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_OPTI_547_597,
.init = machine_at_p5vl_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 50x */
/* This has some form of AMI MegaKey as it uses keyboard controller command 0xCC. */
{
.name = "[SiS 501] AMI Excalibur PCI-II Pentium ISA",
.internal_name = "excaliburpci2",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_SIS_501,
.init = machine_at_excaliburpci2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 501] ASUS PCI/I-P5SP4",
.internal_name = "p5sp4",
.type = MACHINE_TYPE_SOCKET4,
.chipset = MACHINE_CHIPSET_SIS_501,
.init = machine_at_p5sp4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET4,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 5000,
.max_voltage = 5000,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Socket 5 machines */
/* 430NX */
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i430NX] Intel Premiere/PCI II",
.internal_name = "plato",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430NX,
.init = machine_at_plato_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Same as Intel Premiere PCI/II, but with a Dell OEM BIOS */
{
.name = "[i430NX] Dell Dimension XPS Pxxx",
.internal_name = "dellplato",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430NX,
.init = machine_at_dellplato_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the Phoenix MultiKey KBC firmware.
This is basically an Intel Premiere/PCI II with a fancier POST screen. */
{
.name = "[i430NX] AMBRA DP90 PCI",
.internal_name = "ambradp90",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430NX,
.init = machine_at_ambradp90_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 2048,
.max = 131072,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI 'H' KBC firmware. */
{
.name = "[i430NX] Gigabyte GA-586IP",
.internal_name = "586ip",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430NX,
.init = machine_at_586ip_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 262144,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMI MegaKey KBC firmware. */
{
.name = "[i430NX] Teknor TEK-932",
.internal_name = "tek932",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430NX,
.init = machine_at_tek932_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE | MACHINE_APM,
.ram = {
.min = 2048,
.max = 262144,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 430FX */
/* Uses an ACER/NEC 90M002A (UPD82C42C, 8042 clone) with unknown firmware (V5.0). */
{
.name = "[i430FX] Acer V30",
.internal_name = "acerv30",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_acerv30_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey F KBC firmware. */
{
.name = "[i430FX] AMI Apollo",
.internal_name = "apollo",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_apollo_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430FX] Intel Advanced/ZP",
.internal_name = "zappa",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_zappa_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The BIOS sends KBC command B3 which indicates an AMI (or VIA VT82C42N) KBC. */
{
.name = "[i430FX] NEC PowerMate V",
.internal_name = "powermatev",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_powermatev_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey Z(!) KBC firmware. */
{
.name = "[i430FX] TriGem Hawk",
.internal_name = "hawk",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_hawk_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* KBC On-Chip the VT82C406MV. */
{
.name = "[i430FX] FIC PT-2000",
.internal_name = "pt2000",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_pt2000_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* OPTi 596/597 */
/* This uses an AMI KBC firmware in PS/2 mode (it sends command A5 with the
PS/2 "Load Security" meaning), most likely MegaKey as it sends command AF
(Set Extended Controller RAM) just like the later Intel AMI BIOS'es. */
{
.name = "[OPTi 597] TMC PAT54PV",
.internal_name = "pat54pv",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_OPTI_547_597,
.init = machine_at_pat54pv_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_K5, CPU_5K86),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_VLB,
.flags = MACHINE_APM,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* OPTi 596/597/822 */
{
.name = "[OPTi 597] Shuttle HOT-543",
.internal_name = "hot543",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_OPTI_547_597,
.init = machine_at_hot543_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PCIV,
.flags = MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[OPTi 597] Northgate Computer Systems Elegance Pentium 90",
.internal_name = "ncselp90",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_OPTI_547_597,
.init = machine_at_ncselp90_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCIV,
.flags = MACHINE_APM | MACHINE_IDE_DUAL | MACHINE_SUPER_IO,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 85C50x */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 501] ASUS PCI/I-P54SP4",
.internal_name = "p54sp4",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_SIS_501,
.init = machine_at_p54sp4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_K5, CPU_5K86),
.min_bus = 40000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 501] BCM SQ-588",
.internal_name = "sq588",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_SIS_501,
.init = machine_at_sq588_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_PENTIUMMMX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This machine has a Winbond W83C842 KBC */
{
.name = "[SiS 501] Gemlight GMB-P54SPS",
.internal_name = "p54sps",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_SIS_501,
.init = machine_at_p54sps_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
CPU_BLOCK(CPU_PENTIUMMMX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = &keyboard_at_ami_device,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[SiS 5501] MSI MS-5109",
.internal_name = "ms5109",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_SIS_5501,
.init = machine_at_ms5109_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
CPU_BLOCK(CPU_PENTIUMMMX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey Z(!) KBC firmware. */
{
.name = "[SiS 5501] TriGem Torino",
.internal_name = "torino",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_SIS_5501,
.init = machine_at_torino_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
CPU_BLOCK(CPU_PENTIUMMMX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3520,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 1.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &tgui9660_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* UMC 889x */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[UMC 889x] Shuttle HOT-539",
.internal_name = "hot539",
.type = MACHINE_TYPE_SOCKET5,
.chipset = MACHINE_CHIPSET_UMC_UM8890BF,
.init = machine_at_hot539_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_K5, CPU_5K86),
.min_bus = 40000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3600,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Socket 7 (Single Voltage) machines */
/* 430FX */
/* This has an AMIKey-2, which is an updated version of type 'H'.
This also seems to be revision 2.1 with the FDC37C665 SIO. */
{
.name = "[i430FX] ASUS P/I-P55TP4XE",
.internal_name = "p54tp4xe",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_p54tp4xe_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3600,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i430FX] ASUS P/I-P55TP4XE (MR BIOS)",
.internal_name = "p54tp4xe_mr",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_p54tp4xe_mr_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3600,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware. The KBC itself seems to differ between an AMIKEY-2 and a Winbond W83C42. */
{
.name = "[i430FX] DataExpert EXP8551",
.internal_name = "exp8551",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_exp8551_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430FX] Gateway 2000 Thor",
.internal_name = "gw2katx",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_gw2katx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C932 Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430FX] HP Vectra VL 5 Series 4",
.internal_name = "vectra54",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_vectra54_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 2.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_phoenix_trio64_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430FX] Intel Advanced/ATX",
.internal_name = "thor",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_thor_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_phoenix_trio64vplus_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430FX] Intel Advanced/ATX (MR BIOS)",
.internal_name = "mrthor",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_mrthor_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430FX] Intel Advanced/EV",
.internal_name = "endeavor",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_endeavor_init,
.p1_handler = NULL,
.gpio_handler = machine_at_endeavor_gpio_handler,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_SOUND | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_phoenix_trio64_onboard_pci_device,
.snd_device = &sb_vibra16s_onboard_device,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i430FX] MSI MS-5119",
.internal_name = "ms5119",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_ms5119_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This most likely uses AMI MegaKey KBC firmware as well due to having the same
Super I/O chip (that has the KBC firmware on it) as eg. the Advanced/EV. */
{
.name = "[i430FX] Packard Bell PB640",
.internal_name = "pb640",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_pb640_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5440_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC. */
{
.name = "[i430FX] PC Partner MB500N",
.internal_name = "mb500n",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_mb500n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an AMI MegaKey 'H' KBC firmware (1992). */
{
.name = "[i430FX] QDI FMB",
.internal_name = "fmb",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430FX,
.init = machine_at_fmb_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 430HX */
/* Has SST Flash. */
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430HX] Acer V35N",
.internal_name = "acerv35n",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_acerv35n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3450,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 196608,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey-2 or VIA VT82C42N KBC (depending on the revision) with AMIKEY 'F' KBC firmware. */
{
.name = "[i430HX] AOpen AP53",
.internal_name = "ap53",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_ap53_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3450,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] Has a VIA 82C42N KBC, with AMIKey F KBC firmware. */
{
.name = "[i430HX] Biostar MB-8500TUC",
.internal_name = "8500tuc",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_8500tuc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 430VX */
/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430VX] Gateway 2000 Tigereye",
.internal_name = "gw2kte",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_gw2kte_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5501 */
/* Has the Lance LT38C41 KBC. */
{
.name = "[SiS 5501] Chaintech 5SBM2 (M103)",
.internal_name = "5sbm2",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_SIS_5501,
.init = machine_at_5sbm2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5511 */
/* Has AMIKey H KBC firmware (AMIKey-2). */
{
.name = "[SiS 5511] AOpen AP5S",
.internal_name = "ap5s",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_SIS_5511,
.init = machine_at_ap5s_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an SMC FDC37C669QF Super I/O. */
{
.name = "[SiS 5511] IBM PC 140 (type 6260)",
.internal_name = "pc140_6260",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_SIS_5511,
.init = machine_at_pc140_6260_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2, CPU_Cx6x86, CPU_Cx6x86L, CPU_Cx6x86MX, CPU_PENTIUMMMX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &gd5436_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware (AMIKey-2). */
{
.name = "[SiS 5511] MSI MS-5124",
.internal_name = "ms5124",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_SIS_5511,
.init = machine_at_ms5124_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has Megakey 'R' KBC */
{
.name = "[SiS 5511] AMI Atlas PCI-II",
.internal_name = "amis727",
.type = MACHINE_TYPE_SOCKET7_3V,
.chipset = MACHINE_CHIPSET_SIS_5511,
.init = machine_at_amis727_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 3380,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Socket 7 (Dual Voltage) machines */
/* 430HX */
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430HX] Acer M3A",
.internal_name = "acerm3a",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_acerm3a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_Cx6x86MX),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal SCSI */
.ram = {
.min = 8192,
.max = 196608,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware (AMIKey-2). */
{
.name = "[i430HX] ASUS P/I-P55T2P4",
.internal_name = "p55t2p4",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_p55t2p4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 83333333,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The base board has a Holtek HT6542B with the AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)",
.internal_name = "p65up5_cp55t2d",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_p65up5_cp55t2d_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has AMB */
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430HX] Micronics M7S-Hi",
.internal_name = "m7shi",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_m7shi_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430HX] Intel TC430HX",
.internal_name = "tc430hx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_tc430hx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_VIDEO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB, /* Has internal sound: Yamaha YMF701-S */
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_virge_375_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* OEM version of Intel TC430HX, has AMI MegaKey KBC firmware on the PC87306 Super I/O chip. */
{
.name = "[i430HX] Toshiba Infinia 7200",
.internal_name = "infinia7200",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_infinia7200_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_VIDEO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB, /* Has internal sound: Yamaha YMF701-S */
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_virge_375_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* OEM-only Intel CU430HX, has AMI MegaKey KBC firmware on the PC87306 Super I/O chip. */
{
.name = "[i430HX] Intel CU430HX",
.internal_name = "cu430hx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_cu430hx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 196608,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &sb_vibra16c_onboard_device,
.net_device = NULL
},
/* OEM-only Intel CU430HX, has AMI MegaKey KBC firmware on the PC87306 Super I/O chip. */
{
.name = "[i430HX] Toshiba Equium 5200D",
.internal_name = "equium5200",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_equium5200_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 196608,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &sb_vibra16c_onboard_device,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI .
Yes, this is an Intel AMI BIOS with a fancy splash screen. */
{
.name = "[i430HX] Sony Vaio PCV-90",
.internal_name = "pcv90",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_pcv90_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 196608,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] The board doesn't seem to have a KBC at all, which probably means it's an on-chip one on the PC87306 SIO.
A list on a Danish site shows the BIOS as having a -0 string, indicating non-AMI KBC firmware. */
{
.name = "[i430HX] Supermicro P55T2S",
.internal_name = "p55t2s",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_p55t2s_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 430VX */
/* This has the VIA VT82C42N or Holtek HT6542B KBC. */
{
.name = "[i430VX] AOpen AP5VM",
.internal_name = "ap5vm",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_ap5vm_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2600,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SCSI | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware (AMIKey-2) on a BestKey KBC. */
{
.name = "[i430VX] ASUS P/I-P55TVP4",
.internal_name = "p55tvp4",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_p55tvp4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has AMB */
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The BIOS does not send a single non-standard KBC command, so it must have a standard IBM
PS/2 KBC firmware or a clone thereof. */
{
.name = "[i430VX] Azza PT-5IV",
.internal_name = "5ivg",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_5ivg_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] Has AMIKey 'F' KBC firmware on a VIA VT82C42N KBC. */
{
.name = "[i430VX] Biostar MB-8500TVX-A",
.internal_name = "8500tvxa",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_8500tvxa_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2600,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C932QF Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430VX] Compaq Presario 2240",
.internal_name = "presario2240",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_presario2240_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM | MACHINE_ACPI,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_trio64v2_dx_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C931APM Super I/O chip with on-chip KBC with Compaq
KBC firmware. */
{
.name = "[i430VX] Compaq Presario 4500",
.internal_name = "presario4500",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_presario4500_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_VIDEO | MACHINE_APM | MACHINE_ACPI,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_trio64v2_dx_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430VX] Dell Hannibal+",
.internal_name = "dellhannibalp",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_dellhannibalp_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has AMIKey H KBC firmware (AMIKey-2). */
{
.name = "[i430VX] ECS P5VX-B",
.internal_name = "p5vxb",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_p5vxb_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C932FR Super I/O chip with on-chip KBC with AMI
MegaKey (revision '5') KBC firmware. */
{
.name = "[i430VX] Epox P55-VA",
.internal_name = "p55va",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_p55va_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430VX] HP Brio 80xx",
.internal_name = "brio80xx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_brio80xx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 2200,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 16384,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i430VX] Packard Bell PB680",
.internal_name = "pb680",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_pb680_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_VIDEO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_phoenix_trio64vplus_onboard_pci_device,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430VX] Packard Bell PB810",
.internal_name = "pb810",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_pb810_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has the AMIKey 'H' firmware, possibly AMIKey-2. Photos show it with a BestKey, so it
likely clones the behavior of AMIKey 'H'. */
{
.name = "[i430VX] PC Partner MB520N",
.internal_name = "mb520n",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_mb520n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2600,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Unknown PS/2 KBC. */
{
.name = "[i430HX] Radisys EPC-2102",
.internal_name = "epc2102",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430HX,
.init = machine_at_epc2102_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 83333333,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{
.name = "[i430VX] Shuttle HOT-557",
.internal_name = "430vx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430VX,
.init = machine_at_i430vx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_GAMEPORT | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 430TX */
/* The BIOS sends KBC command B8, CA, and CB, so it has an AMI KBC firmware. */
{
.name = "[i430TX] ADLink NuPRO-591/592",
.internal_name = "nupro592",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_nupro592_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 1900,
.max_voltage = 2800,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_VIDEO,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &chips_69000_onboard_device,
.snd_device = NULL,
.net_device = NULL
},
/* This has the AMIKey KBC firmware, which is an updated 'F' type (YM430TX is based on the TX97). */
{
.name = "[i430TX] ASUS TX97",
.internal_name = "tx97",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_tx97_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] Has AMI Megakey '5' KBC firmware on the SM(S)C FDC37C67x Super I/O chip. */
{
.name = "[i430TX] Gateway Tomahawk",
.internal_name = "tomahawk",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_tomahawk_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_VIDEO | MACHINE_SOUND | MACHINE_NIC | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_trio64v2_dx_onboard_pci_device,
.snd_device = &cs4236b_device,
.net_device = &pcnet_am79c973_onboard_device
},
#ifdef USE_AN430TX
/* This has the Phoenix MultiKey KBC firmware. */
{
.name = "[i430TX] Intel AN430TX",
.internal_name = "an430tx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_an430tx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
#endif /* USE_AN430TX */
/* This has the AMIKey KBC firmware, which is an updated 'F' type. */
{
.name = "[i430TX] Intel YM430TX",
.internal_name = "ym430tx",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_ym430tx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* PhoenixBIOS 4.0 Rel 6.0 for 430TX, most likely has AMI KBC of some sort. Also has onboard Yamaha YMF701 which can't be emulated yet. */
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i430TX] Micronics Thunderbolt",
.internal_name = "thunderbolt",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_thunderbolt_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK(CPU_WINCHIP, CPU_WINCHIP2),
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal sound: Yamaha YMF701-S */
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C67x Super I/O chip with on-chip KBC with Phoenix or
AMIKey-2 KBC firmware. */
{
.name = "[i430TX] NEC Mate NX MA23C",
.internal_name = "ma23c",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_ma23c_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2700,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The BIOS sends KBC command BB and expects it to output a byte, which is AMI KBC behavior.
A picture shows a VIA VT82C42N KBC though, so it could be a case of that KBC with AMI firmware. */
{
.name = "[i430TX] PC Partner MB540N",
.internal_name = "mb540n",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_mb540n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2700,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Award BIOS, PS2, EDO, SDRAM, 4 PCI, 4 ISA, VIA VT82C42N KBC */
{
.name = "[i430TX] Soltek SL-56A5",
.internal_name = "56a5",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_56a5_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 55000000,
.max_bus = 75000000,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] Has AMIKey 'H' KBC firmware. */
{
.name = "[i430TX] Supermicro P5MMS98",
.internal_name = "p5mms98",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_p5mms98_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* [TEST] Has AMIKey 'H' KBC firmware. */
{
.name = "[i430TX] TriGem Richmond",
.internal_name = "richmond",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_INTEL_430TX,
.init = machine_at_richmond_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Apollo VPX */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA VPX] FIC VA-502",
.internal_name = "ficva502",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_VPX,
.init = machine_at_ficva502_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Apollo VP3 */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA VP3] FIC PA-2012",
.internal_name = "ficpa2012",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_VP3,
.init = machine_at_ficpa2012_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 55000000,
.max_bus = 75000000,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5571 */
/* Has the SiS 5571 chipset with on-chip KBC. */
{
.name = "[SiS 5571] Daewoo CB52X-SI",
.internal_name = "cb52xsi",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5571,
.init = machine_at_cb52xsi_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the SiS 5571 chipset with on-chip KBC. */
{
.name = "[SiS 5571] MSI MS-5146",
.internal_name = "ms5146",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5571,
.init = machine_at_ms5146_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2800,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the SiS 5571 chipset with on-chip KBC. */
{
.name = "[SiS 5571] Rise R534F",
.internal_name = "r534f",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5571,
.init = machine_at_r534f_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 55000000,
.max_bus = 83333333,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 393216,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5581 */
/* Has the SiS 5581 chipset with on-chip KBC. */
{
.name = "[SiS 5581] ASUS SP97-XV",
.internal_name = "sp97xv",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5581,
.init = machine_at_sp97xv_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1572864,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the SiS 5581 chipset with on-chip KBC. */
{
.name = "[SiS 5581] BCM SQ-578",
.internal_name = "sq578",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5581,
.init = machine_at_sq578_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1572864,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5591 */
/* Has the SiS 5591 chipset with on-chip KBC. */
{
.name = "[SiS 5591] MSI MS-5172",
.internal_name = "ms5172",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_SIS_5591,
.init = machine_at_ms5172_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 75000000,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* ALi ALADDiN IV+ */
/* Has the ALi M1543 southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN IV+] MSI MS-5164",
.internal_name = "ms5164",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_IV_PLUS,
.init = machine_at_ms5164_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 83333333,
.min_voltage = 2100,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the ALi M1543 southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN IV+] PC Chips M560",
.internal_name = "m560",
.type = MACHINE_TYPE_SOCKET7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_IV_PLUS,
.init = machine_at_m560_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 83333333,
.min_voltage = 2500,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Super Socket 7 machines */
/* ALi ALADDiN V */
/* Has the ALi M1543C southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN V] ASUS P5A",
.internal_name = "p5a",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_V,
.init = machine_at_p5a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 120000000,
.min_voltage = 2000,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Is the exact same as the Matsonic MS6260S. Has the ALi M1543C southbridge
with on-chip KBC. */
{
.name = "[ALi ALADDiN V] PC Chips M579",
.internal_name = "m579",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_V,
.init = machine_at_m579_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 2000,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 1024,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* M1534c kbc */
{
.name = "[ALi ALADDiN V] Gateway Lucas",
.internal_name = "gwlucas",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_V,
.init = machine_at_gwlucas_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 2000,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_PCIONLY | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Has internal video: ATI 3D Rage Pro Turbo AGP and sound: Ensoniq ES1373 */
.ram = {
.min = 8192,
.max = 262144,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* Has the ALi M1543C southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN V] Gigabyte GA-5AA",
.internal_name = "5aa",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_V,
.init = machine_at_5aa_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 140000000,
.min_voltage = 1300,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 1024,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the ALi M1543C southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN V] Gigabyte GA-5AX",
.internal_name = "5ax",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_V,
.init = machine_at_5ax_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 140000000,
.min_voltage = 1300,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 1024,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Apollo MVP3 */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA MVP3] AOpen AX59 Pro",
.internal_name = "ax59pro",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_MVP3,
.init = machine_at_ax59pro_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 124242424,
.min_voltage = 1300,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA MVP3] FIC VA-503+",
.internal_name = "ficva503p",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_MVP3,
.init = machine_at_mvp3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 124242424,
.min_voltage = 2000,
.max_voltage = 3200,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the VIA VT82C686A southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA MVP3] FIC VA-503A",
.internal_name = "ficva503a",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_MVP3,
.init = machine_at_ficva503a_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 124242424,
.min_voltage = 1800,
.max_voltage = 3100,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_A97 | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the VIA VT82C686A southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA MVP3] Soyo 5EMA PRO",
.internal_name = "5emapro",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_MVP3,
.init = machine_at_5emapro_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 124242424,
.min_voltage = 2000,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SiS 5591 */
/* Has the SiS 5591 chipset with on-chip KBC. */
{
.name = "[SiS 5591] Gigabyte GA-5SG100",
.internal_name = "5sg100",
.type = MACHINE_TYPE_SOCKETS7,
.chipset = MACHINE_CHIPSET_SIS_5591,
.init = machine_at_5sg100_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET5_7,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 2000,
.max_voltage = 3520,
.min_multi = 1.5,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Socket 8 machines */
/* 450KX */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i450KX] AOpen AP61",
.internal_name = "ap61",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_450KX,
.init = machine_at_ap61_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{
.name = "[i450KX] ASUS P/I-P6RP4",
.internal_name = "p6rp4",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_450KX,
.init = machine_at_p6rp4_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI, /* Machine has AMB */
.flags = MACHINE_IDE_DUAL | MACHINE_APM,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440FX */
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i440FX] Acer V60N",
.internal_name = "acerv60n",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_acerv60n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* The base board has a Holtek HT6542B with AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i440FX] ASUS P/I-P65UP5 (C-P6ND)",
.internal_name = "p65up5_cp6nd",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_p65up5_cp6nd_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has AMB */
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N with likely AMIKey 'F' KBC firmware. */
{
.name = "[i440FX] Biostar MB-8600TTC",
.internal_name = "8600ttc",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_8600ttc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 2900,
.max_voltage = 3300,
.min_multi = 2.0,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* It's a Intel VS440FX with a Gateway 2000 OEM BIOS */
{
.name = "[i440FX] Gateway 2000 Venus",
.internal_name = "gw2kvenus",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_gw2kvenus_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 2.0,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i440FX] Gigabyte GA-686NX",
.internal_name = "686nx",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_686nx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 2.0,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i440FX] Intel AP440FX",
.internal_name = "ap440fx",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_ap440fx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 2.0,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_SOUND | MACHINE_VIDEO | MACHINE_USB, /* Machine has internal video: S3 ViRGE/DX and sound: Crystal CS4236B */
.ram = {
.min = 8192,
.max = 131072,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_virge_375_onboard_pci_device,
.snd_device = &cs4236b_device,
.net_device = NULL
},
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{
.name = "[i440FX] Intel VS440FX",
.internal_name = "vs440fx",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_vs440fx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 2.0,
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i440FX] LG IBM Multinet x61 (MSI MS-6106)",
.internal_name = "lgibmx61",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_lgibmx61_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2500,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB, /* Machine has internal SCSI: Adaptec AIC-78xx */
.ram = {
.min = 40960,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i440FX] Micronics M6Mi",
.internal_name = "m6mi",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_m6mi_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2900,
.max_voltage = 3300,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a VIA VT82C42N KBC with likely AMI MegaKey firmware. */
{
.name = "[i440FX] PC Partner MB600N",
.internal_name = "mb600n",
.type = MACHINE_TYPE_SOCKET8,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_mb600n_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET8,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 66666667,
.min_voltage = 2100,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Slot 1 machines */
/* ALi ALADDiN V */
/* Has the ALi M1543C southbridge with on-chip KBC. */
{
.name = "[ALi ALADDiN-PRO II] PC Chips M729",
.internal_name = "m729",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_ALI_ALADDIN_PRO_II,
.init = machine_at_m729_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal sound: C-Media CMI8330 */
.ram = {
.min = 1024,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440FX */
/* The base board has a Holtek HT6542B KBC with AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i440FX] ASUS P/I-P65UP5 (C-PKND)",
.internal_name = "p65up5_cpknd",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_p65up5_cpknd_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 66666667,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* This has a Holtek KBC and the BIOS does not send a single non-standard KBC command, so it
must be an ASIC that clones the standard IBM PS/2 KBC. */
{
.name = "[i440FX] ASUS KN97",
.internal_name = "kn97",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440FX,
.init = machine_at_kn97_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 83333333,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 127,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440LX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440LX] ABIT LX6",
.internal_name = "lx6",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440LX,
.init = machine_at_lx6_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 60000000,
.max_bus = 100000000,
.min_voltage = 1500,
.max_voltage = 3500,
.min_multi = 2.0,
.max_multi = 5.5
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
MultiKey/42 (version 1.38) KBC firmware. */
{
.name = "[i440LX] Micronics Spitfire",
.internal_name = "spitfire",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440LX,
.init = machine_at_spitfire_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37C67x Super I/O chip with on-chip KBC with Phoenix or
AMIKey-2 KBC firmware. */
{
.name = "[i440LX] NEC Mate NX MA30D/23D",
.internal_name = "ma30d",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440LX,
.init = machine_at_ma30d_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440EX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440EX] QDI EXCELLENT II",
.internal_name = "p6i440e2",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440EX,
.init = machine_at_p6i440e2_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 83333333,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 3.0,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440BX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] ASUS P2B-LS",
.internal_name = "p2bls",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_p2bls_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 50000000,
.max_bus = 112121212,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB, /* Machine has internal SCSI: Adaptec AIC-7890AB */
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] ASUS P3B-F",
.internal_name = "p3bf",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_p3bf_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] ABIT BF6",
.internal_name = "bf6",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_bf6_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] AOpen AX6BC",
.internal_name = "ax6bc",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_ax6bc_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 112121212,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] Gigabyte GA-686BX",
.internal_name = "686bx",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_686bx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a SM(S)C FDC37M60x Super I/O chip with on-chip KBC with most likely
AMIKey-2 KBC firmware. */
{
.name = "[i440BX] HP Vectra VEi 8",
.internal_name = "vei8",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_vei8_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal video: Matrox MGA-G200 and sound: Crystal CS4820 */
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 (updated 'H') KBC firmware. */
{
.name = "[i440BX] LG IBM Multinet i x7G (MSI MS-6119)",
.internal_name = "lgibmx7g",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_lgibmx7g_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a National Semiconductors PC87309 Super I/O chip with on-chip KBC
with most likely AMIKey-2 KBC firmware. */
{
.name = "[i440BX] Tyan Tsunami ATX",
.internal_name = "s1846",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_s1846_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 112121212,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_USB, /* Machine has internal sound: Ensoniq ES1371 */
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &es1371_onboard_device,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] Supermicro P6SBA",
.internal_name = "p6sba",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_p6sba_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440ZX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440ZX] MSI MS-6168",
.internal_name = "ms6168",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440ZX,
.init = machine_at_ms6168_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* AGP is reserved for the internal video */
.flags = MACHINE_IDE_DUAL | MACHINE_AV | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &voodoo_3_2000_agp_onboard_8m_device,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440ZX] Packard Bell Bora Pro",
.internal_name = "borapro",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_INTEL_440ZX,
.init = machine_at_borapro_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 66666667,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* AGP is reserved for the internal video */
.flags = MACHINE_IDE_DUAL | MACHINE_AV | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &voodoo_3_2000_agp_onboard_8m_device,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* SMSC VictoryBX-66 */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[SMSC VictoryBX-66] A-Trend ATC-6310BXII",
.internal_name = "atc6310bxii",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_SMSC_VICTORYBX_66,
.init = machine_at_atc6310bxii_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* VIA Apollo Pro */
/* Has the VIA VT82C596B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA Apollo Pro] FIC KA-6130",
.internal_name = "ficka6130",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO,
.init = machine_at_ficka6130_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal sound: ESS ES1938S */
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[VIA Apollo Pro 133] ASUS P3V133",
.internal_name = "p3v133",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133,
.init = machine_at_p3v133_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[VIA Apollo Pro 133A] ASUS P3V4X",
.internal_name = "p3v4x",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133A,
.init = machine_at_p3v4x_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 2097152,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[VIA Apollo Pro 133A] BCM GT694VA",
.internal_name = "gt694va",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133A,
.init = machine_at_gt694va_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal sound: Ensoniq ES1373 */
.ram = {
.min = 8192,
.max = 3145728,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* SiS (5)600 */
/* Has the SiS (5)600 chipset with on-chip KBC. */
{
.name = "[SiS 5600] Freetech/Flexus P6F99",
.internal_name = "p6f99",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_SIS_5600,
.init = machine_at_p6f99_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB, /* Machine has internal sound: Ensoniq ES1373 */
.ram = {
.min = 8192,
.max = 1572864,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* Has the SiS (5)600 chipset with on-chip KBC. */
{
.name = "[SiS 5600] PC Chips M747",
.internal_name = "m747",
.type = MACHINE_TYPE_SLOT1,
.chipset = MACHINE_CHIPSET_SIS_5600,
.init = machine_at_m747_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1572864,
.step = 1024
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Slot 1/2 machines */
/* 440GX */
/* Has a National Semiconductors PC87309 Super I/O chip with on-chip KBC
with most likely AMIKey-2 KBC firmware. */
{
.name = "[i440GX] Freeway FW-6400GX",
.internal_name = "fw6400gx",
.type = MACHINE_TYPE_SLOT1_2,
.chipset = MACHINE_CHIPSET_INTEL_440GX,
.init = machine_at_fw6400gx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1 | CPU_PKG_SLOT2,
.block = CPU_BLOCK_NONE,
.min_bus = 100000000,
.max_bus = 150000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 3.0,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_NOISA | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 16384,
.max = 2097152,
.step = 16384
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Slot 1/Socket 370 machines */
/* 440BX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] Tyan Trinity 371",
.internal_name = "s1857",
.type = MACHINE_TYPE_SLOT1_370,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_s1857_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1 | CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &es1373_onboard_device,
.net_device = NULL
},
/* VIA Apollo Pro */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[VIA Apollo Pro 133] ECS P6BAT-A+",
.internal_name = "p6bat",
.type = MACHINE_TYPE_SLOT1_370,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133,
.init = machine_at_p6bat_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1 | CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &cmi8738_onboard_device,
.net_device = NULL
},
/* Slot 2 machines */
/* 440GX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440GX] Gigabyte GA-6GXU",
.internal_name = "6gxu",
.type = MACHINE_TYPE_SLOT2,
.chipset = MACHINE_CHIPSET_INTEL_440GX,
.init = machine_at_6gxu_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT2,
.block = CPU_BLOCK_NONE,
.min_bus = 100000000,
.max_bus = 133333333,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB, /* Machine has internal SCSI */
.ram = {
.min = 16384,
.max = 2097152,
.step = 16384
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440GX] Supermicro S2DGE",
.internal_name = "s2dge",
.type = MACHINE_TYPE_SLOT2,
.chipset = MACHINE_CHIPSET_INTEL_440GX,
.init = machine_at_s2dge_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT2,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 16384,
.max = 2097152,
.step = 16384
},
.nvrmask = 511,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* PGA370 machines */
/* 440LX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440LX] Supermicro 370SLM",
.internal_name = "s370slm",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_INTEL_440LX,
.init = machine_at_s370slm_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED,
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440BX */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] AEWIN AW-O671R",
.internal_name = "awo671r",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_awo671r_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0 /* limits assumed */
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB, /* Machine has EISA, possibly for a riser? */
/* Yes, that's a rise slot, not EISA. */
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB | MACHINE_VIDEO, /* Machine has internal video: C&T B69000, sound: ESS ES1938S and NIC: Realtek RTL8139C */
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] ASUS CUBX",
.internal_name = "cubx",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_cubx_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB, /* Machine has quad channel IDE with internal controller: CMD PCI-0648 */
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] AmazePC AM-BX133",
.internal_name = "ambx133",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_ambx133_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0 /* limits assumed */
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 440ZX */
/* Has a Winbond W83977TF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440ZX] Soltek SL-63A1",
.internal_name = "63a1",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_INTEL_440ZX,
.init = machine_at_63a1_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* SMSC VictoryBX-66 */
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[SMSC VictoryBX-66] A-Trend ATC-7020BXII",
.internal_name = "atc7020bxii",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_SMSC_VICTORYBX_66,
.init = machine_at_atc7020bxii_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has an ITE IT8671F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[SMSC VictoryBX-66] PC Chips M773",
.internal_name = "m773",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_SMSC_VICTORYBX_66,
.init = machine_at_m773_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 133333333,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 8192,
.max = 524288,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &cmi8738_onboard_device,
.net_device = NULL
},
/* VIA Apollo Pro */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA Apollo Pro] PC Partner APAS3",
.internal_name = "apas3",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO,
.init = machine_at_apas3_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 100000000,
.min_voltage = 1800,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 786432,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has a Winbond W83977EF Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[VIA Apollo Pro 133] ECS P6BAP-A+",
.internal_name = "p6bap",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133,
.init = machine_at_p6bap_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_AGP | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB | MACHINE_SOUND,
.ram = {
.min = 8192,
.max = 1572864,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &cmi8738_onboard_device,
.net_device = NULL
},
/* Has the VIA VT82C686B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA Apollo Pro 133A] Acorp 6VIA90AP",
.internal_name = "6via90ap",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133A,
.init = machine_at_6via90ap_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = MACHINE_MULTIPLIER_FIXED,
.max_multi = MACHINE_MULTIPLIER_FIXED
},
.bus_flags = MACHINE_PS2_A97 | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_AG | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 16384,
.max = 3145728,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* Has the VIA VT82C686B southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{
.name = "[VIA Apollo Pro 133A] ASUS CUV4X-LS",
.internal_name = "cuv4xls",
.type = MACHINE_TYPE_SOCKET370,
.chipset = MACHINE_CHIPSET_VIA_APOLLO_PRO_133A,
.init = machine_at_cuv4xls_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SOCKET370,
.block = CPU_BLOCK_NONE,
.min_bus = 66666667,
.max_bus = 150000000,
.min_voltage = 1300,
.max_voltage = 3500,
.min_multi = 1.5,
.max_multi = 8.0
},
.bus_flags = MACHINE_PS2_NOI97 | MACHINE_BUS_USB, /* Has Asus-proprietary LAN/SCSI slot */
.flags = MACHINE_IDE_DUAL | MACHINE_SOUND | MACHINE_APM | MACHINE_ACPI | MACHINE_GAMEPORT | MACHINE_USB,
.ram = {
.min = 16384,
.max = 4194304,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = &cmi8738_onboard_device,
.net_device = NULL
},
/* Miscellaneous/Fake/Hypervisor machines */
/* Has a Winbond W83977F Super I/O chip with on-chip KBC with AMIKey-2 KBC
firmware. */
{
.name = "[i440BX] Microsoft Virtual PC 2007",
.internal_name = "vpc2007",
.type = MACHINE_TYPE_MISC,
.chipset = MACHINE_CHIPSET_INTEL_440BX,
.init = machine_at_vpc2007_init,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = CPU_PKG_SLOT1,
.block = CPU_BLOCK(CPU_PENTIUM2, CPU_CYRIX3S),
.min_bus = 0,
.max_bus = 66666667,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_ACPI | MACHINE_USB,
.ram = {
.min = 8192,
.max = 1048576,
.step = 8192
},
.nvrmask = 255,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = NULL,
.internal_name = NULL,
.type = MACHINE_TYPE_NONE,
.chipset = MACHINE_CHIPSET_NONE,
.init = NULL,
.p1_handler = NULL,
.gpio_handler = NULL,
.available_flag = MACHINE_AVAILABLE,
.gpio_acpi_handler = NULL,
.cpu = {
.package = 0,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_BUS_NONE,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 0,
.max = 0,
.step = 0
},
.nvrmask = 0,
.kbc_device = NULL,
.kbc_p1 = 0xff,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
}
// clang-format on
};
/* Saved copies - jumpers get applied to these.
We use also machine_gpio to store IBM PC/XT jumpers as they need more than one byte. */
static uint8_t machine_p1_default;
static uint8_t machine_p1;
static uint32_t machine_gpio_default;
static uint32_t machine_gpio;
static uint32_t machine_gpio_acpi_default;
static uint32_t machine_gpio_acpi;
void *machine_snd = NULL;
uint8_t
machine_get_p1_default(void)
{
return machine_p1_default;
}
uint8_t
machine_get_p1(void)
{
return machine_p1;
}
void
machine_set_p1_default(uint8_t val)
{
machine_p1 = machine_p1_default = val;
}
void
machine_set_p1(uint8_t val)
{
machine_p1 = val;
}
void
machine_and_p1(uint8_t val)
{
machine_p1 = machine_p1_default & val;
}
uint8_t
machine_handle_p1(uint8_t write, uint8_t val)
{
uint8_t ret = 0xff;
if (machines[machine].p1_handler)
ret = machines[machine].p1_handler(write, val);
else {
if (write)
machine_p1 = machine_p1_default & val;
else
ret = machine_p1;
}
return ret;
}
void
machine_init_p1(void)
{
machine_p1 = machine_p1_default = machines[machine].kbc_p1;
}
uint32_t
machine_get_gpio_default(void)
{
return machine_gpio_default;
}
uint32_t
machine_get_gpio(void)
{
return machine_gpio;
}
void
machine_set_gpio_default(uint32_t val)
{
machine_gpio = machine_gpio_default = val;
}
void
machine_set_gpio(uint32_t val)
{
machine_gpio = val;
}
void
machine_and_gpio(uint32_t val)
{
machine_gpio = machine_gpio_default & val;
}
uint32_t
machine_handle_gpio(uint8_t write, uint32_t val)
{
uint32_t ret = 0xffffffff;
if (machines[machine].gpio_handler)
ret = machines[machine].gpio_handler(write, val);
else {
if (write)
machine_gpio = machine_gpio_default & val;
else
ret = machine_gpio;
}
return ret;
}
void
machine_init_gpio(void)
{
machine_gpio = machine_gpio_default = machines[machine].gpio;
}
uint32_t
machine_get_gpio_acpi_default(void)
{
return machine_gpio_acpi_default;
}
uint32_t
machine_get_gpio_acpi(void)
{
return machine_gpio_acpi;
}
void
machine_set_gpio_acpi_default(uint32_t val)
{
machine_gpio_acpi = machine_gpio_acpi_default = val;
}
void
machine_set_gpio_acpi(uint32_t val)
{
machine_gpio_acpi = val;
}
void
machine_and_gpio_acpi(uint32_t val)
{
machine_gpio_acpi = machine_gpio_acpi_default & val;
}
uint32_t
machine_handle_gpio_acpi(uint8_t write, uint32_t val)
{
uint32_t ret = 0xffffffff;
if (machines[machine].gpio_acpi_handler)
ret = machines[machine].gpio_acpi_handler(write, val);
else {
if (write)
machine_gpio_acpi = machine_gpio_acpi_default & val;
else
ret = machine_gpio_acpi;
}
return ret;
}
void
machine_init_gpio_acpi(void)
{
machine_gpio_acpi = machine_gpio_acpi_default = machines[machine].gpio_acpi;
}
int
machine_count(void)
{
return ((sizeof(machines) / sizeof(machine_t)) - 1);
}
const char *
machine_getname(void)
{
return (machines[machine].name);
}
const char *
machine_getname_ex(int m)
{
return (machines[m].name);
}
const device_t *
machine_get_kbc_device(int m)
{
if (machines[m].kbc_device)
return (machines[m].kbc_device);
return (NULL);
}
const device_t *
machine_get_device(int m)
{
if (machines[m].device)
return (machines[m].device);
return (NULL);
}
const device_t *
machine_get_fdc_device(int m)
{
if (machines[m].fdc_device)
return (machines[m].fdc_device);
return (NULL);
}
const device_t *
machine_get_sio_device(int m)
{
if (machines[m].sio_device)
return (machines[m].sio_device);
return (NULL);
}
const device_t *
machine_get_vid_device(int m)
{
if (machines[m].vid_device)
return (machines[m].vid_device);
return (NULL);
}
const device_t *
machine_get_snd_device(int m)
{
if (machines[m].snd_device)
return (machines[m].snd_device);
return (NULL);
}
const device_t *
machine_get_net_device(int m)
{
if (machines[m].net_device)
return (machines[m].net_device);
return (NULL);
}
const char *
machine_get_internal_name(void)
{
return (machines[machine].internal_name);
}
const char *
machine_get_internal_name_ex(int m)
{
return (machines[m].internal_name);
}
int
machine_get_nvrmask(int m)
{
return (machines[m].nvrmask);
}
int
machine_has_flags(int m, int flags)
{
return (machines[m].flags & flags);
}
int
machine_has_bus(int m, int bus_flags)
{
return (machines[m].bus_flags & bus_flags);
}
int
machine_has_cartridge(int m)
{
return (machine_has_bus(m, MACHINE_CARTRIDGE) ? 1 : 0);
}
int
machine_get_min_ram(int m)
{
return (machines[m].ram.min);
}
int
machine_get_max_ram(int m)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
return MIN(((int) machines[m].ram.max), 2097152);
#else
return MIN(((int) machines[m].ram.max), 3145728);
#endif
}
int
machine_get_ram_granularity(int m)
{
return (machines[m].ram.step);
}
int
machine_get_type(int m)
{
return (machines[m].type);
}
int
machine_get_machine_from_internal_name(const char *s)
{
int c = 0;
while (machines[c].init != NULL) {
if (!strcmp(machines[c].internal_name, s))
return c;
c++;
}
return 0;
}
int
machine_has_mouse(void)
{
return (machines[machine].flags & MACHINE_MOUSE);
}
int
machine_is_sony(void)
{
return (!strcmp(machines[machine].internal_name, "pcv90"));
}
``` | /content/code_sandbox/src/machine/machine_table.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 137,050 |
```c++
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Interface to the YMFM emulator.
*
*
* Authors: Adrien Moulin, <adrien@elyosh.org>
*
*/
#include <cstdarg>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include "ymfm/ymfm_opl.h"
extern "C" {
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/sound.h>
#include <86box/snd_opl.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/plat_unused.h>
// Disable c99-designator to avoid the warnings in *_ymfm_device
#ifdef __clang__
# if __has_warning("-Wc99-designator")
# pragma clang diagnostic push
# pragma clang diagnostic ignored "-Wc99-designator"
# endif
#endif
}
#define RSM_FRAC 10
#define OPL_FREQ FREQ_48000
enum {
FLAG_CYCLES = (1 << 0)
};
class YMFMChipBase {
public:
YMFMChipBase(UNUSED(uint32_t clock), fm_type type, uint32_t samplerate)
: m_buf_pos(0)
, m_flags(0)
, m_type(type)
, m_samplerate(samplerate)
{
memset(m_buffer, 0, sizeof(m_buffer));
}
virtual ~YMFMChipBase()
{
}
fm_type type() const { return m_type; }
int8_t flags() const { return m_flags; }
void set_do_cycles(int8_t do_cycles) { do_cycles ? m_flags |= FLAG_CYCLES : m_flags &= ~FLAG_CYCLES; }
int32_t *buffer() const { return (int32_t *) m_buffer; }
void reset_buffer() { m_buf_pos = 0; }
virtual uint32_t sample_rate() const = 0;
virtual void write(uint16_t addr, uint8_t data) = 0;
virtual void generate(int32_t *data, uint32_t num_samples) = 0;
virtual int32_t *update() = 0;
virtual uint8_t read(uint16_t addr) = 0;
virtual void set_clock(uint32_t clock) = 0;
protected:
int32_t m_buffer[MUSICBUFLEN * 2];
int m_buf_pos;
int *m_buf_pos_global;
int8_t m_flags;
fm_type m_type;
uint32_t m_samplerate;
};
template <typename ChipType>
class YMFMChip : public YMFMChipBase, public ymfm::ymfm_interface {
public:
YMFMChip(uint32_t clock, fm_type type, uint32_t samplerate)
: YMFMChipBase(clock, type, samplerate)
, m_chip(*this)
, m_clock(clock)
, m_samplerate(samplerate)
, m_samplecnt(0)
{
memset(m_samples, 0, sizeof(m_samples));
memset(m_oldsamples, 0, sizeof(m_oldsamples));
m_rateratio = (samplerate << RSM_FRAC) / m_chip.sample_rate(m_clock);
m_clock_us = 1000000.0 / (double) m_clock;
m_subtract[0] = 80.0;
m_subtract[1] = 320.0;
m_type = type;
m_buf_pos_global = (samplerate == FREQ_49716) ? &music_pos_global : &wavetable_pos_global;
if (m_type == FM_YMF278B) {
if (rom_load_linear("roms/sound/yamaha/yrw801.rom", 0, 0x200000, 0, m_yrw801) == 0) {
fatal("YRW801 ROM image \"roms/sound/yamaha/yrw801.rom\" not found\n");
}
}
timer_add(&m_timers[0], YMFMChip::timer1, this, 0);
timer_add(&m_timers[1], YMFMChip::timer2, this, 0);
}
virtual uint32_t sample_rate() const override
{
return m_chip.sample_rate(m_clock);
}
virtual void ymfm_set_timer(uint32_t tnum, int32_t duration_in_clocks) override
{
if (tnum > 1)
return;
m_duration_in_clocks[tnum] = duration_in_clocks;
pc_timer_t *timer = &m_timers[tnum];
if (duration_in_clocks < 0)
timer_stop(timer);
else {
double period = m_clock_us * duration_in_clocks;
if (period < m_subtract[tnum])
m_engine->engine_timer_expired(tnum);
else
timer_on_auto(timer, period);
}
}
virtual void set_clock(uint32_t clock) override
{
m_clock = clock;
m_clock_us = 1000000.0 / (double) m_clock;
m_rateratio = (m_samplerate << RSM_FRAC) / m_chip.sample_rate(m_clock);
ymfm_set_timer(0, m_duration_in_clocks[0]);
ymfm_set_timer(1, m_duration_in_clocks[1]);
}
virtual void generate(int32_t *data, uint32_t num_samples) override
{
for (uint32_t i = 0; i < num_samples; i++) {
m_chip.generate(&m_output);
if ((m_type == FM_YMF278B) && (sizeof(m_output.data) > (4 * sizeof(int32_t)))) {
if (ChipType::OUTPUTS == 1) {
*data++ = m_output.data[4];
*data++ = m_output.data[4];
} else {
*data++ = m_output.data[4];
*data++ = m_output.data[5];
}
} else if (ChipType::OUTPUTS == 1) {
*data++ = m_output.data[0];
*data++ = m_output.data[0];
} else {
*data++ = m_output.data[0];
*data++ = m_output.data[1 % ChipType::OUTPUTS];
}
}
}
#if 0
virtual void generate_resampled(int32_t *data, uint32_t num_samples) override
{
if ((m_samplerate == FREQ_49716) || (m_samplerate == FREQ_44100)) {
generate(data, num_samples);
return;
}
for (uint32_t i = 0; i < num_samples; i++) {
while (m_samplecnt >= m_rateratio) {
m_oldsamples[0] = m_samples[0];
m_oldsamples[1] = m_samples[1];
m_chip.generate(&m_output);
if ((m_type == FM_YMF278B) && (sizeof(m_output.data) > (4 * sizeof(int32_t)))) {
if (ChipType::OUTPUTS == 1) {
m_samples[0] = m_output.data[4];
m_samples[1] = m_output.data[4];
} else {
m_samples[0] = m_output.data[4];
m_samples[1] = m_output.data[5];
}
} else if (ChipType::OUTPUTS == 1) {
m_samples[0] = m_output.data[0];
m_samples[1] = m_output.data[0];
} else {
m_samples[0] = m_output.data[0];
m_samples[1] = m_output.data[1 % ChipType::OUTPUTS];
}
m_samplecnt -= m_rateratio;
}
*data++ = ((int32_t) ((m_oldsamples[0] * (m_rateratio - m_samplecnt)
+ m_samples[0] * m_samplecnt)
/ m_rateratio));
*data++ = ((int32_t) ((m_oldsamples[1] * (m_rateratio - m_samplecnt)
+ m_samples[1] * m_samplecnt)
/ m_rateratio));
m_samplecnt += 1 << RSM_FRAC;
}
}
#endif
virtual int32_t *update() override
{
if (m_buf_pos >= *m_buf_pos_global)
return m_buffer;
generate(&m_buffer[m_buf_pos * 2], *m_buf_pos_global - m_buf_pos);
for (; m_buf_pos < *m_buf_pos_global; m_buf_pos++) {
m_buffer[m_buf_pos * 2] /= 2;
m_buffer[(m_buf_pos * 2) + 1] /= 2;
}
return m_buffer;
}
virtual void write(uint16_t addr, uint8_t data) override
{
m_chip.write(addr, data);
}
virtual uint8_t read(uint16_t addr) override
{
return m_chip.read(addr);
}
virtual uint32_t get_special_flags(void) override
{
return ((m_type == FM_YMF262) || (m_type == FM_YMF289B) || (m_type == FM_YMF278B)) ? 0x8000 : 0x0000;
}
static void timer1(void *priv)
{
YMFMChip<ChipType> *drv = (YMFMChip<ChipType> *) priv;
drv->m_engine->engine_timer_expired(0);
}
static void timer2(void *priv)
{
YMFMChip<ChipType> *drv = (YMFMChip<ChipType> *) priv;
drv->m_engine->engine_timer_expired(1);
}
virtual uint8_t ymfm_external_read(ymfm::access_class type, uint32_t address) override
{
if (type == ymfm::access_class::ACCESS_PCM && address < 0x200000) {
return m_yrw801[address];
}
return 0xFF;
}
private:
ChipType m_chip;
uint32_t m_clock;
double m_clock_us;
double m_subtract[2];
typename ChipType::output_data m_output;
pc_timer_t m_timers[2];
int32_t m_duration_in_clocks[2]; // Needed for clock switches.
uint32_t m_samplerate;
// YRW801-M wavetable ROM.
uint8_t m_yrw801[0x200000];
// Resampling
int32_t m_rateratio;
int32_t m_samplecnt;
int32_t m_oldsamples[2];
int32_t m_samples[2];
};
extern "C" {
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "cpu.h"
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/snd_opl.h>
#ifdef ENABLE_OPL_LOG
int ymfm_do_log = ENABLE_OPL_LOG;
static void
ymfm_log(const char *fmt, ...)
{
va_list ap;
if (ymfm_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ymfm_log(fmt, ...)
#endif
static void *
ymfm_drv_init(const device_t *info)
{
YMFMChipBase *fm;
switch (info->local) {
default:
case FM_YM3812:
fm = (YMFMChipBase *) new YMFMChip<ymfm::ym3812>(3579545, FM_YM3812, FREQ_49716);
break;
case FM_YMF262:
fm = (YMFMChipBase *) new YMFMChip<ymfm::ymf262>(14318181, FM_YMF262, FREQ_49716);
break;
case FM_YMF289B:
/* According to the datasheet, we should be using 33868800, but YMFM appears
to cheat and does it using the same values as the YMF262. */
fm = (YMFMChipBase *) new YMFMChip<ymfm::ymf289b>(14318181, FM_YMF289B, FREQ_49716);
break;
case FM_YMF278B:
fm = (YMFMChipBase *) new YMFMChip<ymfm::ymf278b>(33868800, FM_YMF278B, FREQ_44100);
break;
}
fm->set_do_cycles(1);
return fm;
}
static void
ymfm_drv_close(void *priv)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
if (drv != NULL)
delete drv;
}
static uint8_t
ymfm_drv_read(uint16_t port, void *priv)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
if ((port == 0x380) || (port == 0x381))
port |= 4;
/* Point to register read port. */
if (drv->flags() & FLAG_CYCLES)
cycles -= ((int) (isa_timing * 8));
uint8_t ret = drv->read(port);
drv->update();
ymfm_log("YMFM read port %04x, status = %02x\n", port, ret);
return ret;
}
static void
ymfm_drv_write(uint16_t port, uint8_t val, void *priv)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
ymfm_log("YMFM write port %04x value = %02x\n", port, val);
if ((port == 0x380) || (port == 0x381))
port |= 4;
drv->write(port, val);
drv->update();
}
static int32_t *
ymfm_drv_update(void *priv)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
return drv->update();
}
static void
ymfm_drv_reset_buffer(void *priv)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
drv->reset_buffer();
}
static void
ymfm_drv_set_do_cycles(void *priv, int8_t do_cycles)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
drv->set_do_cycles(do_cycles);
}
static void
ymfm_drv_generate(void *priv, int32_t *data, uint32_t num_samples)
{
YMFMChipBase *drv = (YMFMChipBase *) priv;
// drv->generate_resampled(data, num_samples);
drv->generate(data, num_samples);
}
const device_t ym3812_ymfm_device = {
.name = "Yamaha YM3812 OPL2 (YMFM)",
.internal_name = "ym3812_ymfm",
.flags = 0,
.local = FM_YM3812,
.init = ymfm_drv_init,
.close = ymfm_drv_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ymf262_ymfm_device = {
.name = "Yamaha YMF262 OPL3 (YMFM)",
.internal_name = "ymf262_ymfm",
.flags = 0,
.local = FM_YMF262,
.init = ymfm_drv_init,
.close = ymfm_drv_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ymf289b_ymfm_device = {
.name = "Yamaha YMF289B OPL3-L (YMFM)",
.internal_name = "ymf289b_ymfm",
.flags = 0,
.local = FM_YMF289B,
.init = ymfm_drv_init,
.close = ymfm_drv_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ymf278b_ymfm_device = {
.name = "Yamaha YMF278B OPL4 (YMFM)",
.internal_name = "ymf278b_ymfm",
.flags = 0,
.local = FM_YMF278B,
.init = ymfm_drv_init,
.close = ymfm_drv_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const fm_drv_t ymfm_drv {
&ymfm_drv_read,
&ymfm_drv_write,
&ymfm_drv_update,
&ymfm_drv_reset_buffer,
&ymfm_drv_set_do_cycles,
NULL,
ymfm_drv_generate,
};
#ifdef __clang__
# if __has_warning("-Wc99-designator")
# pragma clang diagnostic pop
# endif
#endif
}
``` | /content/code_sandbox/src/sound/snd_opl_ymfm.cpp | c++ | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,938 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* AC'97 audio codec emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/snd_ac97.h>
#include <86box/plat_fallthrough.h>
static const struct {
const device_t *device;
/* Definitions for *_flags and vendor_regs in snd_ac97.h */
uint32_t min_rate;
uint32_t max_rate;
uint32_t misc_flags;
uint16_t reset_flags;
uint16_t extid_flags;
uint8_t pcsr_mask; /* register 26 bits [15:8] */
uint8_t eascr_mask; /* register 2A bits [14:11] */
const ac97_vendor_reg_t *vendor_regs;
} ac97_codecs[] = {
// clang-format off
{
.device = &ad1881_device,
.min_rate = 7000,
.max_rate = 48000,
.misc_flags = AC97_MASTER_6B | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_POP | AC97_MS | AC97_LPBK,
.reset_flags = (1 << AC97_3D_SHIFT), /* datasheet contradicts itself on AC97_HPOUT */
.extid_flags = AC97_VRA,
.pcsr_mask = 0xbf,
.vendor_regs = (const ac97_vendor_reg_t[]) {{0, 0x74, 0x0000, 0xff07}, {0, 0x76, 0x0404, 0xdde5}, {0, 0x78, 48000, 0x0000}, {0, 0x7a, 48000, 0x0000}, {0}}
},
{
.device = &ak4540_device,
.misc_flags = AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.pcsr_mask = 0x1f
},
{
.device = &alc100_device,
.misc_flags = AC97_AUXOUT | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_POP | AC97_MS | AC97_LPBK,
.reset_flags = (22 << AC97_3D_SHIFT),
.extid_flags = AC97_AMAP,
.pcsr_mask = 0xbf
},
{
.device = &cs4297_device,
.misc_flags = AC97_MASTER_6B | AC97_AUXOUT | AC97_AUXOUT_6B | AC97_MONOOUT | AC97_MONOOUT_6B | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.reset_flags = AC97_HPOUT | AC97_DAC_18B | AC97_ADC_18B,
.extid_flags = 0,
.pcsr_mask = 0x7f,
.vendor_regs = (const ac97_vendor_reg_t[]) {{0, 0x5a, 0x0301, 0x0000}, {0}}
},
{
.device = &cs4297a_device,
.misc_flags = AC97_MASTER_6B | AC97_AUXOUT | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.reset_flags = AC97_HPOUT | AC97_DAC_20B | AC97_ADC_18B | (6 << AC97_3D_SHIFT),
.extid_flags = AC97_AMAP,
.pcsr_mask = 0xff,
.vendor_regs = (const ac97_vendor_reg_t[]) {{0, 0x5e, 0x0000, 0x01b0}, {0, 0x60, 0x0023, 0x0001}, {0, 0x68, 0x0000, 0xdfff}, {0}}
},
{
.device = &stac9708_device,
.misc_flags = AC97_AUXOUT | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.reset_flags = (26 << AC97_3D_SHIFT) | AC97_DAC_18B | AC97_ADC_18B,
.extid_flags = AC97_SDAC,
.pcsr_mask = 0xff,
.eascr_mask = 0x02,
.vendor_regs = (const ac97_vendor_reg_t[]) {{0, 0x6c, 0x0000, 0x0003}, {0, 0x74, 0x0000, 0x0003}, {0}}
},
{
.device = &stac9721_device,
.misc_flags = AC97_AUXOUT | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.reset_flags = (26 << AC97_3D_SHIFT) | AC97_DAC_18B | AC97_ADC_18B,
.extid_flags = AC97_AMAP,
.pcsr_mask = 0xff,
.vendor_regs = (const ac97_vendor_reg_t[]) {{0, 0x6c, 0x0000, 0x0000}, {0, 0x6e, 0x0000, 0x0003}, {0, 0x70, 0x0000, 0xffff}, {0, 0x72, 0x0000, 0x0006}, {0, 0x74, 0x0000, 0x0003}, {0, 0x76, 0x0000, 0xffff}, {0, 0x78, 0x0000, 0x3802}, {0}}
},
{
.device = &tr28023_device,
.misc_flags = AC97_MASTER_6B | AC97_MONOOUT | AC97_MONOOUT_6B | AC97_PCBEEP | AC97_PHONE | AC97_POP | AC97_MS | AC97_LPBK,
.reset_flags = 0,
.extid_flags = 0,
.pcsr_mask = 0x3f
},
{
.device = &wm9701a_device,
.misc_flags = AC97_AUXOUT | AC97_MONOOUT | AC97_PCBEEP | AC97_PHONE | AC97_VIDEO | AC97_AUXIN | AC97_MS | AC97_LPBK,
.reset_flags = AC97_DAC_18B | AC97_ADC_18B,
.extid_flags = 0,
.pcsr_mask = 0x3f
}
// clang-format on
};
#ifdef ENABLE_AC97_CODEC_LOG
int ac97_codec_do_log = ENABLE_AC97_CODEC_LOG;
static void
ac97_codec_log(const char *fmt, ...)
{
va_list ap;
if (ac97_codec_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ac97_codec_log(fmt, ...)
#endif
static const int32_t codec_attn[] = {
// clang-format off
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 2, 2, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20,
25, 32, 41, 51, 65, 82, 103, 130, 164, 206, 260, 327, 412, 519, 653, 822,
1036, 1304, 1641, 2067, 2602, 3276, 4125, 5192, 6537, 8230, 10362, 13044, 16422, 20674, 26027, 32767,
41305, 52068, 65636, 82739, 104299, 131477, 165737, 208925
// clang-format on
};
ac97_codec_t **ac97_codec = NULL;
ac97_codec_t **ac97_modem_codec = NULL;
int ac97_codec_count = 0;
int ac97_modem_codec_count = 0;
int ac97_codec_id = 0;
int ac97_modem_codec_id = 0;
uint16_t
ac97_codec_readw(ac97_codec_t *dev, uint8_t reg)
{
/* Redirect a read from extended pages 1+ to the right array. */
reg &= 0x7e;
uint16_t ret = dev->regs[0x24 >> 1] & 0x000f;
if ((ret > 0) && (reg >= 0x60) && (reg < 0x6f))
ret = (ret <= dev->vendor_reg_page_max) ? dev->vendor_reg_pages[(ret << 3) | ((reg & 0x0e) >> 1)] : 0;
else
ret = dev->regs[reg >> 1];
ac97_codec_log("AC97 Codec %d: readw(%02X) = %04X\n", dev->codec_id, reg, ret);
return ret;
}
void
ac97_codec_writew(ac97_codec_t *dev, uint8_t reg, uint16_t val)
{
ac97_codec_log("AC97 Codec %d: writew(%02X, %04X)\n", dev->codec_id, reg, val);
reg &= 0x7e;
uint16_t i = 0;
uint16_t prev = dev->regs[reg >> 1];
int j;
switch (reg) {
case 0x00: /* Reset / ID code */
ac97_codec_reset(dev);
return;
case 0x02: /* Master Volume */
val &= 0xbf3f;
/* Convert 1xxxxx to 011111 where unsupported, per specification. */
if (!(ac97_codecs[dev->model].misc_flags & AC97_MASTER_6B)) {
clamp_5b:
if (val & 0x2000)
val = (val & ~0x2000) | 0x1f00;
clamp_5b_r:
if (val & 0x0020)
val = (val & ~0x0020) | 0x001f;
}
break;
case 0x04: /* Aux Out Volume */
if (!(ac97_codecs[dev->model].misc_flags & AC97_AUXOUT))
return;
val &= 0xbf3f;
/* Convert 1xxxxx to 011111 where unsupported, per specification. */
if (!(ac97_codecs[dev->model].misc_flags & AC97_AUXOUT_6B))
goto clamp_5b;
break;
case 0x06: /* Mono Out Volume */
if (!(ac97_codecs[dev->model].misc_flags & AC97_MONOOUT))
return;
val &= 0x803f;
/* Convert 1xxxxx to 011111 where unsupported, per specification. */
if (!(ac97_codecs[dev->model].misc_flags & AC97_MONOOUT_6B))
goto clamp_5b_r;
break;
case 0x08: /* Master Tone Control */
if (!(ac97_codecs[dev->model].reset_flags & AC97_TONECTL))
return;
val &= 0x0f0f;
break;
case 0x0a: /* PC Beep Volume */
if (ac97_codecs[dev->model].misc_flags & AC97_PCBEEP)
i |= 0x801e;
if (ac97_codecs[dev->model].misc_flags & AC97_PCBEEP_GEN)
i |= 0x1fe0;
val &= i;
break;
case 0x0c: /* Phone Volume */
if (!(ac97_codecs[dev->model].misc_flags & AC97_PHONE))
return;
val &= 0x801f;
break;
case 0x0e: /* Mic Volume */
val &= 0x805f;
break;
case 0x10: /* Line In Volume */
case 0x12: /* CD Volume */
case 0x18: /* PCM Out Volume */
line_gain:
val &= 0x9f1f;
break;
case 0x14: /* Video Volume */
if (!(ac97_codecs[dev->model].misc_flags & AC97_VIDEO))
return;
goto line_gain;
case 0x16: /* Aux In Volume */
if (!(ac97_codecs[dev->model].misc_flags & AC97_AUXIN))
return;
goto line_gain;
case 0x1a: /* Record Select Control */
val &= 0x0707;
break;
case 0x1c: /* Record Gain */
val &= 0x8f0f;
break;
case 0x1e: /* Record Gain Mic */
if (!(ac97_codecs[dev->model].reset_flags & AC97_MICPCM))
return;
val &= 0x800f;
break;
case 0x20: /* General Purpose */
i = AC97_MIX | (ac97_codecs[dev->model].misc_flags & (AC97_POP | AC97_MS | AC97_LPBK));
if (ac97_codecs[dev->model].reset_flags >> AC97_3D_SHIFT)
i |= AC97_3D;
if (ac97_codecs[dev->model].reset_flags & AC97_SIMSTEREO)
i |= AC97_ST;
if (ac97_codecs[dev->model].reset_flags & AC97_LOUDNESS)
i |= AC97_LD;
if (ac97_codecs[dev->model].extid_flags & AC97_DRA)
i |= AC97_DRSS_MASK;
val &= i;
break;
case 0x22: /* 3D Control */
switch (ac97_codecs[dev->model].reset_flags >> AC97_3D_SHIFT) {
case 1: /* Analog Devices */
case 6: /* Crystal */
val &= 0x000f;
break;
case 22: /* Avance Logic / Realtek */
val &= 0x0003;
break;
case 26: /* SigmaTel */
i = 0x0003;
if (ac97_codecs[dev->model].extid_flags & AC97_SDAC)
i |= 0x000c;
val &= i;
break;
default:
return;
}
break;
case 0x24: /* Audio Interrupt and Paging Mechanism */
if ((ac97_codecs[dev->model].extid_flags & AC97_REV_MASK) < AC97_REV_2_3)
return;
val &= 0x000f;
break;
case 0x26: /* Powerdown Control/Status */
i = ac97_codecs[dev->model].pcsr_mask << 8;
val = (val & i) | (prev & ~i);
/* Update status bits to reflect powerdowns. */
val = (val & ~0x300f) | (~(val >> 8) & 0x000f); /* also clear write-only PR4 and PR5 */
if (val & 0x0800) /* PR3 clears both ANL and REF */
val &= ~0x0004;
break;
case 0x28: /* Extended Audio ID */
if (ac97_codecs[dev->model].misc_flags & AC97_DSA)
i |= 0x0030;
val = (val & i) | (prev & ~i);
break;
case 0x2a: /* Extended Audio Status/Control */
i = ac97_codecs[dev->model].extid_flags & (AC97_VRA | AC97_DRA | AC97_SPDIF | AC97_VRM);
if (ac97_codecs[dev->model].extid_flags & AC97_SPDIF)
i |= AC97_SPSA_MASK << AC97_SPSA_SHIFT;
i |= (ac97_codecs[dev->model].eascr_mask << 11) & 0x7800;
val = (val & i) | (prev & ~i);
/* Reset DAC sample rates to 48 KHz (96 KHz with DRA) if VRA is being cleared. */
if (!(val & AC97_VRA)) {
for (i = 0x2c; i <= 0x30; i += 2)
dev->regs[i >> 1] = 48000;
}
/* Reset ADC sample rates to 48 KHz if VRM is being cleared. */
if (!(val & AC97_VRM)) {
for (i = 0x32; i <= 0x34; i += 2)
dev->regs[i >> 1] = 48000;
}
break;
case 0x2c: /* PCM Front DAC Rate */
case 0x32: /* PCM L/R ADC Rate */
rate: /* Writable only if VRA/VRM is set. */
i = (reg >= 0x32) ? AC97_VRM : AC97_VRA;
if (!(ac97_codecs[dev->model].extid_flags & i))
return;
/* Limit to supported sample rate range. */
if (val < ac97_codecs[dev->model].min_rate)
val = ac97_codecs[dev->model].min_rate;
else if (val > ac97_codecs[dev->model].max_rate)
val = ac97_codecs[dev->model].max_rate;
break;
case 0x2e: /* PCM Surround DAC Rate */
if (!(ac97_codecs[dev->model].extid_flags & AC97_SDAC))
return;
goto rate;
case 0x30: /* PCM LFE DAC Rate */
if (!(ac97_codecs[dev->model].extid_flags & AC97_LDAC))
return;
goto rate;
case 0x34: /* Mic ADC Rate */
if (!(ac97_codecs[dev->model].reset_flags & AC97_MICPCM))
return;
goto rate;
case 0x36: /* Center/LFE Volume */
if (ac97_codecs[dev->model].extid_flags & AC97_LDAC)
i |= 0xbf00;
if (ac97_codecs[dev->model].extid_flags & AC97_CDAC)
i |= 0x00bf;
val &= i;
/* Convert 1xxxxx to 011111 where unsupported, per specification. */
if (!(ac97_codecs[dev->model].misc_flags & AC97_LFE_6B) && (val & 0x2000))
val = (val & ~0x2000) | 0x1f00;
if (!(ac97_codecs[dev->model].misc_flags & AC97_CENTER_6B))
goto clamp_5b_r;
break;
case 0x38: /* Surround Volume */
if (!(ac97_codecs[dev->model].extid_flags & AC97_SDAC))
return;
val &= 0xbfbf;
/* Convert 1xxxxx to 011111 where unsupported, per specification. */
if (!(ac97_codecs[dev->model].misc_flags & AC97_SURR_6B))
goto clamp_5b;
break;
case 0x3a: /* S/PDIF Control */
if (!(ac97_codecs[dev->model].extid_flags & AC97_SPDIF))
return;
break;
case 0x60 ... 0x6e: /* Extended */
/* Get extended register page. */
i = dev->regs[0x24 >> 1] & 0x000f;
/* Redirect a write to page 1+ to the right array, part 1. */
if (i > 0) {
/* Don't overflow the pages. */
if (i > dev->vendor_reg_page_max)
return;
/* Get actual previous value. */
prev = dev->vendor_reg_pages[(i << 3) | ((reg & 0x0e) >> 1)];
}
fallthrough;
case 0x5a ... 0x5e: /* Vendor Reserved */
case 0x70 ... 0x7a:
/* Stop if no vendor-specific registers are defined. */
if (!ac97_codecs[dev->model].vendor_regs)
return;
/* Look for a matching vendor-specific register. */
for (j = 0; ac97_codecs[dev->model].vendor_regs[j].index; j++) {
/* If a match was found, inject written bits. */
if ((ac97_codecs[dev->model].vendor_regs[j].page == i) && (ac97_codecs[dev->model].vendor_regs[j].index == reg)) {
val = (val & ac97_codecs[dev->model].vendor_regs[j].write_mask) | (prev & ~ac97_codecs[dev->model].vendor_regs[j].write_mask);
break;
}
}
/* No match found. */
if (!ac97_codecs[dev->model].vendor_regs[j].index)
return;
/* Redirect a write to page 1+ to the right array, part 2. */
if (i > 0) {
dev->vendor_reg_pages[(i << 3) | ((reg & 0x0e) >> 1)] = val;
return;
}
break;
case 0x7c: /* Vendor ID1 */
case 0x7e: /* Vendor ID2 */
return;
default:
break;
}
dev->regs[reg >> 1] = val;
}
void
ac97_codec_reset(void *priv)
{
ac97_codec_t *dev = (ac97_codec_t *) priv;
uint16_t i;
ac97_codec_log("AC97 Codec %d: reset()\n", dev->codec_id);
memset(dev->regs, 0, sizeof(dev->regs));
/* Set default level and gain values. */
dev->regs[0x02 >> 1] = AC97_MUTE;
if (ac97_codecs[dev->model].misc_flags & AC97_AUXOUT)
dev->regs[0x04 >> 1] = AC97_MUTE;
if (ac97_codecs[dev->model].misc_flags & AC97_MONOOUT)
dev->regs[0x06 >> 1] = AC97_MUTE;
if (ac97_codecs[dev->model].misc_flags & AC97_PHONE)
dev->regs[0x0c >> 1] = AC97_MUTE | 0x0008;
dev->regs[0x0e >> 1] = AC97_MUTE | 0x0008; /* mic */
dev->regs[0x10 >> 1] = dev->regs[0x12 >> 1] = dev->regs[0x18 >> 1] = AC97_MUTE | 0x0808; /* line in, CD, PCM out */
if (ac97_codecs[dev->model].misc_flags & AC97_VIDEO)
dev->regs[0x14 >> 1] = AC97_MUTE | 0x0808;
if (ac97_codecs[dev->model].misc_flags & AC97_AUXIN)
dev->regs[0x14 >> 1] = AC97_MUTE | 0x0808;
dev->regs[0x1c >> 1] = AC97_MUTE; /* record gain */
if (ac97_codecs[dev->model].reset_flags & AC97_MICPCM)
dev->regs[0x1e >> 1] = AC97_MUTE; /* mic record gain */
if (ac97_codecs[dev->model].misc_flags & AC97_LDAC)
dev->regs[0x36 >> 1] = AC97_MUTE_L;
if (ac97_codecs[dev->model].misc_flags & AC97_CDAC)
dev->regs[0x36 >> 1] |= AC97_MUTE_R;
if (ac97_codecs[dev->model].misc_flags & AC97_SDAC)
dev->regs[0x38 >> 1] = AC97_MUTE_L | AC97_MUTE_R;
/* Set flags. */
dev->regs[0x00 >> 1] = ac97_codecs[dev->model].reset_flags;
dev->regs[0x26 >> 1] = 0x000f; /* codec ready */
dev->regs[0x28 >> 1] = (dev->codec_id << 14) | ac97_codecs[dev->model].extid_flags;
ac97_codec_writew(dev, 0x2a, 0x0000); /* reset variable DAC/ADC sample rates */
i = ac97_codecs[dev->model].extid_flags & (AC97_CDAC | AC97_SDAC | AC97_LDAC);
dev->regs[0x2a >> 1] |= i | (i << 5); /* any additional DACs are ready but powered down */
if (ac97_codecs[dev->model].extid_flags & AC97_SPDIF)
dev->regs[0x2a >> 1] |= AC97_SPCV;
if (ac97_codecs[dev->model].reset_flags & AC97_MICPCM)
dev->regs[0x2a >> 1] |= AC97_MADC | AC97_PRL;
/* Set vendor ID. */
dev->regs[0x7c >> 1] = ac97_codecs[dev->model].device->local >> 16;
dev->regs[0x7e >> 1] = ac97_codecs[dev->model].device->local;
/* Set vendor-specific registers. */
if (ac97_codecs[dev->model].vendor_regs) {
for (i = 0; ac97_codecs[dev->model].vendor_regs[i].index; i++) {
if (ac97_codecs[dev->model].vendor_regs[i].page > 0)
dev->vendor_reg_pages[(ac97_codecs[dev->model].vendor_regs[i].page << 3) | (ac97_codecs[dev->model].vendor_regs[i].index >> 1)] = ac97_codecs[dev->model].vendor_regs[i].value;
else
dev->regs[ac97_codecs[dev->model].vendor_regs[i].index >> 1] = ac97_codecs[dev->model].vendor_regs[i].value;
}
}
}
void
ac97_codec_getattn(void *priv, uint8_t reg, int *l, int *r)
{
const ac97_codec_t *dev = (ac97_codec_t *) priv;
uint16_t val = dev->regs[reg >> 1];
/* Apply full mute and powerdowns. */
int full_mute = (reg < 0x36);
if ((full_mute && (val & AC97_MUTE)) || /* full mute */
(dev->regs[0x26 >> 1] & 0x0e00) || /* DAC powerdown */
((reg == 0x38) && (dev->regs[0x2a >> 1] & AC97_PRJ))) { /* surround DAC powerdown */
*l = 0;
*r = 0;
} else { /* per-channel mute */
/* Determine attenuation value. */
uint8_t l_val = val >> 8;
uint8_t r_val = val;
if (reg <= 0x06) { /* 6-bit level */
*l = codec_attn[0x3f - (l_val & 0x3f)];
*r = codec_attn[0x3f - (r_val & 0x3f)];
} else { /* 5-bit gain */
*l = codec_attn[0x47 - (l_val & 0x1f)];
*r = codec_attn[0x47 - (r_val & 0x1f)];
}
/* Apply per-channel mute and center/LFE powerdowns where applicable. */
if (!full_mute) {
if ((val & AC97_MUTE_L) || /* left mute */
((reg == 0x36) && (dev->regs[0x2a >> 1] & AC97_PRK))) /* LFE DAC powerdown */
*l = 0;
if ((val & AC97_MUTE_R) || /* right mute */
((reg == 0x36) && (dev->regs[0x2a >> 1] & AC97_PRI))) /* center DAC powerdown */
*r = 0;
}
}
ac97_codec_log("AC97 Codec %d: getattn(%02X) = %d %d\n", dev->codec_id, reg, *l, *r);
}
uint32_t
ac97_codec_getrate(void *priv, uint8_t reg)
{
const ac97_codec_t *dev = (ac97_codec_t *) priv;
/* Get configured sample rate, which is always 48000 if VRA/VRM is not set. */
uint32_t ret = dev->regs[reg >> 1];
/* If this is the PCM DAC, double sample rate if DRA is set. */
if ((reg == 0x2c) && (dev->regs[0x2a >> 1] & AC97_DRA))
ret <<= 1;
ac97_codec_log("AC97 Codec %d: getrate(%02X) = %d\n", dev->codec_id, reg, ret);
return ret;
}
static void *
ac97_codec_init(const device_t *info)
{
ac97_codec_t *dev = malloc(sizeof(ac97_codec_t));
memset(dev, 0, sizeof(ac97_codec_t));
for (; dev->model < (sizeof(ac97_codecs) / sizeof(ac97_codecs[0])); dev->model++) {
if (ac97_codecs[dev->model].device->local == info->local)
break;
}
if (dev->model >= (sizeof(ac97_codecs) / sizeof(ac97_codecs[0]))) {
fatal("AC97 Codec %d: Unknown ID %c%c%c%02X\n", ac97_codec_id, (uint32_t) ((info->local >> 24) & 0xff), (uint32_t) ((info->local >> 16) & 0xff), (uint32_t) ((info->local >> 8) & 0xff), (uint32_t) (info->local & 0xff));
free(dev);
return NULL;
}
ac97_codec_log("AC97 Codec %d: init(%c%c%c%02X)\n", ac97_codec_id,
(ac97_codecs[dev->model].device->local >> 24) & 0xff, (ac97_codecs[dev->model].device->local >> 16) & 0xff,
(ac97_codecs[dev->model].device->local >> 8) & 0xff, ac97_codecs[dev->model].device->local & 0xff);
/* Associate this codec to the current controller. */
if (!ac97_codec || (ac97_codec_count <= 0)) {
pclog("AC97 Codec %d: No controller to associate codec\n", ac97_codec_id);
free(dev);
return NULL;
}
*ac97_codec = dev;
if (--ac97_codec_count == 0)
ac97_codec = NULL;
else
ac97_codec += sizeof(ac97_codec_t *);
dev->codec_id = ac97_codec_id++;
/* Allocate vendor-specific register pages if required. */
if (ac97_codecs[dev->model].vendor_regs) {
/* Get the highest vendor-specific register page number. */
for (uint16_t i = 0; ac97_codecs[dev->model].vendor_regs[i].index; i++) {
if (ac97_codecs[dev->model].vendor_regs[i].page > dev->vendor_reg_page_max)
dev->vendor_reg_page_max = ac97_codecs[dev->model].vendor_regs[i].page;
}
/* Allocate pages 1+. */
if (dev->vendor_reg_page_max > 0) {
ac97_codec_log("AC97 Codec %d: Allocating %d vendor-specific register pages\n", dev->codec_id, dev->vendor_reg_page_max);
int i = 16 * dev->vendor_reg_page_max;
dev->vendor_reg_pages = (uint16_t *) malloc(i);
memset(dev->vendor_reg_pages, 0, i);
}
}
/* Initialize codec registers. */
ac97_codec_reset(dev);
return dev;
}
static void
ac97_codec_close(void *priv)
{
ac97_codec_t *dev = (ac97_codec_t *) priv;
if (!dev)
return;
ac97_codec_log("AC97 Codec %d: close()\n", dev->codec_id);
if (dev->vendor_reg_pages)
free(dev->vendor_reg_pages);
free(dev);
}
const device_t *
ac97_codec_get(uint32_t id)
{
for (int i = 0; i < (sizeof(ac97_codecs) / sizeof(ac97_codecs[0])); i++) {
if (ac97_codecs[i].device->local == id)
return ac97_codecs[i].device;
}
return &tr28023_device; /* fallback */
}
const device_t ad1881_device = {
.name = "Analog Devices AD1881",
.internal_name = "ad1881",
.flags = DEVICE_AC97,
.local = AC97_CODEC_AD1881,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ak4540_device = {
.name = "Asahi Kasei AK4540",
.internal_name = "ak4540",
.flags = DEVICE_AC97,
.local = AC97_CODEC_AK4540,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t alc100_device = {
.name = "Avance Logic ALC100",
.internal_name = "alc100",
.flags = DEVICE_AC97,
.local = AC97_CODEC_ALC100,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t cs4297_device = {
.name = "Crystal CS4297",
.internal_name = "cs4297",
.flags = DEVICE_AC97,
.local = AC97_CODEC_CS4297,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t cs4297a_device = {
.name = "Crystal CS4297A",
.internal_name = "cs4297a",
.flags = DEVICE_AC97,
.local = AC97_CODEC_CS4297A,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stac9708_device = {
.name = "SigmaTel STAC9708",
.internal_name = "stac9708",
.flags = DEVICE_AC97,
.local = AC97_CODEC_STAC9708,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t stac9721_device = {
.name = "SigmaTel STAC9721",
.internal_name = "stac9721",
.flags = DEVICE_AC97,
.local = AC97_CODEC_STAC9721,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t tr28023_device = {
.name = "TriTech TR28023 / Creative CT1297",
.internal_name = "tr28023",
.flags = DEVICE_AC97,
.local = AC97_CODEC_TR28023,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t wm9701a_device = {
.name = "Wolfson WM9701A",
.internal_name = "wm9701a",
.flags = DEVICE_AC97,
.local = AC97_CODEC_WM9701A,
.init = ac97_codec_init,
.close = ac97_codec_close,
.reset = ac97_codec_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sound/snd_ac97_codec.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,905 |
```c
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/filters.h>
#include <86box/gameport.h>
#include <86box/io.h>
#include <86box/midi.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/pic.h>
#include <86box/sound.h>
#include <86box/snd_opl.h>
#include <86box/snd_ym7128.h>
#include <86box/plat_unused.h>
typedef struct adgold_t {
int adgold_irq_status;
int irq;
int dma;
uint8_t adgold_eeprom[0x1a];
uint8_t adgold_status;
int adgold_38x_state;
int adgold_38x_addr;
uint8_t adgold_38x_regs[0x1a];
int adgold_mma_addr;
uint8_t adgold_mma_regs[2][0xe];
int adgold_mma_enable[2];
uint8_t adgold_mma_fifo[2][256];
int adgold_mma_fifo_start[2];
int adgold_mma_fifo_end[2];
uint8_t adgold_mma_status;
int16_t adgold_mma_out[2];
int adgold_mma_intpos[2];
pc_timer_t adgold_mma_timer_count;
uint8_t adgold_midi_ctrl;
uint8_t midi_queue[16];
int midi_r;
int midi_w;
int uart_in;
int uart_out;
int sysex;
struct {
int timer0_latch;
int timer0_count;
int timerbase_latch;
int timerbase_count;
int timer1_latch;
int timer1_count;
int timer2_latch;
int timer2_count;
int timer2_read;
int voice_count[2];
int voice_latch[2];
} adgold_mma;
fm_drv_t opl;
ym7128_t ym7128;
int fm_vol_l;
int fm_vol_r;
int samp_vol_l;
int samp_vol_r;
int aux_vol_l;
int aux_vol_r;
int vol_l;
int vol_r;
int treble;
int bass;
int16_t opl_buffer[SOUNDBUFLEN * 2];
int16_t mma_buffer[2][SOUNDBUFLEN];
int pos;
int gameport_enabled;
int surround_enabled;
} adgold_t;
static int attenuation[0x40];
static int bass_attenuation[0x10] = {
(int) (1.995 * 16384), /*12 dB - filter output is at +6 dB so we use 6 dB here*/
(int) (1.995 * 16384),
(int) (1.995 * 16384),
(int) (1.413 * 16384), /*9 dB*/
(int) (1 * 16384), /*6 dB*/
(int) (0.708 * 16384), /*3 dB*/
(int) (0 * 16384), /*0 dB*/
(int) (0.708 * 16384), /*3 dB*/
(int) (1 * 16384), /*6 dB*/
(int) (1.413 * 16384), /*9 dB*/
(int) (1.995 * 16384), /*12 dB*/
(int) (2.819 * 16384), /*15 dB*/
(int) (2.819 * 16384),
(int) (2.819 * 16384),
(int) (2.819 * 16384),
(int) (2.819 * 16384)
};
static int bass_cut[6] = {
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.178 * 16384), /*-9 dB*/
(int) (0.251 * 16384), /*-6 dB*/
(int) (0.354 * 16384) /*-3 dB - filter output is at +6 dB*/
};
static int treble_attenuation[0x10] = {
(int) (1.995 * 16384), /*12 dB - filter output is at +6 dB so we use 6 dB here*/
(int) (1.995 * 16384),
(int) (1.995 * 16384),
(int) (1.413 * 16384), /*9 dB*/
(int) (1 * 16384), /*6 dB*/
(int) (0.708 * 16384), /*3 dB*/
(int) (0 * 16384), /*0 dB*/
(int) (0.708 * 16384), /*3 dB*/
(int) (1 * 16384), /*6 dB*/
(int) (1.413 * 16384), /*9 dB*/
(int) (1.995 * 16384), /*12 dB*/
(int) (1.995 * 16384),
(int) (1.995 * 16384),
(int) (1.995 * 16384),
(int) (1.995 * 16384),
(int) (1.995 * 16384)
};
static int treble_cut[6] = {
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.126 * 16384), /*-12 dB*/
(int) (0.178 * 16384), /*-9 dB*/
(int) (0.251 * 16384), /*-6 dB*/
(int) (0.354 * 16384) /*-3 dB - filter output is at +6 dB*/
};
void adgold_timer_poll(void *priv);
void adgold_update(adgold_t *adgold);
void
adgold_update_irq_status(adgold_t *adgold)
{
uint8_t temp = 0xf;
if (!(adgold->adgold_mma_regs[0][8] & 0x10) && (adgold->adgold_mma_status & 0x10)) /*Timer 0*/
temp &= ~2;
if (!(adgold->adgold_mma_regs[0][8] & 0x20) && (adgold->adgold_mma_status & 0x20)) /*Timer 1*/
temp &= ~2;
if (!(adgold->adgold_mma_regs[0][8] & 0x40) && (adgold->adgold_mma_status & 0x40)) /*Timer 2*/
temp &= ~2;
if (!(adgold->adgold_mma_regs[0][0xd] & 0x01) && (adgold->adgold_mma_status & 0x04))
temp &= ~2;
if (!(adgold->adgold_mma_regs[0][0xd] & 0x04) && (adgold->adgold_mma_status & 0x08))
temp &= ~2;
if (!(adgold->adgold_mma_regs[0][0xd] & 0x10) && (adgold->adgold_mma_status & 0x80))
temp &= ~2;
if ((adgold->adgold_mma_status & 0x01) && !(adgold->adgold_mma_regs[0][0xc] & 2))
temp &= ~2;
if ((adgold->adgold_mma_status & 0x02) && !(adgold->adgold_mma_regs[1][0xc] & 2))
temp &= ~2;
adgold->adgold_status = temp;
if ((adgold->adgold_status ^ 0xf) && !adgold->adgold_irq_status) {
picint(1 << adgold->irq);
}
adgold->adgold_irq_status = adgold->adgold_status ^ 0xf;
}
int
adgold_getsamp_dma(adgold_t *adgold, int channel)
{
int temp;
dma_set_drq(adgold->dma, 1);
if ((adgold->adgold_mma_regs[channel][0xc] & 0x60) && (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= 127))
return 2;
temp = dma_channel_read(adgold->dma);
if (temp == DMA_NODATA) {
return 1;
}
adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
if (adgold->adgold_mma_regs[channel][0xc] & 0x60) {
temp = dma_channel_read(adgold->dma);
adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_end[channel]] = temp;
adgold->adgold_mma_fifo_end[channel] = (adgold->adgold_mma_fifo_end[channel] + 1) & 255;
}
if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) >= adgold->adgold_mma_intpos[channel]) {
adgold->adgold_mma_status &= ~(0x01 << channel);
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
return 0;
}
void
adgold_write(uint16_t addr, uint8_t val, void *priv)
{
adgold_t *adgold = (adgold_t *) priv;
switch (addr & 7) {
case 0:
case 1:
adgold->opl.write(addr, val, adgold->opl.priv);
break;
case 2:
if (val == 0xff) {
adgold->adgold_38x_state = 1;
return;
}
if (val == 0xfe) {
adgold->adgold_38x_state = 0;
return;
}
if (adgold->adgold_38x_state) /*Write to control chip*/
adgold->adgold_38x_addr = val;
else
adgold->opl.write(addr, val, adgold->opl.priv);
break;
case 3:
if (adgold->adgold_38x_state) {
if (adgold->adgold_38x_addr >= 0x19)
break;
switch (adgold->adgold_38x_addr) {
case 0x00: /*Control/ID*/
if (val & 1)
memcpy(adgold->adgold_38x_regs, adgold->adgold_eeprom, 0x1a);
if (val & 2)
memcpy(adgold->adgold_eeprom, adgold->adgold_38x_regs, 0x1a);
break;
case 0x04: /*Final output volume left*/
adgold->adgold_38x_regs[0x04] = val;
adgold->vol_l = attenuation[val & 0x3f];
break;
case 0x05: /*Final output volume right*/
adgold->adgold_38x_regs[0x05] = val;
adgold->vol_r = attenuation[val & 0x3f];
break;
case 0x06: /*Bass*/
adgold->adgold_38x_regs[0x06] = val;
adgold->bass = val & 0xf;
break;
case 0x07: /*Treble*/
adgold->adgold_38x_regs[0x07] = val;
adgold->treble = val & 0xf;
break;
case 0x09: /*FM volume left*/
adgold->adgold_38x_regs[0x09] = val;
adgold->fm_vol_l = (int) (int8_t) (val - 128);
break;
case 0x0a: /*FM volume right*/
adgold->adgold_38x_regs[0x0a] = val;
adgold->fm_vol_r = (int) (int8_t) (val - 128);
break;
case 0x0b: /*Sample volume left*/
adgold->adgold_38x_regs[0x0b] = val;
adgold->samp_vol_l = (int) (int8_t) (val - 128);
break;
case 0x0c: /*Sample volume right*/
adgold->adgold_38x_regs[0x0c] = val;
adgold->samp_vol_r = (int) (int8_t) (val - 128);
break;
case 0x0d: /*Aux volume left*/
adgold->adgold_38x_regs[0x0d] = val;
adgold->aux_vol_l = (int) (int8_t) (val - 128);
break;
case 0x0e: /*Aux volume right*/
adgold->adgold_38x_regs[0x0e] = val;
adgold->aux_vol_r = (int) (int8_t) (val - 128);
break;
case 0x18: /*Surround*/
adgold->adgold_38x_regs[0x18] = val;
ym7128_write(&adgold->ym7128, val);
break;
default:
adgold->adgold_38x_regs[adgold->adgold_38x_addr] = val;
break;
}
} else
adgold->opl.write(addr, val, adgold->opl.priv);
break;
case 4:
case 6:
adgold->adgold_mma_addr = val;
break;
case 5:
if (adgold->adgold_mma_addr >= 0xf)
break;
switch (adgold->adgold_mma_addr) {
case 0x2:
adgold->adgold_mma.timer0_latch = (adgold->adgold_mma.timer0_latch & 0xff00) | val;
break;
case 0x3:
adgold->adgold_mma.timer0_latch = (adgold->adgold_mma.timer0_latch & 0xff) | (val << 8);
break;
case 0x4:
adgold->adgold_mma.timerbase_latch = (adgold->adgold_mma.timerbase_latch & 0xf00) | val;
break;
case 0x5:
adgold->adgold_mma.timerbase_latch = (adgold->adgold_mma.timerbase_latch & 0xff) | ((val & 0xf) << 8);
adgold->adgold_mma.timer1_latch = val >> 4;
break;
case 0x6:
adgold->adgold_mma.timer2_latch = (adgold->adgold_mma.timer2_latch & 0xff00) | val;
break;
case 0x7:
adgold->adgold_mma.timer2_latch = (adgold->adgold_mma.timer2_latch & 0xff) | (val << 8);
break;
case 0x8:
if ((val & 1) && !(adgold->adgold_mma_regs[0][8] & 1)) /*Reload timer 0*/
adgold->adgold_mma.timer0_count = adgold->adgold_mma.timer0_latch;
if ((val & 2) && !(adgold->adgold_mma_regs[0][8] & 2)) /*Reload timer 1*/
adgold->adgold_mma.timer1_count = adgold->adgold_mma.timer1_latch;
if ((val & 4) && !(adgold->adgold_mma_regs[0][8] & 4)) /*Reload timer 2*/
adgold->adgold_mma.timer2_count = adgold->adgold_mma.timer2_latch;
if ((val & 8) && !(adgold->adgold_mma_regs[0][8] & 8)) /*Reload base timer*/
adgold->adgold_mma.timerbase_count = adgold->adgold_mma.timerbase_latch;
break;
case 0x9:
switch (val & 0x18) {
case 0x00:
adgold->adgold_mma.voice_latch[0] = 12;
break; /*44100 Hz*/
case 0x08:
adgold->adgold_mma.voice_latch[0] = 24;
break; /*22050 Hz*/
case 0x10:
adgold->adgold_mma.voice_latch[0] = 48;
break; /*11025 Hz*/
case 0x18:
adgold->adgold_mma.voice_latch[0] = 72;
break; /* 7350 Hz*/
default:
break;
}
if (val & 0x80) {
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_fifo_end[0] = adgold->adgold_mma_fifo_start[0] = 0;
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if (val & 0x01) /*Start playback*/
{
if (!(adgold->adgold_mma_regs[0][0x9] & 1))
adgold->adgold_mma.voice_count[0] = adgold->adgold_mma.voice_latch[0];
if (adgold->adgold_mma_regs[0][0xc] & 1) {
if (adgold->adgold_mma_regs[0][0xc] & 0x80) {
adgold->adgold_mma_enable[1] = 1;
adgold->adgold_mma.voice_count[1] = adgold->adgold_mma.voice_latch[1];
while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
if (adgold_getsamp_dma(adgold, 0)) {
adgold->adgold_mma_fifo_end[0] = 0;
adgold->adgold_mma_fifo_start[0] = 0;
break;
}
if (adgold_getsamp_dma(adgold, 1)) {
adgold->adgold_mma_fifo_end[1] = 0;
adgold->adgold_mma_fifo_start[1] = 0;
break;
}
}
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) >= adgold->adgold_mma_intpos[1]) {
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
} else {
while (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
if (adgold_getsamp_dma(adgold, 0)) {
adgold->adgold_mma_fifo_end[0] = 0;
adgold->adgold_mma_fifo_start[0] = 0;
break;
}
}
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
}
}
adgold->adgold_mma_enable[0] = val & 0x01;
break;
case 0xb:
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) < 128) {
adgold->adgold_mma_fifo[0][adgold->adgold_mma_fifo_end[0]] = val;
adgold->adgold_mma_fifo_end[0] = (adgold->adgold_mma_fifo_end[0] + 1) & 255;
if (((adgold->adgold_mma_fifo_end[0] - adgold->adgold_mma_fifo_start[0]) & 255) >= adgold->adgold_mma_intpos[0]) {
adgold->adgold_mma_status &= ~0x01;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
break;
case 0xc:
adgold->adgold_mma_intpos[0] = (7 - ((val >> 2) & 7)) * 8;
break;
case 0xd:
adgold->adgold_midi_ctrl = val & 0x3f;
if ((adgold->adgold_midi_ctrl & 0x0f) != 0x0f) {
if ((adgold->adgold_midi_ctrl & 0x0f) == 0x00) {
adgold->uart_out = 0;
adgold->uart_in = 0;
adgold->midi_w = 0;
adgold->midi_r = 0;
adgold->adgold_mma_status &= ~0x8c;
} else {
if (adgold->adgold_midi_ctrl & 0x01)
adgold->uart_in = 1;
if (adgold->adgold_midi_ctrl & 0x04)
adgold->uart_out = 1;
if (adgold->adgold_midi_ctrl & 0x02) {
adgold->uart_in = 0;
adgold->midi_w = 0;
adgold->midi_r = 0;
}
if (adgold->adgold_midi_ctrl & 0x08)
adgold->uart_out = 0;
adgold->adgold_mma_status &= ~0x80;
}
} else
adgold->adgold_mma_status &= ~0x8c;
adgold_update_irq_status(adgold);
break;
case 0xe:
if (adgold->uart_out) {
midi_raw_out_byte(val);
adgold->adgold_mma_status &= ~0x08;
adgold_update_irq_status(adgold);
}
break;
default:
break;
}
adgold->adgold_mma_regs[0][adgold->adgold_mma_addr] = val;
break;
case 7:
if (adgold->adgold_mma_addr >= 0xe)
break;
switch (adgold->adgold_mma_addr) {
case 0x9:
adgold_update(adgold);
switch (val & 0x18) {
case 0x00:
adgold->adgold_mma.voice_latch[1] = 12;
break; /*44100 Hz*/
case 0x08:
adgold->adgold_mma.voice_latch[1] = 24;
break; /*22050 Hz*/
case 0x10:
adgold->adgold_mma.voice_latch[1] = 48;
break; /*11025 Hz*/
case 0x18:
adgold->adgold_mma.voice_latch[1] = 72;
break; /* 7350 Hz*/
default:
break;
}
if (val & 0x80) {
adgold->adgold_mma_enable[1] = 0;
adgold->adgold_mma_fifo_end[1] = adgold->adgold_mma_fifo_start[1] = 0;
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
if (val & 0x01) /*Start playback*/
{
if (!(adgold->adgold_mma_regs[1][0x9] & 1))
adgold->adgold_mma.voice_count[1] = adgold->adgold_mma.voice_latch[1];
if (adgold->adgold_mma_regs[1][0xc] & 1) {
while (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) < 128) {
if (adgold_getsamp_dma(adgold, 1)) {
adgold->adgold_mma_fifo_end[1] = 0;
adgold->adgold_mma_fifo_start[1] = 0;
break;
}
}
}
}
adgold->adgold_mma_enable[1] = val & 0x01;
break;
case 0xb:
if (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) < 128) {
adgold->adgold_mma_fifo[1][adgold->adgold_mma_fifo_end[1]] = val;
adgold->adgold_mma_fifo_end[1] = (adgold->adgold_mma_fifo_end[1] + 1) & 255;
if (((adgold->adgold_mma_fifo_end[1] - adgold->adgold_mma_fifo_start[1]) & 255) >= adgold->adgold_mma_intpos[1]) {
adgold->adgold_mma_status &= ~0x02;
adgold_update_irq_status(adgold);
dma_set_drq(adgold->dma, 0);
}
}
break;
case 0xc:
adgold->adgold_mma_intpos[1] = (7 - ((val >> 2) & 7)) * 8;
break;
default:
break;
}
adgold->adgold_mma_regs[1][adgold->adgold_mma_addr] = val;
break;
default:
break;
}
}
uint8_t
adgold_read(uint16_t addr, void *priv)
{
adgold_t *adgold = (adgold_t *) priv;
uint8_t temp = 0;
switch (addr & 7) {
case 0:
case 1:
temp = adgold->opl.read(addr, adgold->opl.priv);
break;
case 2:
if (adgold->adgold_38x_state) /*Read from control chip*/
temp = adgold->adgold_status;
else
temp = adgold->opl.read(addr, adgold->opl.priv);
break;
case 3:
if (adgold->adgold_38x_state) {
if (adgold->adgold_38x_addr >= 0x19)
temp = 0xff;
switch (adgold->adgold_38x_addr) {
case 0x00: /*Control/ID*/
if (adgold->surround_enabled)
temp = 0x51; /*8-bit ISA, surround module, no telephone/CD-ROM*/
else
temp = 0x71; /*8-bit ISA, no telephone/surround/CD-ROM*/
break;
default:
temp = adgold->adgold_38x_regs[adgold->adgold_38x_addr];
break;
}
} else
temp = adgold->opl.read(addr, adgold->opl.priv);
break;
case 4:
case 6:
temp = adgold->adgold_mma_status;
adgold->adgold_mma_status &= ~0xf3; /*JUKEGOLD expects timer status flags to auto-clear*/
adgold_update_irq_status(adgold);
picintc(1 << adgold->irq);
break;
case 5:
if (adgold->adgold_mma_addr >= 0xf)
temp = 0xff;
switch (adgold->adgold_mma_addr) {
case 6: /*Timer 2 low*/
adgold->adgold_mma.timer2_read = adgold->adgold_mma.timer2_count;
adgold->adgold_mma_status |= 0x40;
temp = adgold->adgold_mma.timer2_read & 0xff;
break;
case 7: /*Timer 2 high*/
temp = adgold->adgold_mma.timer2_read >> 8;
break;
case 0xe:
temp = 0;
if (adgold->uart_in) {
temp = adgold->midi_queue[adgold->midi_r];
if (adgold->midi_r != adgold->midi_w) {
adgold->midi_r++;
adgold->midi_r &= 0x0f;
}
adgold->adgold_mma_status &= ~0x04;
adgold_update_irq_status(adgold);
}
break;
default:
temp = adgold->adgold_mma_regs[0][adgold->adgold_mma_addr];
break;
}
break;
case 7:
if (adgold->adgold_mma_addr >= 0xf)
temp = 0xff;
else
temp = adgold->adgold_mma_regs[1][adgold->adgold_mma_addr];
break;
default:
break;
}
return temp;
}
void
adgold_update(adgold_t *adgold)
{
for (; adgold->pos < sound_pos_global; adgold->pos++) {
adgold->mma_buffer[0][adgold->pos] = adgold->mma_buffer[1][adgold->pos] = 0;
if (adgold->adgold_mma_regs[0][9] & 0x20)
adgold->mma_buffer[0][adgold->pos] += adgold->adgold_mma_out[0] / 2;
if (adgold->adgold_mma_regs[0][9] & 0x40)
adgold->mma_buffer[1][adgold->pos] += adgold->adgold_mma_out[0] / 2;
if (adgold->adgold_mma_regs[1][9] & 0x20)
adgold->mma_buffer[0][adgold->pos] += adgold->adgold_mma_out[1] / 2;
if (adgold->adgold_mma_regs[1][9] & 0x40)
adgold->mma_buffer[1][adgold->pos] += adgold->adgold_mma_out[1] / 2;
}
}
void
adgold_mma_poll(adgold_t *adgold, int channel)
{
int16_t dat;
adgold_update(adgold);
if (adgold->adgold_mma_fifo_start[channel] != adgold->adgold_mma_fifo_end[channel]) {
switch (adgold->adgold_mma_regs[channel][0xc] & 0x60) {
case 0x00: /*8-bit*/
dat = adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_start[channel]] * 256;
adgold->adgold_mma_out[channel] = dat;
adgold->adgold_mma_fifo_start[channel] = (adgold->adgold_mma_fifo_start[channel] + 1) & 255;
break;
case 0x40: /*12-bit sensible format*/
if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) < 2)
return;
dat = adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_start[channel]] & 0xf0;
adgold->adgold_mma_fifo_start[channel] = (adgold->adgold_mma_fifo_start[channel] + 1) & 255;
dat |= (adgold->adgold_mma_fifo[channel][adgold->adgold_mma_fifo_start[channel]] << 8);
adgold->adgold_mma_fifo_start[channel] = (adgold->adgold_mma_fifo_start[channel] + 1) & 255;
adgold->adgold_mma_out[channel] = dat;
break;
default:
break;
}
if (adgold->adgold_mma_regs[channel][0xc] & 1) {
if (adgold_getsamp_dma(adgold, channel)) {
adgold->adgold_mma_fifo_end[channel] = 0;
adgold->adgold_mma_fifo_start[channel] = 0;
return;
}
}
if (((adgold->adgold_mma_fifo_end[channel] - adgold->adgold_mma_fifo_start[channel]) & 255) < adgold->adgold_mma_intpos[channel] && !(adgold->adgold_mma_status & 0x01)) {
adgold->adgold_mma_status |= (1 << channel);
adgold_update_irq_status(adgold);
}
}
if (adgold->adgold_mma_fifo_start[channel] == adgold->adgold_mma_fifo_end[channel]) {
adgold->adgold_mma_enable[channel] = 0;
}
}
void
adgold_timer_poll(void *priv)
{
adgold_t *adgold = (adgold_t *) priv;
/*A small timer period will result in hangs.*/
timer_advance_u64(&adgold->adgold_mma_timer_count, (uint64_t) ((double) TIMER_USEC * 1.88964));
if (adgold->adgold_midi_ctrl & 0x3f) {
if ((adgold->adgold_midi_ctrl & 0x3f) != 0x3f) {
if (adgold->uart_out)
adgold->adgold_mma_status |= 0x08;
if (adgold->adgold_midi_ctrl & 0x10)
adgold->adgold_mma_status |= 0x80;
}
adgold_update_irq_status(adgold);
}
if (adgold->adgold_mma_regs[0][8] & 0x01) /*Timer 0*/
{
adgold->adgold_mma.timer0_count--;
if (!adgold->adgold_mma.timer0_count) {
adgold->adgold_mma.timer0_count = adgold->adgold_mma.timer0_latch;
adgold->adgold_mma_status |= 0x10;
adgold_update_irq_status(adgold);
}
}
if (adgold->adgold_mma_regs[0][8] & 0x08) /*Base timer*/
{
adgold->adgold_mma.timerbase_count--;
if (!adgold->adgold_mma.timerbase_count) {
adgold->adgold_mma.timerbase_count = adgold->adgold_mma.timerbase_latch;
if (adgold->adgold_mma_regs[0][8] & 0x02) /*Timer 1*/
{
adgold->adgold_mma.timer1_count--;
if (!adgold->adgold_mma.timer1_count) {
adgold->adgold_mma.timer1_count = adgold->adgold_mma.timer1_latch;
adgold->adgold_mma_status |= 0x20;
adgold_update_irq_status(adgold);
}
}
if (adgold->adgold_mma_regs[0][8] & 0x04) /*Timer 2*/
{
adgold->adgold_mma.timer2_count--;
if (!adgold->adgold_mma.timer2_count) {
adgold->adgold_mma.timer2_count = adgold->adgold_mma.timer2_latch;
adgold->adgold_mma_status |= 0x40;
adgold_update_irq_status(adgold);
}
}
}
}
if (adgold->adgold_mma_enable[0]) {
adgold->adgold_mma.voice_count[0]--;
if (!adgold->adgold_mma.voice_count[0]) {
adgold->adgold_mma.voice_count[0] = adgold->adgold_mma.voice_latch[0];
adgold_mma_poll(adgold, 0);
}
}
if (adgold->adgold_mma_enable[1]) {
adgold->adgold_mma.voice_count[1]--;
if (!adgold->adgold_mma.voice_count[1]) {
adgold->adgold_mma.voice_count[1] = adgold->adgold_mma.voice_latch[1];
adgold_mma_poll(adgold, 1);
}
}
}
static void
adgold_get_buffer(int32_t *buffer, int len, void *priv)
{
adgold_t *adgold = (adgold_t *) priv;
int16_t *adgold_buffer = malloc(sizeof(int16_t) * len * 2);
if (adgold_buffer == NULL)
fatal("adgold_buffer = NULL");
int c;
adgold_update(adgold);
for (c = 0; c < len * 2; c += 2) {
adgold_buffer[c] += ((adgold->mma_buffer[0][c >> 1] * adgold->samp_vol_l) >> 7) / 4;
adgold_buffer[c + 1] += ((adgold->mma_buffer[1][c >> 1] * adgold->samp_vol_r) >> 7) / 4;
}
if (adgold->surround_enabled)
ym7128_apply(&adgold->ym7128, adgold_buffer, len);
switch (adgold->adgold_38x_regs[0x8] & 6) {
case 0:
for (c = 0; c < len * 2; c++)
adgold_buffer[c] = 0;
break;
case 2: /*Left channel only*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c + 1] = adgold_buffer[c];
break;
case 4: /*Right channel only*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] = adgold_buffer[c + 1];
break;
case 6: /*Left and right channels*/
break;
default:
break;
}
switch (adgold->adgold_38x_regs[0x8] & 0x18) {
case 0x00: /*Forced mono*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] = adgold_buffer[c + 1] = ((int32_t) adgold_buffer[c] + (int32_t) adgold_buffer[c + 1]) / 2;
break;
case 0x08: /*Linear stereo*/
break;
case 0x10: /*Pseudo stereo*/
/*Filter left channel, leave right channel unchanged*/
/*Filter cutoff is largely a guess*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] += adgold_pseudo_stereo_iir(adgold_buffer[c]);
break;
case 0x18: /*Spatial stereo*/
/*Quite probably wrong, I only have the diagram in the TDA8425 datasheet
and a very vague understanding of how op-amps work to go on*/
for (c = 0; c < len * 2; c += 2) {
int16_t l = adgold_buffer[c];
int16_t r = adgold_buffer[c + 1];
adgold_buffer[c] += (r / 3) + ((l * 2) / 3);
adgold_buffer[c + 1] += (l / 3) + ((r * 2) / 3);
}
break;
default:
break;
}
for (c = 0; c < len * 2; c += 2) {
int32_t temp;
int32_t lowpass;
int32_t highpass;
/*Output is deliberately halved to avoid clipping*/
temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 17;
lowpass = adgold_lowpass_iir(0, 0, temp);
highpass = adgold_highpass_iir(0, 0, temp);
if (adgold->bass > 6)
temp += (lowpass * bass_attenuation[adgold->bass]) >> 14;
else if (adgold->bass < 6)
temp = highpass + ((temp * bass_cut[adgold->bass]) >> 14);
if (adgold->treble > 6)
temp += (highpass * treble_attenuation[adgold->treble]) >> 14;
else if (adgold->treble < 6)
temp = lowpass + ((temp * treble_cut[adgold->treble]) >> 14);
if (temp < -32768)
temp = -32768;
if (temp > 32767)
temp = 32767;
buffer[c] += temp;
temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 17;
lowpass = adgold_lowpass_iir(0, 1, temp);
highpass = adgold_highpass_iir(0, 1, temp);
if (adgold->bass > 6)
temp += (lowpass * bass_attenuation[adgold->bass]) >> 14;
else if (adgold->bass < 6)
temp = highpass + ((temp * bass_cut[adgold->bass]) >> 14);
if (adgold->treble > 6)
temp += (highpass * treble_attenuation[adgold->treble]) >> 14;
else if (adgold->treble < 6)
temp = lowpass + ((temp * treble_cut[adgold->treble]) >> 14);
if (temp < -32768)
temp = -32768;
if (temp > 32767)
temp = 32767;
buffer[c + 1] += temp;
}
adgold->pos = 0;
free(adgold_buffer);
}
static void
adgold_get_music_buffer(int32_t *buffer, int len, void *priv)
{
adgold_t *adgold = (adgold_t *) priv;
int16_t *adgold_buffer = malloc(sizeof(int16_t) * len * 2);
if (adgold_buffer == NULL)
fatal("adgold_buffer = NULL");
int c;
const int32_t *opl_buf = adgold->opl.update(adgold->opl.priv);
adgold_update(adgold);
for (c = 0; c < len * 2; c += 2) {
adgold_buffer[c] = ((opl_buf[c] * adgold->fm_vol_l) >> 7) / 2;
adgold_buffer[c + 1] = ((opl_buf[c + 1] * adgold->fm_vol_r) >> 7) / 2;
}
if (adgold->surround_enabled)
ym7128_apply(&adgold->ym7128, adgold_buffer, len);
switch (adgold->adgold_38x_regs[0x8] & 6) {
case 0:
for (c = 0; c < len * 2; c++)
adgold_buffer[c] = 0;
break;
case 2: /*Left channel only*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c + 1] = adgold_buffer[c];
break;
case 4: /*Right channel only*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] = adgold_buffer[c + 1];
break;
case 6: /*Left and right channels*/
break;
default:
break;
}
switch (adgold->adgold_38x_regs[0x8] & 0x18) {
case 0x00: /*Forced mono*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] = adgold_buffer[c + 1] = ((int32_t) adgold_buffer[c] + (int32_t) adgold_buffer[c + 1]) / 2;
break;
case 0x08: /*Linear stereo*/
break;
case 0x10: /*Pseudo stereo*/
/*Filter left channel, leave right channel unchanged*/
/*Filter cutoff is largely a guess*/
for (c = 0; c < len * 2; c += 2)
adgold_buffer[c] += adgold_pseudo_stereo_iir(adgold_buffer[c]);
break;
case 0x18: /*Spatial stereo*/
/*Quite probably wrong, I only have the diagram in the TDA8425 datasheet
and a very vague understanding of how op-amps work to go on*/
for (c = 0; c < len * 2; c += 2) {
int16_t l = adgold_buffer[c];
int16_t r = adgold_buffer[c + 1];
adgold_buffer[c] += (r / 3) + ((l * 2) / 3);
adgold_buffer[c + 1] += (l / 3) + ((r * 2) / 3);
}
break;
default:
break;
}
for (c = 0; c < len * 2; c += 2) {
int32_t temp;
int32_t lowpass;
int32_t highpass;
/*Output is deliberately halved to avoid clipping*/
temp = ((int32_t) adgold_buffer[c] * adgold->vol_l) >> 17;
lowpass = adgold_lowpass_iir(1, 0, temp);
highpass = adgold_highpass_iir(1, 0, temp);
if (adgold->bass > 6)
temp += (lowpass * bass_attenuation[adgold->bass]) >> 14;
else if (adgold->bass < 6)
temp = highpass + ((temp * bass_cut[adgold->bass]) >> 14);
if (adgold->treble > 6)
temp += (highpass * treble_attenuation[adgold->treble]) >> 14;
else if (adgold->treble < 6)
temp = lowpass + ((temp * treble_cut[adgold->treble]) >> 14);
if (temp < -32768)
temp = -32768;
if (temp > 32767)
temp = 32767;
buffer[c] += temp;
temp = ((int32_t) adgold_buffer[c + 1] * adgold->vol_r) >> 17;
lowpass = adgold_lowpass_iir(1, 1, temp);
highpass = adgold_highpass_iir(1, 1, temp);
if (adgold->bass > 6)
temp += (lowpass * bass_attenuation[adgold->bass]) >> 14;
else if (adgold->bass < 6)
temp = highpass + ((temp * bass_cut[adgold->bass]) >> 14);
if (adgold->treble > 6)
temp += (highpass * treble_attenuation[adgold->treble]) >> 14;
else if (adgold->treble < 6)
temp = lowpass + ((temp * treble_cut[adgold->treble]) >> 14);
if (temp < -32768)
temp = -32768;
if (temp > 32767)
temp = 32767;
buffer[c + 1] += temp;
}
adgold->opl.reset_buffer(adgold->opl.priv);
free(adgold_buffer);
}
static void
adgold_filter_cd_audio(int channel, double *buffer, void *priv)
{
const adgold_t *adgold = (adgold_t *) priv;
double c;
int aux = channel ? adgold->aux_vol_r : adgold->aux_vol_l;
int vol = channel ? adgold->vol_r : adgold->vol_l;
c = ((((*buffer) * aux) / 4096.0) * vol) / 4096.0;
*buffer = c;
}
static void
adgold_input_msg(void *priv, uint8_t *msg, uint32_t len)
{
adgold_t *adgold = (adgold_t *) priv;
if (adgold->sysex)
return;
if (adgold->uart_in) {
adgold->adgold_mma_status |= 0x04;
for (uint32_t i = 0; i < len; i++) {
adgold->midi_queue[adgold->midi_w++] = msg[i];
adgold->midi_w &= 0x0f;
}
adgold_update_irq_status(adgold);
}
}
static int
adgold_input_sysex(void *priv, uint8_t *buffer, uint32_t len, int abort)
{
adgold_t *adgold = (adgold_t *) priv;
if (abort) {
adgold->sysex = 0;
return 0;
}
adgold->sysex = 1;
for (uint32_t i = 0; i < len; i++) {
if (adgold->midi_r == adgold->midi_w)
return (len - i);
adgold->midi_queue[adgold->midi_w++] = buffer[i];
adgold->midi_w &= 0x0f;
}
adgold->sysex = 0;
return 0;
}
void *
adgold_init(UNUSED(const device_t *info))
{
FILE *fp;
int c;
double out;
adgold_t *adgold = malloc(sizeof(adgold_t));
memset(adgold, 0, sizeof(adgold_t));
adgold->dma = device_get_config_int("dma");
adgold->irq = device_get_config_int("irq");
adgold->surround_enabled = device_get_config_int("surround");
adgold->gameport_enabled = device_get_config_int("gameport");
fm_driver_get(FM_YMF262, &adgold->opl);
if (adgold->surround_enabled)
ym7128_init(&adgold->ym7128);
out = 65536.0; /*Main volume control ranges from +6 dB to -64 dB in 2 dB steps, then remaining settings are -80 dB (effectively 0)*/
for (c = 0x3f; c >= 0x1c; c--) {
attenuation[c] = (int) out;
out /= 1.25963; /*2 dB steps*/
}
for (; c >= 0; c--)
attenuation[c] = 0;
adgold->adgold_eeprom[0x00] = 0x00;
adgold->adgold_eeprom[0x01] = 0x00;
adgold->adgold_eeprom[0x02] = 0x7f;
adgold->adgold_eeprom[0x03] = 0x7f;
adgold->adgold_eeprom[0x04] = 0xf8; /* vol_l */
adgold->adgold_eeprom[0x05] = 0xf8; /* vol_r */
adgold->adgold_eeprom[0x06] = 0xf6; /* bass */
adgold->adgold_eeprom[0x07] = 0xf6; /* treble */
adgold->adgold_eeprom[0x08] = 0xce;
adgold->adgold_eeprom[0x09] = 0xff; /* fm_vol_l */
adgold->adgold_eeprom[0x0a] = 0xff; /* fm_vol_r */
adgold->adgold_eeprom[0x0b] = 0xff; /* samp_vol_l */
adgold->adgold_eeprom[0x0c] = 0xff; /* samp_vol_r */
adgold->adgold_eeprom[0x0d] = 0xff; /* aux_vol_l */
adgold->adgold_eeprom[0x0e] = 0xff; /* aux_vol_r */
adgold->adgold_eeprom[0x0f] = 0xff;
adgold->adgold_eeprom[0x10] = 0xff;
adgold->adgold_eeprom[0x11] = 0x20;
adgold->adgold_eeprom[0x12] = 0x00;
adgold->adgold_eeprom[0x13] = 0x00;
adgold->adgold_eeprom[0x14] = 0x00;
adgold->adgold_eeprom[0x15] = 0x388 / 8; /*Present at 388-38f*/
adgold->adgold_eeprom[0x16] = 0x00;
adgold->adgold_eeprom[0x17] = 0x68;
adgold->adgold_eeprom[0x18] = 0x00; /* Surround */
adgold->adgold_eeprom[0x19] = 0x00;
fp = nvr_fopen("adgold.bin", "rb");
if (fp) {
if (fread(adgold->adgold_eeprom, 1, 0x1a, fp) != 0x1a)
fatal("adgold_init(): Error reading data\n");
fclose(fp);
}
adgold->adgold_status = 0xf;
adgold->adgold_38x_addr = 0;
switch (adgold->irq) {
case 3:
adgold->adgold_eeprom[0x13] |= 0x00;
break;
case 4:
adgold->adgold_eeprom[0x13] |= 0x01;
break;
case 5:
adgold->adgold_eeprom[0x13] |= 0x02;
break;
case 7:
adgold->adgold_eeprom[0x13] |= 0x03;
break;
default:
break;
}
adgold->adgold_eeprom[0x13] |= (adgold->dma << 3);
adgold->adgold_eeprom[0x14] |= (adgold->dma << 4);
memcpy(adgold->adgold_38x_regs, adgold->adgold_eeprom, 0x19);
adgold->vol_l = attenuation[adgold->adgold_eeprom[0x04] & 0x3f];
adgold->vol_r = attenuation[adgold->adgold_eeprom[0x05] & 0x3f];
adgold->bass = adgold->adgold_eeprom[0x06] & 0xf;
adgold->treble = adgold->adgold_eeprom[0x07] & 0xf;
adgold->fm_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x09] - 128);
adgold->fm_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0a] - 128);
adgold->samp_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x0b] - 128);
adgold->samp_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0c] - 128);
adgold->aux_vol_l = (int) (int8_t) (adgold->adgold_eeprom[0x0d] - 128);
adgold->aux_vol_r = (int) (int8_t) (adgold->adgold_eeprom[0x0e] - 128);
adgold->adgold_mma_enable[0] = 0;
adgold->adgold_mma_fifo_start[0] = adgold->adgold_mma_fifo_end[0] = 0;
/*388/389 are handled by adlib_init*/
io_sethandler(0x0388, 0x0008, adgold_read, NULL, NULL, adgold_write, NULL, NULL, adgold);
if (adgold->gameport_enabled)
gameport_remap(gameport_add(&gameport_201_device), 0x201);
timer_add(&adgold->adgold_mma_timer_count, adgold_timer_poll, adgold, 1);
sound_add_handler(adgold_get_buffer, adgold);
music_add_handler(adgold_get_music_buffer, adgold);
sound_set_cd_audio_filter(adgold_filter_cd_audio, adgold);
if (device_get_config_int("receive_input"))
midi_in_handler(1, adgold_input_msg, adgold_input_sysex, adgold);
return adgold;
}
void
adgold_close(void *priv)
{
FILE *fp;
adgold_t *adgold = (adgold_t *) priv;
fp = nvr_fopen("adgold.bin", "wb");
if (fp) {
fwrite(adgold->adgold_eeprom, 0x1a, 1, fp);
fclose(fp);
}
free(adgold);
}
static const device_config_t adgold_config[] = {
// clang-format off
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "IRQ 3",
.value = 3
},
{
.description = "IRQ 4",
.value = 4
},
{
.description = "IRQ 5",
.value = 5
},
{
.description = "IRQ 7",
.value = 7
},
{ .description = "" }
}
},
{
.name = "dma",
.description = "Low DMA channel",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 1,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "DMA 1",
.value = 1
},
{
.description = "DMA 3",
.value = 3
},
{ .description = "" }
}
},
{
.name = "gameport",
.description = "Enable Game port",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{
.name = "surround",
.description = "Surround module",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{
.name = "receive_input",
.description = "Receive input (MIDI)",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t adgold_device = {
.name = "AdLib Gold",
.internal_name = "adlibgold",
.flags = DEVICE_ISA,
.local = 0,
.init = adgold_init,
.close = adgold_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = adgold_config
};
``` | /content/code_sandbox/src/sound/snd_adlibgold.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 13,850 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* C-Media CMI8x38 PCI audio controller emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/pci.h>
#include <86box/sound.h>
#include <86box/snd_sb.h>
#include <86box/snd_sb_dsp.h>
#include <86box/gameport.h>
#include <86box/nmi.h>
#include <86box/ui.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
enum {
/* [23:16] = reg 0F [7:0] (reg 0C [31:24])
[13] = onboard flag
[12:8] = reg 0B [4:0] (reg 08 [28:24])
[7:0] = PCI device ID [7:0] */
CMEDIA_CMI8338 = 0x000000,
CMEDIA_CMI8738_4CH = 0x040011, /* chip version 039 with 4-channel output */
CMEDIA_CMI8738_6CH = 0x080011 /* chip version 055 with 6-channel output */
};
enum {
TRAP_DMA = 0,
TRAP_PIC,
TRAP_OPL,
TRAP_MPU,
TRAP_MAX
};
typedef struct cmi8x38_dma_t {
uint8_t id;
uint8_t reg;
uint8_t always_run;
uint8_t playback_enabled;
uint8_t channels;
struct _cmi8x38_ *dev;
uint32_t sample_ptr;
uint32_t fifo_pos;
uint32_t fifo_end;
int32_t frame_count_dma;
int32_t frame_count_fragment;
int32_t sample_count_out;
uint8_t fifo[256];
uint8_t restart;
int16_t out_fl;
int16_t out_fr;
int16_t out_rl;
int16_t out_rr;
int16_t out_c;
int16_t out_lfe;
int vol_l;
int vol_r;
int pos;
int32_t buffer[SOUNDBUFLEN * 2];
uint64_t timer_latch;
double dma_latch;
pc_timer_t dma_timer;
pc_timer_t poll_timer;
} cmi8x38_dma_t;
typedef struct _cmi8x38_ {
uint32_t type;
uint16_t io_base;
uint16_t sb_base;
uint16_t opl_base;
uint16_t mpu_base;
uint8_t pci_regs[256];
uint8_t io_regs[256];
uint8_t pci_slot;
uint8_t irq_state;
sb_t *sb;
void *gameport;
void *io_traps[TRAP_MAX];
cmi8x38_dma_t dma[2];
uint16_t tdma_base_addr;
uint16_t tdma_base_count;
int tdma_8;
int tdma_16;
int tdma_mask;
int prev_mask;
int tdma_irq_mask;
int master_vol_l;
int master_vol_r;
int cd_vol_l;
int cd_vol_r;
} cmi8x38_t;
#ifdef ENABLE_CMI8X38_LOG
int cmi8x38_do_log = ENABLE_CMI8X38_LOG;
static void
cmi8x38_log(const char *fmt, ...)
{
va_list ap;
if (cmi8x38_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cmi8x38_log(fmt, ...)
#endif
static const double freqs[] = { 5512.0, 11025.0, 22050.0, 44100.0, 8000.0, 16000.0, 32000.0, 48000.0 };
static const uint16_t opl_ports_cmi8738[] = { 0x388, 0x3c8, 0x3e0, 0x3e8 };
static void cmi8x38_dma_process(void *priv);
static void cmi8x38_speed_changed(void *priv);
static void
cmi8x38_update_irqs(cmi8x38_t *dev)
{
/* Calculate and use the INTR flag. */
if (*((uint32_t *) &dev->io_regs[0x10]) & 0x0401c003) {
dev->io_regs[0x13] |= 0x80;
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
cmi8x38_log("CMI8x38: Raising IRQ\n");
} else {
dev->io_regs[0x13] &= ~0x80;
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
}
}
static void
cmi8x38_mpu_irq_update(void *priv, int set)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
if (set)
dev->io_regs[0x12] |= 0x01;
else
dev->io_regs[0x12] &= ~0x01;
cmi8x38_update_irqs(dev);
}
static int
cmi8x38_mpu_irq_pending(void *priv)
{
const cmi8x38_t *dev = (cmi8x38_t *) priv;
return dev->io_regs[0x12] & 0x01;
}
static void
cmi8x38_sb_irq_update(void *priv, int set)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Interrupt flag shared with the first DMA channel. Combining SB and
PCI DMA is undefined; the VxD driver disables SB if PCI is in use. */
if (set)
dev->io_regs[0x10] |= 0x01;
else
dev->io_regs[0x10] &= ~0x01;
cmi8x38_update_irqs(dev);
}
static int
cmi8x38_sb_dma_post(cmi8x38_t *dev, uint16_t *addr, uint16_t *count, int channel)
{
/* Increment address and decrement count. */
*addr += 1;
*count -= 1;
/* Copy TDMA registers to DMA on CMI8738+. Everything so far suggests that
those chips use PCI bus mastering to directly write to the DMA registers. */
#if 0 /* TSRs don't set ENWR8237, except for the patched C3DPCI - does that bit have no effect? */
if ((dev->type != CMEDIA_CMI8338) && (dev->io_regs[0x17] & 0x10))
#else
if (dev->type != CMEDIA_CMI8338)
#endif
{
if (channel & 4)
dma[channel].ab = (dma[channel].ab & 0xfffe0000) | ((*addr) << 1);
else
dma[channel].ab = (dma[channel].ab & 0xffff0000) | *addr;
dma[channel].ac = dma[channel].ab;
dma[channel].cc = dma[channel].cb = *count;
}
/* Check TDMA position update interrupt if enabled. */
if (dev->io_regs[0x0e] & 0x04) {
/* Nothing uses this; I assume it goes by the SB DSP sample counter (forwards instead of backwards). */
int origlength = (channel & 4) ? dev->sb->dsp.sb_16_origlength : dev->sb->dsp.sb_8_origlength;
int length = (channel & 4) ? dev->sb->dsp.sb_16_length : dev->sb->dsp.sb_8_length;
if ((origlength != length) && (((origlength - length) & dev->tdma_irq_mask) == 0)) { /* skip initial sample */
/* Fire the interrupt. */
dev->io_regs[0x11] |= (channel & 4) ? 0x40 : 0x80;
cmi8x38_update_irqs(dev);
}
}
/* Handle end of DMA. */
if (*count == 0xffff) {
if (dma[channel].mode & 0x10) { /* auto-init */
/* Restart TDMA. */
*addr = dev->tdma_base_addr;
*count = dev->tdma_base_count;
cmi8x38_log("CMI8x38: Restarting TDMA on DMA %d with addr %08X count %04X\n",
channel,
(channel & 4) ? ((dma[channel].ab & 0xfffe0000) | ((*addr) << 1)) : ((dma[channel].ab & 0xffff0000) | *addr),
*count);
} else {
/* Mask TDMA. */
dev->tdma_mask |= 1 << channel;
}
/* Set the mysterious LHBTOG bit, assuming it corresponds
to the 8237 channel status bit. Nothing reads it. */
dev->io_regs[0x10] |= 0x40;
return DMA_OVER;
}
return 0;
}
static int
cmi8x38_sb_dma_readb(void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Stop if the DMA channel is invalid or if TDMA is masked. */
int channel = dev->tdma_8;
if ((channel < 0) || (dev->tdma_mask & (1 << channel)))
return DMA_NODATA;
/* Get 16-bit address and count registers. */
uint16_t *addr = (uint16_t *) &dev->io_regs[0x1c];
uint16_t *count = (uint16_t *) &dev->io_regs[0x1e];
/* Read data. */
int ret = mem_readb_phys((dma[channel].ab & 0xffff0000) | *addr);
/* Handle address, count and end. */
ret |= cmi8x38_sb_dma_post(dev, addr, count, channel);
return ret;
}
static int
cmi8x38_sb_dma_readw(void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Stop if the DMA channel is invalid or if TDMA is masked. */
int channel = dev->tdma_16;
if ((channel < 0) || (dev->tdma_mask & (1 << channel)))
return DMA_NODATA;
/* Get 16-bit address and count registers. */
uint16_t *addr = (uint16_t *) &dev->io_regs[0x1c];
uint16_t *count = (uint16_t *) &dev->io_regs[0x1e];
/* Read data. */
int ret = mem_readw_phys((dma[channel].ab & 0xfffe0000) | ((*addr) << 1));
/* Handle address, count and end. */
ret |= cmi8x38_sb_dma_post(dev, addr, count, channel);
return ret;
}
static int
cmi8x38_sb_dma_writeb(void *priv, uint8_t val)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Stop if the DMA channel is invalid or if TDMA is masked. */
int channel = dev->tdma_8;
if ((channel < 0) || (dev->tdma_mask & (1 << channel)))
return 1;
/* Get 16-bit address and count registers. */
uint16_t *addr = (uint16_t *) &dev->io_regs[0x1c];
uint16_t *count = (uint16_t *) &dev->io_regs[0x1e];
/* Write data. */
mem_writeb_phys((dma[channel].ab & 0xffff0000) | *addr, val);
/* Handle address, count and end. */
cmi8x38_sb_dma_post(dev, addr, count, channel);
return 0;
}
static int
cmi8x38_sb_dma_writew(void *priv, uint16_t val)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Stop if the DMA channel is invalid or if TDMA is masked. */
int channel = dev->tdma_16;
if ((channel < 0) || (dev->tdma_mask & (1 << channel)))
return 1;
/* Get 16-bit address and count registers. */
uint16_t *addr = (uint16_t *) &dev->io_regs[0x1c];
uint16_t *count = (uint16_t *) &dev->io_regs[0x1e];
/* Write data. */
mem_writew_phys((dma[channel].ab & 0xfffe0000) | ((*addr) << 1), val);
/* Handle address, count and end. */
cmi8x38_sb_dma_post(dev, addr, count, channel);
return 0;
}
static void
cmi8x38_dma_write(uint16_t addr, UNUSED(uint8_t val), void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Stop if DMA channel auto-detection is disabled. This is required for the CMI8338 TSR,
which disables auto-detection while copying the TDMA address/count to the SB DMA channel,
so that those writes don't loop back to the DMA register snoop mechanism implemented here. */
if (!(dev->io_regs[0x27] & 0x01))
return;
/* Stop if this is not a TDMA channel. Also set or
clear the high channel flag while we're here. */
int channel;
if (addr < 0x08) {
channel = addr >> 1;
if (channel != dev->tdma_8)
return;
dev->io_regs[0x10] &= ~0x20;
} else {
channel = 4 | ((addr >> 2) & 3);
if (channel != dev->tdma_16)
return;
dev->io_regs[0x10] |= 0x20;
}
/* Write base address and count. */
uint16_t *daddr = (uint16_t *) &dev->io_regs[0x1c];
uint16_t *count = (uint16_t *) &dev->io_regs[0x1e];
*daddr = dev->tdma_base_addr = dma[channel].ab >> !!(channel & 4);
*count = dev->tdma_base_count = dma[channel].cb;
cmi8x38_log("CMI8x38: Starting TDMA on DMA %d with addr %08X count %04X\n",
channel,
(channel & 4) ? ((dma[channel].ab & 0xfffe0000) | ((*daddr) << 1)) : ((dma[channel].ab & 0xffff0000) | *daddr),
*count);
/* Clear the mysterious LHBTOG bit, assuming it corresponds
to the 8237 channel status bit. Nothing reads it. */
dev->io_regs[0x10] &= ~0x40;
}
static void
cmi8x38_dma_mask_write(UNUSED(uint16_t addr), UNUSED(uint8_t val), void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* See comment on dma_write above. */
if (!(dev->io_regs[0x27] & 0x01))
return;
/* Unmask TDMA on DMA unmasking edge. */
if ((dev->tdma_8 >= 0) && (dev->prev_mask & (1 << dev->tdma_8)) && !(dma_m & (1 << dev->tdma_8)))
dev->tdma_mask &= ~(1 << dev->tdma_8);
else if ((dev->tdma_16 >= 0) && (dev->prev_mask & (1 << dev->tdma_16)) && !(dma_m & (1 << dev->tdma_16)))
dev->tdma_mask &= ~(1 << dev->tdma_16);
dev->prev_mask = dma_m;
}
static void
cmi8338_io_trap(UNUSED(int size), uint16_t addr, uint8_t write, uint8_t val, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
#ifdef ENABLE_CMI8X38_LOG
if (write)
cmi8x38_log("CMI8x38: cmi8338_io_trap(%04X, %02X)\n", addr, val);
else
cmi8x38_log("CMI8x38: cmi8338_io_trap(%04X)\n", addr);
#endif
/* Weird offsets, it's best to just treat the register as a big dword. */
uint32_t *lcs = (uint32_t *) &dev->io_regs[0x14];
*lcs &= ~0x0003dff0;
*lcs |= (addr & 0x0f) << 14;
if (write)
*lcs |= 0x1000 | (val << 4);
/* Raise NMI. */
nmi = 1;
}
static uint8_t
cmi8x38_sb_mixer_read(uint16_t addr, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
const sb_ct1745_mixer_t *mixer = &dev->sb->mixer_sb16;
uint8_t ret = sb_ct1745_mixer_read(addr, dev->sb);
if (addr & 1) {
if ((mixer->index == 0x0e) || (mixer->index >= 0xf0))
ret = mixer->regs[mixer->index];
cmi8x38_log("CMI8x38: sb_mixer_read(1, %02X) = %02X\n", mixer->index, ret);
} else {
cmi8x38_log("CMI8x38: sb_mixer_read(0) = %02X\n", ret);
}
return ret;
}
static void
cmi8x38_sb_mixer_write(uint16_t addr, uint8_t val, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
sb_ct1745_mixer_t *mixer = &dev->sb->mixer_sb16;
/* Our clone mixer has a few differences. */
if (addr & 1) {
cmi8x38_log("CMI8x38: sb_mixer_write(1, %02X, %02X)\n", mixer->index, val);
switch (mixer->index) {
/* Reset interleaved stereo flag for SBPro mode. */
case 0x00:
mixer->regs[0x0e] = 0x00;
break;
/* No dynamic MPU port assignment. */
case 0x84:
return;
/* Some extended registers beyond those accepted by the CT1745. */
case 0xf0:
if (dev->type == CMEDIA_CMI8338)
val &= 0xfe;
mixer->regs[mixer->index] = val;
return;
case 0xf8 ... 0xff:
if (dev->type == CMEDIA_CMI8338)
mixer->regs[mixer->index] = val;
fallthrough;
case 0xf1 ... 0xf7:
return;
default:
break;
}
sb_ct1745_mixer_write(addr, val, dev->sb);
/* No [3F:47] controls. */
mixer->input_gain_L = 0;
mixer->input_gain_R = 0;
mixer->output_gain_L = 1.0;
mixer->output_gain_R = 1.0;
mixer->bass_l = 8;
mixer->bass_r = 8;
mixer->treble_l = 8;
mixer->treble_r = 8;
/* Check interleaved stereo flag for SBPro mode. */
if ((mixer->index == 0x00) || (mixer->index == 0x0e))
sb_dsp_set_stereo(&dev->sb->dsp, mixer->regs[0x0e] & 2);
/* Set TDMA channels if auto-detection is enabled. */
if ((dev->io_regs[0x27] & 0x01) && (mixer->index == 0x81)) {
dev->tdma_8 = dev->sb->dsp.sb_8_dmanum;
if (dev->sb->dsp.sb_type >= SB16)
dev->tdma_16 = dev->sb->dsp.sb_16_dmanum;
}
} else {
cmi8x38_log("CMI8x38: sb_mixer_write(0, %02X)\n", val);
sb_ct1745_mixer_write(addr, val, dev->sb);
}
}
static void
cmi8x38_remap_sb(cmi8x38_t *dev)
{
if (dev->sb_base) {
io_removehandler(dev->sb_base, 0x0004, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_removehandler(dev->sb_base + 8, 0x0002, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_removehandler(dev->sb_base + 4, 0x0002, cmi8x38_sb_mixer_read, NULL, NULL,
cmi8x38_sb_mixer_write, NULL, NULL, dev);
sb_dsp_setaddr(&dev->sb->dsp, 0);
}
dev->sb_base = 0x220;
if (dev->type == CMEDIA_CMI8338)
dev->sb_base += (dev->io_regs[0x17] & 0x80) >> 2;
else
dev->sb_base += (dev->io_regs[0x17] & 0x0c) << 3;
if (!(dev->io_regs[0x04] & 0x08))
dev->sb_base = 0;
cmi8x38_log("CMI8x38: remap_sb(%04X)\n", dev->sb_base);
if (dev->sb_base) {
io_sethandler(dev->sb_base, 0x0004, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_sethandler(dev->sb_base + 8, 0x0002, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
io_sethandler(dev->sb_base + 4, 0x0002, cmi8x38_sb_mixer_read, NULL, NULL,
cmi8x38_sb_mixer_write, NULL, NULL, dev);
sb_dsp_setaddr(&dev->sb->dsp, dev->sb_base);
}
}
static void
cmi8x38_remap_opl(cmi8x38_t *dev)
{
if (dev->opl_base) {
io_removehandler(dev->opl_base, 0x0004, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
}
dev->opl_base = (dev->type == CMEDIA_CMI8338) ? 0x388 : opl_ports_cmi8738[dev->io_regs[0x17] & 0x03];
io_trap_remap(dev->io_traps[TRAP_OPL], (dev->io_regs[0x04] & 0x01) && (dev->io_regs[0x16] & 0x80), dev->opl_base, 4);
if (!(dev->io_regs[0x1a] & 0x08))
dev->opl_base = 0;
cmi8x38_log("CMI8x38: remap_opl(%04X)\n", dev->opl_base);
if (dev->opl_base) {
io_sethandler(dev->opl_base, 0x0004, dev->sb->opl.read, NULL, NULL,
dev->sb->opl.write, NULL, NULL, dev->sb->opl.priv);
}
}
static void
cmi8x38_remap_mpu(cmi8x38_t *dev)
{
if (dev->mpu_base)
mpu401_change_addr(dev->sb->mpu, 0);
/* The CMI8338 datasheet's port range of [300:330] is
inaccurate. Drivers expect [330:300] like CMI8738. */
dev->mpu_base = 0x330 - ((dev->io_regs[0x17] & 0x60) >> 1);
io_trap_remap(dev->io_traps[TRAP_MPU], (dev->io_regs[0x04] & 0x01) && (dev->io_regs[0x16] & 0x20), dev->mpu_base, 2);
if (!(dev->io_regs[0x04] & 0x04))
dev->mpu_base = 0;
cmi8x38_log("CMI8x38: remap_mpu(%04X)\n", dev->mpu_base);
if (dev->mpu_base)
mpu401_change_addr(dev->sb->mpu, dev->mpu_base);
}
static void
cmi8x38_remap_traps(cmi8x38_t *dev)
{
cmi8x38_remap_opl(dev);
cmi8x38_remap_mpu(dev);
io_trap_remap(dev->io_traps[TRAP_DMA], (dev->io_regs[0x04] & 0x01) && (dev->io_regs[0x17] & 0x02), 0x0000, 16);
io_trap_remap(dev->io_traps[TRAP_PIC], (dev->io_regs[0x04] & 0x01) && (dev->io_regs[0x17] & 0x01), 0x0020, 2);
}
static void
cmi8x38_start_playback(cmi8x38_t *dev)
{
uint8_t i;
uint8_t val = dev->io_regs[0x00];
i = !(val & 0x01);
if (!dev->dma[0].playback_enabled && i)
timer_set_delay_u64(&dev->dma[0].poll_timer, dev->dma[0].timer_latch);
dev->dma[0].playback_enabled = i;
i = !(val & 0x02);
if (!dev->dma[1].playback_enabled && i)
timer_set_delay_u64(&dev->dma[1].poll_timer, dev->dma[1].timer_latch);
dev->dma[1].playback_enabled = i;
}
static uint8_t
cmi8x38_read(uint16_t addr, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
addr &= 0xff;
uint8_t ret;
switch (addr) {
case 0x22:
case 0x23:
ret = cmi8x38_sb_mixer_read(addr ^ 1, dev);
break;
case 0x40 ... 0x4f:
if (dev->type == CMEDIA_CMI8338)
goto io_reg;
else
ret = mpu401_read(addr, dev->sb->mpu);
break;
case 0x50 ... 0x5f:
if (dev->type == CMEDIA_CMI8338)
goto io_reg;
else
ret = dev->sb->opl.read(addr, dev->sb->opl.priv);
break;
case 0x80:
case 0x88:
ret = dev->dma[(addr & 0x78) >> 3].sample_ptr;
break;
case 0x81:
case 0x89:
ret = dev->dma[(addr & 0x78) >> 3].sample_ptr >> 8;
break;
case 0x82:
case 0x8a:
ret = dev->dma[(addr & 0x78) >> 3].sample_ptr >> 16;
break;
case 0x83:
case 0x8b:
ret = dev->dma[(addr & 0x78) >> 3].sample_ptr >> 24;
break;
case 0x84:
case 0x8c:
ret = dev->dma[(addr & 0x78) >> 3].frame_count_dma;
break;
case 0x85:
case 0x8d:
ret = dev->dma[(addr & 0x78) >> 3].frame_count_dma >> 8;
break;
case 0x86:
case 0x8e:
ret = dev->dma[(addr & 0x78) >> 3].sample_count_out >> 2;
break;
case 0x87:
case 0x8f:
ret = dev->dma[(addr & 0x78) >> 3].sample_count_out >> 10;
break;
default:
io_reg:
ret = dev->io_regs[addr];
break;
}
cmi8x38_log("CMI8x38: read(%02X) = %02X\n", addr, ret);
return ret;
}
static void
cmi8x38_write(uint16_t addr, uint8_t val, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
addr &= 0xff;
cmi8x38_log("CMI8x38: write(%02X, %02X)\n", addr, val);
switch (addr) {
case 0x00:
val &= 0x0f;
/* Don't care about recording DMA. */
dev->dma[0].always_run = val & 0x01;
dev->dma[1].always_run = val & 0x02;
/* Start playback if requested. */
dev->io_regs[addr] = val;
cmi8x38_start_playback(dev);
break;
case 0x02:
/* Reset or start DMA channels if requested. */
dev->io_regs[addr] = val & 0x0f;
for (int i = 0; i < (sizeof(dev->dma) / sizeof(dev->dma[0])); i++) {
if (val & (0x04 << i)) {
/* Reset DMA channel. */
dev->io_regs[addr] &= ~(0x01 << i); /* clear enable */
dev->io_regs[0x10] &= ~(0x01 << i); /* clear interrupt */
/* Reset Sound Blaster as well when resetting channel 0. */
if ((i == 0) && (dev->sb->dsp.sb_8_enable || dev->sb->dsp.sb_16_enable || dev->sb->dsp.sb_irq8 || dev->sb->dsp.sb_irq16))
dev->sb->dsp.sb_8_enable = dev->sb->dsp.sb_16_enable = dev->sb->dsp.sb_irq8 = dev->sb->dsp.sb_irq16 = 0;
} else if (val & (0x01 << i)) {
/* Start DMA channel. */
cmi8x38_log("CMI8x38: DMA %d trigger\n", i);
dev->dma[i].restart = 1;
cmi8x38_dma_process(&dev->dma[i]);
}
}
/* Start playback along with DMA channels. */
if (dev->io_regs[addr] & 0x03)
cmi8x38_start_playback(dev);
/* Update interrupts. */
cmi8x38_update_irqs(dev);
break;
case 0x04:
/* Enable or disable the game port. */
gameport_remap(dev->gameport, (val & 0x02) ? 0x200 : 0);
/* Enable or disable the legacy devices. */
dev->io_regs[addr] = val;
cmi8x38_remap_sb(dev);
/* remap_mpu called by remap_traps */
/* Enable or disable I/O traps. */
cmi8x38_remap_traps(dev);
break;
case 0x05:
dev->io_regs[addr] = val;
cmi8x38_speed_changed(dev);
break;
case 0x08:
if (dev->type == CMEDIA_CMI8338)
val &= 0x0f;
break;
case 0x09:
if (dev->type == CMEDIA_CMI8338)
return;
/* Update sample rate. */
dev->io_regs[addr] = val;
cmi8x38_speed_changed(dev);
break;
case 0x0a:
case 0x0b:
if (dev->type == CMEDIA_CMI8338)
return;
else
val &= 0xe0;
if (addr == 0x0a) {
/* Set PCI latency timer if requested. */
dev->pci_regs[0x0d] = (val & 0x80) ? 0x48 : 0x20; /* clearing SETLAT48 is undefined */
} else {
/* Update channel count. */
dev->io_regs[addr] = val;
cmi8x38_speed_changed(dev);
}
break;
case 0x0e:
val &= 0x07;
/* Clear interrupts. */
dev->io_regs[0x10] &= val | 0xfc;
if (!(val & 0x04))
dev->io_regs[0x11] &= ~0xc0;
cmi8x38_update_irqs(dev);
break;
case 0x15:
if (dev->type == CMEDIA_CMI8338)
return;
else
val &= 0xf0;
/* Update channel count. */
dev->io_regs[addr] = val;
cmi8x38_speed_changed(dev);
break;
case 0x16:
if (dev->type == CMEDIA_CMI8338) {
val &= 0xa0;
/* Enable or disable I/O traps. */
dev->io_regs[addr] = val;
cmi8x38_remap_traps(dev);
}
break;
case 0x17:
if (dev->type == CMEDIA_CMI8338) {
val &= 0xf3;
/* Force IRQ if requested. Clearing this bit is undefined. */
if (val & 0x10)
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else if ((dev->io_regs[0x17] & 0x10) && !(val & 0x10))
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
/* Enable or disable I/O traps. */
dev->io_regs[addr] = val;
cmi8x38_remap_traps(dev);
}
/* Remap the legacy devices. */
dev->io_regs[addr] = val;
cmi8x38_remap_sb(dev);
cmi8x38_remap_mpu(dev);
break;
case 0x18:
if (dev->type == CMEDIA_CMI8338)
val &= 0x0f;
else
val &= 0xdf;
/* Update the TDMA position update interrupt's sample interval. */
dev->tdma_irq_mask = 2047 >> ((val >> 2) & 3);
break;
case 0x19:
if (dev->type == CMEDIA_CMI8338)
return;
else
val &= 0xe0;
break;
case 0x1a:
val &= 0xfd;
/* Enable or disable the OPL. */
dev->io_regs[addr] = val;
cmi8x38_remap_opl(dev);
break;
case 0x1b:
if (dev->type == CMEDIA_CMI8338)
val &= 0xf4; /* bit 2 reserved, mpxplay driver expects writable */
else
val &= 0xd7;
break;
case 0x20:
/* ??? */
break;
case 0x21:
if (dev->type == CMEDIA_CMI8338)
val &= 0xf7;
else
val &= 0x07;
/* Enable or disable SBPro channel swapping. */
dev->sb->dsp.sbleftright_default = !!(val & 0x02);
/* Enable or disable SB16 mode. */
dev->sb->dsp.sb_type = (val & 0x01) ? SBPRO2 : SB16;
break;
case 0x22:
case 0x23:
cmi8x38_sb_mixer_write(addr ^ 1, val, dev);
return;
case 0x24:
if (dev->type == CMEDIA_CMI8338)
val &= 0xcf;
break;
case 0x27:
if (dev->type == CMEDIA_CMI8338)
val &= 0x03;
else
val &= 0x27;
break;
case 0x40 ... 0x4f:
if (dev->type != CMEDIA_CMI8338)
mpu401_write(addr, val, dev->sb->mpu);
return;
case 0x50 ... 0x5f:
if (dev->type != CMEDIA_CMI8338)
dev->sb->opl.write(addr, val, dev->sb->opl.priv);
return;
case 0x80 ... 0x83:
case 0x88 ... 0x8b:
dev->io_regs[addr] = val;
dev->dma[(addr & 0x78) >> 3].sample_ptr = *((uint32_t *) &dev->io_regs[addr & 0xfc]);
return;
case 0x84 ... 0x85:
case 0x8c ... 0x8d:
dev->io_regs[addr] = val;
dev->dma[(addr & 0x78) >> 3].frame_count_dma = dev->dma[(addr & 0x78) >> 3].sample_count_out = *((uint16_t *) &dev->io_regs[addr & 0xfe]) + 1;
return;
case 0x86 ... 0x87:
case 0x8e ... 0x8f:
dev->io_regs[addr] = val;
dev->dma[(addr & 0x78) >> 3].frame_count_fragment = *((uint16_t *) &dev->io_regs[addr & 0xfe]) + 1;
return;
case 0x92:
if (dev->type == CMEDIA_CMI8338)
return;
else
val &= 0x1f;
break;
case 0x93:
if (dev->type == CMEDIA_CMI8338)
return;
else
val &= 0x10;
break;
case 0x25:
case 0x26:
case 0x70:
case 0x71:
break;
default:
return;
}
dev->io_regs[addr] = val;
}
static void
cmi8x38_remap(cmi8x38_t *dev)
{
if (dev->io_base)
io_removehandler(dev->io_base, 256, cmi8x38_read, NULL, NULL, cmi8x38_write, NULL, NULL, dev);
dev->io_base = (dev->pci_regs[0x04] & 0x01) ? (dev->pci_regs[0x11] << 8) : 0;
cmi8x38_log("CMI8x38: remap(%04X)\n", dev->io_base);
if (dev->io_base)
io_sethandler(dev->io_base, 256, cmi8x38_read, NULL, NULL, cmi8x38_write, NULL, NULL, dev);
}
static uint8_t
cmi8x38_pci_read(int func, int addr, void *priv)
{
const cmi8x38_t *dev = (cmi8x38_t *) priv;
uint8_t ret = 0xff;
if (!func) {
ret = dev->pci_regs[addr];
cmi8x38_log("CMI8x38: pci_read(%02X) = %02X\n", addr, ret);
}
return ret;
}
static void
cmi8x38_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
if (func)
return;
cmi8x38_log("CMI8x38: pci_write(%02X, %02X)\n", addr, val);
switch (addr) {
case 0x04:
val &= 0x05;
/* Enable or disable the I/O BAR. */
dev->pci_regs[addr] = val;
cmi8x38_remap(dev);
break;
case 0x05:
val &= 0x01;
break;
case 0x11:
/* Remap the I/O BAR. */
dev->pci_regs[addr] = val;
cmi8x38_remap(dev);
break;
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
if (!(dev->io_regs[0x1a] & 0x01))
return;
break;
case 0x40:
if (dev->type == CMEDIA_CMI8338)
val &= 0x0f;
else
return;
break;
case 0x0c:
case 0x0d:
case 0x3c:
break;
default:
return;
}
dev->pci_regs[addr] = val;
}
static void
cmi8x38_update(cmi8x38_t *dev, cmi8x38_dma_t *dma)
{
const sb_ct1745_mixer_t *mixer = &dev->sb->mixer_sb16;
int32_t l = (dma->out_fl * mixer->voice_l) * mixer->master_l;
int32_t r = (dma->out_fr * mixer->voice_r) * mixer->master_r;
for (; dma->pos < sound_pos_global; dma->pos++) {
dma->buffer[dma->pos * 2] = l;
dma->buffer[dma->pos * 2 + 1] = r;
}
}
static void
cmi8x38_dma_process(void *priv)
{
cmi8x38_dma_t *dma = (cmi8x38_dma_t *) priv;
cmi8x38_t *dev = dma->dev;
/* Stop if this DMA channel is not active. */
uint8_t dma_bit = 0x01 << dma->id;
if (!(dev->io_regs[0x02] & dma_bit)) {
cmi8x38_log("CMI8x38: Stopping DMA %d due to inactive channel (%02X)\n", dma->id, dev->io_regs[0x02]);
return;
}
/* Schedule next run. */
timer_on_auto(&dma->dma_timer, dma->dma_latch);
/* Process DMA if it's active, and the FIFO has room or is disabled. */
uint8_t dma_status = dev->io_regs[0x00] >> dma->id;
if (!(dma_status & 0x04) && (dma->always_run || ((dma->fifo_end - dma->fifo_pos) <= (sizeof(dma->fifo) - 4)))) {
/* Start DMA if requested. */
if (dma->restart) {
/* Set up base address and counters.
Nothing reads sample_count_out; it's implemented as an assumption. */
dma->restart = 0;
dma->sample_ptr = *((uint32_t *) &dev->io_regs[dma->reg]);
dma->frame_count_dma = dma->sample_count_out = *((uint16_t *) &dev->io_regs[dma->reg | 0x4]) + 1;
dma->frame_count_fragment = *((uint16_t *) &dev->io_regs[dma->reg | 0x6]) + 1;
cmi8x38_log("CMI8x38: Starting DMA %d at %08X (count %04X fragment %04X)\n", dma->id, dma->sample_ptr, dma->frame_count_dma, dma->frame_count_fragment);
}
if (dma_status & 0x01) {
/* Write channel: read data from FIFO. */
mem_writel_phys(dma->sample_ptr, *((uint32_t *) &dma->fifo[dma->fifo_end & (sizeof(dma->fifo) - 1)]));
} else {
/* Read channel: write data to FIFO. */
*((uint32_t *) &dma->fifo[dma->fifo_end & (sizeof(dma->fifo) - 1)]) = mem_readl_phys(dma->sample_ptr);
}
dma->fifo_end += 4;
dma->sample_ptr += 4;
/* Check if the fragment size was reached. */
if (--dma->frame_count_fragment <= 0) {
/* Reset fragment counter. */
dma->frame_count_fragment = *((uint16_t *) &dev->io_regs[dma->reg | 0x6]) + 1;
#ifdef ENABLE_CMI8X38_LOG
if (dma->frame_count_fragment > 1) /* avoid log spam if fragment counting is unused, like on the newer WDM drivers (cmudax3) */
cmi8x38_log("CMI8x38: DMA %d fragment size reached at %04X frames left", dma->id, dma->frame_count_dma - 1);
#endif
/* Fire interrupt if requested. */
if (dev->io_regs[0x0e] & dma_bit) {
#ifdef ENABLE_CMI8X38_LOG
if (dma->frame_count_fragment > 1)
cmi8x38_log(", firing interrupt\n");
#endif
/* Set channel interrupt flag. */
dev->io_regs[0x10] |= dma_bit;
/* Fire interrupt. */
cmi8x38_update_irqs(dev);
} else {
#ifdef ENABLE_CMI8X38_LOG
if (dma->frame_count_fragment > 1)
cmi8x38_log("\n");
#endif
}
}
/* Check if the buffer's end was reached. */
if (--dma->frame_count_dma <= 0) {
dma->frame_count_dma = 0;
cmi8x38_log("CMI8x38: DMA %d end reached, restarting\n", dma->id);
/* Restart DMA on the next run. */
dma->restart = 1;
}
}
}
static void
cmi8x38_poll(void *priv)
{
cmi8x38_dma_t *dma = (cmi8x38_dma_t *) priv;
cmi8x38_t *dev = dma->dev;
int16_t *out_l;
int16_t *out_r;
int16_t *out_ol;
int16_t *out_or; /* o = opposite */
/* Schedule next run if playback is enabled. */
if (dma->playback_enabled)
timer_advance_u64(&dma->poll_timer, dma->timer_latch);
/* Update audio buffer. */
cmi8x38_update(dev, dma);
/* Swap stereo pair if this is the rear DMA channel according to ENDBDAC and XCHGDAC. */
if ((dev->io_regs[0x1a] & 0x80) && (!!(dev->io_regs[0x1a] & 0x40) ^ dma->id)) {
out_l = &dma->out_rl;
out_r = &dma->out_rr;
out_ol = &dma->out_fl;
out_or = &dma->out_fr;
} else {
out_l = &dma->out_fl;
out_r = &dma->out_fr;
out_ol = &dma->out_rl;
out_or = &dma->out_rr;
}
*out_ol = *out_or = dma->out_c = dma->out_lfe = 0;
/* Feed next sample from the FIFO. */
switch ((dev->io_regs[0x08] >> (dma->id << 1)) & 0x03) {
case 0x00: /* Mono, 8-bit PCM */
if ((dma->fifo_end - dma->fifo_pos) >= 1) {
*out_l = *out_r = (dma->fifo[dma->fifo_pos++ & (sizeof(dma->fifo) - 1)] ^ 0x80) << 8;
dma->sample_count_out--;
goto n4spk3d;
}
break;
case 0x01: /* Stereo, 8-bit PCM */
if ((dma->fifo_end - dma->fifo_pos) >= 2) {
*out_l = (dma->fifo[dma->fifo_pos++ & (sizeof(dma->fifo) - 1)] ^ 0x80) << 8;
*out_r = (dma->fifo[dma->fifo_pos++ & (sizeof(dma->fifo) - 1)] ^ 0x80) << 8;
dma->sample_count_out -= 2;
goto n4spk3d;
}
break;
case 0x02: /* Mono, 16-bit PCM */
if ((dma->fifo_end - dma->fifo_pos) >= 2) {
*out_l = *out_r = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->sample_count_out -= 2;
goto n4spk3d;
}
break;
case 0x03: /* Stereo, 16-bit PCM, with multi-channel capability */
switch (dma->channels) {
case 2:
if ((dma->fifo_end - dma->fifo_pos) >= 4) {
*out_l = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
*out_r = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->sample_count_out -= 4;
goto n4spk3d;
}
break;
case 4:
if ((dma->fifo_end - dma->fifo_pos) >= 8) {
dma->out_fl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_fr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->sample_count_out -= 8;
return;
}
break;
case 5: /* not supported by WDM and Linux drivers; channel layout assumed */
if ((dma->fifo_end - dma->fifo_pos) >= 10) {
dma->out_fl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_fr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_c = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->sample_count_out -= 10;
return;
}
break;
case 6:
if ((dma->fifo_end - dma->fifo_pos) >= 12) {
dma->out_fl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_fr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rl = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_rr = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_c = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->out_lfe = *((uint16_t *) &dma->fifo[dma->fifo_pos & (sizeof(dma->fifo) - 1)]);
dma->fifo_pos += 2;
dma->sample_count_out -= 12;
return;
}
break;
default:
break;
}
break;
default:
break;
}
/* Feed silence if the FIFO is empty. */
*out_l = *out_r = 0;
/* Stop playback if DMA is disabled. */
if ((*((uint32_t *) &dev->io_regs[0x00]) & (0x00010001 << dma->id)) != (0x00010000 << dma->id)) {
cmi8x38_log("CMI8x38: Stopping playback of DMA channel %d\n", dma->id);
dma->playback_enabled = 0;
}
return;
n4spk3d:
/* Mirror front and rear channels if requested. */
if (dev->io_regs[0x1b] & 0x04) {
*out_ol = *out_l;
*out_or = *out_r;
}
}
static void
cmi8x38_get_buffer(int32_t *buffer, int len, void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Update wave playback channels. */
cmi8x38_update(dev, &dev->dma[0]);
cmi8x38_update(dev, &dev->dma[1]);
/* Apply wave mute. */
if (!(dev->io_regs[0x24] & 0x40)) {
/* Fill buffer. */
for (int c = 0; c < len * 2; c++) {
buffer[c] += dev->dma[0].buffer[c];
buffer[c] += dev->dma[1].buffer[c];
}
}
dev->dma[0].pos = dev->dma[1].pos = 0;
}
static void
cmi8x38_speed_changed(void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
double freq;
uint8_t dsr = dev->io_regs[0x09];
uint8_t freqreg = dev->io_regs[0x05] >> 2;
uint8_t chfmt45 = dev->io_regs[0x0b];
uint8_t chfmt6 = dev->io_regs[0x15];
#ifdef ENABLE_CMI8X38_LOG
char buf[256];
sprintf(buf, "%02X-%02X-%02X-%02X", dsr, freqreg, chfmt45, chfmt6);
#endif
/* CMI8338 claims the frequency controls are for DAC (playback) and ADC (recording)
respectively, while CMI8738 claims they're for channel 0 and channel 1. The Linux
driver just assumes the latter definition, so that's what we're going to use here. */
for (int i = 0; i < (sizeof(dev->dma) / sizeof(dev->dma[0])); i++) {
/* More confusion. The Linux driver implies the sample rate doubling
bits take precedence over any configured sample rate. 128K with both
doubling bits set is also supported there, but that's for newer chips. */
switch (dsr & 0x03) {
case 0x01:
freq = 88200.0;
break;
case 0x02:
freq = 96000.0;
break;
#if 0
case 0x03:
freq = 128000.0;
break;
#endif
default:
freq = freqs[freqreg & 0x07];
break;
}
/* Set polling timer period. */
freq = 1000000.0 / freq;
dev->dma[i].timer_latch = (uint64_t) ((double) TIMER_USEC * freq);
/* Calculate channel count and set DMA timer period. */
if ((dev->type == CMEDIA_CMI8338) || (i == 0)) { /* multi-channel requires channel 1 */
stereo:
dev->dma[i].channels = 2;
} else {
if (chfmt45 & 0x80)
dev->dma[i].channels = (chfmt6 & 0x80) ? 6 : 5;
else if (chfmt45 & 0x20)
dev->dma[i].channels = 4;
else
goto stereo;
}
dev->dma[i].dma_latch = freq / dev->dma[i].channels; /* frequency / approximately(dwords * 2) */
/* Shift sample rate configuration registers. */
#ifdef ENABLE_CMI8X38_LOG
sprintf(&buf[strlen(buf)], " %d:%X-%X-%.0f-%dC", i, dsr & 0x03, freqreg & 0x07, 1000000.0 / freq, dev->dma[i].channels);
#endif
dsr >>= 2;
freqreg >>= 3;
}
#ifdef ENABLE_CMI8X38_LOG
if (cmi8x38_do_log)
ui_sb_bugui(buf);
#endif
}
static void
cmi8x38_reset(void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
/* Reset PCI configuration registers. */
memset(dev->pci_regs, 0, sizeof(dev->pci_regs));
dev->pci_regs[0x00] = 0xf6;
dev->pci_regs[0x01] = 0x13;
dev->pci_regs[0x02] = dev->type;
dev->pci_regs[0x03] = 0x01;
dev->pci_regs[0x06] = (dev->type == CMEDIA_CMI8338) ? 0x80 : 0x10;
dev->pci_regs[0x07] = 0x02;
dev->pci_regs[0x08] = 0x10;
dev->pci_regs[0x0a] = 0x01;
dev->pci_regs[0x0b] = 0x04;
dev->pci_regs[0x0d] = 0x20;
dev->pci_regs[0x10] = 0x01;
dev->pci_regs[0x2c] = 0xf6;
dev->pci_regs[0x2d] = 0x13;
if (dev->type == CMEDIA_CMI8338) {
dev->pci_regs[0x2e] = 0xff;
dev->pci_regs[0x2f] = 0xff;
} else {
dev->pci_regs[0x2e] = dev->type;
dev->pci_regs[0x2f] = 0x01;
dev->pci_regs[0x34] = 0x40;
}
dev->pci_regs[0x3d] = 0x01;
dev->pci_regs[0x3e] = 0x02;
dev->pci_regs[0x3f] = 0x18;
/* Reset I/O space registers. */
memset(dev->io_regs, 0, sizeof(dev->io_regs));
dev->io_regs[0x0b] = (dev->type >> 8) & 0x1f;
dev->io_regs[0x0f] = dev->type >> 16;
dev->tdma_irq_mask = 2047;
/* Reset I/O mappings. */
cmi8x38_remap(dev);
cmi8x38_remap_sb(dev);
/* remap_mpu and remap_opl called by remap_traps */
cmi8x38_remap_traps(dev);
/* Reset DMA channels. */
for (int i = 0; i < (sizeof(dev->dma) / sizeof(dev->dma[0])); i++) {
dev->dma[i].playback_enabled = 0;
dev->dma[i].fifo_pos = dev->dma[i].fifo_end = 0;
memset(dev->dma[i].fifo, 0, sizeof(dev->dma[i].fifo));
}
/* Reset TDMA channel. */
dev->tdma_8 = 1;
dev->tdma_16 = 5;
dev->tdma_mask = 0;
/* Reset Sound Blaster 16 mixer. */
sb_ct1745_mixer_reset(dev->sb);
}
static void *
cmi8x38_init(const device_t *info)
{
cmi8x38_t *dev = malloc(sizeof(cmi8x38_t));
memset(dev, 0, sizeof(cmi8x38_t));
/* Set the chip type. */
if ((info->local == CMEDIA_CMI8738_6CH) && !device_get_config_int("six_channel"))
dev->type = CMEDIA_CMI8738_4CH;
else
dev->type = info->local;
cmi8x38_log("CMI8x38: init(%06X)\n", dev->type);
/* Initialize Sound Blaster 16. */
dev->sb = device_add_inst(device_get_config_int("receive_input") ? &sb_16_compat_device : &sb_16_compat_nompu_device, 1);
dev->sb->opl_enabled = 1; /* let snd_sb.c handle the OPL3 */
dev->sb->mixer_sb16.output_filter = 0; /* no output filtering */
/* Initialize legacy interrupt and DMA handlers. */
mpu401_irq_attach(dev->sb->mpu, cmi8x38_mpu_irq_update, cmi8x38_mpu_irq_pending, dev);
sb_dsp_irq_attach(&dev->sb->dsp, cmi8x38_sb_irq_update, dev);
sb_dsp_dma_attach(&dev->sb->dsp, cmi8x38_sb_dma_readb, cmi8x38_sb_dma_readw, cmi8x38_sb_dma_writeb, cmi8x38_sb_dma_writew, dev);
io_sethandler(0x00, 8, NULL, NULL, NULL, cmi8x38_dma_write, NULL, NULL, dev);
io_sethandler(0x08, 8, NULL, NULL, NULL, cmi8x38_dma_mask_write, NULL, NULL, dev);
io_sethandler(0xc0, 16, NULL, NULL, NULL, cmi8x38_dma_write, NULL, NULL, dev);
io_sethandler(0xd0, 16, NULL, NULL, NULL, cmi8x38_dma_mask_write, NULL, NULL, dev);
/* Initialize DMA channels. */
for (int i = 0; i < (sizeof(dev->dma) / sizeof(dev->dma[0])); i++) {
dev->dma[i].id = i;
dev->dma[i].reg = 0x80 + (8 * i);
dev->dma[i].dev = dev;
timer_add(&dev->dma[i].dma_timer, cmi8x38_dma_process, &dev->dma[i], 0);
timer_add(&dev->dma[i].poll_timer, cmi8x38_poll, &dev->dma[i], 0);
}
cmi8x38_speed_changed(dev);
/* Initialize playback handler and CD audio filter. */
sound_add_handler(cmi8x38_get_buffer, dev);
sound_set_cd_audio_filter(sb16_awe32_filter_cd_audio, dev->sb);
/* Initialize game port. */
dev->gameport = gameport_add(&gameport_pnp_device);
/* Initialize I/O traps. */
if (dev->type == CMEDIA_CMI8338) {
dev->io_traps[TRAP_DMA] = io_trap_add(cmi8338_io_trap, dev);
dev->io_traps[TRAP_PIC] = io_trap_add(cmi8338_io_trap, dev);
dev->io_traps[TRAP_OPL] = io_trap_add(cmi8338_io_trap, dev);
dev->io_traps[TRAP_MPU] = io_trap_add(cmi8338_io_trap, dev);
}
/* Add PCI card. */
pci_add_card((info->local & (1 << 13)) ? PCI_ADD_SOUND : PCI_ADD_NORMAL, cmi8x38_pci_read, cmi8x38_pci_write, dev, &dev->pci_slot);
/* Perform initial reset. */
cmi8x38_reset(dev);
return dev;
}
static void
cmi8x38_close(void *priv)
{
cmi8x38_t *dev = (cmi8x38_t *) priv;
cmi8x38_log("CMI8x38: close()\n");
for (int i = 0; i < TRAP_MAX; i++)
io_trap_remove(dev->io_traps[i]);
free(dev);
}
static const device_config_t cmi8x38_config[] = {
// clang-format off
{
.name = "receive_input",
.description = "Receive input (MPU-401)",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_config_t cmi8738_config[] = {
// clang-format off
{
.name = "six_channel",
.description = "6CH variant (6-channel)",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{
.name = "receive_input",
.description = "Receive input (MPU-401)",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 1
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t cmi8338_device = {
.name = "C-Media CMI8338",
.internal_name = "cmi8338",
.flags = DEVICE_PCI,
.local = CMEDIA_CMI8338,
.init = cmi8x38_init,
.close = cmi8x38_close,
.reset = cmi8x38_reset,
{ .available = NULL },
.speed_changed = cmi8x38_speed_changed,
.force_redraw = NULL,
.config = cmi8x38_config
};
const device_t cmi8338_onboard_device = {
.name = "C-Media CMI8338 (On-Board)",
.internal_name = "cmi8338_onboard",
.flags = DEVICE_PCI,
.local = CMEDIA_CMI8338 | (1 << 13),
.init = cmi8x38_init,
.close = cmi8x38_close,
.reset = cmi8x38_reset,
{ .available = NULL },
.speed_changed = cmi8x38_speed_changed,
.force_redraw = NULL,
.config = cmi8x38_config
};
const device_t cmi8738_device = {
.name = "C-Media CMI8738",
.internal_name = "cmi8738",
.flags = DEVICE_PCI,
.local = CMEDIA_CMI8738_6CH,
.init = cmi8x38_init,
.close = cmi8x38_close,
.reset = cmi8x38_reset,
{ .available = NULL },
.speed_changed = cmi8x38_speed_changed,
.force_redraw = NULL,
.config = cmi8738_config
};
const device_t cmi8738_onboard_device = {
.name = "C-Media CMI8738 (On-Board)",
.internal_name = "cmi8738_onboard",
.flags = DEVICE_PCI,
.local = CMEDIA_CMI8738_4CH | (1 << 13),
.init = cmi8x38_init,
.close = cmi8x38_close,
.reset = cmi8x38_reset,
{ .available = NULL },
.speed_changed = cmi8x38_speed_changed,
.force_redraw = NULL,
.config = cmi8x38_config
};
const device_t cmi8738_6ch_onboard_device = {
.name = "C-Media CMI8738-6CH (On-Board)",
.internal_name = "cmi8738_6ch_onboard",
.flags = DEVICE_PCI,
.local = CMEDIA_CMI8738_6CH | (1 << 13),
.init = cmi8x38_init,
.close = cmi8x38_close,
.reset = cmi8x38_reset,
{ .available = NULL },
.speed_changed = cmi8x38_speed_changed,
.force_redraw = NULL,
.config = cmi8x38_config
};
``` | /content/code_sandbox/src/sound/snd_cmi8x38.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 16,351 |
```c
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/sound.h>
#include <86box/snd_sn76489.h>
#include <86box/plat_unused.h>
int sn76489_mute;
static float volslog[16] = {
0.00000f, 0.59715f, 0.75180f, 0.94650f,
1.19145f, 1.50000f, 1.88835f, 2.37735f,
2.99295f, 3.76785f, 4.74345f, 5.97165f,
7.51785f, 9.46440f, 11.9194f, 15.0000f
};
static int
sn76489_check_tap_2(sn76489_t *sn76489)
{
int ret = ((sn76489->shift >> sn76489->white_noise_tap_2) & 1);
return (sn76489->type == SN76496) ? ret : !ret;
}
static void
sn76489_update(sn76489_t *sn76489)
{
for (; sn76489->pos < sound_pos_global; sn76489->pos++) {
int16_t result = 0;
for (uint8_t c = 1; c < 4; c++) {
if (sn76489->latch[c] > 256)
result += (int16_t) (volslog[sn76489->vol[c]] * sn76489->stat[c]);
else
result += (int16_t) (volslog[sn76489->vol[c]] * 127);
sn76489->count[c] -= (256 * sn76489->psgconst);
while (sn76489->count[c] < 0) {
sn76489->count[c] += sn76489->latch[c];
sn76489->stat[c] = -sn76489->stat[c];
}
}
result += (((sn76489->shift & 1) ^ 1) * 127 * volslog[sn76489->vol[0]] * 2);
sn76489->count[0] -= (512 * sn76489->psgconst);
while ((sn76489->count[0] < 0) && sn76489->latch[0]) {
sn76489->count[0] += (sn76489->latch[0] * 4);
if (!(sn76489->noise & 4)) {
if ((sn76489->shift >> sn76489->white_noise_tap_1) & 1) {
sn76489->shift >>= 1;
sn76489->shift |= sn76489->feedback_mask;
} else
sn76489->shift >>= 1;
} else {
if (((sn76489->shift >> sn76489->white_noise_tap_1) & 1) ^ sn76489_check_tap_2(sn76489)) {
sn76489->shift >>= 1;
sn76489->shift |= sn76489->feedback_mask;
} else
sn76489->shift >>= 1;
}
}
sn76489->buffer[sn76489->pos] = (sn76489->type == NCR8496) ? -result : result;
}
}
static void
sn76489_get_buffer(int32_t *buffer, int len, void *priv)
{
sn76489_t *sn76489 = (sn76489_t *) priv;
sn76489_update(sn76489);
if (!sn76489_mute) {
for (int c = 0; c < len * 2; c++)
buffer[c] += sn76489->buffer[c >> 1];
}
sn76489->pos = 0;
}
static void
sn76489_write(UNUSED(uint16_t addr), uint8_t data, void *priv)
{
sn76489_t *sn76489 = (sn76489_t *) priv;
int freq;
sn76489_update(sn76489);
if (data & 0x80) {
sn76489->firstdat = data;
switch (data & 0x70) {
case 0:
sn76489->freqlo[3] = data & 0xf;
sn76489->latch[3] = (sn76489->freqlo[3] | (sn76489->freqhi[3] << 4)) << 6;
if (!sn76489->extra_divide)
sn76489->latch[3] &= 0x3ff;
if (!sn76489->latch[3])
sn76489->latch[3] = (sn76489->extra_divide ? 2048 : 1024) << 6;
sn76489->lasttone = 3;
break;
case 0x10:
data &= 0xf;
sn76489->vol[3] = 0xf - data;
break;
case 0x20:
sn76489->freqlo[2] = data & 0xf;
sn76489->latch[2] = (sn76489->freqlo[2] | (sn76489->freqhi[2] << 4)) << 6;
if (!sn76489->extra_divide)
sn76489->latch[2] &= 0x3ff;
if (!sn76489->latch[2])
sn76489->latch[2] = (sn76489->extra_divide ? 2048 : 1024) << 6;
sn76489->lasttone = 2;
break;
case 0x30:
data &= 0xf;
sn76489->vol[2] = 0xf - data;
break;
case 0x40:
sn76489->freqlo[1] = data & 0xf;
sn76489->latch[1] = (sn76489->freqlo[1] | (sn76489->freqhi[1] << 4)) << 6;
if (!sn76489->extra_divide)
sn76489->latch[1] &= 0x3ff;
if (!sn76489->latch[1])
sn76489->latch[1] = (sn76489->extra_divide ? 2048 : 1024) << 6;
sn76489->lasttone = 1;
break;
case 0x50:
data &= 0xf;
sn76489->vol[1] = 0xf - data;
break;
case 0x60:
if (((data & 4) != (sn76489->noise & 4)) || (sn76489->type == SN76496))
sn76489->shift = sn76489->feedback_mask;
sn76489->noise = data & 0xf;
if ((data & 3) == 3)
sn76489->latch[0] = sn76489->latch[1];
else
sn76489->latch[0] = 0x400 << (data & 3);
if (!sn76489->latch[0])
sn76489->latch[0] = (sn76489->extra_divide ? 2048 : 1024) << 6;
break;
case 0x70:
data &= 0xf;
sn76489->vol[0] = 0xf - data;
break;
default:
break;
}
} else {
/* NCR8496 ignores writes to registers 1, 3, 5, 6 and 7 with bit 7 clear. */
if ((sn76489->type != SN76496) && ((sn76489->firstdat & 0x10) || ((sn76489->firstdat & 0x70) == 0x60)))
return;
if ((sn76489->firstdat & 0x70) == 0x60 && (sn76489->type == SN76496)) {
if (sn76489->type == SN76496)
sn76489->shift = sn76489->feedback_mask;
sn76489->noise = data & 0xf;
if ((data & 3) == 3)
sn76489->latch[0] = sn76489->latch[1];
else
sn76489->latch[0] = 0x400 << (data & 3);
if (!sn76489->latch[0])
sn76489->latch[0] = (sn76489->extra_divide ? 2048 : 1024) << 6;
} else if ((sn76489->firstdat & 0x70) != 0x60) {
sn76489->freqhi[sn76489->lasttone] = data & 0x7F;
freq = sn76489->freqlo[sn76489->lasttone] |
(sn76489->freqhi[sn76489->lasttone] << 4);
if (!sn76489->extra_divide)
freq &= 0x3ff;
if (!freq)
freq = sn76489->extra_divide ? 2048 : 1024;
if ((sn76489->noise & 3) == 3 && sn76489->lasttone == 1)
sn76489->latch[0] = freq << 6;
sn76489->latch[sn76489->lasttone] = freq << 6;
}
}
}
void
sn74689_set_extra_divide(sn76489_t *sn76489, int enable)
{
sn76489->extra_divide = enable;
if (!enable) {
for (uint8_t c = 1; c < 4; c++)
sn76489->latch[c] &= ~(0x400 << 6);
sn76489->latch[0] &= ~(0x400 << 6);
}
}
void
sn76489_init(sn76489_t *sn76489, uint16_t base, uint16_t size, int type, int freq)
{
sound_add_handler(sn76489_get_buffer, sn76489);
if (type == SN76496) {
sn76489->white_noise_tap_1 = 0;
sn76489->white_noise_tap_2 = 1;
sn76489->feedback_mask = 0x4000;
} else {
sn76489->white_noise_tap_1 = 1;
sn76489->white_noise_tap_2 = 5;
sn76489->feedback_mask = 0x8000;
}
sn76489->latch[0] = sn76489->latch[1] = sn76489->latch[2] = sn76489->latch[3] = 0x3FF << 6;
sn76489->vol[0] = 0;
sn76489->vol[1] = sn76489->vol[2] = sn76489->vol[3] = 8;
sn76489->stat[0] = sn76489->stat[1] = sn76489->stat[2] = sn76489->stat[3] = 127;
srand(time(NULL));
sn76489->count[0] = 0;
sn76489->count[1] = (rand() & 0x3FF) << 6;
sn76489->count[2] = (rand() & 0x3FF) << 6;
sn76489->count[3] = (rand() & 0x3FF) << 6;
sn76489->noise = 3;
sn76489->shift = sn76489->feedback_mask;
sn76489->type = type;
sn76489->psgconst = (((double) freq / 64.0) / (double) FREQ_48000);
sn76489_mute = 0;
io_sethandler(base, size, NULL, NULL, NULL, sn76489_write, NULL, NULL, sn76489);
}
void *
sn76489_device_init(UNUSED(const device_t *info))
{
sn76489_t *sn76489 = malloc(sizeof(sn76489_t));
memset(sn76489, 0, sizeof(sn76489_t));
sn76489_init(sn76489, 0x00c0, 0x0008, SN76496, 3579545);
return sn76489;
}
void *
ncr8496_device_init(UNUSED(const device_t *info))
{
sn76489_t *sn76489 = malloc(sizeof(sn76489_t));
memset(sn76489, 0, sizeof(sn76489_t));
sn76489_init(sn76489, 0x00c0, 0x0008, NCR8496, 3579545);
return sn76489;
}
void *
tndy_device_init(UNUSED(const device_t *info))
{
sn76489_t *sn76489 = malloc(sizeof(sn76489_t));
memset(sn76489, 0, sizeof(sn76489_t));
uint16_t addr = device_get_config_hex16("base");
sn76489_init(sn76489, addr, 0x0008, SN76496, 3579545);
return sn76489;
}
void
sn76489_device_close(void *priv)
{
sn76489_t *sn76489 = (sn76489_t *) priv;
free(sn76489);
}
static const device_config_t tndy_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x0C0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "0x0C0",
.value = 0x0C0
},
{
.description = "0x0E0",
.value = 0x0E0
},
{
.description = "0x1C0",
.value = 0x1C0
},
{
.description = "0x1E0",
.value = 0x1E0
},
{
.description = "0x2C0",
.value = 0x2C0
},
{
.description = "0x2E0",
.value = 0x2E0
},
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t sn76489_device = {
.name = "TI SN74689 PSG",
.internal_name = "sn76489",
.flags = 0,
.local = 0,
.init = sn76489_device_init,
.close = sn76489_device_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ncr8496_device = {
.name = "NCR8496 PSG",
.internal_name = "ncr8496",
.flags = 0,
.local = 0,
.init = ncr8496_device_init,
.close = sn76489_device_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t tndy_device = {
.name = "TNDY",
.internal_name = "tndy",
.flags = DEVICE_ISA,
.local = 0,
.init = tndy_device_init,
.close = sn76489_device_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = tndy_config
};
``` | /content/code_sandbox/src/sound/snd_sn76489.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,684 |
```c
/* Table taken from linux/sound/drivers/opl4/yrw801.c */
/* Macros from Linux source code as well */
#include "yrw801.h"
static const YRW801_REGION_DATA regions_00[] = {
/* Acoustic Grand Piano */
{ 0x14, 0x27, { 0x12c, 7474, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x12d, 6816, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12e, 5899, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12f, 5290, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x130, 4260, 100, 0, 0, 0x0a, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x131, 3625, 100, 0, 0, 0x0a, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x132, 3116, 100, 0, 0, 0x04, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x133, 2081, 100, 0, 0, 0x03, 0xc8, 0x20, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x53, 0x58, { 0x134, 1444, 100, 0, 0, 0x07, 0xc8, 0x20, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x59, 0x6d, { 0x135, 1915, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf4, 0x15, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_01[] = {
/* Bright Acoustic Piano */
{ 0x14, 0x2d, { 0x12c, 7474, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12d, 6816, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12e, 5899, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x12f, 5290, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x130, 4260, 100, 0, 0, 0x0a, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x131, 3625, 100, 0, 0, 0x0a, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x132, 3116, 100, 0, 0, 0x04, 0xc8, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x53, 0x58, { 0x133, 2081, 100, 0, 0, 0x07, 0xc8, 0x20, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x59, 0x5e, { 0x134, 1444, 100, 0, 0, 0x0a, 0xc8, 0x20, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x5f, 0x6d, { 0x135, 1915, 100, 0, 0, 0x00, 0xc8, 0x20, 0xf4, 0x15, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_02[] = {
/* Electric Grand Piano */
{ 0x14, 0x2d, { 0x12c, 7476, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x13, 0x07, 0x0 } },
{ 0x2e, 0x33, { 0x12d, 6818, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x34, 0x39, { 0x12e, 5901, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x3a, 0x3f, { 0x12f, 5292, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x40, 0x45, { 0x130, 4262, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x46, 0x4b, { 0x131, 3627, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x4c, 0x52, { 0x132, 3118, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x07, 0x0 } },
{ 0x53, 0x58, { 0x133, 2083, 100, 1, 0, 0x00, 0xae, 0x20, 0xf2, 0x14, 0x17, 0x0 } },
{ 0x59, 0x5e, { 0x134, 1446, 100, 1, 0, 0x00, 0xae, 0x20, 0xf3, 0x14, 0x17, 0x0 } },
{ 0x5f, 0x6d, { 0x135, 1917, 100, 1, 0, 0x00, 0xae, 0x20, 0xf4, 0x15, 0x07, 0x0 } },
{ 0x00, 0x7f, { 0x06c, 6375, 100, -1, 0, 0x00, 0xc2, 0x28, 0xf4, 0x23, 0x18, 0x0 }}
};
static const YRW801_REGION_DATA regions_03[] = {
/* Honky-Tonk Piano */
{ 0x14, 0x27, { 0x12c, 7474, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x12d, 6816, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12e, 5899, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12f, 5290, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x130, 4260, 100, 0, 0, 0x0a, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x131, 3625, 100, 0, 0, 0x0a, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x132, 3116, 100, 0, 0, 0x04, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x133, 2081, 100, 0, 0, 0x03, 0xb4, 0x20, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x53, 0x58, { 0x134, 1444, 100, 0, 0, 0x07, 0xb4, 0x20, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x59, 0x6d, { 0x135, 1915, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf4, 0x15, 0x08, 0x0 }},
{ 0x14, 0x27, { 0x12c, 7486, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x12d, 6803, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12e, 5912, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12f, 5275, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x130, 4274, 100, 0, 0, 0x0a, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x131, 3611, 100, 0, 0, 0x0a, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x132, 3129, 100, 0, 0, 0x04, 0xb4, 0x20, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x133, 2074, 100, 0, 0, 0x07, 0xb4, 0x20, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x53, 0x58, { 0x134, 1457, 100, 0, 0, 0x01, 0xb4, 0x20, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x59, 0x6d, { 0x135, 1903, 100, 0, 0, 0x00, 0xb4, 0x20, 0xf4, 0x15, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_04[] = {
/* Electric Piano 1 */
{ 0x15, 0x6c, { 0x00b, 6570, 100, 0, 0, 0x00, 0x28, 0x38, 0xf0, 0x00, 0x0c, 0x0 }},
{ 0x00, 0x7f, { 0x06c, 6375, 100, 0, 2, 0x00, 0xb0, 0x22, 0xf4, 0x23, 0x19, 0x0 }}
};
static const YRW801_REGION_DATA regions_05[] = {
/* Electric Piano 2 */
{ 0x14, 0x27, { 0x12c, 7476, 100, 0, 3, 0x00, 0xa2, 0x1b, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x12d, 6818, 100, 0, 3, 0x00, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12e, 5901, 100, 0, 3, 0x00, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12f, 5292, 100, 0, 3, 0x00, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x130, 4262, 100, 0, 3, 0x0a, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x131, 3627, 100, 0, 3, 0x0a, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x132, 3118, 100, 0, 3, 0x04, 0xa2, 0x1b, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x133, 2083, 100, 0, 3, 0x03, 0xa2, 0x1b, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x53, 0x58, { 0x134, 1446, 100, 0, 3, 0x07, 0xa2, 0x1b, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x59, 0x6d, { 0x135, 1917, 100, 0, 3, 0x00, 0xa2, 0x1b, 0xf4, 0x15, 0x08, 0x0 }},
{ 0x14, 0x2d, { 0x12c, 7472, 100, 0, 0, 0x00, 0xa2, 0x18, 0xf2, 0x13, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x12d, 6814, 100, 0, 0, 0x00, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x12e, 5897, 100, 0, 0, 0x00, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x12f, 5288, 100, 0, 0, 0x00, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x130, 4258, 100, 0, 0, 0x0a, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x131, 3623, 100, 0, 0, 0x0a, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x4c, 0x52, { 0x132, 3114, 100, 0, 0, 0x04, 0xa2, 0x18, 0xf2, 0x14, 0x08, 0x0 }},
{ 0x53, 0x58, { 0x133, 2079, 100, 0, 0, 0x07, 0xa2, 0x18, 0xf2, 0x14, 0x18, 0x0 }},
{ 0x59, 0x5e, { 0x134, 1442, 100, 0, 0, 0x0a, 0xa2, 0x18, 0xf3, 0x14, 0x18, 0x0 }},
{ 0x5f, 0x6d, { 0x135, 1913, 100, 0, 0, 0x00, 0xa2, 0x18, 0xf4, 0x15, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_06[] = {
/* Harpsichord */
{ 0x15, 0x39, { 0x080, 5158, 100, 0, 0, 0x00, 0xb2, 0x20, 0xf5, 0x24, 0x19, 0x0 }},
{ 0x3a, 0x3f, { 0x081, 4408, 100, 0, 0, 0x00, 0xb2, 0x20, 0xf5, 0x25, 0x09, 0x0 }},
{ 0x40, 0x45, { 0x082, 3622, 100, 0, 0, 0x00, 0xb2, 0x20, 0xf5, 0x25, 0x09, 0x0 }},
{ 0x46, 0x4d, { 0x083, 2843, 100, 0, 0, 0x00, 0xb2, 0x20, 0xf5, 0x25, 0x19, 0x0 }},
{ 0x4e, 0x6c, { 0x084, 1307, 100, 0, 0, 0x00, 0xb2, 0x20, 0xf5, 0x25, 0x29, 0x0 }}
};
static const YRW801_REGION_DATA regions_07[] = {
/* Clavinet */
{ 0x15, 0x51, { 0x027, 5009, 100, 0, 0, 0x00, 0xd2, 0x28, 0xf5, 0x13, 0x2b, 0x0 }},
{ 0x52, 0x6c, { 0x028, 3495, 100, 0, 0, 0x00, 0xd2, 0x28, 0xf5, 0x13, 0x3b, 0x0 }}
};
static const YRW801_REGION_DATA regions_08[] = {
/* Celesta */
{ 0x15, 0x6c, { 0x02b, 3267, 100, 0, 0, 0x00, 0xdc, 0x20, 0xf4, 0x15, 0x07, 0x3 }}
};
static const YRW801_REGION_DATA regions_09[] = {
/* Glockenspiel */
{ 0x15, 0x78, { 0x0f3, 285, 100, 0, 0, 0x00, 0xc2, 0x28, 0xf6, 0x25, 0x25, 0x0 }}
};
static const YRW801_REGION_DATA regions_0a[] = {
/* Music Box */
{ 0x15, 0x6c, { 0x0f3, 3362, 100, 0, 0, 0x00, 0xb6, 0x20, 0xa6, 0x25, 0x25, 0x0 }},
{ 0x15, 0x6c, { 0x101, 4773, 100, 0, 0, 0x00, 0xaa, 0x20, 0xd4, 0x14, 0x16, 0x0 }}
};
static const YRW801_REGION_DATA regions_0b[] = {
/* Vibraphone */
{ 0x15, 0x6c, { 0x101, 4778, 100, 0, 0, 0x00, 0xc0, 0x28, 0xf4, 0x14, 0x16, 0x4 }}
};
static const YRW801_REGION_DATA regions_0c[] = {
/* Marimba */
{ 0x15, 0x3f, { 0x0f4, 4778, 100, 0, 0, 0x00, 0xc4, 0x38, 0xf7, 0x47, 0x08, 0x0 }},
{ 0x40, 0x4c, { 0x0f5, 3217, 100, 0, 0, 0x00, 0xc4, 0x38, 0xf7, 0x47, 0x08, 0x0 }},
{ 0x4d, 0x5a, { 0x0f5, 3217, 100, 0, 0, 0x00, 0xc4, 0x38, 0xf7, 0x48, 0x08, 0x0 }},
{ 0x5b, 0x7f, { 0x0f5, 3218, 100, 0, 0, 0x00, 0xc4, 0x38, 0xf7, 0x48, 0x18, 0x0 }}
};
static const YRW801_REGION_DATA regions_0d[] = {
/* Xylophone */
{ 0x00, 0x7f, { 0x136, 1729, 100, 0, 0, 0x00, 0xd2, 0x38, 0xf0, 0x06, 0x36, 0x0 }}
};
static const YRW801_REGION_DATA regions_0e[] = {
/* Tubular Bell */
{ 0x01, 0x7f, { 0x0ff, 3999, 100, 0, 1, 0x00, 0x90, 0x21, 0xf4, 0xa3, 0x25, 0x1 }}
};
static const YRW801_REGION_DATA regions_0f[] = {
/* Dulcimer */
{ 0x00, 0x7f, { 0x03f, 4236, 100, 0, 1, 0x00, 0xbc, 0x29, 0xf5, 0x16, 0x07, 0x0 }},
{ 0x00, 0x7f, { 0x040, 4236, 100, 0, 2, 0x0e, 0x94, 0x2a, 0xf5, 0x16, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_10[] = {
/* Drawbar Organ */
{ 0x01, 0x7f, { 0x08e, 4394, 100, 0, 2, 0x14, 0xc2, 0x3a, 0xf0, 0x00, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_11[] = {
/* Percussive Organ */
{ 0x15, 0x3b, { 0x08c, 6062, 100, 0, 3, 0x00, 0xbe, 0x3b, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x3c, 0x6c, { 0x08d, 2984, 100, 0, 3, 0x00, 0xbe, 0x3b, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_12[] = {
/* Rock Organ */
{ 0x15, 0x30, { 0x128, 6574, 100, 0, 1, 0x00, 0xcc, 0x39, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x31, 0x3c, { 0x129, 5040, 100, 0, 1, 0x00, 0xcc, 0x39, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x3d, 0x48, { 0x12a, 3498, 100, 0, 1, 0x00, 0xcc, 0x39, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x49, 0x54, { 0x12b, 1957, 100, 0, 1, 0x00, 0xcc, 0x39, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x55, 0x6c, { 0x127, 423, 100, 0, 1, 0x00, 0xcc, 0x39, 0xf0, 0x00, 0x0a, 0x0 } }
};
static const YRW801_REGION_DATA regions_13[] = {
/* Church Organ */
{ 0x15, 0x29, { 0x087, 7466, 100, 0, 1, 0x00, 0xc4, 0x11, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x2a, 0x30, { 0x088, 6456, 100, 0, 1, 0x00, 0xc4, 0x11, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x31, 0x38, { 0x089, 5428, 100, 0, 1, 0x00, 0xc4, 0x11, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x39, 0x41, { 0x08a, 4408, 100, 0, 1, 0x00, 0xc4, 0x11, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x42, 0x6c, { 0x08b, 3406, 100, 0, 1, 0x00, 0xc4, 0x11, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_14[] = {
/* Reed Organ */
{ 0x00, 0x53, { 0x0ac, 5570, 100, 0, 0, 0x06, 0xc0, 0x38, 0xf0, 0x00, 0x09, 0x1 }},
{ 0x54, 0x7f, { 0x0ad, 2497, 100, 0, 0, 0x00, 0xc0, 0x38, 0xf0, 0x00, 0x09, 0x1 }}
};
static const YRW801_REGION_DATA regions_15[] = {
/* Accordion */
{ 0x15, 0x4c, { 0x006, 4261, 100, 0, 2, 0x00, 0xa4, 0x22, 0x90, 0x00, 0x09, 0x0 }},
{ 0x4d, 0x6c, { 0x007, 1530, 100, 0, 2, 0x00, 0xa4, 0x22, 0x90, 0x00, 0x09, 0x0 }},
{ 0x15, 0x6c, { 0x070, 4391, 100, 0, 3, 0x00, 0x8a, 0x23, 0xa0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_16[] = {
/* Harmonica */
{ 0x15, 0x6c, { 0x070, 4408, 100, 0, 0, 0x00, 0xae, 0x30, 0xa0, 0x00, 0x09, 0x2 }}
};
static const YRW801_REGION_DATA regions_17[] = {
/* Tango Accordion */
{ 0x00, 0x53, { 0x0ac, 5573, 100, 0, 0, 0x00, 0xae, 0x38, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x54, 0x7f, { 0x0ad, 2500, 100, 0, 0, 0x00, 0xae, 0x38, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x15, 0x6c, { 0x041, 8479, 100, 0, 2, 0x00, 0x6a, 0x3a, 0x75, 0x20, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_18[] = {
/* Nylon Guitar */
{ 0x15, 0x2f, { 0x0b3, 6964, 100, 0, 0, 0x05, 0xca, 0x28, 0xf5, 0x34, 0x09, 0x0 }},
{ 0x30, 0x36, { 0x0b7, 5567, 100, 0, 0, 0x0c, 0xca, 0x28, 0xf5, 0x34, 0x09, 0x0 }},
{ 0x37, 0x3c, { 0x0b5, 4653, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x34, 0x09, 0x0 }},
{ 0x3d, 0x43, { 0x0b4, 3892, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x35, 0x09, 0x0 }},
{ 0x44, 0x60, { 0x0b6, 2723, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x35, 0x19, 0x0 }}
};
static const YRW801_REGION_DATA regions_19[] = {
/* Steel Guitar */
{ 0x15, 0x31, { 0x00c, 6937, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x04, 0x19, 0x0 }},
{ 0x32, 0x38, { 0x00d, 5410, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x05, 0x09, 0x0 }},
{ 0x39, 0x47, { 0x00e, 4379, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf5, 0x94, 0x09, 0x0 }},
{ 0x48, 0x6c, { 0x00f, 2843, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf6, 0x95, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_1a[] = {
/* Jazz Guitar */
{ 0x15, 0x31, { 0x05a, 6832, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x34, 0x09, 0x0 }},
{ 0x32, 0x3f, { 0x05b, 4897, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x34, 0x09, 0x0 }},
{ 0x40, 0x6c, { 0x05c, 3218, 100, 0, 0, 0x00, 0xca, 0x28, 0xf6, 0x34, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_1b[] = {
/* Clean Guitar */
{ 0x15, 0x2c, { 0x061, 7053, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x54, 0x0a, 0x0 }},
{ 0x2d, 0x31, { 0x060, 6434, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x54, 0x0a, 0x0 }},
{ 0x32, 0x38, { 0x063, 5764, 100, 0, 1, 0x00, 0xbe, 0x29, 0xf5, 0x55, 0x0a, 0x0 }},
{ 0x39, 0x3f, { 0x062, 4627, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x55, 0x0a, 0x0 }},
{ 0x40, 0x44, { 0x065, 3963, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x55, 0x1a, 0x0 }},
{ 0x45, 0x4b, { 0x064, 3313, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x55, 0x1a, 0x0 }},
{ 0x4c, 0x54, { 0x066, 2462, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf5, 0x55, 0x2a, 0x0 }},
{ 0x55, 0x6c, { 0x067, 1307, 100, 0, 1, 0x00, 0xb4, 0x29, 0xf6, 0x56, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_1c[] = {
/* Muted Guitar */
{ 0x01, 0x7f, { 0x068, 4408, 100, 0, 0, 0x00, 0xcc, 0x28, 0xf6, 0x15, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_1d[] = {
/* Overdriven Guitar */
{ 0x00, 0x40, { 0x0a5, 6589, 100, 0, 1, 0x00, 0xc0, 0x29, 0xf2, 0x11, 0x09, 0x0 }},
{ 0x41, 0x7f, { 0x0a6, 5428, 100, 0, 1, 0x00, 0xc0, 0x29, 0xf2, 0x11, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_1e[] = {
/* Distortion Guitar */
{ 0x15, 0x2a, { 0x051, 6928, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x2b, 0x2e, { 0x052, 6433, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x2f, 0x32, { 0x053, 5944, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x33, 0x36, { 0x054, 5391, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x37, 0x3a, { 0x055, 4897, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x3b, 0x3e, { 0x056, 4408, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x3f, 0x42, { 0x057, 3892, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x43, 0x46, { 0x058, 3361, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }},
{ 0x47, 0x6c, { 0x059, 2784, 100, 0, 1, 0x00, 0xbc, 0x21, 0xa2, 0x12, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_1f[] = {
/* Guitar Harmonics */
{ 0x15, 0x44, { 0x05e, 5499, 100, 0, 0, 0x00, 0xce, 0x28, 0xf4, 0x24, 0x09, 0x0 }},
{ 0x45, 0x49, { 0x05d, 4850, 100, 0, 0, 0x00, 0xe2, 0x28, 0xf4, 0x24, 0x09, 0x0 }},
{ 0x4a, 0x6c, { 0x05f, 4259, 100, 0, 0, 0x00, 0xce, 0x28, 0xf4, 0x24, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_20[] = {
/* Acoustic Bass */
{ 0x15, 0x30, { 0x004, 8053, 100, 0, 0, 0x00, 0xe2, 0x18, 0xf5, 0x15, 0x09, 0x0 }},
{ 0x31, 0x6c, { 0x005, 4754, 100, 0, 0, 0x00, 0xe2, 0x18, 0xf5, 0x15, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_21[] = {
/* Fingered Bass */
{ 0x01, 0x20, { 0x04a, 8762, 100, 0, 0, 0x00, 0xde, 0x18, 0xf6, 0x14, 0x09, 0x0 }},
{ 0x21, 0x25, { 0x04b, 8114, 100, 0, 0, 0x00, 0xde, 0x18, 0xf6, 0x14, 0x09, 0x0 }},
{ 0x26, 0x2a, { 0x04c, 7475, 100, 0, 0, 0x00, 0xde, 0x18, 0xf6, 0x14, 0x09, 0x0 }},
{ 0x2b, 0x7f, { 0x04d, 6841, 100, 0, 0, 0x00, 0xde, 0x18, 0xf6, 0x14, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_22[] = {
/* Picked Bass */
{ 0x15, 0x23, { 0x04f, 7954, 100, 0, 0, 0x00, 0xcc, 0x18, 0xf3, 0x90, 0x0a, 0x0 }},
{ 0x24, 0x2a, { 0x050, 7318, 100, 0, 0, 0x05, 0xcc, 0x18, 0xf3, 0x90, 0x1a, 0x0 }},
{ 0x2b, 0x2f, { 0x06b, 6654, 100, 0, 0, 0x00, 0xcc, 0x18, 0xf3, 0x90, 0x2a, 0x0 }},
{ 0x30, 0x47, { 0x069, 6031, 100, 0, 0, 0x00, 0xcc, 0x18, 0xf5, 0xb0, 0x0a, 0x0 }},
{ 0x48, 0x6c, { 0x06a, 5393, 100, 0, 0, 0x00, 0xcc, 0x18, 0xf5, 0xb0, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_23[] = {
/* Fretless Bass */
{ 0x01, 0x7f, { 0x04e, 5297, 100, 0, 0, 0x00, 0xd2, 0x10, 0xf3, 0x63, 0x19, 0x0 }}
};
static const YRW801_REGION_DATA regions_24[] = {
/* Slap Bass 1 */
{ 0x15, 0x6c, { 0x0a3, 7606, 100, 0, 1, 0x00, 0xde, 0x19, 0xf5, 0x32, 0x1a, 0x0 }}
};
static const YRW801_REGION_DATA regions_25[] = {
/* Slap Bass 2 */
{ 0x01, 0x7f, { 0x0a2, 6694, 100, 0, 0, 0x00, 0xda, 0x20, 0xb0, 0x02, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_26[] = {
/* Synth Bass 1 */
{ 0x15, 0x6c, { 0x0be, 7466, 100, 0, 1, 0x00, 0xb8, 0x39, 0xf4, 0x14, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_27[] = {
/* Synth Bass 2 */
{ 0x00, 0x7f, { 0x117, 8103, 100, 0, 1, 0x00, 0xca, 0x39, 0xf3, 0x50, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_28[] = {
/* Violin */
{ 0x15, 0x3a, { 0x105, 5158, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x3b, 0x3f, { 0x102, 4754, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x40, 0x41, { 0x106, 4132, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x42, 0x44, { 0x107, 4033, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x45, 0x47, { 0x108, 3580, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x48, 0x4a, { 0x10a, 2957, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4b, 0x4c, { 0x10b, 2724, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4d, 0x4e, { 0x10c, 2530, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4f, 0x51, { 0x10d, 2166, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x52, 0x6c, { 0x109, 1825, 100, 0, 3, 0x00, 0xcc, 0x3b, 0xf3, 0x20, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_29[] = {
/* Viola */
{ 0x15, 0x32, { 0x103, 5780, 100, 0, 3, 0x00, 0xc4, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x33, 0x35, { 0x104, 5534, 100, 0, 3, 0x00, 0xc4, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x36, 0x38, { 0x105, 5158, 100, 0, 3, 0x00, 0xc4, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x39, 0x3d, { 0x102, 4754, 100, 0, 3, 0x00, 0xca, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x3e, 0x3f, { 0x106, 4132, 100, 0, 3, 0x00, 0xc4, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x40, 0x42, { 0x107, 4033, 100, 0, 3, 0x00, 0xc4, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x43, 0x45, { 0x108, 3580, 100, 0, 3, 0x00, 0xd0, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x46, 0x48, { 0x10a, 2957, 100, 0, 3, 0x00, 0xca, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x49, 0x4a, { 0x10b, 2724, 100, 0, 3, 0x00, 0xd0, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x4b, 0x4c, { 0x10c, 2530, 100, 0, 3, 0x00, 0xca, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x4d, 0x4f, { 0x10d, 2166, 100, 0, 3, 0x00, 0xd0, 0x3b, 0xa3, 0x20, 0x09, 0x0 }},
{ 0x50, 0x6c, { 0x109, 1825, 100, 0, 3, 0x00, 0xd0, 0x3b, 0xa3, 0x20, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_2a[] = {
/* Cello */
{ 0x15, 0x2d, { 0x112, 6545, 100, 0, 3, 0x00, 0xc0, 0x33, 0xa0, 0x00, 0x08, 0x0 }},
{ 0x2e, 0x37, { 0x113, 5764, 100, 0, 3, 0x00, 0xc0, 0x33, 0xa0, 0x00, 0x08, 0x0 }},
{ 0x38, 0x3e, { 0x115, 4378, 100, 0, 3, 0x00, 0xc0, 0x33, 0xa0, 0x00, 0x18, 0x0 }},
{ 0x3f, 0x44, { 0x116, 3998, 100, 0, 3, 0x00, 0xc0, 0x33, 0xa0, 0x00, 0x18, 0x0 }},
{ 0x45, 0x6c, { 0x114, 3218, 100, 0, 3, 0x00, 0xc0, 0x33, 0xa0, 0x00, 0x18, 0x0 }}
};
static const YRW801_REGION_DATA regions_2b[] = {
/* Contrabass */
{ 0x15, 0x29, { 0x110, 7713, 100, 0, 1, 0x00, 0xc2, 0x19, 0x90, 0x00, 0x09, 0x0 }},
{ 0x2a, 0x6c, { 0x111, 6162, 100, 0, 1, 0x00, 0xc2, 0x19, 0x90, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_2c[] = {
/* Tremolo Strings */
{ 0x15, 0x3b, { 0x0b0, 4810, 100, 0, 0, 0x0a, 0xde, 0x38, 0xf0, 0x00, 0x07, 0x6 }},
{ 0x3c, 0x41, { 0x035, 4035, 100, 0, 0, 0x05, 0xde, 0x38, 0xf0, 0x00, 0x07, 0x6 }},
{ 0x42, 0x47, { 0x033, 3129, 100, 0, 0, 0x05, 0xde, 0x38, 0xf0, 0x00, 0x07, 0x6 }},
{ 0x48, 0x52, { 0x034, 2625, 100, 0, 0, 0x05, 0xde, 0x38, 0xf0, 0x00, 0x07, 0x6 }},
{ 0x53, 0x6c, { 0x0af, 936, 100, 0, 0, 0x00, 0xde, 0x38, 0xf0, 0x00, 0x07, 0x6 } }
};
static const YRW801_REGION_DATA regions_2d[] = {
/* Pizzicato Strings */
{ 0x15, 0x32, { 0x0b8, 6186, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x00, 0x05, 0x0 }},
{ 0x33, 0x3b, { 0x0b9, 5031, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x00, 0x05, 0x0 }},
{ 0x3c, 0x42, { 0x0bb, 4146, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x00, 0x05, 0x0 }},
{ 0x43, 0x48, { 0x0ba, 3245, 100, 0, 0, 0x00, 0xc2, 0x28, 0xf0, 0x00, 0x05, 0x0 }},
{ 0x49, 0x6c, { 0x0bc, 2352, 100, 0, 0, 0x00, 0xbc, 0x28, 0xf0, 0x00, 0x05, 0x0 }}
};
static const YRW801_REGION_DATA regions_2e[] = {
/* Harp */
{ 0x15, 0x46, { 0x07e, 3740, 100, 0, 1, 0x00, 0xd2, 0x29, 0xf5, 0x25, 0x07, 0x0 }},
{ 0x47, 0x6c, { 0x07f, 2319, 100, 0, 1, 0x00, 0xd2, 0x29, 0xf5, 0x25, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_2f[] = {
/* Timpani */
{ 0x15, 0x6c, { 0x100, 6570, 100, 0, 0, 0x00, 0xf8, 0x28, 0xf0, 0x05, 0x16, 0x0 }}
};
static const YRW801_REGION_DATA regions_30[] = {
/* Strings */
{ 0x15, 0x3b, { 0x13c, 4806, 100, 0, 0, 0x00, 0xc8, 0x20, 0x80, 0x00, 0x07, 0x0 }},
{ 0x3c, 0x41, { 0x13e, 4035, 100, 0, 0, 0x00, 0xc8, 0x20, 0x80, 0x00, 0x07, 0x0 }},
{ 0x42, 0x47, { 0x13d, 3122, 100, 0, 0, 0x00, 0xc8, 0x20, 0x80, 0x00, 0x07, 0x0 }},
{ 0x48, 0x52, { 0x13f, 2629, 100, 0, 0, 0x00, 0xbe, 0x20, 0x80, 0x00, 0x07, 0x0 }},
{ 0x53, 0x6c, { 0x140, 950, 100, 0, 0, 0x00, 0xbe, 0x20, 0x80, 0x00, 0x07, 0x0 } }
};
static const YRW801_REGION_DATA regions_31[] = {
/* Slow Strings */
{ 0x15, 0x3b, { 0x0b0, 4810, 100, 0, 1, 0x0a, 0xbe, 0x19, 0xf0, 0x00, 0x07, 0x0 }},
{ 0x3c, 0x41, { 0x035, 4035, 100, 0, 1, 0x05, 0xbe, 0x19, 0xf0, 0x00, 0x07, 0x0 }},
{ 0x42, 0x47, { 0x033, 3129, 100, 0, 1, 0x05, 0xbe, 0x19, 0xf0, 0x00, 0x07, 0x0 }},
{ 0x48, 0x52, { 0x034, 2625, 100, 0, 1, 0x05, 0xbe, 0x19, 0xf0, 0x00, 0x07, 0x0 }},
{ 0x53, 0x6c, { 0x0af, 936, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf0, 0x00, 0x07, 0x0 } }
};
static const YRW801_REGION_DATA regions_32[] = {
/* Synth Strings 1 */
{ 0x05, 0x71, { 0x002, 6045, 100, -2, 0, 0x00, 0xa6, 0x20, 0x93, 0x22, 0x06, 0x0 }},
{ 0x15, 0x6c, { 0x0ae, 3261, 100, 2, 0, 0x00, 0xc6, 0x20, 0x70, 0x01, 0x06, 0x0 } }
};
static const YRW801_REGION_DATA regions_33[] = {
/* Synth Strings 2 */
{ 0x15, 0x6c, { 0x002, 4513, 100, 5, 1, 0x00, 0xb4, 0x19, 0x70, 0x00, 0x06, 0x0 } },
{ 0x15, 0x6c, { 0x002, 4501, 100, -5, 1, 0x00, 0xb4, 0x19, 0x70, 0x00, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_34[] = {
/* Choir Aahs */
{ 0x15, 0x3a, { 0x018, 5010, 100, 0, 2, 0x00, 0xc2, 0x1a, 0x70, 0x00, 0x08, 0x0 }},
{ 0x3b, 0x40, { 0x019, 4370, 100, 0, 2, 0x00, 0xc2, 0x1a, 0x70, 0x00, 0x08, 0x0 }},
{ 0x41, 0x47, { 0x01a, 3478, 100, 0, 2, 0x00, 0xc2, 0x1a, 0x70, 0x00, 0x08, 0x0 }},
{ 0x48, 0x6c, { 0x01b, 2197, 100, 0, 2, 0x00, 0xc2, 0x1a, 0x70, 0x00, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_35[] = {
/* Voice Oohs */
{ 0x15, 0x6c, { 0x029, 3596, 100, 0, 0, 0x00, 0xe6, 0x20, 0xf7, 0x20, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_36[] = {
/* Synth Voice */
{ 0x15, 0x6c, { 0x02a, 3482, 100, 0, 1, 0x00, 0xc2, 0x19, 0x85, 0x21, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_37[] = {
/* Orchestra Hit */
{ 0x15, 0x6c, { 0x049, 4394, 100, 0, 0, 0x00, 0xfe, 0x30, 0x80, 0x05, 0x05, 0x0 }}
};
static const YRW801_REGION_DATA regions_38[] = {
/* Trumpet */
{ 0x15, 0x3c, { 0x0f6, 4706, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x3d, 0x43, { 0x0f8, 3894, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x44, 0x48, { 0x0f7, 3118, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x49, 0x4e, { 0x0fa, 2322, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x4f, 0x55, { 0x0f9, 1634, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x56, 0x6c, { 0x0fb, 786, 100, 0, 2, 0x00, 0xd6, 0x32, 0xf3, 0x20, 0x0a, 0x0 } }
};
static const YRW801_REGION_DATA regions_39[] = {
/* Trombone */
{ 0x15, 0x3a, { 0x0f0, 5053, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x3b, 0x3f, { 0x0f1, 4290, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x40, 0x6c, { 0x0f2, 3580, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_3a[] = {
/* Tuba */
{ 0x15, 0x2d, { 0x085, 7096, 100, 0, 1, 0x00, 0xde, 0x21, 0xf5, 0x10, 0x09, 0x0 }},
{ 0x2e, 0x6c, { 0x086, 6014, 100, 0, 1, 0x00, 0xde, 0x21, 0xf5, 0x10, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_3b[] = {
/* Muted Trumpet */
{ 0x15, 0x45, { 0x0b1, 4135, 100, 0, 0, 0x00, 0xcc, 0x28, 0xf3, 0x10, 0x0a, 0x1 }},
{ 0x46, 0x6c, { 0x0b2, 2599, 100, 0, 0, 0x00, 0xcc, 0x28, 0x83, 0x10, 0x0a, 0x1 }}
};
static const YRW801_REGION_DATA regions_3c[] = {
/* French Horns */
{ 0x15, 0x49, { 0x07c, 3624, 100, 0, 2, 0x00, 0xd0, 0x1a, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x4a, 0x6c, { 0x07d, 2664, 100, 0, 2, 0x00, 0xd0, 0x1a, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_3d[] = {
/* Brass Section */
{ 0x15, 0x42, { 0x0fc, 4375, 100, 0, 0, 0x00, 0xd6, 0x28, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x43, 0x6c, { 0x0fd, 2854, 100, 0, 0, 0x00, 0xd6, 0x28, 0xf0, 0x00, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_3e[] = {
/* Synth Brass 1 */
{ 0x01, 0x27, { 0x0d3, 9094, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x0da, 8335, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x0d4, 7558, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x0db, 6785, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x0d5, 6042, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x0dc, 5257, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x0d6, 4493, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x4c, 0x51, { 0x0dd, 3741, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x52, 0x57, { 0x0d7, 3012, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x58, 0x5d, { 0x0de, 2167, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x5e, 0x63, { 0x0d8, 1421, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x64, 0x7f, { 0x0d9, -115, 100, -1, 0, 0x00, 0xbe, 0x18, 0xa5, 0x11, 0x08, 0x0 }},
{ 0x01, 0x27, { 0x118, 9103, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x28, 0x2d, { 0x119, 8340, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x2e, 0x33, { 0x11a, 7565, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x34, 0x39, { 0x11b, 6804, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x3a, 0x3f, { 0x11c, 6042, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x40, 0x45, { 0x11d, 5277, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x46, 0x4b, { 0x11e, 4520, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x4c, 0x51, { 0x11f, 3741, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x52, 0x57, { 0x120, 3012, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x58, 0x5d, { 0x121, 2166, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x5e, 0x64, { 0x122, 1421, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } },
{ 0x65, 0x7f, { 0x123, -115, 100, 1, 1, 0x00, 0xbe, 0x19, 0x85, 0x23, 0x08, 0x0 } }
};
static const YRW801_REGION_DATA regions_3f[] = {
/* Synth Brass 2 */
{ 0x01, 0x27, { 0x118, 9113, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x28, 0x2d, { 0x119, 8350, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x2e, 0x33, { 0x11a, 7575, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x34, 0x39, { 0x11b, 6814, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x3a, 0x3f, { 0x11c, 6052, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x40, 0x45, { 0x11d, 5287, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x46, 0x4b, { 0x11e, 4530, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x4c, 0x51, { 0x11f, 3751, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x52, 0x57, { 0x120, 3022, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x58, 0x5d, { 0x121, 2176, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x5e, 0x64, { 0x122, 1431, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x65, 0x7f, { 0x123, -105, 100, 3, 6, 0x00, 0xae, 0x26, 0x85, 0x23, 0x08, 0x0 } },
{ 0x00, 0x7f, { 0x124, 4034, 100, -3, 2, 0x00, 0xea, 0x22, 0x85, 0x23, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_40[] = {
/* Soprano Sax */
{ 0x15, 0x3f, { 0x0e3, 4228, 100, 0, 1, 0x00, 0xc8, 0x21, 0xf5, 0x20, 0x0a, 0x0 }},
{ 0x40, 0x45, { 0x0e4, 3495, 100, 0, 1, 0x00, 0xc8, 0x21, 0xf5, 0x20, 0x0a, 0x0 }},
{ 0x46, 0x4b, { 0x0e5, 2660, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf5, 0x20, 0x0a, 0x0 }},
{ 0x4c, 0x51, { 0x0e6, 2002, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf5, 0x20, 0x0a, 0x0 }},
{ 0x52, 0x59, { 0x0e7, 1186, 100, 0, 1, 0x00, 0xd6, 0x21, 0xf5, 0x20, 0x0a, 0x0 }},
{ 0x59, 0x6c, { 0x0e8, 1730, 100, 0, 1, 0x00, 0xc8, 0x21, 0xf5, 0x20, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_41[] = {
/* Alto Sax */
{ 0x15, 0x32, { 0x092, 6204, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x33, 0x35, { 0x096, 5812, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x36, 0x3a, { 0x099, 5318, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x3b, 0x3b, { 0x08f, 5076, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x3c, 0x3e, { 0x093, 4706, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x3f, 0x41, { 0x097, 4321, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x42, 0x44, { 0x09a, 3893, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x45, 0x47, { 0x090, 3497, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x48, 0x4a, { 0x094, 3119, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x4b, 0x4d, { 0x098, 2726, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x4e, 0x50, { 0x09b, 2393, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x51, 0x53, { 0x091, 2088, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }},
{ 0x54, 0x6c, { 0x095, 1732, 100, 0, 1, 0x00, 0xbe, 0x19, 0xf5, 0x20, 0x0b, 0x0 }}
};
static const YRW801_REGION_DATA regions_42[] = {
/* Tenor Sax */
{ 0x24, 0x30, { 0x0e9, 6301, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x31, 0x34, { 0x0ea, 5781, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x35, 0x3a, { 0x0eb, 5053, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x3b, 0x41, { 0x0ed, 4165, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x42, 0x47, { 0x0ec, 3218, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x48, 0x51, { 0x0ee, 2462, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }},
{ 0x52, 0x6c, { 0x0ef, 1421, 100, 0, 1, 0x00, 0xbc, 0x19, 0xf4, 0x10, 0x0b, 0x0 }}
};
static const YRW801_REGION_DATA regions_43[] = {
/* Baritone Sax */
{ 0x15, 0x2d, { 0x0df, 6714, 100, 0, 1, 0x00, 0xce, 0x19, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x2e, 0x34, { 0x0e1, 5552, 100, 0, 1, 0x00, 0xce, 0x19, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x35, 0x39, { 0x0e2, 5178, 100, 0, 1, 0x00, 0xce, 0x19, 0xf0, 0x00, 0x0a, 0x0 }},
{ 0x3a, 0x6c, { 0x0e0, 4437, 100, 0, 1, 0x00, 0xce, 0x19, 0xf0, 0x00, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_44[] = {
/* Oboe */
{ 0x15, 0x3c, { 0x042, 4493, 100, 0, 1, 0x00, 0xe6, 0x39, 0xf4, 0x10, 0x0a, 0x0 }},
{ 0x3d, 0x43, { 0x044, 3702, 100, 0, 1, 0x00, 0xdc, 0x39, 0xf4, 0x10, 0x0a, 0x0 }},
{ 0x44, 0x49, { 0x043, 2956, 100, 0, 1, 0x00, 0xdc, 0x39, 0xf4, 0x10, 0x0a, 0x0 }},
{ 0x4a, 0x4f, { 0x046, 2166, 100, 0, 1, 0x00, 0xdc, 0x39, 0xf4, 0x10, 0x0a, 0x0 }},
{ 0x50, 0x55, { 0x045, 1420, 100, 0, 1, 0x00, 0xdc, 0x39, 0xf4, 0x10, 0x0a, 0x0 }},
{ 0x56, 0x6c, { 0x047, 630, 100, 0, 1, 0x00, 0xe6, 0x39, 0xf4, 0x10, 0x0a, 0x0 } }
};
static const YRW801_REGION_DATA regions_45[] = {
/* English Horn */
{ 0x15, 0x38, { 0x03c, 5098, 100, 0, 1, 0x00, 0xc4, 0x31, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x39, 0x3e, { 0x03b, 4291, 100, 0, 1, 0x00, 0xc4, 0x31, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x3f, 0x6c, { 0x03d, 3540, 100, 0, 1, 0x00, 0xc4, 0x31, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_46[] = {
/* Bassoon */
{ 0x15, 0x22, { 0x038, 7833, 100, 0, 1, 0x00, 0xc6, 0x31, 0xf0, 0x00, 0x0b, 0x0 }},
{ 0x23, 0x2e, { 0x03a, 7070, 100, 0, 1, 0x00, 0xc6, 0x31, 0xf0, 0x00, 0x0b, 0x0 }},
{ 0x2f, 0x6c, { 0x039, 6302, 100, 0, 1, 0x00, 0xc6, 0x31, 0xf0, 0x00, 0x0b, 0x0 }}
};
static const YRW801_REGION_DATA regions_47[] = {
/* Clarinet */
{ 0x15, 0x3b, { 0x09e, 5900, 100, 0, 1, 0x00, 0xc8, 0x29, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x3c, 0x41, { 0x0a0, 5158, 100, 0, 1, 0x00, 0xc8, 0x29, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x42, 0x4a, { 0x09f, 4260, 100, 0, 1, 0x00, 0xc8, 0x29, 0xf3, 0x20, 0x0a, 0x0 }},
{ 0x4b, 0x6c, { 0x0a1, 2957, 100, 0, 1, 0x00, 0xc8, 0x29, 0xf3, 0x20, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_48[] = {
/* Piccolo */
{ 0x15, 0x40, { 0x071, 4803, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x41, 0x4d, { 0x072, 3314, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x4e, 0x53, { 0x073, 1731, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x54, 0x5f, { 0x074, 2085, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x60, 0x6c, { 0x075, 1421, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }}
};
static const YRW801_REGION_DATA regions_49[] = {
/* Flute */
{ 0x15, 0x40, { 0x071, 4803, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x41, 0x4d, { 0x072, 3314, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf0, 0x00, 0x0a, 0x2 }},
{ 0x4e, 0x6c, { 0x073, 1731, 100, 0, 0, 0x00, 0xe6, 0x38, 0xf0, 0x00, 0x0a, 0x2 }}
};
static const YRW801_REGION_DATA regions_4a[] = {
/* Recorder */
{ 0x15, 0x6f, { 0x0bd, 4897, 100, 0, 0, 0x00, 0xec, 0x30, 0x70, 0x00, 0x09, 0x1 }}
};
static const YRW801_REGION_DATA regions_4b[] = {
/* Pan Flute */
{ 0x15, 0x6c, { 0x077, 2359, 100, 0, 0, 0x00, 0xde, 0x38, 0xf0, 0x00, 0x09, 0x3 }}
};
static const YRW801_REGION_DATA regions_4c[] = {
/* Bottle Blow */
{ 0x15, 0x6c, { 0x077, 2359, 100, 0, 0, 0x00, 0xc8, 0x38, 0xf0, 0x00, 0x09, 0x1 }},
{ 0x01, 0x7f, { 0x125, 7372, 100, 0, 0, 0x1e, 0x80, 0x00, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_4d[] = {
/* Shakuhachi */
{ 0x00, 0x7f, { 0x0ab, 4548, 100, 0, 0, 0x00, 0xd6, 0x30, 0xf0, 0x00, 0x0a, 0x3 }},
{ 0x15, 0x6c, { 0x076, 3716, 100, 0, 0, 0x00, 0xa2, 0x28, 0x70, 0x00, 0x09, 0x2 }}
};
static const YRW801_REGION_DATA regions_4e[] = {
/* Whistle */
{ 0x00, 0x7f, { 0x0aa, 1731, 100, 0, 4, 0x00, 0xd2, 0x2c, 0x70, 0x00, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_4f[] = {
/* Ocarina */
{ 0x00, 0x7f, { 0x0aa, 1731, 100, 0, 1, 0x00, 0xce, 0x29, 0x90, 0x00, 0x0a, 0x1 }}
};
static const YRW801_REGION_DATA regions_50[] = {
/* Square Lead */
{ 0x01, 0x2a, { 0x0cc, 9853, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x2b, 0x36, { 0x0cd, 6785, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x37, 0x42, { 0x0ca, 5248, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x43, 0x4e, { 0x0cf, 3713, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x4f, 0x5a, { 0x0ce, 2176, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x5b, 0x7f, { 0x0cb, 640, 100, 3, 0, 0x00, 0xac, 0x38, 0xc6, 0x21, 0x09, 0x0 } },
{ 0x01, 0x2a, { 0x0cc, 9844, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 }},
{ 0x2b, 0x36, { 0x0cd, 6776, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 }},
{ 0x37, 0x42, { 0x0ca, 5239, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 }},
{ 0x43, 0x4e, { 0x0cf, 3704, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 }},
{ 0x4f, 0x5a, { 0x0ce, 2167, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 }},
{ 0x5b, 0x7f, { 0x0cb, 631, 100, -3, 0, 0x00, 0xac, 0x08, 0xc6, 0x21, 0x09, 0x0 } }
};
static const YRW801_REGION_DATA regions_51[] = {
/* Sawtooth Lead */
{ 0x01, 0x27, { 0x118, 9108, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x28, 0x2d, { 0x119, 8345, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x2e, 0x33, { 0x11a, 7570, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x34, 0x39, { 0x11b, 6809, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x3a, 0x3f, { 0x11c, 6047, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x40, 0x45, { 0x11d, 5282, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x46, 0x4b, { 0x11e, 4525, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x4c, 0x51, { 0x11f, 3746, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x52, 0x57, { 0x120, 3017, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x58, 0x5d, { 0x121, 2171, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x5e, 0x66, { 0x122, 1426, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x67, 0x7f, { 0x123, -110, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x01, 0x27, { 0x118, 9098, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x28, 0x2d, { 0x119, 8335, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x2e, 0x33, { 0x11a, 7560, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x34, 0x39, { 0x11b, 6799, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x3a, 0x3f, { 0x11c, 6037, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x40, 0x45, { 0x11d, 5272, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x46, 0x4b, { 0x11e, 4515, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x4c, 0x51, { 0x11f, 3736, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x52, 0x57, { 0x120, 3007, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x58, 0x5d, { 0x121, 2161, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x5e, 0x66, { 0x122, 1416, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }},
{ 0x67, 0x7f, { 0x123, -120, 100, 0, 0, 0x00, 0xc8, 0x30, 0xf2, 0x22, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_52[] = {
/* Calliope Lead */
{ 0x00, 0x7f, { 0x0aa, 1731, 100, 0, 0, 0x00, 0xc2, 0x28, 0x90, 0x00, 0x0a, 0x2 }},
{ 0x15, 0x6c, { 0x076, 3716, 100, 0, 0, 0x00, 0xb6, 0x28, 0xb0, 0x00, 0x09, 0x2 }}
};
static const YRW801_REGION_DATA regions_53[] = {
/* Chiffer Lead */
{ 0x00, 0x7f, { 0x13a, 3665, 100, 0, 2, 0x00, 0xcc, 0x2a, 0xf0, 0x10, 0x09, 0x1 }},
{ 0x01, 0x7f, { 0x0fe, 3660, 100, 0, 0, 0x00, 0xbe, 0x28, 0xf3, 0x10, 0x17, 0x0 }}
};
static const YRW801_REGION_DATA regions_54[] = {
/* Charang Lead */
{ 0x00, 0x40, { 0x0a5, 6594, 100, 0, 3, 0x00, 0xba, 0x33, 0xf2, 0x11, 0x09, 0x0 }},
{ 0x41, 0x7f, { 0x0a6, 5433, 100, 0, 3, 0x00, 0xba, 0x33, 0xf2, 0x11, 0x09, 0x0 }},
{ 0x01, 0x27, { 0x118, 9098, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x28, 0x2d, { 0x119, 8335, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x2e, 0x33, { 0x11a, 7560, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x34, 0x39, { 0x11b, 6799, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x3a, 0x3f, { 0x11c, 6037, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x40, 0x45, { 0x11d, 5272, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x46, 0x4b, { 0x11e, 4515, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x4c, 0x51, { 0x11f, 3736, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x52, 0x57, { 0x120, 3007, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x58, 0x5d, { 0x121, 2161, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x5e, 0x66, { 0x122, 1416, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }},
{ 0x67, 0x7f, { 0x123, -120, 100, 0, 2, 0x00, 0xa4, 0x2a, 0xf2, 0x22, 0x0e, 0x0 }}
};
static const YRW801_REGION_DATA regions_55[] = {
/* Voice Lead */
{ 0x00, 0x7f, { 0x0aa, 1739, 100, 0, 6, 0x00, 0x8c, 0x2e, 0x90, 0x00, 0x0a, 0x0 }},
{ 0x15, 0x6c, { 0x02a, 3474, 100, 0, 1, 0x00, 0xd8, 0x29, 0xf0, 0x05, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_56[] = {
/* 5ths Lead */
{ 0x01, 0x27, { 0x118, 8468, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x28, 0x2d, { 0x119, 7705, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x2e, 0x33, { 0x11a, 6930, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x34, 0x39, { 0x11b, 6169, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x3a, 0x3f, { 0x11c, 5407, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x40, 0x45, { 0x11d, 4642, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x46, 0x4b, { 0x11e, 3885, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x4c, 0x51, { 0x11f, 3106, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x52, 0x57, { 0x120, 2377, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x58, 0x5d, { 0x121, 1531, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x5e, 0x64, { 0x122, 786, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 } },
{ 0x65, 0x7f, { 0x123, -750, 100, 0, 2, 0x00, 0xd0, 0x32, 0xf5, 0x20, 0x08, 0x0 }},
{ 0x05, 0x71, { 0x002, 4503, 100, 0, 1, 0x00, 0xb8, 0x31, 0xb3, 0x20, 0x0b, 0x0 }}
};
static const YRW801_REGION_DATA regions_57[] = {
/* Bass & Lead */
{ 0x00, 0x7f, { 0x117, 8109, 100, 0, 1, 0x00, 0xbc, 0x29, 0xf3, 0x50, 0x08, 0x0 }},
{ 0x01, 0x27, { 0x118, 9097, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x28, 0x2d, { 0x119, 8334, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x2e, 0x33, { 0x11a, 7559, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x34, 0x39, { 0x11b, 6798, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x3a, 0x3f, { 0x11c, 6036, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x40, 0x45, { 0x11d, 5271, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x46, 0x4b, { 0x11e, 4514, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x4c, 0x51, { 0x11f, 3735, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x52, 0x57, { 0x120, 3006, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x58, 0x5d, { 0x121, 2160, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x5e, 0x66, { 0x122, 1415, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }},
{ 0x67, 0x7f, { 0x123, -121, 100, 0, 2, 0x00, 0xbc, 0x2a, 0xf2, 0x20, 0x0a, 0x0 }}
};
static const YRW801_REGION_DATA regions_58[] = {
/* New Age Pad */
{ 0x15, 0x6c, { 0x002, 4501, 100, 0, 4, 0x00, 0xa4, 0x24, 0x80, 0x01, 0x05, 0x0 }},
{ 0x15, 0x6c, { 0x0f3, 4253, 100, 0, 3, 0x00, 0x8c, 0x23, 0xa2, 0x14, 0x06, 0x1 }}
};
static const YRW801_REGION_DATA regions_59[] = {
/* Warm Pad */
{ 0x15, 0x6c, { 0x04e, 5306, 100, 2, 2, 0x00, 0x92, 0x2a, 0x34, 0x23, 0x05, 0x2 } },
{ 0x15, 0x6c, { 0x029, 3575, 100, -2, 2, 0x00, 0xbe, 0x22, 0x31, 0x23, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_5a[] = {
/* Polysynth Pad */
{ 0x01, 0x27, { 0x118, 9111, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x28, 0x2d, { 0x119, 8348, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x2e, 0x33, { 0x11a, 7573, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x34, 0x39, { 0x11b, 6812, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x3a, 0x3f, { 0x11c, 6050, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x40, 0x45, { 0x11d, 5285, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x46, 0x4b, { 0x11e, 4528, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x4c, 0x51, { 0x11f, 3749, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x52, 0x57, { 0x120, 3020, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x58, 0x5d, { 0x121, 2174, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x5e, 0x66, { 0x122, 1429, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x67, 0x7f, { 0x123, -107, 100, 0, 3, 0x00, 0xae, 0x23, 0xf2, 0x20, 0x07, 0x1 }},
{ 0x00, 0x7f, { 0x124, 4024, 100, 0, 2, 0x00, 0xae, 0x22, 0xe5, 0x20, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_5b[] = {
/* Choir Pad */
{ 0x15, 0x3a, { 0x018, 5010, 100, 0, 5, 0x00, 0xb0, 0x25, 0x70, 0x00, 0x06, 0x0 }},
{ 0x3b, 0x40, { 0x019, 4370, 100, 0, 5, 0x00, 0xb0, 0x25, 0x70, 0x00, 0x06, 0x0 }},
{ 0x41, 0x47, { 0x01a, 3478, 100, 0, 5, 0x00, 0xb0, 0x25, 0x70, 0x00, 0x06, 0x0 }},
{ 0x48, 0x6c, { 0x01b, 2197, 100, 0, 5, 0x00, 0xb0, 0x25, 0x70, 0x00, 0x06, 0x0 }},
{ 0x15, 0x6c, { 0x02a, 3482, 100, 0, 4, 0x00, 0x98, 0x24, 0x65, 0x21, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_5c[] = {
/* Bowed Pad */
{ 0x15, 0x6c, { 0x101, 4790, 100, -1, 1, 0x00, 0xbe, 0x19, 0x44, 0x14, 0x16, 0x0 }},
{ 0x00, 0x7f, { 0x0aa, 1720, 100, 1, 1, 0x00, 0x94, 0x19, 0x40, 0x00, 0x06, 0x0 } }
};
static const YRW801_REGION_DATA regions_5d[] = {
/* Metallic Pad */
{ 0x15, 0x31, { 0x00c, 6943, 100, 0, 2, 0x00, 0xa0, 0x0a, 0x60, 0x03, 0x06, 0x0 }},
{ 0x32, 0x38, { 0x00d, 5416, 100, 0, 2, 0x00, 0xa0, 0x0a, 0x60, 0x03, 0x06, 0x0 }},
{ 0x39, 0x47, { 0x00e, 4385, 100, 0, 2, 0x00, 0xa0, 0x0a, 0x60, 0x03, 0x06, 0x0 }},
{ 0x48, 0x6c, { 0x00f, 2849, 100, 0, 2, 0x00, 0xa0, 0x0a, 0x60, 0x03, 0x06, 0x0 }},
{ 0x00, 0x7f, { 0x03f, 4224, 100, 0, 1, 0x00, 0x9c, 0x31, 0x65, 0x16, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_5e[] = {
/* Halo Pad */
{ 0x00, 0x7f, { 0x124, 4038, 100, 0, 2, 0x00, 0xa6, 0x1a, 0x85, 0x23, 0x08, 0x0 }},
{ 0x15, 0x6c, { 0x02a, 3471, 100, 0, 3, 0x00, 0xc0, 0x1b, 0xc0, 0x05, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_5f[] = {
/* Sweep Pad */
{ 0x01, 0x27, { 0x0d3, 9100, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x28, 0x2d, { 0x0da, 8341, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x2e, 0x33, { 0x0d4, 7564, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x34, 0x39, { 0x0db, 6791, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x3a, 0x3f, { 0x0d5, 6048, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x40, 0x45, { 0x0dc, 5263, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x46, 0x4b, { 0x0d6, 4499, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x4c, 0x51, { 0x0dd, 3747, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x52, 0x57, { 0x0d7, 3018, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x58, 0x5d, { 0x0de, 2173, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x5e, 0x63, { 0x0d8, 1427, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x64, 0x7f, { 0x0d9, -109, 100, 0, 1, 0x00, 0xce, 0x19, 0x13, 0x11, 0x06, 0x0 }},
{ 0x01, 0x27, { 0x0d3, 9088, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x28, 0x2d, { 0x0da, 8329, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x2e, 0x33, { 0x0d4, 7552, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x34, 0x39, { 0x0db, 6779, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x3a, 0x3f, { 0x0d5, 6036, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x40, 0x45, { 0x0dc, 5251, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x46, 0x4b, { 0x0d6, 4487, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x4c, 0x51, { 0x0dd, 3735, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x52, 0x57, { 0x0d7, 3006, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x58, 0x5d, { 0x0de, 2161, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x5e, 0x63, { 0x0d8, 1415, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }},
{ 0x64, 0x7f, { 0x0d9, -121, 100, 0, 0, 0x00, 0xce, 0x18, 0x13, 0x11, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_60[] = {
/* Ice Rain */
{ 0x01, 0x7f, { 0x04e, 9345, 100, 0, 2, 0x00, 0xcc, 0x22, 0xa3, 0x63, 0x17, 0x0 }},
{ 0x00, 0x7f, { 0x143, 5586, 20, 0, 2, 0x00, 0x6e, 0x2a, 0xf0, 0x05, 0x05, 0x0 } }
};
static const YRW801_REGION_DATA regions_61[] = {
/* Soundtrack */
{ 0x15, 0x6c, { 0x002, 4501, 100, 0, 2, 0x00, 0xb6, 0x2a, 0x60, 0x01, 0x05, 0x0 }},
{ 0x15, 0x6c, { 0x0f3, 1160, 100, 0, 5, 0x00, 0xa8, 0x2d, 0x52, 0x14, 0x06, 0x2 }}
};
static const YRW801_REGION_DATA regions_62[] = {
/* Crystal */
{ 0x15, 0x6c, { 0x0f3, 1826, 100, 0, 3, 0x00, 0xb8, 0x33, 0xf6, 0x25, 0x25, 0x0 }},
{ 0x15, 0x2c, { 0x06d, 7454, 100, 0, 3, 0x00, 0xac, 0x3b, 0x85, 0x24, 0x06, 0x0 }},
{ 0x2d, 0x36, { 0x06e, 5925, 100, 0, 3, 0x00, 0xac, 0x3b, 0x85, 0x24, 0x06, 0x0 }},
{ 0x37, 0x6c, { 0x06f, 4403, 100, 0, 3, 0x09, 0xac, 0x3b, 0x85, 0x24, 0x06, 0x0 }}
};
static const YRW801_REGION_DATA regions_63[] = {
/* Atmosphere */
{ 0x05, 0x71, { 0x002, 4509, 100, 0, 2, 0x00, 0xc8, 0x32, 0x73, 0x22, 0x06, 0x1 }},
{ 0x15, 0x2f, { 0x0b3, 6964, 100, 0, 2, 0x05, 0xc2, 0x32, 0xf5, 0x34, 0x07, 0x2 }},
{ 0x30, 0x36, { 0x0b7, 5567, 100, 0, 2, 0x0c, 0xc2, 0x32, 0xf5, 0x34, 0x07, 0x2 }},
{ 0x37, 0x3c, { 0x0b5, 4653, 100, 0, 2, 0x00, 0xc2, 0x32, 0xf6, 0x34, 0x07, 0x2 }},
{ 0x3d, 0x43, { 0x0b4, 3892, 100, 0, 2, 0x00, 0xc2, 0x32, 0xf6, 0x35, 0x07, 0x2 }},
{ 0x44, 0x60, { 0x0b6, 2723, 100, 0, 2, 0x00, 0xc2, 0x32, 0xf6, 0x35, 0x17, 0x2 }}
};
static const YRW801_REGION_DATA regions_64[] = {
/* Brightness */
{ 0x00, 0x7f, { 0x137, 5285, 100, 0, 2, 0x00, 0xbe, 0x2a, 0xa5, 0x18, 0x08, 0x0 }},
{ 0x15, 0x6c, { 0x02a, 3481, 100, 0, 1, 0x00, 0xc8, 0x29, 0x80, 0x05, 0x05, 0x0 }}
};
static const YRW801_REGION_DATA regions_65[] = {
/* Goblins */
{ 0x15, 0x6c, { 0x002, 4501, 100, -1, 2, 0x00, 0xca, 0x2a, 0x40, 0x01, 0x05, 0x0 }},
{ 0x15, 0x6c, { 0x009, 9679, 20, 1, 4, 0x00, 0x3c, 0x0c, 0x22, 0x11, 0x06, 0x0 } }
};
static const YRW801_REGION_DATA regions_66[] = {
/* Echoes */
{ 0x15, 0x6c, { 0x02a, 3487, 100, 0, 3, 0x00, 0xae, 0x2b, 0xf5, 0x21, 0x06, 0x0 }},
{ 0x00, 0x7f, { 0x124, 4027, 100, 0, 3, 0x00, 0xae, 0x2b, 0x85, 0x23, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_67[] = {
/* Sci-Fi */
{ 0x15, 0x31, { 0x00c, 6940, 100, 0, 3, 0x00, 0xc8, 0x2b, 0x90, 0x05, 0x06, 0x3 }},
{ 0x32, 0x38, { 0x00d, 5413, 100, 0, 3, 0x00, 0xc8, 0x2b, 0x90, 0x05, 0x06, 0x3 }},
{ 0x39, 0x47, { 0x00e, 4382, 100, 0, 3, 0x00, 0xc8, 0x2b, 0x90, 0x05, 0x06, 0x3 }},
{ 0x48, 0x6c, { 0x00f, 2846, 100, 0, 3, 0x00, 0xc8, 0x2b, 0x90, 0x05, 0x06, 0x3 }},
{ 0x15, 0x6c, { 0x002, 4498, 100, 0, 2, 0x00, 0xd4, 0x22, 0x80, 0x01, 0x05, 0x0 }}
};
static const YRW801_REGION_DATA regions_68[] = {
/* Sitar */
{ 0x00, 0x7f, { 0x10f, 4408, 100, 0, 2, 0x00, 0xc4, 0x32, 0xf4, 0x15, 0x16, 0x1 }}
};
static const YRW801_REGION_DATA regions_69[] = {
/* Banjo */
{ 0x15, 0x34, { 0x013, 5685, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }},
{ 0x35, 0x38, { 0x014, 5009, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }},
{ 0x39, 0x3c, { 0x012, 4520, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }},
{ 0x3d, 0x44, { 0x015, 3622, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }},
{ 0x45, 0x4c, { 0x017, 2661, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }},
{ 0x4d, 0x6d, { 0x016, 1632, 100, 0, 0, 0x00, 0xdc, 0x38, 0xf6, 0x15, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_6a[] = {
/* Shamisen */
{ 0x15, 0x6c, { 0x10e, 3273, 100, 0, 0, 0x00, 0xc0, 0x28, 0xf7, 0x76, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_6b[] = {
/* Koto */
{ 0x00, 0x7f, { 0x0a9, 4033, 100, 0, 0, 0x00, 0xc6, 0x20, 0xf0, 0x06, 0x07, 0x0 }}
};
static const YRW801_REGION_DATA regions_6c[] = {
/* Kalimba */
{ 0x00, 0x7f, { 0x137, 3749, 100, 0, 0, 0x00, 0xce, 0x38, 0xf5, 0x18, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_6d[] = {
/* Bagpipe */
{ 0x15, 0x39, { 0x0a4, 7683, 100, 0, 4, 0x00, 0xc0, 0x1c, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x15, 0x39, { 0x0a7, 7680, 100, 0, 1, 0x00, 0xaa, 0x19, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x3a, 0x6c, { 0x0a8, 3697, 100, 0, 1, 0x00, 0xaa, 0x19, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_6e[] = {
/* Fiddle */
{ 0x15, 0x3a, { 0x105, 5158, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x3b, 0x3f, { 0x102, 4754, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x40, 0x41, { 0x106, 4132, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x42, 0x44, { 0x107, 4033, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x45, 0x47, { 0x108, 3580, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x48, 0x4a, { 0x10a, 2957, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4b, 0x4c, { 0x10b, 2724, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4d, 0x4e, { 0x10c, 2530, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x4f, 0x51, { 0x10d, 2166, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }},
{ 0x52, 0x6c, { 0x109, 1825, 100, 0, 1, 0x00, 0xca, 0x31, 0xf3, 0x20, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_6f[] = {
/* Shanai */
{ 0x15, 0x6c, { 0x041, 6946, 100, 0, 1, 0x00, 0xc4, 0x31, 0x95, 0x20, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_70[] = {
/* Tinkle Bell */
{ 0x15, 0x73, { 0x0f3, 1821, 100, 0, 3, 0x00, 0xc8, 0x3b, 0xd6, 0x25, 0x25, 0x0 }},
{ 0x00, 0x7f, { 0x137, 5669, 100, 0, 3, 0x00, 0x66, 0x3b, 0xf5, 0x18, 0x08, 0x0 }}
};
static const YRW801_REGION_DATA regions_71[] = {
/* Agogo */
{ 0x15, 0x74, { 0x00b, 2474, 100, 0, 0, 0x00, 0xd2, 0x38, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_72[] = {
/* Steel Drums */
{ 0x01, 0x7f, { 0x0fe, 3670, 100, 0, 0, 0x00, 0xca, 0x38, 0xf3, 0x06, 0x17, 0x1 }},
{ 0x15, 0x6c, { 0x100, 9602, 100, 0, 0, 0x00, 0x54, 0x38, 0xb0, 0x05, 0x16, 0x1 }}
};
static const YRW801_REGION_DATA regions_73[] = {
/* Woodblock */
{ 0x15, 0x6c, { 0x02c, 2963, 50, 0, 0, 0x07, 0xd4, 0x00, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_74[] = {
/* Taiko Drum */
{ 0x13, 0x6c, { 0x03e, 1194, 50, 0, 0, 0x00, 0xaa, 0x38, 0xf0, 0x04, 0x04, 0x0 }}
};
static const YRW801_REGION_DATA regions_75[] = {
/* Melodic Tom */
{ 0x15, 0x6c, { 0x0c7, 6418, 50, 0, 0, 0x00, 0xe4, 0x38, 0xf0, 0x05, 0x01, 0x0 }}
};
static const YRW801_REGION_DATA regions_76[] = {
/* Synth Drum */
{ 0x15, 0x6c, { 0x026, 3898, 50, 0, 0, 0x00, 0xd0, 0x38, 0xf0, 0x04, 0x04, 0x0 }}
};
static const YRW801_REGION_DATA regions_77[] = {
/* Reverse Cymbal */
{ 0x15, 0x6c, { 0x031, 4138, 50, 0, 0, 0x00, 0xfe, 0x38, 0x3a, 0xf0, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_78[] = {
/* Guitar Fret Noise */
{ 0x15, 0x6c, { 0x138, 5266, 100, 0, 0, 0x00, 0xa0, 0x38, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_79[] = {
/* Breath Noise */
{ 0x01, 0x7f, { 0x125, 4269, 100, 0, 0, 0x1e, 0xd0, 0x38, 0xf0, 0x00, 0x09, 0x0 }}
};
static const YRW801_REGION_DATA regions_7a[] = {
/* Seashore */
{ 0x15, 0x6c, { 0x008, 2965, 20, -2, 0, 0x00, 0xfe, 0x00, 0x20, 0x03, 0x04, 0x0 }},
{ 0x01, 0x7f, { 0x037, 4394, 20, 2, 0, 0x14, 0xfe, 0x00, 0x20, 0x04, 0x05, 0x0 } }
};
static const YRW801_REGION_DATA regions_7b[] = {
/* Bird Tweet */
{ 0x15, 0x6c, { 0x009, 8078, 5, -4, 7, 0x00, 0xc2, 0x0f, 0x22, 0x12, 0x07, 0x0 }},
{ 0x15, 0x6c, { 0x009, 3583, 5, 4, 5, 0x00, 0xae, 0x15, 0x72, 0x12, 0x07, 0x0 } }
};
static const YRW801_REGION_DATA regions_7c[] = {
/* Telephone Ring */
{ 0x15, 0x6c, { 0x003, 3602, 10, 0, 0, 0x00, 0xce, 0x00, 0xf0, 0x00, 0x0f, 0x0 }}
};
static const YRW801_REGION_DATA regions_7d[] = {
/* Helicopter */
{ 0x0c, 0x7f, { 0x001, 2965, 10, -2, 0, 0x00, 0xe0, 0x08, 0x30, 0x01, 0x07, 0x0 }},
{ 0x01, 0x7f, { 0x037, 4394, 10, 2, 0, 0x44, 0x76, 0x00, 0x30, 0x01, 0x07, 0x0 } }
};
static const YRW801_REGION_DATA regions_7e[] = {
/* Applause */
{ 0x15, 0x6c, { 0x036, 8273, 20, -6, 7, 0x00, 0xc4, 0x0f, 0x70, 0x01, 0x05, 0x0 }},
{ 0x15, 0x6c, { 0x036, 8115, 5, 6, 7, 0x00, 0xc6, 0x07, 0x70, 0x01, 0x05, 0x0 } }
};
static const YRW801_REGION_DATA regions_7f[] = {
/* Gun Shot */
{ 0x15, 0x6c, { 0x139, 2858, 20, 0, 0, 0x00, 0xbe, 0x38, 0xf0, 0x03, 0x00, 0x0 }}
};
static const YRW801_REGION_DATA regions_drums[] = {
{ 0x18, 0x18, { 0x0cb, 6397, 100, 3, 0, 0x00, 0xf4, 0x38, 0xc9, 0x1c, 0x0c, 0x0 } },
{ 0x19, 0x19, { 0x0c4, 3714, 100, 0, 0, 0x00, 0xe0, 0x00, 0x97, 0x19, 0x09, 0x0 } },
{ 0x1a, 0x1a, { 0x0c4, 3519, 100, 0, 0, 0x00, 0xea, 0x00, 0x61, 0x01, 0x07, 0x0 } },
{ 0x1b, 0x1b, { 0x0c4, 3586, 100, 0, 0, 0x00, 0xea, 0x00, 0xf7, 0x19, 0x09, 0x0 } },
{ 0x1c, 0x1c, { 0x0c4, 3586, 100, 0, 0, 0x00, 0xea, 0x00, 0x81, 0x01, 0x07, 0x0 } },
{ 0x1e, 0x1e, { 0x0c3, 4783, 100, 0, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x1f, 0x1f, { 0x0d1, 4042, 100, 0, 0, 0x00, 0xd6, 0x00, 0xf0, 0x05, 0x05, 0x0 } },
{ 0x20, 0x20, { 0x0d2, 5943, 100, 0, 0, 0x00, 0xcc, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x21, 0x21, { 0x011, 3842, 100, 0, 0, 0x00, 0xea, 0x00, 0xf0, 0x16, 0x06, 0x0 } },
{ 0x23, 0x23, { 0x011, 4098, 100, 0, 0, 0x00, 0xea, 0x00, 0xf0, 0x16, 0x06, 0x0 } },
{ 0x24, 0x24, { 0x011, 4370, 100, 0, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x06, 0x0 } },
{ 0x25, 0x25, { 0x0d2, 4404, 100, 0, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x06, 0x0 } },
{ 0x26, 0x26, { 0x0d1, 4298, 100, 0, 0, 0x00, 0xd6, 0x00, 0xf0, 0x05, 0x05, 0x0 } },
{ 0x27, 0x27, { 0x00a, 4403, 100, -1, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x28, 0x28, { 0x0d1, 4554, 100, 0, 0, 0x00, 0xdc, 0x00, 0xf0, 0x07, 0x07, 0x0 } },
{ 0x29, 0x29, { 0x0c8, 4242, 100, -4, 0, 0x00, 0xd6, 0x00, 0xf6, 0x16, 0x06, 0x0 }},
{ 0x2a, 0x2a, { 0x079, 6160, 100, 2, 0, 0x00, 0xe0, 0x00, 0xf5, 0x19, 0x09, 0x0 } },
{ 0x2b, 0x2b, { 0x0c8, 4626, 100, -3, 0, 0x00, 0xd6, 0x00, 0xf6, 0x16, 0x06, 0x0 }},
{ 0x2c, 0x2c, { 0x07b, 6039, 100, 2, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x2d, 0x2d, { 0x0c8, 5394, 100, -2, 0, 0x00, 0xd6, 0x00, 0xf6, 0x16, 0x06, 0x0 }},
{ 0x2e, 0x2e, { 0x07a, 5690, 100, 2, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x05, 0x0 } },
{ 0x2f, 0x2f, { 0x0c7, 5185, 100, 2, 0, 0x00, 0xe0, 0x00, 0xf6, 0x17, 0x07, 0x0 } },
{ 0x30, 0x30, { 0x0c7, 5650, 100, 3, 0, 0x00, 0xe0, 0x00, 0xf6, 0x17, 0x07, 0x0 } },
{ 0x31, 0x31, { 0x031, 4395, 100, 2, 0, 0x00, 0xea, 0x00, 0xf0, 0x05, 0x05, 0x0 } },
{ 0x32, 0x32, { 0x0c7, 6162, 100, 4, 0, 0x00, 0xe0, 0x00, 0xf6, 0x17, 0x07, 0x0 } },
{ 0x33, 0x33, { 0x02e, 4391, 100, -2, 0, 0x00, 0xea, 0x00, 0xf0, 0x05, 0x05, 0x0 }},
{ 0x34, 0x34, { 0x07a, 3009, 100, -2, 0, 0x00, 0xea, 0x00, 0xf2, 0x15, 0x05, 0x0 }},
{ 0x35, 0x35, { 0x021, 4522, 100, -3, 0, 0x00, 0xd6, 0x00, 0xf0, 0x05, 0x05, 0x0 }},
{ 0x36, 0x36, { 0x025, 5163, 100, 1, 0, 0x00, 0xe0, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x37, 0x37, { 0x031, 5287, 100, -1, 0, 0x00, 0xea, 0x00, 0xf5, 0x16, 0x06, 0x0 }},
{ 0x38, 0x38, { 0x01d, 4395, 100, 2, 0, 0x00, 0xe0, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x39, 0x39, { 0x031, 4647, 100, -2, 0, 0x00, 0xea, 0x00, 0xf4, 0x16, 0x06, 0x0 }},
{ 0x3a, 0x3a, { 0x09d, 4426, 100, -4, 0, 0x00, 0xe0, 0x00, 0xf4, 0x17, 0x07, 0x0 }},
{ 0x3b, 0x3b, { 0x02e, 4659, 100, -2, 0, 0x00, 0xea, 0x00, 0xf0, 0x06, 0x06, 0x0 }},
{ 0x3c, 0x3c, { 0x01c, 4769, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x3d, 0x3d, { 0x01c, 4611, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x3e, 0x3e, { 0x01e, 4402, 100, -3, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x3f, 0x3f, { 0x01f, 4387, 100, -3, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x40, 0x40, { 0x01f, 3983, 100, -2, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x41, 0x41, { 0x09c, 4526, 100, 2, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x42, 0x42, { 0x09c, 4016, 100, 2, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x43, 0x43, { 0x00b, 4739, 100, -4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x44, 0x44, { 0x00b, 4179, 100, -4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x45, 0x45, { 0x02f, 4787, 100, -4, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x46, 0x46, { 0x030, 4665, 100, -4, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x47, 0x47, { 0x144, 4519, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x0b, 0x0 } },
{ 0x48, 0x48, { 0x144, 4111, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x0b, 0x0 } },
{ 0x49, 0x49, { 0x024, 6408, 100, 3, 0, 0x00, 0xe0, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x4a, 0x4a, { 0x024, 4144, 100, 3, 0, 0x00, 0xcc, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x4b, 0x4b, { 0x020, 4001, 100, 2, 0, 0x00, 0xe0, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x4c, 0x4c, { 0x02c, 4402, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x4d, 0x4d, { 0x02c, 3612, 100, 4, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 } },
{ 0x4e, 0x4e, { 0x022, 4129, 100, -2, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x4f, 0x4f, { 0x023, 4147, 100, -2, 0, 0x00, 0xea, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x50, 0x50, { 0x032, 4412, 100, -4, 0, 0x00, 0xd6, 0x00, 0xf0, 0x08, 0x09, 0x0 }},
{ 0x51, 0x51, { 0x032, 4385, 100, -4, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 }},
{ 0x52, 0x52, { 0x02f, 5935, 100, -1, 0, 0x00, 0xd6, 0x00, 0xf0, 0x00, 0x09, 0x0 }}
};
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#define REGION(num) \
{ \
ARRAY_SIZE(regions##num), regions##num \
}
const YRW801_REGION_DATA_PTR snd_yrw801_regions[0x81] = {
REGION(_00), REGION(_01), REGION(_02), REGION(_03),
REGION(_04), REGION(_05), REGION(_06), REGION(_07),
REGION(_08), REGION(_09), REGION(_0a), REGION(_0b),
REGION(_0c), REGION(_0d), REGION(_0e), REGION(_0f),
REGION(_10), REGION(_11), REGION(_12), REGION(_13),
REGION(_14), REGION(_15), REGION(_16), REGION(_17),
REGION(_18), REGION(_19), REGION(_1a), REGION(_1b),
REGION(_1c), REGION(_1d), REGION(_1e), REGION(_1f),
REGION(_20), REGION(_21), REGION(_22), REGION(_23),
REGION(_24), REGION(_25), REGION(_26), REGION(_27),
REGION(_28), REGION(_29), REGION(_2a), REGION(_2b),
REGION(_2c), REGION(_2d), REGION(_2e), REGION(_2f),
REGION(_30), REGION(_31), REGION(_32), REGION(_33),
REGION(_34), REGION(_35), REGION(_36), REGION(_37),
REGION(_38), REGION(_39), REGION(_3a), REGION(_3b),
REGION(_3c), REGION(_3d), REGION(_3e), REGION(_3f),
REGION(_40), REGION(_41), REGION(_42), REGION(_43),
REGION(_44), REGION(_45), REGION(_46), REGION(_47),
REGION(_48), REGION(_49), REGION(_4a), REGION(_4b),
REGION(_4c), REGION(_4d), REGION(_4e), REGION(_4f),
REGION(_50), REGION(_51), REGION(_52), REGION(_53),
REGION(_54), REGION(_55), REGION(_56), REGION(_57),
REGION(_58), REGION(_59), REGION(_5a), REGION(_5b),
REGION(_5c), REGION(_5d), REGION(_5e), REGION(_5f),
REGION(_60), REGION(_61), REGION(_62), REGION(_63),
REGION(_64), REGION(_65), REGION(_66), REGION(_67),
REGION(_68), REGION(_69), REGION(_6a), REGION(_6b),
REGION(_6c), REGION(_6d), REGION(_6e), REGION(_6f),
REGION(_70), REGION(_71), REGION(_72), REGION(_73),
REGION(_74), REGION(_75), REGION(_76), REGION(_77),
REGION(_78), REGION(_79), REGION(_7a), REGION(_7b),
REGION(_7c), REGION(_7d), REGION(_7e), REGION(_7f),
REGION(_drums)
};
``` | /content/code_sandbox/src/sound/midi_opl4_yrw801.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 44,533 |
```c
// Based off ROBOPLAY's OPL4 MID player code, with some fixes and modifications to make it work well.
#include <stdint.h>
#include <stdio.h>
#include <stdbool.h>
#include <stdatomic.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/midi.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/rom.h>
#include <86box/sound.h>
#include <86box/ui.h>
#include <86box/snd_opl.h>
#include <86box/opl4_defines.h>
#include "yrw801.h"
#define NR_OF_MIDI_CHANNELS 16
#define NR_OF_WAVE_CHANNELS 24
#define DRUM_CHANNEL 9
typedef struct
{
uint8_t instrument;
uint8_t panpot;
uint8_t vibrato;
bool drum_channel;
} MIDI_CHANNEL_DATA;
typedef struct
{
bool is_active;
uint64_t activated;
uint8_t number;
MIDI_CHANNEL_DATA *midi_channel;
uint8_t note;
uint8_t velocity;
const YRW801_WAVE_DATA *wave_data;
uint8_t level_direct;
uint8_t reg_f_number;
uint8_t reg_misc;
uint8_t reg_lfo_vibrato;
} VOICE_DATA;
static const int16_t g_wave_pitch_map[0x600] = {
0x000, 0x000, 0x001, 0x001, 0x002, 0x002, 0x003, 0x003,
0x004, 0x004, 0x005, 0x005, 0x006, 0x006, 0x006, 0x007,
0x007, 0x008, 0x008, 0x009, 0x009, 0x00a, 0x00a, 0x00b,
0x00b, 0x00c, 0x00c, 0x00d, 0x00d, 0x00d, 0x00e, 0x00e,
0x00f, 0x00f, 0x010, 0x010, 0x011, 0x011, 0x012, 0x012,
0x013, 0x013, 0x014, 0x014, 0x015, 0x015, 0x015, 0x016,
0x016, 0x017, 0x017, 0x018, 0x018, 0x019, 0x019, 0x01a,
0x01a, 0x01b, 0x01b, 0x01c, 0x01c, 0x01d, 0x01d, 0x01e,
0x01e, 0x01e, 0x01f, 0x01f, 0x020, 0x020, 0x021, 0x021,
0x022, 0x022, 0x023, 0x023, 0x024, 0x024, 0x025, 0x025,
0x026, 0x026, 0x027, 0x027, 0x028, 0x028, 0x029, 0x029,
0x029, 0x02a, 0x02a, 0x02b, 0x02b, 0x02c, 0x02c, 0x02d,
0x02d, 0x02e, 0x02e, 0x02f, 0x02f, 0x030, 0x030, 0x031,
0x031, 0x032, 0x032, 0x033, 0x033, 0x034, 0x034, 0x035,
0x035, 0x036, 0x036, 0x037, 0x037, 0x038, 0x038, 0x038,
0x039, 0x039, 0x03a, 0x03a, 0x03b, 0x03b, 0x03c, 0x03c,
0x03d, 0x03d, 0x03e, 0x03e, 0x03f, 0x03f, 0x040, 0x040,
0x041, 0x041, 0x042, 0x042, 0x043, 0x043, 0x044, 0x044,
0x045, 0x045, 0x046, 0x046, 0x047, 0x047, 0x048, 0x048,
0x049, 0x049, 0x04a, 0x04a, 0x04b, 0x04b, 0x04c, 0x04c,
0x04d, 0x04d, 0x04e, 0x04e, 0x04f, 0x04f, 0x050, 0x050,
0x051, 0x051, 0x052, 0x052, 0x053, 0x053, 0x054, 0x054,
0x055, 0x055, 0x056, 0x056, 0x057, 0x057, 0x058, 0x058,
0x059, 0x059, 0x05a, 0x05a, 0x05b, 0x05b, 0x05c, 0x05c,
0x05d, 0x05d, 0x05e, 0x05e, 0x05f, 0x05f, 0x060, 0x060,
0x061, 0x061, 0x062, 0x062, 0x063, 0x063, 0x064, 0x064,
0x065, 0x065, 0x066, 0x066, 0x067, 0x067, 0x068, 0x068,
0x069, 0x069, 0x06a, 0x06a, 0x06b, 0x06b, 0x06c, 0x06c,
0x06d, 0x06d, 0x06e, 0x06e, 0x06f, 0x06f, 0x070, 0x071,
0x071, 0x072, 0x072, 0x073, 0x073, 0x074, 0x074, 0x075,
0x075, 0x076, 0x076, 0x077, 0x077, 0x078, 0x078, 0x079,
0x079, 0x07a, 0x07a, 0x07b, 0x07b, 0x07c, 0x07c, 0x07d,
0x07d, 0x07e, 0x07e, 0x07f, 0x07f, 0x080, 0x081, 0x081,
0x082, 0x082, 0x083, 0x083, 0x084, 0x084, 0x085, 0x085,
0x086, 0x086, 0x087, 0x087, 0x088, 0x088, 0x089, 0x089,
0x08a, 0x08a, 0x08b, 0x08b, 0x08c, 0x08d, 0x08d, 0x08e,
0x08e, 0x08f, 0x08f, 0x090, 0x090, 0x091, 0x091, 0x092,
0x092, 0x093, 0x093, 0x094, 0x094, 0x095, 0x096, 0x096,
0x097, 0x097, 0x098, 0x098, 0x099, 0x099, 0x09a, 0x09a,
0x09b, 0x09b, 0x09c, 0x09c, 0x09d, 0x09d, 0x09e, 0x09f,
0x09f, 0x0a0, 0x0a0, 0x0a1, 0x0a1, 0x0a2, 0x0a2, 0x0a3,
0x0a3, 0x0a4, 0x0a4, 0x0a5, 0x0a6, 0x0a6, 0x0a7, 0x0a7,
0x0a8, 0x0a8, 0x0a9, 0x0a9, 0x0aa, 0x0aa, 0x0ab, 0x0ab,
0x0ac, 0x0ad, 0x0ad, 0x0ae, 0x0ae, 0x0af, 0x0af, 0x0b0,
0x0b0, 0x0b1, 0x0b1, 0x0b2, 0x0b2, 0x0b3, 0x0b4, 0x0b4,
0x0b5, 0x0b5, 0x0b6, 0x0b6, 0x0b7, 0x0b7, 0x0b8, 0x0b8,
0x0b9, 0x0ba, 0x0ba, 0x0bb, 0x0bb, 0x0bc, 0x0bc, 0x0bd,
0x0bd, 0x0be, 0x0be, 0x0bf, 0x0c0, 0x0c0, 0x0c1, 0x0c1,
0x0c2, 0x0c2, 0x0c3, 0x0c3, 0x0c4, 0x0c4, 0x0c5, 0x0c6,
0x0c6, 0x0c7, 0x0c7, 0x0c8, 0x0c8, 0x0c9, 0x0c9, 0x0ca,
0x0cb, 0x0cb, 0x0cc, 0x0cc, 0x0cd, 0x0cd, 0x0ce, 0x0ce,
0x0cf, 0x0d0, 0x0d0, 0x0d1, 0x0d1, 0x0d2, 0x0d2, 0x0d3,
0x0d3, 0x0d4, 0x0d5, 0x0d5, 0x0d6, 0x0d6, 0x0d7, 0x0d7,
0x0d8, 0x0d8, 0x0d9, 0x0da, 0x0da, 0x0db, 0x0db, 0x0dc,
0x0dc, 0x0dd, 0x0de, 0x0de, 0x0df, 0x0df, 0x0e0, 0x0e0,
0x0e1, 0x0e1, 0x0e2, 0x0e3, 0x0e3, 0x0e4, 0x0e4, 0x0e5,
0x0e5, 0x0e6, 0x0e7, 0x0e7, 0x0e8, 0x0e8, 0x0e9, 0x0e9,
0x0ea, 0x0eb, 0x0eb, 0x0ec, 0x0ec, 0x0ed, 0x0ed, 0x0ee,
0x0ef, 0x0ef, 0x0f0, 0x0f0, 0x0f1, 0x0f1, 0x0f2, 0x0f3,
0x0f3, 0x0f4, 0x0f4, 0x0f5, 0x0f5, 0x0f6, 0x0f7, 0x0f7,
0x0f8, 0x0f8, 0x0f9, 0x0f9, 0x0fa, 0x0fb, 0x0fb, 0x0fc,
0x0fc, 0x0fd, 0x0fd, 0x0fe, 0x0ff, 0x0ff, 0x100, 0x100,
0x101, 0x101, 0x102, 0x103, 0x103, 0x104, 0x104, 0x105,
0x106, 0x106, 0x107, 0x107, 0x108, 0x108, 0x109, 0x10a,
0x10a, 0x10b, 0x10b, 0x10c, 0x10c, 0x10d, 0x10e, 0x10e,
0x10f, 0x10f, 0x110, 0x111, 0x111, 0x112, 0x112, 0x113,
0x114, 0x114, 0x115, 0x115, 0x116, 0x116, 0x117, 0x118,
0x118, 0x119, 0x119, 0x11a, 0x11b, 0x11b, 0x11c, 0x11c,
0x11d, 0x11e, 0x11e, 0x11f, 0x11f, 0x120, 0x120, 0x121,
0x122, 0x122, 0x123, 0x123, 0x124, 0x125, 0x125, 0x126,
0x126, 0x127, 0x128, 0x128, 0x129, 0x129, 0x12a, 0x12b,
0x12b, 0x12c, 0x12c, 0x12d, 0x12e, 0x12e, 0x12f, 0x12f,
0x130, 0x131, 0x131, 0x132, 0x132, 0x133, 0x134, 0x134,
0x135, 0x135, 0x136, 0x137, 0x137, 0x138, 0x138, 0x139,
0x13a, 0x13a, 0x13b, 0x13b, 0x13c, 0x13d, 0x13d, 0x13e,
0x13e, 0x13f, 0x140, 0x140, 0x141, 0x141, 0x142, 0x143,
0x143, 0x144, 0x144, 0x145, 0x146, 0x146, 0x147, 0x148,
0x148, 0x149, 0x149, 0x14a, 0x14b, 0x14b, 0x14c, 0x14c,
0x14d, 0x14e, 0x14e, 0x14f, 0x14f, 0x150, 0x151, 0x151,
0x152, 0x153, 0x153, 0x154, 0x154, 0x155, 0x156, 0x156,
0x157, 0x157, 0x158, 0x159, 0x159, 0x15a, 0x15b, 0x15b,
0x15c, 0x15c, 0x15d, 0x15e, 0x15e, 0x15f, 0x160, 0x160,
0x161, 0x161, 0x162, 0x163, 0x163, 0x164, 0x165, 0x165,
0x166, 0x166, 0x167, 0x168, 0x168, 0x169, 0x16a, 0x16a,
0x16b, 0x16b, 0x16c, 0x16d, 0x16d, 0x16e, 0x16f, 0x16f,
0x170, 0x170, 0x171, 0x172, 0x172, 0x173, 0x174, 0x174,
0x175, 0x175, 0x176, 0x177, 0x177, 0x178, 0x179, 0x179,
0x17a, 0x17a, 0x17b, 0x17c, 0x17c, 0x17d, 0x17e, 0x17e,
0x17f, 0x180, 0x180, 0x181, 0x181, 0x182, 0x183, 0x183,
0x184, 0x185, 0x185, 0x186, 0x187, 0x187, 0x188, 0x188,
0x189, 0x18a, 0x18a, 0x18b, 0x18c, 0x18c, 0x18d, 0x18e,
0x18e, 0x18f, 0x190, 0x190, 0x191, 0x191, 0x192, 0x193,
0x193, 0x194, 0x195, 0x195, 0x196, 0x197, 0x197, 0x198,
0x199, 0x199, 0x19a, 0x19a, 0x19b, 0x19c, 0x19c, 0x19d,
0x19e, 0x19e, 0x19f, 0x1a0, 0x1a0, 0x1a1, 0x1a2, 0x1a2,
0x1a3, 0x1a4, 0x1a4, 0x1a5, 0x1a6, 0x1a6, 0x1a7, 0x1a8,
0x1a8, 0x1a9, 0x1a9, 0x1aa, 0x1ab, 0x1ab, 0x1ac, 0x1ad,
0x1ad, 0x1ae, 0x1af, 0x1af, 0x1b0, 0x1b1, 0x1b1, 0x1b2,
0x1b3, 0x1b3, 0x1b4, 0x1b5, 0x1b5, 0x1b6, 0x1b7, 0x1b7,
0x1b8, 0x1b9, 0x1b9, 0x1ba, 0x1bb, 0x1bb, 0x1bc, 0x1bd,
0x1bd, 0x1be, 0x1bf, 0x1bf, 0x1c0, 0x1c1, 0x1c1, 0x1c2,
0x1c3, 0x1c3, 0x1c4, 0x1c5, 0x1c5, 0x1c6, 0x1c7, 0x1c7,
0x1c8, 0x1c9, 0x1c9, 0x1ca, 0x1cb, 0x1cb, 0x1cc, 0x1cd,
0x1cd, 0x1ce, 0x1cf, 0x1cf, 0x1d0, 0x1d1, 0x1d1, 0x1d2,
0x1d3, 0x1d3, 0x1d4, 0x1d5, 0x1d5, 0x1d6, 0x1d7, 0x1d7,
0x1d8, 0x1d9, 0x1d9, 0x1da, 0x1db, 0x1db, 0x1dc, 0x1dd,
0x1dd, 0x1de, 0x1df, 0x1df, 0x1e0, 0x1e1, 0x1e1, 0x1e2,
0x1e3, 0x1e4, 0x1e4, 0x1e5, 0x1e6, 0x1e6, 0x1e7, 0x1e8,
0x1e8, 0x1e9, 0x1ea, 0x1ea, 0x1eb, 0x1ec, 0x1ec, 0x1ed,
0x1ee, 0x1ee, 0x1ef, 0x1f0, 0x1f0, 0x1f1, 0x1f2, 0x1f3,
0x1f3, 0x1f4, 0x1f5, 0x1f5, 0x1f6, 0x1f7, 0x1f7, 0x1f8,
0x1f9, 0x1f9, 0x1fa, 0x1fb, 0x1fb, 0x1fc, 0x1fd, 0x1fe,
0x1fe, 0x1ff, 0x200, 0x200, 0x201, 0x202, 0x202, 0x203,
0x204, 0x205, 0x205, 0x206, 0x207, 0x207, 0x208, 0x209,
0x209, 0x20a, 0x20b, 0x20b, 0x20c, 0x20d, 0x20e, 0x20e,
0x20f, 0x210, 0x210, 0x211, 0x212, 0x212, 0x213, 0x214,
0x215, 0x215, 0x216, 0x217, 0x217, 0x218, 0x219, 0x21a,
0x21a, 0x21b, 0x21c, 0x21c, 0x21d, 0x21e, 0x21e, 0x21f,
0x220, 0x221, 0x221, 0x222, 0x223, 0x223, 0x224, 0x225,
0x226, 0x226, 0x227, 0x228, 0x228, 0x229, 0x22a, 0x22b,
0x22b, 0x22c, 0x22d, 0x22d, 0x22e, 0x22f, 0x230, 0x230,
0x231, 0x232, 0x232, 0x233, 0x234, 0x235, 0x235, 0x236,
0x237, 0x237, 0x238, 0x239, 0x23a, 0x23a, 0x23b, 0x23c,
0x23c, 0x23d, 0x23e, 0x23f, 0x23f, 0x240, 0x241, 0x241,
0x242, 0x243, 0x244, 0x244, 0x245, 0x246, 0x247, 0x247,
0x248, 0x249, 0x249, 0x24a, 0x24b, 0x24c, 0x24c, 0x24d,
0x24e, 0x24f, 0x24f, 0x250, 0x251, 0x251, 0x252, 0x253,
0x254, 0x254, 0x255, 0x256, 0x257, 0x257, 0x258, 0x259,
0x259, 0x25a, 0x25b, 0x25c, 0x25c, 0x25d, 0x25e, 0x25f,
0x25f, 0x260, 0x261, 0x262, 0x262, 0x263, 0x264, 0x265,
0x265, 0x266, 0x267, 0x267, 0x268, 0x269, 0x26a, 0x26a,
0x26b, 0x26c, 0x26d, 0x26d, 0x26e, 0x26f, 0x270, 0x270,
0x271, 0x272, 0x273, 0x273, 0x274, 0x275, 0x276, 0x276,
0x277, 0x278, 0x279, 0x279, 0x27a, 0x27b, 0x27c, 0x27c,
0x27d, 0x27e, 0x27f, 0x27f, 0x280, 0x281, 0x282, 0x282,
0x283, 0x284, 0x285, 0x285, 0x286, 0x287, 0x288, 0x288,
0x289, 0x28a, 0x28b, 0x28b, 0x28c, 0x28d, 0x28e, 0x28e,
0x28f, 0x290, 0x291, 0x291, 0x292, 0x293, 0x294, 0x294,
0x295, 0x296, 0x297, 0x298, 0x298, 0x299, 0x29a, 0x29b,
0x29b, 0x29c, 0x29d, 0x29e, 0x29e, 0x29f, 0x2a0, 0x2a1,
0x2a1, 0x2a2, 0x2a3, 0x2a4, 0x2a5, 0x2a5, 0x2a6, 0x2a7,
0x2a8, 0x2a8, 0x2a9, 0x2aa, 0x2ab, 0x2ab, 0x2ac, 0x2ad,
0x2ae, 0x2af, 0x2af, 0x2b0, 0x2b1, 0x2b2, 0x2b2, 0x2b3,
0x2b4, 0x2b5, 0x2b5, 0x2b6, 0x2b7, 0x2b8, 0x2b9, 0x2b9,
0x2ba, 0x2bb, 0x2bc, 0x2bc, 0x2bd, 0x2be, 0x2bf, 0x2c0,
0x2c0, 0x2c1, 0x2c2, 0x2c3, 0x2c4, 0x2c4, 0x2c5, 0x2c6,
0x2c7, 0x2c7, 0x2c8, 0x2c9, 0x2ca, 0x2cb, 0x2cb, 0x2cc,
0x2cd, 0x2ce, 0x2ce, 0x2cf, 0x2d0, 0x2d1, 0x2d2, 0x2d2,
0x2d3, 0x2d4, 0x2d5, 0x2d6, 0x2d6, 0x2d7, 0x2d8, 0x2d9,
0x2da, 0x2da, 0x2db, 0x2dc, 0x2dd, 0x2dd, 0x2de, 0x2df,
0x2e0, 0x2e1, 0x2e1, 0x2e2, 0x2e3, 0x2e4, 0x2e5, 0x2e5,
0x2e6, 0x2e7, 0x2e8, 0x2e9, 0x2e9, 0x2ea, 0x2eb, 0x2ec,
0x2ed, 0x2ed, 0x2ee, 0x2ef, 0x2f0, 0x2f1, 0x2f1, 0x2f2,
0x2f3, 0x2f4, 0x2f5, 0x2f5, 0x2f6, 0x2f7, 0x2f8, 0x2f9,
0x2f9, 0x2fa, 0x2fb, 0x2fc, 0x2fd, 0x2fd, 0x2fe, 0x2ff,
0x300, 0x301, 0x302, 0x302, 0x303, 0x304, 0x305, 0x306,
0x306, 0x307, 0x308, 0x309, 0x30a, 0x30a, 0x30b, 0x30c,
0x30d, 0x30e, 0x30f, 0x30f, 0x310, 0x311, 0x312, 0x313,
0x313, 0x314, 0x315, 0x316, 0x317, 0x318, 0x318, 0x319,
0x31a, 0x31b, 0x31c, 0x31c, 0x31d, 0x31e, 0x31f, 0x320,
0x321, 0x321, 0x322, 0x323, 0x324, 0x325, 0x326, 0x326,
0x327, 0x328, 0x329, 0x32a, 0x32a, 0x32b, 0x32c, 0x32d,
0x32e, 0x32f, 0x32f, 0x330, 0x331, 0x332, 0x333, 0x334,
0x334, 0x335, 0x336, 0x337, 0x338, 0x339, 0x339, 0x33a,
0x33b, 0x33c, 0x33d, 0x33e, 0x33e, 0x33f, 0x340, 0x341,
0x342, 0x343, 0x343, 0x344, 0x345, 0x346, 0x347, 0x348,
0x349, 0x349, 0x34a, 0x34b, 0x34c, 0x34d, 0x34e, 0x34e,
0x34f, 0x350, 0x351, 0x352, 0x353, 0x353, 0x354, 0x355,
0x356, 0x357, 0x358, 0x359, 0x359, 0x35a, 0x35b, 0x35c,
0x35d, 0x35e, 0x35f, 0x35f, 0x360, 0x361, 0x362, 0x363,
0x364, 0x364, 0x365, 0x366, 0x367, 0x368, 0x369, 0x36a,
0x36a, 0x36b, 0x36c, 0x36d, 0x36e, 0x36f, 0x370, 0x370,
0x371, 0x372, 0x373, 0x374, 0x375, 0x376, 0x377, 0x377,
0x378, 0x379, 0x37a, 0x37b, 0x37c, 0x37d, 0x37d, 0x37e,
0x37f, 0x380, 0x381, 0x382, 0x383, 0x383, 0x384, 0x385,
0x386, 0x387, 0x388, 0x389, 0x38a, 0x38a, 0x38b, 0x38c,
0x38d, 0x38e, 0x38f, 0x390, 0x391, 0x391, 0x392, 0x393,
0x394, 0x395, 0x396, 0x397, 0x398, 0x398, 0x399, 0x39a,
0x39b, 0x39c, 0x39d, 0x39e, 0x39f, 0x39f, 0x3a0, 0x3a1,
0x3a2, 0x3a3, 0x3a4, 0x3a5, 0x3a6, 0x3a7, 0x3a7, 0x3a8,
0x3a9, 0x3aa, 0x3ab, 0x3ac, 0x3ad, 0x3ae, 0x3ae, 0x3af,
0x3b0, 0x3b1, 0x3b2, 0x3b3, 0x3b4, 0x3b5, 0x3b6, 0x3b6,
0x3b7, 0x3b8, 0x3b9, 0x3ba, 0x3bb, 0x3bc, 0x3bd, 0x3be,
0x3bf, 0x3bf, 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4, 0x3c5,
0x3c6, 0x3c7, 0x3c7, 0x3c8, 0x3c9, 0x3ca, 0x3cb, 0x3cc,
0x3cd, 0x3ce, 0x3cf, 0x3d0, 0x3d1, 0x3d1, 0x3d2, 0x3d3,
0x3d4, 0x3d5, 0x3d6, 0x3d7, 0x3d8, 0x3d9, 0x3da, 0x3da,
0x3db, 0x3dc, 0x3dd, 0x3de, 0x3df, 0x3e0, 0x3e1, 0x3e2,
0x3e3, 0x3e4, 0x3e4, 0x3e5, 0x3e6, 0x3e7, 0x3e8, 0x3e9,
0x3ea, 0x3eb, 0x3ec, 0x3ed, 0x3ee, 0x3ef, 0x3ef, 0x3f0,
0x3f1, 0x3f2, 0x3f3, 0x3f4, 0x3f5, 0x3f6, 0x3f7, 0x3f8,
0x3f9, 0x3fa, 0x3fa, 0x3fb, 0x3fc, 0x3fd, 0x3fe, 0x3ff
};
/*
* Attenuation according to GM recommendations, in -0.375 dB units.
* table[v] = 40 * log(v / 127) / -0.375
*/
static const uint8_t g_volume_table[128] = {
255, 224, 192, 173, 160, 150, 141, 134,
128, 122, 117, 113, 109, 105, 102, 99,
96, 93, 90, 88, 85, 83, 81, 79,
77, 75, 73, 71, 70, 68, 67, 65,
64, 62, 61, 59, 58, 57, 56, 54,
53, 52, 51, 50, 49, 48, 47, 46,
45, 44, 43, 42, 41, 40, 39, 39,
38, 37, 36, 35, 34, 34, 33, 32,
31, 31, 30, 29, 29, 28, 27, 27,
26, 25, 25, 24, 24, 23, 22, 22,
21, 21, 20, 19, 19, 18, 18, 17,
17, 16, 16, 15, 15, 14, 14, 13,
13, 12, 12, 11, 11, 10, 10, 9,
9, 9, 8, 8, 7, 7, 6, 6,
6, 5, 5, 4, 4, 4, 3, 3,
2, 2, 2, 1, 1, 0, 0, 0
};
#define BUFFER_SEGMENTS 10
#define RENDER_RATE (48000 / 100)
typedef struct opl4_midi {
fm_drv_t opl4;
MIDI_CHANNEL_DATA midi_channel_data[16];
VOICE_DATA voice_data[24];
int16_t buffer[(48000 / 100) * 2 * BUFFER_SEGMENTS];
float buffer_float[(48000 / 100) * 2 * BUFFER_SEGMENTS];
uint32_t midi_pos;
bool on;
atomic_bool gen_in_progress;
thread_t *thread;
event_t *wait_event;
} opl4_midi_t;
static opl4_midi_t *opl4_midi_cur;
static void
opl4_write_wave_register(const uint8_t reg, const uint8_t value, opl4_midi_t *opl4_midi)
{
opl4_midi->opl4.write(0x380, reg, opl4_midi->opl4.priv);
opl4_midi->opl4.write(0x381, value, opl4_midi->opl4.priv);
}
VOICE_DATA *
get_voice(const YRW801_WAVE_DATA *wave_data, opl4_midi_t *opl4_midi)
{
VOICE_DATA *free_voice = &opl4_midi->voice_data[0];
VOICE_DATA *oldest_voice = &opl4_midi->voice_data[0];
for (uint8_t voice = 0; voice < 24; voice++) {
if (opl4_midi_cur->voice_data[voice].is_active) {
if (opl4_midi_cur->voice_data[voice].activated < oldest_voice->activated)
oldest_voice = &opl4_midi_cur->voice_data[voice];
} else {
if (opl4_midi_cur->voice_data[voice].wave_data == wave_data) {
free_voice = &opl4_midi_cur->voice_data[voice];
break;
}
if (opl4_midi_cur->voice_data[voice].activated < free_voice->activated) {
free_voice = &opl4_midi_cur->voice_data[voice];
break;
}
}
}
/* If no free voice is found, look for one with the same instrument */
if (free_voice->is_active) {
for (uint8_t voice = 0; voice < 24; voice++) {
if (opl4_midi_cur->voice_data[voice].is_active
&& opl4_midi_cur->voice_data[voice].wave_data == wave_data) {
free_voice = &opl4_midi_cur->voice_data[voice];
free_voice->is_active = 0;
free_voice->activated = 0;
free_voice->reg_misc &= ~OPL4_KEY_ON_BIT;
opl4_write_wave_register(OPL4_REG_MISC + free_voice->number, free_voice->reg_misc, opl4_midi);
return free_voice;
}
}
}
/* If still no free voice found, deactivate the 'oldest' */
if (free_voice->is_active) {
free_voice = oldest_voice;
free_voice->is_active = 0;
free_voice->activated = 0;
free_voice->reg_misc &= ~OPL4_KEY_ON_BIT;
opl4_write_wave_register(OPL4_REG_MISC + free_voice->number, free_voice->reg_misc, opl4_midi);
}
return free_voice;
}
static void
update_pan(VOICE_DATA *voice, opl4_midi_t *opl4_midi)
{
int8_t pan = voice->wave_data->panpot;
if (!voice->midi_channel->drum_channel)
pan += voice->midi_channel->panpot;
if (pan < -7)
pan = -7;
else if (pan > 7)
pan = 7;
voice->reg_misc = (voice->reg_misc & ~OPL4_PAN_POT_MASK) | (pan & OPL4_PAN_POT_MASK);
opl4_write_wave_register(OPL4_REG_MISC + voice->number, voice->reg_misc, opl4_midi);
}
void
update_pitch(VOICE_DATA *voice, uint16_t pitch_bend, opl4_midi_t *opl4_midi)
{
int32_t pitch = voice->midi_channel->drum_channel ? 0 : (voice->note - 60) * 128;
pitch = pitch * (int) voice->wave_data->key_scaling / 100;
pitch = pitch + 7680;
pitch += voice->wave_data->pitch_offset;
pitch += pitch_bend * 256 / 0x2000;
if (pitch < 0)
pitch = 0;
else if (pitch > 0x5FFF)
pitch = 0x5FFF;
int8_t octave = pitch / 0x600 - 8;
uint16_t fnumber = g_wave_pitch_map[pitch % 0x600];
opl4_write_wave_register(OPL4_REG_OCTAVE + voice->number, (octave << 4) | ((fnumber >> 7) & 0x07), opl4_midi);
voice->reg_f_number = (voice->reg_f_number & OPL4_TONE_NUMBER_BIT8) | ((fnumber << 1) & OPL4_F_NUMBER_LOW_MASK);
opl4_write_wave_register(OPL4_REG_F_NUMBER + voice->number, voice->reg_f_number, opl4_midi);
}
void
update_volume(VOICE_DATA *voice, opl4_midi_t *opl4_midi)
{
int16_t att = voice->wave_data->tone_attenuate;
att += g_volume_table[voice->velocity];
att = 0x7F - (0x7F - att) * (voice->wave_data->volume_factor) / 0xFE;
att -= 16;
if (att < 0)
att = 0;
else if (att > 0x7E)
att = 0x7E;
opl4_write_wave_register(OPL4_REG_LEVEL + voice->number, (att << 1) | voice->level_direct, opl4_midi);
voice->level_direct = 0;
}
void
note_off(uint8_t note, uint8_t velocity, MIDI_CHANNEL_DATA *midi_channel, opl4_midi_t *opl4_midi)
{
/* Velocity not used */
(void) velocity;
while (opl4_midi->gen_in_progress) { }
for (uint8_t i = 0; i < 24; i++) {
VOICE_DATA *voice = &opl4_midi->voice_data[i];
if (voice->is_active && voice->midi_channel == midi_channel && voice->note == note) {
voice->is_active = false;
voice->activated = 0;
voice->reg_misc &= ~OPL4_KEY_ON_BIT;
opl4_write_wave_register(OPL4_REG_MISC + voice->number, voice->reg_misc, opl4_midi);
}
}
}
void
update_vibrato_depth(VOICE_DATA *voice, opl4_midi_t *opl4_midi)
{
uint16_t depth;
depth = (7 - voice->wave_data->vibrato) * (voice->midi_channel->vibrato & 0x7F);
depth = (depth >> 7) + voice->wave_data->vibrato;
voice->reg_lfo_vibrato &= ~OPL4_VIBRATO_DEPTH_MASK;
voice->reg_lfo_vibrato |= depth & OPL4_VIBRATO_DEPTH_MASK;
opl4_write_wave_register(OPL4_REG_LFO_VIBRATO + voice->number, voice->reg_lfo_vibrato, opl4_midi);
}
void
note_on(uint8_t note, uint8_t velocity, MIDI_CHANNEL_DATA *midi_channel, opl4_midi_t *opl4_midi)
{
const YRW801_REGION_DATA_PTR *region_ptr = &snd_yrw801_regions[0];
const YRW801_WAVE_DATA *wave_data[2];
VOICE_DATA *voice[2];
uint8_t i = 0, voices = 0;
while (opl4_midi->gen_in_progress) { }
if (midi_channel->drum_channel)
wave_data[voices++] = ®ion_ptr[0x80].regions[note - 0x1A].wave_data;
else {
/* Determine the number of voices and voice parameters */
const YRW801_REGION_DATA *region = region_ptr[midi_channel->instrument & 0x7F].regions;
while (i < region_ptr[midi_channel->instrument & 0x7F].count) {
if (note >= region[i].key_min && note <= region[i].key_max) {
wave_data[voices] = ®ion[i].wave_data;
if (++voices >= 2)
break;
}
i++;
}
}
/* Allocate and initialize needed voices */
for (i = 0; i < voices; i++) {
voice[i] = get_voice(wave_data[i], opl4_midi);
voice[i]->is_active = true;
voice[i]->activated = plat_get_ticks();
voice[i]->midi_channel = midi_channel;
voice[i]->note = note;
voice[i]->velocity = velocity & 0x7F;
}
for (i = 0; i < voices; i++) {
voice[i]->reg_f_number = (wave_data[i]->tone >> 8) & OPL4_TONE_NUMBER_BIT8;
opl4_write_wave_register(OPL4_REG_F_NUMBER + voice[i]->number, voice[i]->reg_f_number, opl4_midi);
bool new_wave = (voice[i]->wave_data != wave_data[i]);
/* Set tone number (triggers header loading) */
if (new_wave) {
opl4_write_wave_register(OPL4_REG_TONE_NUMBER + voice[i]->number, wave_data[i]->tone & 0xFF, opl4_midi);
voice[i]->wave_data = wave_data[i];
}
voice[i]->reg_misc = OPL4_LFO_RESET_BIT;
update_pan(voice[i], opl4_midi);
update_pitch(voice[i], 0, opl4_midi);
voice[i]->level_direct = OPL4_LEVEL_DIRECT_BIT;
update_volume(voice[i], opl4_midi);
if (new_wave) {
/* Set remaining parameters */
opl4_write_wave_register(OPL4_REG_ATTACK_DECAY1 + voice[i]->number, voice[i]->wave_data->reg_attack_decay1, opl4_midi);
opl4_write_wave_register(OPL4_REG_LEVEL_DECAY2 + voice[i]->number, voice[i]->wave_data->reg_level_decay2, opl4_midi);
opl4_write_wave_register(OPL4_REG_RELEASE_CORRECTION + voice[i]->number, voice[i]->wave_data->reg_release_correction, opl4_midi);
opl4_write_wave_register(OPL4_REG_TREMOLO + voice[i]->number, voice[i]->wave_data->reg_tremolo, opl4_midi);
voice[i]->reg_lfo_vibrato = voice[i]->wave_data->reg_lfo_vibrato;
if (!midi_channel->drum_channel)
update_vibrato_depth(voice[i], opl4_midi);
}
}
/* Finally, switch on all voices */
for (i = 0; i < voices; i++) {
voice[i]->reg_misc = (voice[i]->reg_misc & 0x1F) | OPL4_KEY_ON_BIT;
opl4_write_wave_register(OPL4_REG_MISC + voice[i]->number, voice[i]->reg_misc, opl4_midi);
}
}
void
control_change(uint8_t midi_channel, uint8_t id, uint8_t value, opl4_midi_t *opl4_midi)
{
int i = 0;
switch (id) {
case 10:
/* Change stereo panning */
if (midi_channel != DRUM_CHANNEL) {
opl4_midi->midi_channel_data[midi_channel].panpot = (value - 0x40) >> 3;
for (i = 0; i < NR_OF_WAVE_CHANNELS; i++) {
if (opl4_midi->voice_data[i].is_active && opl4_midi->voice_data[i].midi_channel == &opl4_midi->midi_channel_data[midi_channel]) {
update_pan(&opl4_midi->voice_data[i], opl4_midi);
}
}
}
break;
}
}
void
pitch_wheel(uint8_t midi_channel, uint16_t value, opl4_midi_t *opl4_midi)
{
int i = 0;
for (i = 0; i < 24; i++) {
if (opl4_midi->voice_data[i].is_active && opl4_midi->voice_data[i].midi_channel == &opl4_midi->midi_channel_data[midi_channel]) {
update_pitch(&opl4_midi->voice_data[i], value, opl4_midi);
}
}
}
void
channel_pressure(uint8_t midi_channel, uint8_t pressure)
{
(void) midi_channel;
(void) pressure;
}
void
key_pressure(uint8_t midi_channel, uint8_t note, uint8_t pressure)
{
(void) midi_channel;
(void) note;
(void) pressure;
}
void
program_change(uint8_t midi_channel, uint8_t program, opl4_midi_t *opl4_midi)
{
opl4_midi->midi_channel_data[midi_channel].instrument = program;
}
static void
opl4_midi_thread(void *arg)
{
opl4_midi_t *opl4_midi = opl4_midi_cur;
uint32_t i = 0;
uint32_t buf_size = RENDER_RATE * 2;
uint32_t buf_size_segments = buf_size * BUFFER_SEGMENTS;
uint32_t buf_pos = 0;
int32_t buffer[RENDER_RATE * 2];
extern void givealbuffer_midi(void *buf, uint32_t size);
while (opl4_midi->on) {
thread_wait_event(opl4_midi->wait_event, -1);
thread_reset_event(opl4_midi->wait_event);
if (!opl4_midi->on)
break;
atomic_store(&opl4_midi->gen_in_progress, true);
opl4_midi->opl4.generate(opl4_midi->opl4.priv, buffer, RENDER_RATE);
atomic_store(&opl4_midi->gen_in_progress, false);
if (sound_is_float) {
for (i = 0; i < (buf_size / 2); i++) {
opl4_midi->buffer_float[(i + buf_pos) * 2] = buffer[i * 2] / 32768.0;
opl4_midi->buffer_float[((i + buf_pos) * 2) + 1] = buffer[(i * 2) + 1] / 32768.0;
}
buf_pos += buf_size / 2;
if (buf_pos >= (buf_size_segments / 2)) {
givealbuffer_midi(opl4_midi->buffer_float, buf_size_segments);
buf_pos = 0;
}
} else {
for (i = 0; i < (buf_size / 2); i++) {
opl4_midi->buffer[(i + buf_pos) * 2] = buffer[i * 2] & 0xFFFF; /* Outputs are clamped beforehand. */
opl4_midi->buffer[((i + buf_pos) * 2) + 1] = buffer[(i * 2) + 1] & 0xFFFF; /* Outputs are clamped beforehand. */
}
buf_pos += buf_size / 2;
if (buf_pos >= (buf_size_segments / 2)) {
givealbuffer_midi(opl4_midi->buffer, buf_size_segments);
buf_pos = 0;
}
}
}
}
static void
opl4_midi_poll(void)
{
opl4_midi_t *opl4_midi = opl4_midi_cur;
opl4_midi->midi_pos++;
if (opl4_midi->midi_pos == RENDER_RATE) {
opl4_midi->midi_pos = 0;
thread_set_event(opl4_midi->wait_event);
}
}
void
opl4_midi_msg(uint8_t *val)
{
opl4_midi_t *opl4_midi = opl4_midi_cur;
uint32_t msg = *(uint32_t *) (val);
uint8_t data_byte_1 = msg & 0xFF;
uint8_t data_byte_2 = (msg >> 8) & 0xFF;
uint8_t data_byte_3 = (msg >> 16) & 0xFF;
uint8_t midi_channel = data_byte_1 & 0x0F;
uint8_t midi_command = data_byte_1 >> 4;
switch (midi_command) {
case 0x8: // Note OFF
note_off(data_byte_2 & 0x7F, data_byte_3, &opl4_midi->midi_channel_data[midi_channel], opl4_midi);
break;
case 0x9: // Note ON
note_on(data_byte_2 & 0x7F, data_byte_3, &opl4_midi->midi_channel_data[midi_channel], opl4_midi);
break;
case 0xA: // Key after-touch
break;
case 0xB: // Control change
control_change(midi_channel, data_byte_2, data_byte_3, opl4_midi);
break;
case 0xC: // Program change
program_change(midi_channel, data_byte_2 & 0x7F, opl4_midi);
break;
case 0xD: // Channel after-touch
break;
case 0xE: // Pitch wheel
pitch_wheel(midi_channel, ((data_byte_3 <<= 7) | data_byte_2), opl4_midi);
break;
}
}
void
opl4_midi_sysex(uint8_t *data, unsigned int len)
{
}
void *
opl4_init(const device_t *info)
{
midi_device_t *dev;
extern void al_set_midi(int freq, int buf_size);
dev = malloc(sizeof(midi_device_t));
memset(dev, 0, sizeof(midi_device_t));
dev->play_msg = opl4_midi_msg;
dev->play_sysex = opl4_midi_sysex;
dev->poll = opl4_midi_poll;
al_set_midi(48000, 4800);
opl4_midi_cur = calloc(1, sizeof(opl4_midi_t));
fm_driver_get(FM_YMF278B, &opl4_midi_cur->opl4);
opl4_midi_cur->opl4.write(0x38A, 0x05, opl4_midi_cur->opl4.priv);
opl4_midi_cur->opl4.write(0x389, 0x3, opl4_midi_cur->opl4.priv);
midi_out_init(dev);
opl4_midi_cur->on = true;
opl4_midi_cur->midi_channel_data[9].drum_channel = true;
atomic_init(&opl4_midi_cur->gen_in_progress, 0);
for (uint8_t voice = 0; voice < NR_OF_WAVE_CHANNELS; voice++) {
opl4_midi_cur->voice_data[voice].number = voice;
opl4_midi_cur->voice_data[voice].is_active = false;
opl4_midi_cur->voice_data[voice].activated = 0;
opl4_midi_cur->voice_data[voice].midi_channel = NULL;
opl4_midi_cur->voice_data[voice].note = 0;
opl4_midi_cur->voice_data[voice].velocity = 0;
opl4_midi_cur->voice_data[voice].wave_data = NULL;
opl4_midi_cur->voice_data[voice].level_direct = 0;
opl4_midi_cur->voice_data[voice].reg_f_number = 0;
opl4_midi_cur->voice_data[voice].reg_misc = 0;
opl4_midi_cur->voice_data[voice].reg_lfo_vibrato = 0;
}
opl4_midi_cur->wait_event = thread_create_event();
opl4_midi_cur->thread = thread_create(opl4_midi_thread, NULL);
return dev;
}
void
opl4_close(void *p)
{
if (!p)
return;
opl4_midi_cur->on = false;
thread_set_event(opl4_midi_cur->wait_event);
thread_wait(opl4_midi_cur->thread);
free(opl4_midi_cur);
opl4_midi_cur = NULL;
}
static int
opl4_midi_available(void)
{
return rom_present("roms/sound/yamaha/yrw801.rom");
}
const device_t opl4_midi_device = {
.name = "OPL4-ML Daughterboard",
.internal_name = "opl4-ml",
.flags = 0,
.local = 0,
.init = opl4_init,
.close = opl4_close,
.reset = NULL,
{ .available = opl4_midi_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/sound/midi_opl4.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 14,807 |
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