text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185 values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 1 Mbit and 2 Mbit, 8-bit and
* 16-bit flash devices.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/plat.h>
#define FLAG_WORD 4
#define FLAG_BXB 2
#define FLAG_INV_A16 1
enum {
BLOCK_MAIN1,
BLOCK_MAIN2,
BLOCK_MAIN3,
BLOCK_MAIN4,
BLOCK_DATA1,
BLOCK_DATA2,
BLOCK_BOOT,
BLOCKS_NUM
};
enum {
CMD_READ_ARRAY = 0xff,
CMD_IID = 0x90,
CMD_READ_STATUS = 0x70,
CMD_CLEAR_STATUS = 0x50,
CMD_ERASE_SETUP = 0x20,
CMD_ERASE_CONFIRM = 0xd0,
CMD_ERASE_SUSPEND = 0xb0,
CMD_PROGRAM_SETUP = 0x40,
CMD_PROGRAM_SETUP_ALT = 0x10
};
typedef struct flash_t {
uint8_t command;
uint8_t status;
uint8_t pad;
uint8_t flags;
uint8_t *array;
uint16_t flash_id;
uint16_t pad16;
uint32_t program_addr;
uint32_t block_start[BLOCKS_NUM];
uint32_t block_end[BLOCKS_NUM];
uint32_t block_len[BLOCKS_NUM];
mem_mapping_t mapping[4];
mem_mapping_t mapping_h[16];
} flash_t;
static char flash_path[1024];
static uint8_t
flash_read(uint32_t addr, void *priv)
{
const flash_t *dev = (flash_t *) priv;
uint8_t ret = 0xff;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
switch (dev->command) {
default:
case CMD_READ_ARRAY:
ret = dev->array[addr];
break;
case CMD_IID:
if (addr & 1)
ret = dev->flash_id & 0xff;
else
ret = 0x89;
break;
case CMD_READ_STATUS:
ret = dev->status;
break;
}
return ret;
}
static uint16_t
flash_readw(uint32_t addr, void *priv)
{
flash_t *dev = (flash_t *) priv;
const uint16_t *q;
uint16_t ret = 0xffff;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
if (dev->flags & FLAG_WORD)
addr &= 0xfffffffe;
q = (uint16_t *) &(dev->array[addr]);
ret = *q;
if (dev->flags & FLAG_WORD)
switch (dev->command) {
default:
case CMD_READ_ARRAY:
break;
case CMD_IID:
if (addr & 2)
ret = dev->flash_id;
else
ret = 0x0089;
break;
case CMD_READ_STATUS:
ret = dev->status;
break;
}
return ret;
}
static uint32_t
flash_readl(uint32_t addr, void *priv)
{
flash_t *dev = (flash_t *) priv;
const uint32_t *q;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
q = (uint32_t *) &(dev->array[addr]);
return *q;
}
static void
flash_write(uint32_t addr, uint8_t val, void *priv)
{
flash_t *dev = (flash_t *) priv;
uint32_t bb_mask = biosmask & 0xffffe000;
if (biosmask == 0x7ffff)
bb_mask &= 0xffff8000;
else if (biosmask == 0x3ffff)
bb_mask &= 0xffffc000;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
switch (dev->command) {
case CMD_ERASE_SETUP:
if (val == CMD_ERASE_CONFIRM) {
for (uint8_t i = 0; i < 6; i++) {
if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
}
dev->status = 0x80;
}
dev->command = CMD_READ_STATUS;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr))
dev->array[addr] = val;
dev->command = CMD_READ_STATUS;
dev->status = 0x80;
break;
default:
dev->command = val;
switch (val) {
case CMD_CLEAR_STATUS:
dev->status = 0;
break;
case CMD_ERASE_SETUP:
for (uint8_t i = 0; i < 7; i++) {
if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
dev->program_addr = i;
}
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
dev->program_addr = addr;
break;
default:
break;
}
}
}
static void
flash_writew(uint32_t addr, uint16_t val, void *priv)
{
flash_t *dev = (flash_t *) priv;
uint32_t bb_mask = biosmask & 0xffffe000;
if (biosmask == 0x7ffff)
bb_mask &= 0xffff8000;
else if (biosmask == 0x3ffff)
bb_mask &= 0xffffc000;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
if (dev->flags & FLAG_WORD)
switch (dev->command) {
case CMD_ERASE_SETUP:
if (val == CMD_ERASE_CONFIRM) {
for (uint8_t i = 0; i < 6; i++) {
if ((i == dev->program_addr) && (addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
}
dev->status = 0x80;
}
dev->command = CMD_READ_STATUS;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
if (((addr & bb_mask) != (dev->block_start[6] & bb_mask)) && (addr == dev->program_addr))
*(uint16_t *) (&dev->array[addr]) = val;
dev->command = CMD_READ_STATUS;
dev->status = 0x80;
break;
default:
dev->command = val & 0xff;
switch (val) {
case CMD_CLEAR_STATUS:
dev->status = 0;
break;
case CMD_ERASE_SETUP:
for (uint8_t i = 0; i < 7; i++) {
if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
dev->program_addr = i;
}
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
dev->program_addr = addr;
break;
default:
break;
}
}
}
static void
flash_writel(UNUSED(uint32_t addr), UNUSED(uint32_t val), UNUSED(void *priv))
{
#if 0
flash_writew(addr, val & 0xffff, priv);
flash_writew(addr + 2, (val >> 16) & 0xffff, priv);
#endif
}
static void
intel_flash_add_mappings(flash_t *dev)
{
uint8_t max = 2;
uint32_t base;
uint32_t fbase;
uint32_t sub = 0x20000;
if (biosmask == 0x7ffff) {
sub = 0x80000;
max = 8;
} else if (biosmask == 0x3ffff) {
sub = 0x40000;
max = 4;
}
for (uint8_t i = 0; i < max; i++) {
if (biosmask == 0x7ffff)
base = 0x80000 + (i << 16);
else if (biosmask == 0x3ffff)
base = 0xc0000 + (i << 16);
else
base = 0xe0000 + (i << 16);
fbase = base & biosmask;
if (dev->flags & FLAG_INV_A16)
fbase ^= 0x10000;
memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000);
if ((max == 2) || (i >= 2)) {
mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
}
mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
mem_mapping_add(&(dev->mapping_h[i + max]), (base | 0xfff00000), 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
}
}
static void
intel_flash_reset(void *priv)
{
flash_t *dev = (flash_t *) priv;
dev->command = CMD_READ_ARRAY;
dev->status = 0;
}
static void *
intel_flash_init(const device_t *info)
{
FILE *fp;
flash_t *dev;
uint8_t type = info->local & 0xff;
dev = malloc(sizeof(flash_t));
memset(dev, 0, sizeof(flash_t));
sprintf(flash_path, "%s.bin", machine_get_internal_name_ex(machine));
dev->flags = info->local & 0xff;
mem_mapping_disable(&bios_mapping);
mem_mapping_disable(&bios_high_mapping);
dev->array = (uint8_t *) malloc(biosmask + 1);
memset(dev->array, 0xff, biosmask + 1);
switch (biosmask) {
case 0x7ffff:
if (dev->flags & FLAG_WORD)
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x4471 : 0x4470;
else
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x8A : 0x89;
/* The block lengths are the same both flash types. */
dev->block_len[BLOCK_MAIN1] = 0x20000;
dev->block_len[BLOCK_MAIN2] = 0x20000;
dev->block_len[BLOCK_MAIN3] = 0x20000;
dev->block_len[BLOCK_MAIN4] = 0x18000;
dev->block_len[BLOCK_DATA1] = 0x02000;
dev->block_len[BLOCK_DATA2] = 0x02000;
dev->block_len[BLOCK_BOOT] = 0x04000;
if (dev->flags & FLAG_BXB) { /* 28F004BX-T/28F400BX-B */
dev->block_start[BLOCK_BOOT] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_BOOT] = 0x1ffff;
dev->block_start[BLOCK_DATA2] = 0x20000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_DATA2] = 0x3ffff;
dev->block_start[BLOCK_DATA1] = 0x40000; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_DATA1] = 0x5ffff;
dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0x77fff;
dev->block_start[BLOCK_MAIN3] = 0x78000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_MAIN3] = 0x79fff;
dev->block_start[BLOCK_MAIN2] = 0x7a000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_MAIN2] = 0x7bfff;
dev->block_start[BLOCK_MAIN1] = 0x7c000; /* BOOT BLOCK */
dev->block_end[BLOCK_MAIN1] = 0x7ffff;
} else {
dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1ffff;
dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0x3ffff;
dev->block_start[BLOCK_MAIN3] = 0x40000; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_MAIN3] = 0x5ffff;
dev->block_start[BLOCK_MAIN4] = 0x60000; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0x77fff;
dev->block_start[BLOCK_DATA1] = 0x78000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x79fff;
dev->block_start[BLOCK_DATA2] = 0x7a000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x7bfff;
dev->block_start[BLOCK_BOOT] = 0x7c000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x7ffff;
}
break;
case 0x3ffff:
if (dev->flags & FLAG_WORD)
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274;
else
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x7D : 0x7C;
/* The block lengths are the same both flash types. */
dev->block_len[BLOCK_MAIN1] = 0x20000;
dev->block_len[BLOCK_MAIN2] = 0x18000;
dev->block_len[BLOCK_MAIN3] = 0x00000;
dev->block_len[BLOCK_MAIN4] = 0x00000;
dev->block_len[BLOCK_DATA1] = 0x02000;
dev->block_len[BLOCK_DATA2] = 0x02000;
dev->block_len[BLOCK_BOOT] = 0x04000;
if (dev->flags & FLAG_BXB) { /* 28F002BX-B/28F200BX-B */
dev->block_start[BLOCK_MAIN1] = 0x20000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x3ffff;
dev->block_start[BLOCK_MAIN2] = 0x08000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0x1ffff;
dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_MAIN3] = 0xfffff;
dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x06000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x07fff;
dev->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x05fff;
dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x03fff;
} else { /* 28F002BX-T/28F200BX-T */
dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1ffff;
dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0x37fff;
dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_MAIN3] = 0xfffff;
dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x38000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x39fff;
dev->block_start[BLOCK_DATA2] = 0x3a000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x3bfff;
dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x3ffff;
}
break;
default:
dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94;
/* The block lengths are the same both flash types. */
dev->block_len[BLOCK_MAIN1] = 0x1c000;
dev->block_len[BLOCK_MAIN2] = 0x00000;
dev->block_len[BLOCK_MAIN3] = 0x00000;
dev->block_len[BLOCK_MAIN4] = 0x00000;
dev->block_len[BLOCK_DATA1] = 0x01000;
dev->block_len[BLOCK_DATA2] = 0x01000;
dev->block_len[BLOCK_BOOT] = 0x02000;
if (dev->flags & FLAG_BXB) { /* 28F001BX-B/28F100BX-B */
dev->block_start[BLOCK_MAIN1] = 0x04000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1ffff;
dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0xfffff;
dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_MAIN3] = 0xfffff;
dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x02000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x02fff;
dev->block_start[BLOCK_DATA2] = 0x03000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x03fff;
dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x01fff;
} else { /* 28F001BX-T/28F100BX-T */
dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1bfff;
dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0xfffff;
dev->block_start[BLOCK_MAIN3] = 0xfffff; /* MAIN BLOCK 3 */
dev->block_end[BLOCK_MAIN3] = 0xfffff;
dev->block_start[BLOCK_MAIN4] = 0xfffff; /* MAIN BLOCK 4 */
dev->block_end[BLOCK_MAIN4] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x1cfff;
dev->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x1dfff;
dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x1ffff;
}
break;
}
intel_flash_add_mappings(dev);
dev->command = CMD_READ_ARRAY;
dev->status = 0;
fp = nvr_fopen(flash_path, "rb");
if (fp) {
(void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, fp);
if (dev->block_len[BLOCK_MAIN2])
(void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, fp);
if (dev->block_len[BLOCK_MAIN3])
(void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, fp);
if (dev->block_len[BLOCK_MAIN4])
(void) !fread(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, fp);
(void) !fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, fp);
(void) !fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, fp);
fclose(fp);
}
return dev;
}
static void
intel_flash_close(void *priv)
{
FILE *fp;
flash_t *dev = (flash_t *) priv;
fp = nvr_fopen(flash_path, "wb");
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, fp);
if (dev->block_len[BLOCK_MAIN2])
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, fp);
if (dev->block_len[BLOCK_MAIN3])
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN3]]), dev->block_len[BLOCK_MAIN3], 1, fp);
if (dev->block_len[BLOCK_MAIN4])
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN4]]), dev->block_len[BLOCK_MAIN4], 1, fp);
fwrite(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, fp);
fwrite(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, fp);
fclose(fp);
free(dev->array);
dev->array = NULL;
free(dev);
}
/* For AMI BIOS'es - Intel 28F001BXT with A16 pin inverted. */
const device_t intel_flash_bxt_ami_device = {
.name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS",
.internal_name = "intel_flash_bxt_ami",
.flags = DEVICE_PCI,
.local = FLAG_INV_A16,
.init = intel_flash_init,
.close = intel_flash_close,
.reset = intel_flash_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t intel_flash_bxt_device = {
.name = "Intel 28F001BXT/28F002BXT/28F004BXT Flash BIOS",
.internal_name = "intel_flash_bxt",
.flags = DEVICE_PCI,
.local = 0,
.init = intel_flash_init,
.close = intel_flash_close,
.reset = intel_flash_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t intel_flash_bxb_device = {
.name = "Intel 28F001BXB/28F002BXB/28F004BXB Flash BIOS",
.internal_name = "intel_flash_bxb",
.flags = DEVICE_PCI,
.local = FLAG_BXB,
.init = intel_flash_init,
.close = intel_flash_close,
.reset = intel_flash_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/mem/intel_flash.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,059 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of an SST flash chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Jasmine Iwanek, <jriwanek@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/plat.h>
#include <86box/m_xt_xi8088.h>
typedef struct sst_t {
uint8_t manufacturer;
uint8_t id;
uint8_t has_bbp;
uint8_t is_39;
uint8_t page_bytes;
uint8_t sdp;
uint8_t bbp_first_8k;
uint8_t bbp_last_8k;
int command_state;
int id_mode;
int dirty;
uint32_t size;
uint32_t mask;
uint32_t page_mask;
uint32_t page_base;
uint32_t last_addr;
uint8_t page_buffer[128];
uint8_t page_dirty[128];
uint8_t *array;
mem_mapping_t mapping[8];
mem_mapping_t mapping_h[8];
pc_timer_t page_write_timer;
} sst_t;
static char flash_path[1024];
#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */
#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */
#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */
#define W_BOOT_BLOCK_PROT 0x40 /* Only W29C020 */
#define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */
#define SST_ERASE 0x80 /* Both 29 and 39 */
/* With data 60h on 6th cycle, it's alt. ID */
#define SST_SET_ID_MODE 0x90 /* Both 29 and 39 */
#define SST_BYTE_PROGRAM 0xa0 /* Both 29 and 39 */
#define SST_CLEAR_ID_MODE 0xf0 /* Both 29 and 39 */
/* 1st cycle variant only on 39 */
#define SST 0xbf /* SST Manufacturer's ID */
#define SST29EE512 0x5d00
#define SST29LE_VE512 0x3d00
#define SST29EE010 0x0700
#define SST29LE_VE010 0x0800
#define SST29EE020 0x1000
#define SST29LE_VE020 0x1200
#define SST39SF512 0xb400
#define SST39SF010 0xb500
#define SST39SF020 0xb600
#define SST39SF040 0xb700
#define SST39LF512 0xd400
#define SST39LF010 0xd500
#define SST39LF020 0xd600
#define SST39LF040 0xd700
#define SST39LF080 0xd800
#define SST39LF016 0xd900
#if 0
// 16 wide
#define SST39WF400 0x272f
#define SST39WF400B 0x272e
#define SST39WF800 0x273f
#define SST39WF800B 0x273e
#define SST39WF1601 0xbf274b
#define SST39WF1602 0xbf274a
#define SST39LF100 0x2788
#define SST39LF200 0x2789
#define SST39LF400 0x2780
#define SST39LF800 0x2781
#define SST39LF160 0x2782
#endif
#define SST49LF002 0x5700
#define SST49LF020 0x6100
#define SST49LF020A 0x5200
#define SST49LF003 0x1b00
#define SST49LF004 0x6000
#define SST49LF004C 0x5400
#define SST49LF040 0x5100
#define SST49LF008 0x5a00
#define SST49LF008C 0x5900
#define SST49LF080 0x5b00
#define SST49LF030 0x1c00
#define SST49LF160 0x4c00
#define SST49LF016 0x5c00
#define WINBOND 0xda /* Winbond Manufacturer's ID */
#define W29C512 0xc800
#define W29C010 0xc100
#define W29C020 0x4500
#define W29C040 0x4600
#define AMD 0x01 /* AMD Manufacturer's ID */
#define AMD29F020A 0xb000
#define SIZE_512K 0x010000
#define SIZE_1M 0x020000
#define SIZE_2M 0x040000
#define SIZE_3M 0x060000
#define SIZE_4M 0x080000
#define SIZE_8M 0x100000
#define SIZE_16M 0x200000
static void
sst_sector_erase(sst_t *dev, uint32_t addr)
{
uint32_t base = addr & (dev->mask & ~0xfff);
if (dev->manufacturer == AMD) {
base = addr & biosmask;
if ((base >= 0x00000) && (base <= 0x0ffff))
memset(&dev->array[0x00000], 0xff, 65536);
else if ((base >= 0x10000) && (base <= 0x1ffff))
memset(&dev->array[0x10000], 0xff, 65536);
else if ((base >= 0x20000) && (base <= 0x2ffff))
memset(&dev->array[0x20000], 0xff, 65536);
else if ((base >= 0x30000) && (base <= 0x37fff))
memset(&dev->array[0x30000], 0xff, 32768);
else if ((base >= 0x38000) && (base <= 0x39fff))
memset(&dev->array[0x38000], 0xff, 8192);
else if ((base >= 0x3a000) && (base <= 0x3bfff))
memset(&dev->array[0x3a000], 0xff, 8192);
else if ((base >= 0x3c000) && (base <= 0x3ffff))
memset(&dev->array[0x3c000], 0xff, 16384);
} else {
if ((base < 0x2000) && (dev->bbp_first_8k & 0x01))
return;
else if ((base >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01))
return;
memset(&dev->array[base], 0xff, 4096);
}
dev->dirty = 1;
}
static void
sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
{
uint32_t base = 0x00000;
uint32_t size = dev->size;
if (dev->command_state == 5)
switch (val) {
case SST_CHIP_ERASE:
if (dev->bbp_first_8k & 0x01) {
base += 0x2000;
size -= 0x2000;
}
if (dev->bbp_last_8k & 0x01)
size -= 0x2000;
memset(&(dev->array[base]), 0xff, size);
dev->command_state = 0;
break;
case SST_SDP_DISABLE:
if (!dev->is_39)
dev->sdp = 0;
dev->command_state = 0;
break;
case SST_SECTOR_ERASE:
if (dev->is_39)
sst_sector_erase(dev, addr);
dev->command_state = 0;
break;
case SST_SET_ID_MODE_ALT:
dev->id_mode = 1;
dev->command_state = 0;
break;
default:
dev->command_state = 0;
break;
}
else
switch (val) {
case SST_ERASE:
dev->command_state = 3;
break;
case SST_SET_ID_MODE:
dev->id_mode = 1;
dev->command_state = 0;
break;
case SST_BYTE_PROGRAM:
if (!dev->is_39) {
dev->sdp = 1;
memset(dev->page_buffer, 0xff, 128);
memset(dev->page_dirty, 0x00, 128);
dev->page_bytes = 0;
dev->last_addr = 0xffffffff;
timer_on_auto(&dev->page_write_timer, 210.0);
}
dev->command_state = 6;
break;
case W_BOOT_BLOCK_PROT:
dev->command_state = dev->has_bbp ? 8 : 0;
break;
case SST_CLEAR_ID_MODE:
dev->id_mode = 0;
dev->command_state = 0;
break;
default:
dev->command_state = 0;
break;
}
}
static void
sst_page_write(void *priv)
{
sst_t *dev = (sst_t *) priv;
if (dev->last_addr != 0xffffffff) {
dev->page_base = dev->last_addr & dev->page_mask;
for (uint8_t i = 0; i < 128; i++) {
if (dev->page_dirty[i]) {
if (((dev->page_base + i) < 0x2000) && (dev->bbp_first_8k & 0x01))
continue;
else if (((dev->page_base + i) >= (dev->size - 0x2000)) && (dev->bbp_last_8k & 0x01))
continue;
dev->array[dev->page_base + i] = dev->page_buffer[i];
dev->dirty |= 1;
}
}
}
dev->page_bytes = 0;
dev->command_state = 0;
timer_disable(&dev->page_write_timer);
}
static uint8_t
sst_read_id(uint32_t addr, void *priv)
{
const sst_t *dev = (sst_t *) priv;
uint8_t ret = 0x00;
uint32_t mask = 0xffff;
if (dev->manufacturer == AMD)
mask >>= 8;
if ((addr & mask) == 0)
ret = dev->manufacturer;
else if ((addr & mask) == 1)
ret = dev->id;
#ifdef UNKNOWN_FLASH
else if ((addr & 0xffff) == 0x100)
ret = 0x1c;
else if ((addr & 0xffff) == 0x101)
ret = 0x92;
#endif
else if (dev->has_bbp) {
if (addr == 0x00002)
ret = dev->bbp_first_8k;
else if (addr == 0x3fff2)
ret = dev->bbp_last_8k;
} else if (dev->manufacturer == AMD) {
if ((addr & mask) == 2)
ret = 0x00;
}
return ret;
}
static void
sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val)
{
dev->page_buffer[addr & 0x0000007f] = val;
dev->page_dirty[addr & 0x0000007f] = 1;
dev->page_bytes++;
dev->last_addr = addr;
if (dev->page_bytes >= 128) {
sst_page_write(dev);
} else
timer_on_auto(&dev->page_write_timer, 210.0);
}
static void
sst_write(uint32_t addr, uint8_t val, void *priv)
{
sst_t *dev = (sst_t *) priv;
uint32_t mask = 0x7fff;
uint32_t addr0 = 0x5555;
uint32_t addr1 = 0x2aaa;
if (dev->manufacturer == AMD) {
mask >>= 4;
addr0 >>= 4;
addr1 >>= 4;
}
switch (dev->command_state) {
case 0:
case 3:
/* 1st and 4th Bus Write Cycle */
if ((val == 0xf0) && dev->is_39 && (dev->command_state == 0)) {
if (dev->id_mode)
dev->id_mode = 0;
dev->command_state = 0;
} else if (((addr & mask) == addr0) && (val == 0xaa))
dev->command_state++;
else {
if (!dev->is_39 && !dev->sdp && (dev->command_state == 0)) {
/* 29 series, software data protection off, start loading the page. */
memset(dev->page_buffer, 0xff, 128);
memset(dev->page_dirty, 0x00, 128);
dev->page_bytes = 0;
dev->command_state = 7;
sst_buf_write(dev, addr, val);
} else
dev->command_state = 0;
}
break;
case 1:
case 4:
/* 2nd and 5th Bus Write Cycle */
if (((addr & mask) == addr1) && (val == 0x55))
dev->command_state++;
else
dev->command_state = 0;
break;
case 2:
case 5:
/* 3rd and 6th Bus Write Cycle */
if ((dev->command_state == 5) && (val == SST_SECTOR_ERASE)) {
/* Sector erase - can be on any address. */
sst_new_command(dev, addr, val);
} else if ((addr & mask) == addr0)
sst_new_command(dev, addr, val);
else
dev->command_state = 0;
break;
case 6:
/* Page Load Cycle (29) / Data Write Cycle (39SF) */
if (dev->is_39) {
dev->command_state = 0;
dev->array[addr & dev->mask] = val;
dev->dirty = 1;
} else {
dev->command_state++;
sst_buf_write(dev, addr, val);
}
break;
case 7:
if (!dev->is_39)
sst_buf_write(dev, addr, val);
break;
case 8:
if ((addr == 0x00000) && (val == 0x00))
dev->bbp_first_8k = 0xff;
else if ((addr == 0x3ffff) && (val == 0xff))
dev->bbp_last_8k = 0xff;
dev->command_state = 0;
break;
default:
break;
}
}
static uint8_t
sst_read(uint32_t addr, void *priv)
{
const sst_t *dev = (sst_t *) priv;
uint8_t ret = 0xff;
addr &= 0x000fffff;
if (dev->id_mode)
ret = sst_read_id(addr, priv);
else {
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = dev->array[addr - biosaddr];
}
return ret;
}
static uint16_t
sst_readw(uint32_t addr, void *priv)
{
sst_t *dev = (sst_t *) priv;
uint16_t ret = 0xffff;
addr &= 0x000fffff;
if (dev->id_mode)
ret = sst_read(addr, priv) | (sst_read(addr + 1, priv) << 8);
else {
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint16_t *) &dev->array[addr - biosaddr];
}
return ret;
}
static uint32_t
sst_readl(uint32_t addr, void *priv)
{
sst_t *dev = (sst_t *) priv;
uint32_t ret = 0xffffffff;
addr &= 0x000fffff;
if (dev->id_mode)
ret = sst_readw(addr, priv) | (sst_readw(addr + 2, priv) << 16);
else {
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint32_t *) &dev->array[addr - biosaddr];
}
return ret;
}
static void
sst_add_mappings(sst_t *dev)
{
int count;
uint32_t base;
uint32_t fbase;
uint32_t root_base;
count = dev->size >> 16;
root_base = 0x100000 - dev->size;
for (int i = 0; i < count; i++) {
base = root_base + (i << 16);
fbase = base & biosmask;
memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000);
if (base >= 0xe0000) {
mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
}
if (is6117) {
mem_mapping_add(&(dev->mapping_h[i]), (base | 0x3f00000), 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
} else {
mem_mapping_add(&(dev->mapping_h[i]), (base | (cpu_16bitbus ? 0xf00000 : 0xfff00000)), 0x10000,
sst_read, sst_readw, sst_readl,
sst_write, NULL, NULL,
dev->array + fbase, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
}
}
}
static void *
sst_init(const device_t *info)
{
FILE *fp;
sst_t *dev = malloc(sizeof(sst_t));
memset(dev, 0, sizeof(sst_t));
sprintf(flash_path, "%s.bin", machine_get_internal_name_ex(machine));
mem_mapping_disable(&bios_mapping);
mem_mapping_disable(&bios_high_mapping);
dev->array = (uint8_t *) malloc(biosmask + 1);
memset(dev->array, 0xff, biosmask + 1);
dev->manufacturer = info->local & 0xff;
dev->id = (info->local >> 8) & 0xff;
dev->has_bbp = (dev->manufacturer == WINBOND) && ((info->local & 0xff00) >= W29C020);
dev->is_39 = (dev->manufacturer == SST) && ((info->local & 0xff00) >= SST39SF512);
if (dev->manufacturer == AMD)
dev->is_39 = 1;
dev->size = info->local & 0xffff0000;
if ((dev->size == 0x20000) && (strstr(machine_get_internal_name_ex(machine), "xi8088")) && !xi8088_bios_128kb())
dev->size = 0x10000;
dev->mask = dev->size - 1;
dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */
dev->sdp = 1;
dev->bbp_first_8k = dev->bbp_last_8k = 0xfe;
sst_add_mappings(dev);
fp = nvr_fopen(flash_path, "rb");
if (fp) {
if (fread(&(dev->array[0x00000]), 1, dev->size, fp) != dev->size)
pclog("Less than %i bytes read from the SST Flash ROM file\n", dev->size);
fclose(fp);
} else
dev->dirty = 1; /* It is by definition dirty on creation. */
if (!dev->is_39)
timer_add(&dev->page_write_timer, sst_page_write, dev, 0);
return dev;
}
static void
sst_close(void *priv)
{
FILE *fp;
sst_t *dev = (sst_t *) priv;
if (dev->dirty) {
fp = nvr_fopen(flash_path, "wb");
if (fp != NULL) {
fwrite(&(dev->array[0x00000]), dev->size, 1, fp);
fclose(fp);
}
}
free(dev->array);
dev->array = NULL;
free(dev);
}
const device_t sst_flash_29ee010_device = {
.name = "SST 29EE010 Flash BIOS",
.internal_name = "sst_flash_29ee010",
.flags = 0,
.local = SST | SST29EE010 | SIZE_1M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_29ee020_device = {
.name = "SST 29EE020 Flash BIOS",
.internal_name = "sst_flash_29ee020",
.flags = 0,
.local = SST | SST29EE020 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t winbond_flash_w29c512_device = {
.name = "Winbond W29C512 Flash BIOS",
.internal_name = "winbond_flash_w29c512",
.flags = 0,
.local = WINBOND | W29C010 | SIZE_512K,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t winbond_flash_w29c010_device = {
.name = "Winbond W29C010 Flash BIOS",
.internal_name = "winbond_flash_w29c010",
.flags = 0,
.local = WINBOND | W29C010 | SIZE_1M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t winbond_flash_w29c020_device = {
.name = "Winbond W29C020 Flash BIOS",
.internal_name = "winbond_flash_w29c020",
.flags = 0,
.local = WINBOND | W29C020 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t winbond_flash_w29c040_device = {
.name = "Winbond W29C040 Flash BIOS",
.internal_name = "winbond_flash_w29c040",
.flags = 0,
.local = WINBOND | W29C040 | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39sf512_device = {
.name = "SST 39SF512 Flash BIOS",
.internal_name = "sst_flash_39sf512",
.flags = 0,
.local = SST | SST39SF512 | SIZE_512K,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39sf010_device = {
.name = "SST 39SF010 Flash BIOS",
.internal_name = "sst_flash_39sf010",
.flags = 0,
.local = SST | SST39SF010 | SIZE_1M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39sf020_device = {
.name = "SST 39SF020 Flash BIOS",
.internal_name = "sst_flash_39sf020",
.flags = 0,
.local = SST | SST39SF020 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39sf040_device = {
.name = "SST 39SF040 Flash BIOS",
.internal_name = "sst_flash_39sf040",
.flags = 0,
.local = SST | SST39SF040 | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf512_device = {
.name = "SST 39LF512 Flash BIOS",
.internal_name = "sst_flash_39lf512",
.flags = 0,
.local = SST | SST39LF512 | SIZE_512K,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf010_device = {
.name = "SST 39LF010 Flash BIOS",
.internal_name = "sst_flash_39lf010",
.flags = 0,
.local = SST | SST39LF010 | SIZE_1M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf020_device = {
.name = "SST 39LF020 Flash BIOS",
.internal_name = "sst_flash_39lf020",
.flags = 0,
.local = SST | SST39LF020 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf040_device = {
.name = "SST 39LF040 Flash BIOS",
.internal_name = "sst_flash_39lf040",
.flags = 0,
.local = SST | SST39LF040 | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf080_device = {
.name = "SST 39LF080 Flash BIOS",
.internal_name = "sst_flash_39lf080",
.flags = 0,
.local = SST | SST39LF080 | SIZE_8M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_39lf016_device = {
.name = "SST 39LF016 Flash BIOS",
.internal_name = "sst_flash_39lf016",
.flags = 0,
.local = SST | SST39LF016 | SIZE_16M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
/*
* Firmware Hubs. The FWH signals are not implemented yet. Firmware Hubs do write cycles
* to read/write on the flash. SST Flashes still do traditional flashing via PP Mode. Our
* BIOS firmwares don't seem to utilize FWH R/W thus the FWH ports remain unknown for an
* implementation. We just contain the ID's so the BIOS can do ESCD & DMI writes with no
* worries.
*/
const device_t sst_flash_49lf002_device = {
.name = "SST 49LF002 Firmware Hub",
.internal_name = "sst_flash_49lf002",
.flags = 0,
.local = SST | SST49LF002 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf020_device = {
.name = "SST 49LF020 Firmware Hub",
.internal_name = "sst_flash_49lf0020",
.flags = 0,
.local = SST | SST49LF020 | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf020a_device = {
.name = "SST 49LF020A Firmware Hub",
.internal_name = "sst_flash_49lf0020a",
.flags = 0,
.local = SST | SST49LF020A | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf003_device = {
.name = "SST 49LF003 Firmware Hub",
.internal_name = "sst_flash_49lf003",
.flags = 0,
.local = SST | SST49LF003 | SIZE_3M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf030_device = {
.name = "SST 49LF030 Firmware Hub",
.internal_name = "sst_flash_49lf030",
.flags = 0,
.local = SST | SST49LF030 | SIZE_3M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf004_device = {
.name = "SST 49LF004 Firmware Hub",
.internal_name = "sst_flash_49lf004",
.flags = 0,
.local = SST | SST49LF004 | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf004c_device = {
.name = "SST 49LF004C Firmware Hub",
.internal_name = "sst_flash_49lf004c",
.flags = 0,
.local = SST | SST49LF004C | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf040_device = {
.name = "SST 49LF040 Firmware Hub",
.internal_name = "sst_flash_49lf040",
.flags = 0,
.local = SST | SST49LF040 | SIZE_4M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf008_device = {
.name = "SST 49LF008 Firmware Hub",
.internal_name = "sst_flash_49lf008",
.flags = 0,
.local = SST | SST49LF008 | SIZE_8M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf008c_device = {
.name = "SST 49LF008C Firmware Hub",
.internal_name = "sst_flash_49lf008c",
.flags = 0,
.local = SST | SST49LF008C | SIZE_8M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf080_device = {
.name = "SST 49LF080 Firmware Hub",
.internal_name = "sst_flash_49lf080",
.flags = 0,
.local = SST | SST49LF080 | SIZE_8M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf016_device = {
.name = "SST 49LF016 Firmware Hub",
.internal_name = "sst_flash_49lf016",
.flags = 0,
.local = SST | SST49LF016 | SIZE_16M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sst_flash_49lf160_device = {
.name = "SST 49LF160 Firmware Hub",
.internal_name = "sst_flash_49lf160",
.flags = 0,
.local = SST | SST49LF160 | SIZE_16M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t amd_flash_29f020a_device = {
.name = "AMD 29F020a Flash BIOS",
.internal_name = "amd_flash_29f020a",
.flags = 0,
.local = AMD | AMD29F020A | SIZE_2M,
.init = sst_init,
.close = sst_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/mem/sst_flash.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,722 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Memory handling and MMU.
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/version.h>
#include "cpu.h"
#include "x86_ops.h"
#include "x86.h"
#include "x86seg_common.h"
#include <86box/machine.h>
#include <86box/m_xt_xi8088.h>
#include <86box/config.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/plat.h>
#include <86box/rom.h>
#include <86box/gdbstub.h>
/* As below, 1 = exec, 4 = read. */
int read_type = 4;
/* Set trap for data address breakpoints - 1 = exec, 2 = write, 4 = read. */
void
mem_debug_check_addr(uint32_t addr, int flags)
{
uint32_t bp_addr;
uint32_t bp_mask;
uint32_t len_type_pair;
int bp_enabled;
uint8_t match_flags[4] = { 0, 2, 0, 6 };
if (cpu_state.abrt || ((flags == 1) && (cpu_state.eflags & RF_FLAG)))
return;
if (dr[7] & 0x000000ff) for (uint8_t i = 0; i < 4; i++) {
bp_addr = dr[i];
bp_enabled = (dr[7] >> (i << 1)) & 0x03;
len_type_pair = (dr[7] >> (16 + (i << 2))) & 0x0f;
bp_mask = ~((len_type_pair >> 2) & 0x03);
if ((flags & match_flags[len_type_pair & 0x03]) && ((bp_addr & bp_mask) == (addr & bp_mask))) {
/*
From the Intel i386 documemntation:
(Note that the processor sets Bn regardless of whether Gn or
Ln is set. If more than one breakpoint condition occurs at one time and if
the breakpoint trap occurs due to an enabled condition other than n, Bn may
be set, even though neither Gn nor Ln is set.)
*/
dr[6] |= (1 << i);
if (bp_enabled)
trap |= (read_type == 1) ? 8 : 4;
}
}
}
uint8_t
mem_readb_map(uint32_t addr)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
uint8_t ret = 0xff;
mem_logical_addr = 0xffffffff;
if (map && map->read_b)
ret = map->read_b(addr, map->priv);
return ret;
}
uint16_t
mem_readw_map(uint32_t addr)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
uint16_t ret;
mem_logical_addr = 0xffffffff;
if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->read_w))
ret = map->read_w(addr, map->priv);
else {
ret = mem_readb_phys(addr + 1) << 8;
ret |= mem_readb_phys(addr);
}
return ret;
}
uint32_t
mem_readl_map(uint32_t addr)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
uint32_t ret;
mem_logical_addr = 0xffffffff;
if (!cpu_16bitbus && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->read_l))
ret = map->read_l(addr, map->priv);
else {
ret = mem_readw_phys(addr + 2) << 16;
ret |= mem_readw_phys(addr);
}
return ret;
}
void
mem_writeb_map(uint32_t addr, uint8_t val)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
mem_logical_addr = 0xffffffff;
if (map && map->write_b)
map->write_b(addr, val, map->priv);
}
void
mem_writew_map(uint32_t addr, uint16_t val)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
mem_logical_addr = 0xffffffff;
if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->write_w))
map->write_w(addr, val, map->priv);
else {
mem_writeb_phys(addr, val & 0xff);
mem_writeb_phys(addr + 1, val >> 8);
}
}
void
mem_writel_map(uint32_t addr, uint32_t val)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
mem_logical_addr = 0xffffffff;
if (!cpu_16bitbus && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->write_l))
map->write_l(addr, val, map->priv);
else {
mem_writew_phys(addr, val & 0xffff);
mem_writew_phys(addr + 2, val >> 16);
}
}
#define mmutranslate_read_2386(addr) mmutranslatereal_2386(addr,0)
#define mmutranslate_write_2386(addr) mmutranslatereal_2386(addr,1)
uint64_t
mmutranslatereal_2386(uint32_t addr, int rw)
{
uint32_t temp;
uint32_t temp2;
uint32_t temp3;
uint32_t addr2;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = mem_readl_map(addr2);
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
/*4MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || ((is486 || isibm486) && (cr0 & WP_FLAG))))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
mem_writel_map(addr2, mem_readl_map(addr2) | (rw ? 0x60 : 0x20));
return (temp & ~0x3fffff) + (addr & 0x3fffff);
}
temp = mem_readl_map((temp & ~0xfff) + ((addr >> 10) & 0xffc));
temp3 = temp & temp2;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || ((is486 || isibm486) && (cr0 & WP_FLAG))))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
mem_writel_map(addr2, mem_readl_map(addr2) | 0x20);
mem_writel_map((temp2 & ~0xfff) + ((addr >> 10) & 0xffc),
mem_readl_map((temp2 & ~0xfff) + ((addr >> 10) & 0xffc)) | (rw ? 0x60 : 0x20));
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
uint64_t
mmutranslate_noabrt_2386(uint32_t addr, int rw)
{
uint32_t temp;
uint32_t temp2;
uint32_t temp3;
uint32_t addr2;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = mem_readl_map(addr2);
if (!(temp & 1))
return 0xffffffffffffffffULL;
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
/*4MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return (temp & ~0x3fffff) + (addr & 0x3fffff);
}
temp = mem_readl_map((temp & ~0xfff) + ((addr >> 10) & 0xffc));
temp3 = temp & temp2;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
uint8_t
readmembl_2386(uint32_t addr)
{
mem_mapping_t *map;
uint64_t a;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 1);
mem_debug_check_addr(addr, read_type);
addr64 = (uint64_t) addr;
mem_logical_addr = addr;
high_page = 0;
if (cr0 >> 31) {
a = mmutranslate_read_2386(addr);
addr64 = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xff;
}
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->priv);
return 0xff;
}
void
writemembl_2386(uint32_t addr, uint8_t val)
{
mem_mapping_t *map;
uint64_t a;
mem_debug_check_addr(addr, 2);
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 1);
addr64 = (uint64_t) addr;
mem_logical_addr = addr;
high_page = 0;
if (cr0 >> 31) {
a = mmutranslate_write_2386(addr);
addr64 = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->priv);
}
/* Read a byte from memory without MMU translation - result of previous MMU translation passed as value. */
uint8_t
readmembl_no_mmut_2386(uint32_t addr, uint32_t a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 1);
mem_logical_addr = addr;
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xff;
addr = a64 & rammask;
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->priv);
return 0xff;
}
/* Write a byte to memory without MMU translation - result of previous MMU translation passed as value. */
void
writemembl_no_mmut_2386(uint32_t addr, uint32_t a64, uint8_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 1);
mem_logical_addr = addr;
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = a64 & rammask;
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->priv);
}
uint16_t
readmemwl_2386(uint32_t addr)
{
mem_mapping_t *map;
uint64_t a;
addr64a[0] = addr;
addr64a[1] = addr + 1;
mem_debug_check_addr(addr, read_type);
mem_debug_check_addr(addr + 1, read_type);
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 2);
mem_logical_addr = addr;
high_page = 0;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
for (uint8_t i = 0; i < 2; i++) {
a = mmutranslate_read_2386(addr + i);
addr64a[i] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffff;
}
}
return readmembl_no_mmut_2386(addr, addr64a[0]) |
(((uint16_t) readmembl_no_mmut_2386(addr + 1, addr64a[1])) << 8);
}
}
if (cr0 >> 31) {
a = mmutranslate_read_2386(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffff;
} else
addr64a[0] = (uint64_t) addr;
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
return map->read_w(addr, map->priv);
if (map && map->read_b) {
return map->read_b(addr, map->priv) | ((uint16_t) (map->read_b(addr + 1, map->priv)) << 8);
}
return 0xffff;
}
void
writememwl_2386(uint32_t addr, uint16_t val)
{
mem_mapping_t *map;
uint64_t a;
addr64a[0] = addr;
addr64a[1] = addr + 1;
mem_debug_check_addr(addr, 2);
mem_debug_check_addr(addr + 1, 2);
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 2);
mem_logical_addr = addr;
high_page = 0;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
for (uint8_t i = 0; i < 2; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
a = mmutranslate_write_2386(addr + i);
addr64a[i] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writemembl_no_mmut_2386(addr, addr64a[0], val);
writemembl_no_mmut_2386(addr + 1, addr64a[1], val >> 8);
return;
}
}
if (cr0 >> 31) {
a = mmutranslate_write_2386(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
return;
}
}
/* Read a word from memory without MMU translation - results of previous MMU translation passed as array. */
uint16_t
readmemwl_no_mmut_2386(uint32_t addr, uint32_t *a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 2);
mem_logical_addr = addr;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffff;
}
return readmembl_no_mmut_2386(addr, a64[0]) |
(((uint16_t) readmembl_no_mmut_2386(addr + 1, a64[1])) << 8);
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffff;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
return map->read_w(addr, map->priv);
if (map && map->read_b) {
return map->read_b(addr, map->priv) | ((uint16_t) (map->read_b(addr + 1, map->priv)) << 8);
}
return 0xffff;
}
/* Write a word to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememwl_no_mmut_2386(uint32_t addr, uint32_t *a64, uint16_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 2);
mem_logical_addr = addr;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
}
writemembl_no_mmut_2386(addr, a64[0], val);
writemembl_no_mmut_2386(addr + 1, a64[1], val >> 8);
return;
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
return;
}
}
uint32_t
readmemll_2386(uint32_t addr)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 4; i++) {
addr64a[i] = (uint64_t) (addr + i);
mem_debug_check_addr(addr + i, read_type);
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 4);
mem_logical_addr = addr;
high_page = 0;
if (cpu_16bitbus || (addr & 3)) {
if ((addr & 3) && (!cpu_cyrix_alignment || (addr & 7) > 4))
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
for (i = 0; i < 4; i++) {
if (i == 0) {
a = mmutranslate_read_2386(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_read_2386(addr + 3);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return 0xffff;
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemwl_no_mmut_2386(addr, addr64a) |
(((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16);
}
}
if (cr0 >> 31) {
a = mmutranslate_read_2386(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffffffff;
}
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv);
if (map && map->read_w)
return map->read_w(addr, map->priv) | ((uint32_t) (map->read_w(addr + 2, map->priv)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->priv) | ((uint32_t) (map->read_b(addr + 1, map->priv)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->priv)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->priv)) << 24);
return 0xffffffff;
}
void
writememll_2386(uint32_t addr, uint32_t val)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 4; i++) {
addr64a[i] = (uint64_t) (addr + i);
mem_debug_check_addr(addr + i, 2);
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 4);
mem_logical_addr = addr;
high_page = 0;
if (cpu_16bitbus || (addr & 3)) {
if ((addr & 3) && (!cpu_cyrix_alignment || (addr & 7) > 4))
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
for (i = 0; i < 4; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
if (i == 0) {
a = mmutranslate_write_2386(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_write_2386(addr + 3);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writememwl_no_mmut_2386(addr, &(addr64a[0]), val);
writememwl_no_mmut_2386(addr + 2, &(addr64a[2]), val >> 16);
return;
}
}
if (cr0 >> 31) {
a = mmutranslate_write_2386(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
return;
}
}
/* Read a long from memory without MMU translation - results of previous MMU translation passed as array. */
uint32_t
readmemll_no_mmut_2386(uint32_t addr, uint32_t *a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 4);
mem_logical_addr = addr;
if (cpu_16bitbus || (addr & 3)) {
if ((addr & 3) && (!cpu_cyrix_alignment || (addr & 7) > 4))
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffffffff;
}
return readmemwl_no_mmut_2386(addr, a64) |
((uint32_t) (readmemwl_no_mmut_2386(addr + 2, &(a64[2]))) << 16);
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffffffff;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv);
if (map && map->read_w)
return map->read_w(addr, map->priv) | ((uint32_t) (map->read_w(addr + 2, map->priv)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->priv) | ((uint32_t) (map->read_b(addr + 1, map->priv)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->priv)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->priv)) << 24);
return 0xffffffff;
}
/* Write a long to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememll_no_mmut_2386(uint32_t addr, uint32_t *a64, uint32_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 4);
mem_logical_addr = addr;
if (cpu_16bitbus || (addr & 3)) {
if ((addr & 3) && (!cpu_cyrix_alignment || (addr & 7) > 4))
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
}
writememwl_no_mmut_2386(addr, &(a64[0]), val);
writememwl_no_mmut_2386(addr + 2, &(a64[2]), val >> 16);
return;
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
return;
}
}
uint64_t
readmemql_2386(uint32_t addr)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 8; i++) {
addr64a[i] = (uint64_t) (addr + i);
mem_debug_check_addr(addr + i, read_type);
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 8);
mem_logical_addr = addr;
high_page = 0;
if (addr & 7) {
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xff8) {
if (cr0 >> 31) {
for (i = 0; i < 8; i++) {
if (i == 0) {
a = mmutranslate_read_2386(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_read_2386(addr + 7);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return 0xffff;
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemll_no_mmut_2386(addr, addr64a) |
(((uint64_t) readmemll_no_mmut_2386(addr + 4, &(addr64a[4]))) << 32);
}
}
if (cr0 >> 31) {
a = mmutranslate_read_2386(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffffffffffffffffULL;
}
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv) | ((uint64_t) map->read_l(addr + 4, map->priv) << 32);
return readmemll(addr) | ((uint64_t) readmemll(addr + 4) << 32);
}
void
writememql_2386(uint32_t addr, uint64_t val)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 8; i++) {
addr64a[i] = (uint64_t) (addr + i);
mem_debug_check_addr(addr + i, 2);
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 8);
mem_logical_addr = addr;
high_page = 0;
if (addr & 7) {
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xff8) {
if (cr0 >> 31) {
for (i = 0; i < 8; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
if (i == 0) {
a = mmutranslate_write_2386(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_write_2386(addr + 7);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (addr64a[i] > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writememll_no_mmut_2386(addr, addr64a, val);
writememll_no_mmut_2386(addr + 4, &(addr64a[4]), val >> 32);
return;
}
}
if (cr0 >> 31) {
addr64a[0] = mmutranslate_write_2386(addr);
if (addr64a[0] > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
map->write_l(addr + 4, val >> 32, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
map->write_w(addr + 4, val >> 32, map->priv);
map->write_w(addr + 6, val >> 48, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
map->write_b(addr + 4, val >> 32, map->priv);
map->write_b(addr + 5, val >> 40, map->priv);
map->write_b(addr + 6, val >> 48, map->priv);
map->write_b(addr + 7, val >> 56, map->priv);
return;
}
}
void
do_mmutranslate_2386(uint32_t addr, uint32_t *a64, int num, int write)
{
int i;
uint32_t last_addr = addr + (num - 1);
uint64_t a = 0x0000000000000000ULL;
mem_debug_check_addr(addr, write ? 2 : read_type);
for (i = 0; i < num; i++)
a64[i] = (uint64_t) addr;
if (!(cr0 >> 31))
return;
for (i = 0; i < num; i++) {
/* If we have encountered at least one page fault, mark all subsequent addresses as
having page faulted, prevents false negatives in readmem*l_no_mmut. */
if ((i > 0) && cpu_state.abrt && !high_page)
a64[i] = a64[i - 1];
/* If we are on the same page, there is no need to translate again, as we can just
reuse the previous result. */
else if (i == 0) {
a = mmutranslatereal_2386(addr, write);
a64[i] = (uint32_t) a;
} else if (!(addr & 0xfff)) {
a = mmutranslatereal_2386(last_addr, write);
a64[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff));
a64[i] = (uint32_t) a;
}
} else {
a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff));
a64[i] = (uint32_t) a;
}
addr++;
}
}
``` | /content/code_sandbox/src/mem/mmu_2386.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,472 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* SMRAM handling.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86_ops.h"
#include "x86.h"
#include <86box/config.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/smram.h>
static smram_t *base_smram;
static smram_t *last_smram;
static uint8_t use_separate_smram = 0;
static uint8_t smram[0x40000];
#ifdef ENABLE_SMRAM_LOG
int smram_do_log = ENABLE_SMRAM_LOG;
static void
smram_log(const char *fmt, ...)
{
va_list ap;
if (smram_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define smram_log(fmt, ...)
#endif
static uint8_t
smram_read(uint32_t addr, void *priv)
{
const smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gb(new_addr, priv);
else if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_ram(new_addr, priv);
else
return dev->mapping.exec[addr - dev->host_base];
}
static uint16_t
smram_readw(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbw(new_addr, priv);
else if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_ramw(new_addr, priv);
else
return *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]);
}
static uint32_t
smram_readl(uint32_t addr, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (new_addr >= (1 << 30))
return mem_read_ram_2gbl(new_addr, priv);
else if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_raml(new_addr, priv);
else
return *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]);
}
static void
smram_write(uint32_t addr, uint8_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (!use_separate_smram || (new_addr >= 0xa0000))
mem_write_ram(new_addr, val, priv);
else
dev->mapping.exec[addr - dev->host_base] = val;
}
static void
smram_writew(uint32_t addr, uint16_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (!use_separate_smram || (new_addr >= 0xa0000))
mem_write_ramw(new_addr, val, priv);
else
*(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]) = val;
}
static void
smram_writel(uint32_t addr, uint32_t val, void *priv)
{
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
if (!use_separate_smram || (new_addr >= 0xa0000))
mem_write_raml(new_addr, val, priv);
else
*(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]) = val;
}
/* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if
the SMRAM mappings change while in SMM, they will be recalculated on return. */
void
smram_backup_all(void)
{
smram_t *temp_smram = base_smram;
smram_t *next;
while (temp_smram != NULL) {
temp_smram->old_host_base = temp_smram->host_base;
temp_smram->old_size = temp_smram->size;
next = temp_smram->next;
temp_smram = next;
}
}
/* Recalculate any mappings, including the backup if returning from SMM. */
void
smram_recalc_all(int ret)
{
smram_t *temp_smram = base_smram;
smram_t *next;
if (base_smram == NULL)
return;
if (ret) {
while (temp_smram != NULL) {
if (temp_smram->old_size != 0x00000000)
mem_mapping_recalc(temp_smram->old_host_base, temp_smram->old_size);
temp_smram->old_host_base = temp_smram->old_size = 0x00000000;
next = temp_smram->next;
temp_smram = next;
}
}
temp_smram = base_smram;
while (temp_smram != NULL) {
if (temp_smram->size != 0x00000000)
mem_mapping_recalc(temp_smram->host_base, temp_smram->size);
next = temp_smram->next;
temp_smram = next;
}
flushmmucache();
}
/* Delete a SMRAM mapping. */
void
smram_del(smram_t *smr)
{
/* Do a sanity check */
if ((base_smram == NULL) && (last_smram != NULL)) {
fatal("smram_del(): NULL base SMRAM with non-NULL last SMRAM\n");
return;
} else if ((base_smram != NULL) && (last_smram == NULL)) {
fatal("smram_del(): Non-NULL base SMRAM with NULL last SMRAM\n");
return;
} else if ((base_smram != NULL) && (base_smram->prev != NULL)) {
fatal("smram_del(): Base SMRAM with a preceding SMRAM\n");
return;
} else if ((last_smram != NULL) && (last_smram->next != NULL)) {
fatal("smram_del(): Last SMRAM with a following SMRAM\n");
return;
}
if (smr == NULL) {
fatal("smram_del(): Invalid SMRAM mapping\n");
return;
}
/* Disable the entry. */
smram_disable(smr);
/* Zap it from the list. */
if (smr->prev != NULL)
smr->prev->next = smr->next;
if (smr->next != NULL)
smr->next->prev = smr->prev;
/* Check if it's the first or the last mapping. */
if (base_smram == smr)
base_smram = smr->next;
if (last_smram == smr)
last_smram = smr->prev;
free(smr);
}
/* Add a SMRAM mapping. */
smram_t *
smram_add(void)
{
smram_t *temp_smram;
/* Do a sanity check */
if ((base_smram == NULL) && (last_smram != NULL)) {
fatal("smram_add(): NULL base SMRAM with non-NULL last SMRAM\n");
return NULL;
} else if ((base_smram != NULL) && (last_smram == NULL)) {
fatal("smram_add(): Non-NULL base SMRAM with NULL last SMRAM\n");
return NULL;
} else if ((base_smram != NULL) && (base_smram->prev != NULL)) {
fatal("smram_add(): Base SMRAM with a preceding SMRAM\n");
return NULL;
} else if ((last_smram != NULL) && (last_smram->next != NULL)) {
fatal("smram_add(): Last SMRAM with a following SMRAM\n");
return NULL;
}
temp_smram = (smram_t *) malloc(sizeof(smram_t));
if (temp_smram == NULL) {
fatal("smram_add(): temp_smram malloc failed\n");
return NULL;
}
memset(temp_smram, 0x00, sizeof(smram_t));
memset(&(temp_smram->mapping), 0x00, sizeof(mem_mapping_t));
/* Add struct to the beginning of the list if necessary.*/
if (base_smram == NULL)
base_smram = temp_smram;
/* Add struct to the end of the list.*/
if (last_smram == NULL)
temp_smram->prev = NULL;
else {
temp_smram->prev = last_smram;
last_smram->next = temp_smram;
}
last_smram = temp_smram;
mem_mapping_add(&(temp_smram->mapping), 0x00000000, 0x00000000,
smram_read, smram_readw, smram_readl,
smram_write, smram_writew, smram_writel,
ram, MEM_MAPPING_SMRAM, temp_smram);
smram_set_separate_smram(0);
return temp_smram;
}
/* Set memory state in the specified model (normal or SMM) according to the specified flags,
separately for bus and CPU. */
void
smram_map_ex(int bus, int smm, uint32_t addr, uint32_t size, int is_smram)
{
if (bus)
mem_set_access_smram_bus(smm, addr, size, is_smram);
else
mem_set_access_smram_cpu(smm, addr, size, is_smram);
}
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
void
smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
{
smram_map_ex(0, smm, addr, size, is_smram);
smram_map_ex(1, smm, addr, size, is_smram);
}
/* Disable a specific SMRAM mapping. */
void
smram_disable(smram_t *smr)
{
if (smr == NULL) {
fatal("smram_disable(): Invalid SMRAM mapping\n");
return;
}
if (smr->size != 0x00000000) {
smram_map(0, smr->host_base, smr->size, 0);
smram_map(1, smr->host_base, smr->size, 0);
smr->host_base = smr->ram_base = 0x00000000;
smr->size = 0x00000000;
mem_mapping_disable(&(smr->mapping));
}
}
/* Disable all SMRAM mappings. */
void
smram_disable_all(void)
{
smram_t *temp_smram = base_smram;
smram_t *next;
while (temp_smram != NULL) {
smram_disable(temp_smram);
next = temp_smram->next;
temp_smram = next;
}
}
/* Enable SMRAM mappings according to flags for both normal and SMM modes, separately for bus
and CPU. */
void
smram_enable_ex(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
int flags_normal, int flags_normal_bus, int flags_smm, int flags_smm_bus)
{
if (smr == NULL) {
fatal("smram_add(): Invalid SMRAM mapping\n");
return;
}
if ((size != 0x00000000) && (flags_normal || flags_smm)) {
smr->host_base = host_base;
smr->ram_base = ram_base;
smr->size = size;
mem_mapping_set_addr(&(smr->mapping), smr->host_base, smr->size);
if (!use_separate_smram || (smr->ram_base >= 0x000a0000)) {
if (smr->ram_base < (1 << 30))
mem_mapping_set_exec(&(smr->mapping), ram + smr->ram_base);
else
mem_mapping_set_exec(&(smr->mapping), ram2 + smr->ram_base - (1 << 30));
} else {
if (smr->ram_base == 0x00030000)
mem_mapping_set_exec(&(smr->mapping), smram);
else if (smr->ram_base == 0x00040000)
mem_mapping_set_exec(&(smr->mapping), smram + 0x10000);
else if (smr->ram_base == 0x00060000)
mem_mapping_set_exec(&(smr->mapping), smram + 0x20000);
else if (smr->ram_base == 0x00070000)
mem_mapping_set_exec(&(smr->mapping), smram + 0x30000);
}
smram_map_ex(0, 0, host_base, size, flags_normal);
smram_map_ex(1, 0, host_base, size, flags_normal_bus);
smram_map_ex(0, 1, host_base, size, flags_smm);
smram_map_ex(1, 1, host_base, size, flags_smm_bus);
} else
smram_disable(smr);
}
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
void
smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, int flags_normal, int flags_smm)
{
smram_enable_ex(smr, host_base, ram_base, size, flags_normal, flags_normal, flags_smm, flags_smm);
}
/* Checks if a SMRAM mapping is enabled or not. */
int
smram_enabled(smram_t *smr)
{
int ret = 0;
if (smr == NULL)
ret = 0;
else
ret = (smr->size != 0x00000000);
return ret;
}
/* Changes the SMRAM state. */
void
smram_state_change(smram_t *smr, int smm, int flags)
{
if (smr == NULL) {
fatal("smram_tate_change(): Invalid SMRAM mapping\n");
return;
}
smram_map(smm, smr->host_base, smr->size, flags);
}
void
smram_set_separate_smram(uint8_t set)
{
use_separate_smram = set;
}
``` | /content/code_sandbox/src/mem/smram.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,398 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the 24Cxx series of I2C EEPROMs.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <wchar.h>
#include <86box/86box.h>
#include <86box/i2c.h>
#include <86box/plat_unused.h>
typedef struct i2c_eeprom_t {
void *i2c;
uint8_t addr;
uint8_t *data;
uint8_t writable;
uint32_t addr_mask;
uint32_t addr_register;
uint8_t addr_len;
uint8_t addr_pos;
} i2c_eeprom_t;
#ifdef ENABLE_I2C_EEPROM_LOG
int i2c_eeprom_do_log = ENABLE_I2C_EEPROM_LOG;
static void
i2c_eeprom_log(const char *fmt, ...)
{
va_list ap;
if (i2c_eeprom_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define i2c_eeprom_log(fmt, ...)
#endif
static uint8_t
i2c_eeprom_start(UNUSED(void *bus), uint8_t addr, uint8_t read, void *priv)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) priv;
i2c_eeprom_log("I2C EEPROM %s %02X: start(%c)\n", i2c_getbusname(dev->i2c), dev->addr, read ? 'R' : 'W');
if (!read) {
dev->addr_pos = 0;
dev->addr_register = (addr << dev->addr_len) & dev->addr_mask;
}
return 1;
}
static uint8_t
i2c_eeprom_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) priv;
uint8_t ret = dev->data[dev->addr_register];
i2c_eeprom_log("I2C EEPROM %s %02X: read(%06X) = %02X\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register, ret);
dev->addr_register = (dev->addr_register + 1) & dev->addr_mask; /* roll-over */
return ret;
}
static uint8_t
i2c_eeprom_write(UNUSED(void *bus), uint8_t addr, uint8_t data, void *priv)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) priv;
if (dev->addr_pos < dev->addr_len) {
dev->addr_register <<= 8;
dev->addr_register |= data;
dev->addr_register &= (1 << dev->addr_len) - 1;
dev->addr_register |= addr << dev->addr_len;
dev->addr_register &= dev->addr_mask;
i2c_eeprom_log("I2C EEPROM %s %02X: write(address, %06X)\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register);
dev->addr_pos += 8;
} else {
i2c_eeprom_log("I2C EEPROM %s %02X: write(%06X, %02X) = %d\n", i2c_getbusname(dev->i2c), dev->addr, dev->addr_register, data, !!dev->writable);
if (dev->writable)
dev->data[dev->addr_register] = data;
dev->addr_register = (dev->addr_register + 1) & dev->addr_mask; /* roll-over */
return dev->writable;
}
return 1;
}
static void
i2c_eeprom_stop(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) priv;
i2c_eeprom_log("I2C EEPROM %s %02X: stop()\n", i2c_getbusname(dev->i2c), dev->addr);
dev->addr_pos = 0;
}
uint8_t
log2i(uint32_t i)
{
uint8_t ret = 0;
while (i >>= 1)
ret++;
return ret;
}
void *
i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t writable)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) malloc(sizeof(i2c_eeprom_t));
memset(dev, 0, sizeof(i2c_eeprom_t));
/* Round size up to the next power of 2. */
uint32_t pow_size = 1 << log2i(size);
if (pow_size < size)
size = pow_size << 1;
if (size >= 8388608)
size = 8388608; /* address space limit of 8 MB = 7 bits from I2C address + 16 bits from command address */
i2c_eeprom_log("I2C EEPROM %s %02X: init(%d, %d)\n", i2c_getbusname(i2c), addr, size, writable);
dev->i2c = i2c;
dev->addr = addr;
dev->data = data;
dev->writable = writable;
dev->addr_len = (size >= 4096) ? 16 : 8; /* use 16-bit addresses on 24C32 and above */
dev->addr_mask = size - 1;
uint8_t i2c_mask = dev->addr_mask >> dev->addr_len;
i2c_sethandler(dev->i2c, dev->addr & ~i2c_mask, i2c_mask + 1, i2c_eeprom_start, i2c_eeprom_read, i2c_eeprom_write, i2c_eeprom_stop, dev);
return dev;
}
void
i2c_eeprom_close(void *dev_handle)
{
i2c_eeprom_t *dev = (i2c_eeprom_t *) dev_handle;
i2c_eeprom_log("I2C EEPROM %s %02X: close()\n", i2c_getbusname(dev->i2c), dev->addr);
uint8_t i2c_mask = dev->addr_mask >> dev->addr_len;
i2c_removehandler(dev->i2c, dev->addr & ~i2c_mask, i2c_mask + 1, i2c_eeprom_start, i2c_eeprom_read, i2c_eeprom_write, i2c_eeprom_stop, dev);
free(dev);
}
``` | /content/code_sandbox/src/mem/i2c_eeprom.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,608 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of SPD (Serial Presence Detect) devices.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/i2c.h>
#include <86box/spd.h>
#include <86box/version.h>
#include <86box/machine.h>
#include <86box/plat_unused.h>
#define SPD_ROLLUP(x) ((x) >= 16 ? ((x) -15) : (x))
uint8_t spd_present = 0;
spd_t *spd_modules[SPD_MAX_SLOTS];
static const device_t spd_device;
#ifdef ENABLE_SPD_LOG
int spd_do_log = ENABLE_SPD_LOG;
static void
spd_log(const char *fmt, ...)
{
va_list ap;
if (spd_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define spd_log(fmt, ...)
#endif
static void
spd_close(UNUSED(void *priv))
{
spd_log("SPD: close()\n");
for (uint8_t i = 0; i < SPD_MAX_SLOTS; i++) {
if (spd_modules[i])
i2c_eeprom_close(spd_modules[i]->eeprom);
}
spd_present = 0;
}
static void *
spd_init(UNUSED(const device_t *info))
{
spd_log("SPD: init()\n");
for (uint8_t i = 0; i < SPD_MAX_SLOTS; i++) {
if (spd_modules[i])
spd_modules[i]->eeprom = i2c_eeprom_init(i2c_smbus, SPD_BASE_ADDR + i, spd_modules[i]->data, sizeof(spd_modules[i]->data), 0);
}
spd_present = 1;
return &spd_modules;
}
int
comp_ui16_rev(const void *elem1, const void *elem2)
{
const uint16_t a = *((const uint16_t *) elem1);
const uint16_t b = *((const uint16_t *) elem2);
return ((a > b) ? -1 : ((a < b) ? 1 : 0));
}
void
spd_populate(uint16_t *rows, uint8_t slot_count, uint16_t total_size, uint16_t min_module_size, uint16_t max_module_size, uint8_t enable_asym)
{
uint8_t row;
uint8_t next_empty_row;
uint8_t split;
uint16_t asym;
/* Populate rows with modules in power-of-2 capacities. */
memset(rows, 0, SPD_MAX_SLOTS << 1);
for (row = 0; row < slot_count && total_size; row++) {
/* populate slot */
rows[row] = 1 << log2i(MIN(total_size, max_module_size));
if (total_size >= rows[row]) {
spd_log("SPD: Initial row %d = %d MB\n", row, rows[row]);
total_size -= rows[row];
} else {
rows[row] = 0;
break;
}
}
/* Did we populate all the RAM? */
if (total_size) {
/* Work backwards to add the missing RAM as asymmetric modules if possible. */
if (enable_asym) {
row = slot_count - 1;
do {
asym = (1 << log2i(MIN(total_size, rows[row])));
if (rows[row] + asym <= max_module_size) {
rows[row] += asym;
total_size -= asym;
}
} while ((row-- > 0) && total_size);
}
if (total_size) /* still not enough */
spd_log("SPD: Not enough RAM slots (%d) to cover memory (%d MB short)\n", slot_count, total_size);
}
/* Populate empty rows by splitting modules... */
split = (total_size == 0); /* ...if possible. */
while (split) {
/* Look for a module to split. */
split = 0;
for (row = 0; row < slot_count; row++) {
if ((rows[row] <= (min_module_size << 1)) || (rows[row] != (1 << log2i(rows[row]))))
continue; /* no module here, module is too small to be split, or asymmetric module */
/* Find next empty row. */
next_empty_row = 0;
for (uint8_t i = row + 1; i < slot_count && !next_empty_row; i++) {
if (!rows[i])
next_empty_row = i;
}
if (!next_empty_row)
break; /* no empty rows left */
/* Split the module into its own row and the next empty row. */
spd_log("SPD: splitting row %d (%d MB) into %d and %d (%d MB each)\n", row, rows[row], row, next_empty_row, rows[row] >> 1);
rows[row] = rows[next_empty_row] = rows[row] >> 1;
split = 1;
break;
}
/* Sort rows by descending capacity if any were split. */
if (split)
qsort(rows, slot_count, sizeof(uint16_t), comp_ui16_rev);
}
}
static int
spd_write_part_no(char *part_no, char *type, uint16_t size)
{
char size_unit;
if (size >= 1024) {
size_unit = 'G';
size >>= 10;
} else {
size_unit = 'M';
}
return sprintf(part_no, EMU_NAME "-%s-%03d%c", type, size, size_unit);
}
void
spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
{
uint8_t slot;
uint8_t slot_count;
uint8_t row;
uint16_t min_module_size;
uint16_t rows[SPD_MAX_SLOTS];
uint16_t asym;
spd_edo_t *edo_data;
spd_sdram_t *sdram_data;
/* Determine the minimum module size for this RAM type. */
switch (ram_type) {
case SPD_TYPE_FPM:
case SPD_TYPE_EDO:
min_module_size = SPD_MIN_SIZE_EDO;
break;
case SPD_TYPE_SDRAM:
min_module_size = SPD_MIN_SIZE_SDRAM;
break;
default:
spd_log("SPD: unknown RAM type %02X\n", ram_type);
return;
}
/* Count how many slots are enabled. */
slot_count = 0;
for (slot = 0; slot < SPD_MAX_SLOTS; slot++) {
rows[slot] = 0;
if (slot_mask & (1 << slot))
slot_count++;
}
/* Populate rows. */
spd_populate(rows, slot_count, (mem_size >> 10), min_module_size, max_module_size, 1);
/* Register SPD devices and populate their data according to the rows. */
row = 0;
for (slot = 0; (slot < SPD_MAX_SLOTS) && rows[row]; slot++) {
if (!(slot_mask & (1 << slot)))
continue; /* slot disabled */
spd_modules[slot] = (spd_t *) malloc(sizeof(spd_t));
memset(spd_modules[slot], 0, sizeof(spd_t));
spd_modules[slot]->slot = slot;
spd_modules[slot]->size = rows[row];
/* Determine the second row size, from which the first row size can be obtained. */
asym = rows[row] - (1 << log2i(rows[row])); /* separate the powers of 2 */
if (!asym) /* is the module asymmetric? */
asym = rows[row] >> 1; /* symmetric, therefore divide by 2 */
spd_modules[slot]->row1 = rows[row] - asym;
spd_modules[slot]->row2 = asym;
spd_log("SPD: Registering slot %d = row %d = %d MB (%d/%d)\n", slot, row, rows[row], spd_modules[slot]->row1, spd_modules[slot]->row2);
switch (ram_type) {
case SPD_TYPE_FPM:
case SPD_TYPE_EDO:
edo_data = &spd_modules[slot]->edo_data;
/* EDO SPD is specified by JEDEC and present in some modules, but
most utilities cannot interpret it correctly. SIV32 at least gets
the module capacities right, so it was used as a reference here. */
edo_data->bytes_used = 0x80;
edo_data->spd_size = 0x08;
edo_data->mem_type = ram_type;
edo_data->row_bits = SPD_ROLLUP(7 + log2i(spd_modules[slot]->row1)); /* first row */
edo_data->col_bits = 9;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
edo_data->row_bits |= SPD_ROLLUP(7 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
edo_data->col_bits |= 9 << 4; /* same as first row, but just in case */
}
edo_data->banks = 2;
edo_data->data_width_lsb = 64;
edo_data->signal_level = SPD_SIGNAL_LVTTL;
edo_data->trac = 50;
edo_data->tcac = 13;
edo_data->refresh_rate = SPD_REFRESH_NORMAL;
edo_data->dram_width = 8;
edo_data->spd_rev = 0x12;
for (int i = spd_write_part_no(edo_data->part_no, (ram_type == SPD_TYPE_FPM) ? "FPM" : "EDO", rows[row]);
i < sizeof(edo_data->part_no); i++)
edo_data->part_no[i] = ' '; /* part number should be space-padded */
edo_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
edo_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
edo_data->mfg_year = 20;
edo_data->mfg_week = 17;
for (uint8_t i = 0; i < 63; i++)
edo_data->checksum += spd_modules[slot]->data[i];
for (uint8_t i = 0; i < 129; i++)
edo_data->checksum2 += spd_modules[slot]->data[i];
break;
case SPD_TYPE_SDRAM:
sdram_data = &spd_modules[slot]->sdram_data;
sdram_data->bytes_used = 0x80;
sdram_data->spd_size = 0x08;
sdram_data->mem_type = ram_type;
sdram_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */
sdram_data->col_bits = 9;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
sdram_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
sdram_data->col_bits |= 9 << 4; /* same as first row, but just in case */
}
sdram_data->rows = 2;
sdram_data->data_width_lsb = 64;
sdram_data->signal_level = SPD_SIGNAL_LVTTL;
sdram_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
sdram_data->tac = 0x10;
sdram_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
sdram_data->sdram_width = 8;
sdram_data->tccd = 1;
sdram_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
sdram_data->banks = 4;
sdram_data->cas = 0x1c; /* CAS 5/4/3 supported */
sdram_data->cslat = sdram_data->we = 0x7f;
sdram_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
sdram_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
sdram_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
sdram_data->tac2 = sdram_data->tac3 = 0x10;
sdram_data->trp = sdram_data->trrd = sdram_data->trcd = sdram_data->tras = 1;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) {
/* Utilities interpret bank_density a bit differently on asymmetric modules. */
sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */
sdram_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */
} else {
sdram_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */
}
sdram_data->ca_setup = sdram_data->data_setup = 0x15;
sdram_data->ca_hold = sdram_data->data_hold = 0x08;
sdram_data->spd_rev = 0x12;
for (int i = spd_write_part_no(sdram_data->part_no, "SDR", rows[row]);
i < sizeof(sdram_data->part_no); i++)
sdram_data->part_no[i] = ' '; /* part number should be space-padded */
sdram_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
sdram_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
sdram_data->mfg_year = 20;
sdram_data->mfg_week = 13;
sdram_data->freq = 100;
sdram_data->features = 0xFF;
for (uint8_t i = 0; i < 63; i++)
sdram_data->checksum += spd_modules[slot]->data[i];
for (uint8_t i = 0; i < 129; i++)
sdram_data->checksum2 += spd_modules[slot]->data[i];
break;
default:
break;
}
row++;
}
device_add(&spd_device);
}
void
spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t dimm;
uint8_t drb;
uint8_t apollo = 0;
uint8_t two_step = !!(drb_unit & 0x80);
uint16_t size;
uint16_t rows[SPD_MAX_SLOTS];
drb_unit &= 0x7f;
/* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */
if (reg_max < reg_min) {
apollo = reg_max;
reg_max = reg_min + 7;
}
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (uint8_t row = 0; row <= (reg_max - reg_min); row++) {
dimm = (row >> 1);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_modules[dimm]) {
if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = (row & 1) ? 0 : drb_unit;
else
size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1;
}
} else {
/* No SPD: use the values calculated above. */
size = (rows[dimm] >> 1);
}
/* Determine the DRB register to write. */
if (two_step)
drb = reg_min + (row << 1);
else
drb = reg_min + row;
if (apollo && ((drb & 0xf) < 0xa))
drb = apollo + (drb & 0xf);
/* Write DRB register, adding the previous DRB's value. */
if (row == 0)
regs[drb] = 0;
else if (apollo && (drb == apollo))
regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */
else
regs[drb] = regs[drb - 1];
if (size)
regs[drb] += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */
spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]);
}
}
/* Needed for 430NX. */
void
spd_write_drbs_with_ext(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t dimm;
uint8_t drb;
uint16_t size;
uint16_t row_val = 0;
uint16_t rows[SPD_MAX_SLOTS];
int shift;
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (uint8_t row = 0; row <= (reg_max - reg_min); row++) {
dimm = (row >> 1);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_modules[dimm]) {
if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = (row & 1) ? 0 : drb_unit;
else
size = (row & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1;
}
} else {
/* No SPD: use the values calculated above. */
size = (rows[dimm] >> 1);
}
/* Determine the DRB register to write. */
drb = reg_min + row;
/* Write DRB register, adding the previous DRB's value. */
if (row == 0)
row_val = 0;
if (size)
row_val += size / drb_unit; /* this will intentionally overflow on 440GX with 2 GB */
regs[drb] = row_val & 0xff;
drb = reg_min + 8 + (row >> 1);
shift = (row & 0x01) << 2;
/* Limit to 1 GB space, per the 430NX datasheet. */
regs[drb] = (regs[drb] & ~(0xf << shift)) | (((row_val >> 8) & 3) << shift);
spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]);
}
}
/* Used by ALi M1531 and M1541/2. */
void
spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t dimm;
uint8_t drb;
uint16_t size;
uint16_t size_acc = 0;
uint16_t rows[SPD_MAX_SLOTS];
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(rows, dimm, mem_size >> 10, drb_unit, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (uint8_t row = 0; row <= (reg_max - reg_min); row += 2) {
dimm = (row >> 2);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_modules[dimm]) {
if (spd_modules[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = ((row >> 1) & 1) ? 0 : drb_unit;
else
size = ((row >> 1) & 1) ? spd_modules[dimm]->row2 : spd_modules[dimm]->row1;
}
} else {
/* No SPD: use the values calculated above. */
size = (rows[dimm] >> 1);
}
/* Determine the DRB register to write. */
drb = reg_min + row;
/* Calculate previous and new size. */
if (row == 0)
size_acc = 0;
else
size_acc += (size / drb_unit);
/* Write DRB register, adding the previous DRB's value. */
regs[drb] = size_acc & 0xff;
regs[drb + 1] = (regs[drb + 1] & 0xf0) | ((size_acc >> 8) & 0x0f);
spd_log("SPD: DRB[%d] = %d MB (%02Xh raw)\n", row >> 1, size, regs[drb]);
}
}
/* This is needed because the ALi M1621 does this stuff completely differently,
as it has DRAM bank registers instead of DRAM row boundary registers. */
void
spd_write_drbs_ali1621(uint8_t *regs, uint8_t reg_min, uint8_t reg_max)
{
uint8_t dimm;
uint8_t drb;
uint16_t size;
uint16_t rows[SPD_MAX_SLOTS];
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 2; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(rows, dimm, mem_size >> 10, 4, 1 << (log2i((machines[machine].ram.max >> 10) / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("SPD: Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (dimm = 0; dimm <= ((reg_max - reg_min) >> 2); dimm++) {
size = 0;
drb = reg_min + (dimm << 2);
regs[drb] = 0xff;
regs[drb + 1] = 0xff;
regs[drb + 2] = 0x00;
regs[drb + 3] = 0xf0;
if (spd_modules[dimm] == NULL)
continue;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
size = (spd_modules[dimm]->row1 + spd_modules[dimm]->row2) >> 1;
} else {
/* No SPD: use the values calculated above. */
size = (rows[dimm] >> 1);
}
if (spd_modules[dimm]->row1)
regs[drb + 3] |= 0x06;
switch (size) {
default:
case 4:
regs[drb + 2] = 0x00;
break;
case 8:
regs[drb + 2] = 0x10;
break;
case 16:
regs[drb + 2] = 0x20;
break;
case 32:
regs[drb + 2] = 0x30;
break;
case 64:
regs[drb + 2] = 0x40;
break;
case 128:
regs[drb + 2] = 0x50;
break;
case 256:
regs[drb + 2] = 0x60;
break;
}
if (spd_modules[dimm]->row2) {
regs[drb + 3] |= 0x01;
regs[drb + 2] |= 0x80;
}
spd_log("SPD: DIMM %i: %02X %02X %02X %02X\n", regs[drb], regs[drb + 1], regs[drb + 2], regs[drb + 3]);
}
}
static const device_t spd_device = {
.name = "Serial Presence Detect ROMs",
.internal_name = "spd",
.flags = DEVICE_ISA,
.local = 0,
.init = spd_init,
.close = spd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/mem/spd.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,333 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handling of ROM image files.
*
* NOTES: - pc2386 BIOS is corrupt (JMP at F000:FFF0 points to RAM)
* - pc2386 video BIOS is underdumped (16k instead of 24k)
* - c386sx16 BIOS fails checksum
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/machine.h>
#include <86box/m_xt_xi8088.h>
#ifdef ENABLE_ROM_LOG
int rom_do_log = ENABLE_ROM_LOG;
static void
rom_log(const char *fmt, ...)
{
va_list ap;
if (rom_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define rom_log(fmt, ...)
#endif
void
rom_add_path(const char *path)
{
char cwd[1024] = { 0 };
rom_path_t *rom_path = &rom_paths;
if (rom_paths.path[0] != '\0') {
// Iterate to the end of the list.
while (rom_path->next != NULL) {
rom_path = rom_path->next;
}
// Allocate the new entry.
rom_path = rom_path->next = calloc(1, sizeof(rom_path_t));
}
// Save the path, turning it into absolute if needed.
if (!path_abs((char *) path)) {
plat_getcwd(cwd, sizeof(cwd));
path_slash(cwd);
snprintf(rom_path->path, sizeof(rom_path->path), "%s%s", cwd, path);
} else {
snprintf(rom_path->path, sizeof(rom_path->path), "%s", path);
}
// Ensure the path ends with a separator.
path_slash(rom_path->path);
}
FILE *
rom_fopen(const char *fn, char *mode)
{
char temp[1024];
FILE *fp = NULL;
if (strstr(fn, "roms/") == fn) {
/* Relative path */
for (rom_path_t *rom_path = &rom_paths; rom_path != NULL; rom_path = rom_path->next) {
path_append_filename(temp, rom_path->path, fn + 5);
if ((fp = plat_fopen(temp, mode)) != NULL) {
return fp;
}
}
return fp;
} else {
/* Absolute path */
return plat_fopen(fn, mode);
}
}
int
rom_getfile(char *fn, char *s, int size)
{
char temp[1024];
if (strstr(fn, "roms/") == fn) {
/* Relative path */
for (rom_path_t *rom_path = &rom_paths; rom_path != NULL; rom_path = rom_path->next) {
path_append_filename(temp, rom_path->path, fn + 5);
if (rom_present(temp)) {
strncpy(s, temp, size);
return 1;
}
}
return 0;
} else {
/* Absolute path */
if (rom_present(fn)) {
strncpy(s, fn, size);
return 1;
}
return 0;
}
}
int
rom_present(const char *fn)
{
FILE *fp;
fp = rom_fopen(fn, "rb");
if (fp != NULL) {
(void) fclose(fp);
return 1;
}
return 0;
}
uint8_t
rom_read(uint32_t addr, void *priv)
{
const rom_t *rom = (rom_t *) priv;
#ifdef ROM_TRACE
if (rom->mapping.base == ROM_TRACE)
rom_log("ROM: read byte from BIOS at %06lX\n", addr);
#endif
if (addr < rom->mapping.base)
return 0xff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xff;
return (rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
uint16_t
rom_readw(uint32_t addr, void *priv)
{
rom_t *rom = (rom_t *) priv;
#ifdef ROM_TRACE
if (rom->mapping.base == ROM_TRACE)
rom_log("ROM: read word from BIOS at %06lX\n", addr);
#endif
if (addr < (rom->mapping.base - 1))
return 0xffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffff;
return (*(uint16_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
uint32_t
rom_readl(uint32_t addr, void *priv)
{
rom_t *rom = (rom_t *) priv;
#ifdef ROM_TRACE
if (rom->mapping.base == ROM_TRACE)
rom_log("ROM: read long from BIOS at %06lX\n", addr);
#endif
if (addr < (rom->mapping.base - 3))
return 0xffffffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffffffff;
return (*(uint32_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
int
rom_load_linear_oddeven(const char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
{
FILE *fp = rom_fopen(fn, "rb");
if (fp == NULL) {
rom_log("ROM: image '%s' not found\n", fn);
return 0;
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000)
addr = 0;
else
addr &= 0x03ffff;
if (ptr != NULL) {
if (fseek(fp, off, SEEK_SET) == -1)
fatal("rom_load_linear(): Error seeking to the beginning of the file\n");
for (int i = 0; i < (sz >> 1); i++) {
if (fread(ptr + (addr + (i << 1)), 1, 1, fp) != 1)
fatal("rom_load_linear(): Error reading even data\n");
}
for (int i = 0; i < (sz >> 1); i++) {
if (fread(ptr + (addr + (i << 1) + 1), 1, 1, fp) != 1)
fatal("rom_load_linear(): Error reading od data\n");
}
}
(void) fclose(fp);
return 1;
}
/* Load a ROM BIOS from its chips, interleaved mode. */
int
rom_load_linear(const char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
{
FILE *fp = rom_fopen(fn, "rb");
if (fp == NULL) {
rom_log("ROM: image '%s' not found\n", fn);
return 0;
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000)
addr = 0;
else
addr &= 0x03ffff;
if (ptr != NULL) {
if (fseek(fp, off, SEEK_SET) == -1)
fatal("rom_load_linear(): Error seeking to the beginning of the file\n");
if (fread(ptr + addr, 1, sz, fp) > sz)
fatal("rom_load_linear(): Error reading data\n");
}
(void) fclose(fp);
return 1;
}
/* Load a ROM BIOS from its chips, linear mode with high bit flipped. */
int
rom_load_linear_inverted(const char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
{
FILE *fp = rom_fopen(fn, "rb");
if (fp == NULL) {
rom_log("ROM: image '%s' not found\n", fn);
return 0;
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000) {
addr = 0;
} else {
addr &= 0x03ffff;
}
(void) fseek(fp, 0, SEEK_END);
if (ftell(fp) < sz) {
(void) fclose(fp);
return 0;
}
if (ptr != NULL) {
if (fseek(fp, off, SEEK_SET) == -1)
fatal("rom_load_linear_inverted(): Error seeking to the beginning of the file\n");
if (fread(ptr + addr + 0x10000, 1, sz >> 1, fp) > (sz >> 1))
fatal("rom_load_linear_inverted(): Error reading the upper half of the data\n");
if (fread(ptr + addr, sz >> 1, 1, fp) > (sz >> 1))
fatal("rom_load_linear_inverted(): Error reading the lower half of the data\n");
if (sz == 0x40000) {
if (fread(ptr + addr + 0x30000, 1, sz >> 1, fp) > (sz >> 1))
fatal("rom_load_linear_inverted(): Error reading the upper half of the data\n");
if (fread(ptr + addr + 0x20000, sz >> 1, 1, fp) > (sz >> 1))
fatal("rom_load_linear_inverted(): Error reading the lower half of the data\n");
}
}
(void) fclose(fp);
return 1;
}
/* Load a ROM BIOS from its chips, interleaved mode. */
int
rom_load_interleaved(const char *fnl, const char *fnh, uint32_t addr, int sz, int off, uint8_t *ptr)
{
FILE *fpl = rom_fopen(fnl, "rb");
FILE *fph = rom_fopen(fnh, "rb");
if (fpl == NULL || fph == NULL) {
if (fpl == NULL)
rom_log("ROM: image '%s' not found\n", fnl);
else
(void) fclose(fpl);
if (fph == NULL)
rom_log("ROM: image '%s' not found\n", fnh);
else
(void) fclose(fph);
return 0;
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000) {
addr = 0;
} else {
addr &= 0x03ffff;
}
if (ptr != NULL) {
(void) fseek(fpl, off, SEEK_SET);
(void) fseek(fph, off, SEEK_SET);
for (int c = 0; c < sz; c += 2) {
ptr[addr + c] = fgetc(fpl) & 0xff;
ptr[addr + c + 1] = fgetc(fph) & 0xff;
}
}
(void) fclose(fph);
(void) fclose(fpl);
return 1;
}
static int
bios_normalize(int n, int up)
{
/* 0x2000 -> 0x0000; 0x4000 -> 0x4000; 0x6000 -> 0x4000 */
int temp_n = n & ~MEM_GRANULARITY_MASK;
/* 0x2000 -> 0x4000; 0x4000 -> 0x4000; 0x6000 -> 0x8000 */
if (up && (n % MEM_GRANULARITY_SIZE))
temp_n += MEM_GRANULARITY_SIZE;
return temp_n;
}
static uint8_t *
rom_reset(uint32_t addr, int sz)
{
biosaddr = bios_normalize(addr, 0);
biosmask = bios_normalize(sz, 1) - 1;
if ((biosaddr + biosmask) > 0x000fffff)
biosaddr = 0x000fffff - biosmask;
rom_log("Load BIOS: %i bytes at %08X-%08X\n", biosmask + 1, biosaddr, biosaddr + biosmask);
/* If not done yet, allocate a 128KB buffer for the BIOS ROM. */
if (rom != NULL) {
rom_log("ROM allocated, freeing...\n");
free(rom);
rom = NULL;
}
rom_log("Allocating ROM...\n");
rom = (uint8_t *) malloc(biosmask + 1);
rom_log("Filling ROM with FF's...\n");
memset(rom, 0xff, biosmask + 1);
return rom;
}
uint8_t
bios_read(uint32_t addr, UNUSED(void *priv))
{
uint8_t ret = 0xff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = rom[addr - biosaddr];
return ret;
}
uint16_t
bios_readw(uint32_t addr, UNUSED(void *priv))
{
uint16_t ret = 0xffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint16_t *) &rom[addr - biosaddr];
return ret;
}
uint32_t
bios_readl(uint32_t addr, UNUSED(void *priv))
{
uint32_t ret = 0xffffffff;
addr &= 0x000fffff;
if ((addr >= biosaddr) && (addr <= (biosaddr + biosmask)))
ret = *(uint32_t *) &rom[addr - biosaddr];
return ret;
}
static void
bios_add(void)
{
int temp_cpu_type;
int temp_cpu_16bitbus = 1;
int temp_is286 = 0;
int temp_is6117 = 0;
if (/*AT && */ cpu_s) {
temp_cpu_type = cpu_s->cpu_type;
temp_cpu_16bitbus = (temp_cpu_type == CPU_286 || temp_cpu_type == CPU_386SX || temp_cpu_type == CPU_486SLC || temp_cpu_type == CPU_IBM386SLC || temp_cpu_type == CPU_IBM486SLC);
temp_is286 = (temp_cpu_type >= CPU_286);
temp_is6117 = !strcmp(cpu_f->manufacturer, "ALi");
}
if (biosmask > 0x1ffff) {
/* 256k+ BIOS'es only have low mappings at E0000-FFFFF. */
mem_mapping_add(&bios_mapping, 0xe0000, 0x20000,
bios_read, bios_readw, bios_readl,
NULL, NULL, NULL,
&rom[biosmask + 1 - 0x20000], MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(0x0e0000, 0x20000,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else {
mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1,
bios_read, bios_readw, bios_readl,
NULL, NULL, NULL,
rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
if (temp_is6117) {
mem_mapping_add(&bios_high_mapping, biosaddr | 0x03f00000, biosmask + 1,
bios_read, bios_readw, bios_readl,
NULL, NULL, NULL,
rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr | 0x03f00000, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else if (temp_is286) {
mem_mapping_add(&bios_high_mapping, biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
bios_read, bios_readw, bios_readl,
NULL, NULL, NULL,
rom, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, 0);
mem_set_mem_state_both(biosaddr | (temp_cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
}
/* These four are for loading the BIOS. */
int
bios_load(const char *fn1, const char *fn2, uint32_t addr, int sz, int off, int flags)
{
uint8_t ret = 0;
uint8_t *ptr = NULL;
int old_sz = sz;
/*
f0000, 65536 = prepare 64k rom starting at f0000, load 64k bios at 0000
fe000, 65536 = prepare 64k rom starting at f0000, load 8k bios at e000
fe000, 49152 = prepare 48k rom starting at f4000, load 8k bios at a000
fe000, 8192 = prepare 16k rom starting at fc000, load 8k bios at 2000
*/
if (!bios_only)
ptr = (flags & FLAG_AUX) ? rom : rom_reset(addr, sz);
if (!(flags & FLAG_AUX) && ((addr + sz) > 0x00100000))
sz = 0x00100000 - addr;
#ifdef ENABLE_ROM_LOG
if (!bios_only)
rom_log("%sing %i bytes of %sBIOS starting with ptr[%08X] (ptr = %08X)\n", (bios_only) ? "Check" : "Load", sz, (flags & FLAG_AUX) ? "auxiliary " : "", addr - biosaddr, ptr);
#endif
if (flags & FLAG_INT)
ret = rom_load_interleaved(fn1, fn2, addr - biosaddr, sz, off, ptr);
else {
if (flags & FLAG_INV)
ret = rom_load_linear_inverted(fn1, addr - biosaddr, sz, off, ptr);
else
ret = rom_load_linear(fn1, addr - biosaddr, sz, off, ptr);
}
if (!bios_only && (flags & FLAG_REP) && (old_sz >= 65536) && (sz < old_sz)) {
old_sz /= sz;
for (int i = 0; i < (old_sz - 1); i++) {
rom_log("Copying ptr[%08X] to ptr[%08X]\n", addr - biosaddr, i * sz);
memcpy(&(ptr[i * sz]), &(ptr[addr - biosaddr]), sz);
}
}
if (!bios_only && ret && !(flags & FLAG_AUX))
bios_add();
return ret;
}
int
bios_load_linear_combined(const char *fn1, const char *fn2, int sz, UNUSED(int off))
{
uint8_t ret = 0;
ret = bios_load_linear(fn1, 0x000f0000, 131072, 128);
ret &= bios_load_aux_linear(fn2, 0x000e0000, sz - 65536, 128);
return ret;
}
int
bios_load_linear_combined2(const char *fn1, const char *fn2, const char *fn3, const char *fn4, const char *fn5, int sz, int off)
{
uint8_t ret = 0;
ret = bios_load_linear(fn3, 0x000f0000, 262144, off);
ret &= bios_load_aux_linear(fn1, 0x000d0000, 65536, off);
ret &= bios_load_aux_linear(fn2, 0x000c0000, 65536, off);
ret &= bios_load_aux_linear(fn4, 0x000e0000, sz - 196608, off);
if (fn5 != NULL)
ret &= bios_load_aux_linear(fn5, 0x000ec000, 16384, 0);
return ret;
}
int
bios_load_linear_combined2_ex(const char *fn1, const char *fn2, const char *fn3, const char *fn4, const char *fn5, int sz, int off)
{
uint8_t ret = 0;
ret = bios_load_linear(fn3, 0x000e0000, 262144, off);
ret &= bios_load_aux_linear(fn1, 0x000c0000, 65536, off);
ret &= bios_load_aux_linear(fn2, 0x000d0000, 65536, off);
ret &= bios_load_aux_linear(fn4, 0x000f0000, sz - 196608, off);
if (fn5 != NULL)
ret &= bios_load_aux_linear(fn5, 0x000fc000, 16384, 0);
return ret;
}
int
rom_init(rom_t *rom, const char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{
rom_log("rom_init(%08X, %s, %08X, %08X, %08X, %08X, %08X)\n", rom, fn, addr, sz, mask, off, flags);
/* Allocate a buffer for the image. */
rom->rom = malloc(sz);
memset(rom->rom, 0xff, sz);
/* Load the image file into the buffer. */
if (!rom_load_linear(fn, addr, sz, off, rom->rom)) {
/* Nope.. clean up. */
free(rom->rom);
rom->rom = NULL;
return (-1);
}
rom->sz = sz;
rom->mask = mask;
mem_mapping_add(&rom->mapping,
addr, sz,
rom_read, rom_readw, rom_readl,
NULL, NULL, NULL,
rom->rom, flags | MEM_MAPPING_ROM_WS, rom);
return 0;
}
int
rom_init_oddeven(rom_t *rom, const char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{
rom_log("rom_init(%08X, %08X, %08X, %08X, %08X, %08X, %08X)\n", rom, fn, addr, sz, mask, off, flags);
/* Allocate a buffer for the image. */
rom->rom = malloc(sz);
memset(rom->rom, 0xff, sz);
/* Load the image file into the buffer. */
if (!rom_load_linear_oddeven(fn, addr, sz, off, rom->rom)) {
/* Nope.. clean up. */
free(rom->rom);
rom->rom = NULL;
return (-1);
}
rom->sz = sz;
rom->mask = mask;
mem_mapping_add(&rom->mapping,
addr, sz,
rom_read, rom_readw, rom_readl,
NULL, NULL, NULL,
rom->rom, flags | MEM_MAPPING_ROM_WS, rom);
return 0;
}
int
rom_init_interleaved(rom_t *rom, const char *fnl, const char *fnh, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{
/* Allocate a buffer for the image. */
rom->rom = malloc(sz);
memset(rom->rom, 0xff, sz);
/* Load the image file into the buffer. */
if (!rom_load_interleaved(fnl, fnh, addr, sz, off, rom->rom)) {
/* Nope.. clean up. */
free(rom->rom);
rom->rom = NULL;
return (-1);
}
rom->sz = sz;
rom->mask = mask;
mem_mapping_add(&rom->mapping,
addr, sz,
rom_read, rom_readw, rom_readl,
NULL, NULL, NULL,
rom->rom, flags | MEM_MAPPING_ROM_WS, rom);
return 0;
}
``` | /content/code_sandbox/src/mem/rom.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,548 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* VDE networking for 86box
* See path_to_url#!tutorials/vdebasics.md
* for basic information about VDE. You can browse the source
* code at path_to_url
*
* VDE support is only available in Linux and MacOS. It _should_
* be available in BSD*, and if someday there is a BSD version of
* 86box this _could_ work out of the box.
*
* Authors: jguillaumes <jguillaumes@gmail.com>
*
* See the COPYING file at the top of the 86box for license details.
* TL;DR: GPL version 2.
*/
#include <stdio.h>
#include <stdlib.h>
#include <errno.h>
#include <string.h>
#include <stdint.h>
#if !defined(_WIN32)
#include <poll.h>
#include <unistd.h>
#else
#error VDE is not supported under windows
#endif
#include <libvdeplug.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/plat_dynld.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_event.h>
#define VDE_PKT_BATCH NET_QUEUE_LEN
#define VDE_DESCRIPTION "86Box virtual card"
enum {
NET_EVENT_STOP = 0,
NET_EVENT_TX,
NET_EVENT_RX,
NET_EVENT_VDE,
NET_EVENT_MAX
};
static volatile void *libvde_handle = NULL;
//+
// VDE connection structure
//-
typedef struct net_vde_t {
void *vdeconn; // VDEPLUG Connection
netcard_t *card; // NIC linked to
thread_t *poll_tid; // Polling thread
net_evt_t tx_event; // Packets to transmit event
net_evt_t stop_event; // Stop thread event
netpkt_t pkt; // Packet read/sent
netpkt_t pktv[VDE_PKT_BATCH]; // Packet queue
uint8_t mac_addr[6]; // MAC Address
} net_vde_t;
//+
// VDE libvdeplug function pointers
//-
static VDECONN *(*f_vde_open)(char *, char *, int, struct vde_open_args *); // This is vde_open_real()
static void (*f_vde_close)(VDECONN *);
static int (*f_vde_datafd)(VDECONN *); // Get the data (read/write) handle
static int (*f_vde_ctlfd)(VDECONN *); // Get the control handle
static ssize_t (*f_vde_recv)(VDECONN *, void *, size_t, int); // Receive a packet
static ssize_t (*f_vde_send)(VDECONN *, const void *, size_t, int); // Send a packet
//+
// VDE libvdeplug function table (for import)
//-
static dllimp_t vde_imports[] = {
{"vde_open_real", &f_vde_open},
{"vde_close", &f_vde_close},
{"vde_datafd", &f_vde_datafd},
{"vde_ctlfd", &f_vde_ctlfd},
{"vde_recv", &f_vde_recv},
{"vde_send", &f_vde_send},
{ NULL, NULL}
};
#ifdef ENABLE_VDE_LOG
#include <stdarg.h>
int vde_do_log = ENABLE_VDE_LOG;
static void
vde_log(const char *fmt, ...) {
va_list ap;
if (vde_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define vde_log(fmt, ...)
#endif
#ifdef _WIN32
#error VDE networking is not supported under windows
#else
//+
// VDE thread
//-
static void net_vde_thread(void *priv) {
net_vde_t *vde = (net_vde_t *) priv;
vde_log("VDE: Polling started.\n");
struct pollfd pfd[NET_EVENT_MAX];
pfd[NET_EVENT_STOP].fd = net_event_get_fd(&vde->stop_event);
pfd[NET_EVENT_STOP].events = POLLIN | POLLPRI;
pfd[NET_EVENT_TX].fd = net_event_get_fd(&vde->tx_event);
pfd[NET_EVENT_TX].events = POLLIN | POLLPRI;
pfd[NET_EVENT_RX].fd = f_vde_datafd(vde->vdeconn);
pfd[NET_EVENT_RX].events = POLLIN;
pfd[NET_EVENT_VDE].fd = f_vde_ctlfd(vde->vdeconn);
pfd[NET_EVENT_VDE].events = POLLIN;
while(1) {
poll(pfd, NET_EVENT_MAX, -1);
// Acvity in the control handle means the link is closed
// We send ourselves a STOP event
if (pfd[NET_EVENT_VDE].revents & POLLIN) {
net_event_set(&vde->stop_event);
}
// There are packets queued to transmit
if (pfd[NET_EVENT_TX].revents & POLLIN) {
net_event_clear(&vde->tx_event);
int packets = network_tx_popv(vde->card, vde->pktv, VDE_PKT_BATCH);
for (int i=0; i<packets; i++) {
int nc = f_vde_send(vde->vdeconn, vde->pktv[i].data,vde->pktv[i].len, 0 );
if (nc == 0) {
vde_log("VDE: Problem, no bytes sent.\n");
}
}
}
// Packets are available for reading. Read packet and queue it
if (pfd[NET_EVENT_RX].revents & POLLIN) {
int nc = f_vde_recv(vde->vdeconn, vde->pkt.data, NET_MAX_FRAME, 0);
vde->pkt.len = nc;
network_rx_put_pkt(vde->card, &vde->pkt);
}
// We have been told to close
if (pfd[NET_EVENT_STOP].revents & POLLIN) {
net_event_clear(&vde->stop_event);
break;
}
}
vde_log("VDE: Polling stopped.\n");
}
#endif
//+
// Prepare the VDE libvdeplug interface.
// Load the dynamic library libvdeplug.
// Returns zero if the library has been loaded, -1 in case of error.
//-
int net_vde_prepare(void) {
#if defined(_WIN32)
#error VDE is not supported in Windows
#elif defined(__APPLE__)
libvde_handle = dynld_module("libvdeplug.dylib", vde_imports);
#else
libvde_handle = dynld_module("libvdeplug.so", vde_imports);
#endif
if (libvde_handle == NULL) {
vde_log("VDE: error loading VDEPLUG module\n");
return -1;
} else {
network_devmap.has_vde = 1;
}
return 0;
}
//+
// Close a VDE socket connection
//-
void net_vde_close(void *priv) {
int i;
if (!priv) return;
net_vde_t *vde = (net_vde_t *) priv;
vde_log("VDE: closing.\n");
net_event_set(&vde->stop_event); // Tell the thread to finish
vde_log("VDE: Waiting for the thread to finish...\n");
thread_wait(vde->poll_tid);
vde_log("VDE: Thread finished.\n");
// Free all the mallocs!
for(i=0;i<VDE_PKT_BATCH; i++) {
free(vde->pktv[i].data);
}
free(vde->pkt.data);
f_vde_close(vde->vdeconn);
net_event_close(&vde->tx_event);
net_event_close(&vde->stop_event);
free(vde);
}
//+
// Signal packets are available to be transmitted
//-
void net_vde_in_available(void *priv) {
net_vde_t *vde = (net_vde_t *) priv;
net_event_set(&vde->tx_event);
}
//+
// Copy error message to the error buffer
// and log if enabled.
//-
void net_vde_error(char *errbuf, const char *message) {
strncpy(errbuf, message, NET_DRV_ERRBUF_SIZE);
vde_log("VDE: %s\n", message);
}
//+
// Initialize VDE for use
// At this point the vdeplug library is already loaded
// card: network card we are attaching
// mac_addr: MAC address we are using
// priv: Name of the VDE contol socket directory
//-
void *net_vde_init(const netcard_t *card, const uint8_t *mac_addr, void *priv, char *netdrv_errbuf) {
struct vde_open_args vde_args;
char *socket_name = (char *) priv;
if (libvde_handle == NULL) {
net_vde_error(netdrv_errbuf, "net_vde_init without library handle");
return NULL;
}
if ((socket_name[0] == '\0') || !strcmp(socket_name, "none")) {
net_vde_error(netdrv_errbuf, "No socket name configured");
return NULL;
}
vde_log("VDE: Attaching to virtual switch at %s\n", socket_name);
net_vde_t *vde = calloc(1, sizeof(net_vde_t));
vde->card = (netcard_t *) card;
memcpy(vde->mac_addr, mac_addr, sizeof(vde->mac_addr));
vde_args.group = 0;
vde_args.port = 0;
vde_args.mode = 0700; // Allow the switch to connect back to our socket if it is run by the same user
// We are calling vde_open_real(), not the vde_open() macro...
if ((vde->vdeconn = f_vde_open(socket_name, VDE_DESCRIPTION,
LIBVDEPLUG_INTERFACE_VERSION, &vde_args)) == NULL) {
char buf[NET_DRV_ERRBUF_SIZE];
snprintf(buf, NET_DRV_ERRBUF_SIZE, "Unable to open socket %s (%s)", socket_name, strerror(errno));
net_vde_error(netdrv_errbuf, buf);
free(vde);
return NULL;
}
vde_log("VDE: Socket opened (%s).\n", socket_name);
for(uint8_t i = 0; i < VDE_PKT_BATCH; i++) {
vde->pktv[i].data = calloc(1, NET_MAX_FRAME);
}
vde->pkt.data = calloc(1,NET_MAX_FRAME);
net_event_init(&vde->tx_event);
net_event_init(&vde->stop_event);
vde->poll_tid = thread_create(net_vde_thread, vde); // Fire up the read-write thread!
return vde;
}
//+
// VDE Driver structure
//-
const netdrv_t net_vde_drv = {
&net_vde_in_available,
&net_vde_init,
&net_vde_close,
NULL
};
``` | /content/code_sandbox/src/network/net_vde.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,606 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Memory handling and MMU.
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/version.h>
#include "cpu.h"
#include "x86_ops.h"
#include "x86.h"
#include "x86seg_common.h"
#include <86box/machine.h>
#include <86box/m_xt_xi8088.h>
#include <86box/config.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/plat.h>
#include <86box/rom.h>
#include <86box/gdbstub.h>
#ifdef USE_DYNAREC
# include "codegen_public.h"
#else
# ifdef USE_NEW_DYNAREC
# define PAGE_MASK_SHIFT 6
# else
# define PAGE_MASK_INDEX_MASK 3
# define PAGE_MASK_INDEX_SHIFT 10
# define PAGE_MASK_SHIFT 4
# endif
# define PAGE_MASK_MASK 63
#endif
#if (!defined(USE_DYNAREC) && defined(USE_NEW_DYNAREC))
# define BLOCK_PC_INVALID 0xffffffff
# define BLOCK_INVALID 0
#endif
mem_mapping_t ram_low_mapping; /* 0..640K mapping */
mem_mapping_t ram_mid_mapping; /* 640..1024K mapping */
mem_mapping_t ram_mid_mapping2; /* 640..1024K mapping, second part, for SiS 471 in relocate mode */
mem_mapping_t ram_remapped_mapping; /* 640..1024K mapping */
mem_mapping_t ram_remapped_mapping2; /* 640..1024K second mapping, for SiS 471 mode */
mem_mapping_t ram_high_mapping; /* 1024K+ mapping */
mem_mapping_t ram_2gb_mapping; /* 1024M+ mapping */
mem_mapping_t ram_split_mapping;
mem_mapping_t bios_mapping;
mem_mapping_t bios_high_mapping;
page_t *pages; /* RAM page table */
page_t **page_lookup; /* pagetable lookup */
uint32_t pages_sz; /* #pages in table */
uint8_t *ram; /* the virtual RAM */
uint8_t *ram2; /* the virtual RAM */
uint8_t page_ff[4096];
uint32_t rammask;
uint32_t addr_space_size;
uint8_t *rom; /* the virtual ROM */
uint32_t biosmask;
uint32_t biosaddr;
uint32_t pccache;
uint8_t *pccache2;
int readlnext;
int readlookup[256];
uintptr_t *readlookup2;
uintptr_t old_rl2;
uint8_t uncached = 0;
int writelnext;
int writelookup[256];
uintptr_t *writelookup2;
uint32_t mem_logical_addr;
int shadowbios = 0;
int shadowbios_write;
int readlnum = 0;
int writelnum = 0;
int cachesize = 256;
uint32_t get_phys_virt;
uint32_t get_phys_phys;
int mem_a20_key = 0;
int mem_a20_alt = 0;
int mem_a20_state = 0;
int mmuflush = 0;
int mmu_perm = 4;
#ifdef USE_NEW_DYNAREC
uint64_t *byte_dirty_mask;
uint64_t *byte_code_present_mask;
uint32_t purgable_page_list_head = 0;
int purgeable_page_count = 0;
#endif
uint8_t high_page = 0; /* if a high (> 4 gb) page was detected */
mem_mapping_t *read_mapping[MEM_MAPPINGS_NO];
mem_mapping_t *write_mapping[MEM_MAPPINGS_NO];
uint8_t *_mem_exec[MEM_MAPPINGS_NO];
/* FIXME: re-do this with a 'mem_ops' struct. */
static uint8_t *page_lookupp; /* pagetable mmu_perm lookup */
static uint8_t *readlookupp;
static uint8_t *writelookupp;
static mem_mapping_t *base_mapping;
static mem_mapping_t *last_mapping;
static mem_mapping_t *read_mapping_bus[MEM_MAPPINGS_NO];
static mem_mapping_t *write_mapping_bus[MEM_MAPPINGS_NO];
static uint8_t _mem_wp[MEM_MAPPINGS_NO];
static uint8_t _mem_wp_bus[MEM_MAPPINGS_NO];
static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff };
static mem_state_t _mem_state[MEM_MAPPINGS_NO];
static uint32_t remap_start_addr;
static uint32_t remap_start_addr2;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
static size_t ram_size = 0;
static size_t ram2_size = 0;
#else
static size_t ram_size = 0;
#endif
#ifdef ENABLE_MEM_LOG
int mem_do_log = ENABLE_MEM_LOG;
static void
mem_log(const char *fmt, ...)
{
va_list ap;
if (mem_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mem_log(fmt, ...)
#endif
int
mem_addr_is_ram(uint32_t addr)
{
const mem_mapping_t *mapping = read_mapping[addr >> MEM_GRANULARITY_BITS];
return (mapping == &ram_low_mapping) || (mapping == &ram_high_mapping) || (mapping == &ram_mid_mapping) ||
(mapping == &ram_mid_mapping2) || (mapping == &ram_remapped_mapping);
}
void
resetreadlookup(void)
{
/* Initialize the page lookup table. */
memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *));
/* Initialize the tables for lower (<= 1024K) RAM. */
for (uint16_t c = 0; c < 256; c++) {
readlookup[c] = 0xffffffff;
writelookup[c] = 0xffffffff;
}
/* Initialize the tables for high (> 1024K) RAM. */
memset(readlookup2, 0xff, (1 << 20) * sizeof(uintptr_t));
memset(readlookupp, 0x04, (1 << 20) * sizeof(uint8_t));
memset(writelookup2, 0xff, (1 << 20) * sizeof(uintptr_t));
memset(writelookupp, 0x04, (1 << 20) * sizeof(uint8_t));
readlnext = 0;
writelnext = 0;
pccache = 0xffffffff;
high_page = 0;
}
void
flushmmucache(void)
{
for (uint16_t c = 0; c < 256; c++) {
if (readlookup[c] != (int) 0xffffffff) {
readlookup2[readlookup[c]] = LOOKUP_INV;
readlookupp[readlookup[c]] = 4;
readlookup[c] = 0xffffffff;
}
if (writelookup[c] != (int) 0xffffffff) {
page_lookup[writelookup[c]] = NULL;
page_lookupp[writelookup[c]] = 4;
writelookup2[writelookup[c]] = LOOKUP_INV;
writelookupp[writelookup[c]] = 4;
writelookup[c] = 0xffffffff;
}
}
mmuflush++;
pccache = (uint32_t) 0xffffffff;
pccache2 = (uint8_t *) 0xffffffff;
#ifdef USE_DYNAREC
codegen_flush();
#endif
}
void
flushmmucache_nopc(void)
{
for (uint16_t c = 0; c < 256; c++) {
if (readlookup[c] != (int) 0xffffffff) {
readlookup2[readlookup[c]] = LOOKUP_INV;
readlookupp[readlookup[c]] = 4;
readlookup[c] = 0xffffffff;
}
if (writelookup[c] != (int) 0xffffffff) {
page_lookup[writelookup[c]] = NULL;
page_lookupp[writelookup[c]] = 4;
writelookup2[writelookup[c]] = LOOKUP_INV;
writelookupp[writelookup[c]] = 4;
writelookup[c] = 0xffffffff;
}
}
}
void
mem_flush_write_page(uint32_t addr, uint32_t virt)
{
const page_t *page_target = &pages[addr >> 12];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
for (uint16_t c = 0; c < 256; c++) {
if (writelookup[c] != (int) 0xffffffff) {
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
uintptr_t target = (uintptr_t) &ram[(uintptr_t) (addr & ~0xfff) - (virt & ~0xfff)];
#else
a = (uintptr_t) (addr & ~0xfff) - (virt & ~0xfff);
uintptr_t target;
if ((addr & ~0xfff) >= (1 << 30))
target = (uintptr_t) &ram2[a - (1 << 30)];
else
target = (uintptr_t) &ram[a];
#endif
if (writelookup2[writelookup[c]] == target || page_lookup[writelookup[c]] == page_target) {
writelookup2[writelookup[c]] = LOOKUP_INV;
page_lookup[writelookup[c]] = NULL;
writelookup[c] = 0xffffffff;
}
}
}
}
#define mmutranslate_read(addr) mmutranslatereal(addr, 0)
#define mmutranslate_write(addr) mmutranslatereal(addr, 1)
#define rammap(x) ((uint32_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK]
#define rammap64(x) ((uint64_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK]
static __inline uint64_t
mmutranslatereal_normal(uint32_t addr, int rw)
{
uint32_t temp;
uint32_t temp2;
uint32_t temp3;
uint32_t addr2;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = rammap(addr2);
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
/*4MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || ((is486 || isibm486) && (cr0 & WP_FLAG))))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap(addr2) |= (rw ? 0x60 : 0x20);
return (temp & ~0x3fffff) + (addr & 0x3fffff);
}
temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc));
temp3 = temp & temp2;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || ((is486 || isibm486) && (cr0 & WP_FLAG))))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap(addr2) |= 0x20;
rammap((temp2 & ~0xfff) + ((addr >> 10) & 0xffc)) |= (rw ? 0x60 : 0x20);
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
static __inline uint64_t
mmutranslatereal_pae(uint32_t addr, int rw)
{
uint64_t temp;
uint64_t temp2;
uint64_t temp3;
uint64_t temp4;
uint64_t addr2;
uint64_t addr3;
uint64_t addr4;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL;
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8);
temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL;
temp3 = temp & temp2;
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
if (temp & 0x80) {
/*2MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap64(addr3) |= (rw ? 0x60 : 0x20);
return ((temp & ~0x1fffffULL) + (addr & 0x1fffffULL)) & 0x000000ffffffffffULL;
}
addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8);
temp = rammap64(addr4) & 0x000000ffffffffffULL;
temp3 = temp & temp4;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
cr2 = addr;
temp &= 1;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
}
mmu_perm = temp & 4;
rammap64(addr3) |= 0x20;
rammap64(addr4) |= (rw ? 0x60 : 0x20);
return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
}
uint64_t
mmutranslatereal(uint32_t addr, int rw)
{
/* Fast path to return invalid without any call if an exception has occurred beforehand. */
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
if (cr4 & CR4_PAE)
return mmutranslatereal_pae(addr, rw);
else
return mmutranslatereal_normal(addr, rw);
}
/* This is needed because the old recompiler calls this to check for page fault. */
uint32_t
mmutranslatereal32(uint32_t addr, int rw)
{
/* Fast path to return invalid without any call if an exception has occurred beforehand. */
if (cpu_state.abrt)
return (uint32_t) 0xffffffffffffffffULL;
return (uint32_t) mmutranslatereal(addr, rw);
}
static __inline uint64_t
mmutranslate_noabrt_normal(uint32_t addr, int rw)
{
uint32_t temp;
uint32_t temp2;
uint32_t temp3;
uint32_t addr2;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc));
temp = temp2 = rammap(addr2);
if (!(temp & 1))
return 0xffffffffffffffffULL;
if ((temp & 0x80) && (cr4 & CR4_PSE)) {
/*4MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return (temp & ~0x3fffff) + (addr & 0x3fffff);
}
temp = rammap((temp & ~0xfff) + ((addr >> 10) & 0xffc));
temp3 = temp & temp2;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
static __inline uint64_t
mmutranslate_noabrt_pae(uint32_t addr, int rw)
{
uint64_t temp;
uint64_t temp2;
uint64_t temp3;
uint64_t temp4;
uint64_t addr2;
uint64_t addr3;
uint64_t addr4;
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
addr2 = (cr3 & ~0x1f) + ((addr >> 27) & 0x18);
temp = temp2 = rammap64(addr2) & 0x000000ffffffffffULL;
if (!(temp & 1))
return 0xffffffffffffffffULL;
addr3 = (temp & ~0xfffULL) + ((addr >> 18) & 0xff8);
temp = temp4 = rammap64(addr3) & 0x000000ffffffffffULL;
temp3 = temp & temp2;
if (!(temp & 1))
return 0xffffffffffffffffULL;
if (temp & 0x80) {
/*2MB page*/
if (((CPL == 3) && !(temp & 4) && !cpl_override) || (rw && !(temp & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return ((temp & ~0x1fffffULL) + (addr & 0x1fffff)) & 0x000000ffffffffffULL;
}
addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8);
temp = rammap64(addr4) & 0x000000ffffffffffULL;
temp3 = temp & temp4;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
return 0xffffffffffffffffULL;
return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
}
uint64_t
mmutranslate_noabrt(uint32_t addr, int rw)
{
/* Fast path to return invalid without any call if an exception has occurred beforehand. */
if (cpu_state.abrt)
return 0xffffffffffffffffULL;
if (cr4 & CR4_PAE)
return mmutranslate_noabrt_pae(addr, rw);
else
return mmutranslate_noabrt_normal(addr, rw);
}
uint8_t
mem_addr_range_match(uint32_t addr, uint32_t start, uint32_t len)
{
if (addr < start)
return 0;
else if (addr >= (start + len))
return 0;
else
return 1;
}
uint32_t
mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len)
{
uint32_t mask = len - 1;
return chunk_start + (addr & mask);
}
void
addreadlookup(uint32_t virt, uint32_t phys)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
if (virt == 0xffffffff)
return;
if (readlookup2[virt >> 12] != (uintptr_t) LOOKUP_INV)
return;
if (readlookup[readlnext] != (int) 0xffffffff) {
if ((readlookup[readlnext] == ((es + DI) >> 12)) || (readlookup[readlnext] == ((es + EDI) >> 12)))
uncached = 1;
readlookup2[readlookup[readlnext]] = LOOKUP_INV;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
readlookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)];
#else
a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff));
if ((phys & ~0xfff) >= (1 << 30))
readlookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)];
else
readlookup2[virt >> 12] = (uintptr_t) &ram[a];
#endif
readlookupp[virt >> 12] = mmu_perm;
readlookup[readlnext++] = virt >> 12;
readlnext &= (cachesize - 1);
cycles -= 9;
}
void
addwritelookup(uint32_t virt, uint32_t phys)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
if (virt == 0xffffffff)
return;
if (page_lookup[virt >> 12])
return;
if (writelookup[writelnext] != -1) {
page_lookup[writelookup[writelnext]] = NULL;
writelookup2[writelookup[writelnext]] = LOOKUP_INV;
}
#ifdef USE_NEW_DYNAREC
# ifdef USE_DYNAREC
if (pages[phys >> 12].block || (phys & ~0xfff) == recomp_page) {
# else
if (pages[phys >> 12].block) {
# endif
#else
# ifdef USE_DYNAREC
if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3] || (phys & ~0xfff) == recomp_page) {
# else
if (pages[phys >> 12].block[0] || pages[phys >> 12].block[1] || pages[phys >> 12].block[2] || pages[phys >> 12].block[3]) {
# endif
#endif
page_lookup[virt >> 12] = &pages[phys >> 12];
page_lookupp[virt >> 12] = mmu_perm;
} else {
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
writelookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)];
#else
a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff));
if ((phys & ~0xfff) >= (1 << 30))
writelookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)];
else
writelookup2[virt >> 12] = (uintptr_t) &ram[a];
#endif
}
writelookupp[virt >> 12] = mmu_perm;
writelookup[writelnext++] = virt >> 12;
writelnext &= (cachesize - 1);
cycles -= 9;
}
uint8_t *
getpccache(uint32_t a)
{
uint64_t a64 = (uint64_t) a;
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
uint8_t *p;
#endif
uint32_t a2;
a2 = a;
if (cr0 >> 31) {
a64 = mmutranslate_read(a64);
if (a64 == 0xffffffffffffffffULL)
return ram;
}
a64 &= rammask;
if (_mem_exec[a64 >> MEM_GRANULARITY_BITS]) {
if (is286) {
if (read_mapping[a64 >> MEM_GRANULARITY_BITS] && (read_mapping[a64 >> MEM_GRANULARITY_BITS]->flags & MEM_MAPPING_ROM_WS))
cpu_prefetch_cycles = cpu_rom_prefetch_cycles;
else
cpu_prefetch_cycles = cpu_mem_prefetch_cycles;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
p = &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t) (a64 & MEM_GRANULARITY_PAGE) - (uintptr_t) (a2 & ~0xfff)];
return (uint8_t *) (((uintptr_t) p & 0x00000000ffffffffULL) | ((uintptr_t) &_mem_exec[a64 >> MEM_GRANULARITY_BITS][0] & 0xffffffff00000000ULL));
#else
return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t) (a64 & MEM_GRANULARITY_PAGE) - (uintptr_t) (a2 & ~0xfff)];
#endif
}
mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a64 >> 32), (uint32_t) (a64 & 0xffffffffULL));
return (uint8_t *) &ff_pccache;
}
uint8_t
read_mem_b(uint32_t addr)
{
mem_mapping_t *map;
uint8_t ret = 0xff;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
ret = map->read_b(addr, map->priv);
resub_cycles(old_cycles);
return ret;
}
uint16_t
read_mem_w(uint32_t addr)
{
mem_mapping_t *map;
uint16_t ret = 0xffff;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
if (addr & 1)
ret = read_mem_b(addr) | (read_mem_b(addr + 1) << 8);
else {
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
ret = map->read_w(addr, map->priv);
else if (map && map->read_b)
ret = map->read_b(addr, map->priv) | (map->read_b(addr + 1, map->priv) << 8);
}
resub_cycles(old_cycles);
return ret;
}
void
write_mem_b(uint32_t addr, uint8_t val)
{
mem_mapping_t *map;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->priv);
resub_cycles(old_cycles);
}
void
write_mem_w(uint32_t addr, uint16_t val)
{
mem_mapping_t *map;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
if (addr & 1) {
write_mem_b(addr, val);
write_mem_b(addr + 1, val >> 8);
} else {
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
if (map->write_w)
map->write_w(addr, val, map->priv);
else if (map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
}
}
}
resub_cycles(old_cycles);
}
uint8_t
readmembl(uint32_t addr)
{
mem_mapping_t *map;
uint64_t a;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 1);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr, read_type);
#endif
addr64 = (uint64_t) addr;
mem_logical_addr = addr;
high_page = 0;
if (cr0 >> 31) {
a = mmutranslate_read(addr);
addr64 = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xff;
}
addr = (uint32_t) (addr64 & rammask);
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->priv);
return 0xff;
}
void
writemembl(uint32_t addr, uint8_t val)
{
mem_mapping_t *map;
uint64_t a;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 1);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr, 2);
#endif
addr64 = (uint64_t) addr;
mem_logical_addr = addr;
high_page = 0;
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_b) {
page_lookup[addr >> 12]->write_b(addr, val, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
a = mmutranslate_write(addr);
addr64 = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = (uint32_t) (addr64 & rammask);
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->priv);
}
/* Read a byte from memory without MMU translation - result of previous MMU translation passed as value. */
uint8_t
readmembl_no_mmut(uint32_t addr, uint32_t a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 1);
mem_logical_addr = addr;
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xff;
addr = a64 & rammask;
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->priv);
return 0xff;
}
/* Write a byte to memory without MMU translation - result of previous MMU translation passed as value. */
void
writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 1);
mem_logical_addr = addr;
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_b) {
page_lookup[addr >> 12]->write_b(addr, val, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = a64 & rammask;
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->priv);
}
uint16_t
readmemwl(uint32_t addr)
{
mem_mapping_t *map;
uint64_t a;
addr64a[0] = addr;
addr64a[1] = addr + 1;
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr, read_type);
mem_debug_check_addr(addr + 1, read_type);
#endif
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 2);
mem_logical_addr = addr;
high_page = 0;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
for (uint8_t i = 0; i < 2; i++) {
a = mmutranslate_read(addr + i);
addr64a[i] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffff;
}
}
return readmembl_no_mmut(addr, addr64a[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, addr64a[1])) << 8);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint16_t *) (readlookup2[addr >> 12] + addr);
}
}
if (cr0 >> 31) {
a = mmutranslate_read(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffff;
} else
addr64a[0] = (uint64_t) addr;
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
return map->read_w(addr, map->priv);
if (map && map->read_b) {
return map->read_b(addr, map->priv) | ((uint16_t) (map->read_b(addr + 1, map->priv)) << 8);
}
return 0xffff;
}
void
writememwl(uint32_t addr, uint16_t val)
{
mem_mapping_t *map;
uint64_t a;
addr64a[0] = addr;
addr64a[1] = addr + 1;
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr, 2);
mem_debug_check_addr(addr + 1, 2);
#endif
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 2);
mem_logical_addr = addr;
high_page = 0;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
for (uint8_t i = 0; i < 2; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
a = mmutranslate_write(addr + i);
addr64a[i] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writemembl_no_mmut(addr, addr64a[0], val);
writemembl_no_mmut(addr + 1, addr64a[1], val >> 8);
return;
} else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = writelookupp[addr >> 12];
*(uint16_t *) (writelookup2[addr >> 12] + addr) = val;
return;
}
}
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_w) {
page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]);
mmu_perm = page_lookupp[addr >> 12];
return;
}
if (cr0 >> 31) {
a = mmutranslate_write(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
return;
}
}
/* Read a word from memory without MMU translation - results of previous MMU translation passed as array. */
uint16_t
readmemwl_no_mmut(uint32_t addr, uint32_t *a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 2);
mem_logical_addr = addr;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffff;
}
return readmembl_no_mmut(addr, a64[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, a64[1])) << 8);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint16_t *) (readlookup2[addr >> 12] + addr);
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffff;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
return map->read_w(addr, map->priv);
if (map && map->read_b) {
return map->read_b(addr, map->priv) | ((uint16_t) (map->read_b(addr + 1, map->priv)) << 8);
}
return 0xffff;
}
/* Write a word to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 2);
mem_logical_addr = addr;
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
}
writemembl_no_mmut(addr, a64[0], val);
writemembl_no_mmut(addr + 1, a64[1], val >> 8);
return;
} else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = writelookupp[addr >> 12];
*(uint16_t *) (writelookup2[addr >> 12] + addr) = val;
return;
}
}
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_w) {
mmu_perm = page_lookupp[addr >> 12];
page_lookup[addr >> 12]->write_w(addr, val, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
return;
}
}
uint32_t
readmemll(uint32_t addr)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 4; i++) {
addr64a[i] = (uint64_t) (addr + i);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr + i, read_type);
#endif
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 4);
mem_logical_addr = addr;
high_page = 0;
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
for (i = 0; i < 4; i++) {
if (i == 0) {
a = mmutranslate_read(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_read(addr + 3);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return 0xffff;
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemwl_no_mmut(addr, addr64a) | (((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint32_t *) (readlookup2[addr >> 12] + addr);
}
}
if (cr0 >> 31) {
a = mmutranslate_read(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffffffff;
}
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv);
if (map && map->read_w)
return map->read_w(addr, map->priv) | ((uint32_t) (map->read_w(addr + 2, map->priv)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->priv) | ((uint32_t) (map->read_b(addr + 1, map->priv)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->priv)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->priv)) << 24);
return 0xffffffff;
}
void
writememll(uint32_t addr, uint32_t val)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 4; i++) {
addr64a[i] = (uint64_t) (addr + i);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr + i, 2);
#endif
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 4);
mem_logical_addr = addr;
high_page = 0;
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
for (i = 0; i < 4; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
if (i == 0) {
a = mmutranslate_write(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_write(addr + 3);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writememwl_no_mmut(addr, &(addr64a[0]), val);
writememwl_no_mmut(addr + 2, &(addr64a[2]), val >> 16);
return;
} else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = writelookupp[addr >> 12];
*(uint32_t *) (writelookup2[addr >> 12] + addr) = val;
return;
}
}
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) {
mmu_perm = page_lookupp[addr >> 12];
page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
a = mmutranslate_write(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
return;
}
}
/* Read a long from memory without MMU translation - results of previous MMU translation passed as array. */
uint32_t
readmemll_no_mmut(uint32_t addr, uint32_t *a64)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_READ, 4);
mem_logical_addr = addr;
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffffffff;
}
return readmemwl_no_mmut(addr, a64) | ((uint32_t) (readmemwl_no_mmut(addr + 2, &(a64[2]))) << 16);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint32_t *) (readlookup2[addr >> 12] + addr);
}
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return 0xffffffff;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv);
if (map && map->read_w)
return map->read_w(addr, map->priv) | ((uint32_t) (map->read_w(addr + 2, map->priv)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->priv) | ((uint32_t) (map->read_b(addr + 1, map->priv)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->priv)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->priv)) << 24);
return 0xffffffff;
}
/* Write a long to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val)
{
mem_mapping_t *map;
GDBSTUB_MEM_ACCESS(addr, GDBSTUB_MEM_WRITE, 4);
mem_logical_addr = addr;
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
}
writememwl_no_mmut(addr, &(a64[0]), val);
writememwl_no_mmut(addr + 2, &(a64[2]), val >> 16);
return;
} else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = writelookupp[addr >> 12];
*(uint32_t *) (writelookup2[addr >> 12] + addr) = val;
return;
}
}
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) {
mmu_perm = page_lookupp[addr >> 12];
page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
if (cpu_state.abrt || high_page)
return;
addr = (uint32_t) (a64[0] & rammask);
} else
addr &= rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
return;
}
}
uint64_t
readmemql(uint32_t addr)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 8; i++) {
addr64a[i] = (uint64_t) (addr + i);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr + i, read_type);
#endif
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_READ, 8);
mem_logical_addr = addr;
high_page = 0;
if (addr & 7) {
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xff8) {
if (cr0 >> 31) {
for (i = 0; i < 8; i++) {
if (i == 0) {
a = mmutranslate_read(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_read(addr + 7);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (a > 0xffffffffULL)
return 0xffff;
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemll_no_mmut(addr, addr64a) | (((uint64_t) readmemll_no_mmut(addr + 4, &(addr64a[4]))) << 32);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint64_t *) (readlookup2[addr >> 12] + addr);
}
}
if (cr0 >> 31) {
a = mmutranslate_read(addr);
addr64a[0] = (uint32_t) a;
if (a > 0xffffffffULL)
return 0xffffffffffffffffULL;
}
addr = addr64a[0] & rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_l)
return map->read_l(addr, map->priv) | ((uint64_t) map->read_l(addr + 4, map->priv) << 32);
return readmemll(addr) | ((uint64_t) readmemll(addr + 4) << 32);
}
void
writememql(uint32_t addr, uint64_t val)
{
mem_mapping_t *map;
int i;
uint64_t a = 0x0000000000000000ULL;
for (i = 0; i < 8; i++) {
addr64a[i] = (uint64_t) (addr + i);
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr + i, 2);
#endif
}
GDBSTUB_MEM_ACCESS_FAST(addr64a, GDBSTUB_MEM_WRITE, 8);
mem_logical_addr = addr;
high_page = 0;
if (addr & 7) {
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xff8) {
if (cr0 >> 31) {
for (i = 0; i < 8; i++) {
/* Do not translate a page that has a valid lookup, as that is by definition valid
and the whole purpose of the lookup is to avoid repeat identical translations. */
if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
if (i == 0) {
a = mmutranslate_write(addr + i);
addr64a[i] = (uint32_t) a;
} else if (!((addr + i) & 0xfff)) {
a = mmutranslate_write(addr + 7);
addr64a[i] = (uint32_t) a;
if (!cpu_state.abrt) {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
} else {
a = (a & ~0xfffLL) | ((uint64_t) ((addr + i) & 0xfff));
addr64a[i] = (uint32_t) a;
}
if (addr64a[i] > 0xffffffffULL)
return;
}
}
}
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
writememll_no_mmut(addr, addr64a, val);
writememll_no_mmut(addr + 4, &(addr64a[4]), val >> 32);
return;
} else if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = writelookupp[addr >> 12];
*(uint64_t *) (writelookup2[addr >> 12] + addr) = val;
return;
}
}
if (page_lookup[addr >> 12] && page_lookup[addr >> 12]->write_l) {
mmu_perm = page_lookupp[addr >> 12];
page_lookup[addr >> 12]->write_l(addr, val, page_lookup[addr >> 12]);
page_lookup[addr >> 12]->write_l(addr + 4, val >> 32, page_lookup[addr >> 12]);
return;
}
if (cr0 >> 31) {
addr64a[0] = mmutranslate_write(addr);
if (addr64a[0] > 0xffffffffULL)
return;
}
addr = addr64a[0] & rammask;
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_l) {
map->write_l(addr, val, map->priv);
map->write_l(addr + 4, val >> 32, map->priv);
return;
}
if (map && map->write_w) {
map->write_w(addr, val, map->priv);
map->write_w(addr + 2, val >> 16, map->priv);
map->write_w(addr + 4, val >> 32, map->priv);
map->write_w(addr + 6, val >> 48, map->priv);
return;
}
if (map && map->write_b) {
map->write_b(addr, val, map->priv);
map->write_b(addr + 1, val >> 8, map->priv);
map->write_b(addr + 2, val >> 16, map->priv);
map->write_b(addr + 3, val >> 24, map->priv);
map->write_b(addr + 4, val >> 32, map->priv);
map->write_b(addr + 5, val >> 40, map->priv);
map->write_b(addr + 6, val >> 48, map->priv);
map->write_b(addr + 7, val >> 56, map->priv);
return;
}
}
void
do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write)
{
int i;
int cond = 1;
uint32_t last_addr = addr + (num - 1);
uint64_t a = 0x0000000000000000ULL;
#ifdef USE_DEBUG_REGS_486
mem_debug_check_addr(addr, write ? 2 : read_type);
#endif
for (i = 0; i < num; i++)
a64[i] = (uint64_t) addr;
if (cr0 >> 31) for (i = 0; i < num; i++) {
if (write && ((i == 0) || !(addr & 0xfff)))
cond = (!page_lookup[addr >> 12] || !page_lookup[addr >> 12]->write_b);
if (cond) {
/* If we have encountered at least one page fault, mark all subsequent addresses as
having page faulted, prevents false negatives in readmem*l_no_mmut. */
if ((i > 0) && cpu_state.abrt && !high_page)
a64[i] = a64[i - 1];
/* If we are on the same page, there is no need to translate again, as we can just
reuse the previous result. */
else if (i == 0) {
a = mmutranslatereal(addr, write);
a64[i] = (uint32_t) a;
high_page = high_page || (!cpu_state.abrt && (a > 0xffffffffULL));
} else if (!(addr & 0xfff)) {
a = mmutranslatereal(last_addr, write);
a64[i] = (uint32_t) a;
high_page = high_page || (!cpu_state.abrt && (a64[i] > 0xffffffffULL));
if (!cpu_state.abrt) {
a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff));
a64[i] = (uint32_t) a;
}
} else {
a = (a & 0xfffffffffffff000ULL) | ((uint64_t) (addr & 0xfff));
a64[i] = (uint32_t) a;
}
} else
mmu_perm = page_lookupp[addr >> 12];
addr++;
}
}
uint8_t
mem_readb_phys(uint32_t addr)
{
mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS];
uint8_t ret = 0xff;
mem_logical_addr = 0xffffffff;
if (map) {
if (cpu_use_exec && map->exec)
ret = map->exec[(addr - map->base) & map->mask];
else if (map->read_b)
ret = map->read_b(addr, map->priv);
}
return ret;
}
uint16_t
mem_readw_phys(uint32_t addr)
{
mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS];
uint16_t ret;
const uint16_t *p;
mem_logical_addr = 0xffffffff;
if (cpu_use_exec && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->exec)) {
p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]);
ret = *p;
} else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->read_w))
ret = map->read_w(addr, map->priv);
else {
ret = mem_readb_phys(addr + 1) << 8;
ret |= mem_readb_phys(addr);
}
return ret;
}
uint32_t
mem_readl_phys(uint32_t addr)
{
mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS];
uint32_t ret;
const uint32_t *p;
mem_logical_addr = 0xffffffff;
if (cpu_use_exec && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->exec)) {
p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]);
ret = *p;
} else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->read_l))
ret = map->read_l(addr, map->priv);
else {
ret = mem_readw_phys(addr + 2) << 16;
ret |= mem_readw_phys(addr);
}
return ret;
}
void
mem_read_phys(void *dest, uint32_t addr, int transfer_size)
{
uint8_t *pb;
uint16_t *pw;
uint32_t *pl;
if (transfer_size == 4) {
pl = (uint32_t *) dest;
*pl = mem_readl_phys(addr);
} else if (transfer_size == 2) {
pw = (uint16_t *) dest;
*pw = mem_readw_phys(addr);
} else if (transfer_size == 1) {
pb = (uint8_t *) dest;
*pb = mem_readb_phys(addr);
}
}
void
mem_writeb_phys(uint32_t addr, uint8_t val)
{
mem_mapping_t *map = write_mapping_bus[addr >> MEM_GRANULARITY_BITS];
mem_logical_addr = 0xffffffff;
if (map) {
if (cpu_use_exec && map->exec)
map->exec[(addr - map->base) & map->mask] = val;
else if (map->write_b)
map->write_b(addr, val, map->priv);
}
}
void
mem_writew_phys(uint32_t addr, uint16_t val)
{
mem_mapping_t *map = write_mapping_bus[addr >> MEM_GRANULARITY_BITS];
uint16_t *p;
mem_logical_addr = 0xffffffff;
if (cpu_use_exec && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->exec)) {
p = (uint16_t *) &(map->exec[(addr - map->base) & map->mask]);
*p = val;
} else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_HBOUND) && (map && map->write_w))
map->write_w(addr, val, map->priv);
else {
mem_writeb_phys(addr, val & 0xff);
mem_writeb_phys(addr + 1, (val >> 8) & 0xff);
}
}
void
mem_writel_phys(uint32_t addr, uint32_t val)
{
mem_mapping_t *map = write_mapping_bus[addr >> MEM_GRANULARITY_BITS];
uint32_t *p;
mem_logical_addr = 0xffffffff;
if (cpu_use_exec && ((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->exec)) {
p = (uint32_t *) &(map->exec[(addr - map->base) & map->mask]);
*p = val;
} else if (((addr & MEM_GRANULARITY_MASK) <= MEM_GRANULARITY_QBOUND) && (map && map->write_l))
map->write_l(addr, val, map->priv);
else {
mem_writew_phys(addr, val & 0xffff);
mem_writew_phys(addr + 2, (val >> 16) & 0xffff);
}
}
void
mem_write_phys(void *src, uint32_t addr, int transfer_size)
{
const uint8_t *pb;
const uint16_t *pw;
const uint32_t *pl;
if (transfer_size == 4) {
pl = (uint32_t *) src;
mem_writel_phys(addr, *pl);
} else if (transfer_size == 2) {
pw = (uint16_t *) src;
mem_writew_phys(addr, *pw);
} else if (transfer_size == 1) {
pb = (uint8_t *) src;
mem_writeb_phys(addr, *pb);
}
}
uint8_t
mem_read_ram(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read B %02X from %08X\n", ram[addr], addr);
#endif
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
uint16_t
mem_read_ramw(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read W %04X from %08X\n", *(uint16_t *) &ram[addr], addr);
#endif
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *) &ram[addr];
}
uint32_t
mem_read_raml(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read L %08X from %08X\n", *(uint32_t *) &ram[addr], addr);
#endif
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *) &ram[addr];
}
uint8_t
mem_read_ram_2gb(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read B %02X from %08X\n", ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
return ram2[addr - (1 << 30)];
}
uint16_t
mem_read_ram_2gbw(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read W %04X from %08X\n", *(uint16_t *) &ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *) &ram2[addr - (1 << 30)];
}
uint32_t
mem_read_ram_2gbl(uint32_t addr, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Read L %08X from %08X\n", *(uint32_t *) &ram[addr], addr);
#endif
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *) &ram2[addr - (1 << 30)];
}
#ifdef USE_NEW_DYNAREC
static inline int
page_index(page_t *page)
{
return ((uintptr_t) page - (uintptr_t) pages) / sizeof(page_t);
}
void
page_add_to_evict_list(page_t *page)
{
pages[purgable_page_list_head].evict_prev = page_index(page);
page->evict_next = purgable_page_list_head;
page->evict_prev = 0;
purgable_page_list_head = pages[purgable_page_list_head].evict_prev;
purgeable_page_count++;
}
void
page_remove_from_evict_list(page_t *page)
{
if (!page_in_evict_list(page))
fatal("page_remove_from_evict_list: not in evict list!\n");
if (page->evict_prev)
pages[page->evict_prev].evict_next = page->evict_next;
else
purgable_page_list_head = page->evict_next;
if (page->evict_next)
pages[page->evict_next].evict_prev = page->evict_prev;
page->evict_prev = EVICT_NOT_IN_LIST;
purgeable_page_count--;
}
void
mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
uint64_t byte_mask = (uint64_t) 1 << (addr & PAGE_BYTE_MASK_MASK);
page->mem[addr & 0xfff] = val;
page->dirty_mask |= mask;
if ((page->code_present_mask & mask) && !page_in_evict_list(page))
page_add_to_evict_list(page);
page->byte_dirty_mask[byte_offset] |= byte_mask;
if ((page->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(page))
page_add_to_evict_list(page);
}
}
void
mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint16_t *) &page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint16_t *) &page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
uint64_t byte_mask = (uint64_t) 1 << (addr & PAGE_BYTE_MASK_MASK);
if ((addr & 0xf) == 0xf)
mask |= (mask << 1);
*(uint16_t *) &page->mem[addr & 0xfff] = val;
page->dirty_mask |= mask;
if ((page->code_present_mask & mask) && !page_in_evict_list(page))
page_add_to_evict_list(page);
if ((addr & PAGE_BYTE_MASK_MASK) == PAGE_BYTE_MASK_MASK) {
page->byte_dirty_mask[byte_offset + 1] |= 1;
if ((page->byte_code_present_mask[byte_offset + 1] & 1) && !page_in_evict_list(page))
page_add_to_evict_list(page);
} else
byte_mask |= (byte_mask << 1);
page->byte_dirty_mask[byte_offset] |= byte_mask;
if ((page->byte_code_present_mask[byte_offset] & byte_mask) && !page_in_evict_list(page))
page_add_to_evict_list(page);
}
}
void
mem_write_raml_page(uint32_t addr, uint32_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint32_t *) &page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint32_t *) &page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
int byte_offset = (addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
uint64_t byte_mask = (uint64_t) 0xf << (addr & PAGE_BYTE_MASK_MASK);
if ((addr & 0xf) >= 0xd)
mask |= (mask << 1);
*(uint32_t *) &page->mem[addr & 0xfff] = val;
page->dirty_mask |= mask;
page->byte_dirty_mask[byte_offset] |= byte_mask;
if (!page_in_evict_list(page) && ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask)))
page_add_to_evict_list(page);
if ((addr & PAGE_BYTE_MASK_MASK) > (PAGE_BYTE_MASK_MASK - 3)) {
uint32_t byte_mask_2 = 0xf >> (4 - (addr & 3));
page->byte_dirty_mask[byte_offset + 1] |= byte_mask_2;
if ((page->byte_code_present_mask[byte_offset + 1] & byte_mask_2) && !page_in_evict_list(page))
page_add_to_evict_list(page);
}
}
}
#else
void
mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
page->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask;
page->mem[addr & 0xfff] = val;
}
}
void
mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint16_t *) &page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint16_t *) &page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
if ((addr & 0xf) == 0xf)
mask |= (mask << 1);
page->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask;
*(uint16_t *) &page->mem[addr & 0xfff] = val;
}
}
void
mem_write_raml_page(uint32_t addr, uint32_t val, page_t *page)
{
if (page == NULL)
return;
# ifdef USE_DYNAREC
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint32_t *) &page->mem[addr & 0xfff]) || codegen_in_recompile) {
# else
if ((page->mem == NULL) || (page->mem == page_ff) || (val != *(uint32_t *) &page->mem[addr & 0xfff])) {
# endif
uint64_t mask = (uint64_t) 1 << ((addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
if ((addr & 0xf) >= 0xd)
mask |= (mask << 1);
page->dirty_mask[(addr >> PAGE_MASK_INDEX_SHIFT) & PAGE_MASK_INDEX_MASK] |= mask;
*(uint32_t *) &page->mem[addr & 0xfff] = val;
}
}
#endif
void
mem_write_ram(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write B %02X to %08X\n", val, addr);
#endif
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[addr >> 12]);
} else
ram[addr] = val;
}
void
mem_write_ramw(uint32_t addr, uint16_t val, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write W %04X to %08X\n", val, addr);
#endif
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[addr >> 12]);
} else
*(uint16_t *) &ram[addr] = val;
}
void
mem_write_raml(uint32_t addr, uint32_t val, UNUSED(void *priv))
{
#ifdef ENABLE_MEM_LOG
if ((addr >= 0xa0000) && (addr <= 0xbffff))
mem_log("Write L %08X to %08X\n", val, addr);
#endif
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[addr >> 12]);
} else
*(uint32_t *) &ram[addr] = val;
}
static uint8_t
mem_read_remapped(uint32_t addr, UNUSED(void *priv))
{
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
static uint16_t
mem_read_remappedw(uint32_t addr, UNUSED(void *priv))
{
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *) &ram[addr];
}
static uint32_t
mem_read_remappedl(uint32_t addr, UNUSED(void *priv))
{
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *) &ram[addr];
}
static uint8_t
mem_read_remapped2(uint32_t addr, UNUSED(void *priv))
{
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return ram[addr];
}
static uint16_t
mem_read_remappedw2(uint32_t addr, UNUSED(void *priv))
{
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint16_t *) &ram[addr];
}
static uint32_t
mem_read_remappedl2(uint32_t addr, UNUSED(void *priv))
{
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec)
addreadlookup(mem_logical_addr, addr);
return *(uint32_t *) &ram[addr];
}
static void
mem_write_remapped(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]);
} else
ram[addr] = val;
}
static void
mem_write_remappedw(uint32_t addr, uint16_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint16_t *) &ram[addr] = val;
}
static void
mem_write_remappedl(uint32_t addr, uint32_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xA0000 + (addr - remap_start_addr);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint32_t *) &ram[addr] = val;
}
static void
mem_write_remapped2(uint32_t addr, uint8_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramb_page(addr, val, &pages[oldaddr >> 12]);
} else
ram[addr] = val;
}
static void
mem_write_remappedw2(uint32_t addr, uint16_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_ramw_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint16_t *) &ram[addr] = val;
}
static void
mem_write_remappedl2(uint32_t addr, uint32_t val, UNUSED(void *priv))
{
uint32_t oldaddr = addr;
addr = 0xD0000 + (addr - remap_start_addr2);
if (cpu_use_exec) {
addwritelookup(mem_logical_addr, addr);
mem_write_raml_page(addr, val, &pages[oldaddr >> 12]);
} else
*(uint32_t *) &ram[addr] = val;
}
void
mem_invalidate_range(uint32_t start_addr, uint32_t end_addr)
{
#ifdef USE_NEW_DYNAREC
page_t *page;
start_addr &= ~PAGE_MASK_MASK;
end_addr = (end_addr + PAGE_MASK_MASK) & ~PAGE_MASK_MASK;
for (; start_addr <= end_addr; start_addr += 0x1000) {
if ((start_addr >> 12) >= pages_sz)
continue;
page = &pages[start_addr >> 12];
if (page) {
page->dirty_mask = 0xffffffffffffffffULL;
if ((page->mem != page_ff) && page->byte_dirty_mask)
memset(page->byte_dirty_mask, 0xff, 64 * sizeof(uint64_t));
if (!page_in_evict_list(page))
page_add_to_evict_list(page);
}
}
#else
uint32_t cur_addr;
start_addr &= ~PAGE_MASK_MASK;
end_addr = (end_addr + PAGE_MASK_MASK) & ~PAGE_MASK_MASK;
for (; start_addr <= end_addr; start_addr += 0x1000) {
/* Do nothing if the pages array is empty or DMA reads/writes to/from PCI device memory addresses
may crash the emulator. */
cur_addr = (start_addr >> 12);
if (cur_addr < pages_sz)
memset(pages[cur_addr].dirty_mask, 0xff, sizeof(pages[cur_addr].dirty_mask));
}
#endif
}
static __inline int
mem_mapping_access_allowed(uint32_t flags, uint16_t access)
{
int ret = 0;
if (!(access & ACCESS_DISABLED)) {
if (access & ACCESS_CACHE)
ret = (flags & MEM_MAPPING_CACHE);
else if (access & ACCESS_SMRAM)
ret = (flags & MEM_MAPPING_SMRAM);
else if (!(access & ACCESS_INTERNAL)) {
if (flags & MEM_MAPPING_IS_ROM) {
if (access & ACCESS_ROMCS)
ret = (flags & MEM_MAPPING_ROMCS);
else
ret = !(flags & MEM_MAPPING_ROMCS);
} else
ret = 1;
ret = ret && !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_SMRAM);
} else
ret = !(flags & MEM_MAPPING_EXTERNAL) && !(flags & MEM_MAPPING_SMRAM);
} else {
/* Still allow SMRAM if access is DISABLED but also has CACHE and/or SMRAM flags set. */
if (access & ACCESS_CACHE)
ret = (flags & MEM_MAPPING_CACHE);
else if (access & ACCESS_SMRAM)
ret = (flags & MEM_MAPPING_SMRAM);
}
return ret;
}
void
mem_mapping_recalc(uint64_t base, uint64_t size)
{
mem_mapping_t *map;
int n;
uint64_t c;
uint8_t wp;
if (!size || (base_mapping == NULL))
return;
map = base_mapping;
/* Clear out old mappings. */
for (c = base; c < base + size; c += MEM_GRANULARITY_SIZE) {
_mem_exec[c >> MEM_GRANULARITY_BITS] = NULL;
write_mapping[c >> MEM_GRANULARITY_BITS] = NULL;
read_mapping[c >> MEM_GRANULARITY_BITS] = NULL;
write_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL;
read_mapping_bus[c >> MEM_GRANULARITY_BITS] = NULL;
}
/* Walk mapping list. */
while (map != NULL) {
/* In range? */
if (map->enable && (uint64_t) map->base < ((uint64_t) base + (uint64_t) size) &&
((uint64_t) map->base + (uint64_t) map->size) > (uint64_t) base) {
uint64_t start = (map->base < base) ? map->base : base;
uint64_t end = (((uint64_t) map->base + (uint64_t) map->size) < (base + size)) ?
((uint64_t) map->base + (uint64_t) map->size) : (base + size);
if (start < map->base)
start = map->base;
for (c = start; c < end; c += MEM_GRANULARITY_SIZE) {
/* CPU */
n = !!in_smm;
wp = _mem_wp[c >> MEM_GRANULARITY_BITS];
if (map->exec && mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].x))
_mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base);
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping[c >> MEM_GRANULARITY_BITS] = map;
/* Bus */
n |= STATE_BUS;
wp = _mem_wp_bus[c >> MEM_GRANULARITY_BITS];
if (!wp && (map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags,
_mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
}
}
map = map->next;
}
flushmmucache_nopc();
#ifdef ENABLE_MEM_LOG
pclog("\nMemory map:\n");
mem_mapping_t *write = (mem_mapping_t *) -1, *read = (mem_mapping_t *) -1, *write_bus = (mem_mapping_t *) -1, *read_bus = (mem_mapping_t *) -1;
for (c = 0; c < (sizeof(write_mapping) / sizeof(write_mapping[0])); c++) {
if ((write_mapping[c] == write) && (read_mapping[c] == read) && (write_mapping_bus[c] == write_bus) && (read_mapping_bus[c] == read_bus))
continue;
write = write_mapping[c];
read = read_mapping[c];
write_bus = write_mapping_bus[c];
read_bus = read_mapping_bus[c];
pclog("%08X | ", c << MEM_GRANULARITY_BITS);
if (read) {
pclog("R%c%c%c %08X+% 8X",
read->read_b ? 'b' : ' ', read->read_w ? 'w' : ' ', read->read_l ? 'l' : ' ',
read->base, read->size);
} else {
pclog(" ");
}
if (write) {
pclog(" | W%c%c%c %08X+% 8X",
write->write_b ? 'b' : ' ', write->write_w ? 'w' : ' ', write->write_l ? 'l' : ' ',
write->base, write->size);
} else {
pclog(" | ");
}
pclog(" | %c\n", _mem_exec[c] ? 'X' : ' ');
if ((write != write_bus) || (read != read_bus)) {
pclog(" ^ bus | ");
if (read_bus) {
pclog("R%c%c%c %08X+% 8X",
read_bus->read_b ? 'b' : ' ', read_bus->read_w ? 'w' : ' ', read_bus->read_l ? 'l' : ' ',
read_bus->base, read_bus->size);
} else {
pclog(" ");
}
if (write_bus) {
pclog(" | W%c%c%c %08X+% 8X",
write_bus->write_b ? 'b' : ' ', write_bus->write_w ? 'w' : ' ', write_bus->write_l ? 'l' : ' ',
write_bus->base, write_bus->size);
} else {
pclog(" | ");
}
pclog(" |\n");
}
}
pclog("\n");
#endif
}
void
mem_set_wp(uint64_t base, uint64_t size, uint8_t flags, uint8_t wp)
{
uint64_t c;
uint64_t end = base + size;
for (c = base; c < end; c += MEM_GRANULARITY_SIZE) {
if (flags & ACCESS_BUS)
_mem_wp_bus[c >> MEM_GRANULARITY_BITS] = wp;
if (flags & ACCESS_CPU)
_mem_wp[c >> MEM_GRANULARITY_BITS] = wp;
}
mem_mapping_recalc(base, size);
}
void
mem_mapping_set(mem_mapping_t *map,
uint32_t base,
uint32_t size,
uint8_t (*read_b)(uint32_t addr, void *priv),
uint16_t (*read_w)(uint32_t addr, void *priv),
uint32_t (*read_l)(uint32_t addr, void *priv),
void (*write_b)(uint32_t addr, uint8_t val, void *priv),
void (*write_w)(uint32_t addr, uint16_t val, void *priv),
void (*write_l)(uint32_t addr, uint32_t val, void *priv),
uint8_t *exec,
uint32_t fl,
void *priv)
{
if (size != 0x00000000)
map->enable = 1;
else
map->enable = 0;
map->base = base;
map->size = size;
map->mask = (map->size ? 0xffffffff : 0x00000000);
map->read_b = read_b;
map->read_w = read_w;
map->read_l = read_l;
map->write_b = write_b;
map->write_w = write_w;
map->write_l = write_l;
map->exec = exec;
map->flags = fl;
map->priv = priv;
map->next = NULL;
mem_log("mem_mapping_add(): Linked list structure: %08X -> %08X -> %08X\n", map->prev, map, map->next);
/* If the mapping is disabled, there is no need to recalc anything. */
if (size != 0x00000000)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_add(mem_mapping_t *map,
uint32_t base,
uint32_t size,
uint8_t (*read_b)(uint32_t addr, void *priv),
uint16_t (*read_w)(uint32_t addr, void *priv),
uint32_t (*read_l)(uint32_t addr, void *priv),
void (*write_b)(uint32_t addr, uint8_t val, void *priv),
void (*write_w)(uint32_t addr, uint16_t val, void *priv),
void (*write_l)(uint32_t addr, uint32_t val, void *priv),
uint8_t *exec,
uint32_t fl,
void *priv)
{
/* Do a sanity check */
if ((base_mapping == NULL) && (last_mapping != NULL)) {
fatal("mem_mapping_add(): NULL base mapping with non-NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (last_mapping == NULL)) {
fatal("mem_mapping_add(): Non-NULL base mapping with NULL last mapping\n");
return;
} else if ((base_mapping != NULL) && (base_mapping->prev != NULL)) {
fatal("mem_mapping_add(): Base mapping with a preceding mapping\n");
return;
} else if ((last_mapping != NULL) && (last_mapping->next != NULL)) {
fatal("mem_mapping_add(): Last mapping with a following mapping\n");
return;
}
/* Add mapping to the beginning of the list if necessary.*/
if (base_mapping == NULL)
base_mapping = map;
/* Add mapping to the end of the list.*/
if (last_mapping == NULL)
map->prev = NULL;
else {
map->prev = last_mapping;
last_mapping->next = map;
}
last_mapping = map;
mem_mapping_set(map, base, size, read_b, read_w, read_l,
write_b, write_w, write_l, exec, fl, priv);
}
void
mem_mapping_do_recalc(mem_mapping_t *map)
{
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_handler(mem_mapping_t *map,
uint8_t (*read_b)(uint32_t addr, void *priv),
uint16_t (*read_w)(uint32_t addr, void *priv),
uint32_t (*read_l)(uint32_t addr, void *priv),
void (*write_b)(uint32_t addr, uint8_t val, void *priv),
void (*write_w)(uint32_t addr, uint16_t val, void *priv),
void (*write_l)(uint32_t addr, uint32_t val, void *priv))
{
map->read_b = read_b;
map->read_w = read_w;
map->read_l = read_l;
map->write_b = write_b;
map->write_w = write_w;
map->write_l = write_l;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_write_handler(mem_mapping_t *map,
void (*write_b)(uint32_t addr, uint8_t val, void *priv),
void (*write_w)(uint32_t addr, uint16_t val, void *priv),
void (*write_l)(uint32_t addr, uint32_t val, void *priv))
{
map->write_b = write_b;
map->write_w = write_w;
map->write_l = write_l;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size)
{
/* Remove old mapping. */
map->enable = 0;
mem_mapping_recalc(map->base, map->size);
/* Set new mapping. */
map->enable = 1;
map->base = base;
map->size = size;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec)
{
map->exec = exec;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_mask(mem_mapping_t *map, uint32_t mask)
{
map->mask = mask;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_p(mem_mapping_t *map, void *priv)
{
map->priv = priv;
}
void
mem_mapping_disable(mem_mapping_t *map)
{
map->enable = 0;
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_enable(mem_mapping_t *map)
{
map->enable = 1;
mem_mapping_recalc(map->base, map->size);
}
void
mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t access)
{
uint16_t mask;
uint16_t smstate = 0x0000;
const uint16_t smstates[4] = { 0x0000, (MEM_READ_SMRAM | MEM_WRITE_SMRAM),
MEM_READ_SMRAM_EX, (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX) };
if (mode)
mask = 0x2d6b;
else
mask = 0x1084;
if (mode) {
if (mode == 1)
access = !!access;
if (mode == 3) {
if (access & ACCESS_SMRAM_X)
smstate |= MEM_EXEC_SMRAM;
if (access & ACCESS_SMRAM_R)
smstate |= MEM_READ_SMRAM_2;
if (access & ACCESS_SMRAM_W)
smstate |= MEM_WRITE_SMRAM;
} else
smstate = smstates[access & 0x07];
} else
smstate = access & 0x6f7b;
for (uint32_t c = 0; c < size; c += MEM_GRANULARITY_SIZE) {
for (uint8_t i = 0; i < 4; i++) {
if (bitmap & (1 << i)) {
_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate;
}
}
#ifdef ENABLE_MEM_LOG
if (((c + base) >= 0xa0000) && ((c + base) <= 0xbffff)) {
mem_log("Set mem state for block at %08X to %04X with bitmap %02X\n",
c + base, smstate, bitmap);
}
#endif
}
mem_mapping_recalc(base, size);
}
void
mem_a20_init(void)
{
if (is286) {
mem_a20_key = mem_a20_alt = mem_a20_state = 0;
rammask = cpu_16bitbus ? 0xffffff : 0xffffffff;
if (is6117)
rammask |= 0x03000000;
flushmmucache();
#if 0
mem_a20_state = mem_a20_key | mem_a20_alt;
#endif
} else {
rammask = 0xfffff;
flushmmucache();
mem_a20_key = mem_a20_alt = mem_a20_state = 0;
}
}
/* Close all the memory mappings. */
void
mem_close(void)
{
mem_mapping_t *map = base_mapping;
mem_mapping_t *next;
while (map != NULL) {
next = map->next;
map->prev = map->next = NULL;
map = next;
}
base_mapping = last_mapping = 0;
}
static void
mem_add_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
{
mem_mapping_add(mapping, base, size,
mem_read_ram, mem_read_ramw, mem_read_raml,
mem_write_ram, mem_write_ramw, mem_write_raml,
ram + base, MEM_MAPPING_INTERNAL, NULL);
}
static void
mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
{
mem_set_mem_state_both(base, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_add_ram_mapping(mapping, base, size);
}
/* Reset the memory state. */
void
mem_reset(void)
{
size_t m;
memset(page_ff, 0xff, sizeof(page_ff));
#ifdef USE_NEW_DYNAREC
if (byte_dirty_mask) {
free(byte_dirty_mask);
byte_dirty_mask = NULL;
}
if (byte_code_present_mask) {
free(byte_code_present_mask);
byte_code_present_mask = NULL;
}
#endif
/* Free the old pages array, if necessary. */
if (pages) {
free(pages);
pages = NULL;
}
if (ram != NULL) {
plat_munmap(ram, ram_size);
ram = NULL;
ram_size = 0;
}
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (ram2 != NULL) {
plat_munmap(ram2, ram2_size);
ram2 = NULL;
ram2_size = 0;
}
if (mem_size > 2097152)
mem_size = 2097152;
#endif
m = 1024UL * (size_t) mem_size;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
ram_size = 1 << 30;
ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block of the first 1 GB */
if (ram == NULL) {
fatal("Failed to allocate primary RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram, 0x00, ram_size);
ram2_size = m - (1 << 30);
/* Allocate 16 extra bytes of RAM to mitigate some dynarec recompiler memory access quirks. */
ram2 = (uint8_t *) plat_mmap(ram2_size + 16, 0); /* allocate and clear the RAM block above 1 GB */
if (ram2 == NULL) {
if (config_changed == 2)
fatal(EMU_NAME " must be restarted for the memory amount change to be applied.\n");
else
fatal("Failed to allocate secondary RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram2, 0x00, ram2_size + 16);
} else
#endif
{
ram_size = m;
/* Allocate 16 extra bytes of RAM to mitigate some dynarec recompiler memory access quirks. */
ram = (uint8_t *) plat_mmap(ram_size + 16, 0); /* allocate and clear the RAM block */
if (ram == NULL) {
fatal("Failed to allocate RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram, 0x00, ram_size + 16);
if (mem_size > 1048576)
ram2 = &(ram[1 << 30]);
}
/*
* Allocate the page table based on how much RAM we have.
* We re-allocate the table on each (hard) reset, as the
* memory amount could have changed.
*/
if (is286) {
if (cpu_16bitbus) {
/* 80286/386SX; maximum address space is 16MB + 16 MB for EMS. */
m = 8192;
/* ALi M6117; maximum address space is 64MB. */
if (is6117)
m <<= 2;
} else {
/* 80386DX+; maximum address space is 4GB. */
m = 1048576;
}
} else {
/* 8088/86; maximum address space is 1MB. */
m = 256;
}
addr_space_size = m;
/*
* Allocate and initialize the (new) page table.
*/
pages_sz = m;
pages = (page_t *) malloc(m * sizeof(page_t));
memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *));
memset(page_lookupp, 0x04, (1 << 20) * sizeof(uint8_t));
memset(pages, 0x00, pages_sz * sizeof(page_t));
#ifdef USE_NEW_DYNAREC
byte_dirty_mask = malloc((mem_size * 1024) / 8);
memset(byte_dirty_mask, 0, (mem_size * 1024) / 8);
byte_code_present_mask = malloc((mem_size * 1024) / 8);
memset(byte_code_present_mask, 0, (mem_size * 1024) / 8);
#endif
for (uint32_t c = 0; c < pages_sz; c++) {
if ((c << 12) >= (mem_size << 10))
pages[c].mem = page_ff;
else {
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
if ((c << 12) < (1 << 30))
pages[c].mem = &ram[c << 12];
else
pages[c].mem = &ram2[(c << 12) - (1 << 30)];
} else
pages[c].mem = &ram[c << 12];
#else
pages[c].mem = &ram[c << 12];
#endif
}
if (c < m) {
pages[c].write_b = mem_write_ramb_page;
pages[c].write_w = mem_write_ramw_page;
pages[c].write_l = mem_write_raml_page;
}
#ifdef USE_NEW_DYNAREC
pages[c].evict_prev = EVICT_NOT_IN_LIST;
pages[c].byte_dirty_mask = &byte_dirty_mask[c * 64];
pages[c].byte_code_present_mask = &byte_code_present_mask[c * 64];
#endif
}
memset(_mem_exec, 0x00, sizeof(_mem_exec));
memset(_mem_wp, 0x00, sizeof(_mem_wp));
memset(_mem_wp_bus, 0x00, sizeof(_mem_wp_bus));
memset(write_mapping, 0x00, sizeof(write_mapping));
memset(read_mapping, 0x00, sizeof(read_mapping));
memset(write_mapping_bus, 0x00, sizeof(write_mapping_bus));
memset(read_mapping_bus, 0x00, sizeof(read_mapping_bus));
base_mapping = last_mapping = NULL;
/* Set the entire memory space as external. */
memset(_mem_state, 0x00, sizeof(_mem_state));
/* Set the low RAM space as internal. */
mem_init_ram_mapping(&ram_low_mapping, 0x000000, (mem_size > 640) ? 0xa0000 : mem_size * 1024);
if (mem_size > 1024) {
if (cpu_16bitbus && !is6117 && mem_size > 16256)
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (16256 - 1024) * 1024);
else if (cpu_16bitbus && is6117 && mem_size > 65408)
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (65408 - 1024) * 1024);
else {
if (mem_size > 1048576) {
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (1048576 - 1024) * 1024);
mem_set_mem_state_both((1 << 30), (mem_size - 1048576) * 1024,
MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_add(&ram_2gb_mapping, (1 << 30),
((mem_size - 1048576) * 1024),
mem_read_ram_2gb, mem_read_ram_2gbw, mem_read_ram_2gbl,
mem_write_ram, mem_write_ramw, mem_write_raml,
ram2, MEM_MAPPING_INTERNAL, NULL);
} else
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024);
}
}
if (mem_size > 768) {
mem_add_ram_mapping(&ram_mid_mapping, 0xa0000, 0x60000);
mem_add_ram_mapping(&ram_mid_mapping2, 0xa0000, 0x60000);
mem_mapping_disable(&ram_mid_mapping2);
}
mem_mapping_add(&ram_remapped_mapping, mem_size * 1024, 256 * 1024,
mem_read_remapped, mem_read_remappedw, mem_read_remappedl,
mem_write_remapped, mem_write_remappedw, mem_write_remappedl,
ram + 0xa0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_disable(&ram_remapped_mapping);
/* Mapping for SiS 471 relocation which relocates A0000-BFFFF, D0000-EFFFF, which is non-contiguous. */
mem_mapping_add(&ram_remapped_mapping2, mem_size * 1024, 256 * 1024,
mem_read_remapped2, mem_read_remappedw2, mem_read_remappedl2,
mem_write_remapped2, mem_write_remappedw2, mem_write_remappedl2,
ram + 0xd0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_disable(&ram_remapped_mapping2);
mem_a20_init();
#ifdef USE_NEW_DYNAREC
purgable_page_list_head = 0;
purgeable_page_count = 0;
#endif
}
void
mem_init(void)
{
/* Perform a one-time init. */
ram = rom = NULL;
ram2 = NULL;
pages = NULL;
/* Allocate the lookup tables. */
page_lookup = (page_t **) malloc((1 << 20) * sizeof(page_t *));
page_lookupp = (uint8_t *) malloc((1 << 20) * sizeof(uint8_t));
readlookup2 = malloc((1 << 20) * sizeof(uintptr_t));
readlookupp = malloc((1 << 20) * sizeof(uint8_t));
writelookup2 = malloc((1 << 20) * sizeof(uintptr_t));
writelookupp = malloc((1 << 20) * sizeof(uint8_t));
}
static void
umc_page_recalc(uint32_t c, int set)
{
if (set) {
pages[c].mem = &ram[(c & 0xff) << 12];
pages[c].write_b = mem_write_ramb_page;
pages[c].write_w = mem_write_ramw_page;
pages[c].write_l = mem_write_raml_page;
} else {
pages[c].mem = page_ff;
pages[c].write_b = NULL;
pages[c].write_w = NULL;
pages[c].write_l = NULL;
}
#ifdef USE_NEW_DYNAREC
pages[c].evict_prev = EVICT_NOT_IN_LIST;
pages[c].byte_dirty_mask = &byte_dirty_mask[(c & 0xff) * 64];
pages[c].byte_code_present_mask = &byte_code_present_mask[(c & 0xff) * 64];
#endif
}
void
umc_smram_recalc(uint32_t start, int set)
{
for (uint32_t c = start; c < (start + 0x0020); c++)
umc_page_recalc(c, set);
}
void
mem_remap_top_ex(int kb, uint32_t start)
{
uint32_t c;
int offset;
int size = mem_size - 640;
int set = 1;
static int old_kb = 0;
int sis_mode = 0;
uint32_t start_addr = 0;
uint32_t addr = 0;
mem_log("MEM: remapping top %iKB (mem=%i)\n", kb, mem_size);
if (mem_size <= 640)
return;
/* SiS 471 special mode. */
if (kb == -256) {
kb = 256;
sis_mode = 1;
}
/* Do not remap if we're have more than (16 MB - RAM) memory. */
if ((kb != 0) && (mem_size >= (16384 - kb)))
return;
if (kb == 0) {
kb = old_kb;
set = 0;
} else
old_kb = kb;
if (size > kb)
size = kb;
remap_start_addr = start << 10;
remap_start_addr2 = (start << 10) + 0x00020000;
for (c = ((start * 1024) >> 12); c < (((start + size) * 1024) >> 12); c++) {
offset = c - ((start * 1024) >> 12);
/* Use A0000-BFFFF, D0000-EFFFF instead of C0000-DFFFF, E0000-FFFFF. */
addr = 0xa0000 + (offset << 12);
if (sis_mode) {
/* A0000-DFFFF -> A0000-BFFFF, D0000-EFFFF */
if (addr >= 0x000c0000)
addr += 0x00010000;
}
if (start_addr == 0)
start_addr = addr;
pages[c].mem = set ? &ram[addr] : page_ff;
pages[c].write_b = set ? mem_write_ramb_page : NULL;
pages[c].write_w = set ? mem_write_ramw_page : NULL;
pages[c].write_l = set ? mem_write_raml_page : NULL;
#ifdef USE_NEW_DYNAREC
pages[c].evict_prev = EVICT_NOT_IN_LIST;
pages[c].byte_dirty_mask = &byte_dirty_mask[(addr >> 12) * 64];
pages[c].byte_code_present_mask = &byte_code_present_mask[(addr >> 12) * 64];
#endif
}
mem_set_mem_state_both(start * 1024, size * 1024, set ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
for (c = 0xa0; c < 0xf0; c++) {
if ((c >= 0xc0) && (c <= 0xcf))
continue;
if (sis_mode || ((c << 12) >= (mem_size << 10)))
pages[c].mem = page_ff;
else {
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
if ((c << 12) < (1 << 30))
pages[c].mem = &ram[c << 12];
else
pages[c].mem = &ram2[(c << 12) - (1 << 30)];
} else
pages[c].mem = &ram[c << 12];
#else
pages[c].mem = &ram[c << 12];
#endif
}
if (!sis_mode && (c < addr_space_size)) {
pages[c].write_b = mem_write_ramb_page;
pages[c].write_w = mem_write_ramw_page;
pages[c].write_l = mem_write_raml_page;
} else {
pages[c].write_b = NULL;
pages[c].write_w = NULL;
pages[c].write_l = NULL;
}
#ifdef USE_NEW_DYNAREC
pages[c].evict_prev = EVICT_NOT_IN_LIST;
pages[c].byte_dirty_mask = &byte_dirty_mask[c * 64];
pages[c].byte_code_present_mask = &byte_code_present_mask[c * 64];
#endif
}
if (set) {
if (sis_mode) {
mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, 0x00020000);
mem_mapping_set_exec(&ram_remapped_mapping, ram + 0x000a0000);
mem_mapping_set_addr(&ram_remapped_mapping2, (start * 1024) + 0x00020000, 0x00020000);
mem_mapping_set_exec(&ram_remapped_mapping2, ram + 0x000d0000);
mem_mapping_set_addr(&ram_mid_mapping, 0x000c0000, 0x00010000);
mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000c0000);
mem_mapping_set_addr(&ram_mid_mapping2, 0x000f0000, 0x00010000);
mem_mapping_set_exec(&ram_mid_mapping2, ram + 0x000f0000);
} else {
mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, size * 1024);
mem_mapping_set_exec(&ram_remapped_mapping, ram + start_addr);
mem_mapping_disable(&ram_remapped_mapping2);
mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000);
mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000);
mem_mapping_disable(&ram_mid_mapping2);
}
} else {
mem_mapping_disable(&ram_remapped_mapping);
mem_mapping_disable(&ram_remapped_mapping2);
mem_mapping_set_addr(&ram_mid_mapping, 0x000a0000, 0x00060000);
mem_mapping_set_exec(&ram_mid_mapping, ram + 0x000a0000);
mem_mapping_disable(&ram_mid_mapping2);
}
flushmmucache();
}
void
mem_remap_top(int kb)
{
mem_remap_top_ex(kb, (mem_size >= 1024) ? mem_size : 1024);
}
void
mem_reset_page_blocks(void)
{
if (pages == NULL)
return;
for (uint32_t c = 0; c < pages_sz; c++) {
pages[c].write_b = mem_write_ramb_page;
pages[c].write_w = mem_write_ramw_page;
pages[c].write_l = mem_write_raml_page;
#ifdef USE_NEW_DYNAREC
pages[c].block = BLOCK_INVALID;
pages[c].block_2 = BLOCK_INVALID;
pages[c].head = BLOCK_INVALID;
#else
pages[c].block[0] = pages[c].block[1] = pages[c].block[2] = pages[c].block[3] = NULL;
pages[c].block_2[0] = pages[c].block_2[1] = pages[c].block_2[2] = pages[c].block_2[3] = NULL;
pages[c].head = NULL;
#endif
}
}
void
mem_a20_recalc(void)
{
int state;
if (!is286) {
rammask = 0xfffff;
flushmmucache();
mem_a20_key = mem_a20_alt = mem_a20_state = 0;
return;
}
state = mem_a20_key | mem_a20_alt;
if (state && !mem_a20_state) {
rammask = cpu_16bitbus ? 0xffffff : 0xffffffff;
if (is6117)
rammask |= 0x03000000;
flushmmucache();
} else if (!state && mem_a20_state) {
rammask = cpu_16bitbus ? 0xefffff : 0xffefffff;
if (is6117)
rammask |= 0x03000000;
flushmmucache();
}
mem_a20_state = state;
}
``` | /content/code_sandbox/src/mem/mem.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 29,317 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of National Semiconductors NMC93Cxx EEPROMs.
*
*
* Authors: Cacodemon345
*
*/
/* Ported over from QEMU */
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/net_eeprom_nmc93cxx.h>
#include <86box/plat_unused.h>
struct nmc93cxx_eeprom_t {
ati_eeprom_t dev;
uint8_t addrbits;
uint16_t size;
char filename[1024];
};
typedef struct nmc93cxx_eeprom_t nmc93cxx_eeprom_t;
#ifdef ENABLE_NMC93CXX_EEPROM_LOG
int nmc93cxx_eeprom_do_log = ENABLE_NMC93CXX_EEPROM_LOG;
static void
nmc93cxx_eeprom_log(int lvl, const char *fmt, ...)
{
va_list ap;
if (nmc93cxx_eeprom_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define nmc93cxx_eeprom_log(lvl, fmt, ...)
#endif
static void *
nmc93cxx_eeprom_init(const device_t *info)
{
uint16_t nwords = 64;
uint8_t addrbits = 6;
uint8_t filldefault = 1;
nmc93cxx_eeprom_params_t *params_details = (nmc93cxx_eeprom_params_t *) info->local;
nmc93cxx_eeprom_t *eeprom = NULL;
if (info->local == 0)
return NULL;
nwords = params_details->nwords;
switch (nwords) {
case 16:
case 64:
addrbits = 6;
break;
case 128:
case 256:
addrbits = 8;
break;
default:
nwords = 64;
addrbits = 6;
break;
}
eeprom = calloc(1, sizeof(nmc93cxx_eeprom_t) + ((nwords + 1) * 2));
if (!eeprom)
return NULL;
eeprom->size = nwords;
eeprom->addrbits = addrbits;
/* Output DO is tristate, read results in 1. */
eeprom->dev.out = 1;
if (params_details->filename) {
FILE *fp = nvr_fopen(params_details->filename, "rb");
strncpy(eeprom->filename, params_details->filename, sizeof(eeprom->filename) - 1);
if (fp) {
filldefault = !fread(eeprom->dev.data, sizeof(uint16_t), nwords, fp);
fclose(fp);
}
}
if (filldefault) {
memcpy(eeprom->dev.data, params_details->default_content, nwords * sizeof(uint16_t));
}
return eeprom;
}
void
nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->dev.count;
uint8_t eedo = eeprom->dev.out;
uint16_t address = eeprom->dev.address;
uint8_t command = eeprom->dev.opcode;
nmc93cxx_eeprom_log(1, "CS=%u SK=%u DI=%u DO=%u, tick = %u\n",
eecs, eesk, eedi, eedo, tick);
if (!eeprom->dev.oldena && eecs) {
/* Start chip select cycle. */
nmc93cxx_eeprom_log(1, "Cycle start, waiting for 1st start bit (0)\n");
tick = 0;
command = 0x0;
address = 0x0;
} else if (eeprom->dev.oldena && !eecs) {
/* End chip select cycle. This triggers write / erase. */
if (!eeprom->dev.wp) {
uint8_t subcommand = address >> (eeprom->addrbits - 2);
if (command == 0 && subcommand == 2) {
/* Erase all. */
for (address = 0; address < eeprom->size; address++) {
eeprom->dev.data[address] = 0xffff;
}
} else if (command == 3) {
/* Erase word. */
eeprom->dev.data[address] = 0xffff;
} else if (tick >= 2 + 2 + eeprom->addrbits + 16) {
if (command == 1) {
/* Write word. */
eeprom->dev.data[address] &= eeprom->dev.dat;
} else if (command == 0 && subcommand == 1) {
/* Write all. */
for (address = 0; address < eeprom->size; address++) {
eeprom->dev.data[address] &= eeprom->dev.dat;
}
}
}
}
/* Output DO is tristate, read results in 1. */
eedo = 1;
} else if (eecs && !eeprom->dev.oldclk && eesk) {
/* Raising edge of clock shifts data in. */
if (tick == 0) {
/* Wait for 1st start bit. */
if (eedi == 0) {
nmc93cxx_eeprom_log(1, "Got correct 1st start bit, waiting for 2nd start bit (1)\n");
tick++;
} else {
nmc93cxx_eeprom_log(1, "wrong 1st start bit (is 1, should be 0)\n");
tick = 2;
#if 0
~ assert(!"wrong start bit");
#endif
}
} else if (tick == 1) {
/* Wait for 2nd start bit. */
if (eedi != 0) {
nmc93cxx_eeprom_log(1, "Got correct 2nd start bit, getting command + address\n");
tick++;
} else {
nmc93cxx_eeprom_log(1, "1st start bit is longer than needed\n");
}
} else if (tick < 2 + 2) {
/* Got 2 start bits, transfer 2 opcode bits. */
tick++;
command <<= 1;
if (eedi) {
command += 1;
}
} else if (tick < 2 + 2 + eeprom->addrbits) {
/* Got 2 start bits and 2 opcode bits, transfer all address bits. */
tick++;
address = ((address << 1) | eedi);
if (tick == 2 + 2 + eeprom->addrbits) {
nmc93cxx_eeprom_log(1, "Address = 0x%02x (value 0x%04x)\n",
address, eeprom->dev.data[address]);
if (command == 2) {
eedo = 0;
}
address = address % eeprom->size;
if (command == 0) {
/* Command code in upper 2 bits of address. */
switch (address >> (eeprom->addrbits - 2)) {
case 0:
nmc93cxx_eeprom_log(1, "write disable command\n");
eeprom->dev.wp = 1;
break;
case 1:
nmc93cxx_eeprom_log(1, "write all command\n");
break;
case 2:
nmc93cxx_eeprom_log(1, "erase all command\n");
break;
case 3:
nmc93cxx_eeprom_log(1, "write enable command\n");
eeprom->dev.wp = 0;
break;
default:
break;
}
} else {
/* Read, write or erase word. */
eeprom->dev.dat = eeprom->dev.data[address];
}
}
} else if (tick < 2 + 2 + eeprom->addrbits + 16) {
/* Transfer 16 data bits. */
tick++;
if (command == 2) {
/* Read word. */
eedo = ((eeprom->dev.dat & 0x8000) != 0);
}
eeprom->dev.dat <<= 1;
eeprom->dev.dat += eedi;
} else {
nmc93cxx_eeprom_log(1, "additional unneeded tick, not processed\n");
}
}
/* Save status of EEPROM. */
eeprom->dev.count = tick;
eeprom->dev.oldena = eecs;
eeprom->dev.oldclk = eesk;
eeprom->dev.out = eedo;
eeprom->dev.address = address;
eeprom->dev.opcode = command;
}
uint16_t
nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom)
{
/* Return status of pin DO (0 or 1). */
return eeprom->dev.out;
}
static void
nmc93cxx_eeprom_close(void *priv)
{
nmc93cxx_eeprom_t *eeprom = (nmc93cxx_eeprom_t *) priv;
FILE *fp = nvr_fopen(eeprom->filename, "wb");
if (fp) {
fwrite(eeprom->dev.data, 2, eeprom->size, fp);
fclose(fp);
}
free(priv);
}
uint16_t *
nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom)
{
if (UNLIKELY(eeprom == NULL))
return NULL;
/* Get EEPROM data array. */
return &eeprom->dev.data[0];
}
const device_t nmc93cxx_device = {
.name = "National Semiconductor NMC93Cxx",
.internal_name = "nmc93cxx",
.flags = 0,
.local = 0,
.init = nmc93cxx_eeprom_init,
.close = nmc93cxx_eeprom_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/network/net_eeprom_nmc93cxx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,432 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of Realtek RTL8139C+ NIC.
*
* Authors: Igor Kovalenko,
* Mark Malakanov,
* Jurgen Lock,
* Frediano Ziglio,
* Benjamin Poirier.
* Cacodemon345,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <stdio.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/random.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/dma.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/network.h>
#include <86box/net_eeprom_nmc93cxx.h>
#include <86box/bswap.h>
#include <86box/nvr.h>
#include "cpu.h"
#include <86box/plat_unused.h>
#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */
#define SET_MASKED(input, mask, curr) \
(((input) & ~(mask)) | ((curr) & (mask)))
/* arg % size for size which is a power of 2 */
#define MOD2(input, size) \
((input) & (size - 1))
#define ETHER_TYPE_LEN 2
#define VLAN_TCI_LEN 2
#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
#ifdef ENABLE_RTL8139_LOG
int rtl8139_do_log = ENABLE_RTL8139_LOG;
static void
rtl8139_log(const char *fmt, ...)
{
va_list ap;
if (rtl8139_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define rtl8139_log(fmt, ...)
#endif
struct RTL8139State;
typedef struct RTL8139State RTL8139State;
/* Symbolic offsets to registers. */
enum RTL8139_registers {
MAC0 = 0, /* Ethernet hardware address. */
MAR0 = 8, /* Multicast filter. */
TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). C mode only */
/* Dump Tally Conter control register(64bit). C+ mode only */
TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
RxBuf = 0x30,
ChipCmd = 0x37,
RxBufPtr = 0x38,
RxBufAddr = 0x3A,
IntrMask = 0x3C,
IntrStatus = 0x3E,
TxConfig = 0x40,
RxConfig = 0x44,
Timer = 0x48, /* A general-purpose counter. */
RxMissed = 0x4C, /* 24 bits valid, write clears. */
Cfg9346 = 0x50,
Config0 = 0x51,
Config1 = 0x52,
FlashReg = 0x54,
MediaStatus = 0x58,
Config3 = 0x59,
Config4 = 0x5A, /* absent on RTL-8139A */
HltClk = 0x5B,
MultiIntr = 0x5C,
PCIRevisionID = 0x5E,
TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
BasicModeCtrl = 0x62,
BasicModeStatus = 0x64,
NWayAdvert = 0x66,
NWayLPAR = 0x68,
NWayExpansion = 0x6A,
/* Undocumented registers, but required for proper operation. */
FIFOTMS = 0x70, /* FIFO Control and test. */
CSCR = 0x74, /* Chip Status and Configuration Register. */
PARA78 = 0x78,
PARA7c = 0x7c, /* Magic transceiver parameter register. */
Config5 = 0xD8, /* absent on RTL-8139A */
/* C+ mode */
TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
TxThresh = 0xEC, /* Early Tx threshold */
};
enum ClearBitMasks {
MultiIntrClear = 0xF000,
ChipCmdClear = 0xE2,
Config1Clear = (1 << 7) | (1 << 6) | (1 << 3) | (1 << 2) | (1 << 1),
};
enum ChipCmdBits {
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
RxBufEmpty = 0x01,
};
/* C+ mode */
enum CplusCmdBits {
CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
CPlusRxEnb = 0x0002,
CPlusTxEnb = 0x0001,
};
/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
PCIErr = 0x8000,
PCSTimeout = 0x4000,
RxFIFOOver = 0x40,
RxUnderrun = 0x20, /* Packet Underrun / Link Change */
RxOverflow = 0x10,
TxErr = 0x08,
TxOK = 0x04,
RxErr = 0x02,
RxOK = 0x01,
RxAckBits = RxFIFOOver | RxOverflow | RxOK,
};
enum TxStatusBits {
TxHostOwns = 0x2000,
TxUnderrun = 0x4000,
TxStatOK = 0x8000,
TxOutOfWindow = 0x20000000,
TxAborted = 0x40000000,
TxCarrierLost = 0x80000000,
};
enum RxStatusBits {
RxMulticast = 0x8000,
RxPhysical = 0x4000,
RxBroadcast = 0x2000,
RxBadSymbol = 0x0020,
RxRunt = 0x0010,
RxTooLong = 0x0008,
RxCRCErr = 0x0004,
RxBadAlign = 0x0002,
RxStatusOK = 0x0001,
};
/* Bits in RxConfig. */
enum rx_mode_bits {
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01,
};
/* Bits in TxConfig. */
enum tx_config_bits {
/* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
TxIFGShift = 24,
TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
TxClearAbt = (1 << 0), /* Clear abort (WO) */
TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
};
/* Transmit Status of All Descriptors (TSAD) Register */
enum TSAD_bits {
TSAD_TOK3 = 1 << 15, // TOK bit of Descriptor 3
TSAD_TOK2 = 1 << 14, // TOK bit of Descriptor 2
TSAD_TOK1 = 1 << 13, // TOK bit of Descriptor 1
TSAD_TOK0 = 1 << 12, // TOK bit of Descriptor 0
TSAD_TUN3 = 1 << 11, // TUN bit of Descriptor 3
TSAD_TUN2 = 1 << 10, // TUN bit of Descriptor 2
TSAD_TUN1 = 1 << 9, // TUN bit of Descriptor 1
TSAD_TUN0 = 1 << 8, // TUN bit of Descriptor 0
TSAD_TABT3 = 1 << 07, // TABT bit of Descriptor 3
TSAD_TABT2 = 1 << 06, // TABT bit of Descriptor 2
TSAD_TABT1 = 1 << 05, // TABT bit of Descriptor 1
TSAD_TABT0 = 1 << 04, // TABT bit of Descriptor 0
TSAD_OWN3 = 1 << 03, // OWN bit of Descriptor 3
TSAD_OWN2 = 1 << 02, // OWN bit of Descriptor 2
TSAD_OWN1 = 1 << 01, // OWN bit of Descriptor 1
TSAD_OWN0 = 1 << 00, // OWN bit of Descriptor 0
};
/* Bits in Config1 */
enum Config1Bits {
Cfg1_PM_Enable = 0x01,
Cfg1_VPD_Enable = 0x02,
Cfg1_PIO = 0x04,
Cfg1_MMIO = 0x08,
LWAKE = 0x10, /* not on 8139, 8139A */
Cfg1_Driver_Load = 0x20,
Cfg1_LED0 = 0x40,
Cfg1_LED1 = 0x80,
SLEEP = (1 << 1), /* only on 8139, 8139A */
PWRDN = (1 << 0), /* only on 8139, 8139A */
};
/* Bits in Config3 */
enum Config3Bits {
Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
};
/* Bits in Config4 */
enum Config4Bits {
LWPTN = (1 << 2), /* not on 8139, 8139A */
};
/* Bits in Config5 */
enum Config5Bits {
Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
};
enum RxConfigBits {
/* rx fifo threshold */
RxCfgFIFOShift = 13,
RxCfgFIFONone = (7 << RxCfgFIFOShift),
/* Max DMA burst */
RxCfgDMAShift = 8,
RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
/* rx ring buffer length */
RxCfgRcv8K = 0,
RxCfgRcv16K = (1 << 11),
RxCfgRcv32K = (1 << 12),
RxCfgRcv64K = (1 << 11) | (1 << 12),
/* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
RxNoWrap = (1 << 7),
};
/* Twister tuning parameters from RealTek.
Completely undocumented, but required to tune bad links on some boards. */
#if 0
enum CSCRBits {
CSCR_LinkOKBit = 0x0400,
CSCR_LinkChangeBit = 0x0800,
CSCR_LinkStatusBits = 0x0f000,
CSCR_LinkDownOffCmd = 0x003c0,
CSCR_LinkDownCmd = 0x0f3c0,
#endif
enum CSCRBits {
CSCR_Testfun = 1 << 15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
CSCR_Cable_Changed = 1 << 11, /* Undocumented: 1 = Cable status changed, 0 = No change */
CSCR_Cable = 1 << 10, /* Undocumented: 1 = Cable connected, 0 = Cable disconnected */
CSCR_LD = 1 << 9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
CSCR_HEART_BIT = 1 << 8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
CSCR_JBEN = 1 << 7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
CSCR_F_LINK_100 = 1 << 6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
CSCR_F_Connect = 1 << 5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
CSCR_Con_status = 1 << 3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
CSCR_Con_status_En = 1 << 2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
CSCR_PASS_SCR = 1 << 0, /* Bypass Scramble, def 0*/
};
enum Cfg9346Bits {
Cfg9346_Normal = 0x00,
Cfg9346_Autoload = 0x40,
Cfg9346_Programming = 0x80,
Cfg9346_ConfigWrite = 0xC0,
};
typedef enum {
CH_8139 = 0,
CH_8139_K,
CH_8139A,
CH_8139A_G,
CH_8139B,
CH_8130,
CH_8139C,
CH_8100,
CH_8100B_8139D,
CH_8101,
} chip_t;
enum chip_flags {
HasHltClk = (1 << 0),
HasLWake = (1 << 1),
};
#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
(b30 << 30 | b29 << 29 | b28 << 28 | b27 << 27 | b26 << 26 | b23 << 23 | b22 << 22)
#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
#define RTL8139_PCI_REVID_8139 0x10
#define RTL8139_PCI_REVID_8139CPLUS 0x20
#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
#pragma pack(push, 1)
typedef struct RTL8139TallyCounters {
/* Tally counters */
uint64_t TxOk;
uint64_t RxOk;
uint64_t TxERR;
uint32_t RxERR;
uint16_t MissPkt;
uint16_t FAE;
uint32_t Tx1Col;
uint32_t TxMCol;
uint64_t RxOkPhy;
uint64_t RxOkBrd;
uint32_t RxOkMul;
uint16_t TxAbt;
uint16_t TxUndrn;
} RTL8139TallyCounters;
#pragma pack(pop)
/* Clears all tally counters */
static void RTL8139TallyCounters_clear(RTL8139TallyCounters *counters);
struct RTL8139State {
/*< private >*/
uint8_t pci_slot;
uint8_t inst;
uint8_t irq_state;
uint8_t pad;
/*< public >*/
uint8_t phys[8]; /* mac address */
uint8_t mult[8]; /* multicast mask array */
uint8_t pci_conf[256];
uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
uint32_t TxAddr[4]; /* TxAddr0 */
uint32_t RxBuf; /* Receive buffer */
uint32_t RxBufferSize; /* internal variable, receive ring buffer size in C mode */
uint32_t RxBufPtr;
uint32_t RxBufAddr;
uint16_t IntrStatus;
uint16_t IntrMask;
uint32_t TxConfig;
uint32_t RxConfig;
uint32_t RxMissed;
uint16_t CSCR;
uint8_t Cfg9346;
uint8_t Config0;
uint8_t Config1;
uint8_t Config3;
uint8_t Config4;
uint8_t Config5;
uint8_t clock_enabled;
uint8_t bChipCmdState;
uint16_t MultiIntr;
uint16_t BasicModeCtrl;
uint16_t BasicModeStatus;
uint16_t NWayAdvert;
uint16_t NWayLPAR;
uint16_t NWayExpansion;
uint16_t CpCmd;
uint8_t TxThresh;
uint8_t pci_latency;
netcard_t *nic;
/* C ring mode */
uint32_t currTxDesc;
/* C+ mode */
uint32_t cplus_enabled;
uint32_t currCPlusRxDesc;
uint32_t currCPlusTxDesc;
uint32_t RxRingAddrLO;
uint32_t RxRingAddrHI;
uint32_t TCTR;
uint32_t TimerInt;
int64_t TCTR_base;
/* Tally counters */
RTL8139TallyCounters tally_counters;
/* Non-persistent data */
uint8_t *cplus_txbuffer;
int cplus_txbuffer_len;
int cplus_txbuffer_offset;
uint32_t mem_base;
/* PCI interrupt timer */
pc_timer_t timer;
mem_mapping_t bar_mem;
/* Support migration to/from old versions */
int rtl8139_mmio_io_addr_dummy;
nmc93cxx_eeprom_t *eeprom;
uint8_t eeprom_data[128];
};
/* Writes tally counters to memory via DMA */
static void RTL8139TallyCounters_dma_write(RTL8139State *s, uint32_t tc_addr);
static void
rtl8139_update_irq(RTL8139State *s)
{
uint8_t d = s->pci_slot;
int isr;
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
rtl8139_log("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
s->IntrMask);
if (isr != 0)
pci_set_irq(d, PCI_INTA, &s->irq_state);
else
pci_clear_irq(d, PCI_INTA, &s->irq_state);
}
static int
rtl8139_RxWrap(RTL8139State *s)
{
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
return (s->RxConfig & (1 << 7));
}
static int
rtl8139_receiver_enabled(RTL8139State *s)
{
return s->bChipCmdState & CmdRxEnb;
}
static int
rtl8139_transmitter_enabled(RTL8139State *s)
{
return s->bChipCmdState & CmdTxEnb;
}
static int
rtl8139_cp_receiver_enabled(RTL8139State *s)
{
return s->CpCmd & CPlusRxEnb;
}
static int
rtl8139_cp_transmitter_enabled(RTL8139State *s)
{
return s->CpCmd & CPlusTxEnb;
}
static void
rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
{
if (s->RxBufAddr + size > s->RxBufferSize) {
int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
/* write packet data */
if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) {
rtl8139_log(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
if (size > wrapped) {
dma_bm_write(s->RxBuf + s->RxBufAddr,
buf, size - wrapped, 1);
}
/* reset buffer pointer */
s->RxBufAddr = 0;
dma_bm_write(s->RxBuf + s->RxBufAddr,
buf + (size - wrapped), wrapped, 1);
s->RxBufAddr = wrapped;
return;
}
}
/* non-wrapping path or overwrapping enabled */
dma_bm_write(s->RxBuf + s->RxBufAddr, buf, size, 1);
s->RxBufAddr += size;
}
static __inline uint32_t
rtl8139_addr64(uint32_t low, UNUSED(uint32_t high))
{
return low;
}
/* Workaround for buggy guest driver such as linux who allocates rx
* rings after the receiver were enabled. */
static bool
rtl8139_cp_rx_valid(RTL8139State *s)
{
return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
}
static bool
rtl8139_can_receive(RTL8139State *s)
{
int avail;
/* Receive (drop) packets if card is disabled. */
if (!s->clock_enabled) {
return true;
}
if (!rtl8139_receiver_enabled(s)) {
return true;
}
if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
/* ??? Flow control not implemented in c+ mode.
This is a hack to work around slirp deficiencies anyway. */
return true;
}
avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
s->RxBufferSize);
return avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow);
}
/* From FreeBSD */
/* XXX: optimize */
static uint32_t
net_crc32(const uint8_t *p, int len)
{
uint32_t crc;
int carry;
uint8_t b;
crc = 0xffffffff;
for (int i = 0; i < len; i++) {
b = *p++;
for (uint8_t j = 0; j < 8; j++) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry) {
crc = ((crc ^ 0x04c11db6) | carry);
}
}
}
return crc;
}
uint32_t
net_crc32_le(const uint8_t *p, int len)
{
uint32_t crc;
int carry;
uint8_t b;
crc = 0xffffffff;
for (int i = 0; i < len; i++) {
b = *p++;
for (uint8_t j = 0; j < 8; j++) {
carry = (crc & 0x1) ^ (b & 0x01);
crc >>= 1;
b >>= 1;
if (carry) {
crc ^= 0xedb88320;
}
}
}
return crc;
}
#define ETH_ALEN 6
static int
rtl8139_do_receive(void *priv, uint8_t *buf, int size_)
{
RTL8139State *s = (RTL8139State *) priv;
/* size is the length of the buffer passed to the driver */
size_t size = size_;
const uint8_t *dot1q_buf = NULL;
uint32_t packet_header = 0;
uint8_t buf1[60 + VLAN_HLEN];
static const uint8_t broadcast_macaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
rtl8139_log(">>> received len=%u\n", (uint32_t) size);
if (!rtl8139_can_receive(s))
return 0;
/* test if board clock is stopped */
if (!s->clock_enabled) {
rtl8139_log("stopped ==========================\n");
return -1;
}
/* first check if receiver is enabled */
if (!rtl8139_receiver_enabled(s)) {
rtl8139_log("receiver disabled ================\n");
return -1;
}
/* XXX: check this */
if (s->RxConfig & AcceptAllPhys) {
/* promiscuous: receive all */
rtl8139_log(">>> packet received in promiscuous mode\n");
} else {
if (!memcmp(buf, broadcast_macaddr, 6)) {
/* broadcast address */
if (!(s->RxConfig & AcceptBroadcast)) {
rtl8139_log(">>> broadcast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
return size;
}
packet_header |= RxBroadcast;
rtl8139_log(">>> broadcast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkBrd;
} else if (buf[0] & 0x01) {
/* multicast */
if (!(s->RxConfig & AcceptMulticast)) {
rtl8139_log(">>> multicast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
return size;
}
int mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
rtl8139_log(">>> multicast address mismatch\n");
/* update tally counter */
++s->tally_counters.RxERR;
return size;
}
packet_header |= RxMulticast;
rtl8139_log(">>> multicast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkMul;
} else if (s->phys[0] == buf[0] && s->phys[1] == buf[1] && s->phys[2] == buf[2] && s->phys[3] == buf[3] && s->phys[4] == buf[4] && s->phys[5] == buf[5]) {
/* match */
if (!(s->RxConfig & AcceptMyPhys)) {
rtl8139_log(">>> rejecting physical address matching packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
return size;
}
packet_header |= RxPhysical;
rtl8139_log(">>> physical address matching packet received\n");
/* update tally counter */
++s->tally_counters.RxOkPhy;
} else {
rtl8139_log(">>> unknown packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
return size;
}
}
if (size < 60 + VLAN_HLEN) {
memcpy(buf1, buf, size);
memset(buf1 + size, 0, 60 + VLAN_HLEN - size);
buf = buf1;
if (size < 60) {
size = 60;
}
}
if (rtl8139_cp_receiver_enabled(s)) {
if (!rtl8139_cp_rx_valid(s)) {
return size;
}
rtl8139_log("in C+ Rx mode ================\n");
/* begin C+ receiver mode */
/* w0 ownership flag */
#define CP_RX_OWN (1 << 31)
/* w0 end of ring flag */
#define CP_RX_EOR (1 << 30)
/* w0 bits 0...12 : buffer size */
#define CP_RX_BUFFER_SIZE_MASK ((1 << 13) - 1)
/* w1 tag available flag */
#define CP_RX_TAVA (1 << 16)
/* w1 bits 0...15 : VLAN tag */
#define CP_RX_VLAN_TAG_MASK ((1 << 16) - 1)
/* w2 low 32bit of Rx buffer ptr */
/* w3 high 32bit of Rx buffer ptr */
int descriptor = s->currCPlusRxDesc;
uint32_t cplus_rx_ring_desc;
cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
cplus_rx_ring_desc += 16 * descriptor;
rtl8139_log("+++ C+ mode reading RX descriptor %d from host memory at "
"%08x %08x = "
"0x%8X"
"\n",
descriptor, s->RxRingAddrHI,
s->RxRingAddrLO, cplus_rx_ring_desc);
uint32_t val;
uint32_t rxdw0;
uint32_t rxdw1;
uint32_t rxbufLO;
uint32_t rxbufHI;
dma_bm_read(cplus_rx_ring_desc, (uint8_t *) &val, 4, 4);
rxdw0 = val;
dma_bm_read(cplus_rx_ring_desc + 4, (uint8_t *) &val, 4, 4);
rxdw1 = val;
dma_bm_read(cplus_rx_ring_desc + 8, (uint8_t *) &val, 4, 4);
rxbufLO = val;
dma_bm_read(cplus_rx_ring_desc + 12, (uint8_t *) &val, 4, 4);
rxbufHI = val;
rtl8139_log("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
if (!(rxdw0 & CP_RX_OWN)) {
rtl8139_log("C+ Rx mode : descriptor %d is owned by host\n",
descriptor);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
/* update tally counter */
++s->tally_counters.RxERR;
++s->tally_counters.MissPkt;
rtl8139_update_irq(s);
return size_;
}
uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
/* write VLAN info to descriptor variables. */
if (s->CpCmd & CPlusRxVLAN && bswap16(*((uint16_t *) &buf[ETH_ALEN * 2])) == 0x8100) {
dot1q_buf = &buf[ETH_ALEN * 2];
size -= VLAN_HLEN;
/* if too small buffer, use the tailroom added duing expansion */
if (size < 60) {
size = 60;
}
rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
/* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
rxdw1 |= CP_RX_TAVA | *((uint16_t *) (&dot1q_buf[ETHER_TYPE_LEN]));
rtl8139_log("C+ Rx mode : extracted vlan tag with tci: "
"%u\n",
bswap16(*((uint16_t *) &dot1q_buf[ETHER_TYPE_LEN])));
} else {
/* reset VLAN tag flag */
rxdw1 &= ~CP_RX_TAVA;
}
/* TODO: scatter the packet over available receive ring descriptors space */
if (size + 4 > rx_space) {
rtl8139_log("C+ Rx mode : descriptor %d size %d received %u + 4\n",
descriptor, rx_space, (uint32_t) size);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
/* update tally counter */
++s->tally_counters.RxERR;
++s->tally_counters.MissPkt;
rtl8139_update_irq(s);
return size_;
}
uint32_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
/* receive/copy to target memory */
if (dot1q_buf) {
dma_bm_write(rx_addr, buf, 2 * ETH_ALEN, 1);
dma_bm_write(rx_addr + 2 * ETH_ALEN,
buf + 2 * ETH_ALEN + VLAN_HLEN,
size - 2 * ETH_ALEN, 1);
} else {
dma_bm_write(rx_addr, buf, size, 1);
}
if (s->CpCmd & CPlusRxChkSum) {
/* do some packet checksumming */
}
/* write checksum */
val = (net_crc32_le(buf, size_));
dma_bm_write(rx_addr + size, (uint8_t *) &val, 4, 4);
/* first segment of received packet flag */
#define CP_RX_STATUS_FS (1 << 29)
/* last segment of received packet flag */
#define CP_RX_STATUS_LS (1 << 28)
/* multicast packet flag */
#define CP_RX_STATUS_MAR (1 << 26)
/* physical-matching packet flag */
#define CP_RX_STATUS_PAM (1 << 25)
/* broadcast packet flag */
#define CP_RX_STATUS_BAR (1 << 24)
/* runt packet flag */
#define CP_RX_STATUS_RUNT (1 << 19)
/* crc error flag */
#define CP_RX_STATUS_CRC (1 << 18)
/* IP checksum error flag */
#define CP_RX_STATUS_IPF (1 << 15)
/* UDP checksum error flag */
#define CP_RX_STATUS_UDPF (1 << 14)
/* TCP checksum error flag */
#define CP_RX_STATUS_TCPF (1 << 13)
/* transfer ownership to target */
rxdw0 &= ~CP_RX_OWN;
/* set first segment bit */
rxdw0 |= CP_RX_STATUS_FS;
/* set last segment bit */
rxdw0 |= CP_RX_STATUS_LS;
/* set received packet type flags */
if (packet_header & RxBroadcast)
rxdw0 |= CP_RX_STATUS_BAR;
if (packet_header & RxMulticast)
rxdw0 |= CP_RX_STATUS_MAR;
if (packet_header & RxPhysical)
rxdw0 |= CP_RX_STATUS_PAM;
/* set received size */
rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
rxdw0 |= (size + 4);
/* update ring data */
val = rxdw0;
dma_bm_write(cplus_rx_ring_desc, (uint8_t *) &val, 4, 4);
val = rxdw1;
dma_bm_write(cplus_rx_ring_desc + 4, (uint8_t *) &val, 4, 4);
/* update tally counter */
++s->tally_counters.RxOk;
/* seek to next Rx descriptor */
if (rxdw0 & CP_RX_EOR) {
s->currCPlusRxDesc = 0;
} else {
++s->currCPlusRxDesc;
}
rtl8139_log("done C+ Rx mode ----------------\n");
} else {
rtl8139_log("in ring Rx mode ================\n");
/* begin ring receiver mode */
int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
/* if receiver buffer is empty then avail == 0 */
#define RX_ALIGN(x) (((x) + 3) & ~0x3)
if (avail != 0 && RX_ALIGN(size + 8) >= avail) {
rtl8139_log("rx overflow: rx buffer length %d head 0x%04x "
"read 0x%04x === available 0x%04x need 0x%04zx\n",
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
rtl8139_update_irq(s);
return 0;
}
packet_header |= RxStatusOK;
packet_header |= (((size + 4) << 16) & 0xffff0000);
/* write header */
uint32_t val = packet_header;
rtl8139_write_buffer(s, (uint8_t *) &val, 4);
rtl8139_write_buffer(s, buf, size);
/* write checksum */
val = (net_crc32_le(buf, size));
rtl8139_write_buffer(s, (uint8_t *) &val, 4);
/* correct buffer write pointer */
s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize);
/* now we can signal we have received something */
rtl8139_log("received: rx buffer length %d head 0x%04x read 0x%04x\n",
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
s->IntrStatus |= RxOK;
{
rtl8139_update_irq(s);
}
return size_;
}
static void
rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
{
s->RxBufferSize = bufferSize;
s->RxBufPtr = 0;
s->RxBufAddr = 0;
}
static void
rtl8139_reset_phy(RTL8139State *s)
{
s->BasicModeStatus = 0x7809;
s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
/* preserve link state */
s->BasicModeStatus |= (net_cards_conf[s->nic->card_num].link_state & NET_LINK_DOWN) ? 0 : 0x04;
s->NWayAdvert = 0x05e1; /* all modes, full duplex */
s->NWayLPAR = 0x05e1; /* all modes, full duplex */
s->NWayExpansion = 0x0001; /* autonegotiation supported */
s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
}
static void
rtl8139_reset(void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
/* reset interrupt mask */
s->IntrStatus = 0;
s->IntrMask = 0;
rtl8139_update_irq(s);
/* mark all status registers as owned by host */
for (uint8_t i = 0; i < 4; ++i) {
s->TxStatus[i] = TxHostOwns;
}
s->currTxDesc = 0;
s->currCPlusRxDesc = 0;
s->currCPlusTxDesc = 0;
s->RxRingAddrLO = 0;
s->RxRingAddrHI = 0;
s->RxBuf = 0;
rtl8139_reset_rxring(s, 8192);
/* ACK the reset */
s->TxConfig = 0;
#if 0
// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
s->clock_enabled = 0;
#else
s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
s->clock_enabled = 1;
#endif
s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */
/* set initial state data */
s->Config0 = 0x0; /* No boot ROM */
s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
s->Config3 = 0x1; /* fast back-to-back compatible */
s->Config5 = 0x0;
s->CpCmd = 0x0; /* reset C+ mode */
s->cplus_enabled = 0;
#if 0
s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
#endif
s->BasicModeCtrl = 0x1000; // autonegotiation
rtl8139_reset_phy(s);
/* also reset timer and disable timer interrupt */
s->TCTR = 0;
s->TimerInt = 0;
s->TCTR_base = 0;
#if 0
rtl8139_set_next_tctr_time(s);
#endif
/* reset tally counters */
RTL8139TallyCounters_clear(&s->tally_counters);
}
static void
RTL8139TallyCounters_clear(RTL8139TallyCounters *counters)
{
counters->TxOk = 0;
counters->RxOk = 0;
counters->TxERR = 0;
counters->RxERR = 0;
counters->MissPkt = 0;
counters->FAE = 0;
counters->Tx1Col = 0;
counters->TxMCol = 0;
counters->RxOkPhy = 0;
counters->RxOkBrd = 0;
counters->RxOkMul = 0;
counters->TxAbt = 0;
counters->TxUndrn = 0;
}
static void
RTL8139TallyCounters_dma_write(RTL8139State *s, uint32_t tc_addr)
{
RTL8139TallyCounters *tally_counters = &s->tally_counters;
dma_bm_write(tc_addr, (uint8_t *) tally_counters, sizeof(RTL8139TallyCounters), 1);
}
static void
rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("ChipCmd write val=0x%08x\n", val);
if (val & CmdReset) {
rtl8139_log("ChipCmd reset\n");
rtl8139_reset(s);
}
if (val & CmdRxEnb) {
rtl8139_log("ChipCmd enable receiver\n");
s->currCPlusRxDesc = 0;
}
if (val & CmdTxEnb) {
rtl8139_log("ChipCmd enable transmitter\n");
s->currCPlusTxDesc = 0;
}
/* mask unwritable bits */
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
/* Deassert reset pin before next read */
val &= ~CmdReset;
s->bChipCmdState = val;
}
static int
rtl8139_RxBufferEmpty(RTL8139State *s)
{
int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
if (unread != 0) {
rtl8139_log("receiver buffer data available 0x%04x\n", unread);
return 0;
}
rtl8139_log("receiver buffer is empty\n");
return 1;
}
static uint32_t
rtl8139_ChipCmd_read(RTL8139State *s)
{
uint32_t ret = s->bChipCmdState;
if (rtl8139_RxBufferEmpty(s))
ret |= RxBufEmpty;
rtl8139_log("ChipCmd read val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
{
val &= 0xffff;
rtl8139_log("C+ command register write(w) val=0x%04x\n", val);
s->cplus_enabled = 1;
/* mask unwritable bits */
val = SET_MASKED(val, 0xff84, s->CpCmd);
s->CpCmd = val;
}
static uint32_t
rtl8139_CpCmd_read(RTL8139State *s)
{
uint32_t ret = s->CpCmd;
rtl8139_log("C+ command register read(w) val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_IntrMitigate_write(UNUSED(RTL8139State *s), uint32_t val)
{
rtl8139_log("C+ IntrMitigate register write(w) val=0x%04x\n", val);
}
static uint32_t
rtl8139_IntrMitigate_read(UNUSED(RTL8139State *s))
{
uint32_t ret = 0;
rtl8139_log("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
return ret;
}
static int
rtl8139_config_writable(RTL8139State *s)
{
if ((s->Cfg9346 & 0xc0) == 0xc0)
return 1;
rtl8139_log("Configuration registers are write-protected\n");
return 0;
}
static void
rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
{
val &= 0xffff;
rtl8139_log("BasicModeCtrl register write(w) val=0x%04x\n", val);
/* mask unwritable bits */
uint32_t mask = 0xccff;
if (1 || !rtl8139_config_writable(s)) {
/* Speed setting and autonegotiation enable bits are read-only */
mask |= 0x3000;
/* Duplex mode setting is read-only */
mask |= 0x0100;
}
if (val & 0x8000) {
/* Reset PHY */
rtl8139_reset_phy(s);
}
val = SET_MASKED(val, mask, s->BasicModeCtrl);
s->BasicModeCtrl = val;
}
static uint32_t
rtl8139_BasicModeCtrl_read(RTL8139State *s)
{
uint32_t ret = s->BasicModeCtrl;
rtl8139_log("BasicModeCtrl register read(w) val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
{
val &= 0xffff;
rtl8139_log("BasicModeStatus register write(w) val=0x%04x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
s->BasicModeStatus = val;
}
static uint32_t
rtl8139_BasicModeStatus_read(RTL8139State *s)
{
uint32_t ret = s->BasicModeStatus;
rtl8139_log("BasicModeStatus register read(w) val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Cfg9346 write val=0x%02x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0x31, s->Cfg9346);
uint32_t opmode = val & 0xc0;
uint32_t eeprom_val = val & 0xf;
if (opmode == 0x80) {
/* eeprom access */
nmc93cxx_eeprom_write(s->eeprom,
!!(eeprom_val & 0x08),
!!(eeprom_val & 0x04),
!!(eeprom_val & 0x02));
} else if (opmode == 0x40) {
/* Reset. */
val = 0;
rtl8139_reset(s);
}
s->Cfg9346 = val;
}
static uint32_t
rtl8139_Cfg9346_read(RTL8139State *s)
{
uint32_t ret = s->Cfg9346;
uint32_t opmode = ret & 0xc0;
if (opmode == 0x80) {
if (nmc93cxx_eeprom_read(s->eeprom))
ret |= 0x01;
else
ret &= ~0x01;
}
rtl8139_log("Cfg9346 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_Config0_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Config0 write val=0x%02x\n", val);
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwritable bits */
val = SET_MASKED(val, 0xf8, s->Config0);
s->Config0 = val;
}
static uint32_t
rtl8139_Config0_read(RTL8139State *s)
{
uint32_t ret = s->Config0;
rtl8139_log("Config0 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_Config1_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Config1 write val=0x%02x\n", val);
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwritable bits */
val = SET_MASKED(val, 0xC, s->Config1);
s->Config1 = val;
}
static uint32_t
rtl8139_Config1_read(RTL8139State *s)
{
uint32_t ret = s->Config1;
rtl8139_log("Config1 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_Config3_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Config3 write val=0x%02x\n", val);
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwritable bits */
val = SET_MASKED(val, 0x8F, s->Config3);
s->Config3 = val;
}
static uint32_t
rtl8139_Config3_read(RTL8139State *s)
{
uint32_t ret = s->Config3;
rtl8139_log("Config3 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_Config4_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Config4 write val=0x%02x\n", val);
if (!rtl8139_config_writable(s)) {
return;
}
/* mask unwritable bits */
val = SET_MASKED(val, 0x0a, s->Config4);
s->Config4 = val;
}
static uint32_t
rtl8139_Config4_read(RTL8139State *s)
{
uint32_t ret = s->Config4;
rtl8139_log("Config4 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_Config5_write(RTL8139State *s, uint32_t val)
{
val &= 0xff;
rtl8139_log("Config5 write val=0x%02x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0x80, s->Config5);
s->Config5 = val;
}
static uint32_t
rtl8139_Config5_read(RTL8139State *s)
{
uint32_t ret = s->Config5;
rtl8139_log("Config5 read val=0x%02x\n", ret);
return ret;
}
static void
rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
{
if (!rtl8139_transmitter_enabled(s)) {
rtl8139_log("transmitter disabled; no TxConfig write val=0x%08x\n", val);
return;
}
rtl8139_log("TxConfig write val=0x%08x\n", val);
val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
s->TxConfig = val;
}
static void
rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
{
rtl8139_log("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
uint32_t tc = s->TxConfig;
tc &= 0xFFFFFF00;
tc |= (val & 0x000000FF);
rtl8139_TxConfig_write(s, tc);
}
static uint32_t
rtl8139_TxConfig_read(RTL8139State *s)
{
uint32_t ret = s->TxConfig;
rtl8139_log("TxConfig read val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("RxConfig write val=0x%08x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
s->RxConfig = val;
/* reset buffer size and read/write pointers */
rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
rtl8139_log("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
}
static uint32_t
rtl8139_RxConfig_read(RTL8139State *s)
{
uint32_t ret = s->RxConfig;
rtl8139_log("RxConfig read val=0x%08x\n", ret);
return ret;
}
void
rtl8139_network_rx_put(netcard_t *card, uint8_t *bufp, int len)
{
(void) network_rx_put(card, bufp, len);
}
static void
rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
UNUSED(int do_interrupt), const uint8_t *dot1q_buf)
{
void (*network_func)(netcard_t *, uint8_t *, int) = (TxLoopBack == (s->TxConfig & TxLoopBack)) ? rtl8139_network_rx_put : network_tx;
if (!size) {
rtl8139_log("+++ empty ethernet frame\n");
return;
}
if (dot1q_buf && size >= ETH_ALEN * 2) {
network_func(s->nic, buf, ETH_ALEN * 2);
network_func(s->nic, (uint8_t *) dot1q_buf, VLAN_HLEN);
network_func(s->nic, buf + ETH_ALEN * 2, size - ETH_ALEN * 2);
return;
}
network_func(s->nic, buf, size);
return;
}
static int
rtl8139_transmit_one(RTL8139State *s, int descriptor)
{
int txsize = s->TxStatus[descriptor] & 0x1fff;
uint8_t txbuffer[0x2000];
if (!rtl8139_transmitter_enabled(s)) {
rtl8139_log("+++ cannot transmit from descriptor %d: transmitter "
"disabled\n", descriptor);
return 0;
}
if (s->TxStatus[descriptor] & TxHostOwns) {
rtl8139_log("+++ cannot transmit from descriptor %d: owned by host "
"(%08x)\n", descriptor, s->TxStatus[descriptor]);
return 0;
}
rtl8139_log("+++ transmitting from descriptor %d\n", descriptor);
rtl8139_log("+++ transmit reading %d bytes from host memory at 0x%08x\n",
txsize, s->TxAddr[descriptor]);
dma_bm_read(s->TxAddr[descriptor], txbuffer, txsize, 1);
/* Mark descriptor as transferred */
s->TxStatus[descriptor] |= TxHostOwns;
s->TxStatus[descriptor] |= TxStatOK;
rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
rtl8139_log("+++ transmitted %d bytes from descriptor %d\n", txsize,
descriptor);
/* update interrupt */
s->IntrStatus |= TxOK;
rtl8139_update_irq(s);
return 1;
}
#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
/* produces ones' complement sum of data */
static uint16_t
ones_complement_sum(uint8_t *data, size_t len)
{
uint32_t result = 0;
for (; len > 1; data += 2, len -= 2) {
result += *(uint16_t *) data;
}
/* add the remainder byte */
if (len) {
uint8_t odd[2] = { *data, 0 };
result += *(uint16_t *) odd;
}
while (result >> 16)
result = (result & 0xffff) + (result >> 16);
return result;
}
static uint16_t
ip_checksum(void *data, size_t len)
{
return ~ones_complement_sum((uint8_t *) data, len);
}
/* TODO: Replace these with equivalents in 86Box if applicable. */
struct ip_header {
uint8_t ip_ver_len; /* version and header length */
uint8_t ip_tos; /* type of service */
uint16_t ip_len; /* total length */
uint16_t ip_id; /* identification */
uint16_t ip_off; /* fragment offset field */
uint8_t ip_ttl; /* time to live */
uint8_t ip_p; /* protocol */
uint16_t ip_sum; /* checksum */
uint32_t ip_src, ip_dst; /* source and destination address */
};
typedef struct tcp_header {
uint16_t th_sport; /* source port */
uint16_t th_dport; /* destination port */
uint32_t th_seq; /* sequence number */
uint32_t th_ack; /* acknowledgment number */
uint16_t th_offset_flags; /* data offset, reserved 6 bits, */
/* TCP protocol flags */
uint16_t th_win; /* window */
uint16_t th_sum; /* checksum */
uint16_t th_urp; /* urgent pointer */
} tcp_header;
typedef struct ip_pseudo_header {
uint32_t ip_src;
uint32_t ip_dst;
uint8_t zeros;
uint8_t ip_proto;
uint16_t ip_payload;
} ip_pseudo_header;
typedef struct udp_header {
uint16_t uh_sport; /* source port */
uint16_t uh_dport; /* destination port */
uint16_t uh_ulen; /* udp length */
uint16_t uh_sum; /* udp checksum */
} udp_header;
#define ETH_HLEN 14
#define ETH_P_IP (0x0800)
#define IP_PROTO_TCP (6)
#define IP_PROTO_UDP (17)
#define IP_HEADER_VERSION_4 (4)
#define TH_PUSH 0x08
#define TH_FIN 0x01
#define IP_HDR_GET_LEN(p) \
((*(uint8_t *) ((p + __builtin_offsetof(struct ip_header, ip_ver_len))) & 0x0F) << 2)
#define IP_HEADER_VERSION(ip) \
(((ip)->ip_ver_len >> 4) & 0xf)
#define TCP_HEADER_DATA_OFFSET(tcp) \
(((be16_to_cpu((tcp)->th_offset_flags) >> 12) & 0xf) << 2)
static int
rtl8139_cplus_transmit_one(RTL8139State *s)
{
if (!rtl8139_transmitter_enabled(s)) {
rtl8139_log("+++ C+ mode: transmitter disabled\n");
return 0;
}
if (!rtl8139_cp_transmitter_enabled(s)) {
rtl8139_log("+++ C+ mode: C+ transmitter disabled\n");
return 0;
}
int descriptor = s->currCPlusTxDesc;
uint32_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
/* Normal priority ring */
cplus_tx_ring_desc += 16 * descriptor;
rtl8139_log("+++ C+ mode reading TX descriptor %d from host memory at "
"%08x %08x = 0x%08X\n", descriptor, s->TxAddr[1],
s->TxAddr[0], cplus_tx_ring_desc);
uint32_t val;
uint32_t txdw0;
uint32_t txdw1;
uint32_t txbufLO;
uint32_t txbufHI;
dma_bm_read(cplus_tx_ring_desc, (uint8_t *) &val, 4, 4);
txdw0 = le32_to_cpu(val);
dma_bm_read(cplus_tx_ring_desc + 4, (uint8_t *) &val, 4, 4);
txdw1 = le32_to_cpu(val);
dma_bm_read(cplus_tx_ring_desc + 8, (uint8_t *) &val, 4, 4);
txbufLO = le32_to_cpu(val);
dma_bm_read(cplus_tx_ring_desc + 12, (uint8_t *) &val, 4, 4);
txbufHI = le32_to_cpu(val);
rtl8139_log("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
txdw0, txdw1, txbufLO, txbufHI);
/* w0 ownership flag */
#define CP_TX_OWN (1 << 31)
/* w0 end of ring flag */
#define CP_TX_EOR (1 << 30)
/* first segment of received packet flag */
#define CP_TX_FS (1 << 29)
/* last segment of received packet flag */
#define CP_TX_LS (1 << 28)
/* large send packet flag */
#define CP_TX_LGSEN (1 << 27)
/* large send MSS mask, bits 16...26 */
#define CP_TC_LGSEN_MSS_SHIFT 16
#define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1)
/* IP checksum offload flag */
#define CP_TX_IPCS (1 << 18)
/* UDP checksum offload flag */
#define CP_TX_UDPCS (1 << 17)
/* TCP checksum offload flag */
#define CP_TX_TCPCS (1 << 16)
/* w0 bits 0...15 : buffer size */
#define CP_TX_BUFFER_SIZE (1 << 16)
#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
/* w1 add tag flag */
#define CP_TX_TAGC (1 << 17)
/* w1 bits 0...15 : VLAN tag (big endian) */
#define CP_TX_VLAN_TAG_MASK ((1 << 16) - 1)
/* w2 low 32bit of Rx buffer ptr */
/* w3 high 32bit of Rx buffer ptr */
/* set after transmission */
/* FIFO underrun flag */
#define CP_TX_STATUS_UNF (1 << 25)
/* transmit error summary flag, valid if set any of three below */
#define CP_TX_STATUS_TES (1 << 23)
/* out-of-window collision flag */
#define CP_TX_STATUS_OWC (1 << 22)
/* link failure flag */
#define CP_TX_STATUS_LNKF (1 << 21)
/* excessive collisions flag */
#define CP_TX_STATUS_EXC (1 << 20)
if (!(txdw0 & CP_TX_OWN)) {
rtl8139_log("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
return 0;
}
rtl8139_log("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
if (txdw0 & CP_TX_FS) {
rtl8139_log("+++ C+ Tx mode : descriptor %d is first segment "
"descriptor\n", descriptor);
/* reset internal buffer offset */
s->cplus_txbuffer_offset = 0;
}
int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
uint32_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
/* make sure we have enough space to assemble the packet */
if (!s->cplus_txbuffer) {
s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
s->cplus_txbuffer = calloc(s->cplus_txbuffer_len, 1);
s->cplus_txbuffer_offset = 0;
rtl8139_log("+++ C+ mode transmission buffer allocated space %d\n",
s->cplus_txbuffer_len);
}
if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) {
/* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
rtl8139_log("+++ C+ mode transmission buffer overrun, truncated descriptor"
"length to %d\n", txsize);
}
/* append more data to the packet */
rtl8139_log("+++ C+ mode transmit reading %d bytes from host memory at "
"%08X to offset %d\n", txsize, tx_addr, s->cplus_txbuffer_offset);
dma_bm_read(tx_addr,
s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize, 1);
s->cplus_txbuffer_offset += txsize;
/* seek to next Rx descriptor */
if (txdw0 & CP_TX_EOR) {
s->currCPlusTxDesc = 0;
} else {
++s->currCPlusTxDesc;
if (s->currCPlusTxDesc >= 64)
s->currCPlusTxDesc = 0;
}
/* Build the Tx Status Descriptor */
uint32_t tx_status = txdw0;
/* transfer ownership to target */
tx_status &= ~CP_TX_OWN;
/* reset error indicator bits */
tx_status &= ~CP_TX_STATUS_UNF;
tx_status &= ~CP_TX_STATUS_TES;
tx_status &= ~CP_TX_STATUS_OWC;
tx_status &= ~CP_TX_STATUS_LNKF;
tx_status &= ~CP_TX_STATUS_EXC;
/* update ring data */
val = cpu_to_le32(tx_status);
dma_bm_write(cplus_tx_ring_desc, (uint8_t *) &val, 4, 4);
/* Now decide if descriptor being processed is holding the last segment of packet */
if (txdw0 & CP_TX_LS) {
uint8_t dot1q_buffer_space[VLAN_HLEN];
uint16_t *dot1q_buffer;
rtl8139_log("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
descriptor);
/* can transfer fully assembled packet */
uint8_t *saved_buffer = s->cplus_txbuffer;
int saved_size = s->cplus_txbuffer_offset;
int saved_buffer_len = s->cplus_txbuffer_len;
/* create vlan tag */
if (txdw1 & CP_TX_TAGC) {
/* the vlan tag is in BE byte order in the descriptor
* BE + le_to_cpu() + ~swap()~ = cpu */
rtl8139_log("+++ C+ Tx mode : inserting vlan tag with "
"tci: %u\n", bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
dot1q_buffer = (uint16_t *) dot1q_buffer_space;
dot1q_buffer[0] = cpu_to_be16(0x8100);
/* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
} else {
dot1q_buffer = NULL;
}
/* reset the card space to protect from recursive call */
s->cplus_txbuffer = NULL;
s->cplus_txbuffer_offset = 0;
s->cplus_txbuffer_len = 0;
if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) {
rtl8139_log("+++ C+ mode offloaded task checksum\n");
/* Large enough for Ethernet and IP headers? */
if (saved_size < ETH_HLEN + sizeof(struct ip_header)) {
goto skip_offload;
}
/* ip packet header */
struct ip_header *ip = NULL;
int hlen = 0;
uint8_t ip_protocol = 0;
uint16_t ip_data_len = 0;
uint8_t *eth_payload_data = NULL;
size_t eth_payload_len = 0;
int proto = be16_to_cpu(*(uint16_t *) (saved_buffer + 12));
if (proto != ETH_P_IP) {
goto skip_offload;
}
rtl8139_log("+++ C+ mode has IP packet\n");
/* Note on memory alignment: eth_payload_data is 16-bit aligned
* since saved_buffer is allocated with g_malloc() and ETH_HLEN is
* even. 32-bit accesses must use ldl/stl wrappers to avoid
* unaligned accesses.
*/
eth_payload_data = saved_buffer + ETH_HLEN;
eth_payload_len = saved_size - ETH_HLEN;
ip = (struct ip_header *) eth_payload_data;
if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
rtl8139_log("+++ C+ mode packet has bad IP version %d "
"expected %d\n", IP_HEADER_VERSION(ip),
IP_HEADER_VERSION_4);
goto skip_offload;
}
hlen = IP_HDR_GET_LEN(ip);
if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) {
goto skip_offload;
}
ip_protocol = ip->ip_p;
ip_data_len = be16_to_cpu(ip->ip_len);
if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
goto skip_offload;
}
ip_data_len -= hlen;
if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & CP_TX_IPCS)) {
rtl8139_log("+++ C+ mode need IP checksum\n");
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(ip, hlen);
rtl8139_log("+++ C+ mode IP header len=%d checksum=%04x\n",
hlen, ip->ip_sum);
}
if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) {
/* Large enough for the TCP header? */
if (ip_data_len < sizeof(tcp_header)) {
goto skip_offload;
}
int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) & CP_TC_LGSEN_MSS_MASK;
if (large_send_mss == 0) {
goto skip_offload;
}
rtl8139_log("+++ C+ mode offloaded task TSO IP data %d "
"frame data %d specified MSS=%d\n",
ip_data_len, saved_size - ETH_HLEN, large_send_mss);
/* maximum IP header length is 60 bytes */
uint8_t saved_ip_header[60];
/* save IP header template; data area is used in tcp checksum calculation */
memcpy(saved_ip_header, eth_payload_data, hlen);
/* a placeholder for checksum calculation routine in tcp case */
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
#if 0
size_t data_to_checksum_len = eth_payload_len - hlen + 12;
#endif
/* pointer to TCP header */
tcp_header *p_tcp_hdr = (tcp_header *) (eth_payload_data + hlen);
int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
/* Invalid TCP data offset? */
if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
goto skip_offload;
}
int tcp_data_len = ip_data_len - tcp_hlen;
rtl8139_log("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
"data len %d\n", ip_data_len, tcp_hlen, tcp_data_len);
/* note the cycle below overwrites IP header data,
but restores it from saved_ip_header before sending packet */
int is_last_frame = 0;
for (int tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += large_send_mss) {
uint16_t chunk_size = large_send_mss;
/* check if this is the last frame */
if (tcp_send_offset + large_send_mss >= tcp_data_len) {
is_last_frame = 1;
chunk_size = tcp_data_len - tcp_send_offset;
}
#if 0
rtl8139_log("+++ C+ mode TSO TCP seqno %08x\n",
ldl_be_p(&p_tcp_hdr->th_seq));
#endif
/* add 4 TCP pseudoheader fields */
/* copy IP source and destination fields */
memcpy(data_to_checksum, saved_ip_header + 12, 8);
rtl8139_log("+++ C+ mode TSO calculating TCP checksum for "
"packet with %d bytes data\n", tcp_hlen + chunk_size);
if (tcp_send_offset) {
memcpy((uint8_t *) p_tcp_hdr + tcp_hlen, (uint8_t *) p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
}
#define TCP_FLAGS_ONLY(flags) ((flags) &0x3f)
#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
/* keep PUSH and FIN flags only for the last frame */
if (!is_last_frame) {
TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN);
}
/* recalculate TCP checksum */
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *) data_to_checksum;
p_tcpip_hdr->zeros = 0;
p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
rtl8139_log("+++ C+ mode TSO TCP checksum %04x\n", tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
/* restore IP header */
memcpy(eth_payload_data, saved_ip_header, hlen);
/* set IP data length and recalculate IP checksum */
ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
/* increment IP id for subsequent frames */
ip->ip_id = cpu_to_be16(tcp_send_offset / large_send_mss + be16_to_cpu(ip->ip_id));
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(eth_payload_data, hlen);
rtl8139_log("+++ C+ mode TSO IP header len=%d checksum=%04x\n",
hlen, ip->ip_sum);
int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
rtl8139_log("+++ C+ mode TSO transferring packet size %d\n",
tso_send_size);
rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
0, (uint8_t *) dot1q_buffer);
/* add transferred count to TCP sequence number */
#if 0
stl_be_p(&p_tcp_hdr->th_seq,
chunk_size + ldl_be_p(&p_tcp_hdr->th_seq));
#endif
p_tcp_hdr->th_seq = bswap32(chunk_size + bswap32(p_tcp_hdr->th_seq));
}
/* Stop sending this frame */
saved_size = 0;
} else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS | CP_TX_UDPCS))) {
rtl8139_log("+++ C+ mode need TCP or UDP checksum\n");
/* maximum IP header length is 60 bytes */
uint8_t saved_ip_header[60];
memcpy(saved_ip_header, eth_payload_data, hlen);
uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
#if 0
size_t data_to_checksum_len = eth_payload_len - hlen + 12;
#endif
/* add 4 TCP pseudoheader fields */
/* copy IP source and destination fields */
memcpy(data_to_checksum, saved_ip_header + 12, 8);
if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) {
rtl8139_log("+++ C+ mode calculating TCP checksum for "
"packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *) data_to_checksum;
p_tcpip_hdr->zeros = 0;
p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
tcp_header *p_tcp_hdr = (tcp_header *) (data_to_checksum + 12);
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
rtl8139_log("+++ C+ mode TCP checksum %04x\n", tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
} else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) {
rtl8139_log("+++ C+ mode calculating UDP checksum for "
"packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *) data_to_checksum;
p_udpip_hdr->zeros = 0;
p_udpip_hdr->ip_proto = IP_PROTO_UDP;
p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
udp_header *p_udp_hdr = (udp_header *) (data_to_checksum + 12);
p_udp_hdr->uh_sum = 0;
int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
rtl8139_log("+++ C+ mode UDP checksum %04x\n", udp_checksum);
p_udp_hdr->uh_sum = udp_checksum;
}
/* restore IP header */
memcpy(eth_payload_data, saved_ip_header, hlen);
}
}
skip_offload:
/* update tally counter */
++s->tally_counters.TxOk;
rtl8139_log("+++ C+ mode transmitting %d bytes packet\n", saved_size);
rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
(uint8_t *) dot1q_buffer);
/* restore card space if there was no recursion and reset offset */
if (!s->cplus_txbuffer) {
s->cplus_txbuffer = saved_buffer;
s->cplus_txbuffer_len = saved_buffer_len;
s->cplus_txbuffer_offset = 0;
} else
free(saved_buffer);
} else {
rtl8139_log("+++ C+ mode transmission continue to next descriptor\n");
}
return 1;
}
static void
rtl8139_cplus_transmit(RTL8139State *s)
{
int txcount = 0;
while (txcount < 64 && rtl8139_cplus_transmit_one(s)) {
++txcount;
}
/* Mark transfer completed */
if (!txcount) {
rtl8139_log("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
s->currCPlusTxDesc);
} else {
/* update interrupt status */
s->IntrStatus |= TxOK;
rtl8139_update_irq(s);
}
}
static void
rtl8139_transmit(RTL8139State *s)
{
int descriptor = s->currTxDesc;
int txcount = 0;
/*while*/
if (rtl8139_transmit_one(s, descriptor)) {
++s->currTxDesc;
s->currTxDesc %= 4;
++txcount;
}
/* Mark transfer completed */
if (!txcount) {
rtl8139_log("transmitter queue stalled, current TxDesc = %d\n",
s->currTxDesc);
}
}
static void
rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
{
int descriptor = txRegOffset / 4;
/* handle C+ transmit mode register configuration */
if (s->cplus_enabled) {
rtl8139_log("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
"descriptor=%d\n", txRegOffset, val, descriptor);
/* handle Dump Tally Counters command */
s->TxStatus[descriptor] = val;
if (descriptor == 0 && (val & 0x8)) {
uint32_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
/* dump tally counters to specified memory location */
RTL8139TallyCounters_dma_write(s, tc_addr);
/* mark dump completed */
s->TxStatus[0] &= ~0x8;
}
return;
}
rtl8139_log("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
txRegOffset, val, descriptor);
/* mask only reserved bits */
val &= ~0xff00c000; /* these bits are reset on write */
val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
s->TxStatus[descriptor] = val;
/* attempt to start transmission */
rtl8139_transmit(s);
}
static uint32_t
rtl8139_TxStatus_TxAddr_read(UNUSED(RTL8139State *s), uint32_t regs[],
uint32_t base, uint8_t addr,
int size)
{
uint32_t reg = (addr - base) / 4;
uint32_t offset = addr & 0x3;
uint32_t ret = 0;
if (addr & (size - 1)) {
rtl8139_log("not implemented read for TxStatus/TxAddr "
"addr=0x%x size=0x%x\n", addr, size);
return ret;
}
switch (size) {
case 1: /* fall through */
case 2: /* fall through */
case 4:
ret = (regs[reg] >> offset * 8) & (((uint64_t) 1 << (size * 8)) - 1);
rtl8139_log("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
reg, addr, size, ret);
break;
default:
rtl8139_log("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
break;
}
return ret;
}
static uint16_t
rtl8139_TSAD_read(RTL8139State *s)
{
uint16_t ret = 0;
/* Simulate TSAD, it is read only anyway */
ret = ((s->TxStatus[3] & TxStatOK) ? TSAD_TOK3 : 0)
| ((s->TxStatus[2] & TxStatOK) ? TSAD_TOK2 : 0)
| ((s->TxStatus[1] & TxStatOK) ? TSAD_TOK1 : 0)
| ((s->TxStatus[0] & TxStatOK) ? TSAD_TOK0 : 0)
| ((s->TxStatus[3] & TxUnderrun) ? TSAD_TUN3 : 0)
| ((s->TxStatus[2] & TxUnderrun) ? TSAD_TUN2 : 0)
| ((s->TxStatus[1] & TxUnderrun) ? TSAD_TUN1 : 0)
| ((s->TxStatus[0] & TxUnderrun) ? TSAD_TUN0 : 0)
| ((s->TxStatus[3] & TxAborted) ? TSAD_TABT3 : 0)
| ((s->TxStatus[2] & TxAborted) ? TSAD_TABT2 : 0)
| ((s->TxStatus[1] & TxAborted) ? TSAD_TABT1 : 0)
| ((s->TxStatus[0] & TxAborted) ? TSAD_TABT0 : 0)
| ((s->TxStatus[3] & TxHostOwns) ? TSAD_OWN3 : 0)
| ((s->TxStatus[2] & TxHostOwns) ? TSAD_OWN2 : 0)
| ((s->TxStatus[1] & TxHostOwns) ? TSAD_OWN1 : 0)
| ((s->TxStatus[0] & TxHostOwns) ? TSAD_OWN0 : 0);
rtl8139_log("TSAD read val=0x%04x\n", ret);
return ret;
}
static uint16_t
rtl8139_CSCR_read(RTL8139State *s)
{
static uint16_t old_ret = 0xffff;
uint16_t ret = s->CSCR |
((net_cards_conf[s->nic->card_num].link_state & NET_LINK_DOWN) ? 0 : CSCR_Cable);
if (old_ret != 0xffff) {
ret &= ~CSCR_Cable_Changed;
if ((ret ^ old_ret) & CSCR_Cable)
ret |= CSCR_Cable_Changed;
}
old_ret = ret;
rtl8139_log("CSCR read val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
{
rtl8139_log("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
s->TxAddr[txAddrOffset / 4] = val;
}
static uint32_t
rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
{
uint32_t ret = s->TxAddr[txAddrOffset / 4];
rtl8139_log("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
return ret;
}
static void
rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("RxBufPtr write val=0x%04x\n", val);
/* this value is off by 16 */
s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
rtl8139_log(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
static uint32_t
rtl8139_RxBufPtr_read(RTL8139State *s)
{
/* this value is off by 16 */
uint32_t ret = s->RxBufPtr - 0x10;
rtl8139_log("RxBufPtr read val=0x%04x\n", ret);
return ret;
}
static uint32_t
rtl8139_RxBufAddr_read(RTL8139State *s)
{
/* this value is NOT off by 16 */
uint32_t ret = s->RxBufAddr;
rtl8139_log("RxBufAddr read val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("RxBuf write val=0x%08x\n", val);
s->RxBuf = val;
/* may need to reset rxring here */
}
static uint32_t
rtl8139_RxBuf_read(RTL8139State *s)
{
uint32_t ret = s->RxBuf;
rtl8139_log("RxBuf read val=0x%08x\n", ret);
return ret;
}
static void
rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("IntrMask write(w) val=0x%04x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0x1e00, s->IntrMask);
s->IntrMask = val;
rtl8139_update_irq(s);
}
static uint32_t
rtl8139_IntrMask_read(RTL8139State *s)
{
uint32_t ret = s->IntrMask;
rtl8139_log("IntrMask read(w) val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("IntrStatus write(w) val=0x%04x\n", val);
#if 0
/* writing to ISR has no effect */
return;
#else
uint16_t newStatus = s->IntrStatus & ~val;
/* mask unwritable bits */
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
/* writing 1 to interrupt status register bit clears it */
s->IntrStatus = 0;
rtl8139_update_irq(s);
s->IntrStatus = newStatus;
rtl8139_update_irq(s);
#endif
}
static uint32_t
rtl8139_IntrStatus_read(RTL8139State *s)
{
uint32_t ret = s->IntrStatus;
rtl8139_log("IntrStatus read(w) val=0x%04x\n", ret);
#if 0
/* reading ISR clears all interrupts */
s->IntrStatus = 0;
rtl8139_update_irq(s);
#endif
return ret;
}
static void
rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
{
rtl8139_log("MultiIntr write(w) val=0x%04x\n", val);
/* mask unwritable bits */
val = SET_MASKED(val, 0xf000, s->MultiIntr);
s->MultiIntr = val;
}
static uint32_t
rtl8139_MultiIntr_read(RTL8139State *s)
{
uint32_t ret = s->MultiIntr;
rtl8139_log("MultiIntr read(w) val=0x%04x\n", ret);
return ret;
}
static void
rtl8139_io_writeb(uint32_t addr, uint8_t val, void *priv)
{
RTL8139State *s = priv;
addr &= 0xFF;
switch (addr) {
case MAC0 ... MAC0 + 4:
s->phys[addr - MAC0] = val;
break;
case MAC0 + 5:
s->phys[addr - MAC0] = val;
break;
case MAC0 + 6 ... MAC0 + 7:
/* reserved */
break;
case MAR0 ... MAR0 + 7:
s->mult[addr - MAR0] = val;
break;
case ChipCmd:
rtl8139_ChipCmd_write(s, val);
break;
case Cfg9346:
rtl8139_Cfg9346_write(s, val);
break;
case TxConfig: /* windows driver sometimes writes using byte-lenth call */
rtl8139_TxConfig_writeb(s, val);
break;
case Config0:
rtl8139_Config0_write(s, val);
break;
case Config1:
rtl8139_Config1_write(s, val);
break;
case Config3:
rtl8139_Config3_write(s, val);
break;
case Config4:
rtl8139_Config4_write(s, val);
break;
case Config5:
rtl8139_Config5_write(s, val);
break;
case MediaStatus:
/* ignore */
rtl8139_log("not implemented write(b) to MediaStatus val=0x%02x\n", val);
break;
case HltClk:
rtl8139_log("HltClk write val=0x%08x\n", val);
if (val == 'R') {
s->clock_enabled = 1;
} else if (val == 'H') {
s->clock_enabled = 0;
}
break;
case TxThresh:
rtl8139_log("C+ TxThresh write(b) val=0x%02x\n", val);
s->TxThresh = val;
break;
case TxPoll:
rtl8139_log("C+ TxPoll write(b) val=0x%02x\n", val);
if (val & (1 << 7)) {
rtl8139_log("C+ TxPoll high priority transmission (not "
"implemented)\n");
#if 0
rtl8139_cplus_transmit(s);
#endif
}
if (val & (1 << 6)) {
rtl8139_log("C+ TxPoll normal priority transmission\n");
rtl8139_cplus_transmit(s);
}
break;
default:
rtl8139_log("not implemented write(b) addr=0x%x val=0x%02x\n", addr, val);
break;
}
}
static void
rtl8139_io_writew(uint32_t addr, uint16_t val, void *priv)
{
RTL8139State *s = priv;
addr &= 0xFF;
switch (addr) {
case IntrMask:
rtl8139_IntrMask_write(s, val);
break;
case IntrStatus:
rtl8139_IntrStatus_write(s, val);
break;
case MultiIntr:
rtl8139_MultiIntr_write(s, val);
break;
case RxBufPtr:
rtl8139_RxBufPtr_write(s, val);
break;
case BasicModeCtrl:
rtl8139_BasicModeCtrl_write(s, val);
break;
case BasicModeStatus:
rtl8139_BasicModeStatus_write(s, val);
break;
case NWayAdvert:
rtl8139_log("NWayAdvert write(w) val=0x%04x\n", val);
s->NWayAdvert = val;
break;
case NWayLPAR:
rtl8139_log("forbidden NWayLPAR write(w) val=0x%04x\n", val);
break;
case NWayExpansion:
rtl8139_log("NWayExpansion write(w) val=0x%04x\n", val);
s->NWayExpansion = val;
break;
case CpCmd:
rtl8139_CpCmd_write(s, val);
break;
case IntrMitigate:
rtl8139_IntrMitigate_write(s, val);
break;
default:
rtl8139_log("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
addr, val);
rtl8139_io_writeb(addr, val & 0xff, priv);
rtl8139_io_writeb(addr + 1, (val >> 8) & 0xff, priv);
break;
}
}
/* TODO: Implement timer. */
static void
rtl8139_io_writel(uint32_t addr, uint32_t val, void *priv)
{
RTL8139State *s = priv;
addr &= 0xFF;
switch (addr) {
case RxMissed:
rtl8139_log("RxMissed clearing on write\n");
s->RxMissed = 0;
break;
case TxConfig:
rtl8139_TxConfig_write(s, val);
break;
case RxConfig:
rtl8139_RxConfig_write(s, val);
break;
case TxStatus0 ... TxStatus0 + 4 * 4 - 1:
rtl8139_TxStatus_write(s, addr - TxStatus0, val);
break;
case TxAddr0 ... TxAddr0 + 4 * 4 - 1:
rtl8139_TxAddr_write(s, addr - TxAddr0, val);
break;
case RxBuf:
rtl8139_RxBuf_write(s, val);
break;
case RxRingAddrLO:
rtl8139_log("C+ RxRing low bits write val=0x%08x\n", val);
s->RxRingAddrLO = val;
break;
case RxRingAddrHI:
rtl8139_log("C+ RxRing high bits write val=0x%08x\n", val);
s->RxRingAddrHI = val;
break;
case Timer:
rtl8139_log("TCTR Timer reset on write\n");
s->TCTR = 0;
#if 0
s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
rtl8139_set_next_tctr_time(s);
#endif
break;
case FlashReg:
rtl8139_log("FlashReg TimerInt write val=0x%08x\n", val);
if (s->TimerInt != val)
s->TimerInt = val;
break;
default:
rtl8139_log("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
addr, val);
rtl8139_io_writeb(addr, val & 0xff, priv);
rtl8139_io_writeb(addr + 1, (val >> 8) & 0xff, priv);
rtl8139_io_writeb(addr + 2, (val >> 16) & 0xff, priv);
rtl8139_io_writeb(addr + 3, (val >> 24) & 0xff, priv);
break;
}
}
static uint8_t
rtl8139_io_readb(uint32_t addr, void *priv)
{
RTL8139State *s = priv;
uint8_t ret;
addr &= 0xFF;
switch (addr) {
case MAC0 ... MAC0 + 5:
ret = s->phys[addr - MAC0];
break;
case MAC0 + 6 ... MAC0 + 7:
ret = 0;
break;
case MAR0 ... MAR0 + 7:
ret = s->mult[addr - MAR0];
break;
case TxStatus0 ... TxStatus0 + 4 * 4 - 1:
ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
addr, 1);
break;
case ChipCmd:
ret = rtl8139_ChipCmd_read(s);
break;
case Cfg9346:
ret = rtl8139_Cfg9346_read(s);
break;
case Config0:
ret = rtl8139_Config0_read(s);
break;
case Config1:
ret = rtl8139_Config1_read(s);
break;
case Config3:
ret = rtl8139_Config3_read(s);
break;
case Config4:
ret = rtl8139_Config4_read(s);
break;
case Config5:
ret = rtl8139_Config5_read(s);
break;
case MediaStatus:
/* The LinkDown bit of MediaStatus is inverse with link status */
ret = 0xd0 | (~s->BasicModeStatus & 0x04);
rtl8139_log("MediaStatus read 0x%x\n", ret);
break;
case HltClk:
ret = s->clock_enabled;
rtl8139_log("HltClk read 0x%x\n", ret);
break;
case PCIRevisionID:
ret = RTL8139_PCI_REVID;
rtl8139_log("PCI Revision ID read 0x%x\n", ret);
break;
case TxThresh:
ret = s->TxThresh;
rtl8139_log("C+ TxThresh read(b) val=0x%02x\n", ret);
break;
case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
ret = s->TxConfig >> 24;
rtl8139_log("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
break;
case CSCR:
ret = rtl8139_CSCR_read(s) & 0xff;
break;
case CSCR + 1:
ret = rtl8139_CSCR_read(s) >> 8;
break;
default:
rtl8139_log("not implemented read(b) addr=0x%x\n", addr);
ret = 0;
break;
}
return ret;
}
static uint16_t
rtl8139_io_readw(uint32_t addr, void *priv)
{
RTL8139State *s = priv;
uint16_t ret;
addr &= 0xFF;
switch (addr) {
case TxAddr0 ... TxAddr0 + 4 * 4 - 1:
ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
break;
case IntrMask:
ret = rtl8139_IntrMask_read(s);
break;
case IntrStatus:
ret = rtl8139_IntrStatus_read(s);
break;
case MultiIntr:
ret = rtl8139_MultiIntr_read(s);
break;
case RxBufPtr:
ret = rtl8139_RxBufPtr_read(s);
break;
case RxBufAddr:
ret = rtl8139_RxBufAddr_read(s);
break;
case BasicModeCtrl:
ret = rtl8139_BasicModeCtrl_read(s);
break;
case BasicModeStatus:
ret = rtl8139_BasicModeStatus_read(s);
break;
case NWayAdvert:
ret = s->NWayAdvert;
rtl8139_log("NWayAdvert read(w) val=0x%04x\n", ret);
break;
case NWayLPAR:
ret = s->NWayLPAR;
rtl8139_log("NWayLPAR read(w) val=0x%04x\n", ret);
break;
case NWayExpansion:
ret = s->NWayExpansion;
rtl8139_log("NWayExpansion read(w) val=0x%04x\n", ret);
break;
case CpCmd:
ret = rtl8139_CpCmd_read(s);
break;
case IntrMitigate:
ret = rtl8139_IntrMitigate_read(s);
break;
case TxSummary:
ret = rtl8139_TSAD_read(s);
break;
case CSCR:
ret = rtl8139_CSCR_read(s);
break;
default:
rtl8139_log("ioport read(w) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(addr, priv);
ret |= rtl8139_io_readb(addr + 1, priv) << 8;
rtl8139_log("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
break;
}
return ret;
}
static uint32_t
rtl8139_io_readl(uint32_t addr, void *priv)
{
RTL8139State *s = priv;
uint32_t ret;
addr &= 0xFF;
switch (addr) {
case RxMissed:
ret = s->RxMissed;
rtl8139_log("RxMissed read val=0x%08x\n", ret);
break;
case TxConfig:
ret = rtl8139_TxConfig_read(s);
break;
case RxConfig:
ret = rtl8139_RxConfig_read(s);
break;
case TxStatus0 ... TxStatus0 + 4 * 4 - 1:
ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
addr, 4);
break;
case TxAddr0 ... TxAddr0 + 4 * 4 - 1:
ret = rtl8139_TxAddr_read(s, addr - TxAddr0);
break;
case RxBuf:
ret = rtl8139_RxBuf_read(s);
break;
case RxRingAddrLO:
ret = s->RxRingAddrLO;
rtl8139_log("C+ RxRing low bits read val=0x%08x\n", ret);
break;
case RxRingAddrHI:
ret = s->RxRingAddrHI;
rtl8139_log("C+ RxRing high bits read val=0x%08x\n", ret);
break;
case Timer:
#if 0
ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) /
PCI_PERIOD;
#endif
ret = s->TCTR;
rtl8139_log("TCTR Timer read val=0x%08x\n", ret);
break;
case FlashReg:
ret = s->TimerInt;
rtl8139_log("FlashReg TimerInt read val=0x%08x\n", ret);
break;
default:
rtl8139_log("ioport read(l) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(addr, priv);
ret |= rtl8139_io_readb(addr + 1, priv) << 8;
ret |= rtl8139_io_readb(addr + 2, priv) << 16;
ret |= rtl8139_io_readb(addr + 3, priv) << 24;
rtl8139_log("read(l) addr=0x%x val=%08x\n", addr, ret);
break;
}
return ret;
}
static uint32_t
rtl8139_io_readl_ioport(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = rtl8139_io_readl(addr, priv);
rtl8139_log("[%04X:%08X] [RLI] %04X = %08X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static uint16_t
rtl8139_io_readw_ioport(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = rtl8139_io_readw(addr, priv);
rtl8139_log("[%04X:%08X] [RWI] %04X = %04X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static uint8_t
rtl8139_io_readb_ioport(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
ret = rtl8139_io_readb(addr, priv);
rtl8139_log("[%04X:%08X] [RBI] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static void
rtl8139_io_writel_ioport(uint16_t addr, uint32_t val, void *priv)
{
rtl8139_log("[%04X:%08X] [WLI] %04X = %08X\n", CS, cpu_state.pc, addr, val);
rtl8139_io_writel(addr, val, priv);
}
static void
rtl8139_io_writew_ioport(uint16_t addr, uint16_t val, void *priv)
{
rtl8139_log("[%04X:%08X] [WWI] %04X = %04X\n", CS, cpu_state.pc, addr, val);
rtl8139_io_writew(addr, val, priv);
}
static void
rtl8139_io_writeb_ioport(uint16_t addr, uint8_t val, void *priv)
{
rtl8139_log("[%04X:%08X] [WBI] %04X = %02X\n", CS, cpu_state.pc, addr, val);
rtl8139_io_writeb(addr, val, priv);
}
static uint32_t
rtl8139_io_readl_mem(uint32_t addr, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
uint32_t ret = 0xffffffff;
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
ret = rtl8139_io_readl(addr, priv);
rtl8139_log("[%04X:%08X] [RLM] %08X = %08X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static uint16_t
rtl8139_io_readw_mem(uint32_t addr, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
uint16_t ret = 0xffff;
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
ret = rtl8139_io_readw(addr, priv);
rtl8139_log("[%04X:%08X] [RWM] %08X = %04X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static uint8_t
rtl8139_io_readb_mem(uint32_t addr, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
uint8_t ret = 0xff;
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
ret = rtl8139_io_readb(addr, priv);
rtl8139_log("[%04X:%08X] [RBM] %08X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static void
rtl8139_io_writel_mem(uint32_t addr, uint32_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
rtl8139_log("[%04X:%08X] [WLM] %08X = %08X\n", CS, cpu_state.pc, addr, val);
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
rtl8139_io_writel(addr, val, priv);
}
static void
rtl8139_io_writew_mem(uint32_t addr, uint16_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
rtl8139_log("[%04X:%08X] [WWM] %08X = %04X\n", CS, cpu_state.pc, addr, val);
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
rtl8139_io_writew(addr, val, priv);
}
static void
rtl8139_io_writeb_mem(uint32_t addr, uint8_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
rtl8139_log("[%04X:%08X] [WBM] %08X = %02X\n", CS, cpu_state.pc, addr, val);
if ((addr >= s->mem_base) && (addr < (s->mem_base + 0xff)))
rtl8139_io_writeb(addr, val, priv);
}
static int
rtl8139_set_link_status(void *priv, uint32_t link_state)
{
RTL8139State *s = (RTL8139State *) priv;
if (link_state & NET_LINK_DOWN) {
s->BasicModeStatus &= ~0x04;
} else {
s->BasicModeStatus |= 0x04;
}
s->IntrStatus |= RxUnderrun;
rtl8139_update_irq(s);
return 0;
}
static void
rtl8139_timer(void *priv)
{
RTL8139State *s = priv;
timer_on_auto(&s->timer, 1000000.0 / ((double) cpu_pci_speed));
if (!s->clock_enabled) {
rtl8139_log(">>> timer: clock is not running\n");
return;
}
s->TCTR++;
if (s->TCTR == s->TimerInt && s->TimerInt != 0) {
s->IntrStatus |= PCSTimeout;
rtl8139_update_irq(s);
}
}
static uint8_t
rtl8139_pci_read(UNUSED(int func), int addr, void *priv)
{
const RTL8139State *s = (RTL8139State *) priv;
switch (addr) {
default:
return s->pci_conf[addr & 0xFF];
case 0x00:
return 0xEC;
case 0x01:
return 0x10;
case 0x02:
return 0x39;
case 0x03:
return 0x81;
case 0x07:
return 0x02;
case 0x06:
return 0x80;
case 0x05:
return s->pci_conf[addr & 0xFF] & 1;
case 0x08:
return 0x20;
case 0x09:
return 0x0;
case 0x0a:
return 0x0;
case 0x0b:
return 0x2;
case 0x0d:
return s->pci_latency;
case 0x10:
return 1;
case 0x14:
return 0;
case 0x15:
#ifdef USE_256_BYTE_BAR
return s->pci_conf[addr & 0xFF];
#else
return s->pci_conf[addr & 0xFF] & 0xf0;
#endif
case 0x2c:
return 0xEC;
case 0x2d:
return 0x10;
case 0x2e:
return 0x39;
case 0x2f:
return 0x81;
case 0x34:
return 0xdc;
case 0x3d:
return PCI_INTA;
}
}
static void
rtl8139_pci_write(int func, int addr, uint8_t val, void *priv)
{
RTL8139State *s = (RTL8139State *) priv;
switch (addr) {
case 0x04:
mem_mapping_disable(&s->bar_mem);
io_removehandler((s->pci_conf[0x11] << 8), 256,
rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport,
rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport,
priv);
s->pci_conf[addr & 0xFF] = val;
if (val & PCI_COMMAND_IO)
io_sethandler((s->pci_conf[0x11] << 8), 256,
rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport,
rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport,
priv);
if ((val & PCI_COMMAND_MEM) && s->bar_mem.size)
mem_mapping_enable(&s->bar_mem);
break;
case 0x05:
s->pci_conf[addr & 0xFF] = val & 1;
break;
case 0x0c:
s->pci_conf[addr & 0xFF] = val;
break;
case 0x0d:
s->pci_latency = val;
break;
case 0x10:
case 0x11:
io_removehandler((s->pci_conf[0x11] << 8), 256,
rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport,
rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport,
priv);
s->pci_conf[addr & 0xFF] = val;
rtl8139_log("New I/O base: %04X\n", s->pci_conf[0x11] << 8);
if (s->pci_conf[0x4] & PCI_COMMAND_IO)
io_sethandler((s->pci_conf[0x11] << 8), 256,
rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport,
rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport,
priv);
break;
#ifndef USE_256_BYTE_BAR
case 0x14:
#endif
case 0x15:
case 0x16:
case 0x17:
s->pci_conf[addr & 0xFF] = val;
s->mem_base = (s->pci_conf[0x15] << 8) | (s->pci_conf[0x16] << 16) |
(s->pci_conf[0x17] << 24);
#ifndef USE_256_BYTE_BAR
s->mem_base &= 0xfffff000;
#endif
rtl8139_log("New memory base: %08X\n", s->mem_base);
if (s->pci_conf[0x4] & PCI_COMMAND_MEM)
#ifdef USE_256_BYTE_BAR
mem_mapping_set_addr(&s->bar_mem, (s->pci_conf[0x15] << 8) | (s->pci_conf[0x16] << 16) |
(s->pci_conf[0x17] << 24), 256);
#else
mem_mapping_set_addr(&s->bar_mem, ((s->pci_conf[0x15] & 0xf0) << 8) |
(s->pci_conf[0x16] << 16) | (s->pci_conf[0x17] << 24), 4096);
#endif
break;
case 0x3c:
s->pci_conf[addr & 0xFF] = val;
break;
}
}
static void *
nic_init(const device_t *info)
{
RTL8139State *s = calloc(1, sizeof(RTL8139State));
nmc93cxx_eeprom_params_t params;
char eeprom_filename[1024] = { 0 };
char filename[1024] = { 0 };
uint8_t *mac_bytes;
uint16_t *eep_data;
uint32_t mac;
mem_mapping_add(&s->bar_mem, 0, 0,
rtl8139_io_readb_mem, rtl8139_io_readw_mem, rtl8139_io_readl_mem,
rtl8139_io_writeb_mem, rtl8139_io_writew_mem, rtl8139_io_writel_mem,
NULL, MEM_MAPPING_EXTERNAL, s);
pci_add_card(PCI_ADD_NORMAL, rtl8139_pci_read, rtl8139_pci_write, s, &s->pci_slot);
s->inst = device_get_instance();
snprintf(eeprom_filename, sizeof(eeprom_filename), "eeprom_rtl8139c_plus_%d.nvr", s->inst);
eep_data = (uint16_t *) s->eeprom_data;
/* prepare eeprom */
eep_data[0] = 0x8129;
/* PCI vendor and device ID should be mirrored here */
eep_data[1] = 0x10EC;
eep_data[2] = 0x8139;
/* XXX: Get proper MAC addresses from real EEPROM dumps. OID taken from net_ne2000.c */
#ifdef USE_REALTEK_OID
eep_data[7] = 0xe000;
eep_data[8] = 0x124c;
#else
eep_data[7] = 0x1400;
eep_data[8] = 0x122a;
#endif
eep_data[9] = 0x1413;
mac_bytes = (uint8_t *) &(eep_data[7]);
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
mac_bytes[3] = random_generate();
mac_bytes[4] = random_generate();
mac_bytes[5] = random_generate();
mac = (((int) mac_bytes[3]) << 16);
mac |= (((int) mac_bytes[4]) << 8);
mac |= ((int) mac_bytes[5]);
device_set_config_mac("mac", mac);
} else {
mac_bytes[3] = (mac >> 16) & 0xff;
mac_bytes[4] = (mac >> 8) & 0xff;
mac_bytes[5] = (mac & 0xff);
}
for (uint32_t i = 0; i < 6; i++)
s->phys[MAC0 + i] = mac_bytes[i];
params.nwords = 64;
params.default_content = (uint16_t *) s->eeprom_data;
params.filename = filename;
snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, device_get_instance());
s->eeprom = device_add_params(&nmc93cxx_device, ¶ms);
if (s->eeprom == NULL) {
free(s);
return NULL;
}
s->nic = network_attach(s, (uint8_t *) &s->phys[MAC0], rtl8139_do_receive, rtl8139_set_link_status);
timer_add(&s->timer, rtl8139_timer, s, 0);
timer_on_auto(&s->timer, 1000000.0 / cpu_pci_speed);
s->cplus_txbuffer = NULL;
s->cplus_txbuffer_len = 0;
s->cplus_txbuffer_offset = 0;
return s;
}
static void
nic_close(void *priv)
{
free(priv);
}
// clang-format off
static const device_config_t rtl8139c_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t rtl8139c_plus_device = {
.name = "Realtek RTL8139C+",
.internal_name = "rtl8139c+",
.flags = DEVICE_PCI,
.local = 0,
.init = nic_init,
.close = nic_close,
.reset = rtl8139_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = rtl8139c_config
};
``` | /content/code_sandbox/src/network/net_rtl8139.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 28,408 |
```c
#ifdef _WIN32
# define WIN32_LEAN_AND_MEAN
# include <windows.h>
#else
# include <unistd.h>
# include <fcntl.h>
#endif
#include <86box/net_event.h>
#include <86box/plat_unused.h>
#ifndef _WIN32
static void
setup_fd(int fd)
{
fcntl(fd, F_SETFD, FD_CLOEXEC);
fcntl(fd, F_SETFL, O_NONBLOCK);
}
#endif
void
net_event_init(net_evt_t *event)
{
#ifdef _WIN32
event->handle = CreateEvent(NULL, FALSE, FALSE, NULL);
#else
(void) !pipe(event->fds);
setup_fd(event->fds[0]);
setup_fd(event->fds[1]);
#endif
}
void
net_event_set(net_evt_t *event)
{
#ifdef _WIN32
SetEvent(event->handle);
#else
(void) !write(event->fds[1], "a", 1);
#endif
}
void
net_event_clear(UNUSED(net_evt_t *event))
{
#ifdef _WIN32
/* Do nothing on WIN32 since we use an auto-reset event */
#else
char dummy[1];
(void) !read(event->fds[0], &dummy, sizeof(dummy));
#endif
}
void
net_event_close(net_evt_t *event)
{
#ifdef _WIN32
CloseHandle(event->handle);
#else
close(event->fds[0]);
close(event->fds[1]);
#endif
}
#ifdef _WIN32
HANDLE
net_event_get_handle(net_evt_t *event)
{
return event->handle;
}
#else
int
net_event_get_fd(net_evt_t *event)
{
return event->fds[0];
}
#endif
``` | /content/code_sandbox/src/network/net_event.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 373 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the following network controller:
* - 3Com Etherlink 3c500/3c501 (ISA 8-bit).
*
*
*
* Based on @(#)Dev3C501.cpp Oracle (VirtualBox)
*
* Authors: TheCollector1995, <mariogplayer@gmail.com>
* Oracle
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#include <stdbool.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/mem.h>
#include <86box/random.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/bswap.h>
#include <86box/plat_unused.h>
/* Maximum number of times we report a link down to the guest (failure to send frame) */
#define ELNK_MAX_LINKDOWN_REPORTED 3
/* Maximum number of times we postpone restoring a link that is temporarily down. */
#define ELNK_MAX_LINKRST_POSTPONED 3
/* Maximum frame size we handle */
#define MAX_FRAME 1536
/* Size of the packet buffer. */
#define ELNK_BUF_SIZE 2048
/* The packet buffer address mask. */
#define ELNK_BUF_ADR_MASK (ELNK_BUF_SIZE - 1)
/* The GP buffer pointer address within the buffer. */
#define ELNK_GP(dev) (dev->uGPBufPtr & ELNK_BUF_ADR_MASK)
/* The GP buffer pointer mask.
* NB: The GP buffer pointer is internally a 12-bit counter. When addressing into the
* packet buffer, bit 11 is ignored. Required to pass 3C501 diagnostics.
*/
#define ELNK_GP_MASK 0xfff
/*********************************************************************************************************************************
* Structures and Typedefs *
*********************************************************************************************************************************/
/**
* EtherLink Transmit Command Register.
*/
typedef struct ELNK_XMIT_CMD {
uint8_t det_ufl : 1; /* Detect underflow. */
uint8_t det_coll : 1; /* Detect collision. */
uint8_t det_16col : 1; /* Detect collision 16. */
uint8_t det_succ : 1; /* Detect successful xmit. */
uint8_t unused : 4;
} EL_XMT_CMD;
/**
* EtherLink Transmit Status Register.
*
* We will never see any real collisions, although collisions (including 16
* successive collisions) may be useful to report when the link is down
* (something the 3C501 does not have a concept of).
*/
typedef struct ELNK_XMIT_STAT {
uint8_t uflow : 1; /* Underflow on transmit. */
uint8_t coll : 1; /* Collision on transmit. */
uint8_t coll16 : 1; /* 16 collisions on transmit. */
uint8_t ready : 1; /* Ready for a new frame. */
uint8_t undef : 4;
} EL_XMT_STAT;
/** Address match (adr_match) modes. */
typedef enum {
EL_ADRM_DISABLED = 0, /* Receiver disabled. */
EL_ADRM_PROMISC = 1, /* Receive all addresses. */
EL_ADRM_BCAST = 2, /* Receive station + broadcast. */
EL_ADRM_MCAST = 3 /* Receive station + multicast. */
} EL_ADDR_MATCH;
/**
* EtherLink Receive Command Register.
*/
typedef struct ELNK_RECV_CMD {
uint8_t det_ofl : 1; /* Detect overflow errors. */
uint8_t det_fcs : 1; /* Detect FCS errors. */
uint8_t det_drbl : 1; /* Detect dribble error. */
uint8_t det_runt : 1; /* Detect short frames. */
uint8_t det_eof : 1; /* Detect EOF (frames without overflow). */
uint8_t acpt_good : 1; /* Accept good frames. */
uint8_t adr_match : 2; /* Address match mode. */
} EL_RCV_CMD;
/**
* EtherLink Receive Status Register.
*/
typedef struct ELNK_RECV_STAT {
uint8_t oflow : 1; /* Overflow on receive. */
uint8_t fcs : 1; /* FCS error. */
uint8_t dribble : 1; /* Dribble error. */
uint8_t runt : 1; /* Short frame. */
uint8_t no_ovf : 1; /* Received packet w/o overflow. */
uint8_t good : 1; /* Received good packet. */
uint8_t undef : 1;
uint8_t stale : 1; /* Stale receive status. */
} EL_RCV_STAT;
/** Buffer control (buf_ctl) modes. */
typedef enum {
EL_BCTL_SYSTEM = 0, /* Host has buffer access. */
EL_BCTL_XMT_RCV = 1, /* Transmit, then receive. */
EL_BCTL_RECEIVE = 2, /* Receive. */
EL_BCTL_LOOPBACK = 3 /* Loopback. */
} EL_BUFFER_CONTROL;
/**
* EtherLink Auxiliary Status Register.
*/
typedef struct ELNK_AUX_CMD {
uint8_t ire : 1; /* Interrupt Request Enable. */
uint8_t xmit_bf : 1; /* Xmit packets with bad FCS. */
uint8_t buf_ctl : 2; /* Packet buffer control. */
uint8_t unused : 1;
uint8_t dma_req : 1; /* DMA request. */
uint8_t ride : 1; /* Request Interrupt and DMA Enable. */
uint8_t reset : 1; /* Card in reset while set. */
} EL_AUX_CMD;
/**
* EtherLink Auxiliary Status Register.
*/
typedef struct ELNK_AUX_STAT {
uint8_t recv_bsy : 1; /* Receive busy. */
uint8_t xmit_bf : 1; /* Xmit packets with bad FCS. */
uint8_t buf_ctl : 2; /* Packet buffer control. */
uint8_t dma_done : 1; /* DMA done. */
uint8_t dma_req : 1; /* DMA request. */
uint8_t ride : 1; /* Request Interrupt and DMA Enable. */
uint8_t xmit_bsy : 1; /* Transmit busy. */
} EL_AUX_STAT;
/**
* Internal interrupt status.
*/
typedef struct ELNK_INTR_STAT {
uint8_t recv_intr : 1; /* Receive interrupt status. */
uint8_t xmit_intr : 1; /* Transmit interrupt status. */
uint8_t dma_intr : 1; /* DMA interrupt status. */
uint8_t unused : 5;
} EL_INTR_STAT;
typedef struct threec501_t {
uint32_t base_address;
int base_irq;
uint32_t bios_addr;
uint8_t maclocal[6]; /* configured MAC (local) address. */
bool fISR; /* Internal interrupt flag. */
int fDMA; /* Internal DMA active flag. */
int fInReset; /* Internal in-reset flag. */
uint8_t aPROM[8]; /* The PROM contents. Only 8 bytes addressable, R/O. */
uint8_t aStationAddr[6]; /* The station address programmed by the guest, W/O. */
uint16_t uGPBufPtr; /* General Purpose (GP) Buffer Pointer, R/W. */
uint16_t uRCVBufPtr; /* Receive (RCV) Buffer Pointer, R/W. */
/** Transmit Command Register, W/O. */
union {
uint8_t XmitCmdReg;
EL_XMT_CMD XmitCmd;
};
/** Transmit Status Register, R/O. */
union {
uint8_t XmitStatReg;
EL_XMT_STAT XmitStat;
};
/** Receive Command Register, W/O. */
union {
uint8_t RcvCmdReg;
EL_RCV_CMD RcvCmd;
};
/** Receive Status Register, R/O. */
union {
uint8_t RcvStatReg;
EL_RCV_STAT RcvStat;
};
/** Auxiliary Command Register, W/O. */
union {
uint8_t AuxCmdReg;
EL_AUX_CMD AuxCmd;
};
/** Auxiliary Status Register, R/O. */
union {
uint8_t AuxStatReg;
EL_AUX_STAT AuxStat;
};
int fLinkUp; /* If set the link is currently up. */
int fLinkTempDown; /* If set the link is temporarily down because of a saved state load. */
uint16_t cLinkDownReported; /* Number of times we've reported the link down. */
uint16_t cLinkRestorePostponed; /* Number of times we've postponed the link restore. */
/* Internal interrupt state. */
union {
uint8_t IntrStateReg;
EL_INTR_STAT IntrState;
};
uint32_t cMsLinkUpDelay; /* MS to wait before we enable the link. */
int dma_channel;
uint8_t abLoopBuf[ELNK_BUF_SIZE]; /* The loopback transmit buffer (avoid stack allocations). */
uint8_t abRuntBuf[64]; /* The runt pad buffer (only really needs 60 bytes). */
uint8_t abPacketBuf[ELNK_BUF_SIZE]; /* The packet buffer. */
int dma_pos;
pc_timer_t timer_restore;
netcard_t *netcard;
} threec501_t;
#ifdef ENABLE_3COM501_LOG
int threec501_do_log = ENABLE_3COM501_LOG;
static void
threec501_log(const char *fmt, ...)
{
va_list ap;
if (threec501_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define threec501_log(fmt, ...)
#endif
static void elnkSoftReset(threec501_t *dev);
static void elnkR3HardReset(threec501_t *dev);
#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */
# define ETHER_IS_MULTICAST(a) ((*(uint8_t *) (a)) & 1)
#endif
#define ETHER_ADDR_LEN ETH_ALEN
#define ETH_ALEN 6
#pragma pack(1)
struct ether_header /** @todo Use RTNETETHERHDR? */
{
uint8_t ether_dhost[ETH_ALEN]; /**< destination ethernet address */
uint8_t ether_shost[ETH_ALEN]; /**< source ethernet address */
uint16_t ether_type; /**< packet type ID field */
};
#pragma pack()
static void
elnk_do_irq(threec501_t *dev, int set)
{
if (set)
picint(1 << dev->base_irq);
else
picintc(1 << dev->base_irq);
}
/**
* Checks if the link is up.
* @returns true if the link is up.
* @returns false if the link is down.
*/
static __inline int
elnkIsLinkUp(threec501_t *dev)
{
return !dev->fLinkTempDown && dev->fLinkUp;
}
/**
* Takes down the link temporarily if it's current status is up.
*
* This is used during restore and when replumbing the network link.
*
* The temporary link outage is supposed to indicate to the OS that all network
* connections have been lost and that it for instance is appropriate to
* renegotiate any DHCP lease.
*
* @param pThis The shared instance data.
*/
static void
elnkTempLinkDown(threec501_t *dev)
{
if (dev->fLinkUp) {
dev->fLinkTempDown = 1;
dev->cLinkDownReported = 0;
dev->cLinkRestorePostponed = 0;
timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
}
}
/**
* @interface_method_impl{PDMDEVREG,pfnReset}
*/
static void
elnkR3Reset(void *priv)
{
threec501_t *dev = (threec501_t *) priv;
if (dev->fLinkTempDown) {
dev->cLinkDownReported = 0x1000;
dev->cLinkRestorePostponed = 0x1000;
timer_disable(&dev->timer_restore);
}
/** @todo How to flush the queues? */
elnkR3HardReset(dev);
}
static void
elnkR3HardReset(threec501_t *dev)
{
dev->fISR = false;
elnk_do_irq(dev, 0);
/* Clear the packet buffer and station address. */
memset(dev->abPacketBuf, 0, sizeof(dev->abPacketBuf));
memset(dev->aStationAddr, 0, sizeof(dev->aStationAddr));
/* Reset the buffer pointers. */
dev->uGPBufPtr = 0;
dev->uRCVBufPtr = 0;
elnkSoftReset(dev);
}
/**
* Check if incoming frame matches the station address.
*/
static __inline int
padr_match(threec501_t *dev, const uint8_t *buf)
{
const struct ether_header *hdr = (const struct ether_header *) buf;
int result;
/* Checks own + broadcast as well as own + multicast. */
result = (dev->RcvCmd.adr_match >= EL_ADRM_BCAST) && !memcmp(hdr->ether_dhost, dev->aStationAddr, 6);
return result;
}
/**
* Check if incoming frame is an accepted broadcast frame.
*/
static __inline int
padr_bcast(threec501_t *dev, const uint8_t *buf)
{
static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const struct ether_header *hdr = (const struct ether_header *) buf;
int result = (dev->RcvCmd.adr_match == EL_ADRM_BCAST) && !memcmp(hdr->ether_dhost, aBCAST, 6);
return result;
}
/**
* Check if incoming frame is an accepted multicast frame.
*/
static __inline int
padr_mcast(threec501_t *dev, const uint8_t *buf)
{
const struct ether_header *hdr = (const struct ether_header *) buf;
int result = (dev->RcvCmd.adr_match == EL_ADRM_MCAST) && ETHER_IS_MULTICAST(hdr->ether_dhost);
return result;
}
/**
* Update the device IRQ line based on internal state.
*/
static void
elnkUpdateIrq(threec501_t *dev)
{
bool fISR = false;
/* IRQ is active if any interrupt source is active and interrupts
* are enabled via RIDE or IRE.
*/
if (dev->IntrStateReg && (dev->AuxCmd.ride || dev->AuxCmd.ire))
fISR = true;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: elnkUpdateIrq: fISR=%d\n", fISR);
#endif
if (fISR != dev->fISR) {
elnk_do_irq(dev, fISR);
dev->fISR = fISR;
}
}
/**
* Perform a software reset of the NIC.
*/
static void
elnkSoftReset(threec501_t *dev)
{
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: elnkSoftReset\n");
#endif
/* Clear some of the user-visible register state. */
dev->XmitCmdReg = 0;
dev->XmitStatReg = 0;
dev->RcvCmdReg = 0;
dev->RcvStatReg = 0;
dev->AuxCmdReg = 0;
dev->AuxStatReg = 0;
/* The "stale receive status" is cleared by receiving an "interesting" packet. */
dev->RcvStat.stale = 1;
/* By virtue of setting the buffer control to system, transmit is set to busy. */
dev->AuxStat.xmit_bsy = 1;
/* Clear internal interrupt state. */
dev->IntrStateReg = 0;
elnkUpdateIrq(dev);
/* Note that a soft reset does not clear the packet buffer; software often
* assumes that it survives soft reset. The programmed station address is
* likewise not reset, and the buffer pointers are not reset either.
* Verified on a real 3C501.
*/
/* No longer in reset state. */
dev->fInReset = 0;
}
/**
* Write incoming data into the packet buffer.
*/
static int
elnkReceiveLocked(void *priv, uint8_t *src, int size)
{
threec501_t *dev = (threec501_t *) priv;
int is_padr = 0;
int is_bcast = 0;
int is_mcast = 0;
bool fLoopback = dev->RcvCmd.adr_match == EL_BCTL_LOOPBACK;
union {
uint8_t RcvStatNewReg;
EL_RCV_STAT RcvStatNew;
} rcvstatnew;
/* Drop everything if address matching is disabled. */
if (dev->RcvCmd.adr_match == EL_ADRM_DISABLED)
return 0;
/* Drop zero-length packets (how does that even happen?). */
if (!size)
return 0;
/*
* Drop all packets if the cable is not connected (and not in loopback).
*/
if (!elnkIsLinkUp(dev) && !fLoopback)
return 0;
/*
* Do not receive further packets until receive status was read.
*/
if (dev->RcvStat.stale == 0)
return 0;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: size on wire=%d, RCV ptr=%u\n", size, dev->uRCVBufPtr);
#endif
/*
* Perform address matching. Packets which do not pass the address
* filter are always ignored.
*/
/// @todo cbToRecv must be 6 or more (complete address)
if ((dev->RcvCmd.adr_match == EL_ADRM_PROMISC) /* promiscuous enabled */
|| (is_padr = padr_match(dev, src))
|| (is_bcast = padr_bcast(dev, src))
|| (is_mcast = padr_mcast(dev, src))) {
uint8_t *dst = dev->abPacketBuf + dev->uRCVBufPtr;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501 Packet passed address filter (is_padr=%d, is_bcast=%d, is_mcast=%d), size=%d\n", is_padr, is_bcast, is_mcast, size);
#endif
/* Receive status is evaluated from scratch. The stale bit must remain set until we know better. */
rcvstatnew.RcvStatNewReg = 0;
rcvstatnew.RcvStatNew.stale = 1;
dev->RcvStatReg = 0x80;
/* Detect errors: Runts, overflow, and FCS errors.
* NB: Dribble errors can not happen because we can only receive an
* integral number of bytes. FCS errors are only possible in loopback
* mode in case the FCS is deliberately corrupted.
*/
/* See if we need to pad, and how much. Have to be careful because the
* Receive Buffer Pointer might be near the end of the buffer.
*/
if (size < 60) {
/* In loopback mode only, short packets are flagged as errors because
* diagnostic tools want to see the errors. Otherwise they're padded to
* minimum length (if packet came over the wire, it should have been
* properly padded).
*/
/// @todo This really is kind of wrong. We shouldn't be doing any
/// padding here, it should be done by the sending side!
if (!fLoopback) {
memset(dev->abRuntBuf, 0, sizeof(dev->abRuntBuf));
memcpy(dev->abRuntBuf, src, size);
size = 60;
src = dev->abRuntBuf;
} else {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501 runt, size=%d\n", size);
#endif
rcvstatnew.RcvStatNew.runt = 1;
}
}
/* We don't care how big the frame is; if it fits into the buffer, all is
* good. But conversely if the Receive Buffer Pointer is initially near the
* end of the buffer, a small frame can trigger an overflow.
*/
if ((dev->uRCVBufPtr + size) <= ELNK_BUF_SIZE)
rcvstatnew.RcvStatNew.no_ovf = 1;
else {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501 overflow, size=%d\n", size);
#endif
rcvstatnew.RcvStatNew.oflow = 1;
}
if (fLoopback && dev->AuxCmd.xmit_bf) {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501 bad FCS\n");
#endif
rcvstatnew.RcvStatNew.fcs = 1;
}
/* Error-free packets are considered good. */
if (rcvstatnew.RcvStatNew.no_ovf && !rcvstatnew.RcvStatNew.fcs && !rcvstatnew.RcvStatNew.runt)
rcvstatnew.RcvStatNew.good = 1;
uint16_t cbCopy = (uint16_t) MIN(ELNK_BUF_SIZE - dev->uRCVBufPtr, size);
/* All packets that passed the address filter are copied to the buffer. */
/* Copy incoming data to the packet buffer. NB: Starts at the current
* Receive Buffer Pointer position.
*/
memcpy(dst, src, cbCopy);
/* Packet length is indicated via the receive buffer pointer. */
dev->uRCVBufPtr = (dev->uRCVBufPtr + cbCopy) & ELNK_GP_MASK;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501 Received packet, size=%d, RP=%u\n", cbCopy, dev->uRCVBufPtr);
#endif
/*
* If one of the "interesting" conditions was hit, stop receiving until
* the status register is read (mark it not stale).
* NB: The precise receive logic is not very well described in the EtherLink
* documentation. It was refined using the 3C501.EXE diagnostic utility.
*/
if ((rcvstatnew.RcvStatNew.good && dev->RcvCmd.acpt_good)
|| (rcvstatnew.RcvStatNew.no_ovf && dev->RcvCmd.det_eof)
|| (rcvstatnew.RcvStatNew.runt && dev->RcvCmd.det_runt)
|| (rcvstatnew.RcvStatNew.dribble && dev->RcvCmd.det_drbl)
|| (rcvstatnew.RcvStatNew.fcs && dev->RcvCmd.det_fcs)
|| (rcvstatnew.RcvStatNew.oflow && dev->RcvCmd.det_ofl)) {
dev->AuxStat.recv_bsy = 0;
dev->IntrState.recv_intr = 1;
rcvstatnew.RcvStatNew.stale = 0; /* Prevents further receive until set again. */
}
/* Finally update the receive status. */
dev->RcvStat = rcvstatnew.RcvStatNew;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: RcvCmd=%02X, RcvStat=%02X, RCVBufPtr=%u\n", dev->RcvCmdReg, dev->RcvStatReg, dev->uRCVBufPtr);
#endif
elnkUpdateIrq(dev);
}
return 1;
}
/**
* Actually try transmit frames.
*
* @threads TX or EMT.
*/
static void
elnkAsyncTransmit(threec501_t *dev)
{
/*
* Just drop it if not transmitting. Can happen with delayed transmits
* if transmit was disabled in the meantime.
*/
if (!dev->AuxStat.xmit_bsy) {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Nope, xmit disabled\n");
#endif
return;
}
if ((dev->AuxCmd.buf_ctl != EL_BCTL_XMT_RCV) && (dev->AuxCmd.buf_ctl != EL_BCTL_LOOPBACK)) {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Nope, not in xmit-then-receive or loopback state\n");
#endif
return;
}
/*
* Blast out data from the packet buffer.
*/
do {
/* Don't send anything when the link is down. */
if (!elnkIsLinkUp(dev)
&& dev->cLinkDownReported > ELNK_MAX_LINKDOWN_REPORTED)
break;
bool const fLoopback = dev->AuxCmd.buf_ctl == EL_BCTL_LOOPBACK;
/*
* Sending is easy peasy, there is by definition always
* a complete packet on hand.
*/
const unsigned cb = ELNK_BUF_SIZE - ELNK_GP(dev); /* Packet size. */
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: cb=%d, loopback=%d.\n", cb, fLoopback);
#endif
dev->XmitStatReg = 0; /* Clear transmit status before filling it out. */
if (elnkIsLinkUp(dev) || fLoopback) {
if (cb <= MAX_FRAME) {
if (fLoopback) {
elnkReceiveLocked(dev, &dev->abPacketBuf[ELNK_GP(dev)], cb);
} else {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: elnkAsyncTransmit: transmit loopbuf xmit pos = %d\n", cb);
#endif
network_tx(dev->netcard, &dev->abPacketBuf[ELNK_GP(dev)], cb);
}
dev->XmitStat.ready = 1;
} else {
/* Signal error, as this violates the Ethernet specs. */
/** @todo check if the correct error is generated. */
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: illegal giant frame (%u bytes) -> signalling error\n", cb);
#endif
}
} else {
/* Signal a transmit error pretending there was a collision. */
dev->cLinkDownReported++;
dev->XmitStat.coll = 1;
}
/* Transmit officially done, update register state. */
dev->AuxStat.xmit_bsy = 0;
dev->IntrState.xmit_intr = !!(dev->XmitCmdReg & dev->XmitStatReg);
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: XmitCmd=%02X, XmitStat=%02X\n", dev->XmitCmdReg, dev->XmitStatReg);
#endif
/* NB: After a transmit, the GP Buffer Pointer points just past
* the end of the packet buffer (3C501 diagnostics).
*/
dev->uGPBufPtr = ELNK_BUF_SIZE;
/* NB: The buffer control does *not* change to Receive and stays the way it was. */
if (!fLoopback) {
dev->AuxStat.recv_bsy = 1; /* Receive Busy now set until a packet is received. */
}
} while (0); /* No loop, because there isn't ever more than one packet to transmit. */
elnkUpdateIrq(dev);
}
static void
elnkCsrWrite(threec501_t *dev, uint8_t data)
{
bool fTransmit = false;
bool fReceive = false;
bool fDMAR;
int mode;
union {
uint8_t reg;
EL_AUX_CMD val;
} auxcmd;
auxcmd.reg = data;
/* Handle reset first. */
if (dev->AuxCmd.reset != auxcmd.val.reset) {
if (auxcmd.val.reset) {
/* Card is placed into reset. Just set the flag. NB: When in reset
* state, we permit writes to other registers, but those have no
* effect and will be overwritten when the card is taken out of reset.
*/
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Card going into reset\n");
#endif
dev->fInReset = true;
/* Many EtherLink drivers like to reset the card a lot. That can lead to
* packet loss if a packet was already received before the card was reset.
*/
} else {
/* Card is being taken out of reset. */
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Card going out of reset\n");
#endif
elnkSoftReset(dev);
}
dev->AuxCmd.reset = auxcmd.val.reset; /* Update the reset bit, if nothing else. */
}
/* If the card is in reset, stop right here. */
if (dev->fInReset) {
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Reset\n");
#endif
return;
}
/* Evaluate DMA state. If it changed, we'll have to go back to R3. */
fDMAR = auxcmd.val.dma_req && auxcmd.val.ride;
if (fDMAR != dev->fDMA) {
/* Start/stop DMA as requested. */
dev->fDMA = fDMAR;
if (fDMAR) {
dma_set_drq(dev->dma_channel, fDMAR);
mode = dma_mode(dev->dma_channel);
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: DMA Mode = %02x.\n", mode & 0x0c);
#endif
if ((mode & 0x0c) == 0x04) {
while (dev->dma_pos < (ELNK_BUF_SIZE - ELNK_GP(dev))) {
dma_channel_write(dev->dma_channel, dev->abPacketBuf[ELNK_GP(dev) + dev->dma_pos]);
dev->dma_pos++;
}
} else {
while (dev->dma_pos < (ELNK_BUF_SIZE - ELNK_GP(dev))) {
int dma_data = dma_channel_read(dev->dma_channel);
dev->abPacketBuf[ELNK_GP(dev) + dev->dma_pos] = dma_data & 0xff;
dev->dma_pos++;
}
}
dev->uGPBufPtr = (dev->uGPBufPtr + dev->dma_pos) & ELNK_GP_MASK;
dma_set_drq(dev->dma_channel, 0);
dev->dma_pos = 0;
dev->IntrState.dma_intr = 1;
dev->AuxStat.dma_done = 1;
elnkUpdateIrq(dev);
}
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: DMARQ for channel %u set to %u\n", dev->dma_channel, fDMAR);
#endif
}
/* Interrupt enable changes. */
if ((dev->AuxCmd.ire != auxcmd.val.ire) || (dev->AuxCmd.ride != auxcmd.val.ride)) {
dev->AuxStat.ride = dev->AuxCmd.ride = auxcmd.val.ride;
dev->AuxCmd.ire = auxcmd.val.ire; /* NB: IRE is not visible in the aux status register. */
}
/* DMA Request changes. */
if (dev->AuxCmd.dma_req != auxcmd.val.dma_req) {
dev->AuxStat.dma_req = dev->AuxCmd.dma_req = auxcmd.val.dma_req;
if (!auxcmd.val.dma_req) {
/* Clearing the DMA Request bit also clears the DMA Done status bit and any DMA interrupt. */
dev->IntrState.dma_intr = 0;
dev->AuxStat.dma_done = 0;
}
}
/* Packet buffer control changes. */
if (dev->AuxCmd.buf_ctl != auxcmd.val.buf_ctl) {
#ifdef ENABLE_3COM501_LOG
static const char *apszBuffCntrl[4] = { "System", "Xmit then Recv", "Receive", "Loopback" };
threec501_log("3Com501: Packet buffer control `%s' -> `%s'\n", apszBuffCntrl[dev->AuxCmd.buf_ctl], apszBuffCntrl[auxcmd.val.buf_ctl]);
#endif
if (auxcmd.val.buf_ctl == EL_BCTL_XMT_RCV) {
/* Transmit, then receive. */
fTransmit = true;
dev->AuxStat.recv_bsy = 0;
} else if (auxcmd.val.buf_ctl == EL_BCTL_SYSTEM) {
dev->AuxStat.xmit_bsy = 1; /* Transmit Busy is set here and cleared once actual transmit completes. */
dev->AuxStat.recv_bsy = 0;
} else if (auxcmd.val.buf_ctl == EL_BCTL_RECEIVE) {
/* Special case: If going from xmit-then-receive mode to receive mode, and we received
* a packet already (right after the receive), don't restart receive and lose the already
* received packet.
*/
if (!dev->uRCVBufPtr)
fReceive = true;
} else {
/* For loopback, we go through the regular transmit and receive path. That may be an
* overkill but the receive path is too complex for a special loopback-only case.
*/
fTransmit = true;
dev->AuxStat.recv_bsy = 1; /* Receive Busy now set until a packet is received. */
}
dev->AuxStat.buf_ctl = dev->AuxCmd.buf_ctl = auxcmd.val.buf_ctl;
}
/* NB: Bit 1 (xmit_bf, transmit packets with bad FCS) is a simple control
* bit which does not require special handling here. Just copy it over.
*/
dev->AuxStat.xmit_bf = dev->AuxCmd.xmit_bf = auxcmd.val.xmit_bf;
/* There are multiple bits that affect interrupt state. Handle them now. */
elnkUpdateIrq(dev);
/* After fully updating register state, do a transmit (including loopback) or receive. */
if (fTransmit)
elnkAsyncTransmit(dev);
else if (fReceive) {
dev->AuxStat.recv_bsy = 1; /* Receive Busy now set until a packet is received. */
}
}
static uint8_t
threec501_read(uint16_t addr, void *priv)
{
threec501_t *dev = (threec501_t *) priv;
uint8_t retval = 0xff;
switch (addr & 0x0f) {
case 0x00: /* Receive status register aliases. The SEEQ 8001 */
case 0x02: /* EDLC clearly only decodes one bit for reads. */
case 0x04:
case 0x06: /* Receive status register. */
retval = dev->RcvStatReg;
dev->RcvStat.stale = 1; /* Allows further reception. */
dev->IntrState.recv_intr = 0; /* Reading clears receive interrupt. */
elnkUpdateIrq(dev);
break;
case 0x01: /* Transmit status register aliases. */
case 0x03:
case 0x05:
case 0x07: /* Transmit status register. */
retval = dev->XmitStatReg;
dev->IntrState.xmit_intr = 0; /* Reading clears transmit interrupt. */
elnkUpdateIrq(dev);
break;
case 0x08: /* GP Buffer pointer LSB. */
retval = (dev->uGPBufPtr & 0xff);
break;
case 0x09: /* GP Buffer pointer MSB. */
retval = (dev->uGPBufPtr >> 8);
break;
case 0x0a: /* RCV Buffer pointer LSB. */
retval = (dev->uRCVBufPtr & 0xff);
break;
case 0x0b: /* RCV Buffer pointer MSB. */
retval = (dev->uRCVBufPtr >> 8);
break;
case 0x0c: /* Ethernet address PROM window. */
case 0x0d: /* Alias. */
/* Reads use low 3 bits of GP buffer pointer, no auto-increment. */
retval = dev->aPROM[dev->uGPBufPtr & 7];
break;
case 0x0e: /* Auxiliary status register. */
retval = dev->AuxStatReg;
break;
case 0x0f: /* Buffer window. */
/* Reads use low 11 bits of GP buffer pointer, auto-increment. */
retval = dev->abPacketBuf[ELNK_GP(dev)];
dev->uGPBufPtr = (dev->uGPBufPtr + 1) & ELNK_GP_MASK;
break;
default:
break;
}
elnkUpdateIrq(dev);
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: read addr %x, value %x\n", addr & 0x0f, retval);
#endif
return retval;
}
static uint8_t
threec501_nic_readb(uint16_t addr, void *priv)
{
return threec501_read(addr, priv);
}
static uint16_t
threec501_nic_readw(uint16_t addr, void *priv)
{
return threec501_read(addr, priv) | (threec501_read(addr + 1, priv) << 8);
}
static void
threec501_write(uint16_t addr, uint8_t value, void *priv)
{
threec501_t *dev = (threec501_t *) priv;
int reg = (addr & 0x0f);
switch (reg) {
case 0x00: /* Six bytes of station address. */
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x05:
dev->aStationAddr[reg] = value;
break;
case 0x06: /* Receive command. */
dev->RcvCmdReg = value;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Receive Command register set to %02X\n", dev->RcvCmdReg);
#endif
break;
case 0x07: /* Transmit command. */
dev->XmitCmdReg = value;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Transmit Command register set to %02X\n", dev->XmitCmdReg);
#endif
break;
case 0x08: /* GP Buffer pointer LSB. */
dev->uGPBufPtr = (dev->uGPBufPtr & 0xff00) | value;
break;
case 0x09: /* GP Buffer pointer MSB. */
dev->uGPBufPtr = (dev->uGPBufPtr & 0x00ff) | (value << 8);
break;
case 0x0a: /* RCV Buffer pointer clear. */
dev->uRCVBufPtr = 0;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: RCV Buffer Pointer cleared (%02X)\n", value);
#endif
break;
case 0x0b: /* RCV buffer pointer MSB. */
case 0x0c: /* Ethernet address PROM window. */
case 0x0d: /* Undocumented. */
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: Writing read-only register %02X!\n", reg);
#endif
break;
case 0x0e: /* Auxiliary Command (CSR). */
elnkCsrWrite(dev, value);
break;
case 0x0f: /* Buffer window. */
/* Writes use low 11 bits of GP buffer pointer, auto-increment. */
if (dev->AuxCmd.buf_ctl != EL_BCTL_SYSTEM) {
/// @todo Does this still increment GPBufPtr?
break;
}
dev->abPacketBuf[ELNK_GP(dev)] = value;
dev->uGPBufPtr = (dev->uGPBufPtr + 1) & ELNK_GP_MASK;
break;
default:
break;
}
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: write addr %x, value %x\n", reg, value);
#endif
}
static void
threec501_nic_writeb(uint16_t addr, uint8_t value, void *priv)
{
threec501_write(addr, value, priv);
}
static void
threec501_nic_writew(uint16_t addr, uint16_t value, void *priv)
{
threec501_write(addr, value & 0xff, priv);
threec501_write(addr + 1, value >> 8, priv);
}
static int
elnkSetLinkState(void *priv, uint32_t link_state)
{
threec501_t *dev = (threec501_t *) priv;
if (link_state & NET_LINK_TEMP_DOWN) {
elnkTempLinkDown(dev);
return 1;
}
bool link_up = !(link_state & NET_LINK_DOWN);
if (dev->fLinkUp != link_up) {
dev->fLinkUp = link_up;
if (link_up) {
dev->fLinkTempDown = 1;
dev->cLinkDownReported = 0;
dev->cLinkRestorePostponed = 0;
timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
} else {
dev->cLinkDownReported = 0;
dev->cLinkRestorePostponed = 0;
}
}
return 0;
}
static void
elnkR3TimerRestore(void *priv)
{
threec501_t *dev = (threec501_t *) priv;
if ((dev->cLinkDownReported <= ELNK_MAX_LINKDOWN_REPORTED) && (dev->cLinkRestorePostponed <= ELNK_MAX_LINKRST_POSTPONED)) {
timer_advance_u64(&dev->timer_restore, 1500000 * TIMER_USEC);
dev->cLinkRestorePostponed++;
} else {
dev->fLinkTempDown = 0;
}
}
static void *
threec501_nic_init(UNUSED(const device_t *info))
{
uint32_t mac;
threec501_t *dev;
dev = malloc(sizeof(threec501_t));
memset(dev, 0x00, sizeof(threec501_t));
dev->maclocal[0] = 0x02; /* 02:60:8C (3Com OID) */
dev->maclocal[1] = 0x60;
dev->maclocal[2] = 0x8C;
dev->base_address = device_get_config_hex16("base");
dev->base_irq = device_get_config_int("irq");
dev->dma_channel = device_get_config_int("dma");
dev->fLinkUp = 1;
dev->cMsLinkUpDelay = 5000;
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/*
* Make this device known to the I/O system.
* PnP and PCI devices start with address spaces inactive.
*/
io_sethandler(dev->base_address, 0x10,
threec501_nic_readb, threec501_nic_readw, NULL,
threec501_nic_writeb, threec501_nic_writew, NULL, dev);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
dev->maclocal[3] = random_generate();
dev->maclocal[4] = random_generate();
dev->maclocal[5] = random_generate();
mac = (((int) dev->maclocal[3]) << 16);
mac |= (((int) dev->maclocal[4]) << 8);
mac |= ((int) dev->maclocal[5]);
device_set_config_mac("mac", mac);
} else {
dev->maclocal[3] = (mac >> 16) & 0xff;
dev->maclocal[4] = (mac >> 8) & 0xff;
dev->maclocal[5] = (mac & 0xff);
}
/* Initialize the PROM */
memcpy(dev->aPROM, dev->maclocal, sizeof(dev->maclocal));
dev->aPROM[6] = dev->aPROM[7] = 0; /* The two padding bytes. */
#ifdef ENABLE_3COM501_LOG
threec501_log("I/O=%04x, IRQ=%d, DMA=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
dev->base_address, dev->base_irq, dev->dma_channel,
dev->aPROM[0], dev->aPROM[1], dev->aPROM[2],
dev->aPROM[3], dev->aPROM[4], dev->aPROM[5]);
#endif
/* Reset the board. */
elnkR3HardReset(dev);
/* Attach ourselves to the network module. */
dev->netcard = network_attach(dev, dev->aPROM, elnkReceiveLocked, elnkSetLinkState);
timer_add(&dev->timer_restore, elnkR3TimerRestore, dev, 0);
return dev;
}
static void
threec501_nic_close(void *priv)
{
threec501_t *dev = (threec501_t *) priv;
#ifdef ENABLE_3COM501_LOG
threec501_log("3Com501: closed\n");
#endif
free(dev);
}
static const device_config_t threec501_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x280", .value = 0x280 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x310", .value = 0x310 },
{ .description = "0x320", .value = 0x320 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2/9", .value = 9 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 6", .value = 6 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "" }
},
},
{
.name = "dma",
.description = "DMA channel",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "DMA 1", .value = 1 },
{ .description = "DMA 2", .value = 2 },
{ .description = "DMA 3", .value = 3 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
const device_t threec501_device = {
.name = "3Com EtherLink (3c500/3c501)",
.internal_name = "3c501",
.flags = DEVICE_ISA,
.local = 0,
.init = threec501_nic_init,
.close = threec501_nic_close,
.reset = elnkR3Reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = threec501_config
};
``` | /content/code_sandbox/src/network/net_3c501.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 11,299 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the AMD PCnet LANCE NIC controller for both the ISA, VLB,
* and PCI buses.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, <mariogplayer@gmail.com>
* Antony T Curtis
*
*/
#ifdef _WIN32
# include <winsock.h>
#else
# include <arpa/inet.h>
#endif
#include <inttypes.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#include <stdbool.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/random.h>
#include <86box/device.h>
#include <86box/isapnp.h>
#include <86box/timer.h>
#include <86box/thread.h>
#include <86box/network.h>
#include <86box/net_pcnet.h>
#include <86box/bswap.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
/* PCI info. */
#define PCI_VENDID 0x1022 /* AMD */
#define PCI_DEVID 0x2000 /* PCnet-PCI II (Am79c970A) */
#define PCI_REGSIZE 256 /* size of PCI space */
#pragma pack(1)
typedef struct RTNETETHERHDR {
uint8_t DstMac[6];
uint8_t SrcMac[6];
/** Ethernet frame type or frame size, depending on the kind of ethernet.
* This is big endian on the wire. */
uint16_t EtherType;
} RTNETETHERHDR;
#pragma pack()
#define BCR_MAX_RAP 50
#define MII_MAX_REG 32
#define CSR_MAX_REG 128
/** Maximum number of times we report a link down to the guest (failure to send frame) */
#define PCNET_MAX_LINKDOWN_REPORTED 3
/** Maximum frame size we handle */
#define MAX_FRAME 1536
/** @name Bus configuration registers
* @{ */
#define BCR_MSRDA 0
#define BCR_MSWRA 1
#define BCR_MC 2
#define BCR_RESERVED3 3
#define BCR_LNKST 4
#define BCR_LED1 5
#define BCR_LED2 6
#define BCR_LED3 7
#define BCR_SWCONFIG 8
#define BCR_FDC 9
/* 10 - 15 = reserved */
#define BCR_IOBASEL 16 /* Reserved */
#define BCR_IOBASEU 16 /* Reserved */
#define BCR_BSBC 18
#define BCR_EECAS 19
#define BCR_SWS 20
#define BCR_INTCON 21 /* Reserved */
#define BCR_PLAT 22
#define BCR_PCISVID 23
#define BCR_PCISID 24
#define BCR_SRAMSIZ 25
#define BCR_SRAMB 26
#define BCR_SRAMIC 27
#define BCR_EBADDRL 28
#define BCR_EBADDRU 29
#define BCR_EBD 30
#define BCR_STVAL 31
#define BCR_MIICAS 32
#define BCR_MIIADDR 33
#define BCR_MIIMDR 34
#define BCR_PCIVID 35
#define BCR_PMC_A 36
#define BCR_DATA0 37
#define BCR_DATA1 38
#define BCR_DATA2 39
#define BCR_DATA3 40
#define BCR_DATA4 41
#define BCR_DATA5 42
#define BCR_DATA6 43
#define BCR_DATA7 44
#define BCR_PMR1 45
#define BCR_PMR2 46
#define BCR_PMR3 47
/** @} */
/** @name Bus configuration sub register accessors.
* @{ */
#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080)
#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS] & 0x0100)
#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS] & 0x00FF)
/** @} */
/** @name CSR subregister accessors.
* @{ */
#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */
#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */
#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */
#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */
#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */
#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */
#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */
#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */
#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */
#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */
#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */
#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */
#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */
#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */
#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */
#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */
#define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */
#define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */
#define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */
#define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */
#define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */
#define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */
/** @name CSR register accessors.
* @{ */
#define CSR_IADR(S) (*(uint32_t *) ((S)->aCSR + 1)) /**< Initialization Block Address */
#define CSR_CRBA(S) (*(uint32_t *) ((S)->aCSR + 18)) /**< Current Receive Buffer Address */
#define CSR_CXBA(S) (*(uint32_t *) ((S)->aCSR + 20)) /**< Current Transmit Buffer Address */
#define CSR_NRBA(S) (*(uint32_t *) ((S)->aCSR + 22)) /**< Next Receive Buffer Address */
#define CSR_BADR(S) (*(uint32_t *) ((S)->aCSR + 24)) /**< Base Address of Receive Ring */
#define CSR_NRDA(S) (*(uint32_t *) ((S)->aCSR + 26)) /**< Next Receive Descriptor Address */
#define CSR_CRDA(S) (*(uint32_t *) ((S)->aCSR + 28)) /**< Current Receive Descriptor Address */
#define CSR_BADX(S) (*(uint32_t *) ((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */
#define CSR_NXDA(S) (*(uint32_t *) ((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */
#define CSR_CXDA(S) (*(uint32_t *) ((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */
#define CSR_NNRD(S) (*(uint32_t *) ((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */
#define CSR_NNXD(S) (*(uint32_t *) ((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */
#define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */
#define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */
#define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */
#define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */
#define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */
#define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */
#define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */
#define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */
#define CSR_PXDA(S) (*(uint32_t *) ((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/
#define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */
#define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */
#define CSR_NXBA(S) (*(uint32_t *) ((S)->aCSR + 64)) /**< Next Transmit Buffer Address */
#define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */
#define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */
#define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */
#define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */
#define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */
#define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */
#define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */
/** Calculates the full physical address. */
#define PHYSADDR(S, A) ((A) | (S)->GCUpperPhys)
static const uint8_t am79c961_pnp_rom[] = {
0x04, 0x96, 0x55, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, /* ADV55AA, dummy checksum (filled in by isapnp_add_card) */
0x0a, 0x10, 0x00, /* PnP version 1.0, vendor version 0.0 */
0x82, 0x1c, 0x00, 'A', 'M', 'D', ' ', 'E', 't', 'h', 'e', 'r', 'n', 'e', 't', ' ', 'N', 'e', 't', 'w', 'o', 'r', 'k', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r', /* ANSI identifier */
0x16, 0x04, 0x96, 0x55, 0xaa, 0x00, 0xbd, /* logical device ADV55AA, supports vendor-specific registers 0x38/0x3A/0x3B/0x3C/0x3D/0x3F */
0x1c, 0x41, 0xd0, 0x82, 0x8c, /* compatible device PNP828C */
0x47, 0x00, 0x00, 0x02, 0xe0, 0x03, 0x20, 0x18, /* I/O 0x200-0x3E0, decodes 10-bit, 32-byte alignment, 24 addresses */
0x2a, 0xe8, 0x02, /* DMA 3/5/6/7, compatibility, no count by word, no count by byte, not bus master, 16-bit only */
0x23, 0x38, 0x9e, 0x09, /* IRQ 3/4/5/9/10/11/12/15, low true level sensitive, high true edge sensitive */
0x79, 0x00 /* end tag, dummy checksum (filled in by isapnp_add_card) */
};
typedef struct {
mem_mapping_t mmio_mapping;
const char *name;
int board;
int is_pci, is_vlb, is_isa;
int PCIBase;
int MMIOBase;
uint32_t base_address;
int base_irq;
int dma_channel;
uint8_t pci_slot; /* PCI card slot */
uint8_t irq_state;
int xmit_pos;
/** Register Address Pointer */
uint32_t u32RAP;
/** Internal interrupt service */
int32_t iISR;
/** ??? */
uint32_t u32Lnkst;
/** Address of the RX descriptor table (ring). Loaded at init. */
uint32_t GCRDRA;
/** Address of the TX descriptor table (ring). Loaded at init. */
uint32_t GCTDRA;
uint8_t aPROM[256];
uint16_t aCSR[CSR_MAX_REG];
uint16_t aBCR[BCR_MAX_RAP];
uint16_t aMII[MII_MAX_REG];
/** The loopback transmit buffer (avoid stack allocations). */
uint8_t abLoopBuf[4096];
/** The recv buffer. */
uint8_t abRecvBuf[4096];
/** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */
int iLog2DescSize;
/** Bits 16..23 in 16-bit mode */
uint32_t GCUpperPhys;
/** We are waiting/about to start waiting for more receive buffers. */
int fMaybeOutOfSpace;
/** True if we signal the guest that RX packets are missing. */
int fSignalRxMiss;
/** Link speed to be reported through CSR68. */
uint32_t u32LinkSpeed;
/** Error counter for bad receive descriptors. */
uint32_t uCntBadRMD;
uint16_t u16CSR0LastSeenByGuest;
/** If set the link is currently up. */
int fLinkUp;
/** If set the link is temporarily down because of a saved state load. */
int fLinkTempDown;
/** Number of times we've reported the link down. */
uint32_t cLinkDownReported;
/** MS to wait before we enable the link. */
uint32_t cMsLinkUpDelay;
int transfer_size;
uint8_t maclocal[6]; /* configured MAC (local) address */
pc_timer_t timer, timer_soft_int, timer_restore;
netcard_t *netcard;
} nic_t;
/** @todo All structs: big endian? */
struct INITBLK16 {
uint16_t mode; /**< copied into csr15 */
uint16_t padr1; /**< MAC 0..15 */
uint16_t padr2; /**< MAC 16..32 */
uint16_t padr3; /**< MAC 33..47 */
uint16_t ladrf1; /**< logical address filter 0..15 */
uint16_t ladrf2; /**< logical address filter 16..31 */
uint16_t ladrf3; /**< logical address filter 32..47 */
uint16_t ladrf4; /**< logical address filter 48..63 */
uint32_t rdra : 24; /**< address of receive descriptor ring */
uint32_t res1 : 5; /**< reserved */
uint32_t rlen : 3; /**< number of receive descriptor ring entries */
uint32_t tdra : 24; /**< address of transmit descriptor ring */
uint32_t res2 : 5; /**< reserved */
uint32_t tlen : 3; /**< number of transmit descriptor ring entries */
};
/** bird: I've changed the type for the bitfields. They should only be 16-bit all together.
* frank: I've changed the bitfiled types to uint32_t to prevent compiler warnings. */
struct INITBLK32 {
uint16_t mode; /**< copied into csr15 */
uint16_t res1 : 4; /**< reserved */
uint16_t rlen : 4; /**< number of receive descriptor ring entries */
uint16_t res2 : 4; /**< reserved */
uint16_t tlen : 4; /**< number of transmit descriptor ring entries */
uint16_t padr1; /**< MAC 0..15 */
uint16_t padr2; /**< MAC 16..31 */
uint16_t padr3; /**< MAC 32..47 */
uint16_t res3; /**< reserved */
uint16_t ladrf1; /**< logical address filter 0..15 */
uint16_t ladrf2; /**< logical address filter 16..31 */
uint16_t ladrf3; /**< logical address filter 32..47 */
uint16_t ladrf4; /**< logical address filter 48..63 */
uint32_t rdra; /**< address of receive descriptor ring */
uint32_t tdra; /**< address of transmit descriptor ring */
};
/** Transmit Message Descriptor */
typedef struct TMD {
struct
{
uint32_t tbadr; /**< transmit buffer address */
} tmd0;
struct
{
uint32_t bcnt : 12; /**< buffer byte count (two's complement) */
uint32_t ones : 4; /**< must be 1111b */
uint32_t res : 7; /**< reserved */
uint32_t bpe : 1; /**< bus parity error */
uint32_t enp : 1; /**< end of packet */
uint32_t stp : 1; /**< start of packet */
uint32_t def : 1; /**< deferred */
uint32_t one : 1; /**< exactly one retry was needed to transmit a frame */
uint32_t ltint : 1; /**< suppress interrupts after successful transmission */
uint32_t nofcs : 1; /**< when set, the state of DXMTFCS is ignored and
transmitter FCS generation is activated. */
uint32_t err : 1; /**< error occurred */
uint32_t own : 1; /**< 0=owned by guest driver, 1=owned by controller */
} tmd1;
struct
{
uint32_t trc : 4; /**< transmit retry count */
uint32_t res : 12; /**< reserved */
uint32_t tdr : 10; /**< ??? */
uint32_t rtry : 1; /**< retry error */
uint32_t lcar : 1; /**< loss of carrier */
uint32_t lcol : 1; /**< late collision */
uint32_t exdef : 1; /**< excessive deferral */
uint32_t uflo : 1; /**< underflow error */
uint32_t buff : 1; /**< out of buffers (ENP not found) */
} tmd2;
struct
{
uint32_t res; /**< reserved for user defined space */
} tmd3;
} TMD;
/** Receive Message Descriptor */
typedef struct RMD {
struct
{
uint32_t rbadr; /**< receive buffer address */
} rmd0;
struct
{
uint32_t bcnt : 12; /**< buffer byte count (two's complement) */
uint32_t ones : 4; /**< must be 1111b */
uint32_t res : 4; /**< reserved */
uint32_t bam : 1; /**< broadcast address match */
uint32_t lafm : 1; /**< logical filter address match */
uint32_t pam : 1; /**< physical address match */
uint32_t bpe : 1; /**< bus parity error */
uint32_t enp : 1; /**< end of packet */
uint32_t stp : 1; /**< start of packet */
uint32_t buff : 1; /**< buffer error */
uint32_t crc : 1; /**< crc error on incoming frame */
uint32_t oflo : 1; /**< overflow error (lost all or part of incoming frame) */
uint32_t fram : 1; /**< frame error */
uint32_t err : 1; /**< error occurred */
uint32_t own : 1; /**< 0=owned by guest driver, 1=owned by controller */
} rmd1;
struct
{
uint32_t mcnt : 12; /**< message byte count */
uint32_t zeros : 4; /**< 0000b */
uint32_t rpc : 8; /**< receive frame tag */
uint32_t rcc : 8; /**< receive frame tag + reserved */
} rmd2;
struct
{
uint32_t res; /**< reserved for user defined space */
} rmd3;
} RMD;
static bar_t pcnet_pci_bar[3];
static uint8_t pcnet_pci_regs[PCI_REGSIZE];
static void pcnetAsyncTransmit(nic_t *dev);
static void pcnetPollRxTx(nic_t *dev);
static void pcnetUpdateIrq(nic_t *dev);
static uint16_t pcnet_bcr_readw(nic_t *dev, uint16_t rap);
static void pcnet_bcr_writew(nic_t *dev, uint16_t rap, uint16_t val);
static void pcnet_csr_writew(nic_t *dev, uint16_t rap, uint16_t val);
static int pcnetCanReceive(nic_t *dev);
#ifdef ENABLE_PCNET_LOG
int pcnet_do_log = ENABLE_PCNET_LOG;
static void
pcnet_log(int lvl, const char *fmt, ...)
{
va_list ap;
if (pcnet_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pcnet_log(lvl, fmt, ...)
#endif
static void
pcnet_do_irq(nic_t *dev, int issue)
{
if (dev->is_pci) {
if (issue)
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
} else {
if (issue)
picint(1 << dev->base_irq);
else
picintc(1 << dev->base_irq);
}
}
/**
* Checks if the link is up.
* @returns true if the link is up.
* @returns false if the link is down.
*/
static __inline int
pcnetIsLinkUp(nic_t *dev)
{
return !dev->fLinkTempDown && dev->fLinkUp;
}
/**
* Load transmit message descriptor
* Make sure we read the own flag first.
*
* @param pThis adapter private data
* @param addr physical address of the descriptor
* @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
* @return true if we own the descriptor, false otherwise
*/
static __inline int
pcnetTmdLoad(nic_t *dev, TMD *tmd, uint32_t addr, int fRetIfNotOwn)
{
uint8_t ownbyte;
uint8_t bytes[4] = { 0, 0, 0, 0 };
uint16_t xda[4];
uint32_t xda32[4];
if (BCR_SWSTYLE(dev) == 0) {
dma_bm_read(addr, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) &xda[0], sizeof(xda), dev->transfer_size);
((uint32_t *) tmd)[0] = (uint32_t) xda[0] | ((uint32_t) (xda[1] & 0x00ff) << 16);
((uint32_t *) tmd)[1] = (uint32_t) xda[2] | ((uint32_t) (xda[1] & 0xff00) << 16);
((uint32_t *) tmd)[2] = (uint32_t) xda[3] << 16;
((uint32_t *) tmd)[3] = 0;
} else if (BCR_SWSTYLE(dev) != 3) {
dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) tmd, 16, dev->transfer_size);
} else {
dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) &xda32[0], sizeof(xda32), dev->transfer_size);
((uint32_t *) tmd)[0] = xda32[2];
((uint32_t *) tmd)[1] = xda32[1];
((uint32_t *) tmd)[2] = xda32[0];
((uint32_t *) tmd)[3] = xda32[3];
}
/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
if (tmd->tmd1.own == 1 && !(ownbyte & 0x80))
pcnet_log(3, "%s: pcnetTmdLoad: own bit flipped while reading!!\n", dev->name);
if (!(ownbyte & 0x80))
tmd->tmd1.own = 0;
return !!tmd->tmd1.own;
}
/**
* Store transmit message descriptor and hand it over to the host (the VM guest).
* Make sure that all data are transmitted before we clear the own flag.
*/
static __inline void
pcnetTmdStorePassHost(nic_t *dev, TMD *tmd, uint32_t addr)
{
uint16_t xda[4];
uint32_t xda32[3];
if (BCR_SWSTYLE(dev) == 0) {
xda[0] = ((uint32_t *) tmd)[0] & 0xffff;
xda[1] = ((((uint32_t *) tmd)[0] >> 16) & 0xff) | ((((uint32_t *) tmd)[1] >> 16) & 0xff00);
xda[2] = ((uint32_t *) tmd)[1] & 0xffff;
xda[3] = ((uint32_t *) tmd)[2] >> 16;
#if 0
xda[1] |= 0x8000;
dma_bm_write(addr, (uint8_t*)&xda[0], sizeof(xda), dev->transfer_size);
#endif
xda[1] &= ~0x8000;
dma_bm_write(addr, (uint8_t *) &xda[0], sizeof(xda), dev->transfer_size);
} else if (BCR_SWSTYLE(dev) != 3) {
#if 0
((uint32_t*)tmd)[1] |= 0x80000000;
dma_bm_write(addr, (uint8_t*)tmd, 12, dev->transfer_size);
#endif
((uint32_t *) tmd)[1] &= ~0x80000000;
dma_bm_write(addr, (uint8_t *) tmd, 12, dev->transfer_size);
} else {
xda32[0] = ((uint32_t *) tmd)[2];
xda32[1] = ((uint32_t *) tmd)[1];
xda32[2] = ((uint32_t *) tmd)[0];
#if 0
xda32[1] |= 0x80000000;
dma_bm_write(addr, (uint8_t*)&xda32[0], sizeof(xda32), dev->transfer_size);
#endif
xda32[1] &= ~0x80000000;
dma_bm_write(addr, (uint8_t *) &xda32[0], sizeof(xda32), dev->transfer_size);
}
}
/**
* Load receive message descriptor
* Make sure we read the own flag first.
*
* @param pThis adapter private data
* @param addr physical address of the descriptor
* @param fRetIfNotOwn return immediately after reading the own flag if we don't own the descriptor
* @return true if we own the descriptor, false otherwise
*/
static __inline int
pcnetRmdLoad(nic_t *dev, RMD *rmd, uint32_t addr, int fRetIfNotOwn)
{
uint8_t ownbyte;
uint8_t bytes[4] = { 0, 0, 0, 0 };
uint16_t rda[4];
uint32_t rda32[4];
if (BCR_SWSTYLE(dev) == 0) {
dma_bm_read(addr, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) &rda[0], sizeof(rda), dev->transfer_size);
((uint32_t *) rmd)[0] = (uint32_t) rda[0] | ((rda[1] & 0x00ff) << 16);
((uint32_t *) rmd)[1] = (uint32_t) rda[2] | ((rda[1] & 0xff00) << 16);
((uint32_t *) rmd)[2] = (uint32_t) rda[3];
((uint32_t *) rmd)[3] = 0;
} else if (BCR_SWSTYLE(dev) != 3) {
dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) rmd, 16, dev->transfer_size);
} else {
dma_bm_read(addr + 4, (uint8_t *) bytes, 4, dev->transfer_size);
ownbyte = bytes[3];
if (!(ownbyte & 0x80) && fRetIfNotOwn)
return 0;
dma_bm_read(addr, (uint8_t *) &rda32[0], sizeof(rda32), dev->transfer_size);
((uint32_t *) rmd)[0] = rda32[2];
((uint32_t *) rmd)[1] = rda32[1];
((uint32_t *) rmd)[2] = rda32[0];
((uint32_t *) rmd)[3] = rda32[3];
}
/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */
if (rmd->rmd1.own == 1 && !(ownbyte & 0x80))
pcnet_log(3, "%s: pcnetRmdLoad: own bit flipped while reading!!\n", dev->name);
if (!(ownbyte & 0x80))
rmd->rmd1.own = 0;
return !!rmd->rmd1.own;
}
/**
* Store receive message descriptor and hand it over to the host (the VM guest).
* Make sure that all data are transmitted before we clear the own flag.
*/
static __inline void
pcnetRmdStorePassHost(nic_t *dev, RMD *rmd, uint32_t addr)
{
uint16_t rda[4];
uint32_t rda32[3];
if (BCR_SWSTYLE(dev) == 0) {
rda[0] = ((uint32_t *) rmd)[0] & 0xffff;
rda[1] = ((((uint32_t *) rmd)[0] >> 16) & 0xff) | ((((uint32_t *) rmd)[1] >> 16) & 0xff00);
rda[2] = ((uint32_t *) rmd)[1] & 0xffff;
rda[3] = ((uint32_t *) rmd)[2] & 0xffff;
#if 0
rda[1] |= 0x8000;
dma_bm_write(addr, (uint8_t*)&rda[0], sizeof(rda), dev->transfer_size);
#endif
rda[1] &= ~0x8000;
dma_bm_write(addr, (uint8_t *) &rda[0], sizeof(rda), dev->transfer_size);
} else if (BCR_SWSTYLE(dev) != 3) {
#if 0
((uint32_t*)rmd)[1] |= 0x80000000;
dma_bm_write(addr, (uint8_t*)rmd, 12, dev->transfer_size);
#endif
((uint32_t *) rmd)[1] &= ~0x80000000;
dma_bm_write(addr, (uint8_t *) rmd, 12, dev->transfer_size);
} else {
rda32[0] = ((uint32_t *) rmd)[2];
rda32[1] = ((uint32_t *) rmd)[1];
rda32[2] = ((uint32_t *) rmd)[0];
#if 0
rda32[1] |= 0x80000000;
dma_bm_write(addr, (uint8_t*)&rda32[0], sizeof(rda32), dev->transfer_size);
#endif
rda32[1] &= ~0x80000000;
dma_bm_write(addr, (uint8_t *) &rda32[0], sizeof(rda32), dev->transfer_size);
}
}
/** Checks if it's a bad (as in invalid) RMD.*/
#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15)
/** The network card is the owner of the RDTE/TDTE, actually it is this driver */
#define CARD_IS_OWNER(desc) (((desc) &0x8000))
/** The host is the owner of the RDTE/TDTE -- actually the VM guest. */
#define HOST_IS_OWNER(desc) (!((desc) &0x8000))
#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */
# define ETHER_IS_MULTICAST(a) ((*(uint8_t *) (a)) & 1)
#endif
#define ETHER_ADDR_LEN ETH_ALEN
#define ETH_ALEN 6
#pragma pack(1)
struct ether_header /** @todo Use RTNETETHERHDR */
{
uint8_t ether_dhost[ETH_ALEN]; /**< destination ethernet address */
uint8_t ether_shost[ETH_ALEN]; /**< source ethernet address */
uint16_t ether_type; /**< packet type ID field */
};
#pragma pack()
#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
#define MULTICAST_FILTER_LEN 8
static __inline uint32_t
lnc_mchash(const uint8_t *ether_addr)
{
#define LNC_POLYNOMIAL 0xEDB88320UL
uint32_t crc = 0xFFFFFFFF;
int bit;
uint8_t data;
for (uint8_t idx = 0; idx < ETHER_ADDR_LEN; idx++) {
for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
data >>= 1;
}
}
return crc;
#undef LNC_POLYNOMIAL
}
#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
/* generated using the AUTODIN II polynomial
* x^32 + x^26 + x^23 + x^22 + x^16 +
* x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
*/
static const uint32_t crctab[256] =
{
0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
};
static __inline int
padr_match(nic_t *dev, const uint8_t *buf, UNUSED(int size))
{
const struct ether_header *hdr = (const struct ether_header *) buf;
int result;
uint8_t padr[6];
padr[0] = dev->aCSR[12] & 0xff;
padr[1] = dev->aCSR[12] >> 8;
padr[2] = dev->aCSR[13] & 0xff;
padr[3] = dev->aCSR[13] >> 8;
padr[4] = dev->aCSR[14] & 0xff;
padr[5] = dev->aCSR[14] >> 8;
result = !CSR_DRCVPA(dev) && !memcmp(hdr->ether_dhost, padr, 6);
pcnet_log(3, "%s: packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
"padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n",
dev->name,
hdr->ether_dhost[0], hdr->ether_dhost[1], hdr->ether_dhost[2],
hdr->ether_dhost[3], hdr->ether_dhost[4], hdr->ether_dhost[5],
padr[0], padr[1], padr[2], padr[3], padr[4], padr[5], result);
return result;
}
static __inline int
padr_bcast(nic_t *dev, const uint8_t *buf, UNUSED(size_t size))
{
static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const struct ether_header *hdr = (const struct ether_header *) buf;
int result = !CSR_DRCVBC(dev) && !memcmp(hdr->ether_dhost, aBCAST, 6);
pcnet_log(3, "%s: padr_bcast result=%d\n", dev->name, result);
return result;
}
static int
ladr_match(nic_t *dev, const uint8_t *buf, UNUSED(size_t size))
{
const struct ether_header *hdr = (const struct ether_header *) buf;
uint64_t *p = (uint64_t *) &dev->aCSR[8];
if ((hdr->ether_dhost[0] & 0x01) && p[0] != 0LL) {
int index;
uint8_t ladr[8];
ladr[0] = dev->aCSR[8] & 0xff;
ladr[1] = dev->aCSR[8] >> 8;
ladr[2] = dev->aCSR[9] & 0xff;
ladr[3] = dev->aCSR[9] >> 8;
ladr[4] = dev->aCSR[10] & 0xff;
ladr[5] = dev->aCSR[10] >> 8;
ladr[6] = dev->aCSR[11] & 0xff;
ladr[7] = dev->aCSR[11] >> 8;
index = lnc_mchash(hdr->ether_dhost) >> 26;
return (ladr[index >> 3] & (1 << (index & 7)));
}
return 0;
}
/**
* Get the receive descriptor ring address with a given index.
*/
static __inline uint32_t
pcnetRdraAddr(nic_t *dev, int idx)
{
return dev->GCRDRA + ((CSR_RCVRL(dev) - idx) << dev->iLog2DescSize);
}
/**
* Get the transmit descriptor ring address with a given index.
*/
static __inline uint32_t
pcnetTdraAddr(nic_t *dev, int idx)
{
return dev->GCTDRA + ((CSR_XMTRL(dev) - idx) << dev->iLog2DescSize);
}
static void
pcnetSoftReset(nic_t *dev)
{
pcnet_log(3, "%s: pcnetSoftReset\n", dev->name);
dev->u32Lnkst = 0x40;
dev->GCRDRA = 0;
dev->GCTDRA = 0;
dev->u32RAP = 0;
dev->aCSR[0] = 0x0004;
dev->aCSR[3] = 0x0000;
dev->aCSR[4] = 0x0115;
dev->aCSR[5] = 0x0000;
dev->aCSR[6] = 0x0000;
dev->aCSR[8] = 0;
dev->aCSR[9] = 0;
dev->aCSR[10] = 0;
dev->aCSR[11] = 0;
dev->aCSR[12] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[0]);
dev->aCSR[13] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[1]);
dev->aCSR[14] = le16_to_cpu(((uint16_t *) &dev->aPROM[0])[2]);
dev->aCSR[15] &= 0x21c4;
CSR_RCVRC(dev) = 1;
CSR_XMTRC(dev) = 1;
CSR_RCVRL(dev) = 1;
CSR_XMTRL(dev) = 1;
dev->aCSR[80] = 0x1410;
switch (dev->board) {
case DEV_AM79C970A:
dev->aCSR[88] = 0x1003;
dev->aCSR[89] = 0x0262;
break;
case DEV_AM79C973:
dev->aCSR[88] = 0x5003;
dev->aCSR[89] = 0x0262;
break;
case DEV_AM79C960:
case DEV_AM79C960_EB:
case DEV_AM79C960_VLB:
case DEV_AM79C961:
dev->aCSR[88] = 0x3003;
dev->aCSR[89] = 0x0000;
break;
default:
break;
}
dev->aCSR[94] = 0x0000;
dev->aCSR[100] = 0x0200;
dev->aCSR[103] = 0x0105;
CSR_MISSC(dev) = 0;
dev->aCSR[114] = 0x0000;
dev->aCSR[122] = 0x0000;
dev->aCSR[124] = 0x0000;
}
static void
pcnetUpdateIrq(nic_t *dev)
{
int iISR = 0;
uint16_t csr0;
csr0 = dev->aCSR[0];
csr0 &= ~0x0080; /* clear INTR */
if (((csr0 & ~dev->aCSR[3]) & 0x5f00) || (((dev->aCSR[4] >> 1) & ~dev->aCSR[4]) & 0x0115) || (((dev->aCSR[5] >> 1) & dev->aCSR[5]) & 0x0048)) {
iISR = !!(csr0 & 0x0040); /* CSR_INEA */
csr0 |= 0x0080; /* set INTR */
}
if (dev->aCSR[4] & 0x0080) { /* UINTCMD */
dev->aCSR[4] &= ~0x0080; /* clear UINTCMD */
dev->aCSR[4] |= 0x0040; /* set UINT */
pcnet_log(2, "%s: user int\n", dev->name);
}
if (dev->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */) {
csr0 |= 0x0080; /* set INTR */
iISR = 1;
}
if (((dev->aCSR[5] >> 1) & dev->aCSR[5]) & 0x0500) {
iISR = 1;
csr0 |= 0x0080; /* set INTR */
}
if ((dev->aCSR[7] & 0x0c00) == 0x0c00) /* STINT + STINTE */
iISR = 1;
dev->aCSR[0] = csr0;
pcnet_log(2, "%s: pcnetUpdateIrq: iISR=%d\n", dev->name, iISR);
pcnet_do_irq(dev, iISR);
dev->iISR = iISR;
}
static void
pcnetInit(nic_t *dev)
{
pcnet_log(3, "%s: pcnetInit: init_addr=%#010x\n", dev->name, PHYSADDR(dev, CSR_IADR(dev)));
/** @todo Documentation says that RCVRL and XMTRL are stored as two's complement!
* Software is allowed to write these registers directly. */
#define PCNET_INIT() \
do { \
dma_bm_read(PHYSADDR(dev, CSR_IADR(dev)), \
(uint8_t *) &initblk, sizeof(initblk), dev->transfer_size); \
dev->aCSR[15] = le16_to_cpu(initblk.mode); \
CSR_RCVRL(dev) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \
CSR_XMTRL(dev) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \
dev->aCSR[6] = (initblk.tlen << 12) | (initblk.rlen << 8); \
dev->aCSR[8] = le16_to_cpu(initblk.ladrf1); \
dev->aCSR[9] = le16_to_cpu(initblk.ladrf2); \
dev->aCSR[10] = le16_to_cpu(initblk.ladrf3); \
dev->aCSR[11] = le16_to_cpu(initblk.ladrf4); \
dev->aCSR[12] = le16_to_cpu(initblk.padr1); \
dev->aCSR[13] = le16_to_cpu(initblk.padr2); \
dev->aCSR[14] = le16_to_cpu(initblk.padr3); \
dev->GCRDRA = PHYSADDR(dev, initblk.rdra); \
dev->GCTDRA = PHYSADDR(dev, initblk.tdra); \
} while (0)
if (BCR_SSIZE32(dev)) {
struct INITBLK32 initblk;
dev->GCUpperPhys = 0;
PCNET_INIT();
pcnet_log(3, "%s: initblk.rlen=%#04x, initblk.tlen=%#04x\n",
dev->name, initblk.rlen, initblk.tlen);
} else {
struct INITBLK16 initblk;
dev->GCUpperPhys = (0xff00 & (uint32_t) dev->aCSR[2]) << 16;
PCNET_INIT();
pcnet_log(3, "%s: initblk.rlen=%#04x, initblk.tlen=%#04x\n",
dev->name, initblk.rlen, initblk.tlen);
}
#undef PCNET_INIT
size_t cbRxBuffers = 0;
for (int i = CSR_RCVRL(dev); i >= 1; i--) {
RMD rmd;
uint32_t rdaddr = PHYSADDR(dev, pcnetRdraAddr(dev, i));
/* At this time it is not guaranteed that the buffers are already initialized. */
if (pcnetRmdLoad(dev, &rmd, rdaddr, 0)) {
uint32_t cbBuf = 4096U - rmd.rmd1.bcnt;
cbRxBuffers += cbBuf;
}
}
/*
* Heuristics: The Solaris pcn driver allocates too few RX buffers (128 buffers of a
* size of 128 bytes are 16KB in summary) leading to frequent RX buffer overflows. In
* that case we don't signal RX overflows through the CSR0_MISS flag as the driver
* re-initializes the device on every miss. Other guests use at least 32 buffers of
* usually 1536 bytes and should therefore not run into condition. If they are still
* short in RX buffers we notify this condition.
*/
dev->fSignalRxMiss = (cbRxBuffers == 0 || cbRxBuffers >= 32 * 1024);
CSR_RCVRC(dev) = CSR_RCVRL(dev);
CSR_XMTRC(dev) = CSR_XMTRL(dev);
/* Reset cached RX and TX states */
CSR_CRST(dev) = CSR_CRBC(dev) = CSR_NRST(dev) = CSR_NRBC(dev) = 0;
CSR_CXST(dev) = CSR_CXBC(dev) = CSR_NXST(dev) = CSR_NXBC(dev) = 0;
pcnet_log(1, "%s: Init: SWSTYLE=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",
dev->name, BCR_SWSTYLE(dev),
dev->GCRDRA, CSR_RCVRL(dev), dev->GCTDRA, CSR_XMTRL(dev),
!dev->fSignalRxMiss ? " (CSR0_MISS disabled)" : "");
if (dev->GCRDRA & (dev->iLog2DescSize - 1))
pcnet_log(1, "%s: Warning: Misaligned RDRA\n", dev->name);
if (dev->GCTDRA & (dev->iLog2DescSize - 1))
pcnet_log(1, "%s: Warning: Misaligned TDRA\n", dev->name);
dev->aCSR[0] |= 0x0101; /* Initialization done */
dev->aCSR[0] &= ~0x0004; /* clear STOP bit */
}
/**
* Start RX/TX operation.
*/
static void
pcnetStart(nic_t *dev)
{
pcnet_log(3, "%s: pcnetStart: Poll timer\n", dev->name);
/* Reset any cached RX/TX descriptor state. */
CSR_CRDA(dev) = CSR_CRBA(dev) = CSR_NRDA(dev) = CSR_NRBA(dev) = 0;
CSR_CRBC(dev) = CSR_NRBC(dev) = CSR_CRST(dev) = 0;
if (!CSR_DTX(dev))
dev->aCSR[0] |= 0x0010; /* set TXON */
if (!CSR_DRX(dev))
dev->aCSR[0] |= 0x0020; /* set RXON */
dev->aCSR[0] &= ~0x0004; /* clear STOP bit */
dev->aCSR[0] |= 0x0002; /* STRT */
timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC);
}
/**
* Stop RX/TX operation.
*/
static void
pcnetStop(nic_t *dev)
{
pcnet_log(3, "%s: pcnetStop: Poll timer\n", dev->name);
dev->aCSR[0] = 0x0004;
dev->aCSR[4] &= ~0x02c2;
dev->aCSR[5] &= ~0x0011;
timer_disable(&dev->timer);
}
/**
* Poll Receive Descriptor Table Entry and cache the results in the appropriate registers.
* Note: Once a descriptor belongs to the network card (this driver), it cannot be changed
* by the host (the guest driver) anymore. Well, it could but the results are undefined by
* definition.
*/
static void
pcnetRdtePoll(nic_t *dev)
{
/* assume lack of a next receive descriptor */
CSR_NRST(dev) = 0;
if (dev->GCRDRA) {
/*
* The current receive message descriptor.
*/
RMD rmd;
int i = CSR_RCVRC(dev);
uint32_t addr;
if (i < 1)
i = CSR_RCVRL(dev);
addr = pcnetRdraAddr(dev, i);
CSR_CRDA(dev) = CSR_CRBA(dev) = 0;
CSR_CRBC(dev) = CSR_CRST(dev) = 0;
if (!pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, addr), 1))
return;
if (!IS_RMD_BAD(rmd)) {
CSR_CRDA(dev) = addr; /* Receive Descriptor Address */
CSR_CRBA(dev) = rmd.rmd0.rbadr; /* Receive Buffer Address */
CSR_CRBC(dev) = rmd.rmd1.bcnt; /* Receive Byte Count */
CSR_CRST(dev) = ((uint32_t *) &rmd)[1] >> 16; /* Receive Status */
} else {
/* This is not problematic since we don't own the descriptor
* We actually do own it, otherwise pcnetRmdLoad would have returned false.
* Don't flood the release log with errors.
*/
if (++dev->uCntBadRMD < 50)
pcnet_log(1, "%s: BAD RMD ENTRIES AT %#010x (i=%d)\n",
dev->name, addr, i);
return;
}
/*
* The next descriptor.
*/
if (--i < 1)
i = CSR_RCVRL(dev);
addr = pcnetRdraAddr(dev, i);
CSR_NRDA(dev) = CSR_NRBA(dev) = 0;
CSR_NRBC(dev) = 0;
if (!pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, addr), 1))
return;
if (!IS_RMD_BAD(rmd)) {
CSR_NRDA(dev) = addr; /* Receive Descriptor Address */
CSR_NRBA(dev) = rmd.rmd0.rbadr; /* Receive Buffer Address */
CSR_NRBC(dev) = rmd.rmd1.bcnt; /* Receive Byte Count */
CSR_NRST(dev) = ((uint32_t *) &rmd)[1] >> 16; /* Receive Status */
} else {
/* This is not problematic since we don't own the descriptor
* We actually do own it, otherwise pcnetRmdLoad would have returned false.
* Don't flood the release log with errors.
*/
if (++dev->uCntBadRMD < 50)
pcnet_log(1, "%s: BAD RMD ENTRIES + AT %#010x (i=%d)\n",
dev->name, addr, i);
return;
}
/**
* @todo NNRD
*/
} else {
CSR_CRDA(dev) = CSR_CRBA(dev) = CSR_NRDA(dev) = CSR_NRBA(dev) = 0;
CSR_CRBC(dev) = CSR_NRBC(dev) = CSR_CRST(dev) = 0;
}
}
/**
* Poll Transmit Descriptor Table Entry
* @return true if transmit descriptors available
*/
static int
pcnetTdtePoll(nic_t *dev, TMD *tmd)
{
if (dev->GCTDRA) {
uint32_t cxda = pcnetTdraAddr(dev, CSR_XMTRC(dev));
if (!pcnetTmdLoad(dev, tmd, PHYSADDR(dev, cxda), 1))
return 0;
if (tmd->tmd1.ones != 15) {
pcnet_log(1, "%s: BAD TMD XDA=%#010x\n",
dev->name, PHYSADDR(dev, cxda));
return 0;
}
/* previous xmit descriptor */
CSR_PXDA(dev) = CSR_CXDA(dev);
CSR_PXBC(dev) = CSR_CXBC(dev);
CSR_PXST(dev) = CSR_CXST(dev);
/* set current transmit descriptor. */
CSR_CXDA(dev) = cxda;
CSR_CXBC(dev) = tmd->tmd1.bcnt;
CSR_CXST(dev) = ((uint32_t *) tmd)[1] >> 16;
return CARD_IS_OWNER(CSR_CXST(dev));
} else {
/** @todo consistency with previous receive descriptor */
CSR_CXDA(dev) = 0;
CSR_CXBC(dev) = CSR_CXST(dev) = 0;
return 0;
}
}
/**
* Poll Transmit Descriptor Table Entry
* @return true if transmit descriptors available
*/
static int
pcnetCalcPacketLen(nic_t *dev, int cb)
{
TMD tmd;
int cbPacket = cb;
uint32_t iDesc = CSR_XMTRC(dev);
uint32_t iFirstDesc = iDesc;
do {
/* Advance the ring counter */
if (iDesc < 2)
iDesc = CSR_XMTRL(dev);
else
iDesc--;
if (iDesc == iFirstDesc)
break;
uint32_t addrDesc = pcnetTdraAddr(dev, iDesc);
if (!pcnetTmdLoad(dev, &tmd, PHYSADDR(dev, addrDesc), 1)) {
/*
* No need to count further since this packet won't be sent anyway
* due to underflow.
*/
pcnet_log(3, "%s: pcnetCalcPacketLen: underflow, return %u\n", dev->name, cbPacket);
return cbPacket;
}
if (tmd.tmd1.ones != 15) {
pcnet_log(1, "%s: BAD TMD XDA=%#010x\n",
dev->name, PHYSADDR(dev, addrDesc));
pcnet_log(3, "%s: pcnetCalcPacketLen: bad TMD, return %u\n", dev->name, cbPacket);
return cbPacket;
}
pcnet_log(3, "%s: pcnetCalcPacketLen: got valid TMD, cb=%u\n", dev->name, 4096 - tmd.tmd1.bcnt);
cbPacket += 4096 - tmd.tmd1.bcnt;
} while (!tmd.tmd1.enp);
pcnet_log(3, "#%d pcnetCalcPacketLen: return %u\n", dev->name, cbPacket);
return cbPacket;
}
/**
* Write data into guest receive buffers.
*/
static int
pcnetReceiveNoSync(void *priv, uint8_t *buf, int size)
{
nic_t *dev = (nic_t *) priv;
int is_padr = 0;
int is_bcast = 0;
int is_ladr = 0;
uint32_t iRxDesc;
int cbPacket;
uint8_t buf1[60];
RMD rmd = { 0 };
if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev) || !size)
return 0;
/* if too small buffer, then expand it */
if (size < 60) {
memcpy(buf1, buf, size);
memset(buf1 + size, 0, 60 - size);
buf = buf1;
size = 60;
}
/*
* Drop packets if the cable is not connected
*/
if (!pcnetIsLinkUp(dev))
return 0;
dev->fMaybeOutOfSpace = !pcnetCanReceive(dev);
if (dev->fMaybeOutOfSpace)
return 0;
pcnet_log(1, "%s: pcnetReceiveNoSync: RX %x:%x:%x:%x:%x:%x > %x:%x:%x:%x:%x:%x len %d\n", dev->name,
buf[6], buf[7], buf[8], buf[9], buf[10], buf[11],
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
size);
/*
* Perform address matching.
*/
if (CSR_PROM(dev)
|| (is_padr = padr_match(dev, buf, size))
|| (is_bcast = padr_bcast(dev, buf, size))
|| (is_ladr = ladr_match(dev, buf, size))) {
if (HOST_IS_OWNER(CSR_CRST(dev)))
pcnetRdtePoll(dev);
if (HOST_IS_OWNER(CSR_CRST(dev))) {
/* Not owned by controller. This should not be possible as
* we already called pcnetCanReceive(). */
const unsigned cb = 1 << dev->iLog2DescSize;
uint32_t GCPhys = dev->GCRDRA;
iRxDesc = CSR_RCVRL(dev);
while (iRxDesc-- > 0) {
pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, GCPhys), 0);
GCPhys += cb;
}
dev->aCSR[0] |= 0x1000; /* Set MISS flag */
CSR_MISSC(dev)
++;
pcnet_log(2, "%s: pcnetReceiveNoSync: packet missed\n", dev->name);
} else {
const RTNETETHERHDR *pEth = (RTNETETHERHDR *) buf;
int fStrip = 0;
size_t len_802_3;
uint8_t *src = &dev->abRecvBuf[8];
uint32_t crda = CSR_CRDA(dev);
uint32_t next_crda;
RMD rmd;
RMD next_rmd;
/*
* Ethernet framing considers these two octets to be
* payload type; 802.3 framing considers them to be
* payload length. IEEE 802.3x-1997 restricts Ethernet
* type to be greater than or equal to 1536 (0x0600), so
* that both framings can coexist on the wire.
*
* NB: CSR_ASTRP_RCV bit affects only 802.3 frames!
*/
len_802_3 = cpu_to_be16(pEth->EtherType);
if (len_802_3 < 46 && CSR_ASTRP_RCV(dev)) {
size = MIN(sizeof(RTNETETHERHDR) + len_802_3, size);
fStrip = 1;
}
memcpy(src, buf, size);
if (!fStrip) {
/* In loopback mode, Runt Packed Accept is always enabled internally;
* don't do any padding because guest may be looping back very short packets.
*/
if (!CSR_LOOP(dev))
while (size < 60)
src[size++] = 0;
uint32_t fcs = UINT32_MAX;
const uint8_t *p = src;
while (p != &src[size])
CRC(fcs, *p++);
/* FCS at the end of the packet */
((uint32_t *) &src[size])[0] = htonl(fcs);
size += 4;
}
cbPacket = size;
pcnetRmdLoad(dev, &rmd, PHYSADDR(dev, crda), 0);
/* if (!CSR_LAPPEN(dev)) */
rmd.rmd1.stp = 1;
size_t cbBuf = MIN(4096 - rmd.rmd1.bcnt, size);
uint32_t rbadr = PHYSADDR(dev, rmd.rmd0.rbadr);
/* save the old value to check if it was changed as long as we didn't
* hold the critical section */
iRxDesc = CSR_RCVRC(dev);
/* We have to leave the critical section here or we risk deadlocking
* with EMT when the write is to an unallocated page or has an access
* handler associated with it.
*
* This shouldn't be a problem because:
* - any modification to the RX descriptor by the driver is
* forbidden as long as it is owned by the device
* - we don't cache any register state beyond this point
*/
dma_bm_write(rbadr, src, cbBuf, dev->transfer_size);
/* RX disabled in the meantime? If so, abort RX. */
if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev)) {
pcnet_log(3, "%s: RX disabled 1\n", dev->name);
return 0;
}
/* Was the register modified in the meantime? If so, don't touch the
* register but still update the RX descriptor. */
if (iRxDesc == CSR_RCVRC(dev)) {
if (iRxDesc-- < 2)
iRxDesc = CSR_RCVRL(dev);
CSR_RCVRC(dev) = iRxDesc;
} else
iRxDesc = CSR_RCVRC(dev);
src += cbBuf;
size -= cbBuf;
while (size > 0) {
/* Read the entire next descriptor as we're likely to need it. */
next_crda = pcnetRdraAddr(dev, iRxDesc);
/* Check next descriptor's own bit. If we don't own it, we have
* to quit and write error status into the last descriptor we own.
*/
if (!pcnetRmdLoad(dev, &next_rmd, PHYSADDR(dev, next_crda), 1))
break;
/* Write back current descriptor, clear the own bit. */
pcnetRmdStorePassHost(dev, &rmd, PHYSADDR(dev, crda));
/* Switch to the next descriptor */
crda = next_crda;
rmd = next_rmd;
cbBuf = MIN(4096 - (size_t) rmd.rmd1.bcnt, size);
uint32_t rbadr2 = PHYSADDR(dev, rmd.rmd0.rbadr);
/* We have to leave the critical section here or we risk deadlocking
* with EMT when the write is to an unallocated page or has an access
* handler associated with it. See above for additional comments. */
dma_bm_write(rbadr2, src, cbBuf, dev->transfer_size);
/* RX disabled in the meantime? If so, abort RX. */
if (CSR_DRX(dev) || CSR_STOP(dev) || CSR_SPND(dev)) {
pcnet_log(3, "%s: RX disabled 2\n", dev->name);
return 0;
}
/* Was the register modified in the meantime? If so, don't touch the
* register but still update the RX descriptor. */
if (iRxDesc == CSR_RCVRC(dev)) {
if (iRxDesc-- < 2)
iRxDesc = CSR_RCVRL(dev);
CSR_RCVRC(dev) = iRxDesc;
} else {
iRxDesc = CSR_RCVRC(dev);
}
src += cbBuf;
size -= cbBuf;
}
if (size == 0) {
rmd.rmd1.enp = 1;
rmd.rmd1.pam = !CSR_PROM(dev) && is_padr;
rmd.rmd1.lafm = !CSR_PROM(dev) && is_ladr;
rmd.rmd1.bam = !CSR_PROM(dev) && is_bcast;
rmd.rmd2.mcnt = cbPacket;
rmd.rmd2.zeros = 0;
} else {
pcnet_log(1, "%s: Overflow by %ubytes\n", dev->name, size);
rmd.rmd1.oflo = 1;
rmd.rmd1.buff = 1;
rmd.rmd1.err = 1;
}
/* write back, clear the own bit */
pcnetRmdStorePassHost(dev, &rmd, PHYSADDR(dev, crda));
dev->aCSR[0] |= 0x0400;
pcnet_log(1, "%s: RINT set, RCVRC=%d CRDA=%#010x\n", dev->name,
CSR_RCVRC(dev), PHYSADDR(dev, CSR_CRDA(dev)));
/* guest driver is owner: force repoll of current and next RDTEs */
CSR_CRST(dev) = 0;
}
}
pcnetUpdateIrq(dev);
return 1;
}
/**
* Fails a TMD with a link down error.
*/
static void
pcnetXmitFailTMDLinkDown(nic_t *dev, TMD *pTmd)
{
/* make carrier error - hope this is correct. */
dev->cLinkDownReported++;
pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR */
}
/**
* Fails a TMD with a generic error.
*/
static void
pcnetXmitFailTMDGeneric(nic_t *dev, TMD *pTmd)
{
/* make carrier error - hope this is correct. */
pTmd->tmd2.lcar = pTmd->tmd1.err = 1;
dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR */
}
/**
* Actually try transmit frames.
*
* @threads TX or EMT.
*/
static void
pcnetAsyncTransmit(nic_t *dev)
{
/*
* Just cleared transmit demand if the transmitter is off.
*/
if (!CSR_TXON(dev)) {
dev->aCSR[0] &= ~0x0008; /* Clear TDMD */
return;
}
/*
* Iterate the transmit descriptors.
*/
unsigned cFlushIrq = 0;
int cMax = 32;
do {
TMD tmd;
if (!pcnetTdtePoll(dev, &tmd))
break;
/* Don't continue sending packets when the link is down. */
if (!pcnetIsLinkUp(dev)
&& dev->cLinkDownReported > PCNET_MAX_LINKDOWN_REPORTED)
break;
pcnet_log(3, "%s: TMDLOAD %#010x\n", dev->name, PHYSADDR(dev, CSR_CXDA(dev)));
int fLoopback = CSR_LOOP(dev);
/*
* The typical case - a complete packet.
*/
if (tmd.tmd1.stp && tmd.tmd1.enp) {
const int cb = 4096 - tmd.tmd1.bcnt;
pcnet_log(3, "%s: pcnetAsyncTransmit: stp&enp: cb=%d xmtrc=%#x\n", dev->name, cb, CSR_XMTRC(dev));
if (pcnetIsLinkUp(dev) || fLoopback) {
/* From the manual: ``A zero length buffer is acceptable as
* long as it is not the last buffer in a chain (STP = 0 and
* ENP = 1).'' That means that the first buffer might have a
* zero length if it is not the last one in the chain. */
if (cb <= MAX_FRAME) {
dev->xmit_pos = cb;
dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size);
if (fLoopback) {
if (HOST_IS_OWNER(CSR_CRST(dev)))
pcnetRdtePoll(dev);
pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos);
} else {
pcnet_log(3, "%s: pcnetAsyncTransmit: transmit loopbuf stp and enp, xmit pos = %d\n", dev->name, dev->xmit_pos);
network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos);
}
} else if (cb == 4096) {
/* The Windows NT4 pcnet driver sometimes marks the first
* unused descriptor as owned by us. Ignore that (by
* passing it back). Do not update the ring counter in this
* case (otherwise that driver becomes even more confused,
* which causes transmit to stall for about 10 seconds).
* This is just a workaround, not a final solution.
*/
/* r=frank: IMHO this is the correct implementation. The
* manual says: ``If the OWN bit is set and the buffer
* length is 0, the OWN bit will be cleared. In the C-LANCE
* the buffer length of 0 is interpreted as a 4096-byte
* buffer.''
*/
/* r=michaln: Perhaps not quite right. The C-LANCE (Am79C90)
* datasheet explains that the old LANCE (Am7990) ignored
* the top four bits next to BCNT and a count of 0 was
* interpreted as 4096. In the C-LANCE, that is still the
* case if the top bits are all ones. If all 16 bits are
* zero, the C-LANCE interprets it as zero-length transmit
* buffer. It's not entirely clear if the later models
* (PCnet-ISA, PCnet-PCI) behave like the C-LANCE or not.
* It is possible that the actual behavior of the C-LANCE
* and later hardware is that the buffer lengths are *16-bit*
* two's complement numbers between 0 and 4096. AMD's drivers
* in fact generally treat the length as a 16-bit quantity. */
pcnet_log(1, "%s: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", dev->name);
pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)));
break;
} else {
pcnetXmitFailTMDGeneric(dev, &tmd);
}
} else {
pcnetXmitFailTMDLinkDown(dev, &tmd);
}
/* Write back the TMD and pass it to the host (clear own bit). */
pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)));
/* advance the ring counter register */
if (CSR_XMTRC(dev) < 2) {
CSR_XMTRC(dev) = CSR_XMTRL(dev);
} else {
CSR_XMTRC(dev)
--;
}
} else if (tmd.tmd1.stp) {
/*
* Read TMDs until end-of-packet or tdte poll fails (underflow).
*
* We allocate a maximum sized buffer here since we do not wish to
* waste time finding out how much space we actually need even if
* we could reliably do that on SMP guests.
*/
unsigned cb = 4096 - tmd.tmd1.bcnt;
dev->xmit_pos = pcnetCalcPacketLen(dev, cb);
dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf, cb, dev->transfer_size);
for (;;) {
/*
* Advance the ring counter register and check the next tmd.
*/
const uint32_t GCPhysPrevTmd = PHYSADDR(dev, CSR_CXDA(dev));
if (CSR_XMTRC(dev) < 2)
CSR_XMTRC(dev) = CSR_XMTRL(dev);
else
CSR_XMTRC(dev)
--;
TMD dummy;
if (!pcnetTdtePoll(dev, &dummy)) {
/*
* Underflow!
*/
tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1;
dev->aCSR[0] |= 0x0200; /* set TINT */
/* Don't allow the guest to clear TINT before reading it */
dev->u16CSR0LastSeenByGuest &= ~0x0200;
if (!CSR_DXSUFLO(dev)) /* stop on xmit underflow */
dev->aCSR[0] &= ~0x0010; /* clear TXON */
pcnetTmdStorePassHost(dev, &tmd, GCPhysPrevTmd);
pcnet_log(3, "%s: pcnetAsyncTransmit: Underflow!!!\n", dev->name);
break;
}
/* release & save the previous tmd, pass it to the host */
pcnetTmdStorePassHost(dev, &tmd, GCPhysPrevTmd);
/*
* The next tmd.
*/
pcnetTmdLoad(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)), 0);
cb = 4096 - tmd.tmd1.bcnt;
if (dev->xmit_pos + cb <= MAX_FRAME) { /** @todo this used to be ... + cb < MAX_FRAME. */
int off = dev->xmit_pos;
dev->xmit_pos = cb + off;
dma_bm_read(PHYSADDR(dev, tmd.tmd0.tbadr), dev->abLoopBuf + off, cb, dev->transfer_size);
}
/*
* Done already?
*/
if (tmd.tmd1.enp) {
if (fLoopback) {
if (HOST_IS_OWNER(CSR_CRST(dev)))
pcnetRdtePoll(dev);
pcnet_log(3, "%s: pcnetAsyncTransmit: receive loopback enp\n", dev->name);
pcnetReceiveNoSync(dev, dev->abLoopBuf, dev->xmit_pos);
} else {
pcnet_log(3, "%s: pcnetAsyncTransmit: transmit loopbuf enp\n", dev->name);
network_tx(dev->netcard, dev->abLoopBuf, dev->xmit_pos);
}
/* Write back the TMD, pass it to the host */
pcnetTmdStorePassHost(dev, &tmd, PHYSADDR(dev, CSR_CXDA(dev)));
/* advance the ring counter register */
if (CSR_XMTRC(dev) < 2)
CSR_XMTRC(dev) = CSR_XMTRL(dev);
else
CSR_XMTRC(dev)
--;
break;
}
} /* the loop */
}
/* Update TDMD, TXSTRT and TINT. */
dev->aCSR[0] &= ~0x0008; /* clear TDMD */
dev->aCSR[4] |= 0x0008; /* set TXSTRT */
dev->xmit_pos = -1;
if (!CSR_TOKINTD(dev) /* Transmit OK Interrupt Disable, no infl. on errors. */
|| (CSR_LTINTEN(dev) && tmd.tmd1.ltint)
|| tmd.tmd1.err) {
cFlushIrq++;
}
if (--cMax == 0)
break;
} while (CSR_TXON(dev)); /* transfer on */
if (cFlushIrq) {
dev->aCSR[0] |= 0x0200; /* set TINT */
/* Don't allow the guest to clear TINT before reading it */
dev->u16CSR0LastSeenByGuest &= ~0x0200;
pcnetUpdateIrq(dev);
}
}
/**
* Poll for changes in RX and TX descriptor rings.
*/
static void
pcnetPollRxTx(nic_t *dev)
{
if (CSR_RXON(dev)) {
/*
* The second case is important for pcnetWaitReceiveAvail(): If CSR_CRST(dev) was
* true but pcnetCanReceive() returned false for some other reason we need to check
* _now_ if we have to wakeup pcnetWaitReceiveAvail().
*/
if (HOST_IS_OWNER(CSR_CRST(dev)) || dev->fMaybeOutOfSpace)
pcnetRdtePoll(dev);
}
if (CSR_TDMD(dev) || (CSR_TXON(dev) && !CSR_DPOLL(dev)))
pcnetAsyncTransmit(dev);
}
static void
pcnetPollTimer(void *priv)
{
nic_t *dev = (nic_t *) priv;
timer_advance_u64(&dev->timer, 2000 * TIMER_USEC);
if (CSR_TDMD(dev))
pcnetAsyncTransmit(dev);
pcnetUpdateIrq(dev);
if (!CSR_STOP(dev) && !CSR_SPND(dev) && (!CSR_DPOLL(dev) || dev->fMaybeOutOfSpace))
pcnetPollRxTx(dev);
}
static void
pcnetHardReset(nic_t *dev)
{
pcnet_log(2, "%s: pcnetHardReset\n", dev->name);
dev->iISR = 0;
pcnet_do_irq(dev, 0);
/* Many of the BCR values would normally be read from the EEPROM. */
dev->aBCR[BCR_MSRDA] = 0x0005;
dev->aBCR[BCR_MSWRA] = 0x0005;
dev->aBCR[BCR_MC] = 0x0002;
dev->aBCR[BCR_LNKST] = 0x00c0;
dev->aBCR[BCR_LED1] = 0x0084;
dev->aBCR[BCR_LED2] = 0x0088;
dev->aBCR[BCR_LED3] = 0x0090;
dev->aBCR[BCR_FDC] = 0x0000;
dev->aBCR[BCR_BSBC] = 0x9001;
dev->aBCR[BCR_EECAS] = 0x0002;
dev->aBCR[BCR_STVAL] = 0xffff;
dev->aCSR[58] = dev->aBCR[BCR_SWS] = 0x0200; /* CSR58 is an alias for BCR20 */
dev->iLog2DescSize = 3;
dev->aBCR[BCR_PLAT] = 0xff06;
dev->aBCR[BCR_MIICAS] = 0x20; /* Auto-negotiation on. */
dev->aBCR[BCR_MIIADDR] = 0; /* Internal PHY on Am79C973 would be (0x1e << 5) */
dev->aBCR[BCR_PCIVID] = 0x1022;
dev->aBCR[BCR_PCISID] = 0x0020;
dev->aBCR[BCR_PCISVID] = 0x1022;
/* Reset the error counter. */
dev->uCntBadRMD = 0;
pcnetSoftReset(dev);
}
static void
pcnet_csr_writew(nic_t *dev, uint16_t rap, uint16_t val)
{
pcnet_log(1, "%s: pcnet_csr_writew: rap=%d val=%#06x\n", dev->name, rap, val);
switch (rap) {
case 0:
{
uint16_t csr0 = dev->aCSR[0];
/* Clear any interrupt flags.
* Don't clear an interrupt flag which was not seen by the guest yet. */
csr0 &= ~(val & 0x7f00 & dev->u16CSR0LastSeenByGuest);
csr0 = (csr0 & ~0x0040) | (val & 0x0048);
val = (val & 0x007f) | (csr0 & 0x7f00);
/* If STOP, STRT and INIT are set, clear STRT and INIT */
if ((val & 7) == 7)
val &= ~3;
pcnet_log(2, "%s: CSR0 val = %04x, val2 = %04x\n", dev->name, val, dev->aCSR[0]);
dev->aCSR[0] = csr0;
if (!CSR_STOP(dev) && (val & 4)) {
pcnet_log(3, "%s: pcnet_csr_writew(): Stop\n", dev->name);
pcnetStop(dev);
}
if (!CSR_INIT(dev) && (val & 1)) {
pcnet_log(3, "%s: pcnet_csr_writew(): Init\n", dev->name);
pcnetInit(dev);
}
if (!CSR_STRT(dev) && (val & 2)) {
pcnet_log(3, "%s: pcnet_csr_writew(): Start\n", dev->name);
pcnetStart(dev);
}
if (CSR_TDMD(dev)) {
pcnet_log(3, "%s: pcnet_csr_writew(): Transmit\n", dev->name);
pcnetAsyncTransmit(dev);
}
}
return;
case 2: /* IADRH */
if (dev->is_isa)
val &= 0x00ff; /* Upper 8 bits ignored on ISA chips. */
case 1: /* IADRL */
case 8: /* LADRF 0..15 */
case 9: /* LADRF 16..31 */
case 10: /* LADRF 32..47 */
case 11: /* LADRF 48..63 */
case 12: /* PADR 0..15 */
case 13: /* PADR 16..31 */
case 14: /* PADR 32..47 */
case 18: /* CRBAL */
case 19: /* CRBAU */
case 20: /* CXBAL */
case 21: /* CXBAU */
case 22: /* NRBAL */
case 23: /* NRBAU */
case 26: /* NRDAL */
case 27: /* NRDAU */
case 28: /* CRDAL */
case 29: /* CRDAU */
case 32: /* NXDAL */
case 33: /* NXDAU */
case 34: /* CXDAL */
case 35: /* CXDAU */
case 36: /* NNRDL */
case 37: /* NNRDU */
case 38: /* NNXDL */
case 39: /* NNXDU */
case 40: /* CRBCL */
case 41: /* CRBCU */
case 42: /* CXBCL */
case 43: /* CXBCU */
case 44: /* NRBCL */
case 45: /* NRBCU */
case 46: /* POLL */
case 47: /* POLLINT */
case 72: /* RCVRC */
case 74: /* XMTRC */
case 112: /* MISSC */
if (CSR_STOP(dev) || CSR_SPND(dev))
break;
return;
case 3: /* Interrupt Mask and Deferral Control */
break;
case 4: /* Test and Features Control */
dev->aCSR[4] &= ~(val & 0x026a);
val &= ~0x026a;
val |= dev->aCSR[4] & 0x026a;
break;
case 5: /* Extended Control and Interrupt 1 */
dev->aCSR[5] &= ~(val & 0x0a90);
val &= ~0x0a90;
val |= dev->aCSR[5] & 0x0a90;
break;
case 7: /* Extended Control and Interrupt 2 */
{
uint16_t csr7 = dev->aCSR[7];
csr7 &= ~0x0400;
csr7 &= ~(val & 0x0800);
csr7 |= (val & 0x0400);
dev->aCSR[7] = csr7;
}
return;
case 15: /* Mode */
break;
case 16: /* IADRL */
pcnet_csr_writew(dev, 1, val);
return;
case 17: /* IADRH */
pcnet_csr_writew(dev, 2, val);
return;
/*
* 24 and 25 are the Base Address of Receive Descriptor.
* We combine and mirror these in GCRDRA.
*/
case 24: /* BADRL */
case 25: /* BADRU */
if (!CSR_STOP(dev) && !CSR_SPND(dev)) {
pcnet_log(3, "%s: WRITE CSR%d, %#06x, ignoring!!\n", dev->name, rap, val);
return;
}
if (rap == 24)
dev->GCRDRA = (dev->GCRDRA & 0xffff0000) | (val & 0x0000ffff);
else
dev->GCRDRA = (dev->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
pcnet_log(3, "%s: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCRDRA);
if (dev->GCRDRA & (dev->iLog2DescSize - 1))
pcnet_log(1, "%s: Warning: Misaligned RDRA (GCRDRA=%#010x)\n", dev->name, dev->GCRDRA);
break;
/*
* 30 & 31 are the Base Address of Transmit Descriptor.
* We combine and mirrorthese in GCTDRA.
*/
case 30: /* BADXL */
case 31: /* BADXU */
if (!CSR_STOP(dev) && !CSR_SPND(dev)) {
pcnet_log(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val);
return;
}
if (rap == 30)
dev->GCTDRA = (dev->GCTDRA & 0xffff0000) | (val & 0x0000ffff);
else
dev->GCTDRA = (dev->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16);
pcnet_log(3, "%s: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", dev->name, rap, val, dev->GCTDRA);
if (dev->GCTDRA & (dev->iLog2DescSize - 1))
pcnet_log(1, "%s: Warning: Misaligned TDRA (GCTDRA=%#010x)\n", dev->name, dev->GCTDRA);
break;
case 58: /* Software Style */
pcnet_bcr_writew(dev, BCR_SWS, val);
break;
/*
* Registers 76 and 78 aren't stored correctly (see todos), but I'm don't dare
* try fix that right now. So, as a quick hack for 'alt init' I'll just correct them here.
*/
case 76: /* RCVRL */ /** @todo call pcnetUpdateRingHandlers */
/** @todo receive ring length is stored in two's complement! */
case 78: /* XMTRL */ /** @todo call pcnetUpdateRingHandlers */
/** @todo transmit ring length is stored in two's complement! */
if (!CSR_STOP(dev) && !CSR_SPND(dev)) {
pcnet_log(3, "%s: WRITE CSR%d, %#06x !!\n", dev->name, rap, val);
return;
}
pcnet_log(3, "%s: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", dev->name,
rap, val, 1 + ~val);
val = 1 + ~val;
/*
* HACK ALERT! Set the counter registers too.
*/
dev->aCSR[rap - 4] = val;
break;
default:
return;
}
dev->aCSR[rap] = val;
}
/**
* Encode a 32-bit link speed into a custom 16-bit floating-point value
*/
static uint16_t
pcnetLinkSpd(uint32_t speed)
{
unsigned exp = 0;
while (speed & 0xFFFFE000) {
speed /= 10;
++exp;
}
return (exp << 13) | speed;
}
static uint16_t
pcnet_csr_readw(nic_t *dev, uint16_t rap)
{
uint16_t val;
switch (rap) {
case 0:
pcnetUpdateIrq(dev);
val = dev->aCSR[0];
val |= (val & 0x7800) ? 0x8000 : 0;
dev->u16CSR0LastSeenByGuest = val;
break;
case 16:
return pcnet_csr_readw(dev, 1);
case 17:
return pcnet_csr_readw(dev, 2);
case 58:
return pcnet_bcr_readw(dev, BCR_SWS);
case 68: /* Custom register to pass link speed to driver */
return pcnetLinkSpd(dev->u32LinkSpeed);
default:
val = dev->aCSR[rap];
break;
}
pcnet_log(3, "%s: pcnet_csr_readw rap=%d val=0x%04x\n", dev->name, rap, val);
return val;
}
static void
pcnet_bcr_writew(nic_t *dev, uint16_t rap, uint16_t val)
{
rap &= 0x7f;
pcnet_log(3, "%s: pcnet_bcr_writew rap=%d val=0x%04x\n", dev->name, rap, val);
switch (rap) {
case BCR_SWS:
if (!(CSR_STOP(dev) || CSR_SPND(dev)))
return;
val &= ~0x0300;
switch (val & 0x00ff) {
default:
case 0:
val |= 0x0200; /* 16 bit */
dev->iLog2DescSize = 3;
dev->GCUpperPhys = (0xff00 & dev->aCSR[2]) << 16;
break;
case 1:
val |= 0x0100; /* 32 bit */
dev->iLog2DescSize = 4;
dev->GCUpperPhys = 0;
break;
case 2:
case 3:
val |= 0x0300; /* 32 bit */
dev->iLog2DescSize = 4;
dev->GCUpperPhys = 0;
break;
}
dev->aCSR[58] = val;
fallthrough;
case BCR_LNKST:
case BCR_LED1:
case BCR_LED2:
case BCR_LED3:
case BCR_MC:
case BCR_FDC:
case BCR_BSBC:
case BCR_EECAS:
case BCR_PLAT:
case BCR_MIIADDR:
dev->aBCR[rap] = val;
break;
case BCR_MIICAS:
dev->netcard->byte_period = (dev->board == DEV_AM79C973 && (val & 0x28)) ? NET_PERIOD_100M : NET_PERIOD_10M;
dev->aBCR[rap] = val;
break;
case BCR_STVAL:
val &= 0xffff;
dev->aBCR[BCR_STVAL] = val;
if (dev->board == DEV_AM79C973)
timer_set_delay_u64(&dev->timer_soft_int, (12.8 * val) * TIMER_USEC);
break;
case BCR_MIIMDR:
dev->aMII[dev->aBCR[BCR_MIIADDR] & 0x1f] = val;
break;
default:
break;
}
}
static uint16_t
pcnet_mii_readw(nic_t *dev, uint16_t miiaddr)
{
uint16_t val;
int autoneg;
int duplex;
int fast;
int isolate;
/* If the DANAS (BCR32.7) bit is set, the MAC does not do any
* auto-negotiation and the PHY must be set up explicitly. DANAS
* effectively disables most other BCR32 bits.
*/
if (dev->aBCR[BCR_MIICAS] & 0x80) {
/* PHY controls auto-negotiation. */
autoneg = duplex = fast = 1;
} else {
/* BCR32 controls auto-negotiation. */
autoneg = (dev->aBCR[BCR_MIICAS] & 0x20) != 0;
duplex = (dev->aBCR[BCR_MIICAS] & 0x10) != 0;
fast = (dev->aBCR[BCR_MIICAS] & 0x08) != 0;
}
/* Electrically isolating the PHY mostly disables it. */
isolate = (dev->aMII[0] & 0x400) != 0;
switch (miiaddr) {
case 0:
/* MII basic mode control register. */
val = 0;
if (autoneg)
val |= 0x1000; /* Enable auto negotiation. */
if (fast)
val |= 0x2000; /* 100 Mbps */
if (duplex) /* Full duplex forced */
val |= 0x0100; /* Full duplex */
if (isolate) /* PHY electrically isolated. */
val |= 0x0400; /* Isolated */
break;
case 1:
/* MII basic mode status register. */
val = 0x7800 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
| 0x0040 /* Mgmt frame preamble not required. */
| 0x0020 /* Auto-negotiation complete. */
| 0x0008 /* Able to do auto-negotiation. */
| 0x0004 /* Link up. */
| 0x0001; /* Extended Capability, i.e. registers 4+ valid. */
if (!pcnetIsLinkUp(dev) || isolate) {
val &= ~(0x0020 | 0x0004);
dev->cLinkDownReported++;
}
if (!autoneg) {
/* Auto-negotiation disabled. */
val &= ~(0x0020 | 0x0008);
if (duplex)
val &= ~0x2800; /* Full duplex forced. */
else
val &= ~0x5000; /* Half duplex forced. */
if (fast)
val &= ~0x1800; /* 100 Mbps forced */
else
val &= ~0x6000; /* 10 Mbps forced */
}
break;
case 2:
/* PHY identifier 1. */
val = 0x22; /* Am79C874/AC101 PHY */
break;
case 3:
/* PHY identifier 2. */
val = 0x561b; /* Am79C874/AC101 PHY */
break;
case 4:
/* Advertisement control register. */
val = 0x01e0 /* Try 100mbps FD/HD and 10mbps FD/HD. */
| 0x0001; /* CSMA selector. */
break;
case 5:
/* Link partner ability register. */
if (pcnetIsLinkUp(dev) && !isolate) {
val = 0x8000 /* Next page bit. */
| 0x4000 /* Link partner acked us. */
| 0x0400 /* Can do flow control. */
| 0x01e0 /* Can do 100mbps FD/HD and 10mbps FD/HD. */
| 0x0001; /* Use CSMA selector. */
} else {
val = 0;
dev->cLinkDownReported++;
}
break;
case 6:
/* Auto negotiation expansion register. */
if (pcnetIsLinkUp(dev) && !isolate) {
val = 0x0008 /* Link partner supports npage. */
| 0x0004 /* Enable npage words. */
| 0x0001; /* Can do N-way auto-negotiation. */
} else {
val = 0;
dev->cLinkDownReported++;
}
break;
case 18:
/* Diagnostic Register (FreeBSD pcn/ac101 driver reads this). */
if (pcnetIsLinkUp(dev) && !isolate) {
val = 0x1000 /* Receive PLL locked. */
| 0x0200; /* Signal detected. */
if (autoneg) {
val |= 0x0400 /* 100Mbps rate. */
| 0x0800; /* Full duplex. */
} else {
if (fast)
val |= 0x0400; /* 100Mbps rate. */
if (duplex)
val |= 0x0800; /* Full duplex. */
}
} else {
val = 0;
dev->cLinkDownReported++;
}
break;
default:
val = 0;
break;
}
return val;
}
static uint16_t
pcnet_bcr_readw(nic_t *dev, uint16_t rap)
{
uint16_t val;
rap &= 0x7f;
switch (rap) {
case BCR_LNKST:
case BCR_LED1:
case BCR_LED2:
case BCR_LED3:
val = dev->aBCR[rap] & ~0x8000;
if (!(pcnetIsLinkUp(dev))) {
if (rap == 4)
dev->cLinkDownReported++;
val &= ~0x40;
}
val |= (val & 0x017f & dev->u32Lnkst) ? 0x8000 : 0;
break;
case BCR_MIIMDR:
if ((dev->board == DEV_AM79C973) && (((dev->aBCR[BCR_MIIADDR] >> 5) & 0x1f) == 0)) {
uint16_t miiaddr = dev->aBCR[BCR_MIIADDR] & 0x1f;
val = pcnet_mii_readw(dev, miiaddr);
} else
val = 0xffff;
break;
case BCR_SWCONFIG:
if (dev->board == DEV_AM79C961)
val = ((dev->base_irq & 0x0f) << 4) | (dev->dma_channel & 0x07);
else
val = 0xffff;
break;
default:
val = rap < BCR_MAX_RAP ? dev->aBCR[rap] : 0;
break;
}
pcnet_log(3, "pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
return val;
}
static void
pcnet_word_write(nic_t *dev, uint32_t addr, uint16_t val)
{
pcnet_log(3, "%s: pcnet_word_write: addr = %04x, val = %04x, DWIO not set = %04x\n", dev->name, addr & 0x0f, val, !BCR_DWIO(dev));
if (!BCR_DWIO(dev)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC);
pcnet_csr_writew(dev, dev->u32RAP, val);
pcnetUpdateIrq(dev);
break;
case 0x02:
dev->u32RAP = val & 0x7f;
break;
case 0x06:
pcnet_bcr_writew(dev, dev->u32RAP, val);
break;
default:
break;
}
}
}
static uint8_t
pcnet_byte_read(nic_t *dev, uint32_t addr)
{
uint8_t val = 0xff;
if (!BCR_DWIO(dev)) {
switch (addr & 0x0f) {
case 0x04:
pcnetSoftReset(dev);
val = 0;
break;
default:
break;
}
}
pcnetUpdateIrq(dev);
pcnet_log(3, "%s: pcnet_word_read: addr = %04x, val = %04x, DWIO not set = %04x\n", dev->name, addr & 0x0f, val, !BCR_DWIO(dev));
return val;
}
static uint16_t
pcnet_word_read(nic_t *dev, uint32_t addr)
{
uint16_t val = 0xffff;
if (!BCR_DWIO(dev)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
/** @note if we're not polling, then the guest will tell us when to poll by setting TDMD in CSR0 */
/** Polling is then useless here and possibly expensive. */
if (!CSR_DPOLL(dev))
timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC);
val = pcnet_csr_readw(dev, dev->u32RAP);
if (dev->u32RAP == 0)
goto skip_update_irq;
break;
case 0x02:
val = dev->u32RAP;
goto skip_update_irq;
case 0x04:
pcnetSoftReset(dev);
val = 0;
break;
case 0x06:
val = pcnet_bcr_readw(dev, dev->u32RAP);
break;
default:
break;
}
}
pcnetUpdateIrq(dev);
skip_update_irq:
pcnet_log(3, "%s: pcnet_word_read: addr = %04x, val = %04x, DWIO not set = %04x\n", dev->name, addr & 0x0f, val, !BCR_DWIO(dev));
return val;
}
static void
pcnet_dword_write(nic_t *dev, uint32_t addr, uint32_t val)
{
if (BCR_DWIO(dev)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC);
pcnet_csr_writew(dev, dev->u32RAP, val & 0xffff);
pcnetUpdateIrq(dev);
break;
case 0x04:
dev->u32RAP = val & 0x7f;
break;
case 0x0c:
pcnet_bcr_writew(dev, dev->u32RAP, val & 0xffff);
break;
default:
break;
}
} else if ((addr & 0x0f) == 0) {
/* switch device to dword i/o mode */
pcnet_bcr_writew(dev, BCR_BSBC, pcnet_bcr_readw(dev, BCR_BSBC) | 0x0080);
pcnet_log(3, "%s: device switched into dword i/o mode\n", dev->name);
}
}
static uint32_t
pcnet_dword_read(nic_t *dev, uint32_t addr)
{
uint32_t val = 0xffffffff;
if (BCR_DWIO(dev)) {
switch (addr & 0x0f) {
case 0x00: /* RDP */
if (!CSR_DPOLL(dev))
timer_set_delay_u64(&dev->timer, 2000 * TIMER_USEC);
val = pcnet_csr_readw(dev, dev->u32RAP);
if (dev->u32RAP == 0)
goto skip_update_irq;
break;
case 0x04:
val = dev->u32RAP;
goto skip_update_irq;
case 0x08:
pcnetSoftReset(dev);
val = 0;
break;
case 0x0c:
val = pcnet_bcr_readw(dev, dev->u32RAP);
break;
default:
break;
}
}
pcnetUpdateIrq(dev);
skip_update_irq:
pcnet_log(3, "%s: Read Long mode, addr = %08x, val = %08x\n", dev->name, addr, val);
return val;
}
static void
pcnet_aprom_writeb(nic_t *dev, uint32_t addr, uint32_t val)
{
/* Check APROMWE bit to enable write access */
if (pcnet_bcr_readw(dev, 2) & 0x80)
dev->aPROM[addr & 0x0f] = val & 0xff;
}
static uint32_t
pcnet_aprom_readb(nic_t *dev, uint32_t addr)
{
uint32_t val = dev->aPROM[addr & 15];
return val;
}
static void
pcnet_write(nic_t *dev, uint32_t addr, uint32_t val, int len)
{
uint16_t off = addr & 0x1f;
pcnet_log(3, "%s: write addr %x, val %x, off %x, len %d\n", dev->name, addr, val, off, len);
if (off < 0x10) {
if (!BCR_DWIO(dev) && len == 1)
pcnet_aprom_writeb(dev, addr, val);
else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2) {
pcnet_aprom_writeb(dev, addr, val);
pcnet_aprom_writeb(dev, addr + 1, val >> 8);
} else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) {
pcnet_aprom_writeb(dev, addr, val);
pcnet_aprom_writeb(dev, addr + 1, val >> 8);
pcnet_aprom_writeb(dev, addr + 2, val >> 16);
pcnet_aprom_writeb(dev, addr + 3, val >> 24);
}
} else {
if (len == 2)
pcnet_word_write(dev, addr, val);
else if (len == 4)
pcnet_dword_write(dev, addr, val);
}
}
static void
pcnet_writeb(uint16_t addr, uint8_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 1);
}
static void
pcnet_writew(uint16_t addr, uint16_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 2);
}
static void
pcnet_writel(uint16_t addr, uint32_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 4);
}
static uint32_t
pcnet_read(nic_t *dev, uint32_t addr, int len)
{
uint32_t retval = 0xffffffff;
uint16_t off = addr & 0x1f;
pcnet_log(3, "%s: read addr %x, off %x, len %d\n", dev->name, addr, off, len);
if (off < 0x10) {
if (!BCR_DWIO(dev) && len == 1)
retval = pcnet_aprom_readb(dev, addr);
else if (!BCR_DWIO(dev) && ((addr & 1) == 0) && len == 2)
retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8);
else if (BCR_DWIO(dev) && ((addr & 3) == 0) && len == 4) {
retval = pcnet_aprom_readb(dev, addr) | (pcnet_aprom_readb(dev, addr + 1) << 8) | (pcnet_aprom_readb(dev, addr + 2) << 16) | (pcnet_aprom_readb(dev, addr + 3) << 24);
}
} else {
if (len == 1)
retval = pcnet_byte_read(dev, addr);
else if (len == 2)
retval = pcnet_word_read(dev, addr);
else if (len == 4)
retval = pcnet_dword_read(dev, addr);
}
pcnet_log(3, "%s: value in read - %08x\n", dev->name, retval);
return retval;
}
static uint8_t
pcnet_readb(uint16_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 1));
}
static uint16_t
pcnet_readw(uint16_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 2));
}
static uint32_t
pcnet_readl(uint16_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 4));
}
static void
pcnet_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 1);
}
static void
pcnet_mmio_writew(uint32_t addr, uint16_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 2);
}
static void
pcnet_mmio_writel(uint32_t addr, uint32_t val, void *priv)
{
pcnet_write((nic_t *) priv, addr, val, 4);
}
static uint8_t
pcnet_mmio_readb(uint32_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 1));
}
static uint16_t
pcnet_mmio_readw(uint32_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 2));
}
static uint32_t
pcnet_mmio_readl(uint32_t addr, void *priv)
{
return (pcnet_read((nic_t *) priv, addr, 4));
}
static void
pcnet_mem_init(nic_t *dev, uint32_t addr)
{
mem_mapping_add(&dev->mmio_mapping, addr, 32,
pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl,
pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel,
NULL, MEM_MAPPING_EXTERNAL, dev);
}
static void
pcnet_mem_set_addr(nic_t *dev, uint32_t base)
{
mem_mapping_set_addr(&dev->mmio_mapping, base, 32);
}
static void
pcnet_mem_disable(nic_t *dev)
{
mem_mapping_disable(&dev->mmio_mapping);
}
static void
pcnet_ioremove(nic_t *dev, uint16_t addr, int len)
{
if (dev->is_pci || dev->is_vlb) {
io_removehandler(addr, len,
pcnet_readb, pcnet_readw, pcnet_readl,
pcnet_writeb, pcnet_writew, pcnet_writel, dev);
} else {
io_removehandler(addr, len,
pcnet_readb, pcnet_readw, NULL,
pcnet_writeb, pcnet_writew, NULL, dev);
}
}
static void
pcnet_ioset(nic_t *dev, uint16_t addr, int len)
{
pcnet_ioremove(dev, addr, len);
if (dev->is_pci || dev->is_vlb) {
io_sethandler(addr, len,
pcnet_readb, pcnet_readw, pcnet_readl,
pcnet_writeb, pcnet_writew, pcnet_writel, dev);
} else {
io_sethandler(addr, len,
pcnet_readb, pcnet_readw, NULL,
pcnet_writeb, pcnet_writew, NULL, dev);
}
}
static void
pcnet_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;
pcnet_log(4, "%s: Write value %02X to register %02X\n", dev->name, val, addr & 0xff);
switch (addr) {
case 0x04:
valxor = (val & 0x57) ^ pcnet_pci_regs[addr];
if (valxor & PCI_COMMAND_IO) {
pcnet_ioremove(dev, dev->PCIBase, 32);
if ((dev->PCIBase != 0) && (val & PCI_COMMAND_IO))
pcnet_ioset(dev, dev->PCIBase, 32);
}
if (valxor & PCI_COMMAND_MEM) {
pcnet_mem_disable(dev);
if ((dev->MMIOBase != 0) && (val & PCI_COMMAND_MEM))
pcnet_mem_set_addr(dev, dev->MMIOBase);
}
pcnet_pci_regs[addr] = val & 0x57;
break;
case 0x05:
pcnet_pci_regs[addr] = val & 0x01;
break;
case 0x0D:
pcnet_pci_regs[addr] = val;
break;
case 0x10:
case 0x11:
case 0x12:
case 0x13:
/* I/O Base set. */
/* First, remove the old I/O. */
pcnet_ioremove(dev, dev->PCIBase, 32);
/* Then let's set the PCI regs. */
pcnet_pci_bar[0].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
pcnet_pci_bar[0].addr &= 0xff00;
dev->PCIBase = pcnet_pci_bar[0].addr;
/* Log the new base. */
pcnet_log(4, "%s: New I/O base is %04X\n", dev->name, dev->PCIBase);
/* We're done, so get out of the here. */
if (pcnet_pci_regs[4] & PCI_COMMAND_IO) {
if (dev->PCIBase != 0)
pcnet_ioset(dev, dev->PCIBase, 32);
}
return;
case 0x15:
case 0x16:
case 0x17:
/* MMIO Base set. */
/* First, remove the old I/O. */
pcnet_mem_disable(dev);
/* Then let's set the PCI regs. */
pcnet_pci_bar[1].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
pcnet_pci_bar[1].addr &= 0xffffc000;
dev->MMIOBase = pcnet_pci_bar[1].addr & 0xffffc000;
/* Log the new base. */
pcnet_log(4, "%s: New MMIO base is %08X\n", dev->name, dev->MMIOBase);
/* We're done, so get out of the here. */
if (pcnet_pci_regs[4] & PCI_COMMAND_MEM) {
if (dev->MMIOBase != 0)
pcnet_mem_set_addr(dev, dev->MMIOBase);
}
return;
case 0x3C:
dev->base_irq = val;
pcnet_pci_regs[addr] = val;
return;
default:
break;
}
}
static uint8_t
pcnet_pci_read(UNUSED(int func), int addr, void *priv)
{
const nic_t *dev = (nic_t *) priv;
pcnet_log(4, "%s: Read to register %02X\n", dev->name, addr & 0xff);
switch (addr) {
case 0x00:
return 0x22;
case 0x01:
return 0x10;
case 0x02:
return 0x00;
case 0x03:
return 0x20;
case 0x04:
return pcnet_pci_regs[0x04] & 0x57; /*Respond to IO and memory accesses*/
case 0x05:
return pcnet_pci_regs[0x05] & 0x01;
case 0x06:
return 0x80;
case 0x07:
return 2;
case 0x08:
return (dev->board == DEV_AM79C973) ? 0x40 : 0x10; /*Revision ID*/
case 0x09:
return 0; /*Programming interface*/
case 0x0A:
return 0; /*devubclass*/
case 0x0B:
return 2; /*Class code*/
case 0x0D:
return pcnet_pci_regs[addr];
case 0x0E:
return 0; /*Header type */
case 0x10:
return 1; /*I/O space*/
case 0x11:
return pcnet_pci_bar[0].addr_regs[1];
case 0x12:
return pcnet_pci_bar[0].addr_regs[2];
case 0x13:
return pcnet_pci_bar[0].addr_regs[3];
case 0x14:
return 0; /*Memory space*/
case 0x15:
return pcnet_pci_bar[1].addr_regs[1];
case 0x16:
return pcnet_pci_bar[1].addr_regs[2];
case 0x17:
return pcnet_pci_bar[1].addr_regs[3];
case 0x2C:
return 0x22;
case 0x2D:
return 0x10;
case 0x2E:
return 0x00;
case 0x2F:
return 0x20;
case 0x3C:
return dev->base_irq;
case 0x3D:
return PCI_INTA;
case 0x3E:
return 0x06;
case 0x3F:
return 0xff;
default:
break;
}
return 0;
}
static void
pcnet_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
if (ld)
return;
nic_t *dev = (nic_t *) priv;
dev->base_address = 0;
dev->base_irq = 0;
dev->dma_channel = -1;
if (dev->base_address) {
pcnet_ioremove(dev, dev->base_address, 0x20);
dev->base_address = 0;
}
if (config->activate) {
dev->base_address = config->io[0].base;
if (dev->base_address != ISAPNP_IO_DISABLED)
pcnet_ioset(dev, dev->base_address, 0x20);
dev->base_irq = config->irq[0].irq;
dev->dma_channel = config->dma[0].dma;
if (dev->dma_channel == ISAPNP_DMA_DISABLED)
dev->dma_channel = -1;
/* Update PnP register mirrors in ROM. */
dev->aPROM[32] = dev->base_address >> 8;
dev->aPROM[33] = dev->base_address;
dev->aPROM[34] = dev->base_irq;
dev->aPROM[35] = (config->irq[0].level << 1) | config->irq[0].type;
dev->aPROM[36] = (dev->dma_channel == -1) ? ISAPNP_DMA_DISABLED : dev->dma_channel;
}
}
static uint8_t
pcnet_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv)
{
const nic_t *dev = (nic_t *) priv;
if (!ld && (reg == 0xf0))
return dev->aPROM[50];
else
return 0x00;
}
static void
pcnet_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv)
{
if (ld)
return;
nic_t *dev = (nic_t *) priv;
if (reg == 0xf0)
dev->aPROM[50] = val & 0x1f;
}
/**
* Takes down the link temporarily if it's current status is up.
*
* This is used during restore and when replumbing the network link.
*
* The temporary link outage is supposed to indicate to the OS that all network
* connections have been lost and that it for instance is appropriate to
* renegotiate any DHCP lease.
*
* @param pThis The PCnet shared instance data.
*/
static void
pcnetTempLinkDown(nic_t *dev)
{
if (dev->fLinkUp) {
dev->fLinkTempDown = 1;
dev->cLinkDownReported = 0;
dev->aCSR[0] |= 0x8000 | 0x2000; /* ERR | CERR (this is probably wrong) */
timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
}
}
/**
* Check if the device/driver can receive data now.
*
* Worker for pcnetNetworkDown_WaitReceiveAvail(). This must be called before
* the pfnRecieve() method is called.
*
* @returns VBox status code.
* @param pThis The PCnet instance data.
*/
static int
pcnetCanReceive(nic_t *dev)
{
int rc = 0;
if (!CSR_DRX(dev) && !CSR_STOP(dev) && !CSR_SPND(dev)) {
if (HOST_IS_OWNER(CSR_CRST(dev)) && dev->GCRDRA)
pcnetRdtePoll(dev);
if (HOST_IS_OWNER(CSR_CRST(dev))) {
/** @todo Notify the guest _now_. Will potentially increase the interrupt load */
if (dev->fSignalRxMiss)
dev->aCSR[0] |= 0x1000; /* Set MISS flag */
} else
rc = 1;
}
return rc;
}
static int
pcnetSetLinkState(void *priv, uint32_t link_state)
{
nic_t *dev = (nic_t *) priv;
if (link_state & NET_LINK_TEMP_DOWN) {
pcnetTempLinkDown(dev);
return 1;
}
bool link_up = !(link_state & NET_LINK_DOWN);
if (dev->fLinkUp != link_up) {
dev->fLinkUp = link_up;
if (link_up) {
dev->fLinkTempDown = 1;
dev->cLinkDownReported = 0;
dev->aCSR[0] |= 0x8000 | 0x2000;
timer_set_delay_u64(&dev->timer_restore, (dev->cMsLinkUpDelay * 1000) * TIMER_USEC);
} else {
dev->cLinkDownReported = 0;
dev->aCSR[0] |= 0x8000 | 0x2000;
}
}
return 0;
}
static void
pcnetTimerSoftInt(void *priv)
{
nic_t *dev = (nic_t *) priv;
dev->aCSR[7] |= 0x0800; /* STINT */
pcnetUpdateIrq(dev);
timer_advance_u64(&dev->timer_soft_int, (12.8 * (dev->aBCR[BCR_STVAL] & 0xffff)) * TIMER_USEC);
}
static void
pcnetTimerRestore(void *priv)
{
nic_t *dev = (nic_t *) priv;
if (dev->cLinkDownReported <= PCNET_MAX_LINKDOWN_REPORTED) {
timer_advance_u64(&dev->timer_restore, 1500000 * TIMER_USEC);
} else {
dev->fLinkTempDown = 0;
if (dev->fLinkUp) {
dev->aCSR[0] &= ~(0x8000 | 0x2000); /* ERR | CERR - probably not 100% correct either... */
}
}
}
static void *
pcnet_init(const device_t *info)
{
uint32_t mac;
nic_t *dev;
int c;
uint16_t checksum;
dev = malloc(sizeof(nic_t));
memset(dev, 0x00, sizeof(nic_t));
dev->name = info->name;
dev->board = info->local & 0xff;
dev->is_pci = !!(info->flags & DEVICE_PCI);
dev->is_vlb = !!(info->flags & DEVICE_VLB);
dev->is_isa = !!(info->flags & (DEVICE_ISA | DEVICE_AT));
if (dev->is_pci || dev->is_vlb)
dev->transfer_size = 4;
else
dev->transfer_size = 2;
if (dev->is_pci) {
pcnet_mem_init(dev, 0x0fffff00);
pcnet_mem_disable(dev);
}
dev->fLinkUp = 1;
dev->cMsLinkUpDelay = 5000;
if (dev->board == DEV_AM79C960_EB) {
dev->maclocal[0] = 0x02; /* 02:07:01 (Racal OID) */
dev->maclocal[1] = 0x07;
dev->maclocal[2] = 0x01;
} else {
dev->maclocal[0] = 0x00; /* 00:0C:87 (AMD OID) */
dev->maclocal[1] = 0x0C;
dev->maclocal[2] = 0x87;
}
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
dev->maclocal[3] = random_generate();
dev->maclocal[4] = random_generate();
dev->maclocal[5] = random_generate();
mac = (((int) dev->maclocal[3]) << 16);
mac |= (((int) dev->maclocal[4]) << 8);
mac |= ((int) dev->maclocal[5]);
device_set_config_mac("mac", mac);
} else {
dev->maclocal[3] = (mac >> 16) & 0xff;
dev->maclocal[4] = (mac >> 8) & 0xff;
dev->maclocal[5] = (mac & 0xff);
}
memcpy(dev->aPROM, dev->maclocal, sizeof(dev->maclocal));
/* Reserved Location: must be 00h */
dev->aPROM[6] = dev->aPROM[7] = 0x00;
/* Reserved Location: must be 00h */
dev->aPROM[8] = 0x00;
/* Hardware ID: must be 11h if compatibility to AMD drivers is desired */
/* 0x00/0xFF=ISA, 0x01=PnP, 0x10=VLB, 0x11=PCI */
if (dev->is_pci)
dev->aPROM[9] = 0x11;
else if (dev->is_vlb)
dev->aPROM[9] = 0x10;
else if (dev->board == DEV_AM79C961)
dev->aPROM[9] = 0x01;
else
dev->aPROM[9] = 0x00;
/* User programmable space, init with 0 */
dev->aPROM[10] = dev->aPROM[11] = 0x00;
if (dev->board == DEV_AM79C960_EB) {
dev->aPROM[14] = 0x52;
dev->aPROM[15] = 0x44; /* NI6510 EtherBlaster 'RD' signature. */
} else {
/* Must be ASCII W (57h) if compatibility to AMD
driver software is desired */
dev->aPROM[14] = dev->aPROM[15] = 0x57;
}
for (c = 0, checksum = 0; c < 16; c++)
checksum += dev->aPROM[c];
*(uint16_t *) &dev->aPROM[12] = cpu_to_le16(checksum);
/*
* Make this device known to the I/O system.
* PCI devices start with address spaces inactive.
*/
if (dev->is_pci) {
/*
* Configure the PCI space registers.
*
* We do this here, so the I/O routines are generic.
*/
/* Enable our address space in PCI. */
pcnet_pci_bar[0].addr_regs[0] = 1;
pcnet_pci_bar[1].addr_regs[0] = 0;
pcnet_pci_regs[0x04] = 3;
/* Add device to the PCI bus, keep its slot number. */
if (info->local & 0x0100)
pci_add_card(PCI_ADD_NETWORK, pcnet_pci_read, pcnet_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, pcnet_pci_read, pcnet_pci_write, dev, &dev->pci_slot);
} else if (dev->board == DEV_AM79C961) {
dev->dma_channel = -1;
/* Weird secondary checksum. The datasheet isn't clear on what
role it might play with the PnP register mirrors before it. */
for (c = 0, checksum = 0; c < 54; c++)
checksum += dev->aPROM[c];
dev->aPROM[51] = checksum;
memcpy(&dev->aPROM[0x40], am79c961_pnp_rom, sizeof(am79c961_pnp_rom));
isapnp_add_card(&dev->aPROM[0x40], sizeof(am79c961_pnp_rom), pcnet_pnp_config_changed, NULL, pcnet_pnp_read_vendor_reg, pcnet_pnp_write_vendor_reg, dev);
} else {
dev->base_address = device_get_config_hex16("base");
dev->base_irq = device_get_config_int("irq");
if (dev->is_vlb)
dev->dma_channel = -1;
else
dev->dma_channel = device_get_config_int("dma");
pcnet_ioset(dev, dev->base_address, 0x20);
}
pcnet_log(2, "%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
dev->name, dev->base_address, dev->base_irq,
dev->aPROM[0], dev->aPROM[1], dev->aPROM[2],
dev->aPROM[3], dev->aPROM[4], dev->aPROM[5]);
pcnet_log(1, "%s: %s attached IO=0x%X IRQ=%d\n", dev->name,
dev->is_pci ? "PCI" : "VLB/ISA", dev->base_address, dev->base_irq);
/* Reset the board. */
pcnetHardReset(dev);
/* Attach ourselves to the network module. */
dev->netcard = network_attach(dev, dev->aPROM, pcnetReceiveNoSync, pcnetSetLinkState);
dev->netcard->byte_period = (dev->board == DEV_AM79C973) ? NET_PERIOD_100M : NET_PERIOD_10M;
timer_add(&dev->timer, pcnetPollTimer, dev, 0);
if (dev->board == DEV_AM79C973)
timer_add(&dev->timer_soft_int, pcnetTimerSoftInt, dev, 0);
timer_add(&dev->timer_restore, pcnetTimerRestore, dev, 0);
return dev;
}
static void
pcnet_close(void *priv)
{
nic_t *dev = (nic_t *) priv;
pcnet_log(1, "%s: closed\n", dev->name);
netcard_close(dev->netcard);
if (dev) {
free(dev);
dev = NULL;
}
}
// clang-format off
static const device_config_t pcnet_pci_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t pcnet_isa_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 12", .value = 12 },
{ .description = "IRQ 15", .value = 15 },
{ .description = "" }
},
},
{
.name = "dma",
.description = "DMA channel",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 5,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "DMA 0", .value = 0 },
{ .description = "DMA 3", .value = 3 },
{ .description = "DMA 5", .value = 5 },
{ .description = "DMA 6", .value = 6 },
{ .description = "DMA 7", .value = 7 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t pcnet_vlb_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 12", .value = 12 },
{ .description = "IRQ 15", .value = 15 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t pcnet_am79c960_device = {
.name = "AMD PCnet-ISA",
.internal_name = "pcnetisa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = DEV_AM79C960,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_isa_config
};
const device_t pcnet_am79c960_eb_device = {
.name = "Racal Interlan EtherBlaster",
.internal_name = "pcnetracal",
.flags = DEVICE_AT | DEVICE_ISA,
.local = DEV_AM79C960_EB,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_isa_config
};
const device_t pcnet_am79c960_vlb_device = {
.name = "AMD PCnet-VL",
.internal_name = "pcnetvlb",
.flags = DEVICE_VLB,
.local = DEV_AM79C960_VLB,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_vlb_config
};
const device_t pcnet_am79c961_device = {
.name = "AMD PCnet-ISA+",
.internal_name = "pcnetisaplus",
.flags = DEVICE_AT | DEVICE_ISA,
.local = DEV_AM79C961,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_pci_config
};
const device_t pcnet_am79c970a_device = {
.name = "AMD PCnet-PCI II",
.internal_name = "pcnetpci",
.flags = DEVICE_PCI,
.local = DEV_AM79C970A,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_pci_config
};
const device_t pcnet_am79c973_device = {
.name = "AMD PCnet-FAST III",
.internal_name = "pcnetfast",
.flags = DEVICE_PCI,
.local = DEV_AM79C973,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_pci_config
};
const device_t pcnet_am79c973_onboard_device = {
.name = "AMD PCnet-FAST III",
.internal_name = "pcnetfast_onboard",
.flags = DEVICE_PCI,
.local = DEV_AM79C973 | 0x0100,
.init = pcnet_init,
.close = pcnet_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pcnet_pci_config
};
``` | /content/code_sandbox/src/network/net_pcnet.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 35,644 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handle SLiRP library processing.
*
* Some of the code was borrowed from libvdeslirp
* <path_to_url
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <inttypes.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/machine.h>
#include <86box/ini.h>
#include <86box/config.h>
#include <86box/video.h>
#include <86box/bswap.h>
#define _SSIZE_T_DEFINED
#include <slirp/libslirp.h>
#ifdef _WIN32
# define WIN32_LEAN_AND_MEAN
# include <windows.h>
#else
# include <poll.h>
#endif
#include <86box/net_event.h>
#define SLIRP_PKT_BATCH NET_QUEUE_LEN
enum {
NET_EVENT_STOP = 0,
NET_EVENT_TX,
NET_EVENT_RX,
NET_EVENT_MAX
};
typedef struct net_slirp_t {
Slirp *slirp;
uint8_t mac_addr[6];
netcard_t *card; /* netcard attached to us */
thread_t *poll_tid;
net_evt_t tx_event;
net_evt_t stop_event;
netpkt_t pkt;
netpkt_t pkt_tx_v[SLIRP_PKT_BATCH];
#ifdef _WIN32
HANDLE sock_event;
#else
uint32_t pfd_len;
uint32_t pfd_size;
struct pollfd *pfd;
#endif
} net_slirp_t;
/* Pulled off from libslirp code. This is only needed for modem. */
#pragma pack(push, 1)
struct arphdr_local {
unsigned char h_dest[6]; /* destination eth addr */
unsigned char h_source[6]; /* source ether addr */
unsigned short h_proto; /* packet type ID field */
unsigned short ar_hrd; /* format of hardware address */
unsigned short ar_pro; /* format of protocol address */
unsigned char ar_hln; /* length of hardware address */
unsigned char ar_pln; /* length of protocol address */
unsigned short ar_op; /* ARP opcode (command) */
/*
* Ethernet looks like this : This bit is variable sized however...
*/
uint8_t ar_sha[6]; /* sender hardware address */
uint32_t ar_sip; /* sender IP address */
uint8_t ar_tha[6]; /* target hardware address */
uint32_t ar_tip; /* target IP address */
};
#pragma pack(pop)
#ifdef ENABLE_SLIRP_LOG
int slirp_do_log = ENABLE_SLIRP_LOG;
static void
slirp_log(const char *fmt, ...)
{
va_list ap;
if (slirp_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define slirp_log(fmt, ...)
#endif
static void
net_slirp_guest_error(UNUSED(const char *msg), UNUSED(void *opaque))
{
slirp_log("SLiRP: guest_error(): %s\n", msg);
}
static int64_t
net_slirp_clock_get_ns(UNUSED(void *opaque))
{
return (int64_t) ((double) tsc / cpuclock * 1000000000.0);
}
static void *
net_slirp_timer_new(SlirpTimerCb cb, void *cb_opaque, UNUSED(void *opaque))
{
pc_timer_t *timer = malloc(sizeof(pc_timer_t));
timer_add(timer, cb, cb_opaque, 0);
return timer;
}
static void
net_slirp_timer_free(void *timer, UNUSED(void *opaque))
{
timer_stop(timer);
free(timer);
}
static void
net_slirp_timer_mod(void *timer, int64_t expire_timer, UNUSED(void *opaque))
{
timer_on_auto(timer, expire_timer * 1000);
}
static void
net_slirp_register_poll_fd(int fd, void *opaque)
{
(void) fd;
(void) opaque;
}
static void
net_slirp_unregister_poll_fd(int fd, void *opaque)
{
(void) fd;
(void) opaque;
}
static void
net_slirp_notify(void *opaque)
{
(void) opaque;
}
#if SLIRP_CHECK_VERSION(4, 8, 0)
slirp_ssize_t
#else
ssize_t
#endif
net_slirp_send_packet(const void *qp, size_t pkt_len, void *opaque)
{
net_slirp_t *slirp = (net_slirp_t *) opaque;
slirp_log("SLiRP: received %d-byte packet\n", pkt_len);
memcpy(slirp->pkt.data, (uint8_t *) qp, pkt_len);
slirp->pkt.len = pkt_len;
network_rx_put_pkt(slirp->card, &slirp->pkt);
return pkt_len;
}
#ifdef _WIN32
static int
net_slirp_add_poll(int fd, int events, void *opaque)
{
net_slirp_t *slirp = (net_slirp_t *) opaque;
long bitmask = 0;
if (events & SLIRP_POLL_IN)
bitmask |= FD_READ | FD_ACCEPT;
if (events & SLIRP_POLL_OUT)
bitmask |= FD_WRITE | FD_CONNECT;
if (events & SLIRP_POLL_HUP)
bitmask |= FD_CLOSE;
if (events & SLIRP_POLL_PRI)
bitmask |= FD_OOB;
WSAEventSelect(fd, slirp->sock_event, bitmask);
return fd;
}
#else
static int
net_slirp_add_poll(int fd, int events, void *opaque)
{
net_slirp_t *slirp = (net_slirp_t *) opaque;
if (slirp->pfd_len >= slirp->pfd_size) {
int newsize = slirp->pfd_size + 16;
struct pollfd *new = realloc(slirp->pfd, newsize * sizeof(struct pollfd));
if (new) {
slirp->pfd = new;
slirp->pfd_size = newsize;
}
}
if ((slirp->pfd_len < slirp->pfd_size)) {
int idx = slirp->pfd_len++;
slirp->pfd[idx].fd = fd;
int pevents = 0;
if (events & SLIRP_POLL_IN)
pevents |= POLLIN;
if (events & SLIRP_POLL_OUT)
pevents |= POLLOUT;
if (events & SLIRP_POLL_ERR)
pevents |= POLLERR;
if (events & SLIRP_POLL_PRI)
pevents |= POLLPRI;
if (events & SLIRP_POLL_HUP)
pevents |= POLLHUP;
slirp->pfd[idx].events = pevents;
return idx;
} else
return -1;
}
#endif
#ifdef _WIN32
static int
net_slirp_get_revents(int idx, void *opaque)
{
net_slirp_t *slirp = (net_slirp_t *) opaque;
int ret = 0;
WSANETWORKEVENTS ev;
if (WSAEnumNetworkEvents(idx, slirp->sock_event, &ev) != 0) {
return ret;
}
# define WSA_TO_POLL(_wsaev, _pollev) \
do { \
if (ev.lNetworkEvents & (_wsaev)) { \
ret |= (_pollev); \
if (ev.iErrorCode[_wsaev##_BIT] != 0) { \
ret |= SLIRP_POLL_ERR; \
} \
} \
} while (0)
WSA_TO_POLL(FD_READ, SLIRP_POLL_IN);
WSA_TO_POLL(FD_ACCEPT, SLIRP_POLL_IN);
WSA_TO_POLL(FD_WRITE, SLIRP_POLL_OUT);
WSA_TO_POLL(FD_CONNECT, SLIRP_POLL_OUT);
WSA_TO_POLL(FD_OOB, SLIRP_POLL_PRI);
WSA_TO_POLL(FD_CLOSE, SLIRP_POLL_HUP);
return ret;
}
#else
static int
net_slirp_get_revents(int idx, void *opaque)
{
net_slirp_t *slirp = (net_slirp_t *) opaque;
int ret = 0;
int events = slirp->pfd[idx].revents;
if (events & POLLIN)
ret |= SLIRP_POLL_IN;
if (events & POLLOUT)
ret |= SLIRP_POLL_OUT;
if (events & POLLPRI)
ret |= SLIRP_POLL_PRI;
if (events & POLLERR)
ret |= SLIRP_POLL_ERR;
if (events & POLLHUP)
ret |= SLIRP_POLL_HUP;
return ret;
}
#endif
static const SlirpCb slirp_cb = {
.send_packet = net_slirp_send_packet,
.guest_error = net_slirp_guest_error,
.clock_get_ns = net_slirp_clock_get_ns,
.timer_new = net_slirp_timer_new,
.timer_free = net_slirp_timer_free,
.timer_mod = net_slirp_timer_mod,
.register_poll_fd = net_slirp_register_poll_fd,
.unregister_poll_fd = net_slirp_unregister_poll_fd,
.notify = net_slirp_notify
};
/* Send a packet to the SLiRP interface. */
static void
net_slirp_in(net_slirp_t *slirp, uint8_t *pkt, int pkt_len)
{
if (!slirp)
return;
slirp_log("SLiRP: sending %d-byte packet to host network\n", pkt_len);
slirp_input(slirp->slirp, (const uint8_t *) pkt, pkt_len);
}
void
net_slirp_in_available(void *priv)
{
net_slirp_t *slirp = (net_slirp_t *) priv;
net_event_set(&slirp->tx_event);
}
#ifdef _WIN32
static void
net_slirp_thread(void *priv)
{
net_slirp_t *slirp = (net_slirp_t *) priv;
/* Start polling. */
slirp_log("SLiRP: polling started.\n");
HANDLE events[3];
events[NET_EVENT_STOP] = net_event_get_handle(&slirp->stop_event);
events[NET_EVENT_TX] = net_event_get_handle(&slirp->tx_event);
events[NET_EVENT_RX] = slirp->sock_event;
bool run = true;
while (run) {
uint32_t timeout = -1;
slirp_pollfds_fill(slirp->slirp, &timeout, net_slirp_add_poll, slirp);
if (timeout < 0)
timeout = INFINITE;
int ret = WaitForMultipleObjects(3, events, FALSE, (DWORD) timeout);
switch (ret - WAIT_OBJECT_0) {
case NET_EVENT_STOP:
run = false;
break;
case NET_EVENT_TX:
{
int packets = network_tx_popv(slirp->card, slirp->pkt_tx_v, SLIRP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
}
}
break;
default:
slirp_pollfds_poll(slirp->slirp, ret == WAIT_FAILED, net_slirp_get_revents, slirp);
break;
}
}
slirp_log("SLiRP: polling stopped.\n");
}
#else
/* Handle the receiving of frames. */
static void
net_slirp_thread(void *priv)
{
net_slirp_t *slirp = (net_slirp_t *) priv;
/* Start polling. */
slirp_log("SLiRP: polling started.\n");
while (1) {
uint32_t timeout = -1;
slirp->pfd_len = 0;
net_slirp_add_poll(net_event_get_fd(&slirp->stop_event), SLIRP_POLL_IN, slirp);
net_slirp_add_poll(net_event_get_fd(&slirp->tx_event), SLIRP_POLL_IN, slirp);
slirp_pollfds_fill(slirp->slirp, &timeout, net_slirp_add_poll, slirp);
int ret = poll(slirp->pfd, slirp->pfd_len, timeout);
slirp_pollfds_poll(slirp->slirp, (ret < 0), net_slirp_get_revents, slirp);
if (slirp->pfd[NET_EVENT_STOP].revents & POLLIN) {
net_event_clear(&slirp->stop_event);
break;
}
if (slirp->pfd[NET_EVENT_TX].revents & POLLIN) {
net_event_clear(&slirp->tx_event);
int packets = network_tx_popv(slirp->card, slirp->pkt_tx_v, SLIRP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_slirp_in(slirp, slirp->pkt_tx_v[i].data, slirp->pkt_tx_v[i].len);
}
}
}
slirp_log("SLiRP: polling stopped.\n");
}
#endif
static int slirp_card_num = 2;
/* Initialize SLiRP for use. */
void *
net_slirp_init(const netcard_t *card, const uint8_t *mac_addr, UNUSED(void *priv), char *netdrv_errbuf)
{
slirp_log("SLiRP: initializing...\n");
net_slirp_t *slirp = calloc(1, sizeof(net_slirp_t));
memcpy(slirp->mac_addr, mac_addr, sizeof(slirp->mac_addr));
slirp->card = (netcard_t *) card;
#ifndef _WIN32
slirp->pfd_size = 16 * sizeof(struct pollfd);
slirp->pfd = malloc(slirp->pfd_size);
memset(slirp->pfd, 0, slirp->pfd_size);
#endif
/* Set the IP addresses to use. */
struct in_addr net = { .s_addr = htonl(0x0a000000 | (slirp_card_num << 8)) }; /* 10.0.x.0 */
struct in_addr mask = { .s_addr = htonl(0xffffff00) }; /* 255.255.255.0 */
struct in_addr host = { .s_addr = htonl(0x0a000002 | (slirp_card_num << 8)) }; /* 10.0.x.2 */
struct in_addr dhcp = { .s_addr = htonl(0x0a00000f | (slirp_card_num << 8)) }; /* 10.0.x.15 */
struct in_addr dns = { .s_addr = htonl(0x0a000003 | (slirp_card_num << 8)) }; /* 10.0.x.3 */
struct in_addr bind = { .s_addr = htonl(0x00000000) }; /* 0.0.0.0 */
struct in6_addr ipv6_dummy = { 0 }; /* contents don't matter; we're not using IPv6 */
/* Initialize SLiRP. */
slirp->slirp = slirp_init(0, 1, net, mask, host, 0, ipv6_dummy, 0, ipv6_dummy, NULL, NULL, NULL, NULL, dhcp, dns, ipv6_dummy, NULL, NULL, &slirp_cb, slirp);
if (!slirp->slirp) {
slirp_log("SLiRP: initialization failed\n");
snprintf(netdrv_errbuf, NET_DRV_ERRBUF_SIZE, "SLiRP initialization failed");
free(slirp);
return NULL;
}
/* Set up port forwarding. */
int udp;
int i = 0;
int external;
int internal;
char category[32];
snprintf(category, sizeof(category), "SLiRP Port Forwarding #%d", card->card_num + 1);
char key[20];
while (1) {
sprintf(key, "%d_protocol", i);
udp = strcmp(config_get_string(category, key, "tcp"), "udp") == 0;
sprintf(key, "%d_external", i);
external = config_get_int(category, key, 0);
sprintf(key, "%d_internal", i);
internal = config_get_int(category, key, 0);
if ((external <= 0) && (internal <= 0))
break;
else if (internal <= 0)
internal = external;
else if (external <= 0)
external = internal;
if (slirp_add_hostfwd(slirp->slirp, udp, bind, external, dhcp, internal) == 0)
pclog("SLiRP: Forwarded %s port external:%d to internal:%d\n", udp ? "UDP" : "TCP", external, internal);
else
pclog("SLiRP: Failed to forward %s port external:%d to internal:%d\n", udp ? "UDP" : "TCP", external, internal);
i++;
}
for (int i = 0; i < SLIRP_PKT_BATCH; i++) {
slirp->pkt_tx_v[i].data = calloc(1, NET_MAX_FRAME);
}
slirp->pkt.data = calloc(1, NET_MAX_FRAME);
net_event_init(&slirp->tx_event);
net_event_init(&slirp->stop_event);
#ifdef _WIN32
slirp->sock_event = CreateEvent(NULL, FALSE, FALSE, NULL);
#endif
if (!strcmp(network_card_get_internal_name(net_cards_conf[net_card_current].device_num), "modem")) {
/* Send a gratuitous ARP here to make SLiRP work properly with SLIP connections. */
struct arphdr_local arphdr;
/* ARP part. */
arphdr.ar_hrd = bswap16(1);
arphdr.ar_pro = bswap16(0x0800);
arphdr.ar_hln = 6;
arphdr.ar_pln = 4;
arphdr.ar_op = bswap16(1);
memcpy(&arphdr.ar_sha, mac_addr, 6);
memcpy(&arphdr.ar_tha, mac_addr, 6);
arphdr.ar_sip = dhcp.s_addr;
arphdr.ar_tip = dhcp.s_addr;
/* Ethernet header part. */
arphdr.h_proto = bswap16(0x0806);
memset(arphdr.h_dest, 0xff, 6);
memset(arphdr.h_source, 0x52, 6);
arphdr.h_source[2] = 0x0a;
arphdr.h_source[3] = 0x00;
arphdr.h_source[4] = slirp_card_num;
arphdr.h_source[5] = 2;
slirp_input(slirp->slirp, (const uint8_t *)&arphdr, sizeof(struct arphdr_local));
}
slirp_log("SLiRP: creating thread...\n");
slirp->poll_tid = thread_create(net_slirp_thread, slirp);
slirp_card_num++;
return slirp;
}
void
net_slirp_close(void *priv)
{
if (!priv)
return;
net_slirp_t *slirp = (net_slirp_t *) priv;
slirp_log("SLiRP: closing\n");
/* Tell the polling thread to shut down. */
net_event_set(&slirp->stop_event);
/* Wait for the thread to finish. */
slirp_log("SLiRP: waiting for thread to end...\n");
thread_wait(slirp->poll_tid);
net_event_close(&slirp->tx_event);
net_event_close(&slirp->stop_event);
slirp_cleanup(slirp->slirp);
for (int i = 0; i < SLIRP_PKT_BATCH; i++) {
free(slirp->pkt_tx_v[i].data);
}
free(slirp->pkt.data);
free(slirp);
slirp_card_num--;
}
const netdrv_t net_slirp_drv = {
&net_slirp_in_available,
&net_slirp_init,
&net_slirp_close
};
``` | /content/code_sandbox/src/network/net_slirp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,845 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Null network driver
*
*
*
* Authors: cold-brewed
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdbool.h>
#ifdef _WIN32
# define WIN32_LEAN_AND_MEAN
# include <windows.h>
# include <winsock2.h>
#else
# include <poll.h>
#endif
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_event.h>
#include <86box/plat_unused.h>
enum {
NET_EVENT_STOP = 0,
NET_EVENT_TX,
NET_EVENT_RX,
NET_EVENT_MAX
};
/* Special define for the windows portion. Because we are not interested
* in NET_EVENT_RX for the null driver, we only need to poll up to
* NET_EVENT_TX. NET_EVENT_RX gives us a different NET_EVENT_MAX
* excluding NET_EVENT_RX. */
#define NET_EVENT_TX_MAX NET_EVENT_RX
#define NULL_PKT_BATCH NET_QUEUE_LEN
typedef struct net_null_t {
uint8_t mac_addr[6];
netcard_t *card;
thread_t *poll_tid;
net_evt_t tx_event;
net_evt_t stop_event;
netpkt_t pkt;
netpkt_t pktv[NULL_PKT_BATCH];
} net_null_t;
#ifdef ENABLE_NET_NULL_LOG
int net_null_do_log = ENABLE_NET_NULL_LOG;
static void
net_null_log(const char *fmt, ...)
{
va_list ap;
if (net_null_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define net_null_log(fmt, ...)
#endif
#ifdef _WIN32
static void
net_null_thread(void *priv)
{
net_null_t *net_null = (net_null_t *) priv;
net_null_log("Null Network: polling started.\n");
HANDLE events[NET_EVENT_TX_MAX];
events[NET_EVENT_STOP] = net_event_get_handle(&net_null->stop_event);
events[NET_EVENT_TX] = net_event_get_handle(&net_null->tx_event);
bool run = true;
while (run) {
int ret = WaitForMultipleObjects(NET_EVENT_TX_MAX, events, FALSE, INFINITE);
switch (ret - WAIT_OBJECT_0) {
case NET_EVENT_STOP:
net_event_clear(&net_null->stop_event);
run = false;
break;
case NET_EVENT_TX:
net_event_clear(&net_null->tx_event);
int packets = network_tx_popv(net_null->card, net_null->pktv, NULL_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_null_log("Null Network: Ignoring TX packet (%d bytes)\n", net_null->pktv[i].len);
}
break;
default:
net_null_log("Null Network: Unknown event.\n");
break;
}
}
net_null_log("Null Network: polling stopped.\n");
}
#else
static void
net_null_thread(void *priv)
{
net_null_t *net_null = (net_null_t *) priv;
net_null_log("Null Network: polling started.\n");
struct pollfd pfd[NET_EVENT_MAX];
pfd[NET_EVENT_STOP].fd = net_event_get_fd(&net_null->stop_event);
pfd[NET_EVENT_STOP].events = POLLIN | POLLPRI;
pfd[NET_EVENT_TX].fd = net_event_get_fd(&net_null->tx_event);
pfd[NET_EVENT_TX].events = POLLIN | POLLPRI;
while (1) {
poll(pfd, NET_EVENT_MAX, -1);
if (pfd[NET_EVENT_STOP].revents & POLLIN) {
net_event_clear(&net_null->stop_event);
break;
}
if (pfd[NET_EVENT_TX].revents & POLLIN) {
net_event_clear(&net_null->tx_event);
int packets = network_tx_popv(net_null->card, net_null->pktv, NULL_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_null_log("Null Network: Ignoring TX packet (%d bytes)\n", net_null->pktv[i].len);
}
}
}
net_null_log("Null Network: polling stopped.\n");
}
#endif
void *
net_null_init(const netcard_t *card, const uint8_t *mac_addr, UNUSED(void *priv), UNUSED(char *netdrv_errbuf))
{
net_null_log("Null Network: Init\n");
net_null_t *net_null = calloc(1, sizeof(net_null_t));
net_null->card = (netcard_t *) card;
memcpy(net_null->mac_addr, mac_addr, sizeof(net_null->mac_addr));
for (int i = 0; i < NULL_PKT_BATCH; i++) {
net_null->pktv[i].data = calloc(1, NET_MAX_FRAME);
}
net_null->pkt.data = calloc(1, NET_MAX_FRAME);
net_event_init(&net_null->tx_event);
net_event_init(&net_null->stop_event);
net_null->poll_tid = thread_create(net_null_thread, net_null);
return net_null;
}
void
net_null_in_available(void *priv)
{
net_null_t *net_null = (net_null_t *) priv;
net_event_set(&net_null->tx_event);
}
void
net_null_close(void *priv)
{
if (!priv)
return;
net_null_t *net_null = (net_null_t *) priv;
net_null_log("Null Network: closing.\n");
/* Tell the thread to terminate. */
net_event_set(&net_null->stop_event);
/* Wait for the thread to finish. */
net_null_log("Null Network: waiting for thread to end...\n");
thread_wait(net_null->poll_tid);
net_null_log("Null Network: thread ended\n");
for (int i = 0; i < NULL_PKT_BATCH; i++) {
free(net_null->pktv[i].data);
}
free(net_null->pkt.data);
net_event_close(&net_null->tx_event);
net_event_close(&net_null->stop_event);
free(net_null);
}
const netdrv_t net_null_drv = {
&net_null_in_available,
&net_null_init,
&net_null_close,
NULL
};
``` | /content/code_sandbox/src/network/net_null.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,500 |
```c
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <stdio.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/dma.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/network.h>
uint16_t
l80225_mii_readw(uint16_t *regs, uint16_t addr)
{
switch (addr) {
case 0x1:
return 0x782D;
case 0x2:
return 0b10110;
case 0x3:
return 0xF830;
case 0x5:
return 0x41E1;
case 0x18:
return 0xC0;
default:
return regs[addr];
}
return 0;
}
void
l80225_mii_writew(uint16_t *regs, uint16_t addr, uint16_t val)
{
regs[addr] = val;
}
``` | /content/code_sandbox/src/network/net_l80225.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 251 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of the network module.
*
* NOTE The definition of the netcard_t is currently not optimal;
* it should be malloc'ed and then linked to the NETCARD def.
* Will be done later.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdatomic.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <time.h>
#include <sys/time.h>
#include <stdbool.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/ui.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_ne2000.h>
#include <86box/net_pcnet.h>
#include <86box/net_wd8003.h>
#ifdef _WIN32
# define WIN32_LEAN_AND_MEAN
# include <windows.h>
# include <winsock2.h>
#endif
static const device_t *net_cards[] = {
&device_none,
&device_internal,
&threec501_device,
&threec503_device,
&pcnet_am79c960_device,
&pcnet_am79c961_device,
&de220p_device,
&ne1000_compat_device,
&ne2000_compat_device,
&ne2000_compat_8bit_device,
&ne1000_device,
&ne2000_device,
&pcnet_am79c960_eb_device,
&rtl8019as_device,
&wd8003e_device,
&wd8003eb_device,
&wd8013ebt_device,
&plip_device,
ðernext_mc_device,
&wd8003eta_device,
&wd8003ea_device,
&wd8013epa_device,
&pcnet_am79c973_device,
&pcnet_am79c970a_device,
&dec_tulip_device,
&rtl8029as_device,
&rtl8139c_plus_device,
&dec_tulip_21140_device,
&dec_tulip_21140_vpc_device,
&dec_tulip_21040_device,
&pcnet_am79c960_vlb_device,
&modem_device,
NULL
};
netcard_conf_t net_cards_conf[NET_CARD_MAX];
uint16_t net_card_current = 0;
/* Global variables. */
network_devmap_t network_devmap = {0};
int network_ndev;
netdev_t network_devs[NET_HOST_INTF_MAX];
/* Local variables. */
#ifdef ENABLE_NETWORK_LOG
int network_do_log = ENABLE_NETWORK_LOG;
static FILE *network_dump = NULL;
static mutex_t *network_dump_mutex;
static void
network_log(const char *fmt, ...)
{
va_list ap;
if (network_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
static void
network_dump_packet(netpkt_t *pkt)
{
if (!network_dump)
return;
struct timeval tv;
gettimeofday(&tv, NULL);
struct {
uint32_t ts_sec;
uint32_t ts_usec;
uint32_t incl_len;
uint32_t orig_len;
} pcap_packet_hdr = {
.ts_sec = tv.tv_sec,
.ts_usec = tv.tv_usec,
.incl_len = pkt->len,
.orig_len = pkt->len
};
if (network_dump_mutex)
thread_wait_mutex(network_dump_mutex);
size_t written;
if ((written = fwrite(&pcap_packet_hdr, 1, sizeof(pcap_packet_hdr), network_dump)) < sizeof(pcap_packet_hdr)) {
network_log("NETWORK: failed to write dump packet header\n");
fseek(network_dump, -written, SEEK_CUR);
} else {
if ((written = fwrite(pkt->data, 1, pkt->len, network_dump)) < pkt->len) {
network_log("NETWORK: failed to write dump packet data\n");
fseek(network_dump, -written - sizeof(pcap_packet_hdr), SEEK_CUR);
} else {
fflush(network_dump);
}
}
if (network_dump_mutex)
thread_release_mutex(network_dump_mutex);
}
#else
# define network_log(fmt, ...)
# define network_dump_packet(pkt)
#endif
#ifdef _WIN32
static void
network_winsock_clean(void)
{
WSACleanup();
}
#endif
/*
* Initialize the configured network cards.
*
* This function gets called only once, from the System
* Platform initialization code (currently in pc.c) to
* set our local stuff to a known state.
*/
void
network_init(void)
{
int i;
#ifdef _WIN32
WSADATA Data;
WSAStartup(MAKEWORD(2, 0), &Data);
atexit(network_winsock_clean);
#endif
/* Create a first device entry that's always there, as needed by UI. */
strcpy(network_devs[0].device, "none");
strcpy(network_devs[0].description, "None");
network_ndev = 1;
/* Initialize the Pcap system module, if present. */
network_devmap.has_slirp = 1;
i = net_pcap_prepare(&network_devs[network_ndev]);
if (i > 0) {
network_devmap.has_pcap = 1;
network_ndev += i;
}
#ifdef HAS_VDE
// Try to load the VDE plug library
if (!net_vde_prepare())
network_devmap.has_vde = 1;
#endif
#ifdef ENABLE_NETWORK_LOG
/* Start packet dump. */
network_dump = fopen("network.pcap", "wb");
if (network_dump) {
struct {
uint32_t magic_number;
uint16_t version_major;
uint16_t version_minor;
int32_t thiszone;
uint32_t sigfigs;
uint32_t snaplen;
uint32_t network;
} pcap_hdr = {
.magic_number = 0xa1b2c3d4,
.version_major = 2,
.version_minor = 4,
.thiszone = 0,
.sigfigs = 0,
.snaplen = 65535,
.network = 1
};
if (fwrite(&pcap_hdr, 1, sizeof(pcap_hdr), network_dump) < sizeof(pcap_hdr)) {
network_log("NETWORK: failed to write dump header\n");
fclose(network_dump);
network_dump = NULL;
} else {
fflush(network_dump);
}
} else {
network_log("NETWORK: failed to open dump file\n");
}
#endif
}
void
network_queue_init(netqueue_t *queue)
{
queue->head = queue->tail = 0;
for (int i = 0; i < NET_QUEUE_LEN; i++) {
queue->packets[i].data = calloc(1, NET_MAX_FRAME);
queue->packets[i].len = 0;
}
}
static bool
network_queue_full(netqueue_t *queue)
{
return ((queue->head + 1) & NET_QUEUE_LEN_MASK) == queue->tail;
}
static bool
network_queue_empty(netqueue_t *queue)
{
return (queue->head == queue->tail);
}
static inline void
network_swap_packet(netpkt_t *pkt1, netpkt_t *pkt2)
{
netpkt_t tmp = *pkt2;
*pkt2 = *pkt1;
*pkt1 = tmp;
}
int
network_queue_put(netqueue_t *queue, uint8_t *data, int len)
{
if (len == 0 || len > NET_MAX_FRAME || network_queue_full(queue)) {
return 0;
}
netpkt_t *pkt = &queue->packets[queue->head];
memcpy(pkt->data, data, len);
pkt->len = len;
queue->head = (queue->head + 1) & NET_QUEUE_LEN_MASK;
return 1;
}
int
network_queue_put_swap(netqueue_t *queue, netpkt_t *src_pkt)
{
if (src_pkt->len == 0 || src_pkt->len > NET_MAX_FRAME || network_queue_full(queue)) {
#ifdef DEBUG
if (src_pkt->len == 0) {
network_log("Discarded zero length packet.\n");
} else if (src_pkt->len > NET_MAX_FRAME) {
network_log("Discarded oversized packet of len=%d.\n", src_pkt->len);
} else {
network_log("Discarded %d bytes packet because the queue is full.\n", src_pkt->len);
}
#endif
return 0;
}
netpkt_t *dst_pkt = &queue->packets[queue->head];
network_swap_packet(src_pkt, dst_pkt);
queue->head = (queue->head + 1) & NET_QUEUE_LEN_MASK;
return 1;
}
static int
network_queue_get_swap(netqueue_t *queue, netpkt_t *dst_pkt)
{
if (network_queue_empty(queue))
return 0;
netpkt_t *src_pkt = &queue->packets[queue->tail];
network_swap_packet(src_pkt, dst_pkt);
queue->tail = (queue->tail + 1) & NET_QUEUE_LEN_MASK;
return 1;
}
static int
network_queue_move(netqueue_t *dst_q, netqueue_t *src_q)
{
if (network_queue_empty(src_q))
return 0;
if (network_queue_full(dst_q)) {
return 0;
}
netpkt_t *src_pkt = &src_q->packets[src_q->tail];
netpkt_t *dst_pkt = &dst_q->packets[dst_q->head];
network_swap_packet(src_pkt, dst_pkt);
dst_q->head = (dst_q->head + 1) & NET_QUEUE_LEN_MASK;
src_q->tail = (src_q->tail + 1) & NET_QUEUE_LEN_MASK;
return dst_pkt->len;
}
void
network_queue_clear(netqueue_t *queue)
{
for (int i = 0; i < NET_QUEUE_LEN; i++) {
free(queue->packets[i].data);
queue->packets[i].len = 0;
}
queue->tail = queue->head = 0;
}
static void
network_rx_queue(void *priv)
{
netcard_t *card = (netcard_t *) priv;
uint32_t new_link_state = net_cards_conf[card->card_num].link_state;
if (new_link_state != card->link_state) {
if (card->set_link_state)
card->set_link_state(card->card_drv, new_link_state);
card->link_state = new_link_state;
}
uint32_t rx_bytes = 0;
for (int i = 0; i < NET_QUEUE_LEN; i++) {
if (card->queued_pkt.len == 0) {
thread_wait_mutex(card->rx_mutex);
int res = network_queue_get_swap(&card->queues[NET_QUEUE_RX], &card->queued_pkt);
thread_release_mutex(card->rx_mutex);
if (!res)
break;
}
network_dump_packet(&card->queued_pkt);
int res = card->rx(card->card_drv, card->queued_pkt.data, card->queued_pkt.len);
if (!res)
break;
rx_bytes += card->queued_pkt.len;
card->queued_pkt.len = 0;
}
/* Transmission. */
uint32_t tx_bytes = 0;
thread_wait_mutex(card->tx_mutex);
for (int i = 0; i < NET_QUEUE_LEN; i++) {
uint32_t bytes = network_queue_move(&card->queues[NET_QUEUE_TX_HOST], &card->queues[NET_QUEUE_TX_VM]);
if (!bytes)
break;
tx_bytes += bytes;
}
thread_release_mutex(card->tx_mutex);
if (tx_bytes) {
/* Notify host that a packet is available in the TX queue */
card->host_drv.notify_in(card->host_drv.priv);
}
double timer_period = card->byte_period * (rx_bytes > tx_bytes ? rx_bytes : tx_bytes);
if (timer_period < 200)
timer_period = 200;
timer_on_auto(&card->timer, timer_period);
bool activity = rx_bytes || tx_bytes;
bool led_on = card->led_timer & 0x80000000;
if ((activity && !led_on) || (card->led_timer & 0x7fffffff) >= 150000) {
ui_sb_update_icon(SB_NETWORK | card->card_num, activity);
card->led_timer = 0 | (activity << 31);
}
card->led_timer += timer_period;
}
/*
* Attach a network card to the system.
*
* This function is called by a hardware driver ("card") after it has
* finished initializing itself, to link itself to the platform support
* modules.
*/
netcard_t *
network_attach(void *card_drv, uint8_t *mac, NETRXCB rx, NETSETLINKSTATE set_link_state)
{
netcard_t *card = calloc(1, sizeof(netcard_t));
int net_type = net_cards_conf[net_card_current].net_type;
card->queued_pkt.data = calloc(1, NET_MAX_FRAME);
card->card_drv = card_drv;
card->rx = rx;
card->set_link_state = set_link_state;
card->tx_mutex = thread_create_mutex();
card->rx_mutex = thread_create_mutex();
card->card_num = net_card_current;
card->byte_period = NET_PERIOD_10M;
char net_drv_error[NET_DRV_ERRBUF_SIZE];
wchar_t tempmsg[NET_DRV_ERRBUF_SIZE * 2];
for (int i = 0; i < NET_QUEUE_COUNT; i++) {
network_queue_init(&card->queues[i]);
}
if ((!strcmp(network_card_get_internal_name(net_cards_conf[net_card_current].device_num), "modem") ||
!strcmp(network_card_get_internal_name(net_cards_conf[net_card_current].device_num), "plip")) && (net_type >= NET_TYPE_PCAP)) {
/* Force SLiRP here. Modem and PLIP only operate on non-Ethernet frames. */
net_type = NET_TYPE_SLIRP;
}
switch (net_type) {
case NET_TYPE_SLIRP:
card->host_drv = net_slirp_drv;
card->host_drv.priv = card->host_drv.init(card, mac, NULL, net_drv_error);
break;
case NET_TYPE_PCAP:
card->host_drv = net_pcap_drv;
card->host_drv.priv = card->host_drv.init(card, mac, net_cards_conf[net_card_current].host_dev_name, net_drv_error);
break;
#ifdef HAS_VDE
case NET_TYPE_VDE:
card->host_drv = net_vde_drv;
card->host_drv.priv = card->host_drv.init(card, mac, net_cards_conf[net_card_current].host_dev_name, net_drv_error);
break;
#endif
default:
card->host_drv.priv = NULL;
break;
}
// Use null driver on:
// * No specific driver selected (card->host_drv.priv is set to null above)
// * Failure to init a specific driver (in which case card->host_drv.priv is null)
if (!card->host_drv.priv) {
if(net_cards_conf[net_card_current].net_type != NET_TYPE_NONE) {
// We're here because of a failure
swprintf(tempmsg, sizeof_w(tempmsg), L"%ls:<br /><br />%s<br /><br />%ls", plat_get_string(STRING_NET_ERROR), net_drv_error, plat_get_string(STRING_NET_ERROR_DESC));
ui_msgbox(MBX_ERROR, tempmsg);
net_cards_conf[net_card_current].net_type = NET_TYPE_NONE;
}
// Init null driver
card->host_drv = net_null_drv;
card->host_drv.priv = card->host_drv.init(card, mac, NULL, net_drv_error);
// Set link state to disconnected by default
network_connect(card->card_num, 0);
ui_sb_update_icon_state(SB_NETWORK | card->card_num, 1);
// If null fails, something is very wrong
// Clean up and fatal
if(!card->host_drv.priv) {
thread_close_mutex(card->tx_mutex);
thread_close_mutex(card->rx_mutex);
for (int i = 0; i < NET_QUEUE_COUNT; i++) {
network_queue_clear(&card->queues[i]);
}
free(card->queued_pkt.data);
free(card);
// Placeholder - insert the error message
fatal("Error initializing the network device: Null driver initialization failed\n");
return NULL;
}
}
timer_add(&card->timer, network_rx_queue, card, 0);
timer_on_auto(&card->timer, 100);
return card;
}
void
netcard_close(netcard_t *card)
{
timer_stop(&card->timer);
card->host_drv.close(card->host_drv.priv);
thread_close_mutex(card->tx_mutex);
thread_close_mutex(card->rx_mutex);
for (int i = 0; i < NET_QUEUE_COUNT; i++) {
network_queue_clear(&card->queues[i]);
}
free(card->queued_pkt.data);
free(card);
}
/* Stop any network activity. */
void
network_close(void)
{
#ifdef ENABLE_NETWORK_LOG
thread_close_mutex(network_dump_mutex);
network_dump_mutex = NULL;
#endif
network_log("NETWORK: closed.\n");
}
/*
* Reset the network card(s).
*
* This function is called each time the system is reset,
* either a hard reset (including power-up) or a soft reset
* including C-A-D reset.) It is responsible for connecting
* everything together.
*/
void
network_reset(void)
{
ui_sb_update_icon(SB_NETWORK, 0);
#ifdef ENABLE_NETWORK_LOG
network_dump_mutex = thread_create_mutex();
#endif
for (uint8_t i = 0; i < NET_CARD_MAX; i++) {
if (!network_dev_available(i)) {
continue;
}
net_card_current = i;
if (net_cards_conf[i].device_num > NET_INTERNAL)
device_add_inst(net_cards[net_cards_conf[i].device_num], i + 1);
}
}
/* Queue a packet for transmission to one of the network providers. */
void
network_tx(netcard_t *card, uint8_t *bufp, int len)
{
network_queue_put(&card->queues[NET_QUEUE_TX_VM], bufp, len);
}
int
network_tx_pop(netcard_t *card, netpkt_t *out_pkt)
{
int ret = 0;
thread_wait_mutex(card->tx_mutex);
ret = network_queue_get_swap(&card->queues[NET_QUEUE_TX_HOST], out_pkt);
thread_release_mutex(card->tx_mutex);
return ret;
}
int
network_tx_popv(netcard_t *card, netpkt_t *pkt_vec, int vec_size)
{
int pkt_count = 0;
netqueue_t *queue = &card->queues[NET_QUEUE_TX_HOST];
thread_wait_mutex(card->tx_mutex);
for (int i = 0; i < vec_size; i++) {
if (!network_queue_get_swap(queue, pkt_vec))
break;
network_dump_packet(pkt_vec);
pkt_count++;
pkt_vec++;
}
thread_release_mutex(card->tx_mutex);
return pkt_count;
}
int
network_rx_put(netcard_t *card, uint8_t *bufp, int len)
{
int ret = 0;
thread_wait_mutex(card->rx_mutex);
ret = network_queue_put(&card->queues[NET_QUEUE_RX], bufp, len);
thread_release_mutex(card->rx_mutex);
return ret;
}
int
network_rx_put_pkt(netcard_t *card, netpkt_t *pkt)
{
int ret = 0;
thread_wait_mutex(card->rx_mutex);
ret = network_queue_put_swap(&card->queues[NET_QUEUE_RX], pkt);
thread_release_mutex(card->rx_mutex);
return ret;
}
void
network_connect(int id, int connect)
{
if (id >= NET_CARD_MAX)
return;
if (connect) {
net_cards_conf[id].link_state &= ~NET_LINK_DOWN;
} else {
net_cards_conf[id].link_state |= NET_LINK_DOWN;
}
}
int
network_is_connected(int id)
{
if (id >= NET_CARD_MAX)
return 0;
return !(net_cards_conf[id].link_state & NET_LINK_DOWN);
}
int
network_dev_to_id(char *devname)
{
for (int i = 0; i < network_ndev; i++) {
if (!strcmp((char *) network_devs[i].device, devname)) {
return i;
}
}
return -1;
}
/* UI */
int
network_dev_available(int id)
{
int available = (net_cards_conf[id].device_num > 0);
if ((net_cards_conf[id].net_type == NET_TYPE_PCAP) &&
(network_dev_to_id(net_cards_conf[id].host_dev_name) <= 0))
available = 0;
// TODO: Handle VDE device
return available;
}
int
network_available(void)
{
int available = 0;
for (int i = 0; i < NET_CARD_MAX; i++) {
available |= network_dev_available(i);
}
return available;
}
/* UI */
int
network_card_available(int card)
{
if (net_cards[card])
return (device_available(net_cards[card]));
return 1;
}
/* UI */
const device_t *
network_card_getdevice(int card)
{
return (net_cards[card]);
}
/* UI */
int
network_card_has_config(int card)
{
if (!net_cards[card])
return 0;
return (device_has_config(net_cards[card]) ? 1 : 0);
}
/* UI */
const char *
network_card_get_internal_name(int card)
{
return device_get_internal_name(net_cards[card]);
}
/* UI */
int
network_card_get_from_internal_name(char *s)
{
int c = 0;
while (net_cards[c] != NULL) {
if (!strcmp(net_cards[c]->internal_name, s))
return c;
c++;
}
return 0;
}
``` | /content/code_sandbox/src/network/network.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,383 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Emulation of the DP8390 Network Interface Controller used by
* the WD family, NE1000/NE2000 family, and 3Com 3C503 NIC's.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Bochs project,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_dp8390.h>
#include <86box/plat_unused.h>
static void dp8390_tx(dp8390_t *dev, uint32_t val);
static int dp8390_rx_common(void *priv, uint8_t *buf, int io_len);
int dp8390_rx(void *priv, uint8_t *buf, int io_len);
int dp3890_inst = 0;
#ifdef ENABLE_DP8390_LOG
int dp8390_do_log = ENABLE_DP8390_LOG;
static void
dp8390_log(const char *fmt, ...)
{
va_list ap;
// if (dp8390_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
// }
}
#else
# define dp8390_log(lvl, fmt, ...)
#endif
/*
* Return the 6-bit index into the multicast
* table. Stolen unashamedly from FreeBSD's if_ed.c
*/
static int
mcast_index(const void *dst)
{
#define POLYNOMIAL 0x04c11db6
uint32_t crc = 0xffffffffL;
int carry;
uint8_t b;
const uint8_t *ep = (const uint8_t *) dst;
for (int8_t i = 6; --i >= 0;) {
b = *ep++;
for (int8_t j = 8; --j >= 0;) {
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
crc <<= 1;
b >>= 1;
if (carry)
crc = ((crc ^ POLYNOMIAL) | carry);
}
}
return (crc >> 26);
#undef POLYNOMIAL
}
/*
* Access the 32K private RAM.
*
* The NE2000 memory is accessed through the data port of the
* ASIC (offset 0) after setting up a remote-DMA transfer.
* Both byte and word accesses are allowed.
* The first 16 bytes contain the MAC address at even locations,
* and there is 16K of buffer memory starting at 16K.
*/
uint32_t
dp8390_chipmem_read(dp8390_t *dev, uint32_t addr, unsigned int len)
{
uint32_t retval = 0;
#ifdef ENABLE_DP8390_LOG
if ((len > 1) && (addr & (len - 1)))
dp8390_log("DP8390: unaligned chipmem word read\n");
#endif
dp8390_log("DP8390: Chipmem Read Address=%04x\n", addr);
/* ROM'd MAC address */
for (unsigned int i = 0; i < len; i++) {
if ((addr >= dev->mem_start) && (addr < dev->mem_end))
retval |= (uint32_t) (dev->mem[addr - dev->mem_start]) << (i << 3);
else if (addr < dev->macaddr_size)
retval |= ((uint32_t) dev->macaddr[addr & (dev->macaddr_size - 1)]) << (i << 3);
else {
dp8390_log("DP8390: out-of-bounds chipmem read, %04X\n", addr);
retval |= 0xff << (i << 3);
}
addr++;
}
return retval;
}
void
dp8390_chipmem_write(dp8390_t *dev, uint32_t addr, uint32_t val, unsigned len)
{
#ifdef ENABLE_DP8390_LOG
if ((len > 1) && (addr & (len - 1)))
dp8390_log("DP8390: unaligned chipmem word write\n");
#endif
dp8390_log("DP8390: Chipmem Write Address=%04x\n", addr);
for (unsigned int i = 0; i < len; i++) {
if ((addr < dev->mem_start) || (addr >= dev->mem_end)) {
dp8390_log("DP8390: out-of-bounds chipmem write, %04X\n", addr);
return;
}
dev->mem[addr - dev->mem_start] = val & 0xff;
val >>= 8;
addr++;
}
}
/* Routines for handling reads/writes to the Command Register. */
uint32_t
dp8390_read_cr(dp8390_t *dev)
{
uint32_t retval;
retval = (((dev->CR.pgsel & 0x03) << 6) | ((dev->CR.rdma_cmd & 0x07) << 3) | (dev->CR.tx_packet << 2) | (dev->CR.start << 1) | (dev->CR.stop));
dp8390_log("DP8390: read CR returns 0x%02x\n", retval);
return retval;
}
void
dp8390_write_cr(dp8390_t *dev, uint32_t val)
{
dp8390_log("DP8390: wrote 0x%02x to CR\n", val);
/* Validate remote-DMA */
if ((val & 0x38) == 0x00) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: CR write - invalid rDMA value 0\n");
#endif
val |= 0x20; /* dma_cmd == 4 is a safe default */
}
/* Check for s/w reset */
if (val & 0x01) {
dev->ISR.reset = 1;
dev->CR.stop = 1;
} else {
dev->CR.stop = 0;
}
dev->CR.rdma_cmd = (val & 0x38) >> 3;
/* If start command issued, the RST bit in the ISR */
/* must be cleared */
if ((val & 0x02) && !dev->CR.start)
dev->ISR.reset = 0;
dev->CR.start = ((val & 0x02) == 0x02);
dev->CR.pgsel = (val & 0xc0) >> 6;
/* Check for send-packet command */
if (dev->CR.rdma_cmd == 3) {
/* Set up DMA read from receive ring */
dev->remote_start = dev->remote_dma = dev->bound_ptr * 256;
dev->remote_bytes = (uint16_t) dp8390_chipmem_read(dev, dev->bound_ptr * 256 + 2, 2);
dp8390_log("DP8390: sending buffer #x%x length %d\n",
dev->remote_start, dev->remote_bytes);
}
/* Check for start-tx */
if ((val & 0x04) && dev->TCR.loop_cntl) {
if (dev->TCR.loop_cntl) {
dp8390_rx_common(dev, &dev->mem[((dev->tx_page_start * 256) - dev->mem_start) & dev->mem_wrap],
dev->tx_bytes);
}
} else if (val & 0x04) {
if (dev->CR.stop || (!dev->CR.start && (dev->flags & DP8390_FLAG_CHECK_CR))) {
if (dev->tx_bytes == 0) /* njh@bandsman.co.uk */
return; /* Solaris9 probe */
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: CR write - tx start, dev in reset\n");
#endif
}
#ifdef ENABLE_DP8390_LOG
if (dev->tx_bytes == 0)
dp8390_log("DP8390: CR write - tx start, tx bytes == 0\n");
#endif
/* Send the packet to the system driver */
dev->CR.tx_packet = 1;
/* TODO: report TX error to the driver ? */
if (!(dev->card->link_state & NET_LINK_DOWN))
network_tx(dev->card, &dev->mem[((dev->tx_page_start * 256) - dev->mem_start) & dev->mem_wrap], dev->tx_bytes);
/* some more debug */
#ifdef ENABLE_DP8390_LOG
if (dev->tx_timer_active)
dp8390_log("DP8390: CR write, tx timer still active\n");
#endif
dp8390_tx(dev, val);
}
/* Linux probes for an interrupt by setting up a remote-DMA read
* of 0 bytes with remote-DMA completion interrupts enabled.
* Detect this here */
if ((dev->CR.rdma_cmd == 0x01) && dev->CR.start && (dev->remote_bytes == 0)) {
dev->ISR.rdma_done = 1;
if (dev->IMR.rdma_inte && dev->interrupt) {
dev->interrupt(dev->priv, 1);
if (dev->flags & DP8390_FLAG_CLEAR_IRQ)
dev->interrupt(dev->priv, 0);
}
}
}
static void
dp8390_tx(dp8390_t *dev, UNUSED(uint32_t val))
{
dev->CR.tx_packet = 0;
dev->TSR.tx_ok = 1;
dev->ISR.pkt_tx = 1;
/* Generate an interrupt if not masked */
if (dev->IMR.tx_inte && dev->interrupt)
dev->interrupt(dev->priv, 1);
dev->tx_timer_active = 0;
}
/*
* Called by the platform-specific code when an Ethernet frame
* has been received. The destination address is tested to see
* if it should be accepted, and if the RX ring has enough room,
* it is copied into it and the receive process is updated.
*/
static int
dp8390_rx_common(void *priv, uint8_t *buf, int io_len)
{
dp8390_t *dev = (dp8390_t *) priv;
static uint8_t bcast_addr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
uint8_t pkthdr[4];
uint8_t *startptr;
int pages;
int avail;
int idx;
int nextpage;
int endbytes;
if (io_len != 60)
dp8390_log("rx_frame with length %d\n", io_len);
if ((dev->CR.stop != 0) || (dev->page_start == 0))
return 0;
if (dev->card->link_state & NET_LINK_DOWN)
return 0;
/*
* Add the pkt header + CRC to the length, and work
* out how many 256-byte pages the frame would occupy.
*/
pages = (io_len + sizeof(pkthdr) + sizeof(uint32_t) + 255) / 256;
if (dev->curr_page < dev->bound_ptr) {
avail = dev->bound_ptr - dev->curr_page;
} else {
avail = (dev->page_stop - dev->page_start) - (dev->curr_page - dev->bound_ptr);
}
/*
* Avoid getting into a buffer overflow condition by
* not attempting to do partial receives. The emulation
* to handle this condition seems particularly painful.
*/
if ((avail < pages)
#if DP8390_NEVER_FULL_RING
|| (avail == pages)
#endif
) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: no space\n");
#endif
return 0;
}
if ((io_len < 40 /*60*/) && !dev->RCR.runts_ok) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: rejected small packet, length %d\n", io_len);
#endif
return 1;
}
/* Some computers don't care... */
if (io_len < 60)
io_len = 60;
dp8390_log("DP8390: RX %x:%x:%x:%x:%x:%x > %x:%x:%x:%x:%x:%x len %d\n",
buf[6], buf[7], buf[8], buf[9], buf[10], buf[11],
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
io_len);
/* Do address filtering if not in promiscuous mode. */
if (!dev->RCR.promisc) {
/* If this is a broadcast frame.. */
if (!memcmp(buf, bcast_addr, 6)) {
/* Broadcast not enabled, we're done. */
if (!dev->RCR.broadcast) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: RX BC disabled\n");
#endif
return 1;
}
}
/* If this is a multicast frame.. */
else if (buf[0] & 0x01) {
/* Multicast not enabled, we're done. */
if (!dev->RCR.multicast) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: RX MC disabled\n");
#endif
return 1;
}
/* Are we listening to this multicast address? */
idx = mcast_index(buf);
if (!(dev->mchash[idx >> 3] & (1 << (idx & 0x7)))) {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: RX MC not listed\n");
#endif
return 1;
}
}
/* Unicast, must be for us.. */
else if (memcmp(buf, dev->physaddr, 6))
return 1;
} else {
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: RX promiscuous receive\n");
#endif
}
nextpage = dev->curr_page + pages;
if (nextpage >= dev->page_stop)
nextpage -= (dev->page_stop - dev->page_start);
/* Set up packet header. */
pkthdr[0] = 0x01; /* RXOK - packet is OK */
if (buf[0] & 0x01)
pkthdr[0] |= 0x20; /* MULTICAST packet */
pkthdr[1] = nextpage; /* ptr to next packet */
pkthdr[2] = (io_len + sizeof(pkthdr)) & 0xff; /* length-low */
pkthdr[3] = (io_len + sizeof(pkthdr)) >> 8; /* length-hi */
dp8390_log("DP8390: RX pkthdr [%02x %02x %02x %02x]\n",
pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]);
/* Copy into buffer, update curpage, and signal interrupt if config'd */
if (((dev->curr_page * 256) - dev->mem_start) >= dev->mem_size)
/* Do this to fix Windows 2000 crashing the emulator when its
MPU-401 probe hits the NIC. */
startptr = dev->sink_buffer;
else
startptr = &dev->mem[(dev->curr_page * 256) - dev->mem_start];
memcpy(startptr, pkthdr, sizeof(pkthdr));
if ((nextpage > dev->curr_page) || ((dev->curr_page + pages) == dev->page_stop)) {
memcpy(startptr + sizeof(pkthdr), buf, io_len);
} else {
endbytes = (dev->page_stop - dev->curr_page) * 256;
memcpy(startptr + sizeof(pkthdr), buf, endbytes - sizeof(pkthdr));
startptr = &dev->mem[((dev->page_start * 256) - dev->mem_start) & dev->mem_wrap];
memcpy(startptr, buf + endbytes - sizeof(pkthdr), io_len - endbytes + 8);
}
dev->curr_page = nextpage;
dev->RSR.rx_ok = 1;
dev->RSR.rx_mbit = (buf[0] & 0x01) ? 1 : 0;
dev->ISR.pkt_rx = 1;
if (dev->IMR.rx_inte && dev->interrupt)
dev->interrupt(dev->priv, 1);
return 1;
}
int
dp8390_rx(void *priv, uint8_t *buf, int io_len)
{
const dp8390_t *dev = (dp8390_t *) priv;
if ((dev->DCR.loop == 0) || (dev->TCR.loop_cntl != 0))
return 0;
return dp8390_rx_common(priv, buf, io_len);
}
/* Handle reads/writes to the 'zeroth' page of the DS8390 register file. */
uint32_t
dp8390_page0_read(dp8390_t *dev, uint32_t off, unsigned int len)
{
uint8_t retval = 0;
if (len > 1) {
/* encountered with win98 hardware probe */
dp8390_log("DP8390: bad length! Page0 read from register 0x%02x, len=%u\n",
off, len);
return retval;
}
switch (off) {
case 0x01: /* CLDA0 */
retval = (dev->local_dma & 0xff);
break;
case 0x02: /* CLDA1 */
retval = (dev->local_dma >> 8);
break;
case 0x03: /* BNRY */
retval = dev->bound_ptr;
break;
case 0x04: /* TSR */
retval = ((dev->TSR.ow_coll << 7) | (dev->TSR.cd_hbeat << 6) | (dev->TSR.fifo_ur << 5) | (dev->TSR.no_carrier << 4) | (dev->TSR.aborted << 3) | (dev->TSR.collided << 2) | (dev->TSR.tx_ok));
break;
case 0x05: /* NCR */
retval = dev->num_coll;
break;
case 0x06: /* FIFO */
/* reading FIFO is only valid in loopback mode */
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: reading FIFO not supported yet\n");
#endif
retval = dev->fifo;
break;
case 0x07: /* ISR */
retval = ((dev->ISR.reset << 7) | (dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx));
break;
case 0x08: /* CRDA0 */
retval = (dev->remote_dma & 0xff);
break;
case 0x09: /* CRDA1 */
retval = (dev->remote_dma >> 8);
break;
case 0x0a: /* reserved / RTL8029ID0 */
retval = dev->id0;
break;
case 0x0b: /* reserved / RTL8029ID1 */
retval = dev->id1;
break;
case 0x0c: /* RSR */
retval = ((dev->RSR.deferred << 7) | (dev->RSR.rx_disabled << 6) | (dev->RSR.rx_mbit << 5) | (dev->RSR.rx_missed << 4) | (dev->RSR.fifo_or << 3) | (dev->RSR.bad_falign << 2) | (dev->RSR.bad_crc << 1) | (dev->RSR.rx_ok));
break;
case 0x0d: /* CNTR0 */
retval = dev->tallycnt_0;
break;
case 0x0e: /* CNTR1 */
retval = dev->tallycnt_1;
break;
case 0x0f: /* CNTR2 */
retval = dev->tallycnt_2;
break;
default:
dp8390_log("DP8390: Page0 register 0x%02x out of range\n", off);
break;
}
dp8390_log("DP8390: Page0 read from register 0x%02x, value=0x%02x\n", off,
retval);
return retval;
}
void
dp8390_page0_write(dp8390_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len))
{
uint8_t val2;
dp8390_log("DP839: Page0 write to register 0x%02x, value=0x%02x\n",
off, val);
switch (off) {
case 0x01: /* PSTART */
dev->page_start = val;
dp8390_log("DP8390: Starting RAM address: %04X\n", val << 8);
break;
case 0x02: /* PSTOP */
dev->page_stop = val;
dp8390_log("DP8390: Stopping RAM address: %04X\n", val << 8);
break;
case 0x03: /* BNRY */
dev->bound_ptr = val;
break;
case 0x04: /* TPSR */
dev->tx_page_start = val;
break;
case 0x05: /* TBCR0 */
/* Clear out low byte and re-insert */
dev->tx_bytes &= 0xff00;
dev->tx_bytes |= (val & 0xff);
break;
case 0x06: /* TBCR1 */
/* Clear out high byte and re-insert */
dev->tx_bytes &= 0x00ff;
dev->tx_bytes |= ((val & 0xff) << 8);
break;
case 0x07: /* ISR */
val &= 0x7f; /* clear RST bit - status-only bit */
/* All other values are cleared iff the ISR bit is 1 */
dev->ISR.pkt_rx &= !((int) ((val & 0x01) == 0x01));
dev->ISR.pkt_tx &= !((int) ((val & 0x02) == 0x02));
dev->ISR.rx_err &= !((int) ((val & 0x04) == 0x04));
dev->ISR.tx_err &= !((int) ((val & 0x08) == 0x08));
dev->ISR.overwrite &= !((int) ((val & 0x10) == 0x10));
dev->ISR.cnt_oflow &= !((int) ((val & 0x20) == 0x20));
dev->ISR.rdma_done &= !((int) ((val & 0x40) == 0x40));
val = ((dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx));
val &= ((dev->IMR.rdma_inte << 6) | (dev->IMR.cofl_inte << 5) | (dev->IMR.overw_inte << 4) | (dev->IMR.txerr_inte << 3) | (dev->IMR.rxerr_inte << 2) | (dev->IMR.tx_inte << 1) | (dev->IMR.rx_inte));
if ((val == 0x00) && dev->interrupt)
dev->interrupt(dev->priv, 0);
break;
case 0x08: /* RSAR0 */
/* Clear out low byte and re-insert */
dev->remote_start &= 0xff00;
dev->remote_start |= (val & 0xff);
dev->remote_dma = dev->remote_start;
break;
case 0x09: /* RSAR1 */
/* Clear out high byte and re-insert */
dev->remote_start &= 0x00ff;
dev->remote_start |= ((val & 0xff) << 8);
dev->remote_dma = dev->remote_start;
break;
case 0x0a: /* RBCR0 */
/* Clear out low byte and re-insert */
dev->remote_bytes &= 0xff00;
dev->remote_bytes |= (val & 0xff);
break;
case 0x0b: /* RBCR1 */
/* Clear out high byte and re-insert */
dev->remote_bytes &= 0x00ff;
dev->remote_bytes |= ((val & 0xff) << 8);
break;
case 0x0c: /* RCR */
/* Check if the reserved bits are set */
#ifdef ENABLE_DP8390_LOG
if (val & 0xc0)
dp8390_log("DP8390: RCR write, reserved bits set\n");
#endif
/* Set all other bit-fields */
dev->RCR.errors_ok = ((val & 0x01) == 0x01);
dev->RCR.runts_ok = ((val & 0x02) == 0x02);
dev->RCR.broadcast = ((val & 0x04) == 0x04);
dev->RCR.multicast = ((val & 0x08) == 0x08);
dev->RCR.promisc = ((val & 0x10) == 0x10);
dev->RCR.monitor = ((val & 0x20) == 0x20);
/* Monitor bit is a little suspicious... */
#ifdef ENABLE_DP8390_LOG
if (val & 0x20)
dp8390_log("DP8390: RCR write, monitor bit set!\n");
#endif
break;
case 0x0d: /* TCR */
/* Check reserved bits */
#ifdef ENABLE_DP8390_LOG
if (val & 0xe0)
dp8390_log("DP8390: TCR write, reserved bits set\n");
#endif
/* Test loop mode (not supported) */
if (val & 0x06) {
dev->TCR.loop_cntl = (val & 0x6) >> 1;
dp8390_log("DP8390: TCR write, loop mode %d not supported\n",
dev->TCR.loop_cntl);
} else
dev->TCR.loop_cntl = 0;
/* Inhibit-CRC not supported. */
#ifdef ENABLE_DP8390_LOG
if (val & 0x01)
dp8390_log("DP8390: TCR write, inhibit-CRC not supported\n");
#endif
/* Auto-transmit disable very suspicious */
#ifdef ENABLE_DP8390_LOG
if (val & 0x08)
dp8390_log("DP8390: TCR write, auto transmit disable not supported\n");
#endif
/* Allow collision-offset to be set, although not used */
dev->TCR.coll_prio = ((val & 0x08) == 0x08);
break;
case 0x0e: /* DCR */
/* the loopback mode is not suppported yet */
#ifdef ENABLE_DP8390_LOG
if (!(val & 0x08))
dp8390_log("DP8390: DCR write, loopback mode selected\n");
#endif
/* It is questionable to set longaddr and auto_rx, since
* they are not supported on the NE2000. Print a warning
* and continue. */
#ifdef ENABLE_DP8390_LOG
if (val & 0x04)
dp8390_log("DP8390: DCR write - LAS set ???\n");
if (val & 0x10)
dp8390_log("DP8390: DCR write - AR set ???\n");
#endif
/* Set other values. */
dev->DCR.wdsize = ((val & 0x01) == 0x01);
dev->DCR.endian = ((val & 0x02) == 0x02);
dev->DCR.longaddr = ((val & 0x04) == 0x04); /* illegal ? */
dev->DCR.loop = ((val & 0x08) == 0x08);
dev->DCR.auto_rx = ((val & 0x10) == 0x10); /* also illegal ? */
dev->DCR.fifo_size = (val & 0x60) >> 5;
break;
case 0x0f: /* IMR */
/* Check for reserved bit */
#ifdef ENABLE_DP8390_LOG
if (val & 0x80)
dp8390_log("DP8390: IMR write, reserved bit set\n");
#endif
/* Set other values */
dev->IMR.rx_inte = ((val & 0x01) == 0x01);
dev->IMR.tx_inte = ((val & 0x02) == 0x02);
dev->IMR.rxerr_inte = ((val & 0x04) == 0x04);
dev->IMR.txerr_inte = ((val & 0x08) == 0x08);
dev->IMR.overw_inte = ((val & 0x10) == 0x10);
dev->IMR.cofl_inte = ((val & 0x20) == 0x20);
dev->IMR.rdma_inte = ((val & 0x40) == 0x40);
val2 = ((dev->ISR.rdma_done << 6) | (dev->ISR.cnt_oflow << 5) | (dev->ISR.overwrite << 4) | (dev->ISR.tx_err << 3) | (dev->ISR.rx_err << 2) | (dev->ISR.pkt_tx << 1) | (dev->ISR.pkt_rx));
if (dev->interrupt) {
if (((val & val2) & 0x7f) == 0)
dev->interrupt(dev->priv, 0);
else
dev->interrupt(dev->priv, 1);
}
break;
default:
dp8390_log("DP8390: Page0 write, bad register 0x%02x\n", off);
break;
}
}
/* Handle reads/writes to the first page of the DS8390 register file. */
uint32_t
dp8390_page1_read(dp8390_t *dev, uint32_t off, UNUSED(unsigned int len))
{
dp8390_log("DP8390: Page1 read from register 0x%02x, len=%u\n",
off, len);
switch (off) {
case 0x01: /* PAR0-5 */
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
return (dev->physaddr[off - 1]);
case 0x07: /* CURR */
dp8390_log("DP8390: returning current page: 0x%02x\n",
(dev->curr_page));
return (dev->curr_page);
case 0x08: /* MAR0-7 */
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
return (dev->mchash[off - 8]);
default:
dp8390_log("DP8390: Page1 read register 0x%02x out of range\n",
off);
return 0;
}
}
void
dp8390_page1_write(dp8390_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len))
{
dp8390_log("DP8390: Page1 write to register 0x%02x, len=%u, value=0x%04x\n",
off, len, val);
switch (off) {
case 0x01: /* PAR0-5 */
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
dev->physaddr[off - 1] = val;
if (off == 6)
dp8390_log("DP8390: Physical address set to %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->physaddr[0], dev->physaddr[1],
dev->physaddr[2], dev->physaddr[3],
dev->physaddr[4], dev->physaddr[5]);
break;
case 0x07: /* CURR */
dev->curr_page = val;
break;
case 0x08: /* MAR0-7 */
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
dev->mchash[off - 8] = val;
break;
default:
dp8390_log("DP8390: Page1 write register 0x%02x out of range\n",
off);
break;
}
}
/* Handle reads/writes to the second page of the DS8390 register file. */
uint32_t
dp8390_page2_read(dp8390_t *dev, uint32_t off, UNUSED(unsigned int len))
{
dp8390_log("DP8390: Page2 read from register 0x%02x, len=%u\n",
off, len);
switch (off) {
case 0x01: /* PSTART */
return (dev->page_start);
case 0x02: /* PSTOP */
return (dev->page_stop);
case 0x03: /* Remote Next-packet pointer */
return (dev->rempkt_ptr);
case 0x04: /* TPSR */
return (dev->tx_page_start);
case 0x05: /* Local Next-packet pointer */
return (dev->localpkt_ptr);
case 0x06: /* Address counter (upper) */
return (dev->address_cnt >> 8);
case 0x07: /* Address counter (lower) */
return (dev->address_cnt & 0xff);
case 0x08: /* Reserved */
case 0x09:
case 0x0a:
case 0x0b:
dp8390_log("DP8390: reserved Page2 read - register 0x%02x\n",
off);
return 0xff;
case 0x0c: /* RCR */
return ((dev->RCR.monitor << 5) | (dev->RCR.promisc << 4) | (dev->RCR.multicast << 3) | (dev->RCR.broadcast << 2) | (dev->RCR.runts_ok << 1) | (dev->RCR.errors_ok));
case 0x0d: /* TCR */
return ((dev->TCR.coll_prio << 4) | (dev->TCR.ext_stoptx << 3) | ((dev->TCR.loop_cntl & 0x3) << 1) | (dev->TCR.crc_disable));
case 0x0e: /* DCR */
return (((dev->DCR.fifo_size & 0x3) << 5) | (dev->DCR.auto_rx << 4) | (dev->DCR.loop << 3) | (dev->DCR.longaddr << 2) | (dev->DCR.endian << 1) | (dev->DCR.wdsize));
case 0x0f: /* IMR */
return ((dev->IMR.rdma_inte << 6) | (dev->IMR.cofl_inte << 5) | (dev->IMR.overw_inte << 4) | (dev->IMR.txerr_inte << 3) | (dev->IMR.rxerr_inte << 2) | (dev->IMR.tx_inte << 1) | (dev->IMR.rx_inte));
default:
dp8390_log("DP8390: Page2 register 0x%02x out of range\n",
off);
break;
}
return 0;
}
void
dp8390_page2_write(dp8390_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len))
{
/* Maybe all writes here should be BX_PANIC()'d, since they
affect internal operation, but let them through for now
and print a warning. */
dp8390_log("DP8390: Page2 write to register 0x%02x, len=%u, value=0x%04x\n",
off, len, val);
switch (off) {
case 0x01: /* CLDA0 */
/* Clear out low byte and re-insert */
dev->local_dma &= 0xff00;
dev->local_dma |= (val & 0xff);
break;
case 0x02: /* CLDA1 */
/* Clear out high byte and re-insert */
dev->local_dma &= 0x00ff;
dev->local_dma |= ((val & 0xff) << 8);
break;
case 0x03: /* Remote Next-pkt pointer */
dev->rempkt_ptr = val;
break;
case 0x04:
#ifdef ENABLE_DP8390_LOG
dp8390_log("DP8390: Page 2 write to reserved register 0x04\n");
#endif
break;
case 0x05: /* Local Next-packet pointer */
dev->localpkt_ptr = val;
break;
case 0x06: /* Address counter (upper) */
/* Clear out high byte and re-insert */
dev->address_cnt &= 0x00ff;
dev->address_cnt |= ((val & 0xff) << 8);
break;
case 0x07: /* Address counter (lower) */
/* Clear out low byte and re-insert */
dev->address_cnt &= 0xff00;
dev->address_cnt |= (val & 0xff);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
dp8390_log("DP8390: Page2 write to reserved register 0x%02x\n",
off);
break;
default:
dp8390_log("DP8390: Page2 write, illegal register 0x%02x\n",
off);
break;
}
}
void
dp8390_set_defaults(dp8390_t *dev, uint8_t flags)
{
dev->macaddr_size = (flags & DP8390_FLAG_EVEN_MAC) ? 32 : 16;
dev->flags = flags;
}
void
dp8390_mem_alloc(dp8390_t *dev, uint32_t start, uint32_t size)
{
dev->mem = (uint8_t *) malloc(size * sizeof(uint8_t));
memset(dev->mem, 0, size * sizeof(uint8_t));
dev->mem_start = start;
dev->mem_end = start + size;
dev->mem_size = size;
dev->mem_wrap = size - 1;
dp8390_log("DP8390: Mapped %i bytes of memory at address %04X in the address space\n", size, start);
}
void
dp8390_set_id(dp8390_t *dev, uint8_t id0, uint8_t id1)
{
dev->id0 = id0;
dev->id1 = id1;
}
void
dp8390_reset(dp8390_t *dev)
{
int max;
int shift = 0;
if (dev->flags & DP8390_FLAG_EVEN_MAC)
shift = 1;
max = 16 << shift;
/* Initialize the MAC address area by doubling the physical address */
for (int i = 0; i < max; i++) {
if (i < (6 << shift))
dev->macaddr[i] = dev->physaddr[i >> shift];
else /* Signature */
dev->macaddr[i] = 0x57;
}
/* Zero out registers and memory */
memset(&dev->CR, 0x00, sizeof(dev->CR));
memset(&dev->ISR, 0x00, sizeof(dev->ISR));
memset(&dev->IMR, 0x00, sizeof(dev->IMR));
memset(&dev->DCR, 0x00, sizeof(dev->DCR));
memset(&dev->TCR, 0x00, sizeof(dev->TCR));
memset(&dev->TSR, 0x00, sizeof(dev->TSR));
memset(&dev->RSR, 0x00, sizeof(dev->RSR));
dev->tx_timer_active = 0;
dev->local_dma = 0;
dev->page_start = 0;
dev->page_stop = 0;
dev->bound_ptr = 0;
dev->tx_page_start = 0;
dev->num_coll = 0;
dev->tx_bytes = 0;
dev->fifo = 0;
dev->remote_dma = 0;
dev->remote_start = 0;
dev->remote_bytes = 0;
dev->tallycnt_0 = 0;
dev->tallycnt_1 = 0;
dev->tallycnt_2 = 0;
dev->curr_page = 0;
dev->rempkt_ptr = 0;
dev->localpkt_ptr = 0;
dev->address_cnt = 0;
memset(dev->mem, 0x00, dev->mem_size);
/* Set power-up conditions */
dev->CR.stop = 1;
dev->CR.rdma_cmd = 4;
dev->ISR.reset = 1;
dev->DCR.longaddr = 1;
if (dev->interrupt)
dev->interrupt(dev->priv, 0);
}
void
dp8390_soft_reset(dp8390_t *dev)
{
memset(&(dev->ISR), 0x00, sizeof(dev->ISR));
dev->ISR.reset = 1;
}
static void *
dp8390_init(UNUSED(const device_t *info))
{
dp8390_t *dp8390 = (dp8390_t *) malloc(sizeof(dp8390_t));
memset(dp8390, 0, sizeof(dp8390_t));
/* Set values assuming WORD and only the clear IRQ flag -
- the NIC can then call dp8390_set_defaults() again to
change that. */
dp8390_set_defaults(dp8390, DP8390_FLAG_CLEAR_IRQ);
/* Set the two registers some NIC's use as ID bytes,
to their default values of 0xFF. */
dp8390_set_id(dp8390, 0xff, 0xff);
return dp8390;
}
static void
dp8390_close(void *priv)
{
dp8390_t *dp8390 = (dp8390_t *) priv;
if (dp8390) {
if (dp8390->mem)
free(dp8390->mem);
if (dp8390->card) {
netcard_close(dp8390->card);
}
free(dp8390);
}
}
const device_t dp8390_device = {
.name = "DP8390 Network Interface Controller",
.internal_name = "dp8390",
.flags = 0,
.local = 0,
.init = dp8390_init,
.close = dp8390_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/network/net_dp8390.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,112 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the following network controllers:
* - SMC/WD 8003E (ISA 8-bit);
* - SMC/WD 8013EBT (ISA 16-bit);
* - SMC/WD 8013EP/A (MCA).
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* TheCollector1995, <mariogplayer@gmail.com>
* Miran Grca, <mgrca8@gmail.com>
* Peter Grehan, <grehan@iprg.nokia.com>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/mca.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/random.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/thread.h>
#include <86box/network.h>
#include <86box/net_dp8390.h>
#include <86box/net_wd8003.h>
#include <86box/bswap.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include "cpu.h"
/* Board type codes in card ID */
#define WE_TYPE_WD8003 0x01
#define WE_TYPE_WD8003S 0x02
#define WE_TYPE_WD8003E 0x03
#define WE_TYPE_WD8013EBT 0x05
#define WE_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
#define WE_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
#define WE_TYPE_TOSHIBA3 0x13 /* named PCETB */
#define WE_TYPE_TOSHIBA4 0x14 /* named PCETC */
#define WE_TYPE_WD8003W 0x24
#define WE_TYPE_WD8003EB 0x25
#define WE_TYPE_WD8013W 0x26
#define WE_TYPE_WD8013EP 0x27
#define WE_TYPE_WD8013WC 0x28
#define WE_TYPE_WD8013EPC 0x29
#define WE_TYPE_SMC8216T 0x2a
#define WE_TYPE_SMC8216C 0x2b
#define WE_TYPE_WD8013EBP 0x2c
#define WE_ICR_16BIT_SLOT 0x01
#define WE_MSR_ENABLE_RAM 0x40
#define WE_MSR_SOFT_RESET 0x80
#define WE_IRR_ENABLE_IRQ 0x80
#define WE_ID_ETHERNET 0x01
#define WE_ID_SOFT_CONFIG 0x20
#define WE_ID_EXTRA_RAM 0x40
#define WE_ID_BUS_MCA 0x80
typedef struct wd_t {
dp8390_t *dp8390;
mem_mapping_t ram_mapping;
uint32_t ram_addr;
uint32_t ram_size;
uint8_t maclocal[6]; /* configured MAC (local) address */
uint8_t bit16;
uint8_t pad;
int board;
const char *name;
uint32_t base_address;
int irq;
/* POS registers, MCA boards only */
uint8_t pos_regs[8];
/* Memory for WD cards*/
uint8_t msr; /* Memory Select Register (MSR) */
uint8_t icr; /* Interface Configuration Register (ICR) */
uint8_t irr; /* Interrupt Request Register (IRR) */
uint8_t laar; /* LA Address Register (read by Windows 98!) */
uint8_t if_chip;
uint8_t board_chip;
} wd_t;
#ifdef ENABLE_WD_LOG
int wd_do_log = ENABLE_WD_LOG;
static void
wdlog(const char *fmt, ...)
{
va_list ap;
if (wd_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define wdlog(fmt, ...)
#endif
static const int we_int_table[4] = { 2, 3, 4, 7 };
static void
wd_interrupt(void *priv, int set)
{
const wd_t *dev = (wd_t *) priv;
if (!(dev->irr & WE_IRR_ENABLE_IRQ))
return;
if (set)
picint(1 << dev->irq);
else
picintc(1 << dev->irq);
}
/* reset - restore state to power-up, cancelling all i/o */
static void
wd_reset(void *priv)
{
wd_t *dev = (wd_t *) priv;
wdlog("%s: reset\n", dev->name);
dp8390_reset(dev->dp8390);
}
static void
wd_soft_reset(void *priv)
{
wd_t *dev = (wd_t *) priv;
dp8390_soft_reset(dev->dp8390);
}
static uint8_t
wd_ram_read(uint32_t addr, void *priv)
{
const wd_t *dev = (wd_t *) priv;
wdlog("WD80x3: RAM Read: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), dev->dp8390->mem[addr & (dev->ram_size - 1)]);
return dev->dp8390->mem[addr & (dev->ram_size - 1)];
}
static void
wd_ram_write(uint32_t addr, uint8_t val, void *priv)
{
wd_t *dev = (wd_t *) priv;
dev->dp8390->mem[addr & (dev->ram_size - 1)] = val;
wdlog("WD80x3: RAM Write: addr=%06x, val=%02x\n", addr & (dev->ram_size - 1), val);
}
static int
wd_get_irq_index(wd_t *dev)
{
uint8_t irq = 255;
for (uint8_t i = 0; i < 4; i++) {
if (we_int_table[i] == dev->irq)
irq = i;
}
if (irq != 255)
return ((irq & 0x03) << 5);
else
return 0;
}
static uint32_t
wd_smc_read(wd_t *dev, uint32_t off)
{
uint32_t retval = 0;
uint32_t checksum = 0;
if (dev->board == WD8003E)
off |= 0x08;
switch (off) {
case 0x00:
if (dev->board_chip & WE_ID_BUS_MCA)
retval = (dev->msr & 0xc0) | ((dev->ram_addr >> 13) & 0x3f);
else
retval = dev->msr;
break;
case 0x01:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
retval = dev->icr;
else
retval = dev->icr & WE_ICR_16BIT_SLOT;
break;
case 0x04:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
retval = (dev->irr & 0x9f) | wd_get_irq_index(dev);
break;
case 0x05:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
retval = dev->laar;
break;
case 0x07:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
retval = dev->if_chip;
break;
case 0x08:
retval = dev->dp8390->physaddr[0];
break;
case 0x09:
retval = dev->dp8390->physaddr[1];
break;
case 0x0a:
retval = dev->dp8390->physaddr[2];
break;
case 0x0b:
retval = dev->dp8390->physaddr[3];
break;
case 0x0c:
retval = dev->dp8390->physaddr[4];
break;
case 0x0d:
retval = dev->dp8390->physaddr[5];
break;
case 0x0e:
retval = dev->board_chip;
break;
case 0x0f:
/*This has to return the byte that adds up to 0xFF*/
checksum = (dev->dp8390->physaddr[0] + dev->dp8390->physaddr[1] + dev->dp8390->physaddr[2] + dev->dp8390->physaddr[3] + dev->dp8390->physaddr[4] + dev->dp8390->physaddr[5] + dev->board_chip);
retval = 0xff - (checksum & 0xff);
break;
default:
break;
}
wdlog("%s: ASIC read addr=0x%02x, value=0x%04x\n",
dev->name, (unsigned) off, (unsigned) retval);
return retval;
}
static void
wd_set_ram(wd_t *dev)
{
uint32_t a13;
if ((dev->board_chip & 0xa0) == 0x20) {
a13 = dev->msr & 0x3f;
a13 <<= 13;
dev->ram_addr = a13 | (1 << 19);
mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size);
wdlog("%s: RAM address set to %08X\n", dev->name, dev->ram_addr);
}
if (dev->msr & WE_MSR_ENABLE_RAM)
mem_mapping_enable(&dev->ram_mapping);
else
mem_mapping_disable(&dev->ram_mapping);
wdlog("%s: RAM now %sabled\n", dev->name, (dev->msr & WE_MSR_ENABLE_RAM) ? "en" : "dis");
}
static void
wd_smc_write(wd_t *dev, uint32_t off, uint32_t val)
{
uint8_t old;
wdlog("%s: ASIC write addr=0x%02x, value=0x%04x\n",
dev->name, (unsigned) off, (unsigned) val);
if (off && (dev->board == WD8003E))
return;
switch (off) {
/* Bits 0-5: Bits 13-18 of memory address (writable?):
Windows 98 requires this to be preloaded with the initial
addresss to work correctly;
Bit 6: Enable memory if set;
Bit 7: Software reset if set. */
case 0x00: /* WD Control register */
old = dev->msr;
if (!(old & WE_MSR_SOFT_RESET) && (val & WE_MSR_SOFT_RESET)) {
wd_soft_reset(dev);
wdlog("WD80x3: Soft reset\n");
}
if ((dev->board_chip & 0xa0) == 0x20)
dev->msr = val;
else
dev->msr = (dev->msr & 0x3f) | (val & 0xc0);
if ((old &= 0x7f) != (val & 0x7f)) {
wd_set_ram(dev);
wdlog("WD80x3: Memory now %sabled (addr = %08X)\n", (val & WE_MSR_ENABLE_RAM) ? "en" : "dis", dev->ram_addr);
}
break;
/* Bit 1: 0 = 8-bit slot, 1 = 16-bit slot;
Bit 3: 0 = 8k RAM, 1 = 32k RAM (only on revision < 2). */
case 0x01:
if (dev->bit16 & 2)
dev->icr = (dev->icr & WE_ICR_16BIT_SLOT) | (val & WE_ICR_16BIT_SLOT);
else
dev->icr = val;
break;
/* Bit 5: Bit 0 of encoded IRQ;
Bit 6: Bit 1 of encoded IRQ;
Bit 7: Enable interrupts. */
case 0x04:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
dev->irr = (dev->irr & 0xe0) | (val & 0x1f);
break;
/* Bits 0-4: Bits 19-23 of memory address (writable?):
Windows 98 requires this to be preloaded with the initial
addresss to work correctly;
Bit 5: Enable software interrupt;
Bit 6: Enable 16-bit RAM for LAN if set;
Bit 7: Enable 16-bit RAM for host if set. */
case 0x05:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
dev->laar = val;
break;
/* Bits 0-4: Chip ID;
Bit 5: Software configuration is supported if present;
Bit 6: 0 = 16k RAM, 1 = 32k RAM. */
case 0x07:
if (dev->board_chip & WE_ID_SOFT_CONFIG)
dev->if_chip = val;
break;
default:
/* This is invalid, but happens under win95 device detection:
maybe some clone cards implement writing for some other
registers? */
wdlog("%s: ASIC write invalid address %04x, ignoring\n",
dev->name, (unsigned) off);
break;
}
}
static uint8_t
wd_read(uint16_t addr, void *priv, int len)
{
wd_t *dev = (wd_t *) priv;
uint8_t retval = 0;
int off = addr - dev->base_address;
wdlog("%s: read addr %x\n", dev->name, addr);
if (off == 0x10)
retval = dp8390_read_cr(dev->dp8390);
else if ((off >= 0x00) && (off <= 0x0f))
retval = wd_smc_read(dev, off);
else {
switch (dev->dp8390->CR.pgsel) {
case 0x00:
retval = dp8390_page0_read(dev->dp8390, off - 0x10, len);
break;
case 0x01:
retval = dp8390_page1_read(dev->dp8390, off - 0x10, len);
break;
case 0x02:
retval = dp8390_page2_read(dev->dp8390, off - 0x10, len);
break;
default:
wdlog("%s: unknown value of pgsel in read - %d\n",
dev->name, dev->dp8390->CR.pgsel);
break;
}
}
return retval;
}
static uint8_t
wd_readb(uint16_t addr, void *priv)
{
wd_t *dev = (wd_t *) priv;
return (wd_read(addr, dev, 1));
}
static uint16_t
wd_readw(uint16_t addr, void *priv)
{
wd_t *dev = (wd_t *) priv;
return (wd_read(addr, dev, 2));
}
static void
wd_write(uint16_t addr, uint8_t val, void *priv, unsigned int len)
{
wd_t *dev = (wd_t *) priv;
int off = addr - dev->base_address;
wdlog("%s: write addr %x, value %x\n", dev->name, addr, val);
if (off == 0x10)
dp8390_write_cr(dev->dp8390, val);
else if ((off >= 0x00) && (off <= 0x0f))
wd_smc_write(dev, off, val);
else {
switch (dev->dp8390->CR.pgsel) {
case 0x00:
dp8390_page0_write(dev->dp8390, off - 0x10, val, len);
break;
case 0x01:
dp8390_page1_write(dev->dp8390, off - 0x10, val, len);
break;
default:
wdlog("%s: unknown value of pgsel in write - %d\n",
dev->name, dev->dp8390->CR.pgsel);
break;
}
}
}
static void
wd_writeb(uint16_t addr, uint8_t val, void *priv)
{
wd_write(addr, val, priv, 1);
}
static void
wd_writew(uint16_t addr, uint16_t val, void *priv)
{
wd_write(addr, val & 0xff, priv, 2);
}
static void
wd_io_set(wd_t *dev, uint16_t addr)
{
if (dev->bit16 & 1) {
io_sethandler(addr, 0x20,
wd_readb, wd_readw, NULL,
wd_writeb, wd_writew, NULL, dev);
} else {
io_sethandler(addr, 0x20,
wd_readb, NULL, NULL,
wd_writeb, NULL, NULL, dev);
}
}
static void
wd_io_remove(wd_t *dev, uint16_t addr)
{
if (dev->bit16 & 1) {
io_removehandler(addr, 0x20,
wd_readb, wd_readw, NULL,
wd_writeb, wd_writew, NULL, dev);
} else {
io_removehandler(addr, 0x20,
wd_readb, NULL, NULL,
wd_writeb, NULL, NULL, dev);
}
}
static uint8_t
wd_mca_read(int port, void *priv)
{
const wd_t *dev = (wd_t *) priv;
return (dev->pos_regs[port & 7]);
}
#define MCA_6FC0_IRQS \
{ \
3, 4, 10, 15 \
}
static void
wd_mca_write(int port, uint8_t val, void *priv)
{
wd_t *dev = (wd_t *) priv;
int8_t irq[4] = MCA_6FC0_IRQS;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
/*
* The PS/2 Model 80 BIOS always enables a card if it finds one,
* even if no resources were assigned yet (because we only added
* the card, but have not run AutoConfig yet...)
*
* So, remove current address, if any.
*/
if (dev->base_address)
wd_io_remove(dev, dev->base_address);
dev->base_address = (dev->pos_regs[2] & 0xfe) << 4;
dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12;
dev->irq = irq[dev->pos_regs[5] & 0x03];
/* Initialize the device if fully configured. */
/* Register (new) I/O handler. */
if (dev->pos_regs[2] & 0x01)
wd_io_set(dev, dev->base_address);
mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size);
mem_mapping_disable(&dev->ram_mapping);
if ((dev->msr & WE_MSR_ENABLE_RAM) && (dev->pos_regs[2] & 0x01))
mem_mapping_enable(&dev->ram_mapping);
wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name,
dev->base_address, dev->irq, dev->ram_addr);
}
static void
wd_8013epa_mca_write(int port, uint8_t val, void *priv)
{
wd_t *dev = (wd_t *) priv;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
/*
* The PS/2 Model 80 BIOS always enables a card if it finds one,
* even if no resources were assigned yet (because we only added
* the card, but have not run AutoConfig yet...)
*
* So, remove current address, if any.
*/
if (dev->base_address)
wd_io_remove(dev, dev->base_address);
dev->base_address = 0x800 + ((dev->pos_regs[2] & 0xf0) << 8);
switch (dev->pos_regs[5] & 0x0c) {
case 0:
dev->irq = 3;
break;
case 4:
dev->irq = 4;
break;
case 8:
dev->irq = 10;
break;
case 0x0c:
dev->irq = 14;
break;
default:
break;
}
if (dev->pos_regs[3] & 0x10)
dev->ram_size = 0x4000;
else
dev->ram_size = 0x2000;
dev->ram_addr = ((dev->pos_regs[3] & 0x0f) << 13) + 0xc0000;
if (dev->pos_regs[3] & 0x80)
dev->ram_addr += 0xf00000;
/* Initialize the device if fully configured. */
/* Register (new) I/O handler. */
if (dev->pos_regs[2] & 0x01)
wd_io_set(dev, dev->base_address);
mem_mapping_set_addr(&dev->ram_mapping, dev->ram_addr, dev->ram_size);
mem_mapping_disable(&dev->ram_mapping);
if ((dev->msr & WE_MSR_ENABLE_RAM) && (dev->pos_regs[2] & 0x01))
mem_mapping_enable(&dev->ram_mapping);
wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name,
dev->base_address, dev->irq, dev->ram_addr);
}
static uint8_t
wd_mca_feedb(UNUSED(void *priv))
{
return 1;
}
static void *
wd_init(const device_t *info)
{
uint32_t mac;
wd_t *dev;
dev = malloc(sizeof(wd_t));
memset(dev, 0x00, sizeof(wd_t));
dev->name = info->name;
dev->board = info->local;
dev->maclocal[0] = 0x00; /* 00:00:C0 (WD/SMC OID) */
dev->maclocal[1] = 0x00;
dev->maclocal[2] = 0xC0;
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
dev->maclocal[3] = random_generate();
dev->maclocal[4] = random_generate();
dev->maclocal[5] = random_generate();
mac = (((int) dev->maclocal[3]) << 16);
mac |= (((int) dev->maclocal[4]) << 8);
mac |= ((int) dev->maclocal[5]);
device_set_config_mac("mac", mac);
} else {
dev->maclocal[3] = (mac >> 16) & 0xff;
dev->maclocal[4] = (mac >> 8) & 0xff;
dev->maclocal[5] = (mac & 0xff);
}
if ((dev->board == WD8003ETA) || (dev->board == WD8003EA) || dev->board == WD8013EPA) {
if (dev->board == WD8013EPA)
mca_add(wd_mca_read, wd_8013epa_mca_write, wd_mca_feedb, NULL, dev);
else
mca_add(wd_mca_read, wd_mca_write, wd_mca_feedb, NULL, dev);
} else {
dev->base_address = device_get_config_hex16("base");
dev->irq = device_get_config_int("irq");
dev->ram_addr = device_get_config_hex20("ram_addr");
}
dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++);
dev->dp8390->priv = dev;
dev->dp8390->interrupt = wd_interrupt;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
switch (dev->board) {
/* Ethernet, ISA, no interface chip, RAM 8k */
case WD8003E:
dev->board_chip = WE_TYPE_WD8003E;
dev->ram_size = 0x2000;
break;
/* Ethernet, ISA, 5x3 interface chip, RAM 8k or 32k */
case WD8003EB:
dev->board_chip = WE_TYPE_WD8003EB;
dev->if_chip = 1;
dev->ram_size = device_get_config_int("ram_size");
if (dev->ram_size == 0x8000)
dev->board_chip |= WE_ID_EXTRA_RAM;
/* Bit A19 is implicit 1. */
dev->msr |= (dev->ram_addr >> 13) & 0x3f;
break;
/* Ethernet, ISA, no interface chip, RAM 8k or 32k (8-bit slot) / 16k or 64k (16-bit slot) */
case WD8013EBT:
dev->board_chip = WE_TYPE_WD8013EBT;
dev->ram_size = device_get_config_int("ram_size");
if (dev->ram_size == 0x10000)
dev->board_chip |= WE_ID_EXTRA_RAM;
dev->bit16 = 2;
if (is286)
dev->bit16 |= 1;
else {
dev->bit16 |= 0;
if (dev->irq == 9)
dev->irq = 2;
dev->ram_size >>= 1; /* Half the RAM when in 8-bit slot. */
}
break;
/* Ethernet, MCA, 5x3 interface chip, RAM 16k */
case WD8003EA:
dev->board_chip = WE_ID_SOFT_CONFIG;
fallthrough;
/* Ethernet, MCA, no interface chip, RAM 16k */
case WD8003ETA:
dev->board_chip |= WE_TYPE_WD8013EBT | WE_ID_BUS_MCA;
dev->ram_size = 0x4000;
dev->pos_regs[0] = 0xC0;
dev->pos_regs[1] = 0x6F;
dev->bit16 = 3;
break;
case WD8013EPA:
dev->board_chip = WE_TYPE_WD8013EP | WE_ID_BUS_MCA;
dev->ram_size = device_get_config_int("ram_size");
dev->pos_regs[0] = 0xC8;
dev->pos_regs[1] = 0x61;
dev->bit16 = 3;
break;
default:
break;
}
dev->irr |= WE_IRR_ENABLE_IRQ;
dev->icr |= (dev->bit16 & 0x01);
dp8390_mem_alloc(dev->dp8390, 0x0000, dev->ram_size);
if (dev->base_address)
wd_io_set(dev, dev->base_address);
memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal));
wdlog("%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
dev->name, dev->base_address, dev->irq,
dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2],
dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]);
/* Reset the board. */
wd_reset(dev);
/* Map this system into the memory map. */
mem_mapping_add(&dev->ram_mapping, dev->ram_addr, dev->ram_size,
wd_ram_read, NULL, NULL,
wd_ram_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
mem_mapping_disable(&dev->ram_mapping);
/* Attach ourselves to the network module. */
dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
if (!(dev->board_chip & WE_ID_BUS_MCA)) {
wdlog("%s: attached IO=0x%X IRQ=%d, RAM addr=0x%06x\n", dev->name,
dev->base_address, dev->irq, dev->ram_addr);
}
return dev;
}
static void
wd_close(void *priv)
{
wd_t *dev = (wd_t *) priv;
wdlog("%s: closed\n", dev->name);
free(dev);
}
// clang-format off
static const device_config_t wd8003_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x240", .value = 0x240 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x380", .value = 0x380 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "" }
},
},
{
.name = "ram_addr",
.description = "RAM address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xD0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C800", .value = 0xC8000 },
{ .description = "CC00", .value = 0xCC000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D400", .value = 0xD4000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "DC00", .value = 0xDC000 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd8003eb_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x280,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x200", .value = 0x200 },
{ .description = "0x220", .value = 0x220 },
{ .description = "0x240", .value = 0x240 },
{ .description = "0x260", .value = 0x260 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2A0", .value = 0x2A0 },
{ .description = "0x2C0", .value = 0x2C0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x380", .value = 0x380 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2/9", .value = 9 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "" }
},
},
{
.name = "ram_addr",
.description = "RAM address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xD0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C000", .value = 0xC0000 },
{ .description = "C400", .value = 0xC4000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "CC00", .value = 0xCC000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D400", .value = 0xD4000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "DC00", .value = 0xDC000 },
{ .description = "" }
},
},
{
.name = "ram_size",
.description = "RAM size",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 8192,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "8 kB", .value = 8192 },
{ .description = "32 kB", .value = 32768 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
/* WD8013EBT configuration and defaults set according to this site:
path_to_url~marcolz/network/wd80x3.html#WD8013EBT */
static const device_config_t wd8013_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x280,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x200", .value = 0x200 },
{ .description = "0x220", .value = 0x220 },
{ .description = "0x240", .value = 0x240 },
{ .description = "0x260", .value = 0x260 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2A0", .value = 0x2A0 },
{ .description = "0x2C0", .value = 0x2C0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x380", .value = 0x380 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2/9", .value = 9 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 15", .value = 15 },
{ .description = "" }
},
},
{
.name = "ram_addr",
.description = "RAM address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xD0000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C000", .value = 0xC0000 },
{ .description = "C400", .value = 0xC4000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "CC00", .value = 0xCC000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D400", .value = 0xD4000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "DC00", .value = 0xDC000 },
{ .description = "" }
},
},
{
.name = "ram_size",
.description = "RAM size",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 16384,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "16 kB", .value = 16384 },
{ .description = "64 kB", .value = 65536 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t wd8013epa_config[] = {
{
.name = "ram_size",
.description = "Initial RAM size",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 16384,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "8 kB", .value = 8192 },
{ .description = "16 kB", .value = 16384 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t mca_mac_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t wd8003e_device = {
.name = "Western Digital WD8003E",
.internal_name = "wd8003e",
.flags = DEVICE_ISA,
.local = WD8003E,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd8003_config
};
const device_t wd8003eb_device = {
.name = "Western Digital WD8003EB",
.internal_name = "wd8003eb",
.flags = DEVICE_ISA,
.local = WD8003EB,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd8003eb_config
};
const device_t wd8013ebt_device = {
.name = "Western Digital WD8013EBT",
.internal_name = "wd8013ebt",
.flags = DEVICE_ISA,
.local = WD8013EBT,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd8013_config
};
const device_t wd8003eta_device = {
.name = "Western Digital WD8003ET/A",
.internal_name = "wd8003eta",
.flags = DEVICE_MCA,
.local = WD8003ETA,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = mca_mac_config
};
const device_t wd8003ea_device = {
.name = "Western Digital WD8003E/A",
.internal_name = "wd8003ea",
.flags = DEVICE_MCA,
.local = WD8003EA,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = mca_mac_config
};
const device_t wd8013epa_device = {
.name = "Western Digital WD8013EP/A",
.internal_name = "wd8013epa",
.flags = DEVICE_MCA,
.local = WD8013EPA,
.init = wd_init,
.close = wd_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = wd8013epa_config
};
``` | /content/code_sandbox/src/network/net_wd8003.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,038 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the following network controllers:
* - 3Com Etherlink II 3c503 (ISA 8-bit).
*
*
*
* Based on @(#)3c503.cpp Carl (MAME)
*
* Authors: TheCollector1995, <mariogplayer@gmail.com>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Carl, <unknown e-mail address>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/mem.h>
#include <86box/random.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_dp8390.h>
#include <86box/bswap.h>
#include <86box/plat_unused.h>
typedef struct threec503_t {
dp8390_t *dp8390;
mem_mapping_t ram_mapping;
uint32_t base_address;
int base_irq;
uint32_t bios_addr;
uint8_t maclocal[6]; /* configured MAC (local) address */
struct {
uint8_t pstr;
uint8_t pspr;
uint8_t dqtr;
uint8_t bcfr;
uint8_t pcfr;
uint8_t gacfr;
uint8_t ctrl;
uint8_t streg;
uint8_t idcfr;
uint16_t da;
uint32_t vptr;
uint8_t rfmsb;
uint8_t rflsb;
} regs;
int dma_channel;
} threec503_t;
#ifdef ENABLE_3COM503_LOG
int threec503_do_log = ENABLE_3COM503_LOG;
static void
threec503_log(const char *fmt, ...)
{
va_list ap;
if (threec503_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define threec503_log(fmt, ...)
#endif
static void
threec503_interrupt(void *priv, int set)
{
threec503_t *dev = (threec503_t *) priv;
switch (dev->base_irq) {
case 2:
dev->regs.idcfr = 0x10;
break;
case 3:
dev->regs.idcfr = 0x20;
break;
case 4:
dev->regs.idcfr = 0x40;
break;
case 5:
dev->regs.idcfr = 0x80;
break;
default:
break;
}
if (set)
picint(1 << dev->base_irq);
else
picintc(1 << dev->base_irq);
}
static void
threec503_ram_write(uint32_t addr, uint8_t val, void *priv)
{
threec503_t *dev = (threec503_t *) priv;
if ((addr & 0x3fff) >= 0x2000)
return;
dev->dp8390->mem[addr & 0x1fff] = val;
}
static uint8_t
threec503_ram_read(uint32_t addr, void *priv)
{
const threec503_t *dev = (threec503_t *) priv;
if ((addr & 0x3fff) >= 0x2000)
return 0xff;
return dev->dp8390->mem[addr & 0x1fff];
}
static void
threec503_set_drq(threec503_t *dev)
{
switch (dev->dma_channel) {
case 1:
dev->regs.idcfr = 1;
break;
case 2:
dev->regs.idcfr = 2;
break;
case 3:
dev->regs.idcfr = 4;
break;
default:
break;
}
}
/* reset - restore state to power-up, cancelling all i/o */
static void
threec503_reset(void *priv)
{
threec503_t *dev = (threec503_t *) priv;
#ifdef ENABLE_3COM503_LOG
threec503_log("3Com503: reset\n");
#endif
dp8390_reset(dev->dp8390);
memset(&dev->regs, 0, sizeof(dev->regs));
dev->regs.ctrl = 0x0a;
}
static uint8_t
threec503_nic_lo_read(uint16_t addr, void *priv)
{
threec503_t *dev = (threec503_t *) priv;
uint8_t retval = 0;
int off = addr - dev->base_address;
switch ((dev->regs.ctrl >> 2) & 3) {
case 0x00:
threec503_log("Read offset=%04x\n", off);
if (off == 0x00)
retval = dp8390_read_cr(dev->dp8390);
else
switch (dev->dp8390->CR.pgsel) {
case 0x00:
retval = dp8390_page0_read(dev->dp8390, off, 1);
break;
case 0x01:
retval = dp8390_page1_read(dev->dp8390, off, 1);
break;
case 0x02:
retval = dp8390_page2_read(dev->dp8390, off, 1);
break;
case 0x03:
retval = 0xff;
break;
default:
break;
}
break;
case 0x01:
retval = dev->dp8390->macaddr[off];
break;
case 0x02:
retval = dev->dp8390->macaddr[off + 0x10];
break;
case 0x03:
retval = 0xff;
break;
default:
break;
}
return retval;
}
static void
threec503_nic_lo_write(uint16_t addr, uint8_t val, void *priv)
{
threec503_t *dev = (threec503_t *) priv;
int off = addr - dev->base_address;
switch ((dev->regs.ctrl >> 2) & 3) {
case 0x00:
/* The high 16 bytes of i/o space are for the ne2000 asic -
the low 16 bytes are for the DS8390, with the current
page being selected by the PS0,PS1 registers in the
command register */
if (off == 0x00)
dp8390_write_cr(dev->dp8390, val);
else
switch (dev->dp8390->CR.pgsel) {
case 0x00:
dp8390_page0_write(dev->dp8390, off, val, 1);
break;
case 0x01:
dp8390_page1_write(dev->dp8390, off, val, 1);
break;
case 0x02:
dp8390_page2_write(dev->dp8390, off, val, 1);
break;
case 0x03:
break;
default:
break;
}
break;
case 0x01:
case 0x02:
case 0x03:
break;
default:
break;
}
threec503_log("3Com503: write addr %x, value %x\n", addr, val);
}
static uint8_t
threec503_nic_hi_read(uint16_t addr, void *priv)
{
threec503_t *dev = (threec503_t *) priv;
threec503_log("3Com503: Read GA address=%04x\n", addr);
switch (addr & 0x0f) {
case 0x00:
return dev->regs.pstr;
case 0x01:
return dev->regs.pspr;
case 0x02:
return dev->regs.dqtr;
case 0x03:
switch (dev->base_address) {
default:
case 0x300:
dev->regs.bcfr = 0x80;
break;
case 0x310:
dev->regs.bcfr = 0x40;
break;
case 0x330:
dev->regs.bcfr = 0x20;
break;
case 0x350:
dev->regs.bcfr = 0x10;
break;
case 0x250:
dev->regs.bcfr = 0x08;
break;
case 0x280:
dev->regs.bcfr = 0x04;
break;
case 0x2a0:
dev->regs.bcfr = 0x02;
break;
case 0x2e0:
dev->regs.bcfr = 0x01;
break;
}
return dev->regs.bcfr;
case 0x04:
switch (dev->bios_addr) {
case 0xdc000:
dev->regs.pcfr = 0x80;
break;
case 0xd8000:
dev->regs.pcfr = 0x40;
break;
case 0xcc000:
dev->regs.pcfr = 0x20;
break;
case 0xc8000:
dev->regs.pcfr = 0x10;
break;
default:
break;
}
return dev->regs.pcfr;
case 0x05:
return dev->regs.gacfr;
case 0x06:
return dev->regs.ctrl;
case 0x07:
return dev->regs.streg;
case 0x08:
return dev->regs.idcfr;
case 0x09:
return (dev->regs.da >> 8);
case 0x0a:
return (dev->regs.da & 0xff);
case 0x0b:
return (dev->regs.vptr >> 12) & 0xff;
case 0x0c:
return (dev->regs.vptr >> 4) & 0xff;
case 0x0d:
return (dev->regs.vptr & 0x0f) << 4;
case 0x0e:
case 0x0f:
if (!(dev->regs.ctrl & 0x80))
return 0xff;
threec503_set_drq(dev);
return dp8390_chipmem_read(dev->dp8390, dev->regs.da++, 1);
default:
break;
}
return 0;
}
static void
threec503_nic_hi_write(uint16_t addr, uint8_t val, void *priv)
{
threec503_t *dev = (threec503_t *) priv;
threec503_log("3Com503: Write GA address=%04x, val=%04x\n", addr, val);
switch (addr & 0x0f) {
case 0x00:
dev->regs.pstr = val;
break;
case 0x01:
dev->regs.pspr = val;
break;
case 0x02:
dev->regs.dqtr = val;
break;
case 0x05:
if ((dev->regs.gacfr & 0x0f) != (val & 0x0f)) {
switch (val & 0x0f) {
case 0: /*ROM mapping*/
/* FIXME: Implement this when a BIOS is found/generated. */
mem_mapping_disable(&dev->ram_mapping);
break;
case 9: /*RAM mapping*/
mem_mapping_enable(&dev->ram_mapping);
break;
default: /*No ROM mapping*/
mem_mapping_disable(&dev->ram_mapping);
break;
}
}
if (!(val & 0x80))
threec503_interrupt(dev, 1);
else
threec503_interrupt(dev, 0);
dev->regs.gacfr = val;
break;
case 0x06:
if (val & 1) {
threec503_reset(dev);
dev->dp8390->ISR.reset = 1;
dev->regs.ctrl = 0x0b;
return;
}
if ((val & 0x80) != (dev->regs.ctrl & 0x80)) {
if (val & 0x80)
dev->regs.streg |= 0x88;
else
dev->regs.streg &= ~0x88;
dev->regs.streg &= ~0x10;
}
dev->regs.ctrl = val;
break;
case 0x08:
switch (val & 0xf0) {
case 0x00:
case 0x10:
case 0x20:
case 0x40:
case 0x80:
dev->regs.idcfr = (dev->regs.idcfr & 0x0f) | (val & 0xf0);
break;
default:
threec503_log("Trying to set multiple IRQs: %02x\n", val);
break;
}
switch (val & 0x0f) {
case 0x00:
case 0x01:
case 0x02:
case 0x04:
dev->regs.idcfr = (dev->regs.idcfr & 0xf0) | (val & 0x0f);
break;
case 0x08:
break;
default:
threec503_log("Trying to set multiple DMA channels: %02x\n", val);
break;
}
break;
case 0x09:
dev->regs.da = (val << 8) | (dev->regs.da & 0xff);
break;
case 0x0a:
dev->regs.da = (dev->regs.da & 0xff00) | val;
break;
case 0x0b:
dev->regs.vptr = (val << 12) | (dev->regs.vptr & 0xfff);
break;
case 0x0c:
dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xff00f);
break;
case 0x0d:
dev->regs.vptr = (val << 4) | (dev->regs.vptr & 0xffff0);
break;
case 0x0e:
case 0x0f:
if (!(dev->regs.ctrl & 0x80))
return;
threec503_set_drq(dev);
dp8390_chipmem_write(dev->dp8390, dev->regs.da++, val, 1);
break;
default:
break;
}
}
static void
threec503_nic_ioset(threec503_t *dev, uint16_t addr)
{
io_sethandler(addr, 0x10,
threec503_nic_lo_read, NULL, NULL,
threec503_nic_lo_write, NULL, NULL, dev);
io_sethandler(addr + 0x400, 0x10,
threec503_nic_hi_read, NULL, NULL,
threec503_nic_hi_write, NULL, NULL, dev);
}
static void *
threec503_nic_init(UNUSED(const device_t *info))
{
uint32_t mac;
threec503_t *dev;
dev = malloc(sizeof(threec503_t));
memset(dev, 0x00, sizeof(threec503_t));
dev->maclocal[0] = 0x02; /* 02:60:8C (3Com OID) */
dev->maclocal[1] = 0x60;
dev->maclocal[2] = 0x8C;
dev->base_address = device_get_config_hex16("base");
dev->base_irq = device_get_config_int("irq");
dev->dma_channel = device_get_config_int("dma");
dev->bios_addr = device_get_config_hex20("bios_addr");
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/*
* Make this device known to the I/O system.
* PnP and PCI devices start with address spaces inactive.
*/
threec503_nic_ioset(dev, dev->base_address);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
dev->maclocal[3] = random_generate();
dev->maclocal[4] = random_generate();
dev->maclocal[5] = random_generate();
mac = (((int) dev->maclocal[3]) << 16);
mac |= (((int) dev->maclocal[4]) << 8);
mac |= ((int) dev->maclocal[5]);
device_set_config_mac("mac", mac);
} else {
dev->maclocal[3] = (mac >> 16) & 0xff;
dev->maclocal[4] = (mac >> 8) & 0xff;
dev->maclocal[5] = (mac & 0xff);
}
dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++);
dev->dp8390->priv = dev;
dev->dp8390->interrupt = threec503_interrupt;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000);
memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal));
threec503_log("I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
dev->base_address, dev->base_irq,
dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2],
dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]);
/* Reset the board. */
threec503_reset(dev);
/* Map this system into the memory map. */
mem_mapping_add(&dev->ram_mapping, dev->bios_addr, 0x4000,
threec503_ram_read, NULL, NULL,
threec503_ram_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
#if 0
mem_mapping_disable(&dev->ram_mapping);
#endif
dev->regs.gacfr = 0x09; /* Start with RAM mapping enabled. */
/* Attach ourselves to the network module. */
dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
return dev;
}
static void
threec503_nic_close(void *priv)
{
threec503_t *dev = (threec503_t *) priv;
#ifdef ENABLE_3COM503_LOG
threec503_log("3Com503: closed\n");
#endif
free(dev);
}
static const device_config_t threec503_config[] = {
// clang-format off
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0x250", .value = 0x250 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2a0", .value = 0x2a0 },
{ .description = "0x2e0", .value = 0x2e0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x310", .value = 0x310 },
{ .description = "0x330", .value = 0x330 },
{ .description = "0x350", .value = 0x350 },
{ .description = "", .value = 0 }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "", .value = 0 }
},
},
{
.name = "dma",
.description = "DMA",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "DMA 1", .value = 1 },
{ .description = "DMA 2", .value = 2 },
{ .description = "DMA 3", .value = 3 },
{ .description = "", .value = 0 }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "", .value = 0 }
},
},
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xCC000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "DC00", .value = 0xDC000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "CC00", .value = 0xCC000 },
{ .description = "", .value = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format off
};
const device_t threec503_device = {
.name = "3Com EtherLink II",
.internal_name = "3c503",
.flags = DEVICE_ISA,
.local = 0,
.init = threec503_nic_init,
.close = threec503_nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = threec503_config
};
``` | /content/code_sandbox/src/network/net_3c503.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,483 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the following network controllers:
* - Novell NE1000 (ISA 8-bit);
* - Novell NE2000 (ISA 16-bit);
* - Novell NE/2 compatible (NetWorth Inc. Ethernext/MC) (MCA 16-bit);
* - Realtek RTL8019AS (ISA 16-bit, PnP);
* - Realtek RTL8029AS (PCI).
*
*
*
* Based on @(#)ne2k.cc v1.56.2.1 2004/02/02 22:37:22 cbothamy
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* TheCollector1995, <mariogplayer@gmail.com>
* Miran Grca, <mgrca8@gmail.com>
* Peter Grehan, <grehan@iprg.nokia.com>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <time.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/mca.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/random.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_dp8390.h>
#include <86box/net_ne2000.h>
#include <86box/bswap.h>
#include <86box/isapnp.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
/* ROM BIOS file paths. */
#define ROM_PATH_NE1000 "roms/network/ne1000/ne1000.rom"
#define ROM_PATH_NE2000 "roms/network/ne2000/ne2000.rom"
#define ROM_PATH_RTL8019 "roms/network/rtl8019as/rtl8019as.rom"
#define ROM_PATH_RTL8029 "roms/network/rtl8029as/rtl8029as.rom"
/* PCI info. */
#define PCI_VENDID 0x10ec /* Realtek, Inc */
#define PCI_DEVID 0x8029 /* RTL8029AS */
#define PCI_REGSIZE 256 /* size of PCI space */
typedef struct nic_t {
dp8390_t *dp8390;
const char *name;
uint8_t pnp_csnsav;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pad;
/* RTL8019AS/RTL8029AS registers */
uint8_t config0;
uint8_t config2;
uint8_t config3;
uint8_t _9346cr;
uint8_t pci_regs[PCI_REGSIZE];
uint8_t eeprom[128]; /* for RTL8029AS */
uint8_t maclocal[6]; /* configured MAC (local) address */
/* POS registers, MCA boards only */
uint8_t pos_regs[8];
int board;
int is_pci;
int is_mca;
int is_8bit;
int base_irq;
int has_bios;
uint32_t base_address;
uint32_t bios_addr;
uint32_t bios_size;
uint32_t bios_mask;
bar_t pci_bar[2];
rom_t bios_rom;
void *pnp_card;
} nic_t;
#ifdef ENABLE_NE2K_LOG
int ne2k_do_log = ENABLE_NE2K_LOG;
static void
nelog(int lvl, const char *fmt, ...)
{
va_list ap;
if (ne2k_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define nelog(lvl, fmt, ...)
#endif
static void
nic_interrupt(void *priv, int set)
{
nic_t *dev = (nic_t *) priv;
if (dev->is_pci) {
if (set)
pci_set_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
else
pci_clear_irq(dev->pci_slot, PCI_INTA, &dev->irq_state);
} else {
if (set)
picint(1 << dev->base_irq);
else
picintc(1 << dev->base_irq);
}
}
/* reset - restore state to power-up, cancelling all i/o */
static void
nic_reset(void *priv)
{
nic_t *dev = (nic_t *) priv;
nelog(1, "%s: reset\n", dev->name);
dp8390_reset(dev->dp8390);
}
static void
nic_soft_reset(void *priv)
{
nic_t *dev = (nic_t *) priv;
dp8390_soft_reset(dev->dp8390);
}
/*
* Access the ASIC I/O space.
*
* This is the high 16 bytes of i/o space (the lower 16 bytes
* is for the DS8390). Only two locations are used: offset 0,
* which is used for data transfer, and offset 0x0f, which is
* used to reset the device.
*
* The data transfer port is used to as 'external' DMA to the
* DS8390. The chip has to have the DMA registers set up, and
* after that, insw/outsw instructions can be used to move
* the appropriate number of bytes to/from the device.
*/
static uint32_t
asic_read(nic_t *dev, uint32_t off, unsigned int len)
{
uint32_t retval = 0;
switch (off) {
case 0x00: /* Data register */
/* A read remote-DMA command must have been issued,
and the source-address and length registers must
have been initialised. */
if (len > dev->dp8390->remote_bytes) {
nelog(3, "%s: DMA read underrun iolen=%d remote_bytes=%d\n",
dev->name, len, dev->dp8390->remote_bytes);
}
nelog(3, "%s: DMA read: addr=%4x remote_bytes=%d\n",
dev->name, dev->dp8390->remote_dma, dev->dp8390->remote_bytes);
retval = dp8390_chipmem_read(dev->dp8390, dev->dp8390->remote_dma, len);
/* The 8390 bumps the address and decreases the byte count
by the selected word size after every access, not by
the amount of data requested by the host (io_len). */
if (len == 4) {
dev->dp8390->remote_dma += len;
} else {
dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1);
}
if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8) {
dev->dp8390->remote_dma = dev->dp8390->page_start << 8;
}
/* keep s.remote_bytes from underflowing */
if (dev->dp8390->remote_bytes > dev->dp8390->DCR.wdsize) {
if (len == 4) {
dev->dp8390->remote_bytes -= len;
} else {
dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1);
}
} else {
dev->dp8390->remote_bytes = 0;
}
/* If all bytes have been written, signal remote-DMA complete */
if (dev->dp8390->remote_bytes == 0) {
dev->dp8390->ISR.rdma_done = 1;
if (dev->dp8390->IMR.rdma_inte)
nic_interrupt(dev, 1);
}
break;
case 0x0f: /* Reset register */
nic_soft_reset(dev);
break;
default:
nelog(3, "%s: ASIC read invalid address %04x\n",
dev->name, (unsigned) off);
break;
}
return retval;
}
static void
asic_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len)
{
nelog(3, "%s: ASIC write addr=0x%02x, value=0x%04x\n",
dev->name, (unsigned) off, (unsigned) val);
switch (off) {
case 0x00: /* Data register - see asic_read for a description */
if ((len > 1) && (dev->dp8390->DCR.wdsize == 0)) {
nelog(3, "%s: DMA write length %d on byte mode operation\n",
dev->name, len);
break;
}
if (dev->dp8390->remote_bytes == 0)
nelog(3, "%s: DMA write, byte count 0\n", dev->name);
dp8390_chipmem_write(dev->dp8390, dev->dp8390->remote_dma, val, len);
if (len == 4)
dev->dp8390->remote_dma += len;
else
dev->dp8390->remote_dma += (dev->dp8390->DCR.wdsize + 1);
if (dev->dp8390->remote_dma == dev->dp8390->page_stop << 8)
dev->dp8390->remote_dma = dev->dp8390->page_start << 8;
if (len == 4)
dev->dp8390->remote_bytes -= len;
else
dev->dp8390->remote_bytes -= (dev->dp8390->DCR.wdsize + 1);
if (dev->dp8390->remote_bytes > dev->dp8390->mem_size)
dev->dp8390->remote_bytes = 0;
/* If all bytes have been written, signal remote-DMA complete */
if (dev->dp8390->remote_bytes == 0) {
dev->dp8390->ISR.rdma_done = 1;
if (dev->dp8390->IMR.rdma_inte)
nic_interrupt(dev, 1);
}
break;
case 0x0f: /* Reset register */
/* end of reset pulse */
break;
default: /* this is invalid, but happens under win95 device detection */
nelog(3, "%s: ASIC write invalid address %04x, ignoring\n",
dev->name, (unsigned) off);
break;
}
}
/* Writes to this page are illegal. */
static uint32_t
page3_read(nic_t *dev, uint32_t off, UNUSED(unsigned int len))
{
if (dev->board >= NE2K_RTL8019AS)
switch (off) {
case 0x1: /* 9346CR */
return (dev->_9346cr);
case 0x3: /* CONFIG0 */
return 0x00; /* Cable not BNC */
case 0x5: /* CONFIG2 */
return (dev->config2 & 0xe0);
case 0x6: /* CONFIG3 */
return (dev->config3 & 0x46);
case 0x8: /* CSNSAV */
return ((dev->board == NE2K_RTL8019AS) ? dev->pnp_csnsav : 0x00);
case 0xe: /* 8029ASID0 */
if (dev->board == NE2K_RTL8029AS)
return 0x29;
break;
case 0xf: /* 8029ASID1 */
if (dev->board == NE2K_RTL8029AS)
return 0x80;
break;
default:
break;
}
nelog(3, "%s: Page3 read register 0x%02x attempted\n", dev->name, off);
return 0x00;
}
static void
page3_write(nic_t *dev, uint32_t off, uint32_t val, UNUSED(unsigned len))
{
if (dev->board >= NE2K_RTL8019AS) {
nelog(3, "%s: Page2 write to register 0x%02x, len=%u, value=0x%04x\n",
dev->name, off, len, val);
switch (off) {
case 0x01: /* 9346CR */
dev->_9346cr = (val & 0xfe);
break;
case 0x05: /* CONFIG2 */
dev->config2 = (val & 0xe0);
break;
case 0x06: /* CONFIG3 */
dev->config3 = (val & 0x46);
break;
case 0x09: /* HLTCLK */
break;
default:
nelog(3, "%s: Page3 write to reserved register 0x%02x\n",
dev->name, off);
break;
}
} else
nelog(3, "%s: Page3 write register 0x%02x attempted\n", dev->name, off);
}
static uint32_t
nic_read(nic_t *dev, uint32_t addr, unsigned len)
{
uint32_t retval = 0;
int off = addr - dev->base_address;
nelog(3, "%s: read addr %x, len %d\n", dev->name, addr, len);
if (off >= 0x10)
retval = asic_read(dev, off - 0x10, len);
else if (off == 0x00)
retval = dp8390_read_cr(dev->dp8390);
else
switch (dev->dp8390->CR.pgsel) {
case 0x00:
retval = dp8390_page0_read(dev->dp8390, off, len);
break;
case 0x01:
retval = dp8390_page1_read(dev->dp8390, off, len);
break;
case 0x02:
retval = dp8390_page2_read(dev->dp8390, off, len);
break;
case 0x03:
retval = page3_read(dev, off, len);
break;
default:
nelog(3, "%s: unknown value of pgsel in read - %d\n",
dev->name, dev->dp8390->CR.pgsel);
break;
}
return retval;
}
static uint8_t
nic_readb(uint16_t addr, void *priv)
{
return (nic_read((nic_t *) priv, addr, 1));
}
static uint16_t
nic_readw(uint16_t addr, void *priv)
{
return (nic_read((nic_t *) priv, addr, 2));
}
static uint32_t
nic_readl(uint16_t addr, void *priv)
{
return (nic_read((nic_t *) priv, addr, 4));
}
static void
nic_write(nic_t *dev, uint32_t addr, uint32_t val, unsigned len)
{
int off = addr - dev->base_address;
nelog(3, "%s: write addr %x, value %x len %d\n", dev->name, addr, val, len);
/* The high 16 bytes of i/o space are for the ne2000 asic -
the low 16 bytes are for the DS8390, with the current
page being selected by the PS0,PS1 registers in the
command register */
if (off >= 0x10)
asic_write(dev, off - 0x10, val, len);
else if (off == 0x00)
dp8390_write_cr(dev->dp8390, val);
else
switch (dev->dp8390->CR.pgsel) {
case 0x00:
dp8390_page0_write(dev->dp8390, off, val, len);
break;
case 0x01:
dp8390_page1_write(dev->dp8390, off, val, len);
break;
case 0x02:
dp8390_page2_write(dev->dp8390, off, val, len);
break;
case 0x03:
page3_write(dev, off, val, len);
break;
default:
nelog(3, "%s: unknown value of pgsel in write - %d\n",
dev->name, dev->dp8390->CR.pgsel);
break;
}
}
static void
nic_writeb(uint16_t addr, uint8_t val, void *priv)
{
nic_write((nic_t *) priv, addr, val, 1);
}
static void
nic_writew(uint16_t addr, uint16_t val, void *priv)
{
nic_write((nic_t *) priv, addr, val, 2);
}
static void
nic_writel(uint16_t addr, uint32_t val, void *priv)
{
nic_write((nic_t *) priv, addr, val, 4);
}
static void nic_ioset(nic_t *dev, uint16_t addr);
static void nic_ioremove(nic_t *dev, uint16_t addr);
static void
nic_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
if (ld)
return;
nic_t *dev = (nic_t *) priv;
if (dev->base_address) {
nic_ioremove(dev, dev->base_address);
dev->base_address = 0;
}
dev->base_address = config->io[0].base;
dev->base_irq = config->irq[0].irq;
if (config->activate && (dev->base_address != ISAPNP_IO_DISABLED))
nic_ioset(dev, dev->base_address);
}
static void
nic_pnp_csn_changed(uint8_t csn, void *priv)
{
nic_t *dev = (nic_t *) priv;
dev->pnp_csnsav = csn;
}
static uint8_t
nic_pnp_read_vendor_reg(uint8_t ld, uint8_t reg, void *priv)
{
if (ld != 0)
return 0x00;
const nic_t *dev = (nic_t *) priv;
switch (reg) {
case 0xF0:
return dev->config0;
case 0xF2:
return dev->config2;
case 0xF3:
return dev->config3;
case 0xF5:
return dev->pnp_csnsav;
default:
break;
}
return 0x00;
}
static void
nic_pnp_write_vendor_reg(uint8_t ld, uint8_t reg, uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
if ((ld == 0) && (reg == 0xf6) && (val & 0x04)) {
uint8_t csn = dev->pnp_csnsav;
isapnp_set_csn(dev->pnp_card, 0);
dev->pnp_csnsav = csn;
}
}
static void
nic_ioset(nic_t *dev, uint16_t addr)
{
if (dev->is_pci) {
io_sethandler(addr, 32,
nic_readb, nic_readw, nic_readl,
nic_writeb, nic_writew, nic_writel, dev);
} else {
io_sethandler(addr, 16,
nic_readb, NULL, NULL,
nic_writeb, NULL, NULL, dev);
if (dev->is_8bit) {
io_sethandler(addr + 16, 16,
nic_readb, NULL, NULL,
nic_writeb, NULL, NULL, dev);
} else {
io_sethandler(addr + 16, 16,
nic_readb, nic_readw, NULL,
nic_writeb, nic_writew, NULL, dev);
}
}
}
static void
nic_ioremove(nic_t *dev, uint16_t addr)
{
if (dev->is_pci) {
io_removehandler(addr, 32,
nic_readb, nic_readw, nic_readl,
nic_writeb, nic_writew, nic_writel, dev);
} else {
io_removehandler(addr, 16,
nic_readb, NULL, NULL,
nic_writeb, NULL, NULL, dev);
if (dev->is_8bit) {
io_removehandler(addr + 16, 16,
nic_readb, NULL, NULL,
nic_writeb, NULL, NULL, dev);
} else {
io_removehandler(addr + 16, 16,
nic_readb, nic_readw, NULL,
nic_writeb, nic_writew, NULL, dev);
}
}
}
static void
nic_update_bios(nic_t *dev)
{
int reg_bios_enable;
reg_bios_enable = 1;
if (!dev->has_bios)
return;
if (dev->is_pci)
reg_bios_enable = dev->pci_bar[1].addr_regs[0] & 0x01;
/* PCI BIOS stuff, just enable_disable. */
if (reg_bios_enable) {
mem_mapping_set_addr(&dev->bios_rom.mapping,
dev->bios_addr, dev->bios_size);
nelog(1, "%s: BIOS now at: %06X\n", dev->name, dev->bios_addr);
} else {
nelog(1, "%s: BIOS disabled\n", dev->name);
mem_mapping_disable(&dev->bios_rom.mapping);
}
}
static uint8_t
nic_pci_read(UNUSED(int func), int addr, void *priv)
{
const nic_t *dev = (nic_t *) priv;
uint8_t ret = 0x00;
switch (addr) {
case 0x00: /* PCI_VID_LO */
case 0x01: /* PCI_VID_HI */
ret = dev->pci_regs[addr];
break;
case 0x02: /* PCI_DID_LO */
case 0x03: /* PCI_DID_HI */
ret = dev->pci_regs[addr];
break;
case 0x04: /* PCI_COMMAND_LO */
case 0x05: /* PCI_COMMAND_HI */
ret = dev->pci_regs[addr];
break;
case 0x06: /* PCI_STATUS_LO */
case 0x07: /* PCI_STATUS_HI */
ret = dev->pci_regs[addr];
break;
case 0x08: /* PCI_REVID */
ret = 0x00; /* Rev. 00 */
break;
case 0x09: /* PCI_PIFR */
ret = 0x00; /* Rev. 00 */
break;
case 0x0A: /* PCI_SCR */
ret = dev->pci_regs[addr];
break;
case 0x0B: /* PCI_BCR */
ret = dev->pci_regs[addr];
break;
case 0x10: /* PCI_BAR 7:5 */
ret = (dev->pci_bar[0].addr_regs[0] & 0xe0) | 0x01;
break;
case 0x11: /* PCI_BAR 15:8 */
ret = dev->pci_bar[0].addr_regs[1];
break;
case 0x12: /* PCI_BAR 23:16 */
ret = dev->pci_bar[0].addr_regs[2];
break;
case 0x13: /* PCI_BAR 31:24 */
ret = dev->pci_bar[0].addr_regs[3];
break;
case 0x2C: /* PCI_SVID_LO */
case 0x2D: /* PCI_SVID_HI */
ret = dev->pci_regs[addr];
break;
case 0x2E: /* PCI_SID_LO */
case 0x2F: /* PCI_SID_HI */
ret = dev->pci_regs[addr];
break;
case 0x30: /* PCI_ROMBAR */
ret = dev->pci_bar[1].addr_regs[0] & 0x01;
break;
case 0x31: /* PCI_ROMBAR 15:11 */
ret = dev->pci_bar[1].addr_regs[1] & 0x80;
break;
case 0x32: /* PCI_ROMBAR 23:16 */
ret = dev->pci_bar[1].addr_regs[2];
break;
case 0x33: /* PCI_ROMBAR 31:24 */
ret = dev->pci_bar[1].addr_regs[3];
break;
case 0x3C: /* PCI_ILR */
ret = dev->pci_regs[addr];
break;
case 0x3D: /* PCI_IPR */
ret = dev->pci_regs[addr];
break;
default:
break;
}
nelog(2, "%s: PCI_Read(%d, %04x) = %02x\n", dev->name, func, addr, ret);
return ret;
}
static void
nic_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint8_t valxor;
nelog(2, "%s: PCI_Write(%d, %04x, %02x)\n", dev->name, func, addr, val);
switch (addr) {
case 0x04: /* PCI_COMMAND_LO */
valxor = (val & 0x03) ^ dev->pci_regs[addr];
if (valxor & PCI_COMMAND_IO) {
nic_ioremove(dev, dev->base_address);
if ((dev->base_address != 0) && (val & PCI_COMMAND_IO)) {
nic_ioset(dev, dev->base_address);
}
}
dev->pci_regs[addr] = val & 0x03;
break;
case 0x10: /* PCI_BAR */
val &= 0xe0; /* 0xe0 acc to RTL DS */
val |= 0x01; /* re-enable IOIN bit */
fallthrough;
case 0x11: /* PCI_BAR */
case 0x12: /* PCI_BAR */
case 0x13: /* PCI_BAR */
/* Remove old I/O. */
nic_ioremove(dev, dev->base_address);
/* Set new I/O as per PCI request. */
dev->pci_bar[0].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
dev->base_address = dev->pci_bar[0].addr & 0xffe0;
/* Log the new base. */
nelog(1, "%s: PCI: new I/O base is %04X\n",
dev->name, dev->base_address);
/* We're done, so get out of the here. */
if (dev->pci_regs[4] & PCI_COMMAND_IO) {
if (dev->base_address != 0) {
nic_ioset(dev, dev->base_address);
}
}
break;
case 0x30: /* PCI_ROMBAR */
case 0x31: /* PCI_ROMBAR */
case 0x32: /* PCI_ROMBAR */
case 0x33: /* PCI_ROMBAR */
dev->pci_bar[1].addr_regs[addr & 3] = val;
#if 0
dev->pci_bar[1].addr_regs[1] &= dev->bios_mask;
#endif
dev->pci_bar[1].addr &= 0xffff8001;
dev->bios_addr = dev->pci_bar[1].addr & 0xffff8000;
nic_update_bios(dev);
return;
case 0x3C: /* PCI_ILR */
nelog(1, "%s: IRQ now: %i\n", dev->name, val);
dev->base_irq = val;
dev->pci_regs[addr] = dev->base_irq;
return;
default:
break;
}
}
static void
nic_rom_init(nic_t *dev, char *s)
{
uint32_t temp;
FILE *fp;
if (s == NULL)
return;
if (dev->bios_addr == 0)
return;
if ((fp = rom_fopen(s, "rb")) != NULL) {
fseek(fp, 0L, SEEK_END);
temp = ftell(fp);
fclose(fp);
dev->bios_size = 0x10000;
if (temp <= 0x8000)
dev->bios_size = 0x8000;
if (temp <= 0x4000)
dev->bios_size = 0x4000;
if (temp <= 0x2000)
dev->bios_size = 0x2000;
dev->bios_mask = (dev->bios_size >> 8) & 0xff;
dev->bios_mask = (0x100 - dev->bios_mask) & 0xff;
} else {
dev->bios_addr = 0x00000;
dev->bios_size = 0;
return;
}
/* Create a memory mapping for the space. */
rom_init(&dev->bios_rom, s, dev->bios_addr,
dev->bios_size, dev->bios_size - 1, 0, MEM_MAPPING_EXTERNAL);
nelog(1, "%s: BIOS configured at %06lX (size %ld)\n",
dev->name, dev->bios_addr, dev->bios_size);
}
static uint8_t
nic_mca_read(int port, void *priv)
{
const nic_t *dev = (nic_t *) priv;
return (dev->pos_regs[port & 7]);
}
#define MCA_611F_IO_PORTS \
{ \
0x300, 0x340, 0x320, 0x360, 0x1300, 0x1340, \
0x1320, 0x1360 \
}
#define MCA_611F_IRQS \
{ \
2, 3, 4, 5, 10, 11, 12, 15 \
}
static void
nic_mca_write(int port, uint8_t val, void *priv)
{
nic_t *dev = (nic_t *) priv;
uint16_t base[] = MCA_611F_IO_PORTS;
int8_t irq[] = MCA_611F_IRQS;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
nic_ioremove(dev, dev->base_address);
/* This is always necessary so that the old handler doesn't remain. */
/* Get the new assigned I/O base address. */
dev->base_address = base[(dev->pos_regs[2] & 0xE0) >> 4];
/* Save the new IRQ values. */
dev->base_irq = irq[(dev->pos_regs[2] & 0xE) >> 1];
dev->bios_addr = 0x0000;
dev->has_bios = 0;
/*
* The PS/2 Model 80 BIOS always enables a card if it finds one,
* even if no resources were assigned yet (because we only added
* the card, but have not run AutoConfig yet...)
*
* So, remove current address, if any.
*/
/* Initialize the device if fully configured. */
if (dev->pos_regs[2] & 0x01) {
/* Card enabled; register (new) I/O handler. */
nic_ioset(dev, dev->base_address);
nic_reset(dev);
nelog(2, "EtherNext/MC: Port=%04x, IRQ=%d\n", dev->base_address, dev->base_irq);
}
}
static uint8_t
nic_mca_feedb(void *priv)
{
const nic_t *dev = (nic_t *) priv;
return (dev->pos_regs[2] & 0x01);
}
static void *
nic_init(const device_t *info)
{
uint32_t mac;
char *rom;
nic_t *dev;
dev = malloc(sizeof(nic_t));
memset(dev, 0x00, sizeof(nic_t));
dev->name = info->name;
dev->board = info->local;
rom = NULL;
if (dev->board >= NE2K_RTL8019AS) {
dev->base_address = 0x340;
dev->base_irq = 12;
if (dev->board == NE2K_RTL8029AS) {
dev->bios_addr = 0xD0000;
dev->has_bios = device_get_config_int("bios");
} else {
dev->bios_addr = 0x00000;
dev->has_bios = 0;
}
} else {
if (dev->board != NE2K_ETHERNEXT_MC) {
dev->base_address = device_get_config_hex16("base");
dev->base_irq = device_get_config_int("irq");
if ((dev->board == NE2K_NE2000) || (dev->board == NE2K_NE2000_COMPAT) ||
(dev->board == NE2K_NE2000_COMPAT_8BIT) ) {
dev->bios_addr = device_get_config_hex20("bios_addr");
dev->has_bios = !!dev->bios_addr;
} else {
dev->bios_addr = 0x00000;
dev->has_bios = 0;
}
} else {
mca_add(nic_mca_read, nic_mca_write, nic_mca_feedb, NULL, dev);
}
}
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
dev->maclocal[3] = random_generate();
dev->maclocal[4] = random_generate();
dev->maclocal[5] = random_generate();
mac = (((int) dev->maclocal[3]) << 16);
mac |= (((int) dev->maclocal[4]) << 8);
mac |= ((int) dev->maclocal[5]);
device_set_config_mac("mac", mac);
} else {
dev->maclocal[3] = (mac >> 16) & 0xff;
dev->maclocal[4] = (mac >> 8) & 0xff;
dev->maclocal[5] = (mac & 0xff);
}
dev->dp8390 = device_add_inst(&dp8390_device, dp3890_inst++);
dev->dp8390->priv = dev;
dev->dp8390->interrupt = nic_interrupt;
switch (dev->board) {
case NE2K_NE1000:
dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */
dev->maclocal[1] = 0x00;
dev->maclocal[2] = 0xD8;
dev->is_8bit = 1;
rom = NULL;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000);
break;
case NE2K_NE1000_COMPAT:
dev->maclocal[0] = 0x00; /* 00:86:B0 (86Box OID) */
dev->maclocal[1] = 0x86;
dev->maclocal[2] = 0xB0;
dev->is_8bit = 1;
rom = NULL;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000);
break;
case NE2K_NE2000:
dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */
dev->maclocal[1] = 0x00;
dev->maclocal[2] = 0xD8;
rom = ROM_PATH_NE2000;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000);
break;
case NE2K_NE2000_COMPAT:
dev->maclocal[0] = 0x00; /* 00:86:B0 (86Box OID) */
dev->maclocal[1] = 0x86;
dev->maclocal[2] = 0xB0;
rom = ROM_PATH_NE2000;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000);
break;
case NE2K_NE2000_COMPAT_8BIT:
dev->maclocal[0] = 0x00; /* 00:86:B0 (86Box OID) */
dev->maclocal[1] = 0x86;
dev->maclocal[2] = 0xB0;
dev->is_8bit = 1;
rom = ROM_PATH_NE2000;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000);
break;
case NE2K_ETHERNEXT_MC:
dev->maclocal[0] = 0x00; /* 00:00:D8 (Networth Inc. OID) */
dev->maclocal[1] = 0x00;
dev->maclocal[2] = 0x79;
dev->pos_regs[0] = 0x1F;
dev->pos_regs[1] = 0x61;
rom = NULL;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000);
break;
case NE2K_DE220P:
dev->maclocal[0] = 0x00; /* 00:80:C8 (D-Link OID) */
dev->maclocal[1] = 0x80;
dev->maclocal[2] = 0xC8;
rom = NULL;
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CLEAR_IRQ);
dp8390_set_id(dev->dp8390, 0x50, 0x70);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x8000);
break;
case NE2K_RTL8019AS:
case NE2K_RTL8029AS:
dev->is_pci = (dev->board == NE2K_RTL8029AS) ? 1 : 0;
dev->maclocal[0] = 0x00; /* 00:E0:4C (Realtek OID) */
dev->maclocal[1] = 0xE0;
dev->maclocal[2] = 0x4C;
rom = (dev->board == NE2K_RTL8019AS) ? ROM_PATH_RTL8019 : ROM_PATH_RTL8029;
if (dev->is_pci)
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC);
else
dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CLEAR_IRQ);
dp8390_set_id(dev->dp8390, 0x50, (dev->board == NE2K_RTL8019AS) ? 0x70 : 0x43);
dp8390_mem_alloc(dev->dp8390, 0x4000, 0x8000);
break;
default:
break;
}
memcpy(dev->dp8390->physaddr, dev->maclocal, sizeof(dev->maclocal));
nelog(2, "%s: I/O=%04x, IRQ=%d, MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
dev->name, dev->base_address, dev->base_irq,
dev->dp8390->physaddr[0], dev->dp8390->physaddr[1], dev->dp8390->physaddr[2],
dev->dp8390->physaddr[3], dev->dp8390->physaddr[4], dev->dp8390->physaddr[5]);
/*
* Make this device known to the I/O system.
* PnP and PCI devices start with address spaces inactive.
*/
if ((dev->board < NE2K_RTL8019AS) && (dev->board != NE2K_ETHERNEXT_MC))
nic_ioset(dev, dev->base_address);
/* Set up our BIOS ROM space, if any. */
nic_rom_init(dev, rom);
if (dev->board >= NE2K_RTL8019AS) {
if (dev->is_pci) {
/*
* Configure the PCI space registers.
*
* We do this here, so the I/O routines are generic.
*/
memset(dev->pci_regs, 0, PCI_REGSIZE);
dev->pci_regs[0x00] = (PCI_VENDID & 0xff);
dev->pci_regs[0x01] = (PCI_VENDID >> 8);
dev->pci_regs[0x02] = (PCI_DEVID & 0xff);
dev->pci_regs[0x03] = (PCI_DEVID >> 8);
dev->pci_regs[0x04] = 0x03; /* IOEN */
dev->pci_regs[0x05] = 0x00;
dev->pci_regs[0x07] = 0x02; /* DST0, medium devsel */
dev->pci_regs[0x09] = 0x00; /* PIFR */
dev->pci_regs[0x0B] = 0x02; /* BCR: Network Controller */
dev->pci_regs[0x0A] = 0x00; /* SCR: Ethernet */
dev->pci_regs[0x2C] = (PCI_VENDID & 0xff);
dev->pci_regs[0x2D] = (PCI_VENDID >> 8);
dev->pci_regs[0x2E] = (PCI_DEVID & 0xff);
dev->pci_regs[0x2F] = (PCI_DEVID >> 8);
dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */
/* Enable our address space in PCI. */
dev->pci_bar[0].addr_regs[0] = 0x01;
/* Enable our BIOS space in PCI, if needed. */
if (dev->bios_addr > 0) {
dev->pci_bar[1].addr = 0xFFFF8000;
dev->pci_bar[1].addr_regs[1] = dev->bios_mask;
} else {
dev->pci_bar[1].addr = 0;
dev->bios_size = 0;
}
mem_mapping_disable(&dev->bios_rom.mapping);
/* Add device to the PCI bus, keep its slot number. */
pci_add_card(PCI_ADD_NORMAL, nic_pci_read, nic_pci_write, dev, &dev->pci_slot);
}
/* Initialize the RTL8029 EEPROM. */
memset(dev->eeprom, 0x00, sizeof(dev->eeprom));
if (dev->board == NE2K_RTL8029AS) {
memcpy(&dev->eeprom[0x02], dev->maclocal, 6);
dev->eeprom[0x76] = dev->eeprom[0x7A] = dev->eeprom[0x7E] = (PCI_DEVID & 0xff);
dev->eeprom[0x77] = dev->eeprom[0x7B] = dev->eeprom[0x7F] = (PCI_DEVID >> 8);
dev->eeprom[0x78] = dev->eeprom[0x7C] = (PCI_VENDID & 0xff);
dev->eeprom[0x79] = dev->eeprom[0x7D] = (PCI_VENDID >> 8);
} else {
const char *pnp_rom_file = NULL;
int pnp_rom_len = 0x4a;
switch (dev->board) {
case NE2K_RTL8019AS:
pnp_rom_file = "roms/network/rtl8019as/RTL8019A.BIN";
break;
case NE2K_DE220P:
pnp_rom_file = "roms/network/de220p/dlk2201a.bin";
pnp_rom_len = 0x43;
break;
default:
break;
}
uint8_t *pnp_rom = NULL;
if (pnp_rom_file) {
FILE *fp = rom_fopen(pnp_rom_file, "rb");
if (fp) {
if (fread(&dev->eeprom[0x12], 1, pnp_rom_len, fp) == pnp_rom_len)
pnp_rom = &dev->eeprom[0x12];
fclose(fp);
}
}
switch (info->local) {
case NE2K_RTL8019AS:
case NE2K_DE220P:
dev->pnp_card = isapnp_add_card(pnp_rom, pnp_rom_len,
nic_pnp_config_changed, nic_pnp_csn_changed,
nic_pnp_read_vendor_reg, nic_pnp_write_vendor_reg,
dev);
break;
default:
break;
}
}
}
if (dev->board != NE2K_ETHERNEXT_MC)
/* Reset the board. */
nic_reset(dev);
/* Attach ourselves to the network module. */
dev->dp8390->card = network_attach(dev->dp8390, dev->dp8390->physaddr, dp8390_rx, NULL);
nelog(1, "%s: %s attached IO=0x%X IRQ=%d\n", dev->name,
dev->is_pci ? "PCI" : "ISA", dev->base_address, dev->base_irq);
return dev;
}
static void
nic_close(void *priv)
{
nic_t *dev = (nic_t *) priv;
nelog(1, "%s: closed\n", dev->name);
free(dev);
}
static int
rtl8019as_available(void)
{
return rom_present("roms/network/rtl8019as/RTL8019A.BIN");
}
static int
de220p_available(void)
{
return rom_present("roms/network/de220p/dlk2201a.bin");
}
// clang-format off
static const device_config_t ne1000_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t ne1000_compat_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "0x200", .value = 0x200 },
{ .description = "0x220", .value = 0x220 },
{ .description = "0x240", .value = 0x240 },
{ .description = "0x260", .value = 0x260 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2a0", .value = 0x2a0 },
{ .description = "0x2c0", .value = 0x2c0 },
{ .description = "0x2e0", .value = 0x2e0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "0x380", .value = 0x380 },
{ .description = "0x3a0", .value = 0x3a0 },
{ .description = "0x3c0", .value = 0x3c0 },
{ .description = "0x3e0", .value = 0x3e0 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t ne2000_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t ne2000_compat_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x300,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file. */
{ .description = "0x200", .value = 0x200 },
{ .description = "0x220", .value = 0x220 },
{ .description = "0x240", .value = 0x240 },
{ .description = "0x260", .value = 0x260 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2a0", .value = 0x2a0 },
{ .description = "0x2c0", .value = 0x2c0 },
{ .description = "0x2e0", .value = 0x2e0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "0x380", .value = 0x380 },
{ .description = "0x3a0", .value = 0x3a0 },
{ .description = "0x3c0", .value = 0x3c0 },
{ .description = "0x3e0", .value = 0x3e0 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 10,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: Windows 95 .INF file - not giving impossible IRQ's
such as 6, 8, or 13. */
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 7", .value = 7 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "IRQ 10", .value = 10 },
{ .description = "IRQ 11", .value = 11 },
{ .description = "IRQ 12", .value = 12 },
{ .description = "IRQ 14", .value = 14 },
{ .description = "IRQ 15", .value = 15 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0x00000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t ne2000_compat_8bit_config[] = {
{
.name = "base",
.description = "Address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x320,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: board docs, path_to_url */
{ .description = "0x200", .value = 0x200 },
{ .description = "0x220", .value = 0x220 },
{ .description = "0x240", .value = 0x240 },
{ .description = "0x260", .value = 0x260 },
{ .description = "0x280", .value = 0x280 },
{ .description = "0x2a0", .value = 0x2a0 },
{ .description = "0x2c0", .value = 0x2c0 },
{ .description = "0x2e0", .value = 0x2e0 },
{ .description = "0x300", .value = 0x300 },
{ .description = "0x320", .value = 0x320 },
{ .description = "0x340", .value = 0x340 },
{ .description = "0x360", .value = 0x360 },
{ .description = "0x380", .value = 0x380 },
{ .description = "0x3a0", .value = 0x3a0 },
{ .description = "0x3c0", .value = 0x3c0 },
{ .description = "0x3e0", .value = 0x3e0 },
{ .description = "" }
},
},
{
.name = "irq",
.description = "IRQ",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 3,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: board docs, path_to_url */
{ .description = "IRQ 2", .value = 2 },
{ .description = "IRQ 3", .value = 3 },
{ .description = "IRQ 4", .value = 4 },
{ .description = "IRQ 5", .value = 5 },
{ .description = "IRQ 9", .value = 9 },
{ .description = "" }
},
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{
.name = "bios_addr",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
/* Source: board docs, path_to_url */
{ .description = "Disabled", .value = 0x00000 },
{ .description = "C000", .value = 0xC0000 },
{ .description = "C400", .value = 0xC4000 },
{ .description = "C800", .value = 0xC8000 },
{ .description = "CC00", .value = 0xCC000 },
{ .description = "D000", .value = 0xD0000 },
{ .description = "D400", .value = 0xD4000 },
{ .description = "D800", .value = 0xD8000 },
{ .description = "DC00", .value = 0xDC000 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t rtl8019as_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t rtl8029as_config[] = {
{
.name = "bios",
.description = "Enable BIOS",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 0
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t mca_mac_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t ne1000_device = {
.name = "Novell NE1000",
.internal_name = "novell_ne1k",
.flags = DEVICE_ISA,
.local = NE2K_NE1000,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ne1000_config
};
const device_t ne1000_compat_device = {
.name = "NE1000 Compatible",
.internal_name = "ne1k",
.flags = DEVICE_ISA,
.local = NE2K_NE1000_COMPAT,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ne1000_compat_config
};
const device_t ne2000_device = {
.name = "Novell NE2000",
.internal_name = "novell_ne2k",
.flags = DEVICE_ISA | DEVICE_AT,
.local = NE2K_NE2000,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ne2000_config
};
const device_t ne2000_compat_device = {
.name = "NE2000 Compatible",
.internal_name = "ne2k",
.flags = DEVICE_ISA | DEVICE_AT,
.local = NE2K_NE2000_COMPAT,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ne2000_compat_config
};
const device_t ne2000_compat_8bit_device = {
.name = "NE2000 Compatible 8-bit",
.internal_name = "ne2k8",
.flags = DEVICE_ISA,
.local = NE2K_NE2000_COMPAT_8BIT,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = ne2000_compat_8bit_config
};
const device_t ethernext_mc_device = {
.name = "NetWorth EtherNext/MC",
.internal_name = "ethernextmc",
.flags = DEVICE_MCA,
.local = NE2K_ETHERNEXT_MC,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = mca_mac_config
};
const device_t rtl8019as_device = {
.name = "Realtek RTL8019AS",
.internal_name = "ne2kpnp",
.flags = DEVICE_ISA | DEVICE_AT,
.local = NE2K_RTL8019AS,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = rtl8019as_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = rtl8019as_config
};
const device_t de220p_device = {
.name = "D-Link DE-220P",
.internal_name = "de220p",
.flags = DEVICE_ISA | DEVICE_AT,
.local = NE2K_DE220P,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = de220p_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = rtl8019as_config
};
const device_t rtl8029as_device = {
.name = "Realtek RTL8029AS",
.internal_name = "ne2kpci",
.flags = DEVICE_PCI,
.local = NE2K_RTL8029AS,
.init = nic_init,
.close = nic_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = rtl8029as_config
};
``` | /content/code_sandbox/src/network/net_ne2000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 15,559 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of a PLIP parallel port network device.
*
* Tested against the Linux plip.c driver and the DOS plip.com
* packet driver. PLIP is not particularly fast, as it's a 4-bit
* half-duplex protocol operating over SPP.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*/
#include <inttypes.h>
#include <memory.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/lpt.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/plat_unused.h>
enum {
PLIP_START = 0x00,
PLIP_TX_LEN_LSB_LOW = 0x10,
PLIP_TX_LEN_LSB_HIGH,
PLIP_TX_LEN_MSB_LOW,
PLIP_TX_LEN_MSB_HIGH,
PLIP_TX_DATA_LOW,
PLIP_TX_DATA_HIGH,
PLIP_TX_CHECKSUM_LOW,
PLIP_TX_CHECKSUM_HIGH,
PLIP_RX_LEN_LSB_LOW = 0x20,
PLIP_RX_LEN_LSB_HIGH,
PLIP_RX_LEN_MSB_LOW,
PLIP_RX_LEN_MSB_HIGH,
PLIP_RX_DATA_LOW,
PLIP_RX_DATA_HIGH,
PLIP_RX_CHECKSUM_LOW,
PLIP_RX_CHECKSUM_HIGH,
PLIP_END = 0x40
};
typedef struct plip_t {
uint8_t mac[6];
void *lpt;
pc_timer_t rx_timer;
pc_timer_t timeout_timer;
uint8_t status;
uint8_t ctrl;
uint8_t state;
uint8_t ack;
uint8_t tx_checksum;
uint8_t tx_checksum_calc;
uint8_t *tx_pkt;
uint16_t tx_len;
uint16_t tx_ptr;
uint8_t *rx_pkt;
uint8_t rx_checksum;
uint8_t rx_return_state;
uint16_t rx_len;
uint16_t rx_ptr;
netcard_t *card;
} plip_t;
static void plip_receive_packet(plip_t *dev);
plip_t *instance;
#ifdef ENABLE_PLIP_LOG
int plip_do_log = ENABLE_PLIP_LOG;
static void
plip_log(uint8_t lvl, const char *fmt, ...)
{
va_list ap;
if (plip_do_log >= lvl) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define plip_log(lvl, fmt, ...)
#endif
static void
timeout_timer(void *priv)
{
plip_t *dev = (plip_t *) priv;
plip_log(1, "PLIP: timeout at state %d status %02X\n", dev->state, dev->status);
/* Throw everything out the window. */
dev->state = PLIP_START;
dev->status = 0x80;
if (dev->tx_pkt) {
free(dev->tx_pkt);
dev->tx_pkt = NULL;
}
if (dev->rx_pkt) {
free(dev->rx_pkt);
dev->rx_pkt = NULL;
}
timer_disable(&dev->timeout_timer);
}
static void
plip_write_data(uint8_t val, void *priv)
{
plip_t *dev = (plip_t *) priv;
plip_log(3, "PLIP: write_data(%02X)\n", val);
switch (dev->state) {
case PLIP_START:
if (val == 0x08) { /* D3/ACK wakes us up */
plip_log(2, "PLIP: ACK wakeup\n");
dev->state = PLIP_TX_LEN_LSB_LOW;
dev->status = 0x08;
break;
}
return;
case PLIP_TX_LEN_LSB_LOW:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
dev->tx_len = val & 0xf;
plip_log(2, "PLIP: tx_len = %04X (1/4)\n", dev->tx_len);
dev->state = PLIP_TX_LEN_LSB_HIGH;
dev->status &= ~0x88;
break;
case PLIP_TX_LEN_LSB_HIGH:
if (val & 0x10)
return; /* D4/BUSY not low yet */
dev->tx_len |= (val & 0xf) << 4;
plip_log(2, "PLIP: tx_len = %04X (2/4)\n", dev->tx_len);
dev->state = PLIP_TX_LEN_MSB_LOW;
dev->status |= 0x80;
break;
case PLIP_TX_LEN_MSB_LOW:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
dev->tx_len |= (val & 0xf) << 8;
plip_log(2, "PLIP: tx_len = %04X (3/4)\n", dev->tx_len);
dev->state = PLIP_TX_LEN_MSB_HIGH;
dev->status &= ~0x80;
break;
case PLIP_TX_LEN_MSB_HIGH:
if (val & 0x10)
return; /* D4/BUSY not low yet */
dev->tx_len |= (val & 0xf) << 12;
plip_log(2, "PLIP: tx_len = %04X (4/4)\n", dev->tx_len);
/* We have the length, allocate a packet. */
if (!(dev->tx_pkt = malloc(dev->tx_len))) /* unlikely */
fatal("PLIP: unable to allocate tx_pkt\n");
dev->tx_ptr = 0;
dev->tx_checksum_calc = 0;
dev->state = PLIP_TX_DATA_LOW;
dev->status |= 0x80;
break;
case PLIP_TX_DATA_LOW:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
dev->tx_pkt[dev->tx_ptr] = val & 0x0f;
plip_log(2, "PLIP: tx_pkt[%d] = %02X (1/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]);
dev->state = PLIP_TX_DATA_HIGH;
dev->status &= ~0x80;
break;
case PLIP_TX_DATA_HIGH:
if (val & 0x10)
return; /* D4/BUSY not low yet */
dev->tx_pkt[dev->tx_ptr] |= (val & 0x0f) << 4;
plip_log(2, "PLIP: tx_pkt[%d] = %02X (2/2)\n", dev->tx_ptr, dev->tx_pkt[dev->tx_ptr]);
dev->tx_checksum_calc += dev->tx_pkt[dev->tx_ptr++];
/* Are we done yet? */
if (dev->tx_ptr < dev->tx_len) /* no, receive another byte */
dev->state = PLIP_TX_DATA_LOW;
else /* yes, move on to checksum */
dev->state = PLIP_TX_CHECKSUM_LOW;
dev->status |= 0x80;
break;
case PLIP_TX_CHECKSUM_LOW:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
dev->tx_checksum = val & 0x0f;
plip_log(2, "PLIP: tx_checksum = %02X (1/2)\n", dev->tx_checksum);
dev->state = PLIP_TX_CHECKSUM_HIGH;
dev->status &= ~0x80;
break;
case PLIP_TX_CHECKSUM_HIGH:
if (val & 0x10)
return; /* D4/BUSY not low yet */
dev->tx_checksum |= (val & 0x0f) << 4;
plip_log(2, "PLIP: tx_checksum = %02X (2/2)\n", dev->tx_checksum);
/* Verify checksum. */
if (dev->tx_checksum_calc == dev->tx_checksum) {
/* Make sure we know the other end's MAC address. */
memcpy(dev->mac, dev->tx_pkt + 6, 6);
/* Transmit packet. */
plip_log(2, "PLIP: transmitting %d-byte packet\n", dev->tx_len);
network_tx(dev->card, dev->tx_pkt, dev->tx_len);
} else {
plip_log(1, "PLIP: checksum error: expected %02X, got %02X\n", dev->tx_checksum_calc, dev->tx_checksum);
}
/* We're done with this packet. */
free(dev->tx_pkt);
dev->tx_pkt = NULL;
dev->tx_len = 0;
dev->state = PLIP_END;
dev->status |= 0x80;
break;
case PLIP_RX_LEN_LSB_LOW:
if (!(val & 0x01))
return; /* D3/ACK not high yet */
plip_log(2, "PLIP: rx_len = %04X (1/4)\n", dev->rx_len);
dev->status = (dev->rx_len & 0x0f) << 3;
dev->state = PLIP_RX_LEN_LSB_HIGH;
break;
case PLIP_RX_LEN_LSB_HIGH:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
plip_log(2, "PLIP: rx_len = %04X (2/4)\n", dev->rx_len);
dev->status = ((dev->rx_len >> 4) & 0x0f) << 3;
dev->status |= 0x80;
dev->state = PLIP_RX_LEN_MSB_LOW;
break;
case PLIP_RX_LEN_MSB_LOW:
if (val & 0x10)
return; /* D4/BUSY not low yet */
plip_log(2, "PLIP: rx_len = %04X (3/4)\n", dev->rx_len);
dev->status = ((dev->rx_len >> 8) & 0x0f) << 3;
dev->state = PLIP_RX_LEN_MSB_HIGH;
break;
case PLIP_RX_LEN_MSB_HIGH:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
plip_log(2, "PLIP: rx_len = %04X (4/4)\n", dev->rx_len);
dev->status = ((dev->rx_len >> 12) & 0x0f) << 3;
dev->status |= 0x80;
dev->rx_ptr = 0;
dev->rx_checksum = 0;
dev->state = PLIP_RX_DATA_LOW;
break;
case PLIP_RX_DATA_LOW:
if (val & 0x10)
return; /* D4/BUSY not low yet */
plip_log(2, "PLIP: rx_pkt[%d] = %02X (1/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]);
dev->status = (dev->rx_pkt[dev->rx_ptr] & 0x0f) << 3;
dev->state = PLIP_RX_DATA_HIGH;
break;
case PLIP_RX_DATA_HIGH:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
plip_log(2, "PLIP: rx_pkt[%d] = %02X (2/2)\n", dev->rx_ptr, dev->rx_pkt[dev->rx_ptr]);
dev->status = ((dev->rx_pkt[dev->rx_ptr] >> 4) & 0x0f) << 3;
dev->status |= 0x80;
dev->rx_checksum += dev->rx_pkt[dev->rx_ptr++];
/* Are we done yet? */
if (dev->rx_ptr < dev->rx_len) /* no, send another byte */
dev->state = PLIP_RX_DATA_LOW;
else /* yes, move on to checksum */
dev->state = PLIP_RX_CHECKSUM_LOW;
break;
case PLIP_RX_CHECKSUM_LOW:
if (val & 0x10)
return; /* D4/BUSY not low yet */
plip_log(2, "PLIP: rx_checksum = %02X (1/2)\n", dev->rx_checksum);
dev->status = (dev->rx_checksum & 0x0f) << 3;
dev->state = PLIP_RX_CHECKSUM_HIGH;
break;
case PLIP_RX_CHECKSUM_HIGH:
if (!(val & 0x10))
return; /* D4/BUSY not high yet */
plip_log(2, "PLIP: rx_checksum = %02X (2/2)\n", dev->rx_checksum);
dev->status = ((dev->rx_checksum >> 4) & 0x0f) << 3;
dev->status |= 0x80;
/* We're done with this packet. */
free(dev->rx_pkt);
dev->rx_pkt = NULL;
dev->rx_len = 0;
dev->state = PLIP_END;
break;
case PLIP_END:
if (val == 0x00) { /* written after TX or RX is done */
plip_log(2, "PLIP: end\n");
dev->status = 0x80;
dev->state = PLIP_START;
timer_set_delay_u64(&dev->rx_timer, ISACONST); /* for DOS */
}
/* Disengage timeout timer. */
timer_disable(&dev->timeout_timer);
return;
default:
break;
}
/* Engage timeout timer unless otherwise specified. */
timer_set_delay_u64(&dev->timeout_timer, 1000000 * TIMER_USEC);
}
static void
plip_write_ctrl(uint8_t val, void *priv)
{
plip_t *dev = (plip_t *) priv;
plip_log(3, "PLIP: write_ctrl(%02X)\n", val);
dev->ctrl = val;
if (val & 0x10) /* for Linux */
timer_set_delay_u64(&dev->rx_timer, ISACONST);
}
static uint8_t
plip_read_status(void *priv)
{
const plip_t *dev = (plip_t *) priv;
plip_log(3, "PLIP: read_status() = %02X\n", dev->status);
return dev->status;
}
static void
plip_receive_packet(plip_t *dev)
{
/* At least the Linux driver supports being interrupted
in the PLIP_TX_LEN_LSB_LOW state, but let's be safe. */
if (dev->state > PLIP_START) {
plip_log(3, "PLIP: cannot receive, operation already in progress\n");
return;
}
if (!dev->rx_pkt || !dev->rx_len) { /* unpause RX queue if there's no packet to receive */
return;
}
if (!(dev->ctrl & 0x10)) { /* checking this is essential to avoid collisions */
plip_log(3, "PLIP: cannot receive, interrupts are off\n");
return;
}
plip_log(2, "PLIP: receiving %d-byte packet\n", dev->rx_len);
/* Set up to receive a packet. */
dev->status = 0xc7; /* DOS expects exactly 0xc7, while Linux masks the 7 off */
dev->state = PLIP_RX_LEN_LSB_LOW;
/* Engage timeout timer. */
timer_set_delay_u64(&dev->timeout_timer, 1000000 * TIMER_USEC);
/* Wake the other end up. */
lpt_irq(dev->lpt, 1);
}
/* This timer defers a call to plip_receive_packet to
the next ISA clock, in order to avoid IRQ weirdness. */
static void
rx_timer(void *priv)
{
plip_t *dev = (plip_t *) priv;
plip_receive_packet(dev);
timer_disable(&dev->rx_timer);
}
static int
plip_rx(void *priv, uint8_t *buf, int io_len)
{
plip_t *dev = (plip_t *) priv;
plip_log(2, "PLIP: incoming %d-byte packet\n", io_len);
if (dev->rx_pkt) { /* shouldn't really happen with the RX queue paused */
plip_log(3, "PLIP: already have a packet to receive");
return 0;
}
if (!(dev->rx_pkt = malloc(io_len))) /* unlikely */
fatal("PLIP: unable to allocate rx_pkt\n");
/* Copy this packet to our buffer. */
dev->rx_len = io_len;
memcpy(dev->rx_pkt, buf, dev->rx_len);
/* Dispatch this packet immediately if we're doing nothing. */
plip_receive_packet(dev);
return 1;
}
static void *
plip_lpt_init(void *lpt)
{
plip_t *dev = (plip_t *) malloc(sizeof(plip_t));
memset(dev, 0, sizeof(plip_t));
plip_log(1, "PLIP: lpt_init()\n");
dev->lpt = lpt;
memset(dev->mac, 0xfc, 6); /* static MAC used by Linux; just a placeholder */
dev->status = 0x80;
timer_add(&dev->rx_timer, rx_timer, dev, 0);
timer_add(&dev->timeout_timer, timeout_timer, dev, 0);
instance = dev;
return dev;
}
static void *
plip_net_init(UNUSED(const device_t *info))
{
plip_log(1, "PLIP: net_init()");
if (!instance) {
plip_log(1, " (not attached to LPT)\n");
return NULL;
}
plip_log(1, " (attached to LPT)\n");
instance->card = network_attach(instance, instance->mac, plip_rx, NULL);
return instance;
}
static void
plip_close(void *priv)
{
if (instance->card) {
netcard_close(instance->card);
}
free(priv);
}
const lpt_device_t lpt_plip_device = {
.name = "Parallel Line Internet Protocol",
.internal_name = "plip",
.init = plip_lpt_init,
.close = plip_close,
.write_data = plip_write_data,
.write_ctrl = plip_write_ctrl,
.read_data = NULL,
.read_status = plip_read_status,
.read_ctrl = NULL
};
const device_t plip_device = {
.name = "Parallel Line Internet Protocol",
.internal_name = "plip",
.flags = DEVICE_LPT,
.local = 0,
.init = plip_net_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/network/net_plip.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,428 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Hayes AT-compliant modem emulation.
*
*
*
* Authors: Cacodemon345
* The DOSBox Team
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <ctype.h>
#include <wchar.h>
#include <stdbool.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/fifo.h>
#include <86box/fifo8.h>
#include <86box/timer.h>
#include <86box/serial.h>
#include <86box/plat.h>
#include <86box/network.h>
#include <86box/version.h>
#include <86box/plat_unused.h>
#include <86box/plat_netsocket.h>
#ifdef ENABLE_MODEM_LOG
int modem_do_log = ENABLE_MODEM_LOG;
static void
modem_log(const char *fmt, ...)
{
va_list ap;
if (modem_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define modem_log(fmt, ...)
#endif
/* From RFC 1055. */
#define END 0300 /* indicates end of packet */
#define ESC 0333 /* indicates byte stuffing */
#define ESC_END 0334 /* ESC ESC_END means END data byte */
#define ESC_ESC 0335 /* ESC ESC_ESC means ESC data byte */
typedef enum ResTypes {
ResNONE,
ResOK,
ResERROR,
ResCONNECT,
ResRING,
ResBUSY,
ResNODIALTONE,
ResNOCARRIER,
ResNOANSWER
} ResTypes;
enum modem_types {
MODEM_TYPE_SLIP = 1,
MODEM_TYPE_PPP = 2,
MODEM_TYPE_TCPIP = 3
};
typedef enum modem_mode_t {
MODEM_MODE_COMMAND = 0,
MODEM_MODE_DATA = 1
} modem_mode_t;
typedef enum modem_slip_stage_t {
MODEM_SLIP_STAGE_USERNAME,
MODEM_SLIP_STAGE_PASSWORD
} modem_slip_stage_t;
#define COMMAND_BUFFER_SIZE 512
#define NUMBER_BUFFER_SIZE 128
#define PHONEBOOK_SIZE 200
typedef struct modem_phonebook_entry_t {
char phone[NUMBER_BUFFER_SIZE];
char address[NUMBER_BUFFER_SIZE];
} modem_phonebook_entry_t;
typedef struct modem_t {
uint8_t mac[6];
serial_t *serial;
uint32_t baudrate;
modem_mode_t mode;
uint8_t esc_character_expected;
pc_timer_t host_to_serial_timer;
pc_timer_t dtr_timer;
pc_timer_t cmdpause_timer;
uint8_t tx_pkt_ser_line[0x10000]; /* SLIP-encoded. */
uint32_t tx_count;
Fifo8 rx_data; /* Data received from the network. */
uint8_t reg[100];
Fifo8 data_pending; /* Data yet to be sent to the host. */
char cmdbuf[COMMAND_BUFFER_SIZE];
char prevcmdbuf[COMMAND_BUFFER_SIZE];
char numberinprogress[NUMBER_BUFFER_SIZE];
char lastnumber[NUMBER_BUFFER_SIZE];
uint32_t cmdpos;
uint32_t port;
int plusinc, flowcontrol;
int in_warmup, dtrmode;
int dcdmode;
bool connected, ringing;
bool echo, numericresponse;
bool tcpIpMode, tcpIpConnInProgress;
bool cooldown;
bool telnet_mode;
bool dtrstate;
uint32_t tcpIpConnCounter;
int doresponse;
int cmdpause;
int listen_port;
int ringtimer;
SOCKET serversocket;
SOCKET clientsocket;
SOCKET waitingclientsocket;
struct {
bool binary[2];
bool echo[2];
bool supressGA[2];
bool timingMark[2];
bool inIAC;
bool recCommand;
uint8_t command;
} telClient;
modem_phonebook_entry_t entries[PHONEBOOK_SIZE];
uint32_t entries_num;
netcard_t *card;
} modem_t;
#define MREG_AUTOANSWER_COUNT 0
#define MREG_RING_COUNT 1
#define MREG_ESCAPE_CHAR 2
#define MREG_CR_CHAR 3
#define MREG_LF_CHAR 4
#define MREG_BACKSPACE_CHAR 5
#define MREG_GUARD_TIME 12
#define MREG_DTR_DELAY 25
static void modem_do_command(modem_t *modem, int repeat);
static void modem_accept_incoming_call(modem_t *modem);
extern ssize_t local_getline(char **buf, size_t *bufsiz, FILE *fp);
// path_to_url
char *
trim(char *str)
{
size_t len = 0;
char *frontp = str;
char *endp = NULL;
if (str == NULL) {
return NULL;
}
if (str[0] == '\0') {
return str;
}
len = strlen(str);
endp = str + len;
/* Move the front and back pointers to address the first non-whitespace
* characters from each end.
*/
while (isspace((unsigned char) *frontp)) {
++frontp;
}
if (endp != frontp) {
while (isspace((unsigned char) *(--endp)) && endp != frontp) { }
}
if (frontp != str && endp == frontp)
*str = '\0';
else if (str + len - 1 != endp)
*(endp + 1) = '\0';
/* Shift the string so that it starts at str so that if it's dynamically
* allocated, we can still free it on the returned pointer. Note the reuse
* of endp to mean the front of the string buffer now.
*/
endp = str;
if (frontp != str) {
while (*frontp) {
*endp++ = *frontp++;
}
*endp = '\0';
}
return str;
}
static void
modem_read_phonebook_file(modem_t *modem, const char *path)
{
FILE *file = plat_fopen(path, "r");
char *buf = NULL;
char *buf2 = NULL;
size_t size = 0;
if (!file)
return;
modem->entries_num = 0;
modem_log("Modem: Reading phone book file %s...\n", path);
while (local_getline(&buf, &size, file) != -1) {
modem_phonebook_entry_t entry = { { 0 }, { 0 } };
buf[strcspn(buf, "\r\n")] = '\0';
/* Remove surrounding whitespace from the input line and find the address part. */
buf = trim(buf);
buf2 = &buf[strcspn(buf, " \t")];
/* Remove surrounding whitespace and any extra text from the address part, then store it. */
buf2 = trim(buf2);
buf2[strcspn(buf2, " \t")] = '\0';
strncpy(entry.address, buf2, sizeof(entry.address) - 1);
/* Split the line to get the phone number part, then store it. */
buf2[0] = '\0';
strncpy(entry.phone, buf, sizeof(entry.phone) - 1);
if ((entry.phone[0] == '\0') || (entry.address[0] == '\0')) {
/* Appears to be a bad line. */
modem_log("Modem: Skipped a bad line\n");
continue;
}
if (strspn(entry.phone, "01234567890*=,;#+>") != strlen(entry.phone)) {
/* Invalid characters. */
pclog("Modem: Invalid character in phone number %s\n", entry.phone);
continue;
}
modem_log("Modem: Mapped phone number %s to address %s\n", entry.phone, entry.address);
modem->entries[modem->entries_num++] = entry;
if (modem->entries_num >= PHONEBOOK_SIZE)
break;
}
fclose(file);
}
static void
modem_echo(modem_t *modem, uint8_t c)
{
if (modem->echo && fifo8_num_free(&modem->data_pending))
fifo8_push(&modem->data_pending, c);
}
static uint32_t
modem_scan_number(char **scan)
{
char c = 0;
uint32_t ret = 0;
while (1) {
c = **scan;
if (c == 0)
break;
if (c >= '0' && c <= '9') {
ret *= 10;
ret += c - '0';
*scan = *scan + 1;
} else
break;
}
return ret;
}
static uint8_t
modem_fetch_character(char **scan)
{
uint8_t c = **scan;
*scan = *scan + 1;
return c;
}
static void
modem_speed_changed(void *priv)
{
modem_t *dev = (modem_t *) priv;
if (!dev)
return;
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / (double) dev->baudrate) * 9);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
modem_send_line(modem_t *modem, const char *line)
{
fifo8_push(&modem->data_pending, modem->reg[MREG_CR_CHAR]);
fifo8_push(&modem->data_pending, modem->reg[MREG_LF_CHAR]);
fifo8_push_all(&modem->data_pending, (uint8_t *) line, strlen(line));
fifo8_push(&modem->data_pending, modem->reg[MREG_CR_CHAR]);
fifo8_push(&modem->data_pending, modem->reg[MREG_LF_CHAR]);
}
static void
modem_send_number(modem_t *modem, uint32_t val)
{
fifo8_push(&modem->data_pending, modem->reg[MREG_CR_CHAR]);
fifo8_push(&modem->data_pending, modem->reg[MREG_LF_CHAR]);
fifo8_push(&modem->data_pending, val / 100 + '0');
val = val % 100;
fifo8_push(&modem->data_pending, val / 10 + '0');
val = val % 10;
fifo8_push(&modem->data_pending, val + '0');
fifo8_push(&modem->data_pending, modem->reg[MREG_CR_CHAR]);
fifo8_push(&modem->data_pending, modem->reg[MREG_LF_CHAR]);
}
static void
process_tx_packet(modem_t *modem, uint8_t *p, uint32_t len)
{
int received = 0;
uint32_t pos = 0;
uint8_t *processed_tx_packet = calloc(len, 1);
uint8_t c = 0;
modem_log("Processing SLIP packet of %u bytes\n", len);
while (pos < len) {
c = p[pos];
pos++;
switch (c) {
case END:
if (received)
goto send_tx_packet;
else
break;
case ESC:
{
c = p[pos];
pos++;
switch (c) {
case ESC_END:
c = END;
break;
case ESC_ESC:
c = ESC;
break;
}
}
default:
if (received < len)
processed_tx_packet[received++] = c;
break;
}
}
send_tx_packet:
if (received) {
uint8_t *buf = calloc(received + 14, 1);
buf[0] = buf[1] = buf[2] = buf[3] = buf[4] = buf[5] = 0xFF;
buf[6] = buf[7] = buf[8] = buf[9] = buf[10] = buf[11] = 0xFC;
buf[12] = 0x08;
buf[13] = 0x00;
memcpy(buf + 14, processed_tx_packet, received);
network_tx(modem->card, buf, received + 14);
free(buf);
}
free(processed_tx_packet);
return;
}
static void
modem_data_mode_process_byte(modem_t *modem, uint8_t data)
{
if (modem->reg[MREG_ESCAPE_CHAR] <= 127) {
if (modem->plusinc >= 1 && modem->plusinc <= 3 && modem->reg[MREG_ESCAPE_CHAR] == data) {
modem->plusinc++;
} else {
modem->plusinc = 0;
}
}
modem->cmdpause = 0;
if (modem->tx_count < 0x10000 && modem->connected) {
modem->tx_pkt_ser_line[modem->tx_count++] = data;
if (data == END && !modem->tcpIpMode) {
process_tx_packet(modem, modem->tx_pkt_ser_line, (uint32_t) modem->tx_count);
modem->tx_count = 0;
}
}
}
static void
host_to_modem_cb(void *priv)
{
modem_t *modem = (modem_t *) priv;
if (modem->in_warmup)
goto no_write_to_machine;
if ((modem->serial->type >= SERIAL_16550) && modem->serial->fifo_enabled) {
if (fifo_get_full(modem->serial->rcvr_fifo)) {
goto no_write_to_machine;
}
} else {
if (modem->serial->lsr & 1) {
goto no_write_to_machine;
}
}
if (!((modem->serial->mctrl & 2) || modem->flowcontrol != 3))
goto no_write_to_machine;
if (modem->mode == MODEM_MODE_DATA && fifo8_num_used(&modem->rx_data) && !modem->cooldown) {
serial_write_fifo(modem->serial, fifo8_pop(&modem->rx_data));
} else if (fifo8_num_used(&modem->data_pending)) {
uint8_t val = fifo8_pop(&modem->data_pending);
serial_write_fifo(modem->serial, val);
}
if (fifo8_num_used(&modem->data_pending) == 0) {
modem->cooldown = false;
}
no_write_to_machine:
timer_on_auto(&modem->host_to_serial_timer, (1000000.0 / (double) modem->baudrate) * (double) 9);
}
static void
modem_write(UNUSED(serial_t *s), void *priv, uint8_t txval)
{
modem_t *modem = (modem_t *) priv;
if (modem->mode == MODEM_MODE_COMMAND) {
if (modem->cmdpos < 2) {
// Ignore everything until we see "AT" sequence.
if (modem->cmdpos == 0 && toupper(txval) != 'A') {
return;
}
if (modem->cmdpos == 1 && toupper(txval) != 'T') {
if (txval == '/') {
// Repeat the last command.
modem_echo(modem, txval);
modem_log("Repeat last command (%s)\n", modem->prevcmdbuf);
modem_do_command(modem, 1);
} else {
modem_echo(modem, modem->reg[MREG_BACKSPACE_CHAR]);
modem->cmdpos = 0;
}
return;
}
} else {
// Now entering command.
if (txval == modem->reg[MREG_BACKSPACE_CHAR]) {
if (modem->cmdpos > 2) {
modem_echo(modem, txval);
modem->cmdpos--;
}
return;
}
if (txval == modem->reg[MREG_LF_CHAR]) {
return; // Real modem doesn't seem to skip this?
}
if (txval == modem->reg[MREG_CR_CHAR]) {
modem_echo(modem, txval);
modem_do_command(modem, 0);
return;
}
}
if (modem->cmdpos < 99) {
modem_echo(modem, txval);
modem->cmdbuf[modem->cmdpos] = txval;
modem->cmdpos++;
}
} else {
modem_data_mode_process_byte(modem, txval);
}
}
void
modem_send_res(modem_t *modem, const ResTypes response)
{
char response_str_connect[256] = { 0 };
const char *response_str = NULL;
uint32_t code = -1;
snprintf(response_str_connect, sizeof(response_str_connect), "CONNECT %u", modem->baudrate);
switch (response) {
case ResOK:
code = 0;
response_str = "OK";
break;
case ResCONNECT:
code = 1;
response_str = response_str_connect;
break;
case ResRING:
code = 2;
response_str = "RING";
break;
case ResNOCARRIER:
code = 3;
response_str = "NO CARRIER";
break;
case ResERROR:
code = 4;
response_str = "ERROR";
break;
case ResNODIALTONE:
code = 6;
response_str = "NO DIALTONE";
break;
case ResBUSY:
code = 7;
response_str = "BUSY";
break;
case ResNOANSWER:
code = 8;
response_str = "NO ANSWER";
break;
case ResNONE:
return;
}
if (modem->doresponse != 1) {
if (modem->doresponse == 2 && (response == ResRING || response == ResCONNECT || response == ResNOCARRIER)) {
return;
}
modem_log("Modem response: %s\n", response_str);
if (modem->numericresponse && code != ~0) {
modem_send_number(modem, code);
} else if (response_str != NULL) {
modem_send_line(modem, response_str);
}
}
}
void
modem_enter_idle_state(modem_t *modem)
{
timer_disable(&modem->dtr_timer);
modem->connected = false;
modem->ringing = false;
modem->mode = MODEM_MODE_COMMAND;
modem->in_warmup = 0;
modem->tcpIpConnInProgress = 0;
modem->tcpIpConnCounter = 0;
if (modem->waitingclientsocket != (SOCKET) -1)
plat_netsocket_close(modem->waitingclientsocket);
if (modem->clientsocket != (SOCKET) -1)
plat_netsocket_close(modem->clientsocket);
modem->clientsocket = modem->waitingclientsocket = (SOCKET) -1;
if (modem->serversocket != (SOCKET) -1) {
modem->waitingclientsocket = plat_netsocket_accept(modem->serversocket);
while (modem->waitingclientsocket != (SOCKET) -1) {
plat_netsocket_close(modem->waitingclientsocket);
modem->waitingclientsocket = plat_netsocket_accept(modem->serversocket);
}
plat_netsocket_close(modem->serversocket);
modem->serversocket = (SOCKET) -1;
}
if (modem->waitingclientsocket != (SOCKET) -1)
plat_netsocket_close(modem->waitingclientsocket);
modem->waitingclientsocket = (SOCKET) -1;
modem->tcpIpMode = false;
modem->tcpIpConnInProgress = false;
if (modem->listen_port) {
modem->serversocket = plat_netsocket_create_server(NET_SOCKET_TCP, modem->listen_port);
if (modem->serversocket == (SOCKET) -1) {
pclog("Failed to set up server on port %d\n", modem->listen_port);
}
}
serial_set_cts(modem->serial, 1);
serial_set_dsr(modem->serial, 1);
serial_set_dcd(modem->serial, (!modem->dcdmode ? 1 : 0));
serial_set_ri(modem->serial, 0);
}
void
modem_enter_connected_state(modem_t *modem)
{
modem_send_res(modem, ResCONNECT);
modem->mode = MODEM_MODE_DATA;
modem->ringing = false;
modem->connected = true;
modem->tcpIpMode = true;
modem->cooldown = true;
modem->tx_count = 0;
plat_netsocket_close(modem->serversocket);
modem->serversocket = -1;
memset(&modem->telClient, 0, sizeof(modem->telClient));
serial_set_dcd(modem->serial, 1);
serial_set_ri(modem->serial, 0);
}
void
modem_reset(modem_t *modem)
{
modem->dcdmode = 1;
modem_enter_idle_state(modem);
modem->cmdpos = 0;
modem->cmdbuf[0] = 0;
modem->prevcmdbuf[0] = 0;
modem->lastnumber[0] = 0;
modem->numberinprogress[0] = 0;
modem->flowcontrol = 0;
modem->cmdpause = 0;
modem->plusinc = 0;
modem->dtrmode = 2;
memset(&modem->reg, 0, sizeof(modem->reg));
modem->reg[MREG_AUTOANSWER_COUNT] = 0; // no autoanswer
modem->reg[MREG_RING_COUNT] = 1;
modem->reg[MREG_ESCAPE_CHAR] = '+';
modem->reg[MREG_CR_CHAR] = '\r';
modem->reg[MREG_LF_CHAR] = '\n';
modem->reg[MREG_BACKSPACE_CHAR] = '\b';
modem->reg[MREG_GUARD_TIME] = 50;
modem->reg[MREG_DTR_DELAY] = 5;
modem->echo = true;
modem->doresponse = 0;
modem->numericresponse = false;
}
void
modem_dial(modem_t *modem, const char *str)
{
modem->tcpIpConnCounter = 0;
modem->tcpIpMode = false;
if (!strcmp(str, "0.0.0.0") || !strcmp(str, "0000")) {
modem_log("Turning on SLIP\n");
modem_enter_connected_state(modem);
modem->numberinprogress[0] = 0;
modem->tcpIpMode = false;
} else {
char buf[NUMBER_BUFFER_SIZE] = "";
strncpy(buf, str, sizeof(buf) - 1);
strncpy(modem->lastnumber, str, sizeof(modem->lastnumber) - 1);
modem_log("Connecting to %s...\n", buf);
// Scan host for port
uint16_t port;
char *hasport = strrchr(buf, ':');
if (hasport) {
*hasport++ = 0;
port = (uint16_t) atoi(hasport);
} else {
port = 23;
}
modem->numberinprogress[0] = 0;
modem->clientsocket = plat_netsocket_create(NET_SOCKET_TCP);
if (modem->clientsocket == -1) {
pclog("Failed to create client socket\n");
modem_send_res(modem, ResNOCARRIER);
modem_enter_idle_state(modem);
return;
}
if (-1 == plat_netsocket_connect(modem->clientsocket, buf, port)) {
pclog("Failed to connect to %s\n", buf);
modem_send_res(modem, ResNOCARRIER);
modem_enter_idle_state(modem);
return;
}
modem->tcpIpConnInProgress = 1;
modem->tcpIpConnCounter = 0;
}
}
static bool
is_next_token(const char *a, size_t N, const char *b)
{
// Is 'b' at least as long as 'a'?
size_t N_without_null = N - 1;
if (strnlen(b, N) < N_without_null)
return false;
return (strncmp(a, b, N_without_null) == 0);
}
static const char *
modem_get_address_from_phonebook(modem_t *modem, const char *input)
{
int i = 0;
for (i = 0; i < modem->entries_num; i++) {
if (strcmp(input, modem->entries[i].phone) == 0)
return modem->entries[i].address;
}
return NULL;
}
static void
modem_do_command(modem_t *modem, int repeat)
{
int i = 0;
char *scanbuf = NULL;
if (repeat) {
/* Handle the case of A/ being invoked without a previous command to run */
if (modem->prevcmdbuf[0] == '\0') {
modem_send_res(modem, ResOK);
return;
}
/* Load the stored previous command line */
strncpy(modem->cmdbuf, modem->prevcmdbuf, sizeof(modem->cmdbuf) - 1);
modem->cmdbuf[COMMAND_BUFFER_SIZE - 1] = '\0';
} else {
/* Store the command line to be recalled */
strncpy(modem->prevcmdbuf, modem->cmdbuf, sizeof(modem->prevcmdbuf) - 1);
modem->prevcmdbuf[COMMAND_BUFFER_SIZE - 1] = '\0';
modem->cmdbuf[modem->cmdpos] = modem->prevcmdbuf[modem->cmdpos] = '\0';
}
modem->cmdpos = 0;
for (i = 0; i < sizeof(modem->cmdbuf); i++) {
modem->cmdbuf[i] = toupper(modem->cmdbuf[i]);
}
/* AT command set interpretation */
if ((modem->cmdbuf[0] != 'A') || (modem->cmdbuf[1] != 'T')) {
modem_send_res(modem, ResERROR);
return;
}
modem_log("Command received: %s (doresponse = %d)\n", modem->cmdbuf, modem->doresponse);
scanbuf = &modem->cmdbuf[2];
while (1) {
char chr = modem_fetch_character(&scanbuf);
switch (chr) {
case '+':
if (is_next_token("NET", sizeof("NET"), scanbuf)) {
// only walk the pointer ahead if the command matches
scanbuf += 3;
const uint32_t requested_mode = modem_scan_number(&scanbuf);
// If the mode isn't valid then stop parsing
if (requested_mode != 1 && requested_mode != 0) {
modem_send_res(modem, ResERROR);
return;
}
// Inform the user on changes
if (modem->telnet_mode != !!requested_mode) {
modem->telnet_mode = !!requested_mode;
}
break;
}
modem_send_res(modem, ResERROR);
return;
case 'D':
{ // Dial.
char buffer[NUMBER_BUFFER_SIZE];
char obuffer[NUMBER_BUFFER_SIZE];
char *foundstr = &scanbuf[0];
const char *mappedaddr = NULL;
size_t i = 0;
if (*foundstr == 'T' || *foundstr == 'P') // Tone/pulse dialing
foundstr++;
else if (*foundstr == 'L') { // Redial last number
if (modem->lastnumber[0] == 0)
modem_send_res(modem, ResERROR);
else {
modem_log("Redialing number %s\n", modem->lastnumber);
modem_dial(modem, modem->lastnumber);
}
return;
}
if ((!foundstr[0] && !modem->numberinprogress[0]) || ((strlen(modem->numberinprogress) + strlen(foundstr)) > (NUMBER_BUFFER_SIZE - 1))) {
// Check for empty or too long strings
modem_send_res(modem, ResERROR);
modem->numberinprogress[0] = 0;
return;
}
foundstr = trim(foundstr);
// Check for ; and return to command mode if found
char *semicolon = strchr(foundstr, ';');
if (semicolon != NULL) {
modem_log("Semicolon found in number, returning to command mode\n");
strncat(modem->numberinprogress, foundstr, strcspn(foundstr, ";"));
scanbuf = semicolon + 1;
break;
} else {
strcat(modem->numberinprogress, foundstr);
foundstr = modem->numberinprogress;
}
modem_log("Dialing number %s\n", foundstr);
mappedaddr = modem_get_address_from_phonebook(modem, foundstr);
if (mappedaddr) {
modem_dial(modem, mappedaddr);
return;
}
if (strlen(foundstr) >= 12) {
// Check if supplied parameter only consists of digits
bool isNum = true;
size_t fl = strlen(foundstr);
for (i = 0; i < fl; i++)
if (foundstr[i] < '0' || foundstr[i] > '9')
isNum = false;
if (isNum && (fl > (NUMBER_BUFFER_SIZE - 5))) {
// Check if the number is long enough to cause buffer
// overflows during the number => IP transformation
modem_send_res(modem, ResERROR);
modem->numberinprogress[0] = 0;
return;
} else if (isNum) {
// Parameter is a number with at least 12 digits => this cannot
// be a valid IP/name
// Transform by adding dots
size_t j = 0;
const size_t foundlen = strlen(foundstr);
for (i = 0; i < foundlen; i++) {
buffer[j++] = foundstr[i];
// Add a dot after the third, sixth and ninth number
if (i == 2 || i == 5 || i == 8)
buffer[j++] = '.';
// If the string is longer than 12 digits,
// interpret the rest as port
if (i == 11 && foundlen > 12)
buffer[j++] = ':';
}
buffer[j] = 0;
foundstr = buffer;
// Remove Zeros from beginning of octets
size_t k = 0;
size_t foundlen2 = strlen(foundstr);
for (i = 0; i < foundlen2; i++) {
if (i == 0 && foundstr[0] == '0')
continue;
if (i == 1 && foundstr[0] == '0' && foundstr[1] == '0')
continue;
if (foundstr[i] == '0' && foundstr[i - 1] == '.')
continue;
if (foundstr[i] == '0' && foundstr[i - 1] == '0' && foundstr[i - 2] == '.')
continue;
obuffer[k++] = foundstr[i];
}
obuffer[k] = 0;
foundstr = obuffer;
}
}
modem_dial(modem, foundstr);
return;
}
case 'I': // Some strings about firmware
switch (modem_scan_number(&scanbuf)) {
case 3:
modem_send_line(modem, "86Box Emulated Modem Firmware V1.00");
break;
case 4:
modem_send_line(modem, "Modem compiled for 86Box version " EMU_VERSION);
break;
}
break;
case 'E': // Echo on/off
switch (modem_scan_number(&scanbuf)) {
case 0:
modem->echo = false;
break;
case 1:
modem->echo = true;
break;
}
break;
case 'V':
switch (modem_scan_number(&scanbuf)) {
case 0:
modem->numericresponse = true;
break;
case 1:
modem->numericresponse = false;
break;
}
break;
case 'H': // Hang up
switch (modem_scan_number(&scanbuf)) {
case 0:
modem->numberinprogress[0] = 0;
if (modem->connected) {
modem_send_res(modem, ResNOCARRIER);
modem_enter_idle_state(modem);
return;
}
// else return ok
}
break;
case 'O': // Return to data mode
switch (modem_scan_number(&scanbuf)) {
case 0:
if (modem->connected) {
modem->mode = MODEM_MODE_DATA;
return;
} else {
modem_send_res(modem, ResERROR);
return;
}
}
break;
case 'T': // Tone Dial
case 'P': // Pulse Dial
break;
case 'M': // Monitor
case 'L': // Volume
case 'W':
case 'X':
modem_scan_number(&scanbuf);
break;
case 'A': // Answer call
{
if (modem->waitingclientsocket == -1) {
modem_send_res(modem, ResERROR);
return;
}
modem_accept_incoming_call(modem);
break;
}
return;
case 'Z':
{ // Reset and load profiles
// scan the number away, if any
modem_scan_number(&scanbuf);
if (modem->connected)
modem_send_res(modem, ResNOCARRIER);
modem_reset(modem);
break;
}
case ' ': // skip space
break;
case 'Q':
{
// Response options
// 0 = all on, 1 = all off,
// 2 = no ring and no connect/carrier in answermode
const uint32_t val = modem_scan_number(&scanbuf);
if (!(val > 2)) {
modem->doresponse = val;
break;
} else {
modem_send_res(modem, ResERROR);
return;
}
}
case 'S':
{ // Registers
const uint32_t index = modem_scan_number(&scanbuf);
if (index >= 100) {
modem_send_res(modem, ResERROR);
return; // goto ret_none;
}
while (scanbuf[0] == ' ')
scanbuf++; // skip spaces
if (scanbuf[0] == '=') { // set register
scanbuf++;
while (scanbuf[0] == ' ')
scanbuf++; // skip spaces
const uint32_t val = modem_scan_number(&scanbuf);
modem->reg[index] = val;
break;
} else if (scanbuf[0] == '?') { // get register
modem_send_number(modem, modem->reg[index]);
scanbuf++;
break;
}
// else
// LOG_MSG("SERIAL: Port %" PRIu8 " print reg %" PRIu32
// " with %" PRIu8 ".",
// GetPortNumber(), index, reg[index]);
}
break;
case '&':
{ // & escaped commands
char cmdchar = modem_fetch_character(&scanbuf);
switch (cmdchar) {
case 'C':
{
const uint32_t val = modem_scan_number(&scanbuf);
if (val < 2)
modem->dcdmode = val;
else {
modem_send_res(modem, ResERROR);
return;
}
break;
}
case 'K':
{
const uint32_t val = modem_scan_number(&scanbuf);
if (val < 5)
modem->flowcontrol = val;
else {
modem_send_res(modem, ResERROR);
return;
}
break;
}
case 'D':
{
const uint32_t val = modem_scan_number(&scanbuf);
if (val < 4)
modem->dtrmode = val;
else {
modem_send_res(modem, ResERROR);
return;
}
break;
}
case '\0':
// end of string
modem_send_res(modem, ResERROR);
return;
}
break;
}
break;
case '\\':
{ // \ escaped commands
char cmdchar = modem_fetch_character(&scanbuf);
switch (cmdchar) {
case 'N':
// error correction stuff - not emulated
if (modem_scan_number(&scanbuf) > 5) {
modem_send_res(modem, ResERROR);
return;
}
break;
case '\0':
// end of string
modem_send_res(modem, ResERROR);
return;
}
break;
}
case '%': // % escaped commands
// Windows 98 modem prober sends unknown command AT%V
modem_send_res(modem, ResERROR);
return;
case '\0':
modem_send_res(modem, ResOK);
return;
}
}
}
void
modem_dtr_callback_timer(void *priv)
{
modem_t *dev = (modem_t *) priv;
if (dev->connected) {
switch (dev->dtrmode) {
case 1:
modem_log("DTR dropped, returning to command mode (dtrmode = %i)\n", dev->dtrmode);
dev->mode = MODEM_MODE_COMMAND;
break;
case 2:
modem_log("DTR dropped, hanging up (dtrmode = %i)\n", dev->dtrmode);
modem_send_res(dev, ResNOCARRIER);
modem_enter_idle_state(dev);
break;
case 3:
modem_log("DTR dropped, resetting modem (dtrmode = %i)\n", dev->dtrmode);
modem_send_res(dev, ResNOCARRIER);
modem_reset(dev);
break;
}
}
}
void
modem_dtr_callback(serial_t *serial, int status, void *priv)
{
modem_t *dev = (modem_t *) priv;
dev->dtrstate = !!status;
if (status == 1)
timer_disable(&dev->dtr_timer);
else if (!timer_is_enabled(&dev->dtr_timer))
timer_on_auto(&dev->dtr_timer, 1000000);
}
static void
fifo8_resize_2x(Fifo8 *fifo)
{
uint32_t pos = 0;
uint32_t size = fifo->capacity * 2;
uint32_t used = fifo8_num_used(fifo);
if (!used)
return;
uint8_t *temp_buf = calloc(fifo->capacity * 2, 1);
if (!temp_buf) {
fatal("net_modem: Out Of Memory!\n");
}
while (!fifo8_is_empty(fifo)) {
temp_buf[pos] = fifo8_pop(fifo);
pos++;
}
pos = 0;
fifo8_destroy(fifo);
fifo8_create(fifo, size);
fifo8_push_all(fifo, temp_buf, used);
free(temp_buf);
}
#define TEL_CLIENT 0
#define TEL_SERVER 1
void
modem_process_telnet(modem_t *modem, uint8_t *data, uint32_t size)
{
uint32_t i = 0;
for (i = 0; i < size; i++) {
uint8_t c = data[i];
if (modem->telClient.inIAC) {
if (modem->telClient.recCommand) {
if ((c != 0) && (c != 1) && (c != 3)) {
if (modem->telClient.command > 250) {
/* Reject anything we don't recognize */
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 252);
modem_data_mode_process_byte(modem, c); /* We won't do crap! */
}
}
switch (modem->telClient.command) {
case 251: /* Will */
if (c == 0)
modem->telClient.binary[TEL_SERVER] = true;
if (c == 1)
modem->telClient.echo[TEL_SERVER] = true;
if (c == 3)
modem->telClient.supressGA[TEL_SERVER] = true;
break;
case 252: /* Won't */
if (c == 0)
modem->telClient.binary[TEL_SERVER] = false;
if (c == 1)
modem->telClient.echo[TEL_SERVER] = false;
if (c == 3)
modem->telClient.supressGA[TEL_SERVER] = false;
break;
case 253: /* Do */
if (c == 0) {
modem->telClient.binary[TEL_CLIENT] = true;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 251);
modem_data_mode_process_byte(modem, 0); /* Will do binary transfer */
}
if (c == 1) {
modem->telClient.echo[TEL_CLIENT] = false;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 252);
modem_data_mode_process_byte(modem, 1); /* Won't echo (too lazy) */
}
if (c == 3) {
modem->telClient.supressGA[TEL_CLIENT] = true;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 251);
modem_data_mode_process_byte(modem, 3); /* Will Suppress GA */
}
break;
case 254: /* Don't */
if (c == 0) {
modem->telClient.binary[TEL_CLIENT] = false;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 252);
modem_data_mode_process_byte(modem, 0); /* Won't do binary transfer */
}
if (c == 1) {
modem->telClient.echo[TEL_CLIENT] = false;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 252);
modem_data_mode_process_byte(modem, 1); /* Won't echo (fine by me) */
}
if (c == 3) {
modem->telClient.supressGA[TEL_CLIENT] = true;
modem_data_mode_process_byte(modem, 0xff);
modem_data_mode_process_byte(modem, 251);
modem_data_mode_process_byte(modem, 3); /* Will Suppress GA (too lazy) */
}
break;
default:
break;
}
modem->telClient.inIAC = false;
modem->telClient.recCommand = false;
continue;
} else {
if (c == 249) {
/* Go Ahead received */
modem->telClient.inIAC = false;
continue;
}
modem->telClient.command = c;
modem->telClient.recCommand = true;
if ((modem->telClient.binary[TEL_SERVER]) && (c == 0xff)) {
/* Binary data with value of 255 */
modem->telClient.inIAC = false;
modem->telClient.recCommand = false;
fifo8_push(&modem->rx_data, 0xff);
continue;
}
}
} else {
if (c == 0xff) {
modem->telClient.inIAC = true;
continue;
}
fifo8_push(&modem->rx_data, c);
}
}
}
static int
modem_rx(void *priv, uint8_t *buf, int io_len)
{
modem_t *modem = (modem_t *) priv;
uint32_t i = 0;
if (modem->tcpIpMode)
return 0;
if (!modem->connected) {
/* Drop packet. */
modem_log("Dropping %d bytes\n", io_len - 14);
return 0;
}
while ((io_len) >= (fifo8_num_free(&modem->rx_data) / 2)) {
fifo8_resize_2x(&modem->rx_data);
}
if (!(buf[12] == 0x08 && buf[13] == 0x00)) {
modem_log("Dropping %d bytes (non-IP packet (ethtype 0x%02X%02X))\n", io_len - 14, buf[12], buf[13]);
return 0;
}
modem_log("Receiving %d bytes\n", io_len - 14);
/* Strip the Ethernet header. */
io_len -= 14;
buf += 14;
fifo8_push(&modem->rx_data, END);
for (i = 0; i < io_len; i++) {
switch (buf[i]) {
case END:
fifo8_push(&modem->rx_data, ESC);
fifo8_push(&modem->rx_data, ESC_END);
break;
case ESC:
fifo8_push(&modem->rx_data, ESC);
fifo8_push(&modem->rx_data, ESC_ESC);
break;
default:
fifo8_push(&modem->rx_data, buf[i]);
break;
}
}
fifo8_push(&modem->rx_data, END);
return 1;
}
static void
modem_rcr_cb(UNUSED(struct serial_s *serial), void *priv)
{
modem_t *dev = (modem_t *) priv;
timer_stop(&dev->host_to_serial_timer);
/* FIXME: do something to dev->baudrate */
timer_on_auto(&dev->host_to_serial_timer, (1000000.0 / (double) dev->baudrate) * (double) 9);
#if 0
serial_clear_fifo(dev->serial);
#endif
}
static void
modem_accept_incoming_call(modem_t *modem)
{
if (modem->waitingclientsocket != -1) {
modem->clientsocket = modem->waitingclientsocket;
modem->waitingclientsocket = -1;
modem_enter_connected_state(modem);
modem->in_warmup = 250;
} else {
modem_enter_idle_state(modem);
}
}
static void
modem_cmdpause_timer_callback(void *priv)
{
modem_t *modem = (modem_t *) priv;
uint32_t guard_threshold = 0;
timer_on_auto(&modem->cmdpause_timer, 1000);
if (modem->tcpIpConnInProgress) {
do {
int status = plat_netsocket_connected(modem->clientsocket);
if (status == -1) {
plat_netsocket_close(modem->clientsocket);
modem->clientsocket = -1;
modem_enter_idle_state(modem);
modem_send_res(modem, ResNOCARRIER);
modem->tcpIpConnInProgress = 0;
break;
} else if (status == 1) {
modem_enter_connected_state(modem);
modem->tcpIpConnInProgress = 0;
break;
}
modem->tcpIpConnCounter++;
if (status < 0 || (status == 0 && modem->tcpIpConnCounter >= 5000)) {
plat_netsocket_close(modem->clientsocket);
modem->clientsocket = -1;
modem_enter_idle_state(modem);
modem_send_res(modem, ResNOANSWER);
modem->tcpIpConnInProgress = 0;
modem->tcpIpMode = 0;
break;
}
} while (0);
}
if (!modem->connected && modem->waitingclientsocket == -1 && modem->serversocket != -1) {
modem->waitingclientsocket = plat_netsocket_accept(modem->serversocket);
if (modem->waitingclientsocket != -1) {
if (modem->dtrstate == 0 && modem->dtrmode != 0) {
modem_enter_idle_state(modem);
} else {
modem->ringing = true;
modem_send_res(modem, ResRING);
serial_set_ri(modem->serial, !serial_get_ri(modem->serial));
modem->ringtimer = 3000;
modem->reg[MREG_RING_COUNT] = 0;
}
}
}
if (modem->ringing) {
if (modem->ringtimer <= 0) {
modem->reg[MREG_RING_COUNT]++;
if ((modem->reg[MREG_AUTOANSWER_COUNT] > 0) && (modem->reg[MREG_RING_COUNT] >= modem->reg[MREG_AUTOANSWER_COUNT])) {
modem_accept_incoming_call(modem);
return;
}
modem_send_res(modem, ResRING);
serial_set_ri(modem->serial, !serial_get_ri(modem->serial));
modem->ringtimer = 3000;
}
--modem->ringtimer;
}
if (modem->in_warmup) {
modem->in_warmup--;
if (modem->in_warmup == 0) {
modem->tx_count = 0;
fifo8_reset(&modem->rx_data);
}
} else if (modem->connected && modem->tcpIpMode) {
if (modem->tx_count) {
int wouldblock = 0;
int res = plat_netsocket_send(modem->clientsocket, modem->tx_pkt_ser_line, modem->tx_count, &wouldblock);
if (res <= 0 && !wouldblock) {
/* No bytes sent or error. */
modem->tx_count = 0;
modem_enter_idle_state(modem);
modem_send_res(modem, ResNOCARRIER);
} else if (res > 0) {
if (res == modem->tx_count) {
modem->tx_count = 0;
} else {
memmove(modem->tx_pkt_ser_line, &modem->tx_pkt_ser_line[res], modem->tx_count - res);
modem->tx_count -= res;
}
}
}
if (modem->connected) {
uint8_t buffer[16];
int wouldblock = 0;
int res = plat_netsocket_receive(modem->clientsocket, buffer, sizeof(buffer), &wouldblock);
if (res > 0) {
if (modem->telnet_mode)
modem_process_telnet(modem, buffer, res);
else
fifo8_push_all(&modem->rx_data, buffer, res);
} else if (res == 0) {
modem->tx_count = 0;
modem_enter_idle_state(modem);
modem_send_res(modem, ResNOCARRIER);
} else if (!wouldblock) {
modem->tx_count = 0;
modem_enter_idle_state(modem);
modem_send_res(modem, ResNOCARRIER);
}
}
}
modem->cmdpause++;
guard_threshold = (uint32_t) (modem->reg[MREG_GUARD_TIME] * 20);
if (modem->cmdpause > guard_threshold) {
if (modem->plusinc == 0) {
modem->plusinc = 1;
} else if (modem->plusinc == 4) {
modem_log("Escape sequence triggered, returning to command mode\n");
modem->mode = MODEM_MODE_COMMAND;
modem_send_res(modem, ResOK);
modem->plusinc = 0;
}
}
}
/* Initialize the device for use by the user. */
static void *
modem_init(const device_t *info)
{
modem_t *modem = (modem_t *) calloc(1, sizeof(modem_t));
const char *phonebook_file = NULL;
memset(modem->mac, 0xfc, 6);
modem->port = device_get_config_int("port");
modem->baudrate = device_get_config_int("baudrate");
modem->listen_port = device_get_config_int("listen_port");
modem->telnet_mode = device_get_config_int("telnet_mode");
modem->clientsocket = modem->serversocket = modem->waitingclientsocket = -1;
fifo8_create(&modem->data_pending, 0x20000);
fifo8_create(&modem->rx_data, 0x20000);
timer_add(&modem->dtr_timer, modem_dtr_callback_timer, modem, 0);
timer_add(&modem->host_to_serial_timer, host_to_modem_cb, modem, 0);
timer_add(&modem->cmdpause_timer, modem_cmdpause_timer_callback, modem, 0);
timer_on_auto(&modem->cmdpause_timer, 1000);
modem->serial = serial_attach_ex_2(modem->port, modem_rcr_cb, modem_write, modem_dtr_callback, modem);
modem_reset(modem);
modem->card = network_attach(modem, modem->mac, modem_rx, NULL);
phonebook_file = device_get_config_string("phonebook_file");
if (phonebook_file && phonebook_file[0] != 0) {
modem_read_phonebook_file(modem, phonebook_file);
}
return modem;
}
void
modem_close(void *priv)
{
modem_t *modem = (modem_t *) priv;
modem->listen_port = 0;
modem_reset(modem);
fifo8_destroy(&modem->data_pending);
fifo8_destroy(&modem->rx_data);
netcard_close(modem->card);
free(priv);
}
// clang-format off
static const device_config_t modem_config[] = {
{
.name = "port",
.description = "Serial Port",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "COM1", .value = 0 },
{ .description = "COM2", .value = 1 },
{ .description = "COM3", .value = 2 },
{ .description = "COM4", .value = 3 },
{ .description = "" }
}
},
{
.name = "baudrate",
.description = "Baud Rate",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 115200,
.file_filter = NULL,
.spinner = { 0 },
.selection = {
{ .description = "115200", .value = 115200 },
{ .description = "57600", .value = 57600 },
{ .description = "56000", .value = 56000 },
{ .description = "38400", .value = 38400 },
{ .description = "19200", .value = 19200 },
{ .description = "14400", .value = 14400 },
{ .description = "9600", .value = 9600 },
{ .description = "7200", .value = 7200 },
{ .description = "4800", .value = 4800 },
{ .description = "2400", .value = 2400 },
{ .description = "1800", .value = 1800 },
{ .description = "1200", .value = 1200 },
{ .description = "600", .value = 600 },
{ .description = "300", .value = 300 },
}
},
{
.name = "listen_port",
.description = "TCP/IP listening port",
.type = CONFIG_SPINNER,
.spinner =
{
.min = 0,
.max = 32767
},
.default_int = 0
},
{
.name = "phonebook_file",
.description = "Phonebook File",
.type = CONFIG_FNAME,
.default_string = "",
.file_filter = "Text files (*.txt)|*.txt"
},
{
.name = "telnet_mode",
.description = "Telnet emulation",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 0
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t modem_device = {
.name = "Standard Hayes-compliant Modem",
.internal_name = "modem",
.flags = DEVICE_COM,
.local = 0,
.init = modem_init,
.close = modem_close,
.reset = NULL,
{ .poll = NULL },
.speed_changed = modem_speed_changed,
.force_redraw = NULL,
.config = modem_config
};
``` | /content/code_sandbox/src/network/net_modem.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 12,876 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Handle WinPcap library processing.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdbool.h>
#ifdef _WIN32
# define WIN32_LEAN_AND_MEAN
# include <windows.h>
# include <winsock2.h>
#else
# include <poll.h>
# include <unistd.h>
# include <fcntl.h>
# include <sys/select.h>
#endif
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/plat_dynld.h>
#include <86box/thread.h>
#include <86box/timer.h>
#include <86box/network.h>
#include <86box/net_event.h>
#define PCAP_PKT_BATCH NET_QUEUE_LEN
enum {
NET_EVENT_STOP = 0,
NET_EVENT_TX,
NET_EVENT_RX,
NET_EVENT_MAX
};
#ifdef __APPLE__
# include <pcap/pcap.h>
#else
typedef int bpf_int32;
typedef unsigned int bpf_u_int32;
/*
* The instruction data structure.
*/
struct bpf_insn {
unsigned short code;
unsigned char jt;
unsigned char jf;
bpf_u_int32 k;
};
/*
* Structure for "pcap_compile()", "pcap_setfilter()", etc..
*/
struct bpf_program {
unsigned int bf_len;
struct bpf_insn *bf_insns;
};
typedef struct pcap_if pcap_if_t;
# define PCAP_ERRBUF_SIZE 256
struct pcap_pkthdr {
struct timeval ts;
bpf_u_int32 caplen;
bpf_u_int32 len;
};
struct pcap_if {
struct pcap_if *next;
char *name;
char *description;
void *addresses;
bpf_u_int32 flags;
};
struct pcap_send_queue {
unsigned int maxlen; /* Maximum size of the queue, in bytes. This
variable contains the size of the buffer field. */
unsigned int len; /* Current size of the queue, in bytes. */
char *buffer; /* Buffer containing the packets to be sent. */
};
typedef struct pcap_send_queue pcap_send_queue;
typedef void (*pcap_handler)(unsigned char *user, const struct pcap_pkthdr *h, const unsigned char *bytes);
#endif
typedef struct {
void *pcap; /* handle to pcap lib instance */
netcard_t *card; /* netcard linked to us */
thread_t *poll_tid;
net_evt_t tx_event;
net_evt_t stop_event;
netpkt_t pkt;
netpkt_t pktv[PCAP_PKT_BATCH];
uint8_t mac_addr[6];
#ifdef _WIN32
struct pcap_send_queue *pcap_queue;
#endif
} net_pcap_t;
typedef struct {
char *intf_name;
uint8_t *mac_addr;
} net_pcap_params_t;
static volatile void *libpcap_handle; /* handle to WinPcap DLL */
/* Pointers to the real functions. */
static const char *(*f_pcap_lib_version)(void);
static int (*f_pcap_findalldevs)(pcap_if_t **, char *);
static void (*f_pcap_freealldevs)(void *);
static void *(*f_pcap_open_live)(const char *, int, int, int, char *);
static int (*f_pcap_compile)(void *, void *, const char *, int, bpf_u_int32);
static int (*f_pcap_setfilter)(void *, void *);
static const unsigned char
*(*f_pcap_next)(void *, void *);
static int (*f_pcap_sendpacket)(void *, const unsigned char *, int);
static void (*f_pcap_close)(void *);
static int (*f_pcap_setnonblock)(void *, int, char *);
static int (*f_pcap_set_immediate_mode)(void *, int);
static int (*f_pcap_set_promisc)(void *, int);
static int (*f_pcap_set_snaplen)(void *, int);
static int (*f_pcap_dispatch)(void *, int, pcap_handler callback, unsigned char *user);
static void *(*f_pcap_create)(const char *, char *);
static int (*f_pcap_activate)(void *);
static void *(*f_pcap_geterr)(void *);
#ifdef _WIN32
static HANDLE (*f_pcap_getevent)(void *);
static int (*f_pcap_sendqueue_queue)(void *, void *, void *);
static unsigned int (*f_pcap_sendqueue_transmit)(void *, void *, int sync);
static void *(*f_pcap_sendqueue_alloc)(unsigned int memsize);
static void (*f_pcap_sendqueue_destroy)(void *);
#else
static int (*f_pcap_get_selectable_fd)(void *);
#endif
static dllimp_t pcap_imports[] = {
{"pcap_lib_version", &f_pcap_lib_version },
{ "pcap_findalldevs", &f_pcap_findalldevs },
{ "pcap_freealldevs", &f_pcap_freealldevs },
{ "pcap_open_live", &f_pcap_open_live },
{ "pcap_compile", &f_pcap_compile },
{ "pcap_setfilter", &f_pcap_setfilter },
{ "pcap_next", &f_pcap_next },
{ "pcap_sendpacket", &f_pcap_sendpacket },
{ "pcap_close", &f_pcap_close },
{ "pcap_setnonblock", &f_pcap_setnonblock },
{ "pcap_set_immediate_mode", &f_pcap_set_immediate_mode},
{ "pcap_set_promisc", &f_pcap_set_promisc },
{ "pcap_set_snaplen", &f_pcap_set_snaplen },
{ "pcap_dispatch", &f_pcap_dispatch },
{ "pcap_create", &f_pcap_create },
{ "pcap_activate", &f_pcap_activate },
{ "pcap_geterr", &f_pcap_geterr },
#ifdef _WIN32
{ "pcap_getevent", &f_pcap_getevent },
{ "pcap_sendqueue_queue", &f_pcap_sendqueue_queue },
{ "pcap_sendqueue_transmit", &f_pcap_sendqueue_transmit},
{ "pcap_sendqueue_alloc", &f_pcap_sendqueue_alloc },
{ "pcap_sendqueue_destroy", &f_pcap_sendqueue_destroy },
#else
{ "pcap_get_selectable_fd", &f_pcap_get_selectable_fd },
#endif
{ NULL, NULL },
};
#ifdef ENABLE_PCAP_LOG
int pcap_do_log = ENABLE_PCAP_LOG;
static void
pcap_log(const char *fmt, ...)
{
va_list ap;
if (pcap_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pcap_log(fmt, ...)
#endif
static void
net_pcap_rx_handler(uint8_t *user, const struct pcap_pkthdr *h, const uint8_t *bytes)
{
net_pcap_t *pcap = (net_pcap_t *) user;
memcpy(pcap->pkt.data, bytes, h->caplen);
pcap->pkt.len = h->caplen;
network_rx_put_pkt(pcap->card, &pcap->pkt);
}
/* Send a packet to the Pcap interface. */
void
net_pcap_in(void *pcap, uint8_t *bufp, int len)
{
if (pcap == NULL)
return;
f_pcap_sendpacket(pcap, bufp, len);
}
void
net_pcap_in_available(void *priv)
{
net_pcap_t *pcap = (net_pcap_t *) priv;
net_event_set(&pcap->tx_event);
}
#ifdef _WIN32
static void
net_pcap_thread(void *priv)
{
net_pcap_t *pcap = (net_pcap_t *) priv;
pcap_log("PCAP: polling started.\n");
HANDLE events[NET_EVENT_MAX];
events[NET_EVENT_STOP] = net_event_get_handle(&pcap->stop_event);
events[NET_EVENT_TX] = net_event_get_handle(&pcap->tx_event);
events[NET_EVENT_RX] = f_pcap_getevent(pcap->pcap);
bool run = true;
struct pcap_pkthdr h;
while (run) {
int ret = WaitForMultipleObjects(NET_EVENT_MAX, events, FALSE, INFINITE);
switch (ret - WAIT_OBJECT_0) {
case NET_EVENT_STOP:
net_event_clear(&pcap->stop_event);
run = false;
break;
case NET_EVENT_TX:
net_event_clear(&pcap->tx_event);
int packets = network_tx_popv(pcap->card, pcap->pktv, PCAP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
h.caplen = pcap->pktv[i].len;
f_pcap_sendqueue_queue(pcap->pcap_queue, &h, pcap->pktv[i].data);
}
f_pcap_sendqueue_transmit(pcap->pcap, pcap->pcap_queue, 0);
pcap->pcap_queue->len = 0;
break;
case NET_EVENT_RX:
f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (unsigned char *) pcap);
break;
default:
break;
}
}
pcap_log("PCAP: polling stopped.\n");
}
#else
static void
net_pcap_thread(void *priv)
{
net_pcap_t *pcap = (net_pcap_t *) priv;
pcap_log("PCAP: polling started.\n");
struct pollfd pfd[NET_EVENT_MAX];
pfd[NET_EVENT_STOP].fd = net_event_get_fd(&pcap->stop_event);
pfd[NET_EVENT_STOP].events = POLLIN | POLLPRI;
pfd[NET_EVENT_TX].fd = net_event_get_fd(&pcap->tx_event);
pfd[NET_EVENT_TX].events = POLLIN | POLLPRI;
pfd[NET_EVENT_RX].fd = f_pcap_get_selectable_fd((void *) pcap->pcap);
pfd[NET_EVENT_RX].events = POLLIN | POLLPRI;
/* As long as the channel is open.. */
while (1) {
poll(pfd, NET_EVENT_MAX, -1);
if (pfd[NET_EVENT_STOP].revents & POLLIN) {
net_event_clear(&pcap->stop_event);
break;
}
if (pfd[NET_EVENT_TX].revents & POLLIN) {
net_event_clear(&pcap->tx_event);
int packets = network_tx_popv(pcap->card, pcap->pktv, PCAP_PKT_BATCH);
for (int i = 0; i < packets; i++) {
net_pcap_in(pcap->pcap, pcap->pktv[i].data, pcap->pktv[i].len);
}
}
if (pfd[NET_EVENT_RX].revents & POLLIN) {
f_pcap_dispatch(pcap->pcap, PCAP_PKT_BATCH, net_pcap_rx_handler, (unsigned char *) pcap);
}
}
pcap_log("PCAP: polling stopped.\n");
}
#endif
/*
* Prepare the (Win)Pcap module for use.
*
* This is called only once, during application init,
* to check for availability of PCAP, and to retrieve
* a list of (usable) intefaces for it.
*/
int
net_pcap_prepare(netdev_t *list)
{
char errbuf[PCAP_ERRBUF_SIZE];
pcap_if_t *devlist;
int i = 0;
/* Try loading the DLL. */
#ifdef _WIN32
/* Add the Npcap directory to the DLL search path. */
char npcap_dir[512];
GetSystemDirectoryA(npcap_dir, 480);
strcat(npcap_dir, "\\Npcap");
SetDllDirectoryA(npcap_dir);
libpcap_handle = dynld_module("wpcap.dll", pcap_imports);
SetDllDirectoryA(NULL); /* reset the DLL search path */
#elif defined __APPLE__
libpcap_handle = dynld_module("libpcap.dylib", pcap_imports);
#else
libpcap_handle = dynld_module("libpcap.so", pcap_imports);
#endif
if (libpcap_handle == NULL) {
pcap_log("PCAP: error loading pcap module\n");
return (-1);
}
/* Retrieve the device list from the local machine */
if (f_pcap_findalldevs(&devlist, errbuf) == -1) {
pcap_log("PCAP: error in pcap_findalldevs: %s\n", errbuf);
return (-1);
}
for (pcap_if_t *dev = devlist; dev != NULL; dev = dev->next) {
if (i >= (NET_HOST_INTF_MAX - 1))
break;
/**
* we initialize the strings to NULL first for strncpy
*/
memset(list->device, '\0', sizeof(list->device));
memset(list->description, '\0', sizeof(list->description));
strncpy(list->device, dev->name, sizeof(list->device) - 1);
if (dev->description) {
strncpy(list->description, dev->description, sizeof(list->description) - 1);
} else {
/* if description is NULL, set the name. This allows pcap to display *something* useful under WINE */
strncpy(list->description, dev->name, sizeof(list->description) - 1);
}
list++;
i++;
}
/* Release the memory. */
f_pcap_freealldevs(devlist);
return i;
}
/*
* Copy error message to the error buffer
* and log if enabled.
*/
void net_pcap_error(char *errbuf, const char *message) {
strncpy(errbuf, message, NET_DRV_ERRBUF_SIZE);
pcap_log("PCAP: %s\n", message);
}
/*
* Initialize (Win)Pcap for use.
*
* We already know we have PCAP available, as this
* is called when the network activates itself and
* tries to attach to the network module.
*/
void *
net_pcap_init(const netcard_t *card, const uint8_t *mac_addr, void *priv, char *netdrv_errbuf)
{
char errbuf[PCAP_ERRBUF_SIZE];
char *str;
char filter_exp[255];
struct bpf_program fp;
char errbuf_prep[NET_DRV_ERRBUF_SIZE];
char *intf_name = (char *) priv;
/* Did we already load the library? */
if (libpcap_handle == NULL) {
net_pcap_error(netdrv_errbuf, "net_pcap_init without handle");
return NULL;
}
/* Get the PCAP library name and version. */
strcpy(errbuf, f_pcap_lib_version());
str = strchr(errbuf, '(');
if (str != NULL)
*(str - 1) = '\0';
pcap_log("PCAP: initializing, %s\n", errbuf);
/* Get the value of our capture interface. */
if ((intf_name[0] == '\0') || !strcmp(intf_name, "none")) {
net_pcap_error(netdrv_errbuf, "No interface configured");
return NULL;
}
pcap_log("PCAP: interface: %s\n", intf_name);
net_pcap_t *pcap = calloc(1, sizeof(net_pcap_t));
pcap->card = (netcard_t *) card;
memcpy(pcap->mac_addr, mac_addr, sizeof(pcap->mac_addr));
if ((pcap->pcap = f_pcap_create(intf_name, errbuf)) == NULL) {
snprintf(errbuf_prep, NET_DRV_ERRBUF_SIZE, " Unable to open device: %s!\n", intf_name);
net_pcap_error(netdrv_errbuf, errbuf_prep);
free(pcap);
return NULL;
}
if (f_pcap_setnonblock(pcap->pcap, 1, errbuf) != 0)
pcap_log("PCAP: failed nonblock %s\n", errbuf);
if (f_pcap_set_immediate_mode(pcap->pcap, 1) != 0)
pcap_log("PCAP: error setting immediate mode\n");
if (f_pcap_set_promisc(pcap->pcap, 1) != 0)
pcap_log("PCAP: error enabling promiscuous mode\n");
if (f_pcap_set_snaplen(pcap->pcap, NET_MAX_FRAME) != 0)
pcap_log("PCAP: error setting snaplen\n");
if (f_pcap_activate(pcap->pcap) != 0) {
snprintf(errbuf_prep, NET_DRV_ERRBUF_SIZE, "%s", (char *)f_pcap_geterr(pcap->pcap));
net_pcap_error(netdrv_errbuf, errbuf_prep);
f_pcap_close(pcap->pcap);
free(pcap);
return NULL;
}
/* Create a MAC address based packet filter. */
pcap_log("PCAP: installing filter for MAC=%02x:%02x:%02x:%02x:%02x:%02x\n",
mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
sprintf(filter_exp,
"( ((ether broadcast) or (ether multicast) or (ether dst %02x:%02x:%02x:%02x:%02x:%02x)) and not (ether src %02x:%02x:%02x:%02x:%02x:%02x) )",
mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5],
mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
if (f_pcap_compile(pcap->pcap, &fp, filter_exp, 0, 0xffffffff) != -1) {
if (f_pcap_setfilter(pcap->pcap, &fp) != 0) {
snprintf(errbuf_prep, NET_DRV_ERRBUF_SIZE, "Error installing filter (%s)\n", filter_exp);
net_pcap_error(netdrv_errbuf, errbuf_prep);
f_pcap_close(pcap->pcap);
free(pcap);
return NULL;
}
} else {
snprintf(errbuf_prep, NET_DRV_ERRBUF_SIZE, "Could not compile filter (%s) : %s!\n", filter_exp, (char *)f_pcap_geterr(pcap->pcap));
net_pcap_error(netdrv_errbuf, errbuf_prep);
f_pcap_close(pcap->pcap);
free(pcap);
return NULL;
}
#ifdef _WIN32
pcap->pcap_queue = f_pcap_sendqueue_alloc(PCAP_PKT_BATCH * NET_MAX_FRAME);
#endif
for (int i = 0; i < PCAP_PKT_BATCH; i++) {
pcap->pktv[i].data = calloc(1, NET_MAX_FRAME);
}
pcap->pkt.data = calloc(1, NET_MAX_FRAME);
net_event_init(&pcap->tx_event);
net_event_init(&pcap->stop_event);
pcap->poll_tid = thread_create(net_pcap_thread, pcap);
return pcap;
}
/* Close up shop. */
void
net_pcap_close(void *priv)
{
if (!priv)
return;
net_pcap_t *pcap = (net_pcap_t *) priv;
pcap_log("PCAP: closing.\n");
/* Tell the thread to terminate. */
net_event_set(&pcap->stop_event);
/* Wait for the thread to finish. */
pcap_log("PCAP: waiting for thread to end...\n");
thread_wait(pcap->poll_tid);
pcap_log("PCAP: thread ended\n");
for (int i = 0; i < PCAP_PKT_BATCH; i++) {
free(pcap->pktv[i].data);
}
free(pcap->pkt.data);
#ifdef _WIN32
f_pcap_sendqueue_destroy((void *) pcap->pcap_queue);
#endif
/* OK, now shut down Pcap itself. */
f_pcap_close(pcap->pcap);
net_event_close(&pcap->tx_event);
net_event_close(&pcap->stop_event);
free(pcap);
}
const netdrv_t net_pcap_drv = {
&net_pcap_in_available,
&net_pcap_init,
&net_pcap_close,
NULL
};
``` | /content/code_sandbox/src/network/net_pcap.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,050 |
```c
/*-
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Christos Zoulas.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
ssize_t
local_getdelim(char **buf, size_t *bufsiz, int delimiter, FILE *fp)
{
char *ptr, *eptr;
if (*buf == NULL || *bufsiz == 0) {
*bufsiz = BUFSIZ;
if ((*buf = malloc(*bufsiz)) == NULL)
return -1;
}
for (ptr = *buf, eptr = *buf + *bufsiz;;) {
int c = fgetc(fp);
if (c == -1) {
if (feof(fp)) {
ssize_t diff = (ssize_t)(ptr - *buf);
if (diff != 0) {
*ptr = '\0';
return diff;
}
}
return -1;
}
*ptr++ = c;
if (c == delimiter) {
*ptr = '\0';
return ptr - *buf;
}
if (ptr + 2 >= eptr) {
char *nbuf;
size_t nbufsiz = *bufsiz * 2;
ssize_t d = ptr - *buf;
if ((nbuf = realloc(*buf, nbufsiz)) == NULL)
return -1;
*buf = nbuf;
*bufsiz = nbufsiz;
eptr = nbuf + nbufsiz;
ptr = nbuf + d;
}
}
}
ssize_t
local_getline(char **buf, size_t *bufsiz, FILE *fp)
{
return local_getdelim(buf, bufsiz, '\n', fp);
}
``` | /content/code_sandbox/src/network/utils/getline.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 664 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of DECchip "Tulip" 21143 NIC.
*
* Authors: Sven Schnelle, <svens@stackframe.org>
* Cacodemon345,
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <string.h>
#include <stdio.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/random.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/dma.h>
#include <86box/device.h>
#include <86box/thread.h>
#include <86box/network.h>
#include <86box/net_eeprom_nmc93cxx.h>
#include <86box/bswap.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#define ROM_PATH_DEC21140 "roms/network/dec21140/BIOS13502.BIN"
#define CSR(_x) ((_x) << 3)
#define BIT(x) (1 << x)
#define CSR0_SWR BIT(0)
#define CSR0_BAR BIT(1)
#define CSR0_DSL_SHIFT 2
#define CSR0_DSL_MASK 0x1f
#define CSR0_BLE BIT(7)
#define CSR0_PBL_SHIFT 8
#define CSR0_PBL_MASK 0x3f
#define CSR0_CAC_SHIFT 14
#define CSR0_CAC_MASK 0x3
#define CSR0_DAS 0x10000
#define CSR0_TAP_SHIFT 17
#define CSR0_TAP_MASK 0x7
#define CSR0_DBO 0x100000
#define CSR1_TPD 0x01
#define CSR0_RLE BIT(23)
#define CSR0_WIE BIT(24)
#define CSR2_RPD 0x01
#define CSR5_TI BIT(0)
#define CSR5_TPS BIT(1)
#define CSR5_TU BIT(2)
#define CSR5_TJT BIT(3)
#define CSR5_LNP_ANC BIT(4)
#define CSR5_UNF BIT(5)
#define CSR5_RI BIT(6)
#define CSR5_RU BIT(7)
#define CSR5_RPS BIT(8)
#define CSR5_RWT BIT(9)
#define CSR5_ETI BIT(10)
#define CSR5_GTE BIT(11)
#define CSR5_LNF BIT(12)
#define CSR5_FBE BIT(13)
#define CSR5_ERI BIT(14)
#define CSR5_AIS BIT(15)
#define CSR5_NIS BIT(16)
#define CSR5_RS_SHIFT 17
#define CSR5_RS_MASK 7
#define CSR5_TS_SHIFT 20
#define CSR5_TS_MASK 7
#define CSR5_TS_STOPPED 0
#define CSR5_TS_RUNNING_FETCH 1
#define CSR5_TS_RUNNING_WAIT_EOT 2
#define CSR5_TS_RUNNING_READ_BUF 3
#define CSR5_TS_RUNNING_SETUP 5
#define CSR5_TS_SUSPENDED 6
#define CSR5_TS_RUNNING_CLOSE 7
#define CSR5_RS_STOPPED 0
#define CSR5_RS_RUNNING_FETCH 1
#define CSR5_RS_RUNNING_CHECK_EOR 2
#define CSR5_RS_RUNNING_WAIT_RECEIVE 3
#define CSR5_RS_SUSPENDED 4
#define CSR5_RS_RUNNING_CLOSE 5
#define CSR5_RS_RUNNING_FLUSH 6
#define CSR5_RS_RUNNING_QUEUE 7
#define CSR5_EB_SHIFT 23
#define CSR5_EB_MASK 7
#define CSR5_GPI BIT(26)
#define CSR5_LC BIT(27)
#define CSR6_HP BIT(0)
#define CSR6_SR BIT(1)
#define CSR6_HO BIT(2)
#define CSR6_PB BIT(3)
#define CSR6_IF BIT(4)
#define CSR6_SB BIT(5)
#define CSR6_PR BIT(6)
#define CSR6_PM BIT(7)
#define CSR6_FKD BIT(8)
#define CSR6_FD BIT(9)
#define CSR6_OM_SHIFT 10
#define CSR6_OM_MASK 3
#define CSR6_OM_NORMAL 0
#define CSR6_OM_INT_LOOPBACK 1
#define CSR6_OM_EXT_LOOPBACK 2
#define CSR6_FC BIT(12)
#define CSR6_ST BIT(13)
#define CSR6_TR_SHIFT 14
#define CSR6_TR_MASK 3
#define CSR6_TR_72 0
#define CSR6_TR_96 1
#define CSR6_TR_128 2
#define CSR6_TR_160 3
#define CSR6_CA BIT(17)
#define CSR6_RA BIT(30)
#define CSR6_SC BIT(31)
#define CSR7_TIM BIT(0)
#define CSR7_TSM BIT(1)
#define CSR7_TUM BIT(2)
#define CSR7_TJM BIT(3)
#define CSR7_LPM BIT(4)
#define CSR7_UNM BIT(5)
#define CSR7_RIM BIT(6)
#define CSR7_RUM BIT(7)
#define CSR7_RSM BIT(8)
#define CSR7_RWM BIT(9)
#define CSR7_TMM BIT(11)
#define CSR7_LFM BIT(12)
#define CSR7_SEM BIT(13)
#define CSR7_ERM BIT(14)
#define CSR7_AIM BIT(15)
#define CSR7_NIM BIT(16)
#define CSR8_MISSED_FRAME_OVL BIT(16)
#define CSR8_MISSED_FRAME_CNT_MASK 0xffff
#define CSR9_DATA_MASK 0xff
#define CSR9_SR_CS BIT(0)
#define CSR9_SR_SK BIT(1)
#define CSR9_SR_DI BIT(2)
#define CSR9_SR_DO BIT(3)
#define CSR9_REG BIT(10)
#define CSR9_SR BIT(11)
#define CSR9_BR BIT(12)
#define CSR9_WR BIT(13)
#define CSR9_RD BIT(14)
#define CSR9_MOD BIT(15)
#define CSR9_MDC BIT(16)
#define CSR9_MDO BIT(17)
#define CSR9_MII BIT(18)
#define CSR9_MDI BIT(19)
#define CSR11_CON BIT(16)
#define CSR11_TIMER_MASK 0xffff
#define CSR12_MRA BIT(0)
#define CSR12_LS100 BIT(1)
#define CSR12_LS10 BIT(2)
#define CSR12_APS BIT(3)
#define CSR12_ARA BIT(8)
#define CSR12_TRA BIT(9)
#define CSR12_NSN BIT(10)
#define CSR12_TRF BIT(11)
#define CSR12_ANS_SHIFT 12
#define CSR12_ANS_MASK 7
#define CSR12_LPN BIT(15)
#define CSR12_LPC_SHIFT 16
#define CSR12_LPC_MASK 0xffff
#define CSR13_SRL BIT(0)
#define CSR13_CAC BIT(2)
#define CSR13_AUI BIT(3)
#define CSR13_SDM_SHIFT 4
#define CSR13_SDM_MASK 0xfff
#define CSR14_ECEN BIT(0)
#define CSR14_LBK BIT(1)
#define CSR14_DREN BIT(2)
#define CSR14_LSE BIT(3)
#define CSR14_CPEN_SHIFT 4
#define CSR14_CPEN_MASK 3
#define CSR14_MBO BIT(6)
#define CSR14_ANE BIT(7)
#define CSR14_RSQ BIT(8)
#define CSR14_CSQ BIT(9)
#define CSR14_CLD BIT(10)
#define CSR14_SQE BIT(11)
#define CSR14_LTE BIT(12)
#define CSR14_APE BIT(13)
#define CSR14_SPP BIT(14)
#define CSR14_TAS BIT(15)
#define CSR15_JBD BIT(0)
#define CSR15_HUJ BIT(1)
#define CSR15_JCK BIT(2)
#define CSR15_ABM BIT(3)
#define CSR15_RWD BIT(4)
#define CSR15_RWR BIT(5)
#define CSR15_LE1 BIT(6)
#define CSR15_LV1 BIT(7)
#define CSR15_TSCK BIT(8)
#define CSR15_FUSQ BIT(9)
#define CSR15_FLF BIT(10)
#define CSR15_LSD BIT(11)
#define CSR15_DPST BIT(12)
#define CSR15_FRL BIT(13)
#define CSR15_LE2 BIT(14)
#define CSR15_LV2 BIT(15)
#define RDES0_OF BIT(0)
#define RDES0_CE BIT(1)
#define RDES0_DB BIT(2)
#define RDES0_RJ BIT(4)
#define RDES0_FT BIT(5)
#define RDES0_CS BIT(6)
#define RDES0_TL BIT(7)
#define RDES0_LS BIT(8)
#define RDES0_FS BIT(9)
#define RDES0_MF BIT(10)
#define RDES0_RF BIT(11)
#define RDES0_DT_SHIFT 12
#define RDES0_DT_MASK 3
#define RDES0_DE BIT(14)
#define RDES0_ES BIT(15)
#define RDES0_FL_SHIFT 16
#define RDES0_FL_MASK 0x3fff
#define RDES0_FF BIT(30)
#define RDES0_OWN BIT(31)
#define RDES1_BUF1_SIZE_SHIFT 0
#define RDES1_BUF1_SIZE_MASK 0x7ff
#define RDES1_BUF2_SIZE_SHIFT 11
#define RDES1_BUF2_SIZE_MASK 0x7ff
#define RDES1_RCH BIT(24)
#define RDES1_RER BIT(25)
#define TDES0_DE BIT(0)
#define TDES0_UF BIT(1)
#define TDES0_LF BIT(2)
#define TDES0_CC_SHIFT 3
#define TDES0_CC_MASK 0xf
#define TDES0_HF BIT(7)
#define TDES0_EC BIT(8)
#define TDES0_LC BIT(9)
#define TDES0_NC BIT(10)
#define TDES0_LO BIT(11)
#define TDES0_TO BIT(14)
#define TDES0_ES BIT(15)
#define TDES0_OWN BIT(31)
#define TDES1_BUF1_SIZE_SHIFT 0
#define TDES1_BUF1_SIZE_MASK 0x7ff
#define TDES1_BUF2_SIZE_SHIFT 11
#define TDES1_BUF2_SIZE_MASK 0x7ff
#define TDES1_FT0 BIT(22)
#define TDES1_DPD BIT(23)
#define TDES1_TCH BIT(24)
#define TDES1_TER BIT(25)
#define TDES1_AC BIT(26)
#define TDES1_SET BIT(27)
#define TDES1_FT1 BIT(28)
#define TDES1_FS BIT(29)
#define TDES1_LS BIT(30)
#define TDES1_IC BIT(31)
#define ETH_ALEN 6
static bar_t tulip_pci_bar[3];
struct tulip_descriptor {
uint32_t status;
uint32_t control;
uint32_t buf_addr1;
uint32_t buf_addr2;
};
struct TULIPState {
uint8_t pci_slot;
uint8_t irq_state;
int PCIBase;
int MMIOBase;
const device_t *device_info;
uint16_t subsys_id;
uint16_t subsys_ven_id;
mem_mapping_t memory;
rom_t bios_rom;
netcard_t *nic;
nmc93cxx_eeprom_t *eeprom;
uint32_t csr[16];
uint8_t pci_conf[256];
uint16_t mii_regs[32];
uint8_t eeprom_data[128];
/* state for MII */
uint32_t old_csr9;
uint32_t mii_word;
uint32_t mii_bitcnt;
/* 21040 ROM read address. */
uint8_t rom_read_addr;
uint32_t current_rx_desc;
uint32_t current_tx_desc;
uint8_t rx_frame[2048];
uint8_t tx_frame[2048];
uint16_t tx_frame_len;
uint16_t rx_frame_len;
uint16_t rx_frame_size;
uint32_t rx_status;
uint32_t bios_addr;
uint8_t filter[16][6];
int has_bios;
};
typedef struct TULIPState TULIPState;
static void
tulip_desc_read(TULIPState *s, uint32_t p,
struct tulip_descriptor *desc)
{
desc->status = mem_readl_phys(p);
desc->control = mem_readl_phys(p + 4);
desc->buf_addr1 = mem_readl_phys(p + 8);
desc->buf_addr2 = mem_readl_phys(p + 12);
if (s->csr[0] & CSR0_DBO) {
bswap32s(&desc->status);
bswap32s(&desc->control);
bswap32s(&desc->buf_addr1);
bswap32s(&desc->buf_addr2);
}
}
static void
tulip_desc_write(TULIPState *s, uint32_t p,
struct tulip_descriptor *desc)
{
if (s->csr[0] & CSR0_DBO) {
mem_writel_phys(p, bswap32(desc->status));
mem_writel_phys(p + 4, bswap32(desc->control));
mem_writel_phys(p + 8, bswap32(desc->buf_addr1));
mem_writel_phys(p + 12, bswap32(desc->buf_addr2));
} else {
mem_writel_phys(p, desc->status);
mem_writel_phys(p + 4, desc->control);
mem_writel_phys(p + 8, desc->buf_addr1);
mem_writel_phys(p + 12, desc->buf_addr2);
}
}
static void
tulip_update_int(TULIPState *s)
{
uint32_t ie = s->csr[5] & s->csr[7];
bool assert = false;
s->csr[5] &= ~(CSR5_AIS | CSR5_NIS);
if (ie & (CSR5_TI | CSR5_TU | CSR5_RI | CSR5_GTE | CSR5_ERI)) {
s->csr[5] |= CSR5_NIS;
}
if (ie & (CSR5_LC | CSR5_GPI | CSR5_FBE | CSR5_LNF | CSR5_ETI | CSR5_RWT | CSR5_RPS | CSR5_RU | CSR5_UNF | CSR5_LNP_ANC | CSR5_TJT | CSR5_TPS)) {
s->csr[5] |= CSR5_AIS;
}
assert = s->csr[5] & s->csr[7] & (CSR5_AIS | CSR5_NIS);
if (!assert)
pci_clear_irq(s->pci_slot, PCI_INTA, &s->irq_state);
else
pci_set_irq(s->pci_slot, PCI_INTA, &s->irq_state);
}
static bool
tulip_rx_stopped(TULIPState *s)
{
return ((s->csr[5] >> CSR5_RS_SHIFT) & CSR5_RS_MASK) == CSR5_RS_STOPPED;
}
static void
tulip_next_rx_descriptor(TULIPState *s,
struct tulip_descriptor *desc)
{
if (desc->control & RDES1_RER) {
s->current_rx_desc = s->csr[3];
} else if (desc->control & RDES1_RCH) {
s->current_rx_desc = desc->buf_addr2;
} else {
s->current_rx_desc += sizeof(struct tulip_descriptor) + (((s->csr[0] >> CSR0_DSL_SHIFT) & CSR0_DSL_MASK) << 2);
}
s->current_rx_desc &= ~3ULL;
}
static void
tulip_copy_rx_bytes(TULIPState *s, struct tulip_descriptor *desc)
{
int len1 = (desc->control >> RDES1_BUF1_SIZE_SHIFT) & RDES1_BUF1_SIZE_MASK;
int len2 = (desc->control >> RDES1_BUF2_SIZE_SHIFT) & RDES1_BUF2_SIZE_MASK;
int len;
if (s->rx_frame_len && len1) {
if (s->rx_frame_len > len1) {
len = len1;
} else {
len = s->rx_frame_len;
}
dma_bm_write(desc->buf_addr1, s->rx_frame + (s->rx_frame_size - s->rx_frame_len), len, 4);
s->rx_frame_len -= len;
}
if (s->rx_frame_len && len2) {
if (s->rx_frame_len > len2) {
len = len2;
} else {
len = s->rx_frame_len;
}
dma_bm_write(desc->buf_addr2, s->rx_frame + (s->rx_frame_size - s->rx_frame_len), len, 4);
s->rx_frame_len -= len;
}
}
static bool
tulip_filter_address(TULIPState *s, const uint8_t *addr)
{
#ifdef BLOCK_BROADCAST
static const char broadcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
#endif
bool ret = false;
for (uint8_t i = 0; i < 16 && ret == false; i++) {
if (!memcmp(&s->filter[i], addr, ETH_ALEN)) {
ret = true;
}
}
/*
Do not block broadcast packets - needed for connections to the guest
to succeed when using SLiRP.
*/
#ifdef BLOCK_BROADCAST
if (!memcmp(addr, broadcast, ETH_ALEN)) {
return true;
}
#endif
if (s->csr[6] & (CSR6_PR | CSR6_RA)) {
/* Promiscuous mode enabled */
s->rx_status |= RDES0_FF;
return true;
}
if ((s->csr[6] & CSR6_PM) && (addr[0] & 1)) {
/* Pass all Multicast enabled */
s->rx_status |= RDES0_MF;
return true;
}
if (s->csr[6] & CSR6_IF) {
ret ^= true;
}
return ret;
}
static int
tulip_receive(void *priv, uint8_t *buf, int size)
{
struct tulip_descriptor desc;
TULIPState *s = (TULIPState *) priv;
int first = 1;
if (size < 14 || size > sizeof(s->rx_frame) - 4
|| s->rx_frame_len || tulip_rx_stopped(s))
return 0;
if (!tulip_filter_address(s, buf)) {
//pclog("Not a filter address.\n");
return 1;
}
//pclog("Size = %d, FrameLen = %d, Buffer[%02x:%02x:%02x:%02x:%02x:%02x].\n", size, s->rx_frame_len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
do {
tulip_desc_read(s, s->current_rx_desc, &desc);
if (!(desc.status & RDES0_OWN)) {
s->csr[5] |= CSR5_RU;
tulip_update_int(s);
if (first)
/* Stop at the very beginning, tell the host 0 bytes have been received. */
return 0;
else
return (s->rx_frame_size - s->rx_frame_len) % s->rx_frame_size;
}
desc.status = 0;
if (!s->rx_frame_len) {
s->rx_frame_size = size + 4;
s->rx_status = RDES0_LS | ((s->rx_frame_size & RDES0_FL_MASK) << RDES0_FL_SHIFT);
desc.status |= RDES0_FS;
memcpy(s->rx_frame, buf, size);
s->rx_frame_len = s->rx_frame_size;
}
tulip_copy_rx_bytes(s, &desc);
if (!s->rx_frame_len) {
desc.status |= s->rx_status;
s->csr[5] |= CSR5_RI;
tulip_update_int(s);
}
tulip_desc_write(s, s->current_rx_desc, &desc);
tulip_next_rx_descriptor(s, &desc);
first = 0;
} while (s->rx_frame_len);
return 1;
}
static void
tulip_update_rs(TULIPState *s, int state)
{
s->csr[5] &= ~(CSR5_RS_MASK << CSR5_RS_SHIFT);
s->csr[5] |= (state & CSR5_RS_MASK) << CSR5_RS_SHIFT;
}
static const uint16_t tulip_mdi_default[] = {
/* MDI Registers 0 - 6, 7 */
0x3100,
0xf02c,
0x7810,
0x0000,
0x0501,
0x4181,
0x0000,
0x0000,
/* MDI Registers 8 - 15 */
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x3800,
0x0000,
/* MDI Registers 16 - 31 */
0x0003,
0x0600,
0x0001,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
};
/* Readonly mask for MDI (PHY) registers */
extern uint16_t l80225_mii_readw(uint16_t* regs, uint16_t addr);
extern void l80225_mii_writew(uint16_t* regs, uint16_t addr, uint16_t val);
static uint16_t
tulip_mii_read(TULIPState *s, int phy, int reg)
{
uint16_t ret = 0;
if (phy == 1) {
ret = l80225_mii_readw(s->mii_regs, reg);
}
//pclog("MII read phy = %02x, regs = %x, reg = %x, ret = %04x.\n", phy, s->mii_regs, reg, ret);
return ret;
}
static void
tulip_mii_write(TULIPState *s, int phy, int reg, uint16_t data)
{
if (phy != 1) {
return;
}
return l80225_mii_writew(s->mii_regs, reg, data);
}
static void
tulip_mii(TULIPState *s)
{
uint32_t changed = s->old_csr9 ^ s->csr[9];
uint16_t data;
int op;
int phy;
int reg;
if (!(changed & CSR9_MDC)) {
//pclog("No Change.\n");
return;
}
if (!(s->csr[9] & CSR9_MDC)) {
//pclog("No Change to MDC.\n");
return;
}
s->mii_bitcnt++;
s->mii_word <<= 1;
if ((s->csr[9] & CSR9_MDO) && (s->mii_bitcnt < 16 || !(s->csr[9] & CSR9_MII))) {
/* write op or address bits */
s->mii_word |= 1;
//pclog("WriteOp.\n");
}
if ((s->mii_bitcnt >= 16) && (s->csr[9] & CSR9_MII)) {
if (s->mii_word & 0x8000) {
s->csr[9] |= CSR9_MDI;
//pclog("CSR9 MDI set.\n");
} else {
s->csr[9] &= ~CSR9_MDI;
//pclog("CSR9 MDI cleared.\n");
}
}
if (s->mii_word == 0xffffffff) {
s->mii_bitcnt = 0;
//pclog("BitCnt = 0.\n");
} else if (s->mii_bitcnt == 16) {
op = (s->mii_word >> 12) & 0x0f;
phy = (s->mii_word >> 7) & 0x1f;
reg = (s->mii_word >> 2) & 0x1f;
//pclog("BitCnt = 16, op=%d, phy=%x, reg=%x.\n");
if (op == 6) {
s->mii_word = tulip_mii_read(s, phy, reg);
}
} else if (s->mii_bitcnt == 32) {
op = (s->mii_word >> 28) & 0x0f;
phy = (s->mii_word >> 23) & 0x1f;
reg = (s->mii_word >> 18) & 0x1f;
data = s->mii_word & 0xffff;
//pclog("BitCnt = 32, op=%d, phy=%x, reg=%x.\n");
if (op == 5) {
tulip_mii_write(s, phy, reg, data);
}
}
}
static uint32_t
tulip_csr9_read(TULIPState *s)
{
if (s->device_info->local == 3) {
return s->eeprom_data[s->rom_read_addr++];
}
if (s->csr[9] & CSR9_SR) {
if (nmc93cxx_eeprom_read(s->eeprom)) {
s->csr[9] |= CSR9_SR_DO;
} else {
s->csr[9] &= ~CSR9_SR_DO;
}
}
tulip_mii(s);
return s->csr[9];
}
static void
tulip_update_ts(TULIPState *s, int state)
{
s->csr[5] &= ~(CSR5_TS_MASK << CSR5_TS_SHIFT);
s->csr[5] |= (state & CSR5_TS_MASK) << CSR5_TS_SHIFT;
}
static uint32_t
tulip_read(uint32_t addr, void *opaque)
{
TULIPState *s = opaque;
uint32_t data = 0;
addr &= 127;
switch (addr) {
case CSR(9):
data = tulip_csr9_read(s);
break;
case CSR(12):
if (s->device_info->local == 3) {
data = 0;
break;
}
/* Fake autocompletion complete until we have PHY emulation */
data = 5 << CSR12_ANS_SHIFT;
break;
default:
if (!(addr & 7))
data = s->csr[addr >> 3];
break;
}
//pclog("[%04X:%08X]: CSR9 read %02x, data = %08x.\n", CS, cpu_state.pc, addr, data);
return data;
}
static void
tulip_tx(TULIPState *s, struct tulip_descriptor *desc)
{
//pclog("TX FrameLen = %d.\n", s->tx_frame_len);
if (s->tx_frame_len) {
if ((s->csr[6] >> CSR6_OM_SHIFT) & CSR6_OM_MASK) {
/* Internal or external Loopback */
tulip_receive(s, s->tx_frame, s->tx_frame_len);
} else if (s->tx_frame_len <= sizeof(s->tx_frame)) {
//pclog("Transmit!.\n");
network_tx(s->nic, s->tx_frame, s->tx_frame_len);
}
}
if (desc->control & TDES1_IC) {
s->csr[5] |= CSR5_TI;
tulip_update_int(s);
}
}
static int
tulip_copy_tx_buffers(TULIPState *s, struct tulip_descriptor *desc)
{
int len1 = (desc->control >> TDES1_BUF1_SIZE_SHIFT) & TDES1_BUF1_SIZE_MASK;
int len2 = (desc->control >> TDES1_BUF2_SIZE_SHIFT) & TDES1_BUF2_SIZE_MASK;
if (s->tx_frame_len + len1 > sizeof(s->tx_frame)) {
return -1;
}
if (len1) {
dma_bm_read(desc->buf_addr1,
s->tx_frame + s->tx_frame_len, len1, 4);
s->tx_frame_len += len1;
}
if (s->tx_frame_len + len2 > sizeof(s->tx_frame)) {
return -1;
}
if (len2) {
dma_bm_read(desc->buf_addr2,
s->tx_frame + s->tx_frame_len, len2, 4);
s->tx_frame_len += len2;
}
desc->status = (len1 + len2) ? 0 : 0x7fffffff;
return 0;
}
static void
tulip_setup_filter_addr(TULIPState *s, uint8_t *buf, int n)
{
int offset = n * 12;
s->filter[n][0] = buf[offset];
s->filter[n][1] = buf[offset + 1];
s->filter[n][2] = buf[offset + 4];
s->filter[n][3] = buf[offset + 5];
s->filter[n][4] = buf[offset + 8];
s->filter[n][5] = buf[offset + 9];
}
static void
tulip_setup_frame(TULIPState *s,
struct tulip_descriptor *desc)
{
uint8_t buf[4096];
int len = (desc->control >> TDES1_BUF1_SIZE_SHIFT) & TDES1_BUF1_SIZE_MASK;
if (len == 192) {
dma_bm_read(desc->buf_addr1, buf, len, 4);
for (uint8_t i = 0; i < 16; i++) {
tulip_setup_filter_addr(s, buf, i);
}
}
desc->status = 0x7fffffff;
if (desc->control & TDES1_IC) {
s->csr[5] |= CSR5_TI;
tulip_update_int(s);
}
}
static void
tulip_next_tx_descriptor(TULIPState *s,
struct tulip_descriptor *desc)
{
if (desc->control & TDES1_TER) {
s->current_tx_desc = s->csr[4];
} else if (desc->control & TDES1_TCH) {
s->current_tx_desc = desc->buf_addr2;
} else {
s->current_tx_desc += sizeof(struct tulip_descriptor) + (((s->csr[0] >> CSR0_DSL_SHIFT) & CSR0_DSL_MASK) << 2);
}
s->current_tx_desc &= ~3ULL;
}
static uint32_t
tulip_ts(TULIPState *s)
{
return (s->csr[5] >> CSR5_TS_SHIFT) & CSR5_TS_MASK;
}
static void
tulip_xmit_list_update(TULIPState *s)
{
#define TULIP_DESC_MAX 128
struct tulip_descriptor desc;
if (tulip_ts(s) != CSR5_TS_SUSPENDED) {
return;
}
for (uint8_t i = 0; i < TULIP_DESC_MAX; i++) {
tulip_desc_read(s, s->current_tx_desc, &desc);
if (!(desc.status & TDES0_OWN)) {
tulip_update_ts(s, CSR5_TS_SUSPENDED);
s->csr[5] |= CSR5_TU;
tulip_update_int(s);
return;
}
if (desc.control & TDES1_SET) {
tulip_setup_frame(s, &desc);
} else {
if (desc.control & TDES1_FS) {
s->tx_frame_len = 0;
}
if (!tulip_copy_tx_buffers(s, &desc)) {
if (desc.control & TDES1_LS) {
tulip_tx(s, &desc);
}
}
}
tulip_desc_write(s, s->current_tx_desc, &desc);
tulip_next_tx_descriptor(s, &desc);
}
}
static void
tulip_csr9_write(TULIPState *s, UNUSED(uint32_t old_val),
uint32_t new_val)
{
if (new_val & CSR9_SR) {
nmc93cxx_eeprom_write(s->eeprom,
!!(new_val & CSR9_SR_CS),
!!(new_val & CSR9_SR_SK),
!!(new_val & CSR9_SR_DI));
}
}
static void
tulip_reset(void *priv)
{
TULIPState *s = (TULIPState *) priv;
const uint16_t *eeprom_data = nmc93cxx_eeprom_data(s->eeprom);
s->csr[0] = 0xfe000000;
s->csr[1] = 0xffffffff;
s->csr[2] = 0xffffffff;
s->csr[5] = 0xfc000000;
s->csr[6] = 0x32000040;
s->csr[7] = 0xfffe0000;
s->csr[8] = 0x00000000;
s->csr[9] = 0xfff483ff;
s->csr[11] = 0xfffe0000;
s->csr[12] = 0xfffffec6;
s->csr[13] = 0xffff0000;
s->csr[14] = 0xffffffff;
s->csr[15] = 0x8ff00000;
if (s->device_info->local != 3) {
s->subsys_id = eeprom_data[1];
s->subsys_ven_id = eeprom_data[0];
}
}
static void
tulip_write(uint32_t addr, uint32_t data, void *opaque)
{
TULIPState *s = opaque;
addr &= 127;
//pclog("[%04X:%08X]: Tulip Write >> 3: %02x, val=%08x.\n", CS, cpu_state.pc, addr >> 3, data);
switch (addr) {
case CSR(0):
s->csr[0] = data;
if (data & CSR0_SWR) {
tulip_reset(s);
tulip_update_int(s);
}
break;
case CSR(1):
tulip_xmit_list_update(s);
break;
case CSR(2):
break;
case CSR(3):
s->csr[3] = data & ~3ULL;
s->current_rx_desc = s->csr[3];
break;
case CSR(4):
s->csr[4] = data & ~3ULL;
s->current_tx_desc = s->csr[4];
tulip_xmit_list_update(s);
break;
case CSR(5):
/* Status register, write clears bit */
s->csr[5] &= ~(data & (CSR5_TI | CSR5_TPS | CSR5_TU | CSR5_TJT | CSR5_LNP_ANC | CSR5_UNF | CSR5_RI | CSR5_RU | CSR5_RPS | CSR5_RWT | CSR5_ETI | CSR5_GTE | CSR5_LNF | CSR5_FBE | CSR5_ERI | CSR5_AIS | CSR5_NIS | CSR5_GPI | CSR5_LC));
tulip_update_int(s);
break;
case CSR(6):
s->csr[6] = data;
if (s->csr[6] & CSR6_SR) {
tulip_update_rs(s, CSR5_RS_RUNNING_WAIT_RECEIVE);
} else {
tulip_update_rs(s, CSR5_RS_STOPPED);
}
if (s->csr[6] & CSR6_ST) {
tulip_update_ts(s, CSR5_TS_SUSPENDED);
tulip_xmit_list_update(s);
} else {
tulip_update_ts(s, CSR5_TS_STOPPED);
s->csr[5] |= CSR5_TPS;
}
break;
case CSR(7):
s->csr[7] = data;
tulip_update_int(s);
break;
case CSR(8):
s->csr[8] = data;
break;
case CSR(9):
if (s->device_info->local != 3) {
tulip_csr9_write(s, s->csr[9], data);
/* don't clear MII read data */
s->csr[9] &= CSR9_MDI;
s->csr[9] |= (data & ~CSR9_MDI);
tulip_mii(s);
s->old_csr9 = s->csr[9];
} else {
s->rom_read_addr = 0;
}
break;
case CSR(10):
s->csr[10] = data;
break;
case CSR(11):
s->csr[11] = data;
break;
case CSR(12):
/* SIA Status register, some bits are cleared by writing 1 */
s->csr[12] &= ~(data & (CSR12_MRA | CSR12_TRA | CSR12_ARA));
break;
case CSR(13):
s->csr[13] = data;
if (s->device_info->local == 3 && (data & 0x4)) {
s->csr[13] = 0x8f01;
s->csr[14] = 0xfffd;
s->csr[15] = 0;
}
break;
case CSR(14):
s->csr[14] = data;
break;
case CSR(15):
s->csr[15] = data;
break;
default:
pclog("%s: write to CSR at unknown address "
"0x%u\n",
__func__, addr);
break;
}
}
static void
tulip_writeb_io(uint16_t addr, uint8_t data, void *opaque)
{
return tulip_write(addr, data, opaque);
}
static void
tulip_writew_io(uint16_t addr, uint16_t data, void *opaque)
{
return tulip_write(addr, data, opaque);
}
static void
tulip_writel_io(uint16_t addr, uint32_t data, void *opaque)
{
return tulip_write(addr, data, opaque);
}
static void
tulip_mem_writeb(uint32_t addr, uint8_t data, void *opaque)
{
if ((addr & 0xfff) < 0x100)
tulip_write(addr, data, opaque);
}
static void
tulip_mem_writew(uint32_t addr, uint16_t data, void *opaque)
{
if ((addr & 0xfff) < 0x100)
tulip_write(addr, data, opaque);
}
static void
tulip_mem_writel(uint32_t addr, uint32_t data, void *opaque)
{
if ((addr & 0xfff) < 0x100)
tulip_write(addr, data, opaque);
}
static uint8_t
tulip_mem_readb(uint32_t addr, void *opaque)
{
uint8_t ret = 0xff;
if ((addr & 0xfff) < 0x100)
ret = tulip_read(addr, opaque);
return ret;
}
static uint16_t
tulip_mem_readw(uint32_t addr, void *opaque)
{
uint16_t ret = 0xffff;
if ((addr & 0xfff) < 0x100)
ret = tulip_read(addr, opaque);
return ret;
}
static uint32_t
tulip_mem_readl(uint32_t addr, void *opaque)
{
uint32_t ret = 0xffffffff;
if ((addr & 0xfff) < 0x100)
ret = tulip_read(addr, opaque);
return ret;
}
static uint8_t
tulip_readb_io(uint16_t addr, void *opaque)
{
return tulip_read(addr, opaque);
}
static uint16_t
tulip_readw_io(uint16_t addr, void *opaque)
{
return tulip_read(addr, opaque);
}
static uint32_t
tulip_readl_io(uint16_t addr, void *opaque)
{
return tulip_read(addr, opaque);
}
static void
tulip_idblock_crc(uint16_t *srom)
{
unsigned char bitval;
unsigned char crc;
const int len = 9;
crc = -1;
for (int word = 0; word < len; word++) {
for (int8_t bit = 15; bit >= 0; bit--) {
if ((word == (len - 1)) && (bit == 7)) {
/*
* Insert the correct CRC result into input data stream
* in place.
*/
srom[len - 1] = (srom[len - 1] & 0xff00) | (unsigned short) crc;
break;
}
bitval = ((srom[word] >> bit) & 1) ^ ((crc >> 7) & 1);
crc = crc << 1;
if (bitval == 1) {
crc ^= 6;
crc |= 0x01;
}
}
}
}
static uint16_t
tulip_srom_crc(uint8_t *eeprom)
{
unsigned long crc = 0xffffffff;
unsigned long flippedcrc = 0;
unsigned char currentbyte;
unsigned int msb;
unsigned int bit;
for (size_t i = 0; i < 126; i++) {
currentbyte = eeprom[i];
for (bit = 0; bit < 8; bit++) {
msb = (crc >> 31) & 1;
crc <<= 1;
if (msb ^ (currentbyte & 1)) {
crc ^= 0x04c11db6;
crc |= 0x00000001;
}
currentbyte >>= 1;
}
}
for (uint8_t i = 0; i < 32; i++) {
flippedcrc <<= 1;
bit = crc & 1;
crc >>= 1;
flippedcrc += bit;
}
return (flippedcrc ^ 0xffffffff) & 0xffff;
}
static uint8_t
tulip_pci_read(UNUSED(int func), int addr, void *priv)
{
const TULIPState *s = (TULIPState *) priv;
uint8_t ret = 0;
switch (addr) {
case 0x00:
ret = 0x11;
break;
case 0x01:
ret = 0x10;
break;
case 0x02:
if (s->device_info->local == 3)
ret = 0x02;
else if (s->device_info->local)
ret = 0x09;
else
ret = 0x19;
break;
case 0x03:
ret = 0x00;
break;
case 0x04:
ret = s->pci_conf[0x04];
break;
case 0x05:
ret = s->pci_conf[0x05];
break;
case 0x06:
ret = 0x80;
break;
case 0x07:
ret = 0x02;
break;
case 0x08:
ret = 0x20;
break;
case 0x09:
ret = 0x00;
break;
case 0x0A:
ret = 0x00;
break;
case 0x0B:
ret = 0x02;
break;
case 0x10:
ret = (tulip_pci_bar[0].addr_regs[0] & 0x80) | 0x01;
break;
case 0x11:
ret = tulip_pci_bar[0].addr_regs[1];
break;
case 0x12:
ret = tulip_pci_bar[0].addr_regs[2];
break;
case 0x13:
ret = tulip_pci_bar[0].addr_regs[3];
break;
#ifdef USE_128_BYTE_BAR
case 0x14:
ret = (tulip_pci_bar[1].addr_regs[0] & 0x80);
break;
#endif
case 0x15:
#ifdef USE_128_BYTE_BAR
ret = tulip_pci_bar[1].addr_regs[1];
#else
ret = tulip_pci_bar[1].addr_regs[1] & 0xf0;
#endif
break;
case 0x16:
ret = tulip_pci_bar[1].addr_regs[2];
break;
case 0x17:
ret = tulip_pci_bar[1].addr_regs[3];
break;
case 0x2C:
ret = s->subsys_ven_id & 0xFF;
break;
case 0x2D:
ret = s->subsys_ven_id >> 8;
break;
case 0x2E:
ret = s->subsys_id & 0xFF;
break;
case 0x2F:
ret = s->subsys_id >> 8;
break;
case 0x30:
ret = (tulip_pci_bar[2].addr_regs[0] & 0x01);
break;
case 0x31:
ret = tulip_pci_bar[2].addr_regs[1];
break;
case 0x32:
ret = tulip_pci_bar[2].addr_regs[2];
break;
case 0x33:
ret = tulip_pci_bar[2].addr_regs[3];
break;
case 0x3C:
ret = s->pci_conf[0x3C];
break;
case 0x3D:
ret = PCI_INTA;
break;
case 0x3E:
case 0x3F:
case 0x41:
ret = s->pci_conf[addr & 0xff];
break;
}
//pclog("PCI read=%02x, ret=%02x.\n", addr, ret);
return ret;
}
static void
tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
TULIPState *s = (TULIPState *) priv;
//pclog("PCI write=%02x, ret=%02x.\n", addr, val);
switch (addr) {
case 0x04:
s->pci_conf[0x04] = val & 0x07;
//pclog("PCI write cmd: IOBase=%04x, MMIOBase=%08x, val=%02x.\n", s->PCIBase, s->MMIOBase, s->pci_conf[0x04]);
io_removehandler(s->PCIBase, 128,
tulip_readb_io, tulip_readw_io, tulip_readl_io,
tulip_writeb_io, tulip_writew_io, tulip_writel_io,
priv);
if ((s->PCIBase != 0) && (val & PCI_COMMAND_IO))
io_sethandler(s->PCIBase, 128,
tulip_readb_io, tulip_readw_io, tulip_readl_io,
tulip_writeb_io, tulip_writew_io, tulip_writel_io,
priv);
//pclog("PCI write cmd: IOBase=%04x, MMIOBase=%08x, val=%02x.\n", s->PCIBase, s->MMIOBase, s->pci_conf[0x04]);
mem_mapping_disable(&s->memory);
if ((s->MMIOBase != 0) && (val & PCI_COMMAND_MEM))
mem_mapping_enable(&s->memory);
break;
case 0x05:
s->pci_conf[0x05] = val & 1;
break;
case 0x10:
case 0x11:
case 0x12:
case 0x13:
io_removehandler(s->PCIBase, 128,
tulip_readb_io, tulip_readw_io, tulip_readl_io,
tulip_writeb_io, tulip_writew_io, tulip_writel_io,
priv);
tulip_pci_bar[0].addr_regs[addr & 3] = val;
tulip_pci_bar[0].addr &= 0xffffff80;
s->PCIBase = tulip_pci_bar[0].addr;
if (s->pci_conf[0x4] & PCI_COMMAND_IO) {
//pclog("PCI write=%02x, base=%04x, io?=%x.\n", addr, s->PCIBase, s->pci_conf[0x4] & PCI_COMMAND_IO);
if (s->PCIBase != 0)
io_sethandler(s->PCIBase, 128,
tulip_readb_io, tulip_readw_io, tulip_readl_io,
tulip_writeb_io, tulip_writew_io, tulip_writel_io,
priv);
}
break;
#ifndef USE_128_BYTE_BAR
case 0x14:
#endif
case 0x15:
case 0x16:
case 0x17:
mem_mapping_disable(&s->memory);
tulip_pci_bar[1].addr_regs[addr & 3] = val;
#ifdef USE_128_BYTE_BAR
tulip_pci_bar[1].addr &= 0xffffff80;
#else
tulip_pci_bar[1].addr &= 0xfffff000;
#endif
s->MMIOBase = tulip_pci_bar[1].addr;
if (s->pci_conf[0x4] & PCI_COMMAND_MEM) {
//pclog("PCI write=%02x, mmiobase=%08x, mmio?=%x.\n", addr, s->PCIBase, s->pci_conf[0x4] & PCI_COMMAND_MEM);
if (s->MMIOBase != 0)
#ifdef USE_128_BYTE_BAR
mem_mapping_set_addr(&s->memory, s->MMIOBase, 128);
#else
mem_mapping_set_addr(&s->memory, s->MMIOBase, 4096);
#endif
}
break;
case 0x30: /* PCI_ROMBAR */
case 0x31: /* PCI_ROMBAR */
case 0x32: /* PCI_ROMBAR */
case 0x33: /* PCI_ROMBAR */
if (!s->has_bios)
return;
mem_mapping_disable(&s->bios_rom.mapping);
tulip_pci_bar[2].addr_regs[addr & 3] = val;
tulip_pci_bar[2].addr &= 0xffff0001;
s->bios_addr = tulip_pci_bar[2].addr & 0xffff0000;
if (tulip_pci_bar[2].addr_regs[0] & 0x01) {
if (s->bios_addr != 0)
mem_mapping_set_addr(&s->bios_rom.mapping, s->bios_addr, 0x10000);
}
return;
case 0x3C:
s->pci_conf[0x3c] = val;
return;
case 0x3E:
case 0x3F:
case 0x41:
s->pci_conf[addr & 0xff] = val;
return;
}
}
static void *
nic_init(const device_t *info)
{
nmc93cxx_eeprom_params_t params;
TULIPState *s = calloc(1, sizeof(TULIPState));
char filename[1024] = { 0 };
uint32_t mac;
uint8_t *eeprom_data;
if (!s)
return NULL;
if (info->local && info->local != 3) {
s->bios_addr = 0xD0000;
s->has_bios = device_get_config_int("bios");
} else {
s->bios_addr = 0;
s->has_bios = 0;
}
#ifdef USE_128_BYTE_BAR
mem_mapping_add(&s->memory, 0x0fffff00, 128, tulip_mem_readb, tulip_mem_readw, tulip_mem_readl, tulip_mem_writeb, tulip_mem_writew, tulip_mem_writel, NULL, MEM_MAPPING_EXTERNAL, s);
#else
mem_mapping_add(&s->memory, 0x0ffff000, 4096, tulip_mem_readb, tulip_mem_readw, tulip_mem_readl, tulip_mem_writeb, tulip_mem_writew, tulip_mem_writel, NULL, MEM_MAPPING_EXTERNAL, s);
#endif
mem_mapping_disable(&s->memory);
s->device_info = info;
if (info->local != 3) {
if (info->local == 2) {
/*Subsystem Vendor ID*/
s->eeprom_data[0] = 0x00;
s->eeprom_data[1] = 0x0a;
/*Subsystem ID*/
s->eeprom_data[2] = 0x14;
s->eeprom_data[3] = 0x21;
} else {
/*Subsystem Vendor ID*/
s->eeprom_data[0] = info->local ? 0x25 : 0x11;
s->eeprom_data[1] = 0x10;
/*Subsystem ID*/
s->eeprom_data[2] = info->local ? 0x10 : 0x0a;
s->eeprom_data[3] = info->local ? 0x03 : 0x50;
}
/*Cardbus CIS Pointer low*/
s->eeprom_data[4] = 0x00;
s->eeprom_data[5] = 0x00;
/*Cardbus CIS Pointer high*/
s->eeprom_data[6] = 0x00;
s->eeprom_data[7] = 0x00;
/*ID Reserved1*/
for (int i = 0; i < 7; i++)
s->eeprom_data[8 + i] = 0x00;
/*MiscHwOptions*/
s->eeprom_data[15] = 0x00;
/*ID_BLOCK_CRC*/
tulip_idblock_crc((uint16_t *) s->eeprom_data);
/*Func0_HwOptions*/
s->eeprom_data[17] = 0x00;
/*SROM Format Version 1, compatible with older guests*/
s->eeprom_data[18] = 0x01;
/*Controller Count*/
s->eeprom_data[19] = 0x01;
/*DEC OID*/
s->eeprom_data[20] = 0x00;
s->eeprom_data[21] = 0x00;
s->eeprom_data[22] = 0xf8;
if (info->local == 2) {
/* Microsoft VPC DEC Tulip. */
s->eeprom_data[20] = 0x00;
s->eeprom_data[21] = 0x03;
s->eeprom_data[22] = 0x0f;
}
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/* Set up our BIA. */
if (mac & 0xff000000) {
/* Generate new local MAC. */
s->eeprom_data[23] = random_generate();
s->eeprom_data[24] = random_generate();
s->eeprom_data[25] = random_generate();
mac = (((int) s->eeprom_data[23]) << 16);
mac |= (((int) s->eeprom_data[24]) << 8);
mac |= ((int) s->eeprom_data[25]);
device_set_config_mac("mac", mac);
} else {
s->eeprom_data[23] = (mac >> 16) & 0xff;
s->eeprom_data[24] = (mac >> 8) & 0xff;
s->eeprom_data[25] = (mac & 0xff);
}
/*Controller_0 Device_Number*/
s->eeprom_data[26] = 0x00;
/*Controller_0 Info Leaf_Offset*/
s->eeprom_data[27] = 0x1e;
s->eeprom_data[28] = 0x00;
/*Selected Connection Type, Powerup AutoSense and Dynamic AutoSense if the board supports it*/
s->eeprom_data[30] = 0x00;
s->eeprom_data[31] = 0x08;
if (info->local) {
/*General Purpose Control*/
s->eeprom_data[32] = 0xff;
/*Block Count*/
s->eeprom_data[33] = 0x01;
/*Extended Format (first part)*/
/*Length (0:6) and Format Indicator (7)*/
s->eeprom_data[34] = 0x81;
/*Block Type (first part)*/
s->eeprom_data[35] = 0x01;
/*Extended Format (second part) - Block Type 0 for 21140*/
/*Length (0:6) and Format Indicator (7)*/
s->eeprom_data[36] = 0x85;
/*Block Type (second part)*/
s->eeprom_data[37] = 0x00;
/*Media Code (0:5), EXT (6), Reserved (7)*/
s->eeprom_data[38] = 0x01;
/*General Purpose Data*/
s->eeprom_data[39] = 0x00;
/*Command*/
s->eeprom_data[40] = 0x00;
s->eeprom_data[41] = 0x00;
} else {
/*SROM Format Version 3*/
s->eeprom_data[18] = 0x03;
/*Block Count*/
s->eeprom_data[32] = 0x01;
/*Extended Format - Block Type 2 for 21142/21143*/
/*Length (0:6) and Format Indicator (7)*/
s->eeprom_data[33] = 0x86;
/*Block Type*/
s->eeprom_data[34] = 0x02;
/*Media Code (0:5), EXT (6), Reserved (7)*/
s->eeprom_data[35] = 0x01;
/*General Purpose Control*/
s->eeprom_data[36] = 0xff;
s->eeprom_data[37] = 0xff;
/*General Purpose Data*/
s->eeprom_data[38] = 0x00;
s->eeprom_data[39] = 0x00;
}
s->eeprom_data[126] = tulip_srom_crc(s->eeprom_data) & 0xff;
s->eeprom_data[127] = tulip_srom_crc(s->eeprom_data) >> 8;
} else {
uint32_t checksum = 0;
/* 21040 is supposed to only have MAC address in its serial ROM if Linux is correct. */
memset(s->eeprom_data, 0, sizeof(s->eeprom_data));
/* See if we have a local MAC address configured. */
mac = device_get_config_mac("mac", -1);
/*DEC OID*/
s->eeprom_data[0] = 0x00;
s->eeprom_data[1] = 0x00;
s->eeprom_data[2] = 0xF8;
if (mac & 0xff000000) {
/* Generate new local MAC. */
s->eeprom_data[3] = random_generate();
s->eeprom_data[4] = random_generate();
s->eeprom_data[5] = random_generate();
mac = (((int) s->eeprom_data[3]) << 16);
mac |= (((int) s->eeprom_data[4]) << 8);
mac |= ((int) s->eeprom_data[5]);
device_set_config_mac("mac", mac);
} else {
s->eeprom_data[3] = (mac >> 16) & 0xff;
s->eeprom_data[4] = (mac >> 8) & 0xff;
s->eeprom_data[5] = (mac & 0xff);
}
/* Generate checksum. */
checksum = (s->eeprom_data[0] * 256) | s->eeprom_data[1];
checksum *= 2;
if (checksum > 65535)
checksum = checksum % 65535;
/* 2nd pair. */
checksum += (s->eeprom_data[2] * 256) | s->eeprom_data[3];
if (checksum > 65535)
checksum = checksum % 65535;
checksum *= 2;
if (checksum > 65535)
checksum = checksum % 65535;
/* 3rd pair. */
checksum += (s->eeprom_data[4] * 256) | s->eeprom_data[5];
if (checksum > 65535)
checksum = checksum % 65535;
if (checksum >= 65535)
checksum = 0;
s->eeprom_data[6] = (checksum >> 8) & 0xFF;
s->eeprom_data[7] = checksum & 0xFF;
}
if (info->local != 3) {
params.nwords = 64;
params.default_content = (uint16_t *) s->eeprom_data;
params.filename = filename;
snprintf(filename, sizeof(filename), "nmc93cxx_eeprom_%s_%d.nvr", info->internal_name, device_get_instance());
s->eeprom = device_add_params(&nmc93cxx_device, ¶ms);
if (s->eeprom == NULL) {
free(s);
return NULL;
}
}
tulip_pci_bar[0].addr_regs[0] = 1;
tulip_pci_bar[1].addr_regs[0] = 0;
s->pci_conf[0x04] = 7;
/* Enable our BIOS space in PCI, if needed. */
if (s->bios_addr > 0) {
rom_init(&s->bios_rom, ROM_PATH_DEC21140, s->bios_addr, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
tulip_pci_bar[2].addr = 0xffff0000;
} else
tulip_pci_bar[2].addr = 0;
mem_mapping_disable(&s->bios_rom.mapping);
eeprom_data = (info->local == 3) ? s->eeprom_data : (uint8_t *) &nmc93cxx_eeprom_data(s->eeprom)[0];
//pclog("EEPROM Data Format=%02x, Count=%02x, MAC=%02x:%02x:%02x:%02x:%02x:%02x.\n", eeprom_data[0x12], eeprom_data[0x13], eeprom_data[0x14], eeprom_data[0x15], eeprom_data[0x16], eeprom_data[0x17], eeprom_data[0x18], eeprom_data[0x19]);
memcpy(s->mii_regs, tulip_mdi_default, sizeof(tulip_mdi_default));
s->nic = network_attach(s, &eeprom_data[(info->local == 3) ? 0 : 20], tulip_receive, NULL);
pci_add_card(PCI_ADD_NORMAL, tulip_pci_read, tulip_pci_write, s, &s->pci_slot);
tulip_reset(s);
return s;
}
static void
nic_close(void *priv)
{
free(priv);
}
// clang-format off
static const device_config_t dec_tulip_21143_config[] = {
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
static const device_config_t dec_tulip_21140_config[] = {
{
.name = "bios",
.description = "Enable BIOS",
.type = CONFIG_BINARY,
.default_string = "",
.default_int = 0
},
{
.name = "mac",
.description = "MAC Address",
.type = CONFIG_MAC,
.default_string = "",
.default_int = -1
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t dec_tulip_device = {
.name = "DEC DE-500A Fast Ethernet (DECchip 21143 \"Tulip\")",
.internal_name = "dec_21143_tulip",
.flags = DEVICE_PCI,
.local = 0,
.init = nic_init,
.close = nic_close,
.reset = tulip_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = dec_tulip_21143_config
};
const device_t dec_tulip_21140_device = {
.name = "DEC 21140 Fast Ethernet (DECchip 21140 \"Tulip FasterNet\")",
.internal_name = "dec_21140_tulip",
.flags = DEVICE_PCI,
.local = 1,
.init = nic_init,
.close = nic_close,
.reset = tulip_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = dec_tulip_21140_config
};
const device_t dec_tulip_21140_vpc_device = {
.name = "Microsoft Virtual PC Network (DECchip 21140 \"Tulip FasterNet\")",
.internal_name = "dec_21140_tulip_vpc",
.flags = DEVICE_PCI,
.local = 2,
.init = nic_init,
.close = nic_close,
.reset = tulip_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = dec_tulip_21140_config
};
const device_t dec_tulip_21040_device = {
.name = "DEC DE-435 EtherWorks Turbo (DECchip 21040 \"Tulip\")",
.internal_name = "dec_21040_tulip",
.flags = DEVICE_PCI,
.local = 3,
.init = nic_init,
.close = nic_close,
.reset = tulip_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = dec_tulip_21143_config
};
``` | /content/code_sandbox/src/network/net_tulip.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 15,368 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Various ASCII to Unicode maps, for the various codepages.
*
*
*
* Authors: Michael Dring, <michael@drueing.de>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Based on code by Frederic Weymann (originally for DosBox.)
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/plat.h>
#include <86box/printer.h>
static const uint16_t cp437Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x00ec, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00f2, 0x00fb, 0x00f9,
0x00ff, 0x00d6, 0x00dc, 0x00a2, 0x00a3, 0x00a5, 0x20a7, 0x0192,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba,
0x00bf, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp737Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 0x039e, 0x039f, 0x03a0,
0x03a1, 0x03a3, 0x03a4, 0x03a5, 0x03a6, 0x03a7, 0x03a8, 0x03a9,
0x03b1, 0x03b2, 0x03b3, 0x03b4, 0x03b5, 0x03b6, 0x03b7, 0x03b8,
0x03b9, 0x03ba, 0x03bb, 0x03bc, 0x03bd, 0x03be, 0x03bf, 0x03c0,
0x03c1, 0x03c3, 0x03c2, 0x03c4, 0x03c5, 0x03c6, 0x03c7, 0x03c8,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03c9, 0x03ac, 0x03ad, 0x03ae, 0x03ca, 0x03af, 0x03cc, 0x03cd,
0x03cb, 0x03ce, 0x0386, 0x0388, 0x0389, 0x038a, 0x038c, 0x038e,
0x038f, 0x00b1, 0x2265, 0x2264, 0x03aa, 0x03ab, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp775Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x0106, 0x00fc, 0x00e9, 0x0101, 0x00e4, 0x0123, 0x00e5, 0x0107,
0x0142, 0x0113, 0x0156, 0x0157, 0x012b, 0x0179, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x014d, 0x00f6, 0x0122, 0x00a2, 0x015a,
0x015b, 0x00d6, 0x00dc, 0x00f8, 0x00a3, 0x00d8, 0x00d7, 0x00a4,
0x0100, 0x012a, 0x00f3, 0x017b, 0x017c, 0x017a, 0x201d, 0x00a6,
0x00a9, 0x00ae, 0x00ac, 0x00bd, 0x00bc, 0x0141, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010c, 0x0118,
0x0116, 0x2563, 0x2551, 0x2557, 0x255d, 0x012e, 0x0160, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x0172, 0x016a,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x017d,
0x0105, 0x010d, 0x0119, 0x0117, 0x012f, 0x0161, 0x0173, 0x016b,
0x017e, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x00d3, 0x00df, 0x014c, 0x0143, 0x00f5, 0x00d5, 0x00b5, 0x0144,
0x0136, 0x0137, 0x013b, 0x013c, 0x0146, 0x0112, 0x0145, 0x2019,
0x00ad, 0x00b1, 0x201c, 0x00be, 0x00b6, 0x00a7, 0x00f7, 0x201e,
0x00b0, 0x2219, 0x00b7, 0x00b9, 0x00b3, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp850Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x00ec, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00f2, 0x00fb, 0x00f9,
0x00ff, 0x00d6, 0x00dc, 0x00f8, 0x00a3, 0x00d8, 0x00d7, 0x0192,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba,
0x00bf, 0x00ae, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00c1, 0x00c2, 0x00c0,
0x00a9, 0x2563, 0x2551, 0x2557, 0x255d, 0x00a2, 0x00a5, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x00e3, 0x00c3,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x00a4,
0x00f0, 0x00d0, 0x00ca, 0x00cb, 0x00c8, 0x0131, 0x00cd, 0x00ce,
0x00cf, 0x2518, 0x250c, 0x2588, 0x2584, 0x00a6, 0x00cc, 0x2580,
0x00d3, 0x00df, 0x00d4, 0x00d2, 0x00f5, 0x00d5, 0x00b5, 0x00fe,
0x00de, 0x00da, 0x00db, 0x00d9, 0x00fd, 0x00dd, 0x00af, 0x00b4,
0x00ad, 0x00b1, 0x2017, 0x00be, 0x00b6, 0x00a7, 0x00f7, 0x00b8,
0x00b0, 0x00a8, 0x00b7, 0x00b9, 0x00b3, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp852Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x016f, 0x0107, 0x00e7,
0x0142, 0x00eb, 0x0150, 0x0151, 0x00ee, 0x0179, 0x00c4, 0x0106,
0x00c9, 0x0139, 0x013a, 0x00f4, 0x00f6, 0x013d, 0x013e, 0x015a,
0x015b, 0x00d6, 0x00dc, 0x0164, 0x0165, 0x0141, 0x00d7, 0x010d,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x0104, 0x0105, 0x017d, 0x017e,
0x0118, 0x0119, 0x00ac, 0x017a, 0x010c, 0x015f, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00c1, 0x00c2, 0x011a,
0x015e, 0x2563, 0x2551, 0x2557, 0x255d, 0x017b, 0x017c, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x0102, 0x0103,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x00a4,
0x0111, 0x0110, 0x010e, 0x00cb, 0x010f, 0x0147, 0x00cd, 0x00ce,
0x011b, 0x2518, 0x250c, 0x2588, 0x2584, 0x0162, 0x016e, 0x2580,
0x00d3, 0x00df, 0x00d4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
0x0154, 0x00da, 0x0155, 0x0170, 0x00fd, 0x00dd, 0x0163, 0x00b4,
0x00ad, 0x02dd, 0x02db, 0x02c7, 0x02d8, 0x00a7, 0x00f7, 0x00b8,
0x00b0, 0x00a8, 0x02d9, 0x0171, 0x0158, 0x0159, 0x25a0, 0x00a0
};
static const uint16_t cp855Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
0x0459, 0x0409, 0x045a, 0x040a, 0x045b, 0x040b, 0x045c, 0x040c,
0x045e, 0x040e, 0x045f, 0x040f, 0x044e, 0x042e, 0x044a, 0x042a,
0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
0x0418, 0x2563, 0x2551, 0x2557, 0x255d, 0x0439, 0x0419, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x043a, 0x041a,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x00a4,
0x043b, 0x041b, 0x043c, 0x041c, 0x043d, 0x041d, 0x043e, 0x041e,
0x043f, 0x2518, 0x250c, 0x2588, 0x2584, 0x041f, 0x044f, 0x2580,
0x042f, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044c, 0x042c, 0x2116,
0x00ad, 0x044b, 0x042b, 0x0437, 0x0417, 0x0448, 0x0428, 0x044d,
0x042d, 0x0449, 0x0429, 0x0447, 0x0427, 0x00a7, 0x25a0, 0x00a0
};
static const uint16_t cp857Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x0131, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00f2, 0x00fb, 0x00f9,
0x0130, 0x00d6, 0x00dc, 0x00f8, 0x00a3, 0x00d8, 0x015e, 0x015f,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x011e, 0x011f,
0x00bf, 0x00ae, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00c1, 0x00c2, 0x00c0,
0x00a9, 0x2563, 0x2551, 0x2557, 0x255d, 0x00a2, 0x00a5, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x00e3, 0x00c3,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x00a4,
0x00ba, 0x00aa, 0x00ca, 0x00cb, 0x00c8, 0x0000, 0x00cd, 0x00ce,
0x00cf, 0x2518, 0x250c, 0x2588, 0x2584, 0x00a6, 0x00cc, 0x2580,
0x00d3, 0x00df, 0x00d4, 0x00d2, 0x00f5, 0x00d5, 0x00b5, 0x0000,
0x00d7, 0x00da, 0x00db, 0x00d9, 0x00ec, 0x00ff, 0x00af, 0x00b4,
0x00ad, 0x00b1, 0x0000, 0x00be, 0x00b6, 0x00a7, 0x00f7, 0x00b8,
0x00b0, 0x00a8, 0x00b7, 0x00b9, 0x00b3, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp860Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e3, 0x00e0, 0x00c1, 0x00e7,
0x00ea, 0x00ca, 0x00e8, 0x00cd, 0x00d4, 0x00ec, 0x00c3, 0x00c2,
0x00c9, 0x00c0, 0x00c8, 0x00f4, 0x00f5, 0x00f2, 0x00da, 0x00f9,
0x00cc, 0x00d5, 0x00dc, 0x00a2, 0x00a3, 0x00d9, 0x20a7, 0x00d3,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba,
0x00bf, 0x00d2, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp861Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00d0, 0x00f0, 0x00de, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00fe, 0x00fb, 0x00dd,
0x00fd, 0x00d6, 0x00dc, 0x00f8, 0x00a3, 0x00d8, 0x20a7, 0x0192,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00c1, 0x00cd, 0x00d3, 0x00da,
0x00bf, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp862Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x05d0, 0x05d1, 0x05d2, 0x05d3, 0x05d4, 0x05d5, 0x05d6, 0x05d7,
0x05d8, 0x05d9, 0x05da, 0x05db, 0x05dc, 0x05dd, 0x05de, 0x05df,
0x05e0, 0x05e1, 0x05e2, 0x05e3, 0x05e4, 0x05e5, 0x05e6, 0x05e7,
0x05e8, 0x05e9, 0x05ea, 0x00a2, 0x00a3, 0x00a5, 0x20a7, 0x0192,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba,
0x00bf, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp863Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00c2, 0x00e0, 0x00b6, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x2017, 0x00c0, 0x00a7,
0x00c9, 0x00c8, 0x00ca, 0x00f4, 0x00cb, 0x00cf, 0x00fb, 0x00f9,
0x00a4, 0x00d4, 0x00dc, 0x00a2, 0x00a3, 0x00d9, 0x00db, 0x0192,
0x00a6, 0x00b4, 0x00f3, 0x00fa, 0x00a8, 0x00b8, 0x00b3, 0x00af,
0x00ce, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00be, 0x00ab, 0x00bb,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp864Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x066a, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00b0, 0x00b7, 0x2219, 0x221a, 0x2592, 0x2500, 0x2502, 0x253c,
0x2524, 0x252c, 0x251c, 0x2534, 0x2510, 0x250c, 0x2514, 0x2518,
0x03b2, 0x221e, 0x03c6, 0x00b1, 0x00bd, 0x00bc, 0x2248, 0x00ab,
0x00bb, 0xfef7, 0xfef8, 0x0000, 0x0000, 0xfefb, 0xfefc, 0x0000,
0x00a0, 0x00ad, 0xfe82, 0x00a3, 0x00a4, 0xfe84, 0x0000, 0x0000,
0xfe8e, 0xfe8f, 0xfe95, 0xfe99, 0x060c, 0xfe9d, 0xfea1, 0xfea5,
0x0660, 0x0661, 0x0662, 0x0663, 0x0664, 0x0665, 0x0666, 0x0667,
0x0668, 0x0669, 0xfed1, 0x061b, 0xfeb1, 0xfeb5, 0xfeb9, 0x061f,
0x00a2, 0xfe80, 0xfe81, 0xfe83, 0xfe85, 0xfeca, 0xfe8b, 0xfe8d,
0xfe91, 0xfe93, 0xfe97, 0xfe9b, 0xfe9f, 0xfea3, 0xfea7, 0xfea9,
0xfeab, 0xfead, 0xfeaf, 0xfeb3, 0xfeb7, 0xfebb, 0xfebf, 0xfec1,
0xfec5, 0xfecb, 0xfecf, 0x00a6, 0x00ac, 0x00f7, 0x00d7, 0xfec9,
0x0640, 0xfed3, 0xfed7, 0xfedb, 0xfedf, 0xfee3, 0xfee7, 0xfeeb,
0xfeed, 0xfeef, 0xfef3, 0xfebd, 0xfecc, 0xfece, 0xfecd, 0xfee1,
0xfe7d, 0x0651, 0xfee5, 0xfee9, 0xfeec, 0xfef0, 0xfef2, 0xfed0,
0xfed5, 0xfef5, 0xfef6, 0xfedd, 0xfed9, 0xfef1, 0x25a0, 0x00a0
};
static const uint16_t cp865Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x00c7, 0x00fc, 0x00e9, 0x00e2, 0x00e4, 0x00e0, 0x00e5, 0x00e7,
0x00ea, 0x00eb, 0x00e8, 0x00ef, 0x00ee, 0x00ec, 0x00c4, 0x00c5,
0x00c9, 0x00e6, 0x00c6, 0x00f4, 0x00f6, 0x00f2, 0x00fb, 0x00f9,
0x00ff, 0x00d6, 0x00dc, 0x00f8, 0x00a3, 0x00d8, 0x20a7, 0x0192,
0x00e1, 0x00ed, 0x00f3, 0x00fa, 0x00f1, 0x00d1, 0x00aa, 0x00ba,
0x00bf, 0x2310, 0x00ac, 0x00bd, 0x00bc, 0x00a1, 0x00ab, 0x00a4,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x03b1, 0x00df, 0x0393, 0x03c0, 0x03a3, 0x03c3, 0x00b5, 0x03c4,
0x03a6, 0x0398, 0x03a9, 0x03b4, 0x221e, 0x03c6, 0x03b5, 0x2229,
0x2261, 0x00b1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00f7, 0x2248,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x207f, 0x00b2, 0x25a0, 0x00a0
};
static const uint16_t cp866Map[256] = {
0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f,
0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0015, 0x0016, 0x0017,
0x0018, 0x0019, 0x001a, 0x001b, 0x001c, 0x001d, 0x001e, 0x001f,
0x0020, 0x0021, 0x0022, 0x0023, 0x0024, 0x0025, 0x0026, 0x0027,
0x0028, 0x0029, 0x002a, 0x002b, 0x002c, 0x002d, 0x002e, 0x002f,
0x0030, 0x0031, 0x0032, 0x0033, 0x0034, 0x0035, 0x0036, 0x0037,
0x0038, 0x0039, 0x003a, 0x003b, 0x003c, 0x003d, 0x003e, 0x003f,
0x0040, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047,
0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f,
0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057,
0x0058, 0x0059, 0x005a, 0x005b, 0x005c, 0x005d, 0x005e, 0x005f,
0x0060, 0x0061, 0x0062, 0x0063, 0x0064, 0x0065, 0x0066, 0x0067,
0x0068, 0x0069, 0x006a, 0x006b, 0x006c, 0x006d, 0x006e, 0x006f,
0x0070, 0x0071, 0x0072, 0x0073, 0x0074, 0x0075, 0x0076, 0x0077,
0x0078, 0x0079, 0x007a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f,
0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
0x0418, 0x0419, 0x041a, 0x041b, 0x041c, 0x041d, 0x041e, 0x041f,
0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
0x0428, 0x0429, 0x042a, 0x042b, 0x042c, 0x042d, 0x042e, 0x042f,
0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
0x0438, 0x0439, 0x043a, 0x043b, 0x043c, 0x043d, 0x043e, 0x043f,
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
0x2555, 0x2563, 0x2551, 0x2557, 0x255d, 0x255c, 0x255b, 0x2510,
0x2514, 0x2534, 0x252c, 0x251c, 0x2500, 0x253c, 0x255e, 0x255f,
0x255a, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256c, 0x2567,
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256b,
0x256a, 0x2518, 0x250c, 0x2588, 0x2584, 0x258c, 0x2590, 0x2580,
0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
0x0448, 0x0449, 0x044a, 0x044b, 0x044c, 0x044d, 0x044e, 0x044f,
0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040e, 0x045e,
0x00b0, 0x2219, 0x00b7, 0x221a, 0x2116, 0x00a4, 0x25a0, 0x00a0
};
static const struct {
uint16_t code;
const uint16_t *map;
} maps[] = {
// clang-format off
{ 437, cp437Map },
{ 737, cp737Map },
{ 775, cp775Map },
{ 850, cp850Map },
{ 852, cp852Map },
{ 855, cp855Map },
{ 857, cp857Map },
{ 860, cp860Map },
{ 861, cp861Map },
{ 862, cp862Map },
{ 863, cp863Map },
{ 864, cp864Map },
{ 865, cp865Map },
{ 866, cp866Map },
{ -1, NULL }
// clang-format on
};
/* Select a ASCII->Unicode mapping by CP number */
void
select_codepage(uint16_t code, uint16_t *curmap)
{
uint16_t i = 0;
const uint16_t *map_to_use;
map_to_use = maps[0].map;
while (maps[i].code != 0) {
if (maps[i].code == code) {
map_to_use = maps[i].map;
break;
}
i++;
}
for (uint16_t j = 0; j < 256; j++)
curmap[j] = map_to_use[j];
}
``` | /content/code_sandbox/src/printer/prt_cpmap.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 23,500 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a generic PostScript printer and a
* generic PCL 5e printer.
*
*
*
* Authors: David Hrdlika, <hrdlickadavid@outlook.com>
* Cacodemon345
*
*/
#include <inttypes.h>
#include <memory.h>
#include <stdbool.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/lpt.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/plat_dynld.h>
#include <86box/ui.h>
#include <86box/prt_devs.h>
#ifdef _WIN32
# define GSDLLAPI __stdcall
#else
# define GSDLLAPI
#endif
#define GS_ARG_ENCODING_UTF8 1
#define gs_error_Quit -101
#ifdef _WIN32
# if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
# define PATH_GHOSTSCRIPT_DLL "gsdll32.dll"
# define PATH_GHOSTPCL_DLL "gpcl6dll32.dll"
# else
# define PATH_GHOSTSCRIPT_DLL "gsdll64.dll"
# define PATH_GHOSTPCL_DLL "gpcl6dll64.dll"
# endif
#elif defined __APPLE__
# define PATH_GHOSTSCRIPT_DLL "libgs.dylib"
# define PATH_GHOSTPCL_DLL "libgpcl6.9.54.dylib"
#else
# define PATH_GHOSTSCRIPT_DLL "libgs.so.9"
# define PATH_GHOSTSCRIPT_DLL_ALT1 "libgs.so.10"
# define PATH_GHOSTSCRIPT_DLL_ALT2 "libgs.so"
# define PATH_GHOSTPCL_DLL "libgpcl6.so.9"
# define PATH_GHOSTPCL_DLL_ALT1 "libgpcl6.so.10"
# define PATH_GHOSTPCL_DLL_ALT2 "libgpcl6.so"
#endif
#define POSTSCRIPT_BUFFER_LENGTH 65536
typedef struct ps_t {
const char *name;
void *lpt;
pc_timer_t pulse_timer;
pc_timer_t timeout_timer;
char data;
bool ack;
bool select;
bool busy;
bool int_pending;
bool error;
bool autofeed;
bool pcl;
bool pcl_escape;
uint8_t ctrl;
char printer_path[260];
char filename[260];
char buffer[POSTSCRIPT_BUFFER_LENGTH];
size_t buffer_pos;
} ps_t;
typedef struct gsapi_revision_s {
const char *product;
const char *copyright;
long revision;
long revisiondate;
} gsapi_revision_t;
static int(GSDLLAPI *gsapi_revision)(gsapi_revision_t *pr, int len);
static int(GSDLLAPI *gsapi_new_instance)(void **pinstance, void *caller_handle);
static void(GSDLLAPI *gsapi_delete_instance)(void *instance);
static int(GSDLLAPI *gsapi_set_arg_encoding)(void *instance, int encoding);
static int(GSDLLAPI *gsapi_init_with_args)(void *instance, int argc, char **argv);
static int(GSDLLAPI *gsapi_exit)(void *instance);
static dllimp_t ghostscript_imports[] = {
// clang-format off
{ "gsapi_revision", &gsapi_revision },
{ "gsapi_new_instance", &gsapi_new_instance },
{ "gsapi_delete_instance", &gsapi_delete_instance },
{ "gsapi_set_arg_encoding", &gsapi_set_arg_encoding },
{ "gsapi_init_with_args", &gsapi_init_with_args },
{ "gsapi_exit", &gsapi_exit },
{ NULL, NULL }
// clang-format on
};
static void *ghostscript_handle = NULL;
static void
reset_ps(ps_t *dev)
{
if (dev == NULL)
return;
dev->ack = false;
dev->buffer[0] = 0;
dev->buffer_pos = 0;
timer_disable(&dev->pulse_timer);
timer_disable(&dev->timeout_timer);
}
static void
pulse_timer(void *priv)
{
ps_t *dev = (ps_t *) priv;
if (dev->ack) {
dev->ack = 0;
lpt_irq(dev->lpt, 1);
}
timer_disable(&dev->pulse_timer);
}
static int
convert_to_pdf(ps_t *dev)
{
volatile int code, arg = 0;
void *instance = NULL;
char input_fn[1024];
char output_fn[1024];
char *gsargv[11];
strcpy(input_fn, dev->printer_path);
path_slash(input_fn);
strcat(input_fn, dev->filename);
strcpy(output_fn, input_fn);
strcpy(output_fn + strlen(output_fn) - (dev->pcl ? 4 : 3), ".pdf");
gsargv[arg++] = "";
gsargv[arg++] = "-dNOPAUSE";
gsargv[arg++] = "-dBATCH";
gsargv[arg++] = "-dSAFER";
gsargv[arg++] = "-sDEVICE=pdfwrite";
if (dev->pcl) {
gsargv[arg++] = "-LPCL";
gsargv[arg++] = "-lPCL5E";
}
gsargv[arg++] = "-q";
gsargv[arg++] = "-o";
gsargv[arg++] = output_fn;
gsargv[arg++] = input_fn;
code = gsapi_new_instance(&instance, dev);
if (code < 0)
return code;
code = gsapi_set_arg_encoding(instance, GS_ARG_ENCODING_UTF8);
if (code == 0)
code = gsapi_init_with_args(instance, arg, gsargv);
if (code == 0 || code == gs_error_Quit)
code = gsapi_exit(instance);
else
gsapi_exit(instance);
gsapi_delete_instance(instance);
if (code == 0)
plat_remove(input_fn);
else
plat_remove(output_fn);
return code;
}
static void
write_buffer(ps_t *dev, bool finish)
{
char path[1024];
FILE *fp;
if (dev->buffer[0] == 0)
return;
if (dev->filename[0] == 0)
plat_tempfile(dev->filename, NULL, dev->pcl ? ".pcl" : ".ps");
strcpy(path, dev->printer_path);
path_slash(path);
strcat(path, dev->filename);
fp = plat_fopen(path, dev->pcl ? "ab" : "a");
if (fp == NULL)
return;
fseek(fp, 0, SEEK_END);
if (dev->pcl)
fwrite(dev->buffer, 1, dev->buffer_pos, fp);
else
fprintf(fp, "%.*s", POSTSCRIPT_BUFFER_LENGTH, dev->buffer);
fclose(fp);
dev->buffer[0] = 0;
dev->buffer_pos = 0;
if (finish) {
if (ghostscript_handle != NULL)
convert_to_pdf(dev);
dev->filename[0] = 0;
}
}
static void
timeout_timer(void *priv)
{
ps_t *dev = (ps_t *) priv;
write_buffer(dev, true);
timer_disable(&dev->timeout_timer);
}
static void
ps_write_data(uint8_t val, void *priv)
{
ps_t *dev = (ps_t *) priv;
if (dev == NULL)
return;
dev->data = (char) val;
}
static void
process_data(ps_t *dev)
{
/* On PCL, check for escape sequences. */
if (dev->pcl) {
if (dev->data == 0x1B)
dev->pcl_escape = true;
else if (dev->pcl_escape) {
dev->pcl_escape = false;
if (dev->data == 0xE) {
dev->buffer[dev->buffer_pos++] = dev->data;
dev->buffer[dev->buffer_pos] = 0;
if (dev->buffer_pos > 2)
write_buffer(dev, true);
return;
}
}
}
/* On PostScript, check for non-printable characters. */
else if ((dev->data < 0x20) || (dev->data == 0x7f)) {
switch (dev->data) {
/* The following characters are considered white-space
by the PostScript specification */
case '\t':
case '\n':
case '\f':
case '\r':
break;
/* Same with NUL, except we better change it to a space first */
case '\0':
dev->data = ' ';
break;
/* Ctrl+D (0x04) marks the end of the document */
case '\4':
write_buffer(dev, true);
return;
/* Don't bother with the others */
default:
return;
}
}
/* Flush the buffer if we have run to its end */
if (dev->buffer_pos == POSTSCRIPT_BUFFER_LENGTH - 1)
write_buffer(dev, false);
dev->buffer[dev->buffer_pos++] = dev->data;
dev->buffer[dev->buffer_pos] = 0;
}
static void
ps_write_ctrl(uint8_t val, void *priv)
{
ps_t *dev = (ps_t *) priv;
if (dev == NULL)
return;
dev->autofeed = val & 0x02 ? true : false;
if (val & 0x08)
dev->select = true;
if ((val & 0x04) && !(dev->ctrl & 0x04)) {
/* Reset printer */
dev->select = false;
reset_ps(dev);
}
if (!(val & 0x01) && (dev->ctrl & 0x01)) {
process_data(dev);
dev->ack = true;
timer_set_delay_u64(&dev->pulse_timer, ISACONST);
timer_set_delay_u64(&dev->timeout_timer, 5000000 * TIMER_USEC);
}
dev->ctrl = val;
}
static uint8_t
ps_read_status(void *priv)
{
const ps_t *dev = (ps_t *) priv;
uint8_t ret = 0x9f;
if (!dev->ack)
ret |= 0x40;
return ret;
}
static void *
ps_init(void *lpt)
{
ps_t *dev;
gsapi_revision_t rev;
dev = (ps_t *) malloc(sizeof(ps_t));
memset(dev, 0x00, sizeof(ps_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL, ghostscript_imports);
#ifdef PATH_GHOSTSCRIPT_DLL_ALT1
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT1, ghostscript_imports);
# ifdef PATH_GHOSTSCRIPT_DLL_ALT2
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTSCRIPT_DLL_ALT2, ghostscript_imports);
# endif
}
#endif
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTSCRIPT_ERROR_TITLE), plat_get_string(STRING_GHOSTSCRIPT_ERROR_DESC));
} else {
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
}
}
/* Cache print folder path. */
memset(dev->printer_path, 0x00, sizeof(dev->printer_path));
path_append_filename(dev->printer_path, usr_path, "printer");
if (!plat_dir_check(dev->printer_path))
plat_dir_create(dev->printer_path);
path_slash(dev->printer_path);
timer_add(&dev->pulse_timer, pulse_timer, dev, 0);
timer_add(&dev->timeout_timer, timeout_timer, dev, 0);
reset_ps(dev);
return dev;
}
#ifdef USE_PCL
static void *
pcl_init(void *lpt)
{
ps_t *dev;
gsapi_revision_t rev;
dev = (ps_t *) malloc(sizeof(ps_t));
memset(dev, 0x00, sizeof(ps_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
dev->pcl = true;
/* Try loading the DLL. */
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL, ghostscript_imports);
#ifdef PATH_GHOSTPCL_DLL_ALT1
if (ghostscript_handle == NULL) {
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT1, ghostscript_imports);
# ifdef PATH_GHOSTPCL_DLL_ALT2
if (ghostscript_handle == NULL)
ghostscript_handle = dynld_module(PATH_GHOSTPCL_DLL_ALT2, ghostscript_imports);
# endif
}
#endif
if (ghostscript_handle == NULL) {
ui_msgbox_header(MBX_ERROR, plat_get_string(STRING_GHOSTPCL_ERROR_TITLE), plat_get_string(STRING_GHOSTPCL_ERROR_DESC));
} else {
if (gsapi_revision(&rev, sizeof(rev)) == 0) {
pclog("Loaded %s, rev %ld (%ld)\n", rev.product, rev.revision, rev.revisiondate);
} else {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
}
}
/* Cache print folder path. */
memset(dev->printer_path, 0x00, sizeof(dev->printer_path));
path_append_filename(dev->printer_path, usr_path, "printer");
if (!plat_dir_check(dev->printer_path))
plat_dir_create(dev->printer_path);
path_slash(dev->printer_path);
timer_add(&dev->pulse_timer, pulse_timer, dev, 0);
timer_add(&dev->timeout_timer, timeout_timer, dev, 0);
reset_ps(dev);
return dev;
}
#endif
static void
ps_close(void *priv)
{
ps_t *dev = (ps_t *) priv;
if (dev == NULL)
return;
if (dev->buffer[0] != 0)
write_buffer(dev, true);
if (ghostscript_handle != NULL) {
dynld_close(ghostscript_handle);
ghostscript_handle = NULL;
}
free(dev);
}
const lpt_device_t lpt_prt_ps_device = {
.name = "Generic PostScript Printer",
.internal_name = "postscript",
.init = ps_init,
.close = ps_close,
.write_data = ps_write_data,
.write_ctrl = ps_write_ctrl,
.read_data = NULL,
.read_status = ps_read_status,
.read_ctrl = NULL
};
#ifdef USE_PCL
const lpt_device_t lpt_prt_pcl_device = {
.name = "Generic PCL5e Printer",
.internal_name = "pcl",
.init = pcl_init,
.close = ps_close,
.write_data = ps_write_data,
.write_ctrl = ps_write_ctrl,
.read_data = NULL,
.read_status = ps_read_status,
.read_ctrl = NULL
};
#endif
``` | /content/code_sandbox/src/printer/prt_ps.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,551 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Provide centralized access to the PNG image handler.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <errno.h>
#define PNG_DEBUG 0
#include <png.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/plat.h>
#include <86box/plat_dynld.h>
#include <86box/ui.h>
#include <86box/video.h>
#include <86box/png_struct.h>
#ifdef _WIN32
# define PATH_PNG_DLL "libpng16-16.dll"
#elif defined __APPLE__
# define PATH_PNG_DLL "libpng16.dylib"
#else
# define PATH_PNG_DLL "libpng16.so"
#endif
#ifndef PNG_Z_DEFAULT_STRATEGY
# define PNG_Z_DEFAULT_STRATEGY 1
#endif
#define PNGFUNC(x) png_##x
#ifdef ENABLE_PNG_LOG
int png_do_log = ENABLE_PNG_LOG;
static void
png_log(const char *fmt, ...)
{
va_list ap;
if (png_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define png_log(fmt, ...)
#endif
static void
error_handler(UNUSED(png_structp arg), UNUSED(const char *str))
{
png_log("PNG: stream 0x%08lx error '%s'\n", arg, str);
}
static void
warning_handler(UNUSED(png_structp arg), UNUSED(const char *str))
{
png_log("PNG: stream 0x%08lx warning '%s'\n", arg, str);
}
/* Write the given image as an 8-bit GrayScale PNG image file. */
int
png_write_gray(char *fn, int inv, uint8_t *pix, int16_t w, int16_t h)
{
png_structp png = NULL;
png_infop info = NULL;
png_bytep row;
FILE *fp;
/* Create the image file. */
fp = plat_fopen(fn, "wb");
if (fp == NULL) {
/* Yes, this looks weird. */
if (fp == NULL)
png_log("PNG: file %s could not be opened for writing!\n", fn);
else
error:
png_log("PNG: fatal error, bailing out, error = %i\n", errno);
if (png != NULL)
PNGFUNC(destroy_write_struct)
(&png, &info);
if (fp != NULL)
(void) fclose(fp);
return 0;
}
/* Initialize PNG stuff. */
png = PNGFUNC(create_write_struct)(PNG_LIBPNG_VER_STRING, NULL,
error_handler, warning_handler);
if (png == NULL) {
png_log("PNG: create_write_struct failed!\n");
goto error;
}
info = PNGFUNC(create_info_struct)(png);
if (info == NULL) {
png_log("PNG: create_info_struct failed!\n");
goto error;
}
PNGFUNC(init_io)
(png, fp);
PNGFUNC(set_IHDR)
(png, info, w, h, 8, PNG_COLOR_TYPE_GRAY,
PNG_INTERLACE_NONE, PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
PNGFUNC(write_info)
(png, info);
/* Create a buffer for one scanline of pixels. */
row = (png_bytep) malloc(PNGFUNC(get_rowbytes)(png, info));
/* Process all scanlines in the image. */
for (int16_t y = 0; y < h; y++) {
for (int16_t x = 0; x < w; x++) {
/* Copy the pixel data. */
if (inv)
row[x] = 255 - pix[(y * w) + x];
else
row[x] = pix[(y * w) + x];
}
/* Write image to the file. */
PNGFUNC(write_rows)
(png, &row, 1);
}
/* No longer need the row buffer. */
free(row);
PNGFUNC(write_end)
(png, NULL);
PNGFUNC(destroy_write_struct)
(&png, &info);
/* Clean up. */
(void) fclose(fp);
return 1;
}
/* Write the given BITMAP-format image as an 8-bit RGBA PNG image file. */
void
png_write_rgb(char *fn, uint8_t *pix, int16_t w, int16_t h, uint16_t pitch, PALETTE palcol)
{
png_structp png = NULL;
png_infop info = NULL;
png_bytep *rows;
png_color palette[256];
FILE *fp;
/* Create the image file. */
fp = plat_fopen(fn, "wb");
if (fp == NULL) {
png_log("PNG: File %s could not be opened for writing!\n", fn);
error:
if (png != NULL)
PNGFUNC(destroy_write_struct)
(&png, &info);
if (fp != NULL)
(void) fclose(fp);
return;
}
/* Initialize PNG stuff. */
png = PNGFUNC(create_write_struct)(PNG_LIBPNG_VER_STRING, NULL,
error_handler, warning_handler);
if (png == NULL) {
png_log("PNG: create_write_struct failed!\n");
goto error;
}
info = PNGFUNC(create_info_struct)(png);
if (info == NULL) {
png_log("PNG: create_info_struct failed!\n");
goto error;
}
/* Finalize the initing of png library */
PNGFUNC(init_io)
(png, fp);
PNGFUNC(set_compression_level)
(png, 9);
/* set other zlib parameters */
PNGFUNC(set_compression_mem_level)
(png, 8);
PNGFUNC(set_compression_strategy)
(png, PNG_Z_DEFAULT_STRATEGY);
PNGFUNC(set_compression_window_bits)
(png, 15);
PNGFUNC(set_compression_method)
(png, 8);
PNGFUNC(set_compression_buffer_size)
(png, 8192);
PNGFUNC(set_IHDR)
(png, info, w, h, 8, PNG_COLOR_TYPE_PALETTE,
PNG_INTERLACE_NONE, PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
for (uint16_t i = 0; i < 256; i++) {
palette[i].red = palcol[i].r;
palette[i].green = palcol[i].g;
palette[i].blue = palcol[i].b;
}
PNGFUNC(set_PLTE)
(png, info, palette, 256);
/* Create a buffer for scanlines of pixels. */
rows = (png_bytep *) malloc(sizeof(png_bytep) * h);
for (int16_t i = 0; i < h; i++) {
/* Create a buffer for this scanline. */
rows[i] = (pix + (i * pitch));
}
PNGFUNC(set_rows)
(png, info, rows);
PNGFUNC(write_png)
(png, info, 0, NULL);
/* Clean up. */
(void) fclose(fp);
PNGFUNC(destroy_write_struct)
(&png, &info);
/* No longer need the row buffers. */
free(rows);
}
``` | /content/code_sandbox/src/printer/png.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,085 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of a generic text printer.
*
* Simple old text printers were unable to do any formatting
* of the text. They were just sheets of paper with a fixed
* size (in the U.S., this would be Letter, 8.5"x11") with a
* set of fixed margings to allow for proper operation of the
* printer mechanics. This would lead to a page being 66 lines
* of 80 characters each.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/lpt.h>
#include <86box/printer.h>
#include <86box/prt_devs.h>
#define FULL_PAGE 1 /* set if no top/bot margins */
/* Default page values (for now.) */
#define PAGE_WIDTH 8.5 /* standard U.S. Letter */
#define PAGE_HEIGHT 11
#define PAGE_LMARGIN 0.25 /* 0.25" left and right */
#define PAGE_RMARGIN 0.25
#if FULL_PAGE
# define PAGE_TMARGIN 0
# define PAGE_BMARGIN 0
#else
# define PAGE_TMARGIN 0.25
# define PAGE_BMARGIN 0.25
#endif
#define PAGE_CPI 10.0 /* standard 10 cpi */
#define PAGE_LPI 6.0 /* standard 6 lpi */
typedef struct psurface_t {
int8_t dirty; /* has the page been printed on? */
char pad;
uint8_t w; /* size //INFO */
uint8_t h;
char *chars; /* character data */
} psurface_t;
typedef struct prnt_t {
const char *name;
void *lpt;
/* Output file name. */
char filename[1024];
/* Printer timeout. */
pc_timer_t pulse_timer;
pc_timer_t timeout_timer;
/* page data (TODO: make configurable) */
double page_width; /* all in inches */
double page_height;
double left_margin;
double top_margin;
double right_margin;
double bot_margin;
/* internal page data */
psurface_t *page;
uint8_t max_chars;
uint8_t max_lines;
uint8_t curr_x; /* print head position (x, chars) */
uint8_t curr_y; /* print head position (y, chars) */
/* font data */
double cpi; /* defined chars per inch */
double lpi; /* defined lines per inch */
/* handshake data */
uint8_t data;
int8_t ack;
int8_t select;
int8_t busy;
int8_t int_pending;
int8_t error;
int8_t autofeed;
uint8_t ctrl;
} prnt_t;
/* Dump the current page into a formatted file. */
static void
dump_page(prnt_t *dev)
{
char path[1024];
uint8_t ch;
FILE *fp;
/* Create the full path for this file. */
memset(path, 0x00, sizeof(path));
path_append_filename(path, usr_path, "printer");
if (!plat_dir_check(path))
plat_dir_create(path);
path_slash(path);
strcat(path, dev->filename);
/* Create the file. */
fp = plat_fopen(path, "a");
if (fp == NULL) {
// ERRLOG("PRNT: unable to create print page '%s'\n", path);
return;
}
fseek(fp, 0, SEEK_END);
/* If this is not a new file, add a formfeed first. */
if (ftell(fp) != 0)
fputc('\014', fp);
for (uint16_t y = 0; y < dev->curr_y; y++) {
for (uint16_t x = 0; x < dev->page->w; x++) {
ch = dev->page->chars[(y * dev->page->w) + x];
if (ch == 0x00) {
/* End of line marker. */
fputc('\n', fp);
break;
} else {
fputc(ch, fp);
}
}
}
/* All done, close the file. */
fclose(fp);
}
static void
new_page(prnt_t *dev)
{
/* Dump the current page if needed. */
if (dev->page->dirty)
dump_page(dev);
/* Clear page. */
memset(dev->page->chars, 0x00, dev->page->h * dev->page->w);
dev->curr_y = 0;
dev->page->dirty = 0;
}
static void
pulse_timer(void *priv)
{
prnt_t *dev = (prnt_t *) priv;
if (dev->ack) {
dev->ack = 0;
lpt_irq(dev->lpt, 1);
}
timer_disable(&dev->pulse_timer);
}
static void
timeout_timer(void *priv)
{
prnt_t *dev = (prnt_t *) priv;
if (dev->page->dirty)
new_page(dev);
timer_disable(&dev->timeout_timer);
}
static void
reset_printer(prnt_t *dev)
{
/* TODO: these three should be configurable */
dev->page_width = PAGE_WIDTH;
dev->page_height = PAGE_HEIGHT;
dev->left_margin = PAGE_LMARGIN;
dev->right_margin = PAGE_RMARGIN;
dev->top_margin = PAGE_TMARGIN;
dev->bot_margin = PAGE_BMARGIN;
dev->cpi = PAGE_CPI;
dev->lpi = PAGE_LPI;
dev->ack = 0;
/* Default page layout. */
dev->max_chars = (int) ((dev->page_width - dev->left_margin - dev->right_margin) * dev->cpi);
dev->max_lines = (int) ((dev->page_height - dev->top_margin - dev->bot_margin) * dev->lpi);
dev->curr_x = dev->curr_y = 0;
if (dev->page != NULL)
dev->page->dirty = 0;
/* Create a file for this page. */
plat_tempfile(dev->filename, NULL, ".txt");
timer_disable(&dev->pulse_timer);
timer_disable(&dev->timeout_timer);
}
static int
process_char(prnt_t *dev, uint8_t ch)
{
uint8_t i;
switch (ch) {
case 0x07: /* Beeper (BEL) */
/* TODO: beep? */
return 1;
case 0x08: /* Backspace (BS) */
if (dev->curr_x > 0)
dev->curr_x--;
return 1;
case 0x09: /* Tab horizontally (HT) */
/* Find tab right to current pos. */
i = dev->curr_x;
dev->page->chars[(dev->curr_y * dev->page->w) + i++] = ' ';
while ((i < dev->max_chars) && ((i % 8) != 0)) {
dev->page->chars[(dev->curr_y * dev->page->w) + i] = ' ';
i++;
}
dev->curr_x = i;
return 1;
case 0x0b: /* Tab vertically (VT) */
dev->curr_x = 0;
return 1;
case 0x0c: /* Form feed (FF) */
new_page(dev);
return 1;
case 0x0d: /* Carriage Return (CR) */
dev->curr_x = 0;
if (!dev->autofeed)
return 1;
fallthrough;
case 0x0a: /* Line feed */
dev->curr_x = 0;
if (++dev->curr_y >= dev->max_lines)
new_page(dev);
return 1;
case 0x0e: /* select wide printing (SO) */
/* Ignore. */
return 1;
case 0x0f: /* select condensed printing (SI) */
/* Ignore. */
return 1;
case 0x11: /* select printer (DC1) */
/* Ignore. */
return 0;
case 0x12: /* cancel condensed printing (DC2) */
/* Ignore. */
return 1;
case 0x13: /* deselect printer (DC3) */
/* Ignore. */
return 1;
case 0x14: /* cancel double-width printing (one line) (DC4) */
/* Ignore. */
return 1;
case 0x18: /* cancel line (CAN) */
/* Ignore. */
return 1;
case 0x1b: /* ESC */
/* Ignore. */
return 1;
default:
break;
}
/* Just a printable character. */
return 0;
}
static void
handle_char(prnt_t *dev)
{
uint8_t ch = dev->data;
if (dev->page == NULL)
return;
if (process_char(dev, ch) == 1) {
/* Command was processed. */
return;
}
/* Store character in the page buffer. */
dev->page->chars[(dev->curr_y * dev->page->w) + dev->curr_x] = ch;
dev->page->dirty = 1;
/* Update print head position. */
if (++dev->curr_x >= dev->max_chars) {
dev->curr_x = 0;
if (++dev->curr_y >= dev->max_lines)
new_page(dev);
}
}
static void
write_data(uint8_t val, void *priv)
{
prnt_t *dev = (prnt_t *) priv;
if (dev == NULL)
return;
dev->data = val;
}
static void
write_ctrl(uint8_t val, void *priv)
{
prnt_t *dev = (prnt_t *) priv;
if (dev == NULL)
return;
/* set autofeed value */
dev->autofeed = val & 0x02 ? 1 : 0;
if (val & 0x08) { /* SELECT */
/* select printer */
dev->select = 1;
}
if ((val & 0x04) && !(dev->ctrl & 0x04)) {
/* reset printer */
dev->select = 0;
reset_printer(dev);
}
if (!(val & 0x01) && (dev->ctrl & 0x01)) { /* STROBE */
/* Process incoming character. */
handle_char(dev);
/* ACK it, will be read on next READ STATUS. */
dev->ack = 1;
timer_set_delay_u64(&dev->pulse_timer, ISACONST);
timer_set_delay_u64(&dev->timeout_timer, 5000000 * TIMER_USEC);
}
dev->ctrl = val;
}
static uint8_t
read_status(void *priv)
{
const prnt_t *dev = (prnt_t *) priv;
uint8_t ret = 0x1f;
ret |= 0x80;
if (!dev->ack)
ret |= 0x40;
return ret;
}
static void *
prnt_init(void *lpt)
{
prnt_t *dev;
/* Initialize a device instance. */
dev = (prnt_t *) malloc(sizeof(prnt_t));
memset(dev, 0x00, sizeof(prnt_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
/* Initialize parameters. */
reset_printer(dev);
/* Create a page buffer. */
dev->page = (psurface_t *) malloc(sizeof(psurface_t));
dev->page->w = dev->max_chars;
dev->page->h = dev->max_lines;
dev->page->chars = (char *) malloc(dev->page->w * dev->page->h);
memset(dev->page->chars, 0x00, dev->page->w * dev->page->h);
timer_add(&dev->pulse_timer, pulse_timer, dev, 0);
timer_add(&dev->timeout_timer, timeout_timer, dev, 0);
return dev;
}
static void
prnt_close(void *priv)
{
prnt_t *dev = (prnt_t *) priv;
if (dev == NULL)
return;
if (dev->page) {
/* print last page if it contains data */
if (dev->page->dirty)
dump_page(dev);
if (dev->page->chars != NULL)
free(dev->page->chars);
free(dev->page);
}
free(dev);
}
const lpt_device_t lpt_prt_text_device = {
.name = "Generic Text Printer",
.internal_name = "text_prt",
.init = prnt_init,
.close = prnt_close,
.write_data = write_data,
.write_ctrl = write_ctrl,
.read_data = NULL,
.read_status = read_status,
.read_ctrl = NULL
};
``` | /content/code_sandbox/src/printer/prt_text.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,437 |
```objective-c
uint32_t ropFLD1(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFLDZ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_constant.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 87 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_mmx_arith.h"
#include "codegen_ops_helpers.h"
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
}
// clang-format off
ropParith(PADDB)
ropParith(PADDW)
ropParith(PADDD)
ropParith(PADDSB)
ropParith(PADDSW)
ropParith(PADDUSB)
ropParith(PADDUSW)
ropParith(PSUBB)
ropParith(PSUBW)
ropParith(PSUBD)
ropParith(PSUBSB)
ropParith(PSUBSW)
ropParith(PSUBUSB)
ropParith(PSUBUSW)
ropParith(PMADDWD)
ropParith(PMULHW)
ropParith(PMULLW)
// clang-format on
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_arith.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 586 |
```objective-c
uint32_t ropPSxxW_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSxxD_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSxxQ_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSLLW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSLLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSLLQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_shift.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 262 |
```objective-c
enum {
ACCREG_cycles = 0,
ACCREG_COUNT
};
struct ir_data_t;
void codegen_accumulate(struct ir_data_t *ir, int acc_reg, int delta);
void codegen_accumulate_flush(struct ir_data_t *ir);
void codegen_accumulate_reset(void);
``` | /content/code_sandbox/src/codegen_new/codegen_accumulate.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 62 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ir_defs.h"
#include "codegen_reg.h"
#include "codegen_ops_helpers.h"
void
LOAD_IMMEDIATE_FROM_RAM_16_unaligned(UNUSED(codeblock_t *block), ir_data_t *ir, int dest_reg, uint32_t addr)
{
/*Word access that crosses two pages. Perform reads from both pages, shift and combine*/
uop_MOVZX_REG_PTR_8(ir, IREG_temp3_W, get_ram_ptr(addr));
uop_MOVZX_REG_PTR_8(ir, dest_reg, get_ram_ptr(addr + 1));
uop_SHL_IMM(ir, IREG_temp3_W, IREG_temp3_W, 8);
uop_OR(ir, dest_reg, dest_reg, IREG_temp3_W);
}
void
LOAD_IMMEDIATE_FROM_RAM_32_unaligned(UNUSED(codeblock_t *block), ir_data_t *ir, int dest_reg, uint32_t addr)
{
/*Dword access that crosses two pages. Perform reads from both pages, shift and combine*/
uop_MOV_REG_PTR(ir, dest_reg, get_ram_ptr(addr & ~3));
uop_MOV_REG_PTR(ir, IREG_temp3, get_ram_ptr((addr + 4) & ~3));
uop_SHR_IMM(ir, dest_reg, dest_reg, (addr & 3) * 8);
uop_SHL_IMM(ir, IREG_temp3, IREG_temp3, (4 - (addr & 3)) * 8);
uop_OR(ir, dest_reg, dest_reg, IREG_temp3);
}
#define UNROLL_MAX_REG_REFERENCES 200
#define UNROLL_MAX_UOPS 1000
#define UNROLL_MAX_COUNT 10
int
codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, UNUSED(uint32_t next_pc), uint32_t dest_addr)
{
int start;
int max_unroll;
int first_instruction;
int TOP = -1;
/*Check that dest instruction was actually compiled into block*/
start = codegen_get_instruction_uop(block, dest_addr, &first_instruction, &TOP);
/*Couldn't find any uOPs corresponding to the destination instruction*/
if (start == -1) {
/*Is instruction jumping to itself?*/
if (dest_addr != cpu_state.oldpc) {
return 0;
} else {
start = ir->wr_pos;
TOP = cpu_state.TOP;
}
}
if (TOP != cpu_state.TOP)
return 0;
max_unroll = UNROLL_MAX_UOPS / ((ir->wr_pos - start) + 6);
if ((max_version_refcount != 0) && (max_unroll > (UNROLL_MAX_REG_REFERENCES / max_version_refcount)))
max_unroll = (UNROLL_MAX_REG_REFERENCES / max_version_refcount);
if (max_unroll > UNROLL_MAX_COUNT)
max_unroll = UNROLL_MAX_COUNT;
if (max_unroll <= 1)
return 0;
codegen_ir_set_unroll(max_unroll, start, first_instruction);
return 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_helpers.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 744 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "x87_sf.h"
#include "x87.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_fpu_constant.h"
#include "codegen_ops_helpers.h"
uint32_t
ropFLD1(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_MOV_IMM(ir, IREG_temp0, 1);
uop_MOV_DOUBLE_INT(ir, IREG_ST(-1), IREG_temp0);
uop_MOV_IMM(ir, IREG_tag(-1), TAG_VALID);
fpu_PUSH(block, ir);
return op_pc;
}
uint32_t
ropFLDZ(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_MOV_IMM(ir, IREG_temp0, 0);
uop_MOV_DOUBLE_INT(ir, IREG_ST(-1), IREG_temp0);
uop_MOV_IMM(ir, IREG_tag(-1), TAG_VALID);
fpu_PUSH(block, ir);
return op_pc;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_constant.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 360 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of the Generic ESC/P Dot-Matrix printer.
*
*
*
* Authors: Michael Dring, <michael@drueing.de>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
* Based on code by Frederic Weymann (originally for DosBox.)
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <ft2build.h>
#include FT_FREETYPE_H
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/pit.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/lpt.h>
#include <86box/video.h>
#include <86box/png_struct.h>
#include <86box/printer.h>
#include <86box/prt_devs.h>
/* Default page values (for now.) */
#define COLOR_BLACK 7 << 5
#define PAGE_WIDTH 8.5 /* standard U.S. Letter */
#define PAGE_HEIGHT 11.0
#define PAGE_LMARGIN 0.0
#define PAGE_RMARGIN PAGE_WIDTH
#define PAGE_TMARGIN 0.0
#define PAGE_BMARGIN PAGE_HEIGHT
#define PAGE_DPI 360
#define PAGE_CPI 10.0 /* standard 10 cpi */
#define PAGE_LPI 6.0 /* standard 6 lpi */
/* FreeType library handles - global so they can be shared. */
FT_Library ft_lib = NULL;
/* The fonts. */
#define FONT_DEFAULT 0
#define FONT_ROMAN 1
#define FONT_SANSSERIF 2
#define FONT_COURIER 3
#define FONT_SCRIPT 4
#define FONT_OCRA 5
#define FONT_OCRB 6
/* Font styles. */
#define STYLE_PROP 0x0001
#define STYLE_CONDENSED 0x0002
#define STYLE_BOLD 0x0004
#define STYLE_DOUBLESTRIKE 0x0008
#define STYLE_DOUBLEWIDTH 0x0010
#define STYLE_ITALICS 0x0020
#define STYLE_UNDERLINE 0x0040
#define STYLE_SUPERSCRIPT 0x0080
#define STYLE_SUBSCRIPT 0x0100
#define STYLE_STRIKETHROUGH 0x0200
#define STYLE_OVERSCORE 0x0400
#define STYLE_DOUBLEWIDTHONELINE 0x0800
#define STYLE_DOUBLEHEIGHT 0x1000
/* Underlining styles. */
#define SCORE_NONE 0x00
#define SCORE_SINGLE 0x01
#define SCORE_DOUBLE 0x02
#define SCORE_SINGLEBROKEN 0x05
#define SCORE_DOUBLEBROKEN 0x06
/* Print quality. */
#define QUALITY_DRAFT 0x01
#define QUALITY_LQ 0x02
/* Typefaces. */
#define TYPEFACE_ROMAN 0
#define TYPEFACE_SANSSERIF 1
#define TYPEFACE_COURIER 2
#define TYPEFACE_PRESTIGE 3
#define TYPEFACE_SCRIPT 4
#define TYPEFACE_OCRB 5
#define TYPEFACE_OCRA 6
#define TYPEFACE_ORATOR 7
#define TYPEFACE_ORATORS 8
#define TYPEFACE_SCRIPTC 9
#define TYPEFACE_ROMANT 10
#define TYPEFACE_SANSSERIFH 11
#define TYPEFACE_SVBUSABA 30
#define TYPEFACE_SVJITTRA 31
/* Some helper macros. */
#define PARAM16(x) (dev->esc_parms[x + 1] * 256 + dev->esc_parms[x])
#define PIXX ((unsigned) floor(dev->curr_x * dev->dpi + 0.5))
#define PIXY ((unsigned) floor(dev->curr_y * dev->dpi + 0.5))
typedef struct psurface_t {
int8_t dirty; /* has the page been printed on? */
char pad;
uint16_t w; /* size and pitch //INFO */
uint16_t h;
uint16_t pitch;
uint8_t *pixels; /* grayscale pixel data */
} psurface_t;
typedef struct escp_t {
const char *name;
void *lpt;
pc_timer_t pulse_timer;
pc_timer_t timeout_timer;
char page_fn[260];
uint8_t color;
/* page data (TODO: make configurable) */
double page_width; /* all in inches */
double page_height;
double left_margin;
double top_margin;
double right_margin;
double bottom_margin;
uint16_t dpi;
double cpi; /* defined chars per inch */
double lpi; /* defined lines per inch */
/* font data */
double actual_cpi; /* actual cpi as with current font */
double linespacing; /* in inch */
double hmi; /* hor. motion index (inch); overrides CPI */
/* tabstops */
double horizontal_tabs[32];
uint8_t num_horizontal_tabs;
double vertical_tabs[16];
int8_t num_vertical_tabs;
/* bit graphics data */
uint16_t bg_h_density; /* in dpi */
uint16_t bg_v_density; /* in dpi */
int8_t bg_adjacent; /* print adjacent pixels (ignored) */
uint8_t bg_bytes_per_column;
uint16_t bg_remaining_bytes; /* #bytes left before img is complete */
uint8_t bg_column[6]; /* #bytes of the current and last col */
uint8_t bg_bytes_read; /* #bytes read so far for current col */
/* handshake data */
uint8_t data;
uint8_t ack;
uint8_t select;
uint8_t busy;
uint8_t int_pending;
uint8_t error;
uint8_t autofeed;
/* ESC command data */
int8_t esc_seen; /* set to 1 if an ESC char was seen */
int8_t fss_seen;
uint16_t esc_pending; /* in which ESC command are we */
uint8_t esc_parms_req;
uint8_t esc_parms_curr;
uint8_t esc_parms[20]; /* 20 should be enough for everybody */
/* internal page data */
char fontpath[1024];
char pagepath[1024];
psurface_t *page;
double curr_x; /* print head position (x, inch) */
double curr_y; /* print head position (y, inch) */
uint16_t current_font;
FT_Face fontface;
int8_t lq_typeface;
uint16_t font_style;
uint8_t print_quality;
uint8_t font_score;
double extra_intra_space; /* extra spacing between chars (inch) */
/* other internal data */
uint16_t char_tables[4]; /* the character tables for ESC t */
uint8_t curr_char_table; /* the active char table index */
uint16_t curr_cpmap[256]; /* current ASCII->Unicode map table */
int8_t multipoint_mode; /* multipoint mode, ESC X */
double multipoint_size; /* size of font, in points */
double multipoint_cpi; /* chars per inch in multipoint mode */
uint8_t density_k; /* density modes for ESC K/L/Y/Z */
uint8_t density_l;
uint8_t density_y;
uint8_t density_z;
int8_t print_upper_control; /* ESC 6, ESC 7 */
int8_t print_everything_count; /* for ESC ( ^ */
double defined_unit; /* internal unit for some ESC/P
* commands. -1 = use default */
uint8_t msb; /* MSB mode, -1 = off */
uint8_t ctrl;
PALETTE palcol;
} escp_t;
static void
update_font(escp_t *dev);
static void
blit_glyph(escp_t *dev, unsigned destx, unsigned desty, int8_t add);
static void
draw_hline(escp_t *dev, unsigned from_x, unsigned to_x, unsigned y, int8_t broken);
static void
init_codepage(escp_t *dev, uint16_t num);
static void
reset_printer(escp_t *dev);
static void
setup_bit_image(escp_t *dev, uint8_t density, uint16_t num_columns);
static void
print_bit_graph(escp_t *dev, uint8_t ch);
static void
new_page(escp_t *dev, int8_t save, int8_t resetx);
/* Codepage table, needed for ESC t ( */
static const uint16_t codepages[15] = {
0, 437, 932, 850, 851, 853, 855, 860,
863, 865, 852, 857, 862, 864, 866
};
/* "patches" to the codepage for the international charsets
* these bytes patch the following 12 positions of the char table, in order:
* 0x23 0x24 0x40 0x5b 0x5c 0x5d 0x5e 0x60 0x7b 0x7c 0x7d 0x7e
* TODO: Implement the missing international charsets
*/
static const uint16_t intCharSets[15][12] = {
{0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 0 USA */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e},
{ 0x0023, 0x0024, 0x00e0, 0x00ba, 0x00e7, 0x00a7, /* 1 France */
0x005e, 0x0060, 0x00e9, 0x00f9, 0x00e8, 0x00a8},
{ 0x0023, 0x0024, 0x00a7, 0x00c4, 0x00d6, 0x00dc, /* 2 Germany */
0x005e, 0x0060, 0x00e4, 0x00f6, 0x00fc, 0x00df},
{ 0x00a3, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 3 UK */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e},
{ 0x0023, 0x0024, 0x0040, 0x00c6, 0x00d8, 0x00c5, /* 4 Denmark (1) */
0x005e, 0x0060, 0x00e6, 0x00f8, 0x00e5, 0x007e},
{ 0x0023, 0x00a4, 0x00c9, 0x00c4, 0x00d6, 0x00c5, /* 5 Sweden */
0x00dc, 0x00e9, 0x00e4, 0x00f6, 0x00e5, 0x00fc},
{ 0x0023, 0x0024, 0x0040, 0x00ba, 0x005c, 0x00e9, /* 6 Italy */
0x005e, 0x00f9, 0x00e0, 0x00f2, 0x00e8, 0x00ec},
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 7 Spain 1 */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 8 Japan (English) */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 9 Norway */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 10 Denmark (2) */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 11 Spain (2) */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 12 Latin America */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x0040, 0x005b, 0x005c, 0x005d, /* 13 Korea */
0x005e, 0x0060, 0x007b, 0x007c, 0x007d, 0x007e}, /* TODO */
{ 0x0023, 0x0024, 0x00a7, 0x00c4, 0x0027, 0x0022, /* 14 Legal */
0x00b6, 0x0060, 0x00a9, 0x00ae, 0x2020, 0x2122}
};
#ifdef ENABLE_ESCP_LOG
int escp_do_log = ENABLE_ESCP_LOG;
static void
escp_log(const char *fmt, ...)
{
va_list ap;
if (escp_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define escp_log(fmt, ...)
#endif
/* Dump the current page into a formatted file. */
static void
dump_page(escp_t *dev)
{
char path[1024];
strcpy(path, dev->pagepath);
strcat(path, dev->page_fn);
png_write_rgb(path, dev->page->pixels, dev->page->w, dev->page->h, dev->page->pitch, dev->palcol);
}
static void
new_page(escp_t *dev, int8_t save, int8_t resetx)
{
/* Dump the current page if needed. */
if (save && dev->page)
dump_page(dev);
if (resetx)
dev->curr_x = dev->left_margin;
/* Clear page. */
dev->curr_y = dev->top_margin;
if (dev->page) {
dev->page->dirty = 0;
memset(dev->page->pixels, 0x00, (size_t) dev->page->pitch * dev->page->h);
}
/* Make the page's file name. */
plat_tempfile(dev->page_fn, NULL, ".png");
}
static void
pulse_timer(void *priv)
{
escp_t *dev = (escp_t *) priv;
if (dev->ack) {
dev->ack = 0;
lpt_irq(dev->lpt, 1);
}
timer_disable(&dev->pulse_timer);
}
static void
timeout_timer(void *priv)
{
escp_t *dev = (escp_t *) priv;
if (dev->page->dirty)
new_page(dev, 1, 1);
timer_disable(&dev->timeout_timer);
}
static void
fill_palette(uint8_t redmax, uint8_t greenmax, uint8_t bluemax, uint8_t colorID, escp_t *dev)
{
uint8_t colormask;
double red = (double) redmax / (double) 30.9;
double green = (double) greenmax / (double) 30.9;
double blue = (double) bluemax / (double) 30.9;
colormask = colorID <<= 5;
for (uint8_t i = 0; i < 32; i++) {
dev->palcol[i + colormask].r = 255 - (uint8_t) floor(red * (double) i);
dev->palcol[i + colormask].g = 255 - (uint8_t) floor(green * (double) i);
dev->palcol[i + colormask].b = 255 - (uint8_t) floor(blue * (double) i);
}
}
static void
reset_printer(escp_t *dev)
{
/* TODO: these should be configurable. */
dev->color = COLOR_BLACK;
dev->curr_x = dev->curr_y = 0.0;
dev->esc_seen = 0;
dev->fss_seen = 0;
dev->esc_pending = 0;
dev->esc_parms_req = dev->esc_parms_curr = 0;
dev->top_margin = dev->left_margin = 0.0;
dev->right_margin = dev->page_width = PAGE_WIDTH;
dev->bottom_margin = dev->page_height = PAGE_HEIGHT;
dev->lpi = PAGE_LPI;
dev->linespacing = 1.0 / dev->lpi;
dev->cpi = PAGE_CPI;
dev->curr_char_table = 1;
dev->font_style = 0;
dev->print_quality = QUALITY_DRAFT;
dev->extra_intra_space = 0.0;
dev->print_upper_control = 1;
dev->bg_remaining_bytes = 0;
dev->density_k = 0;
dev->density_l = 1;
dev->density_y = 2;
dev->density_z = 3;
dev->char_tables[0] = 0; /* italics */
dev->char_tables[1] = dev->char_tables[2] = dev->char_tables[3] = 437; /* all other tables use CP437 */
dev->defined_unit = -1.0;
dev->multipoint_mode = 0;
dev->multipoint_size = 0.0;
dev->multipoint_cpi = 0.0;
dev->hmi = -1;
dev->msb = 255;
dev->print_everything_count = 0;
dev->lq_typeface = TYPEFACE_COURIER;
init_codepage(dev, dev->char_tables[dev->curr_char_table]);
update_font(dev);
new_page(dev, 0, 1);
for (uint8_t i = 0; i < 32; i++)
dev->horizontal_tabs[i] = i * 8.0 * (1.0 / dev->cpi);
dev->num_horizontal_tabs = 32;
dev->num_vertical_tabs = -1;
if (dev->page != NULL)
dev->page->dirty = 0;
escp_log("ESC/P: width=%.1fin,height=%.1fin dpi=%i cpi=%i lpi=%i\n",
dev->page_width, dev->page_height, (int) dev->dpi,
(int) dev->cpi, (int) dev->lpi);
}
static void
reset_printer_hard(escp_t *dev)
{
dev->ack = 0;
timer_disable(&dev->pulse_timer);
timer_disable(&dev->timeout_timer);
reset_printer(dev);
}
/* Select a ASCII->Unicode mapping by CP number */
static void
init_codepage(escp_t *dev, uint16_t num)
{
/* Get the codepage map for this number. */
select_codepage(num, dev->curr_cpmap);
}
static void
update_font(escp_t *dev)
{
char path[1024];
const char *fn;
FT_Matrix matrix;
double hpoints = 10.5;
double vpoints = 10.5;
/* We need the FreeType library. */
if (ft_lib == NULL)
return;
/* Release current font if we have one. */
if (dev->fontface)
FT_Done_Face(dev->fontface);
if (dev->print_quality == QUALITY_DRAFT) {
if (dev->font_style & STYLE_ITALICS)
fn = FONT_FILE_DOTMATRIX_ITALIC;
else
fn = FONT_FILE_DOTMATRIX;
} else
switch (dev->lq_typeface) {
case TYPEFACE_ROMAN:
fn = FONT_FILE_ROMAN;
break;
case TYPEFACE_SANSSERIF:
fn = FONT_FILE_SANSSERIF;
break;
case TYPEFACE_COURIER:
fn = FONT_FILE_COURIER;
break;
case TYPEFACE_SCRIPT:
fn = FONT_FILE_SCRIPT;
break;
case TYPEFACE_OCRA:
fn = FONT_FILE_OCRA;
break;
case TYPEFACE_OCRB:
fn = FONT_FILE_OCRB;
break;
default:
fn = FONT_FILE_ROMAN;
}
/* Create a full pathname for the ROM file. */
strcpy(path, dev->fontpath);
path_slash(path);
strcat(path, fn);
escp_log("Temp file=%s\n", path);
/* Load the new font. */
if (FT_New_Face(ft_lib, path, 0, &dev->fontface)) {
escp_log("ESC/P: unable to load font '%s'\n", path);
dev->fontface = NULL;
}
if (!dev->multipoint_mode) {
dev->actual_cpi = dev->cpi;
if (!(dev->font_style & STYLE_CONDENSED)) {
hpoints *= 10.0 / dev->cpi;
vpoints *= 10.0 / dev->cpi;
}
if (!(dev->font_style & STYLE_PROP)) {
if ((dev->cpi == 10.0) && (dev->font_style & STYLE_CONDENSED)) {
dev->actual_cpi = 17.14;
hpoints *= 10.0 / 17.14;
}
if ((dev->cpi == 12) && (dev->font_style & STYLE_CONDENSED)) {
dev->actual_cpi = 20.0;
hpoints *= 10.0 / 20.0;
vpoints *= 10.0 / 12.0;
}
} else if (dev->font_style & STYLE_CONDENSED)
hpoints /= 2.0;
if ((dev->font_style & STYLE_DOUBLEWIDTH) || (dev->font_style & STYLE_DOUBLEWIDTHONELINE)) {
dev->actual_cpi /= 2.0;
hpoints *= 2.0;
}
if (dev->font_style & STYLE_DOUBLEHEIGHT)
vpoints *= 2.0;
} else {
/* Multipoint mode. */
dev->actual_cpi = dev->multipoint_cpi;
hpoints = vpoints = dev->multipoint_size;
}
if ((dev->font_style & STYLE_SUPERSCRIPT) || (dev->font_style & STYLE_SUBSCRIPT)) {
hpoints *= 2.0 / 3.0;
vpoints *= 2.0 / 3.0;
dev->actual_cpi /= 2.0 / 3.0;
}
FT_Set_Char_Size(dev->fontface,
(uint16_t) (hpoints * 64), (uint16_t) (vpoints * 64),
dev->dpi, dev->dpi);
if ((dev->print_quality != QUALITY_DRAFT) && ((dev->font_style & STYLE_ITALICS) || (dev->char_tables[dev->curr_char_table] == 0))) {
/* Italics transformation. */
matrix.xx = 0x10000L;
matrix.xy = (FT_Fixed) (0.20 * 0x10000L);
matrix.yx = 0;
matrix.yy = 0x10000L;
FT_Set_Transform(dev->fontface, &matrix, 0);
}
}
/* This is the actual ESC/P interpreter. */
static int
process_char(escp_t *dev, uint8_t ch)
{
double new_x;
double new_y;
double move_to;
double unit_size;
double reverse;
double new_top;
double new_bottom;
uint16_t rel_move;
int16_t i;
escp_log("Esc_seen=%d, fss_seen=%d\n", dev->esc_seen, dev->fss_seen);
/* Determine number of additional command params that are expected. */
if (dev->esc_seen || dev->fss_seen) {
dev->esc_pending = ch;
if (dev->fss_seen)
dev->esc_pending |= 0x800;
dev->esc_seen = dev->fss_seen = 0;
dev->esc_parms_curr = 0;
escp_log("Command pending=%02x, font path=%s\n", dev->esc_pending, dev->fontpath);
switch (dev->esc_pending) {
case 0x02: // Undocumented
case 0x0a: // Reverse line feed
case 0x0c: // Return to top of current page
case 0x0e: // Select double-width printing (one line) (ESC SO)
case 0x0f: // Select condensed printing (ESC SI)
case 0x23: // Cancel MSB control (ESC #)
case 0x30: // Select 1/8-inch line spacing (ESC 0)
case 0x31: // Select 7/60-inch line spacing
case 0x32: // Select 1/6-inch line spacing (ESC 2)
case 0x34: // Select italic font (ESC 4)
case 0x35: // Cancel italic font (ESC 5)
case 0x36: // Enable printing of upper control codes (ESC 6)
case 0x37: // Enable upper control codes (ESC 7)
case 0x38: // Disable paper-out detector
case 0x39: // Enable paper-out detector
case 0x3c: // Unidirectional mode (one line) (ESC <)
case 0x3d: // Set MSB to 0 (ESC =)
case 0x3e: // Set MSB to 1 (ESC >)
case 0x40: // Initialize printer (ESC @)
case 0x45: // Select bold font (ESC E)
case 0x46: // Cancel bold font (ESC F)
case 0x47: // Select double-strike printing (ESC G)
case 0x48: // Cancel double-strike printing (ESC H)
case 0x4d: // Select 10.5-point, 12-cpi (ESC M)
case 0x4f: // Cancel bottom margin
case 0x50: // Select 10.5-point, 10-cpi (ESC P)
case 0x54: // Cancel superscript/subscript printing (ESC T)
case 0x5e: // Enable printing of all character codes on next character
case 0x67: // Select 10.5-point, 15-cpi (ESC g)
case 0x834: // Select italic font (FS 4) (= ESC 4)
case 0x835: // Cancel italic font (FS 5) (= ESC 5)
case 0x846: // Select forward feed mode (FS F)
case 0x852: // Select reverse feed mode (FS R)
dev->esc_parms_req = 0;
break;
case 0x19: // Control paper loading/ejecting (ESC EM)
case 0x20: // Set intercharacter space (ESC SP)
case 0x21: // Master select (ESC !)
case 0x2b: // Set n/360-inch line spacing (ESC +)
case 0x2d: // Turn underline on/off (ESC -)
case 0x2f: // Select vertical tab channel (ESC /)
case 0x33: // Set n/180-inch line spacing (ESC 3)
case 0x41: // Set n/60-inch line spacing
case 0x43: // Set page length in lines (ESC C)
case 0x49: // Select character type and print pitch
case 0x4a: // Advance print position vertically (ESC J n)
case 0x4e: // Set bottom margin (ESC N)
case 0x51: // Set right margin (ESC Q)
case 0x52: // Select an international character set (ESC R)
case 0x53: // Select superscript/subscript printing (ESC S)
case 0x55: // Turn unidirectional mode on/off (ESC U)
case 0x57: // Turn double-width printing on/off (ESC W)
case 0x61: // Select justification (ESC a)
case 0x66: // Absolute horizontal tab in columns [conflict]
case 0x68: // Select double or quadruple size
case 0x69: // Immediate print
case 0x6a: // Reverse paper feed
case 0x6b: // Select typeface (ESC k)
case 0x6c: // Set left margin (ESC 1)
case 0x70: // Turn proportional mode on/off (ESC p)
case 0x72: // Select printing color (ESC r)
case 0x73: // Select low-speed mode (ESC s)
case 0x74: // Select character table (ESC t)
case 0x77: // Turn double-height printing on/off (ESC w)
case 0x78: // Select LQ or draft (ESC x)
case 0x7e: // Select/Deselect slash zero (ESC ~)
case 0x832: // Select 1/6-inch line spacing (FS 2) (= ESC 2)
case 0x833: // Set n/360-inch line spacing (FS 3) (= ESC +)
case 0x841: // Set n/60-inch line spacing (FS A) (= ESC A)
case 0x843: // Select LQ type style (FS C) (= ESC k)
case 0x845: // Select character width (FS E)
case 0x849: // Select character table (FS I) (= ESC t)
case 0x853: // Select High Speed/High Density elite pitch (FS S)
case 0x856: // Turn double-height printing on/off (FS V) (= ESC w)
dev->esc_parms_req = 1;
break;
case 0x24: // Set absolute horizontal print position (ESC $)
case 0x3f: // Reassign bit-image mode (ESC ?)
case 0x4b: // Select 60-dpi graphics (ESC K)
case 0x4c: // Select 120-dpi graphics (ESC L)
case 0x59: // Select 120-dpi, double-speed graphics (ESC Y)
case 0x5a: // Select 240-dpi graphics (ESC Z)
case 0x5c: // Set relative horizontal print position (ESC \)
case 0x63: // Set horizontal motion index (HMI) (ESC c)
case 0x65: // Set vertical tab stops every n lines (ESC e)
case 0x85a: // Print 24-bit hex-density graphics (FS Z)
dev->esc_parms_req = 2;
break;
case 0x2a: // Select bit image (ESC *)
case 0x58: // Select font by pitch and point (ESC X)
dev->esc_parms_req = 3;
break;
case 0x5b: // Select character height, width, line spacing
dev->esc_parms_req = 7;
break;
case 0x62: // Set vertical tabs in VFU channels (ESC b)
case 0x42: // Set vertical tabs (ESC B)
dev->num_vertical_tabs = 0;
return 1;
case 0x44: // Set horizontal tabs (ESC D)
dev->num_horizontal_tabs = 0;
return 1;
case 0x25: // Select user-defined set (ESC %)
case 0x26: // Define user-defined characters (ESC &)
case 0x3a: // Copy ROM to RAM (ESC :)
escp_log("ESC/P: User-defined characters not supported (0x%02x).\n", dev->esc_pending);
return 1;
case 0x28: // Two bytes sequence
/* return and wait for second ESC byte */
return 1;
case 0x2e:
fatal("ESC/P: Print Raster Graphics (2E) command is not implemented.\nTerminating the emulator to avoid endless PNG generation.\n");
exit(-1);
default:
escp_log("ESC/P: Unknown command ESC %c (0x%02x). Unable to skip parameters.\n",
dev->esc_pending >= 0x20 ? dev->esc_pending : '?', dev->esc_pending);
dev->esc_parms_req = 0;
dev->esc_pending = 0;
return 1;
}
if (dev->esc_parms_req > 0) {
/* return and wait for parameters to appear */
return 1;
}
}
/* parameter checking for the 2-byte ESC/P2 commands */
if (dev->esc_pending == '(') {
dev->esc_pending = 0x0200 + ch;
escp_log("Two-byte command pending=%03x, font path=%s\n", dev->esc_pending, dev->fontpath);
switch (dev->esc_pending) {
case 0x0242: // Bar code setup and print (ESC (B)
case 0x025e: // Print data as characters (ESC (^)
dev->esc_parms_req = 2;
break;
case 0x0255: // Set unit (ESC (U)
dev->esc_parms_req = 3;
break;
case 0x0243: // Set page length in defined unit (ESC (C)
case 0x0256: // Set absolute vertical print position (ESC (V)
case 0x0276: // Set relative vertical print position (ESC (v)
dev->esc_parms_req = 4;
break;
case 0x0228: // Assign character table (ESC (t)
case 0x022d: // Select line/score (ESC (-)
dev->esc_parms_req = 5;
break;
case 0x0263: // Set page format (ESC (c)
dev->esc_parms_req = 6;
break;
default:
/* ESC ( commands are always followed by a "number of parameters" word parameter */
dev->esc_parms_req = 2;
dev->esc_pending = 0x101; /* dummy value to be checked later */
return 1;
}
/* If we need parameters, return and wait for them to appear. */
if (dev->esc_parms_req > 0)
return 1;
}
/* Ignore VFU channel setting. */
if (dev->esc_pending == 0x62) {
dev->esc_pending = 0x42;
return 1;
}
/* Collect vertical tabs. */
if (dev->esc_pending == 0x42) {
/* check if we're done */
if ((ch == 0) || (dev->num_vertical_tabs > 0 && dev->vertical_tabs[dev->num_vertical_tabs - 1] > (double) ch * dev->linespacing)) {
dev->esc_pending = 0;
} else {
if (dev->num_vertical_tabs >= 0 && dev->num_vertical_tabs < 16)
dev->vertical_tabs[dev->num_vertical_tabs++] = (double) ch * dev->linespacing;
}
}
/* Collect horizontal tabs. */
if (dev->esc_pending == 0x44) {
/* check if we're done... */
if ((ch == 0) || (dev->num_horizontal_tabs > 0 && dev->horizontal_tabs[dev->num_horizontal_tabs - 1] > (double) ch * (1.0 / dev->cpi))) {
dev->esc_pending = 0;
} else {
if (dev->num_horizontal_tabs < 32)
dev->horizontal_tabs[dev->num_horizontal_tabs++] = (double) ch * (1.0 / dev->cpi);
}
}
/* Check if we're still collecting parameters for the current command. */
if (dev->esc_parms_curr < dev->esc_parms_req) {
/* store current parameter */
dev->esc_parms[dev->esc_parms_curr++] = ch;
/* do we still need to continue collecting parameters? */
if (dev->esc_parms_curr < dev->esc_parms_req)
return 1;
}
/* Handle the pending ESC command. */
if (dev->esc_pending != 0) {
switch (dev->esc_pending) {
case 0x02: /* undocumented; ignore */
break;
case 0x0e: /* select double-width (one line) (ESC SO) */
if (!dev->multipoint_mode) {
dev->hmi = -1;
dev->font_style |= STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
}
break;
case 0x0f: /* select condensed printing (ESC SI) */
if (!dev->multipoint_mode && (dev->cpi != 15.0)) {
dev->hmi = -1;
dev->font_style |= STYLE_CONDENSED;
update_font(dev);
}
break;
case 0x19: /* control paper loading/ejecting (ESC EM) */
/* We are not really loading paper, so most
* commands can be ignored */
if (dev->esc_parms[0] == 'R')
new_page(dev, 1, 0);
break;
case 0x20: /* set intercharacter space (ESC SP) */
if (!dev->multipoint_mode) {
dev->extra_intra_space = (double) dev->esc_parms[0] / (dev->print_quality == QUALITY_DRAFT ? 120.0 : 180.0);
dev->hmi = -1;
update_font(dev);
}
break;
case 0x21: /* master select (ESC !) */
dev->cpi = dev->esc_parms[0] & 0x01 ? 12.0 : 10.0;
/* Reset first seven bits. */
dev->font_style &= 0xFF80;
if (dev->esc_parms[0] & 0x02)
dev->font_style |= STYLE_PROP;
if (dev->esc_parms[0] & 0x04)
dev->font_style |= STYLE_CONDENSED;
if (dev->esc_parms[0] & 0x08)
dev->font_style |= STYLE_BOLD;
if (dev->esc_parms[0] & 0x10)
dev->font_style |= STYLE_DOUBLESTRIKE;
if (dev->esc_parms[0] & 0x20)
dev->font_style |= STYLE_DOUBLEWIDTH;
if (dev->esc_parms[0] & 0x40)
dev->font_style |= STYLE_ITALICS;
if (dev->esc_parms[0] & 0x80) {
dev->font_score = SCORE_SINGLE;
dev->font_style |= STYLE_UNDERLINE;
}
dev->hmi = -1;
dev->multipoint_mode = 0;
update_font(dev);
break;
case 0x23: /* cancel MSB control (ESC #) */
dev->msb = 255;
break;
case 0x24: /* set abs horizontal print position (ESC $) */
unit_size = dev->defined_unit;
if (unit_size < 0)
unit_size = 60.0;
new_x = dev->left_margin + ((double) PARAM16(0) / unit_size);
if (new_x <= dev->right_margin)
dev->curr_x = new_x;
break;
case 0x85a: /* Print 24-bit hex-density graphics (FS Z) */
setup_bit_image(dev, 40, PARAM16(0));
break;
case 0x2a: /* select bit image (ESC *) */
setup_bit_image(dev, dev->esc_parms[0], PARAM16(1));
break;
case 0x2b: /* set n/360-inch line spacing (ESC +) */
case 0x833: /* Set n/360-inch line spacing (FS 3) */
dev->linespacing = (double) dev->esc_parms[0] / 360.0;
break;
case 0x2d: /* turn underline on/off (ESC -) */
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0')
dev->font_style &= ~STYLE_UNDERLINE;
if (dev->esc_parms[0] == 1 || dev->esc_parms[0] == '1') {
dev->font_style |= STYLE_UNDERLINE;
dev->font_score = SCORE_SINGLE;
}
update_font(dev);
break;
case 0x2f: /* select vertical tab channel (ESC /) */
/* Ignore */
break;
case 0x30: /* select 1/8-inch line spacing (ESC 0) */
dev->linespacing = 1.0 / 8.0;
break;
case 0x31: /* select 7/60-inch line spacing */
dev->linespacing = 7.0 / 60.0;
break;
case 0x32: /* select 1/6-inch line spacing (ESC 2) */
dev->linespacing = 1.0 / 6.0;
break;
case 0x33: /* set n/180-inch line spacing (ESC 3) */
dev->linespacing = (double) dev->esc_parms[0] / 180.0;
break;
case 0x34: /* select italic font (ESC 4) */
dev->font_style |= STYLE_ITALICS;
update_font(dev);
break;
case 0x35: /* cancel italic font (ESC 5) */
dev->font_style &= ~STYLE_ITALICS;
update_font(dev);
break;
case 0x36: /* enable printing of upper control codes (ESC 6) */
dev->print_upper_control = 1;
break;
case 0x37: /* enable upper control codes (ESC 7) */
dev->print_upper_control = 0;
break;
case 0x3c: /* unidirectional mode (one line) (ESC <) */
/* We don't have a print head, so just
* ignore this. */
break;
case 0x3d: /* set MSB to 0 (ESC =) */
dev->msb = 0;
break;
case 0x3e: /* set MSB to 1 (ESC >) */
dev->msb = 1;
break;
case 0x3f: /* reassign bit-image mode (ESC ?) */
if (dev->esc_parms[0] == 'K')
dev->density_k = dev->esc_parms[1];
if (dev->esc_parms[0] == 'L')
dev->density_l = dev->esc_parms[1];
if (dev->esc_parms[0] == 'Y')
dev->density_y = dev->esc_parms[1];
if (dev->esc_parms[0] == 'Z')
dev->density_z = dev->esc_parms[1];
break;
case 0x40: /* initialize printer (ESC @) */
reset_printer(dev);
break;
case 0x41: /* set n/60-inch line spacing */
case 0x841:
dev->linespacing = (double) dev->esc_parms[0] / 60.0;
break;
case 0x43: /* set page length in lines (ESC C) */
if (dev->esc_parms[0] != 0) {
dev->page_height = dev->bottom_margin = (double) dev->esc_parms[0] * dev->linespacing;
} else { /* == 0 => Set page length in inches */
dev->esc_parms_req = 1;
dev->esc_parms_curr = 0;
dev->esc_pending = 0x100; /* dummy value for later */
return 1;
}
break;
case 0x45: /* select bold font (ESC E) */
dev->font_style |= STYLE_BOLD;
update_font(dev);
break;
case 0x46: /* cancel bold font (ESC F) */
dev->font_style &= ~STYLE_BOLD;
update_font(dev);
break;
case 0x47: /* select dobule-strike printing (ESC G) */
dev->font_style |= STYLE_DOUBLESTRIKE;
break;
case 0x48: /* cancel double-strike printing (ESC H) */
dev->font_style &= ~STYLE_DOUBLESTRIKE;
break;
case 0x4a: /* advance print pos vertically (ESC J n) */
dev->curr_y += (double) ((double) dev->esc_parms[0] / 180.0);
if (dev->curr_y > dev->bottom_margin)
new_page(dev, 1, 0);
break;
case 0x4b: /* select 60-dpi graphics (ESC K) */
/* TODO: graphics stuff */
setup_bit_image(dev, dev->density_k, PARAM16(0));
break;
case 0x4c: /* select 120-dpi graphics (ESC L) */
/* TODO: graphics stuff */
setup_bit_image(dev, dev->density_l, PARAM16(0));
break;
case 0x4d: /* select 10.5-point, 12-cpi (ESC M) */
dev->cpi = 12.0;
dev->hmi = -1;
dev->multipoint_mode = 0;
update_font(dev);
break;
case 0x4e: /* set bottom margin (ESC N) */
dev->top_margin = 0.0;
dev->bottom_margin = (double) dev->esc_parms[0] * dev->linespacing;
break;
case 0x4f: /* cancel bottom (and top) margin */
dev->top_margin = 0.0;
dev->bottom_margin = dev->page_height;
break;
case 0x50: /* select 10.5-point, 10-cpi (ESC P) */
dev->cpi = 10.0;
dev->hmi = -1;
dev->multipoint_mode = 0;
update_font(dev);
break;
case 0x51: /* set right margin */
dev->right_margin = ((double) dev->esc_parms[0] - 1.0) / dev->cpi;
break;
case 0x52: /* select an intl character set (ESC R) */
if (dev->esc_parms[0] <= 13 || dev->esc_parms[0] == '@') {
if (dev->esc_parms[0] == '@')
dev->esc_parms[0] = 14;
dev->curr_cpmap[0x23] = intCharSets[dev->esc_parms[0]][0];
dev->curr_cpmap[0x24] = intCharSets[dev->esc_parms[0]][1];
dev->curr_cpmap[0x40] = intCharSets[dev->esc_parms[0]][2];
dev->curr_cpmap[0x5b] = intCharSets[dev->esc_parms[0]][3];
dev->curr_cpmap[0x5c] = intCharSets[dev->esc_parms[0]][4];
dev->curr_cpmap[0x5d] = intCharSets[dev->esc_parms[0]][5];
dev->curr_cpmap[0x5e] = intCharSets[dev->esc_parms[0]][6];
dev->curr_cpmap[0x60] = intCharSets[dev->esc_parms[0]][7];
dev->curr_cpmap[0x7b] = intCharSets[dev->esc_parms[0]][8];
dev->curr_cpmap[0x7c] = intCharSets[dev->esc_parms[0]][9];
dev->curr_cpmap[0x7d] = intCharSets[dev->esc_parms[0]][10];
dev->curr_cpmap[0x7e] = intCharSets[dev->esc_parms[0]][11];
}
break;
case 0x53: /* select superscript/subscript printing (ESC S) */
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0')
dev->font_style |= STYLE_SUBSCRIPT;
if (dev->esc_parms[0] == 1 || dev->esc_parms[1] == '1')
dev->font_style |= STYLE_SUPERSCRIPT;
update_font(dev);
break;
case 0x54: /* cancel superscript/subscript printing (ESC T) */
dev->font_style &= 0xFFFF - STYLE_SUPERSCRIPT - STYLE_SUBSCRIPT;
update_font(dev);
break;
case 0x55: /* turn unidirectional mode on/off (ESC U) */
/* We don't have a print head, so just ignore this. */
break;
case 0x57: /* turn double-width printing on/off (ESC W) */
if (!dev->multipoint_mode) {
dev->hmi = -1;
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0')
dev->font_style &= ~STYLE_DOUBLEWIDTH;
if (dev->esc_parms[0] == 1 || dev->esc_parms[0] == '1')
dev->font_style |= STYLE_DOUBLEWIDTH;
update_font(dev);
}
break;
case 0x58: /* select font by pitch and point (ESC X) */
dev->multipoint_mode = 1;
/* Copy currently non-multipoint CPI if no value was set so far. */
if (dev->multipoint_cpi == 0.0) {
dev->multipoint_cpi = dev->cpi;
}
if (dev->esc_parms[0] > 0) { /* set CPI */
if (dev->esc_parms[0] == 1) {
/* Proportional spacing. */
dev->font_style |= STYLE_PROP;
} else if (dev->esc_parms[0] >= 5)
dev->multipoint_cpi = 360.0 / (double) dev->esc_parms[0];
}
if (dev->multipoint_size == 0.0)
dev->multipoint_size = 10.5;
if (PARAM16(1) > 0) {
/* set points */
dev->multipoint_size = ((double) PARAM16(1)) / 2.0;
}
update_font(dev);
break;
case 0x59: /* select 120-dpi, double-speed graphics (ESC Y) */
/* TODO: graphics stuff */
setup_bit_image(dev, dev->density_y, PARAM16(0));
break;
case 0x5a: /* select 240-dpi graphics (ESC Z) */
/* TODO: graphics stuff */
setup_bit_image(dev, dev->density_z, PARAM16(0));
break;
case 0x5c: /* set relative horizontal print pos (ESC \) */
rel_move = PARAM16(0);
unit_size = dev->defined_unit;
if (unit_size < 0)
unit_size = (dev->print_quality == QUALITY_DRAFT ? 120.0 : 180.0);
dev->curr_x += ((double) rel_move / unit_size);
break;
case 0x61: /* select justification (ESC a) */
/* Ignore. */
break;
case 0x63: /* set horizontal motion index (HMI) (ESC c) */
dev->hmi = (double) PARAM16(0) / 360.0;
dev->extra_intra_space = 0.0;
break;
case 0x67: /* select 10.5-point, 15-cpi (ESC g) */
dev->cpi = 15;
dev->hmi = -1;
dev->multipoint_mode = 0;
update_font(dev);
break;
case 0x846: // Select forward feed mode (FS F) - set reverse not implemented yet
if (dev->linespacing < 0)
dev->linespacing *= -1;
break;
case 0x6a: // Reverse paper feed (ESC j)
reverse = (double) PARAM16(0) / (double) 216.0;
reverse = dev->curr_y - reverse;
if (reverse < dev->left_margin)
dev->curr_y = dev->left_margin;
else
dev->curr_y = reverse;
break;
case 0x6b: /* select typeface (ESC k) */
if (dev->esc_parms[0] <= 11 || dev->esc_parms[0] == 30 || dev->esc_parms[0] == 31) {
dev->lq_typeface = dev->esc_parms[0];
}
update_font(dev);
break;
case 0x6c: /* set left margin (ESC 1) */
dev->left_margin = ((double) dev->esc_parms[0] - 1.0) / dev->cpi;
if (dev->curr_x < dev->left_margin)
dev->curr_x = dev->left_margin;
break;
case 0x70: /* Turn proportional mode on/off (ESC p) */
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0')
dev->font_style &= ~STYLE_PROP;
if (dev->esc_parms[0] == 1 || dev->esc_parms[0] == '1') {
dev->font_style |= STYLE_PROP;
dev->print_quality = QUALITY_LQ;
}
dev->multipoint_mode = 0;
dev->hmi = -1;
update_font(dev);
break;
case 0x72: /* select printing color (ESC r) */
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] > 6)
dev->color = COLOR_BLACK;
else
dev->color = dev->esc_parms[0] << 5;
break;
case 0x73: /* select low-speed mode (ESC s) */
/* Ignore. */
break;
case 0x74: /* select character table (ESC t) */
case 0x849: /* Select character table (FS I) */
if (dev->esc_parms[0] < 4) {
dev->curr_char_table = dev->esc_parms[0];
} else if ((dev->esc_parms[0] >= '0') && (dev->esc_parms[0] <= '3')) {
dev->curr_char_table = dev->esc_parms[0] - '0';
}
init_codepage(dev, dev->char_tables[dev->curr_char_table]);
update_font(dev);
break;
case 0x77: /* turn double-height printing on/off (ESC w) */
if (!dev->multipoint_mode) {
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0')
dev->font_style &= ~STYLE_DOUBLEHEIGHT;
if (dev->esc_parms[0] == 1 || dev->esc_parms[0] == '1')
dev->font_style |= STYLE_DOUBLEHEIGHT;
update_font(dev);
}
break;
case 0x78: /* select LQ or draft (ESC x) */
if (dev->esc_parms[0] == 0 || dev->esc_parms[0] == '0') {
dev->print_quality = QUALITY_DRAFT;
dev->font_style |= STYLE_CONDENSED;
}
if (dev->esc_parms[0] == 1 || dev->esc_parms[0] == '1') {
dev->print_quality = QUALITY_LQ;
dev->font_style &= ~STYLE_CONDENSED;
}
dev->hmi = -1;
update_font(dev);
break;
/* Our special command markers. */
case 0x0100: /* set page length in inches (ESC C NUL) */
dev->page_height = (double) dev->esc_parms[0];
dev->bottom_margin = dev->page_height;
dev->top_margin = 0.0;
break;
case 0x0101: /* skip unsupported ESC ( command */
dev->esc_parms_req = PARAM16(0);
dev->esc_parms_curr = 0;
break;
/* Extended ESC ( <x> commands */
case 0x0228: /* assign character table (ESC (t) */
case 0x0274:
if (dev->esc_parms[2] < 4 && dev->esc_parms[3] < 16) {
dev->char_tables[dev->esc_parms[2]] = codepages[dev->esc_parms[3]];
if (dev->esc_parms[2] == dev->curr_char_table)
init_codepage(dev, dev->char_tables[dev->curr_char_table]);
}
break;
case 0x022d: /* select line/score (ESC (-) */
dev->font_style &= ~(STYLE_UNDERLINE | STYLE_STRIKETHROUGH | STYLE_OVERSCORE);
dev->font_score = dev->esc_parms[4];
if (dev->font_score) {
if (dev->esc_parms[3] == 1)
dev->font_style |= STYLE_UNDERLINE;
if (dev->esc_parms[3] == 2)
dev->font_style |= STYLE_STRIKETHROUGH;
if (dev->esc_parms[3] == 3)
dev->font_style |= STYLE_OVERSCORE;
}
update_font(dev);
break;
case 0x0242: /* bar code setup and print (ESC (B) */
// ERRLOG("ESC/P: Barcode printing not supported.\n");
/* Find out how many bytes to skip. */
dev->esc_parms_req = PARAM16(0);
dev->esc_parms_curr = 0;
break;
case 0x0243: /* set page length in defined unit (ESC (C) */
if (dev->esc_parms[0] && (dev->defined_unit > 0)) {
dev->page_height = dev->bottom_margin = (double) PARAM16(2) * dev->defined_unit;
dev->top_margin = 0.0;
}
break;
case 0x0255: /* set unit (ESC (U) */
dev->defined_unit = 3600.0 / (double) dev->esc_parms[2];
break;
case 0x0256: /* set abse vertical print pos (ESC (V) */
unit_size = dev->defined_unit;
if (unit_size < 0)
unit_size = 360.0;
new_y = dev->top_margin + (double) PARAM16(2) * unit_size;
if (new_y > dev->bottom_margin)
new_page(dev, 1, 0);
else
dev->curr_y = new_y;
break;
case 0x025e: /* print data as characters (ESC (^) */
dev->print_everything_count = PARAM16(0);
break;
case 0x0263: /* set page format (ESC (c) */
if (dev->defined_unit > 0.0) {
new_top = (double) PARAM16(2) * dev->defined_unit;
new_bottom = (double) PARAM16(4) * dev->defined_unit;
if (new_top >= new_bottom)
break;
if (new_top < dev->page_height)
dev->top_margin = new_top;
if (new_bottom < dev->page_height)
dev->bottom_margin = new_bottom;
if (dev->top_margin > dev->curr_y)
dev->curr_y = dev->top_margin;
}
break;
case 0x0276: /* set relative vertical print pos (ESC (v) */
{
unit_size = dev->defined_unit;
if (unit_size < 0.0)
unit_size = 360.0;
new_y = dev->curr_y + (double) ((int16_t) PARAM16(2)) * unit_size;
if (new_y > dev->top_margin) {
if (new_y > dev->bottom_margin)
new_page(dev, 1, 0);
else
dev->curr_y = new_y;
}
}
break;
default:
break;
}
dev->esc_pending = 0;
return 1;
}
escp_log("CH=%02x\n", ch);
/* Now handle the "regular" control characters. */
switch (ch) {
case 0x00:
return 1;
case 0x07: /* Beeper (BEL) */
/* TODO: beep? */
return 1;
case 0x08: /* Backspace (BS) */
new_x = dev->curr_x - (1.0 / dev->actual_cpi);
if (dev->hmi > 0)
new_x = dev->curr_x - dev->hmi;
if (new_x >= dev->left_margin)
dev->curr_x = new_x;
return 1;
case 0x09: /* Tab horizontally (HT) */
/* Find tab right to current pos. */
move_to = -1.0;
for (i = 0; i < dev->num_horizontal_tabs; i++) {
if (dev->horizontal_tabs[i] > dev->curr_x)
move_to = dev->horizontal_tabs[i];
}
/* Nothing found or out of page bounds => Ignore. */
if (move_to > 0.0 && move_to < dev->right_margin)
dev->curr_x = move_to;
return 1;
case 0x0b: /* Tab vertically (VT) */
if (dev->num_vertical_tabs == 0) {
/* All tabs cleared? => Act like CR */
dev->curr_x = dev->left_margin;
} else if (dev->num_vertical_tabs < 0) {
/* No tabs set since reset => Act like LF */
dev->curr_x = dev->left_margin;
dev->curr_y += dev->linespacing;
if (dev->curr_y > dev->bottom_margin)
new_page(dev, 1, 0);
} else {
/* Find tab below current pos. */
move_to = -1;
for (i = 0; i < dev->num_vertical_tabs; i++) {
if (dev->vertical_tabs[i] > dev->curr_y)
move_to = dev->vertical_tabs[i];
}
/* Nothing found => Act like FF. */
if (move_to > dev->bottom_margin || move_to < 0)
new_page(dev, 1, 0);
else
dev->curr_y = move_to;
}
if (dev->font_style & STYLE_DOUBLEWIDTHONELINE) {
dev->font_style &= 0xFFFF - STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
}
return 1;
case 0x0c: /* Form feed (FF) */
if (dev->font_style & STYLE_DOUBLEWIDTHONELINE) {
dev->font_style &= ~STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
}
new_page(dev, 1, 1);
return 1;
case 0x0d: /* Carriage Return (CR) */
dev->curr_x = dev->left_margin;
if (!dev->autofeed)
return 1;
fallthrough;
case 0x0a: /* Line feed */
if (dev->font_style & STYLE_DOUBLEWIDTHONELINE) {
dev->font_style &= ~STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
}
dev->curr_x = dev->left_margin;
dev->curr_y += dev->linespacing;
if ((dev->curr_y + 0.0001f) > dev->bottom_margin)
new_page(dev, 1, 0);
return 1;
case 0x0e: /* select Real64-width printing (one line) (SO) */
if (!dev->multipoint_mode) {
dev->hmi = -1;
dev->font_style |= STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
}
return 1;
case 0x0f: /* select condensed printing (SI) */
if (!dev->multipoint_mode) {
dev->hmi = -1;
dev->font_style |= STYLE_CONDENSED;
update_font(dev);
}
return 1;
case 0x11: /* select printer (DC1) */
/* Ignore. */
return 0;
case 0x12: /* cancel condensed printing (DC2) */
dev->hmi = -1;
dev->font_style &= ~STYLE_CONDENSED;
update_font(dev);
return 1;
case 0x13: /* deselect printer (DC3) */
/* Ignore. */
return 1;
case 0x14: /* cancel double-width printing (one line) (DC4) */
dev->hmi = -1;
dev->font_style &= ~STYLE_DOUBLEWIDTHONELINE;
update_font(dev);
return 1;
case 0x18: /* cancel line (CAN) */
return 1;
case 0x1b: /* ESC */
dev->esc_seen = 1;
return 1;
case 0x1c: /* FS (IBM commands) */
dev->fss_seen = 1;
return 1;
default:
/* This is a printable character -> print it. */
return 0;
}
}
static void
handle_char(escp_t *dev, uint8_t ch)
{
FT_UInt char_index;
uint16_t pen_x;
uint16_t pen_y;
uint16_t line_start;
uint16_t line_y;
double x_advance;
if (dev->page == NULL)
return;
/* MSB mode */
if (dev->msb != 255) {
if (dev->msb == 0)
ch &= 0x7f;
else if (dev->msb == 1)
ch |= 0x80;
}
if (dev->bg_remaining_bytes > 0) {
print_bit_graph(dev, ch);
return;
}
/* "print everything" mode? aka. ESC ( ^ */
if (dev->print_everything_count > 0) {
escp_log("Print everything count=%d\n", dev->print_everything_count);
/* do not process command char, just continue */
dev->print_everything_count--;
} else if (process_char(dev, ch)) {
/* command was processed */
return;
}
/* We cannot print if we have no font loaded. */
if (dev->fontface == NULL)
return;
if (ch == 0x01)
ch = 0x20;
/* ok, so we need to print the character now */
if (ft_lib) {
char_index = FT_Get_Char_Index(dev->fontface, dev->curr_cpmap[ch]);
FT_Load_Glyph(dev->fontface, char_index, FT_LOAD_DEFAULT);
FT_Render_Glyph(dev->fontface->glyph, FT_RENDER_MODE_NORMAL);
}
pen_x = PIXX + fmax(0.0, dev->fontface->glyph->bitmap_left);
pen_y = (uint16_t) (PIXY + fmax(0.0, -dev->fontface->glyph->bitmap_top + dev->fontface->size->metrics.ascender / 64));
if (dev->font_style & STYLE_SUBSCRIPT)
pen_y += dev->fontface->glyph->bitmap.rows / 2;
/* mark the page as dirty if anything is drawn */
if ((ch != 0x20) || (dev->font_score != SCORE_NONE))
dev->page->dirty = 1;
/* draw the glyph */
blit_glyph(dev, pen_x, pen_y, 0);
blit_glyph(dev, pen_x + 1, pen_y, 1);
/* doublestrike -> draw glyph a second time, 1px below */
if (dev->font_style & STYLE_DOUBLESTRIKE) {
blit_glyph(dev, pen_x, pen_y + 1, 1);
blit_glyph(dev, pen_x + 1, pen_y + 1, 1);
}
/* bold -> draw glyph a second time, 1px to the right */
if (dev->font_style & STYLE_BOLD) {
blit_glyph(dev, pen_x + 1, pen_y, 1);
blit_glyph(dev, pen_x + 2, pen_y, 1);
blit_glyph(dev, pen_x + 3, pen_y, 1);
}
line_start = PIXX;
if (dev->font_style & STYLE_PROP)
x_advance = dev->fontface->glyph->advance.x / (dev->dpi * 64.0);
else {
if (dev->hmi < 0)
x_advance = 1.0 / dev->actual_cpi;
else
x_advance = dev->hmi;
}
x_advance += dev->extra_intra_space;
dev->curr_x += x_advance;
/* Line printing (underline etc.) */
if (dev->font_score != SCORE_NONE && (dev->font_style & (STYLE_UNDERLINE | STYLE_STRIKETHROUGH | STYLE_OVERSCORE))) {
/* Find out where to put the line. */
line_y = PIXY;
if (dev->font_style & STYLE_UNDERLINE)
line_y = (PIXY + (uint16_t) (dev->fontface->size->metrics.height * 0.9));
if (dev->font_style & STYLE_STRIKETHROUGH)
line_y = (PIXY + (uint16_t) (dev->fontface->size->metrics.height * 0.45));
if (dev->font_style & STYLE_OVERSCORE)
line_y = PIXY - ((dev->font_score == SCORE_DOUBLE || dev->font_score == SCORE_DOUBLEBROKEN) ? 5 : 0);
draw_hline(dev, pen_x, PIXX, line_y, dev->font_score == SCORE_SINGLEBROKEN || dev->font_score == SCORE_DOUBLEBROKEN);
if (dev->font_score == SCORE_DOUBLE || dev->font_score == SCORE_DOUBLEBROKEN)
draw_hline(dev, line_start, PIXX, line_y + 5, dev->font_score == SCORE_SINGLEBROKEN || dev->font_score == SCORE_DOUBLEBROKEN);
}
if ((dev->curr_x + x_advance) > dev->right_margin) {
dev->curr_x = dev->left_margin;
dev->curr_y += dev->linespacing;
if (dev->curr_y > dev->bottom_margin)
new_page(dev, 1, 0);
}
}
/* TODO: This can be optimized quite a bit... I'm just too lazy right now ;-) */
static void
blit_glyph(escp_t *dev, unsigned destx, unsigned desty, int8_t add)
{
const FT_Bitmap *bitmap = &dev->fontface->glyph->bitmap;
uint8_t src;
uint8_t *dst;
/* check if freetype is available */
if (ft_lib == NULL)
return;
for (unsigned int y = 0; y < bitmap->rows; y++) {
for (unsigned int x = 0; x < bitmap->width; x++) {
src = *(bitmap->buffer + x + y * bitmap->pitch);
/* ignore background, and respect page size */
if (src > 0 && (destx + x < (unsigned) dev->page->w) && (desty + y < (unsigned) dev->page->h)) {
dst = (uint8_t *) dev->page->pixels + (x + destx) + (y + desty) * dev->page->pitch;
src >>= 3;
if (add) {
if (((*dst) & 0x1f) + src > 31)
*dst |= (dev->color | 0x1f);
else {
*dst += src;
*dst |= dev->color;
}
} else
*dst = src | dev->color;
}
}
}
}
/* Draw anti-aliased line. */
static void
draw_hline(escp_t *dev, unsigned from_x, unsigned to_x, unsigned y, int8_t broken)
{
unsigned breakmod = dev->dpi / 15;
unsigned gapstart = (breakmod * 4) / 5;
for (unsigned int x = from_x; x <= to_x; x++) {
/* Skip parts if broken line or going over the border. */
if ((!broken || (x % breakmod <= gapstart)) && (x < dev->page->w)) {
if (y > 0 && (y - 1) < dev->page->h)
*((uint8_t *) dev->page->pixels + x + (y - 1) * (unsigned) dev->page->pitch) = 240;
if (y < dev->page->h)
*((uint8_t *) dev->page->pixels + x + y * (unsigned) dev->page->pitch) = !broken ? 255 : 240;
if (y + 1 < dev->page->h)
*((uint8_t *) dev->page->pixels + x + (y + 1) * (unsigned) dev->page->pitch) = 240;
}
}
}
static void
setup_bit_image(escp_t *dev, uint8_t density, uint16_t num_columns)
{
escp_log("Density=%d\n", density);
switch (density) {
case 0:
dev->bg_h_density = 60;
dev->bg_v_density = 60;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 1;
break;
case 1:
dev->bg_h_density = 120;
dev->bg_v_density = 60;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 1;
break;
case 2:
dev->bg_h_density = 120;
dev->bg_v_density = 60;
dev->bg_adjacent = 0;
dev->bg_bytes_per_column = 1;
break;
case 3:
dev->bg_h_density = 60;
dev->bg_v_density = 240;
dev->bg_adjacent = 0;
dev->bg_bytes_per_column = 1;
break;
case 4:
dev->bg_h_density = 80;
dev->bg_v_density = 60;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 1;
break;
case 6:
dev->bg_h_density = 90;
dev->bg_v_density = 60;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 1;
break;
case 32:
dev->bg_h_density = 60;
dev->bg_v_density = 180;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 3;
break;
case 33:
dev->bg_h_density = 120;
dev->bg_v_density = 180;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 3;
break;
case 38:
dev->bg_h_density = 90;
dev->bg_v_density = 180;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 3;
break;
case 39:
dev->bg_h_density = 180;
dev->bg_v_density = 180;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 3;
break;
case 40:
dev->bg_h_density = 360;
dev->bg_v_density = 180;
dev->bg_adjacent = 0;
dev->bg_bytes_per_column = 3;
break;
case 71:
dev->bg_h_density = 180;
dev->bg_v_density = 360;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 6;
break;
case 72:
dev->bg_h_density = 360;
dev->bg_v_density = 360;
dev->bg_adjacent = 0;
dev->bg_bytes_per_column = 6;
break;
case 73:
dev->bg_h_density = 360;
dev->bg_v_density = 360;
dev->bg_adjacent = 1;
dev->bg_bytes_per_column = 6;
break;
default:
escp_log("ESC/P: Unsupported bit image density %d.\n", density);
break;
}
dev->bg_remaining_bytes = num_columns * dev->bg_bytes_per_column;
dev->bg_bytes_read = 0;
}
static void
print_bit_graph(escp_t *dev, uint8_t ch)
{
uint8_t pixel_w; /* width of the "pixel" */
uint8_t pixel_h; /* height of the "pixel" */
double old_y;
dev->bg_column[dev->bg_bytes_read++] = ch;
dev->bg_remaining_bytes--;
/* Only print after reading a full column. */
if (dev->bg_bytes_read < dev->bg_bytes_per_column)
return;
old_y = dev->curr_y;
pixel_w = 1;
pixel_h = 1;
if (dev->bg_adjacent) {
/* if page DPI is bigger than bitgraphics DPI, drawn pixels get "bigger" */
pixel_w = dev->dpi / dev->bg_h_density > 0 ? dev->dpi / dev->bg_h_density : 1;
pixel_h = dev->dpi / dev->bg_v_density > 0 ? dev->dpi / dev->bg_v_density : 1;
}
for (uint8_t i = 0; i < dev->bg_bytes_per_column; i++) {
/* for each byte */
for (uint8_t j = 128; j != 0; j >>= 1) {
/* for each bit */
if (dev->bg_column[i] & j) {
/* draw a "pixel" */
for (uint8_t xx = 0; xx < pixel_w; xx++) {
for (uint8_t yy = 0; yy < pixel_h; yy++) {
if (((PIXX + xx) < (unsigned) dev->page->w) && ((PIXY + yy) < (unsigned) dev->page->h))
*((uint8_t *) dev->page->pixels + (PIXX + xx) + (PIXY + yy) * dev->page->pitch) |= (dev->color | 0x1f);
}
}
}
dev->curr_y += 1.0 / (double) dev->bg_v_density;
}
}
/* Mark page dirty. */
dev->page->dirty = 1;
/* Restore Y-position. */
dev->curr_y = old_y;
dev->bg_bytes_read = 0;
/* Advance print head. */
dev->curr_x += 1.0 / dev->bg_h_density;
}
static void
write_data(uint8_t val, void *priv)
{
escp_t *dev = (escp_t *) priv;
if (dev == NULL)
return;
dev->data = val;
}
static void
write_ctrl(uint8_t val, void *priv)
{
escp_t *dev = (escp_t *) priv;
if (dev == NULL)
return;
if (val & 0x08) { /* SELECT */
/* select printer */
dev->select = 1;
}
if ((val & 0x04) && !(dev->ctrl & 0x04)) {
/* reset printer */
dev->select = 0;
reset_printer_hard(dev);
}
/* Data is strobed to the parallel printer on the falling edge of the
strobe bit. */
if (!(val & 0x01) && (dev->ctrl & 0x01)) {
/* Process incoming character. */
handle_char(dev, dev->data);
/* ACK it, will be read on next READ STATUS. */
dev->ack = 1;
timer_set_delay_u64(&dev->pulse_timer, ISACONST);
timer_set_delay_u64(&dev->timeout_timer, 5000000 * TIMER_USEC);
}
dev->ctrl = val;
dev->autofeed = ((val & 0x02) > 0);
}
static uint8_t
read_data(void *priv)
{
const escp_t *dev = (escp_t *) priv;
return dev->data;
}
static uint8_t
read_ctrl(void *priv)
{
const escp_t *dev = (escp_t *) priv;
return 0xe0 | (dev->autofeed ? 0x02 : 0x00) | (dev->ctrl & 0xfd);
}
static uint8_t
read_status(void *priv)
{
const escp_t *dev = (escp_t *) priv;
uint8_t ret = 0x1f;
ret |= 0x80;
if (!dev->ack)
ret |= 0x40;
return ret;
}
static void *
escp_init(void *lpt)
{
escp_t *dev;
/* Initialize FreeType. */
if (ft_lib == NULL) {
if (FT_Init_FreeType(&ft_lib)) {
pclog("ESC/P: FT_Init_FreeType failed\n");
ft_lib = NULL;
return (NULL);
}
}
/* Initialize a device instance. */
dev = (escp_t *) malloc(sizeof(escp_t));
memset(dev, 0x00, sizeof(escp_t));
dev->ctrl = 0x04;
dev->lpt = lpt;
/* Create a full pathname for the font files. */
if (strlen(exe_path) >= sizeof(dev->fontpath)) {
free(dev);
return (NULL);
}
strcpy(dev->fontpath, exe_path);
path_slash(dev->fontpath);
strcat(dev->fontpath, "roms/printer/fonts/");
/* Create the full path for the page images. */
path_append_filename(dev->pagepath, usr_path, "printer");
if (!plat_dir_check(dev->pagepath))
plat_dir_create(dev->pagepath);
path_slash(dev->pagepath);
dev->page_width = PAGE_WIDTH;
dev->page_height = PAGE_HEIGHT;
dev->dpi = PAGE_DPI;
/* Create 8-bit grayscale buffer for the page. */
dev->page = (psurface_t *) malloc(sizeof(psurface_t));
dev->page->w = (int) (dev->dpi * dev->page_width);
dev->page->h = (int) (dev->dpi * dev->page_height);
dev->page->pitch = dev->page->w;
dev->page->pixels = (uint8_t *) malloc((size_t) dev->page->pitch * dev->page->h);
memset(dev->page->pixels, 0x00, (size_t) dev->page->pitch * dev->page->h);
/* Initialize parameters. */
for (uint8_t i = 0; i < 32; i++) {
dev->palcol[i].r = 255;
dev->palcol[i].g = 255;
dev->palcol[i].b = 255;
}
/* 0 = all white needed for logic 000 */
fill_palette(0, 0, 0, 1, dev);
/* 1 = magenta* 001 */
fill_palette(0, 255, 0, 1, dev);
/* 2 = cyan* 010 */
fill_palette(255, 0, 0, 2, dev);
/* 3 = "violet" 011 */
fill_palette(255, 255, 0, 3, dev);
/* 4 = yellow* 100 */
fill_palette(0, 0, 255, 4, dev);
/* 5 = red 101 */
fill_palette(0, 255, 255, 5, dev);
/* 6 = green 110 */
fill_palette(255, 0, 255, 6, dev);
/* 7 = black 111 */
fill_palette(255, 255, 255, 7, dev);
dev->color = COLOR_BLACK;
dev->fontface = 0;
dev->autofeed = 0;
reset_printer(dev);
escp_log("ESC/P: created a virtual page of dimensions %d x %d pixels.\n",
dev->page->w, dev->page->h);
timer_add(&dev->pulse_timer, pulse_timer, dev, 0);
timer_add(&dev->timeout_timer, timeout_timer, dev, 0);
return dev;
}
static void
escp_close(void *priv)
{
escp_t *dev = (escp_t *) priv;
if (dev == NULL)
return;
if (dev->page != NULL) {
/* Print last page if it contains data. */
if (dev->page->dirty)
dump_page(dev);
if (dev->page->pixels != NULL)
free(dev->page->pixels);
free(dev->page);
}
free(dev);
}
const lpt_device_t lpt_prt_escp_device = {
.name = "Generic ESC/P Dot-Matrix",
.internal_name = "dot_matrix",
.init = escp_init,
.close = escp_close,
.write_data = write_data,
.write_ctrl = write_ctrl,
.read_data = read_data,
.read_status = read_status,
.read_ctrl = read_ctrl
};
``` | /content/code_sandbox/src/printer/prt_escp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 20,470 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "x86_flags.h"
#include "codegen.h"
#include "codegen_backend.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_mov.h"
static int
NF_SET_01(void)
{
return NF_SET() ? 1 : 0;
}
static int
VF_SET_01(void)
{
return VF_SET() ? 1 : 0;
}
static int
ropJO_common(UNUSED(codeblock_t *block), ir_data_t *ir, uint32_t dest_addr, UNUSED(uint32_t next_pc))
{
int jump_uop;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Overflow is always zero*/
return 0;
case FLAGS_SUB8:
case FLAGS_DEC8:
jump_uop = uop_CMP_JNO_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
jump_uop = uop_CMP_JNO_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
jump_uop = uop_CMP_JNO_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, VF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
static int
ropJNO_common(UNUSED(codeblock_t *block), ir_data_t *ir, uint32_t dest_addr, UNUSED(uint32_t next_pc))
{
int jump_uop;
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Overflow is always zero*/
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
return 0;
case FLAGS_SUB8:
case FLAGS_DEC8:
jump_uop = uop_CMP_JO_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
jump_uop = uop_CMP_JO_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
jump_uop = uop_CMP_JO_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, VF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
static int
ropJB_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = (CF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Carry is always zero*/
return 0;
case FLAGS_SUB8:
if (do_unroll)
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
if (do_unroll)
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
if (do_unroll)
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
if (do_unroll)
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
else
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, do_unroll ? next_pc : dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJNB_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = (!CF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Carry is always zero*/
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
return 0;
case FLAGS_SUB8:
if (do_unroll)
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
if (do_unroll)
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
if (do_unroll)
jump_uop = uop_CMP_JNB_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JB_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
if (do_unroll)
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
else
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, do_unroll ? next_pc : dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
if (ZF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr)) {
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 1;
} else {
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
}
return 0;
}
int
ropJNE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
if (!ZF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr)) {
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 1;
} else {
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
}
return 0;
}
static int
ropJBE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int jump_uop2 = -1;
int do_unroll = ((CF_SET() || ZF_SET()) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Carry is always zero, so test zero only*/
if (do_unroll)
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_flags_res, 0);
else
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_flags_res, 0);
break;
case FLAGS_SUB8:
if (do_unroll)
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
if (do_unroll)
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
if (do_unroll)
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
if (do_unroll) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
} else {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
}
break;
}
if (do_unroll) {
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
return 1;
} else {
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
}
static int
ropJNBE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int jump_uop2 = -1;
int do_unroll = ((!CF_SET() && !ZF_SET()) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:
/*Carry is always zero, so test zero only*/
if (do_unroll)
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_flags_res, 0);
else
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_flags_res, 0);
break;
case FLAGS_SUB8:
if (do_unroll)
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
if (do_unroll)
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
if (do_unroll)
jump_uop = uop_CMP_JNBE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JBE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
if (do_unroll) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
} else {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, CF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
}
break;
}
if (do_unroll) {
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 1;
} else {
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
return 0;
}
}
static int
ropJS_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = (NF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ADD8:
case FLAGS_SUB8:
case FLAGS_SHL8:
case FLAGS_SHR8:
case FLAGS_SAR8:
case FLAGS_INC8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_B);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_B);
break;
case FLAGS_ZN16:
case FLAGS_ADD16:
case FLAGS_SUB16:
case FLAGS_SHL16:
case FLAGS_SHR16:
case FLAGS_SAR16:
case FLAGS_INC16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_W);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_W);
break;
case FLAGS_ZN32:
case FLAGS_ADD32:
case FLAGS_SUB32:
case FLAGS_SHL32:
case FLAGS_SHR32:
case FLAGS_SAR32:
case FLAGS_INC32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET);
if (do_unroll)
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
else
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, do_unroll ? next_pc : dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJNS_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = (!NF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
case FLAGS_ADD8:
case FLAGS_SUB8:
case FLAGS_SHL8:
case FLAGS_SHR8:
case FLAGS_SAR8:
case FLAGS_INC8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_B);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_B);
break;
case FLAGS_ZN16:
case FLAGS_ADD16:
case FLAGS_SUB16:
case FLAGS_SHL16:
case FLAGS_SHR16:
case FLAGS_SAR16:
case FLAGS_INC16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_W);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_W);
break;
case FLAGS_ZN32:
case FLAGS_ADD32:
case FLAGS_SUB32:
case FLAGS_SHL32:
case FLAGS_SHR32:
case FLAGS_SAR32:
case FLAGS_INC32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET);
if (do_unroll)
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
else
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
break;
}
uop_MOV_IMM(ir, IREG_pc, do_unroll ? next_pc : dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJP_common(UNUSED(codeblock_t *block), ir_data_t *ir, uint32_t dest_addr, UNUSED(uint32_t next_pc))
{
int jump_uop;
uop_CALL_FUNC_RESULT(ir, IREG_temp0, PF_SET);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
static int
ropJNP_common(UNUSED(codeblock_t *block), ir_data_t *ir, uint32_t dest_addr, UNUSED(uint32_t next_pc))
{
int jump_uop;
uop_CALL_FUNC_RESULT(ir, IREG_temp0, PF_SET);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
static int
ropJL_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = ((NF_SET() ? 1 : 0) != (VF_SET() ? 1 : 0) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
/*V flag is always clear. Condition is true if N is set*/
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_B);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_B);
break;
case FLAGS_ZN16:
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_W);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_W);
break;
case FLAGS_ZN32:
if (do_unroll)
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res);
else
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res);
break;
case FLAGS_SUB8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
if (do_unroll)
jump_uop = uop_CMP_JNZ_DEST(ir, IREG_temp0, IREG_temp1);
else
jump_uop = uop_CMP_JZ_DEST(ir, IREG_temp0, IREG_temp1);
break;
}
if (do_unroll)
uop_MOV_IMM(ir, IREG_pc, next_pc);
else
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJNL_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int do_unroll = ((NF_SET() ? 1 : 0) == (VF_SET() ? 1 : 0) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_ZN8:
/*V flag is always clear. Condition is true if N is set*/
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_B);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_B);
break;
case FLAGS_ZN16:
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res_W);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res_W);
break;
case FLAGS_ZN32:
if (do_unroll)
jump_uop = uop_TEST_JNS_DEST(ir, IREG_flags_res);
else
jump_uop = uop_TEST_JS_DEST(ir, IREG_flags_res);
break;
case FLAGS_SUB8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_CMP_JNL_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JL_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
if (do_unroll)
jump_uop = uop_CMP_JZ_DEST(ir, IREG_temp0, IREG_temp1);
else
jump_uop = uop_CMP_JNZ_DEST(ir, IREG_temp0, IREG_temp1);
break;
}
if (do_unroll)
uop_MOV_IMM(ir, IREG_pc, next_pc);
else
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return do_unroll ? 1 : 0;
}
static int
ropJLE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int jump_uop2 = -1;
int do_unroll = (((NF_SET() ? 1 : 0) != (VF_SET() ? 1 : 0) || ZF_SET()) && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_SUB8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
if (do_unroll) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
jump_uop = uop_CMP_JNZ_DEST(ir, IREG_temp0, IREG_temp1);
} else {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
jump_uop = uop_CMP_JZ_DEST(ir, IREG_temp0, IREG_temp1);
}
break;
}
if (do_unroll) {
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
return 1;
} else {
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 0;
}
}
static int
ropJNLE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t next_pc)
{
int jump_uop;
int jump_uop2 = -1;
int do_unroll = ((NF_SET() ? 1 : 0) == (VF_SET() ? 1 : 0) && !ZF_SET() && codegen_can_unroll(block, ir, next_pc, dest_addr));
switch (codegen_flags_changed ? cpu_state.flags_op : FLAGS_UNKNOWN) {
case FLAGS_SUB8:
case FLAGS_DEC8:
if (do_unroll)
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
else
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1_B, IREG_flags_op2_B);
break;
case FLAGS_SUB16:
case FLAGS_DEC16:
if (do_unroll)
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
else
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1_W, IREG_flags_op2_W);
break;
case FLAGS_SUB32:
case FLAGS_DEC32:
if (do_unroll)
jump_uop = uop_CMP_JNLE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
else
jump_uop = uop_CMP_JLE_DEST(ir, IREG_flags_op1, IREG_flags_op2);
break;
case FLAGS_UNKNOWN:
default:
if (do_unroll) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
jump_uop = uop_CMP_JZ_DEST(ir, IREG_temp0, IREG_temp1);
} else {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
uop_CALL_FUNC_RESULT(ir, IREG_temp0, NF_SET_01);
uop_CALL_FUNC_RESULT(ir, IREG_temp1, VF_SET_01);
jump_uop = uop_CMP_JNZ_DEST(ir, IREG_temp0, IREG_temp1);
}
break;
}
if (do_unroll) {
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
uop_MOV_IMM(ir, IREG_pc, next_pc);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
return 1;
} else {
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
if (jump_uop2 != -1)
uop_set_jump_dest(ir, jump_uop2);
return 0;
}
}
#define ropJ(cond) \
uint32_t ropJ##cond##_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc); \
uint32_t dest_addr = op_pc + 1 + offset; \
int ret; \
\
if (!(op_32 & 0x100)) \
dest_addr &= 0xffff; \
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 1); \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
return ret ? dest_addr : (op_pc + 1); \
} \
uint32_t ropJ##cond##_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int16_t) fastreadw(cs + op_pc); \
uint32_t dest_addr = (op_pc + 2 + offset) & 0xffff; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 2); \
\
codegen_mark_code_present(block, cs + op_pc, 2); \
return ret ? dest_addr : (op_pc + 2); \
} \
uint32_t ropJ##cond##_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
uint32_t dest_addr = op_pc + 4 + offset; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 4); \
\
codegen_mark_code_present(block, cs + op_pc, 4); \
return ret ? dest_addr : (op_pc + 4); \
}
ropJ(O)
ropJ(NO)
ropJ(B)
ropJ(NB)
ropJ(E)
ropJ(NE)
ropJ(BE)
ropJ(NBE)
ropJ(S)
ropJ(NS)
ropJ(P)
ropJ(NP)
ropJ(L)
ropJ(NL)
ropJ(LE)
ropJ(NLE)
uint32_t
ropJCXZ(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc);
uint32_t dest_addr = op_pc + 1 + offset;
int jump_uop;
if (!(op_32 & 0x100))
dest_addr &= 0xffff;
if (op_32 & 0x200)
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_ECX, 0);
else
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_CX, 0);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropLOOP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc);
uint32_t dest_addr = op_pc + 1 + offset;
uint32_t ret_addr;
int jump_uop;
if (!(op_32 & 0x100))
dest_addr &= 0xffff;
if (((op_32 & 0x200) ? ECX : CX) != 1 && codegen_can_unroll(block, ir, op_pc + 1, dest_addr)) {
if (op_32 & 0x200) {
uop_SUB_IMM(ir, IREG_ECX, IREG_ECX, 1);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_ECX, 0);
} else {
uop_SUB_IMM(ir, IREG_CX, IREG_CX, 1);
jump_uop = uop_CMP_IMM_JNZ_DEST(ir, IREG_CX, 0);
}
uop_MOV_IMM(ir, IREG_pc, op_pc + 1);
ret_addr = dest_addr;
CPU_BLOCK_END();
} else {
if (op_32 & 0x200) {
uop_SUB_IMM(ir, IREG_ECX, IREG_ECX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_ECX, 0);
} else {
uop_SUB_IMM(ir, IREG_CX, IREG_CX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_CX, 0);
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
ret_addr = op_pc + 1;
}
uop_JMP(ir, codegen_exit_rout);
uop_set_jump_dest(ir, jump_uop);
codegen_mark_code_present(block, cs + op_pc, 1);
return ret_addr;
}
uint32_t
ropLOOPE(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc);
uint32_t dest_addr = op_pc + 1 + offset;
int jump_uop;
int jump_uop2;
if (!(op_32 & 0x100))
dest_addr &= 0xffff;
if (op_32 & 0x200) {
uop_SUB_IMM(ir, IREG_ECX, IREG_ECX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_ECX, 0);
} else {
uop_SUB_IMM(ir, IREG_CX, IREG_CX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_CX, 0);
}
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_NOP_BARRIER(ir);
uop_set_jump_dest(ir, jump_uop);
uop_set_jump_dest(ir, jump_uop2);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropLOOPNE(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc);
uint32_t dest_addr = op_pc + 1 + offset;
int jump_uop;
int jump_uop2;
if (!(op_32 & 0x100))
dest_addr &= 0xffff;
if (op_32 & 0x200) {
uop_SUB_IMM(ir, IREG_ECX, IREG_ECX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_ECX, 0);
} else {
uop_SUB_IMM(ir, IREG_CX, IREG_CX, 1);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_CX, 0);
}
if (!codegen_flags_changed || !flags_res_valid()) {
uop_CALL_FUNC_RESULT(ir, IREG_temp0, ZF_SET);
jump_uop2 = uop_CMP_IMM_JNZ_DEST(ir, IREG_temp0, 0);
} else {
jump_uop2 = uop_CMP_IMM_JZ_DEST(ir, IREG_flags_res, 0);
}
uop_MOV_IMM(ir, IREG_pc, dest_addr);
uop_JMP(ir, codegen_exit_rout);
uop_NOP_BARRIER(ir);
uop_set_jump_dest(ir, jump_uop);
uop_set_jump_dest(ir, jump_uop2);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_branch.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,131 |
```c
#if defined __aarch64__ || defined _M_ARM64
# include <inttypes.h>
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_arm64_defs.h"
# include "codegen_backend_arm64_ops.h"
# define Rt(x) (x)
# define Rd(x) (x)
# define Rn(x) ((x) << 5)
# define Rt2(x) ((x) << 10)
# define Rm(x) ((x) << 16)
# define shift_imm6(x) ((x) << 10)
# define DATA_OFFSET_UP (1 << 23)
# define DATA_OFFSET_DOWN (0 << 23)
# define COND_EQ (0x0)
# define COND_NE (0x1)
# define COND_CS (0x2)
# define COND_CC (0x3)
# define COND_MI (0x4)
# define COND_PL (0x5)
# define COND_VS (0x6)
# define COND_VC (0x7)
# define COND_HI (0x8)
# define COND_LS (0x9)
# define COND_GE (0xa)
# define COND_LT (0xb)
# define COND_GT (0xc)
# define COND_LE (0xd)
# define CSEL_COND(cond) ((cond) << 12)
# define OPCODE_SHIFT 24
# define OPCODE_ADD_IMM (0x11 << OPCODE_SHIFT)
# define OPCODE_ADDX_IMM (0x91 << OPCODE_SHIFT)
# define OPCODE_ADR (0x10 << OPCODE_SHIFT)
# define OPCODE_B (0x14 << OPCODE_SHIFT)
# define OPCODE_BCOND (0x54 << OPCODE_SHIFT)
# define OPCODE_CBNZ (0xb5 << OPCODE_SHIFT)
# define OPCODE_CBZ (0xb4 << OPCODE_SHIFT)
# define OPCODE_CMN_IMM (0x31 << OPCODE_SHIFT)
# define OPCODE_CMNX_IMM (0xb1 << OPCODE_SHIFT)
# define OPCODE_CMP_IMM (0x71 << OPCODE_SHIFT)
# define OPCODE_CMPX_IMM (0xf1 << OPCODE_SHIFT)
# define OPCODE_SUB_IMM (0x51 << OPCODE_SHIFT)
# define OPCODE_SUBX_IMM (0xd1 << OPCODE_SHIFT)
# define OPCODE_TBNZ (0x37 << OPCODE_SHIFT)
# define OPCODE_TBZ (0x36 << OPCODE_SHIFT)
# define OPCODE_AND_IMM (0x024 << 23)
# define OPCODE_ANDS_IMM (0x0e4 << 23)
# define OPCODE_EOR_IMM (0x0a4 << 23)
# define OPCODE_MOVK_W (0x0e5 << 23)
# define OPCODE_MOVK_X (0x1e5 << 23)
# define OPCODE_MOVZ_W (0x0a5 << 23)
# define OPCODE_MOVZ_X (0x1a5 << 23)
# define OPCODE_ORR_IMM (0x064 << 23)
# define OPCODE_BFI (0x0cc << 22)
# define OPCODE_LDR_IMM_W (0x2e5 << 22)
# define OPCODE_LDR_IMM_X (0x3e5 << 22)
# define OPCODE_LDR_IMM_F64 (0x3f5 << 22)
# define OPCODE_LDRB_IMM_W (0x0e5 << 22)
# define OPCODE_LDRH_IMM (0x1e5 << 22)
# define OPCODE_LDP_POSTIDX_X (0x2a3 << 22)
# define OPCODE_SBFX (0x04c << 22)
# define OPCODE_STP_PREIDX_X (0x2a6 << 22)
# define OPCODE_STR_IMM_W (0x2e4 << 22)
# define OPCODE_STR_IMM_Q (0x3e4 << 22)
# define OPCODE_STR_IMM_F64 (0x3f4 << 22)
# define OPCODE_STRB_IMM (0x0e4 << 22)
# define OPCODE_STRH_IMM (0x1e4 << 22)
# define OPCODE_UBFX (0x14c << 22)
# define OPCODE_ADD_LSL (0x058 << 21)
# define OPCODE_ADD_LSR (0x05a << 21)
# define OPCODE_ADDX_LSL (0x458 << 21)
# define OPCODE_AND_ASR (0x054 << 21)
# define OPCODE_AND_LSL (0x050 << 21)
# define OPCODE_AND_ROR (0x056 << 21)
# define OPCODE_ANDS_LSL (0x350 << 21)
# define OPCODE_CMP_LSL (0x358 << 21)
# define OPCODE_CSEL (0x0d4 << 21)
# define OPCODE_EOR_LSL (0x250 << 21)
# define OPCODE_ORR_ASR (0x154 << 21)
# define OPCODE_ORR_LSL (0x150 << 21)
# define OPCODE_ORR_LSR (0x152 << 21)
# define OPCODE_ORR_ROR (0x156 << 21)
# define OPCODE_ORRX_LSL (0x550 << 21)
# define OPCODE_SUB_LSL (0x258 << 21)
# define OPCODE_SUB_LSR (0x25a << 21)
# define OPCODE_SUBX_LSL (0x658 << 21)
# define OPCODE_ADD_V8B (0x0e208400)
# define OPCODE_ADD_V4H (0x0e608400)
# define OPCODE_ADD_V2S (0x0ea08400)
# define OPCODE_ADDP_V4S (0x4ea0bc00)
# define OPCODE_AND_V (0x0e201c00)
# define OPCODE_ASR (0x1ac02800)
# define OPCODE_BIC_V (0x0e601c00)
# define OPCODE_BLR (0xd63f0000)
# define OPCODE_BR (0xd61f0000)
# define OPCODE_CMEQ_V8B (0x2e208c00)
# define OPCODE_CMEQ_V4H (0x2e608c00)
# define OPCODE_CMEQ_V2S (0x2ea08c00)
# define OPCODE_CMGT_V8B (0x0e203400)
# define OPCODE_CMGT_V4H (0x0e603400)
# define OPCODE_CMGT_V2S (0x0ea03400)
# define OPCODE_DUP_V2S (0x0e040400)
# define OPCODE_EOR_V (0x2e201c00)
# define OPCODE_FABS_D (0x1e60c000)
# define OPCODE_FADD_D (0x1e602800)
# define OPCODE_FADD_V2S (0x0e20d400)
# define OPCODE_FCMEQ_V2S (0x0e20e400)
# define OPCODE_FCMGE_V2S (0x2e20e400)
# define OPCODE_FCMGT_V2S (0x2ea0e400)
# define OPCODE_FCMP_D (0x1e602000)
# define OPCODE_FCVT_D_S (0x1e22c000)
# define OPCODE_FCVT_S_D (0x1e624000)
# define OPCODE_FCVTMS_W_D (0x1e700000)
# define OPCODE_FCVTMS_X_D (0x9e700000)
# define OPCODE_FCVTNS_W_D (0x1e600000)
# define OPCODE_FCVTNS_X_D (0x9e600000)
# define OPCODE_FCVTPS_W_D (0x1e680000)
# define OPCODE_FCVTPS_X_D (0x9e680000)
# define OPCODE_FCVTZS_W_D (0x1e780000)
# define OPCODE_FCVTZS_X_D (0x9e780000)
# define OPCODE_FCVTZS_V2S (0x0ea1b800)
# define OPCODE_FDIV_D (0x1e601800)
# define OPCODE_FDIV_S (0x1e201800)
# define OPCODE_FMAX_V2S (0x0e20f400)
# define OPCODE_FMIN_V2S (0x0ea0f400)
# define OPCODE_FMOV_D_D (0x1e604000)
# define OPCODE_FMOV_D_Q (0x9e670000)
# define OPCODE_FMOV_Q_D (0x9e660000)
# define OPCODE_FMOV_S_W (0x1e270000)
# define OPCODE_FMOV_W_S (0x1e260000)
# define OPCODE_FMOV_S_ONE (0x1e2e1000)
# define OPCODE_FMUL_D (0x1e600800)
# define OPCODE_FMUL_V2S (0x2e20dc00)
# define OPCODE_FNEG_D (0x1e614000)
# define OPCODE_FRINTX_D (0x1e674000)
# define OPCODE_FSQRT_D (0x1e61c000)
# define OPCODE_FSQRT_S (0x1e21c000)
# define OPCODE_FSUB_D (0x1e603800)
# define OPCODE_FSUB_V2S (0x0ea0d400)
# define OPCODE_LDR_REG (0xb8606800)
# define OPCODE_LDRX_REG (0xf8606800)
# define OPCODE_LDRB_REG (0x38606800)
# define OPCODE_LDRH_REG (0x78606800)
# define OPCODE_LDRX_REG_LSL3 (0xf8607800)
# define OPCODE_LDR_REG_F32 (0xbc606800)
# define OPCODE_LDR_REG_F64 (0xfc606800)
# define OPCODE_LDR_REG_F64_S (0xfc607800)
# define OPCODE_LSL (0x1ac02000)
# define OPCODE_LSR (0x1ac02400)
# define OPCODE_MSR_FPCR (0xd51b4400)
# define OPCODE_MUL_V4H (0x0e609c00)
# define OPCODE_NOP (0xd503201f)
# define OPCODE_ORR_V (0x0ea01c00)
# define OPCODE_RET (0xd65f0000)
# define OPCODE_ROR (0x1ac02c00)
# define OPCODE_SADDLP_V2S_4H (0x0e602800)
# define OPCODE_SCVTF_D_Q (0x9e620000)
# define OPCODE_SCVTF_D_W (0x1e620000)
# define OPCODE_SCVTF_V2S (0x0e21d800)
# define OPCODE_SQADD_V8B (0x0e200c00)
# define OPCODE_SQADD_V4H (0x0e600c00)
# define OPCODE_SQSUB_V8B (0x0e202c00)
# define OPCODE_SQSUB_V4H (0x0e602c00)
# define OPCODE_SQXTN_V8B_8H (0x0e214800)
# define OPCODE_SQXTN_V4H_4S (0x0e614800)
# define OPCODE_SHL_VD (0x0f005400)
# define OPCODE_SHL_VQ (0x4f005400)
# define OPCODE_SHRN (0x0f008400)
# define OPCODE_SMULL_V4S_4H (0x0e60c000)
# define OPCODE_SSHR_VD (0x0f000400)
# define OPCODE_SSHR_VQ (0x4f000400)
# define OPCODE_STR_REG (0xb8206800)
# define OPCODE_STRB_REG (0x38206800)
# define OPCODE_STRH_REG (0x78206800)
# define OPCODE_STR_REG_F32 (0xbc206800)
# define OPCODE_STR_REG_F64 (0xfc206800)
# define OPCODE_STR_REG_F64_S (0xfc207800)
# define OPCODE_SUB_V8B (0x2e208400)
# define OPCODE_SUB_V4H (0x2e608400)
# define OPCODE_SUB_V2S (0x2ea08400)
# define OPCODE_UQADD_V8B (0x2e200c00)
# define OPCODE_UQADD_V4H (0x2e600c00)
# define OPCODE_UQSUB_V8B (0x2e202c00)
# define OPCODE_UQSUB_V4H (0x2e602c00)
# define OPCODE_UQXTN_V8B_8H (0x2e214800)
# define OPCODE_UQXTN_V4H_4S (0x2e614800)
# define OPCODE_USHR_VD (0x2f000400)
# define OPCODE_USHR_VQ (0x6f000400)
# define OPCODE_ZIP1_V8B (0x0e003800)
# define OPCODE_ZIP1_V4H (0x0e403800)
# define OPCODE_ZIP1_V2S (0x0e803800)
# define OPCODE_ZIP2_V8B (0x0e007800)
# define OPCODE_ZIP2_V4H (0x0e407800)
# define OPCODE_ZIP2_V2S (0x0e807800)
# define DATPROC_SHIFT(sh) (sh << 10)
# define DATPROC_IMM_SHIFT(sh) (sh << 22)
# define MOV_WIDE_HW(hw) (hw << 21)
# define IMM7_X(imm_data) (((imm_data >> 3) & 0x7f) << 15)
# define IMM12(imm_data) ((imm_data) << 10)
# define IMM16(imm_data) ((imm_data) << 5)
# define IMMN(immn) ((immn) << 22)
# define IMMR(immr) ((immr) << 16)
# define IMMS(imms) ((imms) << 10)
# define IMM_LOGICAL(imm) ((imm) << 10)
# define BIT_TBxZ(bit) ((((bit) &0x1f) << 19) | (((bit) &0x20) ? (1 << 31) : 0))
# define OFFSET14(offset) (((offset >> 2) << 5) & 0x0007ffe0)
# define OFFSET19(offset) (((offset >> 2) << 5) & 0x00ffffe0)
# define OFFSET20(offset) (((offset & 3) << 29) | ((((offset) &0x1fffff) >> 2) << 5))
# define OFFSET26(offset) ((offset >> 2) & 0x03ffffff)
# define OFFSET12_B(offset) (offset << 10)
# define OFFSET12_H(offset) ((offset >> 1) << 10)
# define OFFSET12_W(offset) ((offset >> 2) << 10)
# define OFFSET12_Q(offset) ((offset >> 3) << 10)
# define SHIFT_IMM_V4H(shift) (((shift) | 0x10) << 16)
# define SHIFT_IMM_V2S(shift) (((shift) | 0x20) << 16)
# define SHIFT_IMM_V2D(shift) (((shift) | 0x40) << 16)
# define SHRN_SHIFT_IMM_V4S(shift) (((shift) | 0x10) << 16)
# define DUP_ELEMENT(element) ((element) << 19)
/*Returns true if offset fits into 19 bits*/
static int
offset_is_19bit(int offset)
{
if (offset >= (1 << (18 + 2)))
return 0;
if (offset < -(1 << (18 + 2)))
return 0;
return 1;
}
/*Returns true if offset fits into 26 bits*/
static int
offset_is_26bit(int offset)
{
if (offset >= (1 << (25 + 2)))
return 0;
if (offset < -(1 << (25 + 2)))
return 0;
return 1;
}
static inline int
imm_is_imm16(uint32_t imm_data)
{
if (!(imm_data & 0xffff0000) || !(imm_data & 0x0000ffff))
return 1;
return 0;
}
static void codegen_allocate_new_block(codeblock_t *block);
static inline void
codegen_addlong(codeblock_t *block, uint32_t val)
{
if (block_pos >= (BLOCK_MAX - 4))
codegen_allocate_new_block(block);
*(uint32_t *) &block_write_data[block_pos] = val;
block_pos += 4;
}
static void
codegen_allocate_new_block(codeblock_t *block)
{
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
uint32_t offset = (uintptr_t) new_ptr - (uintptr_t) &block_write_data[block_pos];
if (!offset_is_26bit(offset))
fatal("codegen_allocate_new_block - offset out of range %x\n", offset);
/*Add a jump instruction to the new block*/
*(uint32_t *) &block_write_data[block_pos] = OPCODE_B | OFFSET26(offset);
/*Set write address to start of new block*/
block_pos = 0;
block_write_data = new_ptr;
}
void
codegen_alloc(codeblock_t *block, int size)
{
if (block_pos >= (BLOCK_MAX - size))
codegen_allocate_new_block(block);
}
void
host_arm64_ADD_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
if (!imm_data)
host_arm64_MOV_REG(block, dst_reg, src_n_reg, 0);
else if ((int32_t) imm_data < 0 && imm_data != 0x80000000) {
host_arm64_SUB_IMM(block, dst_reg, src_n_reg, -(int32_t) imm_data);
} else if (!(imm_data & 0xff000000)) {
if (imm_data & 0xfff) {
codegen_addlong(block, OPCODE_ADD_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_ADD_IMM | Rd(dst_reg) | Rn(dst_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_ADD_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else {
host_arm64_MOVZ_IMM(block, REG_W16, imm_data & 0xffff);
host_arm64_MOVK_IMM(block, REG_W16, imm_data & 0xffff0000);
codegen_addlong(block, OPCODE_ADD_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_ADDX_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint64_t imm_data)
{
if (!(imm_data & ~0xffffffull)) {
if (imm_data & 0xfff) {
codegen_addlong(block, OPCODE_ADDX_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_ADDX_IMM | Rd(dst_reg) | Rn(dst_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_ADDX_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else
fatal("ADD_IMM_X %016" PRIu64 "\n", imm_data);
}
void
host_arm64_ADD_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ADD_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_ADD_REG_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ADD_LSR | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_ADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ADD_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ADD_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ADD_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ADD_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ADDP_V4S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ADDP_V4S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ADR(codeblock_t *block, int dst_reg, int offset)
{
codegen_addlong(block, OPCODE_ADR | Rd(dst_reg) | OFFSET20(offset));
}
void
host_arm64_AND_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
uint32_t imm_encoding = host_arm64_find_imm(imm_data);
if (imm_encoding) {
codegen_addlong(block, OPCODE_AND_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM_LOGICAL(imm_encoding));
} else {
host_arm64_mov_imm(block, REG_W16, imm_data);
codegen_addlong(block, OPCODE_AND_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_AND_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_AND_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_AND_REG_ASR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_AND_ASR | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_AND_REG_ROR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_AND_ROR | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_AND_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_AND_V | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ANDS_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
uint32_t imm_encoding = host_arm64_find_imm(imm_data);
if (imm_encoding) {
codegen_addlong(block, OPCODE_ANDS_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM_LOGICAL(imm_encoding));
} else {
host_arm64_mov_imm(block, REG_W16, imm_data);
codegen_addlong(block, OPCODE_ANDS_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_ASR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg)
{
codegen_addlong(block, OPCODE_ASR | Rd(dst_reg) | Rn(src_n_reg) | Rm(shift_reg));
}
void
host_arm64_B(codeblock_t *block, void *dest)
{
int offset;
codegen_alloc(block, 4);
offset = (uintptr_t) dest - (uintptr_t) &block_write_data[block_pos];
if (!offset_is_26bit(offset))
fatal("host_arm64_B - offset out of range %x\n", offset);
codegen_addlong(block, OPCODE_B | OFFSET26(offset));
}
void
host_arm64_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
{
codegen_addlong(block, OPCODE_BFI | Rd(dst_reg) | Rn(src_reg) | IMMN(0) | IMMR((32 - lsb) & 31) | IMMS((width - 1) & 31));
}
void
host_arm64_BLR(codeblock_t *block, int addr_reg)
{
codegen_addlong(block, OPCODE_BLR | Rn(addr_reg));
}
uint32_t *
host_arm64_BCC_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_CS | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BCS_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_CC | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BEQ_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_NE | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BGE_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_LT | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BGT_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_LE | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BHI_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_LS | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BLE_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_GT | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BLS_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_HI | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BLT_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_GE | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BMI_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_PL | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BNE_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_EQ | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BPL_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_MI | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BVC_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_VS | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm64_BVS_(codeblock_t *block)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_BCOND | COND_VC | OFFSET19(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_arm64_branch_set_offset(uint32_t *opcode, void *dest)
{
int offset = (uintptr_t) dest - (uintptr_t) opcode;
*opcode |= OFFSET26(offset);
}
void
host_arm64_BR(codeblock_t *block, int addr_reg)
{
codegen_addlong(block, OPCODE_BR | Rn(addr_reg));
}
void
host_arm64_BEQ(codeblock_t *block, void *dest)
{
uint32_t *opcode = host_arm64_BEQ_(block);
host_arm64_branch_set_offset(opcode, dest);
}
void
host_arm64_BIC_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_BIC_V | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CBNZ(codeblock_t *block, int reg, uintptr_t dest)
{
int offset;
codegen_alloc(block, 4);
offset = dest - (uintptr_t) &block_write_data[block_pos];
if (offset_is_19bit(offset)) {
codegen_addlong(block, OPCODE_CBNZ | OFFSET19(offset) | Rt(reg));
} else {
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_CBZ | OFFSET19(8) | Rt(reg));
offset = (uintptr_t) dest - (uintptr_t) &block_write_data[block_pos];
codegen_addlong(block, OPCODE_B | OFFSET26(offset));
}
}
void
host_arm64_CMEQ_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMEQ_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMEQ_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMEQ_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMEQ_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMEQ_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMGT_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMGT_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMGT_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMGT_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMGT_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CMGT_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CMN_IMM(codeblock_t *block, int src_n_reg, uint32_t imm_data)
{
if ((int32_t) imm_data < 0 && imm_data != (1ull << 31)) {
host_arm64_CMP_IMM(block, src_n_reg, -(int32_t) imm_data);
} else if (!(imm_data & 0xfffff000)) {
codegen_addlong(block, OPCODE_CMN_IMM | Rd(REG_WZR) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
} else
fatal("CMN_IMM %08x\n", imm_data);
}
void
host_arm64_CMNX_IMM(codeblock_t *block, int src_n_reg, uint64_t imm_data)
{
if ((int64_t) imm_data < 0 && imm_data != (1ull << 63)) {
host_arm64_CMPX_IMM(block, src_n_reg, -(int64_t) imm_data);
} else if (!(imm_data & 0xfffffffffffff000ull)) {
codegen_addlong(block, OPCODE_CMNX_IMM | Rd(REG_XZR) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
} else
fatal("CMNX_IMM %016" PRIx64 "\n", imm_data);
}
void
host_arm64_CMP_IMM(codeblock_t *block, int src_n_reg, uint32_t imm_data)
{
if ((int32_t) imm_data < 0 && imm_data != (1ull << 31)) {
host_arm64_CMN_IMM(block, src_n_reg, -(int32_t) imm_data);
} else if (!(imm_data & 0xfffff000)) {
codegen_addlong(block, OPCODE_CMP_IMM | Rd(REG_WZR) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
} else
fatal("CMP_IMM %08x\n", imm_data);
}
void
host_arm64_CMPX_IMM(codeblock_t *block, int src_n_reg, uint64_t imm_data)
{
if ((int64_t) imm_data < 0 && imm_data != (1ull << 63)) {
host_arm64_CMNX_IMM(block, src_n_reg, -(int64_t) imm_data);
} else if (!(imm_data & 0xfffffffffffff000ull)) {
codegen_addlong(block, OPCODE_CMPX_IMM | Rd(REG_XZR) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
} else
fatal("CMPX_IMM %08" PRIu64 "\n", imm_data);
}
void
host_arm64_CMP_REG_LSL(codeblock_t *block, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_CMP_LSL | Rd(0x1f) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_CSEL_CC(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CSEL | CSEL_COND(COND_CC) | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CSEL_EQ(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CSEL | CSEL_COND(COND_EQ) | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_CSEL_VS(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_CSEL | CSEL_COND(COND_VS) | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_DUP_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int element)
{
codegen_addlong(block, OPCODE_DUP_V2S | Rd(dst_reg) | Rn(src_n_reg) | DUP_ELEMENT(element));
}
void
host_arm64_EOR_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
uint32_t imm_encoding = host_arm64_find_imm(imm_data);
if (imm_encoding) {
codegen_addlong(block, OPCODE_EOR_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM_LOGICAL(imm_encoding));
} else {
host_arm64_mov_imm(block, REG_W16, imm_data);
codegen_addlong(block, OPCODE_EOR_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_EOR_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_EOR_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_EOR_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_EOR_V | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FABS_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FABS_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FADD_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FADD_D | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FADD_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FADD_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FCMEQ_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FCMEQ_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FCMGE_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FCMGE_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FCMGT_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FCMGT_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FCMP_D(codeblock_t *block, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FCMP_D | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FCVT_D_S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVT_D_S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVT_S_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVT_S_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTMS_W_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTMS_W_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTMS_X_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTMS_X_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTNS_W_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTNS_W_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTNS_X_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTNS_X_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTPS_W_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTPS_W_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTPS_X_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTPS_X_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTZS_W_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTZS_W_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTZS_X_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTZS_X_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FCVTZS_V2S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FCVTZS_V2S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FDIV_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FDIV_D | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FDIV_S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FDIV_S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FMAX_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FMAX_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FMIN_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FMIN_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FMUL_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FMUL_D | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FMUL_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FMUL_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FSUB_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FSUB_D | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FSUB_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_FSUB_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_FMOV_D_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FMOV_D_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FMOV_D_Q(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FMOV_D_Q | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FMOV_Q_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FMOV_Q_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FMOV_S_W(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FMOV_S_W | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FMOV_W_S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FMOV_W_S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FMOV_S_ONE(codeblock_t *block, int dst_reg)
{
codegen_addlong(block, OPCODE_FMOV_S_ONE | Rd(dst_reg));
}
void
host_arm64_FNEG_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FNEG_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FRINTX_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FRINTX_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FSQRT_D(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FSQRT_D | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_FSQRT_S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_FSQRT_S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_LDP_POSTIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset)
{
if (!in_range7_x(offset))
fatal("host_arm64_LDP_POSTIDX out of range7 %i\n", offset);
codegen_addlong(block, OPCODE_LDP_POSTIDX_X | IMM7_X(offset) | Rn(base_reg) | Rt(src_reg1) | Rt2(src_reg2));
}
void
host_arm64_LDR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_w(offset))
fatal("host_arm64_LDR_IMM_W out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_LDR_IMM_W | OFFSET12_W(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_IMM_X(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_q(offset))
fatal("host_arm64_LDR_IMM_X out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_LDR_IMM_X | OFFSET12_Q(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDR_REG | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_REG_X(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDRX_REG | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_REG_F32(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDR_REG_F32 | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_IMM_F64(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
codegen_addlong(block, OPCODE_LDR_IMM_F64 | OFFSET12_Q(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_REG_F64(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDR_REG_F64 | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDR_REG_F64_S(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDR_REG_F64_S | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDRB_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_b(offset))
fatal("host_arm64_LDRB_IMM_W out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_LDRB_IMM_W | OFFSET12_B(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_LDRB_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDRB_REG | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDRH_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_h(offset))
fatal("host_arm64_LDRH_IMM out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_LDRH_IMM | OFFSET12_H(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_LDRH_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDRH_REG | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LDRX_REG_LSL3(codeblock_t *block, int dest_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_LDRX_REG_LSL3 | Rn(base_reg) | Rm(offset_reg) | Rt(dest_reg));
}
void
host_arm64_LSL(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg)
{
codegen_addlong(block, OPCODE_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(shift_reg));
}
void
host_arm64_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg)
{
codegen_addlong(block, OPCODE_LSR | Rd(dst_reg) | Rn(src_n_reg) | Rm(shift_reg));
}
void
host_arm64_MOV_REG_ASR(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ORR_ASR | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_MOV_REG(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
if (dst_reg != src_m_reg || shift)
codegen_addlong(block, OPCODE_ORR_LSL | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ORR_LSR | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_MOV_REG_ROR(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ORR_ROR | Rd(dst_reg) | Rn(REG_WZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_MOVX_IMM(codeblock_t *block, int reg, uint64_t imm_data)
{
codegen_addlong(block, OPCODE_MOVZ_X | MOV_WIDE_HW(0) | IMM16(imm_data & 0xffff) | Rd(reg));
if ((imm_data >> 16) & 0xffff)
codegen_addlong(block, OPCODE_MOVK_X | MOV_WIDE_HW(1) | IMM16((imm_data >> 16) & 0xffff) | Rd(reg));
if ((imm_data >> 32) & 0xffff)
codegen_addlong(block, OPCODE_MOVK_X | MOV_WIDE_HW(2) | IMM16((imm_data >> 32) & 0xffff) | Rd(reg));
if ((imm_data >> 48) & 0xffff)
codegen_addlong(block, OPCODE_MOVK_X | MOV_WIDE_HW(3) | IMM16((imm_data >> 48) & 0xffff) | Rd(reg));
}
void
host_arm64_MOVX_REG(codeblock_t *block, int dst_reg, int src_m_reg, int shift)
{
if (dst_reg != src_m_reg)
codegen_addlong(block, OPCODE_ORRX_LSL | Rd(dst_reg) | Rn(REG_XZR) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_MOVZ_IMM(codeblock_t *block, int reg, uint32_t imm_data)
{
int hw;
if (!imm_is_imm16(imm_data))
fatal("MOVZ_IMM - imm not representable %08x\n", imm_data);
hw = (imm_data & 0xffff0000) ? 1 : 0;
if (hw)
imm_data >>= 16;
codegen_addlong(block, OPCODE_MOVZ_W | MOV_WIDE_HW(hw) | IMM16(imm_data) | Rd(reg));
}
void
host_arm64_MOVK_IMM(codeblock_t *block, int reg, uint32_t imm_data)
{
int hw;
if (!imm_is_imm16(imm_data))
fatal("MOVK_IMM - imm not representable %08x\n", imm_data);
hw = (imm_data & 0xffff0000) ? 1 : 0;
if (hw)
imm_data >>= 16;
codegen_addlong(block, OPCODE_MOVK_W | MOV_WIDE_HW(hw) | IMM16(imm_data) | Rd(reg));
}
void
host_arm64_MSR_FPCR(codeblock_t *block, int src_reg)
{
codegen_addlong(block, OPCODE_MSR_FPCR | Rd(src_reg));
}
void
host_arm64_MUL_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_MUL_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_NOP(codeblock_t *block)
{
codegen_addlong(block, OPCODE_NOP);
}
void
host_arm64_ORR_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
uint32_t imm_encoding = host_arm64_find_imm(imm_data);
if (imm_encoding) {
codegen_addlong(block, OPCODE_ORR_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM_LOGICAL(imm_encoding));
} else {
host_arm64_mov_imm(block, REG_W16, imm_data);
codegen_addlong(block, OPCODE_ORR_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_ORR_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_ORR_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_ORR_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ORR_V | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_RET(codeblock_t *block, int reg)
{
codegen_addlong(block, OPCODE_RET | Rn(reg));
}
void
host_arm64_ROR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg)
{
codegen_addlong(block, OPCODE_ROR | Rd(dst_reg) | Rn(src_n_reg) | Rm(shift_reg));
}
void
host_arm64_SADDLP_V2S_4H(codeblock_t *block, int dst_reg, int src_n_reg)
{
codegen_addlong(block, OPCODE_SADDLP_V2S_4H | Rd(dst_reg) | Rn(src_n_reg));
}
void
host_arm64_SBFX(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
{
codegen_addlong(block, OPCODE_SBFX | Rd(dst_reg) | Rn(src_reg) | IMMN(0) | IMMR(lsb) | IMMS((lsb + width - 1) & 31));
}
void
host_arm64_SCVTF_D_Q(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SCVTF_D_Q | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SCVTF_D_W(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SCVTF_D_W | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SCVTF_V2S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SCVTF_V2S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SHRN_V4H_4S(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 16)
fatal("host_arm64_SHRN_V4H_4S : shift > 16\n");
codegen_addlong(block, OPCODE_SHRN | Rd(dst_reg) | Rn(src_n_reg) | SHRN_SHIFT_IMM_V4S(16 - shift));
}
void
host_arm64_SMULL_V4S_4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SMULL_V4S_4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SQADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SQADD_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SQADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SQADD_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SQSUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SQSUB_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SQSUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SQSUB_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SQXTN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SQXTN_V4H_4S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_SQXTN_V4H_4S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_SHL_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
codegen_addlong(block, OPCODE_SHL_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V4H(shift));
}
void
host_arm64_SHL_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
codegen_addlong(block, OPCODE_SHL_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2S(shift));
}
void
host_arm64_SHL_V2D(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
codegen_addlong(block, OPCODE_SHL_VQ | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2D(shift));
}
void
host_arm64_SSHR_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 16)
fatal("host_arm_USHR_V4H : shift > 16\n");
codegen_addlong(block, OPCODE_SSHR_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V4H(16 - shift));
}
void
host_arm64_SSHR_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 32)
fatal("host_arm_SSHR_V2S : shift > 32\n");
codegen_addlong(block, OPCODE_SSHR_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2S(32 - shift));
}
void
host_arm64_SSHR_V2D(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 64)
fatal("host_arm_SSHR_V2D : shift > 64\n");
codegen_addlong(block, OPCODE_SSHR_VQ | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2D(64 - shift));
}
void
host_arm64_STP_PREIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset)
{
if (!in_range7_x(offset))
fatal("host_arm64_STP_PREIDX out of range7 %i\n", offset);
codegen_addlong(block, OPCODE_STP_PREIDX_X | IMM7_X(offset) | Rn(base_reg) | Rt(src_reg1) | Rt2(src_reg2));
}
void
host_arm64_STR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_w(offset))
fatal("host_arm64_STR_IMM_W out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_STR_IMM_W | OFFSET12_W(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_STR_IMM_Q(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_q(offset))
fatal("host_arm64_STR_IMM_W out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_STR_IMM_Q | OFFSET12_Q(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_STR_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STR_REG | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_STR_REG_F32(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STR_REG_F32 | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_STR_IMM_F64(codeblock_t *block, int src_reg, int base_reg, int offset)
{
codegen_addlong(block, OPCODE_STR_IMM_F64 | OFFSET12_Q(offset) | Rn(base_reg) | Rt(src_reg));
}
void
host_arm64_STR_REG_F64(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STR_REG_F64 | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_STR_REG_F64_S(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STR_REG_F64_S | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_STRB_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_b(offset))
fatal("host_arm64_STRB_IMM out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_STRB_IMM | OFFSET12_B(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_STRB_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STRB_REG | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_STRH_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if (!in_range12_h(offset))
fatal("host_arm64_STRH_IMM out of range12 %i\n", offset);
codegen_addlong(block, OPCODE_STRH_IMM | OFFSET12_H(offset) | Rn(base_reg) | Rt(dest_reg));
}
void
host_arm64_STRH_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg)
{
codegen_addlong(block, OPCODE_STRH_REG | Rn(base_reg) | Rm(offset_reg) | Rt(src_reg));
}
void
host_arm64_SUB_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data)
{
if (!imm_data)
host_arm64_MOV_REG(block, dst_reg, src_n_reg, 0);
else if ((int32_t) imm_data < 0 && imm_data != 0x80000000) {
host_arm64_ADD_IMM(block, dst_reg, src_n_reg, -(int32_t) imm_data);
} else if (!(imm_data & 0xff000000)) {
if (imm_data & 0xfff) {
codegen_addlong(block, OPCODE_SUB_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12(imm_data & 0xfff) | DATPROC_IMM_SHIFT(0));
if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_SUB_IMM | Rd(dst_reg) | Rn(dst_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else if (imm_data & 0xfff000)
codegen_addlong(block, OPCODE_SUB_IMM | Rd(dst_reg) | Rn(src_n_reg) | IMM12((imm_data >> 12) & 0xfff) | DATPROC_IMM_SHIFT(1));
} else {
host_arm64_MOVZ_IMM(block, REG_W16, imm_data & 0xffff);
host_arm64_MOVK_IMM(block, REG_W16, imm_data & 0xffff0000);
codegen_addlong(block, OPCODE_SUB_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(REG_W16) | DATPROC_SHIFT(0));
}
}
void
host_arm64_SUB_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_SUB_LSL | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_SUB_REG_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift)
{
codegen_addlong(block, OPCODE_SUB_LSR | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg) | DATPROC_SHIFT(shift));
}
void
host_arm64_SUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SUB_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SUB_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_SUB_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_SUB_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
uint32_t *
host_arm64_TBNZ(codeblock_t *block, int reg, int bit)
{
codegen_alloc(block, 12);
codegen_addlong(block, OPCODE_TBZ | Rt(reg) | BIT_TBxZ(bit) | OFFSET14(8));
codegen_addlong(block, OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_arm64_UBFX(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
{
codegen_addlong(block, OPCODE_UBFX | Rd(dst_reg) | Rn(src_reg) | IMMN(0) | IMMR(lsb) | IMMS((lsb + width - 1) & 31));
}
void
host_arm64_UQADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_UQADD_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_UQADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_UQADD_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_UQSUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_UQSUB_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_UQSUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_UQSUB_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_UQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_UQXTN_V8B_8H | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_UQXTN_V4H_4S(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_UQXTN_V4H_4S | Rd(dst_reg) | Rn(src_reg));
}
void
host_arm64_USHR_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 16)
fatal("host_arm_USHR_V4H : shift > 16\n");
codegen_addlong(block, OPCODE_USHR_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V4H(16 - shift));
}
void
host_arm64_USHR_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 32)
fatal("host_arm_USHR_V4S : shift > 32\n");
codegen_addlong(block, OPCODE_USHR_VD | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2S(32 - shift));
}
void
host_arm64_USHR_V2D(codeblock_t *block, int dst_reg, int src_n_reg, int shift)
{
if (shift > 64)
fatal("host_arm_USHR_V2D : shift > 64\n");
codegen_addlong(block, OPCODE_USHR_VQ | Rd(dst_reg) | Rn(src_n_reg) | SHIFT_IMM_V2D(64 - shift));
}
void
host_arm64_ZIP1_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP1_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP1_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP1_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP1_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP1_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP2_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP2_V8B | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP2_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP2_V4H | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_ZIP2_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg)
{
codegen_addlong(block, OPCODE_ZIP2_V2S | Rd(dst_reg) | Rn(src_n_reg) | Rm(src_m_reg));
}
void
host_arm64_call(codeblock_t *block, void *dst_addr)
{
host_arm64_MOVX_IMM(block, REG_X16, (uint64_t) dst_addr);
host_arm64_BLR(block, REG_X16);
}
void
host_arm64_jump(codeblock_t *block, uintptr_t dst_addr)
{
host_arm64_MOVX_IMM(block, REG_X16, (uint64_t) dst_addr);
host_arm64_BR(block, REG_X16);
}
void
host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data)
{
if (imm_is_imm16(imm_data))
host_arm64_MOVZ_IMM(block, reg, imm_data);
else {
host_arm64_MOVZ_IMM(block, reg, imm_data & 0xffff);
host_arm64_MOVK_IMM(block, reg, imm_data & 0xffff0000);
}
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64_ops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 18,076 |
```objective-c
uint32_t ropAND_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropAND_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropOR_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropTEST_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_logic.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,442 |
```objective-c
void host_x86_ADD8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_ADD16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_ADD32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_ADD64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data);
void host_x86_ADD8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADD16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADD32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_AND16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_AND32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_AND8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CALL(codeblock_t *block, void *p);
void host_x86_CMP16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_CMP32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_CMP64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data);
void host_x86_CMP8_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CMP16_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CMP32_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_JMP(codeblock_t *block, void *p);
void host_x86_JNZ(codeblock_t *block, void *p);
void host_x86_JZ(codeblock_t *block, void *p);
uint8_t *host_x86_JNZ_short(codeblock_t *block);
uint8_t *host_x86_JS_short(codeblock_t *block);
uint8_t *host_x86_JZ_short(codeblock_t *block);
uint32_t *host_x86_JNB_long(codeblock_t *block);
uint32_t *host_x86_JNBE_long(codeblock_t *block);
uint32_t *host_x86_JNL_long(codeblock_t *block);
uint32_t *host_x86_JNLE_long(codeblock_t *block);
uint32_t *host_x86_JNO_long(codeblock_t *block);
uint32_t *host_x86_JNS_long(codeblock_t *block);
uint32_t *host_x86_JNZ_long(codeblock_t *block);
uint32_t *host_x86_JB_long(codeblock_t *block);
uint32_t *host_x86_JBE_long(codeblock_t *block);
uint32_t *host_x86_JL_long(codeblock_t *block);
uint32_t *host_x86_JLE_long(codeblock_t *block);
uint32_t *host_x86_JO_long(codeblock_t *block);
uint32_t *host_x86_JS_long(codeblock_t *block);
uint32_t *host_x86_JZ_long(codeblock_t *block);
void host_x86_LAHF(codeblock_t *block);
void host_x86_LEA_REG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t offset);
void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV16_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV32_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV64_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV8_ABS_REG_REG_SHIFT_REG(codeblock_t *block, uint32_t addr, int base_reg, int index_reg, int shift, int src_reg);
void host_x86_MOV8_BASE_INDEX_REG(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOV16_BASE_INDEX_REG(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV64_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV8_REG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int base_reg, int index_reg, int shift);
void host_x86_MOV32_REG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOV64_REG_BASE_INDEX_SHIFT(codeblock_t *block, int dst_reg, int base_reg, int index_reg, int scale);
void host_x86_MOV16_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOV32_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOV64_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOV8_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data);
void host_x86_MOV16_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data);
void host_x86_MOV32_REG_IMM(codeblock_t *block, int reg, uint32_t imm_data);
void host_x86_MOV64_REG_IMM(codeblock_t *block, int reg, uint64_t imm_data);
void host_x86_MOV8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_data);
void host_x86_MOVSX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVSX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVSX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_BASE_INDEX_32_8(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_reg, int index_reg);
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p);
void host_x86_NOP(codeblock_t *block);
void host_x86_OR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_OR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_OR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_OR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_OR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_OR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_POP(codeblock_t *block, int src_reg);
void host_x86_PUSH(codeblock_t *block, int src_reg);
void host_x86_RET(codeblock_t *block);
void host_x86_ROL8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL8_CL(codeblock_t *block, int dst_reg);
void host_x86_ROL16_CL(codeblock_t *block, int dst_reg);
void host_x86_ROL32_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR8_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR16_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR8_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR16_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SAR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SAR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL8_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL16_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL32_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR8_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR16_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SUB8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_SUB16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_SUB32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_SUB64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data);
void host_x86_SUB8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUB16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUB32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_TEST8_REG(codeblock_t *block, int src_host_reg, int dst_host_reg);
void host_x86_TEST16_REG(codeblock_t *block, int src_host_reg, int dst_host_reg);
void host_x86_TEST32_REG(codeblock_t *block, int src_reg, int dst_reg);
void host_x86_TEST32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_XOR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_XOR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_XOR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_XOR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,144 |
```c
#if defined __aarch64__ || defined _M_ARM64
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "x86.h"
# include "x86seg_common.h"
# include "x86seg.h"
# include "x87_sf.h"
# include "x87.h"
# include "386_common.h"
# include "codegen.h"
# include "codegen_backend.h"
# include "codegen_backend_arm64_defs.h"
# include "codegen_backend_arm64_ops.h"
# include "codegen_ir_defs.h"
# define OFFSET19(offset) (((offset >> 2) << 5) & 0x00ffffe0)
# define HOST_REG_GET(reg) (IREG_GET_REG(reg) & 0x1f)
# define REG_IS_L(size) (size == IREG_SIZE_L)
# define REG_IS_W(size) (size == IREG_SIZE_W)
# define REG_IS_B(size) (size == IREG_SIZE_B)
# define REG_IS_BH(size) (size == IREG_SIZE_BH)
# define REG_IS_D(size) (size == IREG_SIZE_D)
# define REG_IS_Q(size) (size == IREG_SIZE_Q)
static int
codegen_ADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_ADD_REG(block, dest_reg, src_reg_a, src_reg_b, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_ADD_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_ADD_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_ADD_REG_LSR(block, REG_TEMP, src_reg_a, src_reg_b, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_ADD_REG_LSR(block, REG_TEMP, src_reg_b, src_reg_a, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_a, 0x0000ff00);
host_arm64_ADD_REG(block, REG_TEMP, REG_TEMP, src_reg_b, 0);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("ADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_ADD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_ADD_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_ADD_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_ADD_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_ADD_IMM(block, REG_TEMP, src_reg, uop->imm_data << 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("ADD_IMM %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_ADD_LSHIFT(codeblock_t *block, uop_t *uop)
{
host_arm64_ADD_REG(block, uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real, uop->imm_data);
return 0;
}
static int
codegen_AND(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_AND_REG_V(block, dest_reg, src_reg_a, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_AND_REG(block, dest_reg, src_reg_a, src_reg_b, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b) && dest_reg == src_reg_a) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff0000);
host_arm64_AND_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffffff00);
host_arm64_AND_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff00ff);
host_arm64_AND_REG_ASR(block, dest_reg, src_reg_a, REG_TEMP, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffffff00);
host_arm64_AND_REG_ROR(block, dest_reg, src_reg_a, REG_TEMP, 24);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff00ff);
host_arm64_AND_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_b, 0xffff00ff);
host_arm64_AND_REG_ROR(block, REG_TEMP, src_reg_a, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_ORR_IMM(block, REG_TEMP, src_reg_a, 0xffff00ff);
host_arm64_AND_REG_ROR(block, REG_TEMP, src_reg_b, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_AND_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_AND_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, uop->imm_data | 0xffff0000);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, uop->imm_data | 0xffffff00);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size)) {
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, (uop->imm_data << 8) | 0xffff00ff);
} else
fatal("AND_IMM %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_ANDN(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_BIC_REG_V(block, dest_reg, src_reg_b, src_reg_a);
} else
fatal("ANDN %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_CALL_FUNC(codeblock_t *block, uop_t *uop)
{
host_arm64_call(block, uop->p);
return 0;
}
static int
codegen_CALL_FUNC_RESULT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_L(dest_size))
fatal("CALL_FUNC_RESULT %02x\n", uop->dest_reg_a_real);
host_arm64_call(block, uop->p);
host_arm64_MOV_REG(block, dest_reg, REG_W0, 0);
return 0;
}
static int
codegen_CALL_INSTRUCTION_FUNC(codeblock_t *block, uop_t *uop)
{
host_arm64_call(block, uop->p);
host_arm64_CBNZ(block, REG_X0, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_CMP_IMM_JZ(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_arm64_CMP_IMM(block, src_reg, uop->imm_data);
} else
fatal("CMP_IMM_JZ %02x\n", uop->src_reg_a_real);
host_arm64_BEQ(block, uop->p);
return 0;
}
static int
codegen_CMP_IMM_JNZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_arm64_CMP_IMM(block, src_reg, uop->imm_data);
} else if (REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xffff);
host_arm64_CMP_IMM(block, REG_TEMP, uop->imm_data);
} else
fatal("CMP_IMM_JNZ_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BNE_(block);
return 0;
}
static int
codegen_CMP_IMM_JZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_arm64_CMP_IMM(block, src_reg, uop->imm_data);
} else if (REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xffff);
host_arm64_CMP_IMM(block, REG_TEMP, uop->imm_data);
} else
fatal("CMP_IMM_JZ_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BEQ_(block);
return 0;
}
static int
codegen_CMP_JB(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
uint32_t *jump_p;
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else
fatal("CMP_JB %02x\n", uop->src_reg_a_real);
jump_p = host_arm64_BCC_(block);
host_arm64_branch_set_offset(jump_p, uop->p);
return 0;
}
static int
codegen_CMP_JNBE(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
uint32_t *jump_p;
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else
fatal("CMP_JNBE %02x\n", uop->src_reg_a_real);
jump_p = host_arm64_BHI_(block);
host_arm64_branch_set_offset(jump_p, uop->p);
return 0;
}
static int
codegen_CMP_JNB_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNB_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BCS_(block);
return 0;
}
static int
codegen_CMP_JNBE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNBE_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BHI_(block);
return 0;
}
static int
codegen_CMP_JNL_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNL_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BGE_(block);
return 0;
}
static int
codegen_CMP_JNLE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNLE_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BGT_(block);
return 0;
}
static int
codegen_CMP_JNO_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNO_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BVC_(block);
return 0;
}
static int
codegen_CMP_JNZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JNZ_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BNE_(block);
return 0;
}
static int
codegen_CMP_JB_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JB_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BCC_(block);
return 0;
}
static int
codegen_CMP_JBE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JBE_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BLS_(block);
return 0;
}
static int
codegen_CMP_JL_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JL_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BLT_(block);
return 0;
}
static int
codegen_CMP_JLE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JLE_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BLE_(block);
return 0;
}
static int
codegen_CMP_JO_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JO_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BVS_(block);
return 0;
}
static int
codegen_CMP_JZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_CMP_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 16);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 16);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg_a, 24);
host_arm64_CMP_REG_LSL(block, REG_TEMP, src_reg_b, 24);
} else
fatal("CMP_JZ_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BEQ_(block);
return 0;
}
static int
codegen_FABS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a)) {
host_arm64_FABS_D(block, dest_reg, src_reg_a);
} else
fatal("codegen_FABS %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_FCHS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a)) {
host_arm64_FNEG_D(block, dest_reg, src_reg_a);
} else
fatal("codegen_FCHS %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_FSQRT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a)) {
host_arm64_FSQRT_D(block, dest_reg, src_reg_a);
} else
fatal("codegen_FSQRT %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_FTST(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_W(dest_size) && REG_IS_D(src_size_a)) {
host_arm64_FSUB_D(block, REG_V_TEMP, REG_V_TEMP, REG_V_TEMP);
host_arm64_MOVZ_IMM(block, dest_reg, 0);
host_arm64_FCMP_D(block, src_reg_a, REG_V_TEMP);
host_arm64_ORR_IMM(block, REG_TEMP, dest_reg, FPU_SW_C3);
host_arm64_ORR_IMM(block, REG_TEMP2, dest_reg, FPU_SW_C0);
host_arm64_CSEL_EQ(block, dest_reg, REG_TEMP, dest_reg);
host_arm64_ORR_IMM(block, REG_TEMP, dest_reg, FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3);
host_arm64_CSEL_CC(block, dest_reg, REG_TEMP2, dest_reg);
host_arm64_CSEL_VS(block, dest_reg, REG_TEMP, dest_reg);
} else
fatal("codegen_FTST %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_arm64_FADD_D(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("codegen_FADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FCOM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_W(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_arm64_MOVZ_IMM(block, dest_reg, 0);
host_arm64_FCMP_D(block, src_reg_a, src_reg_b);
host_arm64_ORR_IMM(block, REG_TEMP, dest_reg, FPU_SW_C3);
host_arm64_ORR_IMM(block, REG_TEMP2, dest_reg, FPU_SW_C0);
host_arm64_CSEL_EQ(block, dest_reg, REG_TEMP, dest_reg);
host_arm64_ORR_IMM(block, REG_TEMP, dest_reg, FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3);
host_arm64_CSEL_CC(block, dest_reg, REG_TEMP2, dest_reg);
host_arm64_CSEL_VS(block, dest_reg, REG_TEMP, dest_reg);
} else
fatal("codegen_FCOM %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FDIV(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_arm64_FDIV_D(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("codegen_FDIV %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FMUL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_arm64_FMUL_D(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("codegen_FMUL %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FSUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_arm64_FSUB_D(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("codegen_FSUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_FP_ENTER(codeblock_t *block, uop_t *uop)
{
uint32_t *branch_ptr;
if (!in_range12_w((uintptr_t) &cr0 - (uintptr_t) &cpu_state))
fatal("codegen_FP_ENTER - out of range\n");
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cr0 - (uintptr_t) &cpu_state);
host_arm64_TST_IMM(block, REG_TEMP, 0xc);
branch_ptr = host_arm64_BEQ_(block);
host_arm64_mov_imm(block, REG_TEMP, uop->imm_data);
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.oldpc - (uintptr_t) &cpu_state);
host_arm64_mov_imm(block, REG_ARG0, 7);
host_arm64_call(block, x86_int);
host_arm64_B(block, codegen_exit_rout);
host_arm64_branch_set_offset(branch_ptr, &block_write_data[block_pos]);
return 0;
}
static int
codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
{
uint32_t *branch_ptr;
if (!in_range12_w((uintptr_t) &cr0 - (uintptr_t) &cpu_state))
fatal("codegen_MMX_ENTER - out of range\n");
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cr0 - (uintptr_t) &cpu_state);
host_arm64_TST_IMM(block, REG_TEMP, 0xc);
branch_ptr = host_arm64_BEQ_(block);
host_arm64_mov_imm(block, REG_TEMP, uop->imm_data);
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.oldpc - (uintptr_t) &cpu_state);
host_arm64_mov_imm(block, REG_ARG0, 7);
host_arm64_call(block, x86_int);
host_arm64_B(block, codegen_exit_rout);
host_arm64_branch_set_offset(branch_ptr, &block->data[block_pos]);
host_arm64_mov_imm(block, REG_TEMP, 0x01010101);
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.tag[0] - (uintptr_t) &cpu_state);
host_arm64_STR_IMM_W(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.tag[4] - (uintptr_t) &cpu_state);
host_arm64_STR_IMM_W(block, REG_WZR, REG_CPUSTATE, (uintptr_t) &cpu_state.TOP - (uintptr_t) &cpu_state);
host_arm64_STRB_IMM(block, REG_WZR, REG_CPUSTATE, (uintptr_t) &cpu_state.ismmx - (uintptr_t) &cpu_state);
return 0;
}
static int
codegen_JMP(codeblock_t *block, uop_t *uop)
{
host_arm64_jump(block, (uintptr_t) uop->p);
return 0;
}
static int
codegen_LOAD_FUNC_ARG0(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_ARG0, src_reg, 0xffff);
} else
fatal("codegen_LOAD_FUNC_ARG0 %02x\n", uop->src_reg_a_real);
return 0;
}
static int
codegen_LOAD_FUNC_ARG1(codeblock_t *block, uop_t *uop)
{
fatal("codegen_LOAD_FUNC_ARG1 %02x\n", uop->src_reg_a_real);
return 0;
}
static int
codegen_LOAD_FUNC_ARG2(codeblock_t *block, uop_t *uop)
{
fatal("codegen_LOAD_FUNC_ARG2 %02x\n", uop->src_reg_a_real);
return 0;
}
static int
codegen_LOAD_FUNC_ARG3(codeblock_t *block, uop_t *uop)
{
fatal("codegen_LOAD_FUNC_ARG3 %02x\n", uop->src_reg_a_real);
return 0;
}
static int
codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_ARG0, uop->imm_data);
return 0;
}
static int
codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_ARG1, uop->imm_data);
return 0;
}
static int
codegen_LOAD_FUNC_ARG2_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_ARG2, uop->imm_data);
return 0;
}
static int
codegen_LOAD_FUNC_ARG3_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_ARG3, uop->imm_data);
return 0;
}
static int
codegen_LOAD_SEG(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (!REG_IS_W(src_size))
fatal("LOAD_SEG %02x %p\n", uop->src_reg_a_real, uop->p);
host_arm64_MOVX_IMM(block, REG_ARG1, (uint64_t) uop->p);
host_arm64_AND_IMM(block, REG_ARG0, src_reg, 0xffff);
host_arm64_call(block, (void *) loadseg);
host_arm64_CBNZ(block, REG_X0, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_LOAD_ABS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_arm64_ADD_IMM(block, REG_X0, seg_reg, uop->imm_data);
if (REG_IS_B(dest_size) || REG_IS_BH(dest_size)) {
host_arm64_call(block, codegen_mem_load_byte);
} else if (REG_IS_W(dest_size)) {
host_arm64_call(block, codegen_mem_load_word);
} else if (REG_IS_L(dest_size)) {
host_arm64_call(block, codegen_mem_load_long);
} else
fatal("MEM_LOAD_ABS - %02x\n", uop->dest_reg_a_real);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
if (REG_IS_B(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 0, 8);
} else if (REG_IS_BH(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 8, 8);
} else if (REG_IS_W(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 0, 16);
} else if (REG_IS_L(dest_size)) {
host_arm64_MOV_REG(block, dest_reg, REG_X0, 0);
}
return 0;
}
static int
codegen_MEM_LOAD_REG(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_arm64_ADD_REG(block, REG_X0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
if (REG_IS_B(dest_size) || REG_IS_BH(dest_size)) {
host_arm64_call(block, codegen_mem_load_byte);
} else if (REG_IS_W(dest_size)) {
host_arm64_call(block, codegen_mem_load_word);
} else if (REG_IS_L(dest_size)) {
host_arm64_call(block, codegen_mem_load_long);
} else if (REG_IS_Q(dest_size)) {
host_arm64_call(block, codegen_mem_load_quad);
} else
fatal("MEM_LOAD_REG - %02x\n", uop->dest_reg_a_real);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
if (REG_IS_B(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 0, 8);
} else if (REG_IS_BH(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 8, 8);
} else if (REG_IS_W(dest_size)) {
host_arm64_BFI(block, dest_reg, REG_X0, 0, 16);
} else if (REG_IS_L(dest_size)) {
host_arm64_MOV_REG(block, dest_reg, REG_X0, 0);
} else if (REG_IS_Q(dest_size)) {
host_arm64_FMOV_D_D(block, dest_reg, REG_V_TEMP);
}
return 0;
}
static int
codegen_MEM_LOAD_DOUBLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_D(dest_size))
fatal("MEM_LOAD_DOUBLE - %02x\n", uop->dest_reg_a_real);
host_arm64_ADD_REG(block, REG_X0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
host_arm64_call(block, codegen_mem_load_double);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
host_arm64_FMOV_D_D(block, dest_reg, REG_V_TEMP);
return 0;
}
static int
codegen_MEM_LOAD_SINGLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_D(dest_size))
fatal("MEM_LOAD_DOUBLE - %02x\n", uop->dest_reg_a_real);
host_arm64_ADD_REG(block, REG_X0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
host_arm64_call(block, codegen_mem_load_single);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
host_arm64_FCVT_D_S(block, dest_reg, REG_V_TEMP);
return 0;
}
static int
codegen_MEM_STORE_ABS(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_size = IREG_GET_SIZE(uop->src_reg_b_real);
host_arm64_ADD_IMM(block, REG_W0, seg_reg, uop->imm_data);
if (REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, REG_W1, src_reg, 0xff);
host_arm64_call(block, codegen_mem_store_byte);
} else if (REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_W1, src_reg, 8, 8);
host_arm64_call(block, codegen_mem_store_byte);
} else if (REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_W1, src_reg, 0xffff);
host_arm64_call(block, codegen_mem_store_word);
} else if (REG_IS_L(src_size)) {
host_arm64_MOV_REG(block, REG_W1, src_reg, 0);
host_arm64_call(block, codegen_mem_store_long);
} else
fatal("MEM_STORE_ABS - %02x\n", uop->dest_reg_a_real);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_REG(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
if (REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, REG_W1, src_reg, 0xff);
host_arm64_call(block, codegen_mem_store_byte);
} else if (REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_W1, src_reg, 8, 8);
host_arm64_call(block, codegen_mem_store_byte);
} else if (REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_W1, src_reg, 0xffff);
host_arm64_call(block, codegen_mem_store_word);
} else if (REG_IS_L(src_size)) {
host_arm64_MOV_REG(block, REG_W1, src_reg, 0);
host_arm64_call(block, codegen_mem_store_long);
} else if (REG_IS_Q(src_size)) {
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_mem_store_quad);
} else
fatal("MEM_STORE_REG - %02x\n", uop->src_reg_c_real);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_8(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
host_arm64_mov_imm(block, REG_W1, uop->imm_data);
host_arm64_call(block, codegen_mem_store_byte);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_16(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
host_arm64_mov_imm(block, REG_W1, uop->imm_data);
host_arm64_call(block, codegen_mem_store_word);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_32(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
host_arm64_mov_imm(block, REG_W1, uop->imm_data);
host_arm64_call(block, codegen_mem_store_long);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_SINGLE(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
if (!REG_IS_D(src_size))
fatal("MEM_STORE_REG - %02x\n", uop->dest_reg_a_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
host_arm64_FCVT_S_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_mem_store_single);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_DOUBLE(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
if (!REG_IS_D(src_size))
fatal("MEM_STORE_REG - %02x\n", uop->dest_reg_a_real);
host_arm64_ADD_REG(block, REG_W0, seg_reg, addr_reg, 0);
if (uop->imm_data)
host_arm64_ADD_IMM(block, REG_X0, REG_X0, uop->imm_data);
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_mem_store_double);
host_arm64_CBNZ(block, REG_X1, (uintptr_t) codegen_exit_rout);
return 0;
}
static int
codegen_MOV(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_MOV_REG(block, dest_reg, src_reg, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_BFI(block, dest_reg, src_reg, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_BFI(block, dest_reg, src_reg, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size)) {
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_B(src_size)) {
host_arm64_BFI(block, dest_reg, src_reg, 8, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else if (REG_IS_D(dest_size) && REG_IS_D(src_size)) {
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
} else if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
} else
fatal("MOV %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOV_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_L(dest_size)) {
host_arm64_mov_imm(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size)) {
host_arm64_MOVK_IMM(block, dest_reg, uop->imm_data & 0xffff);
} else if (REG_IS_B(dest_size)) {
host_arm64_MOVZ_IMM(block, REG_TEMP, uop->imm_data & 0xff);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size)) {
host_arm64_MOVZ_IMM(block, REG_TEMP, uop->imm_data & 0xff);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("MOV_IMM %x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOV_PTR(codeblock_t *block, uop_t *uop)
{
host_arm64_MOVX_IMM(block, uop->dest_reg_a_real, (uint64_t) uop->p);
return 0;
}
static int
codegen_MOVSX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_B(src_size)) {
host_arm64_SBFX(block, dest_reg, src_reg, 0, 8);
} else if (REG_IS_L(dest_size) && REG_IS_BH(src_size)) {
host_arm64_SBFX(block, dest_reg, src_reg, 8, 8);
} else if (REG_IS_L(dest_size) && REG_IS_W(src_size)) {
host_arm64_SBFX(block, dest_reg, src_reg, 0, 16);
} else if (REG_IS_W(dest_size) && REG_IS_B(src_size)) {
host_arm64_SBFX(block, REG_TEMP, src_reg, 0, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_W(dest_size) && REG_IS_BH(src_size)) {
host_arm64_SBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else
fatal("MOVSX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_L(src_size)) {
host_arm64_FMOV_D_Q(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_Q(src_size)) {
host_arm64_FMOV_W_S(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, 0xff);
} else if (REG_IS_L(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, dest_reg, src_reg, 8, 8);
} else if (REG_IS_L(dest_size) && REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, dest_reg, src_reg, 0xffff);
} else if (REG_IS_W(dest_size) && REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xff);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_W(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOV_DOUBLE_INT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_L(src_size)) {
host_arm64_SCVTF_D_W(block, dest_reg, src_reg);
} else if (REG_IS_D(dest_size) && REG_IS_W(src_size)) {
host_arm64_SBFX(block, REG_TEMP, src_reg, 0, 16);
host_arm64_SCVTF_D_W(block, dest_reg, REG_TEMP);
} else if (REG_IS_D(dest_size) && REG_IS_Q(src_size)) {
host_arm64_FMOV_Q_D(block, REG_TEMP, src_reg);
host_arm64_SCVTF_D_Q(block, dest_reg, REG_TEMP);
} else
fatal("MOV_DOUBLE_INT %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOV_INT_DOUBLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_D(src_size)) {
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_fp_round);
host_arm64_MOV_REG(block, dest_reg, REG_TEMP, 0);
} else if (REG_IS_W(dest_size) && REG_IS_D(src_size)) {
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_fp_round);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else
fatal("MOV_INT_DOUBLE %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_64_reg = HOST_REG_GET(uop->src_reg_b_real);
int tag_reg = HOST_REG_GET(uop->src_reg_c_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
int src_64_size = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_D(src_size) && REG_IS_Q(src_64_size)) {
uint32_t *branch_offset;
/*If TAG_UINT64 is set then the source is MM[]. Otherwise it is a double in ST()*/
host_arm64_FMOV_D_D(block, dest_reg, src_64_reg);
branch_offset = host_arm64_TBNZ(block, tag_reg, 7);
host_arm64_FMOV_D_D(block, REG_V_TEMP, src_reg);
host_arm64_call(block, codegen_fp_round_quad);
host_arm64_FMOV_D_Q(block, dest_reg, REG_TEMP);
host_arm64_branch_set_offset(branch_offset, &block_write_data[block_pos]);
} else
fatal("MOV_INT_DOUBLE_64 %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_MOV_REG_PTR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_arm64_MOVX_IMM(block, REG_TEMP, (uint64_t) uop->p);
if (REG_IS_L(dest_size)) {
host_arm64_LDR_IMM_W(block, dest_reg, REG_TEMP, 0);
} else
fatal("MOV_REG_PTR %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOVZX_REG_PTR_8(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_arm64_MOVX_IMM(block, REG_TEMP, (uint64_t) uop->p);
if (REG_IS_L(dest_size)) {
host_arm64_LDRB_IMM_W(block, dest_reg, REG_TEMP, 0);
} else if (REG_IS_W(dest_size)) {
host_arm64_LDRB_IMM_W(block, REG_TEMP, REG_TEMP, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size)) {
host_arm64_LDRB_IMM_W(block, REG_TEMP, REG_TEMP, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else
fatal("MOVZX_REG_PTR_8 %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOVZX_REG_PTR_16(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_arm64_MOVX_IMM(block, REG_TEMP, (uint64_t) uop->p);
if (REG_IS_L(dest_size)) {
host_arm64_LDRH_IMM(block, dest_reg, REG_TEMP, 0);
} else if (REG_IS_W(dest_size)) {
host_arm64_LDRH_IMM(block, REG_TEMP, REG_TEMP, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else
fatal("MOVZX_REG_PTR_16 %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_NOP(codeblock_t *block, uop_t *uop)
{
return 0;
}
static int
codegen_OR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ORR_REG_V(block, dest_reg, src_reg_a, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_ORR_REG(block, dest_reg, src_reg_a, src_reg_b, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_ORR_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_b, 0xff);
host_arm64_ORR_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_UBFX(block, REG_TEMP, src_reg_b, 8, 8);
host_arm64_ORR_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_b, 0xff);
host_arm64_ORR_REG(block, dest_reg, src_reg_a, REG_TEMP, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_UBFX(block, REG_TEMP, src_reg_b, 8, 8);
host_arm64_ORR_REG(block, dest_reg, src_reg_a, REG_TEMP, 8);
} else
fatal("OR %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_OR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_ORR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size) && dest_reg == src_reg) {
host_arm64_ORR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size) && dest_reg == src_reg) {
host_arm64_ORR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size) && dest_reg == src_reg) {
host_arm64_ORR_IMM(block, dest_reg, src_reg, uop->imm_data << 8);
} else
fatal("OR_IMM %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PACKSSWB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_arm64_SQXTN_V8B_8H(block, REG_V_TEMP, src_reg_b);
host_arm64_SQXTN_V8B_8H(block, dest_reg, dest_reg);
host_arm64_ZIP1_V2S(block, dest_reg, dest_reg, REG_V_TEMP);
} else
fatal("PACKSSWB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PACKSSDW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_arm64_SQXTN_V4H_4S(block, REG_V_TEMP, src_reg_b);
host_arm64_SQXTN_V4H_4S(block, dest_reg, dest_reg);
host_arm64_ZIP1_V2S(block, dest_reg, dest_reg, REG_V_TEMP);
} else
fatal("PACKSSDW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PACKUSWB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real), src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real), src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_arm64_UQXTN_V8B_8H(block, REG_V_TEMP, src_reg_b);
host_arm64_UQXTN_V8B_8H(block, dest_reg, dest_reg);
host_arm64_ZIP1_V2S(block, dest_reg, dest_reg, REG_V_TEMP);
} else
fatal("PACKUSWB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ADD_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ADD_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ADD_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SQADD_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SQADD_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDUSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_UQADD_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDUSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PADDUSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_UQADD_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PADDUSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPEQB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMEQ_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPEQB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPEQW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMEQ_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPEQW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPEQD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMEQ_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPEQD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPGTB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMGT_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPGTB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPGTW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMGT_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPGTW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PCMPGTD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_CMGT_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PCMPGTD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PF2ID(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
host_arm64_FCVTZS_V2S(block, dest_reg, src_reg_a);
} else
fatal("PF2ID %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_PFADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FADD_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFCMPEQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FCMEQ_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFCMPEQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFCMPGE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FCMGE_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFCMPGE %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFCMPGT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FCMGT_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFCMPGT %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFMAX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FMAX_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFMAX %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFMIN(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FMIN_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFMIN %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFMUL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FMUL_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFMUL %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PFRCP(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
/*TODO: This could be improved (use VRECPE/VRECPS)*/
host_arm64_FMOV_S_ONE(block, REG_V_TEMP);
host_arm64_FDIV_S(block, dest_reg, REG_V_TEMP, src_reg_a);
host_arm64_DUP_V2S(block, dest_reg, dest_reg, 0);
} else
fatal("PFRCP %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_PFRSQRT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
/*TODO: This could be improved (use VRSQRTE/VRSQRTS)*/
host_arm64_FSQRT_S(block, REG_V_TEMP, src_reg_a);
host_arm64_FMOV_S_ONE(block, REG_V_TEMP);
host_arm64_FDIV_S(block, dest_reg, dest_reg, REG_V_TEMP);
host_arm64_DUP_V2S(block, dest_reg, dest_reg, 0);
} else
fatal("PFRSQRT %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_PFSUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_FSUB_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PFSUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PI2FD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
host_arm64_SCVTF_V2S(block, dest_reg, src_reg_a);
} else
fatal("PI2FD %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_PMADDWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SMULL_V4S_4H(block, REG_V_TEMP, src_reg_a, src_reg_b);
host_arm64_ADDP_V4S(block, dest_reg, REG_V_TEMP, REG_V_TEMP);
} else
fatal("PMULHW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PMULHW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SMULL_V4S_4H(block, dest_reg, src_reg_a, src_reg_b);
host_arm64_SHRN_V4H_4S(block, dest_reg, dest_reg, 16);
} else
fatal("PMULHW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PMULLW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_MUL_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PMULLW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSLLW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 15)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_SHL_V4H(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSLLW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSLLD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 31)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_SHL_V2S(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSLLD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSLLQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 63)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_SHL_V2D(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSLLQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRAW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 15)
host_arm64_SSHR_V4H(block, dest_reg, src_reg, 15);
else
host_arm64_SSHR_V4H(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRAW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRAD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 31)
host_arm64_SSHR_V2S(block, dest_reg, src_reg, 31);
else
host_arm64_SSHR_V2S(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRAD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRAQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 63)
host_arm64_SSHR_V2D(block, dest_reg, src_reg, 63);
else
host_arm64_SSHR_V2D(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRAQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRLW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 15)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_USHR_V4H(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRLW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRLD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 31)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_USHR_V2S(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRLD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSRLQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
if (uop->imm_data == 0)
host_arm64_FMOV_D_D(block, dest_reg, src_reg);
else if (uop->imm_data > 63)
host_arm64_EOR_REG_V(block, dest_reg, dest_reg, dest_reg);
else
host_arm64_USHR_V2D(block, dest_reg, src_reg, uop->imm_data);
} else
fatal("PSRLQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_PSUBB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SUB_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SUB_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SUB_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SQSUB_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_SQSUB_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBUSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_UQSUB_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBUSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PSUBUSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_UQSUB_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PSUBUSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKHBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP2_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKHBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKHWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP2_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKHWD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKHDQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP2_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKHDQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKLBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP1_V8B(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKLBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKLWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP1_V4H(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKLWD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_PUNPCKLDQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_ZIP1_V2S(block, dest_reg, src_reg_a, src_reg_b);
} else
fatal("PUNPCKLDQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_ROL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_mov_imm(block, REG_TEMP2, 32);
host_arm64_SUB_REG(block, REG_TEMP2, REG_TEMP2, shift_reg, 0);
host_arm64_ROR(block, dest_reg, src_reg, REG_TEMP2);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_mov_imm(block, REG_TEMP2, 16);
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 16);
host_arm64_SUB_REG(block, REG_TEMP2, REG_TEMP2, shift_reg, 0);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 16);
host_arm64_ROR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
cs = cs;
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_mov_imm(block, REG_TEMP2, 8);
host_arm64_SUB_REG(block, REG_TEMP2, REG_TEMP2, shift_reg, 0);
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 8);
host_arm64_AND_IMM(block, REG_TEMP2, REG_TEMP2, 7);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_mov_imm(block, REG_TEMP2, 8);
host_arm64_SUB_REG(block, REG_TEMP2, REG_TEMP2, shift_reg, 0);
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_AND_IMM(block, REG_TEMP2, REG_TEMP2, 7);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("ROL %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_ROL_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (!(uop->imm_data & 31)) {
if (src_reg != dest_reg)
host_arm64_MOV_REG(block, dest_reg, src_reg, 0);
} else {
host_arm64_MOV_REG_ROR(block, dest_reg, src_reg, 32 - (uop->imm_data & 31));
}
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if ((uop->imm_data & 15) == 0) {
if (src_reg != dest_reg)
host_arm64_BFI(block, dest_reg, src_reg, 0, 16);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 16);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 16);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 16 - (uop->imm_data & 15));
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if ((uop->imm_data & 7) == 0) {
if (src_reg != dest_reg)
host_arm64_BFI(block, dest_reg, src_reg, 0, 8);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 8);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8 - (uop->imm_data & 7));
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
if ((uop->imm_data & 7) == 0) {
if (src_reg != dest_reg)
fatal("ROL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8 - (uop->imm_data & 7));
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
} else
fatal("ROL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_ROR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_ROR(block, dest_reg, src_reg, shift_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 16);
host_arm64_AND_IMM(block, REG_TEMP2, shift_reg, 15);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 16);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 8);
host_arm64_AND_IMM(block, REG_TEMP2, shift_reg, 7);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_AND_IMM(block, REG_TEMP2, shift_reg, 7);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, REG_TEMP2);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("ROR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_ROR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (!(uop->imm_data & 31)) {
if (src_reg != dest_reg)
host_arm64_MOV_REG(block, dest_reg, src_reg, 0);
} else {
host_arm64_MOV_REG_ROR(block, dest_reg, src_reg, uop->imm_data & 31);
}
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if ((uop->imm_data & 15) == 0) {
if (src_reg != dest_reg)
fatal("ROR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 16);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 16);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data & 15);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
}
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if ((uop->imm_data & 7) == 0) {
if (src_reg != dest_reg)
fatal("ROR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 0, 8);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data & 7);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
}
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
if ((uop->imm_data & 7) == 0) {
if (src_reg != dest_reg)
fatal("ROR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
} else {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_ORR_REG(block, REG_TEMP, REG_TEMP, REG_TEMP, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data & 7);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
}
} else
fatal("ROR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SAR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_ASR(block, dest_reg, src_reg, shift_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 16);
host_arm64_ASR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 16, 16);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 24);
host_arm64_ASR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 24, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 16);
host_arm64_ASR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 24, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SAR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SAR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_MOV_REG_ASR(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 16);
host_arm64_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 16, 16);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 24);
host_arm64_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 24, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, 16);
host_arm64_MOV_REG_ASR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_UBFX(block, REG_TEMP, REG_TEMP, 24, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SAR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SHL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_LSL(block, dest_reg, src_reg, shift_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_LSL(block, REG_TEMP, src_reg, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_LSL(block, REG_TEMP, src_reg, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_LSL(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SHL %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SHL_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_MOV_REG(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_MOV_REG(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_MOV_REG(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SHL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SHR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_LSR(block, dest_reg, src_reg, shift_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xffff);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xff);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_LSR(block, REG_TEMP, REG_TEMP, shift_reg);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SHR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_SHR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_MOV_REG_LSR(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xffff);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg, 0xff);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_UBFX(block, REG_TEMP, src_reg, 8, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SHR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_STORE_PTR_IMM(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_W16, uop->imm_data);
if (in_range12_w((uintptr_t) uop->p - (uintptr_t) &cpu_state))
host_arm64_STR_IMM_W(block, REG_W16, REG_CPUSTATE, (uintptr_t) uop->p - (uintptr_t) &cpu_state);
else
fatal("codegen_STORE_PTR_IMM - not in range\n");
return 0;
}
static int
codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
{
host_arm64_mov_imm(block, REG_W16, uop->imm_data);
if (in_range12_b((uintptr_t) uop->p - (uintptr_t) &cpu_state))
host_arm64_STRB_IMM(block, REG_W16, REG_CPUSTATE, (uintptr_t) uop->p - (uintptr_t) &cpu_state);
else
fatal("codegen_STORE_PTR_IMM - not in range\n");
return 0;
}
static int
codegen_SUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_SUB_REG(block, dest_reg, src_reg_a, src_reg_b, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_arm64_SUB_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_SUB_REG(block, REG_TEMP, src_reg_a, src_reg_b, 0);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_SUB_REG_LSR(block, REG_TEMP, src_reg_a, src_reg_b, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_SUB_REG(block, REG_TEMP, src_reg_a, src_reg_b, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg_a, 8);
host_arm64_SUB_REG_LSR(block, REG_TEMP, REG_TEMP, src_reg_b, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b)) {
host_arm64_SUB_REG(block, REG_TEMP, src_reg_a, src_reg_b, 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b)) {
host_arm64_MOV_REG_LSR(block, REG_TEMP, src_reg_a, 8);
host_arm64_SUB_REG_LSR(block, REG_TEMP, REG_TEMP, src_reg_b, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_SUB_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_SUB_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_arm64_SUB_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 16);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_arm64_SUB_IMM(block, REG_TEMP, src_reg, uop->imm_data);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_B(dest_size) && REG_IS_BH(src_size)) {
host_arm64_SUB_IMM(block, REG_TEMP, src_reg, uop->imm_data << 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 0, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size)) {
host_arm64_SUB_IMM(block, REG_TEMP, src_reg, uop->imm_data << 8);
host_arm64_MOV_REG_LSR(block, REG_TEMP, REG_TEMP, 8);
host_arm64_BFI(block, dest_reg, REG_TEMP, 8, 8);
} else
fatal("SUB_IMM %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
static int
codegen_TEST_JNS_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 31);
} else if (REG_IS_W(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 15);
} else if (REG_IS_B(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 7);
} else
fatal("TEST_JNS_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BEQ_(block);
return 0;
}
static int
codegen_TEST_JS_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 31);
} else if (REG_IS_W(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 15);
} else if (REG_IS_B(src_size)) {
host_arm64_TST_IMM(block, src_reg, 1 << 7);
} else
fatal("TEST_JS_DEST %02x\n", uop->src_reg_a_real);
uop->p = host_arm64_BNE_(block);
return 0;
}
static int
codegen_XOR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_arm64_EOR_REG_V(block, dest_reg, src_reg_a, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_arm64_EOR_REG(block, dest_reg, src_reg_a, src_reg_b, 0);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b) && dest_reg == src_reg_a) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_b, 0xffff);
host_arm64_EOR_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_b, 0xff);
host_arm64_EOR_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_UBFX(block, REG_TEMP, src_reg_b, 8, 8);
host_arm64_EOR_REG(block, dest_reg, src_reg_a, REG_TEMP, 0);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_B(src_size_b) && dest_reg == src_reg_a) {
host_arm64_AND_IMM(block, REG_TEMP, src_reg_b, 0xff);
host_arm64_EOR_REG(block, dest_reg, src_reg_a, REG_TEMP, 8);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size_a) && REG_IS_BH(src_size_b) && dest_reg == src_reg_a) {
host_arm64_UBFX(block, REG_TEMP, src_reg_b, 8, 8);
host_arm64_EOR_REG(block, dest_reg, src_reg_a, REG_TEMP, 8);
} else
fatal("XOR %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
return 0;
}
static int
codegen_XOR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_arm64_EOR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size) && dest_reg == src_reg) {
host_arm64_EOR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size) && dest_reg == src_reg) {
host_arm64_EOR_IMM(block, dest_reg, src_reg, uop->imm_data);
} else if (REG_IS_BH(dest_size) && REG_IS_BH(src_size) && dest_reg == src_reg) {
host_arm64_EOR_IMM(block, dest_reg, src_reg, uop->imm_data << 8);
} else
fatal("XOR_IMM %x %x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
return 0;
}
const uOpFn uop_handlers[UOP_MAX] = {
[UOP_CALL_FUNC & UOP_MASK] = codegen_CALL_FUNC,
[UOP_CALL_FUNC_RESULT &
UOP_MASK]
= codegen_CALL_FUNC_RESULT,
[UOP_CALL_INSTRUCTION_FUNC &
UOP_MASK]
= codegen_CALL_INSTRUCTION_FUNC,
[UOP_JMP &
UOP_MASK]
= codegen_JMP,
[UOP_LOAD_SEG &
UOP_MASK]
= codegen_LOAD_SEG,
[UOP_LOAD_FUNC_ARG_0 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG0,
[UOP_LOAD_FUNC_ARG_1 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG1,
[UOP_LOAD_FUNC_ARG_2 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG2,
[UOP_LOAD_FUNC_ARG_3 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG3,
[UOP_LOAD_FUNC_ARG_0_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG0_IMM,
[UOP_LOAD_FUNC_ARG_1_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG1_IMM,
[UOP_LOAD_FUNC_ARG_2_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG2_IMM,
[UOP_LOAD_FUNC_ARG_3_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG3_IMM,
[UOP_STORE_P_IMM &
UOP_MASK]
= codegen_STORE_PTR_IMM,
[UOP_STORE_P_IMM_8 &
UOP_MASK]
= codegen_STORE_PTR_IMM_8,
[UOP_MEM_LOAD_ABS &
UOP_MASK]
= codegen_MEM_LOAD_ABS,
[UOP_MEM_LOAD_REG &
UOP_MASK]
= codegen_MEM_LOAD_REG,
[UOP_MEM_LOAD_SINGLE &
UOP_MASK]
= codegen_MEM_LOAD_SINGLE,
[UOP_MEM_LOAD_DOUBLE &
UOP_MASK]
= codegen_MEM_LOAD_DOUBLE,
[UOP_MEM_STORE_ABS &
UOP_MASK]
= codegen_MEM_STORE_ABS,
[UOP_MEM_STORE_REG &
UOP_MASK]
= codegen_MEM_STORE_REG,
[UOP_MEM_STORE_IMM_8 &
UOP_MASK]
= codegen_MEM_STORE_IMM_8,
[UOP_MEM_STORE_IMM_16 &
UOP_MASK]
= codegen_MEM_STORE_IMM_16,
[UOP_MEM_STORE_IMM_32 &
UOP_MASK]
= codegen_MEM_STORE_IMM_32,
[UOP_MEM_STORE_SINGLE &
UOP_MASK]
= codegen_MEM_STORE_SINGLE,
[UOP_MEM_STORE_DOUBLE &
UOP_MASK]
= codegen_MEM_STORE_DOUBLE,
[UOP_MOV &
UOP_MASK]
= codegen_MOV,
[UOP_MOV_PTR &
UOP_MASK]
= codegen_MOV_PTR,
[UOP_MOV_IMM &
UOP_MASK]
= codegen_MOV_IMM,
[UOP_MOVSX &
UOP_MASK]
= codegen_MOVSX,
[UOP_MOVZX &
UOP_MASK]
= codegen_MOVZX,
[UOP_MOV_DOUBLE_INT &
UOP_MASK]
= codegen_MOV_DOUBLE_INT,
[UOP_MOV_INT_DOUBLE &
UOP_MASK]
= codegen_MOV_INT_DOUBLE,
[UOP_MOV_INT_DOUBLE_64 &
UOP_MASK]
= codegen_MOV_INT_DOUBLE_64,
[UOP_MOV_REG_PTR &
UOP_MASK]
= codegen_MOV_REG_PTR,
[UOP_MOVZX_REG_PTR_8 &
UOP_MASK]
= codegen_MOVZX_REG_PTR_8,
[UOP_MOVZX_REG_PTR_16 &
UOP_MASK]
= codegen_MOVZX_REG_PTR_16,
[UOP_ADD &
UOP_MASK]
= codegen_ADD,
[UOP_ADD_IMM &
UOP_MASK]
= codegen_ADD_IMM,
[UOP_ADD_LSHIFT &
UOP_MASK]
= codegen_ADD_LSHIFT,
[UOP_AND &
UOP_MASK]
= codegen_AND,
[UOP_AND_IMM &
UOP_MASK]
= codegen_AND_IMM,
[UOP_ANDN &
UOP_MASK]
= codegen_ANDN,
[UOP_OR &
UOP_MASK]
= codegen_OR,
[UOP_OR_IMM &
UOP_MASK]
= codegen_OR_IMM,
[UOP_SUB &
UOP_MASK]
= codegen_SUB,
[UOP_SUB_IMM &
UOP_MASK]
= codegen_SUB_IMM,
[UOP_XOR &
UOP_MASK]
= codegen_XOR,
[UOP_XOR_IMM &
UOP_MASK]
= codegen_XOR_IMM,
[UOP_SAR &
UOP_MASK]
= codegen_SAR,
[UOP_SAR_IMM &
UOP_MASK]
= codegen_SAR_IMM,
[UOP_SHL &
UOP_MASK]
= codegen_SHL,
[UOP_SHL_IMM &
UOP_MASK]
= codegen_SHL_IMM,
[UOP_SHR &
UOP_MASK]
= codegen_SHR,
[UOP_SHR_IMM &
UOP_MASK]
= codegen_SHR_IMM,
[UOP_ROL &
UOP_MASK]
= codegen_ROL,
[UOP_ROL_IMM &
UOP_MASK]
= codegen_ROL_IMM,
[UOP_ROR &
UOP_MASK]
= codegen_ROR,
[UOP_ROR_IMM &
UOP_MASK]
= codegen_ROR_IMM,
[UOP_CMP_IMM_JZ &
UOP_MASK]
= codegen_CMP_IMM_JZ,
[UOP_CMP_JB &
UOP_MASK]
= codegen_CMP_JB,
[UOP_CMP_JNBE &
UOP_MASK]
= codegen_CMP_JNBE,
[UOP_CMP_JNB_DEST &
UOP_MASK]
= codegen_CMP_JNB_DEST,
[UOP_CMP_JNBE_DEST &
UOP_MASK]
= codegen_CMP_JNBE_DEST,
[UOP_CMP_JNL_DEST &
UOP_MASK]
= codegen_CMP_JNL_DEST,
[UOP_CMP_JNLE_DEST &
UOP_MASK]
= codegen_CMP_JNLE_DEST,
[UOP_CMP_JNO_DEST &
UOP_MASK]
= codegen_CMP_JNO_DEST,
[UOP_CMP_JNZ_DEST &
UOP_MASK]
= codegen_CMP_JNZ_DEST,
[UOP_CMP_JB_DEST &
UOP_MASK]
= codegen_CMP_JB_DEST,
[UOP_CMP_JBE_DEST &
UOP_MASK]
= codegen_CMP_JBE_DEST,
[UOP_CMP_JL_DEST &
UOP_MASK]
= codegen_CMP_JL_DEST,
[UOP_CMP_JLE_DEST &
UOP_MASK]
= codegen_CMP_JLE_DEST,
[UOP_CMP_JO_DEST &
UOP_MASK]
= codegen_CMP_JO_DEST,
[UOP_CMP_JZ_DEST &
UOP_MASK]
= codegen_CMP_JZ_DEST,
[UOP_CMP_IMM_JNZ_DEST &
UOP_MASK]
= codegen_CMP_IMM_JNZ_DEST,
[UOP_CMP_IMM_JZ_DEST &
UOP_MASK]
= codegen_CMP_IMM_JZ_DEST,
[UOP_TEST_JNS_DEST &
UOP_MASK]
= codegen_TEST_JNS_DEST,
[UOP_TEST_JS_DEST &
UOP_MASK]
= codegen_TEST_JS_DEST,
[UOP_FP_ENTER &
UOP_MASK]
= codegen_FP_ENTER,
[UOP_MMX_ENTER &
UOP_MASK]
= codegen_MMX_ENTER,
[UOP_FADD &
UOP_MASK]
= codegen_FADD,
[UOP_FCOM &
UOP_MASK]
= codegen_FCOM,
[UOP_FDIV &
UOP_MASK]
= codegen_FDIV,
[UOP_FMUL &
UOP_MASK]
= codegen_FMUL,
[UOP_FSUB &
UOP_MASK]
= codegen_FSUB,
[UOP_FABS &
UOP_MASK]
= codegen_FABS,
[UOP_FCHS &
UOP_MASK]
= codegen_FCHS,
[UOP_FSQRT &
UOP_MASK]
= codegen_FSQRT,
[UOP_FTST &
UOP_MASK]
= codegen_FTST,
[UOP_PACKSSWB &
UOP_MASK]
= codegen_PACKSSWB,
[UOP_PACKSSDW &
UOP_MASK]
= codegen_PACKSSDW,
[UOP_PACKUSWB &
UOP_MASK]
= codegen_PACKUSWB,
[UOP_PADDB &
UOP_MASK]
= codegen_PADDB,
[UOP_PADDW &
UOP_MASK]
= codegen_PADDW,
[UOP_PADDD &
UOP_MASK]
= codegen_PADDD,
[UOP_PADDSB &
UOP_MASK]
= codegen_PADDSB,
[UOP_PADDSW &
UOP_MASK]
= codegen_PADDSW,
[UOP_PADDUSB &
UOP_MASK]
= codegen_PADDUSB,
[UOP_PADDUSW &
UOP_MASK]
= codegen_PADDUSW,
[UOP_PCMPEQB &
UOP_MASK]
= codegen_PCMPEQB,
[UOP_PCMPEQW &
UOP_MASK]
= codegen_PCMPEQW,
[UOP_PCMPEQD &
UOP_MASK]
= codegen_PCMPEQD,
[UOP_PCMPGTB &
UOP_MASK]
= codegen_PCMPGTB,
[UOP_PCMPGTW &
UOP_MASK]
= codegen_PCMPGTW,
[UOP_PCMPGTD &
UOP_MASK]
= codegen_PCMPGTD,
[UOP_PF2ID &
UOP_MASK]
= codegen_PF2ID,
[UOP_PFADD &
UOP_MASK]
= codegen_PFADD,
[UOP_PFCMPEQ &
UOP_MASK]
= codegen_PFCMPEQ,
[UOP_PFCMPGE &
UOP_MASK]
= codegen_PFCMPGE,
[UOP_PFCMPGT &
UOP_MASK]
= codegen_PFCMPGT,
[UOP_PFMAX &
UOP_MASK]
= codegen_PFMAX,
[UOP_PFMIN &
UOP_MASK]
= codegen_PFMIN,
[UOP_PFMUL &
UOP_MASK]
= codegen_PFMUL,
[UOP_PFRCP &
UOP_MASK]
= codegen_PFRCP,
[UOP_PFRSQRT &
UOP_MASK]
= codegen_PFRSQRT,
[UOP_PFSUB &
UOP_MASK]
= codegen_PFSUB,
[UOP_PI2FD &
UOP_MASK]
= codegen_PI2FD,
[UOP_PMADDWD &
UOP_MASK]
= codegen_PMADDWD,
[UOP_PMULHW &
UOP_MASK]
= codegen_PMULHW,
[UOP_PMULLW &
UOP_MASK]
= codegen_PMULLW,
[UOP_PSLLW_IMM &
UOP_MASK]
= codegen_PSLLW_IMM,
[UOP_PSLLD_IMM &
UOP_MASK]
= codegen_PSLLD_IMM,
[UOP_PSLLQ_IMM &
UOP_MASK]
= codegen_PSLLQ_IMM,
[UOP_PSRAW_IMM &
UOP_MASK]
= codegen_PSRAW_IMM,
[UOP_PSRAD_IMM &
UOP_MASK]
= codegen_PSRAD_IMM,
[UOP_PSRAQ_IMM &
UOP_MASK]
= codegen_PSRAQ_IMM,
[UOP_PSRLW_IMM &
UOP_MASK]
= codegen_PSRLW_IMM,
[UOP_PSRLD_IMM &
UOP_MASK]
= codegen_PSRLD_IMM,
[UOP_PSRLQ_IMM &
UOP_MASK]
= codegen_PSRLQ_IMM,
[UOP_PSUBB &
UOP_MASK]
= codegen_PSUBB,
[UOP_PSUBW &
UOP_MASK]
= codegen_PSUBW,
[UOP_PSUBD &
UOP_MASK]
= codegen_PSUBD,
[UOP_PSUBSB &
UOP_MASK]
= codegen_PSUBSB,
[UOP_PSUBSW &
UOP_MASK]
= codegen_PSUBSW,
[UOP_PSUBUSB &
UOP_MASK]
= codegen_PSUBUSB,
[UOP_PSUBUSW &
UOP_MASK]
= codegen_PSUBUSW,
[UOP_PUNPCKHBW &
UOP_MASK]
= codegen_PUNPCKHBW,
[UOP_PUNPCKHWD &
UOP_MASK]
= codegen_PUNPCKHWD,
[UOP_PUNPCKHDQ &
UOP_MASK]
= codegen_PUNPCKHDQ,
[UOP_PUNPCKLBW &
UOP_MASK]
= codegen_PUNPCKLBW,
[UOP_PUNPCKLWD &
UOP_MASK]
= codegen_PUNPCKLWD,
[UOP_PUNPCKLDQ &
UOP_MASK]
= codegen_PUNPCKLDQ,
[UOP_NOP_BARRIER &
UOP_MASK]
= codegen_NOP
};
void
codegen_direct_read_8(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_b((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDRB_IMM_W(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_8 - not in range\n");
}
void
codegen_direct_read_16(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_h((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDRH_IMM(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_16 - not in range\n");
}
void
codegen_direct_read_32(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_w((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDR_IMM_W(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_32 - not in range\n");
}
void
codegen_direct_read_64(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_double - not in range\n");
}
void
codegen_direct_read_pointer(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDR_IMM_X(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_pointer - not in range\n");
}
void
codegen_direct_read_double(codeblock_t *block, int host_reg, void *p)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_LDR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_read_double - not in range\n");
}
void
codegen_direct_read_st_8(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_LDRB_REG(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_read_st_64(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_LDR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_read_st_double(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_LDR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_write_8(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_b((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STRB_IMM(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_8 - not in range\n");
}
void
codegen_direct_write_16(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_h((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STRH_IMM(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_16 - not in range\n");
}
void
codegen_direct_write_32(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_w((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STR_IMM_W(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_32 - not in range\n");
}
void
codegen_direct_write_64(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_double - not in range\n");
}
void
codegen_direct_write_double(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STR_IMM_F64(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_double - not in range\n");
}
void
codegen_direct_write_st_8(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_STRB_REG(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_write_st_64(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_STR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_write_st_double(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
host_arm64_LDR_IMM_W(block, REG_TEMP, REG_XSP, IREG_TOP_diff_stack_offset);
host_arm64_ADD_IMM(block, REG_TEMP, REG_TEMP, reg_idx);
host_arm64_ADDX_IMM(block, REG_TEMP2, REG_CPUSTATE, (uintptr_t) base - (uintptr_t) &cpu_state);
host_arm64_AND_IMM(block, REG_TEMP, REG_TEMP, 7);
host_arm64_STR_REG_F64_S(block, host_reg, REG_TEMP2, REG_TEMP);
}
void
codegen_direct_write_ptr(codeblock_t *block, void *p, int host_reg)
{
if (in_range12_q((uintptr_t) p - (uintptr_t) &cpu_state))
host_arm64_STR_IMM_Q(block, host_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("codegen_direct_write_ptr - not in range\n");
}
void
codegen_direct_read_16_stack(codeblock_t *block, int host_reg, int stack_offset)
{
if (in_range12_h(stack_offset))
host_arm64_LDRH_IMM(block, host_reg, REG_XSP, stack_offset);
else
fatal("codegen_direct_read_32_stack - not in range\n");
}
void
codegen_direct_read_32_stack(codeblock_t *block, int host_reg, int stack_offset)
{
if (in_range12_w(stack_offset))
host_arm64_LDR_IMM_W(block, host_reg, REG_XSP, stack_offset);
else
fatal("codegen_direct_read_32_stack - not in range\n");
}
void
codegen_direct_read_pointer_stack(codeblock_t *block, int host_reg, int stack_offset)
{
if (in_range12_q(stack_offset))
host_arm64_LDR_IMM_X(block, host_reg, REG_XSP, stack_offset);
else
fatal("codegen_direct_read_pointer_stack - not in range\n");
}
void
codegen_direct_read_64_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_arm64_LDR_IMM_F64(block, host_reg, REG_XSP, stack_offset);
}
void
codegen_direct_read_double_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_arm64_LDR_IMM_F64(block, host_reg, REG_XSP, stack_offset);
}
void
codegen_direct_write_32_stack(codeblock_t *block, int stack_offset, int host_reg)
{
if (in_range12_w(stack_offset))
host_arm64_STR_IMM_W(block, host_reg, REG_XSP, stack_offset);
else
fatal("codegen_direct_write_32_stack - not in range\n");
}
void
codegen_direct_write_64_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_arm64_STR_IMM_F64(block, host_reg, REG_XSP, stack_offset);
}
void
codegen_direct_write_double_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_arm64_STR_IMM_F64(block, host_reg, REG_XSP, stack_offset);
}
void
codegen_set_jump_dest(codeblock_t *block, void *p)
{
host_arm64_branch_set_offset(p, &block_write_data[block_pos]);
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64_uops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 43,576 |
```objective-c
#include "codegen_backend_arm64_defs.h"
#define BLOCK_SIZE 0x4000
#define BLOCK_MASK 0x3fff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_MAX 0x3c0
void host_arm64_BLR(codeblock_t *block, int addr_reg);
void host_arm64_CBNZ(codeblock_t *block, int reg, uintptr_t dest);
void host_arm64_MOVK_IMM(codeblock_t *block, int reg, uint32_t imm_data);
void host_arm64_MOVZ_IMM(codeblock_t *block, int reg, uint32_t imm_data);
void host_arm64_LDP_POSTIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset);
void host_arm64_LDR_LITERAL_W(codeblock_t *block, int dest_reg, int literal_offset);
void host_arm64_LDR_LITERAL_X(codeblock_t *block, int dest_reg, int literal_offset);
void host_arm64_NOP(codeblock_t *block);
void host_arm64_RET(codeblock_t *block, int reg);
void host_arm64_STP_PREIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset);
void host_arm64_STR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_STRB_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_call(codeblock_t *block, void *dst_addr);
void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
uint32_t host_arm64_find_imm(uint32_t data);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 393 |
```objective-c
uint32_t ropPAND(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPANDN(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPOR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPXOR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_logic.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 169 |
```objective-c
void host_x86_ADDPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADDSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
#define CMPPS_EQ 0
#define CMPPS_NLT 5
#define CMPPS_NLE 6
void host_x86_CMPPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg, int type);
void host_x86_COMISD_XREG_XREG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CVTDQ2PS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTPS2DQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSD2SI_REG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSD2SS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSI2SD_XREG_REG(codeblock_t *block, int dest_reg, int src_reg);
void host_x86_CVTSI2SS_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSS2SD_XREG_XREG(codeblock_t *block, int dest_reg, int src_reg);
void host_x86_CVTSS2SD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_DIVSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_DIVSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_LDMXCSR(codeblock_t *block, void *p);
void host_x86_MAXSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVD_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVD_REG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_ABS_XREG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift, int src_reg);
void host_x86_MOVQ_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVQ_BASE_OFFSET_XREG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOVQ_STACK_OFFSET_XREG(codeblock_t *block, int offset, int src_reg);
void host_x86_MOVQ_XREG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOVQ_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVQ_XREG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOVQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MAXPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MINPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MULPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MULSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKSSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKSSDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKUSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PAND_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PANDN_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_POR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PXOR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMADDWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMULHW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMULLW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSLLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSLLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSLLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSHUFD_XREG_XREG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint8_t shuffle);
void host_x86_PSUBB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SQRTSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SQRTSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUBPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUBSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_UNPCKLPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops_sse.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,126 |
```objective-c
uint32_t ropFLDs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFLDd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTPs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTPd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFILDw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFILDl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFILDq(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTPw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTPl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTPq(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_loadstore.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 605 |
```objective-c
#ifndef _CODEGEN_H_
#define _CODEGEN_H_
#include <86box/mem.h>
#include <stddef.h>
#include "x86_ops.h"
/*Handling self-modifying code (of which there is a lot on x86) :
PCem tracks a 'dirty mask' for each physical page, in which each bit
represents 64 bytes. This is only tracked for pages that have code in - when a
page first has a codeblock generated, it is evicted from the writelookup and
added to the page_lookup for this purpose. When in the page_lookup, each write
will go through the mem_write_ram*_page() functions and set the dirty mask
appropriately.
Each codeblock also contains a code mask (actually two masks, one for each
page the block is/may be in), again with each bit representing 64 bytes.
Each page has a list of codeblocks present in it. As each codeblock can span
up to two pages, two lists are present.
When a codeblock is about to be executed, the code masks are compared with the
dirty masks for the relevant pages. If either intersect, then
codegen_check_flush() is called on the affected page(s), and all affected
blocks are evicted.
The 64 byte granularity appears to work reasonably well for most cases,
avoiding most unnecessary evictions (eg when code & data are stored in the
same page).
*/
typedef struct codeblock_t {
uint32_t pc;
uint32_t _cs;
uint32_t phys, phys_2;
uint16_t status;
uint16_t flags;
uint8_t ins;
uint8_t TOP;
/*Pointers for codeblock tree, used to search for blocks when hash lookup
fails.*/
uint16_t parent, left, right;
uint8_t *data;
uint64_t page_mask, page_mask2;
uint64_t *dirty_mask, *dirty_mask2;
/*Previous and next pointers, for the codeblock list associated with
each physical page. Two sets of pointers, as a codeblock can be
present in two pages.*/
uint16_t prev, next;
uint16_t prev_2, next_2;
/*First mem_block_t used by this block. Any subsequent mem_block_ts
will be in the list starting at head_mem_block->next.*/
struct mem_block_t *head_mem_block;
} codeblock_t;
extern codeblock_t *codeblock;
extern uint16_t *codeblock_hash;
extern uint8_t *block_write_data;
/*Code block uses FPU*/
#define CODEBLOCK_HAS_FPU 1
/*Code block is always entered with the same FPU top-of-stack*/
#define CODEBLOCK_STATIC_TOP 2
/*Code block has been compiled*/
#define CODEBLOCK_WAS_RECOMPILED 4
/*Code block is in free list and is not valid*/
#define CODEBLOCK_IN_FREE_LIST 8
/*Code block spans two pages, page_mask2 and dirty_mask2 are valid*/
#define CODEBLOCK_HAS_PAGE2 0x10
/*Code block is using a byte mask for code present and dirty*/
#define CODEBLOCK_BYTE_MASK 0x20
/*Code block is in dirty list*/
#define CODEBLOCK_IN_DIRTY_LIST 0x40
/*Code block is not inlining immediate parameters, parameters must be fetched from memory*/
#define CODEBLOCK_NO_IMMEDIATES 0x80
#define BLOCK_PC_INVALID 0xffffffff
#define BLOCK_INVALID 0
static inline int
get_block_nr(codeblock_t *block)
{
return ((uintptr_t) block - (uintptr_t) codeblock) / sizeof(codeblock_t);
}
static inline codeblock_t *
codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
codeblock_t *block;
uint64_t a = _cs | ((uint64_t) phys << 32);
if (!pages[phys >> 12].head)
return NULL;
block = &codeblock[pages[phys >> 12].head];
while (block) {
uint64_t block_cmp = block->_cs | ((uint64_t) block->phys << 32);
if (a == block_cmp) {
if (!((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) && ((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK)))
break;
}
if (a < block_cmp)
block = block->left ? &codeblock[block->left] : NULL;
else
block = block->right ? &codeblock[block->right] : NULL;
}
return block;
}
static inline void
codeblock_tree_add(codeblock_t *new_block)
{
codeblock_t *block = &codeblock[pages[new_block->phys >> 12].head];
uint64_t a = new_block->_cs | ((uint64_t) new_block->phys << 32);
if (!pages[new_block->phys >> 12].head) {
pages[new_block->phys >> 12].head = get_block_nr(new_block);
new_block->parent = new_block->left = new_block->right = BLOCK_INVALID;
} else {
codeblock_t *old_block = NULL;
uint64_t old_block_cmp = 0;
while (block) {
old_block = block;
old_block_cmp = old_block->_cs | ((uint64_t) old_block->phys << 32);
if (a < old_block_cmp)
block = block->left ? &codeblock[block->left] : NULL;
else
block = block->right ? &codeblock[block->right] : NULL;
}
if (old_block != NULL) {
if (a < old_block_cmp)
old_block->left = get_block_nr(new_block);
else
old_block->right = get_block_nr(new_block);
new_block->parent = get_block_nr(old_block);
} else
new_block->parent = BLOCK_INVALID;
new_block->left = new_block->right = BLOCK_INVALID;
}
}
static inline void
codeblock_tree_delete(codeblock_t *block)
{
uint16_t parent_nr = block->parent;
codeblock_t *parent;
if (block->parent)
parent = &codeblock[block->parent];
else
parent = NULL;
if (!block->left && !block->right) {
/*Easy case - remove from parent*/
if (!parent)
pages[block->phys >> 12].head = BLOCK_INVALID;
else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
parent->left = BLOCK_INVALID;
if (parent->right == block_nr)
parent->right = BLOCK_INVALID;
}
return;
} else if (!block->left) {
/*Only right node*/
if (!parent_nr) {
pages[block->phys >> 12].head = block->right;
codeblock[pages[block->phys >> 12].head].parent = BLOCK_INVALID;
} else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr) {
parent->left = block->right;
codeblock[parent->left].parent = parent_nr;
}
if (parent->right == block_nr) {
parent->right = block->right;
codeblock[parent->right].parent = parent_nr;
}
}
return;
} else if (!block->right) {
/*Only left node*/
if (!parent_nr) {
pages[block->phys >> 12].head = block->left;
codeblock[pages[block->phys >> 12].head].parent = BLOCK_INVALID;
} else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr) {
parent->left = block->left;
codeblock[parent->left].parent = parent_nr;
}
if (parent->right == block_nr) {
parent->right = block->left;
codeblock[parent->right].parent = parent_nr;
}
}
return;
} else {
/*Difficult case - node has two children. Walk right child to find lowest node*/
codeblock_t *lowest = &codeblock[block->right];
codeblock_t *highest;
codeblock_t *old_parent;
uint16_t lowest_nr;
while (lowest->left)
lowest = &codeblock[lowest->left];
lowest_nr = get_block_nr(lowest);
old_parent = &codeblock[lowest->parent];
/*Replace deleted node with lowest node*/
if (!parent_nr)
pages[block->phys >> 12].head = lowest_nr;
else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
parent->left = lowest_nr;
if (parent->right == block_nr)
parent->right = lowest_nr;
}
lowest->parent = parent_nr;
lowest->left = block->left;
if (lowest->left)
codeblock[lowest->left].parent = lowest_nr;
old_parent->left = BLOCK_INVALID;
highest = &codeblock[lowest->right];
if (!lowest->right) {
if (lowest_nr != block->right) {
lowest->right = block->right;
codeblock[block->right].parent = lowest_nr;
}
return;
}
while (highest->right)
highest = &codeblock[highest->right];
if (block->right && block->right != lowest_nr) {
highest->right = block->right;
codeblock[block->right].parent = get_block_nr(highest);
}
}
}
#define PAGE_MASK_MASK 63
#define PAGE_MASK_SHIFT 6
void codegen_mark_code_present_multibyte(codeblock_t *block, uint32_t start_pc, int len);
static inline void
codegen_mark_code_present(codeblock_t *block, uint32_t start_pc, int len)
{
if (len == 1) {
if (block->flags & CODEBLOCK_BYTE_MASK) {
if (!((start_pc ^ block->pc) & ~0x3f)) /*Starts in second page*/
block->page_mask |= ((uint64_t) 1 << (start_pc & PAGE_MASK_MASK));
else
block->page_mask2 |= ((uint64_t) 1 << (start_pc & PAGE_MASK_MASK));
} else {
if (!((start_pc ^ block->pc) & ~0xfff)) /*Starts in second page*/
block->page_mask |= ((uint64_t) 1 << ((start_pc >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK));
else
block->page_mask2 |= ((uint64_t) 1 << ((start_pc >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK));
}
} else
codegen_mark_code_present_multibyte(block, start_pc, len);
}
extern void codegen_init(void);
extern void codegen_reset(void);
extern void codegen_block_init(uint32_t phys_addr);
extern void codegen_block_remove(void);
extern void codegen_block_start_recompile(codeblock_t *block);
extern void codegen_block_end_recompile(codeblock_t *block);
extern void codegen_block_end(void);
extern void codegen_delete_block(codeblock_t *block);
extern void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_pc, uint32_t old_pc);
extern void codegen_generate_seg_restore(void);
extern void codegen_set_op32(void);
extern void codegen_flush(void);
extern void codegen_check_flush(struct page_t *page, uint64_t mask, uint32_t phys_addr);
struct ir_data_t;
x86seg *codegen_generate_ea(struct ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, uint32_t op_32, int stack_offset);
extern void codegen_check_seg_read(codeblock_t *block, struct ir_data_t *ir, x86seg *seg);
extern void codegen_check_seg_write(codeblock_t *block, struct ir_data_t *ir, x86seg *seg);
extern int codegen_purge_purgable_list(void);
/*Delete a random code block to free memory. This is obviously quite expensive, and
will only be called when the allocator is out of memory*/
extern void codegen_delete_random_block(int required_mem_block);
extern int cpu_block_end;
extern uint32_t codegen_endpc;
extern int cpu_reps;
extern int cpu_notreps;
extern int codegen_block_cycles;
extern void (*codegen_timing_start)(void);
extern void (*codegen_timing_prefix)(uint8_t prefix, uint32_t fetchdat);
extern void (*codegen_timing_opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
extern void (*codegen_timing_block_start)(void);
extern void (*codegen_timing_block_end)(void);
extern int (*codegen_timing_jump_cycles)(void);
typedef struct codegen_timing_t {
void (*start)(void);
void (*prefix)(uint8_t prefix, uint32_t fetchdat);
void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);
void (*block_start)(void);
void (*block_end)(void);
int (*jump_cycles)(void);
} codegen_timing_t;
extern codegen_timing_t codegen_timing_pentium;
extern codegen_timing_t codegen_timing_686;
extern codegen_timing_t codegen_timing_486;
extern codegen_timing_t codegen_timing_winchip;
extern codegen_timing_t codegen_timing_winchip2;
extern codegen_timing_t codegen_timing_k5;
extern codegen_timing_t codegen_timing_k6;
extern codegen_timing_t codegen_timing_p6;
void codegen_timing_set(codegen_timing_t *timing);
extern int block_current;
extern int block_pos;
#define CPU_BLOCK_END() cpu_block_end = 1
/*Current physical page of block being recompiled. -1 if no recompilation taking place */
extern uint32_t recomp_page;
extern x86seg *op_ea_seg;
extern int op_ssegs;
extern uint32_t op_old_pc;
/*Set to 1 if flags have been changed in the block being recompiled, and hence
flags_op is known and can be relied on */
extern int codegen_flags_changed;
extern int codegen_fpu_entered;
extern int codegen_mmx_entered;
extern int codegen_fpu_loaded_iq[8];
extern int codegen_reg_loaded[8];
extern int codegen_in_recompile;
void codegen_generate_reset(void);
int codegen_get_instruction_uop(codeblock_t *block, uint32_t pc, int *first_instruction, int *TOP);
void codegen_set_loop_start(struct ir_data_t *ir, int first_instruction);
#ifdef DEBUG_EXTRA
extern uint32_t instr_counts[256 * 256];
#endif
#endif
``` | /content/code_sandbox/src/codegen_new/codegen.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,267 |
```objective-c
#include "codegen_backend_arm_defs.h"
#define BLOCK_SIZE 0x4000
#define BLOCK_MASK 0x3fff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_MAX 0x3c0
void host_arm_ADD_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_LDMIA_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask);
void host_arm_LDR_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset);
void host_arm_MOV_IMM(codeblock_t *block, int dst_reg, uint32_t imm);
void host_arm_STMDB_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask);
void host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_call(codeblock_t *block, void *dst_addr);
void host_arm_nop(codeblock_t *block);
void codegen_alloc(codeblock_t *block, int size);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 257 |
```c
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_arm_defs.h"
# include "codegen_backend_arm_ops.h"
# define Rm(x) (x)
# define Rs(x) ((x) << 8)
# define Rd(x) ((x) << 12)
# define Rt(x) ((x) << 12)
# define Rn(x) ((x) << 16)
# define Rt2(x) ((x) << 16)
# define Vm(x) (x)
# define Vd(x) ((x) << 12)
# define Vn(x) ((x) << 16)
# define DATA_OFFSET_UP (1 << 23)
# define DATA_OFFSET_DOWN (0 << 23)
# define OPCODE_SHIFT 20
# define OPCODE_ADD_IMM (0x28 << OPCODE_SHIFT)
# define OPCODE_ADD_REG (0x08 << OPCODE_SHIFT)
# define OPCODE_AND_IMM (0x20 << OPCODE_SHIFT)
# define OPCODE_AND_REG (0x00 << OPCODE_SHIFT)
# define OPCODE_B (0xa0 << OPCODE_SHIFT)
# define OPCODE_BIC_IMM (0x3c << OPCODE_SHIFT)
# define OPCODE_BIC_REG (0x1c << OPCODE_SHIFT)
# define OPCODE_BL (0xb0 << OPCODE_SHIFT)
# define OPCODE_CMN_IMM (0x37 << OPCODE_SHIFT)
# define OPCODE_CMN_REG (0x17 << OPCODE_SHIFT)
# define OPCODE_CMP_IMM (0x35 << OPCODE_SHIFT)
# define OPCODE_CMP_REG (0x15 << OPCODE_SHIFT)
# define OPCODE_EOR_IMM (0x22 << OPCODE_SHIFT)
# define OPCODE_EOR_REG (0x02 << OPCODE_SHIFT)
# define OPCODE_LDMIA_WB (0x8b << OPCODE_SHIFT)
# define OPCODE_LDR_IMM (0x51 << OPCODE_SHIFT)
# define OPCODE_LDR_IMM_POST (0x41 << OPCODE_SHIFT)
# define OPCODE_LDR_REG (0x79 << OPCODE_SHIFT)
# define OPCODE_LDRB_IMM (0x55 << OPCODE_SHIFT)
# define OPCODE_LDRB_REG (0x7d << OPCODE_SHIFT)
# define OPCODE_MOV_IMM (0x3a << OPCODE_SHIFT)
# define OPCODE_MOVT_IMM (0x34 << OPCODE_SHIFT)
# define OPCODE_MOVW_IMM (0x30 << OPCODE_SHIFT)
# define OPCODE_MOV_REG (0x1a << OPCODE_SHIFT)
# define OPCODE_MVN_REG (0x1e << OPCODE_SHIFT)
# define OPCODE_ORR_IMM (0x38 << OPCODE_SHIFT)
# define OPCODE_ORR_REG (0x18 << OPCODE_SHIFT)
# define OPCODE_RSB_IMM (0x26 << OPCODE_SHIFT)
# define OPCODE_RSB_REG (0x06 << OPCODE_SHIFT)
# define OPCODE_STMDB_WB (0x92 << OPCODE_SHIFT)
# define OPCODE_STR_IMM (0x50 << OPCODE_SHIFT)
# define OPCODE_STR_IMM_WB (0x52 << OPCODE_SHIFT)
# define OPCODE_STR_REG (0x78 << OPCODE_SHIFT)
# define OPCODE_STRB_IMM (0x54 << OPCODE_SHIFT)
# define OPCODE_STRB_REG (0x7c << OPCODE_SHIFT)
# define OPCODE_SUB_IMM (0x24 << OPCODE_SHIFT)
# define OPCODE_SUB_REG (0x04 << OPCODE_SHIFT)
# define OPCODE_TST_IMM (0x31 << OPCODE_SHIFT)
# define OPCODE_TST_REG (0x11 << OPCODE_SHIFT)
# define OPCODE_BFI 0xe7c00010
# define OPCODE_BLX 0xe12fff30
# define OPCODE_BX 0xe12fff10
# define OPCODE_LDRH_IMM 0xe1d000b0
# define OPCODE_LDRH_REG 0xe19000b0
# define OPCODE_STRH_IMM 0xe1c000b0
# define OPCODE_STRH_REG 0xe18000b0
# define OPCODE_SXTB 0xe6af0070
# define OPCODE_SXTH 0xe6bf0070
# define OPCODE_UADD8 0xe6500f90
# define OPCODE_UADD16 0xe6500f10
# define OPCODE_USUB8 0xe6500ff0
# define OPCODE_USUB16 0xe6500f70
# define OPCODE_UXTB 0xe6ef0070
# define OPCODE_UXTH 0xe6ff0070
# define OPCODE_VABS_D 0xeeb00bc0
# define OPCODE_VADD 0xee300b00
# define OPCODE_VADD_I8 0xf2000800
# define OPCODE_VADD_I16 0xf2100800
# define OPCODE_VADD_I32 0xf2200800
# define OPCODE_VADD_F32 0xf2000d00
# define OPCODE_VAND_D 0xf2000110
# define OPCODE_VBIC_D 0xf2100110
# define OPCODE_VCEQ_F32 0xf2000e00
# define OPCODE_VCEQ_I8 0xf3000810
# define OPCODE_VCEQ_I16 0xf3100810
# define OPCODE_VCEQ_I32 0xf3200810
# define OPCODE_VCGE_F32 0xf3000e00
# define OPCODE_VCGT_F32 0xf3200e00
# define OPCODE_VCGT_S8 0xf2000300
# define OPCODE_VCGT_S16 0xf2100300
# define OPCODE_VCGT_S32 0xf2200300
# define OPCODE_VCMP_D 0xeeb40b40
# define OPCODE_VCVT_D_IS 0xeeb80bc0
# define OPCODE_VCVT_D_S 0xeeb70ac0
# define OPCODE_VCVT_F32_S32 0xf3bb0700
# define OPCODE_VCVT_IS_D 0xeebd0bc0
# define OPCODE_VCVT_S32_F32 0xf3bb0600
# define OPCODE_VCVT_S_D 0xeeb70bc0
# define OPCODE_VCVTR_IS_D 0xeebd0b40
# define OPCODE_VDIV 0xee800b00
# define OPCODE_VDIV_S 0xee800a00
# define OPCODE_VDUP_32 0xf3b40c00
# define OPCODE_VEOR_D 0xf3000110
# define OPCODE_VLDR_D 0xed900b00
# define OPCODE_VLDR_S 0xed900a00
# define OPCODE_VMAX_F32 0xf200f00
# define OPCODE_VMIN_F32 0xf220f00
# define OPCODE_VMOV_32_S 0xee100a10
# define OPCODE_VMOV_64_D 0xec500b10
# define OPCODE_VMOV_D_64 0xec400b10
# define OPCODE_VMOV_S_32 0xee000a10
# define OPCODE_VMOV_D_D 0xeeb00b40
# define OPCODE_VMOVN_I32 0xf3b60200
# define OPCODE_VMOVN_I64 0xf3ba0200
# define OPCODE_VMOV_F32_ONE 0xf2870f10
# define OPCODE_VMRS_APSR 0xeef1fa10
# define OPCODE_VMSR_FPSCR 0xeee10a10
# define OPCODE_VMUL 0xee200b00
# define OPCODE_VMUL_F32 0xf3000d10
# define OPCODE_VMUL_S16 0xf2100910
# define OPCODE_VMULL_S16 0xf2900c00
# define OPCODE_VNEG_D 0xeeb10b40
# define OPCODE_VORR_D 0xf2200110
# define OPCODE_VPADDL_S16 0xf3b40200
# define OPCODE_VPADDL_S32 0xf3b80200
# define OPCODE_VPADDL_Q_S32 0xf3b80240
# define OPCODE_VQADD_S8 0xf2000010
# define OPCODE_VQADD_S16 0xf2100010
# define OPCODE_VQADD_U8 0xf3000010
# define OPCODE_VQADD_U16 0xf3100010
# define OPCODE_VQMOVN_S16 0xf3b20280
# define OPCODE_VQMOVN_S32 0xf3b60280
# define OPCODE_VQMOVN_U16 0xf3b202c0
# define OPCODE_VQSUB_S8 0xf2000210
# define OPCODE_VQSUB_S16 0xf2100210
# define OPCODE_VQSUB_U8 0xf3000210
# define OPCODE_VQSUB_U16 0xf3100210
# define OPCODE_VSHL_D_IMM_16 0xf2900510
# define OPCODE_VSHL_D_IMM_32 0xf2a00510
# define OPCODE_VSHL_D_IMM_64 0xf2800590
# define OPCODE_VSHR_D_S16 0xf2900010
# define OPCODE_VSHR_D_S32 0xf2a00010
# define OPCODE_VSHR_D_S64 0xf2800090
# define OPCODE_VSHR_D_U16 0xf3900010
# define OPCODE_VSHR_D_U32 0xf3a00010
# define OPCODE_VSHR_D_U64 0xf3800090
# define OPCODE_VSHRN 0xf2800810
# define OPCODE_VSQRT_D 0xeeb10bc0
# define OPCODE_VSQRT_S 0xeeb10ac0
# define OPCODE_VSTR_D 0xed800b00
# define OPCODE_VSTR_S 0xed800a00
# define OPCODE_VSUB 0xee300b40
# define OPCODE_VSUB_I8 0xf3000800
# define OPCODE_VSUB_I16 0xf3100800
# define OPCODE_VSUB_I32 0xf3200800
# define OPCODE_VSUB_F32 0xf3000d00
# define OPCODE_VZIP_D8 0xf3b20180
# define OPCODE_VZIP_D16 0xf3b60180
# define OPCODE_VZIP_D32 0xf3ba0080
# define B_OFFSET(x) (((x) >> 2) & 0xffffff)
# define SHIFT_TYPE_SHIFT 5
# define SHIFT_TYPE_LSL (0 << SHIFT_TYPE_SHIFT)
# define SHIFT_TYPE_LSR (1 << SHIFT_TYPE_SHIFT)
# define SHIFT_TYPE_ASR (2 << SHIFT_TYPE_SHIFT)
# define SHIFT_TYPE_ROR (3 << SHIFT_TYPE_SHIFT)
# define SHIFT_TYPE_IMM (0 << 4)
# define SHIFT_TYPE_REG (1 << 4)
# define SHIFT_IMM_SHIFT 7
# define SHIFT_ASR_IMM(x) (SHIFT_TYPE_ASR | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
# define SHIFT_LSL_IMM(x) (SHIFT_TYPE_LSL | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
# define SHIFT_LSR_IMM(x) (SHIFT_TYPE_LSR | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
# define SHIFT_ROR_IMM(x) (SHIFT_TYPE_ROR | SHIFT_TYPE_IMM | ((x) << SHIFT_IMM_SHIFT))
# define SHIFT_ASR_REG(x) (SHIFT_TYPE_ASR | SHIFT_TYPE_REG | Rs(x))
# define SHIFT_LSL_REG(x) (SHIFT_TYPE_LSL | SHIFT_TYPE_REG | Rs(x))
# define SHIFT_LSR_REG(x) (SHIFT_TYPE_LSR | SHIFT_TYPE_REG | Rs(x))
# define SHIFT_ROR_REG(x) (SHIFT_TYPE_ROR | SHIFT_TYPE_REG | Rs(x))
# define BFI_lsb(lsb) ((lsb) << 7)
# define BFI_msb(msb) ((msb) << 16)
# define UXTB_ROTATE(rotate) (((rotate) >> 3) << 10)
# define MOVT_IMM(imm) (((imm) &0xfff) | (((imm) &0xf000) << 4))
# define MOVW_IMM(imm) (((imm) &0xfff) | (((imm) &0xf000) << 4))
# define LDRH_IMM(imm) (((imm) &0xf) | (((imm) &0xf0) << 4))
# define STRH_IMM(imm) LDRH_IMM(imm)
# define VSHIFT_IMM(shift) ((shift) << 16)
# define VSHIFT_IMM_32(shift) (((16 - (shift)) | 0x10) << 16)
# define VDUP_32_IMM(imm) ((imm) << 19)
static void codegen_allocate_new_block(codeblock_t *block);
static inline void
codegen_addlong(codeblock_t *block, uint32_t val)
{
if (block_pos >= (BLOCK_MAX - 4))
codegen_allocate_new_block(block);
*(uint32_t *) &block_write_data[block_pos] = val;
block_pos += 4;
}
static void
codegen_allocate_new_block(codeblock_t *block)
{
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
uint32_t offset = ((uintptr_t) new_ptr - (uintptr_t) &block_write_data[block_pos]) - 8;
/*Add a jump instruction to the new block*/
*(uint32_t *) &block_write_data[block_pos] = COND_AL | OPCODE_B | B_OFFSET(offset);
/*Set write address to start of new block*/
block_pos = 0;
block_write_data = new_ptr;
}
static inline void
codegen_alloc_4(codeblock_t *block)
{
if (block_pos >= (BLOCK_MAX - 4))
codegen_allocate_new_block(block);
}
void
codegen_alloc(codeblock_t *block, int size)
{
if (block_pos >= (BLOCK_MAX - size))
codegen_allocate_new_block(block);
}
static inline uint32_t
arm_data_offset(int offset)
{
if (offset < -0xffc || offset > 0xffc)
fatal("arm_data_offset out of range - %i\n", offset);
if (offset >= 0)
return offset | DATA_OFFSET_UP;
return (-offset) | DATA_OFFSET_DOWN;
}
static inline int
get_arm_imm(uint32_t imm_data, uint32_t *arm_imm)
{
int shift = 0;
if (!(imm_data & 0xffff)) {
shift += 16;
imm_data >>= 16;
}
if (!(imm_data & 0xff)) {
shift += 8;
imm_data >>= 8;
}
if (!(imm_data & 0xf)) {
shift += 4;
imm_data >>= 4;
}
if (!(imm_data & 0x3)) {
shift += 2;
imm_data >>= 2;
}
if (imm_data > 0xff) /*Note - should handle rotation round the word*/
return 0;
*arm_imm = imm_data | ((((32 - shift) >> 1) & 15) << 8);
return 1;
}
static inline int
in_range(void *addr, void *base)
{
int diff = (uintptr_t) addr - (uintptr_t) base;
if (diff < -4095 || diff > 4095)
return 0;
return 1;
}
void host_arm_ADD_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_EOR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
# if 0
void host_arm_ORR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
# endif
void host_arm_SUB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void
host_arm_ADD_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if ((int32_t) imm < 0 && imm != 0x80000000) {
host_arm_SUB_IMM(block, dst_reg, src_reg, -(int32_t) imm);
} else if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_ADD_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_ADD_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_ADD_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_ADD_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_ADD_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_ADD_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void
host_arm_AND_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_AND_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else if (get_arm_imm(~imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_BIC_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_AND_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_AND_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_AND_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_AND_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void
host_arm_B(codeblock_t *block, uintptr_t dest_addr)
{
uint32_t offset;
codegen_alloc_4(block);
offset = (dest_addr - (uintptr_t) &block_write_data[block_pos]) - 8;
if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000) {
host_arm_MOV_IMM(block, REG_R3, dest_addr);
host_arm_BX(block, REG_R3);
} else
codegen_addlong(block, COND_AL | OPCODE_B | B_OFFSET(offset));
}
void
host_arm_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width)
{
codegen_addlong(block, OPCODE_BFI | Rd(dst_reg) | Rm(src_reg) | BFI_lsb(lsb) | BFI_msb((lsb + width) - 1));
}
void
host_arm_BIC_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_BIC_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else if (get_arm_imm(~imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_AND_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_BIC_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_BIC_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_BIC_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_BIC_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_BIC_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void
host_arm_BL(codeblock_t *block, uintptr_t dest_addr)
{
uint32_t offset;
codegen_alloc_4(block);
offset = (dest_addr - (uintptr_t) &block_write_data[block_pos]) - 8;
if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000) {
host_arm_MOV_IMM(block, REG_R3, dest_addr);
host_arm_BLX(block, REG_R3);
} else
codegen_addlong(block, COND_AL | OPCODE_BL | B_OFFSET(offset));
}
void
host_arm_BL_r1(codeblock_t *block, uintptr_t dest_addr)
{
uint32_t offset;
codegen_alloc_4(block);
offset = (dest_addr - (uintptr_t) &block_write_data[block_pos]) - 8;
if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000) {
host_arm_MOV_IMM(block, REG_R1, dest_addr);
host_arm_BLX(block, REG_R1);
} else
codegen_addlong(block, COND_AL | OPCODE_BL | B_OFFSET(offset));
}
void
host_arm_BLX(codeblock_t *block, int addr_reg)
{
codegen_addlong(block, OPCODE_BLX | Rm(addr_reg));
}
uint32_t *
host_arm_BCC_(codeblock_t *block)
{
codegen_addlong(block, COND_CC | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BCS_(codeblock_t *block)
{
codegen_addlong(block, COND_CS | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BEQ_(codeblock_t *block)
{
codegen_addlong(block, COND_EQ | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BGE_(codeblock_t *block)
{
codegen_addlong(block, COND_GE | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BGT_(codeblock_t *block)
{
codegen_addlong(block, COND_GT | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BHI_(codeblock_t *block)
{
codegen_addlong(block, COND_HI | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BLE_(codeblock_t *block)
{
codegen_addlong(block, COND_LE | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BLS_(codeblock_t *block)
{
codegen_addlong(block, COND_LS | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BLT_(codeblock_t *block)
{
codegen_addlong(block, COND_LT | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BMI_(codeblock_t *block)
{
codegen_addlong(block, COND_MI | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BNE_(codeblock_t *block)
{
codegen_addlong(block, COND_NE | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BPL_(codeblock_t *block)
{
codegen_addlong(block, COND_PL | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BVC_(codeblock_t *block)
{
codegen_addlong(block, COND_VC | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_arm_BVS_(codeblock_t *block)
{
codegen_addlong(block, COND_VS | OPCODE_B);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_arm_BEQ(codeblock_t *block, uintptr_t dest_addr)
{
uint32_t offset;
codegen_alloc_4(block);
offset = (dest_addr - (uintptr_t) &block_write_data[block_pos]) - 8;
if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
fatal("host_arm_BEQ - out of range %08x %i\n", offset, offset);
codegen_addlong(block, COND_EQ | OPCODE_B | B_OFFSET(offset));
}
void
host_arm_BNE(codeblock_t *block, uintptr_t dest_addr)
{
uint32_t offset;
codegen_alloc_4(block);
offset = (dest_addr - (uintptr_t) &block_write_data[block_pos]) - 8;
if ((offset & 0xfe000000) && (offset & 0xfe000000) != 0xfe000000)
fatal("host_arm_BNE - out of range %08x %i\n", offset, offset);
codegen_addlong(block, COND_NE | OPCODE_B | B_OFFSET(offset));
}
void
host_arm_BX(codeblock_t *block, int addr_reg)
{
codegen_addlong(block, OPCODE_BLX | Rm(addr_reg));
}
void
host_arm_CMN_IMM(codeblock_t *block, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if ((int32_t) imm < 0 && imm != 0x80000000) {
host_arm_CMP_IMM(block, src_reg, -(int32_t) imm);
} else if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_CMN_IMM | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_CMN_REG_LSL(block, src_reg, REG_TEMP, 0);
}
}
void
host_arm_CMN_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_CMN_REG | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_CMP_IMM(codeblock_t *block, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if ((int32_t) imm < 0 && imm != 0x80000000) {
host_arm_CMN_IMM(block, src_reg, -(int32_t) imm);
} else if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_CMP_IMM | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_CMP_REG_LSL(block, src_reg, REG_TEMP, 0);
}
}
void
host_arm_CMP_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_CMP_REG | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_EOR_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_EOR_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_EOR_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_EOR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_EOR_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_LDMIA_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
{
codegen_addlong(block, COND_AL | OPCODE_LDMIA_WB | Rn(addr_reg) | reg_mask);
}
void
host_arm_LDR_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_LDR_IMM | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
}
void
host_arm_LDR_IMM_POST(codeblock_t *block, int dst_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_LDR_IMM_POST | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
}
void
host_arm_LDR_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_LDR_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_LDRB_ABS(codeblock_t *block, int dst_reg, void *p)
{
if (in_range(p, &cpu_state))
host_arm_LDRB_IMM(block, dst_reg, REG_CPUSTATE, (uintptr_t) p - (uintptr_t) &cpu_state);
else
fatal("LDRB_ABS - not in range\n");
}
void
host_arm_LDRB_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_LDRB_IMM | Rn(addr_reg) | Rd(dst_reg) | arm_data_offset(offset));
}
void
host_arm_LDRB_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_LDRB_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_LDRH_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_LDRH_IMM | Rn(addr_reg) | Rd(dst_reg) | LDRH_IMM(offset));
}
void
host_arm_LDRH_REG(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg)
{
codegen_addlong(block, COND_AL | OPCODE_LDRH_REG | Rn(addr_reg) | Rd(dst_reg) | Rm(offset_reg));
}
void
host_arm_MOV_IMM(codeblock_t *block, int dst_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_MOV_IMM | Rd(dst_reg) | arm_imm);
} else {
host_arm_MOVW_IMM(block, dst_reg, imm & 0xffff);
if (imm >> 16)
host_arm_MOVT_IMM(block, dst_reg, imm >> 16);
}
}
void
host_arm_MOV_REG_ASR(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_ASR_IMM(shift));
}
void
host_arm_MOV_REG_ASR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_ASR_REG(shift_reg));
}
void
host_arm_MOV_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_MOV_REG_LSL_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSL_REG(shift_reg));
}
void
host_arm_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSR_IMM(shift));
}
void
host_arm_MOV_REG_LSR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSR_REG(shift_reg));
}
void
host_arm_MOV_REG_ROR(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_ROR_IMM(shift));
}
void
host_arm_MOV_REG_ROR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg)
{
codegen_addlong(block, COND_AL | OPCODE_MOV_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_ROR_REG(shift_reg));
}
void
host_arm_MOVT_IMM(codeblock_t *block, int dst_reg, uint16_t imm)
{
codegen_addlong(block, COND_AL | OPCODE_MOVT_IMM | Rd(dst_reg) | MOVT_IMM(imm));
}
void
host_arm_MOVW_IMM(codeblock_t *block, int dst_reg, uint16_t imm)
{
codegen_addlong(block, COND_AL | OPCODE_MOVW_IMM | Rd(dst_reg) | MOVW_IMM(imm));
}
void
host_arm_MVN_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_MVN_REG | Rd(dst_reg) | Rm(src_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_ORR_IMM_cond(codeblock_t *block, uint32_t cond, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, cond | OPCODE_ORR_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_ORR_REG_LSL_cond(block, cond, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_ORR_REG_LSL_cond(codeblock_t *block, uint32_t cond, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, cond | OPCODE_ORR_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_RSB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_RSB_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_RSB_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_RSB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_RSB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_RSB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_RSB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void
host_arm_STMDB_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask)
{
codegen_addlong(block, COND_AL | OPCODE_STMDB_WB | Rn(addr_reg) | reg_mask);
}
void
host_arm_STR_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_STR_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
}
void
host_arm_STR_IMM_WB(codeblock_t *block, int src_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_STR_IMM_WB | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
}
void
host_arm_STR_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_STR_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_STRB_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_STRB_IMM | Rn(addr_reg) | Rd(src_reg) | arm_data_offset(offset));
}
void
host_arm_STRB_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_STRB_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg) | SHIFT_LSL_IMM(shift));
}
void
host_arm_STRH_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset)
{
codegen_addlong(block, COND_AL | OPCODE_STRH_IMM | Rn(addr_reg) | Rd(dst_reg) | STRH_IMM(offset));
}
void
host_arm_STRH_REG(codeblock_t *block, int src_reg, int addr_reg, int offset_reg)
{
codegen_addlong(block, COND_AL | OPCODE_STRH_REG | Rn(addr_reg) | Rd(src_reg) | Rm(offset_reg));
}
void
host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if ((int32_t) imm < 0 && imm != 0x80000000) {
host_arm_ADD_IMM(block, dst_reg, src_reg, -(int32_t) imm);
} else if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_SUB_IMM | Rd(dst_reg) | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_SUB_REG_LSL(block, dst_reg, src_reg, REG_TEMP, 0);
}
}
void
host_arm_SUB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_SUB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSL_IMM(shift));
}
void
host_arm_SUB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift)
{
codegen_addlong(block, COND_AL | OPCODE_SUB_REG | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m) | SHIFT_LSR_IMM(shift));
}
void
host_arm_SXTB(codeblock_t *block, int dst_reg, int src_reg, int rotate)
{
codegen_addlong(block, OPCODE_SXTB | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
}
void
host_arm_SXTH(codeblock_t *block, int dst_reg, int src_reg, int rotate)
{
codegen_addlong(block, OPCODE_SXTH | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
}
void
host_arm_TST_IMM(codeblock_t *block, int src_reg, uint32_t imm)
{
uint32_t arm_imm;
if (get_arm_imm(imm, &arm_imm)) {
codegen_addlong(block, COND_AL | OPCODE_TST_IMM | Rn(src_reg) | arm_imm);
} else {
host_arm_MOV_IMM(block, REG_TEMP, imm);
host_arm_TST_REG(block, src_reg, REG_TEMP);
}
}
void
host_arm_TST_REG(codeblock_t *block, int src_reg1, int src_reg2)
{
codegen_addlong(block, COND_AL | OPCODE_TST_REG | Rn(src_reg1) | Rm(src_reg2));
}
void
host_arm_UADD8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
codegen_addlong(block, COND_AL | OPCODE_UADD8 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
}
void
host_arm_UADD16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
codegen_addlong(block, COND_AL | OPCODE_UADD16 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
}
void
host_arm_USUB8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
codegen_addlong(block, COND_AL | OPCODE_USUB8 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
}
void
host_arm_USUB16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
codegen_addlong(block, COND_AL | OPCODE_USUB16 | Rd(dst_reg) | Rn(src_reg_a) | Rm(src_reg_b));
}
void
host_arm_UXTB(codeblock_t *block, int dst_reg, int src_reg, int rotate)
{
codegen_addlong(block, OPCODE_UXTB | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
}
void
host_arm_UXTH(codeblock_t *block, int dst_reg, int src_reg, int rotate)
{
codegen_addlong(block, OPCODE_UXTH | Rd(dst_reg) | Rm(src_reg) | UXTB_ROTATE(rotate));
}
void
host_arm_VABS_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VABS_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VADD_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VADD | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VADD_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VADD_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VADD_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VADD_I8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VADD_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VADD_I16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VADD_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VADD_I32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VAND_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VAND_D | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VBIC_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VBIC_D | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCMP_D(codeblock_t *block, int src_reg_d, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VCMP_D | Rd(src_reg_d) | Rm(src_reg_m));
}
void
host_arm_VCEQ_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCEQ_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCEQ_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCEQ_I8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCEQ_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCEQ_I16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCEQ_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCEQ_I32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCGE_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCGE_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCGT_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCGT_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCGT_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCGT_S8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCGT_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCGT_S16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCGT_S32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VCGT_S32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VCVT_D_IS(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_D_IS | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVT_D_S(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_D_S | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVT_F32_S32(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_F32_S32 | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVT_IS_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_IS_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVT_S32_F32(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_S32_F32 | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVT_S_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVT_S_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VCVTR_IS_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VCVTR_IS_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VDIV_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VDIV | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VDIV_S(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VDIV_S | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VDUP_32(codeblock_t *block, int dst_reg, int src_reg_m, int imm)
{
codegen_addlong(block, COND_AL | OPCODE_VDUP_32 | Rd(dst_reg) | Rm(src_reg_m) | VDUP_32_IMM(imm));
}
void
host_arm_VEOR_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VEOR_D | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VLDR_D(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if ((offset > 1020) || (offset & 3))
fatal("VLDR_D bad offset %i\n", offset);
codegen_addlong(block, COND_AL | OPCODE_VLDR_D | Rd(dest_reg) | Rn(base_reg) | (offset >> 2));
}
void
host_arm_VLDR_S(codeblock_t *block, int dest_reg, int base_reg, int offset)
{
if ((offset > 1020) || (offset & 3))
fatal("VLDR_S bad offset %i\n", offset);
codegen_addlong(block, COND_AL | OPCODE_VLDR_S | Rd(dest_reg) | Rn(base_reg) | (offset >> 2));
}
void
host_arm_VMOV_32_S(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_32_S | Rt(dest_reg) | Vn(src_reg));
}
void
host_arm_VMOV_64_D(codeblock_t *block, int dest_reg_low, int dest_reg_high, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_64_D | Rt(dest_reg_low) | Rt2(dest_reg_high) | Vm(src_reg));
}
void
host_arm_VMOV_D_64(codeblock_t *block, int dest_reg, int src_reg_low, int src_reg_high)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_D_64 | Vm(dest_reg) | Rt(src_reg_low) | Rt2(src_reg_high));
}
void
host_arm_VMOV_S_32(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_S_32 | Vn(dest_reg) | Rt(src_reg));
}
void
host_arm_VMOV_D_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_D_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VMOVN_I32(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VMOVN_I32 | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VMOVN_I64(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VMOVN_I64 | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VMOV_F32_ONE(codeblock_t *block, int dst_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMOV_F32_ONE | Rd(dst_reg));
}
void
host_arm_VMSR_FPSCR(codeblock_t *block, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VMSR_FPSCR | Rd(src_reg));
}
void
host_arm_VMRS_APSR(codeblock_t *block)
{
codegen_addlong(block, COND_AL | OPCODE_VMRS_APSR);
}
void
host_arm_VMAX_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VMAX_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VMIN_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VMIN_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VMUL_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VMUL | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VMUL_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VMUL_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VMUL_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VMUL_S16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VMULL_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VMULL_S16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VNEG_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VNEG_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VORR_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VORR_D | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VPADDL_S16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VPADDL_S16 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VPADDL_S32(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VPADDL_S32 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VPADDL_Q_S32(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VPADDL_Q_S32 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VQADD_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQADD_S8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQADD_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQADD_S16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQADD_U8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQADD_U8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQADD_U16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQADD_U16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQSUB_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQSUB_S8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQSUB_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQSUB_S16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQSUB_U8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQSUB_U8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQSUB_U16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VQSUB_U16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VQMOVN_S16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VQMOVN_S16 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VQMOVN_S32(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VQMOVN_S32 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VQMOVN_U16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_addlong(block, OPCODE_VQMOVN_U16 | Vd(dst_reg) | Vm(src_reg));
}
void
host_arm_VSHL_D_IMM_16(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 15)
fatal("host_arm_VSHL_D_IMM_16 : shift > 15\n");
codegen_addlong(block, OPCODE_VSHL_D_IMM_16 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(shift));
}
void
host_arm_VSHL_D_IMM_32(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 31)
fatal("host_arm_VSHL_D_IMM_32 : shift > 31\n");
codegen_addlong(block, OPCODE_VSHL_D_IMM_32 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(shift));
}
void
host_arm_VSHL_D_IMM_64(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 63)
fatal("host_arm_VSHL_D_IMM_64 : shift > 63\n");
codegen_addlong(block, OPCODE_VSHL_D_IMM_64 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(shift));
}
void
host_arm_VSHR_D_S16(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 15)
fatal("host_arm_VSHR_SD_IMM_16 : shift > 15\n");
codegen_addlong(block, OPCODE_VSHR_D_S16 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(16 - shift));
}
void
host_arm_VSHR_D_S32(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 31)
fatal("host_arm_VSHR_SD_IMM_32 : shift > 31\n");
codegen_addlong(block, OPCODE_VSHR_D_S32 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(32 - shift));
}
void
host_arm_VSHR_D_S64(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 63)
fatal("host_arm_VSHR_SD_IMM_64 : shift > 63\n");
codegen_addlong(block, OPCODE_VSHR_D_S64 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(64 - shift));
}
void
host_arm_VSHR_D_U16(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 15)
fatal("host_arm_VSHR_UD_IMM_16 : shift > 15\n");
codegen_addlong(block, OPCODE_VSHR_D_U16 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(16 - shift));
}
void
host_arm_VSHR_D_U32(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 31)
fatal("host_arm_VSHR_UD_IMM_32 : shift > 31\n");
codegen_addlong(block, OPCODE_VSHR_D_U32 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(32 - shift));
}
void
host_arm_VSHR_D_U64(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 63)
fatal("host_arm_VSHR_UD_IMM_64 : shift > 63\n");
codegen_addlong(block, OPCODE_VSHR_D_U64 | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM(64 - shift));
}
void
host_arm_VSHRN_32(codeblock_t *block, int dst_reg, int src_reg, int shift)
{
if (shift > 16)
fatal("host_arm_VSHRN_32 : shift > 16\n");
codegen_addlong(block, OPCODE_VSHRN | Vd(dst_reg) | Vm(src_reg) | VSHIFT_IMM_32(16 - shift));
}
void
host_arm_VSQRT_D(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VSQRT_D | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VSQRT_S(codeblock_t *block, int dest_reg, int src_reg)
{
codegen_addlong(block, COND_AL | OPCODE_VSQRT_S | Vd(dest_reg) | Vm(src_reg));
}
void
host_arm_VSTR_D(codeblock_t *block, int src_reg, int base_reg, int offset)
{
if ((offset > 1020) || (offset & 3))
fatal("VSTR_D bad offset %i\n", offset);
codegen_addlong(block, COND_AL | OPCODE_VSTR_D | Rd(src_reg) | Rn(base_reg) | (offset >> 2));
}
void
host_arm_VSTR_S(codeblock_t *block, int src_reg, int base_reg, int offset)
{
if ((offset > 1020) || (offset & 3))
fatal("VSTR_S bad offset %i\n", offset);
codegen_addlong(block, COND_AL | OPCODE_VSTR_S | Rd(src_reg) | Rn(base_reg) | (offset >> 2));
}
void
host_arm_VSUB_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VSUB | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VSUB_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, COND_AL | OPCODE_VSUB_F32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VSUB_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VSUB_I8 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VSUB_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VSUB_I16 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VSUB_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m)
{
codegen_addlong(block, OPCODE_VSUB_I32 | Rd(dst_reg) | Rn(src_reg_n) | Rm(src_reg_m));
}
void
host_arm_VZIP_D8(codeblock_t *block, int d_reg, int m_reg)
{
codegen_addlong(block, OPCODE_VZIP_D8 | Vd(d_reg) | Vm(m_reg));
}
void
host_arm_VZIP_D16(codeblock_t *block, int d_reg, int m_reg)
{
codegen_addlong(block, OPCODE_VZIP_D16 | Vd(d_reg) | Vm(m_reg));
}
void
host_arm_VZIP_D32(codeblock_t *block, int d_reg, int m_reg)
{
codegen_addlong(block, OPCODE_VZIP_D32 | Vd(d_reg) | Vm(m_reg));
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm_ops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 15,894 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "x86_flags.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_misc.h"
uint32_t
ropPUSH_r16(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_16(opcode & 7));
SUB_SP(ir, 2);
return op_pc;
}
uint32_t
ropPUSH_r32(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_32(opcode & 7));
SUB_SP(ir, 4);
return op_pc;
}
uint32_t
ropPOP_r16(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_16(opcode & 7), IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_16(opcode & 7), IREG_SS_base, IREG_eaaddr);
}
if ((opcode & 7) != REG_SP)
ADD_SP(ir, 2);
return op_pc;
}
uint32_t
ropPOP_r32(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_32(opcode & 7), IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_32(opcode & 7), IREG_SS_base, IREG_eaaddr);
}
if ((opcode & 7) != REG_ESP)
ADD_SP(ir, 4);
return op_pc;
}
uint32_t
ropPUSH_imm_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm = fastreadw(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 2);
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropPUSH_imm_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t imm = fastreadl(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 4);
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropPUSH_imm_16_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm = (int16_t) (int8_t) fastreadb(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 2);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropPUSH_imm_32_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t imm = (int32_t) (int8_t) fastreadb(cs + op_pc);
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, imm);
SUB_SP(ir, 4);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropPOP_W(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_16(fetchdat & 7), IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_16(fetchdat & 7), IREG_SS_base, IREG_eaaddr);
}
} else {
x86seg *target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 2);
codegen_check_seg_write(block, ir, target_seg);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_temp0, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_temp0);
}
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
}
if ((fetchdat & 0xc7) != (0xc0 | REG_SP))
ADD_SP(ir, 2);
return op_pc + 1;
}
uint32_t
ropPOP_L(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_32(fetchdat & 7), IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_32(fetchdat & 7), IREG_SS_base, IREG_eaaddr);
}
} else {
x86seg *target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 4);
codegen_check_seg_write(block, ir, target_seg);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_temp0, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_temp0);
}
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
}
if ((fetchdat & 0xc7) != (0xc0 | REG_ESP))
ADD_SP(ir, 4);
return op_pc + 1;
}
#define ROP_PUSH_SEG(seg) \
uint32_t ropPUSH_##seg##_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_##seg##_seg_W); \
SUB_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPUSH_##seg##_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4); \
uop_MOVZX(ir, IREG_temp0, IREG_##seg##_seg_W); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_temp0); \
SUB_SP(ir, 4); \
\
return op_pc; \
}
#define ROP_POP_SEG(seg, rseg) \
uint32_t ropPOP_##seg##_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPOP_##seg##_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 4); \
\
return op_pc; \
}
ROP_PUSH_SEG(CS)
ROP_PUSH_SEG(DS)
ROP_PUSH_SEG(ES)
ROP_PUSH_SEG(FS)
ROP_PUSH_SEG(GS)
ROP_PUSH_SEG(SS)
ROP_POP_SEG(DS, cpu_state.seg_ds)
ROP_POP_SEG(ES, cpu_state.seg_es)
ROP_POP_SEG(FS, cpu_state.seg_fs)
ROP_POP_SEG(GS, cpu_state.seg_gs)
uint32_t
ropLEAVE_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_EBP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_BP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr);
}
uop_ADD_IMM(ir, IREG_SP, IREG_BP, 2);
uop_MOV(ir, IREG_BP, IREG_temp0_W);
return op_pc;
}
uint32_t
ropLEAVE_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_EBP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_BP);
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_eaaddr);
}
uop_ADD_IMM(ir, IREG_ESP, IREG_EBP, 4);
uop_MOV(ir, IREG_EBP, IREG_temp0);
return op_pc;
}
uint32_t
ropPUSHA_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -16);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 14, IREG_AX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 12, IREG_CX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 10, IREG_DX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 8, IREG_BX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 6, IREG_SP);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 4, IREG_BP);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 2, IREG_SI);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_DI);
SUB_SP(ir, 16);
return op_pc;
}
uint32_t
ropPUSHA_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -32);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 28, IREG_EAX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 24, IREG_ECX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 20, IREG_EDX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 16, IREG_EBX);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 12, IREG_ESP);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 8, IREG_EBP);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 4, IREG_ESI);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_EDI);
SUB_SP(ir, 32);
return op_pc;
}
uint32_t
ropPOPA_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP(ir);
uop_MEM_LOAD_REG(ir, IREG_DI, IREG_SS_base, sp_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_SI, IREG_SS_base, sp_reg, 2);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_BP, IREG_SS_base, sp_reg, 4);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_BX, IREG_SS_base, sp_reg, 8);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_DX, IREG_SS_base, sp_reg, 10);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_CX, IREG_SS_base, sp_reg, 12);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_AX, IREG_SS_base, sp_reg, 14);
ADD_SP(ir, 16);
return op_pc;
}
uint32_t
ropPOPA_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP(ir);
uop_MEM_LOAD_REG(ir, IREG_EDI, IREG_SS_base, sp_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_ESI, IREG_SS_base, sp_reg, 4);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_EBP, IREG_SS_base, sp_reg, 8);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_EBX, IREG_SS_base, sp_reg, 16);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_EDX, IREG_SS_base, sp_reg, 20);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_ECX, IREG_SS_base, sp_reg, 24);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_EAX, IREG_SS_base, sp_reg, 28);
ADD_SP(ir, 32);
return op_pc;
}
uint32_t
ropPUSHF(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_CALL_FUNC(ir, flags_rebuild);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_flags);
SUB_SP(ir, 2);
return op_pc;
}
uint32_t
ropPUSHFD(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int sp_reg;
if ((cpu_state.eflags & VM_FLAG) && (IOPL < 3))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_CALL_FUNC(ir, flags_rebuild);
if (cpu_CR4_mask & CR4_VME)
uop_AND_IMM(ir, IREG_temp0_W, IREG_eflags, 0x3c);
else if (CPUID)
uop_AND_IMM(ir, IREG_temp0_W, IREG_eflags, 0x24);
else
uop_AND_IMM(ir, IREG_temp0_W, IREG_eflags, 4);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_flags);
uop_MEM_STORE_REG_OFFSET(ir, IREG_SS_base, sp_reg, 2, IREG_temp0_W);
SUB_SP(ir, 4);
return op_pc;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_stack.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,833 |
```objective-c
/*RBP = cpu_state + 128
R12 = ram (if block->flags & CODEBLOCK_NO_IMMEDIATES)*/
#define REG_AX 0
#define REG_CX 1
#define REG_DX 2
#define REG_BX 3
#define REG_SP 4
#define REG_BP 5
#define REG_SI 6
#define REG_DI 7
#define REG_EAX 0
#define REG_ECX 1
#define REG_EDX 2
#define REG_EBX 3
#define REG_ESP 4
#define REG_EBP 5
#define REG_ESI 6
#define REG_EDI 7
#define REG_RAX 0
#define REG_RCX 1
#define REG_RDX 2
#define REG_RBX 3
#define REG_RSP 4
#define REG_RBP 5
#define REG_RSI 6
#define REG_RDI 7
#define REG_R8 8
#define REG_R9 9
#define REG_R10 10
#define REG_R11 11
#define REG_R12 12
#define REG_R13 13
#define REG_R14 14
#define REG_R15 15
#define REG_XMM0 0
#define REG_XMM1 1
#define REG_XMM2 2
#define REG_XMM3 3
#define REG_XMM4 4
#define REG_XMM5 5
#define REG_XMM6 6
#define REG_XMM7 7
#define REG_XMM_TEMP REG_XMM0
#define CODEGEN_HOST_REGS 3
#define CODEGEN_HOST_FP_REGS 7
extern void *codegen_mem_load_byte;
extern void *codegen_mem_load_word;
extern void *codegen_mem_load_long;
extern void *codegen_mem_load_quad;
extern void *codegen_mem_load_single;
extern void *codegen_mem_load_double;
extern void *codegen_mem_store_byte;
extern void *codegen_mem_store_word;
extern void *codegen_mem_store_long;
extern void *codegen_mem_store_quad;
extern void *codegen_mem_store_single;
extern void *codegen_mem_store_double;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_defs.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 492 |
```c
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86_defs.h"
# include "codegen_backend_x86_ops.h"
# include "codegen_backend_x86_ops_helpers.h"
# define RM_OP_ADD 0x00
# define RM_OP_OR 0x08
# define RM_OP_AND 0x20
# define RM_OP_SUB 0x28
# define RM_OP_XOR 0x30
# define RM_OP_CMP 0x38
# define RM_OP_ROL 0x00
# define RM_OP_ROR 0x08
# define RM_OP_SHL 0x20
# define RM_OP_SHR 0x28
# define RM_OP_SAR 0x38
void
host_x86_ADD32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x03, 0x45 | (dst_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x03); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | (dst_reg << 3));
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_ADD8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x04, imm_data); /*ADD AL, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_ADD | dst_reg, imm_data); /*ADD dst_reg, imm_data*/
}
}
void
host_x86_ADD16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_ADD | dst_reg, imm_data & 0xff); /*ADD dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x05); /*ADD AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_ADD | dst_reg); /*ADD dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_ADD32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_ADD | dst_reg, imm_data & 0xff); /*ADD dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x05); /*ADD EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_ADD | dst_reg); /*ADD dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_ADD8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x00, 0xc0 | dst_reg | (src_reg << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_ADD16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x01, 0xc0 | dst_reg | (src_reg << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_ADD32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte2(block, 0x01, 0xc0 | dst_reg | (src_reg << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_AND8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x24, imm_data); /*AND AL, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_AND | dst_reg, imm_data); /*AND dst_reg, imm_data*/
}
}
void
host_x86_AND16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_AND | dst_reg, imm_data & 0xff); /*AND dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x66, 0x25); /*AND AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_AND | dst_reg); /*AND dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_AND32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_AND | dst_reg, imm_data & 0xff); /*AND dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x25); /*AND EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_AND | dst_reg); /*AND dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_AND8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x20, 0xc0 | dst_reg | (src_reg << 3)); /*AND dst_reg, src_reg_b*/
}
void
host_x86_AND16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x21, 0xc0 | dst_reg | (src_reg << 3)); /*AND dst_reg, src_reg_b*/
}
void
host_x86_AND32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x21, 0xc0 | dst_reg | (src_reg << 3)); /*AND dst_reg, src_reg_b*/
}
void
host_x86_CALL(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xe8); /*CALL*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
void
host_x86_CMP16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_CMP | dst_reg, imm_data & 0xff); /*CMP dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x3d); /*CMP AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_CMP | dst_reg); /*CMP dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_CMP32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_CMP | dst_reg, imm_data & 0xff); /*CMP dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x3d); /*CMP EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_CMP | dst_reg); /*CMP dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_CMP8_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x38, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_CMP16_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x39, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_CMP32_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x39, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_INC32_ABS(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0xff, 0x05); /*INC p*/
codegen_addlong(block, (uint32_t) p);
}
void
host_x86_JMP(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xe9); /*JMP*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
uint32_t *
host_x86_JMP_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xe9); /*JMP*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_x86_JNZ(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x85); /*JNZ*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
void
host_x86_JZ(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x84); /*JZ*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
uint8_t *
host_x86_JNZ_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x75, 0); /*JNZ*/
return &block_write_data[block_pos - 1];
}
uint8_t *
host_x86_JS_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x78, 0); /*JS*/
return &block_write_data[block_pos - 1];
}
uint8_t *
host_x86_JZ_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x74, 0); /*JZ*/
return &block_write_data[block_pos - 1];
}
uint32_t *
host_x86_JNB_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x83); /*JNB*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNBE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x87); /*JNBE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNL_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8d); /*JNL*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNLE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8f); /*JNLE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNO_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x81); /*JNO*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNS_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x89); /*JNS*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNZ_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x85); /*JNZ*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JB_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x82); /*JB*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JBE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x86); /*JBE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JL_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8c); /*JL*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JLE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8e); /*JLE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JO_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x80); /*JO*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JS_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x88); /*JS*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JZ_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x84); /*JZ*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_x86_LAHF(codeblock_t *block)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x9f); /*LAHF*/
}
void
host_x86_LEA_REG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t offset)
{
if (offset) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x8d, 0x80 | (dst_reg << 3) | src_reg); /*LEA dst_reg, [offset+src_reg]*/
codegen_addlong(block, offset);
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x8d, 0x00 | (dst_reg << 3) | src_reg); /*LEA dst_reg, [src_reg]*/
}
}
void
host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8d, 0x04 | (dst_reg << 3), (src_reg_b << 3) | src_reg_a); /*LEA dst_reg, [src_reg_a + src_reg_b]*/
}
void
host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8d, 0x04 | (dst_reg << 3), (shift << 6) | (src_reg_b << 3) | src_reg_a); /*LEA dst_reg, [src_reg_a + src_reg_b * (1 << shift)]*/
}
void
host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte3(block, 0xc6, 0x45, offset); /*MOVB offset[EBP], imm_data*/
codegen_addbyte(block, imm_data);
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte2(block, 0xc6, 0x05); /*MOVB p, imm_data*/
codegen_addlong(block, (uint32_t) p);
codegen_addbyte(block, imm_data);
}
}
void
host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[EBP], imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 9);
codegen_addbyte3(block, 0x66, 0xc7, 0x05); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t) p);
codegen_addword(block, imm_data);
}
}
void
host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x45, offset); /*MOV offset[EBP], imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0xc7, 0x05); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t) p);
codegen_addlong(block, imm_data);
}
}
void
host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x88, 0x45 | (src_reg << 3), offset); /*MOVB offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x88); /*MOVB [p], src_reg*/
codegen_addbyte(block, 0x05 | (src_reg << 3));
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV16_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x89, 0x45 | (src_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x66, 0x89, 0x05 | (src_reg << 3)); /*MOV [p], src_reg*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV32_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x45 | (src_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x89); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | (src_reg << 3));
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV8_ABS_REG_REG_SHIFT_REG(codeblock_t *block, uint32_t addr, int base_reg, int idx_reg, int shift, int src_reg)
{
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x88, 0x44 | (src_reg << 3), base_reg | (idx_reg << 3) | (shift << 6), addr & 0xff); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x88, 0x84 | (src_reg << 3), base_reg | (idx_reg << 3) | (shift << 6)); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
codegen_addlong(block, addr);
}
}
void
host_x86_MOV8_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x88, 0x04 | (src_reg << 3), base_reg | (idx_reg << 3)); /*MOV B[base_reg + idx_reg], src_reg*/
}
void
host_x86_MOV16_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x89, 0x04 | (src_reg << 3), base_reg | (idx_reg << 3)); /*MOV W[base_reg + idx_reg], src_reg*/
}
void
host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x04 | (src_reg << 3), base_reg | (idx_reg << 3)); /*MOV L[base_reg + idx_reg], src_reg*/
}
void
host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8a, 0x45 | (dst_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x8a); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | (dst_reg << 3));
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x8b, 0x45 | (dst_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x66, 0x8b, 0x05 | (dst_reg << 3)); /*MOV [p], src_reg*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x45 | (dst_reg << 3), offset); /*MOV offset[EBP], src_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x8b); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | (dst_reg << 3));
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOV32_REG_ABS_INDEX_SHIFT(codeblock_t *block, int dst_reg, void *p, int idx_reg, int shift)
{
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x8b, 0x04 | (dst_reg << 3), (shift << 6) | (idx_reg << 3) | 0x05); /*MOV dst_reg, [p + idx_reg << shift]*/
codegen_addlong(block, (uint32_t) p);
}
void
host_x86_MOV8_REG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int base_reg, int idx_reg, int shift)
{
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x8a, 0x44 | (dst_reg << 3), base_reg | (idx_reg << 3) | (shift << 6), addr & 0xff); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x8a, 0x84 | (dst_reg << 3), base_reg | (idx_reg << 3) | (shift << 6)); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
codegen_addlong(block, addr);
}
}
void
host_x86_MOV32_REG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x04 | (dst_reg << 3), base_reg | (idx_reg << 3)); /*MOV dst_reg, L[base_reg + idx_reg]*/
}
void
host_x86_MOV16_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x8b, 0x40 | base_reg | (dst_reg << 3), offset);
}
} else
fatal("MOV16_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOV32_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), offset);
}
} else
fatal("MOV32_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOV16_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x89, 0x40 | base_reg | (src_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x89, 0x40 | base_reg | (src_reg << 3), offset);
}
} else
fatal("MOV16_BASE_OFFSET_REG - offset %i\n", offset);
}
void
host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x89, 0x40 | base_reg | (src_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x40 | base_reg | (src_reg << 3), offset);
}
} else
fatal("MOV32_BASE_OFFSET_REG - offset %i\n", offset);
}
void
host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
codegen_addlong(block, imm_data);
}
} else
fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
}
void
host_x86_MOV8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xb0 + dst_reg, imm_data); /*MOV reg, imm_data*/
}
void
host_x86_MOV16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (!imm_data) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x31, 0xc0 | dst_reg | (dst_reg << 3)); /*XOR dst_reg, dst_reg*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x66, 0xb8 + dst_reg); /*MOV reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_MOV32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (!imm_data) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x31, 0xc0 | dst_reg | (dst_reg << 3)); /*XOR dst_reg, dst_reg*/
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xb8 + dst_reg); /*MOV reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_MOV8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x88, 0xc0 | dst_reg | (src_reg << 3));
}
void
host_x86_MOV16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x89, 0xc0 | dst_reg | (src_reg << 3));
}
void
host_x86_MOV32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x89, 0xc0 | dst_reg | (src_reg << 3));
}
void
host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_data)
{
if (!offset) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x04, 0x24); /*MOV [ESP], imm_data*/
codegen_addlong(block, imm_data);
} else if (offset >= -0x80 && offset < 0x80) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x44, 0x24, offset & 0xff); /*MOV offset[ESP], imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 11);
codegen_addbyte3(block, 0xc7, 0x84, 0x24); /*MOV offset[ESP], imm_data*/
codegen_addlong(block, offset);
codegen_addlong(block, imm_data);
}
}
void
host_x86_MOVSX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xbe, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVSX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xbe, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVSX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xbf, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | (dst_reg << 3), offset); /*MOV dest_reg, [EBP+offset]*/
} else {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0x66, 0x0f, 0xb6, 0x05 | (dst_reg << 3)); /*MOVZX dst_reg, [p]*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | (dst_reg << 3), offset); /*MOV dest_reg, [EBP+offset]*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x0f, 0xb6, 0x05 | (dst_reg << 3)); /*MOVZX dst_reg, [p]*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb7, 0x45 | (dst_reg << 3), offset); /*MOV dest_reg, [EBP+offset]*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x0f, 0xb7, 0x05 | (dst_reg << 3)); /*MOVZX dst_reg, [p]*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xb7, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_BASE_INDEX_32_8(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb6, 0x04 | (dst_reg << 3), base_reg | (idx_reg << 3)); /*MOVZX dst_reg, B[base_reg + idx_reg]*/
}
void
host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb7, 0x04 | (dst_reg << 3), base_reg | (idx_reg << 3)); /*MOVZX dst_reg, W[base_reg + idx_reg]*/
}
void
host_x86_OR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x08, 0xc0 | dst_reg | (src_reg << 3)); /*OR dst_reg, src_reg_b*/
}
void
host_x86_OR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x09, 0xc0 | dst_reg | (src_reg << 3)); /*OR dst_reg, src_reg_b*/
}
void
host_x86_OR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x09, 0xc0 | dst_reg | (src_reg << 3)); /*OR dst_reg, src_reg_b*/
}
void
host_x86_OR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x0c, imm_data); /*OR AL, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_OR | dst_reg, imm_data); /*OR dst_reg, imm_data*/
}
}
void
host_x86_OR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_OR | dst_reg, imm_data & 0xff); /*OR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x66, 0x0d); /*OR AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_OR | dst_reg); /*OR dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_OR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_OR | dst_reg, imm_data & 0xff); /*OR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x0d); /*OR EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_OR | dst_reg); /*OR dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_POP(codeblock_t *block, int src_reg)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x58 | src_reg); /*POP reg*/
}
void
host_x86_PUSH(codeblock_t *block, int src_reg)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x50 | src_reg); /*PUSH reg*/
}
void
host_x86_RET(codeblock_t *block)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0xc3); /*RET*/
}
void
host_x86_ROL8_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL16_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL32_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL8_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROL16_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROL32_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROR8_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR16_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR32_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_ROR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_ROR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
# define MODRM_MOD_REG(rm, reg) (0xc0 | reg | (rm << 3))
void
host_x86_SAR8_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR16_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR32_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SAR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SAR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SHL8_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL16_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL32_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL8_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHL16_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHL32_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHR8_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR16_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR32_CL(codeblock_t *block, int dst_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SHR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SHR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SUB8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x2c, imm_data); /*SUB AL, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_SUB | dst_reg, imm_data); /*SUB dst_reg, imm_data*/
}
}
void
host_x86_SUB16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_SUB | dst_reg, imm_data & 0xff); /*SUB dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x2d); /*SUB AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_SUB | dst_reg); /*SUB dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_SUB32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_SUB | dst_reg, imm_data & 0xff); /*SUB dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x2d); /*SUB EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_SUB | dst_reg); /*SUB dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_SUB8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x28, 0xc0 | dst_reg | (src_reg << 3)); /*SUB dst_reg, src_reg*/
}
void
host_x86_SUB16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x29, 0xc0 | dst_reg | (src_reg << 3)); /*SUB dst_reg, src_reg*/
}
void
host_x86_SUB32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x29, 0xc0 | dst_reg | (src_reg << 3)); /*SUB dst_reg, src_reg*/
}
void
host_x86_TEST8_REG(codeblock_t *block, int src_host_reg, int dst_host_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x84, MODRM_MOD_REG(dst_host_reg, src_host_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST16_REG(codeblock_t *block, int src_host_reg, int dst_host_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x85, MODRM_MOD_REG(dst_host_reg, src_host_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST32_REG(codeblock_t *block, int src_host_reg, int dst_host_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x85, MODRM_MOD_REG(dst_host_reg, src_host_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xa9); /*TEST EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0xf7, 0xc0 | dst_reg); /*TEST dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_XOR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x30, 0xc0 | dst_reg | (src_reg << 3)); /*XOR dst_reg, src_reg*/
}
void
host_x86_XOR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x31, 0xc0 | dst_reg | (src_reg << 3)); /*XOR dst_reg, src_reg*/
}
void
host_x86_XOR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x31, 0xc0 | dst_reg | (src_reg << 3)); /*XOR dst_reg, src_reg*/
}
void
host_x86_XOR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x34, imm_data); /*XOR AL, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_XOR | dst_reg, imm_data); /*XOR dst_reg, imm_data*/
}
}
void
host_x86_XOR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_XOR | dst_reg, imm_data & 0xff); /*XOR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x35); /*XOR AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_XOR | dst_reg); /*XOR dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_XOR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_XOR | dst_reg, imm_data & 0xff); /*XOR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x35); /*XOR EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_XOR | dst_reg); /*XOR dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 15,053 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "x86_flags.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_backend.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_shift.h"
static uint32_t
shift_common_8(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
{
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SHL_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SHR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SAR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
default:
return 0;
}
} else {
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_temp0_B, IREG_temp0_B, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_temp0_B, IREG_temp0_B, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x28: /*SHR*/
uop_SHR_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x38: /*SAR*/
uop_SAR_IMM(ir, IREG_temp1_B, IREG_temp0_B, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
shift_common_16(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
{
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHL_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SAR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
default:
return 0;
}
} else {
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_temp0_W, IREG_temp0_W, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_temp0_W, IREG_temp0_W, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x28: /*SHR*/
uop_SHR_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x38: /*SAR*/
uop_SAR_IMM(ir, IREG_temp1_W, IREG_temp0_W, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
shift_common_32(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count)
{
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHL_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SAR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), count);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
default:
return 0;
}
} else {
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL_IMM(ir, IREG_temp0, IREG_temp0, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR_IMM(ir, IREG_temp0, IREG_temp0, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL_IMM(ir, IREG_temp1, IREG_temp0, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x28: /*SHR*/
uop_SHR_IMM(ir, IREG_temp1, IREG_temp0, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x38: /*SAR*/
uop_SAR_IMM(ir, IREG_temp1, IREG_temp0, count);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, count);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
static uint32_t
shift_common_variable_32(ir_data_t *ir, uint32_t fetchdat, uint32_t op_pc, x86seg *target_seg, int count_reg)
{
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHL(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SAR(ir, IREG_32(dest_reg), IREG_32(dest_reg), count_reg);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
default:
return 0;
}
} else {
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_temp0, IREG_temp0, count_reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_temp0, IREG_temp0, count_reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL(ir, IREG_temp1, IREG_temp0, count_reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x28: /*SHR*/
uop_SHR(ir, IREG_temp1, IREG_temp0, count_reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x38: /*SAR*/
uop_SAR(ir, IREG_temp1, IREG_temp0, count_reg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, count_reg);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropC0(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
uint8_t imm;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (imm)
return shift_common_8(ir, fetchdat, op_pc, target_seg, imm) + 1;
return op_pc + 1;
}
uint32_t
ropC1_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
uint8_t imm;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (imm)
return shift_common_16(ir, fetchdat, op_pc, target_seg, imm) + 1;
return op_pc + 1;
}
uint32_t
ropC1_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
}
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uint32_t new_pc;
int jump_uop;
LOAD_IMMEDIATE_FROM_RAM_8(block, ir, IREG_temp2, cs + op_pc + 1);
uop_AND_IMM(ir, IREG_temp2, IREG_temp2, 0x1f);
jump_uop = uop_CMP_IMM_JZ_DEST(ir, IREG_temp2, 0);
new_pc = shift_common_variable_32(ir, fetchdat, op_pc, target_seg, IREG_temp2) + 1;
uop_NOP_BARRIER(ir);
uop_set_jump_dest(ir, jump_uop);
return new_pc;
} else {
uint8_t imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (imm)
return shift_common_32(ir, fetchdat, op_pc, target_seg, imm) + 1;
}
return op_pc + 1;
}
uint32_t
ropD0(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
}
return shift_common_8(ir, fetchdat, op_pc, target_seg, 1);
}
uint32_t
ropD1_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
}
return shift_common_16(ir, fetchdat, op_pc, target_seg, 1);
}
uint32_t
ropD1_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
}
return shift_common_32(ir, fetchdat, op_pc, target_seg, 1);
}
uint32_t
ropD2(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
if (!(CL & 0x1f) || !block->ins)
return 0;
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SHL(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SHR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_SAR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_temp0_B, IREG_temp0_B, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_temp0_B, IREG_temp0_B, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x28: /*SHR*/
uop_SHR(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x38: /*SAR*/
uop_SAR(ir, IREG_temp1_B, IREG_temp0_B, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropD3_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
if (!(CL & 0x1f) || !block->ins)
return 0;
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHL(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SAR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x28: /*SHR*/
uop_SHR(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x38: /*SAR*/
uop_SAR(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropD3_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
if ((fetchdat & 0x30) == 0x10) /*RCL/RCR*/
return 0;
if (!(CL & 0x1f) || !block->ins)
return 0;
uop_AND_IMM(ir, IREG_temp2, REG_ECX, 0x1f);
uop_CMP_IMM_JZ(ir, IREG_temp2, 0, codegen_exit_rout);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20:
case 0x30: /*SHL*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHL(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x28: /*SHR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x38: /*SAR*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SAR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp2);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ROL*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROL(ir, IREG_temp0, IREG_temp0, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROL32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x08: /*ROR*/
uop_CALL_FUNC(ir, flags_rebuild);
uop_ROR(ir, IREG_temp0, IREG_temp0, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ROR32);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
break;
case 0x20:
case 0x30: /*SHL*/
uop_SHL(ir, IREG_temp1, IREG_temp0, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x28: /*SHR*/
uop_SHR(ir, IREG_temp1, IREG_temp0, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x38: /*SAR*/
uop_SAR(ir, IREG_temp1, IREG_temp0, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SAR32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSHLD_16_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
int src_reg = (fetchdat >> 3) & 7;
uint8_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (!imm)
return op_pc + 2;
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHL_IMM(ir, IREG_temp0_W, IREG_16(dest_reg), imm);
uop_SHR_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
uop_OR(ir, IREG_16(dest_reg), IREG_temp0_W, IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp2_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SHL_IMM(ir, IREG_temp0_W, IREG_temp2, imm);
uop_SHR_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL16);
}
return op_pc + 2;
}
uint32_t
ropSHLD_32_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
int src_reg = (fetchdat >> 3) & 7;
uint8_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (!imm)
return op_pc + 2;
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHL_IMM(ir, IREG_temp0, IREG_32(dest_reg), imm);
uop_SHR_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
uop_OR(ir, IREG_32(dest_reg), IREG_temp0, IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SHL_IMM(ir, IREG_temp0, IREG_temp2, imm);
uop_SHR_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_temp2);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHL32);
}
return op_pc + 2;
}
uint32_t
ropSHRD_16_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
int src_reg = (fetchdat >> 3) & 7;
uint8_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (!imm)
return op_pc + 2;
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SHR_IMM(ir, IREG_temp0_W, IREG_16(dest_reg), imm);
uop_SHL_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
uop_OR(ir, IREG_16(dest_reg), IREG_temp0_W, IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp2_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SHR_IMM(ir, IREG_temp0_W, IREG_temp2, imm);
uop_SHL_IMM(ir, IREG_temp1_W, IREG_16(src_reg), 16 - imm);
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR16);
}
return op_pc + 2;
}
uint32_t
ropSHRD_32_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg = NULL;
int src_reg = (fetchdat >> 3) & 7;
uint8_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) != 0xc0) {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
}
imm = fastreadb(cs + op_pc + 1) & 0x1f;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
if (!imm)
return op_pc + 2;
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SHR_IMM(ir, IREG_temp0, IREG_32(dest_reg), imm);
uop_SHL_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
uop_OR(ir, IREG_32(dest_reg), IREG_temp0, IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SHR_IMM(ir, IREG_temp0, IREG_temp2, imm);
uop_SHL_IMM(ir, IREG_temp1, IREG_32(src_reg), 32 - imm);
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_temp2);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SHR32);
}
return op_pc + 2;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_shift.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 13,737 |
```c
#if defined __amd64__ || defined _M_X64
# include <stdint.h>
# include <inttypes.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86-64_defs.h"
# include "codegen_backend_x86-64_ops.h"
# include "codegen_backend_x86-64_ops_helpers.h"
# define RM_OP_ADD 0x00
# define RM_OP_OR 0x08
# define RM_OP_AND 0x20
# define RM_OP_SUB 0x28
# define RM_OP_XOR 0x30
# define RM_OP_CMP 0x38
# define RM_OP_ROL 0x00
# define RM_OP_ROR 0x08
# define RM_OP_SHL 0x20
# define RM_OP_SHR 0x28
# define RM_OP_SAR 0x38
static inline void
call(codeblock_t *block, uintptr_t func)
{
intptr_t diff;
codegen_alloc_bytes(block, 5);
diff = (intptr_t) (func - (uintptr_t) &block_write_data[block_pos + 5]);
if (diff >= -0x80000000LL && diff < 0x7fffffffLL) {
codegen_addbyte(block, 0xE8); /*CALL*/
codegen_addlong(block, (uint32_t) diff);
} else {
codegen_alloc_bytes(block, 13);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, func*/
codegen_addquad(block, func);
codegen_addbyte3(block, 0x41, 0xff, 0xd1); /*CALL R9*/
}
}
static inline void
jmp(codeblock_t *block, uintptr_t func)
{
intptr_t diff;
codegen_alloc_bytes(block, 5);
diff = (intptr_t) (func - (uintptr_t) &block_write_data[block_pos + 5]);
if (diff >= -0x80000000LL && diff < 0x7fffffffLL) {
codegen_addbyte(block, 0xe9); /*JMP*/
codegen_addlong(block, (uint32_t) diff);
} else {
codegen_alloc_bytes(block, 13);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, func*/
codegen_addquad(block, func);
codegen_addbyte3(block, 0x41, 0xff, 0xe1); /*JMP R9*/
}
}
void
host_x86_ADD8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_ADD8_REG_IMM - dst_reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x04, imm_data); /*ADD EAX, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_ADD | (dst_reg & 7), imm_data); /*ADD dst_reg, imm_data*/
}
}
void
host_x86_ADD16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_ADD16_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_ADD | (dst_reg & 7), imm_data & 0xff); /*ADD dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x05); /*AND AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_ADD | (dst_reg & 7)); /*ADD dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_ADD32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_ADD32_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_ADD | (dst_reg & 7), imm_data & 0xff); /*ADD dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x05); /*ADD EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_ADD | (dst_reg & 7)); /*ADD dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_ADD64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_ADD64_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x83, 0xc0 | RM_OP_ADD | (dst_reg & 7), imm_data & 0xff); /*ADD dst_reg, imm_data*/
} else
fatal("ADD64_REG_IMM !is_imm8 %016" PRIx64 "\n", imm_data);
}
void
host_x86_ADD8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_ADD8_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x00, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_ADD16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_ADD16_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x01, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_ADD32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_ADD32_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x01, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*ADD dst_reg, src_reg*/
}
void
host_x86_AND8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_AND8_REG_IMM - dst_reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x24, imm_data); /*AND EAX, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_AND | (dst_reg & 7), imm_data); /*AND dst_reg, imm_data*/
}
}
void
host_x86_AND16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_AND16_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_AND | (dst_reg & 7), imm_data & 0xff); /*AND dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x25); /*AND AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_AND | (dst_reg & 7)); /*AND dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_AND32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_AND32_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_AND | (dst_reg & 7), imm_data & 0xff); /*AND dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x25); /*AND EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_AND | (dst_reg & 7)); /*AND dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_AND8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_AND8_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x20, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*AND dst_reg, src_reg*/
}
void
host_x86_AND16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_AND16_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x21, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*AND dst_reg, src_reg*/
}
void
host_x86_AND32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_AND32_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x21, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*AND dst_reg, src_reg*/
}
void
host_x86_CALL(codeblock_t *block, void *p)
{
call(block, (uintptr_t) p);
}
void
host_x86_CMP16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_CMP | dst_reg, imm_data & 0xff); /*CMP dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x3d); /*CMP AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_CMP | dst_reg); /*CMP dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_CMP32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_CMP | dst_reg, imm_data & 0xff); /*CMP dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x3d); /*CMP EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_CMP | dst_reg); /*CMP dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_CMP64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data)
{
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x83, 0xc0 | RM_OP_CMP | dst_reg, imm_data & 0xff); /*CMP dst_reg, imm_data*/
} else
fatal("CMP64_REG_IMM not 8-bit imm\n");
}
void
host_x86_CMP8_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x38, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_CMP16_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x39, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_CMP32_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x39, 0xc0 | src_reg_a | (src_reg_b << 3)); /*CMP src_reg_a, src_reg_b*/
}
void
host_x86_JMP(codeblock_t *block, void *p)
{
jmp(block, (uintptr_t) p);
}
void
host_x86_JNZ(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x85); /*JNZ*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
void
host_x86_JZ(codeblock_t *block, void *p)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x84); /*JZ*/
codegen_addlong(block, (uintptr_t) p - (uintptr_t) &block_write_data[block_pos + 4]);
}
uint8_t *
host_x86_JNZ_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x75, 0); /*JNZ*/
return &block_write_data[block_pos - 1];
}
uint8_t *
host_x86_JS_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x78, 0); /*JS*/
return &block_write_data[block_pos - 1];
}
uint8_t *
host_x86_JZ_short(codeblock_t *block)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x74, 0); /*JZ*/
return &block_write_data[block_pos - 1];
}
uint32_t *
host_x86_JNB_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x83); /*JNB*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNBE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x87); /*JNBE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNL_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8d); /*JNL*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNLE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8f); /*JNLE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNO_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x81); /*JNO*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNS_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x89); /*JNS*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JNZ_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x85); /*JNZ*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JB_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x82); /*JB*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JBE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x86); /*JBE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JL_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8c); /*JL*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JLE_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x8e); /*JLE*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JO_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x80); /*JO*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JS_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x88); /*JS*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
uint32_t *
host_x86_JZ_long(codeblock_t *block)
{
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x0f, 0x84); /*JZ*/
codegen_addlong(block, 0);
return (uint32_t *) &block_write_data[block_pos - 4];
}
void
host_x86_LAHF(codeblock_t *block)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x9f); /*LAHF*/
}
void
host_x86_LEA_REG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t offset)
{
if (offset) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x8d, 0x80 | (dst_reg << 3) | src_reg); /*LEA dst_reg, [offset+src_reg]*/
codegen_addlong(block, offset);
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x8d, 0x00 | (dst_reg << 3) | src_reg); /*LEA dst_reg, [src_reg]*/
}
}
void
host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b)
{
if ((dst_reg & 8) || (src_reg_a & 8) || (src_reg_b & 8))
fatal("host_x86_LEA_REG_REG - bad reg\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8d, 0x04 | ((dst_reg & 7) << 3), /*LEA dst_reg, [Rsrc_reg_a + Rsrc_reg_b]*/
((src_reg_b & 7) << 3) | (src_reg_a & 7));
}
void
host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift)
{
if ((dst_reg & 8) || (src_reg_a & 8) || (src_reg_b & 8))
fatal("host_x86_LEA_REG_REG_SHIFT - bad reg\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8d, 0x04 | ((dst_reg & 7) << 3), /*LEA dst_reg, [Rsrc_reg_a + Rsrc_reg_b * (1 << shift)]*/
(shift << 6) | ((src_reg_b & 7) << 3) | (src_reg_a & 7));
}
void
host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte3(block, 0xc6, 0x45, offset); /*MOVB offset[RBP], imm_data*/
codegen_addbyte(block, imm_data);
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV8_ABS_IMM - out of range %p\n", p);
codegen_alloc_bytes(block, 8);
codegen_addbyte3(block, 0xc6, 0x04, 0x25); /*MOVB p, imm_data*/
codegen_addlong(block, (uint32_t) (uintptr_t) p);
codegen_addbyte(block, imm_data);
}
}
void
host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0xc7, 0x45, offset); /*MOV offset[RBP], imm_data*/
codegen_addword(block, imm_data);
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV32_ABS_IMM - out of range %p\n", p);
codegen_alloc_bytes(block, 10);
codegen_addbyte4(block, 0x66, 0xc7, 0x04, 0x25); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t) (uintptr_t) p);
codegen_addword(block, imm_data);
}
}
void
host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x45, offset); /*MOV offset[RBP], imm_data*/
codegen_addlong(block, imm_data);
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV32_ABS_IMM - out of range %p\n", p);
codegen_alloc_bytes(block, 11);
codegen_addbyte3(block, 0xc7, 0x04, 0x25); /*MOV p, imm_data*/
codegen_addlong(block, (uint32_t) (uintptr_t) p);
codegen_addlong(block, imm_data);
}
}
void
host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (src_reg & 8)
fatal("host_x86_MOV8_ABS_REG - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x88, 0x45 | ((src_reg & 7) << 3), offset); /*MOVB offset[RBP], src_reg*/
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV8_ABS_REG - out of range %p\n", p);
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x88); /*MOVB [p], src_reg*/
codegen_addbyte(block, 0x05 | ((src_reg & 7) << 3));
codegen_addlong(block, (uint32_t) (uintptr_t) p);
}
}
void
host_x86_MOV16_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (src_reg & 8)
fatal("host_x86_MOV16_ABS_REG - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x89, 0x45 | ((src_reg & 7) << 3), offset); /*MOV offset[RBP], src_reg*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x66, 0x89, 0x85 | ((src_reg & 7) << 3)); /*MOV offset[RBP], src_reg*/
codegen_addlong(block, offset);
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV32_ABS_REG - out of range %p\n", p);
}
}
void
host_x86_MOV32_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (src_reg & 8)
fatal("host_x86_MOV32_ABS_REG - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x45 | ((src_reg & 7) << 3), offset); /*MOV offset[RBP], src_reg*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x89, 0x85 | ((src_reg & 7) << 3)); /*MOV offset[RBP], src_reg*/
codegen_addlong(block, offset);
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV32_ABS_REG - out of range %p\n", p);
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x89); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | ((src_reg & 7) << 3));
codegen_addlong(block, (uint32_t) (uintptr_t) p);
}
}
void
host_x86_MOV64_ABS_REG(codeblock_t *block, void *p, int src_reg)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (src_reg & 8)
fatal("host_x86_MOV64_ABS_REG - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x89, 0x45 | ((src_reg & 7) << 3), offset); /*MOV offset[RBP], src_reg*/
} else {
if ((uintptr_t) p >> 32)
fatal("host_x86_MOV64_ABS_REG - out of range %p\n", p);
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0x48, 0x89, 0x04 | ((src_reg & 7) << 3), 0x25); /*MOV [p], src_reg*/
codegen_addlong(block, (uint32_t) (uintptr_t) p);
}
}
void
host_x86_MOV8_ABS_REG_REG_SHIFT_REG(codeblock_t *block, uint32_t addr, int base_reg, int index_reg, int shift, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV8_BASE_INDEX_REG reg & 8\n");
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x88, 0x44 | (src_reg << 3), base_reg | (index_reg << 3) | (shift << 6), addr & 0xff); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x88, 0x84 | (src_reg << 3), base_reg | (index_reg << 3) | (shift << 6)); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
codegen_addlong(block, addr);
}
}
void
host_x86_MOV8_BASE_INDEX_REG(codeblock_t *block, int base_reg, int index_reg, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV8_BASE_INDEX_REG reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x88, 0x04 | (src_reg << 3), (index_reg << 3) | base_reg); /*MOV B[base_reg + index_reg], src_reg*/
}
void
host_x86_MOV16_BASE_INDEX_REG(codeblock_t *block, int base_reg, int index_reg, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV8_BASE_INDEX_REG reg & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x89, 0x04 | (src_reg << 3), (index_reg << 3) | base_reg); /*MOV W[base_reg + index_reg], src_reg*/
}
void
host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int index_reg, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV8_BASE_INDEX_REG reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x04 | (src_reg << 3), (index_reg << 3) | base_reg); /*MOV L[base_reg + index_reg], src_reg*/
}
void
host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
if (dst_reg & 8)
fatal("host_x86_MOV8_REG_ABS reg & 8\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8a, 0x45 | ((dst_reg & 7) << 3), offset); /*MOV dst_reg, offset[RBP]*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x8a, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
codegen_addlong(block, offset);
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0x41, 0x8a, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOV dst_reg, ram_offset[R12]*/
codegen_addlong(block, ram_offset);
} else {
fatal("host_x86_MOV8_REG_ABS - out of range\n");
}
}
void
host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
if (dst_reg & 8)
fatal("host_x86_MOV16_REG_ABS reg & 8\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x8b, 0x45 | ((dst_reg & 7) << 3), offset); /*MOV dst_reg, offset[RBP]*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x66, 0x8b, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
codegen_addlong(block, offset);
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
codegen_alloc_bytes(block, 9);
codegen_addbyte4(block, 0x66, 0x41, 0x8b, 0x84 | ((dst_reg & 7) << 3)); /*MOV dst_reg, ram_offset[R12]*/
codegen_addbyte(block, 0x24);
codegen_addlong(block, ram_offset);
} else {
fatal("host_x86_MOV16_REG_ABS - out of range\n");
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, p*/
codegen_addquad(block, (uintptr_t) p);
codegen_alloc_bytes(block, 1);
codegen_addbyte4(block, 0x66, 0x41, 0x8b, 0x01 | ((dst_reg & 7) << 3)); /*MOV dst_reg, [r9]*/
}
}
void
host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
if (dst_reg & 8)
fatal("host_x86_MOV32_REG_ABS reg & 8\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x45 | ((dst_reg & 7) << 3), offset); /*MOV dst_reg, offset[RBP]*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x8b, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
codegen_addlong(block, offset);
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0x41, 0x8b, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOV dst_reg, ram_offset[R12]*/
codegen_addlong(block, ram_offset);
} else {
fatal("host_x86_MOV32_REG_ABS - out of range\n");
codegen_alloc_bytes(block, 6);
codegen_addbyte(block, 0x8b); /*MOV [p], src_reg*/
codegen_addbyte(block, 0x05 | ((dst_reg & 7) << 3));
codegen_addlong(block, (uint32_t) (uintptr_t) p);
}
}
void
host_x86_MOV64_REG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (dst_reg & 8)
fatal("host_x86_MOV64_REG_ABS reg & 8\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x8b, 0x45 | ((dst_reg & 7) << 3), offset); /*MOV dst_reg, offset[RBP]*/
} else if (offset < (1ULL << 32)) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x48, 0x8b, 0x85 | ((dst_reg & 7) << 3)); /*MOV dst_reg, offset[RBP]*/
codegen_addlong(block, offset);
} else
fatal("host_x86_MOV64_REG_ABS - out of range\n");
}
void
host_x86_MOV8_REG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int base_reg, int index_reg, int shift)
{
if ((dst_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV8_REG_ABS_REG_REG_SHIFT reg & 8\n");
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x8a, 0x44 | (dst_reg << 3), base_reg | (index_reg << 3) | (shift << 6), addr & 0xff); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x8a, 0x84 | (dst_reg << 3), base_reg | (index_reg << 3) | (shift << 6)); /*MOV addr[base_reg + idx_reg << shift], src_reg*/
codegen_addlong(block, addr);
}
}
void
host_x86_MOV32_REG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int index_reg)
{
if ((dst_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOV32_REG_BASE_INDEX reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x04 | (dst_reg << 3), (index_reg << 3) | base_reg); /*MOV dst_reg, Q[base_reg + index_reg]*/
}
void
host_x86_MOV64_REG_BASE_INDEX_SHIFT(codeblock_t *block, int dst_reg, int base_reg, int index_reg, int scale)
{
if ((dst_reg & 8) || (index_reg & 8))
fatal("host_x86_MOV64_REG_BASE_INDEX_SHIFT reg & 8\n");
codegen_alloc_bytes(block, 4);
if (base_reg & 8)
codegen_addbyte4(block, 0x49, 0x8b, 0x04 | ((dst_reg & 7) << 3), (scale << 6) | ((index_reg & 7) << 3) | (base_reg & 7)); /*MOV dst_reg, Q[base_reg + index_reg << scale]*/
else
codegen_addbyte4(block, 0x48, 0x8b, 0x04 | ((dst_reg & 7) << 3), (scale << 6) | ((index_reg & 7) << 3) | (base_reg & 7)); /*MOV dst_reg, Q[base_reg + index_reg << scale]*/
}
void
host_x86_MOV16_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if ((dst_reg & 8) || (base_reg & 8))
fatal("host_x86_MOV16_REG_BASE_OFFSET reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x8b, 0x40 | base_reg | (dst_reg << 3), offset);
}
} else
fatal("MOV16_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOV32_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if ((dst_reg & 8) || (base_reg & 8))
fatal("host_x86_MOV32_REG_BASE_OFFSET reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), offset);
}
} else
fatal("MOV32_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOV64_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if ((dst_reg & 8) || (base_reg & 8))
fatal("host_x86_MOV64_REG_BASE_OFFSET reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x48);
codegen_addbyte4(block, 0x8b, 0x40 | base_reg | (dst_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x8b, 0x40 | base_reg | (dst_reg << 3), offset);
}
} else
fatal("MOV32_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8))
fatal("host_x86_MOV32_BASE_OFFSET_REG reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x89, 0x40 | base_reg | (src_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x89, 0x40 | base_reg | (src_reg << 3), offset);
}
} else
fatal("MOV32_BASE_OFFSET_REG - offset %i\n", offset);
}
void
host_x86_MOV64_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int src_reg)
{
if ((src_reg & 8) || (base_reg & 8))
fatal("host_x86_MOV64_BASE_OFFSET_REG reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x48);
codegen_addbyte4(block, 0x89, 0x40 | base_reg | (src_reg << 3), 0x24, offset);
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x89, 0x40 | base_reg | (src_reg << 3), offset);
}
} else
fatal("MOV64_BASE_OFFSET_REG - offset %i\n", offset);
}
void
host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data)
{
if (base_reg & 8)
fatal("host_x86_MOV32_BASE_OFFSET_IMM reg & 8\n");
if (offset >= -128 && offset < 127) {
if (base_reg == REG_RSP) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x40 | base_reg, 0x24, offset);
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x40 | base_reg, offset);
codegen_addlong(block, imm_data);
}
} else
fatal("MOV32_BASE_OFFSET_IMM - offset %i\n", offset);
}
void
host_x86_MOV8_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data)
{
if (reg >= 8)
fatal("host_x86_MOV8_REG_IMM reg >= 4\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xb0 | reg, imm_data); /*MOV reg, imm_data*/
}
void
host_x86_MOV16_REG_IMM(codeblock_t *block, int reg, uint16_t imm_data)
{
if (reg & 8)
fatal("host_x86_MOV16_REG_IMM reg & 8\n");
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x66, 0xb8 | (reg & 7)); /*MOV reg, imm_data*/
codegen_addword(block, imm_data);
}
void
host_x86_MOV32_REG_IMM(codeblock_t *block, int reg, uint32_t imm_data)
{
if (reg & 8)
fatal("host_x86_MOV32_REG_IMM reg & 8\n");
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xb8 | (reg & 7)); /*MOV reg, imm_data*/
codegen_addlong(block, imm_data);
}
void
host_x86_MOV64_REG_IMM(codeblock_t *block, int reg, uint64_t imm_data)
{
if (reg & 8) {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x49, 0xb8 | (reg & 7)); /*MOVQ reg, imm_data*/
codegen_addquad(block, imm_data);
} else {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x48, 0xb8 | (reg & 7)); /*MOVQ reg, imm_data*/
codegen_addquad(block, imm_data);
}
}
void
host_x86_MOV8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOV8_REG_REG - bad reg\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x88, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
void
host_x86_MOV16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOV16_REG_REG - bad reg\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x89, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
void
host_x86_MOV32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOV32_REG_REG - bad reg\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x89, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3));
}
void
host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_data)
{
if (!offset) {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0xc7, 0x04, 0x24); /*MOV [ESP], imm_data*/
codegen_addlong(block, imm_data);
} else if (offset >= -0x80 && offset < 0x80) {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xc7, 0x44, 0x24, offset & 0xff); /*MOV offset[ESP], imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 11);
codegen_addbyte3(block, 0xc7, 0x84, 0x24); /*MOV offset[ESP], imm_data*/
codegen_addlong(block, offset);
codegen_addlong(block, imm_data);
}
}
void
host_x86_MOVSX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xbe, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVSX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xbe, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVSX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xbf, 0xc0 | (dst_reg << 3) | src_reg); /*MOVSX dst_reg, src_reg*/
}
void
host_x86_MOVZX_BASE_INDEX_32_8(codeblock_t *block, int dst_reg, int base_reg, int index_reg)
{
if ((dst_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOVZX_BASE_INDEX_32_8 reg & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb6, 0x04 | (dst_reg << 3), (index_reg << 3) | base_reg);
}
void
host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_reg, int index_reg)
{
if ((dst_reg & 8) || (base_reg & 8) | (index_reg & 8))
fatal("host_x86_MOVZX_BASE_INDEX_32_16 reg & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb7, 0x04 | (dst_reg << 3), (index_reg << 3) | base_reg);
}
void
host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOVZX_REG_16_8 - bad reg\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOVZX_REG_32_8 - bad reg\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xb6, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_MOVZX_REG_16_8 - bad reg\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0xb7, 0xc0 | (dst_reg << 3) | src_reg); /*MOVZX dst_reg, src_reg*/
}
void
host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_16_8 - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x66, 0x41);
codegen_addbyte4(block, 0x0f, 0xb6, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
codegen_addlong(block, ram_offset);
} else {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, p*/
codegen_addquad(block, (uintptr_t) p);
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x66);
codegen_addbyte4(block, 0x41, 0x0f, 0xb6, 0x01 | ((dst_reg & 7) << 3)); /*MOVZX dst_reg, [r9]*/
}
}
void
host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
#if 0
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
#endif
if (offset >= -128 && offset < 127) {
if (dst_reg & 8) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x44);
codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
} else {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb6, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
}
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
codegen_alloc_bytes(block, 9);
codegen_addbyte(block, 0x41);
codegen_addbyte4(block, 0x0f, 0xb6, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
codegen_addlong(block, ram_offset);
} else {
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_32_8 - bad reg\n");
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, p*/
codegen_addquad(block, (uintptr_t) p);
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x41, 0x0f, 0xb6, 0x01 | ((dst_reg & 7) << 3)); /*MOVZX dst_reg, [r9]*/
}
}
void
host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p)
{
int64_t offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
int64_t ram_offset = (uintptr_t) p - (uintptr_t) ram;
if (dst_reg & 8)
fatal("host_x86_MOVZX_REG_ABS_32_16 - bad reg\n");
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xb7, 0x45 | ((dst_reg & 7) << 3), offset); /*MOVZX dst_reg, offset[RBP]*/
} else if ((ram_offset < (1ULL << 32)) && (block->flags & CODEBLOCK_NO_IMMEDIATES)) {
codegen_alloc_bytes(block, 9);
codegen_addbyte(block, 0x41);
codegen_addbyte4(block, 0x0f, 0xb7, 0x84 | ((dst_reg & 7) << 3), 0x24); /*MOVZX dst_reg, ram_offset[R12]*/
codegen_addlong(block, ram_offset);
} else {
codegen_alloc_bytes(block, 10);
codegen_addbyte2(block, 0x49, 0xb9); /*MOV R9, p*/
codegen_addquad(block, (uintptr_t) p);
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x41, 0x0f, 0xb7, 0x01 | ((dst_reg & 7) << 3)); /*MOVZX dst_reg, [r9]*/
}
}
void
host_x86_NOP(codeblock_t *block)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x90); /*NOP*/
}
void
host_x86_OR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_OR8_REG_IMM - dst_reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x0c, imm_data); /*OR EAX, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_OR | (dst_reg & 7), imm_data); /*OR dst_reg, imm_data*/
}
}
void
host_x86_OR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_OR16_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_OR | (dst_reg & 7), imm_data & 0xff); /*OR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x0d); /*OR AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_OR | (dst_reg & 7)); /*OR dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_OR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_OR32_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_OR | (dst_reg & 7), imm_data & 0xff); /*OR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x0d); /*OR EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_OR | (dst_reg & 7)); /*OR dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_OR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_OR8_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x08, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*OR dst_reg, src_reg*/
}
void
host_x86_OR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_OR16_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x09, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*OR dst_reg, src_reg*/
}
void
host_x86_OR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_OR32_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x09, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*OR dst_reg, src_reg*/
}
void
host_x86_POP(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x41, 0x58 | (dst_reg & 7)); /*POP reg*/
} else {
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x58 | dst_reg); /*POP reg*/
}
}
void
host_x86_PUSH(codeblock_t *block, int src_reg)
{
if (src_reg & 8) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x41, 0x50 | (src_reg & 7)); /*PUSH reg*/
} else {
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0x50 | src_reg); /*PUSH reg*/
}
}
void
host_x86_RET(codeblock_t *block)
{
codegen_alloc_bytes(block, 1);
codegen_addbyte(block, 0xc3); /*RET*/
}
void
host_x86_ROL8_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROL8 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL16_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROL16 CL & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL32_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROL32 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_ROL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_ROL8_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROL8 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROL16_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROL16 imm & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROL32_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROL32 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_ROL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_ROR8_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROR8 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR16_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROR16 CL & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR32_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("ROR32 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_ROR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_ROR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROR8 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_ROR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROR16 imm & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_ROR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("ROR32 im & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_ROR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SAR8_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SAR8 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR16_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SAR16 CL & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR32_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SAR32 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SAR | dst_reg); /*SAR dst_reg, CL*/
}
void
host_x86_SAR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SAR8 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SAR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SAR16 imm & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SAR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SAR32 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SAR | dst_reg, shift); /*SAR dst_reg, shift*/
}
void
host_x86_SHL8_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHL8 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL16_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHL16 CL & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL32_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHL32 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SHL | dst_reg); /*SHL dst_reg, CL*/
}
void
host_x86_SHL8_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHL8 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHL16_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHL16 imm & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHL32_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHL32 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SHL | dst_reg, shift); /*SHL dst_reg, shift*/
}
void
host_x86_SHR8_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHR8 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd2, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR16_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHR16 CL & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0xd3, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR32_CL(codeblock_t *block, int dst_reg)
{
if (dst_reg & 8)
fatal("SHR32 CL & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xd3, 0xc0 | RM_OP_SHR | dst_reg); /*SHR dst_reg, CL*/
}
void
host_x86_SHR8_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHR8 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc0, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SHR16_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHR16 imm & 8\n");
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0xc1, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SHR32_IMM(codeblock_t *block, int dst_reg, int shift)
{
if (dst_reg & 8)
fatal("SHR32 imm & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xc1, 0xc0 | RM_OP_SHR | dst_reg, shift); /*SHR dst_reg, shift*/
}
void
host_x86_SUB8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_SUB8_REG_IMM - dst_reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x2c, imm_data); /*SUB EAX, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_SUB | (dst_reg & 7), imm_data); /*SUB dst_reg, imm_data*/
}
}
void
host_x86_SUB16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_SUB16_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_SUB | (dst_reg & 7), imm_data & 0xff); /*SUB dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x2d); /*SUB AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_SUB | (dst_reg & 7)); /*SUB dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_SUB32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_SUB32_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_SUB | (dst_reg & 7), imm_data & 0xff); /*SUB dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x2d); /*SUB EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_SUB | (dst_reg & 7)); /*SUB dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_SUB64_REG_IMM(codeblock_t *block, int dst_reg, uint64_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_SUB64_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x48, 0x83, 0xc0 | RM_OP_SUB | (dst_reg & 7), imm_data & 0xff); /*SUB dst_reg, imm_data*/
} else
fatal("SUB64_REG_IMM !is_imm8 %016" PRIx64 "\n", imm_data);
}
void
host_x86_SUB8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_SUB8_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x28, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*SUB dst_reg, src_reg*/
}
void
host_x86_SUB16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_SUB16_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x29, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*SUB dst_reg, src_reg*/
}
void
host_x86_SUB32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_SUB32_REG_REG - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x29, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*SUB dst_reg, src_reg*/
}
# define MODRM_MOD_REG(rm, reg) (0xc0 | reg | (rm << 3))
void
host_x86_TEST8_REG(codeblock_t *block, int src_host_reg, int dst_host_reg)
{
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x84, MODRM_MOD_REG(dst_host_reg, src_host_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST16_REG(codeblock_t *block, int src_host_reg, int dst_host_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x85, MODRM_MOD_REG(dst_host_reg, src_host_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST32_REG(codeblock_t *block, int src_reg, int dst_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_TEST32_REG - bad reg\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x85, MODRM_MOD_REG(dst_reg, src_reg)); /*TEST dst_host_reg, src_host_reg*/
}
void
host_x86_TEST32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("TEST32_REG_IMM reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0xa9); /*TEST EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0xf7, 0xc0 | dst_reg); /*TEST dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_XOR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_XOR8_REG_IMM - dst_reg & 8\n");
if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x34, imm_data); /*XOR EAX, imm_data*/
} else {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x80, 0xc0 | RM_OP_XOR | (dst_reg & 7), imm_data); /*XOR dst_reg, imm_data*/
}
}
void
host_x86_XOR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_XOR16_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x83, 0xc0 | RM_OP_XOR | (dst_reg & 7), imm_data & 0xff); /*XOR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 4);
codegen_addbyte2(block, 0x66, 0x35); /*XOR AX, imm_data*/
codegen_addword(block, imm_data);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte3(block, 0x66, 0x81, 0xc0 | RM_OP_XOR | (dst_reg & 7)); /*XOR dst_reg, imm_data*/
codegen_addword(block, imm_data);
}
}
void
host_x86_XOR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data)
{
if (dst_reg & 8)
fatal("host_x86_XOR32_REG_IMM - dst_reg & 8\n");
if (is_imm8(imm_data)) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x83, 0xc0 | RM_OP_XOR | (dst_reg & 7), imm_data & 0xff); /*XOR dst_reg, imm_data*/
} else if (dst_reg == REG_EAX) {
codegen_alloc_bytes(block, 5);
codegen_addbyte(block, 0x35); /*XOR EAX, imm_data*/
codegen_addlong(block, imm_data);
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0x81, 0xc0 | RM_OP_XOR | (dst_reg & 7)); /*XOR dst_reg, imm_data*/
codegen_addlong(block, imm_data);
}
}
void
host_x86_XOR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_XOR8_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x30, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*XOR dst_reg, src_reg*/
}
void
host_x86_XOR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_XOR16_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x66, 0x31, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*XOR dst_reg, src_reg*/
}
void
host_x86_XOR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
if ((dst_reg & 8) || (src_reg & 8))
fatal("host_x86_XOR32_REG_IMM - dst_reg & 8\n");
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0x31, 0xc0 | (dst_reg & 7) | ((src_reg & 7) << 3)); /*XOR dst_reg, src_reg*/
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_ops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 21,116 |
```objective-c
#define COND_SHIFT 28
#define COND_EQ (0x0 << COND_SHIFT)
#define COND_NE (0x1 << COND_SHIFT)
#define COND_CS (0x2 << COND_SHIFT)
#define COND_CC (0x3 << COND_SHIFT)
#define COND_MI (0x4 << COND_SHIFT)
#define COND_PL (0x5 << COND_SHIFT)
#define COND_VS (0x6 << COND_SHIFT)
#define COND_VC (0x7 << COND_SHIFT)
#define COND_HI (0x8 << COND_SHIFT)
#define COND_LS (0x9 << COND_SHIFT)
#define COND_GE (0xa << COND_SHIFT)
#define COND_LT (0xb << COND_SHIFT)
#define COND_GT (0xc << COND_SHIFT)
#define COND_LE (0xd << COND_SHIFT)
#define COND_AL (0xe << COND_SHIFT)
void host_arm_ADD_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
#define host_arm_ADD_REG(block, dst_reg, src_reg_n, src_reg_m) host_arm_ADD_REG_LSL(block, dst_reg, src_reg_n, src_reg_m, 0)
void host_arm_ADD_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_ADD_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_AND_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_AND_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_AND_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_B(codeblock_t *block, uintptr_t dest_addr);
void host_arm_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width);
void host_arm_BIC_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_BIC_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_BIC_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_BL(codeblock_t *block, uintptr_t dest_addr);
void host_arm_BL_r1(codeblock_t *block, uintptr_t dest_addr);
void host_arm_BLX(codeblock_t *block, int addr_reg);
uint32_t *host_arm_BCC_(codeblock_t *block);
uint32_t *host_arm_BCS_(codeblock_t *block);
uint32_t *host_arm_BEQ_(codeblock_t *block);
uint32_t *host_arm_BGE_(codeblock_t *block);
uint32_t *host_arm_BGT_(codeblock_t *block);
uint32_t *host_arm_BHI_(codeblock_t *block);
uint32_t *host_arm_BLE_(codeblock_t *block);
uint32_t *host_arm_BLS_(codeblock_t *block);
uint32_t *host_arm_BLT_(codeblock_t *block);
uint32_t *host_arm_BMI_(codeblock_t *block);
uint32_t *host_arm_BNE_(codeblock_t *block);
uint32_t *host_arm_BPL_(codeblock_t *block);
uint32_t *host_arm_BVC_(codeblock_t *block);
uint32_t *host_arm_BVS_(codeblock_t *block);
void host_arm_BEQ(codeblock_t *block, uintptr_t dest_addr);
void host_arm_BNE(codeblock_t *block, uintptr_t dest_addr);
void host_arm_BX(codeblock_t *block, int addr_reg);
void host_arm_CMN_IMM(codeblock_t *block, int src_reg, uint32_t imm);
void host_arm_CMN_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift);
void host_arm_CMP_IMM(codeblock_t *block, int src_reg, uint32_t imm);
#define host_arm_CMP_REG(block, src_reg_n, src_reg_m) host_arm_CMP_REG_LSL(block, src_reg_n, src_reg_m, 0)
void host_arm_CMP_REG_LSL(codeblock_t *block, int src_reg_n, int src_reg_m, int shift);
void host_arm_EOR_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_EOR_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_LDMIA_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask);
void host_arm_LDR_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset);
void host_arm_LDR_IMM_POST(codeblock_t *block, int dst_reg, int addr_reg, int offset);
#define host_arm_LDR_REG(block, dst_reg, addr_reg, offset_reg) host_arm_LDR_REG_LSL(block, dst_reg, addr_reg, offset_reg, 0)
void host_arm_LDR_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift);
void host_arm_LDRB_ABS(codeblock_t *block, int dst, void *p);
void host_arm_LDRB_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset);
#define host_arm_LDRB_REG(block, dst_reg, addr_reg, offset_reg) host_arm_LDRB_REG_LSL(block, dst_reg, addr_reg, offset_reg, 0)
void host_arm_LDRB_REG_LSL(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg, int shift);
void host_arm_LDRH_IMM(codeblock_t *block, int dst_reg, int addr_reg, int offset);
void host_arm_LDRH_REG(codeblock_t *block, int dst_reg, int addr_reg, int offset_reg);
void host_arm_MOV_IMM(codeblock_t *block, int dst_reg, uint32_t imm);
#define host_arm_MOV_REG(block, dst_reg, src_reg) host_arm_MOV_REG_LSL(block, dst_reg, src_reg, 0)
void host_arm_MOV_REG_ASR(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm_MOV_REG_ASR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg);
void host_arm_MOV_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm_MOV_REG_LSL_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg);
void host_arm_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm_MOV_REG_LSR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg);
void host_arm_MOV_REG_ROR(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm_MOV_REG_ROR_REG(codeblock_t *block, int dst_reg, int src_reg, int shift_reg);
void host_arm_MOVT_IMM(codeblock_t *block, int dst_reg, uint16_t imm);
void host_arm_MOVW_IMM(codeblock_t *block, int dst_reg, uint16_t imm);
void host_arm_MVN_REG_LSL(codeblock_t *block, int dst_reg, int src_reg, int shift);
#define host_arm_NOP(block) host_arm_MOV_REG(block, REG_R0, REG_R0)
void host_arm_ORR_IMM_cond(codeblock_t *block, uint32_t cond, int dst_reg, int src_reg, uint32_t imm);
void host_arm_ORR_REG_LSL_cond(codeblock_t *block, uint32_t cond, int dst_reg, int src_reg_n, int src_reg_m, int shift);
#define host_arm_ORR_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_AL, dst_reg, src_reg, imm)
#define host_arm_ORR_REG_LSL(block, dst_reg, src_reg_a, src_reg_b, shift) host_arm_ORR_REG_LSL_cond(block, COND_AL, dst_reg, src_reg_a, src_reg_b, shift)
#define host_arm_ORRCC_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_CC, dst_reg, src_reg, imm)
#define host_arm_ORREQ_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_EQ, dst_reg, src_reg, imm)
#define host_arm_ORRVS_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_VS, dst_reg, src_reg, imm)
void host_arm_RSB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_RSB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_RSB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_STMDB_WB(codeblock_t *block, int addr_reg, uint32_t reg_mask);
void host_arm_STR_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset);
void host_arm_STR_IMM_WB(codeblock_t *block, int src_reg, int addr_reg, int offset);
#define host_arm_STR_REG(block, src_reg, addr_reg, offset_reg) host_arm_STR_REG_LSL(block, src_reg, addr_reg, offset_reg, 0)
void host_arm_STR_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift);
void host_arm_STRB_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset);
#define host_arm_STRB_REG(block, src_reg, addr_reg, offset_reg) host_arm_STRB_REG_LSL(block, src_reg, addr_reg, offset_reg, 0)
void host_arm_STRB_REG_LSL(codeblock_t *block, int src_reg, int addr_reg, int offset_reg, int shift);
void host_arm_STRH_IMM(codeblock_t *block, int src_reg, int addr_reg, int offset);
void host_arm_STRH_REG(codeblock_t *block, int src_reg, int addr_reg, int offset_reg);
void host_arm_SUB_IMM(codeblock_t *block, int dst_reg, int src_reg, uint32_t imm);
void host_arm_SUB_REG_LSL(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_SUB_REG_LSR(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m, int shift);
void host_arm_SXTB(codeblock_t *block, int dst_reg, int src_reg, int rotate);
void host_arm_SXTH(codeblock_t *block, int dst_reg, int src_reg, int rotate);
void host_arm_TST_IMM(codeblock_t *block, int src_reg1, uint32_t imm);
void host_arm_TST_REG(codeblock_t *block, int src_reg1, int src_reg2);
void host_arm_UADD8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_arm_UADD16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_arm_USUB8(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_arm_USUB16(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_arm_UXTB(codeblock_t *block, int dst_reg, int src_reg, int rotate);
void host_arm_UXTH(codeblock_t *block, int dst_reg, int src_reg, int rotate);
void host_arm_VABS_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VADD_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VADD_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VADD_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VADD_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VADD_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VAND_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VBIC_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCMP_D(codeblock_t *block, int src_reg_d, int src_reg_m);
void host_arm_VCEQ_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCEQ_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCEQ_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCEQ_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCGE_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCGT_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCGT_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCGT_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCGT_S32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VCHS_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_D_IS(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_D_S(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_F32_S32(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_IS_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_S32_F32(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVT_S_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VCVTR_IS_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VDIV_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VDIV_S(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VDUP_32(codeblock_t *block, int dst_reg, int src_reg_m, int imm);
void host_arm_VEOR_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VLDR_D(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm_VLDR_S(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm_VMOV_32_S(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VMOV_64_D(codeblock_t *block, int dest_reg_low, int dest_reg_high, int src_reg);
void host_arm_VMOV_D_64(codeblock_t *block, int dest_reg, int src_reg_low, int src_reg_high);
void host_arm_VMOV_S_32(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VMOV_D_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VMOVN_I32(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VMOVN_I64(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VMRS_APSR(codeblock_t *block);
void host_arm_VMSR_FPSCR(codeblock_t *block, int src_reg);
void host_arm_VMAX_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VMIN_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VMOV_F32_ONE(codeblock_t *block, int dst_reg);
void host_arm_VMUL_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VMUL_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VMUL_S16(codeblock_t *block, int dest_reg, int src_reg_n, int src_reg_m);
void host_arm_VMULL_S16(codeblock_t *block, int dest_reg, int src_reg_n, int src_reg_m);
void host_arm_VNEG_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VORR_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VPADDL_S16(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VPADDL_S32(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VPADDL_Q_S32(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VQADD_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQADD_U8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQADD_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQADD_U16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQSUB_S8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQSUB_U8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQSUB_S16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQSUB_U16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VQMOVN_S16(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VQMOVN_S32(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VQMOVN_U16(codeblock_t *block, int dst_reg, int src_reg);
void host_arm_VSHL_D_IMM_16(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHL_D_IMM_32(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHL_D_IMM_64(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_S16(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_S32(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_S64(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_U16(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_U32(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHR_D_U64(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSHRN_32(codeblock_t *block, int dest_reg, int src_reg, int shift);
void host_arm_VSQRT_D(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VSQRT_S(codeblock_t *block, int dest_reg, int src_reg);
void host_arm_VSTR_D(codeblock_t *block, int src_reg, int base_reg, int offset);
void host_arm_VSTR_S(codeblock_t *block, int src_reg, int base_reg, int offset);
void host_arm_VSUB_D(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VSUB_F32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VSUB_S(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VSUB_I8(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VSUB_I16(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VSUB_I32(codeblock_t *block, int dst_reg, int src_reg_n, int src_reg_m);
void host_arm_VZIP_D8(codeblock_t *block, int d_reg, int m_reg);
void host_arm_VZIP_D16(codeblock_t *block, int d_reg, int m_reg);
void host_arm_VZIP_D32(codeblock_t *block, int d_reg, int m_reg);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,796 |
```objective-c
void host_arm64_ADD_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_ADD_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_ADD_REG_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_ADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ADD_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ADDX_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint64_t imm_data);
void host_arm64_ADDP_V4S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ADR(codeblock_t *block, int dst_reg, int offset);
void host_arm64_AND_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_AND_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_AND_REG_ASR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_AND_REG_ROR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_AND_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ANDS_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_ASR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg);
void host_arm64_B(codeblock_t *block, void *dest);
void host_arm64_BFI(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width);
void host_arm64_BLR(codeblock_t *block, int addr_reg);
void host_arm64_BEQ(codeblock_t *block, void *dest);
uint32_t *host_arm64_BCC_(codeblock_t *block);
uint32_t *host_arm64_BCS_(codeblock_t *block);
uint32_t *host_arm64_BEQ_(codeblock_t *block);
uint32_t *host_arm64_BGE_(codeblock_t *block);
uint32_t *host_arm64_BGT_(codeblock_t *block);
uint32_t *host_arm64_BHI_(codeblock_t *block);
uint32_t *host_arm64_BLE_(codeblock_t *block);
uint32_t *host_arm64_BLS_(codeblock_t *block);
uint32_t *host_arm64_BLT_(codeblock_t *block);
uint32_t *host_arm64_BMI_(codeblock_t *block);
uint32_t *host_arm64_BNE_(codeblock_t *block);
uint32_t *host_arm64_BPL_(codeblock_t *block);
uint32_t *host_arm64_BVC_(codeblock_t *block);
uint32_t *host_arm64_BVS_(codeblock_t *block);
void host_arm64_branch_set_offset(uint32_t *opcode, void *dest);
void host_arm64_BR(codeblock_t *block, int addr_reg);
void host_arm64_BIC_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CBNZ(codeblock_t *block, int reg, uintptr_t dest);
void host_arm64_CMEQ_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMEQ_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMEQ_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMGT_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMGT_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMGT_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CMN_IMM(codeblock_t *block, int src_n_reg, uint32_t imm_data);
void host_arm64_CMNX_IMM(codeblock_t *block, int src_n_reg, uint64_t imm_data);
void host_arm64_CMP_IMM(codeblock_t *block, int src_n_reg, uint32_t imm_data);
void host_arm64_CMPX_IMM(codeblock_t *block, int src_n_reg, uint64_t imm_data);
#define host_arm64_CMP_REG(block, src_n_reg, src_m_reg) host_arm64_CMP_REG_LSL(block, src_n_reg, src_m_reg, 0)
void host_arm64_CMP_REG_LSL(codeblock_t *block, int src_n_reg, int src_m_reg, int shift);
void host_arm64_CSEL_CC(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CSEL_EQ(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_CSEL_VS(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_DUP_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int element);
void host_arm64_EOR_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_EOR_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_EOR_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FABS_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FADD_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FADD_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FCMEQ_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FCMGE_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FCMGT_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FCMP_D(codeblock_t *block, int src_n_reg, int src_m_reg);
void host_arm64_FDIV_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FDIV_S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FMAX_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FMIN_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FMUL_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FMUL_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FSUB_D(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FSUB_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_FCVT_D_S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVT_S_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTMS_W_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTMS_X_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTNS_W_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTNS_X_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTPS_W_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTPS_X_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTZS_W_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTZS_X_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FCVTZS_V2S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_D_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_D_Q(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_Q_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_S_W(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_W_S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FMOV_S_ONE(codeblock_t *block, int dst_reg);
void host_arm64_FNEG_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FRINTX_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FSQRT_D(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_FSQRT_S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_LDP_POSTIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset);
void host_arm64_LDR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_LDR_IMM_X(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_LDR_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDR_REG_X(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDR_REG_F32(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDR_IMM_F64(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_LDR_REG_F64(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDR_REG_F64_S(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDRB_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_LDRB_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDRH_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_LDRH_REG(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LDRX_REG_LSL3(codeblock_t *block, int dest_reg, int base_reg, int offset_reg);
void host_arm64_LSL(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg);
void host_arm64_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg);
void host_arm64_MOV_REG_ASR(codeblock_t *block, int dst_reg, int src_m_reg, int shift);
void host_arm64_MOV_REG(codeblock_t *block, int dst_reg, int src_m_reg, int shift);
void host_arm64_MOV_REG_LSR(codeblock_t *block, int dst_reg, int src_m_reg, int shift);
void host_arm64_MOV_REG_ROR(codeblock_t *block, int dst_reg, int src_m_reg, int shift);
void host_arm64_MOVX_IMM(codeblock_t *block, int reg, uint64_t imm_data);
void host_arm64_MOVX_REG(codeblock_t *block, int dst_reg, int src_m_reg, int shift);
void host_arm64_MOVZ_IMM(codeblock_t *block, int reg, uint32_t imm_data);
void host_arm64_MOVK_IMM(codeblock_t *block, int reg, uint32_t imm_data);
void host_arm64_MSR_FPCR(codeblock_t *block, int src_reg);
void host_arm64_MUL_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_NOP(codeblock_t *block);
void host_arm64_ORR_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_ORR_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_ORR_REG_V(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_RET(codeblock_t *block, int reg);
void host_arm64_ROR(codeblock_t *block, int dst_reg, int src_n_reg, int shift_reg);
void host_arm64_SADDLP_V2S_4H(codeblock_t *block, int dst_reg, int src_n_reg);
void host_arm64_SBFX(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width);
void host_arm64_SCVTF_D_Q(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_SCVTF_D_W(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_SCVTF_V2S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_SQADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SQADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SQSUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SQSUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_SQXTN_V4H_4S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_SHL_V4H(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_SHL_V2S(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_SHL_V2D(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_SHRN_V4H_4S(codeblock_t *block, int dst_reg, int src_n_reg, int shift);
void host_arm64_SMULL_V4S_4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SSHR_V4H(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_SSHR_V2S(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_SSHR_V2D(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_STP_PREIDX_X(codeblock_t *block, int src_reg1, int src_reg2, int base_reg, int offset);
void host_arm64_STR_IMM_W(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_STR_IMM_Q(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_STR_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_STR_REG_F32(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_STR_IMM_F64(codeblock_t *block, int src_reg, int base_reg, int offset);
void host_arm64_STR_REG_F64(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_STR_REG_F64_S(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_STRB_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_STRB_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_STRH_IMM(codeblock_t *block, int dest_reg, int base_reg, int offset);
void host_arm64_STRH_REG(codeblock_t *block, int src_reg, int base_reg, int offset_reg);
void host_arm64_SUB_IMM(codeblock_t *block, int dst_reg, int src_n_reg, uint32_t imm_data);
void host_arm64_SUB_REG(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_SUB_REG_LSR(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg, int shift);
void host_arm64_SUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_SUB_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
uint32_t *host_arm64_TBNZ(codeblock_t *block, int reg, int bit);
#define host_arm64_TST_IMM(block, src_n_reg, imm_data) host_arm64_ANDS_IMM(block, REG_XZR, src_n_reg, imm_data)
void host_arm64_UBFX(codeblock_t *block, int dst_reg, int src_reg, int lsb, int width);
void host_arm64_UQADD_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_UQADD_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_UQSUB_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_UQSUB_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_UQXTN_V8B_8H(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_UQXTN_V4H_4S(codeblock_t *block, int dst_reg, int src_reg);
void host_arm64_USHR_V4H(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_USHR_V2S(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_USHR_V2D(codeblock_t *block, int dst_reg, int src_reg, int shift);
void host_arm64_ZIP1_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ZIP1_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ZIP1_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ZIP2_V8B(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ZIP2_V4H(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_ZIP2_V2S(codeblock_t *block, int dst_reg, int src_n_reg, int src_m_reg);
void host_arm64_call(codeblock_t *block, void *dst_addr);
void host_arm64_jump(codeblock_t *block, uintptr_t dst_addr);
void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
#define in_range7_x(offset) (((offset) >= -0x200) && ((offset) < (0x200)) && !((offset) &7))
#define in_range12_b(offset) (((offset) >= 0) && ((offset) < 0x1000))
#define in_range12_h(offset) (((offset) >= 0) && ((offset) < 0x2000) && !((offset) &1))
#define in_range12_w(offset) (((offset) >= 0) && ((offset) < 0x4000) && !((offset) &3))
#define in_range12_q(offset) (((offset) >= 0) && ((offset) < 0x8000) && !((offset) &7))
void codegen_direct_read_8(codeblock_t *block, int host_reg, void *p);
void codegen_alloc(codeblock_t *block, int size);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,807 |
```objective-c
uint32_t ropC0(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropC1_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropC1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD0(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD1_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD1_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD2(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD3_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropD3_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSHLD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSHLD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSHRD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSHRD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_shift.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 565 |
```objective-c
uint32_t ropFADD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFADDr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFADDP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOM(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMPP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIV(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVRr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVRP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFMUL(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFMULr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFMULP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBRr(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBRP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFUCOM(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFUCOMP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFUCOMPP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFADDs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFADDd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMPs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCOMPd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVRs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFDIVRd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFMULs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFMULd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBRs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSUBRd(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIADDl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIADDw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFICOMl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFICOMw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFICOMPl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFICOMPw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIDIVl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIDIVw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIDIVRl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIDIVRw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIMULl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFIMULw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISUBl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISUBw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISUBRl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISUBRw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFABS(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFCHS(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSQRT(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFTST(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_arith.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,596 |
```objective-c
uint32_t ropFFREE(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFST(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTCW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFSTSW_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFXCH(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_misc.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 342 |
```objective-c
#include "386_common.h"
#include "codegen_backend.h"
static inline int
LOAD_SP_WITH_OFFSET(ir_data_t *ir, int offset)
{
if (stack32) {
if (offset) {
uop_ADD_IMM(ir, IREG_eaaddr, IREG_ESP, offset);
return IREG_eaaddr;
} else
return IREG_ESP;
} else {
if (offset) {
uop_ADD_IMM(ir, IREG_eaaddr_W, IREG_SP, offset);
uop_MOVZX(ir, IREG_eaaddr, IREG_eaaddr_W);
return IREG_eaaddr;
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
return IREG_eaaddr;
}
}
}
static inline int
LOAD_SP(ir_data_t *ir)
{
return LOAD_SP_WITH_OFFSET(ir, 0);
}
static inline void
ADD_SP(ir_data_t *ir, int offset)
{
if (stack32)
uop_ADD_IMM(ir, IREG_ESP, IREG_ESP, offset);
else
uop_ADD_IMM(ir, IREG_SP, IREG_SP, offset);
}
static inline void
SUB_SP(ir_data_t *ir, int offset)
{
if (stack32)
uop_SUB_IMM(ir, IREG_ESP, IREG_ESP, offset);
else
uop_SUB_IMM(ir, IREG_SP, IREG_SP, offset);
}
static inline void
fpu_POP(codeblock_t *block, ir_data_t *ir)
{
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP + 1);
else
uop_ADD_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 1);
}
static inline void
fpu_POP2(codeblock_t *block, ir_data_t *ir)
{
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP + 2);
else
uop_ADD_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 2);
}
static inline void
fpu_PUSH(codeblock_t *block, ir_data_t *ir)
{
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP - 1);
else
uop_SUB_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 1);
}
static inline void
CHECK_SEG_LIMITS(codeblock_t *block, ir_data_t *ir, x86seg *seg, int addr_reg, int end_offset)
{
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) || (seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
return;
uop_CMP_JB(ir, addr_reg, ireg_seg_limit_low(seg), codegen_gpf_rout);
if (end_offset) {
uop_ADD_IMM(ir, IREG_temp3, addr_reg, end_offset);
uop_CMP_JNBE(ir, IREG_temp3, ireg_seg_limit_high(seg), codegen_gpf_rout);
} else
uop_CMP_JNBE(ir, addr_reg, ireg_seg_limit_high(seg), codegen_gpf_rout);
}
static inline void
LOAD_IMMEDIATE_FROM_RAM_8(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
uop_MOVZX_REG_PTR_8(ir, dest_reg, get_ram_ptr(addr));
}
void LOAD_IMMEDIATE_FROM_RAM_16_unaligned(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr);
static inline void
LOAD_IMMEDIATE_FROM_RAM_16(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
if ((addr & 0xfff) == 0xfff)
LOAD_IMMEDIATE_FROM_RAM_16_unaligned(block, ir, dest_reg, addr);
else
uop_MOVZX_REG_PTR_16(ir, dest_reg, get_ram_ptr(addr));
}
void LOAD_IMMEDIATE_FROM_RAM_32_unaligned(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr);
static inline void
LOAD_IMMEDIATE_FROM_RAM_32(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
if ((addr & 0xfff) >= 0xffd)
LOAD_IMMEDIATE_FROM_RAM_32_unaligned(block, ir, dest_reg, addr);
else
uop_MOV_REG_PTR(ir, dest_reg, get_ram_ptr(addr));
}
int codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, uint32_t next_pc, uint32_t dest_addr);
static inline int
codegen_can_unroll(codeblock_t *block, ir_data_t *ir, uint32_t next_pc, uint32_t dest_addr)
{
if (block->flags & CODEBLOCK_BYTE_MASK)
return 0;
/*Is dest within block?*/
if (dest_addr > next_pc)
return 0;
if ((cs + dest_addr) < block->pc)
return 0;
return codegen_can_unroll_full(block, ir, next_pc, dest_addr);
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_helpers.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,194 |
```c
#if defined(__unix__) || defined(__APPLE__) || defined(__HAIKU__)
# include <sys/mman.h>
# include <unistd.h>
# include <stdlib.h>
#endif
#if defined WIN32 || defined _WIN32 || defined _WIN32
# include <windows.h>
#endif
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "codegen.h"
#include "codegen_allocator.h"
typedef struct mem_block_t {
uint32_t offset; /*Offset into mem_block_alloc*/
uint32_t next;
uint16_t code_block;
} mem_block_t;
static mem_block_t mem_blocks[MEM_BLOCK_NR];
static uint32_t mem_block_free_list;
static uint8_t *mem_block_alloc = NULL;
int codegen_allocator_usage = 0;
void
codegen_allocator_init(void)
{
#if defined WIN32 || defined _WIN32 || defined _WIN32
mem_block_alloc = VirtualAlloc(NULL, MEM_BLOCK_NR * MEM_BLOCK_SIZE, MEM_COMMIT, PAGE_EXECUTE_READWRITE);
/* TODO: check deployment target: older Intel-based versions of macOS don't play
nice with MAP_JIT. */
#elif defined(__APPLE__) && defined(MAP_JIT)
mem_block_alloc = mmap(0, MEM_BLOCK_NR * MEM_BLOCK_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE | MAP_JIT, -1, 0);
#else
mem_block_alloc = mmap(0, MEM_BLOCK_NR * MEM_BLOCK_SIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
#endif
for (uint32_t c = 0; c < MEM_BLOCK_NR; c++) {
mem_blocks[c].offset = c * MEM_BLOCK_SIZE;
mem_blocks[c].code_block = BLOCK_INVALID;
if (c < MEM_BLOCK_NR - 1)
mem_blocks[c].next = c + 2;
else
mem_blocks[c].next = 0;
}
mem_block_free_list = 1;
}
mem_block_t *
codegen_allocator_allocate(mem_block_t *parent, int code_block)
{
mem_block_t *block;
uint32_t block_nr;
while (!mem_block_free_list) {
/*Pick a random memory block and free the owning code block*/
block_nr = rand() & MEM_BLOCK_MASK;
block = &mem_blocks[block_nr];
if (block->code_block && block->code_block != code_block)
codegen_delete_block(&codeblock[block->code_block]);
}
/*Remove from free list*/
block_nr = mem_block_free_list;
block = &mem_blocks[block_nr - 1];
mem_block_free_list = block->next;
block->code_block = code_block;
if (parent) {
/*Add to parent list*/
block->next = parent->next;
parent->next = block_nr;
} else
block->next = 0;
codegen_allocator_usage++;
return block;
}
void
codegen_allocator_free(mem_block_t *block)
{
int block_nr = (((uintptr_t) block - (uintptr_t) mem_blocks) / sizeof(mem_block_t)) + 1;
while (1) {
int next_block_nr = block->next;
codegen_allocator_usage--;
block->next = mem_block_free_list;
block->code_block = BLOCK_INVALID;
mem_block_free_list = block_nr;
block_nr = next_block_nr;
if (block_nr)
block = &mem_blocks[block_nr - 1];
else
break;
}
}
uint8_t *
codeblock_allocator_get_ptr(mem_block_t *block)
{
return &mem_block_alloc[block->offset];
}
void
codegen_allocator_clean_blocks(UNUSED(struct mem_block_t *block))
{
#if defined __ARM_EABI__ || defined _ARM_ || defined __aarch64__ || defined _M_ARM || defined _M_ARM64
while (1) {
# ifndef _MSC_VER
__clear_cache(&mem_block_alloc[block->offset], &mem_block_alloc[block->offset + MEM_BLOCK_SIZE]);
# else
FlushInstructionCache(GetCurrentProcess(), &mem_block_alloc[block->offset], MEM_BLOCK_SIZE);
# endif
if (block->next)
block = &mem_blocks[block->next - 1];
else
break;
}
#endif
}
``` | /content/code_sandbox/src/codegen_new/codegen_allocator.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 979 |
```objective-c
#define JMP_LEN_BYTES 5
static inline void
codegen_addbyte(UNUSED(codeblock_t *block), uint8_t val)
{
if (block_pos >= BLOCK_MAX)
fatal("codegen_addbyte over! %i\n", block_pos);
block_write_data[block_pos++] = val;
}
static inline void
codegen_addbyte2(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb)
{
if (block_pos > (BLOCK_MAX - 2))
fatal("codegen_addbyte2 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
}
static inline void
codegen_addbyte3(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb, uint8_t valc)
{
if (block_pos > (BLOCK_MAX - 3))
fatal("codegen_addbyte3 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
}
static inline void
codegen_addbyte4(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald)
{
if (block_pos > (BLOCK_MAX - 4))
fatal("codegen_addbyte4 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
block_write_data[block_pos++] = vald;
}
static inline void
codegen_addword(UNUSED(codeblock_t *block), uint16_t val)
{
if (block_pos > (BLOCK_MAX - 2))
fatal("codegen_addword over! %i\n", block_pos);
*(uint16_t *) &block_write_data[block_pos] = val;
block_pos += 2;
}
static inline void
codegen_addlong(UNUSED(codeblock_t *block), uint32_t val)
{
if (block_pos > (BLOCK_MAX - 4))
fatal("codegen_addlong over! %i\n", block_pos);
*(uint32_t *) &block_write_data[block_pos] = val;
block_pos += 4;
}
static inline void
codegen_addquad(UNUSED(codeblock_t *block), uint64_t val)
{
if (block_pos > (BLOCK_MAX - 8))
fatal("codegen_addquad over! %i\n", block_pos);
*(uint64_t *) &block_write_data[block_pos] = val;
block_pos += 8;
}
static void
codegen_allocate_new_block(codeblock_t *block)
{
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
/*Add a jump instruction to the new block*/
codegen_addbyte(block, 0xe9); /*JMP*/
codegen_addlong(block, (uintptr_t) new_ptr - (uintptr_t) &block_write_data[block_pos + 4]);
/*Set write address to start of new block*/
block_pos = 0;
block_write_data = new_ptr;
}
static inline void
codegen_alloc_bytes(codeblock_t *block, int size)
{
if (block_pos > ((BLOCK_MAX - size) - JMP_LEN_BYTES))
codegen_allocate_new_block(block);
}
static inline int
is_imm8(uint32_t imm_data)
{
if (imm_data <= 0x7f || imm_data >= 0xffffff80)
return 1;
return 0;
}
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops_helpers.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 816 |
```objective-c
#include "codegen_ir_defs.h"
ir_data_t *codegen_ir_init(void);
void codegen_ir_set_unroll(int count, int start, int first_instruction);
void codegen_ir_compile(ir_data_t *ir, codeblock_t *block);
``` | /content/code_sandbox/src/codegen_new/codegen_ir.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 51 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_arith.h"
#include "codegen_ops_helpers.h"
static inline void
get_cf(ir_data_t *ir, int dest_reg)
{
uop_CALL_FUNC_RESULT(ir, dest_reg, CF_SET);
}
uint32_t
ropADC_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_ADD_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_ADD(ir, IREG_AL, IREG_AL, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropADC_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_ADD_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_ADD(ir, IREG_AX, IREG_AX, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropADC_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
uop_ADD_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
uop_ADD(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropADC_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADC_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2_B, IREG_temp0_B, IREG_8(src_reg));
uop_ADD(ir, IREG_temp2_B, IREG_temp2_B, IREG_temp1_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADC_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADC_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2_W, IREG_temp0_W, IREG_16(src_reg));
uop_ADD(ir, IREG_temp2_W, IREG_temp2_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADC_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADC_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp2, IREG_temp0, IREG_32(src_reg));
uop_ADD(ir, IREG_temp2, IREG_temp2, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_ADD_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropADD_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_ADD_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropADD_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_ADD(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
uop_ADD_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
codegen_mark_code_present(block, cs + op_pc, 4);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t
ropADD_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp1_B, IREG_temp0_B, IREG_8(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp1_W, IREG_temp0_W, IREG_16(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropADD_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ADD(ir, IREG_temp1, IREG_temp0, IREG_32(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp1);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_SUB_IMM(ir, IREG_flags_res_B, IREG_AL, imm_data);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropCMP_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_SUB_IMM(ir, IREG_flags_res_W, IREG_AX, imm_data);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropCMP_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
uop_SUB_IMM(ir, IREG_flags_res, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropCMP_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_SUB(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_flags_res_B, IREG_temp0_B, IREG_8(src_reg));
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_SUB(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_flags_res_W, IREG_temp0_W, IREG_16(src_reg));
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_flags_res, IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
uop_SUB(ir, IREG_flags_res, IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropCMP_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_flags_res, IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_flags_res, IREG_temp0, IREG_32(src_reg));
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_SUB_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_SUB(ir, IREG_AL, IREG_AL, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropSBB_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_SUB_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_SUB(ir, IREG_AX, IREG_AX, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropSBB_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
fetchdat = fastreadl(cs + op_pc);
get_cf(ir, IREG_temp0);
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
uop_SUB_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
uop_SUB(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropSBB_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2_B, IREG_temp0_B, IREG_8(src_reg));
uop_SUB(ir, IREG_temp2_B, IREG_temp2_B, IREG_temp1_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2_W, IREG_temp0_W, IREG_16(src_reg));
uop_SUB(ir, IREG_temp2_W, IREG_temp2_W, IREG_temp1_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp2_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSBB_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
get_cf(ir, IREG_temp1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp2, IREG_temp0, IREG_32(src_reg));
uop_SUB(ir, IREG_temp2, IREG_temp2, IREG_temp1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp2);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AL);
uop_SUB_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropSUB_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_MOVZX(ir, IREG_flags_op1, IREG_AX);
uop_SUB_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op2, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropSUB_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MOV(ir, IREG_flags_op1, IREG_EAX);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_SUB(ir, IREG_EAX, IREG_EAX, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
uop_SUB_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
uop_MOV_IMM(ir, IREG_flags_op2, fetchdat);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t
ropSUB_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp1_B, IREG_temp0_B, IREG_8(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp1_W, IREG_temp0_W, IREG_16(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_flags_op2, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_flags_op2);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropSUB_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_SUB(ir, IREG_temp1, IREG_temp0, IREG_32(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_temp1);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
rop80(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int skip_immediate = 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uint8_t imm = fastreadb(cs + op_pc + 1);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
skip_immediate = 1;
LOAD_IMMEDIATE_FROM_RAM_8(block, ir, IREG_temp0_B, cs + op_pc + 1);
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
} else {
uop_ADD_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x08: /*OR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_OR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
else
uop_OR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
} else {
uop_ADD_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_ADD(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
} else {
uop_SUB_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x20: /*AND*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_AND(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
else
uop_AND_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x28: /*SUB*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
} else {
uop_SUB_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x30: /*XOR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_XOR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
else
uop_XOR_IMM(ir, IREG_8(dest_reg), IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_8(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_B);
} else {
uop_SUB_IMM(ir, IREG_flags_res_B, IREG_8(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uint8_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
codegen_check_seg_read(block, ir, target_seg);
else
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadb(cs + op_pc + 1);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_ADD_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x08: /*OR*/
uop_OR_IMM(ir, IREG_temp0_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_ADD(ir, IREG_temp1_B, IREG_temp1_B, IREG_temp2_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_SUB(ir, IREG_temp1_B, IREG_temp1_B, IREG_temp2_B);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
break;
case 0x28: /*SUB*/
uop_SUB_IMM(ir, IREG_temp1_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
break;
case 0x30: /*XOR*/
uop_XOR_IMM(ir, IREG_temp0_B, IREG_temp0_B, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB_IMM(ir, IREG_flags_res_B, IREG_temp0_B, imm);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB8);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
if (!skip_immediate)
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
rop81_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int skip_immediate = 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uint16_t imm = fastreadw(cs + op_pc + 1);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
skip_immediate = 1;
LOAD_IMMEDIATE_FROM_RAM_16(block, ir, IREG_temp0_W, cs + op_pc + 1);
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
} else {
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x08: /*OR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_OR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
else
uop_OR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
} else {
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
} else {
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20: /*AND*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_AND(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
else
uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x28: /*SUB*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
} else {
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x30: /*XOR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_XOR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
else
uop_XOR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_op2, IREG_temp0_W);
} else {
uop_SUB_IMM(ir, IREG_flags_res_W, IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uint16_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
codegen_check_seg_read(block, ir, target_seg);
else
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadw(cs + op_pc + 1);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
skip_immediate = 1;
LOAD_IMMEDIATE_FROM_RAM_16(block, ir, IREG_temp2_W, cs + op_pc + 1);
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_ADD(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2_W);
else
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOVZX(ir, IREG_flags_op2, IREG_temp2_W);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x08: /*OR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2_W);
else
uop_OR_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp3);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_ADD(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2_W);
else
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_ADD(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp3_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOVZX(ir, IREG_flags_op2, IREG_temp2_W);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp3);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_SUB(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2_W);
else
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp3_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOVZX(ir, IREG_flags_op2, IREG_temp2_W);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x20: /*AND*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_AND(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2_W);
else
uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_SUB(ir, IREG_temp1_W, IREG_temp0_W, IREG_temp2_W);
else
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOVZX(ir, IREG_flags_op2, IREG_temp2_W);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x30: /*XOR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_XOR(ir, IREG_temp0_W, IREG_temp0_W, IREG_temp2_W);
else
uop_XOR_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_MOVZX(ir, IREG_flags_op2, IREG_temp2_W);
uop_SUB(ir, IREG_flags_res_W, IREG_temp0_W, IREG_temp2_W);
} else {
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB_IMM(ir, IREG_flags_res_W, IREG_temp0_W, imm);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
if (!skip_immediate)
codegen_mark_code_present(block, cs + op_pc + 1, 2);
return op_pc + 3;
}
uint32_t
rop81_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int skip_immediate = 0;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uint32_t imm = fastreadl(cs + op_pc + 1);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
skip_immediate = 1;
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc + 1);
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x08: /*OR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_OR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
else
uop_OR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20: /*AND*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_AND(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
else
uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x28: /*SUB*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x30: /*XOR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_XOR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
else
uop_XOR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x38: /*CMP*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_SUB(ir, IREG_flags_res, IREG_32(dest_reg), IREG_temp0);
uop_MOV(ir, IREG_flags_op2, IREG_temp0);
} else {
uop_SUB_IMM(ir, IREG_flags_res, IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uint32_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
codegen_check_seg_read(block, ir, target_seg);
else
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadl(cs + op_pc + 1);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
skip_immediate = 1;
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp2, cs + op_pc + 1);
}
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_ADD(ir, IREG_temp1, IREG_temp0, IREG_temp2);
else
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x08: /*OR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_temp2);
else
uop_OR_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp3);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_ADD(ir, IREG_temp1, IREG_temp0, IREG_temp2);
else
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp3);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp3);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_SUB(ir, IREG_temp1, IREG_temp0, IREG_temp2);
else
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp3);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x20: /*AND*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_AND(ir, IREG_temp0, IREG_temp0, IREG_temp2);
else
uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_SUB(ir, IREG_temp1, IREG_temp0, IREG_temp2);
else
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
else
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x30: /*XOR*/
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
uop_XOR(ir, IREG_temp0, IREG_temp0, IREG_temp2);
else
uop_XOR_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
uop_MOV(ir, IREG_flags_op2, IREG_temp2);
uop_SUB(ir, IREG_flags_res, IREG_temp0, IREG_temp2);
} else {
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB_IMM(ir, IREG_flags_res, IREG_temp0, imm);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
if (!skip_immediate)
codegen_mark_code_present(block, cs + op_pc + 1, 4);
return op_pc + 5;
}
uint32_t
rop83_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uint16_t imm = (int16_t) (int8_t) fastreadb(cs + op_pc + 1);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x08: /*OR*/
uop_OR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_ADD_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp1_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x28: /*SUB*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SUB_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x30: /*XOR*/
uop_XOR_IMM(ir, IREG_16(dest_reg), IREG_16(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_16(dest_reg));
uop_SUB_IMM(ir, IREG_flags_res_W, IREG_16(dest_reg), imm);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uint16_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
codegen_check_seg_read(block, ir, target_seg);
else
codegen_check_seg_write(block, ir, target_seg);
imm = (int16_t) (int8_t) fastreadb(cs + op_pc + 1);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x08: /*OR*/
uop_OR_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_ADD(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_SUB(ir, IREG_temp1_W, IREG_temp1_W, IREG_temp2_W);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
uop_SUB_IMM(ir, IREG_temp1_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_W);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_W);
break;
case 0x30: /*XOR*/
uop_XOR_IMM(ir, IREG_temp0_W, IREG_temp0_W, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_W);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB_IMM(ir, IREG_flags_res_W, IREG_temp0_W, imm);
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB16);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
rop83_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uint32_t imm = (int32_t) (int8_t) fastreadb(cs + op_pc + 1);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x08: /*OR*/
uop_OR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_ADD_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_ADD(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x28: /*SUB*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x30: /*XOR*/
uop_XOR_IMM(ir, IREG_32(dest_reg), IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
break;
case 0x38: /*CMP*/
uop_MOV(ir, IREG_flags_op1, IREG_32(dest_reg));
uop_SUB_IMM(ir, IREG_flags_res, IREG_32(dest_reg), imm);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
break;
default:
return 0;
}
} else {
x86seg *target_seg;
uint32_t imm;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
if ((fetchdat & 0x38) == 0x38) /*CMP*/
codegen_check_seg_read(block, ir, target_seg);
else
codegen_check_seg_write(block, ir, target_seg);
imm = (int32_t) (int8_t) fastreadb(cs + op_pc + 1);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
switch (fetchdat & 0x38) {
case 0x00: /*ADD*/
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADD32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x08: /*OR*/
uop_OR_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x10: /*ADC*/
get_cf(ir, IREG_temp2);
uop_ADD_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_ADD(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ADC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x18: /*SBB*/
get_cf(ir, IREG_temp2);
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_SUB(ir, IREG_temp1, IREG_temp1, IREG_temp2);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SBC32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x20: /*AND*/
uop_AND_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
uop_SUB_IMM(ir, IREG_temp1, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1);
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
uop_MOV(ir, IREG_flags_res, IREG_temp1);
break;
case 0x30: /*XOR*/
uop_XOR_IMM(ir, IREG_temp0, IREG_temp0, imm);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
uop_MOV(ir, IREG_flags_op1, IREG_temp0);
uop_MOV_IMM(ir, IREG_flags_op2, imm);
uop_SUB_IMM(ir, IREG_flags_res, IREG_temp0, imm);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_SUB32);
break;
default:
return 0;
}
}
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
static void
rebuild_c(ir_data_t *ir)
{
int needs_rebuild = 1;
if (codegen_flags_changed) {
switch (cpu_state.flags_op) {
case FLAGS_INC8:
case FLAGS_INC16:
case FLAGS_INC32:
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:
needs_rebuild = 0;
break;
default:
break;
}
}
if (needs_rebuild) {
uop_CALL_FUNC(ir, flags_rebuild_c);
}
}
uint32_t
ropINC_r16(UNUSED(UNUSED(codeblock_t *block)), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
rebuild_c(ir);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(opcode & 7));
uop_ADD_IMM(ir, IREG_16(opcode & 7), IREG_16(opcode & 7), 1);
uop_MOVZX(ir, IREG_flags_res, IREG_16(opcode & 7));
uop_MOV_IMM(ir, IREG_flags_op2, 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC16);
codegen_flags_changed = 1;
return op_pc;
}
uint32_t
ropINC_r32(UNUSED(UNUSED(codeblock_t *block)), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
rebuild_c(ir);
uop_MOV(ir, IREG_flags_op1, IREG_32(opcode & 7));
uop_ADD_IMM(ir, IREG_32(opcode & 7), IREG_32(opcode & 7), 1);
uop_MOV(ir, IREG_flags_res, IREG_32(opcode & 7));
uop_MOV_IMM(ir, IREG_flags_op2, 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC32);
codegen_flags_changed = 1;
return op_pc;
}
uint32_t
ropDEC_r16(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
rebuild_c(ir);
uop_MOVZX(ir, IREG_flags_op1, IREG_16(opcode & 7));
uop_SUB_IMM(ir, IREG_16(opcode & 7), IREG_16(opcode & 7), 1);
uop_MOVZX(ir, IREG_flags_res, IREG_16(opcode & 7));
uop_MOV_IMM(ir, IREG_flags_op2, 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC16);
codegen_flags_changed = 1;
return op_pc;
}
uint32_t
ropDEC_r32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
rebuild_c(ir);
uop_MOV(ir, IREG_flags_op1, IREG_32(opcode & 7));
uop_SUB_IMM(ir, IREG_32(opcode & 7), IREG_32(opcode & 7), 1);
uop_MOV(ir, IREG_flags_res, IREG_32(opcode & 7));
uop_MOV_IMM(ir, IREG_flags_op2, 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC32);
codegen_flags_changed = 1;
return op_pc;
}
uint32_t
ropINCDEC(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
codegen_mark_code_present(block, cs + op_pc, 1);
rebuild_c(ir);
if ((fetchdat & 0xc0) == 0xc0) {
uop_MOVZX(ir, IREG_flags_op1, IREG_8(fetchdat & 7));
if (fetchdat & 0x38) {
uop_SUB_IMM(ir, IREG_8(fetchdat & 7), IREG_8(fetchdat & 7), 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC8);
} else {
uop_ADD_IMM(ir, IREG_8(fetchdat & 7), IREG_8(fetchdat & 7), 1);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC8);
}
uop_MOVZX(ir, IREG_flags_res, IREG_8(fetchdat & 7));
uop_MOV_IMM(ir, IREG_flags_op2, 1);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
if (fetchdat & 0x38) {
uop_SUB_IMM(ir, IREG_temp1_B, IREG_temp0_B, 1);
} else {
uop_ADD_IMM(ir, IREG_temp1_B, IREG_temp0_B, 1);
}
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp1_B);
uop_MOVZX(ir, IREG_flags_op1, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp1_B);
uop_MOV_IMM(ir, IREG_flags_op2, 1);
if (fetchdat & 0x38) {
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_DEC8);
} else {
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_INC8);
}
}
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_arith.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 30,579 |
```c
#if defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
# include <stdint.h>
# include <stdlib.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_arm_defs.h"
# include "codegen_backend_arm_ops.h"
# include "codegen_reg.h"
# include "x86.h"
# include "x86seg_common.h"
# include "x86seg.h"
# include "x87_sf.h"
# include "x87.h"
# if defined(__linux__) || defined(__APPLE__)
# include <sys/mman.h>
# include <unistd.h>
# endif
# if defined WIN32 || defined _WIN32 || defined _WIN32
# include <windows.h>
# endif
# include <string.h>
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
void *codegen_mem_load_quad;
void *codegen_mem_load_single;
void *codegen_mem_load_double;
void *codegen_mem_store_byte;
void *codegen_mem_store_word;
void *codegen_mem_store_long;
void *codegen_mem_store_quad;
void *codegen_mem_store_single;
void *codegen_mem_store_double;
void *codegen_fp_round;
void *codegen_gpf_rout;
void *codegen_exit_rout;
host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] = {
{ REG_R4, 0},
{ REG_R5, 0},
{ REG_R6, 0},
{ REG_R7, 0},
{ REG_R8, 0},
{ REG_R9, 0},
{ REG_R11, 0}
};
host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] = {
{ REG_D8, 0},
{ REG_D9, 0},
{ REG_D10, 0},
{ REG_D11, 0},
{ REG_D12, 0},
{ REG_D13, 0},
{ REG_D14, 0},
{ REG_D15, 0}
};
static void
build_load_routine(codeblock_t *block, int size, int is_float)
{
uint32_t *branch_offset;
uint32_t *misaligned_offset;
/*In - R0 = address
Out - R0 = data, R1 = abrt*/
/*MOV R1, R0, LSR #12
MOV R2, #readlookup2
LDR R1, [R2, R1, LSL #2]
CMP R1, #-1
BNE +
LDRB R0, [R1, R0]
MOV R1, #0
MOV PC, LR
* STR LR, [SP, -4]!
BL readmembl
LDRB R1, cpu_state.abrt
LDR PC, [SP], #4
*/
codegen_alloc(block, 80);
host_arm_MOV_REG_LSR(block, REG_R1, REG_R0, 12);
host_arm_MOV_IMM(block, REG_R2, (uint32_t) readlookup2);
host_arm_LDR_REG_LSL(block, REG_R1, REG_R2, REG_R1, 2);
if (size != 1) {
host_arm_TST_IMM(block, REG_R0, size - 1);
misaligned_offset = host_arm_BNE_(block);
}
host_arm_CMP_IMM(block, REG_R1, -1);
branch_offset = host_arm_BEQ_(block);
if (size == 1 && !is_float)
host_arm_LDRB_REG(block, REG_R0, REG_R1, REG_R0);
else if (size == 2 && !is_float)
host_arm_LDRH_REG(block, REG_R0, REG_R1, REG_R0);
else if (size == 4 && !is_float)
host_arm_LDR_REG(block, REG_R0, REG_R1, REG_R0);
else if (size == 4 && is_float) {
host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R1);
host_arm_VLDR_S(block, REG_D_TEMP, REG_R0, 0);
} else if (size == 8) {
host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R1);
host_arm_VLDR_D(block, REG_D_TEMP, REG_R0, 0);
}
host_arm_MOV_IMM(block, REG_R1, 0);
host_arm_MOV_REG(block, REG_PC, REG_LR);
*branch_offset |= ((((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 8) & 0x3fffffc) >> 2;
if (size != 1)
*misaligned_offset |= ((((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 8) & 0x3fffffc) >> 2;
host_arm_STR_IMM_WB(block, REG_LR, REG_HOST_SP, -4);
if (size == 1)
host_arm_BL(block, (uintptr_t) readmembl);
else if (size == 2)
host_arm_BL(block, (uintptr_t) readmemwl);
else if (size == 4)
host_arm_BL(block, (uintptr_t) readmemll);
else if (size == 8)
host_arm_BL(block, (uintptr_t) readmemql);
else
fatal("build_load_routine - unknown size %i\n", size);
if (size == 4 && is_float)
host_arm_VMOV_S_32(block, REG_D_TEMP, REG_R0);
else if (size == 8)
host_arm_VMOV_D_64(block, REG_D_TEMP, REG_R0, REG_R1);
host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
host_arm_LDR_IMM_POST(block, REG_PC, REG_HOST_SP, 4);
}
static void
build_store_routine(codeblock_t *block, int size, int is_float)
{
uint32_t *branch_offset;
uint32_t *misaligned_offset;
/*In - R0 = address
Out - R0 = data, R1 = abrt*/
/*MOV R1, R0, LSR #12
MOV R2, #readlookup2
LDR R1, [R2, R1, LSL #2]
CMP R1, #-1
BNE +
LDRB R0, [R1, R0]
MOV R1, #0
MOV PC, LR
* STR LR, [SP, -4]!
BL readmembl
LDRB R1, cpu_state.abrt
LDR PC, [SP], #4
*/
codegen_alloc(block, 80);
host_arm_MOV_REG_LSR(block, REG_R2, REG_R0, 12);
host_arm_MOV_IMM(block, REG_R3, (uint32_t) writelookup2);
host_arm_LDR_REG_LSL(block, REG_R2, REG_R3, REG_R2, 2);
if (size != 1) {
host_arm_TST_IMM(block, REG_R0, size - 1);
misaligned_offset = host_arm_BNE_(block);
}
host_arm_CMP_IMM(block, REG_R2, -1);
branch_offset = host_arm_BEQ_(block);
if (size == 1 && !is_float)
host_arm_STRB_REG(block, REG_R1, REG_R2, REG_R0);
else if (size == 2 && !is_float)
host_arm_STRH_REG(block, REG_R1, REG_R2, REG_R0);
else if (size == 4 && !is_float)
host_arm_STR_REG(block, REG_R1, REG_R2, REG_R0);
else if (size == 4 && is_float) {
host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R2);
host_arm_VSTR_S(block, REG_D_TEMP, REG_R0, 0);
} else if (size == 8) {
host_arm_ADD_REG(block, REG_R0, REG_R0, REG_R2);
host_arm_VSTR_D(block, REG_D_TEMP, REG_R0, 0);
}
host_arm_MOV_IMM(block, REG_R1, 0);
host_arm_MOV_REG(block, REG_PC, REG_LR);
*branch_offset |= ((((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 8) & 0x3fffffc) >> 2;
if (size != 1)
*misaligned_offset |= ((((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 8) & 0x3fffffc) >> 2;
host_arm_STR_IMM_WB(block, REG_LR, REG_HOST_SP, -4);
if (size == 4 && is_float)
host_arm_VMOV_32_S(block, REG_R1, REG_D_TEMP);
else if (size == 8)
host_arm_VMOV_64_D(block, REG_R2, REG_R3, REG_D_TEMP);
if (size == 1)
host_arm_BL(block, (uintptr_t) writemembl);
else if (size == 2)
host_arm_BL(block, (uintptr_t) writememwl);
else if (size == 4)
host_arm_BL(block, (uintptr_t) writememll);
else if (size == 8)
host_arm_BL_r1(block, (uintptr_t) writememql);
else
fatal("build_store_routine - unknown size %i\n", size);
host_arm_LDRB_ABS(block, REG_R1, &cpu_state.abrt);
host_arm_LDR_IMM_POST(block, REG_PC, REG_HOST_SP, 4);
}
static void
build_loadstore_routines(codeblock_t *block)
{
codegen_mem_load_byte = &block_write_data[block_pos];
build_load_routine(block, 1, 0);
codegen_mem_load_word = &block_write_data[block_pos];
build_load_routine(block, 2, 0);
codegen_mem_load_long = &block_write_data[block_pos];
build_load_routine(block, 4, 0);
codegen_mem_load_quad = &block_write_data[block_pos];
build_load_routine(block, 8, 0);
codegen_mem_load_single = &block_write_data[block_pos];
build_load_routine(block, 4, 1);
codegen_mem_load_double = &block_write_data[block_pos];
build_load_routine(block, 8, 1);
codegen_mem_store_byte = &block_write_data[block_pos];
build_store_routine(block, 1, 0);
codegen_mem_store_word = &block_write_data[block_pos];
build_store_routine(block, 2, 0);
codegen_mem_store_long = &block_write_data[block_pos];
build_store_routine(block, 4, 0);
codegen_mem_store_quad = &block_write_data[block_pos];
build_store_routine(block, 8, 0);
codegen_mem_store_single = &block_write_data[block_pos];
build_store_routine(block, 4, 1);
codegen_mem_store_double = &block_write_data[block_pos];
build_store_routine(block, 8, 1);
}
/*VFP has a specific round-to-zero instruction, and the default rounding mode
is nearest. For round up/down, temporarily change the rounding mode in FPCSR*/
# define FPCSR_ROUNDING_MASK (3 << 22)
# define FPCSR_ROUNDING_UP (1 << 22)
# define FPCSR_ROUNDING_DOWN (2 << 22)
static void
build_fp_round_routine(codeblock_t *block)
{
uint32_t *jump_table;
codegen_alloc(block, 80);
host_arm_MOV_REG(block, REG_TEMP2, REG_LR);
host_arm_MOV_REG(block, REG_LR, REG_TEMP2);
host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.new_fp_control - (uintptr_t) &cpu_state);
host_arm_LDR_REG(block, REG_PC, REG_PC, REG_TEMP);
host_arm_NOP(block);
jump_table = (uint32_t *) &block_write_data[block_pos];
host_arm_NOP(block);
host_arm_NOP(block);
host_arm_NOP(block);
host_arm_NOP(block);
jump_table[X87_ROUNDING_NEAREST] = (uint64_t) (uintptr_t) &block_write_data[block_pos]; // tie even
host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);
jump_table[X87_ROUNDING_UP] = (uint64_t) (uintptr_t) &block_write_data[block_pos]; // pos inf
host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.old_fp_control - (uintptr_t) &cpu_state);
host_arm_BIC_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_MASK);
host_arm_ORR_IMM(block, REG_TEMP2, REG_TEMP2, FPCSR_ROUNDING_UP);
host_arm_VMSR_FPSCR(block, REG_TEMP2);
host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_VMSR_FPSCR(block, REG_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);
jump_table[X87_ROUNDING_DOWN] = (uint64_t) (uintptr_t) &block_write_data[block_pos]; // neg inf
host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.old_fp_control - (uintptr_t) &cpu_state);
host_arm_BIC_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_MASK);
host_arm_ORR_IMM(block, REG_TEMP2, REG_TEMP, FPCSR_ROUNDING_DOWN);
host_arm_VMSR_FPSCR(block, REG_TEMP2);
host_arm_VCVTR_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_VMSR_FPSCR(block, REG_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);
jump_table[X87_ROUNDING_CHOP] = (uint64_t) (uintptr_t) &block_write_data[block_pos]; // zero
host_arm_VCVT_IS_D(block, REG_D_TEMP, REG_D_TEMP);
host_arm_MOV_REG(block, REG_PC, REG_LR);
}
void
codegen_backend_init(void)
{
codeblock_t *block;
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
for (int c = 0; c < BLOCK_SIZE; c++)
codeblock[c].pc = BLOCK_PC_INVALID;
block_current = 0;
block_pos = 0;
block = &codeblock[block_current];
block->head_mem_block = codegen_allocator_allocate(NULL, block_current);
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
block_write_data = block->data;
build_loadstore_routines(&codeblock[block_current]);
# if 0
pclog("block_pos=%i\n", block_pos);
# endif
codegen_fp_round = &block_write_data[block_pos];
build_fp_round_routine(&codeblock[block_current]);
codegen_alloc(block, 80);
codegen_gpf_rout = &block_write_data[block_pos];
host_arm_MOV_IMM(block, REG_R0, 0);
host_arm_MOV_IMM(block, REG_R1, 0);
host_arm_call(block, x86gpf);
codegen_exit_rout = &block_write_data[block_pos];
host_arm_ADD_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
host_arm_LDMIA_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_PC);
block_write_data = NULL;
# if 0
fatal("block_pos=%i\n", block_pos);
# endif
asm("vmrs %0, fpscr\n"
: "=r"(cpu_state.old_fp_control));
if ((cpu_state.old_fp_control >> 22) & 3)
fatal("VFP not in nearest rounding mode\n");
}
void
codegen_set_rounding_mode(int mode)
{
if (mode < 0 || mode > 3)
fatal("codegen_set_rounding_mode - invalid mode\n");
cpu_state.new_fp_control = mode << 2;
}
/*R10 - cpu_state*/
void
codegen_backend_prologue(codeblock_t *block)
{
block_pos = BLOCK_START;
/*Entry code*/
host_arm_STMDB_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_LR);
host_arm_SUB_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
host_arm_MOV_IMM(block, REG_CPUSTATE, (uint32_t) &cpu_state);
if (block->flags & CODEBLOCK_HAS_FPU) {
host_arm_LDR_IMM(block, REG_TEMP, REG_CPUSTATE, (uintptr_t) &cpu_state.TOP - (uintptr_t) &cpu_state);
host_arm_SUB_IMM(block, REG_TEMP, REG_TEMP, block->TOP);
host_arm_STR_IMM(block, REG_TEMP, REG_HOST_SP, IREG_TOP_diff_stack_offset);
}
}
void
codegen_backend_epilogue(codeblock_t *block)
{
host_arm_ADD_IMM(block, REG_HOST_SP, REG_HOST_SP, 0x40);
host_arm_LDMIA_WB(block, REG_HOST_SP, REG_MASK_LOCAL | REG_MASK_PC);
codegen_allocator_clean_blocks(block->head_mem_block);
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,027 |
```objective-c
#define REG_W0 0
#define REG_W1 1
#define REG_W2 2
#define REG_W3 3
#define REG_W4 4
#define REG_W5 5
#define REG_W6 6
#define REG_W7 7
#define REG_W8 8
#define REG_W9 9
#define REG_W10 10
#define REG_W11 11
#define REG_W12 12
#define REG_W13 13
#define REG_W14 14
#define REG_W15 15
#define REG_W16 16
#define REG_W17 17
#define REG_W18 18
#define REG_W19 19
#define REG_W20 20
#define REG_W21 21
#define REG_W22 22
#define REG_W23 23
#define REG_W24 24
#define REG_W25 25
#define REG_W26 26
#define REG_W27 27
#define REG_W28 28
#define REG_W29 29
#define REG_W30 30
#define REG_WZR 31
#define REG_X0 0
#define REG_X1 1
#define REG_X2 2
#define REG_X3 3
#define REG_X4 4
#define REG_X5 5
#define REG_X6 6
#define REG_X7 7
#define REG_X8 8
#define REG_X9 9
#define REG_X10 10
#define REG_X11 11
#define REG_X12 12
#define REG_X13 13
#define REG_X14 14
#define REG_X15 15
#define REG_X16 16
#define REG_X17 17
#define REG_X18 18
#define REG_X19 19
#define REG_X20 20
#define REG_X21 21
#define REG_X22 22
#define REG_X23 23
#define REG_X24 24
#define REG_X25 25
#define REG_X26 26
#define REG_X27 27
#define REG_X28 28
#define REG_X29 29
#define REG_X30 30
#define REG_XZR 31
#define REG_V0 0
#define REG_V1 1
#define REG_V2 2
#define REG_V3 3
#define REG_V4 4
#define REG_V5 5
#define REG_V6 6
#define REG_V7 7
#define REG_V8 8
#define REG_V9 9
#define REG_V10 10
#define REG_V11 11
#define REG_V12 12
#define REG_V13 13
#define REG_V14 14
#define REG_V15 15
#define REG_V16 16
#define REG_V17 17
#define REG_V18 18
#define REG_V19 19
#define REG_V20 20
#define REG_V21 21
#define REG_V22 22
#define REG_V23 23
#define REG_V24 24
#define REG_V25 25
#define REG_V26 26
#define REG_V27 27
#define REG_V28 28
#define REG_V29 29
#define REG_V30 30
#define REG_V31 31
#define REG_XSP 31
#define REG_ARG0 REG_X0
#define REG_ARG1 REG_X1
#define REG_ARG2 REG_X2
#define REG_ARG3 REG_X3
#define REG_CPUSTATE REG_X29
#define REG_TEMP REG_X7
#define REG_TEMP2 REG_X6
#define REG_V_TEMP REG_V0
#define CODEGEN_HOST_REGS 10
#define CODEGEN_HOST_FP_REGS 8
extern void *codegen_mem_load_byte;
extern void *codegen_mem_load_word;
extern void *codegen_mem_load_long;
extern void *codegen_mem_load_quad;
extern void *codegen_mem_load_single;
extern void *codegen_mem_load_double;
extern void *codegen_mem_store_byte;
extern void *codegen_mem_store_word;
extern void *codegen_mem_store_long;
extern void *codegen_mem_store_quad;
extern void *codegen_mem_store_single;
extern void *codegen_mem_store_double;
extern void *codegen_fp_round;
extern void *codegen_fp_round_quad;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64_defs.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 994 |
```c
#include <stdio.h>
#include <stdint.h>
/*ARM64 logical instructions have an 'interesting' immediate encoding.
All valid values are in the table below, which we perform a binary
search over*/
#define IMM_NR 1302
static uint32_t imm_table[][2] = {
{ 0x800, 0x00000001},
{ 0xfc0, 0x00000002},
{ 0x801, 0x00000003},
{ 0xf80, 0x00000004},
{ 0xfc1, 0x00000006},
{ 0x802, 0x00000007},
{ 0xf40, 0x00000008},
{ 0xf81, 0x0000000c},
{ 0xfc2, 0x0000000e},
{ 0x803, 0x0000000f},
{ 0xf00, 0x00000010},
{ 0xf41, 0x00000018},
{ 0xf82, 0x0000001c},
{ 0xfc3, 0x0000001e},
{ 0x804, 0x0000001f},
{ 0xec0, 0x00000020},
{ 0xf01, 0x00000030},
{ 0xf42, 0x00000038},
{ 0xf83, 0x0000003c},
{ 0xfc4, 0x0000003e},
{ 0x805, 0x0000003f},
{ 0xe80, 0x00000040},
{ 0xec1, 0x00000060},
{ 0xf02, 0x00000070},
{ 0xf43, 0x00000078},
{ 0xf84, 0x0000007c},
{ 0xfc5, 0x0000007e},
{ 0x806, 0x0000007f},
{ 0xe40, 0x00000080},
{ 0xe81, 0x000000c0},
{ 0xec2, 0x000000e0},
{ 0xf03, 0x000000f0},
{ 0xf44, 0x000000f8},
{ 0xf85, 0x000000fc},
{ 0xfc6, 0x000000fe},
{ 0x807, 0x000000ff},
{ 0xe00, 0x00000100},
{ 0xe41, 0x00000180},
{ 0xe82, 0x000001c0},
{ 0xec3, 0x000001e0},
{ 0xf04, 0x000001f0},
{ 0xf45, 0x000001f8},
{ 0xf86, 0x000001fc},
{ 0xfc7, 0x000001fe},
{ 0x808, 0x000001ff},
{ 0xdc0, 0x00000200},
{ 0xe01, 0x00000300},
{ 0xe42, 0x00000380},
{ 0xe83, 0x000003c0},
{ 0xec4, 0x000003e0},
{ 0xf05, 0x000003f0},
{ 0xf46, 0x000003f8},
{ 0xf87, 0x000003fc},
{ 0xfc8, 0x000003fe},
{ 0x809, 0x000003ff},
{ 0xd80, 0x00000400},
{ 0xdc1, 0x00000600},
{ 0xe02, 0x00000700},
{ 0xe43, 0x00000780},
{ 0xe84, 0x000007c0},
{ 0xec5, 0x000007e0},
{ 0xf06, 0x000007f0},
{ 0xf47, 0x000007f8},
{ 0xf88, 0x000007fc},
{ 0xfc9, 0x000007fe},
{ 0x80a, 0x000007ff},
{ 0xd40, 0x00000800},
{ 0xd81, 0x00000c00},
{ 0xdc2, 0x00000e00},
{ 0xe03, 0x00000f00},
{ 0xe44, 0x00000f80},
{ 0xe85, 0x00000fc0},
{ 0xec6, 0x00000fe0},
{ 0xf07, 0x00000ff0},
{ 0xf48, 0x00000ff8},
{ 0xf89, 0x00000ffc},
{ 0xfca, 0x00000ffe},
{ 0x80b, 0x00000fff},
{ 0xd00, 0x00001000},
{ 0xd41, 0x00001800},
{ 0xd82, 0x00001c00},
{ 0xdc3, 0x00001e00},
{ 0xe04, 0x00001f00},
{ 0xe45, 0x00001f80},
{ 0xe86, 0x00001fc0},
{ 0xec7, 0x00001fe0},
{ 0xf08, 0x00001ff0},
{ 0xf49, 0x00001ff8},
{ 0xf8a, 0x00001ffc},
{ 0xfcb, 0x00001ffe},
{ 0x80c, 0x00001fff},
{ 0xcc0, 0x00002000},
{ 0xd01, 0x00003000},
{ 0xd42, 0x00003800},
{ 0xd83, 0x00003c00},
{ 0xdc4, 0x00003e00},
{ 0xe05, 0x00003f00},
{ 0xe46, 0x00003f80},
{ 0xe87, 0x00003fc0},
{ 0xec8, 0x00003fe0},
{ 0xf09, 0x00003ff0},
{ 0xf4a, 0x00003ff8},
{ 0xf8b, 0x00003ffc},
{ 0xfcc, 0x00003ffe},
{ 0x80d, 0x00003fff},
{ 0xc80, 0x00004000},
{ 0xcc1, 0x00006000},
{ 0xd02, 0x00007000},
{ 0xd43, 0x00007800},
{ 0xd84, 0x00007c00},
{ 0xdc5, 0x00007e00},
{ 0xe06, 0x00007f00},
{ 0xe47, 0x00007f80},
{ 0xe88, 0x00007fc0},
{ 0xec9, 0x00007fe0},
{ 0xf0a, 0x00007ff0},
{ 0xf4b, 0x00007ff8},
{ 0xf8c, 0x00007ffc},
{ 0xfcd, 0x00007ffe},
{ 0x80e, 0x00007fff},
{ 0xc40, 0x00008000},
{ 0xc81, 0x0000c000},
{ 0xcc2, 0x0000e000},
{ 0xd03, 0x0000f000},
{ 0xd44, 0x0000f800},
{ 0xd85, 0x0000fc00},
{ 0xdc6, 0x0000fe00},
{ 0xe07, 0x0000ff00},
{ 0xe48, 0x0000ff80},
{ 0xe89, 0x0000ffc0},
{ 0xeca, 0x0000ffe0},
{ 0xf0b, 0x0000fff0},
{ 0xf4c, 0x0000fff8},
{ 0xf8d, 0x0000fffc},
{ 0xfce, 0x0000fffe},
{ 0x80f, 0x0000ffff},
{ 0xc00, 0x00010000},
{ 0xc20, 0x00010001},
{ 0xc41, 0x00018000},
{ 0xc82, 0x0001c000},
{ 0xcc3, 0x0001e000},
{ 0xd04, 0x0001f000},
{ 0xd45, 0x0001f800},
{ 0xd86, 0x0001fc00},
{ 0xdc7, 0x0001fe00},
{ 0xe08, 0x0001ff00},
{ 0xe49, 0x0001ff80},
{ 0xe8a, 0x0001ffc0},
{ 0xecb, 0x0001ffe0},
{ 0xf0c, 0x0001fff0},
{ 0xf4d, 0x0001fff8},
{ 0xf8e, 0x0001fffc},
{ 0xfcf, 0x0001fffe},
{ 0x810, 0x0001ffff},
{ 0xbc0, 0x00020000},
{ 0xfe0, 0x00020002},
{ 0xc01, 0x00030000},
{ 0xc21, 0x00030003},
{ 0xc42, 0x00038000},
{ 0xc83, 0x0003c000},
{ 0xcc4, 0x0003e000},
{ 0xd05, 0x0003f000},
{ 0xd46, 0x0003f800},
{ 0xd87, 0x0003fc00},
{ 0xdc8, 0x0003fe00},
{ 0xe09, 0x0003ff00},
{ 0xe4a, 0x0003ff80},
{ 0xe8b, 0x0003ffc0},
{ 0xecc, 0x0003ffe0},
{ 0xf0d, 0x0003fff0},
{ 0xf4e, 0x0003fff8},
{ 0xf8f, 0x0003fffc},
{ 0xfd0, 0x0003fffe},
{ 0x811, 0x0003ffff},
{ 0xb80, 0x00040000},
{ 0xfa0, 0x00040004},
{ 0xbc1, 0x00060000},
{ 0xfe1, 0x00060006},
{ 0xc02, 0x00070000},
{ 0xc22, 0x00070007},
{ 0xc43, 0x00078000},
{ 0xc84, 0x0007c000},
{ 0xcc5, 0x0007e000},
{ 0xd06, 0x0007f000},
{ 0xd47, 0x0007f800},
{ 0xd88, 0x0007fc00},
{ 0xdc9, 0x0007fe00},
{ 0xe0a, 0x0007ff00},
{ 0xe4b, 0x0007ff80},
{ 0xe8c, 0x0007ffc0},
{ 0xecd, 0x0007ffe0},
{ 0xf0e, 0x0007fff0},
{ 0xf4f, 0x0007fff8},
{ 0xf90, 0x0007fffc},
{ 0xfd1, 0x0007fffe},
{ 0x812, 0x0007ffff},
{ 0xb40, 0x00080000},
{ 0xf60, 0x00080008},
{ 0xb81, 0x000c0000},
{ 0xfa1, 0x000c000c},
{ 0xbc2, 0x000e0000},
{ 0xfe2, 0x000e000e},
{ 0xc03, 0x000f0000},
{ 0xc23, 0x000f000f},
{ 0xc44, 0x000f8000},
{ 0xc85, 0x000fc000},
{ 0xcc6, 0x000fe000},
{ 0xd07, 0x000ff000},
{ 0xd48, 0x000ff800},
{ 0xd89, 0x000ffc00},
{ 0xdca, 0x000ffe00},
{ 0xe0b, 0x000fff00},
{ 0xe4c, 0x000fff80},
{ 0xe8d, 0x000fffc0},
{ 0xece, 0x000fffe0},
{ 0xf0f, 0x000ffff0},
{ 0xf50, 0x000ffff8},
{ 0xf91, 0x000ffffc},
{ 0xfd2, 0x000ffffe},
{ 0x813, 0x000fffff},
{ 0xb00, 0x00100000},
{ 0xf20, 0x00100010},
{ 0xb41, 0x00180000},
{ 0xf61, 0x00180018},
{ 0xb82, 0x001c0000},
{ 0xfa2, 0x001c001c},
{ 0xbc3, 0x001e0000},
{ 0xfe3, 0x001e001e},
{ 0xc04, 0x001f0000},
{ 0xc24, 0x001f001f},
{ 0xc45, 0x001f8000},
{ 0xc86, 0x001fc000},
{ 0xcc7, 0x001fe000},
{ 0xd08, 0x001ff000},
{ 0xd49, 0x001ff800},
{ 0xd8a, 0x001ffc00},
{ 0xdcb, 0x001ffe00},
{ 0xe0c, 0x001fff00},
{ 0xe4d, 0x001fff80},
{ 0xe8e, 0x001fffc0},
{ 0xecf, 0x001fffe0},
{ 0xf10, 0x001ffff0},
{ 0xf51, 0x001ffff8},
{ 0xf92, 0x001ffffc},
{ 0xfd3, 0x001ffffe},
{ 0x814, 0x001fffff},
{ 0xac0, 0x00200000},
{ 0xee0, 0x00200020},
{ 0xb01, 0x00300000},
{ 0xf21, 0x00300030},
{ 0xb42, 0x00380000},
{ 0xf62, 0x00380038},
{ 0xb83, 0x003c0000},
{ 0xfa3, 0x003c003c},
{ 0xbc4, 0x003e0000},
{ 0xfe4, 0x003e003e},
{ 0xc05, 0x003f0000},
{ 0xc25, 0x003f003f},
{ 0xc46, 0x003f8000},
{ 0xc87, 0x003fc000},
{ 0xcc8, 0x003fe000},
{ 0xd09, 0x003ff000},
{ 0xd4a, 0x003ff800},
{ 0xd8b, 0x003ffc00},
{ 0xdcc, 0x003ffe00},
{ 0xe0d, 0x003fff00},
{ 0xe4e, 0x003fff80},
{ 0xe8f, 0x003fffc0},
{ 0xed0, 0x003fffe0},
{ 0xf11, 0x003ffff0},
{ 0xf52, 0x003ffff8},
{ 0xf93, 0x003ffffc},
{ 0xfd4, 0x003ffffe},
{ 0x815, 0x003fffff},
{ 0xa80, 0x00400000},
{ 0xea0, 0x00400040},
{ 0xac1, 0x00600000},
{ 0xee1, 0x00600060},
{ 0xb02, 0x00700000},
{ 0xf22, 0x00700070},
{ 0xb43, 0x00780000},
{ 0xf63, 0x00780078},
{ 0xb84, 0x007c0000},
{ 0xfa4, 0x007c007c},
{ 0xbc5, 0x007e0000},
{ 0xfe5, 0x007e007e},
{ 0xc06, 0x007f0000},
{ 0xc26, 0x007f007f},
{ 0xc47, 0x007f8000},
{ 0xc88, 0x007fc000},
{ 0xcc9, 0x007fe000},
{ 0xd0a, 0x007ff000},
{ 0xd4b, 0x007ff800},
{ 0xd8c, 0x007ffc00},
{ 0xdcd, 0x007ffe00},
{ 0xe0e, 0x007fff00},
{ 0xe4f, 0x007fff80},
{ 0xe90, 0x007fffc0},
{ 0xed1, 0x007fffe0},
{ 0xf12, 0x007ffff0},
{ 0xf53, 0x007ffff8},
{ 0xf94, 0x007ffffc},
{ 0xfd5, 0x007ffffe},
{ 0x816, 0x007fffff},
{ 0xa40, 0x00800000},
{ 0xe60, 0x00800080},
{ 0xa81, 0x00c00000},
{ 0xea1, 0x00c000c0},
{ 0xac2, 0x00e00000},
{ 0xee2, 0x00e000e0},
{ 0xb03, 0x00f00000},
{ 0xf23, 0x00f000f0},
{ 0xb44, 0x00f80000},
{ 0xf64, 0x00f800f8},
{ 0xb85, 0x00fc0000},
{ 0xfa5, 0x00fc00fc},
{ 0xbc6, 0x00fe0000},
{ 0xfe6, 0x00fe00fe},
{ 0xc07, 0x00ff0000},
{ 0xc27, 0x00ff00ff},
{ 0xc48, 0x00ff8000},
{ 0xc89, 0x00ffc000},
{ 0xcca, 0x00ffe000},
{ 0xd0b, 0x00fff000},
{ 0xd4c, 0x00fff800},
{ 0xd8d, 0x00fffc00},
{ 0xdce, 0x00fffe00},
{ 0xe0f, 0x00ffff00},
{ 0xe50, 0x00ffff80},
{ 0xe91, 0x00ffffc0},
{ 0xed2, 0x00ffffe0},
{ 0xf13, 0x00fffff0},
{ 0xf54, 0x00fffff8},
{ 0xf95, 0x00fffffc},
{ 0xfd6, 0x00fffffe},
{ 0x817, 0x00ffffff},
{ 0xa00, 0x01000000},
{ 0xe20, 0x01000100},
{ 0xe30, 0x01010101},
{ 0xa41, 0x01800000},
{ 0xe61, 0x01800180},
{ 0xa82, 0x01c00000},
{ 0xea2, 0x01c001c0},
{ 0xac3, 0x01e00000},
{ 0xee3, 0x01e001e0},
{ 0xb04, 0x01f00000},
{ 0xf24, 0x01f001f0},
{ 0xb45, 0x01f80000},
{ 0xf65, 0x01f801f8},
{ 0xb86, 0x01fc0000},
{ 0xfa6, 0x01fc01fc},
{ 0xbc7, 0x01fe0000},
{ 0xfe7, 0x01fe01fe},
{ 0xc08, 0x01ff0000},
{ 0xc28, 0x01ff01ff},
{ 0xc49, 0x01ff8000},
{ 0xc8a, 0x01ffc000},
{ 0xccb, 0x01ffe000},
{ 0xd0c, 0x01fff000},
{ 0xd4d, 0x01fff800},
{ 0xd8e, 0x01fffc00},
{ 0xdcf, 0x01fffe00},
{ 0xe10, 0x01ffff00},
{ 0xe51, 0x01ffff80},
{ 0xe92, 0x01ffffc0},
{ 0xed3, 0x01ffffe0},
{ 0xf14, 0x01fffff0},
{ 0xf55, 0x01fffff8},
{ 0xf96, 0x01fffffc},
{ 0xfd7, 0x01fffffe},
{ 0x818, 0x01ffffff},
{ 0x9c0, 0x02000000},
{ 0xde0, 0x02000200},
{ 0xff0, 0x02020202},
{ 0xa01, 0x03000000},
{ 0xe21, 0x03000300},
{ 0xe31, 0x03030303},
{ 0xa42, 0x03800000},
{ 0xe62, 0x03800380},
{ 0xa83, 0x03c00000},
{ 0xea3, 0x03c003c0},
{ 0xac4, 0x03e00000},
{ 0xee4, 0x03e003e0},
{ 0xb05, 0x03f00000},
{ 0xf25, 0x03f003f0},
{ 0xb46, 0x03f80000},
{ 0xf66, 0x03f803f8},
{ 0xb87, 0x03fc0000},
{ 0xfa7, 0x03fc03fc},
{ 0xbc8, 0x03fe0000},
{ 0xfe8, 0x03fe03fe},
{ 0xc09, 0x03ff0000},
{ 0xc29, 0x03ff03ff},
{ 0xc4a, 0x03ff8000},
{ 0xc8b, 0x03ffc000},
{ 0xccc, 0x03ffe000},
{ 0xd0d, 0x03fff000},
{ 0xd4e, 0x03fff800},
{ 0xd8f, 0x03fffc00},
{ 0xdd0, 0x03fffe00},
{ 0xe11, 0x03ffff00},
{ 0xe52, 0x03ffff80},
{ 0xe93, 0x03ffffc0},
{ 0xed4, 0x03ffffe0},
{ 0xf15, 0x03fffff0},
{ 0xf56, 0x03fffff8},
{ 0xf97, 0x03fffffc},
{ 0xfd8, 0x03fffffe},
{ 0x819, 0x03ffffff},
{ 0x980, 0x04000000},
{ 0xda0, 0x04000400},
{ 0xfb0, 0x04040404},
{ 0x9c1, 0x06000000},
{ 0xde1, 0x06000600},
{ 0xff1, 0x06060606},
{ 0xa02, 0x07000000},
{ 0xe22, 0x07000700},
{ 0xe32, 0x07070707},
{ 0xa43, 0x07800000},
{ 0xe63, 0x07800780},
{ 0xa84, 0x07c00000},
{ 0xea4, 0x07c007c0},
{ 0xac5, 0x07e00000},
{ 0xee5, 0x07e007e0},
{ 0xb06, 0x07f00000},
{ 0xf26, 0x07f007f0},
{ 0xb47, 0x07f80000},
{ 0xf67, 0x07f807f8},
{ 0xb88, 0x07fc0000},
{ 0xfa8, 0x07fc07fc},
{ 0xbc9, 0x07fe0000},
{ 0xfe9, 0x07fe07fe},
{ 0xc0a, 0x07ff0000},
{ 0xc2a, 0x07ff07ff},
{ 0xc4b, 0x07ff8000},
{ 0xc8c, 0x07ffc000},
{ 0xccd, 0x07ffe000},
{ 0xd0e, 0x07fff000},
{ 0xd4f, 0x07fff800},
{ 0xd90, 0x07fffc00},
{ 0xdd1, 0x07fffe00},
{ 0xe12, 0x07ffff00},
{ 0xe53, 0x07ffff80},
{ 0xe94, 0x07ffffc0},
{ 0xed5, 0x07ffffe0},
{ 0xf16, 0x07fffff0},
{ 0xf57, 0x07fffff8},
{ 0xf98, 0x07fffffc},
{ 0xfd9, 0x07fffffe},
{ 0x81a, 0x07ffffff},
{ 0x940, 0x08000000},
{ 0xd60, 0x08000800},
{ 0xf70, 0x08080808},
{ 0x981, 0x0c000000},
{ 0xda1, 0x0c000c00},
{ 0xfb1, 0x0c0c0c0c},
{ 0x9c2, 0x0e000000},
{ 0xde2, 0x0e000e00},
{ 0xff2, 0x0e0e0e0e},
{ 0xa03, 0x0f000000},
{ 0xe23, 0x0f000f00},
{ 0xe33, 0x0f0f0f0f},
{ 0xa44, 0x0f800000},
{ 0xe64, 0x0f800f80},
{ 0xa85, 0x0fc00000},
{ 0xea5, 0x0fc00fc0},
{ 0xac6, 0x0fe00000},
{ 0xee6, 0x0fe00fe0},
{ 0xb07, 0x0ff00000},
{ 0xf27, 0x0ff00ff0},
{ 0xb48, 0x0ff80000},
{ 0xf68, 0x0ff80ff8},
{ 0xb89, 0x0ffc0000},
{ 0xfa9, 0x0ffc0ffc},
{ 0xbca, 0x0ffe0000},
{ 0xfea, 0x0ffe0ffe},
{ 0xc0b, 0x0fff0000},
{ 0xc2b, 0x0fff0fff},
{ 0xc4c, 0x0fff8000},
{ 0xc8d, 0x0fffc000},
{ 0xcce, 0x0fffe000},
{ 0xd0f, 0x0ffff000},
{ 0xd50, 0x0ffff800},
{ 0xd91, 0x0ffffc00},
{ 0xdd2, 0x0ffffe00},
{ 0xe13, 0x0fffff00},
{ 0xe54, 0x0fffff80},
{ 0xe95, 0x0fffffc0},
{ 0xed6, 0x0fffffe0},
{ 0xf17, 0x0ffffff0},
{ 0xf58, 0x0ffffff8},
{ 0xf99, 0x0ffffffc},
{ 0xfda, 0x0ffffffe},
{ 0x81b, 0x0fffffff},
{ 0x900, 0x10000000},
{ 0xd20, 0x10001000},
{ 0xf30, 0x10101010},
{ 0xf38, 0x11111111},
{ 0x941, 0x18000000},
{ 0xd61, 0x18001800},
{ 0xf71, 0x18181818},
{ 0x982, 0x1c000000},
{ 0xda2, 0x1c001c00},
{ 0xfb2, 0x1c1c1c1c},
{ 0x9c3, 0x1e000000},
{ 0xde3, 0x1e001e00},
{ 0xff3, 0x1e1e1e1e},
{ 0xa04, 0x1f000000},
{ 0xe24, 0x1f001f00},
{ 0xe34, 0x1f1f1f1f},
{ 0xa45, 0x1f800000},
{ 0xe65, 0x1f801f80},
{ 0xa86, 0x1fc00000},
{ 0xea6, 0x1fc01fc0},
{ 0xac7, 0x1fe00000},
{ 0xee7, 0x1fe01fe0},
{ 0xb08, 0x1ff00000},
{ 0xf28, 0x1ff01ff0},
{ 0xb49, 0x1ff80000},
{ 0xf69, 0x1ff81ff8},
{ 0xb8a, 0x1ffc0000},
{ 0xfaa, 0x1ffc1ffc},
{ 0xbcb, 0x1ffe0000},
{ 0xfeb, 0x1ffe1ffe},
{ 0xc0c, 0x1fff0000},
{ 0xc2c, 0x1fff1fff},
{ 0xc4d, 0x1fff8000},
{ 0xc8e, 0x1fffc000},
{ 0xccf, 0x1fffe000},
{ 0xd10, 0x1ffff000},
{ 0xd51, 0x1ffff800},
{ 0xd92, 0x1ffffc00},
{ 0xdd3, 0x1ffffe00},
{ 0xe14, 0x1fffff00},
{ 0xe55, 0x1fffff80},
{ 0xe96, 0x1fffffc0},
{ 0xed7, 0x1fffffe0},
{ 0xf18, 0x1ffffff0},
{ 0xf59, 0x1ffffff8},
{ 0xf9a, 0x1ffffffc},
{ 0xfdb, 0x1ffffffe},
{ 0x81c, 0x1fffffff},
{ 0x8c0, 0x20000000},
{ 0xce0, 0x20002000},
{ 0xef0, 0x20202020},
{ 0xff8, 0x22222222},
{ 0x901, 0x30000000},
{ 0xd21, 0x30003000},
{ 0xf31, 0x30303030},
{ 0xf39, 0x33333333},
{ 0x942, 0x38000000},
{ 0xd62, 0x38003800},
{ 0xf72, 0x38383838},
{ 0x983, 0x3c000000},
{ 0xda3, 0x3c003c00},
{ 0xfb3, 0x3c3c3c3c},
{ 0x9c4, 0x3e000000},
{ 0xde4, 0x3e003e00},
{ 0xff4, 0x3e3e3e3e},
{ 0xa05, 0x3f000000},
{ 0xe25, 0x3f003f00},
{ 0xe35, 0x3f3f3f3f},
{ 0xa46, 0x3f800000},
{ 0xe66, 0x3f803f80},
{ 0xa87, 0x3fc00000},
{ 0xea7, 0x3fc03fc0},
{ 0xac8, 0x3fe00000},
{ 0xee8, 0x3fe03fe0},
{ 0xb09, 0x3ff00000},
{ 0xf29, 0x3ff03ff0},
{ 0xb4a, 0x3ff80000},
{ 0xf6a, 0x3ff83ff8},
{ 0xb8b, 0x3ffc0000},
{ 0xfab, 0x3ffc3ffc},
{ 0xbcc, 0x3ffe0000},
{ 0xfec, 0x3ffe3ffe},
{ 0xc0d, 0x3fff0000},
{ 0xc2d, 0x3fff3fff},
{ 0xc4e, 0x3fff8000},
{ 0xc8f, 0x3fffc000},
{ 0xcd0, 0x3fffe000},
{ 0xd11, 0x3ffff000},
{ 0xd52, 0x3ffff800},
{ 0xd93, 0x3ffffc00},
{ 0xdd4, 0x3ffffe00},
{ 0xe15, 0x3fffff00},
{ 0xe56, 0x3fffff80},
{ 0xe97, 0x3fffffc0},
{ 0xed8, 0x3fffffe0},
{ 0xf19, 0x3ffffff0},
{ 0xf5a, 0x3ffffff8},
{ 0xf9b, 0x3ffffffc},
{ 0xfdc, 0x3ffffffe},
{ 0x81d, 0x3fffffff},
{ 0x880, 0x40000000},
{ 0xca0, 0x40004000},
{ 0xeb0, 0x40404040},
{ 0xfb8, 0x44444444},
{ 0xfbc, 0x55555555},
{ 0x8c1, 0x60000000},
{ 0xce1, 0x60006000},
{ 0xef1, 0x60606060},
{ 0xff9, 0x66666666},
{ 0x902, 0x70000000},
{ 0xd22, 0x70007000},
{ 0xf32, 0x70707070},
{ 0xf3a, 0x77777777},
{ 0x943, 0x78000000},
{ 0xd63, 0x78007800},
{ 0xf73, 0x78787878},
{ 0x984, 0x7c000000},
{ 0xda4, 0x7c007c00},
{ 0xfb4, 0x7c7c7c7c},
{ 0x9c5, 0x7e000000},
{ 0xde5, 0x7e007e00},
{ 0xff5, 0x7e7e7e7e},
{ 0xa06, 0x7f000000},
{ 0xe26, 0x7f007f00},
{ 0xe36, 0x7f7f7f7f},
{ 0xa47, 0x7f800000},
{ 0xe67, 0x7f807f80},
{ 0xa88, 0x7fc00000},
{ 0xea8, 0x7fc07fc0},
{ 0xac9, 0x7fe00000},
{ 0xee9, 0x7fe07fe0},
{ 0xb0a, 0x7ff00000},
{ 0xf2a, 0x7ff07ff0},
{ 0xb4b, 0x7ff80000},
{ 0xf6b, 0x7ff87ff8},
{ 0xb8c, 0x7ffc0000},
{ 0xfac, 0x7ffc7ffc},
{ 0xbcd, 0x7ffe0000},
{ 0xfed, 0x7ffe7ffe},
{ 0xc0e, 0x7fff0000},
{ 0xc2e, 0x7fff7fff},
{ 0xc4f, 0x7fff8000},
{ 0xc90, 0x7fffc000},
{ 0xcd1, 0x7fffe000},
{ 0xd12, 0x7ffff000},
{ 0xd53, 0x7ffff800},
{ 0xd94, 0x7ffffc00},
{ 0xdd5, 0x7ffffe00},
{ 0xe16, 0x7fffff00},
{ 0xe57, 0x7fffff80},
{ 0xe98, 0x7fffffc0},
{ 0xed9, 0x7fffffe0},
{ 0xf1a, 0x7ffffff0},
{ 0xf5b, 0x7ffffff8},
{ 0xf9c, 0x7ffffffc},
{ 0xfdd, 0x7ffffffe},
{ 0x81e, 0x7fffffff},
{ 0x840, 0x80000000},
{ 0x841, 0x80000001},
{ 0x842, 0x80000003},
{ 0x843, 0x80000007},
{ 0x844, 0x8000000f},
{ 0x845, 0x8000001f},
{ 0x846, 0x8000003f},
{ 0x847, 0x8000007f},
{ 0x848, 0x800000ff},
{ 0x849, 0x800001ff},
{ 0x84a, 0x800003ff},
{ 0x84b, 0x800007ff},
{ 0x84c, 0x80000fff},
{ 0x84d, 0x80001fff},
{ 0x84e, 0x80003fff},
{ 0x84f, 0x80007fff},
{ 0xc60, 0x80008000},
{ 0x850, 0x8000ffff},
{ 0xc61, 0x80018001},
{ 0x851, 0x8001ffff},
{ 0xc62, 0x80038003},
{ 0x852, 0x8003ffff},
{ 0xc63, 0x80078007},
{ 0x853, 0x8007ffff},
{ 0xc64, 0x800f800f},
{ 0x854, 0x800fffff},
{ 0xc65, 0x801f801f},
{ 0x855, 0x801fffff},
{ 0xc66, 0x803f803f},
{ 0x856, 0x803fffff},
{ 0xc67, 0x807f807f},
{ 0x857, 0x807fffff},
{ 0xe70, 0x80808080},
{ 0xc68, 0x80ff80ff},
{ 0x858, 0x80ffffff},
{ 0xe71, 0x81818181},
{ 0xc69, 0x81ff81ff},
{ 0x859, 0x81ffffff},
{ 0xe72, 0x83838383},
{ 0xc6a, 0x83ff83ff},
{ 0x85a, 0x83ffffff},
{ 0xe73, 0x87878787},
{ 0xc6b, 0x87ff87ff},
{ 0x85b, 0x87ffffff},
{ 0xf78, 0x88888888},
{ 0xe74, 0x8f8f8f8f},
{ 0xc6c, 0x8fff8fff},
{ 0x85c, 0x8fffffff},
{ 0xf79, 0x99999999},
{ 0xe75, 0x9f9f9f9f},
{ 0xc6d, 0x9fff9fff},
{ 0x85d, 0x9fffffff},
{ 0xffc, 0xaaaaaaaa},
{ 0xf7a, 0xbbbbbbbb},
{ 0xe76, 0xbfbfbfbf},
{ 0xc6e, 0xbfffbfff},
{ 0x85e, 0xbfffffff},
{ 0x881, 0xc0000000},
{ 0x882, 0xc0000001},
{ 0x883, 0xc0000003},
{ 0x884, 0xc0000007},
{ 0x885, 0xc000000f},
{ 0x886, 0xc000001f},
{ 0x887, 0xc000003f},
{ 0x888, 0xc000007f},
{ 0x889, 0xc00000ff},
{ 0x88a, 0xc00001ff},
{ 0x88b, 0xc00003ff},
{ 0x88c, 0xc00007ff},
{ 0x88d, 0xc0000fff},
{ 0x88e, 0xc0001fff},
{ 0x88f, 0xc0003fff},
{ 0x890, 0xc0007fff},
{ 0xca1, 0xc000c000},
{ 0x891, 0xc000ffff},
{ 0xca2, 0xc001c001},
{ 0x892, 0xc001ffff},
{ 0xca3, 0xc003c003},
{ 0x893, 0xc003ffff},
{ 0xca4, 0xc007c007},
{ 0x894, 0xc007ffff},
{ 0xca5, 0xc00fc00f},
{ 0x895, 0xc00fffff},
{ 0xca6, 0xc01fc01f},
{ 0x896, 0xc01fffff},
{ 0xca7, 0xc03fc03f},
{ 0x897, 0xc03fffff},
{ 0xca8, 0xc07fc07f},
{ 0x898, 0xc07fffff},
{ 0xeb1, 0xc0c0c0c0},
{ 0xca9, 0xc0ffc0ff},
{ 0x899, 0xc0ffffff},
{ 0xeb2, 0xc1c1c1c1},
{ 0xcaa, 0xc1ffc1ff},
{ 0x89a, 0xc1ffffff},
{ 0xeb3, 0xc3c3c3c3},
{ 0xcab, 0xc3ffc3ff},
{ 0x89b, 0xc3ffffff},
{ 0xeb4, 0xc7c7c7c7},
{ 0xcac, 0xc7ffc7ff},
{ 0x89c, 0xc7ffffff},
{ 0xfb9, 0xcccccccc},
{ 0xeb5, 0xcfcfcfcf},
{ 0xcad, 0xcfffcfff},
{ 0x89d, 0xcfffffff},
{ 0xfba, 0xdddddddd},
{ 0xeb6, 0xdfdfdfdf},
{ 0xcae, 0xdfffdfff},
{ 0x89e, 0xdfffffff},
{ 0x8c2, 0xe0000000},
{ 0x8c3, 0xe0000001},
{ 0x8c4, 0xe0000003},
{ 0x8c5, 0xe0000007},
{ 0x8c6, 0xe000000f},
{ 0x8c7, 0xe000001f},
{ 0x8c8, 0xe000003f},
{ 0x8c9, 0xe000007f},
{ 0x8ca, 0xe00000ff},
{ 0x8cb, 0xe00001ff},
{ 0x8cc, 0xe00003ff},
{ 0x8cd, 0xe00007ff},
{ 0x8ce, 0xe0000fff},
{ 0x8cf, 0xe0001fff},
{ 0x8d0, 0xe0003fff},
{ 0x8d1, 0xe0007fff},
{ 0xce2, 0xe000e000},
{ 0x8d2, 0xe000ffff},
{ 0xce3, 0xe001e001},
{ 0x8d3, 0xe001ffff},
{ 0xce4, 0xe003e003},
{ 0x8d4, 0xe003ffff},
{ 0xce5, 0xe007e007},
{ 0x8d5, 0xe007ffff},
{ 0xce6, 0xe00fe00f},
{ 0x8d6, 0xe00fffff},
{ 0xce7, 0xe01fe01f},
{ 0x8d7, 0xe01fffff},
{ 0xce8, 0xe03fe03f},
{ 0x8d8, 0xe03fffff},
{ 0xce9, 0xe07fe07f},
{ 0x8d9, 0xe07fffff},
{ 0xef2, 0xe0e0e0e0},
{ 0xcea, 0xe0ffe0ff},
{ 0x8da, 0xe0ffffff},
{ 0xef3, 0xe1e1e1e1},
{ 0xceb, 0xe1ffe1ff},
{ 0x8db, 0xe1ffffff},
{ 0xef4, 0xe3e3e3e3},
{ 0xcec, 0xe3ffe3ff},
{ 0x8dc, 0xe3ffffff},
{ 0xef5, 0xe7e7e7e7},
{ 0xced, 0xe7ffe7ff},
{ 0x8dd, 0xe7ffffff},
{ 0xffa, 0xeeeeeeee},
{ 0xef6, 0xefefefef},
{ 0xcee, 0xefffefff},
{ 0x8de, 0xefffffff},
{ 0x903, 0xf0000000},
{ 0x904, 0xf0000001},
{ 0x905, 0xf0000003},
{ 0x906, 0xf0000007},
{ 0x907, 0xf000000f},
{ 0x908, 0xf000001f},
{ 0x909, 0xf000003f},
{ 0x90a, 0xf000007f},
{ 0x90b, 0xf00000ff},
{ 0x90c, 0xf00001ff},
{ 0x90d, 0xf00003ff},
{ 0x90e, 0xf00007ff},
{ 0x90f, 0xf0000fff},
{ 0x910, 0xf0001fff},
{ 0x911, 0xf0003fff},
{ 0x912, 0xf0007fff},
{ 0xd23, 0xf000f000},
{ 0x913, 0xf000ffff},
{ 0xd24, 0xf001f001},
{ 0x914, 0xf001ffff},
{ 0xd25, 0xf003f003},
{ 0x915, 0xf003ffff},
{ 0xd26, 0xf007f007},
{ 0x916, 0xf007ffff},
{ 0xd27, 0xf00ff00f},
{ 0x917, 0xf00fffff},
{ 0xd28, 0xf01ff01f},
{ 0x918, 0xf01fffff},
{ 0xd29, 0xf03ff03f},
{ 0x919, 0xf03fffff},
{ 0xd2a, 0xf07ff07f},
{ 0x91a, 0xf07fffff},
{ 0xf33, 0xf0f0f0f0},
{ 0xd2b, 0xf0fff0ff},
{ 0x91b, 0xf0ffffff},
{ 0xf34, 0xf1f1f1f1},
{ 0xd2c, 0xf1fff1ff},
{ 0x91c, 0xf1ffffff},
{ 0xf35, 0xf3f3f3f3},
{ 0xd2d, 0xf3fff3ff},
{ 0x91d, 0xf3ffffff},
{ 0xf36, 0xf7f7f7f7},
{ 0xd2e, 0xf7fff7ff},
{ 0x91e, 0xf7ffffff},
{ 0x944, 0xf8000000},
{ 0x945, 0xf8000001},
{ 0x946, 0xf8000003},
{ 0x947, 0xf8000007},
{ 0x948, 0xf800000f},
{ 0x949, 0xf800001f},
{ 0x94a, 0xf800003f},
{ 0x94b, 0xf800007f},
{ 0x94c, 0xf80000ff},
{ 0x94d, 0xf80001ff},
{ 0x94e, 0xf80003ff},
{ 0x94f, 0xf80007ff},
{ 0x950, 0xf8000fff},
{ 0x951, 0xf8001fff},
{ 0x952, 0xf8003fff},
{ 0x953, 0xf8007fff},
{ 0xd64, 0xf800f800},
{ 0x954, 0xf800ffff},
{ 0xd65, 0xf801f801},
{ 0x955, 0xf801ffff},
{ 0xd66, 0xf803f803},
{ 0x956, 0xf803ffff},
{ 0xd67, 0xf807f807},
{ 0x957, 0xf807ffff},
{ 0xd68, 0xf80ff80f},
{ 0x958, 0xf80fffff},
{ 0xd69, 0xf81ff81f},
{ 0x959, 0xf81fffff},
{ 0xd6a, 0xf83ff83f},
{ 0x95a, 0xf83fffff},
{ 0xd6b, 0xf87ff87f},
{ 0x95b, 0xf87fffff},
{ 0xf74, 0xf8f8f8f8},
{ 0xd6c, 0xf8fff8ff},
{ 0x95c, 0xf8ffffff},
{ 0xf75, 0xf9f9f9f9},
{ 0xd6d, 0xf9fff9ff},
{ 0x95d, 0xf9ffffff},
{ 0xf76, 0xfbfbfbfb},
{ 0xd6e, 0xfbfffbff},
{ 0x95e, 0xfbffffff},
{ 0x985, 0xfc000000},
{ 0x986, 0xfc000001},
{ 0x987, 0xfc000003},
{ 0x988, 0xfc000007},
{ 0x989, 0xfc00000f},
{ 0x98a, 0xfc00001f},
{ 0x98b, 0xfc00003f},
{ 0x98c, 0xfc00007f},
{ 0x98d, 0xfc0000ff},
{ 0x98e, 0xfc0001ff},
{ 0x98f, 0xfc0003ff},
{ 0x990, 0xfc0007ff},
{ 0x991, 0xfc000fff},
{ 0x992, 0xfc001fff},
{ 0x993, 0xfc003fff},
{ 0x994, 0xfc007fff},
{ 0xda5, 0xfc00fc00},
{ 0x995, 0xfc00ffff},
{ 0xda6, 0xfc01fc01},
{ 0x996, 0xfc01ffff},
{ 0xda7, 0xfc03fc03},
{ 0x997, 0xfc03ffff},
{ 0xda8, 0xfc07fc07},
{ 0x998, 0xfc07ffff},
{ 0xda9, 0xfc0ffc0f},
{ 0x999, 0xfc0fffff},
{ 0xdaa, 0xfc1ffc1f},
{ 0x99a, 0xfc1fffff},
{ 0xdab, 0xfc3ffc3f},
{ 0x99b, 0xfc3fffff},
{ 0xdac, 0xfc7ffc7f},
{ 0x99c, 0xfc7fffff},
{ 0xfb5, 0xfcfcfcfc},
{ 0xdad, 0xfcfffcff},
{ 0x99d, 0xfcffffff},
{ 0xfb6, 0xfdfdfdfd},
{ 0xdae, 0xfdfffdff},
{ 0x99e, 0xfdffffff},
{ 0x9c6, 0xfe000000},
{ 0x9c7, 0xfe000001},
{ 0x9c8, 0xfe000003},
{ 0x9c9, 0xfe000007},
{ 0x9ca, 0xfe00000f},
{ 0x9cb, 0xfe00001f},
{ 0x9cc, 0xfe00003f},
{ 0x9cd, 0xfe00007f},
{ 0x9ce, 0xfe0000ff},
{ 0x9cf, 0xfe0001ff},
{ 0x9d0, 0xfe0003ff},
{ 0x9d1, 0xfe0007ff},
{ 0x9d2, 0xfe000fff},
{ 0x9d3, 0xfe001fff},
{ 0x9d4, 0xfe003fff},
{ 0x9d5, 0xfe007fff},
{ 0xde6, 0xfe00fe00},
{ 0x9d6, 0xfe00ffff},
{ 0xde7, 0xfe01fe01},
{ 0x9d7, 0xfe01ffff},
{ 0xde8, 0xfe03fe03},
{ 0x9d8, 0xfe03ffff},
{ 0xde9, 0xfe07fe07},
{ 0x9d9, 0xfe07ffff},
{ 0xdea, 0xfe0ffe0f},
{ 0x9da, 0xfe0fffff},
{ 0xdeb, 0xfe1ffe1f},
{ 0x9db, 0xfe1fffff},
{ 0xdec, 0xfe3ffe3f},
{ 0x9dc, 0xfe3fffff},
{ 0xded, 0xfe7ffe7f},
{ 0x9dd, 0xfe7fffff},
{ 0xff6, 0xfefefefe},
{ 0xdee, 0xfefffeff},
{ 0x9de, 0xfeffffff},
{ 0xa07, 0xff000000},
{ 0xa08, 0xff000001},
{ 0xa09, 0xff000003},
{ 0xa0a, 0xff000007},
{ 0xa0b, 0xff00000f},
{ 0xa0c, 0xff00001f},
{ 0xa0d, 0xff00003f},
{ 0xa0e, 0xff00007f},
{ 0xa0f, 0xff0000ff},
{ 0xa10, 0xff0001ff},
{ 0xa11, 0xff0003ff},
{ 0xa12, 0xff0007ff},
{ 0xa13, 0xff000fff},
{ 0xa14, 0xff001fff},
{ 0xa15, 0xff003fff},
{ 0xa16, 0xff007fff},
{ 0xe27, 0xff00ff00},
{ 0xa17, 0xff00ffff},
{ 0xe28, 0xff01ff01},
{ 0xa18, 0xff01ffff},
{ 0xe29, 0xff03ff03},
{ 0xa19, 0xff03ffff},
{ 0xe2a, 0xff07ff07},
{ 0xa1a, 0xff07ffff},
{ 0xe2b, 0xff0fff0f},
{ 0xa1b, 0xff0fffff},
{ 0xe2c, 0xff1fff1f},
{ 0xa1c, 0xff1fffff},
{ 0xe2d, 0xff3fff3f},
{ 0xa1d, 0xff3fffff},
{ 0xe2e, 0xff7fff7f},
{ 0xa1e, 0xff7fffff},
{ 0xa48, 0xff800000},
{ 0xa49, 0xff800001},
{ 0xa4a, 0xff800003},
{ 0xa4b, 0xff800007},
{ 0xa4c, 0xff80000f},
{ 0xa4d, 0xff80001f},
{ 0xa4e, 0xff80003f},
{ 0xa4f, 0xff80007f},
{ 0xa50, 0xff8000ff},
{ 0xa51, 0xff8001ff},
{ 0xa52, 0xff8003ff},
{ 0xa53, 0xff8007ff},
{ 0xa54, 0xff800fff},
{ 0xa55, 0xff801fff},
{ 0xa56, 0xff803fff},
{ 0xa57, 0xff807fff},
{ 0xe68, 0xff80ff80},
{ 0xa58, 0xff80ffff},
{ 0xe69, 0xff81ff81},
{ 0xa59, 0xff81ffff},
{ 0xe6a, 0xff83ff83},
{ 0xa5a, 0xff83ffff},
{ 0xe6b, 0xff87ff87},
{ 0xa5b, 0xff87ffff},
{ 0xe6c, 0xff8fff8f},
{ 0xa5c, 0xff8fffff},
{ 0xe6d, 0xff9fff9f},
{ 0xa5d, 0xff9fffff},
{ 0xe6e, 0xffbfffbf},
{ 0xa5e, 0xffbfffff},
{ 0xa89, 0xffc00000},
{ 0xa8a, 0xffc00001},
{ 0xa8b, 0xffc00003},
{ 0xa8c, 0xffc00007},
{ 0xa8d, 0xffc0000f},
{ 0xa8e, 0xffc0001f},
{ 0xa8f, 0xffc0003f},
{ 0xa90, 0xffc0007f},
{ 0xa91, 0xffc000ff},
{ 0xa92, 0xffc001ff},
{ 0xa93, 0xffc003ff},
{ 0xa94, 0xffc007ff},
{ 0xa95, 0xffc00fff},
{ 0xa96, 0xffc01fff},
{ 0xa97, 0xffc03fff},
{ 0xa98, 0xffc07fff},
{ 0xea9, 0xffc0ffc0},
{ 0xa99, 0xffc0ffff},
{ 0xeaa, 0xffc1ffc1},
{ 0xa9a, 0xffc1ffff},
{ 0xeab, 0xffc3ffc3},
{ 0xa9b, 0xffc3ffff},
{ 0xeac, 0xffc7ffc7},
{ 0xa9c, 0xffc7ffff},
{ 0xead, 0xffcfffcf},
{ 0xa9d, 0xffcfffff},
{ 0xeae, 0xffdfffdf},
{ 0xa9e, 0xffdfffff},
{ 0xaca, 0xffe00000},
{ 0xacb, 0xffe00001},
{ 0xacc, 0xffe00003},
{ 0xacd, 0xffe00007},
{ 0xace, 0xffe0000f},
{ 0xacf, 0xffe0001f},
{ 0xad0, 0xffe0003f},
{ 0xad1, 0xffe0007f},
{ 0xad2, 0xffe000ff},
{ 0xad3, 0xffe001ff},
{ 0xad4, 0xffe003ff},
{ 0xad5, 0xffe007ff},
{ 0xad6, 0xffe00fff},
{ 0xad7, 0xffe01fff},
{ 0xad8, 0xffe03fff},
{ 0xad9, 0xffe07fff},
{ 0xeea, 0xffe0ffe0},
{ 0xada, 0xffe0ffff},
{ 0xeeb, 0xffe1ffe1},
{ 0xadb, 0xffe1ffff},
{ 0xeec, 0xffe3ffe3},
{ 0xadc, 0xffe3ffff},
{ 0xeed, 0xffe7ffe7},
{ 0xadd, 0xffe7ffff},
{ 0xeee, 0xffefffef},
{ 0xade, 0xffefffff},
{ 0xb0b, 0xfff00000},
{ 0xb0c, 0xfff00001},
{ 0xb0d, 0xfff00003},
{ 0xb0e, 0xfff00007},
{ 0xb0f, 0xfff0000f},
{ 0xb10, 0xfff0001f},
{ 0xb11, 0xfff0003f},
{ 0xb12, 0xfff0007f},
{ 0xb13, 0xfff000ff},
{ 0xb14, 0xfff001ff},
{ 0xb15, 0xfff003ff},
{ 0xb16, 0xfff007ff},
{ 0xb17, 0xfff00fff},
{ 0xb18, 0xfff01fff},
{ 0xb19, 0xfff03fff},
{ 0xb1a, 0xfff07fff},
{ 0xf2b, 0xfff0fff0},
{ 0xb1b, 0xfff0ffff},
{ 0xf2c, 0xfff1fff1},
{ 0xb1c, 0xfff1ffff},
{ 0xf2d, 0xfff3fff3},
{ 0xb1d, 0xfff3ffff},
{ 0xf2e, 0xfff7fff7},
{ 0xb1e, 0xfff7ffff},
{ 0xb4c, 0xfff80000},
{ 0xb4d, 0xfff80001},
{ 0xb4e, 0xfff80003},
{ 0xb4f, 0xfff80007},
{ 0xb50, 0xfff8000f},
{ 0xb51, 0xfff8001f},
{ 0xb52, 0xfff8003f},
{ 0xb53, 0xfff8007f},
{ 0xb54, 0xfff800ff},
{ 0xb55, 0xfff801ff},
{ 0xb56, 0xfff803ff},
{ 0xb57, 0xfff807ff},
{ 0xb58, 0xfff80fff},
{ 0xb59, 0xfff81fff},
{ 0xb5a, 0xfff83fff},
{ 0xb5b, 0xfff87fff},
{ 0xf6c, 0xfff8fff8},
{ 0xb5c, 0xfff8ffff},
{ 0xf6d, 0xfff9fff9},
{ 0xb5d, 0xfff9ffff},
{ 0xf6e, 0xfffbfffb},
{ 0xb5e, 0xfffbffff},
{ 0xb8d, 0xfffc0000},
{ 0xb8e, 0xfffc0001},
{ 0xb8f, 0xfffc0003},
{ 0xb90, 0xfffc0007},
{ 0xb91, 0xfffc000f},
{ 0xb92, 0xfffc001f},
{ 0xb93, 0xfffc003f},
{ 0xb94, 0xfffc007f},
{ 0xb95, 0xfffc00ff},
{ 0xb96, 0xfffc01ff},
{ 0xb97, 0xfffc03ff},
{ 0xb98, 0xfffc07ff},
{ 0xb99, 0xfffc0fff},
{ 0xb9a, 0xfffc1fff},
{ 0xb9b, 0xfffc3fff},
{ 0xb9c, 0xfffc7fff},
{ 0xfad, 0xfffcfffc},
{ 0xb9d, 0xfffcffff},
{ 0xfae, 0xfffdfffd},
{ 0xb9e, 0xfffdffff},
{ 0xbce, 0xfffe0000},
{ 0xbcf, 0xfffe0001},
{ 0xbd0, 0xfffe0003},
{ 0xbd1, 0xfffe0007},
{ 0xbd2, 0xfffe000f},
{ 0xbd3, 0xfffe001f},
{ 0xbd4, 0xfffe003f},
{ 0xbd5, 0xfffe007f},
{ 0xbd6, 0xfffe00ff},
{ 0xbd7, 0xfffe01ff},
{ 0xbd8, 0xfffe03ff},
{ 0xbd9, 0xfffe07ff},
{ 0xbda, 0xfffe0fff},
{ 0xbdb, 0xfffe1fff},
{ 0xbdc, 0xfffe3fff},
{ 0xbdd, 0xfffe7fff},
{ 0xfee, 0xfffefffe},
{ 0xbde, 0xfffeffff},
{ 0xc0f, 0xffff0000},
{ 0xc10, 0xffff0001},
{ 0xc11, 0xffff0003},
{ 0xc12, 0xffff0007},
{ 0xc13, 0xffff000f},
{ 0xc14, 0xffff001f},
{ 0xc15, 0xffff003f},
{ 0xc16, 0xffff007f},
{ 0xc17, 0xffff00ff},
{ 0xc18, 0xffff01ff},
{ 0xc19, 0xffff03ff},
{ 0xc1a, 0xffff07ff},
{ 0xc1b, 0xffff0fff},
{ 0xc1c, 0xffff1fff},
{ 0xc1d, 0xffff3fff},
{ 0xc1e, 0xffff7fff},
{ 0xc50, 0xffff8000},
{ 0xc51, 0xffff8001},
{ 0xc52, 0xffff8003},
{ 0xc53, 0xffff8007},
{ 0xc54, 0xffff800f},
{ 0xc55, 0xffff801f},
{ 0xc56, 0xffff803f},
{ 0xc57, 0xffff807f},
{ 0xc58, 0xffff80ff},
{ 0xc59, 0xffff81ff},
{ 0xc5a, 0xffff83ff},
{ 0xc5b, 0xffff87ff},
{ 0xc5c, 0xffff8fff},
{ 0xc5d, 0xffff9fff},
{ 0xc5e, 0xffffbfff},
{ 0xc91, 0xffffc000},
{ 0xc92, 0xffffc001},
{ 0xc93, 0xffffc003},
{ 0xc94, 0xffffc007},
{ 0xc95, 0xffffc00f},
{ 0xc96, 0xffffc01f},
{ 0xc97, 0xffffc03f},
{ 0xc98, 0xffffc07f},
{ 0xc99, 0xffffc0ff},
{ 0xc9a, 0xffffc1ff},
{ 0xc9b, 0xffffc3ff},
{ 0xc9c, 0xffffc7ff},
{ 0xc9d, 0xffffcfff},
{ 0xc9e, 0xffffdfff},
{ 0xcd2, 0xffffe000},
{ 0xcd3, 0xffffe001},
{ 0xcd4, 0xffffe003},
{ 0xcd5, 0xffffe007},
{ 0xcd6, 0xffffe00f},
{ 0xcd7, 0xffffe01f},
{ 0xcd8, 0xffffe03f},
{ 0xcd9, 0xffffe07f},
{ 0xcda, 0xffffe0ff},
{ 0xcdb, 0xffffe1ff},
{ 0xcdc, 0xffffe3ff},
{ 0xcdd, 0xffffe7ff},
{ 0xcde, 0xffffefff},
{ 0xd13, 0xfffff000},
{ 0xd14, 0xfffff001},
{ 0xd15, 0xfffff003},
{ 0xd16, 0xfffff007},
{ 0xd17, 0xfffff00f},
{ 0xd18, 0xfffff01f},
{ 0xd19, 0xfffff03f},
{ 0xd1a, 0xfffff07f},
{ 0xd1b, 0xfffff0ff},
{ 0xd1c, 0xfffff1ff},
{ 0xd1d, 0xfffff3ff},
{ 0xd1e, 0xfffff7ff},
{ 0xd54, 0xfffff800},
{ 0xd55, 0xfffff801},
{ 0xd56, 0xfffff803},
{ 0xd57, 0xfffff807},
{ 0xd58, 0xfffff80f},
{ 0xd59, 0xfffff81f},
{ 0xd5a, 0xfffff83f},
{ 0xd5b, 0xfffff87f},
{ 0xd5c, 0xfffff8ff},
{ 0xd5d, 0xfffff9ff},
{ 0xd5e, 0xfffffbff},
{ 0xd95, 0xfffffc00},
{ 0xd96, 0xfffffc01},
{ 0xd97, 0xfffffc03},
{ 0xd98, 0xfffffc07},
{ 0xd99, 0xfffffc0f},
{ 0xd9a, 0xfffffc1f},
{ 0xd9b, 0xfffffc3f},
{ 0xd9c, 0xfffffc7f},
{ 0xd9d, 0xfffffcff},
{ 0xd9e, 0xfffffdff},
{ 0xdd6, 0xfffffe00},
{ 0xdd7, 0xfffffe01},
{ 0xdd8, 0xfffffe03},
{ 0xdd9, 0xfffffe07},
{ 0xdda, 0xfffffe0f},
{ 0xddb, 0xfffffe1f},
{ 0xddc, 0xfffffe3f},
{ 0xddd, 0xfffffe7f},
{ 0xdde, 0xfffffeff},
{ 0xe17, 0xffffff00},
{ 0xe18, 0xffffff01},
{ 0xe19, 0xffffff03},
{ 0xe1a, 0xffffff07},
{ 0xe1b, 0xffffff0f},
{ 0xe1c, 0xffffff1f},
{ 0xe1d, 0xffffff3f},
{ 0xe1e, 0xffffff7f},
{ 0xe58, 0xffffff80},
{ 0xe59, 0xffffff81},
{ 0xe5a, 0xffffff83},
{ 0xe5b, 0xffffff87},
{ 0xe5c, 0xffffff8f},
{ 0xe5d, 0xffffff9f},
{ 0xe5e, 0xffffffbf},
{ 0xe99, 0xffffffc0},
{ 0xe9a, 0xffffffc1},
{ 0xe9b, 0xffffffc3},
{ 0xe9c, 0xffffffc7},
{ 0xe9d, 0xffffffcf},
{ 0xe9e, 0xffffffdf},
{ 0xeda, 0xffffffe0},
{ 0xedb, 0xffffffe1},
{ 0xedc, 0xffffffe3},
{ 0xedd, 0xffffffe7},
{ 0xede, 0xffffffef},
{ 0xf1b, 0xfffffff0},
{ 0xf1c, 0xfffffff1},
{ 0xf1d, 0xfffffff3},
{ 0xf1e, 0xfffffff7},
{ 0xf5c, 0xfffffff8},
{ 0xf5d, 0xfffffff9},
{ 0xf5e, 0xfffffffb},
{ 0xf9d, 0xfffffffc},
{ 0xf9e, 0xfffffffd},
{ 0xfde, 0xfffffffe},
};
uint32_t
host_arm64_find_imm(uint32_t data)
{
int l = 0;
int r = IMM_NR - 1;
while (l <= r) {
int m = (l + r) >> 1;
if (imm_table[m][1] < data)
l = m + 1;
else if (imm_table[m][1] > data)
r = m - 1;
else
return imm_table[m][0];
}
return 0;
}
``` | /content/code_sandbox/src/codegen_new/codegen_backend_arm64_imm.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 19,160 |
```objective-c
#ifndef _CODEGEN_REG_H_
#define _CODEGEN_REG_H_
#define IREG_REG_MASK 0xff
#define IREG_SIZE_SHIFT 8
#define IREG_SIZE_MASK (7 << IREG_SIZE_SHIFT)
#define IREG_GET_REG(reg) ((reg) &IREG_REG_MASK)
#define IREG_GET_SIZE(reg) ((reg) &IREG_SIZE_MASK)
#define IREG_SIZE_L (0 << IREG_SIZE_SHIFT)
#define IREG_SIZE_W (1 << IREG_SIZE_SHIFT)
#define IREG_SIZE_B (2 << IREG_SIZE_SHIFT)
#define IREG_SIZE_BH (3 << IREG_SIZE_SHIFT)
#define IREG_SIZE_D (4 << IREG_SIZE_SHIFT)
#define IREG_SIZE_Q (5 << IREG_SIZE_SHIFT)
enum {
IREG_EAX = 0,
IREG_ECX = 1,
IREG_EDX = 2,
IREG_EBX = 3,
IREG_ESP = 4,
IREG_EBP = 5,
IREG_ESI = 6,
IREG_EDI = 7,
IREG_flags_op = 8,
IREG_flags_res = 9,
IREG_flags_op1 = 10,
IREG_flags_op2 = 11,
IREG_pc = 12,
IREG_oldpc = 13,
IREG_eaaddr = 14,
IREG_ea_seg = 15,
IREG_op32 = 16,
IREG_ssegsx = 17,
IREG_rm_mod_reg = 18,
IREG_acycs = 19,
IREG_cycles = 20,
IREG_CS_base = 21,
IREG_DS_base = 22,
IREG_ES_base = 23,
IREG_FS_base = 24,
IREG_GS_base = 25,
IREG_SS_base = 26,
IREG_CS_seg = 27,
IREG_DS_seg = 28,
IREG_ES_seg = 29,
IREG_FS_seg = 30,
IREG_GS_seg = 31,
IREG_SS_seg = 32,
/*Temporary registers are stored on the stack, and are not guaranteed to
be preserved across uOPs. They will not be written back if they will
not be read again.*/
IREG_temp0 = 33,
IREG_temp1 = 34,
IREG_temp2 = 35,
IREG_temp3 = 36,
IREG_FPU_TOP = 37,
IREG_temp0d = 38,
IREG_temp1d = 39,
/*FPU stack registers are physical registers. Use IREG_ST() / IREG_tag()
to access.
When CODEBLOCK_STATIC_TOP is set, the physical register number will be
used directly to index the stack. When it is clear, the difference
between the current value of TOP and the value when the block was
first compiled will be added to adjust for any changes in TOP.*/
IREG_ST0 = 40,
IREG_ST1 = 41,
IREG_ST2 = 42,
IREG_ST3 = 43,
IREG_ST4 = 44,
IREG_ST5 = 45,
IREG_ST6 = 46,
IREG_ST7 = 47,
IREG_tag0 = 48,
IREG_tag1 = 49,
IREG_tag2 = 50,
IREG_tag3 = 51,
IREG_tag4 = 52,
IREG_tag5 = 53,
IREG_tag6 = 54,
IREG_tag7 = 55,
IREG_ST0_i64 = 56,
IREG_ST1_i64 = 57,
IREG_ST2_i64 = 58,
IREG_ST3_i64 = 59,
IREG_ST4_i64 = 60,
IREG_ST5_i64 = 61,
IREG_ST6_i64 = 62,
IREG_ST7_i64 = 63,
IREG_MM0x = 64,
IREG_MM1x = 65,
IREG_MM2x = 66,
IREG_MM3x = 67,
IREG_MM4x = 68,
IREG_MM5x = 69,
IREG_MM6x = 70,
IREG_MM7x = 71,
IREG_NPXCx = 72,
IREG_NPXSx = 73,
IREG_flagsx = 74,
IREG_eflagsx = 75,
IREG_CS_limit_low = 76,
IREG_DS_limit_low = 77,
IREG_ES_limit_low = 78,
IREG_FS_limit_low = 79,
IREG_GS_limit_low = 80,
IREG_SS_limit_low = 81,
IREG_CS_limit_high = 82,
IREG_DS_limit_high = 83,
IREG_ES_limit_high = 84,
IREG_FS_limit_high = 85,
IREG_GS_limit_high = 86,
IREG_SS_limit_high = 87,
IREG_COUNT = 88,
IREG_INVALID = 255,
IREG_AX = IREG_EAX + IREG_SIZE_W,
IREG_CX = IREG_ECX + IREG_SIZE_W,
IREG_DX = IREG_EDX + IREG_SIZE_W,
IREG_BX = IREG_EBX + IREG_SIZE_W,
IREG_SP = IREG_ESP + IREG_SIZE_W,
IREG_BP = IREG_EBP + IREG_SIZE_W,
IREG_SI = IREG_ESI + IREG_SIZE_W,
IREG_DI = IREG_EDI + IREG_SIZE_W,
IREG_AL = IREG_EAX + IREG_SIZE_B,
IREG_CL = IREG_ECX + IREG_SIZE_B,
IREG_DL = IREG_EDX + IREG_SIZE_B,
IREG_BL = IREG_EBX + IREG_SIZE_B,
IREG_AH = IREG_EAX + IREG_SIZE_BH,
IREG_CH = IREG_ECX + IREG_SIZE_BH,
IREG_DH = IREG_EDX + IREG_SIZE_BH,
IREG_BH = IREG_EBX + IREG_SIZE_BH,
IREG_flags_res_W = IREG_flags_res + IREG_SIZE_W,
IREG_flags_op1_W = IREG_flags_op1 + IREG_SIZE_W,
IREG_flags_op2_W = IREG_flags_op2 + IREG_SIZE_W,
IREG_flags_res_B = IREG_flags_res + IREG_SIZE_B,
IREG_flags_op1_B = IREG_flags_op1 + IREG_SIZE_B,
IREG_flags_op2_B = IREG_flags_op2 + IREG_SIZE_B,
IREG_temp0_W = IREG_temp0 + IREG_SIZE_W,
IREG_temp1_W = IREG_temp1 + IREG_SIZE_W,
IREG_temp2_W = IREG_temp2 + IREG_SIZE_W,
IREG_temp3_W = IREG_temp3 + IREG_SIZE_W,
IREG_temp0_B = IREG_temp0 + IREG_SIZE_B,
IREG_temp1_B = IREG_temp1 + IREG_SIZE_B,
IREG_temp2_B = IREG_temp2 + IREG_SIZE_B,
IREG_temp3_B = IREG_temp3 + IREG_SIZE_B,
IREG_temp0_D = IREG_temp0d + IREG_SIZE_D,
IREG_temp1_D = IREG_temp1d + IREG_SIZE_D,
IREG_temp0_Q = IREG_temp0d + IREG_SIZE_Q,
IREG_temp1_Q = IREG_temp1d + IREG_SIZE_Q,
IREG_eaaddr_W = IREG_eaaddr + IREG_SIZE_W,
IREG_CS_seg_W = IREG_CS_seg + IREG_SIZE_W,
IREG_DS_seg_W = IREG_DS_seg + IREG_SIZE_W,
IREG_ES_seg_W = IREG_ES_seg + IREG_SIZE_W,
IREG_FS_seg_W = IREG_FS_seg + IREG_SIZE_W,
IREG_GS_seg_W = IREG_GS_seg + IREG_SIZE_W,
IREG_SS_seg_W = IREG_SS_seg + IREG_SIZE_W,
IREG_MM0 = IREG_MM0x + IREG_SIZE_Q,
IREG_MM1 = IREG_MM1x + IREG_SIZE_Q,
IREG_MM2 = IREG_MM2x + IREG_SIZE_Q,
IREG_MM3 = IREG_MM3x + IREG_SIZE_Q,
IREG_MM4 = IREG_MM4x + IREG_SIZE_Q,
IREG_MM5 = IREG_MM5x + IREG_SIZE_Q,
IREG_MM6 = IREG_MM6x + IREG_SIZE_Q,
IREG_MM7 = IREG_MM7x + IREG_SIZE_Q,
IREG_NPXC = IREG_NPXCx + IREG_SIZE_W,
IREG_NPXS = IREG_NPXSx + IREG_SIZE_W,
IREG_ssegs = IREG_ssegsx + IREG_SIZE_B,
IREG_flags = IREG_flagsx + IREG_SIZE_W,
IREG_eflags = IREG_eflagsx + IREG_SIZE_W
};
#define IREG_8(reg) (((reg) &4) ? (((reg) &3) + IREG_AH) : ((reg) + IREG_AL))
#define IREG_16(reg) ((reg) + IREG_AX)
#define IREG_32(reg) ((reg) + IREG_EAX)
#define IREG_ST(r) (IREG_ST0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_D)
#define IREG_ST_i64(r) (IREG_ST0_i64 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_Q)
#define IREG_tag(r) (IREG_tag0 + ((cpu_state.TOP + (r)) & 7))
#define IREG_tag_B(r) (IREG_tag0 + ((cpu_state.TOP + (r)) & 7) + IREG_SIZE_B)
#define IREG_MM(reg) ((reg) + IREG_MM0)
#define IREG_TOP_diff_stack_offset 32
static inline int
ireg_seg_base(x86seg *seg)
{
if (seg == &cpu_state.seg_cs)
return IREG_CS_base;
if (seg == &cpu_state.seg_ds)
return IREG_DS_base;
if (seg == &cpu_state.seg_es)
return IREG_ES_base;
if (seg == &cpu_state.seg_fs)
return IREG_FS_base;
if (seg == &cpu_state.seg_gs)
return IREG_GS_base;
if (seg == &cpu_state.seg_ss)
return IREG_SS_base;
fatal("ireg_seg_base : unknown segment\n");
return 0;
}
static inline int
ireg_seg_limit_low(x86seg *seg)
{
if (seg == &cpu_state.seg_cs)
return IREG_CS_limit_low;
if (seg == &cpu_state.seg_ds)
return IREG_DS_limit_low;
if (seg == &cpu_state.seg_es)
return IREG_ES_limit_low;
if (seg == &cpu_state.seg_fs)
return IREG_FS_limit_low;
if (seg == &cpu_state.seg_gs)
return IREG_GS_limit_low;
if (seg == &cpu_state.seg_ss)
return IREG_SS_limit_low;
fatal("ireg_seg_limit_low : unknown segment\n");
return 0;
}
static inline int
ireg_seg_limit_high(x86seg *seg)
{
if (seg == &cpu_state.seg_cs)
return IREG_CS_limit_high;
if (seg == &cpu_state.seg_ds)
return IREG_DS_limit_high;
if (seg == &cpu_state.seg_es)
return IREG_ES_limit_high;
if (seg == &cpu_state.seg_fs)
return IREG_FS_limit_high;
if (seg == &cpu_state.seg_gs)
return IREG_GS_limit_high;
if (seg == &cpu_state.seg_ss)
return IREG_SS_limit_high;
fatal("ireg_seg_limit_high : unknown segment\n");
return 0;
}
extern uint8_t reg_last_version[IREG_COUNT];
/*This version of the register must be calculated, regardless of whether it is
apparently required or not. Do not optimise out.*/
#define REG_FLAGS_REQUIRED (1 << 0)
/*This register and the parent uOP have been optimised out.*/
#define REG_FLAGS_DEAD (1 << 1)
typedef struct {
/*Refcount of pending reads on this register version*/
uint8_t refcount;
/*Flags*/
uint8_t flags;
/*uOP that generated this register version*/
uint16_t parent_uop;
/*Pointer to next register version in dead register list*/
uint16_t next;
} reg_version_t;
extern reg_version_t reg_version[IREG_COUNT][256];
/*Head of dead register list; a list of register versions that are not used and
can be optimised out*/
extern uint16_t reg_dead_list;
static inline void
add_to_dead_list(reg_version_t *regv, int reg, int version)
{
regv->next = reg_dead_list;
reg_dead_list = version | (reg << 8);
}
typedef struct {
uint16_t reg;
uint16_t version;
} ir_reg_t;
extern ir_reg_t invalid_ir_reg;
typedef uint16_t ir_host_reg_t;
extern int max_version_refcount;
#define REG_VERSION_MAX 250
#define REG_REFCOUNT_MAX 250
static inline ir_reg_t
codegen_reg_read(int reg)
{
ir_reg_t ireg;
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_read - IREG_INVALID\n");
#endif
ireg.reg = reg;
ireg.version = reg_last_version[IREG_GET_REG(reg)];
version = ®_version[IREG_GET_REG(ireg.reg)][ireg.version];
version->flags = 0;
version->refcount++;
#ifndef RELEASE_BUILD
if (!version->refcount)
fatal("codegen_reg_read - refcount overflow\n");
else
#endif
if (version->refcount > REG_REFCOUNT_MAX)
CPU_BLOCK_END();
if (version->refcount > max_version_refcount)
max_version_refcount = version->refcount;
#if 0
pclog("codegen_reg_read: %i %i %i\n", reg & IREG_REG_MASK, ireg.version, reg_version_refcount[IREG_GET_REG(ireg.reg)][ireg.version]);
#endif
return ireg;
}
int reg_is_native_size(ir_reg_t ir_reg);
static inline ir_reg_t
codegen_reg_write(int reg, int uop_nr)
{
ir_reg_t ireg;
int last_version = reg_last_version[IREG_GET_REG(reg)];
reg_version_t *version;
#ifndef RELEASE_BUILD
if (IREG_GET_REG(reg) == IREG_INVALID)
fatal("codegen_reg_write - IREG_INVALID\n");
#endif
ireg.reg = reg;
ireg.version = last_version + 1;
if (IREG_GET_REG(reg) > IREG_EBX && last_version && !reg_version[IREG_GET_REG(reg)][last_version].refcount && !(reg_version[IREG_GET_REG(reg)][last_version].flags & REG_FLAGS_REQUIRED)) {
if (reg_is_native_size(ireg)) /*Non-native size registers have an implicit dependency on the previous version, so don't add to dead list*/
add_to_dead_list(®_version[IREG_GET_REG(reg)][last_version], IREG_GET_REG(reg), last_version);
}
reg_last_version[IREG_GET_REG(reg)]++;
#ifndef RELEASE_BUILD
if (!reg_last_version[IREG_GET_REG(reg)])
fatal("codegen_reg_write - version overflow\n");
else
#endif
if (reg_last_version[IREG_GET_REG(reg)] > REG_VERSION_MAX)
CPU_BLOCK_END();
if (reg_last_version[IREG_GET_REG(reg)] > max_version_refcount)
max_version_refcount = reg_last_version[IREG_GET_REG(reg)];
version = ®_version[IREG_GET_REG(reg)][ireg.version];
version->refcount = 0;
version->flags = 0;
version->parent_uop = uop_nr;
#if 0
pclog("codegen_reg_write: %i\n", reg & IREG_REG_MASK);
#endif
return ireg;
}
static inline int
ir_reg_is_invalid(ir_reg_t ir_reg)
{
return (IREG_GET_REG(ir_reg.reg) == IREG_INVALID);
}
struct ir_data_t;
void codegen_reg_reset(void);
/*Write back all dirty registers*/
void codegen_reg_flush(struct ir_data_t *ir, codeblock_t *block);
/*Write back and evict all registers*/
void codegen_reg_flush_invalidate(struct ir_data_t *ir, codeblock_t *block);
/*Register ir_reg usage for this uOP. This ensures that required registers aren't evicted*/
void codegen_reg_alloc_register(ir_reg_t dest_reg_a, ir_reg_t src_reg_a, ir_reg_t src_reg_b, ir_reg_t src_reg_c);
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
int codegen_reg_is_loaded(ir_reg_t ir_reg);
void codegen_reg_write_imm(codeblock_t *block, ir_reg_t ir_reg, uint32_t imm_data);
#endif
ir_host_reg_t codegen_reg_alloc_read_reg(codeblock_t *block, ir_reg_t ir_reg, int *host_reg_idx);
ir_host_reg_t codegen_reg_alloc_write_reg(codeblock_t *block, ir_reg_t ir_reg);
void codegen_reg_rename(codeblock_t *block, ir_reg_t src, ir_reg_t dst);
void codegen_reg_mark_as_required(void);
void codegen_reg_process_dead_list(struct ir_data_t *ir);
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_reg.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,007 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_mmx_logic.h"
#include "codegen_ops_helpers.h"
uint32_t
ropPAND(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q);
}
return op_pc + 1;
}
uint32_t
ropPANDN(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_ANDN(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_ANDN(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q);
}
return op_pc + 1;
}
uint32_t
ropPOR(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_OR(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q);
}
return op_pc + 1;
}
uint32_t
ropPXOR(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_XOR(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q);
}
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_logic.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,223 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_logic.h"
uint32_t
ropAND_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_AND_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropAND_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_AND_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropAND_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_AND(ir, IREG_EAX, IREG_EAX, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
uop_AND_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
return op_pc + 4;
}
uint32_t
ropAND_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropAND_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_AND(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_temp0_B, IREG_temp0_B, IREG_8(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropAND_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropAND_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_AND(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_temp0_W, IREG_temp0_W, IREG_16(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropAND_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropAND_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_AND(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_temp0, IREG_temp0, IREG_32(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_OR_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropOR_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_OR_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropOR_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_OR(ir, IREG_EAX, IREG_EAX, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
uop_OR_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropOR_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_OR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_OR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_temp0_B, IREG_temp0_B, IREG_8(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_OR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_OR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_temp0_W, IREG_temp0_W, IREG_16(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_OR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, dest_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropOR_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_OR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_OR(ir, IREG_temp0, IREG_temp0, IREG_32(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropTEST_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropTEST_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropTEST_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_AND(ir, IREG_flags_res, IREG_EAX, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
uop_AND_IMM(ir, IREG_flags_res, IREG_EAX, fetchdat);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropTEST_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res_B, IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_B);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropTEST_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res_W, IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOVZX(ir, IREG_flags_res, IREG_flags_res_W);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropTEST_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_AND(ir, IREG_flags_res, IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_AND(ir, IREG_flags_res, IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_AL_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm_data = fastreadb(cs + op_pc);
uop_XOR_IMM(ir, IREG_AL, IREG_AL, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_AL);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropXOR_AX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm_data = fastreadw(cs + op_pc);
uop_XOR_IMM(ir, IREG_AX, IREG_AX, imm_data);
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_AX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropXOR_EAX_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_temp0, cs + op_pc);
uop_XOR(ir, IREG_EAX, IREG_EAX, IREG_temp0);
} else {
fetchdat = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
uop_XOR_IMM(ir, IREG_EAX, IREG_EAX, fetchdat);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, IREG_EAX);
codegen_flags_changed = 1;
codegen_mark_code_present(block, cs + op_pc, 4);
return op_pc + 4;
}
uint32_t
ropXOR_b_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_XOR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_b_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_XOR(ir, IREG_8(dest_reg), IREG_8(dest_reg), IREG_8(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_8(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_temp0_B, IREG_temp0_B, IREG_8(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_B);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_B);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN8);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_w_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_XOR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_w_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_XOR(ir, IREG_16(dest_reg), IREG_16(dest_reg), IREG_16(src_reg));
uop_MOVZX(ir, IREG_flags_res, IREG_16(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_temp0_W, IREG_temp0_W, IREG_16(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0_W);
uop_MOVZX(ir, IREG_flags_res, IREG_temp0_W);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN16);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_l_rm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_XOR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
uop_MOV(ir, IREG_flags_res, dest_reg);
codegen_flags_changed = 1;
return op_pc + 1;
}
uint32_t
ropXOR_l_rmw(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_XOR(ir, IREG_32(dest_reg), IREG_32(dest_reg), IREG_32(src_reg));
uop_MOV(ir, IREG_flags_res, IREG_32(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_XOR(ir, IREG_temp0, IREG_temp0, IREG_32(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
uop_MOV(ir, IREG_flags_res, IREG_temp0);
}
uop_MOV_IMM(ir, IREG_flags_op, FLAGS_ZN32);
codegen_flags_changed = 1;
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_logic.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,207 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "x87_sf.h"
#include "x87.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_fpu_arith.h"
#include "codegen_ops_helpers.h"
uint32_t
ropFADD(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_ST(src_reg));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFADDr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FADD(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFADDP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FADD(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFCOM(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(src_reg));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
return op_pc;
}
uint32_t
ropFCOMP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(src_reg));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFCOMPP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(1));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
fpu_POP2(block, ir);
return op_pc;
}
uint32_t
ropFDIV(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_ST(src_reg));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFDIVR(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(0), IREG_ST(src_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFDIVr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFDIVRr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(dest_reg), IREG_ST(0), IREG_ST(dest_reg));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFDIVP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFDIVRP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FDIV(ir, IREG_ST(dest_reg), IREG_ST(0), IREG_ST(dest_reg));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFMUL(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_ST(src_reg));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFMULr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FMUL(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFMULP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FMUL(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFSUB(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_ST(src_reg));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFSUBR(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(0), IREG_ST(src_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFSUBr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFSUBRr(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(dest_reg), IREG_ST(0), IREG_ST(dest_reg));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
return op_pc;
}
uint32_t
ropFSUBP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(dest_reg), IREG_ST(dest_reg), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFSUBRP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FSUB(ir, IREG_ST(dest_reg), IREG_ST(0), IREG_ST(dest_reg));
uop_MOV_IMM(ir, IREG_tag(dest_reg), TAG_VALID);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFUCOM(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(src_reg));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
return op_pc;
}
uint32_t
ropFUCOMP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(src_reg));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFUCOMPP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FCOM(ir, IREG_temp0_W, IREG_ST(0), IREG_ST(1));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
fpu_POP2(block, ir);
return op_pc;
}
#define ropF_arith_mem(name, load_uop) \
uint32_t ropFADD##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
if ((cpu_state.npxc >> 10) & 3) \
return 0; \
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFCOM##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFCOMP##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFDIV##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFDIVR##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFMUL##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUB##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUBR##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
}
// clang-format off
ropF_arith_mem(s, uop_MEM_LOAD_SINGLE)
ropF_arith_mem(d, uop_MEM_LOAD_DOUBLE)
// clang-format on
#define ropFI_arith_mem(name, temp_reg) \
uint32_t ropFIADD##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFICOM##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFICOMP##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIV##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIVR##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIMUL##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUB##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUBR##name(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
}
ropFI_arith_mem(l, IREG_temp0)
ropFI_arith_mem(w, IREG_temp0_W)
uint32_t
ropFABS(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FABS(ir, IREG_ST(0), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFCHS(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FCHS(ir, IREG_ST(0), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFSQRT(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FSQRT(ir, IREG_ST(0), IREG_ST(0));
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID);
return op_pc;
}
uint32_t
ropFTST(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_FTST(ir, IREG_temp0_W, IREG_ST(0));
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3));
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp0_W);
return op_pc;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_arith.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,006 |
```c
#if defined __amd64__ || defined _M_X64
# include <stdlib.h>
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86-64_defs.h"
# include "codegen_backend_x86-64_ops.h"
# include "codegen_backend_x86-64_ops_sse.h"
# include "codegen_reg.h"
# include "x86.h"
# include "x86seg_common.h"
# include "x86seg.h"
# if defined(__linux__) || defined(__APPLE__)
# include <sys/mman.h>
# include <unistd.h>
# endif
# if defined WIN32 || defined _WIN32 || defined _WIN32
# include <windows.h>
# endif
# include <string.h>
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
void *codegen_mem_load_quad;
void *codegen_mem_load_single;
void *codegen_mem_load_double;
void *codegen_mem_store_byte;
void *codegen_mem_store_word;
void *codegen_mem_store_long;
void *codegen_mem_store_quad;
void *codegen_mem_store_single;
void *codegen_mem_store_double;
void *codegen_gpf_rout;
void *codegen_exit_rout;
host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] = {
/*Note: while EAX and EDX are normally volatile registers under x86
calling conventions, the recompiler will explicitly save and restore
them across funcion calls*/
{REG_EAX, 0},
{ REG_EBX, 0},
{ REG_EDX, 0}
};
host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] = {
# if _WIN64
/*Windows x86-64 calling convention preserves XMM6-XMM15*/
{REG_XMM6, 0 },
{ REG_XMM7, 0 },
# else
/*System V AMD64 calling convention does not preserve any XMM registers*/
{ REG_XMM6, HOST_REG_FLAG_VOLATILE },
{ REG_XMM7, HOST_REG_FLAG_VOLATILE },
# endif
{ REG_XMM1, HOST_REG_FLAG_VOLATILE},
{ REG_XMM2, HOST_REG_FLAG_VOLATILE},
{ REG_XMM3, HOST_REG_FLAG_VOLATILE},
{ REG_XMM4, HOST_REG_FLAG_VOLATILE},
{ REG_XMM5, HOST_REG_FLAG_VOLATILE}
};
static void
build_load_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ESI = address
Out - ECX = data, ESI = abrt*/
/*MOV ECX, ESI
SHR ESI, 12
MOV RSI, [readlookup2+ESI*4]
CMP ESI, -1
JNZ +
MOVZX ECX, B[RSI+RCX]
XOR ESI,ESI
RET
* PUSH EAX
PUSH EDX
PUSH ECX
CALL readmembl
POP ECX
POP EDX
POP EAX
MOVZX ECX, AL
RET
*/
host_x86_MOV32_REG_REG(block, REG_ECX, REG_ESI);
host_x86_SHR32_IMM(block, REG_ESI, 12);
host_x86_MOV64_REG_IMM(block, REG_RDI, (uint64_t) (uintptr_t) readlookup2);
host_x86_MOV64_REG_BASE_INDEX_SHIFT(block, REG_RSI, REG_RDI, REG_RSI, 3);
if (size != 1) {
host_x86_TEST32_REG_IMM(block, REG_ECX, size - 1);
misaligned_offset = host_x86_JNZ_short(block);
}
host_x86_CMP64_REG_IMM(block, REG_RSI, (uint32_t) -1);
branch_offset = host_x86_JZ_short(block);
if (size == 1 && !is_float)
host_x86_MOVZX_BASE_INDEX_32_8(block, REG_ECX, REG_RSI, REG_RCX);
else if (size == 2 && !is_float)
host_x86_MOVZX_BASE_INDEX_32_16(block, REG_ECX, REG_RSI, REG_RCX);
else if (size == 4 && !is_float)
host_x86_MOV32_REG_BASE_INDEX(block, REG_ECX, REG_RSI, REG_RCX);
else if (size == 4 && is_float)
host_x86_CVTSS2SD_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_RSI, REG_RCX);
else if (size == 8)
host_x86_MOVQ_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_RSI, REG_RCX);
else
fatal("build_load_routine: size=%i\n", size);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
host_x86_RET(block);
*branch_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 1;
if (size != 1)
*misaligned_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
# if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x20);
// host_x86_MOV32_REG_REG(block, REG_ECX, uop->imm_data);
# else
host_x86_MOV32_REG_REG(block, REG_EDI, REG_ECX);
# endif
if (size == 1 && !is_float) {
host_x86_CALL(block, (void *) readmembl);
host_x86_MOVZX_REG_32_8(block, REG_ECX, REG_EAX);
} else if (size == 2 && !is_float) {
host_x86_CALL(block, (void *) readmemwl);
host_x86_MOVZX_REG_32_16(block, REG_ECX, REG_EAX);
} else if (size == 4 && !is_float) {
host_x86_CALL(block, (void *) readmemll);
host_x86_MOV32_REG_REG(block, REG_ECX, REG_EAX);
} else if (size == 4 && is_float) {
host_x86_CALL(block, (void *) readmemll);
host_x86_MOVD_XREG_REG(block, REG_XMM_TEMP, REG_EAX);
host_x86_CVTSS2SD_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP);
} else if (size == 8) {
host_x86_CALL(block, (void *) readmemql);
host_x86_MOVQ_XREG_REG(block, REG_XMM_TEMP, REG_RAX);
}
# if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x20);
# endif
host_x86_POP(block, REG_RDX);
host_x86_POP(block, REG_RAX);
host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
host_x86_RET(block);
}
static void
build_store_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ECX = data, ESI = address
Out - ESI = abrt
Corrupts EDI*/
/*MOV EDI, ESI
SHR ESI, 12
MOV ESI, [writelookup2+ESI*4]
CMP ESI, -1
JNZ +
MOV [RSI+RDI], ECX
XOR ESI,ESI
RET
* PUSH EAX
PUSH EDX
PUSH ECX
CALL writemembl
POP ECX
POP EDX
POP EAX
MOVZX ECX, AL
RET
*/
host_x86_MOV32_REG_REG(block, REG_EDI, REG_ESI);
host_x86_SHR32_IMM(block, REG_ESI, 12);
host_x86_MOV64_REG_IMM(block, REG_R8, (uint64_t) (uintptr_t) writelookup2);
host_x86_MOV64_REG_BASE_INDEX_SHIFT(block, REG_RSI, REG_R8, REG_RSI, 3);
if (size != 1) {
host_x86_TEST32_REG_IMM(block, REG_EDI, size - 1);
misaligned_offset = host_x86_JNZ_short(block);
}
host_x86_CMP64_REG_IMM(block, REG_RSI, (uint32_t) -1);
branch_offset = host_x86_JZ_short(block);
if (size == 1 && !is_float)
host_x86_MOV8_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
else if (size == 2 && !is_float)
host_x86_MOV16_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
else if (size == 4 && !is_float)
host_x86_MOV32_BASE_INDEX_REG(block, REG_RSI, REG_RDI, REG_ECX);
else if (size == 4 && is_float)
host_x86_MOVD_BASE_INDEX_XREG(block, REG_RSI, REG_RDI, REG_XMM_TEMP);
else if (size == 8)
host_x86_MOVQ_BASE_INDEX_XREG(block, REG_RSI, REG_RDI, REG_XMM_TEMP);
else
fatal("build_store_routine: size=%i\n", size);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
host_x86_RET(block);
*branch_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 1;
if (size != 1)
*misaligned_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 1;
host_x86_PUSH(block, REG_RAX);
host_x86_PUSH(block, REG_RDX);
# if _WIN64
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x28);
if (size == 4 && is_float)
host_x86_MOVD_REG_XREG(block, REG_EDX, REG_XMM_TEMP); // data
else if (size == 8)
host_x86_MOVQ_REG_XREG(block, REG_RDX, REG_XMM_TEMP); // data
else
host_x86_MOV32_REG_REG(block, REG_EDX, REG_ECX); // data
host_x86_MOV32_REG_REG(block, REG_ECX, REG_EDI); // address
# else
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x8);
// host_x86_MOV32_REG_REG(block, REG_EDI, REG_ECX); //address
if (size == 4 && is_float)
host_x86_MOVD_REG_XREG(block, REG_ESI, REG_XMM_TEMP); // data
else if (size == 8)
host_x86_MOVQ_REG_XREG(block, REG_RSI, REG_XMM_TEMP); // data
else
host_x86_MOV32_REG_REG(block, REG_ESI, REG_ECX); // data
# endif
if (size == 1)
host_x86_CALL(block, (void *) writemembl);
else if (size == 2)
host_x86_CALL(block, (void *) writememwl);
else if (size == 4)
host_x86_CALL(block, (void *) writememll);
else if (size == 8)
host_x86_CALL(block, (void *) writememql);
# if _WIN64
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x28);
# else
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x8);
# endif
host_x86_POP(block, REG_RDX);
host_x86_POP(block, REG_RAX);
host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
host_x86_RET(block);
}
static void
build_loadstore_routines(codeblock_t *block)
{
codegen_mem_load_byte = &codeblock[block_current].data[block_pos];
build_load_routine(block, 1, 0);
codegen_mem_load_word = &codeblock[block_current].data[block_pos];
build_load_routine(block, 2, 0);
codegen_mem_load_long = &codeblock[block_current].data[block_pos];
build_load_routine(block, 4, 0);
codegen_mem_load_quad = &codeblock[block_current].data[block_pos];
build_load_routine(block, 8, 0);
codegen_mem_load_single = &codeblock[block_current].data[block_pos];
build_load_routine(block, 4, 1);
codegen_mem_load_double = &codeblock[block_current].data[block_pos];
build_load_routine(block, 8, 1);
codegen_mem_store_byte = &codeblock[block_current].data[block_pos];
build_store_routine(block, 1, 0);
codegen_mem_store_word = &codeblock[block_current].data[block_pos];
build_store_routine(block, 2, 0);
codegen_mem_store_long = &codeblock[block_current].data[block_pos];
build_store_routine(block, 4, 0);
codegen_mem_store_quad = &codeblock[block_current].data[block_pos];
build_store_routine(block, 8, 0);
codegen_mem_store_single = &codeblock[block_current].data[block_pos];
build_store_routine(block, 4, 1);
codegen_mem_store_double = &codeblock[block_current].data[block_pos];
build_store_routine(block, 8, 1);
}
void
codegen_backend_init(void)
{
codeblock_t *block;
int c;
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
for (c = 0; c < BLOCK_SIZE; c++)
codeblock[c].pc = BLOCK_PC_INVALID;
block_current = 0;
block_pos = 0;
block = &codeblock[block_current];
codeblock[block_current].head_mem_block = codegen_allocator_allocate(NULL, block_current);
codeblock[block_current].data = codeblock_allocator_get_ptr(codeblock[block_current].head_mem_block);
block_write_data = codeblock[block_current].data;
build_loadstore_routines(&codeblock[block_current]);
codegen_gpf_rout = &codeblock[block_current].data[block_pos];
# if _WIN64
host_x86_XOR32_REG_REG(block, REG_ECX, REG_ECX);
host_x86_XOR32_REG_REG(block, REG_EDX, REG_EDX);
# else
host_x86_XOR32_REG_REG(block, REG_EDI, REG_EDI);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
# endif
host_x86_CALL(block, (void *) x86gpf);
codegen_exit_rout = &codeblock[block_current].data[block_pos];
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x38);
host_x86_POP(block, REG_R15);
host_x86_POP(block, REG_R14);
host_x86_POP(block, REG_R13);
host_x86_POP(block, REG_R12);
host_x86_POP(block, REG_RDI);
host_x86_POP(block, REG_RSI);
host_x86_POP(block, REG_RBP);
host_x86_POP(block, REG_RDX);
host_x86_RET(block);
block_write_data = NULL;
asm(
"stmxcsr %0\n"
: "=m"(cpu_state.old_fp_control));
cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
}
void
codegen_set_rounding_mode(int mode)
{
cpu_state.new_fp_control = (cpu_state.old_fp_control & ~0x6000) | (mode << 13);
}
void
codegen_backend_prologue(codeblock_t *block)
{
block_pos = BLOCK_START; /*Entry code*/
host_x86_PUSH(block, REG_RBX);
host_x86_PUSH(block, REG_RBP);
host_x86_PUSH(block, REG_RSI);
host_x86_PUSH(block, REG_RDI);
host_x86_PUSH(block, REG_R12);
host_x86_PUSH(block, REG_R13);
host_x86_PUSH(block, REG_R14);
host_x86_PUSH(block, REG_R15);
host_x86_SUB64_REG_IMM(block, REG_RSP, 0x38);
host_x86_MOV64_REG_IMM(block, REG_RBP, ((uintptr_t) &cpu_state) + 128);
if (block->flags & CODEBLOCK_HAS_FPU) {
host_x86_MOV32_REG_ABS(block, REG_EAX, &cpu_state.TOP);
host_x86_SUB32_REG_IMM(block, REG_EAX, block->TOP);
host_x86_MOV32_BASE_OFFSET_REG(block, REG_RSP, IREG_TOP_diff_stack_offset, REG_EAX);
}
if (block->flags & CODEBLOCK_NO_IMMEDIATES)
host_x86_MOV64_REG_IMM(block, REG_R12, (uintptr_t) ram);
}
void
codegen_backend_epilogue(codeblock_t *block)
{
host_x86_ADD64_REG_IMM(block, REG_RSP, 0x38);
host_x86_POP(block, REG_R15);
host_x86_POP(block, REG_R14);
host_x86_POP(block, REG_R13);
host_x86_POP(block, REG_R12);
host_x86_POP(block, REG_RDI);
host_x86_POP(block, REG_RSI);
host_x86_POP(block, REG_RBP);
host_x86_POP(block, REG_RDX);
host_x86_RET(block);
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,161 |
```objective-c
#include "codegen_backend_x86-64_defs.h"
#define BLOCK_SIZE 0x4000
#define BLOCK_MASK 0x3fff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_MAX 0x3c0
#define CODEGEN_BACKEND_HAS_MOV_IMM
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 91 |
```objective-c
uint32_t ropPCMPEQB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPEQW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPEQD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPGTB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPGTW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPGTD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_cmp.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 264 |
```c
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86_defs.h"
# include "codegen_backend_x86_ops_fpu.h"
# include "codegen_backend_x86_ops_helpers.h"
void
host_x87_FILDq_BASE(codeblock_t *block, int base_reg)
{
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xdf, 0x2c, 0x24); /*FILDq [ESP]*/
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xdf, 0x28 | base_reg); /*FILDq [base_reg]*/
}
}
void
host_x87_FISTPq_BASE(codeblock_t *block, int base_reg)
{
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xdf, 0x3c, 0x24); /*FISTPq [ESP]*/
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xdf, 0x38 | base_reg); /*FISTPq [base_reg]*/
}
}
void
host_x87_FLDCW(codeblock_t *block, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xd9, 0x68 | REG_EBP, offset); /*FLDCW offset[EBP]*/
} else {
codegen_alloc_bytes(block, 6);
codegen_addbyte2(block, 0xd9, 0x2d); /*FLDCW [p]*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x87_FLDd_BASE(codeblock_t *block, int base_reg)
{
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xdd, 0x04, 0x24); /*FILDq [ESP]*/
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xdd, 0x08 | base_reg); /*FILDq [base_reg]*/
}
}
void
host_x87_FSTPd_BASE(codeblock_t *block, int base_reg)
{
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0xdd, 0x1c, 0x24); /*FILDq [ESP]*/
} else {
codegen_alloc_bytes(block, 2);
codegen_addbyte2(block, 0xdd, 0x18 | base_reg); /*FILDq [base_reg]*/
}
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops_fpu.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 769 |
```objective-c
#define JMP_LEN_BYTES 5
static inline void
codegen_addbyte(UNUSED(codeblock_t *block), uint8_t val)
{
if (block_pos >= BLOCK_MAX) {
fatal("codegen_addbyte over! %i\n", block_pos);
#if 0
CPU_BLOCK_END();
#endif
}
block_write_data[block_pos++] = val;
}
static inline void
codegen_addbyte2(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb)
{
if (block_pos > (BLOCK_MAX - 2)) {
fatal("codegen_addbyte2 over! %i\n", block_pos);
CPU_BLOCK_END();
}
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
}
static inline void
codegen_addbyte3(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb, uint8_t valc)
{
if (block_pos > (BLOCK_MAX - 3)) {
fatal("codegen_addbyte3 over! %i\n", block_pos);
CPU_BLOCK_END();
}
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
}
static inline void
codegen_addbyte4(UNUSED(codeblock_t *block), uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald)
{
if (block_pos > (BLOCK_MAX - 4)) {
fatal("codegen_addbyte4 over! %i\n", block_pos);
CPU_BLOCK_END();
}
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
block_write_data[block_pos++] = vald;
}
static inline void
codegen_addword(UNUSED(codeblock_t *block), uint16_t val)
{
if (block_pos > (BLOCK_MAX - 2)) {
fatal("codegen_addword over! %i\n", block_pos);
CPU_BLOCK_END();
}
*(uint16_t *) &block_write_data[block_pos] = val;
block_pos += 2;
}
static inline void
codegen_addlong(UNUSED(codeblock_t *block), uint32_t val)
{
if (block_pos > (BLOCK_MAX - 4)) {
fatal("codegen_addlong over! %i\n", block_pos);
CPU_BLOCK_END();
}
*(uint32_t *) &block_write_data[block_pos] = val;
block_pos += 4;
}
static inline void
codegen_addquad(UNUSED(codeblock_t *block), uint64_t val)
{
if (block_pos > (BLOCK_MAX - 8)) {
fatal("codegen_addquad over! %i\n", block_pos);
CPU_BLOCK_END();
}
*(uint64_t *) &block_write_data[block_pos] = val;
block_pos += 8;
}
static inline void
codegen_alloc_bytes(codeblock_t *block, int size)
{
if (block_pos > ((BLOCK_MAX - size) - JMP_LEN_BYTES)) {
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
/*Add a jump instruction to the new block*/
codegen_addbyte(block, 0xe9); /*JMP*/
codegen_addlong(block, (uintptr_t) new_ptr - (uintptr_t) &block_write_data[block_pos + 4]);
/*Set write address to start of new block*/
block_pos = 0;
block_write_data = new_ptr;
}
}
static inline int
is_imm8(uint32_t imm_data)
{
if (imm_data <= 0x7f || imm_data >= 0xffffff80)
return 1;
return 0;
}
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_ops_helpers.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 858 |
```objective-c
void host_x86_ADDPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADDSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
#define CMPPS_EQ 0
#define CMPPS_NLT 5
#define CMPPS_NLE 6
void host_x86_CMPPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg, int type);
void host_x86_COMISD_XREG_XREG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CVTDQ2PS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTPS2DQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSD2SI_REG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSD2SI_REG64_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSD2SS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSI2SD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSI2SD_XREG_REG64(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSI2SS_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSS2SD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CVTSS2SD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_DIVSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_DIVSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_LDMXCSR(codeblock_t *block, void *p);
void host_x86_MAXSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVD_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVD_REG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_ABS_XREG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift, int src_reg);
void host_x86_MOVQ_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVQ_BASE_OFFSET_XREG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOVQ_XREG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOVQ_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVQ_XREG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOVQ_REG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MAXPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MINPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MULPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MULSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MULSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKSSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKSSDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PACKUSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PADDUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PAND_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PANDN_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_POR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PXOR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPEQD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PCMPGTD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMADDWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMULHW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PMULLW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSLLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSLLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSLLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRAQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSRLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_PSUBB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PSUBUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKHBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKHWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKHDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_PUNPCKLDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SQRTSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SQRTSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUBPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUBSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_UNPCKLPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_ops_sse.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,280 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "codegen.h"
#include "codegen_allocator.h"
#include "codegen_backend.h"
#include "codegen_ir.h"
#include "codegen_reg.h"
extern int has_ea;
static ir_data_t ir_block;
static int codegen_unroll_start;
static int codegen_unroll_count;
static int codegen_unroll_first_instruction;
ir_data_t *
codegen_ir_init(void)
{
ir_block.wr_pos = 0;
codegen_unroll_count = 0;
return &ir_block;
}
void
codegen_ir_set_unroll(int count, int start, int first_instruction)
{
codegen_unroll_count = count;
codegen_unroll_start = start;
codegen_unroll_first_instruction = first_instruction;
}
static void
duplicate_uop(ir_data_t *ir, uop_t *uop, int offset)
{
uop_t *new_uop = uop_alloc(ir, uop->type);
if (!ir_reg_is_invalid(uop->src_reg_a))
new_uop->src_reg_a = codegen_reg_read(uop->src_reg_a.reg);
if (!ir_reg_is_invalid(uop->src_reg_b))
new_uop->src_reg_b = codegen_reg_read(uop->src_reg_b.reg);
if (!ir_reg_is_invalid(uop->src_reg_c))
new_uop->src_reg_c = codegen_reg_read(uop->src_reg_c.reg);
if (!ir_reg_is_invalid(uop->dest_reg_a))
new_uop->dest_reg_a = codegen_reg_write(uop->dest_reg_a.reg, ir->wr_pos - 1);
new_uop->type = uop->type;
new_uop->imm_data = uop->imm_data;
new_uop->p = uop->p;
new_uop->pc = uop->pc;
if (uop->jump_dest_uop != -1) {
new_uop->jump_dest_uop = uop->jump_dest_uop + offset;
}
}
void
codegen_ir_compile(ir_data_t *ir, codeblock_t *block)
{
int jump_target_at_end = -1;
int c;
if (codegen_unroll_count) {
int unroll_end;
codegen_set_loop_start(ir, codegen_unroll_first_instruction);
unroll_end = ir->wr_pos;
for (int unroll_count = 1; unroll_count < codegen_unroll_count; unroll_count++) {
int offset = ir->wr_pos - codegen_unroll_start;
// pclog("Unroll from %i to %i, offset %i - iteration %i\n", codegen_unroll_start, ir->wr_pos, offset, unroll_count);
for (c = codegen_unroll_start; c < unroll_end; c++) {
// pclog(" Duplicate uop %i\n", c);
duplicate_uop(ir, &ir->uops[c], offset);
}
}
}
codegen_reg_mark_as_required();
codegen_reg_process_dead_list(ir);
block_write_data = codeblock_allocator_get_ptr(block->head_mem_block);
block_pos = 0;
codegen_backend_prologue(block);
for (c = 0; c < ir->wr_pos; c++) {
uop_t *uop = &ir->uops[c];
// pclog("uOP %i : %08x\n", c, uop->type);
if (uop->type & UOP_TYPE_BARRIER)
codegen_reg_flush_invalidate(ir, block);
if (uop->type & UOP_TYPE_JUMP_DEST) {
uop_t *uop_dest = uop;
while (uop_dest->jump_list_next != -1) {
uop_dest = &ir->uops[uop_dest->jump_list_next];
codegen_set_jump_dest(block, uop_dest->p);
}
}
if ((uop->type & UOP_MASK) == UOP_INVALID)
continue;
#ifdef CODEGEN_BACKEND_HAS_MOV_IMM
if ((uop->type & UOP_MASK) == (UOP_MOV_IMM & UOP_MASK) && reg_is_native_size(uop->dest_reg_a) && !codegen_reg_is_loaded(uop->dest_reg_a) && reg_version[IREG_GET_REG(uop->dest_reg_a.reg)][uop->dest_reg_a.version].refcount <= 0) {
/*Special case for UOP_MOV_IMM - if destination not already in host register
and won't be used again then just store directly to memory*/
codegen_reg_write_imm(block, uop->dest_reg_a, uop->imm_data);
} else
#endif
if ((uop->type & UOP_MASK) == (UOP_MOV & UOP_MASK) && reg_version[IREG_GET_REG(uop->src_reg_a.reg)][uop->src_reg_a.version].refcount <= 1 && reg_is_native_size(uop->src_reg_a) && reg_is_native_size(uop->dest_reg_a)) {
/*Special case for UOP_MOV - if source register won't be used again then
just rename it to dest register instead of moving*/
codegen_reg_alloc_register(invalid_ir_reg, uop->src_reg_a, invalid_ir_reg, invalid_ir_reg);
uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
codegen_reg_rename(block, uop->src_reg_a, uop->dest_reg_a);
if (uop->type & UOP_TYPE_ORDER_BARRIER)
codegen_reg_flush(ir, block);
} else {
if (uop->type & UOP_TYPE_PARAMS_REGS) {
codegen_reg_alloc_register(uop->dest_reg_a, uop->src_reg_a, uop->src_reg_b, uop->src_reg_c);
if (uop->src_reg_a.reg != IREG_INVALID) {
uop->src_reg_a_real = codegen_reg_alloc_read_reg(block, uop->src_reg_a, NULL);
}
if (uop->src_reg_b.reg != IREG_INVALID) {
uop->src_reg_b_real = codegen_reg_alloc_read_reg(block, uop->src_reg_b, NULL);
}
if (uop->src_reg_c.reg != IREG_INVALID) {
uop->src_reg_c_real = codegen_reg_alloc_read_reg(block, uop->src_reg_c, NULL);
}
}
if (uop->type & UOP_TYPE_ORDER_BARRIER)
codegen_reg_flush(ir, block);
if (uop->type & UOP_TYPE_PARAMS_REGS) {
if (uop->dest_reg_a.reg != IREG_INVALID) {
uop->dest_reg_a_real = codegen_reg_alloc_write_reg(block, uop->dest_reg_a);
}
}
#ifndef RELEASE_BUILD
if (!uop_handlers[uop->type & UOP_MASK])
fatal("!uop_handlers[uop->type & UOP_MASK] %08x\n", uop->type);
#endif
uop_handlers[uop->type & UOP_MASK](block, uop);
}
if (uop->type & UOP_TYPE_JUMP) {
if (uop->jump_dest_uop == ir->wr_pos) {
if (jump_target_at_end == -1)
jump_target_at_end = c;
else {
uop_t *uop_dest = &ir->uops[jump_target_at_end];
while (uop_dest->jump_list_next != -1)
uop_dest = &ir->uops[uop_dest->jump_list_next];
uop_dest->jump_list_next = c;
}
} else {
uop_t *uop_dest = &ir->uops[uop->jump_dest_uop];
while (uop_dest->jump_list_next != -1)
uop_dest = &ir->uops[uop_dest->jump_list_next];
uop_dest->jump_list_next = c;
ir->uops[uop->jump_dest_uop].type |= UOP_TYPE_JUMP_DEST;
}
}
}
codegen_reg_flush_invalidate(ir, block);
if (jump_target_at_end != -1) {
uop_t *uop_dest = &ir->uops[jump_target_at_end];
while (1) {
codegen_set_jump_dest(block, uop_dest->p);
if (uop_dest->jump_list_next == -1)
break;
uop_dest = &ir->uops[uop_dest->jump_list_next];
}
}
codegen_backend_epilogue(block);
block_write_data = NULL;
#if 0
if (has_ea)
fatal("IR compilation complete\n");
#endif
}
``` | /content/code_sandbox/src/codegen_new/codegen_ir.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,939 |
```objective-c
#include "codegen_backend_x86_defs.h"
#define BLOCK_SIZE 0x10000
#define BLOCK_MASK 0xffff
#define BLOCK_START 0
#define HASH_SIZE 0x20000
#define HASH_MASK 0x1ffff
#define HASH(l) ((l) &0x1ffff)
#define BLOCK_MAX 0x3c0
#define CODEGEN_BACKEND_HAS_MOV_IMM
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 87 |
```objective-c
uint32_t ropPADDB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDSB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDUSB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPADDUSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBSB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBUSB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSUBUSW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPMADDWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPMULHW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPMULLW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_arith.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 732 |
```c
#include <inttypes.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86_ops.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "x87_sf.h"
#include "x87.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_allocator.h"
#include "codegen_backend.h"
#include "codegen_ir.h"
#include "codegen_reg.h"
uint8_t *block_write_data = NULL;
int codegen_flat_ds;
int codegen_flat_ss;
int mmx_ebx_ecx_loaded;
int codegen_flags_changed = 0;
int codegen_fpu_entered = 0;
int codegen_mmx_entered = 0;
int codegen_fpu_loaded_iq[8];
x86seg *op_ea_seg;
int op_ssegs;
uint32_t op_old_pc;
uint32_t recomp_page = -1;
int block_current = 0;
static int block_num;
int block_pos;
uint32_t codegen_endpc;
int codegen_block_cycles;
static int codegen_block_ins;
static int codegen_block_full_ins;
static uint32_t last_op32;
static x86seg *last_ea_seg;
static int last_ssegs;
#ifdef DEBUG_EXTRA
uint32_t instr_counts[256 * 256];
#endif
static uint16_t block_free_list;
static void delete_block(codeblock_t *block);
static void delete_dirty_block(codeblock_t *block);
/*Temporary list of code blocks that have recently been evicted. This allows for
some historical state to be kept when a block is the target of self-modifying
code.
The size of this list is limited to DIRTY_LIST_MAX_SIZE blocks. When this is
exceeded the oldest entry will be moved to the free list.*/
static uint16_t block_dirty_list_head;
static uint16_t block_dirty_list_tail;
static int dirty_list_size = 0;
#define DIRTY_LIST_MAX_SIZE 64
static void
block_free_list_add(codeblock_t *block)
{
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("block_free_list_add: block=%p in dirty list\n", block);
#endif
if (block_free_list)
block->next = block_free_list;
else
block->next = 0;
block_free_list = get_block_nr(block);
block->flags = CODEBLOCK_IN_FREE_LIST;
}
static void
block_dirty_list_add(codeblock_t *block)
{
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("block_dirty_list_add: block=%p already in dirty list\n", block);
#endif
if (block_dirty_list_head != BLOCK_INVALID) {
codeblock_t *old_head = &codeblock[block_dirty_list_head];
block->next = block_dirty_list_head;
block->prev = BLOCK_INVALID;
block_dirty_list_head = old_head->prev = get_block_nr(block);
} else {
/*List empty*/
block->prev = block->next = BLOCK_INVALID;
block_dirty_list_head = block_dirty_list_tail = get_block_nr(block);
}
block->flags |= CODEBLOCK_IN_DIRTY_LIST;
dirty_list_size++;
if (dirty_list_size > DIRTY_LIST_MAX_SIZE) {
/*Evict oldest block to the free list*/
codeblock_t *evict_block = &codeblock[block_dirty_list_tail];
#ifndef RELEASE_BUILD
if (!(evict_block->flags & CODEBLOCK_IN_DIRTY_LIST))
fatal("block_dirty_list_add: evict_block=%p %x %x not in dirty list\n", evict_block, evict_block->phys, evict_block->flags);
if (!block_dirty_list_tail)
fatal("block_dirty_list_add - !block_dirty_list_tail\n");
if (evict_block->prev == BLOCK_INVALID)
fatal("block_dirty_list_add - evict_block->prev == BLOCK_INVALID\n");
#endif
block_dirty_list_tail = evict_block->prev;
codeblock[evict_block->prev].next = BLOCK_INVALID;
dirty_list_size--;
evict_block->flags &= ~CODEBLOCK_IN_DIRTY_LIST;
delete_dirty_block(evict_block);
}
}
static void
block_dirty_list_remove(codeblock_t *block)
{
codeblock_t *prev_block = &codeblock[block->prev];
codeblock_t *next_block = &codeblock[block->next];
#ifndef RELEASE_BUILD
if (!(block->flags & CODEBLOCK_IN_DIRTY_LIST))
fatal("block_dirty_list_remove: block=%p not in dirty list\n", block);
#endif
/*Is block head of list*/
if (block->prev == BLOCK_INVALID)
block_dirty_list_head = block->next;
else
prev_block->next = block->next;
/*Is block tail of list?*/
if (block->next == BLOCK_INVALID)
block_dirty_list_tail = block->prev;
else
next_block->prev = block->prev;
dirty_list_size--;
#ifndef RELEASE_BUILD
if (dirty_list_size < 0)
fatal("remove - dirty_list_size < 0!\n");
#endif
block->flags &= ~CODEBLOCK_IN_DIRTY_LIST;
}
int
codegen_purge_purgable_list(void)
{
if (purgable_page_list_head) {
page_t *page = &pages[purgable_page_list_head];
if (page->code_present_mask & page->dirty_mask) {
codegen_check_flush(page, page->dirty_mask, purgable_page_list_head << 12);
if (block_free_list)
return 1;
}
}
return 0;
}
static codeblock_t *
block_free_list_get(void)
{
codeblock_t *block = NULL;
while (!block_free_list) {
/*Free list is empty, check the dirty list*/
if (block_dirty_list_tail) {
#ifndef RELEASE_BUILD
if (dirty_list_size <= 0)
fatal("get - dirty_list_size <= 0!\n");
#endif
/*Reuse oldest block*/
block = &codeblock[block_dirty_list_tail];
block_dirty_list_tail = block->prev;
if (block->prev == BLOCK_INVALID)
block_dirty_list_head = BLOCK_INVALID;
else
codeblock[block->prev].next = BLOCK_INVALID;
dirty_list_size--;
block->flags &= ~CODEBLOCK_IN_DIRTY_LIST;
delete_dirty_block(block);
block_free_list = get_block_nr(block);
break;
}
/*Free list is empty - free up a block*/
if (!codegen_purge_purgable_list())
codegen_delete_random_block(0);
}
block = &codeblock[block_free_list];
block_free_list = block->next;
block->flags &= ~CODEBLOCK_IN_FREE_LIST;
block->next = 0;
return block;
}
void
codegen_init(void)
{
codegen_allocator_init();
codegen_backend_init();
block_free_list = 0;
for (uint32_t c = 0; c < BLOCK_SIZE; c++)
block_free_list_add(&codeblock[c]);
block_dirty_list_head = block_dirty_list_tail = 0;
dirty_list_size = 0;
#ifdef DEBUG_EXTRA
memset(instr_counts, 0, sizeof(instr_counts));
#endif
}
void
codegen_reset(void)
{
int c;
for (c = 1; c < BLOCK_SIZE; c++) {
codeblock_t *block = &codeblock[c];
if (block->pc != BLOCK_PC_INVALID) {
block->phys = 0;
block->phys_2 = 0;
delete_block(block);
}
}
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(uint16_t));
mem_reset_page_blocks();
block_free_list = 0;
for (c = 0; c < BLOCK_SIZE; c++) {
codeblock[c].pc = BLOCK_PC_INVALID;
block_free_list_add(&codeblock[c]);
}
}
void
dump_block(void)
{
#if 0
codeblock_t *block = pages[0x119000 >> 12].block;
pclog("dump_block:\n");
while (block) {
uint32_t start_pc = (block->pc & 0xffc) | (block->phys & ~0xfff);
uint32_t end_pc = (block->endpc & 0xffc) | (block->phys & ~0xfff);
pclog(" %p : %08x-%08x %08x-%08x %p %p\n", (void *)block, start_pc, end_pc, block->pc, block->endpc, (void *)block->prev, (void *)block->next);
if (!block->pc)
fatal("Dead PC=0\n");
block = block->next;
}
pclog("dump_block done\n");*/
#endif
}
static void
add_to_block_list(codeblock_t *block)
{
uint16_t block_prev_nr = pages[block->phys >> 12].block;
uint16_t block_nr = get_block_nr(block);
#ifndef RELEASE_BUILD
if (!block->page_mask)
fatal("add_to_block_list - mask = 0 %" PRIx64 " %" PRIx64 "\n", block->page_mask, block->page_mask2);
#endif
if (block_prev_nr) {
block->next = block_prev_nr;
codeblock[block_prev_nr].prev = block_nr;
pages[block->phys >> 12].block = block_nr;
} else {
block->next = BLOCK_INVALID;
pages[block->phys >> 12].block = block_nr;
}
if (block->next) {
#ifndef RELEASE_BUILD
if (codeblock[block->next].pc == BLOCK_PC_INVALID)
fatal("block->next->pc=BLOCK_PC_INVALID %p %p %x %x\n", (void *) &codeblock[block->next], (void *) codeblock, block_current, block_pos);
#endif
}
if (block->page_mask2) {
block->flags |= CODEBLOCK_HAS_PAGE2;
block_prev_nr = pages[block->phys_2 >> 12].block_2;
if (block_prev_nr) {
block->next_2 = block_prev_nr;
codeblock[block_prev_nr].prev_2 = block_nr;
pages[block->phys_2 >> 12].block_2 = block_nr;
} else {
block->next_2 = BLOCK_INVALID;
pages[block->phys_2 >> 12].block_2 = block_nr;
}
}
}
static void
remove_from_block_list(codeblock_t *block, UNUSED(uint32_t pc))
{
if (!block->page_mask)
return;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("remove_from_block_list: in dirty list\n");
#endif
if (block->prev) {
codeblock[block->prev].next = block->next;
if (block->next)
codeblock[block->next].prev = block->prev;
} else {
pages[block->phys >> 12].block = block->next;
if (block->next)
codeblock[block->next].prev = BLOCK_INVALID;
else
mem_flush_write_page(block->phys, 0);
}
if (!(block->flags & CODEBLOCK_HAS_PAGE2)) {
#ifndef RELEASE_BUILD
if (block->prev_2 || block->next_2)
fatal("Invalid block_2 %x %p %08x\n", block->flags, block, block->phys);
#endif
return;
}
block->flags &= ~CODEBLOCK_HAS_PAGE2;
if (block->prev_2) {
codeblock[block->prev_2].next_2 = block->next_2;
if (block->next_2)
codeblock[block->next_2].prev_2 = block->prev_2;
} else {
pages[block->phys_2 >> 12].block_2 = block->next_2;
if (block->next_2)
codeblock[block->next_2].prev_2 = BLOCK_INVALID;
else
mem_flush_write_page(block->phys_2, 0);
}
}
static void
invalidate_block(codeblock_t *block)
{
uint32_t old_pc = block->pc;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
fatal("invalidate_block: already in dirty list\n");
if (block->pc == BLOCK_PC_INVALID)
fatal("Invalidating deleted block\n");
#endif
remove_from_block_list(block, old_pc);
block_dirty_list_add(block);
if (block->head_mem_block)
codegen_allocator_free(block->head_mem_block);
block->head_mem_block = NULL;
}
static void
delete_block(codeblock_t *block)
{
uint32_t old_pc = block->pc;
if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
#ifndef RELEASE_BUILD
if (block->pc == BLOCK_PC_INVALID)
fatal("Deleting deleted block\n");
#endif
block->pc = BLOCK_PC_INVALID;
codeblock_tree_delete(block);
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
block_dirty_list_remove(block);
else
remove_from_block_list(block, old_pc);
if (block->head_mem_block)
codegen_allocator_free(block->head_mem_block);
block->head_mem_block = NULL;
block_free_list_add(block);
}
static void
delete_dirty_block(codeblock_t *block)
{
if (block == &codeblock[codeblock_hash[HASH(block->phys)]])
codeblock_hash[HASH(block->phys)] = BLOCK_INVALID;
#ifndef RELEASE_BUILD
if (block->pc == BLOCK_PC_INVALID)
fatal("Deleting deleted block\n");
#endif
block->pc = BLOCK_PC_INVALID;
codeblock_tree_delete(block);
block_free_list_add(block);
}
void
codegen_delete_block(codeblock_t *block)
{
if (block->pc != BLOCK_PC_INVALID)
delete_block(block);
}
void
codegen_delete_random_block(int required_mem_block)
{
int block_nr = rand() & BLOCK_MASK;
while (1) {
if (block_nr && block_nr != block_current) {
codeblock_t *block = &codeblock[block_nr];
if (block->pc != BLOCK_PC_INVALID && (!required_mem_block || block->head_mem_block)) {
delete_block(block);
return;
}
}
block_nr = (block_nr + 1) & BLOCK_MASK;
}
}
void
codegen_check_flush(page_t *page, UNUSED(uint64_t mask), UNUSED(uint32_t phys_addr))
{
uint16_t block_nr = page->block;
int remove_from_evict_list = 0;
while (block_nr) {
codeblock_t *block = &codeblock[block_nr];
uint16_t next_block = block->next;
if (*block->dirty_mask & block->page_mask) {
invalidate_block(block);
}
#ifndef RELEASE_BUILD
if (block_nr == next_block)
fatal("Broken 1\n");
#endif
block_nr = next_block;
}
block_nr = page->block_2;
while (block_nr) {
codeblock_t *block = &codeblock[block_nr];
uint16_t next_block = block->next_2;
if (*block->dirty_mask2 & block->page_mask2) {
invalidate_block(block);
}
#ifndef RELEASE_BUILD
if (block_nr == next_block)
fatal("Broken 2\n");
#endif
block_nr = next_block;
}
if (page->code_present_mask & page->dirty_mask)
remove_from_evict_list = 1;
page->code_present_mask &= ~page->dirty_mask;
page->dirty_mask = 0;
for (uint8_t c = 0; c < 64; c++) {
if (page->byte_code_present_mask[c] & page->byte_dirty_mask[c])
remove_from_evict_list = 0;
page->byte_code_present_mask[c] &= ~page->byte_dirty_mask[c];
page->byte_dirty_mask[c] = 0;
}
if (remove_from_evict_list)
page_remove_from_evict_list(page);
}
void
codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
page_t *page = &pages[phys_addr >> 12];
if (!page->block)
mem_flush_write_page(phys_addr, cs + cpu_state.pc);
block = block_free_list_get();
#ifndef RELEASE_BUILD
if (!block)
fatal("codegen_block_init: block_free_list_get() returned NULL\n");
#endif
block_current = get_block_nr(block);
block_num = HASH(phys_addr);
codeblock_hash[block_num] = block_current;
block->ins = 0;
block->pc = cs + cpu_state.pc;
block->_cs = cs;
block->phys = phys_addr;
block->dirty_mask = &page->dirty_mask;
block->dirty_mask2 = NULL;
block->next = block->prev = BLOCK_INVALID;
block->next_2 = block->prev_2 = BLOCK_INVALID;
block->page_mask = block->page_mask2 = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
recomp_page = block->phys & ~0xfff;
codeblock_tree_add(block);
}
static ir_data_t *ir_data;
ir_data_t *
codegen_get_ir_data(void)
{
return ir_data;
}
void
codegen_block_start_recompile(codeblock_t *block)
{
page_t *page = &pages[block->phys >> 12];
if (!page->block)
mem_flush_write_page(block->phys, cs + cpu_state.pc);
block_num = HASH(block->phys);
block_current = get_block_nr(block); // block->pnt;
#ifndef RELEASE_BUILD
if (block->pc != cs + cpu_state.pc || (block->flags & CODEBLOCK_WAS_RECOMPILED))
fatal("Recompile to used block!\n");
#endif
block->head_mem_block = codegen_allocator_allocate(NULL, block_current);
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
block->status = cpu_cur_status;
block->page_mask = block->page_mask2 = 0;
block->ins = 0;
cpu_block_end = 0;
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
codegen_block_cycles = 0;
codegen_timing_block_start();
codegen_block_ins = 0;
codegen_block_full_ins = 0;
recomp_page = block->phys & ~0xfff;
codegen_flags_changed = 0;
codegen_fpu_entered = 0;
codegen_mmx_entered = 0;
codegen_fpu_loaded_iq[0] = codegen_fpu_loaded_iq[1] = codegen_fpu_loaded_iq[2] = codegen_fpu_loaded_iq[3] = codegen_fpu_loaded_iq[4] = codegen_fpu_loaded_iq[5] = codegen_fpu_loaded_iq[6] = codegen_fpu_loaded_iq[7] = 0;
cpu_state.seg_ds.checked = cpu_state.seg_es.checked = cpu_state.seg_fs.checked = cpu_state.seg_gs.checked = (cr0 & 1) ? 0 : 1;
block->TOP = cpu_state.TOP & 7;
block->flags |= CODEBLOCK_WAS_RECOMPILED;
codegen_flat_ds = !(cpu_cur_status & CPU_STATUS_NOTFLATDS);
codegen_flat_ss = !(cpu_cur_status & CPU_STATUS_NOTFLATSS);
if (block->flags & CODEBLOCK_BYTE_MASK) {
block->dirty_mask = &page->byte_dirty_mask[(block->phys >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK];
block->dirty_mask2 = NULL;
}
ir_data = codegen_ir_init();
ir_data->block = block;
codegen_reg_reset();
codegen_accumulate_reset();
codegen_generate_reset();
}
void
codegen_block_remove(void)
{
codeblock_t *block = &codeblock[block_current];
delete_block(block);
recomp_page = -1;
}
void
codegen_block_generate_end_mask_recompile(void)
{
codeblock_t *block = &codeblock[block_current];
page_t *p;
p = &pages[block->phys >> 12];
if (block->flags & CODEBLOCK_BYTE_MASK) {
int offset = (block->phys >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
p->byte_code_present_mask[offset] |= block->page_mask;
} else
p->code_present_mask |= block->page_mask;
if ((*(block->dirty_mask) & block->page_mask) && !page_in_evict_list(p))
page_add_to_evict_list(p);
block->phys_2 = -1;
block->next_2 = block->prev_2 = BLOCK_INVALID;
if (block->page_mask2) {
block->phys_2 = get_phys_noabrt(codegen_endpc);
if (block->phys_2 != -1) {
page_t *page_2 = &pages[block->phys_2 >> 12];
if (block->flags & CODEBLOCK_BYTE_MASK) {
int offset = (block->phys_2 >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
page_2->byte_code_present_mask[offset] |= block->page_mask2;
block->dirty_mask2 = &page_2->byte_dirty_mask[offset];
} else {
page_2->code_present_mask |= block->page_mask2;
block->dirty_mask2 = &page_2->dirty_mask;
}
if (((*block->dirty_mask2) & block->page_mask2) && !page_in_evict_list(page_2))
page_add_to_evict_list(page_2);
if (!pages[block->phys_2 >> 12].block_2)
mem_flush_write_page(block->phys_2, codegen_endpc);
#ifndef RELEASE_BUILD
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2) {
if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *) &codeblock[block->next_2]);
}
#endif
} else {
/*Second page not present. page_mask2 is most likely set only because
the recompiler didn't know how long the last instruction was, so
clear it*/
block->page_mask2 = 0;
}
}
recomp_page = -1;
}
void
codegen_block_generate_end_mask_mark(void)
{
codeblock_t *block = &codeblock[block_current];
uint32_t start_pc;
uint32_t end_pc;
page_t *p;
#ifndef RELEASE_BUILD
if (block->flags & CODEBLOCK_BYTE_MASK)
fatal("codegen_block_generate_end_mask2() - BYTE_MASK\n");
#endif
block->page_mask = 0;
start_pc = (block->pc & 0xfff) & ~63;
if ((block->pc ^ codegen_endpc) & ~0xfff)
end_pc = 0xfff & ~63;
else
end_pc = (codegen_endpc & 0xfff) & ~63;
if (end_pc < start_pc)
end_pc = 0xfff;
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++) {
block->page_mask |= ((uint64_t) 1 << start_pc);
}
p = &pages[block->phys >> 12];
p->code_present_mask |= block->page_mask;
if ((p->dirty_mask & block->page_mask) && !page_in_evict_list(p))
page_add_to_evict_list(p);
block->phys_2 = -1;
block->page_mask2 = 0;
block->next_2 = block->prev_2 = BLOCK_INVALID;
if ((block->pc ^ codegen_endpc) & ~0xfff) {
block->phys_2 = get_phys_noabrt(codegen_endpc);
if (block->phys_2 != -1) {
page_t *page_2 = &pages[block->phys_2 >> 12];
start_pc = 0;
end_pc = (codegen_endpc & 0xfff) >> PAGE_MASK_SHIFT;
for (; start_pc <= end_pc; start_pc++)
block->page_mask2 |= ((uint64_t) 1 << start_pc);
page_2->code_present_mask |= block->page_mask2;
if ((page_2->dirty_mask & block->page_mask2) && !page_in_evict_list(page_2))
page_add_to_evict_list(page_2);
if (!pages[block->phys_2 >> 12].block_2)
mem_flush_write_page(block->phys_2, codegen_endpc);
#ifndef RELEASE_BUILD
if (!block->page_mask2)
fatal("!page_mask2\n");
if (block->next_2) {
if (codeblock[block->next_2].pc == BLOCK_PC_INVALID)
fatal("block->next_2->pc=BLOCK_PC_INVALID %p\n", (void *) &codeblock[block->next_2]);
}
#endif
block->dirty_mask2 = &page_2->dirty_mask;
} else {
/*Second page not present. page_mask2 is most likely set only because
the recompiler didn't know how long the last instruction was, so
clear it*/
block->page_mask2 = 0;
}
}
recomp_page = -1;
}
void
codegen_block_end(void)
{
codeblock_t *block = &codeblock[block_current];
codegen_block_generate_end_mask_mark();
add_to_block_list(block);
}
void
codegen_block_end_recompile(codeblock_t *block)
{
codegen_timing_block_end();
codegen_accumulate(ir_data, ACCREG_cycles, -codegen_block_cycles);
if (block->flags & CODEBLOCK_IN_DIRTY_LIST)
block_dirty_list_remove(block);
else
remove_from_block_list(block, block->pc);
block->next = block->prev = BLOCK_INVALID;
block->next_2 = block->prev_2 = BLOCK_INVALID;
codegen_block_generate_end_mask_recompile();
add_to_block_list(block);
if (!(block->flags & CODEBLOCK_HAS_FPU))
block->flags &= ~CODEBLOCK_STATIC_TOP;
codegen_accumulate_flush(ir_data);
codegen_ir_compile(ir_data, block);
}
void
codegen_flush(void)
{
return;
}
void
codegen_mark_code_present_multibyte(codeblock_t *block, uint32_t start_pc, int len)
{
if (len) {
uint32_t end_pc = start_pc + (len - 1);
if (block->flags & CODEBLOCK_BYTE_MASK) {
uint32_t start_pc_masked = start_pc & PAGE_MASK_MASK;
uint32_t end_pc_masked = end_pc & PAGE_MASK_MASK;
if ((start_pc ^ block->pc) & ~0x3f) /*Starts in second page*/
{
for (; start_pc_masked <= end_pc_masked; start_pc_masked++)
block->page_mask2 |= ((uint64_t) 1 << start_pc_masked);
} else if (((start_pc + (len - 1)) ^ block->pc) & ~0x3f) /*Crosses both pages*/
{
for (; start_pc_masked <= 63; start_pc_masked++)
block->page_mask |= ((uint64_t) 1 << start_pc_masked);
for (start_pc_masked = 0; start_pc_masked <= end_pc_masked; start_pc_masked++)
block->page_mask2 |= ((uint64_t) 1 << start_pc_masked);
} else /*First page only*/
{
for (; start_pc_masked <= end_pc_masked; start_pc_masked++)
block->page_mask |= ((uint64_t) 1 << start_pc_masked);
}
} else {
uint32_t start_pc_shifted = start_pc >> PAGE_MASK_SHIFT;
uint32_t end_pc_shifted = end_pc >> PAGE_MASK_SHIFT;
start_pc_shifted &= PAGE_MASK_MASK;
end_pc_shifted &= PAGE_MASK_MASK;
if ((start_pc ^ block->pc) & ~0xfff) /*Starts in second page*/
{
for (; start_pc_shifted <= end_pc_shifted; start_pc_shifted++)
block->page_mask2 |= ((uint64_t) 1 << start_pc_shifted);
} else if (((start_pc + (len - 1)) ^ block->pc) & ~0xfff) /*Crosses both pages*/
{
for (; start_pc_shifted <= 63; start_pc_shifted++)
block->page_mask |= ((uint64_t) 1 << start_pc_shifted);
for (start_pc_shifted = 0; start_pc_shifted <= end_pc_shifted; start_pc_shifted++)
block->page_mask2 |= ((uint64_t) 1 << start_pc_shifted);
} else /*First page only*/
{
for (; start_pc_shifted <= end_pc_shifted; start_pc_shifted++)
block->page_mask |= ((uint64_t) 1 << start_pc_shifted);
}
}
}
}
``` | /content/code_sandbox/src/codegen_new/codegen_block.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,621 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_mmx_loadstore.h"
#include "codegen_ops_helpers.h"
uint32_t
ropMOVD_r_d(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_MM(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_MM(dest_reg), IREG_temp0);
}
return op_pc + 1;
}
uint32_t
ropMOVD_d_r(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
if (cpu_iscyrix && in_smm)
return 0;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 3);
uop_MOVZX(ir, IREG_temp0, IREG_MM(src_reg));
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_temp0);
}
return op_pc + 1;
}
uint32_t
ropMOVQ_r_q(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_MM(dest_reg), ireg_seg_base(target_seg), IREG_eaaddr);
}
return op_pc + 1;
}
uint32_t
ropMOVQ_q_r(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 7);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_MM(src_reg));
}
return op_pc + 1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_loadstore.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,206 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_3dnow.h"
#include "codegen_ops_helpers.h"
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
codegen_mark_code_present(block, cs + op_pc + 1, 1); \
return op_pc + 2; \
}
// clang-format off
ropParith(PFADD)
ropParith(PFCMPEQ)
ropParith(PFCMPGE)
ropParith(PFCMPGT)
ropParith(PFMAX)
ropParith(PFMIN)
ropParith(PFMUL)
ropParith(PFSUB)
// clang-format on
uint32_t ropPF2ID(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_PF2ID(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_PF2ID(ir, IREG_MM(dest_reg), IREG_temp0_Q);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPFSUBR(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_PFSUB(ir, IREG_MM(dest_reg), IREG_MM(src_reg), IREG_MM(dest_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_PFSUB(ir, IREG_MM(dest_reg), IREG_temp0_Q, IREG_MM(dest_reg));
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPI2FD(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_PI2FD(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_PI2FD(ir, IREG_MM(dest_reg), IREG_temp0_Q);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPFRCPIT(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_MM(dest_reg), ireg_seg_base(target_seg), IREG_eaaddr);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPFRCP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_PFRCP(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_PFRCP(ir, IREG_MM(dest_reg), IREG_temp0_Q);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPFRSQRT(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_PFRSQRT(ir, IREG_MM(dest_reg), IREG_MM(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr);
uop_PFRSQRT(ir, IREG_MM(dest_reg), IREG_temp0_Q);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPFRSQIT1(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_3dnow.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,353 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_mov.h"
uint32_t
ropMOV_rb_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint8_t imm = fastreadb(cs + op_pc);
uop_MOV_IMM(ir, IREG_8(opcode & 7), imm);
codegen_mark_code_present(block, cs + op_pc, 1);
return op_pc + 1;
}
uint32_t
ropMOV_rw_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t imm = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_16(opcode & 7), imm);
codegen_mark_code_present(block, cs + op_pc, 2);
return op_pc + 2;
}
uint32_t
ropMOV_rl_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_32(opcode & 7), cs + op_pc);
} else {
fetchdat = fastreadl(cs + op_pc);
uop_MOV_IMM(ir, IREG_32(opcode & 7), fetchdat);
codegen_mark_code_present(block, cs + op_pc, 4);
}
return op_pc + 4;
}
uint32_t
ropMOV_b_r(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 0);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_8(src_reg));
}
return op_pc + 1;
}
uint32_t
ropMOV_w_r(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_16(src_reg));
}
return op_pc + 1;
}
uint32_t
ropMOV_l_r(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 3);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_32(src_reg));
}
return op_pc + 1;
}
uint32_t
ropMOV_r_b(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_8(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_8(dest_reg), ireg_seg_base(target_seg), IREG_eaaddr);
}
return op_pc + 1;
}
uint32_t
ropMOV_r_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_16(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_16(dest_reg), ireg_seg_base(target_seg), IREG_eaaddr);
}
return op_pc + 1;
}
uint32_t
ropMOV_r_l(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOV(ir, IREG_32(dest_reg), IREG_32(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_32(dest_reg), ireg_seg_base(target_seg), IREG_eaaddr);
}
return op_pc + 1;
}
uint32_t
ropMOV_AL_abs(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_read(block, ir, op_ea_seg);
uop_MEM_LOAD_ABS(ir, IREG_AL, ireg_seg_base(op_ea_seg), addr);
codegen_mark_code_present(block, cs + op_pc, (op_32 & 0x200) ? 4 : 2);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_AX_abs(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_read(block, ir, op_ea_seg);
uop_MEM_LOAD_ABS(ir, IREG_AX, ireg_seg_base(op_ea_seg), addr);
codegen_mark_code_present(block, cs + op_pc, (op_32 & 0x200) ? 4 : 2);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_EAX_abs(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr = 0;
if (op_32 & 0x200) {
if (block->flags & CODEBLOCK_NO_IMMEDIATES) {
LOAD_IMMEDIATE_FROM_RAM_32(block, ir, IREG_eaaddr, cs + op_pc);
} else {
addr = fastreadl(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 4);
}
} else {
addr = fastreadw(cs + op_pc);
codegen_mark_code_present(block, cs + op_pc, 2);
}
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_read(block, ir, op_ea_seg);
if ((block->flags & CODEBLOCK_NO_IMMEDIATES) && (op_32 & 0x200))
uop_MEM_LOAD_REG(ir, IREG_EAX, ireg_seg_base(op_ea_seg), IREG_eaaddr);
else
uop_MEM_LOAD_ABS(ir, IREG_EAX, ireg_seg_base(op_ea_seg), addr);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_abs_AL(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_write(block, ir, op_ea_seg);
uop_MEM_STORE_ABS(ir, ireg_seg_base(op_ea_seg), addr, IREG_AL);
codegen_mark_code_present(block, cs + op_pc, (op_32 & 0x200) ? 4 : 2);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_abs_AX(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_write(block, ir, op_ea_seg);
uop_MEM_STORE_ABS(ir, ireg_seg_base(op_ea_seg), addr, IREG_AX);
codegen_mark_code_present(block, cs + op_pc, (op_32 & 0x200) ? 4 : 2);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_abs_EAX(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t addr;
if (op_32 & 0x200)
addr = fastreadl(cs + op_pc);
else
addr = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
codegen_check_seg_write(block, ir, op_ea_seg);
uop_MEM_STORE_ABS(ir, ireg_seg_base(op_ea_seg), addr, IREG_EAX);
codegen_mark_code_present(block, cs + op_pc, (op_32 & 0x200) ? 4 : 2);
return op_pc + ((op_32 & 0x200) ? 4 : 2);
}
uint32_t
ropMOV_b_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg;
uint8_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
imm = fastreadb(cs + op_pc + 1);
uop_MOV_IMM(ir, IREG_8(dest_reg), imm);
} else {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadb(cs + op_pc + 1);
uop_MEM_STORE_IMM_8(ir, ireg_seg_base(target_seg), IREG_eaaddr, imm);
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropMOV_w_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg;
uint16_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
imm = fastreadw(cs + op_pc + 1);
uop_MOV_IMM(ir, IREG_16(dest_reg), imm);
} else {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadw(cs + op_pc + 1);
uop_MEM_STORE_IMM_16(ir, ireg_seg_base(target_seg), IREG_eaaddr, imm);
}
codegen_mark_code_present(block, cs + op_pc + 1, 2);
return op_pc + 3;
}
uint32_t
ropMOV_l_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg;
uint32_t imm;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
imm = fastreadl(cs + op_pc + 1);
uop_MOV_IMM(ir, IREG_32(dest_reg), imm);
} else {
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
imm = fastreadl(cs + op_pc + 1);
uop_MEM_STORE_IMM_32(ir, ireg_seg_base(target_seg), IREG_eaaddr, imm);
}
codegen_mark_code_present(block, cs + op_pc + 1, 4);
return op_pc + 5;
}
uint32_t
ropMOV_w_seg(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
codegen_mark_code_present(block, cs + op_pc, 1);
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
src_reg = IREG_ES_seg_W;
break;
case 0x08: /*CS*/
src_reg = IREG_CS_seg_W;
break;
case 0x18: /*DS*/
src_reg = IREG_DS_seg_W;
break;
case 0x10: /*SS*/
src_reg = IREG_SS_seg_W;
break;
case 0x20: /*FS*/
src_reg = IREG_FS_seg_W;
break;
case 0x28: /*GS*/
src_reg = IREG_GS_seg_W;
break;
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOV(ir, IREG_16(dest_reg), src_reg);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
CHECK_SEG_LIMITS(block, ir, target_seg, IREG_eaaddr, 1);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, src_reg);
}
return op_pc + 1;
}
uint32_t
ropMOV_l_seg(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
codegen_mark_code_present(block, cs + op_pc, 1);
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
src_reg = IREG_ES_seg_W;
break;
case 0x08: /*CS*/
src_reg = IREG_CS_seg_W;
break;
case 0x18: /*DS*/
src_reg = IREG_DS_seg_W;
break;
case 0x10: /*SS*/
src_reg = IREG_SS_seg_W;
break;
case 0x20: /*FS*/
src_reg = IREG_FS_seg_W;
break;
case 0x28: /*GS*/
src_reg = IREG_GS_seg_W;
break;
default:
return 0;
}
if ((fetchdat & 0xc0) == 0xc0) {
int dest_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), src_reg);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, src_reg);
}
return op_pc + 1;
}
uint32_t
ropMOV_seg_w(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int src_reg;
x86seg *rseg;
codegen_mark_code_present(block, cs + op_pc, 1);
switch (fetchdat & 0x38) {
case 0x00: /*ES*/
rseg = &cpu_state.seg_es;
break;
case 0x18: /*DS*/
rseg = &cpu_state.seg_ds;
break;
case 0x20: /*FS*/
rseg = &cpu_state.seg_fs;
break;
case 0x28: /*GS*/
rseg = &cpu_state.seg_gs;
break;
default:
return 0;
}
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if ((fetchdat & 0xc0) == 0xc0) {
uop_MOV(ir, IREG_temp0_W, IREG_16(fetchdat & 7));
src_reg = IREG_temp0_W;
} else {
x86seg *target_seg;
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
src_reg = IREG_temp0_W;
}
uop_LOAD_SEG(ir, rseg, src_reg);
return op_pc + 1;
}
uint32_t
ropMOVSX_16_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVSX(ir, IREG_16(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVSX(ir, IREG_16(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t
ropMOVSX_32_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVSX(ir, IREG_32(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVSX(ir, IREG_32(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t
ropMOVSX_32_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVSX(ir, IREG_32(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVSX(ir, IREG_32(dest_reg), IREG_temp0_W);
}
return op_pc + 1;
}
uint32_t
ropMOVZX_16_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_16(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_16(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t
ropMOVZX_32_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), IREG_8(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_32(dest_reg), IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t
ropMOVZX_32_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int dest_reg = (fetchdat >> 3) & 7;
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int src_reg = fetchdat & 7;
uop_MOVZX(ir, IREG_32(dest_reg), IREG_16(src_reg));
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_read(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MOVZX(ir, IREG_32(dest_reg), IREG_temp0_W);
}
return op_pc + 1;
}
uint32_t
ropXCHG_AX(UNUSED(codeblock_t *block), ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int reg2 = IREG_16(opcode & 7);
uop_MOV(ir, IREG_temp0_W, IREG_AX);
uop_MOV(ir, IREG_AX, reg2);
uop_MOV(ir, reg2, IREG_temp0_W);
return op_pc;
}
uint32_t
ropXCHG_EAX(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int reg2 = IREG_32(opcode & 7);
uop_MOV(ir, IREG_temp0, IREG_EAX);
uop_MOV(ir, IREG_EAX, reg2);
uop_MOV(ir, reg2, IREG_temp0);
return op_pc;
}
uint32_t
ropXCHG_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_8((fetchdat >> 3) & 7);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int reg2 = IREG_8(fetchdat & 7);
uop_MOV(ir, IREG_temp0_B, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0_B);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_B, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0_B);
}
return op_pc + 1;
}
uint32_t
ropXCHG_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_16((fetchdat >> 3) & 7);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int reg2 = IREG_16(fetchdat & 7);
uop_MOV(ir, IREG_temp0_W, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0_W);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0_W);
}
return op_pc + 1;
}
uint32_t
ropXCHG_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
int reg1 = IREG_32((fetchdat >> 3) & 7);
codegen_mark_code_present(block, cs + op_pc, 1);
if ((fetchdat & 0xc0) == 0xc0) {
int reg2 = IREG_32(fetchdat & 7);
uop_MOV(ir, IREG_temp0, reg1);
uop_MOV(ir, reg1, reg2);
uop_MOV(ir, reg2, IREG_temp0);
} else {
x86seg *target_seg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, reg1);
uop_MOV(ir, reg1, IREG_temp0);
}
return op_pc + 1;
}
uint32_t
ropXLAT(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_MOVZX(ir, IREG_eaaddr, IREG_AL);
uop_ADD(ir, IREG_eaaddr, IREG_eaaddr, IREG_EBX);
if (!(op_32 & 0x200))
uop_AND_IMM(ir, IREG_eaaddr, IREG_eaaddr, 0xffff);
uop_MEM_LOAD_REG(ir, IREG_AL, ireg_seg_base(op_ea_seg), IREG_eaaddr);
return op_pc;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mov.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,201 |
```objective-c
uint32_t ropPACKSSWB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPACKSSDW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPACKUSWB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKLBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKLWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKLDQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKHBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKHWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKHDQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_pack.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 406 |
```objective-c
void host_x86_ADD32_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_ADD8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_ADD16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_ADD32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_ADD8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADD16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_ADD32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_AND16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_AND32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_AND8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_AND32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_CALL(codeblock_t *block, void *p);
void host_x86_CMP16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_CMP32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_CMP8_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CMP16_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_CMP32_REG_REG(codeblock_t *block, int src_reg_a, int src_reg_b);
void host_x86_INC32_ABS(codeblock_t *block, void *p);
void host_x86_JMP(codeblock_t *block, void *p);
uint32_t *host_x86_JMP_short(codeblock_t *block);
uint32_t *host_x86_JMP_long(codeblock_t *block);
void host_x86_JNZ(codeblock_t *block, void *p);
void host_x86_JZ(codeblock_t *block, void *p);
uint8_t *host_x86_JNZ_short(codeblock_t *block);
uint8_t *host_x86_JS_short(codeblock_t *block);
uint8_t *host_x86_JZ_short(codeblock_t *block);
uint32_t *host_x86_JNB_long(codeblock_t *block);
uint32_t *host_x86_JNBE_long(codeblock_t *block);
uint32_t *host_x86_JNL_long(codeblock_t *block);
uint32_t *host_x86_JNLE_long(codeblock_t *block);
uint32_t *host_x86_JNO_long(codeblock_t *block);
uint32_t *host_x86_JNS_long(codeblock_t *block);
uint32_t *host_x86_JNZ_long(codeblock_t *block);
uint32_t *host_x86_JB_long(codeblock_t *block);
uint32_t *host_x86_JBE_long(codeblock_t *block);
uint32_t *host_x86_JL_long(codeblock_t *block);
uint32_t *host_x86_JLE_long(codeblock_t *block);
uint32_t *host_x86_JO_long(codeblock_t *block);
uint32_t *host_x86_JS_long(codeblock_t *block);
uint32_t *host_x86_JZ_long(codeblock_t *block);
void host_x86_LAHF(codeblock_t *block);
void host_x86_LEA_REG_IMM(codeblock_t *block, int dst_reg, int src_reg_a, uint32_t offset);
void host_x86_LEA_REG_REG(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b);
void host_x86_LEA_REG_REG_SHIFT(codeblock_t *block, int dst_reg, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOV8_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV16_ABS_IMM(codeblock_t *block, void *p, uint16_t imm_data);
void host_x86_MOV32_ABS_IMM(codeblock_t *block, void *p, uint32_t imm_data);
void host_x86_MOV8_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV16_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV32_ABS_REG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOV8_ABS_REG_REG_SHIFT_REG(codeblock_t *block, uint32_t addr, int base_reg, int idx_reg, int shift, int src_reg);
void host_x86_MOV8_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOV16_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOV32_BASE_INDEX_REG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOV16_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
void host_x86_MOV32_BASE_OFFSET_REG(codeblock_t *block, int base_reg, int offset, int dst_reg);
void host_x86_MOV32_BASE_OFFSET_IMM(codeblock_t *block, int base_reg, int offset, uint32_t imm_data);
void host_x86_MOV8_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV16_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV32_REG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOV32_REG_ABS_INDEX_SHIFT(codeblock_t *block, int dst_reg, void *p, int idx_reg, int shift);
void host_x86_MOV8_REG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_addr, uint32_t addr, int base_reg, int idx_reg, int shift);
void host_x86_MOV32_REG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOV16_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOV32_REG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOV8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_MOV16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_MOV32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_MOV8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOV32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
#define host_x86_MOV16_STACK_REG(block, offset, src_reg) host_x86_MOV16_BASE_OFFSET_REG(block, REG_ESP, offset, src_reg)
void host_x86_MOV32_STACK_IMM(codeblock_t *block, int32_t offset, uint32_t imm_data);
void host_x86_MOVSX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVSX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVSX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_16_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_8(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_32_16(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVZX_REG_ABS_16_8(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVZX_REG_ABS_32_8(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVZX_REG_ABS_32_16(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVZX_BASE_INDEX_32_8(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVZX_BASE_INDEX_32_16(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_OR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_OR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_OR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_OR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_OR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_OR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_POP(codeblock_t *block, int src_reg);
void host_x86_PUSH(codeblock_t *block, int src_reg);
void host_x86_RET(codeblock_t *block);
void host_x86_ROL8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROL8_CL(codeblock_t *block, int dst_reg);
void host_x86_ROL16_CL(codeblock_t *block, int dst_reg);
void host_x86_ROL32_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_ROR8_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR16_CL(codeblock_t *block, int dst_reg);
void host_x86_ROR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR8_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR16_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SAR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SAR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SAR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL8_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL16_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL32_CL(codeblock_t *block, int dst_reg);
void host_x86_SHL8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHL32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR8_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR16_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR32_CL(codeblock_t *block, int dst_reg);
void host_x86_SHR8_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR16_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SHR32_IMM(codeblock_t *block, int dst_reg, int shift);
void host_x86_SUB8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_SUB16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_SUB32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
void host_x86_SUB8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUB16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_SUB32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_TEST8_REG(codeblock_t *block, int src_host_reg, int dst_host_reg);
void host_x86_TEST16_REG(codeblock_t *block, int src_host_reg, int dst_host_reg);
void host_x86_TEST32_REG(codeblock_t *block, int src_host_reg, int dst_host_reg);
void host_x86_TEST32_REG_IMM(codeblock_t *block, int src_host_reg, uint32_t imm_data);
void host_x86_XOR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_XOR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_XOR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,081 |
```c
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include <stddef.h>
# include <stdint.h>
# include <stdlib.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86_defs.h"
# include "codegen_backend_x86_ops.h"
# include "codegen_backend_x86_ops_sse.h"
# include "codegen_reg.h"
# include "x86.h"
# include "x86seg_common.h"
# include "x86seg.h"
# if defined(__linux__) || defined(__APPLE__)
# include <sys/mman.h>
# include <unistd.h>
# endif
# if defined WIN32 || defined _WIN32 || defined _WIN32
# include <windows.h>
# endif
# include <string.h>
void *codegen_mem_load_byte;
void *codegen_mem_load_word;
void *codegen_mem_load_long;
void *codegen_mem_load_quad;
void *codegen_mem_load_single;
void *codegen_mem_load_double;
void *codegen_mem_store_byte;
void *codegen_mem_store_word;
void *codegen_mem_store_long;
void *codegen_mem_store_quad;
void *codegen_mem_store_single;
void *codegen_mem_store_double;
void *codegen_gpf_rout;
void *codegen_exit_rout;
host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS] = {
/*Note: while EAX and EDX are normally volatile registers under x86
calling conventions, the recompiler will explicitly save and restore
them across funcion calls*/
{REG_EAX, 0},
{ REG_EBX, 0},
{ REG_EDX, 0}
};
host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS] = {
{REG_XMM0, HOST_REG_FLAG_VOLATILE},
{ REG_XMM1, HOST_REG_FLAG_VOLATILE},
{ REG_XMM2, HOST_REG_FLAG_VOLATILE},
{ REG_XMM3, HOST_REG_FLAG_VOLATILE},
{ REG_XMM4, HOST_REG_FLAG_VOLATILE},
{ REG_XMM5, HOST_REG_FLAG_VOLATILE}
};
static void
build_load_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ESI = address
Out - ECX = data, ESI = abrt*/
/*MOV ECX, ESI
SHR ESI, 12
MOV ESI, [readlookup2+ESI*4]
CMP ESI, -1
JNZ +
MOVZX ECX, B[ESI+ECX]
XOR ESI,ESI
RET
* PUSH EAX
PUSH EDX
PUSH ECX
CALL readmembl
POP ECX
POP EDX
POP EAX
MOVZX ECX, AL
RET
*/
host_x86_MOV32_REG_REG(block, REG_ECX, REG_ESI);
host_x86_SHR32_IMM(block, REG_ESI, 12);
host_x86_MOV32_REG_ABS_INDEX_SHIFT(block, REG_ESI, readlookup2, REG_ESI, 2);
if (size != 1) {
host_x86_TEST32_REG_IMM(block, REG_ECX, size - 1);
misaligned_offset = host_x86_JNZ_short(block);
}
host_x86_CMP32_REG_IMM(block, REG_ESI, (uint32_t) -1);
branch_offset = host_x86_JZ_short(block);
if (size == 1 && !is_float)
host_x86_MOVZX_BASE_INDEX_32_8(block, REG_ECX, REG_ESI, REG_ECX);
else if (size == 2 && !is_float)
host_x86_MOVZX_BASE_INDEX_32_16(block, REG_ECX, REG_ESI, REG_ECX);
else if (size == 4 && !is_float)
host_x86_MOV32_REG_BASE_INDEX(block, REG_ECX, REG_ESI, REG_ECX);
else if (size == 4 && is_float)
host_x86_CVTSS2SD_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_ESI, REG_ECX);
else if (size == 8)
host_x86_MOVQ_XREG_BASE_INDEX(block, REG_XMM_TEMP, REG_ESI, REG_ECX);
else
fatal("build_load_routine: size=%i\n", size);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
host_x86_RET(block);
*branch_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 1;
if (size != 1)
*misaligned_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 1;
host_x86_PUSH(block, REG_EAX);
host_x86_PUSH(block, REG_EDX);
host_x86_PUSH(block, REG_ECX);
if (size == 1)
host_x86_CALL(block, (void *) readmembl);
else if (size == 2)
host_x86_CALL(block, (void *) readmemwl);
else if (size == 4)
host_x86_CALL(block, (void *) readmemll);
else if (size == 8)
host_x86_CALL(block, (void *) readmemql);
host_x86_POP(block, REG_ECX);
if (size == 1 && !is_float)
host_x86_MOVZX_REG_32_8(block, REG_ECX, REG_EAX);
else if (size == 2 && !is_float)
host_x86_MOVZX_REG_32_16(block, REG_ECX, REG_EAX);
else if (size == 4 && !is_float)
host_x86_MOV32_REG_REG(block, REG_ECX, REG_EAX);
else if (size == 4 && is_float) {
host_x86_MOVD_XREG_REG(block, REG_XMM_TEMP, REG_EAX);
host_x86_CVTSS2SD_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP);
} else if (size == 8) {
host_x86_MOVD_XREG_REG(block, REG_XMM_TEMP, REG_EAX);
host_x86_MOVD_XREG_REG(block, REG_XMM_TEMP2, REG_EDX);
host_x86_UNPCKLPS_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP2);
}
host_x86_POP(block, REG_EDX);
host_x86_POP(block, REG_EAX);
host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
host_x86_RET(block);
block_pos = (block_pos + 63) & ~63;
}
static void
build_store_routine(codeblock_t *block, int size, int is_float)
{
uint8_t *branch_offset;
uint8_t *misaligned_offset = NULL;
/*In - ECX = data, ESI = address
Out - ESI = abrt
Corrupts EDI*/
/*MOV EDI, ESI
SHR ESI, 12
MOV ESI, [writelookup2+ESI*4]
CMP ESI, -1
JNZ +
MOV [ESI+EDI], ECX
XOR ESI,ESI
RET
* PUSH EAX
PUSH EDX
PUSH ECX
CALL writemembl
POP ECX
POP EDX
POP EAX
MOVZX ECX, AL
RET
*/
host_x86_MOV32_REG_REG(block, REG_EDI, REG_ESI);
host_x86_SHR32_IMM(block, REG_ESI, 12);
host_x86_MOV32_REG_ABS_INDEX_SHIFT(block, REG_ESI, writelookup2, REG_ESI, 2);
if (size != 1) {
host_x86_TEST32_REG_IMM(block, REG_EDI, size - 1);
misaligned_offset = host_x86_JNZ_short(block);
}
host_x86_CMP32_REG_IMM(block, REG_ESI, (uint32_t) -1);
branch_offset = host_x86_JZ_short(block);
if (size == 1 && !is_float)
host_x86_MOV8_BASE_INDEX_REG(block, REG_ESI, REG_EDI, REG_ECX);
else if (size == 2 && !is_float)
host_x86_MOV16_BASE_INDEX_REG(block, REG_ESI, REG_EDI, REG_ECX);
else if (size == 4 && !is_float)
host_x86_MOV32_BASE_INDEX_REG(block, REG_ESI, REG_EDI, REG_ECX);
else if (size == 4 && is_float)
host_x86_MOVD_BASE_INDEX_XREG(block, REG_ESI, REG_EDI, REG_XMM_TEMP);
else if (size == 8)
host_x86_MOVQ_BASE_INDEX_XREG(block, REG_ESI, REG_EDI, REG_XMM_TEMP);
else
fatal("build_store_routine: size=%i is_float=%i\n", size, is_float);
host_x86_XOR32_REG_REG(block, REG_ESI, REG_ESI);
host_x86_RET(block);
*branch_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 1;
if (size != 1)
*misaligned_offset = (uint8_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) misaligned_offset) - 1;
if (size == 4 && is_float)
host_x86_MOVD_REG_XREG(block, REG_ECX, REG_XMM_TEMP);
host_x86_PUSH(block, REG_EAX);
host_x86_PUSH(block, REG_EDX);
host_x86_PUSH(block, REG_ECX);
if (size == 8) {
host_x86_MOVQ_STACK_OFFSET_XREG(block, -8, REG_XMM_TEMP);
host_x86_SUB32_REG_IMM(block, REG_ESP, 8);
}
host_x86_PUSH(block, REG_EDI);
if (size == 1)
host_x86_CALL(block, (void *) writemembl);
else if (size == 2)
host_x86_CALL(block, (void *) writememwl);
else if (size == 4)
host_x86_CALL(block, (void *) writememll);
else if (size == 8)
host_x86_CALL(block, (void *) writememql);
host_x86_POP(block, REG_EDI);
if (size == 8)
host_x86_ADD32_REG_IMM(block, REG_ESP, 8);
host_x86_POP(block, REG_ECX);
host_x86_POP(block, REG_EDX);
host_x86_POP(block, REG_EAX);
host_x86_MOVZX_REG_ABS_32_8(block, REG_ESI, &cpu_state.abrt);
host_x86_RET(block);
block_pos = (block_pos + 63) & ~63;
}
static void
build_loadstore_routines(codeblock_t *block)
{
codegen_mem_load_byte = &codeblock[block_current].data[block_pos];
build_load_routine(block, 1, 0);
codegen_mem_load_word = &codeblock[block_current].data[block_pos];
build_load_routine(block, 2, 0);
codegen_mem_load_long = &codeblock[block_current].data[block_pos];
build_load_routine(block, 4, 0);
codegen_mem_load_quad = &codeblock[block_current].data[block_pos];
build_load_routine(block, 8, 0);
codegen_mem_load_single = &codeblock[block_current].data[block_pos];
build_load_routine(block, 4, 1);
codegen_mem_load_double = &codeblock[block_current].data[block_pos];
build_load_routine(block, 8, 1);
codegen_mem_store_byte = &codeblock[block_current].data[block_pos];
build_store_routine(block, 1, 0);
codegen_mem_store_word = &codeblock[block_current].data[block_pos];
build_store_routine(block, 2, 0);
codegen_mem_store_long = &codeblock[block_current].data[block_pos];
build_store_routine(block, 4, 0);
codegen_mem_store_quad = &codeblock[block_current].data[block_pos];
build_store_routine(block, 8, 0);
codegen_mem_store_single = &codeblock[block_current].data[block_pos];
build_store_routine(block, 4, 1);
codegen_mem_store_double = &codeblock[block_current].data[block_pos];
build_store_routine(block, 8, 1);
}
void
codegen_backend_init(void)
{
codeblock_t *block;
codeblock = malloc(BLOCK_SIZE * sizeof(codeblock_t));
codeblock_hash = malloc(HASH_SIZE * sizeof(codeblock_t *));
memset(codeblock, 0, BLOCK_SIZE * sizeof(codeblock_t));
memset(codeblock_hash, 0, HASH_SIZE * sizeof(codeblock_t *));
for (uint32_t c = 0; c < BLOCK_SIZE; c++)
codeblock[c].pc = BLOCK_PC_INVALID;
block_current = 0;
block_pos = 0;
block = &codeblock[block_current];
block->head_mem_block = codegen_allocator_allocate(NULL, block_current);
block->data = codeblock_allocator_get_ptr(block->head_mem_block);
block_write_data = block->data;
build_loadstore_routines(block);
codegen_gpf_rout = &codeblock[block_current].data[block_pos];
host_x86_MOV32_STACK_IMM(block, STACK_ARG0, 0);
host_x86_MOV32_STACK_IMM(block, STACK_ARG1, 0);
host_x86_CALL(block, (void *) x86gpf);
codegen_exit_rout = &codeblock[block_current].data[block_pos];
host_x86_ADD32_REG_IMM(block, REG_ESP, 64);
host_x86_POP(block, REG_EDI);
host_x86_POP(block, REG_ESI);
host_x86_POP(block, REG_EBP);
host_x86_POP(block, REG_EDX);
host_x86_RET(block);
block_write_data = NULL;
cpu_state.old_fp_control = 0;
asm(
"fstcw %0\n"
"stmxcsr %1\n"
: "=m"(cpu_state.old_fp_control2),
"=m"(cpu_state.old_fp_control));
cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000;
}
void
codegen_set_rounding_mode(int mode)
{
/*SSE*/
cpu_state.new_fp_control = (cpu_state.old_fp_control & ~0x6000) | (mode << 13);
/*x87 - used for double -> i64 conversions*/
cpu_state.new_fp_control2 = (cpu_state.old_fp_control2 & ~0x0c00) | (mode << 10);
}
void
codegen_backend_prologue(codeblock_t *block)
{
block_pos = BLOCK_START; /*Entry code*/
host_x86_PUSH(block, REG_EBX);
host_x86_PUSH(block, REG_EBP);
host_x86_PUSH(block, REG_ESI);
host_x86_PUSH(block, REG_EDI);
host_x86_SUB32_REG_IMM(block, REG_ESP, 64);
host_x86_MOV32_REG_IMM(block, REG_EBP, ((uintptr_t) &cpu_state) + 128);
if (block->flags & CODEBLOCK_HAS_FPU) {
host_x86_MOV32_REG_ABS(block, REG_EAX, &cpu_state.TOP);
host_x86_SUB32_REG_IMM(block, REG_EAX, block->TOP);
host_x86_MOV32_BASE_OFFSET_REG(block, REG_ESP, IREG_TOP_diff_stack_offset, REG_EAX);
}
}
void
codegen_backend_epilogue(codeblock_t *block)
{
host_x86_ADD32_REG_IMM(block, REG_ESP, 64);
host_x86_POP(block, REG_EDI);
host_x86_POP(block, REG_ESI);
host_x86_POP(block, REG_EBP);
host_x86_POP(block, REG_EDX);
host_x86_RET(block);
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,714 |
```objective-c
uint32_t ropLEA_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLEA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF6(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF7_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropF7_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropNOP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCDQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCWDE(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLDS_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLDS_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLES_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLES_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLFS_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLFS_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLGS_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLGS_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLSS_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLSS_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCLC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSTC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSTD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCLI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSTI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_misc.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,244 |
```objective-c
#ifndef _CODEGEN_OPS_H_
#define _CODEGEN_OPS_H_
#include "codegen.h"
struct ir_data_t;
typedef uint32_t (*RecompOpFn)(codeblock_t *block, struct ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
extern RecompOpFn recomp_opcodes[512];
extern RecompOpFn recomp_opcodes_0f[512];
extern RecompOpFn recomp_opcodes_0f_no_mmx[512];
extern RecompOpFn recomp_opcodes_3DNOW[256];
extern RecompOpFn recomp_opcodes_d8[512];
extern RecompOpFn recomp_opcodes_d9[512];
extern RecompOpFn recomp_opcodes_da[512];
extern RecompOpFn recomp_opcodes_db[512];
extern RecompOpFn recomp_opcodes_dc[512];
extern RecompOpFn recomp_opcodes_dd[512];
extern RecompOpFn recomp_opcodes_de[512];
extern RecompOpFn recomp_opcodes_df[512];
#if 0
extern RecompOpFn recomp_opcodes_REPE[512];
extern RecompOpFn recomp_opcodes_REPNE[512];
#endif
#define REG_EAX 0
#define REG_ECX 1
#define REG_EDX 2
#define REG_EBX 3
#define REG_ESP 4
#define REG_EBP 5
#define REG_ESI 6
#define REG_EDI 7
#define REG_AX 0
#define REG_CX 1
#define REG_DX 2
#define REG_BX 3
#define REG_SP 4
#define REG_BP 5
#define REG_SI 6
#define REG_DI 7
#define REG_AL 0
#define REG_AH 4
#define REG_CL 1
#define REG_CH 5
#define REG_DL 2
#define REG_DH 6
#define REG_BL 3
#define REG_BH 7
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_ops.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 450 |
```c
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "codegen.h"
# include "codegen_allocator.h"
# include "codegen_backend.h"
# include "codegen_backend_x86_defs.h"
# include "codegen_backend_x86_ops_sse.h"
# include "codegen_backend_x86_ops_helpers.h"
void
host_x86_ADDPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x58, 0xc0 | src_reg | (dst_reg << 3)); /*ADDPS dst_reg, src_reg*/
}
void
host_x86_ADDSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x58, 0xc0 | src_reg | (dst_reg << 3));
}
void
host_x86_CMPPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg, int type)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xc2, 0xc0 | src_reg | (dst_reg << 3), type); /*CMPPS dst_reg, src_reg, type*/
}
void
host_x86_COMISD_XREG_XREG(codeblock_t *block, int src_reg_a, int src_reg_b)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x2e, 0xc0 | src_reg_b | (src_reg_a << 3));
}
void
host_x86_CVTDQ2PS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x5b, 0xc0 | src_reg | (dst_reg << 3)); /*CVTDQ2PS dst_reg, src_reg*/
}
void
host_x86_CVTPS2DQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x5b, 0xc0 | src_reg | (dst_reg << 3)); /*CVTPS2DQ dst_reg, src_reg*/
}
void
host_x86_CVTSD2SI_REG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x2d, 0xc0 | src_reg | (dst_reg << 3)); /*CVTSD2SI dst_reg, src_reg*/
}
void
host_x86_CVTSD2SS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x5a, 0xc0 | src_reg | (dst_reg << 3)); /*CVTSD2SS dst_reg, src_reg*/
}
void
host_x86_CVTSI2SD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x2a, 0xc0 | src_reg | (dst_reg << 3)); /*CVTSI2SD dst_reg, src_reg*/
}
void
host_x86_CVTSI2SS_XREG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf3, 0x0f, 0x2a, 0xc0 | src_reg | (dst_reg << 3)); /*CVTSI2SD dst_reg, src_reg*/
}
void
host_x86_CVTSS2SD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf3, 0x0f, 0x5a, 0xc0 | src_reg | (dst_reg << 3));
}
void
host_x86_CVTSS2SD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0xf3, 0x0f, 0x5a, 0x04 | (dst_reg << 3)); /*CVTSS2SD XMMx, [base_reg + idx_reg]*/
codegen_addbyte(block, base_reg | (idx_reg << 3));
}
void
host_x86_DIVSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x5e, 0xc0 | src_reg | (dst_reg << 3)); /*DIVSD dst_reg, src_reg*/
}
void
host_x86_DIVSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf3, 0x0f, 0x5e, 0xc0 | src_reg | (dst_reg << 3)); /*DIVSS dst_reg, src_reg*/
}
void
host_x86_LDMXCSR(codeblock_t *block, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x0f, 0xae, 0x50 | REG_EBP, offset); /*LDMXCSR offset[EBP]*/
} else {
codegen_alloc_bytes(block, 7);
codegen_addbyte3(block, 0x0f, 0xae, 0x15); /*LDMXCSR [p]*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MAXSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x5f, 0xc0 | src_reg | (dst_reg << 3)); /*MAXSD dst_reg, src_reg*/
}
void
host_x86_MOVD_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x7e, 0x04 | (src_reg << 3)); /*MOVD XMMx, [base_reg + idx_reg]*/
codegen_addbyte(block, base_reg | (idx_reg << 3));
}
void
host_x86_MOVD_REG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x7e, 0xc0 | dst_reg | (src_reg << 3));
}
void
host_x86_MOVD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x6e, 0x04 | (dst_reg << 3)); /*MOVD XMMx, [base_reg + idx_reg]*/
codegen_addbyte(block, base_reg | (idx_reg << 3));
}
void
host_x86_MOVD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x6e, 0xc0 | src_reg | (dst_reg << 3));
}
void
host_x86_MOVQ_ABS_XREG(codeblock_t *block, void *p, int src_reg)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x45 | (src_reg << 3)); /*MOVQ offset[EBP], src_reg*/
codegen_addbyte(block, offset);
} else {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x05 | (src_reg << 3)); /*MOVQ [p], src_reg*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift, int src_reg)
{
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 6);
codegen_addbyte3(block, 0x66, 0x0f, 0xd6); /*MOVQ addr[src_reg_a + src_reg_b << shift], XMMx*/
codegen_addbyte3(block, 0x44 | (src_reg << 3), src_reg_a | (src_reg_b << 3) | (shift << 6), addr & 0xff);
} else {
codegen_alloc_bytes(block, 9);
codegen_addbyte3(block, 0x66, 0x0f, 0xd6); /*MOVQ addr[src_reg_a + src_reg_b << shift], XMMx*/
codegen_addbyte2(block, 0x84 | (src_reg << 3), src_reg_a | (src_reg_b << 3) | (shift << 6));
codegen_addlong(block, addr);
}
}
void
host_x86_MOVQ_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x04 | (src_reg << 3)); /*MOVQ XMMx, [base_reg + idx_reg]*/
codegen_addbyte(block, base_reg | (idx_reg << 3));
}
void
host_x86_MOVQ_BASE_OFFSET_XREG(codeblock_t *block, int base_reg, int offset, int src_reg)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x44 | (src_reg << 3)); /*MOVQ [ESP + offset], XMMx*/
codegen_addbyte2(block, 0x24, offset);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x40 | base_reg | (src_reg << 3)); /*MOVQ [base_reg + offset], XMMx*/
codegen_addbyte(block, offset);
}
} else
fatal("MOVQ_BASE_OFFSET_XREG - offset %i\n", offset);
}
void
host_x86_MOVQ_STACK_OFFSET_XREG(codeblock_t *block, int offset, int src_reg)
{
if (!offset) {
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x04 | (src_reg << 3)); /*MOVQ [ESP], src_reg*/
codegen_addbyte(block, 0x24);
} else if (offset >= -0x80 && offset < 0x80) {
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x44 | (src_reg << 3)); /*MOVQ offset[ESP], src_reg*/
codegen_addbyte2(block, 0x24, offset & 0xff);
} else {
codegen_alloc_bytes(block, 9);
codegen_addbyte4(block, 0x66, 0x0f, 0xd6, 0x84 | (src_reg << 3)); /*MOVQ offset[ESP], src_reg*/
codegen_addbyte(block, 0x24);
codegen_addlong(block, offset);
}
}
void
host_x86_MOVQ_XREG_ABS(codeblock_t *block, int dst_reg, void *p)
{
int offset = (uintptr_t) p - (((uintptr_t) &cpu_state) + 128);
if (offset >= -128 && offset < 127) {
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0x45 | (dst_reg << 3)); /*MOVQ offset[EBP], src_reg*/
codegen_addbyte(block, offset);
} else {
codegen_alloc_bytes(block, 8);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0x05 | (dst_reg << 3)); /*MOVQ [p], src_reg*/
codegen_addlong(block, (uint32_t) p);
}
}
void
host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b, int shift)
{
if (addr < 0x80 || addr >= 0xffffff80) {
codegen_alloc_bytes(block, 6);
codegen_addbyte3(block, 0xf3, 0x0f, 0x7e); /*MOVQ XMMx, addr[src_reg_a + src_reg_b << shift]*/
codegen_addbyte3(block, 0x44 | (dst_reg << 3), src_reg_a | (src_reg_b << 3) | (shift << 6), addr & 0xff);
} else {
codegen_alloc_bytes(block, 9);
codegen_addbyte3(block, 0xf3, 0x0f, 0x7e); /*MOVQ XMMx, addr[src_reg_a + src_reg_b << shift]*/
codegen_addbyte2(block, 0x84 | (dst_reg << 3), src_reg_a | (src_reg_b << 3) | (shift << 6));
codegen_addlong(block, addr);
}
}
void
host_x86_MOVQ_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0x04 | (dst_reg << 3)); /*MOVQ XMMx, [base_reg + idx_reg]*/
codegen_addbyte(block, base_reg | (idx_reg << 3));
}
void
host_x86_MOVQ_XREG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset)
{
if (offset >= -128 && offset < 127) {
if (base_reg == REG_ESP) {
codegen_alloc_bytes(block, 6);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0x44 | (dst_reg << 3)); /*MOVQ XMMx, [ESP + offset]*/
codegen_addbyte2(block, 0x24, offset);
} else {
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0x40 | base_reg | (dst_reg << 3)); /*MOVQ XMMx, [base_reg + offset]*/
codegen_addbyte(block, offset);
}
} else
fatal("MOVQ_REG_BASE_OFFSET - offset %i\n", offset);
}
void
host_x86_MOVQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf3, 0x0f, 0x7e, 0xc0 | src_reg | (dst_reg << 3)); /*MOVQ dst_reg, src_reg*/
}
void
host_x86_MAXPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x5f, 0xc0 | src_reg | (dst_reg << 3)); /*MAXPS dst_reg, src_reg*/
}
void
host_x86_MINPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x5d, 0xc0 | src_reg | (dst_reg << 3)); /*MINPS dst_reg, src_reg*/
}
void
host_x86_MULPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x59, 0xc0 | src_reg | (dst_reg << 3)); /*MULPS dst_reg, src_reg*/
}
void
host_x86_MULSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x59, 0xc0 | src_reg | (dst_reg << 3));
}
void
host_x86_PACKSSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 9);
codegen_addbyte4(block, 0x66, 0x0f, 0x63, 0xc0 | src_reg | (dst_reg << 3)); /*PACKSSWB dst_reg, src_reg*/
codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0x88 (move bits 64-95 to 32-63)*/
codegen_addbyte(block, 0x88);
}
void
host_x86_PACKSSDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 9);
codegen_addbyte4(block, 0x66, 0x0f, 0x6b, 0xc0 | src_reg | (dst_reg << 3)); /*PACKSSDW dst_reg, src_reg*/
codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0x88 (move bits 64-95 to 32-63)*/
codegen_addbyte(block, 0x88);
}
void
host_x86_PACKUSWB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 9);
codegen_addbyte4(block, 0x66, 0x0f, 0x67, 0xc0 | src_reg | (dst_reg << 3)); /*PACKUSWB dst_reg, src_reg*/
codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | dst_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0x88 (move bits 64-95 to 32-63)*/
codegen_addbyte(block, 0x88);
}
void
host_x86_PADDB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xfc, 0xc0 | src_reg | (dst_reg << 3)); /*PADDB dst_reg, src_reg*/
}
void
host_x86_PADDW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xfd, 0xc0 | src_reg | (dst_reg << 3)); /*PADDW dst_reg, src_reg*/
}
void
host_x86_PADDD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xfe, 0xc0 | src_reg | (dst_reg << 3)); /*PADDD dst_reg, src_reg*/
}
void
host_x86_PADDSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xec, 0xc0 | src_reg | (dst_reg << 3)); /*PADDSB dst_reg, src_reg*/
}
void
host_x86_PADDSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xed, 0xc0 | src_reg | (dst_reg << 3)); /*PADDSW dst_reg, src_reg*/
}
void
host_x86_PADDUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xdc, 0xc0 | src_reg | (dst_reg << 3)); /*PADDUSB dst_reg, src_reg*/
}
void
host_x86_PADDUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xdd, 0xc0 | src_reg | (dst_reg << 3)); /*PADDUSW dst_reg, src_reg*/
}
void
host_x86_PAND_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xdb, 0xc0 | src_reg | (dst_reg << 3)); /*PAND dst_reg, src_reg*/
}
void
host_x86_PANDN_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xdf, 0xc0 | src_reg | (dst_reg << 3)); /*PANDN dst_reg, src_reg*/
}
void
host_x86_POR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xeb, 0xc0 | src_reg | (dst_reg << 3)); /*POR dst_reg, src_reg*/
}
void
host_x86_PXOR_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xef, 0xc0 | src_reg | (dst_reg << 3)); /*PXOR dst_reg, src_reg*/
}
void
host_x86_PCMPEQB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x74, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPEQB dst_reg, src_reg*/
}
void
host_x86_PCMPEQW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x75, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPEQW dst_reg, src_reg*/
}
void
host_x86_PCMPEQD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x76, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPEQD dst_reg, src_reg*/
}
void
host_x86_PCMPGTB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x64, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPGTB dst_reg, src_reg*/
}
void
host_x86_PCMPGTW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x65, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPGTW dst_reg, src_reg*/
}
void
host_x86_PCMPGTD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x66, 0xc0 | src_reg | (dst_reg << 3)); /*PCMPGTD dst_reg, src_reg*/
}
void
host_x86_PMADDWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xf5, 0xc0 | src_reg | (dst_reg << 3)); /*PMULLW dst_reg, src_reg*/
}
void
host_x86_PMULHW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xe5, 0xc0 | src_reg | (dst_reg << 3)); /*PMULLW dst_reg, src_reg*/
}
void
host_x86_PMULLW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xd5, 0xc0 | src_reg | (dst_reg << 3)); /*PMULLW dst_reg, src_reg*/
}
void
host_x86_PSHUFD_XREG_XREG_IMM(codeblock_t *block, int dst_reg, int src_reg, uint8_t shuffle)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x70, 0xc0 | src_reg | (dst_reg << 3)); /*PSHUFD dst_reg, dst_reg, 0xee (move top 64-bits to low 64-bits)*/
codegen_addbyte(block, shuffle);
}
void
host_x86_PSLLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x71, 0xc0 | 0x30 | dst_reg); /*PSLLW dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSLLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x72, 0xc0 | 0x30 | dst_reg); /*PSLLD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSLLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x73, 0xc0 | 0x30 | dst_reg); /*PSLLD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRAW_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x71, 0xc0 | 0x20 | dst_reg); /*PSRAW dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRAD_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x72, 0xc0 | 0x20 | dst_reg); /*PSRAD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRAQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x73, 0xc0 | 0x20 | dst_reg); /*PSRAD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRLW_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x71, 0xc0 | 0x10 | dst_reg); /*PSRLW dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRLD_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x72, 0xc0 | 0x10 | dst_reg); /*PSRLD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSRLQ_XREG_IMM(codeblock_t *block, int dst_reg, int shift)
{
codegen_alloc_bytes(block, 5);
codegen_addbyte4(block, 0x66, 0x0f, 0x73, 0xc0 | 0x10 | dst_reg); /*PSRLD dst_reg, imm*/
codegen_addbyte(block, shift);
}
void
host_x86_PSUBB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xf8, 0xc0 | src_reg | (dst_reg << 3)); /*PADDB dst_reg, src_reg*/
}
void
host_x86_PSUBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xf9, 0xc0 | src_reg | (dst_reg << 3)); /*PADDW dst_reg, src_reg*/
}
void
host_x86_PSUBD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xfa, 0xc0 | src_reg | (dst_reg << 3)); /*PADDD dst_reg, src_reg*/
}
void
host_x86_PSUBSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xe8, 0xc0 | src_reg | (dst_reg << 3)); /*PSUBSB dst_reg, src_reg*/
}
void
host_x86_PSUBSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xe9, 0xc0 | src_reg | (dst_reg << 3)); /*PSUBSW dst_reg, src_reg*/
}
void
host_x86_PSUBUSB_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xd8, 0xc0 | src_reg | (dst_reg << 3)); /*PSUBUSB dst_reg, src_reg*/
}
void
host_x86_PSUBUSW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0xd9, 0xc0 | src_reg | (dst_reg << 3)); /*PSUBUSW dst_reg, src_reg*/
}
void
host_x86_PUNPCKLBW_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x60, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLBW dst_reg, src_reg*/
}
void
host_x86_PUNPCKLWD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x61, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLWD dst_reg, src_reg*/
}
void
host_x86_PUNPCKLDQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0x66, 0x0f, 0x62, 0xc0 | src_reg | (dst_reg << 3)); /*PUNPCKLDQ dst_reg, src_reg*/
}
void
host_x86_SQRTSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x51, 0xc0 | src_reg | (dst_reg << 3)); /*SQRTSD dst_reg, src_reg*/
}
void
host_x86_SQRTSS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf3, 0x0f, 0x51, 0xc0 | src_reg | (dst_reg << 3)); /*SQRTSS dst_reg, src_reg*/
}
void
host_x86_SUBPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x5c, 0xc0 | src_reg | (dst_reg << 3)); /*SUBPS dst_reg, src_reg*/
}
void
host_x86_SUBSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 4);
codegen_addbyte4(block, 0xf2, 0x0f, 0x5c, 0xc0 | src_reg | (dst_reg << 3));
}
void
host_x86_UNPCKLPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg)
{
codegen_alloc_bytes(block, 3);
codegen_addbyte3(block, 0x0f, 0x14, 0xc0 | src_reg | (dst_reg << 3));
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops_sse.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,762 |
```objective-c
#ifndef _CODEGEN_BACKEND_H_
#define _CODEGEN_BACKEND_H_
#if defined __amd64__ || defined _M_X64
# include "codegen_backend_x86-64.h"
#elif defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
# include "codegen_backend_x86.h"
#elif defined __ARM_EABI__ || defined _ARM_ || defined _M_ARM
# include "codegen_backend_arm.h"
#elif defined __aarch64__ || defined _M_ARM64
# include "codegen_backend_arm64.h"
#else
# error Dynamic recompiler not implemented on your platform
#endif
void codegen_backend_init(void);
void codegen_backend_prologue(codeblock_t *block);
void codegen_backend_epilogue(codeblock_t *block);
struct ir_data_t;
struct uop_t;
struct ir_data_t *codegen_get_ir_data(void);
typedef int (*uOpFn)(codeblock_t *codeblock, struct uop_t *uop);
extern const uOpFn uop_handlers[];
/*Register will not be preserved across function calls*/
#define HOST_REG_FLAG_VOLATILE (1 << 0)
typedef struct host_reg_def_t {
int reg;
int flags;
} host_reg_def_t;
extern host_reg_def_t codegen_host_reg_list[CODEGEN_HOST_REGS];
extern host_reg_def_t codegen_host_fp_reg_list[CODEGEN_HOST_FP_REGS];
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 309 |
```objective-c
uint32_t ropMOV_rb_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_rw_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_rl_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_b_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_w_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_l_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_r_b(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_r_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_r_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_AL_abs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_AX_abs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_EAX_abs(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_abs_AL(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_abs_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_abs_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_b_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_w_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_l_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_w_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_l_seg(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOV_seg_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVSX_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVSX_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVSX_32_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_16_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_32_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVZX_32_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_EAX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_8(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXCHG_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXLAT(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mov.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,451 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_helpers.h"
#include "codegen_ops_mov.h"
uint32_t
ropJMP_r8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc);
uint32_t dest_addr = op_pc + 1 + offset;
if (!(op_32 & 0x100))
dest_addr &= 0xffff;
if (offset < 0)
codegen_can_unroll(block, ir, op_pc + 1, dest_addr);
codegen_mark_code_present(block, cs + op_pc, 1);
return dest_addr;
}
uint32_t
ropJMP_r16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t offset = (int32_t) (int16_t) fastreadw(cs + op_pc);
uint32_t dest_addr = op_pc + 2 + offset;
dest_addr &= 0xffff;
if (offset < 0)
codegen_can_unroll(block, ir, op_pc + 1, dest_addr);
codegen_mark_code_present(block, cs + op_pc, 2);
return dest_addr;
}
uint32_t
ropJMP_r32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t offset = fastreadl(cs + op_pc);
uint32_t dest_addr = op_pc + 4 + offset;
if (offset < 0)
codegen_can_unroll(block, ir, op_pc + 1, dest_addr);
codegen_mark_code_present(block, cs + op_pc, 4);
return dest_addr;
}
uint32_t
ropJMP_far_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t new_pc = fastreadw(cs + op_pc);
uint16_t new_cs = fastreadw(cs + op_pc + 2);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_MOV_IMM(ir, IREG_pc, new_pc);
uop_LOAD_FUNC_ARG_IMM(ir, 0, new_cs);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 4);
uop_CALL_FUNC(ir, loadcsjmp);
codegen_mark_code_present(block, cs + op_pc, 4);
return -1;
}
uint32_t
ropJMP_far_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t new_pc = fastreadl(cs + op_pc);
uint16_t new_cs = fastreadw(cs + op_pc + 4);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
uop_MOV_IMM(ir, IREG_pc, new_pc);
uop_LOAD_FUNC_ARG_IMM(ir, 0, new_cs);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 4);
uop_CALL_FUNC(ir, loadcsjmp);
codegen_mark_code_present(block, cs + op_pc, 6);
return -1;
}
uint32_t
ropCALL_r16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t offset = (int32_t) (int16_t) fastreadw(cs + op_pc);
uint16_t ret_addr = op_pc + 2;
uint16_t dest_addr = ret_addr + offset;
int sp_reg;
dest_addr &= 0xffff;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2);
uop_MEM_STORE_IMM_16(ir, IREG_SS_base, sp_reg, ret_addr);
SUB_SP(ir, 2);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
codegen_mark_code_present(block, cs + op_pc, 2);
return -1;
}
uint32_t
ropCALL_r32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint32_t offset = fastreadl(cs + op_pc);
uint32_t ret_addr = op_pc + 4;
uint32_t dest_addr = ret_addr + offset;
int sp_reg;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4);
uop_MEM_STORE_IMM_32(ir, IREG_SS_base, sp_reg, ret_addr);
SUB_SP(ir, 4);
uop_MOV_IMM(ir, IREG_pc, dest_addr);
codegen_mark_code_present(block, cs + op_pc, 4);
return -1;
}
uint32_t
ropRET_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), UNUSED(uint32_t op_pc))
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr);
}
ADD_SP(ir, 2);
uop_MOVZX(ir, IREG_pc, IREG_temp0_W);
return -1;
}
uint32_t
ropRET_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), UNUSED(uint32_t op_pc))
{
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_pc, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_pc, IREG_SS_base, IREG_eaaddr);
}
ADD_SP(ir, 4);
return -1;
}
uint32_t
ropRET_imm_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr);
}
ADD_SP(ir, 2 + offset);
uop_MOVZX(ir, IREG_pc, IREG_temp0_W);
codegen_mark_code_present(block, cs + op_pc, 2);
return -1;
}
uint32_t
ropRET_imm_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32)
uop_MEM_LOAD_REG(ir, IREG_pc, IREG_SS_base, IREG_ESP);
else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_pc, IREG_SS_base, IREG_eaaddr);
}
ADD_SP(ir, 4 + offset);
codegen_mark_code_present(block, cs + op_pc, 2);
return -1;
}
uint32_t
ropRETF_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), UNUSED(uint32_t op_pc))
{
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32) {
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_ESP, 2);
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_eaaddr, 2);
}
uop_MOVZX(ir, IREG_pc, IREG_temp0_W);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_CALL_FUNC(ir, loadcs);
ADD_SP(ir, 4);
return -1;
}
uint32_t
ropRETF_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), UNUSED(uint32_t op_pc))
{
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG))
return 0;
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32) {
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_ESP);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_ESP, 4);
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_eaaddr);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_eaaddr, 4);
}
uop_MOV(ir, IREG_pc, IREG_temp0);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_CALL_FUNC(ir, loadcs);
ADD_SP(ir, 8);
return -1;
}
uint32_t
ropRETF_imm_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t offset;
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG))
return 0;
offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32) {
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_ESP, 2);
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_eaaddr, 2);
}
uop_MOVZX(ir, IREG_pc, IREG_temp0_W);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_CALL_FUNC(ir, loadcs);
ADD_SP(ir, 4 + offset);
codegen_mark_code_present(block, cs + op_pc, 2);
return -1;
}
uint32_t
ropRETF_imm_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uint16_t offset;
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG))
return 0;
offset = fastreadw(cs + op_pc);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
if (stack32) {
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_ESP);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_ESP, 4);
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
uop_MEM_LOAD_REG(ir, IREG_temp0, IREG_SS_base, IREG_eaaddr);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, IREG_SS_base, IREG_eaaddr, 4);
}
uop_MOV(ir, IREG_pc, IREG_temp0);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_CALL_FUNC(ir, loadcs);
ADD_SP(ir, 8 + offset);
codegen_mark_code_present(block, cs + op_pc, 2);
return -1;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_jump.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,201 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_mmx_shift.h"
#include "codegen_ops_helpers.h"
uint32_t
ropPSxxW_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = fastreadb(cs + op_pc + 1);
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
switch (op) {
case 0x10: /*PSRLW*/
uop_PSRLW_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x20: /*PSRAW*/
uop_PSRAW_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x30: /*PSLLW*/
uop_PSLLW_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
default:
return 0;
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPSxxD_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = fastreadb(cs + op_pc + 1);
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
switch (op) {
case 0x10: /*PSRLD*/
uop_PSRLD_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x20: /*PSRAD*/
uop_PSRAD_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x30: /*PSLLD*/
uop_PSLLD_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
default:
return 0;
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
uint32_t
ropPSxxQ_imm(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = fastreadb(cs + op_pc + 1);
uop_MMX_ENTER(ir);
codegen_mark_code_present(block, cs + op_pc, 1);
switch (op) {
case 0x10: /*PSRLQ*/
uop_PSRLQ_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x20: /*PSRAQ*/
uop_PSRAQ_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
case 0x30: /*PSLLQ*/
uop_PSLLQ_IMM(ir, IREG_MM(reg), IREG_MM(reg), shift);
break;
default:
return 0;
}
codegen_mark_code_present(block, cs + op_pc + 1, 1);
return op_pc + 2;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_shift.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 897 |
```c
#if defined __amd64__ || defined _M_X64
# include <stdint.h>
# include <86box/86box.h>
# include "cpu.h"
# include <86box/mem.h>
# include <86box/plat_unused.h>
# include "x86.h"
# include "x86seg_common.h"
# include "x86seg.h"
# include "x87_sf.h"
# include "x87.h"
# include "386_common.h"
# include "codegen.h"
# include "codegen_backend.h"
# include "codegen_backend_x86-64_defs.h"
# include "codegen_backend_x86-64_ops.h"
# include "codegen_backend_x86-64_ops_sse.h"
# include "codegen_ir_defs.h"
# define STACK_ARG0 (0)
# define STACK_ARG1 (4)
# define STACK_ARG2 (8)
# define STACK_ARG3 (12)
# define HOST_REG_GET(reg) ((IREG_GET_SIZE(reg) == IREG_SIZE_BH) ? (IREG_GET_REG((reg) &3) | 4) : (IREG_GET_REG(reg) & 7))
# define REG_IS_L(size) (size == IREG_SIZE_L)
# define REG_IS_W(size) (size == IREG_SIZE_W)
# define REG_IS_B(size) (size == IREG_SIZE_B || size == IREG_SIZE_BH)
# define REG_IS_BH(size) (size == IREG_SIZE_BH)
# define REG_IS_D(size) (size == IREG_SIZE_D)
# define REG_IS_Q(size) (size == IREG_SIZE_Q)
static int
codegen_ADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_LEA_REG_REG(block, dest_reg, src_reg_a, src_reg_b);
else
host_x86_ADD32_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_ADD16_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_ADD8_REG_REG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_ADD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (dest_reg != src_reg)
host_x86_LEA_REG_IMM(block, dest_reg, src_reg, uop->imm_data);
else
host_x86_ADD32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_ADD16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_ADD8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ADD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_ADD_LSHIFT(codeblock_t *block, uop_t *uop)
{
if (!uop->imm_data) {
if (uop->dest_reg_a_real == uop->src_reg_a_real)
host_x86_ADD32_REG_REG(block, uop->dest_reg_a_real, uop->src_reg_b_real);
else
host_x86_LEA_REG_REG(block, uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
} else if (uop->imm_data < 4)
host_x86_LEA_REG_REG_SHIFT(block, uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real, uop->imm_data);
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_ADD_LSHIFT - shift out of range %i\n", uop->imm_data);
# endif
return 0;
}
static int
codegen_AND(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PAND_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND32_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND16_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_AND8_REG_REG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("AND %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_AND_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_AND32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_AND16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_AND8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("AND_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_ANDN(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
#if 0
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
#endif
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PANDN_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ANDN %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_CALL_FUNC(codeblock_t *block, uop_t *uop)
{
host_x86_CALL(block, uop->p);
return 0;
}
static int
codegen_CALL_FUNC_RESULT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
# ifdef RECOMPILER_DEBUG
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_L(dest_size))
fatal("CALL_FUNC_RESULT %02x\n", uop->dest_reg_a_real);
# endif
host_x86_CALL(block, uop->p);
host_x86_MOV32_REG_REG(block, dest_reg, REG_EAX);
return 0;
}
static int
codegen_CALL_INSTRUCTION_FUNC(codeblock_t *block, uop_t *uop)
{
host_x86_CALL(block, uop->p);
host_x86_TEST32_REG(block, REG_EAX, REG_EAX);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_CMP_IMM_JZ(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_x86_CMP32_REG_IMM(block, src_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_IMM_JZ %02x\n", uop->src_reg_a_real);
# endif
host_x86_JZ(block, uop->p);
return 0;
}
static int
codegen_CMP_IMM_JNZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_x86_CMP32_REG_IMM(block, src_reg, uop->imm_data);
} else if (REG_IS_W(src_size)) {
host_x86_CMP16_REG_IMM(block, src_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_IMM_JNZ_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNZ_long(block);
return 0;
}
static int
codegen_CMP_IMM_JZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_x86_CMP32_REG_IMM(block, src_reg, uop->imm_data);
} else if (REG_IS_W(src_size)) {
host_x86_CMP16_REG_IMM(block, src_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_IMM_JZ_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JZ_long(block);
return 0;
}
static int
codegen_CMP_JB(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
uint32_t *jump_p;
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JB %02x\n", uop->src_reg_a_real);
# endif
jump_p = host_x86_JB_long(block);
*jump_p = (uintptr_t) uop->p - ((uintptr_t) jump_p + 4);
return 0;
}
static int
codegen_CMP_JNBE(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
uint32_t *jump_p;
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNBE %02x\n", uop->src_reg_a_real);
# endif
jump_p = host_x86_JNBE_long(block);
*jump_p = (uintptr_t) uop->p - ((uintptr_t) jump_p + 4);
return 0;
}
static int
codegen_CMP_JNB_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNB_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNB_long(block);
return 0;
}
static int
codegen_CMP_JNBE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNBE_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNBE_long(block);
return 0;
}
static int
codegen_CMP_JNL_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNL_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNL_long(block);
return 0;
}
static int
codegen_CMP_JNLE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNLE_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNLE_long(block);
return 0;
}
static int
codegen_CMP_JNO_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNO_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNO_long(block);
return 0;
}
static int
codegen_CMP_JNZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JNZ_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNZ_long(block);
return 0;
}
static int
codegen_CMP_JB_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JB_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JB_long(block);
return 0;
}
static int
codegen_CMP_JBE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JBE_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JBE_long(block);
return 0;
}
static int
codegen_CMP_JL_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JL_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JL_long(block);
return 0;
}
static int
codegen_CMP_JLE_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JLE_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JLE_long(block);
return 0;
}
static int
codegen_CMP_JO_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JO_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JO_long(block);
return 0;
}
static int
codegen_CMP_JZ_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
host_x86_CMP32_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
host_x86_CMP16_REG_REG(block, src_reg_a, src_reg_b);
} else if (REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
host_x86_CMP8_REG_REG(block, src_reg_a, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("CMP_JZ_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JZ_long(block);
return 0;
}
static int
codegen_FABS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && dest_reg == src_reg_a) {
host_x86_PXOR_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP);
host_x86_SUBSD_XREG_XREG(block, REG_XMM_TEMP, dest_reg);
host_x86_MAXSD_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FABS %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_FCHS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a)) {
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_PXOR_XREG_XREG(block, dest_reg, dest_reg);
host_x86_SUBSD_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FCHS %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_FSQRT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a)) {
host_x86_SQRTSD_XREG_XREG(block, dest_reg, src_reg_a);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FSQRT %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_FTST(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_W(dest_size) && REG_IS_D(src_size_a)) {
host_x86_PXOR_XREG_XREG(block, REG_XMM_TEMP, REG_XMM_TEMP);
if (dest_reg != REG_EAX)
host_x86_MOV32_REG_REG(block, REG_ECX, REG_EAX);
host_x86_XOR32_REG_REG(block, REG_EAX, REG_EAX);
host_x86_COMISD_XREG_XREG(block, src_reg_a, REG_XMM_TEMP);
host_x86_LAHF(block);
host_x86_AND16_REG_IMM(block, REG_EAX, FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3);
if (dest_reg != REG_EAX) {
host_x86_MOV16_REG_REG(block, dest_reg, REG_EAX);
host_x86_MOV32_REG_REG(block, REG_EAX, REG_ECX);
}
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FTST %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b) && dest_reg == src_reg_a) {
host_x86_ADDSD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FCOM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_W(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
if (dest_reg != REG_EAX)
host_x86_MOV32_REG_REG(block, REG_ECX, REG_EAX);
host_x86_XOR32_REG_REG(block, REG_EAX, REG_EAX);
host_x86_COMISD_XREG_XREG(block, src_reg_a, src_reg_b);
host_x86_LAHF(block);
host_x86_AND16_REG_IMM(block, REG_EAX, FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3);
if (dest_reg != REG_EAX) {
host_x86_MOV16_REG_REG(block, dest_reg, REG_EAX);
host_x86_MOV32_REG_REG(block, REG_EAX, REG_ECX);
}
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FCOM %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FDIV(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b) && dest_reg == src_reg_a) {
host_x86_DIVSD_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_DIVSD_XREG_XREG(block, REG_XMM_TEMP, src_reg_b);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FDIV %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FMUL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b) && dest_reg == src_reg_a) {
host_x86_MULSD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FMUL %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FSUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b) && dest_reg == src_reg_a) {
host_x86_SUBSD_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_D(dest_size) && REG_IS_D(src_size_a) && REG_IS_D(src_size_b)) {
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_SUBSD_XREG_XREG(block, REG_XMM_TEMP, src_reg_b);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_FSUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_FP_ENTER(codeblock_t *block, uop_t *uop)
{
uint32_t *branch_offset;
host_x86_MOV32_REG_ABS(block, REG_ECX, &cr0);
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
# if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
# else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
# endif
host_x86_CALL(block, x86_int);
host_x86_JMP(block, codegen_exit_rout);
*branch_offset = (uint32_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 4;
return 0;
}
static int
codegen_MMX_ENTER(codeblock_t *block, uop_t *uop)
{
uint32_t *branch_offset;
host_x86_MOV32_REG_ABS(block, REG_ECX, &cr0);
host_x86_TEST32_REG_IMM(block, REG_ECX, 0xc);
branch_offset = host_x86_JZ_long(block);
host_x86_MOV32_ABS_IMM(block, &cpu_state.oldpc, uop->imm_data);
# if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, 7);
# else
host_x86_MOV32_REG_IMM(block, REG_EDI, 7);
# endif
host_x86_CALL(block, x86_int);
host_x86_JMP(block, codegen_exit_rout);
*branch_offset = (uint32_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 4;
host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[0], 0x01010101);
host_x86_MOV32_ABS_IMM(block, &cpu_state.tag[4], 0x01010101);
host_x86_MOV32_ABS_IMM(block, &cpu_state.TOP, 0);
host_x86_MOV8_ABS_IMM(block, &cpu_state.ismmx, 1);
return 0;
}
static int
codegen_JMP(codeblock_t *block, uop_t *uop)
{
host_x86_JMP(block, uop->p);
return 0;
}
static int
codegen_LOAD_FUNC_ARG0(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_W(src_size)) {
# if _WIN64
host_x86_MOVZX_REG_32_16(block, REG_ECX, src_reg);
# else
host_x86_MOVZX_REG_32_16(block, REG_EDI, src_reg);
# endif
}
# ifdef RECOMPILER_DEBUG
else
fatal("codegen_LOAD_FUNC_ARG0 %02x\n", uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG1(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
# ifdef RECOMPILER_DEBUG
fatal("codegen_LOAD_FUNC_ARG1 %02x\n", uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG2(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
# ifdef RECOMPILER_DEBUG
fatal("codegen_LOAD_FUNC_ARG2 %02x\n", uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG3(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
# ifdef RECOMPILER_DEBUG
fatal("codegen_LOAD_FUNC_ARG3 %02x\n", uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG0_IMM(codeblock_t *block, uop_t *uop)
{
# if _WIN64
host_x86_MOV32_REG_IMM(block, REG_ECX, uop->imm_data);
# else
host_x86_MOV32_REG_IMM(block, REG_EDI, uop->imm_data);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG1_IMM(codeblock_t *block, uop_t *uop)
{
# if _WIN64
host_x86_MOV32_REG_IMM(block, REG_EDX, uop->imm_data);
# else
host_x86_MOV32_REG_IMM(block, REG_ESI, uop->imm_data);
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG2_IMM(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
# ifdef RECOMPILER_DEBUG
fatal("codegen_LOAD_FUNC_ARG2_IMM\n");
# endif
return 0;
}
static int
codegen_LOAD_FUNC_ARG3_IMM(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
# ifdef RECOMPILER_DEBUG
fatal("codegen_LOAD_FUNC_ARG3_IMM\n");
# endif
return 0;
}
static int
codegen_LOAD_SEG(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
# ifdef RECOMPILER_DEBUG
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (!REG_IS_W(src_size))
fatal("LOAD_SEG %02x %p\n", uop->src_reg_a_real, uop->p);
# endif
# if _WIN64
host_x86_MOV16_REG_REG(block, REG_CX, src_reg);
host_x86_MOV64_REG_IMM(block, REG_EDX, (uint64_t) uop->p);
# else
host_x86_MOV16_REG_REG(block, REG_DI, src_reg);
host_x86_MOV64_REG_IMM(block, REG_ESI, (uint64_t) uop->p);
# endif
host_x86_CALL(block, (void *) loadseg);
host_x86_TEST32_REG(block, REG_EAX, REG_EAX);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_LOAD_ABS(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_x86_LEA_REG_IMM(block, REG_ESI, seg_reg, uop->imm_data);
if (REG_IS_B(dest_size)) {
host_x86_CALL(block, codegen_mem_load_byte);
} else if (REG_IS_W(dest_size)) {
host_x86_CALL(block, codegen_mem_load_word);
} else if (REG_IS_L(dest_size)) {
host_x86_CALL(block, codegen_mem_load_long);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MEM_LOAD_ABS - %02x\n", uop->dest_reg_a_real);
# endif
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
if (REG_IS_B(dest_size)) {
host_x86_MOV8_REG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_W(dest_size)) {
host_x86_MOV16_REG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_L(dest_size)) {
host_x86_MOV32_REG_REG(block, dest_reg, REG_ECX);
}
return 0;
}
static int
codegen_MEM_LOAD_REG(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
if (REG_IS_B(dest_size)) {
host_x86_CALL(block, codegen_mem_load_byte);
} else if (REG_IS_W(dest_size)) {
host_x86_CALL(block, codegen_mem_load_word);
} else if (REG_IS_L(dest_size)) {
host_x86_CALL(block, codegen_mem_load_long);
} else if (REG_IS_Q(dest_size)) {
host_x86_CALL(block, codegen_mem_load_quad);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MEM_LOAD_REG - %02x\n", uop->dest_reg_a_real);
# endif
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
if (REG_IS_B(dest_size)) {
host_x86_MOV8_REG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_W(dest_size)) {
host_x86_MOV16_REG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_L(dest_size)) {
host_x86_MOV32_REG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_Q(dest_size)) {
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
return 0;
}
static int
codegen_MEM_LOAD_SINGLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
# ifdef RECOMPILER_DEBUG
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_D(dest_size))
fatal("MEM_LOAD_SINGLE - %02x\n", uop->dest_reg_a_real);
# endif
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
host_x86_CALL(block, codegen_mem_load_single);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
return 0;
}
static int
codegen_MEM_LOAD_DOUBLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
# ifdef RECOMPILER_DEBUG
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (!REG_IS_D(dest_size))
fatal("MEM_LOAD_DOUBLE - %02x\n", uop->dest_reg_a_real);
# endif
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
host_x86_CALL(block, codegen_mem_load_double);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
return 0;
}
static int
codegen_MEM_STORE_ABS(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_size = IREG_GET_SIZE(uop->src_reg_b_real);
host_x86_LEA_REG_IMM(block, REG_ESI, seg_reg, uop->imm_data);
if (REG_IS_B(src_size)) {
host_x86_MOV8_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_byte);
} else if (REG_IS_W(src_size)) {
host_x86_MOV16_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_word);
} else if (REG_IS_L(src_size)) {
host_x86_MOV32_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_long);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MEM_STORE_ABS - %02x\n", uop->src_reg_b_real);
# endif
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_8(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
host_x86_MOV8_REG_IMM(block, REG_ECX, uop->imm_data);
host_x86_CALL(block, codegen_mem_store_byte);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_16(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
host_x86_MOV16_REG_IMM(block, REG_ECX, uop->imm_data);
host_x86_CALL(block, codegen_mem_store_word);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_IMM_32(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
host_x86_MOV32_REG_IMM(block, REG_ECX, uop->imm_data);
host_x86_CALL(block, codegen_mem_store_long);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_REG(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
if (REG_IS_B(src_size)) {
host_x86_MOV8_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_byte);
} else if (REG_IS_W(src_size)) {
host_x86_MOV16_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_word);
} else if (REG_IS_L(src_size)) {
host_x86_MOV32_REG_REG(block, REG_ECX, src_reg);
host_x86_CALL(block, codegen_mem_store_long);
} else if (REG_IS_Q(src_size)) {
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg);
host_x86_CALL(block, codegen_mem_store_quad);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MEM_STORE_REG - %02x\n", uop->src_reg_b_real);
# endif
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_SINGLE(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
# ifdef RECOMPILER_DEBUG
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
if (!REG_IS_D(src_size))
fatal("MEM_STORE_SINGLE - %02x\n", uop->src_reg_b_real);
# endif
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
host_x86_CVTSD2SS_XREG_XREG(block, REG_XMM_TEMP, src_reg);
host_x86_CALL(block, codegen_mem_store_single);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MEM_STORE_DOUBLE(codeblock_t *block, uop_t *uop)
{
int seg_reg = HOST_REG_GET(uop->src_reg_a_real);
int addr_reg = HOST_REG_GET(uop->src_reg_b_real);
int src_reg = HOST_REG_GET(uop->src_reg_c_real);
# ifdef RECOMPILER_DEBUG
int src_size = IREG_GET_SIZE(uop->src_reg_c_real);
if (!REG_IS_D(src_size))
fatal("MEM_STORE_DOUBLE - %02x\n", uop->src_reg_b_real);
# endif
host_x86_LEA_REG_REG(block, REG_ESI, seg_reg, addr_reg);
if (uop->imm_data)
host_x86_ADD32_REG_IMM(block, REG_ESI, uop->imm_data);
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg);
host_x86_CALL(block, codegen_mem_store_double);
host_x86_TEST32_REG(block, REG_ESI, REG_ESI);
host_x86_JNZ(block, codegen_exit_rout);
return 0;
}
static int
codegen_MOV(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
} else if (REG_IS_D(dest_size) && REG_IS_D(src_size)) {
host_x86_MOVQ_XREG_XREG(block, dest_reg, src_reg);
} else if (REG_IS_Q(dest_size) && REG_IS_Q(src_size)) {
host_x86_MOVQ_XREG_XREG(block, dest_reg, src_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOV %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_MOV_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_L(dest_size)) {
host_x86_MOV32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size)) {
host_x86_MOV16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size)) {
host_x86_MOV8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOV_IMM %02x\n", uop->dest_reg_a_real);
# endif
return 0;
}
static int
codegen_MOV_PTR(codeblock_t *block, uop_t *uop)
{
host_x86_MOV64_REG_IMM(block, uop->dest_reg_a_real, (uint64_t) uop->p);
return 0;
}
static int
codegen_MOV_REG_PTR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_L(dest_size)) {
host_x86_MOV32_REG_ABS(block, dest_reg, uop->p);
} else
fatal("MOV_REG_PTR %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOVZX_REG_PTR_8(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_L(dest_size)) {
host_x86_MOVZX_REG_ABS_32_8(block, dest_reg, uop->p);
} else if (REG_IS_W(dest_size)) {
host_x86_MOVZX_REG_ABS_16_8(block, dest_reg, uop->p);
} else if (REG_IS_B(dest_size)) {
host_x86_MOV8_REG_ABS(block, dest_reg, uop->p);
} else
fatal("MOVZX_REG_PTR_8 %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOVZX_REG_PTR_16(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_L(dest_size)) {
host_x86_MOVZX_REG_ABS_32_16(block, dest_reg, uop->p);
} else if (REG_IS_W(dest_size)) {
host_x86_MOV16_REG_ABS(block, dest_reg, uop->p);
} else
fatal("MOVZX_REG_PTR_16 %02x\n", uop->dest_reg_a_real);
return 0;
}
static int
codegen_MOVSX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_W(src_size)) {
host_x86_MOVSX_REG_32_16(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_B(src_size)) {
host_x86_MOVSX_REG_32_8(block, dest_reg, src_reg);
} else if (REG_IS_W(dest_size) && REG_IS_B(src_size)) {
host_x86_MOVSX_REG_16_8(block, dest_reg, src_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOVSX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_MOVZX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_L(src_size)) {
host_x86_MOVD_XREG_REG(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_Q(src_size)) {
host_x86_MOVD_REG_XREG(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_W(src_size)) {
host_x86_MOVZX_REG_32_16(block, dest_reg, src_reg);
} else if (REG_IS_L(dest_size) && REG_IS_B(src_size)) {
host_x86_MOVZX_REG_32_8(block, dest_reg, src_reg);
} else if (REG_IS_W(dest_size) && REG_IS_B(src_size)) {
host_x86_MOVZX_REG_16_8(block, dest_reg, src_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOVZX %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_MOV_DOUBLE_INT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_D(dest_size) && REG_IS_L(src_size)) {
host_x86_CVTSI2SD_XREG_REG(block, dest_reg, src_reg);
} else if (REG_IS_D(dest_size) && REG_IS_W(src_size)) {
host_x86_MOVSX_REG_32_16(block, REG_ECX, src_reg);
host_x86_CVTSI2SD_XREG_REG(block, dest_reg, REG_ECX);
} else if (REG_IS_D(dest_size) && REG_IS_Q(src_size)) {
host_x86_MOVQ_REG_XREG(block, REG_RCX, src_reg);
host_x86_CVTSI2SD_XREG_REG64(block, dest_reg, REG_RCX);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOV_DOUBLE_INT %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_MOV_INT_DOUBLE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_D(src_size)) {
host_x86_LDMXCSR(block, &cpu_state.new_fp_control);
host_x86_CVTSD2SI_REG_XREG(block, dest_reg, src_reg);
host_x86_LDMXCSR(block, &cpu_state.old_fp_control);
} else if (REG_IS_W(dest_size) && REG_IS_D(src_size)) {
host_x86_LDMXCSR(block, &cpu_state.new_fp_control);
host_x86_CVTSD2SI_REG_XREG(block, REG_ECX, src_reg);
host_x86_MOV16_REG_REG(block, dest_reg, REG_ECX);
host_x86_LDMXCSR(block, &cpu_state.old_fp_control);
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOV_INT_DOUBLE %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_MOV_INT_DOUBLE_64(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_64_reg = HOST_REG_GET(uop->src_reg_b_real);
int tag_reg = HOST_REG_GET(uop->src_reg_c_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
int src_64_size = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_D(src_size) && REG_IS_Q(src_64_size)) {
uint32_t *branch_offset;
/*If TAG_UINT64 is set then the source is MM[]. Otherwise it is a double in ST()*/
host_x86_MOVQ_XREG_XREG(block, dest_reg, src_64_reg);
host_x86_TEST8_REG(block, tag_reg, tag_reg);
branch_offset = host_x86_JS_long(block);
host_x86_LDMXCSR(block, &cpu_state.new_fp_control);
host_x86_CVTSD2SI_REG64_XREG(block, REG_RCX, src_reg);
host_x86_LDMXCSR(block, &cpu_state.old_fp_control);
host_x86_MOVQ_XREG_REG(block, dest_reg, REG_RCX);
*branch_offset = (uint32_t) ((uintptr_t) &block_write_data[block_pos] - (uintptr_t) branch_offset) - 4;
}
# ifdef RECOMPILER_DEBUG
else
fatal("MOV_INT_DOUBLE_64 %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_NOP(UNUSED(codeblock_t *block), UNUSED(uop_t *uop))
{
return 0;
}
static int
codegen_OR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_POR_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg_a);
host_x86_OR32_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_OR16_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_OR8_REG_REG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("OR %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_OR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_x86_OR32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_x86_OR16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_x86_OR8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("OR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PACKSSWB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PACKSSWB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PACKSSWB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PACKSSDW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PACKSSDW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PACKSSDW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PACKUSWB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PACKUSWB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PACKUSWB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDSB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDSW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDUSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDUSB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDUSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PADDUSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PADDUSW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PADDUSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPEQB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPEQB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPEQB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPEQW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPEQW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPEQW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPEQD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPEQD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPEQD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPGTB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPGTB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPGTB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPGTW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPGTW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPGTW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PCMPGTD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PCMPGTD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PCMPGTD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PF2ID(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
host_x86_LDMXCSR(block, &cpu_state.trunc_fp_control);
host_x86_CVTPS2DQ_XREG_XREG(block, dest_reg, src_reg_a);
host_x86_LDMXCSR(block, &cpu_state.old_fp_control);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PF2ID %02x %02x\n", uop->dest_reg_a_real);
# endif
return 0;
}
static int
codegen_PFADD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_ADDPS_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFADD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFCMPEQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_CMPPS_XREG_XREG(block, dest_reg, src_reg_b, CMPPS_EQ);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFCMPEQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFCMPGE(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_CMPPS_XREG_XREG(block, dest_reg, src_reg_b, CMPPS_NLT);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFCMPGE %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFCMPGT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_CMPPS_XREG_XREG(block, dest_reg, src_reg_b, CMPPS_NLE);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFCMPGT %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFMAX(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_MAXPS_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFMAX %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFMIN(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_MINPS_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFMIN %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFMUL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_MULPS_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFMUL %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PFRCP(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
/*TODO: This could be improved (use RCPSS + iteration)*/
host_x86_MOV32_REG_IMM(block, REG_ECX, 1);
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_CVTSI2SS_XREG_REG(block, dest_reg, REG_ECX);
host_x86_DIVSS_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
host_x86_UNPCKLPS_XREG_XREG(block, dest_reg, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFRCP %02x %02x\n", uop->dest_reg_a_real);
# endif
return 0;
}
static int
codegen_PFRSQRT(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
/*TODO: This could be improved (use RSQRTSS + iteration)*/
host_x86_SQRTSS_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_MOV32_REG_IMM(block, REG_ECX, 1);
host_x86_CVTSI2SS_XREG_REG(block, dest_reg, REG_ECX);
host_x86_DIVSS_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
host_x86_UNPCKLPS_XREG_XREG(block, dest_reg, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFRSQRT %02x %02x\n", uop->dest_reg_a_real);
# endif
return 0;
}
static int
codegen_PFSUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_SUBPS_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b)) {
host_x86_MOVQ_XREG_XREG(block, REG_XMM_TEMP, src_reg_a);
host_x86_SUBPS_XREG_XREG(block, REG_XMM_TEMP, src_reg_b);
host_x86_MOVQ_XREG_XREG(block, dest_reg, REG_XMM_TEMP);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PFSUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PI2FD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a)) {
host_x86_CVTDQ2PS_XREG_XREG(block, dest_reg, src_reg_a);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PI2FD %02x %02x\n", uop->dest_reg_a_real);
# endif
return 0;
}
static int
codegen_PMADDWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PMADDWD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PMULHW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PMULHW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PMULHW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PMULHW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PMULLW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PMULLW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PMULLW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSLLW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSLLW_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSLLW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSLLD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSLLD_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSLLD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSLLQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSLLQ_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSLLQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRAW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRAW_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRAW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRAD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRAD_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRAD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRAQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRAQ_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRAQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRLW_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRLW_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRLW_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRLD_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRLD_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRLD_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSRLQ_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
if (REG_IS_Q(dest_size) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSRLQ_XREG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSRLQ_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_PSUBB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBSB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBSW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBUSB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBUSB_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBUSB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PSUBUSW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PSUBUSW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PSUBUSW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKHBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKHBW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKHBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKHWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKHWD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKHWD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKHDQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKHDQ_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKHDQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKLBW(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKLBW_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKLBW %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKLWD(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKLWD_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKLWD %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_PUNPCKLDQ(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PUNPCKLDQ_XREG_XREG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("PUNPCKLDQ %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_ROL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
host_x86_MOV32_REG_REG(block, REG_ECX, shift_reg);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_ROL32_CL(block, dest_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_ROL16_CL(block, dest_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_ROL8_CL(block, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ROL %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_ROL_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_ROL32_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_ROL16_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_ROL8_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ROL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_ROR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
host_x86_MOV32_REG_REG(block, REG_ECX, shift_reg);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_ROR32_CL(block, dest_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_ROR16_CL(block, dest_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_ROR8_CL(block, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ROR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_ROR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_ROR32_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_ROR16_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_ROR8_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("ROR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SAR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
host_x86_MOV32_REG_REG(block, REG_ECX, shift_reg);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SAR32_CL(block, dest_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SAR16_CL(block, dest_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SAR8_CL(block, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SAR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SAR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SAR32_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SAR16_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SAR8_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SAR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SHL(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
host_x86_MOV32_REG_REG(block, REG_ECX, shift_reg);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SHL32_CL(block, dest_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SHL16_CL(block, dest_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SHL8_CL(block, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SHL %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SHL_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SHL32_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SHL16_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SHL8_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SHL_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SHR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int shift_reg = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
host_x86_MOV32_REG_REG(block, REG_ECX, shift_reg);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SHR32_CL(block, dest_reg);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SHR16_CL(block, dest_reg);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SHR8_CL(block, dest_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SHR %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_SHR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SHR32_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SHR16_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (uop->dest_reg_a_real != uop->src_reg_a_real)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SHR8_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SHR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_STORE_PTR_IMM(codeblock_t *block, uop_t *uop)
{
# ifdef RECOMPILER_DEBUG
if (((uintptr_t) uop->p) >> 32)
fatal("STORE_PTR_IMM 64-bit addr\n");
# endif
host_x86_MOV32_ABS_IMM(block, uop->p, uop->imm_data);
return 0;
}
static int
codegen_STORE_PTR_IMM_8(codeblock_t *block, uop_t *uop)
{
# ifdef RECOMPILER_DEBUG
if (((uintptr_t) uop->p) >> 32)
fatal("STORE_PTR_IMM_8 64-bit addr\n");
# endif
host_x86_MOV8_ABS_IMM(block, uop->p, uop->imm_data);
return 0;
}
static int
codegen_SUB(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_a = HOST_REG_GET(uop->src_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg_a);
host_x86_SUB32_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg_a);
host_x86_SUB16_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b)) {
if (dest_reg != src_reg_a)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg_a);
host_x86_SUB8_REG_REG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SUB %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_SUB_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV32_REG_REG(block, dest_reg, src_reg);
host_x86_SUB32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV16_REG_REG(block, dest_reg, src_reg);
host_x86_SUB16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
if (dest_reg != src_reg)
host_x86_MOV8_REG_REG(block, dest_reg, src_reg);
host_x86_SUB8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("SUB_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
static int
codegen_TEST_JNS_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_x86_TEST32_REG(block, src_reg, src_reg);
} else if (REG_IS_W(src_size)) {
host_x86_TEST16_REG(block, src_reg, src_reg);
} else if (REG_IS_B(src_size)) {
host_x86_TEST8_REG(block, src_reg, src_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("TEST_JNS_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JNS_long(block);
return 0;
}
static int
codegen_TEST_JS_DEST(codeblock_t *block, uop_t *uop)
{
int src_reg = HOST_REG_GET(uop->src_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(src_size)) {
host_x86_TEST32_REG(block, src_reg, src_reg);
} else if (REG_IS_W(src_size)) {
host_x86_TEST16_REG(block, src_reg, src_reg);
} else if (REG_IS_B(src_size)) {
host_x86_TEST8_REG(block, src_reg, src_reg);
}
# ifdef RECOMPILER_DEBUG
else
fatal("TEST_JS_DEST %02x\n", uop->src_reg_a_real);
# endif
uop->p = host_x86_JS_long(block);
return 0;
}
static int
codegen_XOR(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int src_reg_b = HOST_REG_GET(uop->src_reg_b_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size_a = IREG_GET_SIZE(uop->src_reg_a_real);
int src_size_b = IREG_GET_SIZE(uop->src_reg_b_real);
if (REG_IS_Q(dest_size) && REG_IS_Q(src_size_a) && REG_IS_Q(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_PXOR_XREG_XREG(block, dest_reg, src_reg_b);
} else if (REG_IS_L(dest_size) && REG_IS_L(src_size_a) && REG_IS_L(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_XOR32_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size_a) && REG_IS_W(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_XOR16_REG_REG(block, dest_reg, src_reg_b);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size_a) && REG_IS_B(src_size_b) && uop->dest_reg_a_real == uop->src_reg_a_real) {
host_x86_XOR8_REG_REG(block, dest_reg, src_reg_b);
}
# ifdef RECOMPILER_DEBUG
else
fatal("XOR %02x %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real, uop->src_reg_b_real);
# endif
return 0;
}
static int
codegen_XOR_IMM(codeblock_t *block, uop_t *uop)
{
int dest_reg = HOST_REG_GET(uop->dest_reg_a_real);
int dest_size = IREG_GET_SIZE(uop->dest_reg_a_real);
int src_size = IREG_GET_SIZE(uop->src_reg_a_real);
if (REG_IS_L(dest_size) && REG_IS_L(src_size)) {
host_x86_XOR32_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_W(dest_size) && REG_IS_W(src_size)) {
host_x86_XOR16_REG_IMM(block, dest_reg, uop->imm_data);
} else if (REG_IS_B(dest_size) && REG_IS_B(src_size)) {
host_x86_XOR8_REG_IMM(block, dest_reg, uop->imm_data);
}
# ifdef RECOMPILER_DEBUG
else
fatal("XOR_IMM %02x %02x\n", uop->dest_reg_a_real, uop->src_reg_a_real);
# endif
return 0;
}
const uOpFn uop_handlers[UOP_MAX] = {
[UOP_CALL_FUNC & UOP_MASK] = codegen_CALL_FUNC,
[UOP_CALL_FUNC_RESULT &
UOP_MASK]
= codegen_CALL_FUNC_RESULT,
[UOP_CALL_INSTRUCTION_FUNC &
UOP_MASK]
= codegen_CALL_INSTRUCTION_FUNC,
[UOP_JMP &
UOP_MASK]
= codegen_JMP,
[UOP_LOAD_SEG &
UOP_MASK]
= codegen_LOAD_SEG,
[UOP_LOAD_FUNC_ARG_0 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG0,
[UOP_LOAD_FUNC_ARG_1 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG1,
[UOP_LOAD_FUNC_ARG_2 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG2,
[UOP_LOAD_FUNC_ARG_3 &
UOP_MASK]
= codegen_LOAD_FUNC_ARG3,
[UOP_LOAD_FUNC_ARG_0_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG0_IMM,
[UOP_LOAD_FUNC_ARG_1_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG1_IMM,
[UOP_LOAD_FUNC_ARG_2_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG2_IMM,
[UOP_LOAD_FUNC_ARG_3_IMM &
UOP_MASK]
= codegen_LOAD_FUNC_ARG3_IMM,
[UOP_STORE_P_IMM &
UOP_MASK]
= codegen_STORE_PTR_IMM,
[UOP_STORE_P_IMM_8 &
UOP_MASK]
= codegen_STORE_PTR_IMM_8,
[UOP_MEM_LOAD_ABS &
UOP_MASK]
= codegen_MEM_LOAD_ABS,
[UOP_MEM_LOAD_REG &
UOP_MASK]
= codegen_MEM_LOAD_REG,
[UOP_MEM_LOAD_SINGLE &
UOP_MASK]
= codegen_MEM_LOAD_SINGLE,
[UOP_MEM_LOAD_DOUBLE &
UOP_MASK]
= codegen_MEM_LOAD_DOUBLE,
[UOP_MEM_STORE_ABS &
UOP_MASK]
= codegen_MEM_STORE_ABS,
[UOP_MEM_STORE_REG &
UOP_MASK]
= codegen_MEM_STORE_REG,
[UOP_MEM_STORE_IMM_8 &
UOP_MASK]
= codegen_MEM_STORE_IMM_8,
[UOP_MEM_STORE_IMM_16 &
UOP_MASK]
= codegen_MEM_STORE_IMM_16,
[UOP_MEM_STORE_IMM_32 &
UOP_MASK]
= codegen_MEM_STORE_IMM_32,
[UOP_MEM_STORE_SINGLE &
UOP_MASK]
= codegen_MEM_STORE_SINGLE,
[UOP_MEM_STORE_DOUBLE &
UOP_MASK]
= codegen_MEM_STORE_DOUBLE,
[UOP_MOV &
UOP_MASK]
= codegen_MOV,
[UOP_MOV_PTR &
UOP_MASK]
= codegen_MOV_PTR,
[UOP_MOV_IMM &
UOP_MASK]
= codegen_MOV_IMM,
[UOP_MOVSX &
UOP_MASK]
= codegen_MOVSX,
[UOP_MOVZX &
UOP_MASK]
= codegen_MOVZX,
[UOP_MOV_DOUBLE_INT &
UOP_MASK]
= codegen_MOV_DOUBLE_INT,
[UOP_MOV_INT_DOUBLE &
UOP_MASK]
= codegen_MOV_INT_DOUBLE,
[UOP_MOV_INT_DOUBLE_64 &
UOP_MASK]
= codegen_MOV_INT_DOUBLE_64,
[UOP_MOV_REG_PTR &
UOP_MASK]
= codegen_MOV_REG_PTR,
[UOP_MOVZX_REG_PTR_8 &
UOP_MASK]
= codegen_MOVZX_REG_PTR_8,
[UOP_MOVZX_REG_PTR_16 &
UOP_MASK]
= codegen_MOVZX_REG_PTR_16,
[UOP_ADD &
UOP_MASK]
= codegen_ADD,
[UOP_ADD_IMM &
UOP_MASK]
= codegen_ADD_IMM,
[UOP_ADD_LSHIFT &
UOP_MASK]
= codegen_ADD_LSHIFT,
[UOP_AND &
UOP_MASK]
= codegen_AND,
[UOP_ANDN &
UOP_MASK]
= codegen_ANDN,
[UOP_AND_IMM &
UOP_MASK]
= codegen_AND_IMM,
[UOP_OR &
UOP_MASK]
= codegen_OR,
[UOP_OR_IMM &
UOP_MASK]
= codegen_OR_IMM,
[UOP_SUB &
UOP_MASK]
= codegen_SUB,
[UOP_SUB_IMM &
UOP_MASK]
= codegen_SUB_IMM,
[UOP_XOR &
UOP_MASK]
= codegen_XOR,
[UOP_XOR_IMM &
UOP_MASK]
= codegen_XOR_IMM,
[UOP_SAR &
UOP_MASK]
= codegen_SAR,
[UOP_SAR_IMM &
UOP_MASK]
= codegen_SAR_IMM,
[UOP_SHL &
UOP_MASK]
= codegen_SHL,
[UOP_SHL_IMM &
UOP_MASK]
= codegen_SHL_IMM,
[UOP_SHR &
UOP_MASK]
= codegen_SHR,
[UOP_SHR_IMM &
UOP_MASK]
= codegen_SHR_IMM,
[UOP_ROL &
UOP_MASK]
= codegen_ROL,
[UOP_ROL_IMM &
UOP_MASK]
= codegen_ROL_IMM,
[UOP_ROR &
UOP_MASK]
= codegen_ROR,
[UOP_ROR_IMM &
UOP_MASK]
= codegen_ROR_IMM,
[UOP_CMP_IMM_JZ &
UOP_MASK]
= codegen_CMP_IMM_JZ,
[UOP_CMP_JB &
UOP_MASK]
= codegen_CMP_JB,
[UOP_CMP_JNBE &
UOP_MASK]
= codegen_CMP_JNBE,
[UOP_CMP_JNB_DEST &
UOP_MASK]
= codegen_CMP_JNB_DEST,
[UOP_CMP_JNBE_DEST &
UOP_MASK]
= codegen_CMP_JNBE_DEST,
[UOP_CMP_JNL_DEST &
UOP_MASK]
= codegen_CMP_JNL_DEST,
[UOP_CMP_JNLE_DEST &
UOP_MASK]
= codegen_CMP_JNLE_DEST,
[UOP_CMP_JNO_DEST &
UOP_MASK]
= codegen_CMP_JNO_DEST,
[UOP_CMP_JNZ_DEST &
UOP_MASK]
= codegen_CMP_JNZ_DEST,
[UOP_CMP_JB_DEST &
UOP_MASK]
= codegen_CMP_JB_DEST,
[UOP_CMP_JBE_DEST &
UOP_MASK]
= codegen_CMP_JBE_DEST,
[UOP_CMP_JL_DEST &
UOP_MASK]
= codegen_CMP_JL_DEST,
[UOP_CMP_JLE_DEST &
UOP_MASK]
= codegen_CMP_JLE_DEST,
[UOP_CMP_JO_DEST &
UOP_MASK]
= codegen_CMP_JO_DEST,
[UOP_CMP_JZ_DEST &
UOP_MASK]
= codegen_CMP_JZ_DEST,
[UOP_CMP_IMM_JNZ_DEST &
UOP_MASK]
= codegen_CMP_IMM_JNZ_DEST,
[UOP_CMP_IMM_JZ_DEST &
UOP_MASK]
= codegen_CMP_IMM_JZ_DEST,
[UOP_TEST_JNS_DEST &
UOP_MASK]
= codegen_TEST_JNS_DEST,
[UOP_TEST_JS_DEST &
UOP_MASK]
= codegen_TEST_JS_DEST,
[UOP_FP_ENTER &
UOP_MASK]
= codegen_FP_ENTER,
[UOP_MMX_ENTER &
UOP_MASK]
= codegen_MMX_ENTER,
[UOP_FADD &
UOP_MASK]
= codegen_FADD,
[UOP_FCOM &
UOP_MASK]
= codegen_FCOM,
[UOP_FDIV &
UOP_MASK]
= codegen_FDIV,
[UOP_FMUL &
UOP_MASK]
= codegen_FMUL,
[UOP_FSUB &
UOP_MASK]
= codegen_FSUB,
[UOP_FABS &
UOP_MASK]
= codegen_FABS,
[UOP_FCHS &
UOP_MASK]
= codegen_FCHS,
[UOP_FSQRT &
UOP_MASK]
= codegen_FSQRT,
[UOP_FTST &
UOP_MASK]
= codegen_FTST,
[UOP_PACKSSWB &
UOP_MASK]
= codegen_PACKSSWB,
[UOP_PACKSSDW &
UOP_MASK]
= codegen_PACKSSDW,
[UOP_PACKUSWB &
UOP_MASK]
= codegen_PACKUSWB,
[UOP_PADDB &
UOP_MASK]
= codegen_PADDB,
[UOP_PADDW &
UOP_MASK]
= codegen_PADDW,
[UOP_PADDD &
UOP_MASK]
= codegen_PADDD,
[UOP_PADDSB &
UOP_MASK]
= codegen_PADDSB,
[UOP_PADDSW &
UOP_MASK]
= codegen_PADDSW,
[UOP_PADDUSB &
UOP_MASK]
= codegen_PADDUSB,
[UOP_PADDUSW &
UOP_MASK]
= codegen_PADDUSW,
[UOP_PCMPEQB &
UOP_MASK]
= codegen_PCMPEQB,
[UOP_PCMPEQW &
UOP_MASK]
= codegen_PCMPEQW,
[UOP_PCMPEQD &
UOP_MASK]
= codegen_PCMPEQD,
[UOP_PCMPGTB &
UOP_MASK]
= codegen_PCMPGTB,
[UOP_PCMPGTW &
UOP_MASK]
= codegen_PCMPGTW,
[UOP_PCMPGTD &
UOP_MASK]
= codegen_PCMPGTD,
[UOP_PF2ID &
UOP_MASK]
= codegen_PF2ID,
[UOP_PFADD &
UOP_MASK]
= codegen_PFADD,
[UOP_PFCMPEQ &
UOP_MASK]
= codegen_PFCMPEQ,
[UOP_PFCMPGE &
UOP_MASK]
= codegen_PFCMPGE,
[UOP_PFCMPGT &
UOP_MASK]
= codegen_PFCMPGT,
[UOP_PFMAX &
UOP_MASK]
= codegen_PFMAX,
[UOP_PFMIN &
UOP_MASK]
= codegen_PFMIN,
[UOP_PFMUL &
UOP_MASK]
= codegen_PFMUL,
[UOP_PFRCP &
UOP_MASK]
= codegen_PFRCP,
[UOP_PFRSQRT &
UOP_MASK]
= codegen_PFRSQRT,
[UOP_PFSUB &
UOP_MASK]
= codegen_PFSUB,
[UOP_PI2FD &
UOP_MASK]
= codegen_PI2FD,
[UOP_PMADDWD &
UOP_MASK]
= codegen_PMADDWD,
[UOP_PMULHW &
UOP_MASK]
= codegen_PMULHW,
[UOP_PMULLW &
UOP_MASK]
= codegen_PMULLW,
[UOP_PSLLW_IMM &
UOP_MASK]
= codegen_PSLLW_IMM,
[UOP_PSLLD_IMM &
UOP_MASK]
= codegen_PSLLD_IMM,
[UOP_PSLLQ_IMM &
UOP_MASK]
= codegen_PSLLQ_IMM,
[UOP_PSRAW_IMM &
UOP_MASK]
= codegen_PSRAW_IMM,
[UOP_PSRAD_IMM &
UOP_MASK]
= codegen_PSRAD_IMM,
[UOP_PSRAQ_IMM &
UOP_MASK]
= codegen_PSRAQ_IMM,
[UOP_PSRLW_IMM &
UOP_MASK]
= codegen_PSRLW_IMM,
[UOP_PSRLD_IMM &
UOP_MASK]
= codegen_PSRLD_IMM,
[UOP_PSRLQ_IMM &
UOP_MASK]
= codegen_PSRLQ_IMM,
[UOP_PSUBB &
UOP_MASK]
= codegen_PSUBB,
[UOP_PSUBW &
UOP_MASK]
= codegen_PSUBW,
[UOP_PSUBD &
UOP_MASK]
= codegen_PSUBD,
[UOP_PSUBSB &
UOP_MASK]
= codegen_PSUBSB,
[UOP_PSUBSW &
UOP_MASK]
= codegen_PSUBSW,
[UOP_PSUBUSB &
UOP_MASK]
= codegen_PSUBUSB,
[UOP_PSUBUSW &
UOP_MASK]
= codegen_PSUBUSW,
[UOP_PUNPCKHBW &
UOP_MASK]
= codegen_PUNPCKHBW,
[UOP_PUNPCKHWD &
UOP_MASK]
= codegen_PUNPCKHWD,
[UOP_PUNPCKHDQ &
UOP_MASK]
= codegen_PUNPCKHDQ,
[UOP_PUNPCKLBW &
UOP_MASK]
= codegen_PUNPCKLBW,
[UOP_PUNPCKLWD &
UOP_MASK]
= codegen_PUNPCKLWD,
[UOP_PUNPCKLDQ &
UOP_MASK]
= codegen_PUNPCKLDQ,
[UOP_NOP_BARRIER &
UOP_MASK]
= codegen_NOP
};
void
codegen_direct_read_8(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOV8_REG_ABS(block, host_reg, p);
}
void
codegen_direct_read_16(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOV16_REG_ABS(block, host_reg, p);
}
void
codegen_direct_read_32(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOV32_REG_ABS(block, host_reg, p);
}
void
codegen_direct_read_64(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOVQ_XREG_ABS(block, host_reg, p);
}
void
codegen_direct_read_pointer(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOV64_REG_ABS(block, host_reg, p);
}
void
codegen_direct_read_double(codeblock_t *block, int host_reg, void *p)
{
host_x86_MOVQ_XREG_ABS(block, host_reg, p);
}
void
codegen_direct_read_st_8(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOV8_REG_ABS_REG_REG_SHIFT(block, host_reg, offset, REG_RBP, REG_ECX, 0);
}
void
codegen_direct_read_st_64(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(block, host_reg, offset, REG_RBP, REG_ECX, 3);
}
void
codegen_direct_read_st_double(codeblock_t *block, int host_reg, void *base, int reg_idx)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(block, host_reg, offset, REG_RBP, REG_ECX, 3);
}
void
codegen_direct_write_8(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOV8_ABS_REG(block, p, host_reg);
}
void
codegen_direct_write_16(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOV16_ABS_REG(block, p, host_reg);
}
void
codegen_direct_write_32(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOV32_ABS_REG(block, p, host_reg);
}
void
codegen_direct_write_64(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOVQ_ABS_XREG(block, p, host_reg);
}
void
codegen_direct_write_pointer(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOV64_ABS_REG(block, p, host_reg);
}
void
codegen_direct_write_double(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOVQ_ABS_XREG(block, p, host_reg);
}
void
codegen_direct_write_st_8(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOV8_ABS_REG_REG_SHIFT_REG(block, offset, REG_RBP, REG_ECX, 0, host_reg);
}
void
codegen_direct_write_st_64(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(block, offset, REG_RBP, REG_ECX, 3, host_reg);
}
void
codegen_direct_write_st_double(codeblock_t *block, void *base, int reg_idx, int host_reg)
{
int offset = (uintptr_t) base - (((uintptr_t) &cpu_state) + 128);
host_x86_MOV32_REG_BASE_OFFSET(block, REG_ECX, REG_RSP, IREG_TOP_diff_stack_offset);
host_x86_ADD32_REG_IMM(block, REG_ECX, reg_idx);
host_x86_AND32_REG_IMM(block, REG_ECX, 7);
host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(block, offset, REG_RBP, REG_ECX, 3, host_reg);
}
void
codegen_direct_write_ptr(codeblock_t *block, void *p, int host_reg)
{
host_x86_MOV64_ABS_REG(block, p, host_reg);
}
void
codegen_direct_read_16_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_x86_MOV16_REG_BASE_OFFSET(block, host_reg, REG_ESP, stack_offset);
}
void
codegen_direct_read_32_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_x86_MOV32_REG_BASE_OFFSET(block, host_reg, REG_RSP, stack_offset);
}
void
codegen_direct_read_64_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_x86_MOVQ_XREG_BASE_OFFSET(block, host_reg, REG_RSP, stack_offset);
}
void
codegen_direct_read_pointer_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_x86_MOV64_REG_BASE_OFFSET(block, host_reg, REG_RSP, stack_offset);
}
void
codegen_direct_read_double_stack(codeblock_t *block, int host_reg, int stack_offset)
{
host_x86_MOVQ_XREG_BASE_OFFSET(block, host_reg, REG_RSP, stack_offset);
}
void
codegen_direct_write_32_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_x86_MOV32_BASE_OFFSET_REG(block, REG_RSP, stack_offset, host_reg);
}
void
codegen_direct_write_64_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_x86_MOVQ_BASE_OFFSET_XREG(block, REG_RSP, stack_offset, host_reg);
}
void
codegen_direct_write_pointer_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_x86_MOV64_BASE_OFFSET_REG(block, REG_RSP, stack_offset, host_reg);
}
void
codegen_direct_write_double_stack(codeblock_t *block, int stack_offset, int host_reg)
{
host_x86_MOVQ_BASE_OFFSET_XREG(block, REG_RSP, stack_offset, host_reg);
}
void
codegen_set_jump_dest(UNUSED(codeblock_t *block), void *p)
{
*(uint32_t *) p = (uintptr_t) &block_write_data[block_pos] - ((uintptr_t) p + 4);
}
void
codegen_direct_write_8_imm(codeblock_t *block, void *p, uint8_t imm_data)
{
host_x86_MOV8_ABS_IMM(block, p, imm_data);
}
void
codegen_direct_write_16_imm(codeblock_t *block, void *p, uint16_t imm_data)
{
host_x86_MOV16_ABS_IMM(block, p, imm_data);
}
void
codegen_direct_write_32_imm(codeblock_t *block, void *p, uint32_t imm_data)
{
host_x86_MOV32_ABS_IMM(block, p, imm_data);
}
void
codegen_direct_write_32_imm_stack(codeblock_t *block, int stack_offset, uint32_t imm_data)
{
host_x86_MOV32_BASE_OFFSET_IMM(block, REG_ESP, stack_offset, imm_data);
}
#endif
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86-64_uops.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 38,603 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_mmx_pack.h"
#include "codegen_ops_helpers.h"
#define ropPpack(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
}
// clang-format off
ropPpack(PACKSSWB)
ropPpack(PACKSSDW)
ropPpack(PACKUSWB)
ropPpack(PUNPCKLBW)
ropPpack(PUNPCKLWD)
ropPpack(PUNPCKLDQ)
ropPpack(PUNPCKHBW)
ropPpack(PUNPCKHWD)
ropPpack(PUNPCKHDQ)
// clang-format on
``` | /content/code_sandbox/src/codegen_new/codegen_ops_mmx_pack.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 536 |
```objective-c
void host_x87_FILDq_BASE(codeblock_t *block, int base_reg);
void host_x87_FISTPq_BASE(codeblock_t *block, int base_reg);
void host_x87_FLDCW(codeblock_t *block, void *p);
void host_x87_FLDd_BASE(codeblock_t *block, int base_reg);
void host_x87_FSTPd_BASE(codeblock_t *block, int base_reg);
``` | /content/code_sandbox/src/codegen_new/codegen_backend_x86_ops_fpu.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 92 |
```c
#include <stdint.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include "x86.h"
#include "x86_flags.h"
#include "x86seg_common.h"
#include "x86seg.h"
#include "386_common.h"
#include "x87_sf.h"
#include "x87.h"
#include "codegen.h"
#include "codegen_accumulate.h"
#include "codegen_ir.h"
#include "codegen_ops.h"
#include "codegen_ops_fpu_misc.h"
#include "codegen_ops_helpers.h"
uint32_t
ropFFREE(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_tag(dest_reg), TAG_EMPTY);
return op_pc;
}
uint32_t
ropFLD(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int src_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_ST(-1), IREG_ST(src_reg));
uop_MOV(ir, IREG_ST_i64(-1), IREG_ST_i64(src_reg));
uop_MOV(ir, IREG_tag(-1), IREG_tag(src_reg));
fpu_PUSH(block, ir);
return op_pc;
}
uint32_t
ropFST(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_ST(dest_reg), IREG_ST(0));
uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_ST_i64(0));
uop_MOV(ir, IREG_tag(dest_reg), IREG_tag(0));
return op_pc;
}
uint32_t
ropFSTP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_ST(dest_reg), IREG_ST(0));
uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_ST_i64(0));
uop_MOV(ir, IREG_tag(dest_reg), IREG_tag(0));
fpu_POP(block, ir);
return op_pc;
}
uint32_t
ropFSTCW(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg;
uop_FP_ENTER(ir);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
op_pc--;
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_NPXC);
return op_pc + 1;
}
uint32_t
ropFSTSW(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc)
{
x86seg *target_seg;
uop_FP_ENTER(ir);
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc);
op_pc--;
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0);
codegen_check_seg_write(block, ir, target_seg);
uop_MEM_STORE_REG(ir, ireg_seg_base(target_seg), IREG_eaaddr, IREG_NPXS);
return op_pc + 1;
}
uint32_t
ropFSTSW_AX(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_AX, IREG_NPXS);
return op_pc;
}
uint32_t
ropFXCH(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc)
{
int dest_reg = fetchdat & 7;
uop_FP_ENTER(ir);
uop_MOV(ir, IREG_temp0_D, IREG_ST(0));
uop_MOV(ir, IREG_temp1_Q, IREG_ST_i64(0));
uop_MOV(ir, IREG_temp2, IREG_tag(0));
uop_MOV(ir, IREG_ST(0), IREG_ST(dest_reg));
uop_MOV(ir, IREG_ST_i64(0), IREG_ST_i64(dest_reg));
uop_MOV(ir, IREG_tag(0), IREG_tag(dest_reg));
uop_MOV(ir, IREG_ST(dest_reg), IREG_temp0_D);
uop_MOV(ir, IREG_ST_i64(dest_reg), IREG_temp1_Q);
uop_MOV(ir, IREG_tag(dest_reg), IREG_temp2);
return op_pc;
}
``` | /content/code_sandbox/src/codegen_new/codegen_ops_fpu_misc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,265 |
```objective-c
uint32_t ropADC_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADC_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropADD_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropCMP_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSBB_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_AL_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_AX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_EAX_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_b_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_b_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_w_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSUB_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop80(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop81_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropDEC_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropDEC_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropINC_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropINC_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropINCDEC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
``` | /content/code_sandbox/src/codegen_new/codegen_ops_arith.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,388 |
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